1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_arch; /* which cpu to codegen for */
137 extern enum processor_type mips_tune; /* which cpu to schedule for */
138 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
139 extern int mips_isa; /* architectural level */
140 extern int mips16; /* whether generating mips16 code */
141 extern int mips16_hard_float; /* mips16 without -msoft-float */
142 extern int mips_entry; /* generate entry/exit for mips16 */
143 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
144 extern const char *mips_arch_string; /* for -march=<xxx> */
145 extern const char *mips_tune_string; /* for -mtune=<xxx> */
146 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
147 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
148 extern const char *mips_entry_string; /* for -mentry */
149 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
150 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
151 extern int mips_split_addresses; /* perform high/lo_sum support */
152 extern int dslots_load_total; /* total # load related delay slots */
153 extern int dslots_load_filled; /* # filled load delay slots */
154 extern int dslots_jump_total; /* total # jump related delay slots */
155 extern int dslots_jump_filled; /* # filled jump delay slots */
156 extern int dslots_number_nops; /* # of nops needed by previous insn */
157 extern int num_refs[3]; /* # 1/2/3 word references */
158 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
159 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
160 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
161 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
162 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
163 extern int mips_string_length; /* length of strings for mips16 */
164 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
166 /* Functions to change what output section we are using. */
167 extern void rdata_section PARAMS ((void));
168 extern void sdata_section PARAMS ((void));
169 extern void sbss_section PARAMS ((void));
171 /* Stubs for half-pic support if not OSF/1 reference platform. */
174 #define HALF_PIC_P() 0
175 #define HALF_PIC_NUMBER_PTRS 0
176 #define HALF_PIC_NUMBER_REFS 0
177 #define HALF_PIC_ENCODE(DECL)
178 #define HALF_PIC_DECLARE(NAME)
179 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
180 #define HALF_PIC_ADDRESS_P(X) 0
181 #define HALF_PIC_PTR(X) X
182 #define HALF_PIC_FINISH(STREAM)
185 /* Macros to silence warnings about numbers being signed in traditional
186 C and unsigned in ISO C when compiled on 32-bit hosts. */
188 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
189 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
190 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
193 /* Run-time compilation parameters selecting different hardware subsets. */
195 /* Macros used in the machine description to test the flags. */
197 /* Bits for real switches */
198 #define MASK_INT64 0x00000001 /* ints are 64 bits */
199 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
200 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
201 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
202 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
203 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
204 #define MASK_STATS 0x00000040 /* print statistics to stderr */
205 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
206 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
207 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
208 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
209 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
210 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
211 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
212 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
213 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
214 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
215 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
216 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
217 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
218 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
219 #define MASK_NO_CHECK_ZERO_DIV \
220 0x00200000 /* divide by zero checking */
221 #define MASK_CHECK_RANGE_DIV \
222 0x00400000 /* divide result range checking */
223 #define MASK_UNINIT_CONST_IN_RODATA \
224 0x00800000 /* Store uninitialized
226 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
227 multiply-add operations. */
229 /* Debug switches, not documented */
230 #define MASK_DEBUG 0 /* unused */
231 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
232 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
233 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
234 #define MASK_DEBUG_D 0 /* don't do define_split's */
235 #define MASK_DEBUG_E 0 /* function_arg debug */
236 #define MASK_DEBUG_F 0 /* ??? */
237 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
238 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
239 #define MASK_DEBUG_I 0 /* unused */
241 /* Dummy switches used only in specs */
242 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
244 /* r4000 64 bit sizes */
245 #define TARGET_INT64 (target_flags & MASK_INT64)
246 #define TARGET_LONG64 (target_flags & MASK_LONG64)
247 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
248 #define TARGET_64BIT (target_flags & MASK_64BIT)
250 /* Mips vs. GNU linker */
251 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
253 /* Mips vs. GNU assembler */
254 #define TARGET_GAS (target_flags & MASK_GAS)
255 #define TARGET_MIPS_AS (!TARGET_GAS)
258 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
259 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
260 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
261 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
262 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
263 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
264 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
265 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
266 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
267 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
269 /* Reg. Naming in .s ($21 vs. $a0) */
270 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
272 /* Optimize for Sdata/Sbss */
273 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
275 /* print program statistics */
276 #define TARGET_STATS (target_flags & MASK_STATS)
278 /* call memcpy instead of inline code */
279 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
281 /* .abicalls, etc from Pyramid V.4 */
282 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
284 /* OSF pic references to externs */
285 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
287 /* software floating point */
288 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
289 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
291 /* always call through a register */
292 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
294 /* generate embedded PIC code;
296 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
298 /* for embedded systems, optimize for
299 reduced RAM space instead of for
301 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
303 /* always store uninitialized const
304 variables in rodata, requires
305 TARGET_EMBEDDED_DATA. */
306 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
308 /* generate big endian code. */
309 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
311 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
312 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
314 #define TARGET_MAD (target_flags & MASK_MAD)
316 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
318 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
320 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
321 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
323 /* This is true if we must enable the assembly language file switching
326 #define TARGET_FILE_SWITCHING \
327 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
329 /* We must disable the function end stabs when doing the file switching trick,
330 because the Lscope stabs end up in the wrong place, making it impossible
331 to debug the resulting code. */
332 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
334 /* Generate mips16 code */
335 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
337 /* Architecture target defines. */
338 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
339 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
340 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
341 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
343 /* Scheduling target defines. */
344 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
345 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
346 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
347 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
348 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
350 /* Macro to define tables used to set the flags.
351 This is a list in braces of pairs in braces,
352 each pair being { "NAME", VALUE }
353 where VALUE is the bits to set or minus the bits to clear.
354 An empty string NAME is used to identify the default VALUE. */
356 #define TARGET_SWITCHES \
359 N_("No default crt0.o") }, \
360 {"int64", MASK_INT64 | MASK_LONG64, \
361 N_("Use 64-bit int type")}, \
362 {"long64", MASK_LONG64, \
363 N_("Use 64-bit long type")}, \
364 {"long32", -(MASK_LONG64 | MASK_INT64), \
365 N_("Use 32-bit long type")}, \
366 {"split-addresses", MASK_SPLIT_ADDR, \
367 N_("Optimize lui/addiu address loads")}, \
368 {"no-split-addresses", -MASK_SPLIT_ADDR, \
369 N_("Don't optimize lui/addiu address loads")}, \
370 {"mips-as", -MASK_GAS, \
371 N_("Use MIPS as")}, \
374 {"rnames", MASK_NAME_REGS, \
375 N_("Use symbolic register names")}, \
376 {"no-rnames", -MASK_NAME_REGS, \
377 N_("Don't use symbolic register names")}, \
378 {"gpOPT", MASK_GPOPT, \
379 N_("Use GP relative sdata/sbss sections")}, \
380 {"gpopt", MASK_GPOPT, \
381 N_("Use GP relative sdata/sbss sections")}, \
382 {"no-gpOPT", -MASK_GPOPT, \
383 N_("Don't use GP relative sdata/sbss sections")}, \
384 {"no-gpopt", -MASK_GPOPT, \
385 N_("Don't use GP relative sdata/sbss sections")}, \
386 {"stats", MASK_STATS, \
387 N_("Output compiler statistics")}, \
388 {"no-stats", -MASK_STATS, \
389 N_("Don't output compiler statistics")}, \
390 {"memcpy", MASK_MEMCPY, \
391 N_("Don't optimize block moves")}, \
392 {"no-memcpy", -MASK_MEMCPY, \
393 N_("Optimize block moves")}, \
394 {"mips-tfile", MASK_MIPS_TFILE, \
395 N_("Use mips-tfile asm postpass")}, \
396 {"no-mips-tfile", -MASK_MIPS_TFILE, \
397 N_("Don't use mips-tfile asm postpass")}, \
398 {"soft-float", MASK_SOFT_FLOAT, \
399 N_("Use software floating point")}, \
400 {"hard-float", -MASK_SOFT_FLOAT, \
401 N_("Use hardware floating point")}, \
402 {"fp64", MASK_FLOAT64, \
403 N_("Use 64-bit FP registers")}, \
404 {"fp32", -MASK_FLOAT64, \
405 N_("Use 32-bit FP registers")}, \
406 {"gp64", MASK_64BIT, \
407 N_("Use 64-bit general registers")}, \
408 {"gp32", -MASK_64BIT, \
409 N_("Use 32-bit general registers")}, \
410 {"abicalls", MASK_ABICALLS, \
411 N_("Use Irix PIC")}, \
412 {"no-abicalls", -MASK_ABICALLS, \
413 N_("Don't use Irix PIC")}, \
414 {"half-pic", MASK_HALF_PIC, \
415 N_("Use OSF PIC")}, \
416 {"no-half-pic", -MASK_HALF_PIC, \
417 N_("Don't use OSF PIC")}, \
418 {"long-calls", MASK_LONG_CALLS, \
419 N_("Use indirect calls")}, \
420 {"no-long-calls", -MASK_LONG_CALLS, \
421 N_("Don't use indirect calls")}, \
422 {"embedded-pic", MASK_EMBEDDED_PIC, \
423 N_("Use embedded PIC")}, \
424 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
425 N_("Don't use embedded PIC")}, \
426 {"embedded-data", MASK_EMBEDDED_DATA, \
427 N_("Use ROM instead of RAM")}, \
428 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
429 N_("Don't use ROM instead of RAM")}, \
430 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
431 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
432 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
433 N_("Don't put uninitialized constants in ROM")}, \
434 {"eb", MASK_BIG_ENDIAN, \
435 N_("Use big-endian byte order")}, \
436 {"el", -MASK_BIG_ENDIAN, \
437 N_("Use little-endian byte order")}, \
438 {"single-float", MASK_SINGLE_FLOAT, \
439 N_("Use single (32-bit) FP only")}, \
440 {"double-float", -MASK_SINGLE_FLOAT, \
441 N_("Don't use single (32-bit) FP only")}, \
443 N_("Use multiply accumulate")}, \
444 {"no-mad", -MASK_MAD, \
445 N_("Don't use multiply accumulate")}, \
446 {"no-fused-madd", MASK_NO_FUSED_MADD, \
447 N_("Don't generate fused multiply/add instructions")}, \
448 {"fused-madd", -MASK_NO_FUSED_MADD, \
449 N_("Generate fused multiply/add instructions")}, \
450 {"fix4300", MASK_4300_MUL_FIX, \
451 N_("Work around early 4300 hardware bug")}, \
452 {"no-fix4300", -MASK_4300_MUL_FIX, \
453 N_("Don't work around early 4300 hardware bug")}, \
455 N_("Optimize for 3900")}, \
457 N_("Optimize for 4650")}, \
458 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
459 N_("Trap on integer divide by zero")}, \
460 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
461 N_("Don't trap on integer divide by zero")}, \
462 {"check-range-division",MASK_CHECK_RANGE_DIV, \
463 N_("Trap on integer divide overflow")}, \
464 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
465 N_("Don't trap on integer divide overflow")}, \
466 {"debug", MASK_DEBUG, \
468 {"debuga", MASK_DEBUG_A, \
470 {"debugb", MASK_DEBUG_B, \
472 {"debugc", MASK_DEBUG_C, \
474 {"debugd", MASK_DEBUG_D, \
476 {"debuge", MASK_DEBUG_E, \
478 {"debugf", MASK_DEBUG_F, \
480 {"debugg", MASK_DEBUG_G, \
482 {"debugh", MASK_DEBUG_H, \
484 {"debugi", MASK_DEBUG_I, \
486 {"", (TARGET_DEFAULT \
487 | TARGET_CPU_DEFAULT \
488 | TARGET_ENDIAN_DEFAULT), \
492 /* Default target_flags if no switches are specified */
494 #ifndef TARGET_DEFAULT
495 #define TARGET_DEFAULT 0
498 #ifndef TARGET_CPU_DEFAULT
499 #define TARGET_CPU_DEFAULT 0
502 #ifndef TARGET_ENDIAN_DEFAULT
504 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
506 #define TARGET_ENDIAN_DEFAULT 0
510 #ifndef MIPS_ISA_DEFAULT
511 #define MIPS_ISA_DEFAULT 1
516 /* Make this compile time constant for libgcc2 */
518 #define TARGET_64BIT 1
520 #define TARGET_64BIT 0
522 #endif /* IN_LIBGCC2 */
524 #ifndef MULTILIB_ENDIAN_DEFAULT
525 #if TARGET_ENDIAN_DEFAULT == 0
526 #define MULTILIB_ENDIAN_DEFAULT "EL"
528 #define MULTILIB_ENDIAN_DEFAULT "EB"
532 #ifndef MULTILIB_ISA_DEFAULT
533 # if MIPS_ISA_DEFAULT == 1
534 # define MULTILIB_ISA_DEFAULT "mips1"
536 # if MIPS_ISA_DEFAULT == 2
537 # define MULTILIB_ISA_DEFAULT "mips2"
539 # if MIPS_ISA_DEFAULT == 3
540 # define MULTILIB_ISA_DEFAULT "mips3"
542 # if MIPS_ISA_DEFAULT == 4
543 # define MULTILIB_ISA_DEFAULT "mips4"
545 # define MULTILIB_ISA_DEFAULT "mips1"
552 #ifndef MULTILIB_DEFAULTS
553 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
556 /* We must pass -EL to the linker by default for little endian embedded
557 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
558 linker will default to using big-endian output files. The OUTPUT_FORMAT
559 line must be in the linker script, otherwise -EB/-EL will not work. */
562 #if TARGET_ENDIAN_DEFAULT == 0
563 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
565 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
569 /* This macro is similar to `TARGET_SWITCHES' but defines names of
570 command options that have values. Its definition is an
571 initializer with a subgrouping for each command option.
573 Each subgrouping contains a string constant, that defines the
574 fixed part of the option name, and the address of a variable.
575 The variable, type `char *', is set to the variable part of the
576 given option if the fixed part matches. The actual option name
577 is made by appending `-m' to the specified name.
579 Here is an example which defines `-mshort-data-NUMBER'. If the
580 given option is `-mshort-data-512', the variable `m88k_short_data'
581 will be set to the string `"512"'.
583 extern char *m88k_short_data;
584 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
586 #define TARGET_OPTIONS \
588 SUBTARGET_TARGET_OPTIONS \
589 { "cpu=", &mips_cpu_string, \
590 N_("Specify CPU for scheduling purposes")}, \
591 { "tune=", &mips_tune_string, \
592 N_("Specify CPU for scheduling purposes")}, \
593 { "arch=", &mips_arch_string, \
594 N_("Specify CPU for code generation purposes")}, \
595 { "ips", &mips_isa_string, \
596 N_("Specify a Standard MIPS ISA")}, \
597 { "entry", &mips_entry_string, \
598 N_("Use mips16 entry/exit psuedo ops")}, \
599 { "no-mips16", &mips_no_mips16_string, \
600 N_("Don't use MIPS16 instructions")}, \
601 { "explicit-type-size", &mips_explicit_type_size_string, \
605 /* This is meant to be redefined in the host dependent files. */
606 #define SUBTARGET_TARGET_OPTIONS
608 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
610 /* Generate three-operand multiply instructions for both SImode and DImode. */
611 #define GENERATE_MULT3 (TARGET_MIPS3900 \
614 /* Macros to decide whether certain features are available or not,
615 depending on the instruction set architecture level. */
617 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
618 #define HAVE_SQRT_P() (mips_isa != 1)
620 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
621 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
624 /* ISA has branch likely instructions (eg. mips2). */
625 /* Disable branchlikely for tx39 until compare rewrite. They haven't
626 been generated up to this point. */
627 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
628 /* || TARGET_MIPS3900 */)
630 /* ISA has the conditional move instructions introduced in mips4. */
631 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
634 /* ISA has just the integer condition move instructions (movn,movz) */
635 #define ISA_HAS_INT_CONDMOVE 0
639 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
640 branch on CC, and move (both FP and non-FP) on CC. */
641 #define ISA_HAS_8CC (mips_isa == 4 \
645 /* This is a catch all for the other new mips4 instructions: indexed load and
646 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
647 and the FP recip and recip sqrt instructions */
648 #define ISA_HAS_FP4 (mips_isa == 4 \
651 /* ISA has conditional trap instructions. */
652 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
654 /* ISA has nmadd and nmsub instructions. */
655 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
658 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
659 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
660 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
661 target_flags, and -mgp64 sets MASK_64BIT.
663 Setting MASK_64BIT in target_flags will cause gcc to assume that
664 registers are 64 bits wide. int, long and void * will be 32 bit;
665 this may be changed with -mint64 or -mlong64.
667 The gen* programs link code that refers to MASK_64BIT. They don't
668 actually use the information in target_flags; they just refer to
671 /* Switch Recognition by gcc.c. Add -G xx support */
673 #ifdef SWITCH_TAKES_ARG
674 #undef SWITCH_TAKES_ARG
677 #define SWITCH_TAKES_ARG(CHAR) \
678 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
680 /* Sometimes certain combinations of command options do not make sense
681 on a particular target machine. You can define a macro
682 `OVERRIDE_OPTIONS' to take account of this. This macro, if
683 defined, is executed once just after all the command options have
686 On the MIPS, it is used to handle -G. We also use it to set up all
687 of the tables referenced in the other macros. */
689 #define OVERRIDE_OPTIONS override_options ()
691 /* Zero or more C statements that may conditionally modify two
692 variables `fixed_regs' and `call_used_regs' (both of type `char
693 []') after they have been initialized from the two preceding
696 This is necessary in case the fixed or call-clobbered registers
697 depend on target flags.
699 You need not define this macro if it has no work to do.
701 If the usage of an entire class of registers depends on the target
702 flags, you may indicate this to GCC by using this macro to modify
703 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
704 the classes which should not be used by GCC. Also define the macro
705 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
706 letter for a class that shouldn't be used.
708 (However, if this class is not included in `GENERAL_REGS' and all
709 of the insn patterns whose constraints permit this class are
710 controlled by target switches, then GCC will automatically avoid
711 using these registers when the target switches are opposed to
714 #define CONDITIONAL_REGISTER_USAGE \
717 if (!TARGET_HARD_FLOAT) \
721 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
722 fixed_regs[regno] = call_used_regs[regno] = 1; \
723 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
724 fixed_regs[regno] = call_used_regs[regno] = 1; \
726 else if (! ISA_HAS_8CC) \
730 /* We only have a single condition code register. We \
731 implement this by hiding all the condition code registers, \
732 and generating RTL that refers directly to ST_REG_FIRST. */ \
733 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
734 fixed_regs[regno] = call_used_regs[regno] = 1; \
736 /* In mips16 mode, we permit the $t temporary registers to be used \
737 for reload. We prohibit the unused $s registers, since they \
738 are caller saved, and saving them via a mips16 register would \
739 probably waste more time than just reloading the value. */ \
742 fixed_regs[18] = call_used_regs[18] = 1; \
743 fixed_regs[19] = call_used_regs[19] = 1; \
744 fixed_regs[20] = call_used_regs[20] = 1; \
745 fixed_regs[21] = call_used_regs[21] = 1; \
746 fixed_regs[22] = call_used_regs[22] = 1; \
747 fixed_regs[23] = call_used_regs[23] = 1; \
748 fixed_regs[26] = call_used_regs[26] = 1; \
749 fixed_regs[27] = call_used_regs[27] = 1; \
750 fixed_regs[30] = call_used_regs[30] = 1; \
752 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
756 /* This is meant to be redefined in the host dependent files. */
757 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
759 /* Show we can debug even without a frame pointer. */
760 #define CAN_DEBUG_WITHOUT_FP
762 /* Complain about missing specs and predefines that should be defined in each
763 of the target tm files to override the defaults. This is mostly a place-
764 holder until I can get each of the files updated [mm]. */
766 #if defined(OSF_OS) \
767 || defined(DECSTATION) \
768 || defined(SGI_TARGET) \
769 || defined(MIPS_NEWS) \
770 || defined(MIPS_SYSV) \
771 || defined(MIPS_SVR4) \
772 || defined(MIPS_BSD43)
774 #ifndef CPP_PREDEFINES
775 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
779 #error "Define LIB_SPEC in the appropriate tm.h file"
782 #ifndef STARTFILE_SPEC
783 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
787 #error "Define MACHINE_TYPE in the appropriate tm.h file"
791 /* Tell collect what flags to pass to nm. */
793 #define NM_FLAGS "-Bn"
797 /* Names to predefine in the preprocessor for this target machine. */
799 #ifndef CPP_PREDEFINES
800 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
801 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
802 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
805 /* Assembler specs. */
807 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
810 #define MIPS_AS_ASM_SPEC "\
811 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
812 %{pipe: %e-pipe is not supported.} \
813 %{K} %(subtarget_mips_as_asm_spec)"
815 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
816 rather than gas. It may be overridden by subtargets. */
818 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
819 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
822 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
825 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
827 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
828 GAS_ASM_SPEC as the default, depending upon the value of
831 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
834 #define TARGET_ASM_SPEC "\
835 %{mmips-as: %(mips_as_asm_spec)} \
836 %{!mmips-as: %(gas_asm_spec)}"
840 #define TARGET_ASM_SPEC "\
841 %{!mgas: %(mips_as_asm_spec)} \
842 %{mgas: %(gas_asm_spec)}"
846 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
847 to the assembler. It may be overridden by subtargets. */
848 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
849 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
851 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
854 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
855 the assembler. It may be overridden by subtargets. */
856 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
857 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
858 %{g} %{g0} %{g1} %{g2} %{g3} \
859 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
860 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
861 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
862 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
865 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
866 overridden by subtargets. */
868 #ifndef SUBTARGET_ASM_SPEC
869 #define SUBTARGET_ASM_SPEC ""
872 /* ASM_SPEC is the set of arguments to pass to the assembler. */
876 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
877 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
878 %(subtarget_asm_optimizing_spec) \
879 %(subtarget_asm_debugging_spec) \
882 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
884 %(subtarget_asm_spec)"
886 /* Specify to run a post-processor, mips-tfile after the assembler
887 has run to stuff the mips debug information into the object file.
888 This is needed because the $#!%^ MIPS assembler provides no way
889 of specifying such information in the assembly file. If we are
890 cross compiling, disable mips-tfile unless the user specifies
893 #ifndef ASM_FINAL_SPEC
894 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
896 #define ASM_FINAL_SPEC "\
897 %{mmips-as: %{!mno-mips-tfile: \
898 \n mips-tfile %{v*: -v} \
900 %{!K: %{save-temps: -I %b.o~}} \
901 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
902 %{.s:%i} %{!.s:%g.s}}}"
906 #define ASM_FINAL_SPEC "\
907 %{!mgas: %{!mno-mips-tfile: \
908 \n mips-tfile %{v*: -v} \
910 %{!K: %{save-temps: -I %b.o~}} \
911 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
912 %{.s:%i} %{!.s:%g.s}}}"
915 #endif /* ASM_FINAL_SPEC */
917 /* Redefinition of libraries used. Mips doesn't support normal
918 UNIX style profiling via calling _mcount. It does offer
919 profiling that samples the PC, so do what we can... */
922 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
925 /* Extra switches sometimes passed to the linker. */
926 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
927 will interpret it as a -b option. */
932 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
933 %{bestGnum} %{shared} %{non_shared}"
934 #endif /* LINK_SPEC defined */
936 /* Specs for the compiler proper */
938 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
939 overridden by subtargets. */
940 #ifndef SUBTARGET_CC1_SPEC
941 #define SUBTARGET_CC1_SPEC ""
944 /* Deal with historic options. */
946 #define CC1_CPU_SPEC "\
948 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
949 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
950 %{m4650:-march=r4650 -mmad -msingle-float \
951 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
954 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
958 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
959 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
960 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
961 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
962 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
963 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
964 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
965 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
966 %{pic-none: -mno-half-pic} \
967 %{pic-lib: -mhalf-pic} \
968 %{pic-extern: -mhalf-pic} \
969 %{pic-calls: -mhalf-pic} \
971 %(subtarget_cc1_spec) \
975 /* Preprocessor specs. */
977 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
978 be overridden by subtargets. */
980 #ifndef SUBTARGET_CPP_SIZE_SPEC
981 #define SUBTARGET_CPP_SIZE_SPEC "\
982 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
983 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
986 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
987 overridden by subtargets. */
988 #ifndef SUBTARGET_CPP_SPEC
989 #define SUBTARGET_CPP_SPEC ""
992 /* If we're using 64bit longs, then we have to define __LONG_MAX__
993 correctly. Similarly for 64bit ints and __INT_MAX__. */
994 #ifndef LONG_MAX_SPEC
995 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
996 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
998 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
1002 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1003 of the source file extension. */
1004 #undef CPLUSPLUS_CPP_SPEC
1005 #define CPLUSPLUS_CPP_SPEC "\
1006 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1009 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1013 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1014 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1015 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1016 %(subtarget_cpp_size_spec) \
1017 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1018 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1019 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1020 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1021 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1022 %{msoft-float:-D__mips_soft_float} \
1023 %{mabi=eabi:-D__mips_eabi} \
1024 %{mips16:%{!mno-mips16:-D__mips16}} \
1025 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1026 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1028 %(subtarget_cpp_spec) "
1031 /* This macro defines names of additional specifications to put in the specs
1032 that can be used in various specifications like CC1_SPEC. Its definition
1033 is an initializer with a subgrouping for each command option.
1035 Each subgrouping contains a string constant, that defines the
1036 specification name, and a string constant that used by the GNU CC driver
1039 Do not define this macro if it does not need to do anything. */
1041 #define EXTRA_SPECS \
1042 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1043 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1044 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1045 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1046 { "long_max_spec", LONG_MAX_SPEC }, \
1047 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1048 { "gas_asm_spec", GAS_ASM_SPEC }, \
1049 { "target_asm_spec", TARGET_ASM_SPEC }, \
1050 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1051 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1052 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1053 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1054 { "endian_spec", ENDIAN_SPEC }, \
1055 SUBTARGET_EXTRA_SPECS
1057 #ifndef SUBTARGET_EXTRA_SPECS
1058 #define SUBTARGET_EXTRA_SPECS
1061 /* If defined, this macro is an additional prefix to try after
1062 `STANDARD_EXEC_PREFIX'. */
1064 #ifndef MD_EXEC_PREFIX
1065 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1068 #ifndef MD_STARTFILE_PREFIX
1069 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1073 /* Print subsidiary information on the compiler version in use. */
1075 #define MIPS_VERSION "[AL 1.1, MM 40]"
1077 #ifndef MACHINE_TYPE
1078 #define MACHINE_TYPE "BSD Mips"
1081 #ifndef TARGET_VERSION_INTERNAL
1082 #define TARGET_VERSION_INTERNAL(STREAM) \
1083 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1086 #ifndef TARGET_VERSION
1087 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1091 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1092 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1093 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1095 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1096 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1099 /* By default, turn on GDB extensions. */
1100 #define DEFAULT_GDB_EXTENSIONS 1
1102 /* If we are passing smuggling stabs through the MIPS ECOFF object
1103 format, put a comment in front of the .stab<x> operation so
1104 that the MIPS assembler does not choke. The mips-tfile program
1105 will correctly put the stab into the object file. */
1107 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1108 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1109 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1111 /* Local compiler-generated symbols must have a prefix that the assembler
1112 understands. By default, this is $, although some targets (e.g.,
1113 NetBSD-ELF) need to override this. */
1115 #ifndef LOCAL_LABEL_PREFIX
1116 #define LOCAL_LABEL_PREFIX "$"
1119 /* By default on the mips, external symbols do not have an underscore
1120 prepended, but some targets (e.g., NetBSD) require this. */
1122 #ifndef USER_LABEL_PREFIX
1123 #define USER_LABEL_PREFIX ""
1126 /* Forward references to tags are allowed. */
1127 #define SDB_ALLOW_FORWARD_REFERENCES
1129 /* Unknown tags are also allowed. */
1130 #define SDB_ALLOW_UNKNOWN_REFERENCES
1132 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1133 since the length can run past this up to a continuation point. */
1134 #undef DBX_CONTIN_LENGTH
1135 #define DBX_CONTIN_LENGTH 1500
1137 /* How to renumber registers for dbx and gdb. */
1138 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1140 /* The mapping from gcc register number to DWARF 2 CFA column number.
1141 This mapping does not allow for tracking register 0, since SGI's broken
1142 dwarf reader thinks column 0 is used for the frame address, but since
1143 register 0 is fixed this is not a problem. */
1144 #define DWARF_FRAME_REGNUM(REG) \
1145 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1147 /* The DWARF 2 CFA column which tracks the return address. */
1148 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1150 /* Before the prologue, RA lives in r31. */
1151 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1153 /* Describe how we implement __builtin_eh_return. */
1154 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1155 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1157 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1158 The default for this in 64-bit mode is 8, which causes problems with
1159 SFmode register saves. */
1160 #define DWARF_CIE_DATA_ALIGNMENT 4
1162 /* Overrides for the COFF debug format. */
1163 #define PUT_SDB_SCL(a) \
1165 extern FILE *asm_out_text_file; \
1166 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1169 #define PUT_SDB_INT_VAL(a) \
1171 extern FILE *asm_out_text_file; \
1172 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1175 #define PUT_SDB_VAL(a) \
1177 extern FILE *asm_out_text_file; \
1178 fputs ("\t.val\t", asm_out_text_file); \
1179 output_addr_const (asm_out_text_file, (a)); \
1180 fputc (';', asm_out_text_file); \
1183 #define PUT_SDB_DEF(a) \
1185 extern FILE *asm_out_text_file; \
1186 fprintf (asm_out_text_file, "\t%s.def\t", \
1187 (TARGET_GAS) ? "" : "#"); \
1188 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1189 fputc (';', asm_out_text_file); \
1192 #define PUT_SDB_PLAIN_DEF(a) \
1194 extern FILE *asm_out_text_file; \
1195 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1196 (TARGET_GAS) ? "" : "#", (a)); \
1199 #define PUT_SDB_ENDEF \
1201 extern FILE *asm_out_text_file; \
1202 fprintf (asm_out_text_file, "\t.endef\n"); \
1205 #define PUT_SDB_TYPE(a) \
1207 extern FILE *asm_out_text_file; \
1208 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1211 #define PUT_SDB_SIZE(a) \
1213 extern FILE *asm_out_text_file; \
1214 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1217 #define PUT_SDB_DIM(a) \
1219 extern FILE *asm_out_text_file; \
1220 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1223 #ifndef PUT_SDB_START_DIM
1224 #define PUT_SDB_START_DIM \
1226 extern FILE *asm_out_text_file; \
1227 fprintf (asm_out_text_file, "\t.dim\t"); \
1231 #ifndef PUT_SDB_NEXT_DIM
1232 #define PUT_SDB_NEXT_DIM(a) \
1234 extern FILE *asm_out_text_file; \
1235 fprintf (asm_out_text_file, "%d,", a); \
1239 #ifndef PUT_SDB_LAST_DIM
1240 #define PUT_SDB_LAST_DIM(a) \
1242 extern FILE *asm_out_text_file; \
1243 fprintf (asm_out_text_file, "%d;", a); \
1247 #define PUT_SDB_TAG(a) \
1249 extern FILE *asm_out_text_file; \
1250 fprintf (asm_out_text_file, "\t.tag\t"); \
1251 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1252 fputc (';', asm_out_text_file); \
1255 /* For block start and end, we create labels, so that
1256 later we can figure out where the correct offset is.
1257 The normal .ent/.end serve well enough for functions,
1258 so those are just commented out. */
1260 #define PUT_SDB_BLOCK_START(LINE) \
1262 extern FILE *asm_out_text_file; \
1263 fprintf (asm_out_text_file, \
1264 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1265 LOCAL_LABEL_PREFIX, \
1267 (TARGET_GAS) ? "" : "#", \
1268 LOCAL_LABEL_PREFIX, \
1271 sdb_label_count++; \
1274 #define PUT_SDB_BLOCK_END(LINE) \
1276 extern FILE *asm_out_text_file; \
1277 fprintf (asm_out_text_file, \
1278 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1279 LOCAL_LABEL_PREFIX, \
1281 (TARGET_GAS) ? "" : "#", \
1282 LOCAL_LABEL_PREFIX, \
1285 sdb_label_count++; \
1288 #define PUT_SDB_FUNCTION_START(LINE)
1290 #define PUT_SDB_FUNCTION_END(LINE) \
1292 extern FILE *asm_out_text_file; \
1293 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1296 #define PUT_SDB_EPILOGUE_END(NAME)
1298 #define PUT_SDB_SRC_FILE(FILENAME) \
1300 extern FILE *asm_out_text_file; \
1301 output_file_directive (asm_out_text_file, (FILENAME)); \
1304 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1305 sprintf ((BUFFER), ".%dfake", (NUMBER));
1307 /* Correct the offset of automatic variables and arguments. Note that
1308 the MIPS debug format wants all automatic variables and arguments
1309 to be in terms of the virtual frame pointer (stack pointer before
1310 any adjustment in the function), while the MIPS 3.0 linker wants
1311 the frame pointer to be the stack pointer after the initial
1314 #define DEBUGGER_AUTO_OFFSET(X) \
1315 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1316 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1317 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1319 /* Tell collect that the object format is ECOFF */
1320 #ifndef OBJECT_FORMAT_ROSE
1321 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1322 #define EXTENDED_COFF /* ECOFF, not normal coff */
1325 /* Target machine storage layout */
1327 /* Define in order to support both big and little endian float formats
1328 in the same gcc binary. */
1329 #define REAL_ARITHMETIC
1331 /* Define this if most significant bit is lowest numbered
1332 in instructions that operate on numbered bit-fields.
1334 #define BITS_BIG_ENDIAN 0
1336 /* Define this if most significant byte of a word is the lowest numbered. */
1337 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1339 /* Define this if most significant word of a multiword number is the lowest. */
1340 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1342 /* Define this to set the endianness to use in libgcc2.c, which can
1343 not depend on target_flags. */
1344 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1345 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1347 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1350 /* Number of bits in an addressable storage unit */
1351 #define BITS_PER_UNIT 8
1353 /* Width in bits of a "word", which is the contents of a machine register.
1354 Note that this is not necessarily the width of data type `int';
1355 if using 16-bit ints on a 68000, this would still be 32.
1356 But on a machine with 16-bit registers, this would be 16. */
1357 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1358 #define MAX_BITS_PER_WORD 64
1360 /* Width of a word, in units (bytes). */
1361 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1362 #define MIN_UNITS_PER_WORD 4
1364 /* For MIPS, width of a floating point register. */
1365 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1367 /* A C expression for the size in bits of the type `int' on the
1368 target machine. If you don't define this, the default is one
1370 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1371 #define MAX_INT_TYPE_SIZE 64
1373 /* Tell the preprocessor the maximum size of wchar_t. */
1374 #ifndef MAX_WCHAR_TYPE_SIZE
1375 #ifndef WCHAR_TYPE_SIZE
1376 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1380 /* A C expression for the size in bits of the type `short' on the
1381 target machine. If you don't define this, the default is half a
1382 word. (If this would be less than one storage unit, it is
1383 rounded up to one unit.) */
1384 #define SHORT_TYPE_SIZE 16
1386 /* A C expression for the size in bits of the type `long' on the
1387 target machine. If you don't define this, the default is one
1389 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1390 #define MAX_LONG_TYPE_SIZE 64
1392 /* A C expression for the size in bits of the type `long long' on the
1393 target machine. If you don't define this, the default is two
1395 #define LONG_LONG_TYPE_SIZE 64
1397 /* A C expression for the size in bits of the type `char' on the
1398 target machine. If you don't define this, the default is one
1399 quarter of a word. (If this would be less than one storage unit,
1400 it is rounded up to one unit.) */
1401 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1403 /* A C expression for the size in bits of the type `float' on the
1404 target machine. If you don't define this, the default is one
1406 #define FLOAT_TYPE_SIZE 32
1408 /* A C expression for the size in bits of the type `double' on the
1409 target machine. If you don't define this, the default is two
1411 #define DOUBLE_TYPE_SIZE 64
1413 /* A C expression for the size in bits of the type `long double' on
1414 the target machine. If you don't define this, the default is two
1416 #define LONG_DOUBLE_TYPE_SIZE 64
1418 /* Width in bits of a pointer.
1419 See also the macro `Pmode' defined below. */
1420 #ifndef POINTER_SIZE
1421 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1424 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1425 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1427 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1428 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1430 /* Allocation boundary (in *bits*) for the code of a function. */
1431 #define FUNCTION_BOUNDARY 32
1433 /* Alignment of field after `int : 0' in a structure. */
1434 #define EMPTY_FIELD_BOUNDARY 32
1436 /* Every structure's size must be a multiple of this. */
1437 /* 8 is observed right on a DECstation and on riscos 4.02. */
1438 #define STRUCTURE_SIZE_BOUNDARY 8
1440 /* There is no point aligning anything to a rounder boundary than this. */
1441 #define BIGGEST_ALIGNMENT 64
1443 /* Set this nonzero if move instructions will actually fail to work
1444 when given unaligned data. */
1445 #define STRICT_ALIGNMENT 1
1447 /* Define this if you wish to imitate the way many other C compilers
1448 handle alignment of bitfields and the structures that contain
1451 The behavior is that the type written for a bitfield (`int',
1452 `short', or other integer type) imposes an alignment for the
1453 entire structure, as if the structure really did contain an
1454 ordinary field of that type. In addition, the bitfield is placed
1455 within the structure so that it would fit within such a field,
1456 not crossing a boundary for it.
1458 Thus, on most machines, a bitfield whose type is written as `int'
1459 would not cross a four-byte boundary, and would force four-byte
1460 alignment for the whole structure. (The alignment used may not
1461 be four bytes; it is controlled by the other alignment
1464 If the macro is defined, its definition should be a C expression;
1465 a nonzero value for the expression enables this behavior. */
1467 #define PCC_BITFIELD_TYPE_MATTERS 1
1469 /* If defined, a C expression to compute the alignment given to a
1470 constant that is being placed in memory. CONSTANT is the constant
1471 and ALIGN is the alignment that the object would ordinarily have.
1472 The value of this macro is used instead of that alignment to align
1475 If this macro is not defined, then ALIGN is used.
1477 The typical use of this macro is to increase alignment for string
1478 constants to be word aligned so that `strcpy' calls that copy
1479 constants can be done inline. */
1481 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1482 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1483 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1485 /* If defined, a C expression to compute the alignment for a static
1486 variable. TYPE is the data type, and ALIGN is the alignment that
1487 the object would ordinarily have. The value of this macro is used
1488 instead of that alignment to align the object.
1490 If this macro is not defined, then ALIGN is used.
1492 One use of this macro is to increase alignment of medium-size
1493 data to make it all fit in fewer cache lines. Another is to
1494 cause character arrays to be word-aligned so that `strcpy' calls
1495 that copy constants to character arrays can be done inline. */
1497 #undef DATA_ALIGNMENT
1498 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1499 ((((ALIGN) < BITS_PER_WORD) \
1500 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1501 || TREE_CODE (TYPE) == UNION_TYPE \
1502 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1505 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1507 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1509 /* Define this macro if an argument declared as `char' or `short' in a
1510 prototype should actually be passed as an `int'. In addition to
1511 avoiding errors in certain cases of mismatch, it also makes for
1512 better code on certain machines. */
1514 #define PROMOTE_PROTOTYPES 1
1516 /* Define if operations between registers always perform the operation
1517 on the full register even if a narrower mode is specified. */
1518 #define WORD_REGISTER_OPERATIONS
1520 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1521 will either zero-extend or sign-extend. The value of this macro should
1522 be the code that says which one of the two operations is implicitly
1525 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1526 moves. All other referces are zero extended. */
1527 #define LOAD_EXTEND_OP(MODE) \
1528 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1529 ? SIGN_EXTEND : ZERO_EXTEND)
1531 /* Define this macro if it is advisable to hold scalars in registers
1532 in a wider mode than that declared by the program. In such cases,
1533 the value is constrained to be within the bounds of the declared
1534 type, but kept valid in the wider mode. The signedness of the
1535 extension may differ from that of the type.
1537 We promote any value smaller than SImode up to SImode. We don't
1538 want to promote to DImode when in 64 bit mode, because that would
1539 prevent us from using the faster SImode multiply and divide
1542 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1543 if (GET_MODE_CLASS (MODE) == MODE_INT \
1544 && GET_MODE_SIZE (MODE) < 4) \
1547 /* Define this if function arguments should also be promoted using the above
1550 #define PROMOTE_FUNCTION_ARGS
1552 /* Likewise, if the function return value is promoted. */
1554 #define PROMOTE_FUNCTION_RETURN
1556 /* Standard register usage. */
1558 /* Number of actual hardware registers.
1559 The hardware registers are assigned numbers for the compiler
1560 from 0 to just below FIRST_PSEUDO_REGISTER.
1561 All registers that the compiler knows about must be given numbers,
1562 even those that are not normally considered general registers.
1564 On the Mips, we have 32 integer registers, 32 floating point
1565 registers, 8 condition code registers, and the special registers
1566 hi, lo, hilo, and rap. The 8 condition code registers are only
1567 used if mips_isa >= 4. The hilo register is only used in 64 bit
1568 mode. It represents a 64 bit value stored as two 32 bit values in
1569 the hi and lo registers; this is the result of the mult
1570 instruction. rap is a pointer to the stack where the return
1571 address reg ($31) was stored. This is needed for C++ exception
1574 #define FIRST_PSEUDO_REGISTER 76
1576 /* 1 for registers that have pervasive standard uses
1577 and are not available for the register allocator.
1579 On the MIPS, see conventions, page D-2 */
1581 #define FIXED_REGISTERS \
1583 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1591 /* 1 for registers not available across function calls.
1592 These must include the FIXED_REGISTERS and also any
1593 registers that can be used without being saved.
1594 The latter must include the registers where values are returned
1595 and the register where structure-value addresses are passed.
1596 Aside from that, you can include as many other registers as you like. */
1598 #define CALL_USED_REGISTERS \
1600 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1601 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1602 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1603 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1608 /* Internal macros to classify a register number as to whether it's a
1609 general purpose register, a floating point register, a
1610 multiply/divide register, or a status register. */
1612 #define GP_REG_FIRST 0
1613 #define GP_REG_LAST 31
1614 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1615 #define GP_DBX_FIRST 0
1617 #define FP_REG_FIRST 32
1618 #define FP_REG_LAST 63
1619 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1620 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1622 #define MD_REG_FIRST 64
1623 #define MD_REG_LAST 66
1624 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1626 #define ST_REG_FIRST 67
1627 #define ST_REG_LAST 74
1628 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1630 #define RAP_REG_NUM 75
1632 #define AT_REGNUM (GP_REG_FIRST + 1)
1633 #define HI_REGNUM (MD_REG_FIRST + 0)
1634 #define LO_REGNUM (MD_REG_FIRST + 1)
1635 #define HILO_REGNUM (MD_REG_FIRST + 2)
1637 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1638 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1639 should be used instead. */
1640 #define FPSW_REGNUM ST_REG_FIRST
1642 #define GP_REG_P(REGNO) \
1643 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1644 #define M16_REG_P(REGNO) \
1645 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1646 #define FP_REG_P(REGNO) \
1647 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1648 #define MD_REG_P(REGNO) \
1649 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1650 #define ST_REG_P(REGNO) \
1651 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1653 /* Return number of consecutive hard regs needed starting at reg REGNO
1654 to hold something of mode MODE.
1655 This is ordinarily the length in words of a value of mode MODE
1656 but can be less for certain modes in special long registers.
1658 On the MIPS, all general registers are one word long. Except on
1659 the R4000 with the FR bit set, the floating point uses register
1660 pairs, with the second register not being allocable. */
1662 #define HARD_REGNO_NREGS(REGNO, MODE) \
1663 (! FP_REG_P (REGNO) \
1664 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1665 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1667 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1668 MODE. In 32 bit mode, require that DImode and DFmode be in even
1669 registers. For DImode, this makes some of the insns easier to
1670 write, since you don't have to worry about a DImode value in
1671 registers 3 & 4, producing a result in 4 & 5.
1673 To make the code simpler HARD_REGNO_MODE_OK now just references an
1674 array built in override_options. Because machmodes.h is not yet
1675 included before this file is processed, the MODE bound can't be
1678 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1680 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1681 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1683 /* Value is 1 if it is a good idea to tie two pseudo registers
1684 when one has mode MODE1 and one has mode MODE2.
1685 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1686 for any hard reg, then this must be 0 for correct output. */
1687 #define MODES_TIEABLE_P(MODE1, MODE2) \
1688 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1689 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1690 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1691 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1693 /* MIPS pc is not overloaded on a register. */
1694 /* #define PC_REGNUM xx */
1696 /* Register to use for pushing function arguments. */
1697 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1699 /* Offset from the stack pointer to the first available location. Use
1700 the default value zero. */
1701 /* #define STACK_POINTER_OFFSET 0 */
1703 /* Base register for access to local variables of the function. We
1704 pretend that the frame pointer is $1, and then eliminate it to
1705 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1706 a fixed register, and will not be used for anything else. */
1707 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1709 /* Temporary scratch register for use by the assembler. */
1710 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1712 /* $30 is not available on the mips16, so we use $17 as the frame
1714 #define HARD_FRAME_POINTER_REGNUM \
1715 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1717 /* Value should be nonzero if functions must have frame pointers.
1718 Zero means the frame pointer need not be set up (and parms
1719 may be accessed via the stack pointer) in functions that seem suitable.
1720 This is computed in `reload', in reload1.c. */
1721 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1723 /* Base register for access to arguments of the function. */
1724 #define ARG_POINTER_REGNUM GP_REG_FIRST
1726 /* Fake register that holds the address on the stack of the
1727 current function's return address. */
1728 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1730 /* Register in which static-chain is passed to a function. */
1731 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1733 /* If the structure value address is passed in a register, then
1734 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1735 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1737 /* If the structure value address is not passed in a register, define
1738 `STRUCT_VALUE' as an expression returning an RTX for the place
1739 where the address is passed. If it returns 0, the address is
1740 passed as an "invisible" first argument. */
1741 #define STRUCT_VALUE 0
1743 /* Mips registers used in prologue/epilogue code when the stack frame
1744 is larger than 32K bytes. These registers must come from the
1745 scratch register set, and not used for passing and returning
1746 arguments and any other information used in the calling sequence
1747 (such as pic). Must start at 12, since t0/t3 are parameter passing
1748 registers in the 64 bit ABI. */
1750 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1751 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1753 /* Define this macro if it is as good or better to call a constant
1754 function address than to call an address kept in a register. */
1755 #define NO_FUNCTION_CSE 1
1757 /* Define this macro if it is as good or better for a function to
1758 call itself with an explicit address than to call an address
1759 kept in a register. */
1760 #define NO_RECURSIVE_FUNCTION_CSE 1
1762 /* The register number of the register used to address a table of
1763 static data addresses in memory. In some cases this register is
1764 defined by a processor's "application binary interface" (ABI).
1765 When this macro is defined, RTL is generated for this register
1766 once, as with the stack pointer and frame pointer registers. If
1767 this macro is not defined, it is up to the machine-dependent
1768 files to allocate such a register (if necessary). */
1769 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1771 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1773 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1774 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1775 isn't always called for static inline functions. */
1776 #define INIT_EXPANDERS \
1778 embedded_pic_fnaddr_rtx = NULL; \
1779 mips16_gp_pseudo_rtx = NULL; \
1782 /* Define the classes of registers for register constraints in the
1783 machine description. Also define ranges of constants.
1785 One of the classes must always be named ALL_REGS and include all hard regs.
1786 If there is more than one class, another class must be named NO_REGS
1787 and contain no registers.
1789 The name GENERAL_REGS must be the name of a class (or an alias for
1790 another name such as ALL_REGS). This is the class of registers
1791 that is allowed by "g" or "r" in a register constraint.
1792 Also, registers outside this class are allocated only when
1793 instructions express preferences for them.
1795 The classes must be numbered in nondecreasing order; that is,
1796 a larger-numbered class must never be contained completely
1797 in a smaller-numbered class.
1799 For any two classes, it is very desirable that there be another
1800 class that represents their union. */
1804 NO_REGS, /* no registers in set */
1805 M16_NA_REGS, /* mips16 regs not used to pass args */
1806 M16_REGS, /* mips16 directly accessible registers */
1807 T_REG, /* mips16 T register ($24) */
1808 M16_T_REGS, /* mips16 registers plus T register */
1809 GR_REGS, /* integer registers */
1810 FP_REGS, /* floating point registers */
1811 HI_REG, /* hi register */
1812 LO_REG, /* lo register */
1813 HILO_REG, /* hilo register pair for 64 bit mode mult */
1814 MD_REGS, /* multiply/divide registers (hi/lo) */
1815 HI_AND_GR_REGS, /* union classes */
1818 ST_REGS, /* status registers (fp status) */
1819 ALL_REGS, /* all registers */
1820 LIM_REG_CLASSES /* max value + 1 */
1823 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1825 #define GENERAL_REGS GR_REGS
1827 /* An initializer containing the names of the register classes as C
1828 string constants. These names are used in writing some of the
1831 #define REG_CLASS_NAMES \
1846 "HILO_AND_GR_REGS", \
1851 /* An initializer containing the contents of the register classes,
1852 as integers which are bit masks. The Nth integer specifies the
1853 contents of class N. The way the integer MASK is interpreted is
1854 that register R is in the class if `MASK & (1 << R)' is 1.
1856 When the machine has more than 32 registers, an integer does not
1857 suffice. Then the integers are replaced by sub-initializers,
1858 braced groupings containing several integers. Each
1859 sub-initializer must be suitable as an initializer for the type
1860 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1862 #define REG_CLASS_CONTENTS \
1864 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1865 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1866 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1867 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1868 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1869 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1870 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1871 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1872 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1873 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1874 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1875 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1876 { 0xffffffff, 0x00000000, 0x00000002 }, \
1877 { 0xffffffff, 0x00000000, 0x00000004 }, \
1878 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1879 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1883 /* A C expression whose value is a register class containing hard
1884 register REGNO. In general there is more that one such class;
1885 choose a class which is "minimal", meaning that no smaller class
1886 also contains the register. */
1888 extern enum reg_class mips_regno_to_class[];
1890 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1892 /* A macro whose definition is the name of the class to which a
1893 valid base register must belong. A base register is one used in
1894 an address which is the register value plus a displacement. */
1896 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1898 /* A macro whose definition is the name of the class to which a
1899 valid index register must belong. An index register is one used
1900 in an address where its value is either multiplied by a scale
1901 factor or added to another register (as well as added to a
1904 #define INDEX_REG_CLASS NO_REGS
1906 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1907 registers explicitly used in the rtl to be used as spill registers
1908 but prevents the compiler from extending the lifetime of these
1911 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1913 /* This macro is used later on in the file. */
1914 #define GR_REG_CLASS_P(CLASS) \
1915 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1916 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1918 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1919 is the default value (allocate the registers in numeric order). We
1920 define it just so that we can override it for the mips16 target in
1921 ORDER_REGS_FOR_LOCAL_ALLOC. */
1923 #define REG_ALLOC_ORDER \
1924 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1925 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1926 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1927 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1928 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1931 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1932 to be rearranged based on a particular function. On the mips16, we
1933 want to allocate $24 (T_REG) before other registers for
1934 instructions for which it is possible. */
1936 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1938 /* REGISTER AND CONSTANT CLASSES */
1940 /* Get reg_class from a letter such as appears in the machine
1943 DEFINED REGISTER CLASSES:
1945 'd' General (aka integer) registers
1946 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1947 'y' General registers (in both mips16 and non mips16 mode)
1948 'e' mips16 non argument registers (M16_NA_REGS)
1949 't' mips16 temporary register ($24)
1950 'f' Floating point registers
1953 'x' Multiply/divide registers
1955 'z' FP Status register
1956 'b' All registers */
1958 extern enum reg_class mips_char_to_class[];
1960 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1962 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1963 string can be used to stand for particular ranges of immediate
1964 operands. This macro defines what the ranges are. C is the
1965 letter, and VALUE is a constant value. Return 1 if VALUE is
1966 in the range specified by C. */
1970 `I' is used for the range of constants an arithmetic insn can
1971 actually contain (16 bits signed integers).
1973 `J' is used for the range which is just zero (ie, $r0).
1975 `K' is used for the range of constants a logical insn can actually
1976 contain (16 bit zero-extended integers).
1978 `L' is used for the range of constants that be loaded with lui
1979 (ie, the bottom 16 bits are zero).
1981 `M' is used for the range of constants that take two words to load
1982 (ie, not matched by `I', `K', and `L').
1984 `N' is used for negative 16 bit constants other than -65536.
1986 `O' is a 15 bit signed integer.
1988 `P' is used for positive 16 bit constants. */
1990 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1991 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1993 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1994 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1995 : (C) == 'J' ? ((VALUE) == 0) \
1996 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1997 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1998 && (((VALUE) & ~2147483647) == 0 \
1999 || ((VALUE) & ~2147483647) == ~2147483647)) \
2000 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2001 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2002 && (((VALUE) & 0x0000ffff) != 0 \
2003 || (((VALUE) & ~2147483647) != 0 \
2004 && ((VALUE) & ~2147483647) != ~2147483647))) \
2005 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2006 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2007 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2010 /* Similar, but for floating constants, and defining letters G and H.
2011 Here VALUE is the CONST_DOUBLE rtx itself. */
2015 'G' : Floating point 0 */
2017 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2019 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2021 /* Letters in the range `Q' through `U' may be defined in a
2022 machine-dependent fashion to stand for arbitrary operand types.
2023 The machine description macro `EXTRA_CONSTRAINT' is passed the
2024 operand as its first argument and the constraint letter as its
2027 `Q' is for mips16 GP relative constants
2028 `R' is for memory references which take 1 word for the instruction.
2029 `S' is for references to extern items which are PIC for OSF/rose.
2030 `T' is for memory addresses that can be used to load two words. */
2032 #define EXTRA_CONSTRAINT(OP,CODE) \
2033 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2034 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2035 && mips16_gp_offset_p (OP)) \
2036 : (GET_CODE (OP) != MEM) ? FALSE \
2037 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2038 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2039 && HALF_PIC_ADDRESS_P (OP)) \
2042 /* Given an rtx X being reloaded into a reg required to be
2043 in class CLASS, return the class of reg to actually use.
2044 In general this is just CLASS; but on some machines
2045 in some cases it is preferable to use a more restrictive class. */
2047 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2048 ((CLASS) != ALL_REGS \
2049 ? (! TARGET_MIPS16 \
2051 : ((CLASS) != GR_REGS \
2054 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2055 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2056 ? (TARGET_SOFT_FLOAT \
2057 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2059 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2060 || GET_MODE (X) == VOIDmode) \
2061 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2064 /* Certain machines have the property that some registers cannot be
2065 copied to some other registers without using memory. Define this
2066 macro on those machines to be a C expression that is non-zero if
2067 objects of mode MODE in registers of CLASS1 can only be copied to
2068 registers of class CLASS2 by storing a register of CLASS1 into
2069 memory and loading that memory location into a register of CLASS2.
2071 Do not define this macro if its value would always be zero. */
2073 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2074 ((!TARGET_DEBUG_H_MODE \
2075 && GET_MODE_CLASS (MODE) == MODE_INT \
2076 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2077 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2078 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2079 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2080 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2082 /* The HI and LO registers can only be reloaded via the general
2083 registers. Condition code registers can only be loaded to the
2084 general registers, and from the floating point registers. */
2086 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2087 mips_secondary_reload_class (CLASS, MODE, X, 1)
2088 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2089 mips_secondary_reload_class (CLASS, MODE, X, 0)
2091 /* Return the maximum number of consecutive registers
2092 needed to represent mode MODE in a register of class CLASS. */
2094 #define CLASS_UNITS(mode, size) \
2095 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2097 #define CLASS_MAX_NREGS(CLASS, MODE) \
2098 ((CLASS) == FP_REGS \
2100 ? CLASS_UNITS (MODE, 8) \
2101 : 2 * CLASS_UNITS (MODE, 8)) \
2102 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2104 /* If defined, gives a class of registers that cannot be used as the
2105 operand of a SUBREG that changes the mode of the object illegally. */
2107 #define CLASS_CANNOT_CHANGE_MODE \
2108 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2110 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2112 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2113 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2115 /* Stack layout; function entry, exit and calling. */
2117 /* Define this if pushing a word on the stack
2118 makes the stack pointer a smaller address. */
2119 #define STACK_GROWS_DOWNWARD
2121 /* Define this if the nominal address of the stack frame
2122 is at the high-address end of the local variables;
2123 that is, each additional local variable allocated
2124 goes at a more negative offset in the frame. */
2125 /* #define FRAME_GROWS_DOWNWARD */
2127 /* Offset within stack frame to start allocating local variables at.
2128 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2129 first local allocated. Otherwise, it is the offset to the BEGINNING
2130 of the first local allocated. */
2131 #define STARTING_FRAME_OFFSET \
2132 (current_function_outgoing_args_size \
2133 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2135 /* Offset from the stack pointer register to an item dynamically
2136 allocated on the stack, e.g., by `alloca'.
2138 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2139 length of the outgoing arguments. The default is correct for most
2140 machines. See `function.c' for details.
2142 The MIPS ABI states that functions which dynamically allocate the
2143 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2144 we are trying to create a second frame pointer to the function, so
2145 allocate some stack space to make it happy.
2147 However, the linker currently complains about linking any code that
2148 dynamically allocates stack space, and there seems to be a bug in
2149 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2152 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2153 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2154 ? 4*UNITS_PER_WORD \
2155 : current_function_outgoing_args_size)
2158 /* The return address for the current frame is in r31 is this is a leaf
2159 function. Otherwise, it is on the stack. It is at a variable offset
2160 from sp/fp/ap, so we define a fake hard register rap which is a
2161 poiner to the return address on the stack. This always gets eliminated
2162 during reload to be either the frame pointer or the stack pointer plus
2165 /* ??? This definition fails for leaf functions. There is currently no
2166 general solution for this problem. */
2168 /* ??? There appears to be no way to get the return address of any previous
2169 frame except by disassembling instructions in the prologue/epilogue.
2170 So currently we support only the current frame. */
2172 #define RETURN_ADDR_RTX(count, frame) \
2174 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2177 /* Structure to be filled in by compute_frame_size with register
2178 save masks, and offsets for the current function. */
2180 struct mips_frame_info
2182 long total_size; /* # bytes that the entire frame takes up */
2183 long var_size; /* # bytes that variables take up */
2184 long args_size; /* # bytes that outgoing arguments take up */
2185 long extra_size; /* # bytes of extra gunk */
2186 int gp_reg_size; /* # bytes needed to store gp regs */
2187 int fp_reg_size; /* # bytes needed to store fp regs */
2188 long mask; /* mask of saved gp registers */
2189 long fmask; /* mask of saved fp registers */
2190 long gp_save_offset; /* offset from vfp to store gp registers */
2191 long fp_save_offset; /* offset from vfp to store fp registers */
2192 long gp_sp_offset; /* offset from new sp to store gp registers */
2193 long fp_sp_offset; /* offset from new sp to store fp registers */
2194 int initialized; /* != 0 if frame size already calculated */
2195 int num_gp; /* number of gp registers saved */
2196 int num_fp; /* number of fp registers saved */
2197 long insns_len; /* length of insns; mips16 only */
2200 extern struct mips_frame_info current_frame_info;
2202 /* If defined, this macro specifies a table of register pairs used to
2203 eliminate unneeded registers that point into the stack frame. If
2204 it is not defined, the only elimination attempted by the compiler
2205 is to replace references to the frame pointer with references to
2208 The definition of this macro is a list of structure
2209 initializations, each of which specifies an original and
2210 replacement register.
2212 On some machines, the position of the argument pointer is not
2213 known until the compilation is completed. In such a case, a
2214 separate hard register must be used for the argument pointer.
2215 This register can be eliminated by replacing it with either the
2216 frame pointer or the argument pointer, depending on whether or not
2217 the frame pointer has been eliminated.
2219 In this case, you might specify:
2220 #define ELIMINABLE_REGS \
2221 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2222 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2223 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2225 Note that the elimination of the argument pointer with the stack
2226 pointer is specified first since that is the preferred elimination.
2228 The eliminations to $17 are only used on the mips16. See the
2229 definition of HARD_FRAME_POINTER_REGNUM. */
2231 #define ELIMINABLE_REGS \
2232 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2233 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2234 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2235 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2236 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2237 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2238 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2239 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2240 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2241 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2243 /* A C expression that returns non-zero if the compiler is allowed to
2244 try to replace register number FROM-REG with register number
2245 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2246 defined, and will usually be the constant 1, since most of the
2247 cases preventing register elimination are things that the compiler
2248 already knows about.
2250 When not in mips16 and mips64, we can always eliminate to the
2251 frame pointer. We can eliminate to the stack pointer unless
2252 a frame pointer is needed. In mips16 mode, we need a frame
2253 pointer for a large frame; otherwise, reload may be unable
2254 to compute the address of a local variable, since there is
2255 no way to add a large constant to the stack pointer
2256 without using a temporary register.
2258 In mips16, for some instructions (eg lwu), we can't eliminate the
2259 frame pointer for the stack pointer. These instructions are
2260 only generated in TARGET_64BIT mode.
2263 #define CAN_ELIMINATE(FROM, TO) \
2264 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2265 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2266 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2267 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2268 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2269 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2270 && (! TARGET_MIPS16 \
2271 || compute_frame_size (get_frame_size ()) < 32768)))))
2273 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2274 specifies the initial difference between the specified pair of
2275 registers. This macro must be defined if `ELIMINABLE_REGS' is
2278 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2279 { compute_frame_size (get_frame_size ()); \
2280 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2281 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2282 (OFFSET) = - current_function_outgoing_args_size; \
2283 else if ((FROM) == FRAME_POINTER_REGNUM) \
2285 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2286 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2287 (OFFSET) = (current_frame_info.total_size \
2288 - current_function_outgoing_args_size \
2289 - ((mips_abi != ABI_32 \
2290 && mips_abi != ABI_O64 \
2291 && mips_abi != ABI_EABI) \
2292 ? current_function_pretend_args_size \
2294 else if ((FROM) == ARG_POINTER_REGNUM) \
2295 (OFFSET) = (current_frame_info.total_size \
2296 - ((mips_abi != ABI_32 \
2297 && mips_abi != ABI_O64 \
2298 && mips_abi != ABI_EABI) \
2299 ? current_function_pretend_args_size \
2301 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2302 so we must add 4 bytes to the offset to get the right value. */ \
2303 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2305 if (leaf_function_p ()) \
2307 else (OFFSET) = current_frame_info.gp_sp_offset \
2308 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2309 * (BYTES_BIG_ENDIAN != 0)); \
2313 /* If we generate an insn to push BYTES bytes,
2314 this says how many the stack pointer really advances by.
2315 On the VAX, sp@- in a byte insn really pushes a word. */
2317 /* #define PUSH_ROUNDING(BYTES) 0 */
2319 /* If defined, the maximum amount of space required for outgoing
2320 arguments will be computed and placed into the variable
2321 `current_function_outgoing_args_size'. No space will be pushed
2322 onto the stack for each call; instead, the function prologue
2323 should increase the stack frame size by this amount.
2325 It is not proper to define both `PUSH_ROUNDING' and
2326 `ACCUMULATE_OUTGOING_ARGS'. */
2327 #define ACCUMULATE_OUTGOING_ARGS 1
2329 /* Offset from the argument pointer register to the first argument's
2330 address. On some machines it may depend on the data type of the
2333 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2334 the first argument's address.
2336 On the MIPS, we must skip the first argument position if we are
2337 returning a structure or a union, to account for its address being
2338 passed in $4. However, at the current time, this produces a compiler
2339 that can't bootstrap, so comment it out for now. */
2342 #define FIRST_PARM_OFFSET(FNDECL) \
2344 && TREE_TYPE (FNDECL) != 0 \
2345 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2346 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2347 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2351 #define FIRST_PARM_OFFSET(FNDECL) 0
2354 /* When a parameter is passed in a register, stack space is still
2355 allocated for it. For the MIPS, stack space must be allocated, cf
2356 Asm Lang Prog Guide page 7-8.
2358 BEWARE that some space is also allocated for non existing arguments
2359 in register. In case an argument list is of form GF used registers
2360 are a0 (a2,a3), but we should push over a1... */
2362 #define REG_PARM_STACK_SPACE(FNDECL) \
2363 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2365 /* Define this if it is the responsibility of the caller to
2366 allocate the area reserved for arguments passed in registers.
2367 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2368 of this macro is to determine whether the space is included in
2369 `current_function_outgoing_args_size'. */
2370 #define OUTGOING_REG_PARM_STACK_SPACE
2372 /* Align stack frames on 64 bits (Double Word ). */
2373 #ifndef STACK_BOUNDARY
2374 #define STACK_BOUNDARY 64
2377 /* Make sure 4 words are always allocated on the stack. */
2379 #ifndef STACK_ARGS_ADJUST
2380 #define STACK_ARGS_ADJUST(SIZE) \
2382 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2383 SIZE.constant = 4 * UNITS_PER_WORD; \
2388 /* A C expression that should indicate the number of bytes of its
2389 own arguments that a function pops on returning, or 0
2390 if the function pops no arguments and the caller must therefore
2391 pop them all after the function returns.
2393 FUNDECL is the declaration node of the function (as a tree).
2395 FUNTYPE is a C variable whose value is a tree node that
2396 describes the function in question. Normally it is a node of
2397 type `FUNCTION_TYPE' that describes the data type of the function.
2398 From this it is possible to obtain the data types of the value
2399 and arguments (if known).
2401 When a call to a library function is being considered, FUNTYPE
2402 will contain an identifier node for the library function. Thus,
2403 if you need to distinguish among various library functions, you
2404 can do so by their names. Note that "library function" in this
2405 context means a function used to perform arithmetic, whose name
2406 is known specially in the compiler and was not mentioned in the
2407 C code being compiled.
2409 STACK-SIZE is the number of bytes of arguments passed on the
2410 stack. If a variable number of bytes is passed, it is zero, and
2411 argument popping will always be the responsibility of the
2412 calling function. */
2414 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2417 /* Symbolic macros for the registers used to return integer and floating
2420 #define GP_RETURN (GP_REG_FIRST + 2)
2421 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2423 /* Symbolic macros for the first/last argument registers. */
2425 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2426 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2427 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2428 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2430 #define MAX_ARGS_IN_REGISTERS 4
2432 /* Define how to find the value returned by a library function
2433 assuming the value has mode MODE. Because we define
2434 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2435 PROMOTE_MODE does. */
2437 #define LIBCALL_VALUE(MODE) \
2439 ((GET_MODE_CLASS (MODE) != MODE_INT \
2440 || GET_MODE_SIZE (MODE) >= 4) \
2443 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2444 && (! TARGET_SINGLE_FLOAT \
2445 || GET_MODE_SIZE (MODE) <= 4)) \
2449 /* Define how to find the value returned by a function.
2450 VALTYPE is the data type of the value (as a tree).
2451 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2452 otherwise, FUNC is 0. */
2454 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2457 /* 1 if N is a possible register number for a function value.
2458 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2459 Currently, R2 and F0 are only implemented here (C has no complex type) */
2461 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2463 /* 1 if N is a possible register number for function argument passing.
2464 We have no FP argument registers when soft-float. When FP registers
2465 are 32 bits, we can't directly reference the odd numbered ones. */
2467 #define FUNCTION_ARG_REGNO_P(N) \
2468 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2469 || ((! TARGET_SOFT_FLOAT \
2470 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2471 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2472 && ! fixed_regs[N]))
2474 /* A C expression which can inhibit the returning of certain function
2475 values in registers, based on the type of value. A nonzero value says
2476 to return the function value in memory, just as large structures are
2477 always returned. Here TYPE will be a C expression of type
2478 `tree', representing the data type of the value.
2480 Note that values of mode `BLKmode' must be explicitly
2481 handled by this macro. Also, the option `-fpcc-struct-return'
2482 takes effect regardless of this macro. On most systems, it is
2483 possible to leave the macro undefined; this causes a default
2484 definition to be used, whose value is the constant 1 for BLKmode
2485 values, and 0 otherwise.
2487 GCC normally converts 1 byte structures into chars, 2 byte
2488 structs into shorts, and 4 byte structs into ints, and returns
2489 them this way. Defining the following macro overrides this,
2490 to give us MIPS cc compatibility. */
2492 #define RETURN_IN_MEMORY(TYPE) \
2493 (TYPE_MODE (TYPE) == BLKmode)
2495 /* A code distinguishing the floating point format of the target
2496 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2497 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2499 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2502 /* Define a data type for recording info about an argument list
2503 during the scan of that argument list. This data type should
2504 hold all necessary information about the function itself
2505 and about the args processed so far, enough to enable macros
2506 such as FUNCTION_ARG to determine where the next arg should go.
2508 On the mips16, we need to keep track of which floating point
2509 arguments were passed in general registers, but would have been
2510 passed in the FP regs if this were a 32 bit function, so that we
2511 can move them to the FP regs if we wind up calling a 32 bit
2512 function. We record this information in fp_code, encoded in base
2513 four. A zero digit means no floating point argument, a one digit
2514 means an SFmode argument, and a two digit means a DFmode argument,
2515 and a three digit is not used. The low order digit is the first
2516 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2517 an SFmode argument. ??? A more sophisticated approach will be
2518 needed if MIPS_ABI != ABI_32. */
2520 typedef struct mips_args {
2521 int gp_reg_found; /* whether a gp register was found yet */
2522 unsigned int arg_number; /* argument number */
2523 unsigned int arg_words; /* # total words the arguments take */
2524 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2525 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2526 int fp_code; /* Mode of FP arguments (mips16) */
2527 unsigned int num_adjusts; /* number of adjustments made */
2528 /* Adjustments made to args pass in regs. */
2529 /* ??? The size is doubled to work around a
2530 bug in the code that sets the adjustments
2532 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2535 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2536 for a call to a function whose data type is FNTYPE.
2537 For a library call, FNTYPE is 0.
2541 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2542 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2544 /* Update the data in CUM to advance over an argument
2545 of mode MODE and data type TYPE.
2546 (TYPE is null for libcalls where that information may not be available.) */
2548 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2549 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2551 /* Determine where to put an argument to a function.
2552 Value is zero to push the argument on the stack,
2553 or a hard register in which to store the argument.
2555 MODE is the argument's machine mode.
2556 TYPE is the data type of the argument (as a tree).
2557 This is null for libcalls where that information may
2559 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2560 the preceding args and about the function being called.
2561 NAMED is nonzero if this argument is a named parameter
2562 (otherwise it is an extra parameter matching an ellipsis). */
2564 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2565 function_arg( &CUM, MODE, TYPE, NAMED)
2567 /* For an arg passed partly in registers and partly in memory,
2568 this is the number of registers used.
2569 For args passed entirely in registers or entirely in memory, zero. */
2571 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2572 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2574 /* If defined, a C expression that gives the alignment boundary, in
2575 bits, of an argument with the specified mode and type. If it is
2576 not defined, `PARM_BOUNDARY' is used for all arguments. */
2578 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2580 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2582 : TYPE_ALIGN(TYPE)) \
2583 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2585 : GET_MODE_ALIGNMENT(MODE)))
2588 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2590 #define MUST_SAVE_REGISTER(regno) \
2591 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2592 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2593 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2595 /* ALIGN FRAMES on double word boundaries */
2596 #ifndef MIPS_STACK_ALIGN
2597 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2601 /* Define the `__builtin_va_list' type for the ABI. */
2602 #define BUILD_VA_LIST_TYPE(VALIST) \
2603 (VALIST) = mips_build_va_list ()
2605 /* Implement `va_start' for varargs and stdarg. */
2606 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2607 mips_va_start (stdarg, valist, nextarg)
2609 /* Implement `va_arg'. */
2610 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2611 mips_va_arg (valist, type)
2613 /* Output assembler code to FILE to increment profiler label # LABELNO
2614 for profiling a function entry. */
2616 #define FUNCTION_PROFILER(FILE, LABELNO) \
2618 if (TARGET_MIPS16) \
2619 sorry ("mips16 function profiling"); \
2620 fprintf (FILE, "\t.set\tnoreorder\n"); \
2621 fprintf (FILE, "\t.set\tnoat\n"); \
2622 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2623 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2624 fprintf (FILE, "\tjal\t_mcount\n"); \
2626 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2627 TARGET_64BIT ? "dsubu" : "subu", \
2628 reg_names[STACK_POINTER_REGNUM], \
2629 reg_names[STACK_POINTER_REGNUM], \
2630 Pmode == DImode ? 16 : 8); \
2631 fprintf (FILE, "\t.set\treorder\n"); \
2632 fprintf (FILE, "\t.set\tat\n"); \
2635 /* Define this macro if the code for function profiling should come
2636 before the function prologue. Normally, the profiling code comes
2639 /* #define PROFILE_BEFORE_PROLOGUE */
2641 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2642 the stack pointer does not matter. The value is tested only in
2643 functions that have frame pointers.
2644 No definition is equivalent to always zero. */
2646 #define EXIT_IGNORE_STACK 1
2649 /* A C statement to output, on the stream FILE, assembler code for a
2650 block of data that contains the constant parts of a trampoline.
2651 This code should not include a label--the label is taken care of
2654 #define TRAMPOLINE_TEMPLATE(STREAM) \
2656 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2657 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2658 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2659 if (Pmode == DImode) \
2661 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2662 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2666 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2667 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2669 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2670 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2671 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2672 if (Pmode == DImode) \
2674 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2675 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2679 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2680 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2684 /* A C expression for the size in bytes of the trampoline, as an
2687 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2689 /* Alignment required for trampolines, in bits. */
2691 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2693 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2694 program and data caches. */
2696 #ifndef CACHE_FLUSH_FUNC
2697 #define CACHE_FLUSH_FUNC "_flush_cache"
2700 /* A C statement to initialize the variable parts of a trampoline.
2701 ADDR is an RTX for the address of the trampoline; FNADDR is an
2702 RTX for the address of the nested function; STATIC_CHAIN is an
2703 RTX for the static chain value that should be passed to the
2704 function when it is called. */
2706 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2709 if (Pmode == DImode) \
2711 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2712 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2716 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2717 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2720 /* Flush both caches. We need to flush the data cache in case \
2721 the system has a write-back cache. */ \
2722 /* ??? Should check the return value for errors. */ \
2723 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2724 0, VOIDmode, 3, addr, Pmode, \
2725 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2726 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2729 /* Addressing modes, and classification of registers for them. */
2731 /* #define HAVE_POST_INCREMENT 0 */
2732 /* #define HAVE_POST_DECREMENT 0 */
2734 /* #define HAVE_PRE_DECREMENT 0 */
2735 /* #define HAVE_PRE_INCREMENT 0 */
2737 /* These assume that REGNO is a hard or pseudo reg number.
2738 They give nonzero only if REGNO is a hard reg of the suitable class
2739 or a pseudo reg currently allocated to a suitable hard reg.
2740 These definitions are NOT overridden anywhere. */
2742 #define BASE_REG_P(regno, mode) \
2744 ? (M16_REG_P (regno) \
2745 || (regno) == FRAME_POINTER_REGNUM \
2746 || (regno) == ARG_POINTER_REGNUM \
2747 || ((regno) == STACK_POINTER_REGNUM \
2748 && (GET_MODE_SIZE (mode) == 4 \
2749 || GET_MODE_SIZE (mode) == 8))) \
2752 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2753 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2756 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2757 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2759 #define REGNO_OK_FOR_INDEX_P(regno) 0
2760 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2761 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2763 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2764 and check its validity for a certain class.
2765 We have two alternate definitions for each of them.
2766 The usual definition accepts all pseudo regs; the other rejects them all.
2767 The symbol REG_OK_STRICT causes the latter definition to be used.
2769 Most source files want to accept pseudo regs in the hope that
2770 they will get allocated to the class that the insn wants them to be in.
2771 Some source files that are used after register allocation
2772 need to be strict. */
2774 #ifndef REG_OK_STRICT
2775 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2776 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2778 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2779 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2782 #define REG_OK_FOR_INDEX_P(X) 0
2785 /* Maximum number of registers that can appear in a valid memory address. */
2787 #define MAX_REGS_PER_ADDRESS 1
2789 /* A C compound statement with a conditional `goto LABEL;' executed
2790 if X (an RTX) is a legitimate memory address on the target
2791 machine for a memory operand of mode MODE.
2793 It usually pays to define several simpler macros to serve as
2794 subroutines for this one. Otherwise it may be too complicated
2797 This macro must exist in two variants: a strict variant and a
2798 non-strict one. The strict variant is used in the reload pass.
2799 It must be defined so that any pseudo-register that has not been
2800 allocated a hard register is considered a memory reference. In
2801 contexts where some kind of register is required, a
2802 pseudo-register with no hard register must be rejected.
2804 The non-strict variant is used in other passes. It must be
2805 defined to accept all pseudo-registers in every context where
2806 some kind of register is required.
2808 Compiler source files that want to use the strict variant of
2809 this macro define the macro `REG_OK_STRICT'. You should use an
2810 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2811 in that case and the non-strict variant otherwise.
2813 Typically among the subroutines used to define
2814 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2815 acceptable registers for various purposes (one for base
2816 registers, one for index registers, and so on). Then only these
2817 subroutine macros need have two variants; the higher levels of
2818 macros may be the same whether strict or not.
2820 Normally, constant addresses which are the sum of a `symbol_ref'
2821 and an integer are stored inside a `const' RTX to mark them as
2822 constant. Therefore, there is no need to recognize such sums
2823 specifically as legitimate addresses. Normally you would simply
2824 recognize any `const' as legitimate.
2826 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2827 constant sums that are not marked with `const'. It assumes
2828 that a naked `plus' indicates indexing. If so, then you *must*
2829 reject such naked constant sums as illegitimate addresses, so
2830 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2832 On some machines, whether a symbolic address is legitimate
2833 depends on the section that the address refers to. On these
2834 machines, define the macro `ENCODE_SECTION_INFO' to store the
2835 information into the `symbol_ref', and then check for it here.
2836 When you see a `const', you will have to look inside it to find
2837 the `symbol_ref' in order to determine the section. */
2840 #define GO_PRINTF(x) fprintf(stderr, (x))
2841 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2842 #define GO_DEBUG_RTX(x) debug_rtx(x)
2845 #define GO_PRINTF(x)
2846 #define GO_PRINTF2(x,y)
2847 #define GO_DEBUG_RTX(x)
2850 #ifdef REG_OK_STRICT
2851 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2853 if (mips_legitimate_address_p (MODE, X, 1)) \
2857 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2859 if (mips_legitimate_address_p (MODE, X, 0)) \
2864 /* A C expression that is 1 if the RTX X is a constant which is a
2865 valid address. This is defined to be the same as `CONSTANT_P (X)',
2866 but rejecting CONST_DOUBLE. */
2867 /* When pic, we must reject addresses of the form symbol+large int.
2868 This is because an instruction `sw $4,s+70000' needs to be converted
2869 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2870 assembler would use $at as a temp to load in the large offset. In this
2871 case $at is already in use. We convert such problem addresses to
2872 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2873 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2874 #define CONSTANT_ADDRESS_P(X) \
2875 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2876 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2877 || (GET_CODE (X) == CONST \
2878 && ! (flag_pic && pic_address_needs_scratch (X)) \
2879 && (mips_abi == ABI_32 \
2880 || mips_abi == ABI_O64 \
2881 || mips_abi == ABI_EABI))) \
2882 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2884 /* Define this, so that when PIC, reload won't try to reload invalid
2885 addresses which require two reload registers. */
2887 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2889 /* Nonzero if the constant value X is a legitimate general operand.
2890 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2892 At present, GAS doesn't understand li.[sd], so don't allow it
2893 to be generated at present. Also, the MIPS assembler does not
2894 grok li.d Infinity. */
2896 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2897 Note that the Irix 6 assembler problem may already be fixed.
2898 Note also that the GET_CODE (X) == CONST test catches the mips16
2899 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2900 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2901 ABI_64 to work together, we'll need to fix this. */
2902 #define LEGITIMATE_CONSTANT_P(X) \
2903 ((GET_CODE (X) != CONST_DOUBLE \
2904 || mips_const_double_ok (X, GET_MODE (X))) \
2905 && ! (GET_CODE (X) == CONST \
2907 && (mips_abi == ABI_N32 \
2908 || mips_abi == ABI_64)) \
2909 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2911 /* A C compound statement that attempts to replace X with a valid
2912 memory address for an operand of mode MODE. WIN will be a C
2913 statement label elsewhere in the code; the macro definition may
2916 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2918 to avoid further processing if the address has become legitimate.
2920 X will always be the result of a call to `break_out_memory_refs',
2921 and OLDX will be the operand that was given to that function to
2924 The code generated by this macro should not alter the
2925 substructure of X. If it transforms X into a more legitimate
2926 form, it should assign X (which will always be a C variable) a
2929 It is not necessary for this macro to come up with a legitimate
2930 address. The compiler has standard ways of doing so in all
2931 cases. In fact, it is safe for this macro to do nothing. But
2932 often a machine-dependent strategy can generate better code.
2934 For the MIPS, transform:
2936 memory(X + <large int>)
2940 Y = <large int> & ~0x7fff;
2942 memory (Z + (<large int> & 0x7fff));
2944 This is for CSE to find several similar references, and only use one Z.
2946 When PIC, convert addresses of the form memory (symbol+large int) to
2947 memory (reg+large int). */
2950 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2952 register rtx xinsn = (X); \
2954 if (TARGET_DEBUG_B_MODE) \
2956 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2957 GO_DEBUG_RTX (xinsn); \
2960 if (mips_split_addresses && mips_check_split (X, MODE)) \
2962 /* ??? Is this ever executed? */ \
2963 X = gen_rtx_LO_SUM (Pmode, \
2964 copy_to_mode_reg (Pmode, \
2965 gen_rtx (HIGH, Pmode, X)), \
2970 if (GET_CODE (xinsn) == CONST \
2971 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2972 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2973 || (mips_abi != ABI_32 \
2974 && mips_abi != ABI_O64 \
2975 && mips_abi != ABI_EABI))) \
2977 rtx ptr_reg = gen_reg_rtx (Pmode); \
2978 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2980 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2982 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2983 if (SMALL_INT (constant)) \
2985 /* Otherwise we fall through so the code below will fix the \
2990 if (GET_CODE (xinsn) == PLUS) \
2992 register rtx xplus0 = XEXP (xinsn, 0); \
2993 register rtx xplus1 = XEXP (xinsn, 1); \
2994 register enum rtx_code code0 = GET_CODE (xplus0); \
2995 register enum rtx_code code1 = GET_CODE (xplus1); \
2997 if (code0 != REG && code1 == REG) \
2999 xplus0 = XEXP (xinsn, 1); \
3000 xplus1 = XEXP (xinsn, 0); \
3001 code0 = GET_CODE (xplus0); \
3002 code1 = GET_CODE (xplus1); \
3005 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3006 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3008 rtx int_reg = gen_reg_rtx (Pmode); \
3009 rtx ptr_reg = gen_reg_rtx (Pmode); \
3011 emit_move_insn (int_reg, \
3012 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3014 emit_insn (gen_rtx_SET (VOIDmode, \
3016 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3018 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3023 if (TARGET_DEBUG_B_MODE) \
3024 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3028 /* A C statement or compound statement with a conditional `goto
3029 LABEL;' executed if memory address X (an RTX) can have different
3030 meanings depending on the machine mode of the memory reference it
3033 Autoincrement and autodecrement addresses typically have
3034 mode-dependent effects because the amount of the increment or
3035 decrement is the size of the operand being addressed. Some
3036 machines have other mode-dependent addresses. Many RISC machines
3037 have no mode-dependent addresses.
3039 You may assume that ADDR is a valid address for the machine. */
3041 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3044 /* Define this macro if references to a symbol must be treated
3045 differently depending on something about the variable or
3046 function named by the symbol (such as what section it is in).
3048 The macro definition, if any, is executed immediately after the
3049 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3050 The value of the rtl will be a `mem' whose address is a
3053 The usual thing for this macro to do is to a flag in the
3054 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3055 name string in the `symbol_ref' (if one bit is not enough
3058 The best way to modify the name string is by adding text to the
3059 beginning, with suitable punctuation to prevent any ambiguity.
3060 Allocate the new name in `saveable_obstack'. You will have to
3061 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3062 and output the name accordingly.
3064 You can also check the information stored in the `symbol_ref' in
3065 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3066 `PRINT_OPERAND_ADDRESS'.
3068 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3071 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3072 symbols which are not in the .text section.
3074 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3075 constants which are put in the .text section. We also record the
3076 total length of all such strings; this total is used to decide
3077 whether we need to split the constant table, and need not be
3080 When not mips16 code nor embedded PIC, if a symbol is in a
3081 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3082 splitting the reference so that gas can generate a gp relative
3085 When TARGET_EMBEDDED_DATA is set, we assume that all const
3086 variables will be stored in ROM, which is too far from %gp to use
3087 %gprel addressing. Note that (1) we include "extern const"
3088 variables in this, which mips_select_section doesn't, and (2) we
3089 can't always tell if they're really const (they might be const C++
3090 objects with non-const constructors), so we err on the side of
3091 caution and won't use %gprel anyway (otherwise we'd have to defer
3092 this decision to the linker/loader). The handling of extern consts
3093 is why the DECL_INITIAL macros differ from mips_select_section.
3095 If you are changing this macro, you should look at
3096 mips_select_section and see if it needs a similar change. */
3098 #define ENCODE_SECTION_INFO(DECL) \
3101 if (TARGET_MIPS16) \
3103 if (TREE_CODE (DECL) == STRING_CST \
3104 && ! flag_writable_strings \
3105 /* If this string is from a function, and the function will \
3106 go in a gnu linkonce section, then we can't directly \
3107 access the string. This gets an assembler error \
3108 "unsupported PC relative reference to different section".\
3109 If we modify SELECT_SECTION to put it in function_section\
3110 instead of text_section, it still fails because \
3111 DECL_SECTION_NAME isn't set until assemble_start_function.\
3112 If we fix that, it still fails because strings are shared\
3113 among multiple functions, and we have cross section \
3114 references again. We force it to work by putting string \
3115 addresses in the constant pool and indirecting. */ \
3116 && (! current_function_decl \
3117 || ! DECL_ONE_ONLY (current_function_decl))) \
3119 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3120 mips_string_length += TREE_STRING_LENGTH (DECL); \
3124 if (TARGET_EMBEDDED_DATA \
3125 && (TREE_CODE (DECL) == VAR_DECL \
3126 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3127 && (!DECL_INITIAL (DECL) \
3128 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3130 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3133 else if (TARGET_EMBEDDED_PIC) \
3135 if (TREE_CODE (DECL) == VAR_DECL) \
3136 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3137 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3138 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3139 else if (TREE_CODE (DECL) == STRING_CST \
3140 && ! flag_writable_strings) \
3141 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3143 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3146 else if (TREE_CODE (DECL) == VAR_DECL \
3147 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3148 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3150 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3153 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3156 /* We can not perform GP optimizations on variables which are in \
3157 specific sections, except for .sdata and .sbss which are \
3159 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3160 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3162 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3164 if (size > 0 && size <= mips_section_threshold) \
3165 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3168 else if (HALF_PIC_P ()) \
3170 HALF_PIC_ENCODE (DECL); \
3175 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3176 'the start of the function that this code is output in'. */
3178 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3179 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3180 asm_fprintf ((FILE), "%U%s", \
3181 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3183 asm_fprintf ((FILE), "%U%s", (NAME))
3185 /* The mips16 wants the constant pool to be after the function,
3186 because the PC relative load instructions use unsigned offsets. */
3188 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3190 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3191 mips_string_length = 0;
3194 /* In mips16 mode, put most string constants after the function. */
3195 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3196 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3199 /* Specify the machine mode that this machine uses
3200 for the index in the tablejump instruction.
3201 ??? Using HImode in mips16 mode can cause overflow. However, the
3202 overflow is no more likely than the overflow in a branch
3203 instruction. Large functions can currently break in both ways. */
3204 #define CASE_VECTOR_MODE \
3205 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3207 /* Define as C expression which evaluates to nonzero if the tablejump
3208 instruction expects the table to contain offsets from the address of the
3210 Do not define this if the table should contain absolute addresses. */
3211 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3213 /* Specify the tree operation to be used to convert reals to integers. */
3214 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3216 /* This is the kind of divide that is easiest to do in the general case. */
3217 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3219 /* Define this as 1 if `char' should by default be signed; else as 0. */
3220 #ifndef DEFAULT_SIGNED_CHAR
3221 #define DEFAULT_SIGNED_CHAR 1
3224 /* Max number of bytes we can move from memory to memory
3225 in one reasonably fast instruction. */
3226 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3227 #define MAX_MOVE_MAX 8
3229 /* Define this macro as a C expression which is nonzero if
3230 accessing less than a word of memory (i.e. a `char' or a
3231 `short') is no faster than accessing a word of memory, i.e., if
3232 such access require more than one instruction or if there is no
3233 difference in cost between byte and (aligned) word loads.
3235 On RISC machines, it tends to generate better code to define
3236 this as 1, since it avoids making a QI or HI mode register. */
3237 #define SLOW_BYTE_ACCESS 1
3239 /* We assume that the store-condition-codes instructions store 0 for false
3240 and some other value for true. This is the value stored for true. */
3242 #define STORE_FLAG_VALUE 1
3244 /* Define this if zero-extension is slow (more than one real instruction). */
3245 #define SLOW_ZERO_EXTEND
3247 /* Define this to be nonzero if shift instructions ignore all but the low-order
3249 #define SHIFT_COUNT_TRUNCATED 1
3251 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3252 is done just by pretending it is already truncated. */
3253 /* In 64 bit mode, 32 bit instructions require that register values be properly
3254 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3255 converts a value >32 bits to a value <32 bits. */
3256 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3257 Something needs to be done about this. Perhaps not use any 32 bit
3258 instructions? Perhaps use PROMOTE_MODE? */
3259 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3260 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3262 /* Specify the machine mode that pointers have.
3263 After generation of rtl, the compiler makes no further distinction
3264 between pointers and any other objects of this machine mode.
3266 For MIPS we make pointers are the smaller of longs and gp-registers. */
3269 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3272 /* A function address in a call instruction
3273 is a word address (for indexing purposes)
3274 so give the MEM rtx a words's mode. */
3276 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3278 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3279 memset, instead of the BSD functions bcopy and bzero. */
3281 #if defined(MIPS_SYSV) || defined(OSF_OS)
3282 #define TARGET_MEM_FUNCTIONS
3286 /* A part of a C `switch' statement that describes the relative
3287 costs of constant RTL expressions. It must contain `case'
3288 labels for expression codes `const_int', `const', `symbol_ref',
3289 `label_ref' and `const_double'. Each case must ultimately reach
3290 a `return' statement to return the relative cost of the use of
3291 that kind of constant value in an expression. The cost may
3292 depend on the precise value of the constant, which is available
3293 for examination in X.
3295 CODE is the expression code--redundant, since it can be obtained
3296 with `GET_CODE (X)'. */
3298 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3300 if (! TARGET_MIPS16) \
3302 /* Always return 0, since we don't have different sized \
3303 instructions, hence different costs according to Richard \
3307 if ((OUTER_CODE) == SET) \
3309 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3311 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3312 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3313 return COSTS_N_INSNS (1); \
3315 return COSTS_N_INSNS (2); \
3317 /* A PLUS could be an address. We don't want to force an address \
3318 to use a register, so accept any signed 16 bit value without \
3320 if ((OUTER_CODE) == PLUS \
3321 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3323 /* A number between 1 and 8 inclusive is efficient for a shift. \
3324 Otherwise, we will need an extended instruction. */ \
3325 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3326 || (OUTER_CODE) == LSHIFTRT) \
3328 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3330 return COSTS_N_INSNS (1); \
3332 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3333 if ((OUTER_CODE) == XOR \
3334 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3336 /* We may be able to use slt or sltu for a comparison with a \
3337 signed 16 bit value. (The boundary conditions aren't quite \
3338 right, but this is just a heuristic anyhow.) */ \
3339 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3340 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3341 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3342 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3343 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3345 /* Equality comparisons with 0 are cheap. */ \
3346 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3347 && INTVAL (X) == 0) \
3350 /* Otherwise, work out the cost to load the value into a \
3352 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3353 return COSTS_N_INSNS (1); \
3354 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3355 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3356 return COSTS_N_INSNS (2); \
3358 return COSTS_N_INSNS (3); \
3361 return COSTS_N_INSNS (2); \
3365 rtx offset = const0_rtx; \
3366 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3368 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3370 /* Treat this like a signed 16 bit CONST_INT. */ \
3371 if ((OUTER_CODE) == PLUS) \
3373 else if ((OUTER_CODE) == SET) \
3374 return COSTS_N_INSNS (1); \
3376 return COSTS_N_INSNS (2); \
3379 if (GET_CODE (symref) == LABEL_REF) \
3380 return COSTS_N_INSNS (2); \
3382 if (GET_CODE (symref) != SYMBOL_REF) \
3383 return COSTS_N_INSNS (4); \
3385 /* let's be paranoid.... */ \
3386 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3387 return COSTS_N_INSNS (2); \
3389 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3393 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3395 case CONST_DOUBLE: \
3398 if (TARGET_MIPS16) \
3399 return COSTS_N_INSNS (4); \
3400 split_double (X, &high, &low); \
3401 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3402 || low == CONST0_RTX (GET_MODE (low))) \
3406 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3407 This can be used, for example, to indicate how costly a multiply
3408 instruction is. In writing this macro, you can use the construct
3409 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3411 This macro is optional; do not define it if the default cost
3412 assumptions are adequate for the target machine.
3414 If -mdebugd is used, change the multiply cost to 2, so multiply by
3415 a constant isn't converted to a series of shifts. This helps
3416 strength reduction, and also makes it easier to identify what the
3417 compiler is doing. */
3419 /* ??? Fix this to be right for the R8000. */
3420 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3423 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3424 if (simple_memory_operand (X, GET_MODE (X))) \
3425 return COSTS_N_INSNS (num_words); \
3427 return COSTS_N_INSNS (2*num_words); \
3431 return COSTS_N_INSNS (6); \
3434 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3439 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3440 return COSTS_N_INSNS (2); \
3447 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3448 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3454 enum machine_mode xmode = GET_MODE (X); \
3455 if (xmode == SFmode || xmode == DFmode) \
3456 return COSTS_N_INSNS (1); \
3458 return COSTS_N_INSNS (4); \
3464 enum machine_mode xmode = GET_MODE (X); \
3465 if (xmode == SFmode || xmode == DFmode) \
3469 return COSTS_N_INSNS (2); \
3470 else if (TUNE_MIPS6000) \
3471 return COSTS_N_INSNS (3); \
3473 return COSTS_N_INSNS (6); \
3476 if (xmode == DImode && !TARGET_64BIT) \
3477 return COSTS_N_INSNS (4); \
3483 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3490 enum machine_mode xmode = GET_MODE (X); \
3491 if (xmode == SFmode) \
3496 return COSTS_N_INSNS (4); \
3497 else if (TUNE_MIPS6000) \
3498 return COSTS_N_INSNS (5); \
3500 return COSTS_N_INSNS (7); \
3503 if (xmode == DFmode) \
3508 return COSTS_N_INSNS (5); \
3509 else if (TUNE_MIPS6000) \
3510 return COSTS_N_INSNS (6); \
3512 return COSTS_N_INSNS (8); \
3515 if (TUNE_MIPS3000) \
3516 return COSTS_N_INSNS (12); \
3517 else if (TUNE_MIPS3900) \
3518 return COSTS_N_INSNS (2); \
3519 else if (TUNE_MIPS6000) \
3520 return COSTS_N_INSNS (17); \
3521 else if (TUNE_MIPS5000) \
3522 return COSTS_N_INSNS (5); \
3524 return COSTS_N_INSNS (10); \
3530 enum machine_mode xmode = GET_MODE (X); \
3531 if (xmode == SFmode) \
3535 return COSTS_N_INSNS (12); \
3536 else if (TUNE_MIPS6000) \
3537 return COSTS_N_INSNS (15); \
3539 return COSTS_N_INSNS (23); \
3542 if (xmode == DFmode) \
3546 return COSTS_N_INSNS (19); \
3547 else if (TUNE_MIPS6000) \
3548 return COSTS_N_INSNS (16); \
3550 return COSTS_N_INSNS (36); \
3553 /* fall through */ \
3559 return COSTS_N_INSNS (35); \
3560 else if (TUNE_MIPS6000) \
3561 return COSTS_N_INSNS (38); \
3562 else if (TUNE_MIPS5000) \
3563 return COSTS_N_INSNS (36); \
3565 return COSTS_N_INSNS (69); \
3568 /* A sign extend from SImode to DImode in 64 bit mode is often \
3569 zero instructions, because the result can often be used \
3570 directly by another instruction; we'll call it one. */ \
3571 if (TARGET_64BIT && GET_MODE (X) == DImode \
3572 && GET_MODE (XEXP (X, 0)) == SImode) \
3573 return COSTS_N_INSNS (1); \
3575 return COSTS_N_INSNS (2); \
3578 if (TARGET_64BIT && GET_MODE (X) == DImode \
3579 && GET_MODE (XEXP (X, 0)) == SImode) \
3580 return COSTS_N_INSNS (2); \
3582 return COSTS_N_INSNS (1);
3584 /* An expression giving the cost of an addressing mode that
3585 contains ADDRESS. If not defined, the cost is computed from the
3586 form of the ADDRESS expression and the `CONST_COSTS' values.
3588 For most CISC machines, the default cost is a good approximation
3589 of the true cost of the addressing mode. However, on RISC
3590 machines, all instructions normally have the same length and
3591 execution time. Hence all addresses will have equal costs.
3593 In cases where more than one form of an address is known, the
3594 form with the lowest cost will be used. If multiple forms have
3595 the same, lowest, cost, the one that is the most complex will be
3598 For example, suppose an address that is equal to the sum of a
3599 register and a constant is used twice in the same basic block.
3600 When this macro is not defined, the address will be computed in
3601 a register and memory references will be indirect through that
3602 register. On machines where the cost of the addressing mode
3603 containing the sum is no higher than that of a simple indirect
3604 reference, this will produce an additional instruction and
3605 possibly require an additional register. Proper specification
3606 of this macro eliminates this overhead for such machines.
3608 Similar use of this macro is made in strength reduction of loops.
3610 ADDRESS need not be valid as an address. In such a case, the
3611 cost is not relevant and can be any value; invalid addresses
3612 need not be assigned a different cost.
3614 On machines where an address involving more than one register is
3615 as cheap as an address computation involving only one register,
3616 defining `ADDRESS_COST' to reflect this can cause two registers
3617 to be live over a region of code where only one would have been
3618 if `ADDRESS_COST' were not defined in that manner. This effect
3619 should be considered in the definition of this macro.
3620 Equivalent costs should probably only be given to addresses with
3621 different numbers of registers on machines with lots of registers.
3623 This macro will normally either not be defined or be defined as
3626 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3628 /* A C expression for the cost of moving data from a register in
3629 class FROM to one in class TO. The classes are expressed using
3630 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3631 the default; other values are interpreted relative to that.
3633 It is not required that the cost always equal 2 when FROM is the
3634 same as TO; on some machines it is expensive to move between
3635 registers if they are not general registers.
3637 If reload sees an insn consisting of a single `set' between two
3638 hard registers, and if `REGISTER_MOVE_COST' applied to their
3639 classes returns a value of 2, reload does not check to ensure
3640 that the constraints of the insn are met. Setting a cost of
3641 other than 2 will allow reload to verify that the constraints are
3642 met. You should do this if the `movM' pattern's constraints do
3643 not allow such copying.
3645 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3646 registers the same as for one of moving general registers to
3647 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3648 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3649 isn't clear if it is wise. And it might not work in all cases. We
3650 could solve the DImode LO reg problem by using a multiply, just like
3651 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3652 by using divide instructions. divu puts the remainder in the HI
3653 reg, so doing a divide by -1 will move the value in the HI reg for
3654 all values except -1. We could handle that case by using a signed
3655 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3656 compare/branch to test the input value to see which instruction we
3657 need to use. This gets pretty messy, but it is feasible. */
3659 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3660 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3661 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3662 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3663 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3664 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3665 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3666 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3667 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3668 : (((FROM) == HI_REG || (FROM) == LO_REG \
3669 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3670 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3671 : (((TO) == HI_REG || (TO) == LO_REG \
3672 || (TO) == MD_REGS || (TO) == HILO_REG) \
3673 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3674 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3675 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3678 /* ??? Fix this to be right for the R8000. */
3679 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3680 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3681 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3683 /* Define if copies to/from condition code registers should be avoided.
3685 This is needed for the MIPS because reload_outcc is not complete;
3686 it needs to handle cases where the source is a general or another
3687 condition code register. */
3688 #define AVOID_CCMODE_COPIES
3690 /* A C expression for the cost of a branch instruction. A value of
3691 1 is the default; other values are interpreted relative to that. */
3693 /* ??? Fix this to be right for the R8000. */
3694 #define BRANCH_COST \
3696 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3699 /* If defined, modifies the length assigned to instruction INSN as a
3700 function of the context in which it is used. LENGTH is an lvalue
3701 that contains the initially computed length of the insn and should
3702 be updated with the correct length of the insn. */
3703 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3704 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3707 /* Optionally define this if you have added predicates to
3708 `MACHINE.c'. This macro is called within an initializer of an
3709 array of structures. The first field in the structure is the
3710 name of a predicate and the second field is an array of rtl
3711 codes. For each predicate, list all rtl codes that can be in
3712 expressions matched by the predicate. The list should have a
3713 trailing comma. Here is an example of two entries in the list
3714 for a typical RISC machine:
3716 #define PREDICATE_CODES \
3717 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3718 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3720 Defining this macro does not affect the generated code (however,
3721 incorrect definitions that omit an rtl code that may be matched
3722 by the predicate can cause the compiler to malfunction).
3723 Instead, it allows the table built by `genrecog' to be more
3724 compact and efficient, thus speeding up the compiler. The most
3725 important predicates to include in the list specified by this
3726 macro are thoses used in the most insn patterns. */
3728 #define PREDICATE_CODES \
3729 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3730 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3731 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3732 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3733 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3734 {"small_int", { CONST_INT }}, \
3735 {"large_int", { CONST_INT }}, \
3736 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3737 {"const_float_1_operand", { CONST_DOUBLE }}, \
3738 {"simple_memory_operand", { MEM, SUBREG }}, \
3739 {"equality_op", { EQ, NE }}, \
3740 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3742 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3743 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3744 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3745 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3746 SYMBOL_REF, LABEL_REF, SUBREG, \
3748 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3749 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3750 MEM, SIGN_EXTEND }}, \
3751 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3752 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3754 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3756 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3758 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3759 SYMBOL_REF, LABEL_REF, SUBREG, \
3760 REG, SIGN_EXTEND }}, \
3761 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3762 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3763 CONST_DOUBLE, CONST }}, \
3764 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3765 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3767 /* A list of predicates that do special things with modes, and so
3768 should not elicit warnings for VOIDmode match_operand. */
3770 #define SPECIAL_MODE_PREDICATES \
3771 "pc_or_label_operand",
3774 /* If defined, a C statement to be executed just prior to the
3775 output of assembler code for INSN, to modify the extracted
3776 operands so they will be output differently.
3778 Here the argument OPVEC is the vector containing the operands
3779 extracted from INSN, and NOPERANDS is the number of elements of
3780 the vector which contain meaningful data for this insn. The
3781 contents of this vector are what will be used to convert the
3782 insn template into assembler code, so you can change the
3783 assembler output by changing the contents of the vector.
3785 We use it to check if the current insn needs a nop in front of it
3786 because of load delays, and also to update the delay slot
3789 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3790 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3793 /* Control the assembler format that we output. */
3795 /* Output at beginning of assembler file.
3796 If we are optimizing to use the global pointer, create a temporary
3797 file to hold all of the text stuff, and write it out to the end.
3798 This is needed because the MIPS assembler is evidently one pass,
3799 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3800 declaration when the code is processed, it generates a two
3801 instruction sequence. */
3803 #undef ASM_FILE_START
3804 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3806 /* Output to assembler file text saying following lines
3807 may contain character constants, extra white space, comments, etc. */
3810 #define ASM_APP_ON " #APP\n"
3813 /* Output to assembler file text saying following lines
3814 no longer contain unusual constructs. */
3817 #define ASM_APP_OFF " #NO_APP\n"
3820 /* How to refer to registers in assembler output.
3821 This sequence is indexed by compiler's hard-register-number (see above).
3823 In order to support the two different conventions for register names,
3824 we use the name of a table set up in mips.c, which is overwritten
3825 if -mrnames is used. */
3827 #define REGISTER_NAMES \
3829 &mips_reg_names[ 0][0], \
3830 &mips_reg_names[ 1][0], \
3831 &mips_reg_names[ 2][0], \
3832 &mips_reg_names[ 3][0], \
3833 &mips_reg_names[ 4][0], \
3834 &mips_reg_names[ 5][0], \
3835 &mips_reg_names[ 6][0], \
3836 &mips_reg_names[ 7][0], \
3837 &mips_reg_names[ 8][0], \
3838 &mips_reg_names[ 9][0], \
3839 &mips_reg_names[10][0], \
3840 &mips_reg_names[11][0], \
3841 &mips_reg_names[12][0], \
3842 &mips_reg_names[13][0], \
3843 &mips_reg_names[14][0], \
3844 &mips_reg_names[15][0], \
3845 &mips_reg_names[16][0], \
3846 &mips_reg_names[17][0], \
3847 &mips_reg_names[18][0], \
3848 &mips_reg_names[19][0], \
3849 &mips_reg_names[20][0], \
3850 &mips_reg_names[21][0], \
3851 &mips_reg_names[22][0], \
3852 &mips_reg_names[23][0], \
3853 &mips_reg_names[24][0], \
3854 &mips_reg_names[25][0], \
3855 &mips_reg_names[26][0], \
3856 &mips_reg_names[27][0], \
3857 &mips_reg_names[28][0], \
3858 &mips_reg_names[29][0], \
3859 &mips_reg_names[30][0], \
3860 &mips_reg_names[31][0], \
3861 &mips_reg_names[32][0], \
3862 &mips_reg_names[33][0], \
3863 &mips_reg_names[34][0], \
3864 &mips_reg_names[35][0], \
3865 &mips_reg_names[36][0], \
3866 &mips_reg_names[37][0], \
3867 &mips_reg_names[38][0], \
3868 &mips_reg_names[39][0], \
3869 &mips_reg_names[40][0], \
3870 &mips_reg_names[41][0], \
3871 &mips_reg_names[42][0], \
3872 &mips_reg_names[43][0], \
3873 &mips_reg_names[44][0], \
3874 &mips_reg_names[45][0], \
3875 &mips_reg_names[46][0], \
3876 &mips_reg_names[47][0], \
3877 &mips_reg_names[48][0], \
3878 &mips_reg_names[49][0], \
3879 &mips_reg_names[50][0], \
3880 &mips_reg_names[51][0], \
3881 &mips_reg_names[52][0], \
3882 &mips_reg_names[53][0], \
3883 &mips_reg_names[54][0], \
3884 &mips_reg_names[55][0], \
3885 &mips_reg_names[56][0], \
3886 &mips_reg_names[57][0], \
3887 &mips_reg_names[58][0], \
3888 &mips_reg_names[59][0], \
3889 &mips_reg_names[60][0], \
3890 &mips_reg_names[61][0], \
3891 &mips_reg_names[62][0], \
3892 &mips_reg_names[63][0], \
3893 &mips_reg_names[64][0], \
3894 &mips_reg_names[65][0], \
3895 &mips_reg_names[66][0], \
3896 &mips_reg_names[67][0], \
3897 &mips_reg_names[68][0], \
3898 &mips_reg_names[69][0], \
3899 &mips_reg_names[70][0], \
3900 &mips_reg_names[71][0], \
3901 &mips_reg_names[72][0], \
3902 &mips_reg_names[73][0], \
3903 &mips_reg_names[74][0], \
3904 &mips_reg_names[75][0], \
3907 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3908 So define this for it. */
3909 #define DEBUG_REGISTER_NAMES \
3911 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3912 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3913 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3914 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3915 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3916 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3917 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3918 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3919 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3920 "$fcc5","$fcc6","$fcc7","$rap" \
3923 /* If defined, a C initializer for an array of structures
3924 containing a name and a register number. This macro defines
3925 additional names for hard registers, thus allowing the `asm'
3926 option in declarations to refer to registers using alternate
3929 We define both names for the integer registers here. */
3931 #define ADDITIONAL_REGISTER_NAMES \
3933 { "$0", 0 + GP_REG_FIRST }, \
3934 { "$1", 1 + GP_REG_FIRST }, \
3935 { "$2", 2 + GP_REG_FIRST }, \
3936 { "$3", 3 + GP_REG_FIRST }, \
3937 { "$4", 4 + GP_REG_FIRST }, \
3938 { "$5", 5 + GP_REG_FIRST }, \
3939 { "$6", 6 + GP_REG_FIRST }, \
3940 { "$7", 7 + GP_REG_FIRST }, \
3941 { "$8", 8 + GP_REG_FIRST }, \
3942 { "$9", 9 + GP_REG_FIRST }, \
3943 { "$10", 10 + GP_REG_FIRST }, \
3944 { "$11", 11 + GP_REG_FIRST }, \
3945 { "$12", 12 + GP_REG_FIRST }, \
3946 { "$13", 13 + GP_REG_FIRST }, \
3947 { "$14", 14 + GP_REG_FIRST }, \
3948 { "$15", 15 + GP_REG_FIRST }, \
3949 { "$16", 16 + GP_REG_FIRST }, \
3950 { "$17", 17 + GP_REG_FIRST }, \
3951 { "$18", 18 + GP_REG_FIRST }, \
3952 { "$19", 19 + GP_REG_FIRST }, \
3953 { "$20", 20 + GP_REG_FIRST }, \
3954 { "$21", 21 + GP_REG_FIRST }, \
3955 { "$22", 22 + GP_REG_FIRST }, \
3956 { "$23", 23 + GP_REG_FIRST }, \
3957 { "$24", 24 + GP_REG_FIRST }, \
3958 { "$25", 25 + GP_REG_FIRST }, \
3959 { "$26", 26 + GP_REG_FIRST }, \
3960 { "$27", 27 + GP_REG_FIRST }, \
3961 { "$28", 28 + GP_REG_FIRST }, \
3962 { "$29", 29 + GP_REG_FIRST }, \
3963 { "$30", 30 + GP_REG_FIRST }, \
3964 { "$31", 31 + GP_REG_FIRST }, \
3965 { "$sp", 29 + GP_REG_FIRST }, \
3966 { "$fp", 30 + GP_REG_FIRST }, \
3967 { "at", 1 + GP_REG_FIRST }, \
3968 { "v0", 2 + GP_REG_FIRST }, \
3969 { "v1", 3 + GP_REG_FIRST }, \
3970 { "a0", 4 + GP_REG_FIRST }, \
3971 { "a1", 5 + GP_REG_FIRST }, \
3972 { "a2", 6 + GP_REG_FIRST }, \
3973 { "a3", 7 + GP_REG_FIRST }, \
3974 { "t0", 8 + GP_REG_FIRST }, \
3975 { "t1", 9 + GP_REG_FIRST }, \
3976 { "t2", 10 + GP_REG_FIRST }, \
3977 { "t3", 11 + GP_REG_FIRST }, \
3978 { "t4", 12 + GP_REG_FIRST }, \
3979 { "t5", 13 + GP_REG_FIRST }, \
3980 { "t6", 14 + GP_REG_FIRST }, \
3981 { "t7", 15 + GP_REG_FIRST }, \
3982 { "s0", 16 + GP_REG_FIRST }, \
3983 { "s1", 17 + GP_REG_FIRST }, \
3984 { "s2", 18 + GP_REG_FIRST }, \
3985 { "s3", 19 + GP_REG_FIRST }, \
3986 { "s4", 20 + GP_REG_FIRST }, \
3987 { "s5", 21 + GP_REG_FIRST }, \
3988 { "s6", 22 + GP_REG_FIRST }, \
3989 { "s7", 23 + GP_REG_FIRST }, \
3990 { "t8", 24 + GP_REG_FIRST }, \
3991 { "t9", 25 + GP_REG_FIRST }, \
3992 { "k0", 26 + GP_REG_FIRST }, \
3993 { "k1", 27 + GP_REG_FIRST }, \
3994 { "gp", 28 + GP_REG_FIRST }, \
3995 { "sp", 29 + GP_REG_FIRST }, \
3996 { "fp", 30 + GP_REG_FIRST }, \
3997 { "ra", 31 + GP_REG_FIRST }, \
3998 { "$sp", 29 + GP_REG_FIRST }, \
3999 { "$fp", 30 + GP_REG_FIRST } \
4002 /* A C compound statement to output to stdio stream STREAM the
4003 assembler syntax for an instruction operand X. X is an RTL
4006 CODE is a value that can be used to specify one of several ways
4007 of printing the operand. It is used when identical operands
4008 must be printed differently depending on the context. CODE
4009 comes from the `%' specification that was used to request
4010 printing of the operand. If the specification was just `%DIGIT'
4011 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4012 is the ASCII code for LTR.
4014 If X is a register, this macro should print the register's name.
4015 The names can be found in an array `reg_names' whose type is
4016 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4018 When the machine description has a specification `%PUNCT' (a `%'
4019 followed by a punctuation character), this macro is called with
4020 a null pointer for X and the punctuation character for CODE.
4022 See mips.c for the MIPS specific codes. */
4024 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4026 /* A C expression which evaluates to true if CODE is a valid
4027 punctuation character for use in the `PRINT_OPERAND' macro. If
4028 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4029 punctuation characters (except for the standard one, `%') are
4030 used in this way. */
4032 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4034 /* A C compound statement to output to stdio stream STREAM the
4035 assembler syntax for an instruction operand that is a memory
4036 reference whose address is ADDR. ADDR is an RTL expression.
4038 On some machines, the syntax for a symbolic address depends on
4039 the section that the address refers to. On these machines,
4040 define the macro `ENCODE_SECTION_INFO' to store the information
4041 into the `symbol_ref', and then check for it here. */
4043 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4046 /* A C statement, to be executed after all slot-filler instructions
4047 have been output. If necessary, call `dbr_sequence_length' to
4048 determine the number of slots filled in a sequence (zero if not
4049 currently outputting a sequence), to decide how many no-ops to
4050 output, or whatever.
4052 Don't define this macro if it has nothing to do, but it is
4053 helpful in reading assembly output if the extent of the delay
4054 sequence is made explicit (e.g. with white space).
4056 Note that output routines for instructions with delay slots must
4057 be prepared to deal with not being output as part of a sequence
4058 (i.e. when the scheduling pass is not run, or when no slot
4059 fillers could be found.) The variable `final_sequence' is null
4060 when not processing a sequence, otherwise it contains the
4061 `sequence' rtx being output. */
4063 #define DBR_OUTPUT_SEQEND(STREAM) \
4066 if (set_nomacro > 0 && --set_nomacro == 0) \
4067 fputs ("\t.set\tmacro\n", STREAM); \
4069 if (set_noreorder > 0 && --set_noreorder == 0) \
4070 fputs ("\t.set\treorder\n", STREAM); \
4072 dslots_jump_filled++; \
4073 fputs ("\n", STREAM); \
4078 /* How to tell the debugger about changes of source files. Note, the
4079 mips ECOFF format cannot deal with changes of files inside of
4080 functions, which means the output of parser generators like bison
4081 is generally not debuggable without using the -l switch. Lose,
4082 lose, lose. Silicon graphics seems to want all .file's hardwired
4085 #ifndef SET_FILE_NUMBER
4086 #define SET_FILE_NUMBER() ++num_source_filenames
4089 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4090 mips_output_filename (STREAM, NAME)
4092 /* This is defined so that it can be overridden in iris6.h. */
4093 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4096 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4097 output_quoted_string (STREAM, NAME); \
4098 fputs ("\n", STREAM); \
4102 /* This is how to output a note the debugger telling it the line number
4103 to which the following sequence of instructions corresponds.
4104 Silicon graphics puts a label after each .loc. */
4106 #ifndef LABEL_AFTER_LOC
4107 #define LABEL_AFTER_LOC(STREAM)
4110 #ifndef ASM_OUTPUT_SOURCE_LINE
4111 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4112 mips_output_lineno (STREAM, LINE)
4115 /* The MIPS implementation uses some labels for its own purpose. The
4116 following lists what labels are created, and are all formed by the
4117 pattern $L[a-z].*. The machine independent portion of GCC creates
4118 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4120 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4121 $Lb[0-9]+ Begin blocks for MIPS debug support
4122 $Lc[0-9]+ Label for use in s<xx> operation.
4123 $Le[0-9]+ End blocks for MIPS debug support
4124 $Lp\..+ Half-pic labels. */
4126 /* This is how to output the definition of a user-level label named NAME,
4127 such as the label on a static function or variable NAME.
4129 If we are optimizing the gp, remember that this label has been put
4130 out, so we know not to emit an .extern for it in mips_asm_file_end.
4131 We use one of the common bits in the IDENTIFIER tree node for this,
4132 since those bits seem to be unused, and we don't have any method
4133 of getting the decl nodes from the name. */
4135 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4137 assemble_name (STREAM, NAME); \
4138 fputs (":\n", STREAM); \
4142 /* A C statement (sans semicolon) to output to the stdio stream
4143 STREAM any text necessary for declaring the name NAME of an
4144 initialized variable which is being defined. This macro must
4145 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4146 The argument DECL is the `VAR_DECL' tree node representing the
4149 If this macro is not defined, then the variable name is defined
4150 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4152 #undef ASM_DECLARE_OBJECT_NAME
4153 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4156 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4157 HALF_PIC_DECLARE (NAME); \
4162 /* This is how to output a command to make the user-level label named NAME
4163 defined for reference from other files. */
4165 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4167 fputs ("\t.globl\t", STREAM); \
4168 assemble_name (STREAM, NAME); \
4169 fputs ("\n", STREAM); \
4172 /* This says how to define a global common symbol. */
4174 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4176 /* If the target wants uninitialized const declarations in \
4177 .rdata then don't put them in .comm */ \
4178 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4179 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4180 && (DECL_INITIAL (DECL) == 0 \
4181 || DECL_INITIAL (DECL) == error_mark_node)) \
4183 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4184 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4186 READONLY_DATA_SECTION (); \
4187 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4188 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4192 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4197 /* This says how to define a local common symbol (ie, not visible to
4200 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4201 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4204 /* This says how to output an external. It would be possible not to
4205 output anything and let undefined symbol become external. However
4206 the assembler uses length information on externals to allocate in
4207 data/sdata bss/sbss, thereby saving exec time. */
4209 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4210 mips_output_external(STREAM,DECL,NAME)
4212 /* This says what to print at the end of the assembly file */
4214 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4217 /* Play switch file games if we're optimizing the global pointer. */
4220 #define TEXT_SECTION() \
4222 extern FILE *asm_out_text_file; \
4223 if (TARGET_FILE_SWITCHING) \
4224 asm_out_file = asm_out_text_file; \
4225 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4226 fputc ('\n', asm_out_file); \
4230 /* This is how to declare a function name. The actual work of
4231 emitting the label is moved to function_prologue, so that we can
4232 get the line number correctly emitted before the .ent directive,
4233 and after any .file directives. */
4235 #undef ASM_DECLARE_FUNCTION_NAME
4236 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4237 HALF_PIC_DECLARE (NAME)
4239 /* This is how to output an internal numbered label where
4240 PREFIX is the class of label and NUM is the number within the class. */
4242 #undef ASM_OUTPUT_INTERNAL_LABEL
4243 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4244 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4246 /* This is how to store into the string LABEL
4247 the symbol_ref name of an internal numbered label where
4248 PREFIX is the class of label and NUM is the number within the class.
4249 This is suitable for output with `assemble_name'. */
4251 #undef ASM_GENERATE_INTERNAL_LABEL
4252 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4253 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4255 /* This is how to output an assembler line defining a `double' constant. */
4257 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4258 mips_output_double (STREAM, VALUE)
4261 /* This is how to output an assembler line defining a `float' constant. */
4263 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4264 mips_output_float (STREAM, VALUE)
4267 /* This is how to output an assembler line defining an `int' constant. */
4269 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4271 fprintf (STREAM, "\t.word\t"); \
4272 output_addr_const (STREAM, (VALUE)); \
4273 fprintf (STREAM, "\n"); \
4276 /* Likewise for 64 bit, `char' and `short' constants.
4278 FIXME: operand_subword can't handle some complex constant expressions
4279 that output_addr_const can (for example it does not call
4280 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4281 rely on that to avoid operand_subword for most of the cases where this
4282 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4283 or the same case with the type of 'i' changed to long long.
4287 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4289 if (TARGET_64BIT || TARGET_GAS) \
4291 fprintf (STREAM, "\t.dword\t"); \
4292 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4293 /* We can't use 'X' for negative numbers, because then we won't \
4294 get the right value for the upper 32 bits. */ \
4295 output_addr_const (STREAM, VALUE); \
4297 /* We must use 'X', because otherwise LONG_MIN will print as \
4298 a number that the Irix 6 assembler won't accept. */ \
4299 print_operand (STREAM, VALUE, 'X'); \
4300 fprintf (STREAM, "\n"); \
4304 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4305 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4306 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4307 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4311 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4313 fprintf (STREAM, "\t.half\t"); \
4314 output_addr_const (STREAM, (VALUE)); \
4315 fprintf (STREAM, "\n"); \
4318 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4320 fprintf (STREAM, "\t.byte\t"); \
4321 output_addr_const (STREAM, (VALUE)); \
4322 fprintf (STREAM, "\n"); \
4325 /* This is how to output an assembler line for a numeric constant byte. */
4327 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4328 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4330 /* This is how to output an element of a case-vector that is absolute. */
4332 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4333 fprintf (STREAM, "\t%s\t%sL%d\n", \
4334 Pmode == DImode ? ".dword" : ".word", \
4335 LOCAL_LABEL_PREFIX, \
4338 /* This is how to output an element of a case-vector that is relative.
4339 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4340 TARGET_EMBEDDED_PIC). */
4342 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4344 if (TARGET_MIPS16) \
4345 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4346 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4347 else if (TARGET_EMBEDDED_PIC) \
4348 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4349 Pmode == DImode ? ".dword" : ".word", \
4350 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4351 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4352 fprintf (STREAM, "\t%s\t%sL%d\n", \
4353 Pmode == DImode ? ".gpdword" : ".gpword", \
4354 LOCAL_LABEL_PREFIX, VALUE); \
4356 fprintf (STREAM, "\t%s\t%sL%d\n", \
4357 Pmode == DImode ? ".dword" : ".word", \
4358 LOCAL_LABEL_PREFIX, VALUE); \
4361 /* When generating embedded PIC or mips16 code we want to put the jump
4362 table in the .text section. In all other cases, we want to put the
4363 jump table in the .rdata section. Unfortunately, we can't use
4364 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4365 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4366 section if appropriate. */
4367 #undef ASM_OUTPUT_CASE_LABEL
4368 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4370 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4371 function_section (current_function_decl); \
4372 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4375 /* This is how to output an assembler line
4376 that says to advance the location counter
4377 to a multiple of 2**LOG bytes. */
4379 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4380 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4382 /* This is how to output an assembler line to advance the location
4383 counter by SIZE bytes. */
4385 #undef ASM_OUTPUT_SKIP
4386 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4387 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4389 /* This is how to output a string. */
4390 #undef ASM_OUTPUT_ASCII
4391 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4392 mips_output_ascii (STREAM, STRING, LEN)
4394 /* Handle certain cpp directives used in header files on sysV. */
4395 #define SCCS_DIRECTIVE
4397 #ifndef ASM_OUTPUT_IDENT
4398 /* Output #ident as a in the read-only data section. */
4399 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4401 const char *p = STRING; \
4402 int size = strlen (p) + 1; \
4404 assemble_string (p, size); \
4408 /* Default to -G 8 */
4409 #ifndef MIPS_DEFAULT_GVALUE
4410 #define MIPS_DEFAULT_GVALUE 8
4413 /* Define the strings to put out for each section in the object file. */
4414 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4415 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4416 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4417 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4418 #undef READONLY_DATA_SECTION
4419 #define READONLY_DATA_SECTION rdata_section
4420 #define SMALL_DATA_SECTION sdata_section
4422 /* What other sections we support other than the normal .data/.text. */
4424 #undef EXTRA_SECTIONS
4425 #define EXTRA_SECTIONS in_sdata, in_rdata
4427 /* Define the additional functions to select our additional sections. */
4429 /* on the MIPS it is not a good idea to put constants in the text
4430 section, since this defeats the sdata/data mechanism. This is
4431 especially true when -O is used. In this case an effort is made to
4432 address with faster (gp) register relative addressing, which can
4433 only get at sdata and sbss items (there is no stext !!) However,
4434 if the constant is too large for sdata, and it's readonly, it
4435 will go into the .rdata section. */
4437 #undef EXTRA_SECTION_FUNCTIONS
4438 #define EXTRA_SECTION_FUNCTIONS \
4442 if (in_section != in_sdata) \
4444 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4445 in_section = in_sdata; \
4452 if (in_section != in_rdata) \
4454 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4455 in_section = in_rdata; \
4459 /* Given a decl node or constant node, choose the section to output it in
4460 and select that section. */
4462 #undef SELECT_RTX_SECTION
4463 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4465 #undef SELECT_SECTION
4466 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4469 /* Store in OUTPUT a string (made with alloca) containing
4470 an assembler-name for a local static variable named NAME.
4471 LABELNO is an integer which is different for each call. */
4473 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4474 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4475 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4477 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4480 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4481 TARGET_64BIT ? "dsubu" : "subu", \
4482 reg_names[STACK_POINTER_REGNUM], \
4483 reg_names[STACK_POINTER_REGNUM], \
4484 TARGET_64BIT ? "sd" : "sw", \
4486 reg_names[STACK_POINTER_REGNUM]); \
4490 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4493 if (! set_noreorder) \
4494 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4496 dslots_load_total++; \
4497 dslots_load_filled++; \
4498 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4499 TARGET_64BIT ? "ld" : "lw", \
4501 reg_names[STACK_POINTER_REGNUM], \
4502 TARGET_64BIT ? "daddu" : "addu", \
4503 reg_names[STACK_POINTER_REGNUM], \
4504 reg_names[STACK_POINTER_REGNUM]); \
4506 if (! set_noreorder) \
4507 fprintf (STREAM, "\t.set\treorder\n"); \
4511 /* How to start an assembler comment.
4512 The leading space is important (the mips native assembler requires it). */
4513 #ifndef ASM_COMMENT_START
4514 #define ASM_COMMENT_START " #"
4518 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4519 and mips-tdump.c to print them out.
4521 These must match the corresponding definitions in gdb/mipsread.c.
4522 Unfortunately, gcc and gdb do not currently share any directories. */
4524 #define CODE_MASK 0x8F300
4525 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4526 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4527 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4530 /* Default definitions for size_t and ptrdiff_t. */
4533 #define NO_BUILTIN_SIZE_TYPE
4534 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4537 #ifndef PTRDIFF_TYPE
4538 #define NO_BUILTIN_PTRDIFF_TYPE
4539 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4542 /* See mips_expand_prologue's use of loadgp for when this should be
4545 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4546 && mips_abi != ABI_32 \
4547 && mips_abi != ABI_O64)
4549 /* In mips16 mode, we need to look through the function to check for
4550 PC relative loads that are out of range. */
4551 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4553 /* We need to use a special set of functions to handle hard floating
4554 point code in mips16 mode. */
4556 #ifndef INIT_SUBTARGET_OPTABS
4557 #define INIT_SUBTARGET_OPTABS
4560 #define INIT_TARGET_OPTABS \
4563 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4564 INIT_SUBTARGET_OPTABS; \
4567 add_optab->handlers[(int) SFmode].libfunc = \
4568 init_one_libfunc ("__mips16_addsf3"); \
4569 sub_optab->handlers[(int) SFmode].libfunc = \
4570 init_one_libfunc ("__mips16_subsf3"); \
4571 smul_optab->handlers[(int) SFmode].libfunc = \
4572 init_one_libfunc ("__mips16_mulsf3"); \
4573 sdiv_optab->handlers[(int) SFmode].libfunc = \
4574 init_one_libfunc ("__mips16_divsf3"); \
4576 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4577 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4578 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4579 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4580 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4581 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4583 floatsisf_libfunc = \
4584 init_one_libfunc ("__mips16_floatsisf"); \
4586 init_one_libfunc ("__mips16_fixsfsi"); \
4588 if (TARGET_DOUBLE_FLOAT) \
4590 add_optab->handlers[(int) DFmode].libfunc = \
4591 init_one_libfunc ("__mips16_adddf3"); \
4592 sub_optab->handlers[(int) DFmode].libfunc = \
4593 init_one_libfunc ("__mips16_subdf3"); \
4594 smul_optab->handlers[(int) DFmode].libfunc = \
4595 init_one_libfunc ("__mips16_muldf3"); \
4596 sdiv_optab->handlers[(int) DFmode].libfunc = \
4597 init_one_libfunc ("__mips16_divdf3"); \
4599 extendsfdf2_libfunc = \
4600 init_one_libfunc ("__mips16_extendsfdf2"); \
4601 truncdfsf2_libfunc = \
4602 init_one_libfunc ("__mips16_truncdfsf2"); \
4605 init_one_libfunc ("__mips16_eqdf2"); \
4607 init_one_libfunc ("__mips16_nedf2"); \
4609 init_one_libfunc ("__mips16_gtdf2"); \
4611 init_one_libfunc ("__mips16_gedf2"); \
4613 init_one_libfunc ("__mips16_ltdf2"); \
4615 init_one_libfunc ("__mips16_ledf2"); \
4617 floatsidf_libfunc = \
4618 init_one_libfunc ("__mips16_floatsidf"); \
4620 init_one_libfunc ("__mips16_fixdfsi"); \
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