1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* Which processor to schedule for. Since there is no difference between
47 a R2000 and R3000 in terms of the scheduler, we collapse them into
48 just an R3000. The elements of the enumeration must match exactly
49 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
78 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
79 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
80 to work on a 64 bit machine. */
88 /* Whether to emit abicalls code sequences or not. */
90 enum mips_abicalls_type {
95 /* Recast the abicalls class to be the abicalls attribute. */
96 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
98 /* Which type of block move to do (whether or not the last store is
99 split out so it can fill a branch delay slot). */
101 enum block_move_type {
102 BLOCK_MOVE_NORMAL, /* generate complete block move */
103 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
104 BLOCK_MOVE_LAST /* generate just the last store */
107 /* Information about one recognized processor. Defined here for the
108 benefit of TARGET_CPU_CPP_BUILTINS. */
109 struct mips_cpu_info {
110 /* The 'canonical' name of the processor as far as GCC is concerned.
111 It's typically a manufacturer's prefix followed by a numerical
112 designation. It should be lower case. */
115 /* The internal processor number that most closely matches this
116 entry. Several processors can have the same value, if there's no
117 difference between them from GCC's point of view. */
118 enum processor_type cpu;
120 /* The ISA level that the processor implements. */
124 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
125 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
126 extern const char *current_function_file; /* filename current function is in */
127 extern int num_source_filenames; /* current .file # */
128 extern int inside_function; /* != 0 if inside of a function */
129 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
130 extern int file_in_function_warning; /* warning given about .file in func */
131 extern int sdb_label_count; /* block start/end next label # */
132 extern int sdb_begin_function_line; /* Starting Line of current function */
133 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
134 /* extern unsigned HOST_WIDE_INT g_switch_value; */ /* value of the -G xx switch */
135 extern int g_switch_set; /* whether -G xx was passed. */
136 extern int sym_lineno; /* sgi next label # for each stmt */
137 extern int set_noreorder; /* # of nested .set noreorder's */
138 extern int set_nomacro; /* # of nested .set nomacro's */
139 extern int set_noat; /* # of nested .set noat's */
140 extern int set_volatile; /* # of nested .set volatile's */
141 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
142 extern int mips_dbx_regno[]; /* Map register # to debug register # */
143 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
144 extern enum cmp_type branch_type; /* what type of branch to use */
145 extern enum processor_type mips_arch; /* which cpu to codegen for */
146 extern enum processor_type mips_tune; /* which cpu to schedule for */
147 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
148 extern int mips_isa; /* architectural level */
149 extern int mips16; /* whether generating mips16 code */
150 extern int mips16_hard_float; /* mips16 without -msoft-float */
151 extern int mips_entry; /* generate entry/exit for mips16 */
152 extern const char *mips_arch_string; /* for -march=<xxx> */
153 extern const char *mips_tune_string; /* for -mtune=<xxx> */
154 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
155 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
156 extern const char *mips_entry_string; /* for -mentry */
157 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
158 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
159 extern int mips_string_length; /* length of strings for mips16 */
160 extern const struct mips_cpu_info mips_cpu_info_table[];
161 extern const struct mips_cpu_info *mips_arch_info;
162 extern const struct mips_cpu_info *mips_tune_info;
164 /* Functions to change what output section we are using. */
165 extern void sdata_section PARAMS ((void));
166 extern void sbss_section PARAMS ((void));
168 /* Macros to silence warnings about numbers being signed in traditional
169 C and unsigned in ISO C when compiled on 32-bit hosts. */
171 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
172 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
173 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
176 /* Run-time compilation parameters selecting different hardware subsets. */
178 /* Macros used in the machine description to test the flags. */
180 /* Bits for real switches */
181 #define MASK_INT64 0x00000001 /* ints are 64 bits */
182 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
183 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
184 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
185 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
186 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
187 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
188 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
189 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
190 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
191 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
192 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
193 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
194 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
195 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
196 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
197 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
198 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
199 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
200 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
201 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
202 #define MASK_NO_CHECK_ZERO_DIV \
203 0x00200000 /* divide by zero checking */
204 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
206 #define MASK_UNINIT_CONST_IN_RODATA \
207 0x00800000 /* Store uninitialized
209 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
210 multiply-add operations. */
212 /* Debug switches, not documented */
213 #define MASK_DEBUG 0 /* unused */
214 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
215 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
216 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
217 #define MASK_DEBUG_D 0 /* don't do define_split's */
218 #define MASK_DEBUG_E 0 /* function_arg debug */
219 #define MASK_DEBUG_F 0 /* ??? */
220 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
221 #define MASK_DEBUG_I 0 /* unused */
223 /* Dummy switches used only in specs */
224 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
226 /* r4000 64 bit sizes */
227 #define TARGET_INT64 (target_flags & MASK_INT64)
228 #define TARGET_LONG64 (target_flags & MASK_LONG64)
229 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
230 #define TARGET_64BIT (target_flags & MASK_64BIT)
232 /* Mips vs. GNU linker */
233 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
235 /* Mips vs. GNU assembler */
236 #define TARGET_GAS (target_flags & MASK_GAS)
237 #define TARGET_MIPS_AS (!TARGET_GAS)
240 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
241 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
242 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
243 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
244 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
245 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
246 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
247 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
248 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
250 /* Reg. Naming in .s ($21 vs. $a0) */
251 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
253 /* Optimize for Sdata/Sbss */
254 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
256 /* call memcpy instead of inline code */
257 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
259 /* .abicalls, etc from Pyramid V.4 */
260 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
262 /* software floating point */
263 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
264 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
266 /* always call through a register */
267 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
269 /* generate embedded PIC code;
271 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
273 /* for embedded systems, optimize for
274 reduced RAM space instead of for
276 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
278 /* always store uninitialized const
279 variables in rodata, requires
280 TARGET_EMBEDDED_DATA. */
281 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
283 /* generate big endian code. */
284 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
286 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
287 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
289 #define TARGET_MAD (target_flags & MASK_MAD)
291 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
293 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
295 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
297 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
300 /* True if we should use NewABI-style relocation operators for
301 symbolic addresses. This is never true for mips16 code,
302 which has its own conventions. */
304 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
307 /* True if the call patterns should be split into a jalr followed by
308 an instruction to restore $gp. This is only ever true for SVR4 PIC,
309 in which $gp is call-clobbered. It is only safe to split the load
310 from the call when every use of $gp is explicit. */
312 #define TARGET_SPLIT_CALLS \
313 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
315 /* True if we can optimize sibling calls. For simplicity, we only
316 handle cases in which call_insn_operand will reject invalid
317 sibcall addresses. There are two cases in which this isn't true:
319 - TARGET_MIPS16. call_insn_operand accepts constant addresses
320 but there is no direct jump instruction. It isn't worth
321 using sibling calls in this case anyway; they would usually
322 be longer than normal calls.
324 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
325 accepts global constants, but "jr $25" is the only allowed
328 #define TARGET_SIBCALLS \
329 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
331 /* True if .gpword or .gpdword should be used for switch tables.
332 Not all SGI assemblers support this. */
334 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
336 /* Generate mips16 code */
337 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
339 /* Generic ISA defines. */
340 #define ISA_MIPS1 (mips_isa == 1)
341 #define ISA_MIPS2 (mips_isa == 2)
342 #define ISA_MIPS3 (mips_isa == 3)
343 #define ISA_MIPS4 (mips_isa == 4)
344 #define ISA_MIPS32 (mips_isa == 32)
345 #define ISA_MIPS32R2 (mips_isa == 33)
346 #define ISA_MIPS64 (mips_isa == 64)
348 /* Architecture target defines. */
349 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
350 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
351 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
352 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
353 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
354 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
355 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
356 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
357 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
358 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
359 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
361 /* Scheduling target defines. */
362 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
363 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
364 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
365 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
366 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
367 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
368 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
369 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
370 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
372 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
374 /* Define preprocessor macros for the -march and -mtune options.
375 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
376 processor. If INFO's canonical name is "foo", define PREFIX to
377 be "foo", and define an additional macro PREFIX_FOO. */
378 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
383 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
384 for (p = macro; *p != 0; p++) \
387 builtin_define (macro); \
388 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
393 /* Target CPU builtins. */
394 #define TARGET_CPU_CPP_BUILTINS() \
397 builtin_assert ("cpu=mips"); \
398 builtin_define ("__mips__"); \
399 builtin_define ("_mips"); \
401 /* We do this here because __mips is defined below \
402 and so we can't use builtin_define_std. */ \
404 builtin_define ("mips"); \
406 /* Treat _R3000 and _R4000 like register-size defines, \
407 which is how they've historically been used. */ \
410 builtin_define ("__mips64"); \
411 builtin_define_std ("R4000"); \
412 builtin_define ("_R4000"); \
416 builtin_define_std ("R3000"); \
417 builtin_define ("_R3000"); \
419 if (TARGET_FLOAT64) \
420 builtin_define ("__mips_fpr=64"); \
422 builtin_define ("__mips_fpr=32"); \
425 builtin_define ("__mips16"); \
427 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
428 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
432 builtin_define ("__mips=1"); \
433 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
435 else if (ISA_MIPS2) \
437 builtin_define ("__mips=2"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
440 else if (ISA_MIPS3) \
442 builtin_define ("__mips=3"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
445 else if (ISA_MIPS4) \
447 builtin_define ("__mips=4"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
450 else if (ISA_MIPS32) \
452 builtin_define ("__mips=32"); \
453 builtin_define ("__mips_isa_rev=1"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
456 else if (ISA_MIPS32R2) \
458 builtin_define ("__mips=32"); \
459 builtin_define ("__mips_isa_rev=2"); \
460 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
462 else if (ISA_MIPS64) \
464 builtin_define ("__mips=64"); \
465 builtin_define ("__mips_isa_rev=1"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
469 if (TARGET_HARD_FLOAT) \
470 builtin_define ("__mips_hard_float"); \
471 else if (TARGET_SOFT_FLOAT) \
472 builtin_define ("__mips_soft_float"); \
474 if (TARGET_SINGLE_FLOAT) \
475 builtin_define ("__mips_single_float"); \
477 if (TARGET_BIG_ENDIAN) \
479 builtin_define_std ("MIPSEB"); \
480 builtin_define ("_MIPSEB"); \
484 builtin_define_std ("MIPSEL"); \
485 builtin_define ("_MIPSEL"); \
488 /* Macros dependent on the C dialect. */ \
489 if (preprocessing_asm_p ()) \
491 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
492 builtin_define ("_LANGUAGE_ASSEMBLY"); \
494 else if (c_language == clk_c) \
496 builtin_define_std ("LANGUAGE_C"); \
497 builtin_define ("_LANGUAGE_C"); \
499 else if (c_language == clk_cplusplus) \
501 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
502 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
503 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
507 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
508 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
509 /* Bizzare, but needed at least for Irix. */ \
510 builtin_define_std ("LANGUAGE_C"); \
511 builtin_define ("_LANGUAGE_C"); \
514 if (mips_abi == ABI_EABI) \
515 builtin_define ("__mips_eabi"); \
521 /* Macro to define tables used to set the flags.
522 This is a list in braces of pairs in braces,
523 each pair being { "NAME", VALUE }
524 where VALUE is the bits to set or minus the bits to clear.
525 An empty string NAME is used to identify the default VALUE. */
527 #define TARGET_SWITCHES \
529 SUBTARGET_TARGET_SWITCHES \
530 {"int64", MASK_INT64 | MASK_LONG64, \
531 N_("Use 64-bit int type")}, \
532 {"long64", MASK_LONG64, \
533 N_("Use 64-bit long type")}, \
534 {"long32", -(MASK_LONG64 | MASK_INT64), \
535 N_("Use 32-bit long type")}, \
536 {"split-addresses", MASK_SPLIT_ADDR, \
537 N_("Optimize lui/addiu address loads")}, \
538 {"no-split-addresses", -MASK_SPLIT_ADDR, \
539 N_("Don't optimize lui/addiu address loads")}, \
540 {"mips-as", -MASK_GAS, \
541 N_("Use MIPS as")}, \
544 {"rnames", MASK_NAME_REGS, \
545 N_("Use symbolic register names")}, \
546 {"no-rnames", -MASK_NAME_REGS, \
547 N_("Don't use symbolic register names")}, \
548 {"gpOPT", MASK_GPOPT, \
549 N_("Use GP relative sdata/sbss sections")}, \
550 {"gpopt", MASK_GPOPT, \
551 N_("Use GP relative sdata/sbss sections")}, \
552 {"no-gpOPT", -MASK_GPOPT, \
553 N_("Don't use GP relative sdata/sbss sections")}, \
554 {"no-gpopt", -MASK_GPOPT, \
555 N_("Don't use GP relative sdata/sbss sections")}, \
557 N_("Output compiler statistics (now ignored)")}, \
559 N_("Don't output compiler statistics")}, \
560 {"memcpy", MASK_MEMCPY, \
561 N_("Don't optimize block moves")}, \
562 {"no-memcpy", -MASK_MEMCPY, \
563 N_("Optimize block moves")}, \
564 {"mips-tfile", MASK_MIPS_TFILE, \
565 N_("Use mips-tfile asm postpass")}, \
566 {"no-mips-tfile", -MASK_MIPS_TFILE, \
567 N_("Don't use mips-tfile asm postpass")}, \
568 {"soft-float", MASK_SOFT_FLOAT, \
569 N_("Use software floating point")}, \
570 {"hard-float", -MASK_SOFT_FLOAT, \
571 N_("Use hardware floating point")}, \
572 {"fp64", MASK_FLOAT64, \
573 N_("Use 64-bit FP registers")}, \
574 {"fp32", -MASK_FLOAT64, \
575 N_("Use 32-bit FP registers")}, \
576 {"gp64", MASK_64BIT, \
577 N_("Use 64-bit general registers")}, \
578 {"gp32", -MASK_64BIT, \
579 N_("Use 32-bit general registers")}, \
580 {"abicalls", MASK_ABICALLS, \
581 N_("Use Irix PIC")}, \
582 {"no-abicalls", -MASK_ABICALLS, \
583 N_("Don't use Irix PIC")}, \
584 {"long-calls", MASK_LONG_CALLS, \
585 N_("Use indirect calls")}, \
586 {"no-long-calls", -MASK_LONG_CALLS, \
587 N_("Don't use indirect calls")}, \
588 {"embedded-pic", MASK_EMBEDDED_PIC, \
589 N_("Use embedded PIC")}, \
590 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
591 N_("Don't use embedded PIC")}, \
592 {"embedded-data", MASK_EMBEDDED_DATA, \
593 N_("Use ROM instead of RAM")}, \
594 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
595 N_("Don't use ROM instead of RAM")}, \
596 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
597 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
598 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
599 N_("Don't put uninitialized constants in ROM")}, \
600 {"eb", MASK_BIG_ENDIAN, \
601 N_("Use big-endian byte order")}, \
602 {"el", -MASK_BIG_ENDIAN, \
603 N_("Use little-endian byte order")}, \
604 {"single-float", MASK_SINGLE_FLOAT, \
605 N_("Use single (32-bit) FP only")}, \
606 {"double-float", -MASK_SINGLE_FLOAT, \
607 N_("Don't use single (32-bit) FP only")}, \
609 N_("Use multiply accumulate")}, \
610 {"no-mad", -MASK_MAD, \
611 N_("Don't use multiply accumulate")}, \
612 {"no-fused-madd", MASK_NO_FUSED_MADD, \
613 N_("Don't generate fused multiply/add instructions")}, \
614 {"fused-madd", -MASK_NO_FUSED_MADD, \
615 N_("Generate fused multiply/add instructions")}, \
616 {"fix4300", MASK_4300_MUL_FIX, \
617 N_("Work around early 4300 hardware bug")}, \
618 {"no-fix4300", -MASK_4300_MUL_FIX, \
619 N_("Don't work around early 4300 hardware bug")}, \
620 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
621 N_("Trap on integer divide by zero")}, \
622 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
623 N_("Don't trap on integer divide by zero")}, \
624 { "branch-likely", MASK_BRANCHLIKELY, \
625 N_("Use Branch Likely instructions, overriding default for arch")}, \
626 { "no-branch-likely", -MASK_BRANCHLIKELY, \
627 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
628 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
629 N_("Use NewABI-style %reloc() assembly operators")}, \
630 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
631 N_("Use assembler macros instead of relocation operators")}, \
632 {"debug", MASK_DEBUG, \
634 {"debuga", MASK_DEBUG_A, \
636 {"debugb", MASK_DEBUG_B, \
638 {"debugc", MASK_DEBUG_C, \
640 {"debugd", MASK_DEBUG_D, \
642 {"debuge", MASK_DEBUG_E, \
644 {"debugf", MASK_DEBUG_F, \
646 {"debugg", MASK_DEBUG_G, \
648 {"debugi", MASK_DEBUG_I, \
650 {"", (TARGET_DEFAULT \
651 | TARGET_CPU_DEFAULT \
652 | TARGET_ENDIAN_DEFAULT), \
656 /* Default target_flags if no switches are specified */
658 #ifndef TARGET_DEFAULT
659 #define TARGET_DEFAULT 0
662 #ifndef TARGET_CPU_DEFAULT
663 #define TARGET_CPU_DEFAULT 0
666 #ifndef TARGET_ENDIAN_DEFAULT
667 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
670 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
671 #ifndef MIPS_ISA_DEFAULT
672 #ifndef MIPS_CPU_STRING_DEFAULT
673 #define MIPS_CPU_STRING_DEFAULT "from-abi"
679 /* Make this compile time constant for libgcc2 */
681 #define TARGET_64BIT 1
683 #define TARGET_64BIT 0
685 #endif /* IN_LIBGCC2 */
687 #ifndef MULTILIB_ENDIAN_DEFAULT
688 #if TARGET_ENDIAN_DEFAULT == 0
689 #define MULTILIB_ENDIAN_DEFAULT "EL"
691 #define MULTILIB_ENDIAN_DEFAULT "EB"
695 #ifndef MULTILIB_ISA_DEFAULT
696 # if MIPS_ISA_DEFAULT == 1
697 # define MULTILIB_ISA_DEFAULT "mips1"
699 # if MIPS_ISA_DEFAULT == 2
700 # define MULTILIB_ISA_DEFAULT "mips2"
702 # if MIPS_ISA_DEFAULT == 3
703 # define MULTILIB_ISA_DEFAULT "mips3"
705 # if MIPS_ISA_DEFAULT == 4
706 # define MULTILIB_ISA_DEFAULT "mips4"
708 # if MIPS_ISA_DEFAULT == 32
709 # define MULTILIB_ISA_DEFAULT "mips32"
711 # if MIPS_ISA_DEFAULT == 33
712 # define MULTILIB_ISA_DEFAULT "mips32r2"
714 # if MIPS_ISA_DEFAULT == 64
715 # define MULTILIB_ISA_DEFAULT "mips64"
717 # define MULTILIB_ISA_DEFAULT "mips1"
727 #ifndef MULTILIB_DEFAULTS
728 #define MULTILIB_DEFAULTS \
729 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
732 /* We must pass -EL to the linker by default for little endian embedded
733 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
734 linker will default to using big-endian output files. The OUTPUT_FORMAT
735 line must be in the linker script, otherwise -EB/-EL will not work. */
738 #if TARGET_ENDIAN_DEFAULT == 0
739 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
741 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
745 #define TARGET_OPTIONS \
747 SUBTARGET_TARGET_OPTIONS \
748 { "tune=", &mips_tune_string, \
749 N_("Specify CPU for scheduling purposes"), 0}, \
750 { "arch=", &mips_arch_string, \
751 N_("Specify CPU for code generation purposes"), 0}, \
752 { "abi=", &mips_abi_string, \
753 N_("Specify an ABI"), 0}, \
754 { "ips", &mips_isa_string, \
755 N_("Specify a Standard MIPS ISA"), 0}, \
756 { "entry", &mips_entry_string, \
757 N_("Use mips16 entry/exit psuedo ops"), 0}, \
758 { "no-mips16", &mips_no_mips16_string, \
759 N_("Don't use MIPS16 instructions"), 0}, \
760 { "no-flush-func", &mips_cache_flush_func, \
761 N_("Don't call any cache flush functions"), 0}, \
762 { "flush-func=", &mips_cache_flush_func, \
763 N_("Specify cache flush function"), 0}, \
766 /* This is meant to be redefined in the host dependent files. */
767 #define SUBTARGET_TARGET_OPTIONS
769 /* Support for a compile-time default CPU, et cetera. The rules are:
770 --with-arch is ignored if -march is specified or a -mips is specified
771 (other than -mips16).
772 --with-tune is ignored if -mtune is specified.
773 --with-abi is ignored if -mabi is specified.
774 --with-float is ignored if -mhard-float or -msoft-float are
776 #define OPTION_DEFAULT_SPECS \
777 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
778 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
779 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
780 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
783 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
787 /* Generate three-operand multiply instructions for SImode. */
788 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
796 /* Generate three-operand multiply instructions for DImode. */
797 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
800 /* Macros to decide whether certain features are available or not,
801 depending on the instruction set architecture level. */
803 #define HAVE_SQRT_P() (!ISA_MIPS1)
805 /* True if the ABI can only work with 64-bit integer registers. We
806 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
807 otherwise floating-point registers must also be 64-bit. */
808 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
809 || mips_abi == ABI_O64 \
810 || mips_abi == ABI_N32)
812 /* Likewise for 32-bit regs. */
813 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
815 /* True if symbols are 64 bits wide. At present, n64 is the only
816 ABI for which this is true. */
817 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
819 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
820 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
824 /* ISA has branch likely instructions (eg. mips2). */
825 /* Disable branchlikely for tx39 until compare rewrite. They haven't
826 been generated up to this point. */
827 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
830 /* ISA has the conditional move instructions introduced in mips4. */
831 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
835 && !TARGET_MIPS5500 \
838 /* ISA has just the integer condition move instructions (movn,movz) */
839 #define ISA_HAS_INT_CONDMOVE 0
841 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
842 branch on CC, and move (both FP and non-FP) on CC. */
843 #define ISA_HAS_8CC (ISA_MIPS4 \
848 /* This is a catch all for the other new mips4 instructions: indexed load and
849 indexed prefetch instructions, the FP madd and msub instructions,
850 and the FP recip and recip sqrt instructions */
851 #define ISA_HAS_FP4 ((ISA_MIPS4 \
855 /* ISA has conditional trap instructions. */
856 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
859 /* ISA has integer multiply-accumulate instructions, madd and msub. */
860 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
865 /* ISA has floating-point nmadd and nmsub instructions. */
866 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
868 && (!TARGET_MIPS5400 || TARGET_MAD) \
871 /* ISA has count leading zeroes/ones instruction (not implemented). */
872 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
877 /* ISA has double-word count leading zeroes/ones instruction (not
879 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
882 /* ISA has three operand multiply instructions that put
883 the high part in an accumulator: mulhi or mulhiu. */
884 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
889 /* ISA has three operand multiply instructions that
890 negates the result and puts the result in an accumulator. */
891 #define ISA_HAS_MULS (TARGET_MIPS5400 \
896 /* ISA has three operand multiply instructions that subtracts the
897 result from a 4th operand and puts the result in an accumulator. */
898 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
902 /* ISA has three operand multiply instructions that the result
903 from a 4th operand and puts the result in an accumulator. */
904 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
910 /* ISA has 32-bit rotate right instruction. */
911 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
918 /* ISA has 64-bit rotate right instruction. */
919 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
921 && (TARGET_MIPS5400 \
926 /* ISA has data prefetch instruction. */
927 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
933 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
934 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
935 also requires TARGET_DOUBLE_FLOAT. */
936 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
938 /* ISA includes the MIPS32r2 seb and seh instructions. */
939 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
943 /* True if the result of a load is not available to the next instruction.
944 A nop will then be needed between instructions like "lw $4,..."
945 and "addiu $4,$4,1". */
946 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
947 && !TARGET_MIPS3900 \
950 /* Likewise mtc1 and mfc1. */
951 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
953 /* Likewise floating-point comparisons. */
954 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
956 /* True if mflo and mfhi can be immediately followed by instructions
957 which write to the HI and LO registers. Most targets require a
958 two-instruction gap. */
959 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
961 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
962 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
963 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
964 target_flags, and -mgp64 sets MASK_64BIT.
966 Setting MASK_64BIT in target_flags will cause gcc to assume that
967 registers are 64 bits wide. int, long and void * will be 32 bit;
968 this may be changed with -mint64 or -mlong64.
970 The gen* programs link code that refers to MASK_64BIT. They don't
971 actually use the information in target_flags; they just refer to
974 /* Switch Recognition by gcc.c. Add -G xx support */
976 #undef SWITCH_TAKES_ARG
977 #define SWITCH_TAKES_ARG(CHAR) \
978 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
980 /* Sometimes certain combinations of command options do not make sense
981 on a particular target machine. You can define a macro
982 `OVERRIDE_OPTIONS' to take account of this. This macro, if
983 defined, is executed once just after all the command options have
986 On the MIPS, it is used to handle -G. We also use it to set up all
987 of the tables referenced in the other macros. */
989 #define OVERRIDE_OPTIONS override_options ()
991 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
993 /* Show we can debug even without a frame pointer. */
994 #define CAN_DEBUG_WITHOUT_FP
996 /* Tell collect what flags to pass to nm. */
998 #define NM_FLAGS "-Bn"
1002 /* Assembler specs. */
1004 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1007 #define MIPS_AS_ASM_SPEC "\
1008 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1009 %{pipe: %e-pipe is not supported} \
1010 %{K} %(subtarget_mips_as_asm_spec)"
1012 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1013 rather than gas. It may be overridden by subtargets. */
1015 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1016 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1019 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1022 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1024 #define SUBTARGET_TARGET_SWITCHES
1026 extern int mips_abi;
1028 #ifndef MIPS_ABI_DEFAULT
1029 #define MIPS_ABI_DEFAULT ABI_32
1032 /* Use the most portable ABI flag for the ASM specs. */
1034 #if MIPS_ABI_DEFAULT == ABI_32
1035 #define MULTILIB_ABI_DEFAULT "mabi=32"
1036 #define ASM_ABI_DEFAULT_SPEC "-32"
1039 #if MIPS_ABI_DEFAULT == ABI_O64
1040 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1041 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1044 #if MIPS_ABI_DEFAULT == ABI_N32
1045 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1046 #define ASM_ABI_DEFAULT_SPEC "-n32"
1049 #if MIPS_ABI_DEFAULT == ABI_64
1050 #define MULTILIB_ABI_DEFAULT "mabi=64"
1051 #define ASM_ABI_DEFAULT_SPEC "-64"
1054 #if MIPS_ABI_DEFAULT == ABI_EABI
1055 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1056 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1059 /* Only ELF targets can switch the ABI. */
1060 #ifndef OBJECT_FORMAT_ELF
1061 #undef ASM_ABI_DEFAULT_SPEC
1062 #define ASM_ABI_DEFAULT_SPEC ""
1065 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1066 GAS_ASM_SPEC as the default, depending upon the value of
1069 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1072 #define TARGET_ASM_SPEC "\
1073 %{mmips-as: %(mips_as_asm_spec)} \
1074 %{!mmips-as: %(gas_asm_spec)}"
1078 #define TARGET_ASM_SPEC "\
1079 %{!mgas: %(mips_as_asm_spec)} \
1080 %{mgas: %(gas_asm_spec)}"
1082 #endif /* not GAS */
1084 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1085 to the assembler. It may be overridden by subtargets. */
1086 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1087 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1089 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1092 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1093 the assembler. It may be overridden by subtargets. */
1094 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1095 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1096 %{g} %{g0} %{g1} %{g2} %{g3} \
1097 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1098 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1099 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1100 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1104 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1105 and stabs debugging info. */
1106 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1108 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1110 #define MDEBUG_ASM_SPEC ""
1111 #endif /* not GAS */
1113 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1114 overridden by subtargets. */
1116 #ifndef SUBTARGET_ASM_SPEC
1117 #define SUBTARGET_ASM_SPEC ""
1120 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1121 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1122 whether we're using GAS. These options can only be used properly
1123 with GAS, and it is better to get an error from a non-GAS assembler
1124 than to silently generate bad code. */
1128 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1129 %{mips32} %{mips32r2} %{mips64} \
1130 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1131 %(subtarget_asm_optimizing_spec) \
1132 %(subtarget_asm_debugging_spec) \
1134 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1135 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1136 %{mgp32} %{mgp64} %{march=*} \
1137 %(target_asm_spec) \
1138 %(subtarget_asm_spec)"
1140 /* Specify to run a post-processor, mips-tfile after the assembler
1141 has run to stuff the mips debug information into the object file.
1142 This is needed because the $#!%^ MIPS assembler provides no way
1143 of specifying such information in the assembly file. If we are
1144 cross compiling, disable mips-tfile unless the user specifies
1147 #ifndef ASM_FINAL_SPEC
1148 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1150 #define ASM_FINAL_SPEC "\
1151 %{mmips-as: %{!mno-mips-tfile: \
1152 \n mips-tfile %{v*: -v} \
1154 %{!K: %{save-temps: -I %b.o~}} \
1155 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1156 %{.s:%i} %{!.s:%g.s}}}"
1160 #define ASM_FINAL_SPEC "\
1161 %{!mgas: %{!mno-mips-tfile: \
1162 \n mips-tfile %{v*: -v} \
1164 %{!K: %{save-temps: -I %b.o~}} \
1165 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1166 %{.s:%i} %{!.s:%g.s}}}"
1169 #endif /* ASM_FINAL_SPEC */
1171 /* Redefinition of libraries used. Mips doesn't support normal
1172 UNIX style profiling via calling _mcount. It does offer
1173 profiling that samples the PC, so do what we can... */
1176 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1179 /* Extra switches sometimes passed to the linker. */
1180 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1181 will interpret it as a -b option. */
1184 #define LINK_SPEC "\
1186 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1187 %{bestGnum} %{shared} %{non_shared}"
1188 #endif /* LINK_SPEC defined */
1191 /* Specs for the compiler proper */
1193 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1194 overridden by subtargets. */
1195 #ifndef SUBTARGET_CC1_SPEC
1196 #define SUBTARGET_CC1_SPEC ""
1199 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1200 /* Note, we will need to adjust the following if we ever find a MIPS variant
1201 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1202 that show up in this case. */
1206 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1207 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1209 %(subtarget_cc1_spec)"
1212 /* Preprocessor specs. */
1214 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1215 overridden by subtargets. */
1216 #ifndef SUBTARGET_CPP_SPEC
1217 #define SUBTARGET_CPP_SPEC ""
1220 #define CPP_SPEC "%(subtarget_cpp_spec)"
1222 /* This macro defines names of additional specifications to put in the specs
1223 that can be used in various specifications like CC1_SPEC. Its definition
1224 is an initializer with a subgrouping for each command option.
1226 Each subgrouping contains a string constant, that defines the
1227 specification name, and a string constant that used by the GNU CC driver
1230 Do not define this macro if it does not need to do anything. */
1232 #define EXTRA_SPECS \
1233 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1234 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1235 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1236 { "gas_asm_spec", GAS_ASM_SPEC }, \
1237 { "target_asm_spec", TARGET_ASM_SPEC }, \
1238 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1239 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1240 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1241 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1242 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1243 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1244 { "endian_spec", ENDIAN_SPEC }, \
1245 SUBTARGET_EXTRA_SPECS
1247 #ifndef SUBTARGET_EXTRA_SPECS
1248 #define SUBTARGET_EXTRA_SPECS
1251 /* If defined, this macro is an additional prefix to try after
1252 `STANDARD_EXEC_PREFIX'. */
1254 #ifndef MD_EXEC_PREFIX
1255 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1258 #ifndef MD_STARTFILE_PREFIX
1259 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1263 /* Print subsidiary information on the compiler version in use. */
1265 #define MIPS_VERSION "[AL 1.1, MM 40]"
1267 #ifndef MACHINE_TYPE
1268 #define MACHINE_TYPE "BSD Mips"
1271 #ifndef TARGET_VERSION_INTERNAL
1272 #define TARGET_VERSION_INTERNAL(STREAM) \
1273 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1276 #ifndef TARGET_VERSION
1277 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1281 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1282 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1283 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1285 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1286 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1289 /* By default, turn on GDB extensions. */
1290 #define DEFAULT_GDB_EXTENSIONS 1
1292 /* If we are passing smuggling stabs through the MIPS ECOFF object
1293 format, put a comment in front of the .stab<x> operation so
1294 that the MIPS assembler does not choke. The mips-tfile program
1295 will correctly put the stab into the object file. */
1297 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1298 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1299 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1301 /* Local compiler-generated symbols must have a prefix that the assembler
1302 understands. By default, this is $, although some targets (e.g.,
1303 NetBSD-ELF) need to override this. */
1305 #ifndef LOCAL_LABEL_PREFIX
1306 #define LOCAL_LABEL_PREFIX "$"
1309 /* By default on the mips, external symbols do not have an underscore
1310 prepended, but some targets (e.g., NetBSD) require this. */
1312 #ifndef USER_LABEL_PREFIX
1313 #define USER_LABEL_PREFIX ""
1316 /* Forward references to tags are allowed. */
1317 #define SDB_ALLOW_FORWARD_REFERENCES
1319 /* Unknown tags are also allowed. */
1320 #define SDB_ALLOW_UNKNOWN_REFERENCES
1322 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1323 since the length can run past this up to a continuation point. */
1324 #undef DBX_CONTIN_LENGTH
1325 #define DBX_CONTIN_LENGTH 1500
1327 /* How to renumber registers for dbx and gdb. */
1328 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1330 /* The mapping from gcc register number to DWARF 2 CFA column number.
1331 This mapping does not allow for tracking register 0, since SGI's broken
1332 dwarf reader thinks column 0 is used for the frame address, but since
1333 register 0 is fixed this is not a problem. */
1334 #define DWARF_FRAME_REGNUM(REG) \
1335 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1337 /* The DWARF 2 CFA column which tracks the return address. */
1338 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1340 /* Before the prologue, RA lives in r31. */
1341 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1343 /* Describe how we implement __builtin_eh_return. */
1344 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1345 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1347 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1348 The default for this in 64-bit mode is 8, which causes problems with
1349 SFmode register saves. */
1350 #define DWARF_CIE_DATA_ALIGNMENT 4
1352 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1354 #define PUT_SDB_DEF(a) \
1356 fprintf (asm_out_file, "\t%s.def\t", \
1357 (TARGET_GAS) ? "" : "#"); \
1358 ASM_OUTPUT_LABELREF (asm_out_file, a); \
1359 fputc (';', asm_out_file); \
1362 #define PUT_SDB_PLAIN_DEF(a) \
1364 fprintf (asm_out_file, "\t%s.def\t.%s;", \
1365 (TARGET_GAS) ? "" : "#", (a)); \
1368 /* For block start and end, we create labels, so that
1369 later we can figure out where the correct offset is.
1370 The normal .ent/.end serve well enough for functions,
1371 so those are just commented out. */
1373 #define PUT_SDB_BLOCK_START(LINE) \
1375 fprintf (asm_out_file, \
1376 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1377 LOCAL_LABEL_PREFIX, \
1379 (TARGET_GAS) ? "" : "#", \
1380 LOCAL_LABEL_PREFIX, \
1383 sdb_label_count++; \
1386 #define PUT_SDB_BLOCK_END(LINE) \
1388 fprintf (asm_out_file, \
1389 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1390 LOCAL_LABEL_PREFIX, \
1392 (TARGET_GAS) ? "" : "#", \
1393 LOCAL_LABEL_PREFIX, \
1396 sdb_label_count++; \
1399 #define PUT_SDB_FUNCTION_START(LINE)
1401 #define PUT_SDB_FUNCTION_END(LINE) \
1403 ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line); \
1406 #define PUT_SDB_EPILOGUE_END(NAME)
1408 /* Correct the offset of automatic variables and arguments. Note that
1409 the MIPS debug format wants all automatic variables and arguments
1410 to be in terms of the virtual frame pointer (stack pointer before
1411 any adjustment in the function), while the MIPS 3.0 linker wants
1412 the frame pointer to be the stack pointer after the initial
1415 #define DEBUGGER_AUTO_OFFSET(X) \
1416 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1417 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1418 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1420 /* Tell collect that the object format is ECOFF */
1421 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1422 #define EXTENDED_COFF /* ECOFF, not normal coff */
1424 /* Target machine storage layout */
1426 /* Define this if most significant bit is lowest numbered
1427 in instructions that operate on numbered bit-fields.
1429 #define BITS_BIG_ENDIAN 0
1431 /* Define this if most significant byte of a word is the lowest numbered. */
1432 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1434 /* Define this if most significant word of a multiword number is the lowest. */
1435 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1437 /* Define this to set the endianness to use in libgcc2.c, which can
1438 not depend on target_flags. */
1439 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1440 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1442 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1445 #define MAX_BITS_PER_WORD 64
1447 /* Width of a word, in units (bytes). */
1448 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1449 #define MIN_UNITS_PER_WORD 4
1451 /* For MIPS, width of a floating point register. */
1452 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1454 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1455 the next available register. */
1456 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1458 /* The largest size of value that can be held in floating-point
1459 registers and moved with a single instruction. */
1460 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1462 /* The largest size of value that can be held in floating-point
1464 #define UNITS_PER_FPVALUE \
1465 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1467 /* The number of bytes in a double. */
1468 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1470 /* A C expression for the size in bits of the type `int' on the
1471 target machine. If you don't define this, the default is one
1473 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1475 /* Tell the preprocessor the maximum size of wchar_t. */
1476 #ifndef MAX_WCHAR_TYPE_SIZE
1477 #ifndef WCHAR_TYPE_SIZE
1478 #define MAX_WCHAR_TYPE_SIZE 64
1482 /* A C expression for the size in bits of the type `short' on the
1483 target machine. If you don't define this, the default is half a
1484 word. (If this would be less than one storage unit, it is
1485 rounded up to one unit.) */
1486 #define SHORT_TYPE_SIZE 16
1488 /* A C expression for the size in bits of the type `long' on the
1489 target machine. If you don't define this, the default is one
1491 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1492 #define MAX_LONG_TYPE_SIZE 64
1494 /* A C expression for the size in bits of the type `long long' on the
1495 target machine. If you don't define this, the default is two
1497 #define LONG_LONG_TYPE_SIZE 64
1499 /* A C expression for the size in bits of the type `float' on the
1500 target machine. If you don't define this, the default is one
1502 #define FLOAT_TYPE_SIZE 32
1504 /* A C expression for the size in bits of the type `double' on the
1505 target machine. If you don't define this, the default is two
1507 #define DOUBLE_TYPE_SIZE 64
1509 /* A C expression for the size in bits of the type `long double' on
1510 the target machine. If you don't define this, the default is two
1512 #define LONG_DOUBLE_TYPE_SIZE \
1513 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1515 /* long double is not a fixed mode, but the idea is that, if we
1516 support long double, we also want a 128-bit integer type. */
1517 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1520 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1521 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1522 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1524 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1528 /* Width in bits of a pointer. */
1529 #ifndef POINTER_SIZE
1530 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1533 #define POINTERS_EXTEND_UNSIGNED 0
1535 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1536 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1537 || mips_abi == ABI_64 \
1538 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1541 /* Allocation boundary (in *bits*) for the code of a function. */
1542 #define FUNCTION_BOUNDARY 32
1544 /* Alignment of field after `int : 0' in a structure. */
1545 #define EMPTY_FIELD_BOUNDARY 32
1547 /* Every structure's size must be a multiple of this. */
1548 /* 8 is observed right on a DECstation and on riscos 4.02. */
1549 #define STRUCTURE_SIZE_BOUNDARY 8
1551 /* There is no point aligning anything to a rounder boundary than this. */
1552 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1554 /* Set this nonzero if move instructions will actually fail to work
1555 when given unaligned data. */
1556 #define STRICT_ALIGNMENT 1
1558 /* Define this if you wish to imitate the way many other C compilers
1559 handle alignment of bitfields and the structures that contain
1562 The behavior is that the type written for a bit-field (`int',
1563 `short', or other integer type) imposes an alignment for the
1564 entire structure, as if the structure really did contain an
1565 ordinary field of that type. In addition, the bit-field is placed
1566 within the structure so that it would fit within such a field,
1567 not crossing a boundary for it.
1569 Thus, on most machines, a bit-field whose type is written as `int'
1570 would not cross a four-byte boundary, and would force four-byte
1571 alignment for the whole structure. (The alignment used may not
1572 be four bytes; it is controlled by the other alignment
1575 If the macro is defined, its definition should be a C expression;
1576 a nonzero value for the expression enables this behavior. */
1578 #define PCC_BITFIELD_TYPE_MATTERS 1
1580 /* If defined, a C expression to compute the alignment given to a
1581 constant that is being placed in memory. CONSTANT is the constant
1582 and ALIGN is the alignment that the object would ordinarily have.
1583 The value of this macro is used instead of that alignment to align
1586 If this macro is not defined, then ALIGN is used.
1588 The typical use of this macro is to increase alignment for string
1589 constants to be word aligned so that `strcpy' calls that copy
1590 constants can be done inline. */
1592 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1593 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1594 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1596 /* If defined, a C expression to compute the alignment for a static
1597 variable. TYPE is the data type, and ALIGN is the alignment that
1598 the object would ordinarily have. The value of this macro is used
1599 instead of that alignment to align the object.
1601 If this macro is not defined, then ALIGN is used.
1603 One use of this macro is to increase alignment of medium-size
1604 data to make it all fit in fewer cache lines. Another is to
1605 cause character arrays to be word-aligned so that `strcpy' calls
1606 that copy constants to character arrays can be done inline. */
1608 #undef DATA_ALIGNMENT
1609 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1610 ((((ALIGN) < BITS_PER_WORD) \
1611 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1612 || TREE_CODE (TYPE) == UNION_TYPE \
1613 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1616 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1618 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1620 /* Define this macro if an argument declared as `char' or `short' in a
1621 prototype should actually be passed as an `int'. In addition to
1622 avoiding errors in certain cases of mismatch, it also makes for
1623 better code on certain machines. */
1625 #define PROMOTE_PROTOTYPES 1
1627 /* Define if operations between registers always perform the operation
1628 on the full register even if a narrower mode is specified. */
1629 #define WORD_REGISTER_OPERATIONS
1631 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1632 will either zero-extend or sign-extend. The value of this macro should
1633 be the code that says which one of the two operations is implicitly
1636 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1637 moves. All other referces are zero extended. */
1638 #define LOAD_EXTEND_OP(MODE) \
1639 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1640 ? SIGN_EXTEND : ZERO_EXTEND)
1642 /* Define this macro if it is advisable to hold scalars in registers
1643 in a wider mode than that declared by the program. In such cases,
1644 the value is constrained to be within the bounds of the declared
1645 type, but kept valid in the wider mode. The signedness of the
1646 extension may differ from that of the type. */
1648 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1649 if (GET_MODE_CLASS (MODE) == MODE_INT \
1650 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1652 if ((MODE) == SImode) \
1657 /* Define if loading short immediate values into registers sign extends. */
1658 #define SHORT_IMMEDIATES_SIGN_EXTEND
1661 /* Define this if function arguments should also be promoted using the above
1663 #define PROMOTE_FUNCTION_ARGS
1665 /* Likewise, if the function return value is promoted. */
1666 #define PROMOTE_FUNCTION_RETURN
1669 /* Standard register usage. */
1671 /* Number of actual hardware registers.
1672 The hardware registers are assigned numbers for the compiler
1673 from 0 to just below FIRST_PSEUDO_REGISTER.
1674 All registers that the compiler knows about must be given numbers,
1675 even those that are not normally considered general registers.
1677 On the Mips, we have 32 integer registers, 32 floating point
1678 registers, 8 condition code registers, and the special registers
1679 hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
1680 and 32 COP3 registers. (COP1 is the floating-point processor.)
1681 The 8 condition code registers are only used if mips_isa >= 4. */
1683 #define FIRST_PSEUDO_REGISTER 176
1685 /* 1 for registers that have pervasive standard uses
1686 and are not available for the register allocator.
1688 On the MIPS, see conventions, page D-2 */
1690 /* Regarding coprocessor registers: without evidence to the contrary,
1691 it's best to assume that each coprocessor register has a unique
1692 use. This can be overridden, in, e.g., override_options() or
1693 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1694 for a particular target. */
1696 #define FIXED_REGISTERS \
1698 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1699 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1700 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1701 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1702 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1703 /* COP0 registers */ \
1704 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1705 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1706 /* COP2 registers */ \
1707 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1708 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1709 /* COP3 registers */ \
1710 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1711 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1715 /* Don't mark $31 as a call-clobbered register. The idea is that
1716 it's really the call instructions themselves which clobber $31.
1717 We don't care what the called function does with it afterwards.
1719 This approach makes it easier to implement sibcalls. Unlike normal
1720 calls, sibcalls don't clobber $31, so the register reaches the
1721 called function in tact. EPILOGUE_USES says that $31 is useful
1722 to the called function. */
1724 #define CALL_USED_REGISTERS \
1726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1727 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1728 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1729 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1730 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1731 /* COP0 registers */ \
1732 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1733 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1734 /* COP2 registers */ \
1735 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1736 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1737 /* COP3 registers */ \
1738 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1739 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1742 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1743 problem which makes CALL_USED_REGISTERS *always* include
1744 all the FIXED_REGISTERS. Until this problem has been
1745 resolved this macro can be used to overcome this situation.
1746 In particular, block_propagate() requires this list
1747 be acurate, or we can remove registers which should be live.
1748 This macro is used in regs_invalidated_by_call. */
1751 #define CALL_REALLY_USED_REGISTERS \
1752 { /* General registers. */ \
1753 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1754 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1755 /* Floating-point registers. */ \
1756 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1757 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1759 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1760 /* COP0 registers */ \
1761 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1763 /* COP2 registers */ \
1764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1766 /* COP3 registers */ \
1767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1771 /* Internal macros to classify a register number as to whether it's a
1772 general purpose register, a floating point register, a
1773 multiply/divide register, or a status register. */
1775 #define GP_REG_FIRST 0
1776 #define GP_REG_LAST 31
1777 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1778 #define GP_DBX_FIRST 0
1780 #define FP_REG_FIRST 32
1781 #define FP_REG_LAST 63
1782 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1783 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1785 #define MD_REG_FIRST 64
1786 #define MD_REG_LAST 65
1787 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1788 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1790 #define ST_REG_FIRST 67
1791 #define ST_REG_LAST 74
1792 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1795 /* FIXME: renumber. */
1796 #define COP0_REG_FIRST 80
1797 #define COP0_REG_LAST 111
1798 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1800 #define COP2_REG_FIRST 112
1801 #define COP2_REG_LAST 143
1802 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1804 #define COP3_REG_FIRST 144
1805 #define COP3_REG_LAST 175
1806 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1807 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1808 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1810 #define AT_REGNUM (GP_REG_FIRST + 1)
1811 #define HI_REGNUM (MD_REG_FIRST + 0)
1812 #define LO_REGNUM (MD_REG_FIRST + 1)
1814 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1815 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1816 should be used instead. */
1817 #define FPSW_REGNUM ST_REG_FIRST
1819 #define GP_REG_P(REGNO) \
1820 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1821 #define M16_REG_P(REGNO) \
1822 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1823 #define FP_REG_P(REGNO) \
1824 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1825 #define MD_REG_P(REGNO) \
1826 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1827 #define ST_REG_P(REGNO) \
1828 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1829 #define COP0_REG_P(REGNO) \
1830 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1831 #define COP2_REG_P(REGNO) \
1832 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1833 #define COP3_REG_P(REGNO) \
1834 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1835 #define ALL_COP_REG_P(REGNO) \
1836 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1838 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1840 /* Return coprocessor number from register number. */
1842 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1843 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1844 : COP3_REG_P (REGNO) ? '3' : '?')
1846 /* Return number of consecutive hard regs needed starting at reg REGNO
1847 to hold something of mode MODE.
1848 This is ordinarily the length in words of a value of mode MODE
1849 but can be less for certain modes in special long registers.
1851 On the MIPS, all general registers are one word long. Except on
1852 the R4000 with the FR bit set, the floating point uses register
1853 pairs, with the second register not being allocable. */
1855 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1857 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1858 MODE. In 32 bit mode, require that DImode and DFmode be in even
1859 registers. For DImode, this makes some of the insns easier to
1860 write, since you don't have to worry about a DImode value in
1861 registers 3 & 4, producing a result in 4 & 5.
1863 To make the code simpler HARD_REGNO_MODE_OK now just references an
1864 array built in override_options. Because machmodes.h is not yet
1865 included before this file is processed, the MODE bound can't be
1868 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1870 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1871 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1873 /* Value is 1 if it is a good idea to tie two pseudo registers
1874 when one has mode MODE1 and one has mode MODE2.
1875 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1876 for any hard reg, then this must be 0 for correct output. */
1877 #define MODES_TIEABLE_P(MODE1, MODE2) \
1878 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1879 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1880 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1881 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1883 /* MIPS pc is not overloaded on a register. */
1884 /* #define PC_REGNUM xx */
1886 /* Register to use for pushing function arguments. */
1887 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1889 /* Offset from the stack pointer to the first available location. Use
1890 the default value zero. */
1891 /* #define STACK_POINTER_OFFSET 0 */
1893 /* Base register for access to local variables of the function. We
1894 pretend that the frame pointer is $1, and then eliminate it to
1895 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1896 a fixed register, and will not be used for anything else. */
1897 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1899 /* Temporary scratch register for use by the assembler. */
1900 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1902 /* $30 is not available on the mips16, so we use $17 as the frame
1904 #define HARD_FRAME_POINTER_REGNUM \
1905 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1907 /* Value should be nonzero if functions must have frame pointers.
1908 Zero means the frame pointer need not be set up (and parms
1909 may be accessed via the stack pointer) in functions that seem suitable.
1910 This is computed in `reload', in reload1.c. */
1911 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1913 /* Base register for access to arguments of the function. */
1914 #define ARG_POINTER_REGNUM GP_REG_FIRST
1916 /* Register in which static-chain is passed to a function. */
1917 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1919 /* If the structure value address is passed in a register, then
1920 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1921 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1923 /* If the structure value address is not passed in a register, define
1924 `STRUCT_VALUE' as an expression returning an RTX for the place
1925 where the address is passed. If it returns 0, the address is
1926 passed as an "invisible" first argument. */
1927 #define STRUCT_VALUE 0
1929 /* Mips registers used in prologue/epilogue code when the stack frame
1930 is larger than 32K bytes. These registers must come from the
1931 scratch register set, and not used for passing and returning
1932 arguments and any other information used in the calling sequence
1933 (such as pic). Must start at 12, since t0/t3 are parameter passing
1934 registers in the 64 bit ABI. */
1936 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1937 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1939 /* Define this macro if it is as good or better to call a constant
1940 function address than to call an address kept in a register. */
1941 #define NO_FUNCTION_CSE 1
1943 /* Define this macro if it is as good or better for a function to
1944 call itself with an explicit address than to call an address
1945 kept in a register. */
1946 #define NO_RECURSIVE_FUNCTION_CSE 1
1948 /* The ABI-defined global pointer. Sometimes we use a different
1949 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1950 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1952 /* We normally use $28 as the global pointer. However, when generating
1953 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1954 register instead. They can then avoid saving and restoring $28
1955 and perhaps avoid using a frame at all.
1957 When a leaf function uses something other than $28, mips_expand_prologue
1958 will modify pic_offset_table_rtx in place. Take the register number
1959 from there after reload. */
1960 #define PIC_OFFSET_TABLE_REGNUM \
1961 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1963 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1965 /* Define the classes of registers for register constraints in the
1966 machine description. Also define ranges of constants.
1968 One of the classes must always be named ALL_REGS and include all hard regs.
1969 If there is more than one class, another class must be named NO_REGS
1970 and contain no registers.
1972 The name GENERAL_REGS must be the name of a class (or an alias for
1973 another name such as ALL_REGS). This is the class of registers
1974 that is allowed by "g" or "r" in a register constraint.
1975 Also, registers outside this class are allocated only when
1976 instructions express preferences for them.
1978 The classes must be numbered in nondecreasing order; that is,
1979 a larger-numbered class must never be contained completely
1980 in a smaller-numbered class.
1982 For any two classes, it is very desirable that there be another
1983 class that represents their union. */
1987 NO_REGS, /* no registers in set */
1988 M16_NA_REGS, /* mips16 regs not used to pass args */
1989 M16_REGS, /* mips16 directly accessible registers */
1990 T_REG, /* mips16 T register ($24) */
1991 M16_T_REGS, /* mips16 registers plus T register */
1992 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1993 LEA_REGS, /* Every GPR except $25 */
1994 GR_REGS, /* integer registers */
1995 FP_REGS, /* floating point registers */
1996 HI_REG, /* hi register */
1997 LO_REG, /* lo register */
1998 MD_REGS, /* multiply/divide registers (hi/lo) */
1999 COP0_REGS, /* generic coprocessor classes */
2002 HI_AND_GR_REGS, /* union classes */
2009 ALL_COP_AND_GR_REGS,
2010 ST_REGS, /* status registers (fp status) */
2011 ALL_REGS, /* all registers */
2012 LIM_REG_CLASSES /* max value + 1 */
2015 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2017 #define GENERAL_REGS GR_REGS
2019 /* An initializer containing the names of the register classes as C
2020 string constants. These names are used in writing some of the
2023 #define REG_CLASS_NAMES \
2030 "PIC_FN_ADDR_REG", \
2037 /* coprocessor registers */ \
2044 "COP0_AND_GR_REGS", \
2045 "COP2_AND_GR_REGS", \
2046 "COP3_AND_GR_REGS", \
2048 "ALL_COP_AND_GR_REGS", \
2053 /* An initializer containing the contents of the register classes,
2054 as integers which are bit masks. The Nth integer specifies the
2055 contents of class N. The way the integer MASK is interpreted is
2056 that register R is in the class if `MASK & (1 << R)' is 1.
2058 When the machine has more than 32 registers, an integer does not
2059 suffice. Then the integers are replaced by sub-initializers,
2060 braced groupings containing several integers. Each
2061 sub-initializer must be suitable as an initializer for the type
2062 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2064 #define REG_CLASS_CONTENTS \
2066 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2067 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2068 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2069 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2070 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2071 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
2072 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
2073 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2074 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2075 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2076 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2077 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2078 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2079 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2080 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2081 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2082 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2083 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2084 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2085 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2086 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2087 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2088 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2089 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2090 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2094 /* A C expression whose value is a register class containing hard
2095 register REGNO. In general there is more that one such class;
2096 choose a class which is "minimal", meaning that no smaller class
2097 also contains the register. */
2099 extern const enum reg_class mips_regno_to_class[];
2101 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2103 /* A macro whose definition is the name of the class to which a
2104 valid base register must belong. A base register is one used in
2105 an address which is the register value plus a displacement. */
2107 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2109 /* A macro whose definition is the name of the class to which a
2110 valid index register must belong. An index register is one used
2111 in an address where its value is either multiplied by a scale
2112 factor or added to another register (as well as added to a
2115 #define INDEX_REG_CLASS NO_REGS
2117 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2118 registers explicitly used in the rtl to be used as spill registers
2119 but prevents the compiler from extending the lifetime of these
2122 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2124 /* This macro is used later on in the file. */
2125 #define GR_REG_CLASS_P(CLASS) \
2126 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2127 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
2128 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
2130 /* This macro is also used later on in the file. */
2131 #define COP_REG_CLASS_P(CLASS) \
2132 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2134 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2135 is the default value (allocate the registers in numeric order). We
2136 define it just so that we can override it for the mips16 target in
2137 ORDER_REGS_FOR_LOCAL_ALLOC. */
2139 #define REG_ALLOC_ORDER \
2140 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2141 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2142 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2143 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2144 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2145 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2146 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2147 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2148 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2149 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2150 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2153 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2154 to be rearranged based on a particular function. On the mips16, we
2155 want to allocate $24 (T_REG) before other registers for
2156 instructions for which it is possible. */
2158 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2160 /* REGISTER AND CONSTANT CLASSES */
2162 /* Get reg_class from a letter such as appears in the machine
2165 DEFINED REGISTER CLASSES:
2167 'd' General (aka integer) registers
2168 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2169 'y' General registers (in both mips16 and non mips16 mode)
2170 'e' mips16 non argument registers (M16_NA_REGS)
2171 't' mips16 temporary register ($24)
2172 'f' Floating point registers
2175 'x' Multiply/divide registers
2176 'z' FP Status register
2180 'b' All registers */
2182 extern enum reg_class mips_char_to_class[256];
2184 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2186 /* True if VALUE is a signed 16-bit number. */
2188 #define SMALL_OPERAND(VALUE) \
2189 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2191 /* True if VALUE is an unsigned 16-bit number. */
2193 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2194 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2196 /* True if VALUE can be loaded into a register using LUI. */
2198 #define LUI_OPERAND(VALUE) \
2199 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2200 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2202 /* Return a value X with the low 16 bits clear, and such that
2203 VALUE - X is a signed 16-bit value. */
2205 #define CONST_HIGH_PART(VALUE) \
2206 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2208 #define CONST_LOW_PART(VALUE) \
2209 ((VALUE) - CONST_HIGH_PART (VALUE))
2211 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2212 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2213 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2215 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2216 string can be used to stand for particular ranges of immediate
2217 operands. This macro defines what the ranges are. C is the
2218 letter, and VALUE is a constant value. Return 1 if VALUE is
2219 in the range specified by C. */
2223 `I' is used for the range of constants an arithmetic insn can
2224 actually contain (16 bits signed integers).
2226 `J' is used for the range which is just zero (ie, $r0).
2228 `K' is used for the range of constants a logical insn can actually
2229 contain (16 bit zero-extended integers).
2231 `L' is used for the range of constants that be loaded with lui
2232 (ie, the bottom 16 bits are zero).
2234 `M' is used for the range of constants that take two words to load
2235 (ie, not matched by `I', `K', and `L').
2237 `N' is used for negative 16 bit constants other than -65536.
2239 `O' is a 15 bit signed integer.
2241 `P' is used for positive 16 bit constants. */
2243 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2244 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2245 : (C) == 'J' ? ((VALUE) == 0) \
2246 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2247 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2248 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2249 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2250 && !LUI_OPERAND (VALUE)) \
2251 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2252 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2253 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2256 /* Similar, but for floating constants, and defining letters G and H.
2257 Here VALUE is the CONST_DOUBLE rtx itself. */
2261 'G' : Floating point 0 */
2263 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2265 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2267 /* True if OP is a constant that should not be moved into $25.
2268 We need this because many versions of gas treat 'la $25,foo' as
2269 part of a call sequence and allow a global 'foo' to be lazily bound. */
2271 #define DANGEROUS_FOR_LA25_P(OP) \
2273 && !TARGET_EXPLICIT_RELOCS \
2274 && mips_global_pic_constant_p (OP))
2276 /* Letters in the range `Q' through `U' may be defined in a
2277 machine-dependent fashion to stand for arbitrary operand types.
2278 The machine description macro `EXTRA_CONSTRAINT' is passed the
2279 operand as its first argument and the constraint letter as its
2282 `Q' is for signed 16-bit constants.
2283 `R' is for single-instruction memory references. Note that this
2284 constraint has often been used in linux and glibc code.
2285 `S' is for legitimate constant call addresses.
2286 `T' is for constant move_operands that cannot be safely loaded into $25.
2287 `U' is for constant move_operands that can be safely loaded into $25. */
2289 #define EXTRA_CONSTRAINT(OP,CODE) \
2290 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2291 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2292 && mips_fetch_insns (OP) == 1) \
2293 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2294 && call_insn_operand (OP, VOIDmode)) \
2295 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2296 && move_operand (OP, VOIDmode) \
2297 && DANGEROUS_FOR_LA25_P (OP)) \
2298 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2299 && move_operand (OP, VOIDmode) \
2300 && !DANGEROUS_FOR_LA25_P (OP)) \
2303 /* Given an rtx X being reloaded into a reg required to be
2304 in class CLASS, return the class of reg to actually use.
2305 In general this is just CLASS; but on some machines
2306 in some cases it is preferable to use a more restrictive class. */
2308 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2309 ((CLASS) != ALL_REGS \
2310 ? (! TARGET_MIPS16 \
2312 : ((CLASS) != GR_REGS \
2315 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2316 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2317 ? (TARGET_SOFT_FLOAT \
2318 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2320 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2321 || GET_MODE (X) == VOIDmode) \
2322 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2325 /* Certain machines have the property that some registers cannot be
2326 copied to some other registers without using memory. Define this
2327 macro on those machines to be a C expression that is nonzero if
2328 objects of mode MODE in registers of CLASS1 can only be copied to
2329 registers of class CLASS2 by storing a register of CLASS1 into
2330 memory and loading that memory location into a register of CLASS2.
2332 Do not define this macro if its value would always be zero. */
2334 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2335 ((!TARGET_DEBUG_H_MODE \
2336 && GET_MODE_CLASS (MODE) == MODE_INT \
2337 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2338 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2339 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2340 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2341 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2343 /* The HI and LO registers can only be reloaded via the general
2344 registers. Condition code registers can only be loaded to the
2345 general registers, and from the floating point registers. */
2347 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2348 mips_secondary_reload_class (CLASS, MODE, X, 1)
2349 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2350 mips_secondary_reload_class (CLASS, MODE, X, 0)
2352 /* Return the maximum number of consecutive registers
2353 needed to represent mode MODE in a register of class CLASS. */
2355 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2357 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2358 mips_cannot_change_mode_class (FROM, TO, CLASS)
2360 /* Stack layout; function entry, exit and calling. */
2362 #define STACK_GROWS_DOWNWARD
2364 /* The offset of the first local variable from the beginning of the frame.
2365 See compute_frame_size for details about the frame layout. */
2366 #define STARTING_FRAME_OFFSET \
2367 (current_function_outgoing_args_size \
2368 + (TARGET_ABICALLS && !TARGET_NEWABI \
2369 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2371 /* Offset from the stack pointer register to an item dynamically
2372 allocated on the stack, e.g., by `alloca'.
2374 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2375 length of the outgoing arguments. The default is correct for most
2376 machines. See `function.c' for details.
2378 The MIPS ABI states that functions which dynamically allocate the
2379 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2380 we are trying to create a second frame pointer to the function, so
2381 allocate some stack space to make it happy.
2383 However, the linker currently complains about linking any code that
2384 dynamically allocates stack space, and there seems to be a bug in
2385 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2388 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2389 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2390 ? 4*UNITS_PER_WORD \
2391 : current_function_outgoing_args_size)
2394 /* The return address for the current frame is in r31 if this is a leaf
2395 function. Otherwise, it is on the stack. It is at a variable offset
2396 from sp/fp/ap, so we define a fake hard register rap which is a
2397 poiner to the return address on the stack. This always gets eliminated
2398 during reload to be either the frame pointer or the stack pointer plus
2401 #define RETURN_ADDR_RTX mips_return_addr
2403 /* Since the mips16 ISA mode is encoded in the least-significant bit
2404 of the address, mask it off return addresses for purposes of
2405 finding exception handling regions. */
2407 #define MASK_RETURN_ADDR GEN_INT (-2)
2410 /* Similarly, don't use the least-significant bit to tell pointers to
2411 code from vtable index. */
2413 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2415 /* If defined, this macro specifies a table of register pairs used to
2416 eliminate unneeded registers that point into the stack frame. If
2417 it is not defined, the only elimination attempted by the compiler
2418 is to replace references to the frame pointer with references to
2421 The definition of this macro is a list of structure
2422 initializations, each of which specifies an original and
2423 replacement register.
2425 On some machines, the position of the argument pointer is not
2426 known until the compilation is completed. In such a case, a
2427 separate hard register must be used for the argument pointer.
2428 This register can be eliminated by replacing it with either the
2429 frame pointer or the argument pointer, depending on whether or not
2430 the frame pointer has been eliminated.
2432 In this case, you might specify:
2433 #define ELIMINABLE_REGS \
2434 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2435 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2436 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2438 Note that the elimination of the argument pointer with the stack
2439 pointer is specified first since that is the preferred elimination.
2441 The eliminations to $17 are only used on the mips16. See the
2442 definition of HARD_FRAME_POINTER_REGNUM. */
2444 #define ELIMINABLE_REGS \
2445 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2446 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2447 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2448 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2449 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2450 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2452 /* A C expression that returns nonzero if the compiler is allowed to
2453 try to replace register number FROM-REG with register number
2454 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2455 defined, and will usually be the constant 1, since most of the
2456 cases preventing register elimination are things that the compiler
2457 already knows about.
2459 When not in mips16 and mips64, we can always eliminate to the
2460 frame pointer. We can eliminate to the stack pointer unless
2461 a frame pointer is needed. In mips16 mode, we need a frame
2462 pointer for a large frame; otherwise, reload may be unable
2463 to compute the address of a local variable, since there is
2464 no way to add a large constant to the stack pointer
2465 without using a temporary register.
2467 In mips16, for some instructions (eg lwu), we can't eliminate the
2468 frame pointer for the stack pointer. These instructions are
2469 only generated in TARGET_64BIT mode.
2472 #define CAN_ELIMINATE(FROM, TO) \
2473 (((TO) == HARD_FRAME_POINTER_REGNUM \
2474 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2475 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2476 && (! TARGET_MIPS16 \
2477 || compute_frame_size (get_frame_size ()) < 32768))))
2479 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2480 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2482 /* If we generate an insn to push BYTES bytes,
2483 this says how many the stack pointer really advances by.
2484 On the VAX, sp@- in a byte insn really pushes a word. */
2486 /* #define PUSH_ROUNDING(BYTES) 0 */
2488 /* If defined, the maximum amount of space required for outgoing
2489 arguments will be computed and placed into the variable
2490 `current_function_outgoing_args_size'. No space will be pushed
2491 onto the stack for each call; instead, the function prologue
2492 should increase the stack frame size by this amount.
2494 It is not proper to define both `PUSH_ROUNDING' and
2495 `ACCUMULATE_OUTGOING_ARGS'. */
2496 #define ACCUMULATE_OUTGOING_ARGS 1
2498 /* Offset from the argument pointer register to the first argument's
2499 address. On some machines it may depend on the data type of the
2502 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2503 the first argument's address.
2505 On the MIPS, we must skip the first argument position if we are
2506 returning a structure or a union, to account for its address being
2507 passed in $4. However, at the current time, this produces a compiler
2508 that can't bootstrap, so comment it out for now. */
2511 #define FIRST_PARM_OFFSET(FNDECL) \
2513 && TREE_TYPE (FNDECL) != 0 \
2514 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2515 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2516 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2520 #define FIRST_PARM_OFFSET(FNDECL) 0
2523 /* When a parameter is passed in a register, stack space is still
2524 allocated for it. For the MIPS, stack space must be allocated, cf
2525 Asm Lang Prog Guide page 7-8.
2527 BEWARE that some space is also allocated for non existing arguments
2528 in register. In case an argument list is of form GF used registers
2529 are a0 (a2,a3), but we should push over a1... */
2531 #define REG_PARM_STACK_SPACE(FNDECL) \
2532 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2533 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2536 /* Define this if it is the responsibility of the caller to
2537 allocate the area reserved for arguments passed in registers.
2538 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2539 of this macro is to determine whether the space is included in
2540 `current_function_outgoing_args_size'. */
2541 #define OUTGOING_REG_PARM_STACK_SPACE
2543 #define STACK_BOUNDARY \
2544 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2547 /* Make sure 4 words are always allocated on the stack. */
2549 #ifndef STACK_ARGS_ADJUST
2550 #define STACK_ARGS_ADJUST(SIZE) \
2552 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2553 SIZE.constant = 4 * UNITS_PER_WORD; \
2558 /* A C expression that should indicate the number of bytes of its
2559 own arguments that a function pops on returning, or 0
2560 if the function pops no arguments and the caller must therefore
2561 pop them all after the function returns.
2563 FUNDECL is the declaration node of the function (as a tree).
2565 FUNTYPE is a C variable whose value is a tree node that
2566 describes the function in question. Normally it is a node of
2567 type `FUNCTION_TYPE' that describes the data type of the function.
2568 From this it is possible to obtain the data types of the value
2569 and arguments (if known).
2571 When a call to a library function is being considered, FUNTYPE
2572 will contain an identifier node for the library function. Thus,
2573 if you need to distinguish among various library functions, you
2574 can do so by their names. Note that "library function" in this
2575 context means a function used to perform arithmetic, whose name
2576 is known specially in the compiler and was not mentioned in the
2577 C code being compiled.
2579 STACK-SIZE is the number of bytes of arguments passed on the
2580 stack. If a variable number of bytes is passed, it is zero, and
2581 argument popping will always be the responsibility of the
2582 calling function. */
2584 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2587 /* Symbolic macros for the registers used to return integer and floating
2590 #define GP_RETURN (GP_REG_FIRST + 2)
2591 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2593 #define MAX_ARGS_IN_REGISTERS \
2594 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2596 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2598 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2600 /* Symbolic macros for the first/last argument registers. */
2602 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2603 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2604 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2605 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2607 /* Define how to find the value returned by a library function
2608 assuming the value has mode MODE. Because we define
2609 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2610 PROMOTE_MODE does. */
2612 #define LIBCALL_VALUE(MODE) \
2613 mips_function_value (NULL_TREE, NULL, (MODE))
2615 /* Define how to find the value returned by a function.
2616 VALTYPE is the data type of the value (as a tree).
2617 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2618 otherwise, FUNC is 0. */
2620 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2621 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2623 /* 1 if N is a possible register number for a function value.
2624 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2625 Currently, R2 and F0 are only implemented here (C has no complex type) */
2627 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2628 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2629 && (N) == FP_RETURN + 2))
2631 /* 1 if N is a possible register number for function argument passing.
2632 We have no FP argument registers when soft-float. When FP registers
2633 are 32 bits, we can't directly reference the odd numbered ones. */
2635 #define FUNCTION_ARG_REGNO_P(N) \
2636 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2637 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2638 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2641 /* A C expression which can inhibit the returning of certain function
2642 values in registers, based on the type of value. A nonzero value says
2643 to return the function value in memory, just as large structures are
2644 always returned. Here TYPE will be a C expression of type
2645 `tree', representing the data type of the value.
2647 Note that values of mode `BLKmode' must be explicitly
2648 handled by this macro. Also, the option `-fpcc-struct-return'
2649 takes effect regardless of this macro. On most systems, it is
2650 possible to leave the macro undefined; this causes a default
2651 definition to be used, whose value is the constant 1 for BLKmode
2652 values, and 0 otherwise.
2654 GCC normally converts 1 byte structures into chars, 2 byte
2655 structs into shorts, and 4 byte structs into ints, and returns
2656 them this way. Defining the following macro overrides this,
2657 to give us MIPS cc compatibility. */
2659 #define RETURN_IN_MEMORY(TYPE) \
2660 mips_return_in_memory (TYPE)
2662 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2663 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2666 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2668 /* Define a data type for recording info about an argument list
2669 during the scan of that argument list. This data type should
2670 hold all necessary information about the function itself
2671 and about the args processed so far, enough to enable macros
2672 such as FUNCTION_ARG to determine where the next arg should go.
2674 This structure has to cope with two different argument allocation
2675 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2676 first N words go in registers and the rest go on the stack. If I < N,
2677 the Ith word might go in Ith integer argument register or the
2678 Ith floating-point one. In some cases, it has to go in both (see
2679 function_arg). For these ABIs, we only need to remember the number
2680 of words passed so far.
2682 The EABI instead allocates the integer and floating-point arguments
2683 separately. The first N words of FP arguments go in FP registers,
2684 the rest go on the stack. Likewise, the first N words of the other
2685 arguments go in integer registers, and the rest go on the stack. We
2686 need to maintain three counts: the number of integer registers used,
2687 the number of floating-point registers used, and the number of words
2688 passed on the stack.
2690 We could keep separate information for the two ABIs (a word count for
2691 the standard ABIs, and three separate counts for the EABI). But it
2692 seems simpler to view the standard ABIs as forms of EABI that do not
2693 allocate floating-point registers.
2695 So for the standard ABIs, the first N words are allocated to integer
2696 registers, and function_arg decides on an argument-by-argument basis
2697 whether that argument should really go in an integer register, or in
2698 a floating-point one. */
2700 typedef struct mips_args {
2701 /* Always true for varargs functions. Otherwise true if at least
2702 one argument has been passed in an integer register. */
2705 /* The number of arguments seen so far. */
2706 unsigned int arg_number;
2708 /* For EABI, the number of integer registers used so far. For other
2709 ABIs, the number of words passed in registers (whether integer
2710 or floating-point). */
2711 unsigned int num_gprs;
2713 /* For EABI, the number of floating-point registers used so far. */
2714 unsigned int num_fprs;
2716 /* The number of words passed on the stack. */
2717 unsigned int stack_words;
2719 /* On the mips16, we need to keep track of which floating point
2720 arguments were passed in general registers, but would have been
2721 passed in the FP regs if this were a 32 bit function, so that we
2722 can move them to the FP regs if we wind up calling a 32 bit
2723 function. We record this information in fp_code, encoded in base
2724 four. A zero digit means no floating point argument, a one digit
2725 means an SFmode argument, and a two digit means a DFmode argument,
2726 and a three digit is not used. The low order digit is the first
2727 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2728 an SFmode argument. ??? A more sophisticated approach will be
2729 needed if MIPS_ABI != ABI_32. */
2732 /* True if the function has a prototype. */
2735 /* When a structure does not take up a full register, the argument
2736 should sometimes be shifted left so that it occupies the high part
2737 of the register. These two fields describe an array of ashl
2738 patterns for doing this. See function_arg_advance, which creates
2739 the shift patterns, and function_arg, which returns them when given
2740 a VOIDmode argument. */
2741 unsigned int num_adjusts;
2742 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2745 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2746 for a call to a function whose data type is FNTYPE.
2747 For a library call, FNTYPE is 0.
2751 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2752 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2754 /* Update the data in CUM to advance over an argument
2755 of mode MODE and data type TYPE.
2756 (TYPE is null for libcalls where that information may not be available.) */
2758 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2759 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2761 /* Determine where to put an argument to a function.
2762 Value is zero to push the argument on the stack,
2763 or a hard register in which to store the argument.
2765 MODE is the argument's machine mode.
2766 TYPE is the data type of the argument (as a tree).
2767 This is null for libcalls where that information may
2769 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2770 the preceding args and about the function being called.
2771 NAMED is nonzero if this argument is a named parameter
2772 (otherwise it is an extra parameter matching an ellipsis). */
2774 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2775 function_arg( &CUM, MODE, TYPE, NAMED)
2777 /* For an arg passed partly in registers and partly in memory,
2778 this is the number of registers used.
2779 For args passed entirely in registers or entirely in memory, zero. */
2781 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2782 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2784 /* If defined, a C expression that gives the alignment boundary, in
2785 bits, of an argument with the specified mode and type. If it is
2786 not defined, `PARM_BOUNDARY' is used for all arguments. */
2788 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2790 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2792 : TYPE_ALIGN(TYPE)) \
2793 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2795 : GET_MODE_ALIGNMENT(MODE)))
2797 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2798 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2800 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2801 (! BYTES_BIG_ENDIAN \
2803 : (((MODE) == BLKmode \
2804 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2805 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2806 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2807 && (mips_abi == ABI_32 \
2808 || mips_abi == ABI_O64 \
2809 || mips_abi == ABI_EABI \
2810 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2811 ? downward : upward))
2813 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2814 (mips_abi == ABI_EABI && (NAMED) \
2815 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2817 /* Modified version of the macro in expr.h. */
2818 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2820 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2821 || TREE_ADDRESSABLE (TYPE) \
2822 || ((MODE) == BLKmode \
2823 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2824 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2825 && 0 == (int_size_in_bytes (TYPE) \
2826 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2827 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2828 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2830 /* True if using EABI and varargs can be passed in floating-point
2831 registers. Under these conditions, we need a more complex form
2832 of va_list, which tracks GPR, FPR and stack arguments separately. */
2833 #define EABI_FLOAT_VARARGS_P \
2834 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2837 /* Say that the epilogue uses the return address register. Note that
2838 in the case of sibcalls, the values "used by the epilogue" are
2839 considered live at the start of the called function. */
2840 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2842 /* Treat LOC as a byte offset from the stack pointer and round it up
2843 to the next fully-aligned offset. */
2844 #define MIPS_STACK_ALIGN(LOC) \
2845 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2846 ? ((LOC) + 7) & ~7 \
2847 : ((LOC) + 15) & ~15)
2850 /* Define the `__builtin_va_list' type for the ABI. */
2851 #define BUILD_VA_LIST_TYPE(VALIST) \
2852 (VALIST) = mips_build_va_list ()
2854 /* Implement `va_start' for varargs and stdarg. */
2855 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2856 mips_va_start (valist, nextarg)
2858 /* Implement `va_arg'. */
2859 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2860 mips_va_arg (valist, type)
2862 /* Output assembler code to FILE to increment profiler label # LABELNO
2863 for profiling a function entry. */
2865 #define FUNCTION_PROFILER(FILE, LABELNO) \
2867 if (TARGET_MIPS16) \
2868 sorry ("mips16 function profiling"); \
2869 fprintf (FILE, "\t.set\tnoat\n"); \
2870 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2871 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2872 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2875 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2876 TARGET_64BIT ? "dsubu" : "subu", \
2877 reg_names[STACK_POINTER_REGNUM], \
2878 reg_names[STACK_POINTER_REGNUM], \
2879 Pmode == DImode ? 16 : 8); \
2881 fprintf (FILE, "\tjal\t_mcount\n"); \
2882 fprintf (FILE, "\t.set\tat\n"); \
2885 /* Define this macro if the code for function profiling should come
2886 before the function prologue. Normally, the profiling code comes
2889 /* #define PROFILE_BEFORE_PROLOGUE */
2891 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2892 the stack pointer does not matter. The value is tested only in
2893 functions that have frame pointers.
2894 No definition is equivalent to always zero. */
2896 #define EXIT_IGNORE_STACK 1
2899 /* A C statement to output, on the stream FILE, assembler code for a
2900 block of data that contains the constant parts of a trampoline.
2901 This code should not include a label--the label is taken care of
2904 #define TRAMPOLINE_TEMPLATE(STREAM) \
2906 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2907 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2908 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2909 if (ptr_mode == DImode) \
2911 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2912 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2916 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2917 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2919 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2920 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2921 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2922 if (ptr_mode == DImode) \
2924 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2925 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2929 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2930 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2934 /* A C expression for the size in bytes of the trampoline, as an
2937 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2939 /* Alignment required for trampolines, in bits. */
2941 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2943 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2944 program and data caches. */
2946 #ifndef CACHE_FLUSH_FUNC
2947 #define CACHE_FLUSH_FUNC "_flush_cache"
2950 /* A C statement to initialize the variable parts of a trampoline.
2951 ADDR is an RTX for the address of the trampoline; FNADDR is an
2952 RTX for the address of the nested function; STATIC_CHAIN is an
2953 RTX for the static chain value that should be passed to the
2954 function when it is called. */
2956 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2958 rtx func_addr, chain_addr; \
2960 func_addr = plus_constant (ADDR, 32); \
2961 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2962 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2963 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2964 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2965 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2967 /* Flush both caches. We need to flush the data cache in case \
2968 the system has a write-back cache. */ \
2969 /* ??? Should check the return value for errors. */ \
2970 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2971 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2972 0, VOIDmode, 3, ADDR, Pmode, \
2973 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2974 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2977 /* Addressing modes, and classification of registers for them. */
2979 /* These assume that REGNO is a hard or pseudo reg number.
2980 They give nonzero only if REGNO is a hard reg of the suitable class
2981 or a pseudo reg currently allocated to a suitable hard reg.
2982 These definitions are NOT overridden anywhere. */
2984 #define BASE_REG_P(regno, mode) \
2986 ? (M16_REG_P (regno) \
2987 || (regno) == FRAME_POINTER_REGNUM \
2988 || (regno) == ARG_POINTER_REGNUM \
2989 || ((regno) == STACK_POINTER_REGNUM \
2990 && (GET_MODE_SIZE (mode) == 4 \
2991 || GET_MODE_SIZE (mode) == 8))) \
2994 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2995 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2998 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2999 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3001 #define REGNO_OK_FOR_INDEX_P(regno) 0
3002 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3003 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3005 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3006 and check its validity for a certain class.
3007 We have two alternate definitions for each of them.
3008 The usual definition accepts all pseudo regs; the other rejects them all.
3009 The symbol REG_OK_STRICT causes the latter definition to be used.
3011 Most source files want to accept pseudo regs in the hope that
3012 they will get allocated to the class that the insn wants them to be in.
3013 Some source files that are used after register allocation
3014 need to be strict. */
3016 #ifndef REG_OK_STRICT
3017 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3018 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3020 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3021 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3024 #define REG_OK_FOR_INDEX_P(X) 0
3027 /* Maximum number of registers that can appear in a valid memory address. */
3029 #define MAX_REGS_PER_ADDRESS 1
3031 /* A C compound statement with a conditional `goto LABEL;' executed
3032 if X (an RTX) is a legitimate memory address on the target
3033 machine for a memory operand of mode MODE. */
3036 #define GO_PRINTF(x) fprintf(stderr, (x))
3037 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3038 #define GO_DEBUG_RTX(x) debug_rtx(x)
3041 #define GO_PRINTF(x)
3042 #define GO_PRINTF2(x,y)
3043 #define GO_DEBUG_RTX(x)
3046 #ifdef REG_OK_STRICT
3047 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3049 if (mips_legitimate_address_p (MODE, X, 1)) \
3053 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3055 if (mips_legitimate_address_p (MODE, X, 0)) \
3060 /* Check for constness inline but use mips_legitimate_address_p
3061 to check whether a constant really is an address. */
3063 #define CONSTANT_ADDRESS_P(X) \
3064 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
3067 /* Nonzero if the constant value X is a legitimate general operand.
3068 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3070 At present, GAS doesn't understand li.[sd], so don't allow it
3071 to be generated at present. Also, the MIPS assembler does not
3072 grok li.d Infinity. */
3074 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3075 Note that the Irix 6 assembler problem may already be fixed.
3076 Note also that the GET_CODE (X) == CONST test catches the mips16
3077 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3078 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3079 ABI_64 to work together, we'll need to fix this. */
3080 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
3082 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3084 if (mips_legitimize_address (&(X), MODE)) \
3089 /* A C statement or compound statement with a conditional `goto
3090 LABEL;' executed if memory address X (an RTX) can have different
3091 meanings depending on the machine mode of the memory reference it
3094 Autoincrement and autodecrement addresses typically have
3095 mode-dependent effects because the amount of the increment or
3096 decrement is the size of the operand being addressed. Some
3097 machines have other mode-dependent addresses. Many RISC machines
3098 have no mode-dependent addresses.
3100 You may assume that ADDR is a valid address for the machine. */
3102 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3104 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3105 'the start of the function that this code is output in'. */
3107 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3108 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3109 asm_fprintf ((FILE), "%U%s", \
3110 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3112 asm_fprintf ((FILE), "%U%s", (NAME))
3114 /* The mips16 wants the constant pool to be after the function,
3115 because the PC relative load instructions use unsigned offsets. */
3117 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3119 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3120 mips_string_length = 0;
3122 /* Specify the machine mode that this machine uses
3123 for the index in the tablejump instruction.
3124 ??? Using HImode in mips16 mode can cause overflow. However, the
3125 overflow is no more likely than the overflow in a branch
3126 instruction. Large functions can currently break in both ways. */
3127 #define CASE_VECTOR_MODE \
3128 (TARGET_MIPS16 ? HImode : ptr_mode)
3130 /* Define as C expression which evaluates to nonzero if the tablejump
3131 instruction expects the table to contain offsets from the address of the
3133 Do not define this if the table should contain absolute addresses. */
3134 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3136 /* Define this as 1 if `char' should by default be signed; else as 0. */
3137 #ifndef DEFAULT_SIGNED_CHAR
3138 #define DEFAULT_SIGNED_CHAR 1
3141 /* Max number of bytes we can move from memory to memory
3142 in one reasonably fast instruction. */
3143 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3144 #define MAX_MOVE_MAX 8
3146 /* Define this macro as a C expression which is nonzero if
3147 accessing less than a word of memory (i.e. a `char' or a
3148 `short') is no faster than accessing a word of memory, i.e., if
3149 such access require more than one instruction or if there is no
3150 difference in cost between byte and (aligned) word loads.
3152 On RISC machines, it tends to generate better code to define
3153 this as 1, since it avoids making a QI or HI mode register. */
3154 #define SLOW_BYTE_ACCESS 1
3156 /* Define this to be nonzero if shift instructions ignore all but the low-order
3158 #define SHIFT_COUNT_TRUNCATED 1
3160 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3161 is done just by pretending it is already truncated. */
3162 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3163 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3166 /* Specify the machine mode that pointers have.
3167 After generation of rtl, the compiler makes no further distinction
3168 between pointers and any other objects of this machine mode. */
3171 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
3174 /* Give call MEMs SImode since it is the "most permissive" mode
3175 for both 32-bit and 64-bit targets. */
3177 #define FUNCTION_MODE SImode
3180 /* The cost of loading values from the constant pool. It should be
3181 larger than the cost of any constant we want to synthesise in-line. */
3183 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
3185 /* A C expression for the cost of moving data from a register in
3186 class FROM to one in class TO. The classes are expressed using
3187 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3188 the default; other values are interpreted relative to that.
3190 It is not required that the cost always equal 2 when FROM is the
3191 same as TO; on some machines it is expensive to move between
3192 registers if they are not general registers.
3194 If reload sees an insn consisting of a single `set' between two
3195 hard registers, and if `REGISTER_MOVE_COST' applied to their
3196 classes returns a value of 2, reload does not check to ensure
3197 that the constraints of the insn are met. Setting a cost of
3198 other than 2 will allow reload to verify that the constraints are
3199 met. You should do this if the `movM' pattern's constraints do
3200 not allow such copying. */
3202 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3203 mips_register_move_cost (MODE, FROM, TO)
3205 /* ??? Fix this to be right for the R8000. */
3206 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3207 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3208 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3210 /* Define if copies to/from condition code registers should be avoided.
3212 This is needed for the MIPS because reload_outcc is not complete;
3213 it needs to handle cases where the source is a general or another
3214 condition code register. */
3215 #define AVOID_CCMODE_COPIES
3217 /* A C expression for the cost of a branch instruction. A value of
3218 1 is the default; other values are interpreted relative to that. */
3220 /* ??? Fix this to be right for the R8000. */
3221 #define BRANCH_COST \
3223 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3226 /* If defined, modifies the length assigned to instruction INSN as a
3227 function of the context in which it is used. LENGTH is an lvalue
3228 that contains the initially computed length of the insn and should
3229 be updated with the correct length of the insn. */
3230 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3231 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3234 /* Optionally define this if you have added predicates to
3235 `MACHINE.c'. This macro is called within an initializer of an
3236 array of structures. The first field in the structure is the
3237 name of a predicate and the second field is an array of rtl
3238 codes. For each predicate, list all rtl codes that can be in
3239 expressions matched by the predicate. The list should have a
3240 trailing comma. Here is an example of two entries in the list
3241 for a typical RISC machine:
3243 #define PREDICATE_CODES \
3244 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3245 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3247 Defining this macro does not affect the generated code (however,
3248 incorrect definitions that omit an rtl code that may be matched
3249 by the predicate can cause the compiler to malfunction).
3250 Instead, it allows the table built by `genrecog' to be more
3251 compact and efficient, thus speeding up the compiler. The most
3252 important predicates to include in the list specified by this
3253 macro are thoses used in the most insn patterns. */
3255 #define PREDICATE_CODES \
3256 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3257 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
3258 {"const_arith_operand", { CONST, CONST_INT }}, \
3259 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
3260 {"arith32_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
3261 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3262 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
3263 {"small_int", { CONST_INT }}, \
3264 {"large_int", { CONST_INT }}, \
3265 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3266 {"const_float_1_operand", { CONST_DOUBLE }}, \
3267 {"simple_memory_operand", { MEM, SUBREG }}, \
3268 {"equality_op", { EQ, NE }}, \
3269 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3271 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3272 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3273 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
3274 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3275 SYMBOL_REF, LABEL_REF, SUBREG, \
3277 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3278 CONST_DOUBLE, CONST }}, \
3279 {"fcc_register_operand", { REG, SUBREG }}, \
3280 {"hilo_operand", { REG }}, \
3281 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
3283 /* A list of predicates that do special things with modes, and so
3284 should not elicit warnings for VOIDmode match_operand. */
3286 #define SPECIAL_MODE_PREDICATES \
3287 "pc_or_label_operand",
3289 /* Control the assembler format that we output. */
3291 /* Output at beginning of assembler file.
3292 If we are optimizing to use the global pointer, create a temporary
3293 file to hold all of the text stuff, and write it out to the end.
3294 This is needed because the MIPS assembler is evidently one pass,
3295 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3296 declaration when the code is processed, it generates a two
3297 instruction sequence. */
3299 #undef ASM_FILE_START
3300 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3302 /* Output to assembler file text saying following lines
3303 may contain character constants, extra white space, comments, etc. */
3306 #define ASM_APP_ON " #APP\n"
3309 /* Output to assembler file text saying following lines
3310 no longer contain unusual constructs. */
3313 #define ASM_APP_OFF " #NO_APP\n"
3316 /* How to refer to registers in assembler output.
3317 This sequence is indexed by compiler's hard-register-number (see above).
3319 In order to support the two different conventions for register names,
3320 we use the name of a table set up in mips.c, which is overwritten
3321 if -mrnames is used. */
3323 #define REGISTER_NAMES \
3325 &mips_reg_names[ 0][0], \
3326 &mips_reg_names[ 1][0], \
3327 &mips_reg_names[ 2][0], \
3328 &mips_reg_names[ 3][0], \
3329 &mips_reg_names[ 4][0], \
3330 &mips_reg_names[ 5][0], \
3331 &mips_reg_names[ 6][0], \
3332 &mips_reg_names[ 7][0], \
3333 &mips_reg_names[ 8][0], \
3334 &mips_reg_names[ 9][0], \
3335 &mips_reg_names[10][0], \
3336 &mips_reg_names[11][0], \
3337 &mips_reg_names[12][0], \
3338 &mips_reg_names[13][0], \
3339 &mips_reg_names[14][0], \
3340 &mips_reg_names[15][0], \
3341 &mips_reg_names[16][0], \
3342 &mips_reg_names[17][0], \
3343 &mips_reg_names[18][0], \
3344 &mips_reg_names[19][0], \
3345 &mips_reg_names[20][0], \
3346 &mips_reg_names[21][0], \
3347 &mips_reg_names[22][0], \
3348 &mips_reg_names[23][0], \
3349 &mips_reg_names[24][0], \
3350 &mips_reg_names[25][0], \
3351 &mips_reg_names[26][0], \
3352 &mips_reg_names[27][0], \
3353 &mips_reg_names[28][0], \
3354 &mips_reg_names[29][0], \
3355 &mips_reg_names[30][0], \
3356 &mips_reg_names[31][0], \
3357 &mips_reg_names[32][0], \
3358 &mips_reg_names[33][0], \
3359 &mips_reg_names[34][0], \
3360 &mips_reg_names[35][0], \
3361 &mips_reg_names[36][0], \
3362 &mips_reg_names[37][0], \
3363 &mips_reg_names[38][0], \
3364 &mips_reg_names[39][0], \
3365 &mips_reg_names[40][0], \
3366 &mips_reg_names[41][0], \
3367 &mips_reg_names[42][0], \
3368 &mips_reg_names[43][0], \
3369 &mips_reg_names[44][0], \
3370 &mips_reg_names[45][0], \
3371 &mips_reg_names[46][0], \
3372 &mips_reg_names[47][0], \
3373 &mips_reg_names[48][0], \
3374 &mips_reg_names[49][0], \
3375 &mips_reg_names[50][0], \
3376 &mips_reg_names[51][0], \
3377 &mips_reg_names[52][0], \
3378 &mips_reg_names[53][0], \
3379 &mips_reg_names[54][0], \
3380 &mips_reg_names[55][0], \
3381 &mips_reg_names[56][0], \
3382 &mips_reg_names[57][0], \
3383 &mips_reg_names[58][0], \
3384 &mips_reg_names[59][0], \
3385 &mips_reg_names[60][0], \
3386 &mips_reg_names[61][0], \
3387 &mips_reg_names[62][0], \
3388 &mips_reg_names[63][0], \
3389 &mips_reg_names[64][0], \
3390 &mips_reg_names[65][0], \
3391 &mips_reg_names[66][0], \
3392 &mips_reg_names[67][0], \
3393 &mips_reg_names[68][0], \
3394 &mips_reg_names[69][0], \
3395 &mips_reg_names[70][0], \
3396 &mips_reg_names[71][0], \
3397 &mips_reg_names[72][0], \
3398 &mips_reg_names[73][0], \
3399 &mips_reg_names[74][0], \
3400 &mips_reg_names[75][0], \
3401 &mips_reg_names[76][0], \
3402 &mips_reg_names[77][0], \
3403 &mips_reg_names[78][0], \
3404 &mips_reg_names[79][0], \
3405 &mips_reg_names[80][0], \
3406 &mips_reg_names[81][0], \
3407 &mips_reg_names[82][0], \
3408 &mips_reg_names[83][0], \
3409 &mips_reg_names[84][0], \
3410 &mips_reg_names[85][0], \
3411 &mips_reg_names[86][0], \
3412 &mips_reg_names[87][0], \
3413 &mips_reg_names[88][0], \
3414 &mips_reg_names[89][0], \
3415 &mips_reg_names[90][0], \
3416 &mips_reg_names[91][0], \
3417 &mips_reg_names[92][0], \
3418 &mips_reg_names[93][0], \
3419 &mips_reg_names[94][0], \
3420 &mips_reg_names[95][0], \
3421 &mips_reg_names[96][0], \
3422 &mips_reg_names[97][0], \
3423 &mips_reg_names[98][0], \
3424 &mips_reg_names[99][0], \
3425 &mips_reg_names[100][0], \
3426 &mips_reg_names[101][0], \
3427 &mips_reg_names[102][0], \
3428 &mips_reg_names[103][0], \
3429 &mips_reg_names[104][0], \
3430 &mips_reg_names[105][0], \
3431 &mips_reg_names[106][0], \
3432 &mips_reg_names[107][0], \
3433 &mips_reg_names[108][0], \
3434 &mips_reg_names[109][0], \
3435 &mips_reg_names[110][0], \
3436 &mips_reg_names[111][0], \
3437 &mips_reg_names[112][0], \
3438 &mips_reg_names[113][0], \
3439 &mips_reg_names[114][0], \
3440 &mips_reg_names[115][0], \
3441 &mips_reg_names[116][0], \
3442 &mips_reg_names[117][0], \
3443 &mips_reg_names[118][0], \
3444 &mips_reg_names[119][0], \
3445 &mips_reg_names[120][0], \
3446 &mips_reg_names[121][0], \
3447 &mips_reg_names[122][0], \
3448 &mips_reg_names[123][0], \
3449 &mips_reg_names[124][0], \
3450 &mips_reg_names[125][0], \
3451 &mips_reg_names[126][0], \
3452 &mips_reg_names[127][0], \
3453 &mips_reg_names[128][0], \
3454 &mips_reg_names[129][0], \
3455 &mips_reg_names[130][0], \
3456 &mips_reg_names[131][0], \
3457 &mips_reg_names[132][0], \
3458 &mips_reg_names[133][0], \
3459 &mips_reg_names[134][0], \
3460 &mips_reg_names[135][0], \
3461 &mips_reg_names[136][0], \
3462 &mips_reg_names[137][0], \
3463 &mips_reg_names[138][0], \
3464 &mips_reg_names[139][0], \
3465 &mips_reg_names[140][0], \
3466 &mips_reg_names[141][0], \
3467 &mips_reg_names[142][0], \
3468 &mips_reg_names[143][0], \
3469 &mips_reg_names[144][0], \
3470 &mips_reg_names[145][0], \
3471 &mips_reg_names[146][0], \
3472 &mips_reg_names[147][0], \
3473 &mips_reg_names[148][0], \
3474 &mips_reg_names[149][0], \
3475 &mips_reg_names[150][0], \
3476 &mips_reg_names[151][0], \
3477 &mips_reg_names[152][0], \
3478 &mips_reg_names[153][0], \
3479 &mips_reg_names[154][0], \
3480 &mips_reg_names[155][0], \
3481 &mips_reg_names[156][0], \
3482 &mips_reg_names[157][0], \
3483 &mips_reg_names[158][0], \
3484 &mips_reg_names[159][0], \
3485 &mips_reg_names[160][0], \
3486 &mips_reg_names[161][0], \
3487 &mips_reg_names[162][0], \
3488 &mips_reg_names[163][0], \
3489 &mips_reg_names[164][0], \
3490 &mips_reg_names[165][0], \
3491 &mips_reg_names[166][0], \
3492 &mips_reg_names[167][0], \
3493 &mips_reg_names[168][0], \
3494 &mips_reg_names[169][0], \
3495 &mips_reg_names[170][0], \
3496 &mips_reg_names[171][0], \
3497 &mips_reg_names[172][0], \
3498 &mips_reg_names[173][0], \
3499 &mips_reg_names[174][0], \
3500 &mips_reg_names[175][0] \
3503 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3504 So define this for it. */
3505 #define DEBUG_REGISTER_NAMES \
3507 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3508 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3509 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3510 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3511 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3512 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3513 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3514 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3515 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3516 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3517 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3518 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3519 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3520 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3521 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3522 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3523 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3524 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3525 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3526 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3527 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3528 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3531 /* If defined, a C initializer for an array of structures
3532 containing a name and a register number. This macro defines
3533 additional names for hard registers, thus allowing the `asm'
3534 option in declarations to refer to registers using alternate
3537 We define both names for the integer registers here. */
3539 #define ADDITIONAL_REGISTER_NAMES \
3541 { "$0", 0 + GP_REG_FIRST }, \
3542 { "$1", 1 + GP_REG_FIRST }, \
3543 { "$2", 2 + GP_REG_FIRST }, \
3544 { "$3", 3 + GP_REG_FIRST }, \
3545 { "$4", 4 + GP_REG_FIRST }, \
3546 { "$5", 5 + GP_REG_FIRST }, \
3547 { "$6", 6 + GP_REG_FIRST }, \
3548 { "$7", 7 + GP_REG_FIRST }, \
3549 { "$8", 8 + GP_REG_FIRST }, \
3550 { "$9", 9 + GP_REG_FIRST }, \
3551 { "$10", 10 + GP_REG_FIRST }, \
3552 { "$11", 11 + GP_REG_FIRST }, \
3553 { "$12", 12 + GP_REG_FIRST }, \
3554 { "$13", 13 + GP_REG_FIRST }, \
3555 { "$14", 14 + GP_REG_FIRST }, \
3556 { "$15", 15 + GP_REG_FIRST }, \
3557 { "$16", 16 + GP_REG_FIRST }, \
3558 { "$17", 17 + GP_REG_FIRST }, \
3559 { "$18", 18 + GP_REG_FIRST }, \
3560 { "$19", 19 + GP_REG_FIRST }, \
3561 { "$20", 20 + GP_REG_FIRST }, \
3562 { "$21", 21 + GP_REG_FIRST }, \
3563 { "$22", 22 + GP_REG_FIRST }, \
3564 { "$23", 23 + GP_REG_FIRST }, \
3565 { "$24", 24 + GP_REG_FIRST }, \
3566 { "$25", 25 + GP_REG_FIRST }, \
3567 { "$26", 26 + GP_REG_FIRST }, \
3568 { "$27", 27 + GP_REG_FIRST }, \
3569 { "$28", 28 + GP_REG_FIRST }, \
3570 { "$29", 29 + GP_REG_FIRST }, \
3571 { "$30", 30 + GP_REG_FIRST }, \
3572 { "$31", 31 + GP_REG_FIRST }, \
3573 { "$sp", 29 + GP_REG_FIRST }, \
3574 { "$fp", 30 + GP_REG_FIRST }, \
3575 { "at", 1 + GP_REG_FIRST }, \
3576 { "v0", 2 + GP_REG_FIRST }, \
3577 { "v1", 3 + GP_REG_FIRST }, \
3578 { "a0", 4 + GP_REG_FIRST }, \
3579 { "a1", 5 + GP_REG_FIRST }, \
3580 { "a2", 6 + GP_REG_FIRST }, \
3581 { "a3", 7 + GP_REG_FIRST }, \
3582 { "t0", 8 + GP_REG_FIRST }, \
3583 { "t1", 9 + GP_REG_FIRST }, \
3584 { "t2", 10 + GP_REG_FIRST }, \
3585 { "t3", 11 + GP_REG_FIRST }, \
3586 { "t4", 12 + GP_REG_FIRST }, \
3587 { "t5", 13 + GP_REG_FIRST }, \
3588 { "t6", 14 + GP_REG_FIRST }, \
3589 { "t7", 15 + GP_REG_FIRST }, \
3590 { "s0", 16 + GP_REG_FIRST }, \
3591 { "s1", 17 + GP_REG_FIRST }, \
3592 { "s2", 18 + GP_REG_FIRST }, \
3593 { "s3", 19 + GP_REG_FIRST }, \
3594 { "s4", 20 + GP_REG_FIRST }, \
3595 { "s5", 21 + GP_REG_FIRST }, \
3596 { "s6", 22 + GP_REG_FIRST }, \
3597 { "s7", 23 + GP_REG_FIRST }, \
3598 { "t8", 24 + GP_REG_FIRST }, \
3599 { "t9", 25 + GP_REG_FIRST }, \
3600 { "k0", 26 + GP_REG_FIRST }, \
3601 { "k1", 27 + GP_REG_FIRST }, \
3602 { "gp", 28 + GP_REG_FIRST }, \
3603 { "sp", 29 + GP_REG_FIRST }, \
3604 { "fp", 30 + GP_REG_FIRST }, \
3605 { "ra", 31 + GP_REG_FIRST }, \
3606 { "$sp", 29 + GP_REG_FIRST }, \
3607 { "$fp", 30 + GP_REG_FIRST } \
3608 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3611 /* This is meant to be redefined in the host dependent files. It is a
3612 set of alternative names and regnums for mips coprocessors. */
3614 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3616 /* A C compound statement to output to stdio stream STREAM the
3617 assembler syntax for an instruction operand X. X is an RTL
3620 CODE is a value that can be used to specify one of several ways
3621 of printing the operand. It is used when identical operands
3622 must be printed differently depending on the context. CODE
3623 comes from the `%' specification that was used to request
3624 printing of the operand. If the specification was just `%DIGIT'
3625 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3626 is the ASCII code for LTR.
3628 If X is a register, this macro should print the register's name.
3629 The names can be found in an array `reg_names' whose type is
3630 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3632 When the machine description has a specification `%PUNCT' (a `%'
3633 followed by a punctuation character), this macro is called with
3634 a null pointer for X and the punctuation character for CODE.
3636 See mips.c for the MIPS specific codes. */
3638 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3640 /* A C expression which evaluates to true if CODE is a valid
3641 punctuation character for use in the `PRINT_OPERAND' macro. If
3642 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3643 punctuation characters (except for the standard one, `%') are
3644 used in this way. */
3646 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3648 /* A C compound statement to output to stdio stream STREAM the
3649 assembler syntax for an instruction operand that is a memory
3650 reference whose address is ADDR. ADDR is an RTL expression. */
3652 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3655 /* A C statement, to be executed after all slot-filler instructions
3656 have been output. If necessary, call `dbr_sequence_length' to
3657 determine the number of slots filled in a sequence (zero if not
3658 currently outputting a sequence), to decide how many no-ops to
3659 output, or whatever.
3661 Don't define this macro if it has nothing to do, but it is
3662 helpful in reading assembly output if the extent of the delay
3663 sequence is made explicit (e.g. with white space).
3665 Note that output routines for instructions with delay slots must
3666 be prepared to deal with not being output as part of a sequence
3667 (i.e. when the scheduling pass is not run, or when no slot
3668 fillers could be found.) The variable `final_sequence' is null
3669 when not processing a sequence, otherwise it contains the
3670 `sequence' rtx being output. */
3672 #define DBR_OUTPUT_SEQEND(STREAM) \
3675 if (set_nomacro > 0 && --set_nomacro == 0) \
3676 fputs ("\t.set\tmacro\n", STREAM); \
3678 if (set_noreorder > 0 && --set_noreorder == 0) \
3679 fputs ("\t.set\treorder\n", STREAM); \
3681 fputs ("\n", STREAM); \
3686 /* How to tell the debugger about changes of source files. Note, the
3687 mips ECOFF format cannot deal with changes of files inside of
3688 functions, which means the output of parser generators like bison
3689 is generally not debuggable without using the -l switch. Lose,
3690 lose, lose. Silicon graphics seems to want all .file's hardwired
3693 #ifndef SET_FILE_NUMBER
3694 #define SET_FILE_NUMBER() ++num_source_filenames
3697 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3698 mips_output_filename (STREAM, NAME)
3700 /* This is defined so that it can be overridden in iris6.h. */
3701 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3704 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3705 output_quoted_string (STREAM, NAME); \
3706 fputs ("\n", STREAM); \
3710 /* This is how to output a note the debugger telling it the line number
3711 to which the following sequence of instructions corresponds.
3712 Silicon graphics puts a label after each .loc. */
3714 #ifndef LABEL_AFTER_LOC
3715 #define LABEL_AFTER_LOC(STREAM)
3718 #ifndef ASM_OUTPUT_SOURCE_LINE
3719 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3720 mips_output_lineno (STREAM, LINE)
3723 /* The MIPS implementation uses some labels for its own purpose. The
3724 following lists what labels are created, and are all formed by the
3725 pattern $L[a-z].*. The machine independent portion of GCC creates
3726 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3728 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3729 $Lb[0-9]+ Begin blocks for MIPS debug support
3730 $Lc[0-9]+ Label for use in s<xx> operation.
3731 $Le[0-9]+ End blocks for MIPS debug support */
3733 /* A C statement (sans semicolon) to output to the stdio stream
3734 STREAM any text necessary for declaring the name NAME of an
3735 initialized variable which is being defined. This macro must
3736 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3737 The argument DECL is the `VAR_DECL' tree node representing the
3740 If this macro is not defined, then the variable name is defined
3741 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3743 #undef ASM_DECLARE_OBJECT_NAME
3744 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3747 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3751 /* Globalizing directive for a label. */
3752 #define GLOBAL_ASM_OP "\t.globl\t"
3754 /* This says how to define a global common symbol. */
3756 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3758 /* If the target wants uninitialized const declarations in \
3759 .rdata then don't put them in .comm */ \
3760 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3761 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3762 && (DECL_INITIAL (DECL) == 0 \
3763 || DECL_INITIAL (DECL) == error_mark_node)) \
3765 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3766 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3768 readonly_data_section (); \
3769 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3770 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3774 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3779 /* This says how to define a local common symbol (ie, not visible to
3782 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3783 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3786 /* This says how to output an external. It would be possible not to
3787 output anything and let undefined symbol become external. However
3788 the assembler uses length information on externals to allocate in
3789 data/sdata bss/sbss, thereby saving exec time. */
3791 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3792 mips_output_external(STREAM,DECL,NAME)
3795 /* This is how to declare a function name. The actual work of
3796 emitting the label is moved to function_prologue, so that we can
3797 get the line number correctly emitted before the .ent directive,
3798 and after any .file directives. Define as empty so that the function
3799 is not declared before the .ent directive elsewhere. */
3801 #undef ASM_DECLARE_FUNCTION_NAME
3802 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3804 /* This is how to store into the string LABEL
3805 the symbol_ref name of an internal numbered label where
3806 PREFIX is the class of label and NUM is the number within the class.
3807 This is suitable for output with `assemble_name'. */
3809 #undef ASM_GENERATE_INTERNAL_LABEL
3810 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3811 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3813 /* This is how to output an element of a case-vector that is absolute. */
3815 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3816 fprintf (STREAM, "\t%s\t%sL%d\n", \
3817 ptr_mode == DImode ? ".dword" : ".word", \
3818 LOCAL_LABEL_PREFIX, \
3821 /* This is how to output an element of a case-vector that is relative.
3822 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3823 TARGET_EMBEDDED_PIC). */
3825 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3827 if (TARGET_MIPS16) \
3828 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3829 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3830 else if (TARGET_EMBEDDED_PIC) \
3831 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3832 ptr_mode == DImode ? ".dword" : ".word", \
3833 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3834 else if (TARGET_GPWORD) \
3835 fprintf (STREAM, "\t%s\t%sL%d\n", \
3836 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3837 LOCAL_LABEL_PREFIX, VALUE); \
3839 fprintf (STREAM, "\t%s\t%sL%d\n", \
3840 ptr_mode == DImode ? ".dword" : ".word", \
3841 LOCAL_LABEL_PREFIX, VALUE); \
3844 /* When generating embedded PIC or mips16 code we want to put the jump
3845 table in the .text section. In all other cases, we want to put the
3846 jump table in the .rdata section. Unfortunately, we can't use
3847 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3848 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3849 section if appropriate. */
3850 #undef ASM_OUTPUT_CASE_LABEL
3851 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3853 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3854 function_section (current_function_decl); \
3855 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3858 /* This is how to output an assembler line
3859 that says to advance the location counter
3860 to a multiple of 2**LOG bytes. */
3862 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3863 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3865 /* This is how to output an assembler line to advance the location
3866 counter by SIZE bytes. */
3868 #undef ASM_OUTPUT_SKIP
3869 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3870 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3872 /* This is how to output a string. */
3873 #undef ASM_OUTPUT_ASCII
3874 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3875 mips_output_ascii (STREAM, STRING, LEN)
3877 /* Output #ident as a in the read-only data section. */
3878 #undef ASM_OUTPUT_IDENT
3879 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3881 const char *p = STRING; \
3882 int size = strlen (p) + 1; \
3883 readonly_data_section (); \
3884 assemble_string (p, size); \
3887 /* Default to -G 8 */
3888 #ifndef MIPS_DEFAULT_GVALUE
3889 #define MIPS_DEFAULT_GVALUE 8
3892 /* Define the strings to put out for each section in the object file. */
3893 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3894 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3895 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3897 #undef READONLY_DATA_SECTION_ASM_OP
3898 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3900 #define SMALL_DATA_SECTION sdata_section
3902 /* What other sections we support other than the normal .data/.text. */
3904 #undef EXTRA_SECTIONS
3905 #define EXTRA_SECTIONS in_sdata
3907 /* Define the additional functions to select our additional sections. */
3909 /* on the MIPS it is not a good idea to put constants in the text
3910 section, since this defeats the sdata/data mechanism. This is
3911 especially true when -O is used. In this case an effort is made to
3912 address with faster (gp) register relative addressing, which can
3913 only get at sdata and sbss items (there is no stext !!) However,
3914 if the constant is too large for sdata, and it's readonly, it
3915 will go into the .rdata section. */
3917 #undef EXTRA_SECTION_FUNCTIONS
3918 #define EXTRA_SECTION_FUNCTIONS \
3922 if (in_section != in_sdata) \
3924 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3925 in_section = in_sdata; \
3929 /* Given a decl node or constant node, choose the section to output it in
3930 and select that section. */
3932 #undef TARGET_ASM_SELECT_SECTION
3933 #define TARGET_ASM_SELECT_SECTION mips_select_section
3935 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3938 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3939 TARGET_64BIT ? "dsubu" : "subu", \
3940 reg_names[STACK_POINTER_REGNUM], \
3941 reg_names[STACK_POINTER_REGNUM], \
3942 TARGET_64BIT ? "sd" : "sw", \
3944 reg_names[STACK_POINTER_REGNUM]); \
3948 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3951 if (! set_noreorder) \
3952 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3954 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3955 TARGET_64BIT ? "ld" : "lw", \
3957 reg_names[STACK_POINTER_REGNUM], \
3958 TARGET_64BIT ? "daddu" : "addu", \
3959 reg_names[STACK_POINTER_REGNUM], \
3960 reg_names[STACK_POINTER_REGNUM]); \
3962 if (! set_noreorder) \
3963 fprintf (STREAM, "\t.set\treorder\n"); \
3967 /* How to start an assembler comment.
3968 The leading space is important (the mips native assembler requires it). */
3969 #ifndef ASM_COMMENT_START
3970 #define ASM_COMMENT_START " #"
3974 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3975 and mips-tdump.c to print them out.
3977 These must match the corresponding definitions in gdb/mipsread.c.
3978 Unfortunately, gcc and gdb do not currently share any directories. */
3980 #define CODE_MASK 0x8F300
3981 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3982 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3983 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3986 /* Default definitions for size_t and ptrdiff_t. We must override the
3987 definitions from ../svr4.h on mips-*-linux-gnu. */
3990 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3993 #ifndef PTRDIFF_TYPE
3994 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3997 /* See mips_expand_prologue's use of loadgp for when this should be
4000 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4001 && mips_abi != ABI_32 \
4002 && mips_abi != ABI_O64)
4004 /* We need to use a special set of functions to handle hard floating
4005 point code in mips16 mode. */
4007 #ifndef INIT_SUBTARGET_OPTABS
4008 #define INIT_SUBTARGET_OPTABS
4011 #define INIT_TARGET_OPTABS \
4014 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4015 INIT_SUBTARGET_OPTABS; \
4018 add_optab->handlers[(int) SFmode].libfunc = \
4019 init_one_libfunc ("__mips16_addsf3"); \
4020 sub_optab->handlers[(int) SFmode].libfunc = \
4021 init_one_libfunc ("__mips16_subsf3"); \
4022 smul_optab->handlers[(int) SFmode].libfunc = \
4023 init_one_libfunc ("__mips16_mulsf3"); \
4024 sdiv_optab->handlers[(int) SFmode].libfunc = \
4025 init_one_libfunc ("__mips16_divsf3"); \
4027 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4028 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4029 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4030 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4031 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4032 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4034 floatsisf_libfunc = \
4035 init_one_libfunc ("__mips16_floatsisf"); \
4037 init_one_libfunc ("__mips16_fixsfsi"); \
4039 if (TARGET_DOUBLE_FLOAT) \
4041 add_optab->handlers[(int) DFmode].libfunc = \
4042 init_one_libfunc ("__mips16_adddf3"); \
4043 sub_optab->handlers[(int) DFmode].libfunc = \
4044 init_one_libfunc ("__mips16_subdf3"); \
4045 smul_optab->handlers[(int) DFmode].libfunc = \
4046 init_one_libfunc ("__mips16_muldf3"); \
4047 sdiv_optab->handlers[(int) DFmode].libfunc = \
4048 init_one_libfunc ("__mips16_divdf3"); \
4050 extendsfdf2_libfunc = \
4051 init_one_libfunc ("__mips16_extendsfdf2"); \
4052 truncdfsf2_libfunc = \
4053 init_one_libfunc ("__mips16_truncdfsf2"); \
4056 init_one_libfunc ("__mips16_eqdf2"); \
4058 init_one_libfunc ("__mips16_nedf2"); \
4060 init_one_libfunc ("__mips16_gtdf2"); \
4062 init_one_libfunc ("__mips16_gedf2"); \
4064 init_one_libfunc ("__mips16_ltdf2"); \
4066 init_one_libfunc ("__mips16_ledf2"); \
4068 floatsidf_libfunc = \
4069 init_one_libfunc ("__mips16_floatsidf"); \
4071 init_one_libfunc ("__mips16_fixdfsi"); \
4077 #define DFMODE_NAN \
4078 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4079 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4080 #define SFMODE_NAN \
4081 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4082 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4084 /* Generate calls to memcpy, etc., not bcopy, etc. */
4085 #define TARGET_MEM_FUNCTIONS
4088 /* Since the bits of the _init and _fini function is spread across
4089 many object files, each potentially with its own GP, we must assume
4090 we need to load our GP. We don't preserve $gp or $ra, since each
4091 init/fini chunk is supposed to initialize $gp, and crti/crtn
4092 already take care of preserving $ra and, when appropriate, $gp. */
4093 #if _MIPS_SIM == _MIPS_SIM_ABI32
4094 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4095 asm (SECTION_OP "\n\
4101 jal " USER_LABEL_PREFIX #FUNC "\n\
4102 " TEXT_SECTION_ASM_OP);
4103 #endif /* Switch to #elif when we're no longer limited by K&R C. */
4104 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
4105 || (defined _ABI64 && _MIPS_SIM == _ABI64)
4106 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
4107 asm (SECTION_OP "\n\
4112 .cpsetup $31, $2, 1b\n\
4113 jal " USER_LABEL_PREFIX #FUNC "\n\
4114 " TEXT_SECTION_ASM_OP);