1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_arch; /* which cpu to codegen for */
137 extern enum processor_type mips_tune; /* which cpu to schedule for */
138 extern enum processor_type mips_cpu; /* historical codegen/sched */
139 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
140 extern int mips_isa; /* architectural level */
141 extern int mips16; /* whether generating mips16 code */
142 extern int mips16_hard_float; /* mips16 without -msoft-float */
143 extern int mips_entry; /* generate entry/exit for mips16 */
144 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
145 extern const char *mips_arch_string; /* for -march=<xxx> */
146 extern const char *mips_tune_string; /* for -mtune=<xxx> */
147 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
148 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
149 extern const char *mips_entry_string; /* for -mentry */
150 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
151 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
152 extern int mips_split_addresses; /* perform high/lo_sum support */
153 extern int dslots_load_total; /* total # load related delay slots */
154 extern int dslots_load_filled; /* # filled load delay slots */
155 extern int dslots_jump_total; /* total # jump related delay slots */
156 extern int dslots_jump_filled; /* # filled jump delay slots */
157 extern int dslots_number_nops; /* # of nops needed by previous insn */
158 extern int num_refs[3]; /* # 1/2/3 word references */
159 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
160 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
161 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
162 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
163 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
164 extern int mips_string_length; /* length of strings for mips16 */
165 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
167 /* Functions to change what output section we are using. */
168 extern void rdata_section PARAMS ((void));
169 extern void sdata_section PARAMS ((void));
170 extern void sbss_section PARAMS ((void));
172 /* Stubs for half-pic support if not OSF/1 reference platform. */
175 #define HALF_PIC_P() 0
176 #define HALF_PIC_NUMBER_PTRS 0
177 #define HALF_PIC_NUMBER_REFS 0
178 #define HALF_PIC_ENCODE(DECL)
179 #define HALF_PIC_DECLARE(NAME)
180 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
181 #define HALF_PIC_ADDRESS_P(X) 0
182 #define HALF_PIC_PTR(X) X
183 #define HALF_PIC_FINISH(STREAM)
186 /* Macros to silence warnings about numbers being signed in traditional
187 C and unsigned in ISO C when compiled on 32-bit hosts. */
189 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
190 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
191 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
194 /* Run-time compilation parameters selecting different hardware subsets. */
196 /* Macros used in the machine description to test the flags. */
198 /* Bits for real switches */
199 #define MASK_INT64 0x00000001 /* ints are 64 bits */
200 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
201 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
202 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
203 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
204 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
205 #define MASK_STATS 0x00000040 /* print statistics to stderr */
206 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
207 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
208 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
209 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
210 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
211 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
212 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
213 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
214 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
215 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
216 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
217 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
218 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
219 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
220 #define MASK_NO_CHECK_ZERO_DIV \
221 0x00200000 /* divide by zero checking */
222 #define MASK_CHECK_RANGE_DIV \
223 0x00400000 /* divide result range checking */
224 #define MASK_UNINIT_CONST_IN_RODATA \
225 0x00800000 /* Store uninitialized
228 /* Debug switches, not documented */
229 #define MASK_DEBUG 0 /* unused */
230 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
231 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
232 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
233 #define MASK_DEBUG_D 0 /* don't do define_split's */
234 #define MASK_DEBUG_E 0 /* function_arg debug */
235 #define MASK_DEBUG_F 0 /* ??? */
236 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
237 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
238 #define MASK_DEBUG_I 0 /* unused */
240 /* Dummy switches used only in specs */
241 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
243 /* r4000 64 bit sizes */
244 #define TARGET_INT64 (target_flags & MASK_INT64)
245 #define TARGET_LONG64 (target_flags & MASK_LONG64)
246 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
247 #define TARGET_64BIT (target_flags & MASK_64BIT)
249 /* Mips vs. GNU linker */
250 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
252 /* Mips vs. GNU assembler */
253 #define TARGET_GAS (target_flags & MASK_GAS)
254 #define TARGET_MIPS_AS (!TARGET_GAS)
257 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
258 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
259 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
260 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
261 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
262 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
263 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
264 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
265 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
266 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
268 /* Reg. Naming in .s ($21 vs. $a0) */
269 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
271 /* Optimize for Sdata/Sbss */
272 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
274 /* print program statistics */
275 #define TARGET_STATS (target_flags & MASK_STATS)
277 /* call memcpy instead of inline code */
278 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
280 /* .abicalls, etc from Pyramid V.4 */
281 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
283 /* OSF pic references to externs */
284 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
286 /* software floating point */
287 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
288 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
290 /* always call through a register */
291 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
293 /* generate embedded PIC code;
295 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
297 /* for embedded systems, optimize for
298 reduced RAM space instead of for
300 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
302 /* always store uninitialized const
303 variables in rodata, requires
304 TARGET_EMBEDDED_DATA. */
305 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
307 /* generate big endian code. */
308 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
310 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
311 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
313 #define TARGET_MAD (target_flags & MASK_MAD)
315 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
317 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
318 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
320 /* This is true if we must enable the assembly language file switching
323 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
325 /* We must disable the function end stabs when doing the file switching trick,
326 because the Lscope stabs end up in the wrong place, making it impossible
327 to debug the resulting code. */
328 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
330 /* Generate mips16 code */
331 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
333 /* Architecture target defines. */
334 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
335 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
336 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
337 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
339 /* Scheduling target defines. */
340 #define TUNE_MIPS3000 (mips_cpu == PROCESSOR_R3000)
341 #define TUNE_MIPS3900 (mips_cpu == PROCESSOR_R3900)
342 #define TUNE_MIPS4000 (mips_cpu == PROCESSOR_R4000)
343 #define TUNE_MIPS5000 (mips_cpu == PROCESSOR_R5000)
344 #define TUNE_MIPS6000 (mips_cpu == PROCESSOR_R6000)
346 /* Macro to define tables used to set the flags.
347 This is a list in braces of pairs in braces,
348 each pair being { "NAME", VALUE }
349 where VALUE is the bits to set or minus the bits to clear.
350 An empty string NAME is used to identify the default VALUE. */
352 #define TARGET_SWITCHES \
355 N_("No default crt0.o") }, \
356 {"int64", MASK_INT64 | MASK_LONG64, \
357 N_("Use 64-bit int type")}, \
358 {"long64", MASK_LONG64, \
359 N_("Use 64-bit long type")}, \
360 {"long32", -(MASK_LONG64 | MASK_INT64), \
361 N_("Use 32-bit long type")}, \
362 {"split-addresses", MASK_SPLIT_ADDR, \
363 N_("Optimize lui/addiu address loads")}, \
364 {"no-split-addresses", -MASK_SPLIT_ADDR, \
365 N_("Don't optimize lui/addiu address loads")}, \
366 {"mips-as", -MASK_GAS, \
367 N_("Use MIPS as")}, \
370 {"rnames", MASK_NAME_REGS, \
371 N_("Use symbolic register names")}, \
372 {"no-rnames", -MASK_NAME_REGS, \
373 N_("Don't use symbolic register names")}, \
374 {"gpOPT", MASK_GPOPT, \
375 N_("Use GP relative sdata/sbss sections")}, \
376 {"gpopt", MASK_GPOPT, \
377 N_("Use GP relative sdata/sbss sections")}, \
378 {"no-gpOPT", -MASK_GPOPT, \
379 N_("Don't use GP relative sdata/sbss sections")}, \
380 {"no-gpopt", -MASK_GPOPT, \
381 N_("Don't use GP relative sdata/sbss sections")}, \
382 {"stats", MASK_STATS, \
383 N_("Output compiler statistics")}, \
384 {"no-stats", -MASK_STATS, \
385 N_("Don't output compiler statistics")}, \
386 {"memcpy", MASK_MEMCPY, \
387 N_("Don't optimize block moves")}, \
388 {"no-memcpy", -MASK_MEMCPY, \
389 N_("Optimize block moves")}, \
390 {"mips-tfile", MASK_MIPS_TFILE, \
391 N_("Use mips-tfile asm postpass")}, \
392 {"no-mips-tfile", -MASK_MIPS_TFILE, \
393 N_("Don't use mips-tfile asm postpass")}, \
394 {"soft-float", MASK_SOFT_FLOAT, \
395 N_("Use software floating point")}, \
396 {"hard-float", -MASK_SOFT_FLOAT, \
397 N_("Use hardware floating point")}, \
398 {"fp64", MASK_FLOAT64, \
399 N_("Use 64-bit FP registers")}, \
400 {"fp32", -MASK_FLOAT64, \
401 N_("Use 32-bit FP registers")}, \
402 {"gp64", MASK_64BIT, \
403 N_("Use 64-bit general registers")}, \
404 {"gp32", -MASK_64BIT, \
405 N_("Use 32-bit general registers")}, \
406 {"abicalls", MASK_ABICALLS, \
407 N_("Use Irix PIC")}, \
408 {"no-abicalls", -MASK_ABICALLS, \
409 N_("Don't use Irix PIC")}, \
410 {"half-pic", MASK_HALF_PIC, \
411 N_("Use OSF PIC")}, \
412 {"no-half-pic", -MASK_HALF_PIC, \
413 N_("Don't use OSF PIC")}, \
414 {"long-calls", MASK_LONG_CALLS, \
415 N_("Use indirect calls")}, \
416 {"no-long-calls", -MASK_LONG_CALLS, \
417 N_("Don't use indirect calls")}, \
418 {"embedded-pic", MASK_EMBEDDED_PIC, \
419 N_("Use embedded PIC")}, \
420 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
421 N_("Don't use embedded PIC")}, \
422 {"embedded-data", MASK_EMBEDDED_DATA, \
423 N_("Use ROM instead of RAM")}, \
424 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
425 N_("Don't use ROM instead of RAM")}, \
426 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
427 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
428 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
429 N_("Don't put uninitialized constants in ROM")}, \
430 {"eb", MASK_BIG_ENDIAN, \
431 N_("Use big-endian byte order")}, \
432 {"el", -MASK_BIG_ENDIAN, \
433 N_("Use little-endian byte order")}, \
434 {"single-float", MASK_SINGLE_FLOAT, \
435 N_("Use single (32-bit) FP only")}, \
436 {"double-float", -MASK_SINGLE_FLOAT, \
437 N_("Don't use single (32-bit) FP only")}, \
439 N_("Use multiply accumulate")}, \
440 {"no-mad", -MASK_MAD, \
441 N_("Don't use multiply accumulate")}, \
442 {"fix4300", MASK_4300_MUL_FIX, \
443 N_("Work around early 4300 hardware bug")}, \
444 {"no-fix4300", -MASK_4300_MUL_FIX, \
445 N_("Don't work around early 4300 hardware bug")}, \
447 N_("Optimize for 3900")}, \
449 N_("Optimize for 4650")}, \
450 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
451 N_("Trap on integer divide by zero")}, \
452 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
453 N_("Don't trap on integer divide by zero")}, \
454 {"check-range-division",MASK_CHECK_RANGE_DIV, \
455 N_("Trap on integer divide overflow")}, \
456 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
457 N_("Don't trap on integer divide overflow")}, \
458 {"debug", MASK_DEBUG, \
460 {"debuga", MASK_DEBUG_A, \
462 {"debugb", MASK_DEBUG_B, \
464 {"debugc", MASK_DEBUG_C, \
466 {"debugd", MASK_DEBUG_D, \
468 {"debuge", MASK_DEBUG_E, \
470 {"debugf", MASK_DEBUG_F, \
472 {"debugg", MASK_DEBUG_G, \
474 {"debugh", MASK_DEBUG_H, \
476 {"debugi", MASK_DEBUG_I, \
478 {"", (TARGET_DEFAULT \
479 | TARGET_CPU_DEFAULT \
480 | TARGET_ENDIAN_DEFAULT), \
484 /* Default target_flags if no switches are specified */
486 #ifndef TARGET_DEFAULT
487 #define TARGET_DEFAULT 0
490 #ifndef TARGET_CPU_DEFAULT
491 #define TARGET_CPU_DEFAULT 0
494 #ifndef TARGET_ENDIAN_DEFAULT
496 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
498 #define TARGET_ENDIAN_DEFAULT 0
502 #ifndef MIPS_ISA_DEFAULT
503 #define MIPS_ISA_DEFAULT 1
508 /* Make this compile time constant for libgcc2 */
510 #define TARGET_64BIT 1
512 #define TARGET_64BIT 0
514 #endif /* IN_LIBGCC2 */
516 #ifndef MULTILIB_ENDIAN_DEFAULT
517 #if TARGET_ENDIAN_DEFAULT == 0
518 #define MULTILIB_ENDIAN_DEFAULT "EL"
520 #define MULTILIB_ENDIAN_DEFAULT "EB"
524 #ifndef MULTILIB_ISA_DEFAULT
525 # if MIPS_ISA_DEFAULT == 1
526 # define MULTILIB_ISA_DEFAULT "mips1"
528 # if MIPS_ISA_DEFAULT == 2
529 # define MULTILIB_ISA_DEFAULT "mips2"
531 # if MIPS_ISA_DEFAULT == 3
532 # define MULTILIB_ISA_DEFAULT "mips3"
534 # if MIPS_ISA_DEFAULT == 4
535 # define MULTILIB_ISA_DEFAULT "mips4"
537 # define MULTILIB_ISA_DEFAULT "mips1"
544 #ifndef MULTILIB_DEFAULTS
545 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
548 /* We must pass -EL to the linker by default for little endian embedded
549 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
550 linker will default to using big-endian output files. The OUTPUT_FORMAT
551 line must be in the linker script, otherwise -EB/-EL will not work. */
554 #if TARGET_ENDIAN_DEFAULT == 0
555 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
557 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
561 /* This macro is similar to `TARGET_SWITCHES' but defines names of
562 command options that have values. Its definition is an
563 initializer with a subgrouping for each command option.
565 Each subgrouping contains a string constant, that defines the
566 fixed part of the option name, and the address of a variable.
567 The variable, type `char *', is set to the variable part of the
568 given option if the fixed part matches. The actual option name
569 is made by appending `-m' to the specified name.
571 Here is an example which defines `-mshort-data-NUMBER'. If the
572 given option is `-mshort-data-512', the variable `m88k_short_data'
573 will be set to the string `"512"'.
575 extern char *m88k_short_data;
576 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
578 #define TARGET_OPTIONS \
580 SUBTARGET_TARGET_OPTIONS \
581 { "cpu=", &mips_cpu_string, \
582 N_("Specify CPU for scheduling purposes")}, \
583 { "tune=", &mips_tune_string, \
584 N_("Specify CPU for scheduling purposes")}, \
585 { "arch=", &mips_arch_string, \
586 N_("Specify CPU for code generation purposes")}, \
587 { "ips", &mips_isa_string, \
588 N_("Specify a Standard MIPS ISA")}, \
589 { "entry", &mips_entry_string, \
590 N_("Use mips16 entry/exit psuedo ops")}, \
591 { "no-mips16", &mips_no_mips16_string, \
592 N_("Don't use MIPS16 instructions")}, \
593 { "explicit-type-size", &mips_explicit_type_size_string, \
597 /* This is meant to be redefined in the host dependent files. */
598 #define SUBTARGET_TARGET_OPTIONS
600 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
602 /* Generate three-operand multiply instructions for both SImode and DImode. */
603 #define GENERATE_MULT3 (TARGET_MIPS3900 \
606 /* Macros to decide whether certain features are available or not,
607 depending on the instruction set architecture level. */
609 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
610 #define HAVE_SQRT_P() (mips_isa != 1)
612 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
613 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
616 /* ISA has branch likely instructions (eg. mips2). */
617 /* Disable branchlikely for tx39 until compare rewrite. They haven't
618 been generated up to this point. */
619 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
620 /* || TARGET_MIPS3900 */)
622 /* ISA has the conditional move instructions introduced in mips4. */
623 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
626 /* ISA has just the integer condition move instructions (movn,movz) */
627 #define ISA_HAS_INT_CONDMOVE 0
631 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
632 branch on CC, and move (both FP and non-FP) on CC. */
633 #define ISA_HAS_8CC (mips_isa == 4 \
637 /* This is a catch all for the other new mips4 instructions: indexed load and
638 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
639 and the FP recip and recip sqrt instructions */
640 #define ISA_HAS_FP4 (mips_isa == 4 \
643 /* ISA has conditional trap instructions. */
644 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
647 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
648 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
649 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
650 target_flags, and -mgp64 sets MASK_64BIT.
652 Setting MASK_64BIT in target_flags will cause gcc to assume that
653 registers are 64 bits wide. int, long and void * will be 32 bit;
654 this may be changed with -mint64 or -mlong64.
656 The gen* programs link code that refers to MASK_64BIT. They don't
657 actually use the information in target_flags; they just refer to
660 /* Switch Recognition by gcc.c. Add -G xx support */
662 #ifdef SWITCH_TAKES_ARG
663 #undef SWITCH_TAKES_ARG
666 #define SWITCH_TAKES_ARG(CHAR) \
667 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
669 /* Sometimes certain combinations of command options do not make sense
670 on a particular target machine. You can define a macro
671 `OVERRIDE_OPTIONS' to take account of this. This macro, if
672 defined, is executed once just after all the command options have
675 On the MIPS, it is used to handle -G. We also use it to set up all
676 of the tables referenced in the other macros. */
678 #define OVERRIDE_OPTIONS override_options ()
680 /* Zero or more C statements that may conditionally modify two
681 variables `fixed_regs' and `call_used_regs' (both of type `char
682 []') after they have been initialized from the two preceding
685 This is necessary in case the fixed or call-clobbered registers
686 depend on target flags.
688 You need not define this macro if it has no work to do.
690 If the usage of an entire class of registers depends on the target
691 flags, you may indicate this to GCC by using this macro to modify
692 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
693 the classes which should not be used by GCC. Also define the macro
694 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
695 letter for a class that shouldn't be used.
697 (However, if this class is not included in `GENERAL_REGS' and all
698 of the insn patterns whose constraints permit this class are
699 controlled by target switches, then GCC will automatically avoid
700 using these registers when the target switches are opposed to
703 #define CONDITIONAL_REGISTER_USAGE \
706 if (!TARGET_HARD_FLOAT) \
710 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
711 fixed_regs[regno] = call_used_regs[regno] = 1; \
712 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
713 fixed_regs[regno] = call_used_regs[regno] = 1; \
715 else if (! ISA_HAS_8CC) \
719 /* We only have a single condition code register. We \
720 implement this by hiding all the condition code registers, \
721 and generating RTL that refers directly to ST_REG_FIRST. */ \
722 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
723 fixed_regs[regno] = call_used_regs[regno] = 1; \
725 /* In mips16 mode, we permit the $t temporary registers to be used \
726 for reload. We prohibit the unused $s registers, since they \
727 are caller saved, and saving them via a mips16 register would \
728 probably waste more time than just reloading the value. */ \
731 fixed_regs[18] = call_used_regs[18] = 1; \
732 fixed_regs[19] = call_used_regs[19] = 1; \
733 fixed_regs[20] = call_used_regs[20] = 1; \
734 fixed_regs[21] = call_used_regs[21] = 1; \
735 fixed_regs[22] = call_used_regs[22] = 1; \
736 fixed_regs[23] = call_used_regs[23] = 1; \
737 fixed_regs[26] = call_used_regs[26] = 1; \
738 fixed_regs[27] = call_used_regs[27] = 1; \
739 fixed_regs[30] = call_used_regs[30] = 1; \
741 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
745 /* This is meant to be redefined in the host dependent files. */
746 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
748 /* Show we can debug even without a frame pointer. */
749 #define CAN_DEBUG_WITHOUT_FP
751 /* Complain about missing specs and predefines that should be defined in each
752 of the target tm files to override the defaults. This is mostly a place-
753 holder until I can get each of the files updated [mm]. */
755 #if defined(OSF_OS) \
756 || defined(DECSTATION) \
757 || defined(SGI_TARGET) \
758 || defined(MIPS_NEWS) \
759 || defined(MIPS_SYSV) \
760 || defined(MIPS_SVR4) \
761 || defined(MIPS_BSD43)
763 #ifndef CPP_PREDEFINES
764 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
768 #error "Define LIB_SPEC in the appropriate tm.h file"
771 #ifndef STARTFILE_SPEC
772 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
776 #error "Define MACHINE_TYPE in the appropriate tm.h file"
780 /* Tell collect what flags to pass to nm. */
782 #define NM_FLAGS "-Bn"
786 /* Names to predefine in the preprocessor for this target machine. */
788 #ifndef CPP_PREDEFINES
789 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
790 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
791 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
794 /* Assembler specs. */
796 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
799 #define MIPS_AS_ASM_SPEC "\
800 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
801 %{pipe: %e-pipe is not supported.} \
802 %{K} %(subtarget_mips_as_asm_spec)"
804 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
805 rather than gas. It may be overridden by subtargets. */
807 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
808 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
811 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
814 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
816 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
817 GAS_ASM_SPEC as the default, depending upon the value of
820 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
823 #define TARGET_ASM_SPEC "\
824 %{mmips-as: %(mips_as_asm_spec)} \
825 %{!mmips-as: %(gas_asm_spec)}"
829 #define TARGET_ASM_SPEC "\
830 %{!mgas: %(mips_as_asm_spec)} \
831 %{mgas: %(gas_asm_spec)}"
835 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
836 to the assembler. It may be overridden by subtargets. */
837 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
838 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
840 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
843 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
844 the assembler. It may be overridden by subtargets. */
845 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
846 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
847 %{g} %{g0} %{g1} %{g2} %{g3} \
848 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
849 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
850 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
851 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
854 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
855 overridden by subtargets. */
857 #ifndef SUBTARGET_ASM_SPEC
858 #define SUBTARGET_ASM_SPEC ""
861 /* ASM_SPEC is the set of arguments to pass to the assembler. */
864 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
865 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
866 %(subtarget_asm_optimizing_spec) \
867 %(subtarget_asm_debugging_spec) \
870 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
872 %(subtarget_asm_spec)"
874 /* Specify to run a post-processor, mips-tfile after the assembler
875 has run to stuff the mips debug information into the object file.
876 This is needed because the $#!%^ MIPS assembler provides no way
877 of specifying such information in the assembly file. If we are
878 cross compiling, disable mips-tfile unless the user specifies
881 #ifndef ASM_FINAL_SPEC
882 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
884 #define ASM_FINAL_SPEC "\
885 %{mmips-as: %{!mno-mips-tfile: \
886 \n mips-tfile %{v*: -v} \
888 %{!K: %{save-temps: -I %b.o~}} \
889 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
890 %{.s:%i} %{!.s:%g.s}}}"
894 #define ASM_FINAL_SPEC "\
895 %{!mgas: %{!mno-mips-tfile: \
896 \n mips-tfile %{v*: -v} \
898 %{!K: %{save-temps: -I %b.o~}} \
899 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
900 %{.s:%i} %{!.s:%g.s}}}"
903 #endif /* ASM_FINAL_SPEC */
905 /* Redefinition of libraries used. Mips doesn't support normal
906 UNIX style profiling via calling _mcount. It does offer
907 profiling that samples the PC, so do what we can... */
910 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
913 /* Extra switches sometimes passed to the linker. */
914 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
915 will interpret it as a -b option. */
920 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
921 %{bestGnum} %{shared} %{non_shared}"
922 #endif /* LINK_SPEC defined */
924 /* Specs for the compiler proper */
926 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
927 overridden by subtargets. */
928 #ifndef SUBTARGET_CC1_SPEC
929 #define SUBTARGET_CC1_SPEC ""
932 /* Deal with historic options. */
934 #define CC1_CPU_SPEC "\
936 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
937 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
938 %{m4650:-march=r4650 -mmad -msingle-float \
939 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
942 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
946 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
947 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
948 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
949 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
950 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
951 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
952 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
953 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
954 %{pic-none: -mno-half-pic} \
955 %{pic-lib: -mhalf-pic} \
956 %{pic-extern: -mhalf-pic} \
957 %{pic-calls: -mhalf-pic} \
959 %(subtarget_cc1_spec) \
963 /* Preprocessor specs. */
965 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
966 be overridden by subtargets. */
968 #ifndef SUBTARGET_CPP_SIZE_SPEC
969 #define SUBTARGET_CPP_SIZE_SPEC "\
970 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
971 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
974 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
975 overridden by subtargets. */
976 #ifndef SUBTARGET_CPP_SPEC
977 #define SUBTARGET_CPP_SPEC ""
980 /* If we're using 64bit longs, then we have to define __LONG_MAX__
981 correctly. Similarly for 64bit ints and __INT_MAX__. */
982 #ifndef LONG_MAX_SPEC
983 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
984 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
986 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
990 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
991 of the source file extension. */
992 #define CPLUSPLUS_CPP_SPEC "\
993 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
996 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1000 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1001 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1002 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1003 %(subtarget_cpp_size_spec) \
1004 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1005 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1006 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1007 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1008 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1009 %{msoft-float:-D__mips_soft_float} \
1010 %{mabi=eabi:-D__mips_eabi} \
1011 %{mips16:%{!mno-mips16:-D__mips16}} \
1012 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1013 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1015 %(subtarget_cpp_spec) "
1018 /* This macro defines names of additional specifications to put in the specs
1019 that can be used in various specifications like CC1_SPEC. Its definition
1020 is an initializer with a subgrouping for each command option.
1022 Each subgrouping contains a string constant, that defines the
1023 specification name, and a string constant that used by the GNU CC driver
1026 Do not define this macro if it does not need to do anything. */
1028 #define EXTRA_SPECS \
1029 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1030 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1031 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1032 { "long_max_spec", LONG_MAX_SPEC }, \
1033 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1034 { "gas_asm_spec", GAS_ASM_SPEC }, \
1035 { "target_asm_spec", TARGET_ASM_SPEC }, \
1036 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1037 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1038 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1039 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1040 { "endian_spec", ENDIAN_SPEC }, \
1041 SUBTARGET_EXTRA_SPECS
1043 #ifndef SUBTARGET_EXTRA_SPECS
1044 #define SUBTARGET_EXTRA_SPECS
1047 /* If defined, this macro is an additional prefix to try after
1048 `STANDARD_EXEC_PREFIX'. */
1050 #ifndef MD_EXEC_PREFIX
1051 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1054 #ifndef MD_STARTFILE_PREFIX
1055 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1059 /* Print subsidiary information on the compiler version in use. */
1061 #define MIPS_VERSION "[AL 1.1, MM 40]"
1063 #ifndef MACHINE_TYPE
1064 #define MACHINE_TYPE "BSD Mips"
1067 #ifndef TARGET_VERSION_INTERNAL
1068 #define TARGET_VERSION_INTERNAL(STREAM) \
1069 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1072 #ifndef TARGET_VERSION
1073 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1077 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1078 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1079 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1081 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1082 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1085 /* By default, turn on GDB extensions. */
1086 #define DEFAULT_GDB_EXTENSIONS 1
1088 /* If we are passing smuggling stabs through the MIPS ECOFF object
1089 format, put a comment in front of the .stab<x> operation so
1090 that the MIPS assembler does not choke. The mips-tfile program
1091 will correctly put the stab into the object file. */
1093 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1094 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1095 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1097 /* Local compiler-generated symbols must have a prefix that the assembler
1098 understands. By default, this is $, although some targets (e.g.,
1099 NetBSD-ELF) need to override this. */
1101 #ifndef LOCAL_LABEL_PREFIX
1102 #define LOCAL_LABEL_PREFIX "$"
1105 /* By default on the mips, external symbols do not have an underscore
1106 prepended, but some targets (e.g., NetBSD) require this. */
1108 #ifndef USER_LABEL_PREFIX
1109 #define USER_LABEL_PREFIX ""
1112 /* Forward references to tags are allowed. */
1113 #define SDB_ALLOW_FORWARD_REFERENCES
1115 /* Unknown tags are also allowed. */
1116 #define SDB_ALLOW_UNKNOWN_REFERENCES
1118 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1119 since the length can run past this up to a continuation point. */
1120 #undef DBX_CONTIN_LENGTH
1121 #define DBX_CONTIN_LENGTH 1500
1123 /* How to renumber registers for dbx and gdb. */
1124 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1126 /* The mapping from gcc register number to DWARF 2 CFA column number.
1127 This mapping does not allow for tracking register 0, since SGI's broken
1128 dwarf reader thinks column 0 is used for the frame address, but since
1129 register 0 is fixed this is not a problem. */
1130 #define DWARF_FRAME_REGNUM(REG) \
1131 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1133 /* The DWARF 2 CFA column which tracks the return address. */
1134 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1136 /* Before the prologue, RA lives in r31. */
1137 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1139 /* Describe how we implement __builtin_eh_return. */
1140 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1141 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1143 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1144 The default for this in 64-bit mode is 8, which causes problems with
1145 SFmode register saves. */
1146 #define DWARF_CIE_DATA_ALIGNMENT 4
1148 /* Overrides for the COFF debug format. */
1149 #define PUT_SDB_SCL(a) \
1151 extern FILE *asm_out_text_file; \
1152 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1155 #define PUT_SDB_INT_VAL(a) \
1157 extern FILE *asm_out_text_file; \
1158 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1161 #define PUT_SDB_VAL(a) \
1163 extern FILE *asm_out_text_file; \
1164 fputs ("\t.val\t", asm_out_text_file); \
1165 output_addr_const (asm_out_text_file, (a)); \
1166 fputc (';', asm_out_text_file); \
1169 #define PUT_SDB_DEF(a) \
1171 extern FILE *asm_out_text_file; \
1172 fprintf (asm_out_text_file, "\t%s.def\t", \
1173 (TARGET_GAS) ? "" : "#"); \
1174 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1175 fputc (';', asm_out_text_file); \
1178 #define PUT_SDB_PLAIN_DEF(a) \
1180 extern FILE *asm_out_text_file; \
1181 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1182 (TARGET_GAS) ? "" : "#", (a)); \
1185 #define PUT_SDB_ENDEF \
1187 extern FILE *asm_out_text_file; \
1188 fprintf (asm_out_text_file, "\t.endef\n"); \
1191 #define PUT_SDB_TYPE(a) \
1193 extern FILE *asm_out_text_file; \
1194 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1197 #define PUT_SDB_SIZE(a) \
1199 extern FILE *asm_out_text_file; \
1200 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1203 #define PUT_SDB_DIM(a) \
1205 extern FILE *asm_out_text_file; \
1206 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1209 #ifndef PUT_SDB_START_DIM
1210 #define PUT_SDB_START_DIM \
1212 extern FILE *asm_out_text_file; \
1213 fprintf (asm_out_text_file, "\t.dim\t"); \
1217 #ifndef PUT_SDB_NEXT_DIM
1218 #define PUT_SDB_NEXT_DIM(a) \
1220 extern FILE *asm_out_text_file; \
1221 fprintf (asm_out_text_file, "%d,", a); \
1225 #ifndef PUT_SDB_LAST_DIM
1226 #define PUT_SDB_LAST_DIM(a) \
1228 extern FILE *asm_out_text_file; \
1229 fprintf (asm_out_text_file, "%d;", a); \
1233 #define PUT_SDB_TAG(a) \
1235 extern FILE *asm_out_text_file; \
1236 fprintf (asm_out_text_file, "\t.tag\t"); \
1237 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1238 fputc (';', asm_out_text_file); \
1241 /* For block start and end, we create labels, so that
1242 later we can figure out where the correct offset is.
1243 The normal .ent/.end serve well enough for functions,
1244 so those are just commented out. */
1246 #define PUT_SDB_BLOCK_START(LINE) \
1248 extern FILE *asm_out_text_file; \
1249 fprintf (asm_out_text_file, \
1250 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1251 LOCAL_LABEL_PREFIX, \
1253 (TARGET_GAS) ? "" : "#", \
1254 LOCAL_LABEL_PREFIX, \
1257 sdb_label_count++; \
1260 #define PUT_SDB_BLOCK_END(LINE) \
1262 extern FILE *asm_out_text_file; \
1263 fprintf (asm_out_text_file, \
1264 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1265 LOCAL_LABEL_PREFIX, \
1267 (TARGET_GAS) ? "" : "#", \
1268 LOCAL_LABEL_PREFIX, \
1271 sdb_label_count++; \
1274 #define PUT_SDB_FUNCTION_START(LINE)
1276 #define PUT_SDB_FUNCTION_END(LINE) \
1278 extern FILE *asm_out_text_file; \
1279 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1282 #define PUT_SDB_EPILOGUE_END(NAME)
1284 #define PUT_SDB_SRC_FILE(FILENAME) \
1286 extern FILE *asm_out_text_file; \
1287 output_file_directive (asm_out_text_file, (FILENAME)); \
1290 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1291 sprintf ((BUFFER), ".%dfake", (NUMBER));
1293 /* Correct the offset of automatic variables and arguments. Note that
1294 the MIPS debug format wants all automatic variables and arguments
1295 to be in terms of the virtual frame pointer (stack pointer before
1296 any adjustment in the function), while the MIPS 3.0 linker wants
1297 the frame pointer to be the stack pointer after the initial
1300 #define DEBUGGER_AUTO_OFFSET(X) \
1301 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1302 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1303 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1305 /* Tell collect that the object format is ECOFF */
1306 #ifndef OBJECT_FORMAT_ROSE
1307 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1308 #define EXTENDED_COFF /* ECOFF, not normal coff */
1311 #if 0 /* These definitions normally have no effect because
1312 MIPS systems define USE_COLLECT2, so
1313 assemble_constructor does nothing anyway. */
1315 /* Don't use the default definitions, because we don't have gld.
1316 Also, we don't want stabs when generating ECOFF output.
1317 Instead we depend on collect to handle these. */
1319 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1320 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1324 /* Target machine storage layout */
1326 /* Define in order to support both big and little endian float formats
1327 in the same gcc binary. */
1328 #define REAL_ARITHMETIC
1330 /* Define this if most significant bit is lowest numbered
1331 in instructions that operate on numbered bit-fields.
1333 #define BITS_BIG_ENDIAN 0
1335 /* Define this if most significant byte of a word is the lowest numbered. */
1336 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1338 /* Define this if most significant word of a multiword number is the lowest. */
1339 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1341 /* Define this to set the endianness to use in libgcc2.c, which can
1342 not depend on target_flags. */
1343 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1344 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1346 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1349 /* Number of bits in an addressable storage unit */
1350 #define BITS_PER_UNIT 8
1352 /* Width in bits of a "word", which is the contents of a machine register.
1353 Note that this is not necessarily the width of data type `int';
1354 if using 16-bit ints on a 68000, this would still be 32.
1355 But on a machine with 16-bit registers, this would be 16. */
1356 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1357 #define MAX_BITS_PER_WORD 64
1359 /* Width of a word, in units (bytes). */
1360 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1361 #define MIN_UNITS_PER_WORD 4
1363 /* For MIPS, width of a floating point register. */
1364 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1366 /* A C expression for the size in bits of the type `int' on the
1367 target machine. If you don't define this, the default is one
1369 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1370 #define MAX_INT_TYPE_SIZE 64
1372 /* Tell the preprocessor the maximum size of wchar_t. */
1373 #ifndef MAX_WCHAR_TYPE_SIZE
1374 #ifndef WCHAR_TYPE_SIZE
1375 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1379 /* A C expression for the size in bits of the type `short' on the
1380 target machine. If you don't define this, the default is half a
1381 word. (If this would be less than one storage unit, it is
1382 rounded up to one unit.) */
1383 #define SHORT_TYPE_SIZE 16
1385 /* A C expression for the size in bits of the type `long' on the
1386 target machine. If you don't define this, the default is one
1388 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1389 #define MAX_LONG_TYPE_SIZE 64
1391 /* A C expression for the size in bits of the type `long long' on the
1392 target machine. If you don't define this, the default is two
1394 #define LONG_LONG_TYPE_SIZE 64
1396 /* A C expression for the size in bits of the type `char' on the
1397 target machine. If you don't define this, the default is one
1398 quarter of a word. (If this would be less than one storage unit,
1399 it is rounded up to one unit.) */
1400 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1402 /* A C expression for the size in bits of the type `float' on the
1403 target machine. If you don't define this, the default is one
1405 #define FLOAT_TYPE_SIZE 32
1407 /* A C expression for the size in bits of the type `double' on the
1408 target machine. If you don't define this, the default is two
1410 #define DOUBLE_TYPE_SIZE 64
1412 /* A C expression for the size in bits of the type `long double' on
1413 the target machine. If you don't define this, the default is two
1415 #define LONG_DOUBLE_TYPE_SIZE 64
1417 /* Width in bits of a pointer.
1418 See also the macro `Pmode' defined below. */
1419 #ifndef POINTER_SIZE
1420 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1423 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1424 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1426 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1427 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1429 /* Allocation boundary (in *bits*) for the code of a function. */
1430 #define FUNCTION_BOUNDARY 32
1432 /* Alignment of field after `int : 0' in a structure. */
1433 #define EMPTY_FIELD_BOUNDARY 32
1435 /* Every structure's size must be a multiple of this. */
1436 /* 8 is observed right on a DECstation and on riscos 4.02. */
1437 #define STRUCTURE_SIZE_BOUNDARY 8
1439 /* There is no point aligning anything to a rounder boundary than this. */
1440 #define BIGGEST_ALIGNMENT 64
1442 /* Set this nonzero if move instructions will actually fail to work
1443 when given unaligned data. */
1444 #define STRICT_ALIGNMENT 1
1446 /* Define this if you wish to imitate the way many other C compilers
1447 handle alignment of bitfields and the structures that contain
1450 The behavior is that the type written for a bitfield (`int',
1451 `short', or other integer type) imposes an alignment for the
1452 entire structure, as if the structure really did contain an
1453 ordinary field of that type. In addition, the bitfield is placed
1454 within the structure so that it would fit within such a field,
1455 not crossing a boundary for it.
1457 Thus, on most machines, a bitfield whose type is written as `int'
1458 would not cross a four-byte boundary, and would force four-byte
1459 alignment for the whole structure. (The alignment used may not
1460 be four bytes; it is controlled by the other alignment
1463 If the macro is defined, its definition should be a C expression;
1464 a nonzero value for the expression enables this behavior. */
1466 #define PCC_BITFIELD_TYPE_MATTERS 1
1468 /* If defined, a C expression to compute the alignment given to a
1469 constant that is being placed in memory. CONSTANT is the constant
1470 and ALIGN is the alignment that the object would ordinarily have.
1471 The value of this macro is used instead of that alignment to align
1474 If this macro is not defined, then ALIGN is used.
1476 The typical use of this macro is to increase alignment for string
1477 constants to be word aligned so that `strcpy' calls that copy
1478 constants can be done inline. */
1480 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1481 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1482 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1484 /* If defined, a C expression to compute the alignment for a static
1485 variable. TYPE is the data type, and ALIGN is the alignment that
1486 the object would ordinarily have. The value of this macro is used
1487 instead of that alignment to align the object.
1489 If this macro is not defined, then ALIGN is used.
1491 One use of this macro is to increase alignment of medium-size
1492 data to make it all fit in fewer cache lines. Another is to
1493 cause character arrays to be word-aligned so that `strcpy' calls
1494 that copy constants to character arrays can be done inline. */
1496 #undef DATA_ALIGNMENT
1497 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1498 ((((ALIGN) < BITS_PER_WORD) \
1499 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1500 || TREE_CODE (TYPE) == UNION_TYPE \
1501 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1504 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1506 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1508 /* Define this macro if an argument declared as `char' or `short' in a
1509 prototype should actually be passed as an `int'. In addition to
1510 avoiding errors in certain cases of mismatch, it also makes for
1511 better code on certain machines. */
1513 #define PROMOTE_PROTOTYPES 1
1515 /* Define if operations between registers always perform the operation
1516 on the full register even if a narrower mode is specified. */
1517 #define WORD_REGISTER_OPERATIONS
1519 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1520 will either zero-extend or sign-extend. The value of this macro should
1521 be the code that says which one of the two operations is implicitly
1524 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1525 moves. All other referces are zero extended. */
1526 #define LOAD_EXTEND_OP(MODE) \
1527 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1528 ? SIGN_EXTEND : ZERO_EXTEND)
1530 /* Define this macro if it is advisable to hold scalars in registers
1531 in a wider mode than that declared by the program. In such cases,
1532 the value is constrained to be within the bounds of the declared
1533 type, but kept valid in the wider mode. The signedness of the
1534 extension may differ from that of the type.
1536 We promote any value smaller than SImode up to SImode. We don't
1537 want to promote to DImode when in 64 bit mode, because that would
1538 prevent us from using the faster SImode multiply and divide
1541 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1542 if (GET_MODE_CLASS (MODE) == MODE_INT \
1543 && GET_MODE_SIZE (MODE) < 4) \
1546 /* Define this if function arguments should also be promoted using the above
1549 #define PROMOTE_FUNCTION_ARGS
1551 /* Likewise, if the function return value is promoted. */
1553 #define PROMOTE_FUNCTION_RETURN
1555 /* Standard register usage. */
1557 /* Number of actual hardware registers.
1558 The hardware registers are assigned numbers for the compiler
1559 from 0 to just below FIRST_PSEUDO_REGISTER.
1560 All registers that the compiler knows about must be given numbers,
1561 even those that are not normally considered general registers.
1563 On the Mips, we have 32 integer registers, 32 floating point
1564 registers, 8 condition code registers, and the special registers
1565 hi, lo, hilo, and rap. The 8 condition code registers are only
1566 used if mips_isa >= 4. The hilo register is only used in 64 bit
1567 mode. It represents a 64 bit value stored as two 32 bit values in
1568 the hi and lo registers; this is the result of the mult
1569 instruction. rap is a pointer to the stack where the return
1570 address reg ($31) was stored. This is needed for C++ exception
1573 #define FIRST_PSEUDO_REGISTER 76
1575 /* 1 for registers that have pervasive standard uses
1576 and are not available for the register allocator.
1578 On the MIPS, see conventions, page D-2 */
1580 #define FIXED_REGISTERS \
1582 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1590 /* 1 for registers not available across function calls.
1591 These must include the FIXED_REGISTERS and also any
1592 registers that can be used without being saved.
1593 The latter must include the registers where values are returned
1594 and the register where structure-value addresses are passed.
1595 Aside from that, you can include as many other registers as you like. */
1597 #define CALL_USED_REGISTERS \
1599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1600 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1602 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1607 /* Internal macros to classify a register number as to whether it's a
1608 general purpose register, a floating point register, a
1609 multiply/divide register, or a status register. */
1611 #define GP_REG_FIRST 0
1612 #define GP_REG_LAST 31
1613 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1614 #define GP_DBX_FIRST 0
1616 #define FP_REG_FIRST 32
1617 #define FP_REG_LAST 63
1618 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1619 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1621 #define MD_REG_FIRST 64
1622 #define MD_REG_LAST 66
1623 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1625 #define ST_REG_FIRST 67
1626 #define ST_REG_LAST 74
1627 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1629 #define RAP_REG_NUM 75
1631 #define AT_REGNUM (GP_REG_FIRST + 1)
1632 #define HI_REGNUM (MD_REG_FIRST + 0)
1633 #define LO_REGNUM (MD_REG_FIRST + 1)
1634 #define HILO_REGNUM (MD_REG_FIRST + 2)
1636 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1637 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1638 should be used instead. */
1639 #define FPSW_REGNUM ST_REG_FIRST
1641 #define GP_REG_P(REGNO) \
1642 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1643 #define M16_REG_P(REGNO) \
1644 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1645 #define FP_REG_P(REGNO) \
1646 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1647 #define MD_REG_P(REGNO) \
1648 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1649 #define ST_REG_P(REGNO) \
1650 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1652 /* Return number of consecutive hard regs needed starting at reg REGNO
1653 to hold something of mode MODE.
1654 This is ordinarily the length in words of a value of mode MODE
1655 but can be less for certain modes in special long registers.
1657 On the MIPS, all general registers are one word long. Except on
1658 the R4000 with the FR bit set, the floating point uses register
1659 pairs, with the second register not being allocable. */
1661 #define HARD_REGNO_NREGS(REGNO, MODE) \
1662 (! FP_REG_P (REGNO) \
1663 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1664 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1666 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1667 MODE. In 32 bit mode, require that DImode and DFmode be in even
1668 registers. For DImode, this makes some of the insns easier to
1669 write, since you don't have to worry about a DImode value in
1670 registers 3 & 4, producing a result in 4 & 5.
1672 To make the code simpler HARD_REGNO_MODE_OK now just references an
1673 array built in override_options. Because machmodes.h is not yet
1674 included before this file is processed, the MODE bound can't be
1677 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1679 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1680 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1682 /* Value is 1 if it is a good idea to tie two pseudo registers
1683 when one has mode MODE1 and one has mode MODE2.
1684 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1685 for any hard reg, then this must be 0 for correct output. */
1686 #define MODES_TIEABLE_P(MODE1, MODE2) \
1687 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1688 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1689 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1690 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1692 /* MIPS pc is not overloaded on a register. */
1693 /* #define PC_REGNUM xx */
1695 /* Register to use for pushing function arguments. */
1696 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1698 /* Offset from the stack pointer to the first available location. Use
1699 the default value zero. */
1700 /* #define STACK_POINTER_OFFSET 0 */
1702 /* Base register for access to local variables of the function. We
1703 pretend that the frame pointer is $1, and then eliminate it to
1704 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1705 a fixed register, and will not be used for anything else. */
1706 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1708 /* Temporary scratch register for use by the assembler. */
1709 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1711 /* $30 is not available on the mips16, so we use $17 as the frame
1713 #define HARD_FRAME_POINTER_REGNUM \
1714 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1716 /* Value should be nonzero if functions must have frame pointers.
1717 Zero means the frame pointer need not be set up (and parms
1718 may be accessed via the stack pointer) in functions that seem suitable.
1719 This is computed in `reload', in reload1.c. */
1720 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1722 /* Base register for access to arguments of the function. */
1723 #define ARG_POINTER_REGNUM GP_REG_FIRST
1725 /* Fake register that holds the address on the stack of the
1726 current function's return address. */
1727 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1729 /* Register in which static-chain is passed to a function. */
1730 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1732 /* If the structure value address is passed in a register, then
1733 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1734 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1736 /* If the structure value address is not passed in a register, define
1737 `STRUCT_VALUE' as an expression returning an RTX for the place
1738 where the address is passed. If it returns 0, the address is
1739 passed as an "invisible" first argument. */
1740 #define STRUCT_VALUE 0
1742 /* Mips registers used in prologue/epilogue code when the stack frame
1743 is larger than 32K bytes. These registers must come from the
1744 scratch register set, and not used for passing and returning
1745 arguments and any other information used in the calling sequence
1746 (such as pic). Must start at 12, since t0/t3 are parameter passing
1747 registers in the 64 bit ABI. */
1749 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1750 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1752 /* Define this macro if it is as good or better to call a constant
1753 function address than to call an address kept in a register. */
1754 #define NO_FUNCTION_CSE 1
1756 /* Define this macro if it is as good or better for a function to
1757 call itself with an explicit address than to call an address
1758 kept in a register. */
1759 #define NO_RECURSIVE_FUNCTION_CSE 1
1761 /* The register number of the register used to address a table of
1762 static data addresses in memory. In some cases this register is
1763 defined by a processor's "application binary interface" (ABI).
1764 When this macro is defined, RTL is generated for this register
1765 once, as with the stack pointer and frame pointer registers. If
1766 this macro is not defined, it is up to the machine-dependent
1767 files to allocate such a register (if necessary). */
1768 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1770 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1772 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1773 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1774 isn't always called for static inline functions. */
1775 #define INIT_EXPANDERS \
1777 embedded_pic_fnaddr_rtx = NULL; \
1778 mips16_gp_pseudo_rtx = NULL; \
1781 /* Define the classes of registers for register constraints in the
1782 machine description. Also define ranges of constants.
1784 One of the classes must always be named ALL_REGS and include all hard regs.
1785 If there is more than one class, another class must be named NO_REGS
1786 and contain no registers.
1788 The name GENERAL_REGS must be the name of a class (or an alias for
1789 another name such as ALL_REGS). This is the class of registers
1790 that is allowed by "g" or "r" in a register constraint.
1791 Also, registers outside this class are allocated only when
1792 instructions express preferences for them.
1794 The classes must be numbered in nondecreasing order; that is,
1795 a larger-numbered class must never be contained completely
1796 in a smaller-numbered class.
1798 For any two classes, it is very desirable that there be another
1799 class that represents their union. */
1803 NO_REGS, /* no registers in set */
1804 M16_NA_REGS, /* mips16 regs not used to pass args */
1805 M16_REGS, /* mips16 directly accessible registers */
1806 T_REG, /* mips16 T register ($24) */
1807 M16_T_REGS, /* mips16 registers plus T register */
1808 GR_REGS, /* integer registers */
1809 FP_REGS, /* floating point registers */
1810 HI_REG, /* hi register */
1811 LO_REG, /* lo register */
1812 HILO_REG, /* hilo register pair for 64 bit mode mult */
1813 MD_REGS, /* multiply/divide registers (hi/lo) */
1814 HI_AND_GR_REGS, /* union classes */
1817 ST_REGS, /* status registers (fp status) */
1818 ALL_REGS, /* all registers */
1819 LIM_REG_CLASSES /* max value + 1 */
1822 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1824 #define GENERAL_REGS GR_REGS
1826 /* An initializer containing the names of the register classes as C
1827 string constants. These names are used in writing some of the
1830 #define REG_CLASS_NAMES \
1845 "HILO_AND_GR_REGS", \
1850 /* An initializer containing the contents of the register classes,
1851 as integers which are bit masks. The Nth integer specifies the
1852 contents of class N. The way the integer MASK is interpreted is
1853 that register R is in the class if `MASK & (1 << R)' is 1.
1855 When the machine has more than 32 registers, an integer does not
1856 suffice. Then the integers are replaced by sub-initializers,
1857 braced groupings containing several integers. Each
1858 sub-initializer must be suitable as an initializer for the type
1859 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1861 #define REG_CLASS_CONTENTS \
1863 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1864 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1865 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1866 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1867 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1868 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1869 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1870 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1871 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1872 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1873 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1874 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1875 { 0xffffffff, 0x00000000, 0x00000002 }, \
1876 { 0xffffffff, 0x00000000, 0x00000004 }, \
1877 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1878 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1882 /* A C expression whose value is a register class containing hard
1883 register REGNO. In general there is more that one such class;
1884 choose a class which is "minimal", meaning that no smaller class
1885 also contains the register. */
1887 extern enum reg_class mips_regno_to_class[];
1889 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1891 /* A macro whose definition is the name of the class to which a
1892 valid base register must belong. A base register is one used in
1893 an address which is the register value plus a displacement. */
1895 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1897 /* A macro whose definition is the name of the class to which a
1898 valid index register must belong. An index register is one used
1899 in an address where its value is either multiplied by a scale
1900 factor or added to another register (as well as added to a
1903 #define INDEX_REG_CLASS NO_REGS
1905 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1906 registers explicitly used in the rtl to be used as spill registers
1907 but prevents the compiler from extending the lifetime of these
1910 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1912 /* This macro is used later on in the file. */
1913 #define GR_REG_CLASS_P(CLASS) \
1914 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1915 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1917 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1918 is the default value (allocate the registers in numeric order). We
1919 define it just so that we can override it for the mips16 target in
1920 ORDER_REGS_FOR_LOCAL_ALLOC. */
1922 #define REG_ALLOC_ORDER \
1923 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1924 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1925 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1926 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1927 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1930 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1931 to be rearranged based on a particular function. On the mips16, we
1932 want to allocate $24 (T_REG) before other registers for
1933 instructions for which it is possible. */
1935 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1937 /* REGISTER AND CONSTANT CLASSES */
1939 /* Get reg_class from a letter such as appears in the machine
1942 DEFINED REGISTER CLASSES:
1944 'd' General (aka integer) registers
1945 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1946 'y' General registers (in both mips16 and non mips16 mode)
1947 'e' mips16 non argument registers (M16_NA_REGS)
1948 't' mips16 temporary register ($24)
1949 'f' Floating point registers
1952 'x' Multiply/divide registers
1954 'z' FP Status register
1955 'b' All registers */
1957 extern enum reg_class mips_char_to_class[];
1959 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1961 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1962 string can be used to stand for particular ranges of immediate
1963 operands. This macro defines what the ranges are. C is the
1964 letter, and VALUE is a constant value. Return 1 if VALUE is
1965 in the range specified by C. */
1969 `I' is used for the range of constants an arithmetic insn can
1970 actually contain (16 bits signed integers).
1972 `J' is used for the range which is just zero (ie, $r0).
1974 `K' is used for the range of constants a logical insn can actually
1975 contain (16 bit zero-extended integers).
1977 `L' is used for the range of constants that be loaded with lui
1978 (ie, the bottom 16 bits are zero).
1980 `M' is used for the range of constants that take two words to load
1981 (ie, not matched by `I', `K', and `L').
1983 `N' is used for negative 16 bit constants other than -65536.
1985 `O' is a 15 bit signed integer.
1987 `P' is used for positive 16 bit constants. */
1989 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1990 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1992 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1993 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1994 : (C) == 'J' ? ((VALUE) == 0) \
1995 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1996 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1997 && (((VALUE) & ~2147483647) == 0 \
1998 || ((VALUE) & ~2147483647) == ~2147483647)) \
1999 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2000 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2001 && (((VALUE) & 0x0000ffff) != 0 \
2002 || (((VALUE) & ~2147483647) != 0 \
2003 && ((VALUE) & ~2147483647) != ~2147483647))) \
2004 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2005 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2006 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2009 /* Similar, but for floating constants, and defining letters G and H.
2010 Here VALUE is the CONST_DOUBLE rtx itself. */
2014 'G' : Floating point 0 */
2016 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2018 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2020 /* Letters in the range `Q' through `U' may be defined in a
2021 machine-dependent fashion to stand for arbitrary operand types.
2022 The machine description macro `EXTRA_CONSTRAINT' is passed the
2023 operand as its first argument and the constraint letter as its
2026 `Q' is for mips16 GP relative constants
2027 `R' is for memory references which take 1 word for the instruction.
2028 `S' is for references to extern items which are PIC for OSF/rose.
2029 `T' is for memory addresses that can be used to load two words. */
2031 #define EXTRA_CONSTRAINT(OP,CODE) \
2032 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2033 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2034 && mips16_gp_offset_p (OP)) \
2035 : (GET_CODE (OP) != MEM) ? FALSE \
2036 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2037 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2038 && HALF_PIC_ADDRESS_P (OP)) \
2041 /* Given an rtx X being reloaded into a reg required to be
2042 in class CLASS, return the class of reg to actually use.
2043 In general this is just CLASS; but on some machines
2044 in some cases it is preferable to use a more restrictive class. */
2046 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2047 ((CLASS) != ALL_REGS \
2048 ? (! TARGET_MIPS16 \
2050 : ((CLASS) != GR_REGS \
2053 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2054 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2055 ? (TARGET_SOFT_FLOAT \
2056 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2058 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2059 || GET_MODE (X) == VOIDmode) \
2060 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2063 /* Certain machines have the property that some registers cannot be
2064 copied to some other registers without using memory. Define this
2065 macro on those machines to be a C expression that is non-zero if
2066 objects of mode MODE in registers of CLASS1 can only be copied to
2067 registers of class CLASS2 by storing a register of CLASS1 into
2068 memory and loading that memory location into a register of CLASS2.
2070 Do not define this macro if its value would always be zero. */
2072 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2073 ((!TARGET_DEBUG_H_MODE \
2074 && GET_MODE_CLASS (MODE) == MODE_INT \
2075 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2076 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2077 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2078 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2079 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2081 /* The HI and LO registers can only be reloaded via the general
2082 registers. Condition code registers can only be loaded to the
2083 general registers, and from the floating point registers. */
2085 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2086 mips_secondary_reload_class (CLASS, MODE, X, 1)
2087 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2088 mips_secondary_reload_class (CLASS, MODE, X, 0)
2090 /* Return the maximum number of consecutive registers
2091 needed to represent mode MODE in a register of class CLASS. */
2093 #define CLASS_UNITS(mode, size) \
2094 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2096 #define CLASS_MAX_NREGS(CLASS, MODE) \
2097 ((CLASS) == FP_REGS \
2099 ? CLASS_UNITS (MODE, 8) \
2100 : 2 * CLASS_UNITS (MODE, 8)) \
2101 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2103 /* If defined, gives a class of registers that cannot be used as the
2104 operand of a SUBREG that changes the mode of the object illegally. */
2106 #define CLASS_CANNOT_CHANGE_MODE \
2107 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2109 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2111 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2112 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2114 /* Stack layout; function entry, exit and calling. */
2116 /* Define this if pushing a word on the stack
2117 makes the stack pointer a smaller address. */
2118 #define STACK_GROWS_DOWNWARD
2120 /* Define this if the nominal address of the stack frame
2121 is at the high-address end of the local variables;
2122 that is, each additional local variable allocated
2123 goes at a more negative offset in the frame. */
2124 /* #define FRAME_GROWS_DOWNWARD */
2126 /* Offset within stack frame to start allocating local variables at.
2127 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2128 first local allocated. Otherwise, it is the offset to the BEGINNING
2129 of the first local allocated. */
2130 #define STARTING_FRAME_OFFSET \
2131 (current_function_outgoing_args_size \
2132 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2134 /* Offset from the stack pointer register to an item dynamically
2135 allocated on the stack, e.g., by `alloca'.
2137 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2138 length of the outgoing arguments. The default is correct for most
2139 machines. See `function.c' for details.
2141 The MIPS ABI states that functions which dynamically allocate the
2142 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2143 we are trying to create a second frame pointer to the function, so
2144 allocate some stack space to make it happy.
2146 However, the linker currently complains about linking any code that
2147 dynamically allocates stack space, and there seems to be a bug in
2148 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2151 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2152 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2153 ? 4*UNITS_PER_WORD \
2154 : current_function_outgoing_args_size)
2157 /* The return address for the current frame is in r31 is this is a leaf
2158 function. Otherwise, it is on the stack. It is at a variable offset
2159 from sp/fp/ap, so we define a fake hard register rap which is a
2160 poiner to the return address on the stack. This always gets eliminated
2161 during reload to be either the frame pointer or the stack pointer plus
2164 /* ??? This definition fails for leaf functions. There is currently no
2165 general solution for this problem. */
2167 /* ??? There appears to be no way to get the return address of any previous
2168 frame except by disassembling instructions in the prologue/epilogue.
2169 So currently we support only the current frame. */
2171 #define RETURN_ADDR_RTX(count, frame) \
2173 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2176 /* Structure to be filled in by compute_frame_size with register
2177 save masks, and offsets for the current function. */
2179 struct mips_frame_info
2181 long total_size; /* # bytes that the entire frame takes up */
2182 long var_size; /* # bytes that variables take up */
2183 long args_size; /* # bytes that outgoing arguments take up */
2184 long extra_size; /* # bytes of extra gunk */
2185 int gp_reg_size; /* # bytes needed to store gp regs */
2186 int fp_reg_size; /* # bytes needed to store fp regs */
2187 long mask; /* mask of saved gp registers */
2188 long fmask; /* mask of saved fp registers */
2189 long gp_save_offset; /* offset from vfp to store gp registers */
2190 long fp_save_offset; /* offset from vfp to store fp registers */
2191 long gp_sp_offset; /* offset from new sp to store gp registers */
2192 long fp_sp_offset; /* offset from new sp to store fp registers */
2193 int initialized; /* != 0 if frame size already calculated */
2194 int num_gp; /* number of gp registers saved */
2195 int num_fp; /* number of fp registers saved */
2196 long insns_len; /* length of insns; mips16 only */
2199 extern struct mips_frame_info current_frame_info;
2201 /* If defined, this macro specifies a table of register pairs used to
2202 eliminate unneeded registers that point into the stack frame. If
2203 it is not defined, the only elimination attempted by the compiler
2204 is to replace references to the frame pointer with references to
2207 The definition of this macro is a list of structure
2208 initializations, each of which specifies an original and
2209 replacement register.
2211 On some machines, the position of the argument pointer is not
2212 known until the compilation is completed. In such a case, a
2213 separate hard register must be used for the argument pointer.
2214 This register can be eliminated by replacing it with either the
2215 frame pointer or the argument pointer, depending on whether or not
2216 the frame pointer has been eliminated.
2218 In this case, you might specify:
2219 #define ELIMINABLE_REGS \
2220 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2221 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2222 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2224 Note that the elimination of the argument pointer with the stack
2225 pointer is specified first since that is the preferred elimination.
2227 The eliminations to $17 are only used on the mips16. See the
2228 definition of HARD_FRAME_POINTER_REGNUM. */
2230 #define ELIMINABLE_REGS \
2231 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2232 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2233 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2234 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2235 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2236 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2237 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2238 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2239 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2240 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2242 /* A C expression that returns non-zero if the compiler is allowed to
2243 try to replace register number FROM-REG with register number
2244 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2245 defined, and will usually be the constant 1, since most of the
2246 cases preventing register elimination are things that the compiler
2247 already knows about.
2249 When not in mips16 and mips64, we can always eliminate to the
2250 frame pointer. We can eliminate to the stack pointer unless
2251 a frame pointer is needed. In mips16 mode, we need a frame
2252 pointer for a large frame; otherwise, reload may be unable
2253 to compute the address of a local variable, since there is
2254 no way to add a large constant to the stack pointer
2255 without using a temporary register.
2257 In mips16, for some instructions (eg lwu), we can't eliminate the
2258 frame pointer for the stack pointer. These instructions are
2259 only generated in TARGET_64BIT mode.
2262 #define CAN_ELIMINATE(FROM, TO) \
2263 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2264 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2265 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2266 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2267 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2268 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2269 && (! TARGET_MIPS16 \
2270 || compute_frame_size (get_frame_size ()) < 32768)))))
2272 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2273 specifies the initial difference between the specified pair of
2274 registers. This macro must be defined if `ELIMINABLE_REGS' is
2277 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2278 { compute_frame_size (get_frame_size ()); \
2279 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2280 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2281 (OFFSET) = - current_function_outgoing_args_size; \
2282 else if ((FROM) == FRAME_POINTER_REGNUM) \
2284 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2285 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2286 (OFFSET) = (current_frame_info.total_size \
2287 - current_function_outgoing_args_size \
2288 - ((mips_abi != ABI_32 \
2289 && mips_abi != ABI_O64 \
2290 && mips_abi != ABI_EABI) \
2291 ? current_function_pretend_args_size \
2293 else if ((FROM) == ARG_POINTER_REGNUM) \
2294 (OFFSET) = (current_frame_info.total_size \
2295 - ((mips_abi != ABI_32 \
2296 && mips_abi != ABI_O64 \
2297 && mips_abi != ABI_EABI) \
2298 ? current_function_pretend_args_size \
2300 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2301 so we must add 4 bytes to the offset to get the right value. */ \
2302 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2304 if (leaf_function_p ()) \
2306 else (OFFSET) = current_frame_info.gp_sp_offset \
2307 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2308 * (BYTES_BIG_ENDIAN != 0)); \
2312 /* If we generate an insn to push BYTES bytes,
2313 this says how many the stack pointer really advances by.
2314 On the vax, sp@- in a byte insn really pushes a word. */
2316 /* #define PUSH_ROUNDING(BYTES) 0 */
2318 /* If defined, the maximum amount of space required for outgoing
2319 arguments will be computed and placed into the variable
2320 `current_function_outgoing_args_size'. No space will be pushed
2321 onto the stack for each call; instead, the function prologue
2322 should increase the stack frame size by this amount.
2324 It is not proper to define both `PUSH_ROUNDING' and
2325 `ACCUMULATE_OUTGOING_ARGS'. */
2326 #define ACCUMULATE_OUTGOING_ARGS 1
2328 /* Offset from the argument pointer register to the first argument's
2329 address. On some machines it may depend on the data type of the
2332 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2333 the first argument's address.
2335 On the MIPS, we must skip the first argument position if we are
2336 returning a structure or a union, to account for its address being
2337 passed in $4. However, at the current time, this produces a compiler
2338 that can't bootstrap, so comment it out for now. */
2341 #define FIRST_PARM_OFFSET(FNDECL) \
2343 && TREE_TYPE (FNDECL) != 0 \
2344 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2345 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2346 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2350 #define FIRST_PARM_OFFSET(FNDECL) 0
2353 /* When a parameter is passed in a register, stack space is still
2354 allocated for it. For the MIPS, stack space must be allocated, cf
2355 Asm Lang Prog Guide page 7-8.
2357 BEWARE that some space is also allocated for non existing arguments
2358 in register. In case an argument list is of form GF used registers
2359 are a0 (a2,a3), but we should push over a1... */
2361 #define REG_PARM_STACK_SPACE(FNDECL) \
2362 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2364 /* Define this if it is the responsibility of the caller to
2365 allocate the area reserved for arguments passed in registers.
2366 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2367 of this macro is to determine whether the space is included in
2368 `current_function_outgoing_args_size'. */
2369 #define OUTGOING_REG_PARM_STACK_SPACE
2371 /* Align stack frames on 64 bits (Double Word ). */
2372 #ifndef STACK_BOUNDARY
2373 #define STACK_BOUNDARY 64
2376 /* Make sure 4 words are always allocated on the stack. */
2378 #ifndef STACK_ARGS_ADJUST
2379 #define STACK_ARGS_ADJUST(SIZE) \
2381 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2382 SIZE.constant = 4 * UNITS_PER_WORD; \
2387 /* A C expression that should indicate the number of bytes of its
2388 own arguments that a function pops on returning, or 0
2389 if the function pops no arguments and the caller must therefore
2390 pop them all after the function returns.
2392 FUNDECL is the declaration node of the function (as a tree).
2394 FUNTYPE is a C variable whose value is a tree node that
2395 describes the function in question. Normally it is a node of
2396 type `FUNCTION_TYPE' that describes the data type of the function.
2397 From this it is possible to obtain the data types of the value
2398 and arguments (if known).
2400 When a call to a library function is being considered, FUNTYPE
2401 will contain an identifier node for the library function. Thus,
2402 if you need to distinguish among various library functions, you
2403 can do so by their names. Note that "library function" in this
2404 context means a function used to perform arithmetic, whose name
2405 is known specially in the compiler and was not mentioned in the
2406 C code being compiled.
2408 STACK-SIZE is the number of bytes of arguments passed on the
2409 stack. If a variable number of bytes is passed, it is zero, and
2410 argument popping will always be the responsibility of the
2411 calling function. */
2413 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2416 /* Symbolic macros for the registers used to return integer and floating
2419 #define GP_RETURN (GP_REG_FIRST + 2)
2420 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2422 /* Symbolic macros for the first/last argument registers. */
2424 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2425 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2426 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2427 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2429 #define MAX_ARGS_IN_REGISTERS 4
2431 /* Define how to find the value returned by a library function
2432 assuming the value has mode MODE. Because we define
2433 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2434 PROMOTE_MODE does. */
2436 #define LIBCALL_VALUE(MODE) \
2438 ((GET_MODE_CLASS (MODE) != MODE_INT \
2439 || GET_MODE_SIZE (MODE) >= 4) \
2442 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2443 && (! TARGET_SINGLE_FLOAT \
2444 || GET_MODE_SIZE (MODE) <= 4)) \
2448 /* Define how to find the value returned by a function.
2449 VALTYPE is the data type of the value (as a tree).
2450 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2451 otherwise, FUNC is 0. */
2453 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2456 /* 1 if N is a possible register number for a function value.
2457 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2458 Currently, R2 and F0 are only implemented here (C has no complex type) */
2460 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2462 /* 1 if N is a possible register number for function argument passing.
2463 We have no FP argument registers when soft-float. When FP registers
2464 are 32 bits, we can't directly reference the odd numbered ones. */
2466 #define FUNCTION_ARG_REGNO_P(N) \
2467 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2468 || ((! TARGET_SOFT_FLOAT \
2469 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2470 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2471 && ! fixed_regs[N]))
2473 /* A C expression which can inhibit the returning of certain function
2474 values in registers, based on the type of value. A nonzero value says
2475 to return the function value in memory, just as large structures are
2476 always returned. Here TYPE will be a C expression of type
2477 `tree', representing the data type of the value.
2479 Note that values of mode `BLKmode' must be explicitly
2480 handled by this macro. Also, the option `-fpcc-struct-return'
2481 takes effect regardless of this macro. On most systems, it is
2482 possible to leave the macro undefined; this causes a default
2483 definition to be used, whose value is the constant 1 for BLKmode
2484 values, and 0 otherwise.
2486 GCC normally converts 1 byte structures into chars, 2 byte
2487 structs into shorts, and 4 byte structs into ints, and returns
2488 them this way. Defining the following macro overrides this,
2489 to give us MIPS cc compatibility. */
2491 #define RETURN_IN_MEMORY(TYPE) \
2492 (TYPE_MODE (TYPE) == BLKmode)
2494 /* A code distinguishing the floating point format of the target
2495 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2496 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2498 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2501 /* Define a data type for recording info about an argument list
2502 during the scan of that argument list. This data type should
2503 hold all necessary information about the function itself
2504 and about the args processed so far, enough to enable macros
2505 such as FUNCTION_ARG to determine where the next arg should go.
2507 On the mips16, we need to keep track of which floating point
2508 arguments were passed in general registers, but would have been
2509 passed in the FP regs if this were a 32 bit function, so that we
2510 can move them to the FP regs if we wind up calling a 32 bit
2511 function. We record this information in fp_code, encoded in base
2512 four. A zero digit means no floating point argument, a one digit
2513 means an SFmode argument, and a two digit means a DFmode argument,
2514 and a three digit is not used. The low order digit is the first
2515 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2516 an SFmode argument. ??? A more sophisticated approach will be
2517 needed if MIPS_ABI != ABI_32. */
2519 typedef struct mips_args {
2520 int gp_reg_found; /* whether a gp register was found yet */
2521 unsigned int arg_number; /* argument number */
2522 unsigned int arg_words; /* # total words the arguments take */
2523 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2524 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2525 int fp_code; /* Mode of FP arguments (mips16) */
2526 unsigned int num_adjusts; /* number of adjustments made */
2527 /* Adjustments made to args pass in regs. */
2528 /* ??? The size is doubled to work around a
2529 bug in the code that sets the adjustments
2531 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2534 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2535 for a call to a function whose data type is FNTYPE.
2536 For a library call, FNTYPE is 0.
2540 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2541 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2543 /* Update the data in CUM to advance over an argument
2544 of mode MODE and data type TYPE.
2545 (TYPE is null for libcalls where that information may not be available.) */
2547 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2548 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2550 /* Determine where to put an argument to a function.
2551 Value is zero to push the argument on the stack,
2552 or a hard register in which to store the argument.
2554 MODE is the argument's machine mode.
2555 TYPE is the data type of the argument (as a tree).
2556 This is null for libcalls where that information may
2558 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2559 the preceding args and about the function being called.
2560 NAMED is nonzero if this argument is a named parameter
2561 (otherwise it is an extra parameter matching an ellipsis). */
2563 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2564 function_arg( &CUM, MODE, TYPE, NAMED)
2566 /* For an arg passed partly in registers and partly in memory,
2567 this is the number of registers used.
2568 For args passed entirely in registers or entirely in memory, zero. */
2570 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2571 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2573 /* If defined, a C expression that gives the alignment boundary, in
2574 bits, of an argument with the specified mode and type. If it is
2575 not defined, `PARM_BOUNDARY' is used for all arguments. */
2577 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2579 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2581 : TYPE_ALIGN(TYPE)) \
2582 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2584 : GET_MODE_ALIGNMENT(MODE)))
2587 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2589 #define MUST_SAVE_REGISTER(regno) \
2590 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2591 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2592 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2594 /* ALIGN FRAMES on double word boundaries */
2595 #ifndef MIPS_STACK_ALIGN
2596 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2600 /* Define the `__builtin_va_list' type for the ABI. */
2601 #define BUILD_VA_LIST_TYPE(VALIST) \
2602 (VALIST) = mips_build_va_list ()
2604 /* Implement `va_start' for varargs and stdarg. */
2605 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2606 mips_va_start (stdarg, valist, nextarg)
2608 /* Implement `va_arg'. */
2609 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2610 mips_va_arg (valist, type)
2612 /* Output assembler code to FILE to increment profiler label # LABELNO
2613 for profiling a function entry. */
2615 #define FUNCTION_PROFILER(FILE, LABELNO) \
2617 if (TARGET_MIPS16) \
2618 sorry ("mips16 function profiling"); \
2619 fprintf (FILE, "\t.set\tnoreorder\n"); \
2620 fprintf (FILE, "\t.set\tnoat\n"); \
2621 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2622 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2623 fprintf (FILE, "\tjal\t_mcount\n"); \
2625 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2626 TARGET_64BIT ? "dsubu" : "subu", \
2627 reg_names[STACK_POINTER_REGNUM], \
2628 reg_names[STACK_POINTER_REGNUM], \
2629 Pmode == DImode ? 16 : 8); \
2630 fprintf (FILE, "\t.set\treorder\n"); \
2631 fprintf (FILE, "\t.set\tat\n"); \
2634 /* Define this macro if the code for function profiling should come
2635 before the function prologue. Normally, the profiling code comes
2638 /* #define PROFILE_BEFORE_PROLOGUE */
2640 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2641 the stack pointer does not matter. The value is tested only in
2642 functions that have frame pointers.
2643 No definition is equivalent to always zero. */
2645 #define EXIT_IGNORE_STACK 1
2648 /* A C statement to output, on the stream FILE, assembler code for a
2649 block of data that contains the constant parts of a trampoline.
2650 This code should not include a label--the label is taken care of
2653 #define TRAMPOLINE_TEMPLATE(STREAM) \
2655 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2656 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2657 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2658 if (Pmode == DImode) \
2660 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2661 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2665 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2666 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2668 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2669 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2670 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2671 if (Pmode == DImode) \
2673 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2674 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2678 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2679 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2683 /* A C expression for the size in bytes of the trampoline, as an
2686 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2688 /* Alignment required for trampolines, in bits. */
2690 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2692 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2693 program and data caches. */
2695 #ifndef CACHE_FLUSH_FUNC
2696 #define CACHE_FLUSH_FUNC "_flush_cache"
2699 /* A C statement to initialize the variable parts of a trampoline.
2700 ADDR is an RTX for the address of the trampoline; FNADDR is an
2701 RTX for the address of the nested function; STATIC_CHAIN is an
2702 RTX for the static chain value that should be passed to the
2703 function when it is called. */
2705 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2708 if (Pmode == DImode) \
2710 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2711 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2715 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2716 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2719 /* Flush both caches. We need to flush the data cache in case \
2720 the system has a write-back cache. */ \
2721 /* ??? Should check the return value for errors. */ \
2722 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2723 0, VOIDmode, 3, addr, Pmode, \
2724 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2725 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2728 /* Addressing modes, and classification of registers for them. */
2730 /* #define HAVE_POST_INCREMENT 0 */
2731 /* #define HAVE_POST_DECREMENT 0 */
2733 /* #define HAVE_PRE_DECREMENT 0 */
2734 /* #define HAVE_PRE_INCREMENT 0 */
2736 /* These assume that REGNO is a hard or pseudo reg number.
2737 They give nonzero only if REGNO is a hard reg of the suitable class
2738 or a pseudo reg currently allocated to a suitable hard reg.
2739 These definitions are NOT overridden anywhere. */
2741 #define BASE_REG_P(regno, mode) \
2743 ? (M16_REG_P (regno) \
2744 || (regno) == FRAME_POINTER_REGNUM \
2745 || (regno) == ARG_POINTER_REGNUM \
2746 || ((regno) == STACK_POINTER_REGNUM \
2747 && (GET_MODE_SIZE (mode) == 4 \
2748 || GET_MODE_SIZE (mode) == 8))) \
2751 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2752 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2755 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2756 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2758 #define REGNO_OK_FOR_INDEX_P(regno) 0
2759 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2760 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2762 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2763 and check its validity for a certain class.
2764 We have two alternate definitions for each of them.
2765 The usual definition accepts all pseudo regs; the other rejects them all.
2766 The symbol REG_OK_STRICT causes the latter definition to be used.
2768 Most source files want to accept pseudo regs in the hope that
2769 they will get allocated to the class that the insn wants them to be in.
2770 Some source files that are used after register allocation
2771 need to be strict. */
2773 #ifndef REG_OK_STRICT
2774 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2775 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2777 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2778 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2781 #define REG_OK_FOR_INDEX_P(X) 0
2784 /* Maximum number of registers that can appear in a valid memory address. */
2786 #define MAX_REGS_PER_ADDRESS 1
2788 /* A C compound statement with a conditional `goto LABEL;' executed
2789 if X (an RTX) is a legitimate memory address on the target
2790 machine for a memory operand of mode MODE.
2792 It usually pays to define several simpler macros to serve as
2793 subroutines for this one. Otherwise it may be too complicated
2796 This macro must exist in two variants: a strict variant and a
2797 non-strict one. The strict variant is used in the reload pass.
2798 It must be defined so that any pseudo-register that has not been
2799 allocated a hard register is considered a memory reference. In
2800 contexts where some kind of register is required, a
2801 pseudo-register with no hard register must be rejected.
2803 The non-strict variant is used in other passes. It must be
2804 defined to accept all pseudo-registers in every context where
2805 some kind of register is required.
2807 Compiler source files that want to use the strict variant of
2808 this macro define the macro `REG_OK_STRICT'. You should use an
2809 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2810 in that case and the non-strict variant otherwise.
2812 Typically among the subroutines used to define
2813 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2814 acceptable registers for various purposes (one for base
2815 registers, one for index registers, and so on). Then only these
2816 subroutine macros need have two variants; the higher levels of
2817 macros may be the same whether strict or not.
2819 Normally, constant addresses which are the sum of a `symbol_ref'
2820 and an integer are stored inside a `const' RTX to mark them as
2821 constant. Therefore, there is no need to recognize such sums
2822 specifically as legitimate addresses. Normally you would simply
2823 recognize any `const' as legitimate.
2825 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2826 constant sums that are not marked with `const'. It assumes
2827 that a naked `plus' indicates indexing. If so, then you *must*
2828 reject such naked constant sums as illegitimate addresses, so
2829 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2831 On some machines, whether a symbolic address is legitimate
2832 depends on the section that the address refers to. On these
2833 machines, define the macro `ENCODE_SECTION_INFO' to store the
2834 information into the `symbol_ref', and then check for it here.
2835 When you see a `const', you will have to look inside it to find
2836 the `symbol_ref' in order to determine the section. */
2839 #define GO_PRINTF(x) fprintf(stderr, (x))
2840 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2841 #define GO_DEBUG_RTX(x) debug_rtx(x)
2844 #define GO_PRINTF(x)
2845 #define GO_PRINTF2(x,y)
2846 #define GO_DEBUG_RTX(x)
2849 #ifdef REG_OK_STRICT
2850 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2852 if (mips_legitimate_address_p (MODE, X, 1)) \
2856 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2858 if (mips_legitimate_address_p (MODE, X, 0)) \
2863 /* A C expression that is 1 if the RTX X is a constant which is a
2864 valid address. This is defined to be the same as `CONSTANT_P (X)',
2865 but rejecting CONST_DOUBLE. */
2866 /* When pic, we must reject addresses of the form symbol+large int.
2867 This is because an instruction `sw $4,s+70000' needs to be converted
2868 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2869 assembler would use $at as a temp to load in the large offset. In this
2870 case $at is already in use. We convert such problem addresses to
2871 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2872 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2873 #define CONSTANT_ADDRESS_P(X) \
2874 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2875 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2876 || (GET_CODE (X) == CONST \
2877 && ! (flag_pic && pic_address_needs_scratch (X)) \
2878 && (mips_abi == ABI_32 \
2879 || mips_abi == ABI_O64 \
2880 || mips_abi == ABI_EABI))) \
2881 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2883 /* Define this, so that when PIC, reload won't try to reload invalid
2884 addresses which require two reload registers. */
2886 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2888 /* Nonzero if the constant value X is a legitimate general operand.
2889 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2891 At present, GAS doesn't understand li.[sd], so don't allow it
2892 to be generated at present. Also, the MIPS assembler does not
2893 grok li.d Infinity. */
2895 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2896 Note that the Irix 6 assembler problem may already be fixed.
2897 Note also that the GET_CODE (X) == CONST test catches the mips16
2898 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2899 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2900 ABI_64 to work together, we'll need to fix this. */
2901 #define LEGITIMATE_CONSTANT_P(X) \
2902 ((GET_CODE (X) != CONST_DOUBLE \
2903 || mips_const_double_ok (X, GET_MODE (X))) \
2904 && ! (GET_CODE (X) == CONST \
2906 && (mips_abi == ABI_N32 \
2907 || mips_abi == ABI_64)) \
2908 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2910 /* A C compound statement that attempts to replace X with a valid
2911 memory address for an operand of mode MODE. WIN will be a C
2912 statement label elsewhere in the code; the macro definition may
2915 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2917 to avoid further processing if the address has become legitimate.
2919 X will always be the result of a call to `break_out_memory_refs',
2920 and OLDX will be the operand that was given to that function to
2923 The code generated by this macro should not alter the
2924 substructure of X. If it transforms X into a more legitimate
2925 form, it should assign X (which will always be a C variable) a
2928 It is not necessary for this macro to come up with a legitimate
2929 address. The compiler has standard ways of doing so in all
2930 cases. In fact, it is safe for this macro to do nothing. But
2931 often a machine-dependent strategy can generate better code.
2933 For the MIPS, transform:
2935 memory(X + <large int>)
2939 Y = <large int> & ~0x7fff;
2941 memory (Z + (<large int> & 0x7fff));
2943 This is for CSE to find several similar references, and only use one Z.
2945 When PIC, convert addresses of the form memory (symbol+large int) to
2946 memory (reg+large int). */
2949 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2951 register rtx xinsn = (X); \
2953 if (TARGET_DEBUG_B_MODE) \
2955 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2956 GO_DEBUG_RTX (xinsn); \
2959 if (mips_split_addresses && mips_check_split (X, MODE)) \
2961 /* ??? Is this ever executed? */ \
2962 X = gen_rtx_LO_SUM (Pmode, \
2963 copy_to_mode_reg (Pmode, \
2964 gen_rtx (HIGH, Pmode, X)), \
2969 if (GET_CODE (xinsn) == CONST \
2970 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2971 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2972 || (mips_abi != ABI_32 \
2973 && mips_abi != ABI_O64 \
2974 && mips_abi != ABI_EABI))) \
2976 rtx ptr_reg = gen_reg_rtx (Pmode); \
2977 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2979 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2981 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2982 if (SMALL_INT (constant)) \
2984 /* Otherwise we fall through so the code below will fix the \
2989 if (GET_CODE (xinsn) == PLUS) \
2991 register rtx xplus0 = XEXP (xinsn, 0); \
2992 register rtx xplus1 = XEXP (xinsn, 1); \
2993 register enum rtx_code code0 = GET_CODE (xplus0); \
2994 register enum rtx_code code1 = GET_CODE (xplus1); \
2996 if (code0 != REG && code1 == REG) \
2998 xplus0 = XEXP (xinsn, 1); \
2999 xplus1 = XEXP (xinsn, 0); \
3000 code0 = GET_CODE (xplus0); \
3001 code1 = GET_CODE (xplus1); \
3004 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3005 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3007 rtx int_reg = gen_reg_rtx (Pmode); \
3008 rtx ptr_reg = gen_reg_rtx (Pmode); \
3010 emit_move_insn (int_reg, \
3011 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3013 emit_insn (gen_rtx_SET (VOIDmode, \
3015 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3017 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3022 if (TARGET_DEBUG_B_MODE) \
3023 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3027 /* A C statement or compound statement with a conditional `goto
3028 LABEL;' executed if memory address X (an RTX) can have different
3029 meanings depending on the machine mode of the memory reference it
3032 Autoincrement and autodecrement addresses typically have
3033 mode-dependent effects because the amount of the increment or
3034 decrement is the size of the operand being addressed. Some
3035 machines have other mode-dependent addresses. Many RISC machines
3036 have no mode-dependent addresses.
3038 You may assume that ADDR is a valid address for the machine. */
3040 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3043 /* Define this macro if references to a symbol must be treated
3044 differently depending on something about the variable or
3045 function named by the symbol (such as what section it is in).
3047 The macro definition, if any, is executed immediately after the
3048 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3049 The value of the rtl will be a `mem' whose address is a
3052 The usual thing for this macro to do is to a flag in the
3053 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3054 name string in the `symbol_ref' (if one bit is not enough
3057 The best way to modify the name string is by adding text to the
3058 beginning, with suitable punctuation to prevent any ambiguity.
3059 Allocate the new name in `saveable_obstack'. You will have to
3060 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3061 and output the name accordingly.
3063 You can also check the information stored in the `symbol_ref' in
3064 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3065 `PRINT_OPERAND_ADDRESS'.
3067 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3070 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3071 symbols which are not in the .text section.
3073 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3074 constants which are put in the .text section. We also record the
3075 total length of all such strings; this total is used to decide
3076 whether we need to split the constant table, and need not be
3079 When not mips16 code nor embedded PIC, if a symbol is in a
3080 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3081 splitting the reference so that gas can generate a gp relative
3084 When TARGET_EMBEDDED_DATA is set, we assume that all const
3085 variables will be stored in ROM, which is too far from %gp to use
3086 %gprel addressing. Note that (1) we include "extern const"
3087 variables in this, which mips_select_section doesn't, and (2) we
3088 can't always tell if they're really const (they might be const C++
3089 objects with non-const constructors), so we err on the side of
3090 caution and won't use %gprel anyway (otherwise we'd have to defer
3091 this decision to the linker/loader). The handling of extern consts
3092 is why the DECL_INITIAL macros differ from mips_select_section.
3094 If you are changing this macro, you should look at
3095 mips_select_section and see if it needs a similar change. */
3097 #ifndef UNIQUE_SECTION_P
3098 #define UNIQUE_SECTION_P(DECL) (0)
3101 #define ENCODE_SECTION_INFO(DECL) \
3104 if (TARGET_MIPS16) \
3106 if (TREE_CODE (DECL) == STRING_CST \
3107 && ! flag_writable_strings \
3108 /* If this string is from a function, and the function will \
3109 go in a gnu linkonce section, then we can't directly \
3110 access the string. This gets an assembler error \
3111 "unsupported PC relative reference to different section".\
3112 If we modify SELECT_SECTION to put it in function_section\
3113 instead of text_section, it still fails because \
3114 DECL_SECTION_NAME isn't set until assemble_start_function.\
3115 If we fix that, it still fails because strings are shared\
3116 among multiple functions, and we have cross section \
3117 references again. We force it to work by putting string \
3118 addresses in the constant pool and indirecting. */ \
3119 && (! current_function_decl \
3120 || ! UNIQUE_SECTION_P (current_function_decl))) \
3122 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3123 mips_string_length += TREE_STRING_LENGTH (DECL); \
3127 if (TARGET_EMBEDDED_DATA \
3128 && (TREE_CODE (DECL) == VAR_DECL \
3129 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3130 && (!DECL_INITIAL (DECL) \
3131 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3133 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3136 else if (TARGET_EMBEDDED_PIC) \
3138 if (TREE_CODE (DECL) == VAR_DECL) \
3139 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3140 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3141 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3142 else if (TREE_CODE (DECL) == STRING_CST \
3143 && ! flag_writable_strings) \
3144 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3146 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3149 else if (TREE_CODE (DECL) == VAR_DECL \
3150 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3151 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3153 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3156 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3159 /* We can not perform GP optimizations on variables which are in \
3160 specific sections, except for .sdata and .sbss which are \
3162 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3163 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3165 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3167 if (size > 0 && size <= mips_section_threshold) \
3168 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3171 else if (HALF_PIC_P ()) \
3173 HALF_PIC_ENCODE (DECL); \
3178 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3179 'the start of the function that this code is output in'. */
3181 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3182 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3183 asm_fprintf ((FILE), "%U%s", \
3184 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3186 asm_fprintf ((FILE), "%U%s", (NAME))
3188 /* The mips16 wants the constant pool to be after the function,
3189 because the PC relative load instructions use unsigned offsets. */
3191 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3193 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3194 mips_string_length = 0;
3197 /* In mips16 mode, put most string constants after the function. */
3198 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3199 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3202 /* Specify the machine mode that this machine uses
3203 for the index in the tablejump instruction.
3204 ??? Using HImode in mips16 mode can cause overflow. However, the
3205 overflow is no more likely than the overflow in a branch
3206 instruction. Large functions can currently break in both ways. */
3207 #define CASE_VECTOR_MODE \
3208 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3210 /* Define as C expression which evaluates to nonzero if the tablejump
3211 instruction expects the table to contain offsets from the address of the
3213 Do not define this if the table should contain absolute addresses. */
3214 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3216 /* Specify the tree operation to be used to convert reals to integers. */
3217 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3219 /* This is the kind of divide that is easiest to do in the general case. */
3220 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3222 /* Define this as 1 if `char' should by default be signed; else as 0. */
3223 #ifndef DEFAULT_SIGNED_CHAR
3224 #define DEFAULT_SIGNED_CHAR 1
3227 /* Max number of bytes we can move from memory to memory
3228 in one reasonably fast instruction. */
3229 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3230 #define MAX_MOVE_MAX 8
3232 /* Define this macro as a C expression which is nonzero if
3233 accessing less than a word of memory (i.e. a `char' or a
3234 `short') is no faster than accessing a word of memory, i.e., if
3235 such access require more than one instruction or if there is no
3236 difference in cost between byte and (aligned) word loads.
3238 On RISC machines, it tends to generate better code to define
3239 this as 1, since it avoids making a QI or HI mode register. */
3240 #define SLOW_BYTE_ACCESS 1
3242 /* We assume that the store-condition-codes instructions store 0 for false
3243 and some other value for true. This is the value stored for true. */
3245 #define STORE_FLAG_VALUE 1
3247 /* Define this if zero-extension is slow (more than one real instruction). */
3248 #define SLOW_ZERO_EXTEND
3250 /* Define this to be nonzero if shift instructions ignore all but the low-order
3252 #define SHIFT_COUNT_TRUNCATED 1
3254 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3255 is done just by pretending it is already truncated. */
3256 /* In 64 bit mode, 32 bit instructions require that register values be properly
3257 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3258 converts a value >32 bits to a value <32 bits. */
3259 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3260 Something needs to be done about this. Perhaps not use any 32 bit
3261 instructions? Perhaps use PROMOTE_MODE? */
3262 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3263 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3265 /* Specify the machine mode that pointers have.
3266 After generation of rtl, the compiler makes no further distinction
3267 between pointers and any other objects of this machine mode.
3269 For MIPS we make pointers are the smaller of longs and gp-registers. */
3272 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3275 /* A function address in a call instruction
3276 is a word address (for indexing purposes)
3277 so give the MEM rtx a words's mode. */
3279 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3281 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3282 memset, instead of the BSD functions bcopy and bzero. */
3284 #if defined(MIPS_SYSV) || defined(OSF_OS)
3285 #define TARGET_MEM_FUNCTIONS
3289 /* A part of a C `switch' statement that describes the relative
3290 costs of constant RTL expressions. It must contain `case'
3291 labels for expression codes `const_int', `const', `symbol_ref',
3292 `label_ref' and `const_double'. Each case must ultimately reach
3293 a `return' statement to return the relative cost of the use of
3294 that kind of constant value in an expression. The cost may
3295 depend on the precise value of the constant, which is available
3296 for examination in X.
3298 CODE is the expression code--redundant, since it can be obtained
3299 with `GET_CODE (X)'. */
3301 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3303 if (! TARGET_MIPS16) \
3305 /* Always return 0, since we don't have different sized \
3306 instructions, hence different costs according to Richard \
3310 if ((OUTER_CODE) == SET) \
3312 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3314 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3315 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3316 return COSTS_N_INSNS (1); \
3318 return COSTS_N_INSNS (2); \
3320 /* A PLUS could be an address. We don't want to force an address \
3321 to use a register, so accept any signed 16 bit value without \
3323 if ((OUTER_CODE) == PLUS \
3324 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3326 /* A number between 1 and 8 inclusive is efficient for a shift. \
3327 Otherwise, we will need an extended instruction. */ \
3328 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3329 || (OUTER_CODE) == LSHIFTRT) \
3331 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3333 return COSTS_N_INSNS (1); \
3335 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3336 if ((OUTER_CODE) == XOR \
3337 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3339 /* We may be able to use slt or sltu for a comparison with a \
3340 signed 16 bit value. (The boundary conditions aren't quite \
3341 right, but this is just a heuristic anyhow.) */ \
3342 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3343 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3344 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3345 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3346 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3348 /* Equality comparisons with 0 are cheap. */ \
3349 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3350 && INTVAL (X) == 0) \
3353 /* Otherwise, work out the cost to load the value into a \
3355 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3356 return COSTS_N_INSNS (1); \
3357 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3358 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3359 return COSTS_N_INSNS (2); \
3361 return COSTS_N_INSNS (3); \
3364 return COSTS_N_INSNS (2); \
3368 rtx offset = const0_rtx; \
3369 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3371 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3373 /* Treat this like a signed 16 bit CONST_INT. */ \
3374 if ((OUTER_CODE) == PLUS) \
3376 else if ((OUTER_CODE) == SET) \
3377 return COSTS_N_INSNS (1); \
3379 return COSTS_N_INSNS (2); \
3382 if (GET_CODE (symref) == LABEL_REF) \
3383 return COSTS_N_INSNS (2); \
3385 if (GET_CODE (symref) != SYMBOL_REF) \
3386 return COSTS_N_INSNS (4); \
3388 /* let's be paranoid.... */ \
3389 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3390 return COSTS_N_INSNS (2); \
3392 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3396 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3398 case CONST_DOUBLE: \
3401 if (TARGET_MIPS16) \
3402 return COSTS_N_INSNS (4); \
3403 split_double (X, &high, &low); \
3404 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3405 || low == CONST0_RTX (GET_MODE (low))) \
3409 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3410 This can be used, for example, to indicate how costly a multiply
3411 instruction is. In writing this macro, you can use the construct
3412 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3414 This macro is optional; do not define it if the default cost
3415 assumptions are adequate for the target machine.
3417 If -mdebugd is used, change the multiply cost to 2, so multiply by
3418 a constant isn't converted to a series of shifts. This helps
3419 strength reduction, and also makes it easier to identify what the
3420 compiler is doing. */
3422 /* ??? Fix this to be right for the R8000. */
3423 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3426 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3427 if (simple_memory_operand (X, GET_MODE (X))) \
3428 return COSTS_N_INSNS (num_words); \
3430 return COSTS_N_INSNS (2*num_words); \
3434 return COSTS_N_INSNS (6); \
3437 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3442 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3443 return COSTS_N_INSNS (2); \
3450 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3451 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3457 enum machine_mode xmode = GET_MODE (X); \
3458 if (xmode == SFmode || xmode == DFmode) \
3459 return COSTS_N_INSNS (1); \
3461 return COSTS_N_INSNS (4); \
3467 enum machine_mode xmode = GET_MODE (X); \
3468 if (xmode == SFmode || xmode == DFmode) \
3472 return COSTS_N_INSNS (2); \
3473 else if (TUNE_MIPS6000) \
3474 return COSTS_N_INSNS (3); \
3476 return COSTS_N_INSNS (6); \
3479 if (xmode == DImode && !TARGET_64BIT) \
3480 return COSTS_N_INSNS (4); \
3486 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3493 enum machine_mode xmode = GET_MODE (X); \
3494 if (xmode == SFmode) \
3499 return COSTS_N_INSNS (4); \
3500 else if (TUNE_MIPS6000) \
3501 return COSTS_N_INSNS (5); \
3503 return COSTS_N_INSNS (7); \
3506 if (xmode == DFmode) \
3511 return COSTS_N_INSNS (5); \
3512 else if (TUNE_MIPS6000) \
3513 return COSTS_N_INSNS (6); \
3515 return COSTS_N_INSNS (8); \
3518 if (TUNE_MIPS3000) \
3519 return COSTS_N_INSNS (12); \
3520 else if (TUNE_MIPS3900) \
3521 return COSTS_N_INSNS (2); \
3522 else if (TUNE_MIPS6000) \
3523 return COSTS_N_INSNS (17); \
3524 else if (TUNE_MIPS5000) \
3525 return COSTS_N_INSNS (5); \
3527 return COSTS_N_INSNS (10); \
3533 enum machine_mode xmode = GET_MODE (X); \
3534 if (xmode == SFmode) \
3538 return COSTS_N_INSNS (12); \
3539 else if (TUNE_MIPS6000) \
3540 return COSTS_N_INSNS (15); \
3542 return COSTS_N_INSNS (23); \
3545 if (xmode == DFmode) \
3549 return COSTS_N_INSNS (19); \
3550 else if (TUNE_MIPS6000) \
3551 return COSTS_N_INSNS (16); \
3553 return COSTS_N_INSNS (36); \
3556 /* fall through */ \
3562 return COSTS_N_INSNS (35); \
3563 else if (TUNE_MIPS6000) \
3564 return COSTS_N_INSNS (38); \
3565 else if (TUNE_MIPS5000) \
3566 return COSTS_N_INSNS (36); \
3568 return COSTS_N_INSNS (69); \
3571 /* A sign extend from SImode to DImode in 64 bit mode is often \
3572 zero instructions, because the result can often be used \
3573 directly by another instruction; we'll call it one. */ \
3574 if (TARGET_64BIT && GET_MODE (X) == DImode \
3575 && GET_MODE (XEXP (X, 0)) == SImode) \
3576 return COSTS_N_INSNS (1); \
3578 return COSTS_N_INSNS (2); \
3581 if (TARGET_64BIT && GET_MODE (X) == DImode \
3582 && GET_MODE (XEXP (X, 0)) == SImode) \
3583 return COSTS_N_INSNS (2); \
3585 return COSTS_N_INSNS (1);
3587 /* An expression giving the cost of an addressing mode that
3588 contains ADDRESS. If not defined, the cost is computed from the
3589 form of the ADDRESS expression and the `CONST_COSTS' values.
3591 For most CISC machines, the default cost is a good approximation
3592 of the true cost of the addressing mode. However, on RISC
3593 machines, all instructions normally have the same length and
3594 execution time. Hence all addresses will have equal costs.
3596 In cases where more than one form of an address is known, the
3597 form with the lowest cost will be used. If multiple forms have
3598 the same, lowest, cost, the one that is the most complex will be
3601 For example, suppose an address that is equal to the sum of a
3602 register and a constant is used twice in the same basic block.
3603 When this macro is not defined, the address will be computed in
3604 a register and memory references will be indirect through that
3605 register. On machines where the cost of the addressing mode
3606 containing the sum is no higher than that of a simple indirect
3607 reference, this will produce an additional instruction and
3608 possibly require an additional register. Proper specification
3609 of this macro eliminates this overhead for such machines.
3611 Similar use of this macro is made in strength reduction of loops.
3613 ADDRESS need not be valid as an address. In such a case, the
3614 cost is not relevant and can be any value; invalid addresses
3615 need not be assigned a different cost.
3617 On machines where an address involving more than one register is
3618 as cheap as an address computation involving only one register,
3619 defining `ADDRESS_COST' to reflect this can cause two registers
3620 to be live over a region of code where only one would have been
3621 if `ADDRESS_COST' were not defined in that manner. This effect
3622 should be considered in the definition of this macro.
3623 Equivalent costs should probably only be given to addresses with
3624 different numbers of registers on machines with lots of registers.
3626 This macro will normally either not be defined or be defined as
3629 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3631 /* A C expression for the cost of moving data from a register in
3632 class FROM to one in class TO. The classes are expressed using
3633 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3634 the default; other values are interpreted relative to that.
3636 It is not required that the cost always equal 2 when FROM is the
3637 same as TO; on some machines it is expensive to move between
3638 registers if they are not general registers.
3640 If reload sees an insn consisting of a single `set' between two
3641 hard registers, and if `REGISTER_MOVE_COST' applied to their
3642 classes returns a value of 2, reload does not check to ensure
3643 that the constraints of the insn are met. Setting a cost of
3644 other than 2 will allow reload to verify that the constraints are
3645 met. You should do this if the `movM' pattern's constraints do
3646 not allow such copying.
3648 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3649 registers the same as for one of moving general registers to
3650 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3651 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3652 isn't clear if it is wise. And it might not work in all cases. We
3653 could solve the DImode LO reg problem by using a multiply, just like
3654 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3655 by using divide instructions. divu puts the remainder in the HI
3656 reg, so doing a divide by -1 will move the value in the HI reg for
3657 all values except -1. We could handle that case by using a signed
3658 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3659 compare/branch to test the input value to see which instruction we
3660 need to use. This gets pretty messy, but it is feasible. */
3662 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3663 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3664 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3665 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3666 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3667 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3668 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3669 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3670 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3671 : (((FROM) == HI_REG || (FROM) == LO_REG \
3672 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3673 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3674 : (((TO) == HI_REG || (TO) == LO_REG \
3675 || (TO) == MD_REGS || (TO) == HILO_REG) \
3676 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3677 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3678 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3681 /* ??? Fix this to be right for the R8000. */
3682 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3683 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3684 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3686 /* Define if copies to/from condition code registers should be avoided.
3688 This is needed for the MIPS because reload_outcc is not complete;
3689 it needs to handle cases where the source is a general or another
3690 condition code register. */
3691 #define AVOID_CCMODE_COPIES
3693 /* A C expression for the cost of a branch instruction. A value of
3694 1 is the default; other values are interpreted relative to that. */
3696 /* ??? Fix this to be right for the R8000. */
3697 #define BRANCH_COST \
3699 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3702 /* A C statement (sans semicolon) to update the integer variable COST
3703 based on the relationship between INSN that is dependent on
3704 DEP_INSN through the dependence LINK. The default is to make no
3705 adjustment to COST. On the MIPS, ignore the cost of anti- and
3706 output-dependencies. */
3708 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3709 if (REG_NOTE_KIND (LINK) != 0) \
3710 (COST) = 0; /* Anti or output dependence. */
3712 /* If defined, modifies the length assigned to instruction INSN as a
3713 function of the context in which it is used. LENGTH is an lvalue
3714 that contains the initially computed length of the insn and should
3715 be updated with the correct length of the insn. */
3716 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3717 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3720 /* Optionally define this if you have added predicates to
3721 `MACHINE.c'. This macro is called within an initializer of an
3722 array of structures. The first field in the structure is the
3723 name of a predicate and the second field is an array of rtl
3724 codes. For each predicate, list all rtl codes that can be in
3725 expressions matched by the predicate. The list should have a
3726 trailing comma. Here is an example of two entries in the list
3727 for a typical RISC machine:
3729 #define PREDICATE_CODES \
3730 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3731 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3733 Defining this macro does not affect the generated code (however,
3734 incorrect definitions that omit an rtl code that may be matched
3735 by the predicate can cause the compiler to malfunction).
3736 Instead, it allows the table built by `genrecog' to be more
3737 compact and efficient, thus speeding up the compiler. The most
3738 important predicates to include in the list specified by this
3739 macro are thoses used in the most insn patterns. */
3741 #define PREDICATE_CODES \
3742 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3743 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3744 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3745 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3746 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3747 {"small_int", { CONST_INT }}, \
3748 {"large_int", { CONST_INT }}, \
3749 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3750 {"const_float_1_operand", { CONST_DOUBLE }}, \
3751 {"simple_memory_operand", { MEM, SUBREG }}, \
3752 {"equality_op", { EQ, NE }}, \
3753 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3755 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3756 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3757 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3758 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3759 SYMBOL_REF, LABEL_REF, SUBREG, \
3761 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3762 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3763 MEM, SIGN_EXTEND }}, \
3764 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3765 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3767 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3769 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3771 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3772 SYMBOL_REF, LABEL_REF, SUBREG, \
3773 REG, SIGN_EXTEND }}, \
3774 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3775 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3776 CONST_DOUBLE, CONST }}, \
3777 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3778 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3780 /* A list of predicates that do special things with modes, and so
3781 should not elicit warnings for VOIDmode match_operand. */
3783 #define SPECIAL_MODE_PREDICATES \
3784 "pc_or_label_operand",
3787 /* If defined, a C statement to be executed just prior to the
3788 output of assembler code for INSN, to modify the extracted
3789 operands so they will be output differently.
3791 Here the argument OPVEC is the vector containing the operands
3792 extracted from INSN, and NOPERANDS is the number of elements of
3793 the vector which contain meaningful data for this insn. The
3794 contents of this vector are what will be used to convert the
3795 insn template into assembler code, so you can change the
3796 assembler output by changing the contents of the vector.
3798 We use it to check if the current insn needs a nop in front of it
3799 because of load delays, and also to update the delay slot
3802 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3803 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3806 /* Control the assembler format that we output. */
3808 /* Output at beginning of assembler file.
3809 If we are optimizing to use the global pointer, create a temporary
3810 file to hold all of the text stuff, and write it out to the end.
3811 This is needed because the MIPS assembler is evidently one pass,
3812 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3813 declaration when the code is processed, it generates a two
3814 instruction sequence. */
3816 #undef ASM_FILE_START
3817 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3819 /* Output to assembler file text saying following lines
3820 may contain character constants, extra white space, comments, etc. */
3822 #define ASM_APP_ON " #APP\n"
3824 /* Output to assembler file text saying following lines
3825 no longer contain unusual constructs. */
3827 #define ASM_APP_OFF " #NO_APP\n"
3829 /* How to refer to registers in assembler output.
3830 This sequence is indexed by compiler's hard-register-number (see above).
3832 In order to support the two different conventions for register names,
3833 we use the name of a table set up in mips.c, which is overwritten
3834 if -mrnames is used. */
3836 #define REGISTER_NAMES \
3838 &mips_reg_names[ 0][0], \
3839 &mips_reg_names[ 1][0], \
3840 &mips_reg_names[ 2][0], \
3841 &mips_reg_names[ 3][0], \
3842 &mips_reg_names[ 4][0], \
3843 &mips_reg_names[ 5][0], \
3844 &mips_reg_names[ 6][0], \
3845 &mips_reg_names[ 7][0], \
3846 &mips_reg_names[ 8][0], \
3847 &mips_reg_names[ 9][0], \
3848 &mips_reg_names[10][0], \
3849 &mips_reg_names[11][0], \
3850 &mips_reg_names[12][0], \
3851 &mips_reg_names[13][0], \
3852 &mips_reg_names[14][0], \
3853 &mips_reg_names[15][0], \
3854 &mips_reg_names[16][0], \
3855 &mips_reg_names[17][0], \
3856 &mips_reg_names[18][0], \
3857 &mips_reg_names[19][0], \
3858 &mips_reg_names[20][0], \
3859 &mips_reg_names[21][0], \
3860 &mips_reg_names[22][0], \
3861 &mips_reg_names[23][0], \
3862 &mips_reg_names[24][0], \
3863 &mips_reg_names[25][0], \
3864 &mips_reg_names[26][0], \
3865 &mips_reg_names[27][0], \
3866 &mips_reg_names[28][0], \
3867 &mips_reg_names[29][0], \
3868 &mips_reg_names[30][0], \
3869 &mips_reg_names[31][0], \
3870 &mips_reg_names[32][0], \
3871 &mips_reg_names[33][0], \
3872 &mips_reg_names[34][0], \
3873 &mips_reg_names[35][0], \
3874 &mips_reg_names[36][0], \
3875 &mips_reg_names[37][0], \
3876 &mips_reg_names[38][0], \
3877 &mips_reg_names[39][0], \
3878 &mips_reg_names[40][0], \
3879 &mips_reg_names[41][0], \
3880 &mips_reg_names[42][0], \
3881 &mips_reg_names[43][0], \
3882 &mips_reg_names[44][0], \
3883 &mips_reg_names[45][0], \
3884 &mips_reg_names[46][0], \
3885 &mips_reg_names[47][0], \
3886 &mips_reg_names[48][0], \
3887 &mips_reg_names[49][0], \
3888 &mips_reg_names[50][0], \
3889 &mips_reg_names[51][0], \
3890 &mips_reg_names[52][0], \
3891 &mips_reg_names[53][0], \
3892 &mips_reg_names[54][0], \
3893 &mips_reg_names[55][0], \
3894 &mips_reg_names[56][0], \
3895 &mips_reg_names[57][0], \
3896 &mips_reg_names[58][0], \
3897 &mips_reg_names[59][0], \
3898 &mips_reg_names[60][0], \
3899 &mips_reg_names[61][0], \
3900 &mips_reg_names[62][0], \
3901 &mips_reg_names[63][0], \
3902 &mips_reg_names[64][0], \
3903 &mips_reg_names[65][0], \
3904 &mips_reg_names[66][0], \
3905 &mips_reg_names[67][0], \
3906 &mips_reg_names[68][0], \
3907 &mips_reg_names[69][0], \
3908 &mips_reg_names[70][0], \
3909 &mips_reg_names[71][0], \
3910 &mips_reg_names[72][0], \
3911 &mips_reg_names[73][0], \
3912 &mips_reg_names[74][0], \
3913 &mips_reg_names[75][0], \
3916 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3917 So define this for it. */
3918 #define DEBUG_REGISTER_NAMES \
3920 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3921 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3922 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3923 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3924 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3925 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3926 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3927 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3928 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3929 "$fcc5","$fcc6","$fcc7","$rap" \
3932 /* If defined, a C initializer for an array of structures
3933 containing a name and a register number. This macro defines
3934 additional names for hard registers, thus allowing the `asm'
3935 option in declarations to refer to registers using alternate
3938 We define both names for the integer registers here. */
3940 #define ADDITIONAL_REGISTER_NAMES \
3942 { "$0", 0 + GP_REG_FIRST }, \
3943 { "$1", 1 + GP_REG_FIRST }, \
3944 { "$2", 2 + GP_REG_FIRST }, \
3945 { "$3", 3 + GP_REG_FIRST }, \
3946 { "$4", 4 + GP_REG_FIRST }, \
3947 { "$5", 5 + GP_REG_FIRST }, \
3948 { "$6", 6 + GP_REG_FIRST }, \
3949 { "$7", 7 + GP_REG_FIRST }, \
3950 { "$8", 8 + GP_REG_FIRST }, \
3951 { "$9", 9 + GP_REG_FIRST }, \
3952 { "$10", 10 + GP_REG_FIRST }, \
3953 { "$11", 11 + GP_REG_FIRST }, \
3954 { "$12", 12 + GP_REG_FIRST }, \
3955 { "$13", 13 + GP_REG_FIRST }, \
3956 { "$14", 14 + GP_REG_FIRST }, \
3957 { "$15", 15 + GP_REG_FIRST }, \
3958 { "$16", 16 + GP_REG_FIRST }, \
3959 { "$17", 17 + GP_REG_FIRST }, \
3960 { "$18", 18 + GP_REG_FIRST }, \
3961 { "$19", 19 + GP_REG_FIRST }, \
3962 { "$20", 20 + GP_REG_FIRST }, \
3963 { "$21", 21 + GP_REG_FIRST }, \
3964 { "$22", 22 + GP_REG_FIRST }, \
3965 { "$23", 23 + GP_REG_FIRST }, \
3966 { "$24", 24 + GP_REG_FIRST }, \
3967 { "$25", 25 + GP_REG_FIRST }, \
3968 { "$26", 26 + GP_REG_FIRST }, \
3969 { "$27", 27 + GP_REG_FIRST }, \
3970 { "$28", 28 + GP_REG_FIRST }, \
3971 { "$29", 29 + GP_REG_FIRST }, \
3972 { "$30", 30 + GP_REG_FIRST }, \
3973 { "$31", 31 + GP_REG_FIRST }, \
3974 { "$sp", 29 + GP_REG_FIRST }, \
3975 { "$fp", 30 + GP_REG_FIRST }, \
3976 { "at", 1 + GP_REG_FIRST }, \
3977 { "v0", 2 + GP_REG_FIRST }, \
3978 { "v1", 3 + GP_REG_FIRST }, \
3979 { "a0", 4 + GP_REG_FIRST }, \
3980 { "a1", 5 + GP_REG_FIRST }, \
3981 { "a2", 6 + GP_REG_FIRST }, \
3982 { "a3", 7 + GP_REG_FIRST }, \
3983 { "t0", 8 + GP_REG_FIRST }, \
3984 { "t1", 9 + GP_REG_FIRST }, \
3985 { "t2", 10 + GP_REG_FIRST }, \
3986 { "t3", 11 + GP_REG_FIRST }, \
3987 { "t4", 12 + GP_REG_FIRST }, \
3988 { "t5", 13 + GP_REG_FIRST }, \
3989 { "t6", 14 + GP_REG_FIRST }, \
3990 { "t7", 15 + GP_REG_FIRST }, \
3991 { "s0", 16 + GP_REG_FIRST }, \
3992 { "s1", 17 + GP_REG_FIRST }, \
3993 { "s2", 18 + GP_REG_FIRST }, \
3994 { "s3", 19 + GP_REG_FIRST }, \
3995 { "s4", 20 + GP_REG_FIRST }, \
3996 { "s5", 21 + GP_REG_FIRST }, \
3997 { "s6", 22 + GP_REG_FIRST }, \
3998 { "s7", 23 + GP_REG_FIRST }, \
3999 { "t8", 24 + GP_REG_FIRST }, \
4000 { "t9", 25 + GP_REG_FIRST }, \
4001 { "k0", 26 + GP_REG_FIRST }, \
4002 { "k1", 27 + GP_REG_FIRST }, \
4003 { "gp", 28 + GP_REG_FIRST }, \
4004 { "sp", 29 + GP_REG_FIRST }, \
4005 { "fp", 30 + GP_REG_FIRST }, \
4006 { "ra", 31 + GP_REG_FIRST }, \
4007 { "$sp", 29 + GP_REG_FIRST }, \
4008 { "$fp", 30 + GP_REG_FIRST } \
4011 /* A C compound statement to output to stdio stream STREAM the
4012 assembler syntax for an instruction operand X. X is an RTL
4015 CODE is a value that can be used to specify one of several ways
4016 of printing the operand. It is used when identical operands
4017 must be printed differently depending on the context. CODE
4018 comes from the `%' specification that was used to request
4019 printing of the operand. If the specification was just `%DIGIT'
4020 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4021 is the ASCII code for LTR.
4023 If X is a register, this macro should print the register's name.
4024 The names can be found in an array `reg_names' whose type is
4025 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4027 When the machine description has a specification `%PUNCT' (a `%'
4028 followed by a punctuation character), this macro is called with
4029 a null pointer for X and the punctuation character for CODE.
4031 See mips.c for the MIPS specific codes. */
4033 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4035 /* A C expression which evaluates to true if CODE is a valid
4036 punctuation character for use in the `PRINT_OPERAND' macro. If
4037 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4038 punctuation characters (except for the standard one, `%') are
4039 used in this way. */
4041 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4043 /* A C compound statement to output to stdio stream STREAM the
4044 assembler syntax for an instruction operand that is a memory
4045 reference whose address is ADDR. ADDR is an RTL expression.
4047 On some machines, the syntax for a symbolic address depends on
4048 the section that the address refers to. On these machines,
4049 define the macro `ENCODE_SECTION_INFO' to store the information
4050 into the `symbol_ref', and then check for it here. */
4052 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4055 /* A C statement, to be executed after all slot-filler instructions
4056 have been output. If necessary, call `dbr_sequence_length' to
4057 determine the number of slots filled in a sequence (zero if not
4058 currently outputting a sequence), to decide how many no-ops to
4059 output, or whatever.
4061 Don't define this macro if it has nothing to do, but it is
4062 helpful in reading assembly output if the extent of the delay
4063 sequence is made explicit (e.g. with white space).
4065 Note that output routines for instructions with delay slots must
4066 be prepared to deal with not being output as part of a sequence
4067 (i.e. when the scheduling pass is not run, or when no slot
4068 fillers could be found.) The variable `final_sequence' is null
4069 when not processing a sequence, otherwise it contains the
4070 `sequence' rtx being output. */
4072 #define DBR_OUTPUT_SEQEND(STREAM) \
4075 if (set_nomacro > 0 && --set_nomacro == 0) \
4076 fputs ("\t.set\tmacro\n", STREAM); \
4078 if (set_noreorder > 0 && --set_noreorder == 0) \
4079 fputs ("\t.set\treorder\n", STREAM); \
4081 dslots_jump_filled++; \
4082 fputs ("\n", STREAM); \
4087 /* How to tell the debugger about changes of source files. Note, the
4088 mips ECOFF format cannot deal with changes of files inside of
4089 functions, which means the output of parser generators like bison
4090 is generally not debuggable without using the -l switch. Lose,
4091 lose, lose. Silicon graphics seems to want all .file's hardwired
4094 #ifndef SET_FILE_NUMBER
4095 #define SET_FILE_NUMBER() ++num_source_filenames
4098 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4099 mips_output_filename (STREAM, NAME)
4101 /* This is defined so that it can be overridden in iris6.h. */
4102 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4105 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4106 output_quoted_string (STREAM, NAME); \
4107 fputs ("\n", STREAM); \
4111 /* This is how to output a note the debugger telling it the line number
4112 to which the following sequence of instructions corresponds.
4113 Silicon graphics puts a label after each .loc. */
4115 #ifndef LABEL_AFTER_LOC
4116 #define LABEL_AFTER_LOC(STREAM)
4119 #undef ASM_OUTPUT_SOURCE_LINE
4120 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4121 mips_output_lineno (STREAM, LINE)
4123 /* The MIPS implementation uses some labels for its own purpose. The
4124 following lists what labels are created, and are all formed by the
4125 pattern $L[a-z].*. The machine independent portion of GCC creates
4126 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4128 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4129 $Lb[0-9]+ Begin blocks for MIPS debug support
4130 $Lc[0-9]+ Label for use in s<xx> operation.
4131 $Le[0-9]+ End blocks for MIPS debug support
4132 $Lp\..+ Half-pic labels. */
4134 /* This is how to output the definition of a user-level label named NAME,
4135 such as the label on a static function or variable NAME.
4137 If we are optimizing the gp, remember that this label has been put
4138 out, so we know not to emit an .extern for it in mips_asm_file_end.
4139 We use one of the common bits in the IDENTIFIER tree node for this,
4140 since those bits seem to be unused, and we don't have any method
4141 of getting the decl nodes from the name. */
4143 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4145 assemble_name (STREAM, NAME); \
4146 fputs (":\n", STREAM); \
4150 /* A C statement (sans semicolon) to output to the stdio stream
4151 STREAM any text necessary for declaring the name NAME of an
4152 initialized variable which is being defined. This macro must
4153 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4154 The argument DECL is the `VAR_DECL' tree node representing the
4157 If this macro is not defined, then the variable name is defined
4158 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4160 #undef ASM_DECLARE_OBJECT_NAME
4161 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4164 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4165 HALF_PIC_DECLARE (NAME); \
4170 /* This is how to output a command to make the user-level label named NAME
4171 defined for reference from other files. */
4173 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4175 fputs ("\t.globl\t", STREAM); \
4176 assemble_name (STREAM, NAME); \
4177 fputs ("\n", STREAM); \
4180 /* This says how to define a global common symbol. */
4182 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4184 /* If the target wants uninitialized const declarations in \
4185 .rdata then don't put them in .comm */ \
4186 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4187 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4188 && (DECL_INITIAL (DECL) == 0 \
4189 || DECL_INITIAL (DECL) == error_mark_node)) \
4191 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4192 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4194 READONLY_DATA_SECTION (); \
4195 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4196 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4200 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4205 /* This says how to define a local common symbol (ie, not visible to
4208 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4209 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4212 /* This says how to output an external. It would be possible not to
4213 output anything and let undefined symbol become external. However
4214 the assembler uses length information on externals to allocate in
4215 data/sdata bss/sbss, thereby saving exec time. */
4217 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4218 mips_output_external(STREAM,DECL,NAME)
4220 /* This says what to print at the end of the assembly file */
4222 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4225 /* This is how to declare a function name. The actual work of
4226 emitting the label is moved to function_prologue, so that we can
4227 get the line number correctly emitted before the .ent directive,
4228 and after any .file directives.
4230 Also, switch files if we are optimizing the global pointer. */
4232 #undef ASM_DECLARE_FUNCTION_NAME
4233 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4235 extern FILE *asm_out_text_file; \
4236 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4238 STREAM = asm_out_text_file; \
4239 /* ??? text_section gets called too soon. If the previous \
4240 function is in a special section and we're not, we have \
4241 to switch back to the text section. We can't call \
4242 text_section again as gcc thinks we're already there. */ \
4243 /* ??? See varasm.c. There are other things that get output \
4244 too early, like alignment (before we've switched STREAM). */ \
4245 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4246 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4249 HALF_PIC_DECLARE (NAME); \
4252 /* This is how to output an internal numbered label where
4253 PREFIX is the class of label and NUM is the number within the class. */
4255 #undef ASM_OUTPUT_INTERNAL_LABEL
4256 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4257 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4259 /* This is how to store into the string LABEL
4260 the symbol_ref name of an internal numbered label where
4261 PREFIX is the class of label and NUM is the number within the class.
4262 This is suitable for output with `assemble_name'. */
4264 #undef ASM_GENERATE_INTERNAL_LABEL
4265 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4266 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4268 /* This is how to output an assembler line defining a `double' constant. */
4270 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4271 mips_output_double (STREAM, VALUE)
4274 /* This is how to output an assembler line defining a `float' constant. */
4276 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4277 mips_output_float (STREAM, VALUE)
4280 /* This is how to output an assembler line defining an `int' constant. */
4282 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4284 fprintf (STREAM, "\t.word\t"); \
4285 output_addr_const (STREAM, (VALUE)); \
4286 fprintf (STREAM, "\n"); \
4289 /* Likewise for 64 bit, `char' and `short' constants.
4291 FIXME: operand_subword can't handle some complex constant expressions
4292 that output_addr_const can (for example it does not call
4293 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4294 rely on that to avoid operand_subword for most of the cases where this
4295 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4296 or the same case with the type of 'i' changed to long long.
4300 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4302 if (TARGET_64BIT || TARGET_GAS) \
4304 fprintf (STREAM, "\t.dword\t"); \
4305 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4306 /* We can't use 'X' for negative numbers, because then we won't \
4307 get the right value for the upper 32 bits. */ \
4308 output_addr_const (STREAM, VALUE); \
4310 /* We must use 'X', because otherwise LONG_MIN will print as \
4311 a number that the Irix 6 assembler won't accept. */ \
4312 print_operand (STREAM, VALUE, 'X'); \
4313 fprintf (STREAM, "\n"); \
4317 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4318 UNITS_PER_WORD, 1); \
4319 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4320 UNITS_PER_WORD, 1); \
4324 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4326 fprintf (STREAM, "\t.half\t"); \
4327 output_addr_const (STREAM, (VALUE)); \
4328 fprintf (STREAM, "\n"); \
4331 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4333 fprintf (STREAM, "\t.byte\t"); \
4334 output_addr_const (STREAM, (VALUE)); \
4335 fprintf (STREAM, "\n"); \
4338 /* This is how to output an assembler line for a numeric constant byte. */
4340 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4341 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4343 /* This is how to output an element of a case-vector that is absolute. */
4345 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4346 fprintf (STREAM, "\t%s\t%sL%d\n", \
4347 Pmode == DImode ? ".dword" : ".word", \
4348 LOCAL_LABEL_PREFIX, \
4351 /* This is how to output an element of a case-vector that is relative.
4352 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4353 TARGET_EMBEDDED_PIC). */
4355 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4357 if (TARGET_MIPS16) \
4358 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4359 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4360 else if (TARGET_EMBEDDED_PIC) \
4361 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4362 Pmode == DImode ? ".dword" : ".word", \
4363 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4364 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4365 fprintf (STREAM, "\t%s\t%sL%d\n", \
4366 Pmode == DImode ? ".gpdword" : ".gpword", \
4367 LOCAL_LABEL_PREFIX, VALUE); \
4369 fprintf (STREAM, "\t%s\t%sL%d\n", \
4370 Pmode == DImode ? ".dword" : ".word", \
4371 LOCAL_LABEL_PREFIX, VALUE); \
4374 /* When generating embedded PIC or mips16 code we want to put the jump
4375 table in the .text section. In all other cases, we want to put the
4376 jump table in the .rdata section. Unfortunately, we can't use
4377 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4378 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4379 section if appropriate. */
4380 #undef ASM_OUTPUT_CASE_LABEL
4381 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4383 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4384 function_section (current_function_decl); \
4385 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4388 /* This is how to output an assembler line
4389 that says to advance the location counter
4390 to a multiple of 2**LOG bytes. */
4392 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4393 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4395 /* This is how to output an assembler line to advance the location
4396 counter by SIZE bytes. */
4398 #undef ASM_OUTPUT_SKIP
4399 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4400 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4402 /* This is how to output a string. */
4403 #undef ASM_OUTPUT_ASCII
4404 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4405 mips_output_ascii (STREAM, STRING, LEN)
4407 /* Handle certain cpp directives used in header files on sysV. */
4408 #define SCCS_DIRECTIVE
4410 /* Output #ident as a in the read-only data section. */
4411 #undef ASM_OUTPUT_IDENT
4412 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4414 const char *p = STRING; \
4415 int size = strlen (p) + 1; \
4417 assemble_string (p, size); \
4420 /* Default to -G 8 */
4421 #ifndef MIPS_DEFAULT_GVALUE
4422 #define MIPS_DEFAULT_GVALUE 8
4425 /* Define the strings to put out for each section in the object file. */
4426 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4427 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4428 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4429 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4430 #undef READONLY_DATA_SECTION
4431 #define READONLY_DATA_SECTION rdata_section
4432 #define SMALL_DATA_SECTION sdata_section
4434 /* What other sections we support other than the normal .data/.text. */
4436 #undef EXTRA_SECTIONS
4437 #define EXTRA_SECTIONS in_sdata, in_rdata
4439 /* Define the additional functions to select our additional sections. */
4441 /* on the MIPS it is not a good idea to put constants in the text
4442 section, since this defeats the sdata/data mechanism. This is
4443 especially true when -O is used. In this case an effort is made to
4444 address with faster (gp) register relative addressing, which can
4445 only get at sdata and sbss items (there is no stext !!) However,
4446 if the constant is too large for sdata, and it's readonly, it
4447 will go into the .rdata section. */
4449 #undef EXTRA_SECTION_FUNCTIONS
4450 #define EXTRA_SECTION_FUNCTIONS \
4454 if (in_section != in_sdata) \
4456 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4457 in_section = in_sdata; \
4464 if (in_section != in_rdata) \
4466 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4467 in_section = in_rdata; \
4471 /* Given a decl node or constant node, choose the section to output it in
4472 and select that section. */
4474 #undef SELECT_RTX_SECTION
4475 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4477 #undef SELECT_SECTION
4478 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4481 /* Store in OUTPUT a string (made with alloca) containing
4482 an assembler-name for a local static variable named NAME.
4483 LABELNO is an integer which is different for each call. */
4485 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4486 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4487 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4489 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4492 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4493 TARGET_64BIT ? "dsubu" : "subu", \
4494 reg_names[STACK_POINTER_REGNUM], \
4495 reg_names[STACK_POINTER_REGNUM], \
4496 TARGET_64BIT ? "sd" : "sw", \
4498 reg_names[STACK_POINTER_REGNUM]); \
4502 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4505 if (! set_noreorder) \
4506 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4508 dslots_load_total++; \
4509 dslots_load_filled++; \
4510 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4511 TARGET_64BIT ? "ld" : "lw", \
4513 reg_names[STACK_POINTER_REGNUM], \
4514 TARGET_64BIT ? "daddu" : "addu", \
4515 reg_names[STACK_POINTER_REGNUM], \
4516 reg_names[STACK_POINTER_REGNUM]); \
4518 if (! set_noreorder) \
4519 fprintf (STREAM, "\t.set\treorder\n"); \
4523 /* Define the parentheses used to group arithmetic operations
4524 in assembler code. */
4526 #define ASM_OPEN_PAREN "("
4527 #define ASM_CLOSE_PAREN ")"
4529 /* How to start an assembler comment.
4530 The leading space is important (the mips native assembler requires it). */
4531 #ifndef ASM_COMMENT_START
4532 #define ASM_COMMENT_START " #"
4536 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4537 and mips-tdump.c to print them out.
4539 These must match the corresponding definitions in gdb/mipsread.c.
4540 Unfortunately, gcc and gdb do not currently share any directories. */
4542 #define CODE_MASK 0x8F300
4543 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4544 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4545 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4548 /* Default definitions for size_t and ptrdiff_t. */
4551 #define NO_BUILTIN_SIZE_TYPE
4552 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4555 #ifndef PTRDIFF_TYPE
4556 #define NO_BUILTIN_PTRDIFF_TYPE
4557 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4560 /* See mips_expand_prologue's use of loadgp for when this should be
4563 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4564 && mips_abi != ABI_32 \
4565 && mips_abi != ABI_O64)
4567 /* In mips16 mode, we need to look through the function to check for
4568 PC relative loads that are out of range. */
4569 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4571 /* We need to use a special set of functions to handle hard floating
4572 point code in mips16 mode. */
4574 #ifndef INIT_SUBTARGET_OPTABS
4575 #define INIT_SUBTARGET_OPTABS
4578 #define INIT_TARGET_OPTABS \
4581 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4582 INIT_SUBTARGET_OPTABS; \
4585 add_optab->handlers[(int) SFmode].libfunc = \
4586 init_one_libfunc ("__mips16_addsf3"); \
4587 sub_optab->handlers[(int) SFmode].libfunc = \
4588 init_one_libfunc ("__mips16_subsf3"); \
4589 smul_optab->handlers[(int) SFmode].libfunc = \
4590 init_one_libfunc ("__mips16_mulsf3"); \
4591 flodiv_optab->handlers[(int) SFmode].libfunc = \
4592 init_one_libfunc ("__mips16_divsf3"); \
4594 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4595 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4596 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4597 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4598 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4599 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4601 floatsisf_libfunc = \
4602 init_one_libfunc ("__mips16_floatsisf"); \
4604 init_one_libfunc ("__mips16_fixsfsi"); \
4606 if (TARGET_DOUBLE_FLOAT) \
4608 add_optab->handlers[(int) DFmode].libfunc = \
4609 init_one_libfunc ("__mips16_adddf3"); \
4610 sub_optab->handlers[(int) DFmode].libfunc = \
4611 init_one_libfunc ("__mips16_subdf3"); \
4612 smul_optab->handlers[(int) DFmode].libfunc = \
4613 init_one_libfunc ("__mips16_muldf3"); \
4614 flodiv_optab->handlers[(int) DFmode].libfunc = \
4615 init_one_libfunc ("__mips16_divdf3"); \
4617 extendsfdf2_libfunc = \
4618 init_one_libfunc ("__mips16_extendsfdf2"); \
4619 truncdfsf2_libfunc = \
4620 init_one_libfunc ("__mips16_truncdfsf2"); \
4623 init_one_libfunc ("__mips16_eqdf2"); \
4625 init_one_libfunc ("__mips16_nedf2"); \
4627 init_one_libfunc ("__mips16_gtdf2"); \
4629 init_one_libfunc ("__mips16_gedf2"); \
4631 init_one_libfunc ("__mips16_ltdf2"); \
4633 init_one_libfunc ("__mips16_ledf2"); \
4635 floatsidf_libfunc = \
4636 init_one_libfunc ("__mips16_floatsidf"); \
4638 init_one_libfunc ("__mips16_fixdfsi"); \
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