1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern const char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_arch; /* which cpu to codegen for */
137 extern enum processor_type mips_tune; /* which cpu to schedule for */
138 extern enum processor_type mips_cpu; /* historical codegen/sched */
139 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
140 extern int mips_isa; /* architectural level */
141 extern int mips16; /* whether generating mips16 code */
142 extern int mips16_hard_float; /* mips16 without -msoft-float */
143 extern int mips_entry; /* generate entry/exit for mips16 */
144 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
145 extern const char *mips_arch_string; /* for -march=<xxx> */
146 extern const char *mips_tune_string; /* for -mtune=<xxx> */
147 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
148 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
149 extern const char *mips_entry_string; /* for -mentry */
150 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
151 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
152 extern int mips_split_addresses; /* perform high/lo_sum support */
153 extern int dslots_load_total; /* total # load related delay slots */
154 extern int dslots_load_filled; /* # filled load delay slots */
155 extern int dslots_jump_total; /* total # jump related delay slots */
156 extern int dslots_jump_filled; /* # filled jump delay slots */
157 extern int dslots_number_nops; /* # of nops needed by previous insn */
158 extern int num_refs[3]; /* # 1/2/3 word references */
159 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
160 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
161 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
162 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
163 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
164 extern int mips_string_length; /* length of strings for mips16 */
165 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
167 /* Functions to change what output section we are using. */
168 extern void rdata_section PARAMS ((void));
169 extern void sdata_section PARAMS ((void));
170 extern void sbss_section PARAMS ((void));
172 /* Stubs for half-pic support if not OSF/1 reference platform. */
175 #define HALF_PIC_P() 0
176 #define HALF_PIC_NUMBER_PTRS 0
177 #define HALF_PIC_NUMBER_REFS 0
178 #define HALF_PIC_ENCODE(DECL)
179 #define HALF_PIC_DECLARE(NAME)
180 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
181 #define HALF_PIC_ADDRESS_P(X) 0
182 #define HALF_PIC_PTR(X) X
183 #define HALF_PIC_FINISH(STREAM)
186 /* Macros to silence warnings about numbers being signed in traditional
187 C and unsigned in ISO C when compiled on 32-bit hosts. */
189 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
190 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
191 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
194 /* Run-time compilation parameters selecting different hardware subsets. */
196 /* Macros used in the machine description to test the flags. */
198 /* Bits for real switches */
199 #define MASK_INT64 0x00000001 /* ints are 64 bits */
200 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
201 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
202 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
203 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
204 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
205 #define MASK_STATS 0x00000040 /* print statistics to stderr */
206 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
207 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
208 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
209 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
210 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
211 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
212 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
213 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
214 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
215 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
216 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
217 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
218 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
219 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
220 #define MASK_NO_CHECK_ZERO_DIV \
221 0x00200000 /* divide by zero checking */
222 #define MASK_CHECK_RANGE_DIV \
223 0x00400000 /* divide result range checking */
224 #define MASK_UNINIT_CONST_IN_RODATA \
225 0x00800000 /* Store uninitialized
228 /* Debug switches, not documented */
229 #define MASK_DEBUG 0 /* unused */
230 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
231 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
232 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
233 #define MASK_DEBUG_D 0 /* don't do define_split's */
234 #define MASK_DEBUG_E 0 /* function_arg debug */
235 #define MASK_DEBUG_F 0 /* ??? */
236 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
237 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
238 #define MASK_DEBUG_I 0 /* unused */
240 /* Dummy switches used only in specs */
241 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
243 /* r4000 64 bit sizes */
244 #define TARGET_INT64 (target_flags & MASK_INT64)
245 #define TARGET_LONG64 (target_flags & MASK_LONG64)
246 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
247 #define TARGET_64BIT (target_flags & MASK_64BIT)
249 /* Mips vs. GNU linker */
250 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
252 /* Mips vs. GNU assembler */
253 #define TARGET_GAS (target_flags & MASK_GAS)
254 #define TARGET_MIPS_AS (!TARGET_GAS)
257 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
258 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
259 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
260 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
261 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
262 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
263 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
264 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
265 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
266 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
268 /* Reg. Naming in .s ($21 vs. $a0) */
269 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
271 /* Optimize for Sdata/Sbss */
272 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
274 /* print program statistics */
275 #define TARGET_STATS (target_flags & MASK_STATS)
277 /* call memcpy instead of inline code */
278 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
280 /* .abicalls, etc from Pyramid V.4 */
281 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
283 /* OSF pic references to externs */
284 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
286 /* software floating point */
287 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
288 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
290 /* always call through a register */
291 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
293 /* generate embedded PIC code;
295 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
297 /* for embedded systems, optimize for
298 reduced RAM space instead of for
300 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
302 /* always store uninitialized const
303 variables in rodata, requires
304 TARGET_EMBEDDED_DATA. */
305 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
307 /* generate big endian code. */
308 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
310 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
311 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
313 #define TARGET_MAD (target_flags & MASK_MAD)
315 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
317 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
318 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
320 /* This is true if we must enable the assembly language file switching
323 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
325 /* We must disable the function end stabs when doing the file switching trick,
326 because the Lscope stabs end up in the wrong place, making it impossible
327 to debug the resulting code. */
328 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
330 /* Generate mips16 code */
331 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
333 /* Architecture target defines. */
334 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
335 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
336 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
337 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
339 /* Scheduling target defines. */
340 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
341 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
342 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
343 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
344 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
346 /* Macro to define tables used to set the flags.
347 This is a list in braces of pairs in braces,
348 each pair being { "NAME", VALUE }
349 where VALUE is the bits to set or minus the bits to clear.
350 An empty string NAME is used to identify the default VALUE. */
352 #define TARGET_SWITCHES \
355 N_("No default crt0.o") }, \
356 {"int64", MASK_INT64 | MASK_LONG64, \
357 N_("Use 64-bit int type")}, \
358 {"long64", MASK_LONG64, \
359 N_("Use 64-bit long type")}, \
360 {"long32", -(MASK_LONG64 | MASK_INT64), \
361 N_("Use 32-bit long type")}, \
362 {"split-addresses", MASK_SPLIT_ADDR, \
363 N_("Optimize lui/addiu address loads")}, \
364 {"no-split-addresses", -MASK_SPLIT_ADDR, \
365 N_("Don't optimize lui/addiu address loads")}, \
366 {"mips-as", -MASK_GAS, \
367 N_("Use MIPS as")}, \
370 {"rnames", MASK_NAME_REGS, \
371 N_("Use symbolic register names")}, \
372 {"no-rnames", -MASK_NAME_REGS, \
373 N_("Don't use symbolic register names")}, \
374 {"gpOPT", MASK_GPOPT, \
375 N_("Use GP relative sdata/sbss sections")}, \
376 {"gpopt", MASK_GPOPT, \
377 N_("Use GP relative sdata/sbss sections")}, \
378 {"no-gpOPT", -MASK_GPOPT, \
379 N_("Don't use GP relative sdata/sbss sections")}, \
380 {"no-gpopt", -MASK_GPOPT, \
381 N_("Don't use GP relative sdata/sbss sections")}, \
382 {"stats", MASK_STATS, \
383 N_("Output compiler statistics")}, \
384 {"no-stats", -MASK_STATS, \
385 N_("Don't output compiler statistics")}, \
386 {"memcpy", MASK_MEMCPY, \
387 N_("Don't optimize block moves")}, \
388 {"no-memcpy", -MASK_MEMCPY, \
389 N_("Optimize block moves")}, \
390 {"mips-tfile", MASK_MIPS_TFILE, \
391 N_("Use mips-tfile asm postpass")}, \
392 {"no-mips-tfile", -MASK_MIPS_TFILE, \
393 N_("Don't use mips-tfile asm postpass")}, \
394 {"soft-float", MASK_SOFT_FLOAT, \
395 N_("Use software floating point")}, \
396 {"hard-float", -MASK_SOFT_FLOAT, \
397 N_("Use hardware floating point")}, \
398 {"fp64", MASK_FLOAT64, \
399 N_("Use 64-bit FP registers")}, \
400 {"fp32", -MASK_FLOAT64, \
401 N_("Use 32-bit FP registers")}, \
402 {"gp64", MASK_64BIT, \
403 N_("Use 64-bit general registers")}, \
404 {"gp32", -MASK_64BIT, \
405 N_("Use 32-bit general registers")}, \
406 {"abicalls", MASK_ABICALLS, \
407 N_("Use Irix PIC")}, \
408 {"no-abicalls", -MASK_ABICALLS, \
409 N_("Don't use Irix PIC")}, \
410 {"half-pic", MASK_HALF_PIC, \
411 N_("Use OSF PIC")}, \
412 {"no-half-pic", -MASK_HALF_PIC, \
413 N_("Don't use OSF PIC")}, \
414 {"long-calls", MASK_LONG_CALLS, \
415 N_("Use indirect calls")}, \
416 {"no-long-calls", -MASK_LONG_CALLS, \
417 N_("Don't use indirect calls")}, \
418 {"embedded-pic", MASK_EMBEDDED_PIC, \
419 N_("Use embedded PIC")}, \
420 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
421 N_("Don't use embedded PIC")}, \
422 {"embedded-data", MASK_EMBEDDED_DATA, \
423 N_("Use ROM instead of RAM")}, \
424 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
425 N_("Don't use ROM instead of RAM")}, \
426 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
427 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
428 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
429 N_("Don't put uninitialized constants in ROM")}, \
430 {"eb", MASK_BIG_ENDIAN, \
431 N_("Use big-endian byte order")}, \
432 {"el", -MASK_BIG_ENDIAN, \
433 N_("Use little-endian byte order")}, \
434 {"single-float", MASK_SINGLE_FLOAT, \
435 N_("Use single (32-bit) FP only")}, \
436 {"double-float", -MASK_SINGLE_FLOAT, \
437 N_("Don't use single (32-bit) FP only")}, \
439 N_("Use multiply accumulate")}, \
440 {"no-mad", -MASK_MAD, \
441 N_("Don't use multiply accumulate")}, \
442 {"fix4300", MASK_4300_MUL_FIX, \
443 N_("Work around early 4300 hardware bug")}, \
444 {"no-fix4300", -MASK_4300_MUL_FIX, \
445 N_("Don't work around early 4300 hardware bug")}, \
447 N_("Optimize for 3900")}, \
449 N_("Optimize for 4650")}, \
450 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
451 N_("Trap on integer divide by zero")}, \
452 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
453 N_("Don't trap on integer divide by zero")}, \
454 {"check-range-division",MASK_CHECK_RANGE_DIV, \
455 N_("Trap on integer divide overflow")}, \
456 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
457 N_("Don't trap on integer divide overflow")}, \
458 {"debug", MASK_DEBUG, \
460 {"debuga", MASK_DEBUG_A, \
462 {"debugb", MASK_DEBUG_B, \
464 {"debugc", MASK_DEBUG_C, \
466 {"debugd", MASK_DEBUG_D, \
468 {"debuge", MASK_DEBUG_E, \
470 {"debugf", MASK_DEBUG_F, \
472 {"debugg", MASK_DEBUG_G, \
474 {"debugh", MASK_DEBUG_H, \
476 {"debugi", MASK_DEBUG_I, \
478 {"", (TARGET_DEFAULT \
479 | TARGET_CPU_DEFAULT \
480 | TARGET_ENDIAN_DEFAULT), \
484 /* Default target_flags if no switches are specified */
486 #ifndef TARGET_DEFAULT
487 #define TARGET_DEFAULT 0
490 #ifndef TARGET_CPU_DEFAULT
491 #define TARGET_CPU_DEFAULT 0
494 #ifndef TARGET_ENDIAN_DEFAULT
496 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
498 #define TARGET_ENDIAN_DEFAULT 0
502 #ifndef MIPS_ISA_DEFAULT
503 #define MIPS_ISA_DEFAULT 1
508 /* Make this compile time constant for libgcc2 */
510 #define TARGET_64BIT 1
512 #define TARGET_64BIT 0
514 #endif /* IN_LIBGCC2 */
516 #ifndef MULTILIB_ENDIAN_DEFAULT
517 #if TARGET_ENDIAN_DEFAULT == 0
518 #define MULTILIB_ENDIAN_DEFAULT "EL"
520 #define MULTILIB_ENDIAN_DEFAULT "EB"
524 #ifndef MULTILIB_ISA_DEFAULT
525 # if MIPS_ISA_DEFAULT == 1
526 # define MULTILIB_ISA_DEFAULT "mips1"
528 # if MIPS_ISA_DEFAULT == 2
529 # define MULTILIB_ISA_DEFAULT "mips2"
531 # if MIPS_ISA_DEFAULT == 3
532 # define MULTILIB_ISA_DEFAULT "mips3"
534 # if MIPS_ISA_DEFAULT == 4
535 # define MULTILIB_ISA_DEFAULT "mips4"
537 # define MULTILIB_ISA_DEFAULT "mips1"
544 #ifndef MULTILIB_DEFAULTS
545 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
548 /* We must pass -EL to the linker by default for little endian embedded
549 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
550 linker will default to using big-endian output files. The OUTPUT_FORMAT
551 line must be in the linker script, otherwise -EB/-EL will not work. */
554 #if TARGET_ENDIAN_DEFAULT == 0
555 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EL} %{EB}"
557 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EB} %{EL}"
561 /* This macro is similar to `TARGET_SWITCHES' but defines names of
562 command options that have values. Its definition is an
563 initializer with a subgrouping for each command option.
565 Each subgrouping contains a string constant, that defines the
566 fixed part of the option name, and the address of a variable.
567 The variable, type `char *', is set to the variable part of the
568 given option if the fixed part matches. The actual option name
569 is made by appending `-m' to the specified name.
571 Here is an example which defines `-mshort-data-NUMBER'. If the
572 given option is `-mshort-data-512', the variable `m88k_short_data'
573 will be set to the string `"512"'.
575 extern char *m88k_short_data;
576 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
578 #define TARGET_OPTIONS \
580 SUBTARGET_TARGET_OPTIONS \
581 { "cpu=", &mips_cpu_string, \
582 N_("Specify CPU for scheduling purposes")}, \
583 { "tune=", &mips_tune_string, \
584 N_("Specify CPU for scheduling purposes")}, \
585 { "arch=", &mips_arch_string, \
586 N_("Specify CPU for code generation purposes")}, \
587 { "ips", &mips_isa_string, \
588 N_("Specify a Standard MIPS ISA")}, \
589 { "entry", &mips_entry_string, \
590 N_("Use mips16 entry/exit psuedo ops")}, \
591 { "no-mips16", &mips_no_mips16_string, \
592 N_("Don't use MIPS16 instructions")}, \
593 { "explicit-type-size", &mips_explicit_type_size_string, \
597 /* This is meant to be redefined in the host dependent files. */
598 #define SUBTARGET_TARGET_OPTIONS
600 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
602 /* Generate three-operand multiply instructions for both SImode and DImode. */
603 #define GENERATE_MULT3 (TARGET_MIPS3900 \
606 /* Macros to decide whether certain features are available or not,
607 depending on the instruction set architecture level. */
609 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
610 #define HAVE_SQRT_P() (mips_isa != 1)
612 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
613 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
616 /* ISA has branch likely instructions (eg. mips2). */
617 /* Disable branchlikely for tx39 until compare rewrite. They haven't
618 been generated up to this point. */
619 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
620 /* || TARGET_MIPS3900 */)
622 /* ISA has the conditional move instructions introduced in mips4. */
623 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
626 /* ISA has just the integer condition move instructions (movn,movz) */
627 #define ISA_HAS_INT_CONDMOVE 0
631 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
632 branch on CC, and move (both FP and non-FP) on CC. */
633 #define ISA_HAS_8CC (mips_isa == 4 \
637 /* This is a catch all for the other new mips4 instructions: indexed load and
638 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
639 and the FP recip and recip sqrt instructions */
640 #define ISA_HAS_FP4 (mips_isa == 4 \
643 /* ISA has conditional trap instructions. */
644 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
646 /* ISA has nmadd and nmsub instructions. */
647 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
650 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
651 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
652 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
653 target_flags, and -mgp64 sets MASK_64BIT.
655 Setting MASK_64BIT in target_flags will cause gcc to assume that
656 registers are 64 bits wide. int, long and void * will be 32 bit;
657 this may be changed with -mint64 or -mlong64.
659 The gen* programs link code that refers to MASK_64BIT. They don't
660 actually use the information in target_flags; they just refer to
663 /* Switch Recognition by gcc.c. Add -G xx support */
665 #ifdef SWITCH_TAKES_ARG
666 #undef SWITCH_TAKES_ARG
669 #define SWITCH_TAKES_ARG(CHAR) \
670 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
672 /* Sometimes certain combinations of command options do not make sense
673 on a particular target machine. You can define a macro
674 `OVERRIDE_OPTIONS' to take account of this. This macro, if
675 defined, is executed once just after all the command options have
678 On the MIPS, it is used to handle -G. We also use it to set up all
679 of the tables referenced in the other macros. */
681 #define OVERRIDE_OPTIONS override_options ()
683 /* Zero or more C statements that may conditionally modify two
684 variables `fixed_regs' and `call_used_regs' (both of type `char
685 []') after they have been initialized from the two preceding
688 This is necessary in case the fixed or call-clobbered registers
689 depend on target flags.
691 You need not define this macro if it has no work to do.
693 If the usage of an entire class of registers depends on the target
694 flags, you may indicate this to GCC by using this macro to modify
695 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
696 the classes which should not be used by GCC. Also define the macro
697 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
698 letter for a class that shouldn't be used.
700 (However, if this class is not included in `GENERAL_REGS' and all
701 of the insn patterns whose constraints permit this class are
702 controlled by target switches, then GCC will automatically avoid
703 using these registers when the target switches are opposed to
706 #define CONDITIONAL_REGISTER_USAGE \
709 if (!TARGET_HARD_FLOAT) \
713 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
714 fixed_regs[regno] = call_used_regs[regno] = 1; \
715 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
716 fixed_regs[regno] = call_used_regs[regno] = 1; \
718 else if (! ISA_HAS_8CC) \
722 /* We only have a single condition code register. We \
723 implement this by hiding all the condition code registers, \
724 and generating RTL that refers directly to ST_REG_FIRST. */ \
725 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
726 fixed_regs[regno] = call_used_regs[regno] = 1; \
728 /* In mips16 mode, we permit the $t temporary registers to be used \
729 for reload. We prohibit the unused $s registers, since they \
730 are caller saved, and saving them via a mips16 register would \
731 probably waste more time than just reloading the value. */ \
734 fixed_regs[18] = call_used_regs[18] = 1; \
735 fixed_regs[19] = call_used_regs[19] = 1; \
736 fixed_regs[20] = call_used_regs[20] = 1; \
737 fixed_regs[21] = call_used_regs[21] = 1; \
738 fixed_regs[22] = call_used_regs[22] = 1; \
739 fixed_regs[23] = call_used_regs[23] = 1; \
740 fixed_regs[26] = call_used_regs[26] = 1; \
741 fixed_regs[27] = call_used_regs[27] = 1; \
742 fixed_regs[30] = call_used_regs[30] = 1; \
744 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
748 /* This is meant to be redefined in the host dependent files. */
749 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
751 /* Show we can debug even without a frame pointer. */
752 #define CAN_DEBUG_WITHOUT_FP
754 /* Complain about missing specs and predefines that should be defined in each
755 of the target tm files to override the defaults. This is mostly a place-
756 holder until I can get each of the files updated [mm]. */
758 #if defined(OSF_OS) \
759 || defined(DECSTATION) \
760 || defined(SGI_TARGET) \
761 || defined(MIPS_NEWS) \
762 || defined(MIPS_SYSV) \
763 || defined(MIPS_SVR4) \
764 || defined(MIPS_BSD43)
766 #ifndef CPP_PREDEFINES
767 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
771 #error "Define LIB_SPEC in the appropriate tm.h file"
774 #ifndef STARTFILE_SPEC
775 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
779 #error "Define MACHINE_TYPE in the appropriate tm.h file"
783 /* Tell collect what flags to pass to nm. */
785 #define NM_FLAGS "-Bn"
789 /* Names to predefine in the preprocessor for this target machine. */
791 #ifndef CPP_PREDEFINES
792 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
793 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
794 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
797 /* Assembler specs. */
799 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
802 #define MIPS_AS_ASM_SPEC "\
803 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
804 %{pipe: %e-pipe is not supported.} \
805 %{K} %(subtarget_mips_as_asm_spec)"
807 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
808 rather than gas. It may be overridden by subtargets. */
810 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
811 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
814 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
817 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
819 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
820 GAS_ASM_SPEC as the default, depending upon the value of
823 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
826 #define TARGET_ASM_SPEC "\
827 %{mmips-as: %(mips_as_asm_spec)} \
828 %{!mmips-as: %(gas_asm_spec)}"
832 #define TARGET_ASM_SPEC "\
833 %{!mgas: %(mips_as_asm_spec)} \
834 %{mgas: %(gas_asm_spec)}"
838 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
839 to the assembler. It may be overridden by subtargets. */
840 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
841 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
843 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
846 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
847 the assembler. It may be overridden by subtargets. */
848 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
849 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
850 %{g} %{g0} %{g1} %{g2} %{g3} \
851 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
852 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
853 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
854 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
857 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
858 overridden by subtargets. */
860 #ifndef SUBTARGET_ASM_SPEC
861 #define SUBTARGET_ASM_SPEC ""
864 /* ASM_SPEC is the set of arguments to pass to the assembler. */
867 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
868 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
869 %(subtarget_asm_optimizing_spec) \
870 %(subtarget_asm_debugging_spec) \
873 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
875 %(subtarget_asm_spec)"
877 /* Specify to run a post-processor, mips-tfile after the assembler
878 has run to stuff the mips debug information into the object file.
879 This is needed because the $#!%^ MIPS assembler provides no way
880 of specifying such information in the assembly file. If we are
881 cross compiling, disable mips-tfile unless the user specifies
884 #ifndef ASM_FINAL_SPEC
885 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
887 #define ASM_FINAL_SPEC "\
888 %{mmips-as: %{!mno-mips-tfile: \
889 \n mips-tfile %{v*: -v} \
891 %{!K: %{save-temps: -I %b.o~}} \
892 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
893 %{.s:%i} %{!.s:%g.s}}}"
897 #define ASM_FINAL_SPEC "\
898 %{!mgas: %{!mno-mips-tfile: \
899 \n mips-tfile %{v*: -v} \
901 %{!K: %{save-temps: -I %b.o~}} \
902 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
903 %{.s:%i} %{!.s:%g.s}}}"
906 #endif /* ASM_FINAL_SPEC */
908 /* Redefinition of libraries used. Mips doesn't support normal
909 UNIX style profiling via calling _mcount. It does offer
910 profiling that samples the PC, so do what we can... */
913 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
916 /* Extra switches sometimes passed to the linker. */
917 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
918 will interpret it as a -b option. */
923 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
924 %{bestGnum} %{shared} %{non_shared}"
925 #endif /* LINK_SPEC defined */
927 /* Specs for the compiler proper */
929 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
930 overridden by subtargets. */
931 #ifndef SUBTARGET_CC1_SPEC
932 #define SUBTARGET_CC1_SPEC ""
935 /* Deal with historic options. */
937 #define CC1_CPU_SPEC "\
939 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
940 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
941 %{m4650:-march=r4650 -mmad -msingle-float \
942 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
945 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
949 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
950 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
951 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
952 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
953 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
954 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
955 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
956 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
957 %{pic-none: -mno-half-pic} \
958 %{pic-lib: -mhalf-pic} \
959 %{pic-extern: -mhalf-pic} \
960 %{pic-calls: -mhalf-pic} \
962 %(subtarget_cc1_spec) \
966 /* Preprocessor specs. */
968 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
969 be overridden by subtargets. */
971 #ifndef SUBTARGET_CPP_SIZE_SPEC
972 #define SUBTARGET_CPP_SIZE_SPEC "\
973 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
974 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
977 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
978 overridden by subtargets. */
979 #ifndef SUBTARGET_CPP_SPEC
980 #define SUBTARGET_CPP_SPEC ""
983 /* If we're using 64bit longs, then we have to define __LONG_MAX__
984 correctly. Similarly for 64bit ints and __INT_MAX__. */
985 #ifndef LONG_MAX_SPEC
986 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
987 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
989 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
993 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
994 of the source file extension. */
995 #define CPLUSPLUS_CPP_SPEC "\
996 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
999 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1003 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1004 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1005 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1006 %(subtarget_cpp_size_spec) \
1007 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1008 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1009 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1010 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1011 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1012 %{msoft-float:-D__mips_soft_float} \
1013 %{mabi=eabi:-D__mips_eabi} \
1014 %{mips16:%{!mno-mips16:-D__mips16}} \
1015 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1016 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1018 %(subtarget_cpp_spec) "
1021 /* This macro defines names of additional specifications to put in the specs
1022 that can be used in various specifications like CC1_SPEC. Its definition
1023 is an initializer with a subgrouping for each command option.
1025 Each subgrouping contains a string constant, that defines the
1026 specification name, and a string constant that used by the GNU CC driver
1029 Do not define this macro if it does not need to do anything. */
1031 #define EXTRA_SPECS \
1032 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1033 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1034 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1035 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1036 { "long_max_spec", LONG_MAX_SPEC }, \
1037 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1038 { "gas_asm_spec", GAS_ASM_SPEC }, \
1039 { "target_asm_spec", TARGET_ASM_SPEC }, \
1040 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1041 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1042 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1043 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1044 { "endian_spec", ENDIAN_SPEC }, \
1045 SUBTARGET_EXTRA_SPECS
1047 #ifndef SUBTARGET_EXTRA_SPECS
1048 #define SUBTARGET_EXTRA_SPECS
1051 /* If defined, this macro is an additional prefix to try after
1052 `STANDARD_EXEC_PREFIX'. */
1054 #ifndef MD_EXEC_PREFIX
1055 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1058 #ifndef MD_STARTFILE_PREFIX
1059 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1063 /* Print subsidiary information on the compiler version in use. */
1065 #define MIPS_VERSION "[AL 1.1, MM 40]"
1067 #ifndef MACHINE_TYPE
1068 #define MACHINE_TYPE "BSD Mips"
1071 #ifndef TARGET_VERSION_INTERNAL
1072 #define TARGET_VERSION_INTERNAL(STREAM) \
1073 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1076 #ifndef TARGET_VERSION
1077 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1081 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1082 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1083 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1085 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1086 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1089 /* By default, turn on GDB extensions. */
1090 #define DEFAULT_GDB_EXTENSIONS 1
1092 /* If we are passing smuggling stabs through the MIPS ECOFF object
1093 format, put a comment in front of the .stab<x> operation so
1094 that the MIPS assembler does not choke. The mips-tfile program
1095 will correctly put the stab into the object file. */
1097 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1098 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1099 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1101 /* Local compiler-generated symbols must have a prefix that the assembler
1102 understands. By default, this is $, although some targets (e.g.,
1103 NetBSD-ELF) need to override this. */
1105 #ifndef LOCAL_LABEL_PREFIX
1106 #define LOCAL_LABEL_PREFIX "$"
1109 /* By default on the mips, external symbols do not have an underscore
1110 prepended, but some targets (e.g., NetBSD) require this. */
1112 #ifndef USER_LABEL_PREFIX
1113 #define USER_LABEL_PREFIX ""
1116 /* Forward references to tags are allowed. */
1117 #define SDB_ALLOW_FORWARD_REFERENCES
1119 /* Unknown tags are also allowed. */
1120 #define SDB_ALLOW_UNKNOWN_REFERENCES
1122 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1123 since the length can run past this up to a continuation point. */
1124 #undef DBX_CONTIN_LENGTH
1125 #define DBX_CONTIN_LENGTH 1500
1127 /* How to renumber registers for dbx and gdb. */
1128 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1130 /* The mapping from gcc register number to DWARF 2 CFA column number.
1131 This mapping does not allow for tracking register 0, since SGI's broken
1132 dwarf reader thinks column 0 is used for the frame address, but since
1133 register 0 is fixed this is not a problem. */
1134 #define DWARF_FRAME_REGNUM(REG) \
1135 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1137 /* The DWARF 2 CFA column which tracks the return address. */
1138 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1140 /* Before the prologue, RA lives in r31. */
1141 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1143 /* Describe how we implement __builtin_eh_return. */
1144 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1145 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1147 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1148 The default for this in 64-bit mode is 8, which causes problems with
1149 SFmode register saves. */
1150 #define DWARF_CIE_DATA_ALIGNMENT 4
1152 /* Overrides for the COFF debug format. */
1153 #define PUT_SDB_SCL(a) \
1155 extern FILE *asm_out_text_file; \
1156 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1159 #define PUT_SDB_INT_VAL(a) \
1161 extern FILE *asm_out_text_file; \
1162 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1165 #define PUT_SDB_VAL(a) \
1167 extern FILE *asm_out_text_file; \
1168 fputs ("\t.val\t", asm_out_text_file); \
1169 output_addr_const (asm_out_text_file, (a)); \
1170 fputc (';', asm_out_text_file); \
1173 #define PUT_SDB_DEF(a) \
1175 extern FILE *asm_out_text_file; \
1176 fprintf (asm_out_text_file, "\t%s.def\t", \
1177 (TARGET_GAS) ? "" : "#"); \
1178 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1179 fputc (';', asm_out_text_file); \
1182 #define PUT_SDB_PLAIN_DEF(a) \
1184 extern FILE *asm_out_text_file; \
1185 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1186 (TARGET_GAS) ? "" : "#", (a)); \
1189 #define PUT_SDB_ENDEF \
1191 extern FILE *asm_out_text_file; \
1192 fprintf (asm_out_text_file, "\t.endef\n"); \
1195 #define PUT_SDB_TYPE(a) \
1197 extern FILE *asm_out_text_file; \
1198 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1201 #define PUT_SDB_SIZE(a) \
1203 extern FILE *asm_out_text_file; \
1204 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1207 #define PUT_SDB_DIM(a) \
1209 extern FILE *asm_out_text_file; \
1210 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1213 #ifndef PUT_SDB_START_DIM
1214 #define PUT_SDB_START_DIM \
1216 extern FILE *asm_out_text_file; \
1217 fprintf (asm_out_text_file, "\t.dim\t"); \
1221 #ifndef PUT_SDB_NEXT_DIM
1222 #define PUT_SDB_NEXT_DIM(a) \
1224 extern FILE *asm_out_text_file; \
1225 fprintf (asm_out_text_file, "%d,", a); \
1229 #ifndef PUT_SDB_LAST_DIM
1230 #define PUT_SDB_LAST_DIM(a) \
1232 extern FILE *asm_out_text_file; \
1233 fprintf (asm_out_text_file, "%d;", a); \
1237 #define PUT_SDB_TAG(a) \
1239 extern FILE *asm_out_text_file; \
1240 fprintf (asm_out_text_file, "\t.tag\t"); \
1241 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1242 fputc (';', asm_out_text_file); \
1245 /* For block start and end, we create labels, so that
1246 later we can figure out where the correct offset is.
1247 The normal .ent/.end serve well enough for functions,
1248 so those are just commented out. */
1250 #define PUT_SDB_BLOCK_START(LINE) \
1252 extern FILE *asm_out_text_file; \
1253 fprintf (asm_out_text_file, \
1254 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1255 LOCAL_LABEL_PREFIX, \
1257 (TARGET_GAS) ? "" : "#", \
1258 LOCAL_LABEL_PREFIX, \
1261 sdb_label_count++; \
1264 #define PUT_SDB_BLOCK_END(LINE) \
1266 extern FILE *asm_out_text_file; \
1267 fprintf (asm_out_text_file, \
1268 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1269 LOCAL_LABEL_PREFIX, \
1271 (TARGET_GAS) ? "" : "#", \
1272 LOCAL_LABEL_PREFIX, \
1275 sdb_label_count++; \
1278 #define PUT_SDB_FUNCTION_START(LINE)
1280 #define PUT_SDB_FUNCTION_END(LINE) \
1282 extern FILE *asm_out_text_file; \
1283 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1286 #define PUT_SDB_EPILOGUE_END(NAME)
1288 #define PUT_SDB_SRC_FILE(FILENAME) \
1290 extern FILE *asm_out_text_file; \
1291 output_file_directive (asm_out_text_file, (FILENAME)); \
1294 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1295 sprintf ((BUFFER), ".%dfake", (NUMBER));
1297 /* Correct the offset of automatic variables and arguments. Note that
1298 the MIPS debug format wants all automatic variables and arguments
1299 to be in terms of the virtual frame pointer (stack pointer before
1300 any adjustment in the function), while the MIPS 3.0 linker wants
1301 the frame pointer to be the stack pointer after the initial
1304 #define DEBUGGER_AUTO_OFFSET(X) \
1305 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1306 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1307 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1309 /* Tell collect that the object format is ECOFF */
1310 #ifndef OBJECT_FORMAT_ROSE
1311 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1312 #define EXTENDED_COFF /* ECOFF, not normal coff */
1315 #if 0 /* These definitions normally have no effect because
1316 MIPS systems define USE_COLLECT2, so
1317 assemble_constructor does nothing anyway. */
1319 /* Don't use the default definitions, because we don't have gld.
1320 Also, we don't want stabs when generating ECOFF output.
1321 Instead we depend on collect to handle these. */
1323 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1324 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1328 /* Target machine storage layout */
1330 /* Define in order to support both big and little endian float formats
1331 in the same gcc binary. */
1332 #define REAL_ARITHMETIC
1334 /* Define this if most significant bit is lowest numbered
1335 in instructions that operate on numbered bit-fields.
1337 #define BITS_BIG_ENDIAN 0
1339 /* Define this if most significant byte of a word is the lowest numbered. */
1340 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1342 /* Define this if most significant word of a multiword number is the lowest. */
1343 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1345 /* Define this to set the endianness to use in libgcc2.c, which can
1346 not depend on target_flags. */
1347 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1348 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1350 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1353 /* Number of bits in an addressable storage unit */
1354 #define BITS_PER_UNIT 8
1356 /* Width in bits of a "word", which is the contents of a machine register.
1357 Note that this is not necessarily the width of data type `int';
1358 if using 16-bit ints on a 68000, this would still be 32.
1359 But on a machine with 16-bit registers, this would be 16. */
1360 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1361 #define MAX_BITS_PER_WORD 64
1363 /* Width of a word, in units (bytes). */
1364 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1365 #define MIN_UNITS_PER_WORD 4
1367 /* For MIPS, width of a floating point register. */
1368 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1370 /* A C expression for the size in bits of the type `int' on the
1371 target machine. If you don't define this, the default is one
1373 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1374 #define MAX_INT_TYPE_SIZE 64
1376 /* Tell the preprocessor the maximum size of wchar_t. */
1377 #ifndef MAX_WCHAR_TYPE_SIZE
1378 #ifndef WCHAR_TYPE_SIZE
1379 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1383 /* A C expression for the size in bits of the type `short' on the
1384 target machine. If you don't define this, the default is half a
1385 word. (If this would be less than one storage unit, it is
1386 rounded up to one unit.) */
1387 #define SHORT_TYPE_SIZE 16
1389 /* A C expression for the size in bits of the type `long' on the
1390 target machine. If you don't define this, the default is one
1392 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1393 #define MAX_LONG_TYPE_SIZE 64
1395 /* A C expression for the size in bits of the type `long long' on the
1396 target machine. If you don't define this, the default is two
1398 #define LONG_LONG_TYPE_SIZE 64
1400 /* A C expression for the size in bits of the type `char' on the
1401 target machine. If you don't define this, the default is one
1402 quarter of a word. (If this would be less than one storage unit,
1403 it is rounded up to one unit.) */
1404 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1406 /* A C expression for the size in bits of the type `float' on the
1407 target machine. If you don't define this, the default is one
1409 #define FLOAT_TYPE_SIZE 32
1411 /* A C expression for the size in bits of the type `double' on the
1412 target machine. If you don't define this, the default is two
1414 #define DOUBLE_TYPE_SIZE 64
1416 /* A C expression for the size in bits of the type `long double' on
1417 the target machine. If you don't define this, the default is two
1419 #define LONG_DOUBLE_TYPE_SIZE 64
1421 /* Width in bits of a pointer.
1422 See also the macro `Pmode' defined below. */
1423 #ifndef POINTER_SIZE
1424 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1427 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1428 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1430 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1431 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1433 /* Allocation boundary (in *bits*) for the code of a function. */
1434 #define FUNCTION_BOUNDARY 32
1436 /* Alignment of field after `int : 0' in a structure. */
1437 #define EMPTY_FIELD_BOUNDARY 32
1439 /* Every structure's size must be a multiple of this. */
1440 /* 8 is observed right on a DECstation and on riscos 4.02. */
1441 #define STRUCTURE_SIZE_BOUNDARY 8
1443 /* There is no point aligning anything to a rounder boundary than this. */
1444 #define BIGGEST_ALIGNMENT 64
1446 /* Set this nonzero if move instructions will actually fail to work
1447 when given unaligned data. */
1448 #define STRICT_ALIGNMENT 1
1450 /* Define this if you wish to imitate the way many other C compilers
1451 handle alignment of bitfields and the structures that contain
1454 The behavior is that the type written for a bitfield (`int',
1455 `short', or other integer type) imposes an alignment for the
1456 entire structure, as if the structure really did contain an
1457 ordinary field of that type. In addition, the bitfield is placed
1458 within the structure so that it would fit within such a field,
1459 not crossing a boundary for it.
1461 Thus, on most machines, a bitfield whose type is written as `int'
1462 would not cross a four-byte boundary, and would force four-byte
1463 alignment for the whole structure. (The alignment used may not
1464 be four bytes; it is controlled by the other alignment
1467 If the macro is defined, its definition should be a C expression;
1468 a nonzero value for the expression enables this behavior. */
1470 #define PCC_BITFIELD_TYPE_MATTERS 1
1472 /* If defined, a C expression to compute the alignment given to a
1473 constant that is being placed in memory. CONSTANT is the constant
1474 and ALIGN is the alignment that the object would ordinarily have.
1475 The value of this macro is used instead of that alignment to align
1478 If this macro is not defined, then ALIGN is used.
1480 The typical use of this macro is to increase alignment for string
1481 constants to be word aligned so that `strcpy' calls that copy
1482 constants can be done inline. */
1484 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1485 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1486 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1488 /* If defined, a C expression to compute the alignment for a static
1489 variable. TYPE is the data type, and ALIGN is the alignment that
1490 the object would ordinarily have. The value of this macro is used
1491 instead of that alignment to align the object.
1493 If this macro is not defined, then ALIGN is used.
1495 One use of this macro is to increase alignment of medium-size
1496 data to make it all fit in fewer cache lines. Another is to
1497 cause character arrays to be word-aligned so that `strcpy' calls
1498 that copy constants to character arrays can be done inline. */
1500 #undef DATA_ALIGNMENT
1501 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1502 ((((ALIGN) < BITS_PER_WORD) \
1503 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1504 || TREE_CODE (TYPE) == UNION_TYPE \
1505 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1508 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1510 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1512 /* Define this macro if an argument declared as `char' or `short' in a
1513 prototype should actually be passed as an `int'. In addition to
1514 avoiding errors in certain cases of mismatch, it also makes for
1515 better code on certain machines. */
1517 #define PROMOTE_PROTOTYPES 1
1519 /* Define if operations between registers always perform the operation
1520 on the full register even if a narrower mode is specified. */
1521 #define WORD_REGISTER_OPERATIONS
1523 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1524 will either zero-extend or sign-extend. The value of this macro should
1525 be the code that says which one of the two operations is implicitly
1528 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1529 moves. All other referces are zero extended. */
1530 #define LOAD_EXTEND_OP(MODE) \
1531 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1532 ? SIGN_EXTEND : ZERO_EXTEND)
1534 /* Define this macro if it is advisable to hold scalars in registers
1535 in a wider mode than that declared by the program. In such cases,
1536 the value is constrained to be within the bounds of the declared
1537 type, but kept valid in the wider mode. The signedness of the
1538 extension may differ from that of the type.
1540 We promote any value smaller than SImode up to SImode. We don't
1541 want to promote to DImode when in 64 bit mode, because that would
1542 prevent us from using the faster SImode multiply and divide
1545 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1546 if (GET_MODE_CLASS (MODE) == MODE_INT \
1547 && GET_MODE_SIZE (MODE) < 4) \
1550 /* Define this if function arguments should also be promoted using the above
1553 #define PROMOTE_FUNCTION_ARGS
1555 /* Likewise, if the function return value is promoted. */
1557 #define PROMOTE_FUNCTION_RETURN
1559 /* Standard register usage. */
1561 /* Number of actual hardware registers.
1562 The hardware registers are assigned numbers for the compiler
1563 from 0 to just below FIRST_PSEUDO_REGISTER.
1564 All registers that the compiler knows about must be given numbers,
1565 even those that are not normally considered general registers.
1567 On the Mips, we have 32 integer registers, 32 floating point
1568 registers, 8 condition code registers, and the special registers
1569 hi, lo, hilo, and rap. The 8 condition code registers are only
1570 used if mips_isa >= 4. The hilo register is only used in 64 bit
1571 mode. It represents a 64 bit value stored as two 32 bit values in
1572 the hi and lo registers; this is the result of the mult
1573 instruction. rap is a pointer to the stack where the return
1574 address reg ($31) was stored. This is needed for C++ exception
1577 #define FIRST_PSEUDO_REGISTER 76
1579 /* 1 for registers that have pervasive standard uses
1580 and are not available for the register allocator.
1582 On the MIPS, see conventions, page D-2 */
1584 #define FIXED_REGISTERS \
1586 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1594 /* 1 for registers not available across function calls.
1595 These must include the FIXED_REGISTERS and also any
1596 registers that can be used without being saved.
1597 The latter must include the registers where values are returned
1598 and the register where structure-value addresses are passed.
1599 Aside from that, you can include as many other registers as you like. */
1601 #define CALL_USED_REGISTERS \
1603 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1604 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1605 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1606 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1607 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1611 /* Internal macros to classify a register number as to whether it's a
1612 general purpose register, a floating point register, a
1613 multiply/divide register, or a status register. */
1615 #define GP_REG_FIRST 0
1616 #define GP_REG_LAST 31
1617 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1618 #define GP_DBX_FIRST 0
1620 #define FP_REG_FIRST 32
1621 #define FP_REG_LAST 63
1622 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1623 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1625 #define MD_REG_FIRST 64
1626 #define MD_REG_LAST 66
1627 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1629 #define ST_REG_FIRST 67
1630 #define ST_REG_LAST 74
1631 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1633 #define RAP_REG_NUM 75
1635 #define AT_REGNUM (GP_REG_FIRST + 1)
1636 #define HI_REGNUM (MD_REG_FIRST + 0)
1637 #define LO_REGNUM (MD_REG_FIRST + 1)
1638 #define HILO_REGNUM (MD_REG_FIRST + 2)
1640 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1641 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1642 should be used instead. */
1643 #define FPSW_REGNUM ST_REG_FIRST
1645 #define GP_REG_P(REGNO) \
1646 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1647 #define M16_REG_P(REGNO) \
1648 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1649 #define FP_REG_P(REGNO) \
1650 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1651 #define MD_REG_P(REGNO) \
1652 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1653 #define ST_REG_P(REGNO) \
1654 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1656 /* Return number of consecutive hard regs needed starting at reg REGNO
1657 to hold something of mode MODE.
1658 This is ordinarily the length in words of a value of mode MODE
1659 but can be less for certain modes in special long registers.
1661 On the MIPS, all general registers are one word long. Except on
1662 the R4000 with the FR bit set, the floating point uses register
1663 pairs, with the second register not being allocable. */
1665 #define HARD_REGNO_NREGS(REGNO, MODE) \
1666 (! FP_REG_P (REGNO) \
1667 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1668 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1670 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1671 MODE. In 32 bit mode, require that DImode and DFmode be in even
1672 registers. For DImode, this makes some of the insns easier to
1673 write, since you don't have to worry about a DImode value in
1674 registers 3 & 4, producing a result in 4 & 5.
1676 To make the code simpler HARD_REGNO_MODE_OK now just references an
1677 array built in override_options. Because machmodes.h is not yet
1678 included before this file is processed, the MODE bound can't be
1681 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1683 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1684 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1686 /* Value is 1 if it is a good idea to tie two pseudo registers
1687 when one has mode MODE1 and one has mode MODE2.
1688 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1689 for any hard reg, then this must be 0 for correct output. */
1690 #define MODES_TIEABLE_P(MODE1, MODE2) \
1691 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1692 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1693 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1694 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1696 /* MIPS pc is not overloaded on a register. */
1697 /* #define PC_REGNUM xx */
1699 /* Register to use for pushing function arguments. */
1700 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1702 /* Offset from the stack pointer to the first available location. Use
1703 the default value zero. */
1704 /* #define STACK_POINTER_OFFSET 0 */
1706 /* Base register for access to local variables of the function. We
1707 pretend that the frame pointer is $1, and then eliminate it to
1708 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1709 a fixed register, and will not be used for anything else. */
1710 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1712 /* Temporary scratch register for use by the assembler. */
1713 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1715 /* $30 is not available on the mips16, so we use $17 as the frame
1717 #define HARD_FRAME_POINTER_REGNUM \
1718 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1720 /* Value should be nonzero if functions must have frame pointers.
1721 Zero means the frame pointer need not be set up (and parms
1722 may be accessed via the stack pointer) in functions that seem suitable.
1723 This is computed in `reload', in reload1.c. */
1724 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1726 /* Base register for access to arguments of the function. */
1727 #define ARG_POINTER_REGNUM GP_REG_FIRST
1729 /* Fake register that holds the address on the stack of the
1730 current function's return address. */
1731 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1733 /* Register in which static-chain is passed to a function. */
1734 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1736 /* If the structure value address is passed in a register, then
1737 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1738 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1740 /* If the structure value address is not passed in a register, define
1741 `STRUCT_VALUE' as an expression returning an RTX for the place
1742 where the address is passed. If it returns 0, the address is
1743 passed as an "invisible" first argument. */
1744 #define STRUCT_VALUE 0
1746 /* Mips registers used in prologue/epilogue code when the stack frame
1747 is larger than 32K bytes. These registers must come from the
1748 scratch register set, and not used for passing and returning
1749 arguments and any other information used in the calling sequence
1750 (such as pic). Must start at 12, since t0/t3 are parameter passing
1751 registers in the 64 bit ABI. */
1753 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1754 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1756 /* Define this macro if it is as good or better to call a constant
1757 function address than to call an address kept in a register. */
1758 #define NO_FUNCTION_CSE 1
1760 /* Define this macro if it is as good or better for a function to
1761 call itself with an explicit address than to call an address
1762 kept in a register. */
1763 #define NO_RECURSIVE_FUNCTION_CSE 1
1765 /* The register number of the register used to address a table of
1766 static data addresses in memory. In some cases this register is
1767 defined by a processor's "application binary interface" (ABI).
1768 When this macro is defined, RTL is generated for this register
1769 once, as with the stack pointer and frame pointer registers. If
1770 this macro is not defined, it is up to the machine-dependent
1771 files to allocate such a register (if necessary). */
1772 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1774 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1776 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1777 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1778 isn't always called for static inline functions. */
1779 #define INIT_EXPANDERS \
1781 embedded_pic_fnaddr_rtx = NULL; \
1782 mips16_gp_pseudo_rtx = NULL; \
1785 /* Define the classes of registers for register constraints in the
1786 machine description. Also define ranges of constants.
1788 One of the classes must always be named ALL_REGS and include all hard regs.
1789 If there is more than one class, another class must be named NO_REGS
1790 and contain no registers.
1792 The name GENERAL_REGS must be the name of a class (or an alias for
1793 another name such as ALL_REGS). This is the class of registers
1794 that is allowed by "g" or "r" in a register constraint.
1795 Also, registers outside this class are allocated only when
1796 instructions express preferences for them.
1798 The classes must be numbered in nondecreasing order; that is,
1799 a larger-numbered class must never be contained completely
1800 in a smaller-numbered class.
1802 For any two classes, it is very desirable that there be another
1803 class that represents their union. */
1807 NO_REGS, /* no registers in set */
1808 M16_NA_REGS, /* mips16 regs not used to pass args */
1809 M16_REGS, /* mips16 directly accessible registers */
1810 T_REG, /* mips16 T register ($24) */
1811 M16_T_REGS, /* mips16 registers plus T register */
1812 GR_REGS, /* integer registers */
1813 FP_REGS, /* floating point registers */
1814 HI_REG, /* hi register */
1815 LO_REG, /* lo register */
1816 HILO_REG, /* hilo register pair for 64 bit mode mult */
1817 MD_REGS, /* multiply/divide registers (hi/lo) */
1818 HI_AND_GR_REGS, /* union classes */
1821 ST_REGS, /* status registers (fp status) */
1822 ALL_REGS, /* all registers */
1823 LIM_REG_CLASSES /* max value + 1 */
1826 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1828 #define GENERAL_REGS GR_REGS
1830 /* An initializer containing the names of the register classes as C
1831 string constants. These names are used in writing some of the
1834 #define REG_CLASS_NAMES \
1849 "HILO_AND_GR_REGS", \
1854 /* An initializer containing the contents of the register classes,
1855 as integers which are bit masks. The Nth integer specifies the
1856 contents of class N. The way the integer MASK is interpreted is
1857 that register R is in the class if `MASK & (1 << R)' is 1.
1859 When the machine has more than 32 registers, an integer does not
1860 suffice. Then the integers are replaced by sub-initializers,
1861 braced groupings containing several integers. Each
1862 sub-initializer must be suitable as an initializer for the type
1863 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1865 #define REG_CLASS_CONTENTS \
1867 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1868 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1869 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1870 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1871 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1872 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1873 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1874 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1875 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1876 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1877 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1878 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1879 { 0xffffffff, 0x00000000, 0x00000002 }, \
1880 { 0xffffffff, 0x00000000, 0x00000004 }, \
1881 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1882 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1886 /* A C expression whose value is a register class containing hard
1887 register REGNO. In general there is more that one such class;
1888 choose a class which is "minimal", meaning that no smaller class
1889 also contains the register. */
1891 extern enum reg_class mips_regno_to_class[];
1893 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1895 /* A macro whose definition is the name of the class to which a
1896 valid base register must belong. A base register is one used in
1897 an address which is the register value plus a displacement. */
1899 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1901 /* A macro whose definition is the name of the class to which a
1902 valid index register must belong. An index register is one used
1903 in an address where its value is either multiplied by a scale
1904 factor or added to another register (as well as added to a
1907 #define INDEX_REG_CLASS NO_REGS
1909 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1910 registers explicitly used in the rtl to be used as spill registers
1911 but prevents the compiler from extending the lifetime of these
1914 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1916 /* This macro is used later on in the file. */
1917 #define GR_REG_CLASS_P(CLASS) \
1918 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1919 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1921 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1922 is the default value (allocate the registers in numeric order). We
1923 define it just so that we can override it for the mips16 target in
1924 ORDER_REGS_FOR_LOCAL_ALLOC. */
1926 #define REG_ALLOC_ORDER \
1927 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1928 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1929 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1930 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1931 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1934 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1935 to be rearranged based on a particular function. On the mips16, we
1936 want to allocate $24 (T_REG) before other registers for
1937 instructions for which it is possible. */
1939 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1941 /* REGISTER AND CONSTANT CLASSES */
1943 /* Get reg_class from a letter such as appears in the machine
1946 DEFINED REGISTER CLASSES:
1948 'd' General (aka integer) registers
1949 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1950 'y' General registers (in both mips16 and non mips16 mode)
1951 'e' mips16 non argument registers (M16_NA_REGS)
1952 't' mips16 temporary register ($24)
1953 'f' Floating point registers
1956 'x' Multiply/divide registers
1958 'z' FP Status register
1959 'b' All registers */
1961 extern enum reg_class mips_char_to_class[];
1963 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1965 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1966 string can be used to stand for particular ranges of immediate
1967 operands. This macro defines what the ranges are. C is the
1968 letter, and VALUE is a constant value. Return 1 if VALUE is
1969 in the range specified by C. */
1973 `I' is used for the range of constants an arithmetic insn can
1974 actually contain (16 bits signed integers).
1976 `J' is used for the range which is just zero (ie, $r0).
1978 `K' is used for the range of constants a logical insn can actually
1979 contain (16 bit zero-extended integers).
1981 `L' is used for the range of constants that be loaded with lui
1982 (ie, the bottom 16 bits are zero).
1984 `M' is used for the range of constants that take two words to load
1985 (ie, not matched by `I', `K', and `L').
1987 `N' is used for negative 16 bit constants other than -65536.
1989 `O' is a 15 bit signed integer.
1991 `P' is used for positive 16 bit constants. */
1993 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1994 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1996 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1997 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1998 : (C) == 'J' ? ((VALUE) == 0) \
1999 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2000 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2001 && (((VALUE) & ~2147483647) == 0 \
2002 || ((VALUE) & ~2147483647) == ~2147483647)) \
2003 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2004 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2005 && (((VALUE) & 0x0000ffff) != 0 \
2006 || (((VALUE) & ~2147483647) != 0 \
2007 && ((VALUE) & ~2147483647) != ~2147483647))) \
2008 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2009 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2010 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2013 /* Similar, but for floating constants, and defining letters G and H.
2014 Here VALUE is the CONST_DOUBLE rtx itself. */
2018 'G' : Floating point 0 */
2020 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2022 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2024 /* Letters in the range `Q' through `U' may be defined in a
2025 machine-dependent fashion to stand for arbitrary operand types.
2026 The machine description macro `EXTRA_CONSTRAINT' is passed the
2027 operand as its first argument and the constraint letter as its
2030 `Q' is for mips16 GP relative constants
2031 `R' is for memory references which take 1 word for the instruction.
2032 `S' is for references to extern items which are PIC for OSF/rose.
2033 `T' is for memory addresses that can be used to load two words. */
2035 #define EXTRA_CONSTRAINT(OP,CODE) \
2036 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2037 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2038 && mips16_gp_offset_p (OP)) \
2039 : (GET_CODE (OP) != MEM) ? FALSE \
2040 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2041 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2042 && HALF_PIC_ADDRESS_P (OP)) \
2045 /* Given an rtx X being reloaded into a reg required to be
2046 in class CLASS, return the class of reg to actually use.
2047 In general this is just CLASS; but on some machines
2048 in some cases it is preferable to use a more restrictive class. */
2050 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2051 ((CLASS) != ALL_REGS \
2052 ? (! TARGET_MIPS16 \
2054 : ((CLASS) != GR_REGS \
2057 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2058 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2059 ? (TARGET_SOFT_FLOAT \
2060 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2062 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2063 || GET_MODE (X) == VOIDmode) \
2064 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2067 /* Certain machines have the property that some registers cannot be
2068 copied to some other registers without using memory. Define this
2069 macro on those machines to be a C expression that is non-zero if
2070 objects of mode MODE in registers of CLASS1 can only be copied to
2071 registers of class CLASS2 by storing a register of CLASS1 into
2072 memory and loading that memory location into a register of CLASS2.
2074 Do not define this macro if its value would always be zero. */
2076 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2077 ((!TARGET_DEBUG_H_MODE \
2078 && GET_MODE_CLASS (MODE) == MODE_INT \
2079 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2080 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2081 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2082 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2083 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2085 /* The HI and LO registers can only be reloaded via the general
2086 registers. Condition code registers can only be loaded to the
2087 general registers, and from the floating point registers. */
2089 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2090 mips_secondary_reload_class (CLASS, MODE, X, 1)
2091 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2092 mips_secondary_reload_class (CLASS, MODE, X, 0)
2094 /* Return the maximum number of consecutive registers
2095 needed to represent mode MODE in a register of class CLASS. */
2097 #define CLASS_UNITS(mode, size) \
2098 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2100 #define CLASS_MAX_NREGS(CLASS, MODE) \
2101 ((CLASS) == FP_REGS \
2103 ? CLASS_UNITS (MODE, 8) \
2104 : 2 * CLASS_UNITS (MODE, 8)) \
2105 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2107 /* If defined, gives a class of registers that cannot be used as the
2108 operand of a SUBREG that changes the mode of the object illegally. */
2110 #define CLASS_CANNOT_CHANGE_MODE \
2111 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2113 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2115 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2116 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2118 /* Stack layout; function entry, exit and calling. */
2120 /* Define this if pushing a word on the stack
2121 makes the stack pointer a smaller address. */
2122 #define STACK_GROWS_DOWNWARD
2124 /* Define this if the nominal address of the stack frame
2125 is at the high-address end of the local variables;
2126 that is, each additional local variable allocated
2127 goes at a more negative offset in the frame. */
2128 /* #define FRAME_GROWS_DOWNWARD */
2130 /* Offset within stack frame to start allocating local variables at.
2131 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2132 first local allocated. Otherwise, it is the offset to the BEGINNING
2133 of the first local allocated. */
2134 #define STARTING_FRAME_OFFSET \
2135 (current_function_outgoing_args_size \
2136 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2138 /* Offset from the stack pointer register to an item dynamically
2139 allocated on the stack, e.g., by `alloca'.
2141 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2142 length of the outgoing arguments. The default is correct for most
2143 machines. See `function.c' for details.
2145 The MIPS ABI states that functions which dynamically allocate the
2146 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2147 we are trying to create a second frame pointer to the function, so
2148 allocate some stack space to make it happy.
2150 However, the linker currently complains about linking any code that
2151 dynamically allocates stack space, and there seems to be a bug in
2152 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2155 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2156 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2157 ? 4*UNITS_PER_WORD \
2158 : current_function_outgoing_args_size)
2161 /* The return address for the current frame is in r31 is this is a leaf
2162 function. Otherwise, it is on the stack. It is at a variable offset
2163 from sp/fp/ap, so we define a fake hard register rap which is a
2164 poiner to the return address on the stack. This always gets eliminated
2165 during reload to be either the frame pointer or the stack pointer plus
2168 /* ??? This definition fails for leaf functions. There is currently no
2169 general solution for this problem. */
2171 /* ??? There appears to be no way to get the return address of any previous
2172 frame except by disassembling instructions in the prologue/epilogue.
2173 So currently we support only the current frame. */
2175 #define RETURN_ADDR_RTX(count, frame) \
2177 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2180 /* Structure to be filled in by compute_frame_size with register
2181 save masks, and offsets for the current function. */
2183 struct mips_frame_info
2185 long total_size; /* # bytes that the entire frame takes up */
2186 long var_size; /* # bytes that variables take up */
2187 long args_size; /* # bytes that outgoing arguments take up */
2188 long extra_size; /* # bytes of extra gunk */
2189 int gp_reg_size; /* # bytes needed to store gp regs */
2190 int fp_reg_size; /* # bytes needed to store fp regs */
2191 long mask; /* mask of saved gp registers */
2192 long fmask; /* mask of saved fp registers */
2193 long gp_save_offset; /* offset from vfp to store gp registers */
2194 long fp_save_offset; /* offset from vfp to store fp registers */
2195 long gp_sp_offset; /* offset from new sp to store gp registers */
2196 long fp_sp_offset; /* offset from new sp to store fp registers */
2197 int initialized; /* != 0 if frame size already calculated */
2198 int num_gp; /* number of gp registers saved */
2199 int num_fp; /* number of fp registers saved */
2200 long insns_len; /* length of insns; mips16 only */
2203 extern struct mips_frame_info current_frame_info;
2205 /* If defined, this macro specifies a table of register pairs used to
2206 eliminate unneeded registers that point into the stack frame. If
2207 it is not defined, the only elimination attempted by the compiler
2208 is to replace references to the frame pointer with references to
2211 The definition of this macro is a list of structure
2212 initializations, each of which specifies an original and
2213 replacement register.
2215 On some machines, the position of the argument pointer is not
2216 known until the compilation is completed. In such a case, a
2217 separate hard register must be used for the argument pointer.
2218 This register can be eliminated by replacing it with either the
2219 frame pointer or the argument pointer, depending on whether or not
2220 the frame pointer has been eliminated.
2222 In this case, you might specify:
2223 #define ELIMINABLE_REGS \
2224 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2225 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2226 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2228 Note that the elimination of the argument pointer with the stack
2229 pointer is specified first since that is the preferred elimination.
2231 The eliminations to $17 are only used on the mips16. See the
2232 definition of HARD_FRAME_POINTER_REGNUM. */
2234 #define ELIMINABLE_REGS \
2235 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2236 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2237 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2238 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2239 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2240 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2241 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2242 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2243 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2244 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2246 /* A C expression that returns non-zero if the compiler is allowed to
2247 try to replace register number FROM-REG with register number
2248 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2249 defined, and will usually be the constant 1, since most of the
2250 cases preventing register elimination are things that the compiler
2251 already knows about.
2253 When not in mips16 and mips64, we can always eliminate to the
2254 frame pointer. We can eliminate to the stack pointer unless
2255 a frame pointer is needed. In mips16 mode, we need a frame
2256 pointer for a large frame; otherwise, reload may be unable
2257 to compute the address of a local variable, since there is
2258 no way to add a large constant to the stack pointer
2259 without using a temporary register.
2261 In mips16, for some instructions (eg lwu), we can't eliminate the
2262 frame pointer for the stack pointer. These instructions are
2263 only generated in TARGET_64BIT mode.
2266 #define CAN_ELIMINATE(FROM, TO) \
2267 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2268 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2269 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2270 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2271 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2272 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2273 && (! TARGET_MIPS16 \
2274 || compute_frame_size (get_frame_size ()) < 32768)))))
2276 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2277 specifies the initial difference between the specified pair of
2278 registers. This macro must be defined if `ELIMINABLE_REGS' is
2281 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2282 { compute_frame_size (get_frame_size ()); \
2283 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2284 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2285 (OFFSET) = - current_function_outgoing_args_size; \
2286 else if ((FROM) == FRAME_POINTER_REGNUM) \
2288 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2289 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2290 (OFFSET) = (current_frame_info.total_size \
2291 - current_function_outgoing_args_size \
2292 - ((mips_abi != ABI_32 \
2293 && mips_abi != ABI_O64 \
2294 && mips_abi != ABI_EABI) \
2295 ? current_function_pretend_args_size \
2297 else if ((FROM) == ARG_POINTER_REGNUM) \
2298 (OFFSET) = (current_frame_info.total_size \
2299 - ((mips_abi != ABI_32 \
2300 && mips_abi != ABI_O64 \
2301 && mips_abi != ABI_EABI) \
2302 ? current_function_pretend_args_size \
2304 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2305 so we must add 4 bytes to the offset to get the right value. */ \
2306 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2308 if (leaf_function_p ()) \
2310 else (OFFSET) = current_frame_info.gp_sp_offset \
2311 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2312 * (BYTES_BIG_ENDIAN != 0)); \
2316 /* If we generate an insn to push BYTES bytes,
2317 this says how many the stack pointer really advances by.
2318 On the vax, sp@- in a byte insn really pushes a word. */
2320 /* #define PUSH_ROUNDING(BYTES) 0 */
2322 /* If defined, the maximum amount of space required for outgoing
2323 arguments will be computed and placed into the variable
2324 `current_function_outgoing_args_size'. No space will be pushed
2325 onto the stack for each call; instead, the function prologue
2326 should increase the stack frame size by this amount.
2328 It is not proper to define both `PUSH_ROUNDING' and
2329 `ACCUMULATE_OUTGOING_ARGS'. */
2330 #define ACCUMULATE_OUTGOING_ARGS 1
2332 /* Offset from the argument pointer register to the first argument's
2333 address. On some machines it may depend on the data type of the
2336 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2337 the first argument's address.
2339 On the MIPS, we must skip the first argument position if we are
2340 returning a structure or a union, to account for its address being
2341 passed in $4. However, at the current time, this produces a compiler
2342 that can't bootstrap, so comment it out for now. */
2345 #define FIRST_PARM_OFFSET(FNDECL) \
2347 && TREE_TYPE (FNDECL) != 0 \
2348 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2349 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2350 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2354 #define FIRST_PARM_OFFSET(FNDECL) 0
2357 /* When a parameter is passed in a register, stack space is still
2358 allocated for it. For the MIPS, stack space must be allocated, cf
2359 Asm Lang Prog Guide page 7-8.
2361 BEWARE that some space is also allocated for non existing arguments
2362 in register. In case an argument list is of form GF used registers
2363 are a0 (a2,a3), but we should push over a1... */
2365 #define REG_PARM_STACK_SPACE(FNDECL) \
2366 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2368 /* Define this if it is the responsibility of the caller to
2369 allocate the area reserved for arguments passed in registers.
2370 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2371 of this macro is to determine whether the space is included in
2372 `current_function_outgoing_args_size'. */
2373 #define OUTGOING_REG_PARM_STACK_SPACE
2375 /* Align stack frames on 64 bits (Double Word ). */
2376 #ifndef STACK_BOUNDARY
2377 #define STACK_BOUNDARY 64
2380 /* Make sure 4 words are always allocated on the stack. */
2382 #ifndef STACK_ARGS_ADJUST
2383 #define STACK_ARGS_ADJUST(SIZE) \
2385 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2386 SIZE.constant = 4 * UNITS_PER_WORD; \
2391 /* A C expression that should indicate the number of bytes of its
2392 own arguments that a function pops on returning, or 0
2393 if the function pops no arguments and the caller must therefore
2394 pop them all after the function returns.
2396 FUNDECL is the declaration node of the function (as a tree).
2398 FUNTYPE is a C variable whose value is a tree node that
2399 describes the function in question. Normally it is a node of
2400 type `FUNCTION_TYPE' that describes the data type of the function.
2401 From this it is possible to obtain the data types of the value
2402 and arguments (if known).
2404 When a call to a library function is being considered, FUNTYPE
2405 will contain an identifier node for the library function. Thus,
2406 if you need to distinguish among various library functions, you
2407 can do so by their names. Note that "library function" in this
2408 context means a function used to perform arithmetic, whose name
2409 is known specially in the compiler and was not mentioned in the
2410 C code being compiled.
2412 STACK-SIZE is the number of bytes of arguments passed on the
2413 stack. If a variable number of bytes is passed, it is zero, and
2414 argument popping will always be the responsibility of the
2415 calling function. */
2417 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2420 /* Symbolic macros for the registers used to return integer and floating
2423 #define GP_RETURN (GP_REG_FIRST + 2)
2424 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2426 /* Symbolic macros for the first/last argument registers. */
2428 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2429 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2430 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2431 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2433 #define MAX_ARGS_IN_REGISTERS 4
2435 /* Define how to find the value returned by a library function
2436 assuming the value has mode MODE. Because we define
2437 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2438 PROMOTE_MODE does. */
2440 #define LIBCALL_VALUE(MODE) \
2442 ((GET_MODE_CLASS (MODE) != MODE_INT \
2443 || GET_MODE_SIZE (MODE) >= 4) \
2446 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2447 && (! TARGET_SINGLE_FLOAT \
2448 || GET_MODE_SIZE (MODE) <= 4)) \
2452 /* Define how to find the value returned by a function.
2453 VALTYPE is the data type of the value (as a tree).
2454 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2455 otherwise, FUNC is 0. */
2457 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2460 /* 1 if N is a possible register number for a function value.
2461 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2462 Currently, R2 and F0 are only implemented here (C has no complex type) */
2464 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2466 /* 1 if N is a possible register number for function argument passing.
2467 We have no FP argument registers when soft-float. When FP registers
2468 are 32 bits, we can't directly reference the odd numbered ones. */
2470 #define FUNCTION_ARG_REGNO_P(N) \
2471 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2472 || ((! TARGET_SOFT_FLOAT \
2473 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2474 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2475 && ! fixed_regs[N]))
2477 /* A C expression which can inhibit the returning of certain function
2478 values in registers, based on the type of value. A nonzero value says
2479 to return the function value in memory, just as large structures are
2480 always returned. Here TYPE will be a C expression of type
2481 `tree', representing the data type of the value.
2483 Note that values of mode `BLKmode' must be explicitly
2484 handled by this macro. Also, the option `-fpcc-struct-return'
2485 takes effect regardless of this macro. On most systems, it is
2486 possible to leave the macro undefined; this causes a default
2487 definition to be used, whose value is the constant 1 for BLKmode
2488 values, and 0 otherwise.
2490 GCC normally converts 1 byte structures into chars, 2 byte
2491 structs into shorts, and 4 byte structs into ints, and returns
2492 them this way. Defining the following macro overrides this,
2493 to give us MIPS cc compatibility. */
2495 #define RETURN_IN_MEMORY(TYPE) \
2496 (TYPE_MODE (TYPE) == BLKmode)
2498 /* A code distinguishing the floating point format of the target
2499 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2500 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2502 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2505 /* Define a data type for recording info about an argument list
2506 during the scan of that argument list. This data type should
2507 hold all necessary information about the function itself
2508 and about the args processed so far, enough to enable macros
2509 such as FUNCTION_ARG to determine where the next arg should go.
2511 On the mips16, we need to keep track of which floating point
2512 arguments were passed in general registers, but would have been
2513 passed in the FP regs if this were a 32 bit function, so that we
2514 can move them to the FP regs if we wind up calling a 32 bit
2515 function. We record this information in fp_code, encoded in base
2516 four. A zero digit means no floating point argument, a one digit
2517 means an SFmode argument, and a two digit means a DFmode argument,
2518 and a three digit is not used. The low order digit is the first
2519 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2520 an SFmode argument. ??? A more sophisticated approach will be
2521 needed if MIPS_ABI != ABI_32. */
2523 typedef struct mips_args {
2524 int gp_reg_found; /* whether a gp register was found yet */
2525 unsigned int arg_number; /* argument number */
2526 unsigned int arg_words; /* # total words the arguments take */
2527 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2528 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2529 int fp_code; /* Mode of FP arguments (mips16) */
2530 unsigned int num_adjusts; /* number of adjustments made */
2531 /* Adjustments made to args pass in regs. */
2532 /* ??? The size is doubled to work around a
2533 bug in the code that sets the adjustments
2535 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2538 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2539 for a call to a function whose data type is FNTYPE.
2540 For a library call, FNTYPE is 0.
2544 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2545 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2547 /* Update the data in CUM to advance over an argument
2548 of mode MODE and data type TYPE.
2549 (TYPE is null for libcalls where that information may not be available.) */
2551 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2552 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2554 /* Determine where to put an argument to a function.
2555 Value is zero to push the argument on the stack,
2556 or a hard register in which to store the argument.
2558 MODE is the argument's machine mode.
2559 TYPE is the data type of the argument (as a tree).
2560 This is null for libcalls where that information may
2562 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2563 the preceding args and about the function being called.
2564 NAMED is nonzero if this argument is a named parameter
2565 (otherwise it is an extra parameter matching an ellipsis). */
2567 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2568 function_arg( &CUM, MODE, TYPE, NAMED)
2570 /* For an arg passed partly in registers and partly in memory,
2571 this is the number of registers used.
2572 For args passed entirely in registers or entirely in memory, zero. */
2574 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2575 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2577 /* If defined, a C expression that gives the alignment boundary, in
2578 bits, of an argument with the specified mode and type. If it is
2579 not defined, `PARM_BOUNDARY' is used for all arguments. */
2581 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2583 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2585 : TYPE_ALIGN(TYPE)) \
2586 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2588 : GET_MODE_ALIGNMENT(MODE)))
2591 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2593 #define MUST_SAVE_REGISTER(regno) \
2594 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2595 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2596 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2598 /* ALIGN FRAMES on double word boundaries */
2599 #ifndef MIPS_STACK_ALIGN
2600 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2604 /* Define the `__builtin_va_list' type for the ABI. */
2605 #define BUILD_VA_LIST_TYPE(VALIST) \
2606 (VALIST) = mips_build_va_list ()
2608 /* Implement `va_start' for varargs and stdarg. */
2609 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2610 mips_va_start (stdarg, valist, nextarg)
2612 /* Implement `va_arg'. */
2613 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2614 mips_va_arg (valist, type)
2616 /* Output assembler code to FILE to increment profiler label # LABELNO
2617 for profiling a function entry. */
2619 #define FUNCTION_PROFILER(FILE, LABELNO) \
2621 if (TARGET_MIPS16) \
2622 sorry ("mips16 function profiling"); \
2623 fprintf (FILE, "\t.set\tnoreorder\n"); \
2624 fprintf (FILE, "\t.set\tnoat\n"); \
2625 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2626 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2627 fprintf (FILE, "\tjal\t_mcount\n"); \
2629 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2630 TARGET_64BIT ? "dsubu" : "subu", \
2631 reg_names[STACK_POINTER_REGNUM], \
2632 reg_names[STACK_POINTER_REGNUM], \
2633 Pmode == DImode ? 16 : 8); \
2634 fprintf (FILE, "\t.set\treorder\n"); \
2635 fprintf (FILE, "\t.set\tat\n"); \
2638 /* Define this macro if the code for function profiling should come
2639 before the function prologue. Normally, the profiling code comes
2642 /* #define PROFILE_BEFORE_PROLOGUE */
2644 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2645 the stack pointer does not matter. The value is tested only in
2646 functions that have frame pointers.
2647 No definition is equivalent to always zero. */
2649 #define EXIT_IGNORE_STACK 1
2652 /* A C statement to output, on the stream FILE, assembler code for a
2653 block of data that contains the constant parts of a trampoline.
2654 This code should not include a label--the label is taken care of
2657 #define TRAMPOLINE_TEMPLATE(STREAM) \
2659 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2660 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2661 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2662 if (Pmode == DImode) \
2664 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2665 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2669 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2670 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2672 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2673 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2674 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2675 if (Pmode == DImode) \
2677 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2678 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2682 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2683 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2687 /* A C expression for the size in bytes of the trampoline, as an
2690 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2692 /* Alignment required for trampolines, in bits. */
2694 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2696 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2697 program and data caches. */
2699 #ifndef CACHE_FLUSH_FUNC
2700 #define CACHE_FLUSH_FUNC "_flush_cache"
2703 /* A C statement to initialize the variable parts of a trampoline.
2704 ADDR is an RTX for the address of the trampoline; FNADDR is an
2705 RTX for the address of the nested function; STATIC_CHAIN is an
2706 RTX for the static chain value that should be passed to the
2707 function when it is called. */
2709 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2712 if (Pmode == DImode) \
2714 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2715 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2719 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2720 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2723 /* Flush both caches. We need to flush the data cache in case \
2724 the system has a write-back cache. */ \
2725 /* ??? Should check the return value for errors. */ \
2726 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2727 0, VOIDmode, 3, addr, Pmode, \
2728 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2729 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2732 /* Addressing modes, and classification of registers for them. */
2734 /* #define HAVE_POST_INCREMENT 0 */
2735 /* #define HAVE_POST_DECREMENT 0 */
2737 /* #define HAVE_PRE_DECREMENT 0 */
2738 /* #define HAVE_PRE_INCREMENT 0 */
2740 /* These assume that REGNO is a hard or pseudo reg number.
2741 They give nonzero only if REGNO is a hard reg of the suitable class
2742 or a pseudo reg currently allocated to a suitable hard reg.
2743 These definitions are NOT overridden anywhere. */
2745 #define BASE_REG_P(regno, mode) \
2747 ? (M16_REG_P (regno) \
2748 || (regno) == FRAME_POINTER_REGNUM \
2749 || (regno) == ARG_POINTER_REGNUM \
2750 || ((regno) == STACK_POINTER_REGNUM \
2751 && (GET_MODE_SIZE (mode) == 4 \
2752 || GET_MODE_SIZE (mode) == 8))) \
2755 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2756 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2759 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2760 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2762 #define REGNO_OK_FOR_INDEX_P(regno) 0
2763 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2764 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2766 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2767 and check its validity for a certain class.
2768 We have two alternate definitions for each of them.
2769 The usual definition accepts all pseudo regs; the other rejects them all.
2770 The symbol REG_OK_STRICT causes the latter definition to be used.
2772 Most source files want to accept pseudo regs in the hope that
2773 they will get allocated to the class that the insn wants them to be in.
2774 Some source files that are used after register allocation
2775 need to be strict. */
2777 #ifndef REG_OK_STRICT
2778 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2779 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2781 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2782 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2785 #define REG_OK_FOR_INDEX_P(X) 0
2788 /* Maximum number of registers that can appear in a valid memory address. */
2790 #define MAX_REGS_PER_ADDRESS 1
2792 /* A C compound statement with a conditional `goto LABEL;' executed
2793 if X (an RTX) is a legitimate memory address on the target
2794 machine for a memory operand of mode MODE.
2796 It usually pays to define several simpler macros to serve as
2797 subroutines for this one. Otherwise it may be too complicated
2800 This macro must exist in two variants: a strict variant and a
2801 non-strict one. The strict variant is used in the reload pass.
2802 It must be defined so that any pseudo-register that has not been
2803 allocated a hard register is considered a memory reference. In
2804 contexts where some kind of register is required, a
2805 pseudo-register with no hard register must be rejected.
2807 The non-strict variant is used in other passes. It must be
2808 defined to accept all pseudo-registers in every context where
2809 some kind of register is required.
2811 Compiler source files that want to use the strict variant of
2812 this macro define the macro `REG_OK_STRICT'. You should use an
2813 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2814 in that case and the non-strict variant otherwise.
2816 Typically among the subroutines used to define
2817 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2818 acceptable registers for various purposes (one for base
2819 registers, one for index registers, and so on). Then only these
2820 subroutine macros need have two variants; the higher levels of
2821 macros may be the same whether strict or not.
2823 Normally, constant addresses which are the sum of a `symbol_ref'
2824 and an integer are stored inside a `const' RTX to mark them as
2825 constant. Therefore, there is no need to recognize such sums
2826 specifically as legitimate addresses. Normally you would simply
2827 recognize any `const' as legitimate.
2829 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2830 constant sums that are not marked with `const'. It assumes
2831 that a naked `plus' indicates indexing. If so, then you *must*
2832 reject such naked constant sums as illegitimate addresses, so
2833 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2835 On some machines, whether a symbolic address is legitimate
2836 depends on the section that the address refers to. On these
2837 machines, define the macro `ENCODE_SECTION_INFO' to store the
2838 information into the `symbol_ref', and then check for it here.
2839 When you see a `const', you will have to look inside it to find
2840 the `symbol_ref' in order to determine the section. */
2843 #define GO_PRINTF(x) fprintf(stderr, (x))
2844 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2845 #define GO_DEBUG_RTX(x) debug_rtx(x)
2848 #define GO_PRINTF(x)
2849 #define GO_PRINTF2(x,y)
2850 #define GO_DEBUG_RTX(x)
2853 #ifdef REG_OK_STRICT
2854 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2856 if (mips_legitimate_address_p (MODE, X, 1)) \
2860 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2862 if (mips_legitimate_address_p (MODE, X, 0)) \
2867 /* A C expression that is 1 if the RTX X is a constant which is a
2868 valid address. This is defined to be the same as `CONSTANT_P (X)',
2869 but rejecting CONST_DOUBLE. */
2870 /* When pic, we must reject addresses of the form symbol+large int.
2871 This is because an instruction `sw $4,s+70000' needs to be converted
2872 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2873 assembler would use $at as a temp to load in the large offset. In this
2874 case $at is already in use. We convert such problem addresses to
2875 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2876 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2877 #define CONSTANT_ADDRESS_P(X) \
2878 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2879 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2880 || (GET_CODE (X) == CONST \
2881 && ! (flag_pic && pic_address_needs_scratch (X)) \
2882 && (mips_abi == ABI_32 \
2883 || mips_abi == ABI_O64 \
2884 || mips_abi == ABI_EABI))) \
2885 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2887 /* Define this, so that when PIC, reload won't try to reload invalid
2888 addresses which require two reload registers. */
2890 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2892 /* Nonzero if the constant value X is a legitimate general operand.
2893 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2895 At present, GAS doesn't understand li.[sd], so don't allow it
2896 to be generated at present. Also, the MIPS assembler does not
2897 grok li.d Infinity. */
2899 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2900 Note that the Irix 6 assembler problem may already be fixed.
2901 Note also that the GET_CODE (X) == CONST test catches the mips16
2902 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2903 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2904 ABI_64 to work together, we'll need to fix this. */
2905 #define LEGITIMATE_CONSTANT_P(X) \
2906 ((GET_CODE (X) != CONST_DOUBLE \
2907 || mips_const_double_ok (X, GET_MODE (X))) \
2908 && ! (GET_CODE (X) == CONST \
2910 && (mips_abi == ABI_N32 \
2911 || mips_abi == ABI_64)) \
2912 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2914 /* A C compound statement that attempts to replace X with a valid
2915 memory address for an operand of mode MODE. WIN will be a C
2916 statement label elsewhere in the code; the macro definition may
2919 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2921 to avoid further processing if the address has become legitimate.
2923 X will always be the result of a call to `break_out_memory_refs',
2924 and OLDX will be the operand that was given to that function to
2927 The code generated by this macro should not alter the
2928 substructure of X. If it transforms X into a more legitimate
2929 form, it should assign X (which will always be a C variable) a
2932 It is not necessary for this macro to come up with a legitimate
2933 address. The compiler has standard ways of doing so in all
2934 cases. In fact, it is safe for this macro to do nothing. But
2935 often a machine-dependent strategy can generate better code.
2937 For the MIPS, transform:
2939 memory(X + <large int>)
2943 Y = <large int> & ~0x7fff;
2945 memory (Z + (<large int> & 0x7fff));
2947 This is for CSE to find several similar references, and only use one Z.
2949 When PIC, convert addresses of the form memory (symbol+large int) to
2950 memory (reg+large int). */
2953 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2955 register rtx xinsn = (X); \
2957 if (TARGET_DEBUG_B_MODE) \
2959 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2960 GO_DEBUG_RTX (xinsn); \
2963 if (mips_split_addresses && mips_check_split (X, MODE)) \
2965 /* ??? Is this ever executed? */ \
2966 X = gen_rtx_LO_SUM (Pmode, \
2967 copy_to_mode_reg (Pmode, \
2968 gen_rtx (HIGH, Pmode, X)), \
2973 if (GET_CODE (xinsn) == CONST \
2974 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2975 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2976 || (mips_abi != ABI_32 \
2977 && mips_abi != ABI_O64 \
2978 && mips_abi != ABI_EABI))) \
2980 rtx ptr_reg = gen_reg_rtx (Pmode); \
2981 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2983 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2985 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
2986 if (SMALL_INT (constant)) \
2988 /* Otherwise we fall through so the code below will fix the \
2993 if (GET_CODE (xinsn) == PLUS) \
2995 register rtx xplus0 = XEXP (xinsn, 0); \
2996 register rtx xplus1 = XEXP (xinsn, 1); \
2997 register enum rtx_code code0 = GET_CODE (xplus0); \
2998 register enum rtx_code code1 = GET_CODE (xplus1); \
3000 if (code0 != REG && code1 == REG) \
3002 xplus0 = XEXP (xinsn, 1); \
3003 xplus1 = XEXP (xinsn, 0); \
3004 code0 = GET_CODE (xplus0); \
3005 code1 = GET_CODE (xplus1); \
3008 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3009 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3011 rtx int_reg = gen_reg_rtx (Pmode); \
3012 rtx ptr_reg = gen_reg_rtx (Pmode); \
3014 emit_move_insn (int_reg, \
3015 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3017 emit_insn (gen_rtx_SET (VOIDmode, \
3019 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3021 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3026 if (TARGET_DEBUG_B_MODE) \
3027 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3031 /* A C statement or compound statement with a conditional `goto
3032 LABEL;' executed if memory address X (an RTX) can have different
3033 meanings depending on the machine mode of the memory reference it
3036 Autoincrement and autodecrement addresses typically have
3037 mode-dependent effects because the amount of the increment or
3038 decrement is the size of the operand being addressed. Some
3039 machines have other mode-dependent addresses. Many RISC machines
3040 have no mode-dependent addresses.
3042 You may assume that ADDR is a valid address for the machine. */
3044 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3047 /* Define this macro if references to a symbol must be treated
3048 differently depending on something about the variable or
3049 function named by the symbol (such as what section it is in).
3051 The macro definition, if any, is executed immediately after the
3052 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3053 The value of the rtl will be a `mem' whose address is a
3056 The usual thing for this macro to do is to a flag in the
3057 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3058 name string in the `symbol_ref' (if one bit is not enough
3061 The best way to modify the name string is by adding text to the
3062 beginning, with suitable punctuation to prevent any ambiguity.
3063 Allocate the new name in `saveable_obstack'. You will have to
3064 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3065 and output the name accordingly.
3067 You can also check the information stored in the `symbol_ref' in
3068 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3069 `PRINT_OPERAND_ADDRESS'.
3071 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3074 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3075 symbols which are not in the .text section.
3077 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3078 constants which are put in the .text section. We also record the
3079 total length of all such strings; this total is used to decide
3080 whether we need to split the constant table, and need not be
3083 When not mips16 code nor embedded PIC, if a symbol is in a
3084 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3085 splitting the reference so that gas can generate a gp relative
3088 When TARGET_EMBEDDED_DATA is set, we assume that all const
3089 variables will be stored in ROM, which is too far from %gp to use
3090 %gprel addressing. Note that (1) we include "extern const"
3091 variables in this, which mips_select_section doesn't, and (2) we
3092 can't always tell if they're really const (they might be const C++
3093 objects with non-const constructors), so we err on the side of
3094 caution and won't use %gprel anyway (otherwise we'd have to defer
3095 this decision to the linker/loader). The handling of extern consts
3096 is why the DECL_INITIAL macros differ from mips_select_section.
3098 If you are changing this macro, you should look at
3099 mips_select_section and see if it needs a similar change. */
3101 #ifndef UNIQUE_SECTION_P
3102 #define UNIQUE_SECTION_P(DECL) (0)
3105 #define ENCODE_SECTION_INFO(DECL) \
3108 if (TARGET_MIPS16) \
3110 if (TREE_CODE (DECL) == STRING_CST \
3111 && ! flag_writable_strings \
3112 /* If this string is from a function, and the function will \
3113 go in a gnu linkonce section, then we can't directly \
3114 access the string. This gets an assembler error \
3115 "unsupported PC relative reference to different section".\
3116 If we modify SELECT_SECTION to put it in function_section\
3117 instead of text_section, it still fails because \
3118 DECL_SECTION_NAME isn't set until assemble_start_function.\
3119 If we fix that, it still fails because strings are shared\
3120 among multiple functions, and we have cross section \
3121 references again. We force it to work by putting string \
3122 addresses in the constant pool and indirecting. */ \
3123 && (! current_function_decl \
3124 || ! UNIQUE_SECTION_P (current_function_decl))) \
3126 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3127 mips_string_length += TREE_STRING_LENGTH (DECL); \
3131 if (TARGET_EMBEDDED_DATA \
3132 && (TREE_CODE (DECL) == VAR_DECL \
3133 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3134 && (!DECL_INITIAL (DECL) \
3135 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3137 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3140 else if (TARGET_EMBEDDED_PIC) \
3142 if (TREE_CODE (DECL) == VAR_DECL) \
3143 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3144 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3145 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3146 else if (TREE_CODE (DECL) == STRING_CST \
3147 && ! flag_writable_strings) \
3148 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3150 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3153 else if (TREE_CODE (DECL) == VAR_DECL \
3154 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3155 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3157 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3160 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3163 /* We can not perform GP optimizations on variables which are in \
3164 specific sections, except for .sdata and .sbss which are \
3166 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3167 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3169 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3171 if (size > 0 && size <= mips_section_threshold) \
3172 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3175 else if (HALF_PIC_P ()) \
3177 HALF_PIC_ENCODE (DECL); \
3182 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3183 'the start of the function that this code is output in'. */
3185 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3186 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3187 asm_fprintf ((FILE), "%U%s", \
3188 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3190 asm_fprintf ((FILE), "%U%s", (NAME))
3192 /* The mips16 wants the constant pool to be after the function,
3193 because the PC relative load instructions use unsigned offsets. */
3195 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3197 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3198 mips_string_length = 0;
3201 /* In mips16 mode, put most string constants after the function. */
3202 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3203 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3206 /* Specify the machine mode that this machine uses
3207 for the index in the tablejump instruction.
3208 ??? Using HImode in mips16 mode can cause overflow. However, the
3209 overflow is no more likely than the overflow in a branch
3210 instruction. Large functions can currently break in both ways. */
3211 #define CASE_VECTOR_MODE \
3212 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3214 /* Define as C expression which evaluates to nonzero if the tablejump
3215 instruction expects the table to contain offsets from the address of the
3217 Do not define this if the table should contain absolute addresses. */
3218 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3220 /* Specify the tree operation to be used to convert reals to integers. */
3221 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3223 /* This is the kind of divide that is easiest to do in the general case. */
3224 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3226 /* Define this as 1 if `char' should by default be signed; else as 0. */
3227 #ifndef DEFAULT_SIGNED_CHAR
3228 #define DEFAULT_SIGNED_CHAR 1
3231 /* Max number of bytes we can move from memory to memory
3232 in one reasonably fast instruction. */
3233 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3234 #define MAX_MOVE_MAX 8
3236 /* Define this macro as a C expression which is nonzero if
3237 accessing less than a word of memory (i.e. a `char' or a
3238 `short') is no faster than accessing a word of memory, i.e., if
3239 such access require more than one instruction or if there is no
3240 difference in cost between byte and (aligned) word loads.
3242 On RISC machines, it tends to generate better code to define
3243 this as 1, since it avoids making a QI or HI mode register. */
3244 #define SLOW_BYTE_ACCESS 1
3246 /* We assume that the store-condition-codes instructions store 0 for false
3247 and some other value for true. This is the value stored for true. */
3249 #define STORE_FLAG_VALUE 1
3251 /* Define this if zero-extension is slow (more than one real instruction). */
3252 #define SLOW_ZERO_EXTEND
3254 /* Define this to be nonzero if shift instructions ignore all but the low-order
3256 #define SHIFT_COUNT_TRUNCATED 1
3258 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3259 is done just by pretending it is already truncated. */
3260 /* In 64 bit mode, 32 bit instructions require that register values be properly
3261 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3262 converts a value >32 bits to a value <32 bits. */
3263 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3264 Something needs to be done about this. Perhaps not use any 32 bit
3265 instructions? Perhaps use PROMOTE_MODE? */
3266 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3267 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3269 /* Specify the machine mode that pointers have.
3270 After generation of rtl, the compiler makes no further distinction
3271 between pointers and any other objects of this machine mode.
3273 For MIPS we make pointers are the smaller of longs and gp-registers. */
3276 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3279 /* A function address in a call instruction
3280 is a word address (for indexing purposes)
3281 so give the MEM rtx a words's mode. */
3283 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3285 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3286 memset, instead of the BSD functions bcopy and bzero. */
3288 #if defined(MIPS_SYSV) || defined(OSF_OS)
3289 #define TARGET_MEM_FUNCTIONS
3293 /* A part of a C `switch' statement that describes the relative
3294 costs of constant RTL expressions. It must contain `case'
3295 labels for expression codes `const_int', `const', `symbol_ref',
3296 `label_ref' and `const_double'. Each case must ultimately reach
3297 a `return' statement to return the relative cost of the use of
3298 that kind of constant value in an expression. The cost may
3299 depend on the precise value of the constant, which is available
3300 for examination in X.
3302 CODE is the expression code--redundant, since it can be obtained
3303 with `GET_CODE (X)'. */
3305 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3307 if (! TARGET_MIPS16) \
3309 /* Always return 0, since we don't have different sized \
3310 instructions, hence different costs according to Richard \
3314 if ((OUTER_CODE) == SET) \
3316 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3318 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3319 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3320 return COSTS_N_INSNS (1); \
3322 return COSTS_N_INSNS (2); \
3324 /* A PLUS could be an address. We don't want to force an address \
3325 to use a register, so accept any signed 16 bit value without \
3327 if ((OUTER_CODE) == PLUS \
3328 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3330 /* A number between 1 and 8 inclusive is efficient for a shift. \
3331 Otherwise, we will need an extended instruction. */ \
3332 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3333 || (OUTER_CODE) == LSHIFTRT) \
3335 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3337 return COSTS_N_INSNS (1); \
3339 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3340 if ((OUTER_CODE) == XOR \
3341 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3343 /* We may be able to use slt or sltu for a comparison with a \
3344 signed 16 bit value. (The boundary conditions aren't quite \
3345 right, but this is just a heuristic anyhow.) */ \
3346 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3347 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3348 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3349 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3350 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3352 /* Equality comparisons with 0 are cheap. */ \
3353 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3354 && INTVAL (X) == 0) \
3357 /* Otherwise, work out the cost to load the value into a \
3359 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3360 return COSTS_N_INSNS (1); \
3361 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3362 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3363 return COSTS_N_INSNS (2); \
3365 return COSTS_N_INSNS (3); \
3368 return COSTS_N_INSNS (2); \
3372 rtx offset = const0_rtx; \
3373 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3375 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3377 /* Treat this like a signed 16 bit CONST_INT. */ \
3378 if ((OUTER_CODE) == PLUS) \
3380 else if ((OUTER_CODE) == SET) \
3381 return COSTS_N_INSNS (1); \
3383 return COSTS_N_INSNS (2); \
3386 if (GET_CODE (symref) == LABEL_REF) \
3387 return COSTS_N_INSNS (2); \
3389 if (GET_CODE (symref) != SYMBOL_REF) \
3390 return COSTS_N_INSNS (4); \
3392 /* let's be paranoid.... */ \
3393 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3394 return COSTS_N_INSNS (2); \
3396 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3400 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3402 case CONST_DOUBLE: \
3405 if (TARGET_MIPS16) \
3406 return COSTS_N_INSNS (4); \
3407 split_double (X, &high, &low); \
3408 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3409 || low == CONST0_RTX (GET_MODE (low))) \
3413 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3414 This can be used, for example, to indicate how costly a multiply
3415 instruction is. In writing this macro, you can use the construct
3416 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3418 This macro is optional; do not define it if the default cost
3419 assumptions are adequate for the target machine.
3421 If -mdebugd is used, change the multiply cost to 2, so multiply by
3422 a constant isn't converted to a series of shifts. This helps
3423 strength reduction, and also makes it easier to identify what the
3424 compiler is doing. */
3426 /* ??? Fix this to be right for the R8000. */
3427 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3430 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3431 if (simple_memory_operand (X, GET_MODE (X))) \
3432 return COSTS_N_INSNS (num_words); \
3434 return COSTS_N_INSNS (2*num_words); \
3438 return COSTS_N_INSNS (6); \
3441 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3446 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3447 return COSTS_N_INSNS (2); \
3454 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3455 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3461 enum machine_mode xmode = GET_MODE (X); \
3462 if (xmode == SFmode || xmode == DFmode) \
3463 return COSTS_N_INSNS (1); \
3465 return COSTS_N_INSNS (4); \
3471 enum machine_mode xmode = GET_MODE (X); \
3472 if (xmode == SFmode || xmode == DFmode) \
3476 return COSTS_N_INSNS (2); \
3477 else if (TUNE_MIPS6000) \
3478 return COSTS_N_INSNS (3); \
3480 return COSTS_N_INSNS (6); \
3483 if (xmode == DImode && !TARGET_64BIT) \
3484 return COSTS_N_INSNS (4); \
3490 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3497 enum machine_mode xmode = GET_MODE (X); \
3498 if (xmode == SFmode) \
3503 return COSTS_N_INSNS (4); \
3504 else if (TUNE_MIPS6000) \
3505 return COSTS_N_INSNS (5); \
3507 return COSTS_N_INSNS (7); \
3510 if (xmode == DFmode) \
3515 return COSTS_N_INSNS (5); \
3516 else if (TUNE_MIPS6000) \
3517 return COSTS_N_INSNS (6); \
3519 return COSTS_N_INSNS (8); \
3522 if (TUNE_MIPS3000) \
3523 return COSTS_N_INSNS (12); \
3524 else if (TUNE_MIPS3900) \
3525 return COSTS_N_INSNS (2); \
3526 else if (TUNE_MIPS6000) \
3527 return COSTS_N_INSNS (17); \
3528 else if (TUNE_MIPS5000) \
3529 return COSTS_N_INSNS (5); \
3531 return COSTS_N_INSNS (10); \
3537 enum machine_mode xmode = GET_MODE (X); \
3538 if (xmode == SFmode) \
3542 return COSTS_N_INSNS (12); \
3543 else if (TUNE_MIPS6000) \
3544 return COSTS_N_INSNS (15); \
3546 return COSTS_N_INSNS (23); \
3549 if (xmode == DFmode) \
3553 return COSTS_N_INSNS (19); \
3554 else if (TUNE_MIPS6000) \
3555 return COSTS_N_INSNS (16); \
3557 return COSTS_N_INSNS (36); \
3560 /* fall through */ \
3566 return COSTS_N_INSNS (35); \
3567 else if (TUNE_MIPS6000) \
3568 return COSTS_N_INSNS (38); \
3569 else if (TUNE_MIPS5000) \
3570 return COSTS_N_INSNS (36); \
3572 return COSTS_N_INSNS (69); \
3575 /* A sign extend from SImode to DImode in 64 bit mode is often \
3576 zero instructions, because the result can often be used \
3577 directly by another instruction; we'll call it one. */ \
3578 if (TARGET_64BIT && GET_MODE (X) == DImode \
3579 && GET_MODE (XEXP (X, 0)) == SImode) \
3580 return COSTS_N_INSNS (1); \
3582 return COSTS_N_INSNS (2); \
3585 if (TARGET_64BIT && GET_MODE (X) == DImode \
3586 && GET_MODE (XEXP (X, 0)) == SImode) \
3587 return COSTS_N_INSNS (2); \
3589 return COSTS_N_INSNS (1);
3591 /* An expression giving the cost of an addressing mode that
3592 contains ADDRESS. If not defined, the cost is computed from the
3593 form of the ADDRESS expression and the `CONST_COSTS' values.
3595 For most CISC machines, the default cost is a good approximation
3596 of the true cost of the addressing mode. However, on RISC
3597 machines, all instructions normally have the same length and
3598 execution time. Hence all addresses will have equal costs.
3600 In cases where more than one form of an address is known, the
3601 form with the lowest cost will be used. If multiple forms have
3602 the same, lowest, cost, the one that is the most complex will be
3605 For example, suppose an address that is equal to the sum of a
3606 register and a constant is used twice in the same basic block.
3607 When this macro is not defined, the address will be computed in
3608 a register and memory references will be indirect through that
3609 register. On machines where the cost of the addressing mode
3610 containing the sum is no higher than that of a simple indirect
3611 reference, this will produce an additional instruction and
3612 possibly require an additional register. Proper specification
3613 of this macro eliminates this overhead for such machines.
3615 Similar use of this macro is made in strength reduction of loops.
3617 ADDRESS need not be valid as an address. In such a case, the
3618 cost is not relevant and can be any value; invalid addresses
3619 need not be assigned a different cost.
3621 On machines where an address involving more than one register is
3622 as cheap as an address computation involving only one register,
3623 defining `ADDRESS_COST' to reflect this can cause two registers
3624 to be live over a region of code where only one would have been
3625 if `ADDRESS_COST' were not defined in that manner. This effect
3626 should be considered in the definition of this macro.
3627 Equivalent costs should probably only be given to addresses with
3628 different numbers of registers on machines with lots of registers.
3630 This macro will normally either not be defined or be defined as
3633 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3635 /* A C expression for the cost of moving data from a register in
3636 class FROM to one in class TO. The classes are expressed using
3637 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3638 the default; other values are interpreted relative to that.
3640 It is not required that the cost always equal 2 when FROM is the
3641 same as TO; on some machines it is expensive to move between
3642 registers if they are not general registers.
3644 If reload sees an insn consisting of a single `set' between two
3645 hard registers, and if `REGISTER_MOVE_COST' applied to their
3646 classes returns a value of 2, reload does not check to ensure
3647 that the constraints of the insn are met. Setting a cost of
3648 other than 2 will allow reload to verify that the constraints are
3649 met. You should do this if the `movM' pattern's constraints do
3650 not allow such copying.
3652 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3653 registers the same as for one of moving general registers to
3654 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3655 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3656 isn't clear if it is wise. And it might not work in all cases. We
3657 could solve the DImode LO reg problem by using a multiply, just like
3658 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3659 by using divide instructions. divu puts the remainder in the HI
3660 reg, so doing a divide by -1 will move the value in the HI reg for
3661 all values except -1. We could handle that case by using a signed
3662 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3663 compare/branch to test the input value to see which instruction we
3664 need to use. This gets pretty messy, but it is feasible. */
3666 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3667 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3668 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3669 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3670 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3671 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3672 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3673 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3674 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3675 : (((FROM) == HI_REG || (FROM) == LO_REG \
3676 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3677 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3678 : (((TO) == HI_REG || (TO) == LO_REG \
3679 || (TO) == MD_REGS || (TO) == HILO_REG) \
3680 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3681 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3682 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3685 /* ??? Fix this to be right for the R8000. */
3686 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3687 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3688 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3690 /* Define if copies to/from condition code registers should be avoided.
3692 This is needed for the MIPS because reload_outcc is not complete;
3693 it needs to handle cases where the source is a general or another
3694 condition code register. */
3695 #define AVOID_CCMODE_COPIES
3697 /* A C expression for the cost of a branch instruction. A value of
3698 1 is the default; other values are interpreted relative to that. */
3700 /* ??? Fix this to be right for the R8000. */
3701 #define BRANCH_COST \
3703 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3706 /* A C statement (sans semicolon) to update the integer variable COST
3707 based on the relationship between INSN that is dependent on
3708 DEP_INSN through the dependence LINK. The default is to make no
3709 adjustment to COST. On the MIPS, ignore the cost of anti- and
3710 output-dependencies. */
3712 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3713 if (REG_NOTE_KIND (LINK) != 0) \
3714 (COST) = 0; /* Anti or output dependence. */
3716 /* If defined, modifies the length assigned to instruction INSN as a
3717 function of the context in which it is used. LENGTH is an lvalue
3718 that contains the initially computed length of the insn and should
3719 be updated with the correct length of the insn. */
3720 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3721 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3724 /* Optionally define this if you have added predicates to
3725 `MACHINE.c'. This macro is called within an initializer of an
3726 array of structures. The first field in the structure is the
3727 name of a predicate and the second field is an array of rtl
3728 codes. For each predicate, list all rtl codes that can be in
3729 expressions matched by the predicate. The list should have a
3730 trailing comma. Here is an example of two entries in the list
3731 for a typical RISC machine:
3733 #define PREDICATE_CODES \
3734 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3735 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3737 Defining this macro does not affect the generated code (however,
3738 incorrect definitions that omit an rtl code that may be matched
3739 by the predicate can cause the compiler to malfunction).
3740 Instead, it allows the table built by `genrecog' to be more
3741 compact and efficient, thus speeding up the compiler. The most
3742 important predicates to include in the list specified by this
3743 macro are thoses used in the most insn patterns. */
3745 #define PREDICATE_CODES \
3746 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3747 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3748 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3749 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3750 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3751 {"small_int", { CONST_INT }}, \
3752 {"large_int", { CONST_INT }}, \
3753 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3754 {"const_float_1_operand", { CONST_DOUBLE }}, \
3755 {"simple_memory_operand", { MEM, SUBREG }}, \
3756 {"equality_op", { EQ, NE }}, \
3757 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3759 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3760 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3761 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3762 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3763 SYMBOL_REF, LABEL_REF, SUBREG, \
3765 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3766 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3767 MEM, SIGN_EXTEND }}, \
3768 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3769 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3771 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3773 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3775 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3776 SYMBOL_REF, LABEL_REF, SUBREG, \
3777 REG, SIGN_EXTEND }}, \
3778 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3779 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3780 CONST_DOUBLE, CONST }}, \
3781 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3782 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3784 /* A list of predicates that do special things with modes, and so
3785 should not elicit warnings for VOIDmode match_operand. */
3787 #define SPECIAL_MODE_PREDICATES \
3788 "pc_or_label_operand",
3791 /* If defined, a C statement to be executed just prior to the
3792 output of assembler code for INSN, to modify the extracted
3793 operands so they will be output differently.
3795 Here the argument OPVEC is the vector containing the operands
3796 extracted from INSN, and NOPERANDS is the number of elements of
3797 the vector which contain meaningful data for this insn. The
3798 contents of this vector are what will be used to convert the
3799 insn template into assembler code, so you can change the
3800 assembler output by changing the contents of the vector.
3802 We use it to check if the current insn needs a nop in front of it
3803 because of load delays, and also to update the delay slot
3806 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3807 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3810 /* Control the assembler format that we output. */
3812 /* Output at beginning of assembler file.
3813 If we are optimizing to use the global pointer, create a temporary
3814 file to hold all of the text stuff, and write it out to the end.
3815 This is needed because the MIPS assembler is evidently one pass,
3816 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3817 declaration when the code is processed, it generates a two
3818 instruction sequence. */
3820 #undef ASM_FILE_START
3821 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3823 /* Output to assembler file text saying following lines
3824 may contain character constants, extra white space, comments, etc. */
3826 #define ASM_APP_ON " #APP\n"
3828 /* Output to assembler file text saying following lines
3829 no longer contain unusual constructs. */
3831 #define ASM_APP_OFF " #NO_APP\n"
3833 /* How to refer to registers in assembler output.
3834 This sequence is indexed by compiler's hard-register-number (see above).
3836 In order to support the two different conventions for register names,
3837 we use the name of a table set up in mips.c, which is overwritten
3838 if -mrnames is used. */
3840 #define REGISTER_NAMES \
3842 &mips_reg_names[ 0][0], \
3843 &mips_reg_names[ 1][0], \
3844 &mips_reg_names[ 2][0], \
3845 &mips_reg_names[ 3][0], \
3846 &mips_reg_names[ 4][0], \
3847 &mips_reg_names[ 5][0], \
3848 &mips_reg_names[ 6][0], \
3849 &mips_reg_names[ 7][0], \
3850 &mips_reg_names[ 8][0], \
3851 &mips_reg_names[ 9][0], \
3852 &mips_reg_names[10][0], \
3853 &mips_reg_names[11][0], \
3854 &mips_reg_names[12][0], \
3855 &mips_reg_names[13][0], \
3856 &mips_reg_names[14][0], \
3857 &mips_reg_names[15][0], \
3858 &mips_reg_names[16][0], \
3859 &mips_reg_names[17][0], \
3860 &mips_reg_names[18][0], \
3861 &mips_reg_names[19][0], \
3862 &mips_reg_names[20][0], \
3863 &mips_reg_names[21][0], \
3864 &mips_reg_names[22][0], \
3865 &mips_reg_names[23][0], \
3866 &mips_reg_names[24][0], \
3867 &mips_reg_names[25][0], \
3868 &mips_reg_names[26][0], \
3869 &mips_reg_names[27][0], \
3870 &mips_reg_names[28][0], \
3871 &mips_reg_names[29][0], \
3872 &mips_reg_names[30][0], \
3873 &mips_reg_names[31][0], \
3874 &mips_reg_names[32][0], \
3875 &mips_reg_names[33][0], \
3876 &mips_reg_names[34][0], \
3877 &mips_reg_names[35][0], \
3878 &mips_reg_names[36][0], \
3879 &mips_reg_names[37][0], \
3880 &mips_reg_names[38][0], \
3881 &mips_reg_names[39][0], \
3882 &mips_reg_names[40][0], \
3883 &mips_reg_names[41][0], \
3884 &mips_reg_names[42][0], \
3885 &mips_reg_names[43][0], \
3886 &mips_reg_names[44][0], \
3887 &mips_reg_names[45][0], \
3888 &mips_reg_names[46][0], \
3889 &mips_reg_names[47][0], \
3890 &mips_reg_names[48][0], \
3891 &mips_reg_names[49][0], \
3892 &mips_reg_names[50][0], \
3893 &mips_reg_names[51][0], \
3894 &mips_reg_names[52][0], \
3895 &mips_reg_names[53][0], \
3896 &mips_reg_names[54][0], \
3897 &mips_reg_names[55][0], \
3898 &mips_reg_names[56][0], \
3899 &mips_reg_names[57][0], \
3900 &mips_reg_names[58][0], \
3901 &mips_reg_names[59][0], \
3902 &mips_reg_names[60][0], \
3903 &mips_reg_names[61][0], \
3904 &mips_reg_names[62][0], \
3905 &mips_reg_names[63][0], \
3906 &mips_reg_names[64][0], \
3907 &mips_reg_names[65][0], \
3908 &mips_reg_names[66][0], \
3909 &mips_reg_names[67][0], \
3910 &mips_reg_names[68][0], \
3911 &mips_reg_names[69][0], \
3912 &mips_reg_names[70][0], \
3913 &mips_reg_names[71][0], \
3914 &mips_reg_names[72][0], \
3915 &mips_reg_names[73][0], \
3916 &mips_reg_names[74][0], \
3917 &mips_reg_names[75][0], \
3920 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3921 So define this for it. */
3922 #define DEBUG_REGISTER_NAMES \
3924 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3925 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3926 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3927 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3928 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3929 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3930 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3931 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3932 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3933 "$fcc5","$fcc6","$fcc7","$rap" \
3936 /* If defined, a C initializer for an array of structures
3937 containing a name and a register number. This macro defines
3938 additional names for hard registers, thus allowing the `asm'
3939 option in declarations to refer to registers using alternate
3942 We define both names for the integer registers here. */
3944 #define ADDITIONAL_REGISTER_NAMES \
3946 { "$0", 0 + GP_REG_FIRST }, \
3947 { "$1", 1 + GP_REG_FIRST }, \
3948 { "$2", 2 + GP_REG_FIRST }, \
3949 { "$3", 3 + GP_REG_FIRST }, \
3950 { "$4", 4 + GP_REG_FIRST }, \
3951 { "$5", 5 + GP_REG_FIRST }, \
3952 { "$6", 6 + GP_REG_FIRST }, \
3953 { "$7", 7 + GP_REG_FIRST }, \
3954 { "$8", 8 + GP_REG_FIRST }, \
3955 { "$9", 9 + GP_REG_FIRST }, \
3956 { "$10", 10 + GP_REG_FIRST }, \
3957 { "$11", 11 + GP_REG_FIRST }, \
3958 { "$12", 12 + GP_REG_FIRST }, \
3959 { "$13", 13 + GP_REG_FIRST }, \
3960 { "$14", 14 + GP_REG_FIRST }, \
3961 { "$15", 15 + GP_REG_FIRST }, \
3962 { "$16", 16 + GP_REG_FIRST }, \
3963 { "$17", 17 + GP_REG_FIRST }, \
3964 { "$18", 18 + GP_REG_FIRST }, \
3965 { "$19", 19 + GP_REG_FIRST }, \
3966 { "$20", 20 + GP_REG_FIRST }, \
3967 { "$21", 21 + GP_REG_FIRST }, \
3968 { "$22", 22 + GP_REG_FIRST }, \
3969 { "$23", 23 + GP_REG_FIRST }, \
3970 { "$24", 24 + GP_REG_FIRST }, \
3971 { "$25", 25 + GP_REG_FIRST }, \
3972 { "$26", 26 + GP_REG_FIRST }, \
3973 { "$27", 27 + GP_REG_FIRST }, \
3974 { "$28", 28 + GP_REG_FIRST }, \
3975 { "$29", 29 + GP_REG_FIRST }, \
3976 { "$30", 30 + GP_REG_FIRST }, \
3977 { "$31", 31 + GP_REG_FIRST }, \
3978 { "$sp", 29 + GP_REG_FIRST }, \
3979 { "$fp", 30 + GP_REG_FIRST }, \
3980 { "at", 1 + GP_REG_FIRST }, \
3981 { "v0", 2 + GP_REG_FIRST }, \
3982 { "v1", 3 + GP_REG_FIRST }, \
3983 { "a0", 4 + GP_REG_FIRST }, \
3984 { "a1", 5 + GP_REG_FIRST }, \
3985 { "a2", 6 + GP_REG_FIRST }, \
3986 { "a3", 7 + GP_REG_FIRST }, \
3987 { "t0", 8 + GP_REG_FIRST }, \
3988 { "t1", 9 + GP_REG_FIRST }, \
3989 { "t2", 10 + GP_REG_FIRST }, \
3990 { "t3", 11 + GP_REG_FIRST }, \
3991 { "t4", 12 + GP_REG_FIRST }, \
3992 { "t5", 13 + GP_REG_FIRST }, \
3993 { "t6", 14 + GP_REG_FIRST }, \
3994 { "t7", 15 + GP_REG_FIRST }, \
3995 { "s0", 16 + GP_REG_FIRST }, \
3996 { "s1", 17 + GP_REG_FIRST }, \
3997 { "s2", 18 + GP_REG_FIRST }, \
3998 { "s3", 19 + GP_REG_FIRST }, \
3999 { "s4", 20 + GP_REG_FIRST }, \
4000 { "s5", 21 + GP_REG_FIRST }, \
4001 { "s6", 22 + GP_REG_FIRST }, \
4002 { "s7", 23 + GP_REG_FIRST }, \
4003 { "t8", 24 + GP_REG_FIRST }, \
4004 { "t9", 25 + GP_REG_FIRST }, \
4005 { "k0", 26 + GP_REG_FIRST }, \
4006 { "k1", 27 + GP_REG_FIRST }, \
4007 { "gp", 28 + GP_REG_FIRST }, \
4008 { "sp", 29 + GP_REG_FIRST }, \
4009 { "fp", 30 + GP_REG_FIRST }, \
4010 { "ra", 31 + GP_REG_FIRST }, \
4011 { "$sp", 29 + GP_REG_FIRST }, \
4012 { "$fp", 30 + GP_REG_FIRST } \
4015 /* A C compound statement to output to stdio stream STREAM the
4016 assembler syntax for an instruction operand X. X is an RTL
4019 CODE is a value that can be used to specify one of several ways
4020 of printing the operand. It is used when identical operands
4021 must be printed differently depending on the context. CODE
4022 comes from the `%' specification that was used to request
4023 printing of the operand. If the specification was just `%DIGIT'
4024 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4025 is the ASCII code for LTR.
4027 If X is a register, this macro should print the register's name.
4028 The names can be found in an array `reg_names' whose type is
4029 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4031 When the machine description has a specification `%PUNCT' (a `%'
4032 followed by a punctuation character), this macro is called with
4033 a null pointer for X and the punctuation character for CODE.
4035 See mips.c for the MIPS specific codes. */
4037 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4039 /* A C expression which evaluates to true if CODE is a valid
4040 punctuation character for use in the `PRINT_OPERAND' macro. If
4041 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4042 punctuation characters (except for the standard one, `%') are
4043 used in this way. */
4045 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4047 /* A C compound statement to output to stdio stream STREAM the
4048 assembler syntax for an instruction operand that is a memory
4049 reference whose address is ADDR. ADDR is an RTL expression.
4051 On some machines, the syntax for a symbolic address depends on
4052 the section that the address refers to. On these machines,
4053 define the macro `ENCODE_SECTION_INFO' to store the information
4054 into the `symbol_ref', and then check for it here. */
4056 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4059 /* A C statement, to be executed after all slot-filler instructions
4060 have been output. If necessary, call `dbr_sequence_length' to
4061 determine the number of slots filled in a sequence (zero if not
4062 currently outputting a sequence), to decide how many no-ops to
4063 output, or whatever.
4065 Don't define this macro if it has nothing to do, but it is
4066 helpful in reading assembly output if the extent of the delay
4067 sequence is made explicit (e.g. with white space).
4069 Note that output routines for instructions with delay slots must
4070 be prepared to deal with not being output as part of a sequence
4071 (i.e. when the scheduling pass is not run, or when no slot
4072 fillers could be found.) The variable `final_sequence' is null
4073 when not processing a sequence, otherwise it contains the
4074 `sequence' rtx being output. */
4076 #define DBR_OUTPUT_SEQEND(STREAM) \
4079 if (set_nomacro > 0 && --set_nomacro == 0) \
4080 fputs ("\t.set\tmacro\n", STREAM); \
4082 if (set_noreorder > 0 && --set_noreorder == 0) \
4083 fputs ("\t.set\treorder\n", STREAM); \
4085 dslots_jump_filled++; \
4086 fputs ("\n", STREAM); \
4091 /* How to tell the debugger about changes of source files. Note, the
4092 mips ECOFF format cannot deal with changes of files inside of
4093 functions, which means the output of parser generators like bison
4094 is generally not debuggable without using the -l switch. Lose,
4095 lose, lose. Silicon graphics seems to want all .file's hardwired
4098 #ifndef SET_FILE_NUMBER
4099 #define SET_FILE_NUMBER() ++num_source_filenames
4102 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4103 mips_output_filename (STREAM, NAME)
4105 /* This is defined so that it can be overridden in iris6.h. */
4106 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4109 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4110 output_quoted_string (STREAM, NAME); \
4111 fputs ("\n", STREAM); \
4115 /* This is how to output a note the debugger telling it the line number
4116 to which the following sequence of instructions corresponds.
4117 Silicon graphics puts a label after each .loc. */
4119 #ifndef LABEL_AFTER_LOC
4120 #define LABEL_AFTER_LOC(STREAM)
4123 #undef ASM_OUTPUT_SOURCE_LINE
4124 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4125 mips_output_lineno (STREAM, LINE)
4127 /* The MIPS implementation uses some labels for its own purpose. The
4128 following lists what labels are created, and are all formed by the
4129 pattern $L[a-z].*. The machine independent portion of GCC creates
4130 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4132 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4133 $Lb[0-9]+ Begin blocks for MIPS debug support
4134 $Lc[0-9]+ Label for use in s<xx> operation.
4135 $Le[0-9]+ End blocks for MIPS debug support
4136 $Lp\..+ Half-pic labels. */
4138 /* This is how to output the definition of a user-level label named NAME,
4139 such as the label on a static function or variable NAME.
4141 If we are optimizing the gp, remember that this label has been put
4142 out, so we know not to emit an .extern for it in mips_asm_file_end.
4143 We use one of the common bits in the IDENTIFIER tree node for this,
4144 since those bits seem to be unused, and we don't have any method
4145 of getting the decl nodes from the name. */
4147 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4149 assemble_name (STREAM, NAME); \
4150 fputs (":\n", STREAM); \
4154 /* A C statement (sans semicolon) to output to the stdio stream
4155 STREAM any text necessary for declaring the name NAME of an
4156 initialized variable which is being defined. This macro must
4157 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4158 The argument DECL is the `VAR_DECL' tree node representing the
4161 If this macro is not defined, then the variable name is defined
4162 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4164 #undef ASM_DECLARE_OBJECT_NAME
4165 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4168 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4169 HALF_PIC_DECLARE (NAME); \
4174 /* This is how to output a command to make the user-level label named NAME
4175 defined for reference from other files. */
4177 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4179 fputs ("\t.globl\t", STREAM); \
4180 assemble_name (STREAM, NAME); \
4181 fputs ("\n", STREAM); \
4184 /* This says how to define a global common symbol. */
4186 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4188 /* If the target wants uninitialized const declarations in \
4189 .rdata then don't put them in .comm */ \
4190 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4191 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4192 && (DECL_INITIAL (DECL) == 0 \
4193 || DECL_INITIAL (DECL) == error_mark_node)) \
4195 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4196 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4198 READONLY_DATA_SECTION (); \
4199 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4200 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4204 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4209 /* This says how to define a local common symbol (ie, not visible to
4212 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4213 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4216 /* This says how to output an external. It would be possible not to
4217 output anything and let undefined symbol become external. However
4218 the assembler uses length information on externals to allocate in
4219 data/sdata bss/sbss, thereby saving exec time. */
4221 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4222 mips_output_external(STREAM,DECL,NAME)
4224 /* This says what to print at the end of the assembly file */
4226 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4229 /* This is how to declare a function name. The actual work of
4230 emitting the label is moved to function_prologue, so that we can
4231 get the line number correctly emitted before the .ent directive,
4232 and after any .file directives.
4234 Also, switch files if we are optimizing the global pointer. */
4236 #undef ASM_DECLARE_FUNCTION_NAME
4237 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4239 extern FILE *asm_out_text_file; \
4240 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4242 STREAM = asm_out_text_file; \
4243 /* ??? text_section gets called too soon. If the previous \
4244 function is in a special section and we're not, we have \
4245 to switch back to the text section. We can't call \
4246 text_section again as gcc thinks we're already there. */ \
4247 /* ??? See varasm.c. There are other things that get output \
4248 too early, like alignment (before we've switched STREAM). */ \
4249 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4250 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4253 HALF_PIC_DECLARE (NAME); \
4256 /* This is how to output an internal numbered label where
4257 PREFIX is the class of label and NUM is the number within the class. */
4259 #undef ASM_OUTPUT_INTERNAL_LABEL
4260 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4261 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4263 /* This is how to store into the string LABEL
4264 the symbol_ref name of an internal numbered label where
4265 PREFIX is the class of label and NUM is the number within the class.
4266 This is suitable for output with `assemble_name'. */
4268 #undef ASM_GENERATE_INTERNAL_LABEL
4269 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4270 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4272 /* This is how to output an assembler line defining a `double' constant. */
4274 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4275 mips_output_double (STREAM, VALUE)
4278 /* This is how to output an assembler line defining a `float' constant. */
4280 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4281 mips_output_float (STREAM, VALUE)
4284 /* This is how to output an assembler line defining an `int' constant. */
4286 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4288 fprintf (STREAM, "\t.word\t"); \
4289 output_addr_const (STREAM, (VALUE)); \
4290 fprintf (STREAM, "\n"); \
4293 /* Likewise for 64 bit, `char' and `short' constants.
4295 FIXME: operand_subword can't handle some complex constant expressions
4296 that output_addr_const can (for example it does not call
4297 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4298 rely on that to avoid operand_subword for most of the cases where this
4299 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4300 or the same case with the type of 'i' changed to long long.
4304 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4306 if (TARGET_64BIT || TARGET_GAS) \
4308 fprintf (STREAM, "\t.dword\t"); \
4309 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4310 /* We can't use 'X' for negative numbers, because then we won't \
4311 get the right value for the upper 32 bits. */ \
4312 output_addr_const (STREAM, VALUE); \
4314 /* We must use 'X', because otherwise LONG_MIN will print as \
4315 a number that the Irix 6 assembler won't accept. */ \
4316 print_operand (STREAM, VALUE, 'X'); \
4317 fprintf (STREAM, "\n"); \
4321 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4322 UNITS_PER_WORD, 1); \
4323 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4324 UNITS_PER_WORD, 1); \
4328 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4330 fprintf (STREAM, "\t.half\t"); \
4331 output_addr_const (STREAM, (VALUE)); \
4332 fprintf (STREAM, "\n"); \
4335 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4337 fprintf (STREAM, "\t.byte\t"); \
4338 output_addr_const (STREAM, (VALUE)); \
4339 fprintf (STREAM, "\n"); \
4342 /* This is how to output an assembler line for a numeric constant byte. */
4344 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4345 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4347 /* This is how to output an element of a case-vector that is absolute. */
4349 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4350 fprintf (STREAM, "\t%s\t%sL%d\n", \
4351 Pmode == DImode ? ".dword" : ".word", \
4352 LOCAL_LABEL_PREFIX, \
4355 /* This is how to output an element of a case-vector that is relative.
4356 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4357 TARGET_EMBEDDED_PIC). */
4359 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4361 if (TARGET_MIPS16) \
4362 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4363 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4364 else if (TARGET_EMBEDDED_PIC) \
4365 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4366 Pmode == DImode ? ".dword" : ".word", \
4367 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4368 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4369 fprintf (STREAM, "\t%s\t%sL%d\n", \
4370 Pmode == DImode ? ".gpdword" : ".gpword", \
4371 LOCAL_LABEL_PREFIX, VALUE); \
4373 fprintf (STREAM, "\t%s\t%sL%d\n", \
4374 Pmode == DImode ? ".dword" : ".word", \
4375 LOCAL_LABEL_PREFIX, VALUE); \
4378 /* When generating embedded PIC or mips16 code we want to put the jump
4379 table in the .text section. In all other cases, we want to put the
4380 jump table in the .rdata section. Unfortunately, we can't use
4381 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4382 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4383 section if appropriate. */
4384 #undef ASM_OUTPUT_CASE_LABEL
4385 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4387 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4388 function_section (current_function_decl); \
4389 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4392 /* This is how to output an assembler line
4393 that says to advance the location counter
4394 to a multiple of 2**LOG bytes. */
4396 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4397 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4399 /* This is how to output an assembler line to advance the location
4400 counter by SIZE bytes. */
4402 #undef ASM_OUTPUT_SKIP
4403 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4404 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4406 /* This is how to output a string. */
4407 #undef ASM_OUTPUT_ASCII
4408 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4409 mips_output_ascii (STREAM, STRING, LEN)
4411 /* Handle certain cpp directives used in header files on sysV. */
4412 #define SCCS_DIRECTIVE
4414 /* Output #ident as a in the read-only data section. */
4415 #undef ASM_OUTPUT_IDENT
4416 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4418 const char *p = STRING; \
4419 int size = strlen (p) + 1; \
4421 assemble_string (p, size); \
4424 /* Default to -G 8 */
4425 #ifndef MIPS_DEFAULT_GVALUE
4426 #define MIPS_DEFAULT_GVALUE 8
4429 /* Define the strings to put out for each section in the object file. */
4430 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4431 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4432 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4433 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4434 #undef READONLY_DATA_SECTION
4435 #define READONLY_DATA_SECTION rdata_section
4436 #define SMALL_DATA_SECTION sdata_section
4438 /* What other sections we support other than the normal .data/.text. */
4440 #undef EXTRA_SECTIONS
4441 #define EXTRA_SECTIONS in_sdata, in_rdata
4443 /* Define the additional functions to select our additional sections. */
4445 /* on the MIPS it is not a good idea to put constants in the text
4446 section, since this defeats the sdata/data mechanism. This is
4447 especially true when -O is used. In this case an effort is made to
4448 address with faster (gp) register relative addressing, which can
4449 only get at sdata and sbss items (there is no stext !!) However,
4450 if the constant is too large for sdata, and it's readonly, it
4451 will go into the .rdata section. */
4453 #undef EXTRA_SECTION_FUNCTIONS
4454 #define EXTRA_SECTION_FUNCTIONS \
4458 if (in_section != in_sdata) \
4460 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4461 in_section = in_sdata; \
4468 if (in_section != in_rdata) \
4470 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4471 in_section = in_rdata; \
4475 /* Given a decl node or constant node, choose the section to output it in
4476 and select that section. */
4478 #undef SELECT_RTX_SECTION
4479 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4481 #undef SELECT_SECTION
4482 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4485 /* Store in OUTPUT a string (made with alloca) containing
4486 an assembler-name for a local static variable named NAME.
4487 LABELNO is an integer which is different for each call. */
4489 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4490 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4491 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4493 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4496 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4497 TARGET_64BIT ? "dsubu" : "subu", \
4498 reg_names[STACK_POINTER_REGNUM], \
4499 reg_names[STACK_POINTER_REGNUM], \
4500 TARGET_64BIT ? "sd" : "sw", \
4502 reg_names[STACK_POINTER_REGNUM]); \
4506 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4509 if (! set_noreorder) \
4510 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4512 dslots_load_total++; \
4513 dslots_load_filled++; \
4514 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4515 TARGET_64BIT ? "ld" : "lw", \
4517 reg_names[STACK_POINTER_REGNUM], \
4518 TARGET_64BIT ? "daddu" : "addu", \
4519 reg_names[STACK_POINTER_REGNUM], \
4520 reg_names[STACK_POINTER_REGNUM]); \
4522 if (! set_noreorder) \
4523 fprintf (STREAM, "\t.set\treorder\n"); \
4527 /* How to start an assembler comment.
4528 The leading space is important (the mips native assembler requires it). */
4529 #ifndef ASM_COMMENT_START
4530 #define ASM_COMMENT_START " #"
4534 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4535 and mips-tdump.c to print them out.
4537 These must match the corresponding definitions in gdb/mipsread.c.
4538 Unfortunately, gcc and gdb do not currently share any directories. */
4540 #define CODE_MASK 0x8F300
4541 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4542 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4543 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4546 /* Default definitions for size_t and ptrdiff_t. */
4549 #define NO_BUILTIN_SIZE_TYPE
4550 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4553 #ifndef PTRDIFF_TYPE
4554 #define NO_BUILTIN_PTRDIFF_TYPE
4555 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4558 /* See mips_expand_prologue's use of loadgp for when this should be
4561 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4562 && mips_abi != ABI_32 \
4563 && mips_abi != ABI_O64)
4565 /* In mips16 mode, we need to look through the function to check for
4566 PC relative loads that are out of range. */
4567 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4569 /* We need to use a special set of functions to handle hard floating
4570 point code in mips16 mode. */
4572 #ifndef INIT_SUBTARGET_OPTABS
4573 #define INIT_SUBTARGET_OPTABS
4576 #define INIT_TARGET_OPTABS \
4579 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4580 INIT_SUBTARGET_OPTABS; \
4583 add_optab->handlers[(int) SFmode].libfunc = \
4584 init_one_libfunc ("__mips16_addsf3"); \
4585 sub_optab->handlers[(int) SFmode].libfunc = \
4586 init_one_libfunc ("__mips16_subsf3"); \
4587 smul_optab->handlers[(int) SFmode].libfunc = \
4588 init_one_libfunc ("__mips16_mulsf3"); \
4589 flodiv_optab->handlers[(int) SFmode].libfunc = \
4590 init_one_libfunc ("__mips16_divsf3"); \
4592 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4593 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4594 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4595 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4596 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4597 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4599 floatsisf_libfunc = \
4600 init_one_libfunc ("__mips16_floatsisf"); \
4602 init_one_libfunc ("__mips16_fixsfsi"); \
4604 if (TARGET_DOUBLE_FLOAT) \
4606 add_optab->handlers[(int) DFmode].libfunc = \
4607 init_one_libfunc ("__mips16_adddf3"); \
4608 sub_optab->handlers[(int) DFmode].libfunc = \
4609 init_one_libfunc ("__mips16_subdf3"); \
4610 smul_optab->handlers[(int) DFmode].libfunc = \
4611 init_one_libfunc ("__mips16_muldf3"); \
4612 flodiv_optab->handlers[(int) DFmode].libfunc = \
4613 init_one_libfunc ("__mips16_divdf3"); \
4615 extendsfdf2_libfunc = \
4616 init_one_libfunc ("__mips16_extendsfdf2"); \
4617 truncdfsf2_libfunc = \
4618 init_one_libfunc ("__mips16_truncdfsf2"); \
4621 init_one_libfunc ("__mips16_eqdf2"); \
4623 init_one_libfunc ("__mips16_nedf2"); \
4625 init_one_libfunc ("__mips16_gtdf2"); \
4627 init_one_libfunc ("__mips16_gedf2"); \
4629 init_one_libfunc ("__mips16_ltdf2"); \
4631 init_one_libfunc ("__mips16_ledf2"); \
4633 floatsidf_libfunc = \
4634 init_one_libfunc ("__mips16_floatsidf"); \
4636 init_one_libfunc ("__mips16_fixdfsi"); \
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