1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
27 #include "config/vxworks-dummy.h"
29 /* MIPS external variables defined in mips.c. */
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
73 /* Costs of various operations on the different architectures. */
75 struct mips_rtx_cost_data
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
100 /* Information about one recognized processor. Defined here for the
101 benefit of TARGET_CPU_CPP_BUILTINS. */
102 struct mips_cpu_info {
103 /* The 'canonical' name of the processor as far as GCC is concerned.
104 It's typically a manufacturer's prefix followed by a numerical
105 designation. It should be lowercase. */
108 /* The internal processor number that most closely matches this
109 entry. Several processors can have the same value, if there's no
110 difference between them from GCC's point of view. */
111 enum processor_type cpu;
113 /* The ISA level that the processor implements. */
117 /* Enumerates the setting of the -mcode-readable option. */
118 enum mips_code_readable_setting {
124 #ifndef USED_FOR_TARGET
125 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
126 extern const char *current_function_file; /* filename current function is in */
127 extern int num_source_filenames; /* current .file # */
128 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[];
136 extern int mips_dwarf_regno[];
137 extern bool mips_split_p[];
138 extern GTY(()) rtx cmp_operands[2];
139 extern enum processor_type mips_arch; /* which cpu to codegen for */
140 extern enum processor_type mips_tune; /* which cpu to schedule for */
141 extern int mips_isa; /* architectural level */
142 extern int mips_abi; /* which ABI to use */
143 extern const struct mips_cpu_info mips_cpu_info_table[];
144 extern const struct mips_cpu_info *mips_arch_info;
145 extern const struct mips_cpu_info *mips_tune_info;
146 extern const struct mips_rtx_cost_data *mips_cost;
147 extern enum mips_code_readable_setting mips_code_readable;
150 /* Macros to silence warnings about numbers being signed in traditional
151 C and unsigned in ISO C when compiled on 32-bit hosts. */
153 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
154 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
155 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
158 /* Run-time compilation parameters selecting different hardware subsets. */
160 /* True if we are generating position-independent VxWorks RTP code. */
161 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
163 /* True if the call patterns should be split into a jalr followed by
164 an instruction to restore $gp. It is only safe to split the load
165 from the call when every use of $gp is explicit. */
167 #define TARGET_SPLIT_CALLS \
168 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
170 /* True if we're generating a form of -mabicalls in which we can use
171 operators like %hi and %lo to refer to locally-binding symbols.
172 We can only do this for -mno-shared, and only then if we can use
173 relocation operations instead of assembly macros. It isn't really
174 worth using absolute sequences for 64-bit symbols because GOT
175 accesses are so much shorter. */
177 #define TARGET_ABSOLUTE_ABICALLS \
180 && TARGET_EXPLICIT_RELOCS \
181 && !ABI_HAS_64BIT_SYMBOLS)
183 /* True if we can optimize sibling calls. For simplicity, we only
184 handle cases in which call_insn_operand will reject invalid
185 sibcall addresses. There are two cases in which this isn't true:
187 - TARGET_MIPS16. call_insn_operand accepts constant addresses
188 but there is no direct jump instruction. It isn't worth
189 using sibling calls in this case anyway; they would usually
190 be longer than normal calls.
192 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
193 accepts global constants, but all sibcalls must be indirect. */
194 #define TARGET_SIBCALLS \
195 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
197 /* True if we need to use a global offset table to access some symbols. */
198 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
200 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
201 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
203 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
204 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
206 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
207 This is true for both the PIC and non-PIC VxWorks RTP modes. */
208 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
210 /* True if .gpword or .gpdword should be used for switch tables.
212 Although GAS does understand .gpdword, the SGI linker mishandles
213 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
214 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
215 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
217 /* Generate mips16 code */
218 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
219 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
220 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
221 /* Generate mips16e register save/restore sequences. */
222 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
224 /* True if we're generating a form of MIPS16 code in which general
225 text loads are allowed. */
226 #define TARGET_MIPS16_TEXT_LOADS \
227 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
229 /* True if we're generating a form of MIPS16 code in which PC-relative
230 loads are allowed. */
231 #define TARGET_MIPS16_PCREL_LOADS \
232 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
234 /* Generic ISA defines. */
235 #define ISA_MIPS1 (mips_isa == 1)
236 #define ISA_MIPS2 (mips_isa == 2)
237 #define ISA_MIPS3 (mips_isa == 3)
238 #define ISA_MIPS4 (mips_isa == 4)
239 #define ISA_MIPS32 (mips_isa == 32)
240 #define ISA_MIPS32R2 (mips_isa == 33)
241 #define ISA_MIPS64 (mips_isa == 64)
243 /* Architecture target defines. */
244 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
245 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
246 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
247 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
248 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
249 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
250 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
251 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
252 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
253 || mips_arch == PROCESSOR_SB1A)
254 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
256 /* Scheduling target defines. */
257 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
258 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
259 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
260 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
261 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
262 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
263 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
264 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
265 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
266 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
267 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
268 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
269 || mips_tune == PROCESSOR_SB1A)
270 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
271 || mips_tune == PROCESSOR_24KF2_1 \
272 || mips_tune == PROCESSOR_24KF1_1)
273 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
274 || mips_tune == PROCESSOR_74KF2_1 \
275 || mips_tune == PROCESSOR_74KF1_1 \
276 || mips_tune == PROCESSOR_74KF3_2)
277 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
279 /* True if the pre-reload scheduler should try to create chains of
280 multiply-add or multiply-subtract instructions. For example,
288 t1 will have a higher priority than t2 and t3 will have a higher
289 priority than t4. However, before reload, there is no dependence
290 between t1 and t3, and they can often have similar priorities.
291 The scheduler will then tend to prefer:
298 which stops us from making full use of macc/madd-style instructions.
299 This sort of situation occurs frequently in Fourier transforms and
302 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
303 queue so that chained multiply-add and multiply-subtract instructions
304 appear ahead of any other instruction that is likely to clobber lo.
305 In the example above, if t2 and t3 become ready at the same time,
306 the code ensures that t2 is scheduled first.
308 Multiply-accumulate instructions are a bigger win for some targets
309 than others, so this macro is defined on an opt-in basis. */
310 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
315 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
316 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
318 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
319 directly accessible, while the command-line options select
320 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
322 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
323 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
325 /* IRIX specific stuff. */
326 #define TARGET_IRIX 0
327 #define TARGET_IRIX6 0
329 /* Define preprocessor macros for the -march and -mtune options.
330 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
331 processor. If INFO's canonical name is "foo", define PREFIX to
332 be "foo", and define an additional macro PREFIX_FOO. */
333 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
338 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
339 for (p = macro; *p != 0; p++) \
342 builtin_define (macro); \
343 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
348 /* Target CPU builtins. */
349 #define TARGET_CPU_CPP_BUILTINS() \
352 /* Everyone but IRIX defines this to mips. */ \
354 builtin_assert ("machine=mips"); \
356 builtin_assert ("cpu=mips"); \
357 builtin_define ("__mips__"); \
358 builtin_define ("_mips"); \
360 /* We do this here because __mips is defined below \
361 and so we can't use builtin_define_std. */ \
363 builtin_define ("mips"); \
366 builtin_define ("__mips64"); \
370 /* Treat _R3000 and _R4000 like register-size \
371 defines, which is how they've historically \
375 builtin_define_std ("R4000"); \
376 builtin_define ("_R4000"); \
380 builtin_define_std ("R3000"); \
381 builtin_define ("_R3000"); \
384 if (TARGET_FLOAT64) \
385 builtin_define ("__mips_fpr=64"); \
387 builtin_define ("__mips_fpr=32"); \
390 builtin_define ("__mips16"); \
393 builtin_define ("__mips3d"); \
395 if (TARGET_SMARTMIPS) \
396 builtin_define ("__mips_smartmips"); \
400 builtin_define ("__mips_dsp"); \
403 builtin_define ("__mips_dspr2"); \
404 builtin_define ("__mips_dsp_rev=2"); \
407 builtin_define ("__mips_dsp_rev=1"); \
410 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
411 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
415 builtin_define ("__mips=1"); \
416 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
418 else if (ISA_MIPS2) \
420 builtin_define ("__mips=2"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
423 else if (ISA_MIPS3) \
425 builtin_define ("__mips=3"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
428 else if (ISA_MIPS4) \
430 builtin_define ("__mips=4"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
433 else if (ISA_MIPS32) \
435 builtin_define ("__mips=32"); \
436 builtin_define ("__mips_isa_rev=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
439 else if (ISA_MIPS32R2) \
441 builtin_define ("__mips=32"); \
442 builtin_define ("__mips_isa_rev=2"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
445 else if (ISA_MIPS64) \
447 builtin_define ("__mips=64"); \
448 builtin_define ("__mips_isa_rev=1"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 builtin_define ("_ABIO32=1"); \
456 builtin_define ("_MIPS_SIM=_ABIO32"); \
460 builtin_define ("_ABIN32=2"); \
461 builtin_define ("_MIPS_SIM=_ABIN32"); \
465 builtin_define ("_ABI64=3"); \
466 builtin_define ("_MIPS_SIM=_ABI64"); \
470 builtin_define ("_ABIO64=4"); \
471 builtin_define ("_MIPS_SIM=_ABIO64"); \
475 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
476 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
477 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
478 builtin_define_with_int_value ("_MIPS_FPSET", \
479 32 / MAX_FPRS_PER_FMT); \
481 /* These defines reflect the ABI in use, not whether the \
482 FPU is directly accessible. */ \
483 if (TARGET_HARD_FLOAT_ABI) \
484 builtin_define ("__mips_hard_float"); \
486 builtin_define ("__mips_soft_float"); \
488 if (TARGET_SINGLE_FLOAT) \
489 builtin_define ("__mips_single_float"); \
491 if (TARGET_PAIRED_SINGLE_FLOAT) \
492 builtin_define ("__mips_paired_single_float"); \
494 if (TARGET_BIG_ENDIAN) \
496 builtin_define_std ("MIPSEB"); \
497 builtin_define ("_MIPSEB"); \
501 builtin_define_std ("MIPSEL"); \
502 builtin_define ("_MIPSEL"); \
505 /* Macros dependent on the C dialect. */ \
506 if (preprocessing_asm_p ()) \
508 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
509 builtin_define ("_LANGUAGE_ASSEMBLY"); \
511 else if (c_dialect_cxx ()) \
513 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
514 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
515 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
519 builtin_define_std ("LANGUAGE_C"); \
520 builtin_define ("_LANGUAGE_C"); \
522 if (c_dialect_objc ()) \
524 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
525 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
526 /* Bizarre, but needed at least for Irix. */ \
527 builtin_define_std ("LANGUAGE_C"); \
528 builtin_define ("_LANGUAGE_C"); \
531 if (mips_abi == ABI_EABI) \
532 builtin_define ("__mips_eabi"); \
536 /* Default target_flags if no switches are specified */
538 #ifndef TARGET_DEFAULT
539 #define TARGET_DEFAULT 0
542 #ifndef TARGET_CPU_DEFAULT
543 #define TARGET_CPU_DEFAULT 0
546 #ifndef TARGET_ENDIAN_DEFAULT
547 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
550 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
551 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
554 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
555 #ifndef MIPS_ISA_DEFAULT
556 #ifndef MIPS_CPU_STRING_DEFAULT
557 #define MIPS_CPU_STRING_DEFAULT "from-abi"
563 /* Make this compile time constant for libgcc2 */
565 #define TARGET_64BIT 1
567 #define TARGET_64BIT 0
569 #endif /* IN_LIBGCC2 */
571 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
573 #ifndef MULTILIB_ENDIAN_DEFAULT
574 #if TARGET_ENDIAN_DEFAULT == 0
575 #define MULTILIB_ENDIAN_DEFAULT "EL"
577 #define MULTILIB_ENDIAN_DEFAULT "EB"
581 #ifndef MULTILIB_ISA_DEFAULT
582 # if MIPS_ISA_DEFAULT == 1
583 # define MULTILIB_ISA_DEFAULT "mips1"
585 # if MIPS_ISA_DEFAULT == 2
586 # define MULTILIB_ISA_DEFAULT "mips2"
588 # if MIPS_ISA_DEFAULT == 3
589 # define MULTILIB_ISA_DEFAULT "mips3"
591 # if MIPS_ISA_DEFAULT == 4
592 # define MULTILIB_ISA_DEFAULT "mips4"
594 # if MIPS_ISA_DEFAULT == 32
595 # define MULTILIB_ISA_DEFAULT "mips32"
597 # if MIPS_ISA_DEFAULT == 33
598 # define MULTILIB_ISA_DEFAULT "mips32r2"
600 # if MIPS_ISA_DEFAULT == 64
601 # define MULTILIB_ISA_DEFAULT "mips64"
603 # define MULTILIB_ISA_DEFAULT "mips1"
613 #ifndef MULTILIB_DEFAULTS
614 #define MULTILIB_DEFAULTS \
615 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
618 /* We must pass -EL to the linker by default for little endian embedded
619 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
620 linker will default to using big-endian output files. The OUTPUT_FORMAT
621 line must be in the linker script, otherwise -EB/-EL will not work. */
624 #if TARGET_ENDIAN_DEFAULT == 0
625 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
627 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
631 /* A spec condition that matches all non-mips16 -mips arguments. */
633 #define MIPS_ISA_LEVEL_OPTION_SPEC \
634 "mips1|mips2|mips3|mips4|mips32*|mips64*"
636 /* A spec condition that matches all non-mips16 architecture arguments. */
638 #define MIPS_ARCH_OPTION_SPEC \
639 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
641 /* A spec that infers a -mips argument from an -march argument,
642 or injects the default if no architecture is specified. */
644 #define MIPS_ISA_LEVEL_SPEC \
645 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
646 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
647 %{march=mips2|march=r6000:-mips2} \
648 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
649 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
650 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
651 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
652 |march=34k*|march=74k*: -mips32r2} \
653 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
654 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
656 /* A spec condition that matches 32-bit options. It only works if
657 MIPS_ISA_LEVEL_SPEC has been applied. */
659 #define MIPS_32BIT_OPTION_SPEC \
660 "mips1|mips2|mips32*|mgp32"
662 /* Support for a compile-time default CPU, et cetera. The rules are:
663 --with-arch is ignored if -march is specified or a -mips is specified
664 (other than -mips16).
665 --with-tune is ignored if -mtune is specified.
666 --with-abi is ignored if -mabi is specified.
667 --with-float is ignored if -mhard-float or -msoft-float are
669 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
671 #define OPTION_DEFAULT_SPECS \
672 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
673 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
674 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
675 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
676 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
679 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
680 && ISA_HAS_COND_TRAP)
682 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
686 /* True if the ABI can only work with 64-bit integer registers. We
687 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
688 otherwise floating-point registers must also be 64-bit. */
689 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
691 /* Likewise for 32-bit regs. */
692 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
694 /* True if symbols are 64 bits wide. At present, n64 is the only
695 ABI for which this is true. */
696 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
698 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
699 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
703 /* ISA has branch likely instructions (e.g. mips2). */
704 /* Disable branchlikely for tx39 until compare rewrite. They haven't
705 been generated up to this point. */
706 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
708 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
709 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
720 /* ISA has the conditional move instructions introduced in mips4. */
721 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
725 && !TARGET_MIPS5500 \
728 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
729 branch on CC, and move (both FP and non-FP) on CC. */
730 #define ISA_HAS_8CC (ISA_MIPS4 \
735 /* This is a catch all for other mips4 instructions: indexed load, the
736 FP madd and msub instructions, and the FP recip and recip sqrt
738 #define ISA_HAS_FP4 ((ISA_MIPS4 \
739 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
743 /* ISA has conditional trap instructions. */
744 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
747 /* ISA has integer multiply-accumulate instructions, madd and msub. */
748 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
753 /* Integer multiply-accumulate instructions should be generated. */
754 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
756 /* ISA has floating-point nmadd and nmsub instructions. */
757 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
759 && (!TARGET_MIPS5400 || TARGET_MAD) \
762 /* ISA has count leading zeroes/ones instruction (not implemented). */
763 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
768 /* ISA has three operand multiply instructions that put
769 the high part in an accumulator: mulhi or mulhiu. */
770 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
775 /* ISA has three operand multiply instructions that
776 negates the result and puts the result in an accumulator. */
777 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
782 /* ISA has three operand multiply instructions that subtracts the
783 result from a 4th operand and puts the result in an accumulator. */
784 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
789 /* ISA has three operand multiply instructions that the result
790 from a 4th operand and puts the result in an accumulator. */
791 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
798 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
799 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
800 || TARGET_MIPS4130) \
803 /* ISA has the "ror" (rotate right) instructions. */
804 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
808 || TARGET_SMARTMIPS) \
811 /* ISA has data prefetch instructions. This controls use of 'pref'. */
812 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
818 /* ISA has data indexed prefetch instructions. This controls use of
819 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
820 (prefx is a cop1x instruction, so can only be used if FP is
822 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
827 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
828 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
829 also requires TARGET_DOUBLE_FLOAT. */
830 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
832 /* ISA includes the MIPS32r2 seb and seh instructions. */
833 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
836 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
837 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
840 /* ISA has instructions for accessing top part of 64-bit fp regs. */
841 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
843 /* ISA has lwxs instruction (load w/scaled index address. */
844 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
846 /* True if the result of a load is not available to the next instruction.
847 A nop will then be needed between instructions like "lw $4,..."
848 and "addiu $4,$4,1". */
849 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
850 && !TARGET_MIPS3900 \
853 /* Likewise mtc1 and mfc1. */
854 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
856 /* Likewise floating-point comparisons. */
857 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
859 /* True if mflo and mfhi can be immediately followed by instructions
860 which write to the HI and LO registers.
862 According to MIPS specifications, MIPS ISAs I, II, and III need
863 (at least) two instructions between the reads of HI/LO and
864 instructions which write them, and later ISAs do not. Contradicting
865 the MIPS specifications, some MIPS IV processor user manuals (e.g.
866 the UM for the NEC Vr5000) document needing the instructions between
867 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
868 MIPS64 and later ISAs to have the interlocks, plus any specific
869 earlier-ISA CPUs for which CPU documentation declares that the
870 instructions are really interlocked. */
871 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
876 /* ISA includes synci, jr.hb and jalr.hb. */
877 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
880 /* Add -G xx support. */
882 #undef SWITCH_TAKES_ARG
883 #define SWITCH_TAKES_ARG(CHAR) \
884 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
886 #define OVERRIDE_OPTIONS override_options ()
888 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
890 /* Show we can debug even without a frame pointer. */
891 #define CAN_DEBUG_WITHOUT_FP
893 /* Tell collect what flags to pass to nm. */
895 #define NM_FLAGS "-Bn"
899 #ifndef MIPS_ABI_DEFAULT
900 #define MIPS_ABI_DEFAULT ABI_32
903 /* Use the most portable ABI flag for the ASM specs. */
905 #if MIPS_ABI_DEFAULT == ABI_32
906 #define MULTILIB_ABI_DEFAULT "mabi=32"
909 #if MIPS_ABI_DEFAULT == ABI_O64
910 #define MULTILIB_ABI_DEFAULT "mabi=o64"
913 #if MIPS_ABI_DEFAULT == ABI_N32
914 #define MULTILIB_ABI_DEFAULT "mabi=n32"
917 #if MIPS_ABI_DEFAULT == ABI_64
918 #define MULTILIB_ABI_DEFAULT "mabi=64"
921 #if MIPS_ABI_DEFAULT == ABI_EABI
922 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
925 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
926 to the assembler. It may be overridden by subtargets. */
927 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
928 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
930 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
933 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
934 the assembler. It may be overridden by subtargets.
936 Beginning with gas 2.13, -mdebug must be passed to correctly handle
937 COFF debugging info. */
939 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
940 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
941 %{g} %{g0} %{g1} %{g2} %{g3} \
942 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
943 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
944 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
945 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
946 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
949 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
950 overridden by subtargets. */
952 #ifndef SUBTARGET_ASM_SPEC
953 #define SUBTARGET_ASM_SPEC ""
958 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
959 %{mips32} %{mips32r2} %{mips64} \
960 %{mips16} %{mno-mips16:-no-mips16} \
961 %{mips3d} %{mno-mips3d:-no-mips3d} \
962 %{mdmx} %{mno-mdmx:-no-mdmx} \
964 %{mdspr2} %{mno-dspr2} \
965 %{msmartmips} %{mno-smartmips} \
967 %{mfix-vr4120} %{mfix-vr4130} \
968 %(subtarget_asm_optimizing_spec) \
969 %(subtarget_asm_debugging_spec) \
970 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
971 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
973 %{mshared} %{mno-shared} \
974 %{msym32} %{mno-sym32} \
976 %(subtarget_asm_spec)"
978 /* Extra switches sometimes passed to the linker. */
979 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
980 will interpret it as a -b option. */
985 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
986 %{bestGnum} %{shared} %{non_shared}"
987 #endif /* LINK_SPEC defined */
990 /* Specs for the compiler proper */
992 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
993 overridden by subtargets. */
994 #ifndef SUBTARGET_CC1_SPEC
995 #define SUBTARGET_CC1_SPEC ""
998 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1002 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1003 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1005 %(subtarget_cc1_spec)"
1007 /* Preprocessor specs. */
1009 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1010 overridden by subtargets. */
1011 #ifndef SUBTARGET_CPP_SPEC
1012 #define SUBTARGET_CPP_SPEC ""
1015 #define CPP_SPEC "%(subtarget_cpp_spec)"
1017 /* This macro defines names of additional specifications to put in the specs
1018 that can be used in various specifications like CC1_SPEC. Its definition
1019 is an initializer with a subgrouping for each command option.
1021 Each subgrouping contains a string constant, that defines the
1022 specification name, and a string constant that used by the GCC driver
1025 Do not define this macro if it does not need to do anything. */
1027 #define EXTRA_SPECS \
1028 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1029 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1030 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1031 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1032 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1033 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1034 { "endian_spec", ENDIAN_SPEC }, \
1035 SUBTARGET_EXTRA_SPECS
1037 #ifndef SUBTARGET_EXTRA_SPECS
1038 #define SUBTARGET_EXTRA_SPECS
1041 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1042 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1043 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1045 #ifndef PREFERRED_DEBUGGING_TYPE
1046 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1049 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1051 /* By default, turn on GDB extensions. */
1052 #define DEFAULT_GDB_EXTENSIONS 1
1054 /* Local compiler-generated symbols must have a prefix that the assembler
1055 understands. By default, this is $, although some targets (e.g.,
1056 NetBSD-ELF) need to override this. */
1058 #ifndef LOCAL_LABEL_PREFIX
1059 #define LOCAL_LABEL_PREFIX "$"
1062 /* By default on the mips, external symbols do not have an underscore
1063 prepended, but some targets (e.g., NetBSD) require this. */
1065 #ifndef USER_LABEL_PREFIX
1066 #define USER_LABEL_PREFIX ""
1069 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1070 since the length can run past this up to a continuation point. */
1071 #undef DBX_CONTIN_LENGTH
1072 #define DBX_CONTIN_LENGTH 1500
1074 /* How to renumber registers for dbx and gdb. */
1075 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1077 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1078 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1080 /* The DWARF 2 CFA column which tracks the return address. */
1081 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1083 /* Before the prologue, RA lives in r31. */
1084 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1086 /* Describe how we implement __builtin_eh_return. */
1087 #define EH_RETURN_DATA_REGNO(N) \
1088 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1090 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1092 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1093 The default for this in 64-bit mode is 8, which causes problems with
1094 SFmode register saves. */
1095 #define DWARF_CIE_DATA_ALIGNMENT -4
1097 /* Correct the offset of automatic variables and arguments. Note that
1098 the MIPS debug format wants all automatic variables and arguments
1099 to be in terms of the virtual frame pointer (stack pointer before
1100 any adjustment in the function), while the MIPS 3.0 linker wants
1101 the frame pointer to be the stack pointer after the initial
1104 #define DEBUGGER_AUTO_OFFSET(X) \
1105 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1106 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1107 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1109 /* Target machine storage layout */
1111 #define BITS_BIG_ENDIAN 0
1112 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1113 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1115 /* Define this to set the endianness to use in libgcc2.c, which can
1116 not depend on target_flags. */
1117 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1118 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1120 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1123 #define MAX_BITS_PER_WORD 64
1125 /* Width of a word, in units (bytes). */
1126 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1128 #define MIN_UNITS_PER_WORD 4
1131 /* For MIPS, width of a floating point register. */
1132 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1134 /* The number of consecutive floating-point registers needed to store the
1135 largest format supported by the FPU. */
1136 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1138 /* The number of consecutive floating-point registers needed to store the
1139 smallest format supported by the FPU. */
1140 #define MIN_FPRS_PER_FMT \
1141 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1143 /* The largest size of value that can be held in floating-point
1144 registers and moved with a single instruction. */
1145 #define UNITS_PER_HWFPVALUE \
1146 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1148 /* The largest size of value that can be held in floating-point
1150 #define UNITS_PER_FPVALUE \
1151 (TARGET_SOFT_FLOAT_ABI ? 0 \
1152 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1153 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1155 /* The number of bytes in a double. */
1156 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1158 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1160 /* Set the sizes of the core types. */
1161 #define SHORT_TYPE_SIZE 16
1162 #define INT_TYPE_SIZE 32
1163 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1164 #define LONG_LONG_TYPE_SIZE 64
1166 #define FLOAT_TYPE_SIZE 32
1167 #define DOUBLE_TYPE_SIZE 64
1168 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1170 /* long double is not a fixed mode, but the idea is that, if we
1171 support long double, we also want a 128-bit integer type. */
1172 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1175 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1176 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1177 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1179 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1183 /* Width in bits of a pointer. */
1184 #ifndef POINTER_SIZE
1185 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1188 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1189 #define PARM_BOUNDARY BITS_PER_WORD
1191 /* Allocation boundary (in *bits*) for the code of a function. */
1192 #define FUNCTION_BOUNDARY 32
1194 /* Alignment of field after `int : 0' in a structure. */
1195 #define EMPTY_FIELD_BOUNDARY 32
1197 /* Every structure's size must be a multiple of this. */
1198 /* 8 is observed right on a DECstation and on riscos 4.02. */
1199 #define STRUCTURE_SIZE_BOUNDARY 8
1201 /* There is no point aligning anything to a rounder boundary than this. */
1202 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1204 /* All accesses must be aligned. */
1205 #define STRICT_ALIGNMENT 1
1207 /* Define this if you wish to imitate the way many other C compilers
1208 handle alignment of bitfields and the structures that contain
1211 The behavior is that the type written for a bit-field (`int',
1212 `short', or other integer type) imposes an alignment for the
1213 entire structure, as if the structure really did contain an
1214 ordinary field of that type. In addition, the bit-field is placed
1215 within the structure so that it would fit within such a field,
1216 not crossing a boundary for it.
1218 Thus, on most machines, a bit-field whose type is written as `int'
1219 would not cross a four-byte boundary, and would force four-byte
1220 alignment for the whole structure. (The alignment used may not
1221 be four bytes; it is controlled by the other alignment
1224 If the macro is defined, its definition should be a C expression;
1225 a nonzero value for the expression enables this behavior. */
1227 #define PCC_BITFIELD_TYPE_MATTERS 1
1229 /* If defined, a C expression to compute the alignment given to a
1230 constant that is being placed in memory. CONSTANT is the constant
1231 and ALIGN is the alignment that the object would ordinarily have.
1232 The value of this macro is used instead of that alignment to align
1235 If this macro is not defined, then ALIGN is used.
1237 The typical use of this macro is to increase alignment for string
1238 constants to be word aligned so that `strcpy' calls that copy
1239 constants can be done inline. */
1241 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1242 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1243 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1245 /* If defined, a C expression to compute the alignment for a static
1246 variable. TYPE is the data type, and ALIGN is the alignment that
1247 the object would ordinarily have. The value of this macro is used
1248 instead of that alignment to align the object.
1250 If this macro is not defined, then ALIGN is used.
1252 One use of this macro is to increase alignment of medium-size
1253 data to make it all fit in fewer cache lines. Another is to
1254 cause character arrays to be word-aligned so that `strcpy' calls
1255 that copy constants to character arrays can be done inline. */
1257 #undef DATA_ALIGNMENT
1258 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1259 ((((ALIGN) < BITS_PER_WORD) \
1260 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1261 || TREE_CODE (TYPE) == UNION_TYPE \
1262 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1265 #define PAD_VARARGS_DOWN \
1266 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1268 /* Define if operations between registers always perform the operation
1269 on the full register even if a narrower mode is specified. */
1270 #define WORD_REGISTER_OPERATIONS
1272 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1273 moves. All other references are zero extended. */
1274 #define LOAD_EXTEND_OP(MODE) \
1275 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1276 ? SIGN_EXTEND : ZERO_EXTEND)
1278 /* Define this macro if it is advisable to hold scalars in registers
1279 in a wider mode than that declared by the program. In such cases,
1280 the value is constrained to be within the bounds of the declared
1281 type, but kept valid in the wider mode. The signedness of the
1282 extension may differ from that of the type. */
1284 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1285 if (GET_MODE_CLASS (MODE) == MODE_INT \
1286 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1288 if ((MODE) == SImode) \
1293 /* Define if loading short immediate values into registers sign extends. */
1294 #define SHORT_IMMEDIATES_SIGN_EXTEND
1296 /* The [d]clz instructions have the natural values at 0. */
1298 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1299 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1301 /* Standard register usage. */
1303 /* Number of hardware registers. We have:
1305 - 32 integer registers
1306 - 32 floating point registers
1307 - 8 condition code registers
1308 - 2 accumulator registers (hi and lo)
1309 - 32 registers each for coprocessors 0, 2 and 3
1311 - ARG_POINTER_REGNUM
1312 - FRAME_POINTER_REGNUM
1313 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1314 - 3 dummy entries that were used at various times in the past.
1315 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1316 - 6 DSP control registers */
1318 #define FIRST_PSEUDO_REGISTER 188
1320 /* By default, fix the kernel registers ($26 and $27), the global
1321 pointer ($28) and the stack pointer ($29). This can change
1322 depending on the command-line options.
1324 Regarding coprocessor registers: without evidence to the contrary,
1325 it's best to assume that each coprocessor register has a unique
1326 use. This can be overridden, in, e.g., override_options() or
1327 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1328 for a particular target. */
1330 #define FIXED_REGISTERS \
1332 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1333 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1334 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1336 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1337 /* COP0 registers */ \
1338 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1339 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1340 /* COP2 registers */ \
1341 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1342 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1343 /* COP3 registers */ \
1344 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1345 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1346 /* 6 DSP accumulator registers & 6 control registers */ \
1347 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1351 /* Set up this array for o32 by default.
1353 Note that we don't mark $31 as a call-clobbered register. The idea is
1354 that it's really the call instructions themselves which clobber $31.
1355 We don't care what the called function does with it afterwards.
1357 This approach makes it easier to implement sibcalls. Unlike normal
1358 calls, sibcalls don't clobber $31, so the register reaches the
1359 called function in tact. EPILOGUE_USES says that $31 is useful
1360 to the called function. */
1362 #define CALL_USED_REGISTERS \
1364 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1365 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1366 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1367 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1368 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1369 /* COP0 registers */ \
1370 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1371 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1372 /* COP2 registers */ \
1373 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1374 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1375 /* COP3 registers */ \
1376 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1377 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1378 /* 6 DSP accumulator registers & 6 control registers */ \
1379 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1383 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1385 #define CALL_REALLY_USED_REGISTERS \
1386 { /* General registers. */ \
1387 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1388 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1389 /* Floating-point registers. */ \
1390 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1391 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1393 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1394 /* COP0 registers */ \
1395 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1396 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1397 /* COP2 registers */ \
1398 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1399 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1400 /* COP3 registers */ \
1401 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1402 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1403 /* 6 DSP accumulator registers & 6 control registers */ \
1404 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1407 /* Internal macros to classify a register number as to whether it's a
1408 general purpose register, a floating point register, a
1409 multiply/divide register, or a status register. */
1411 #define GP_REG_FIRST 0
1412 #define GP_REG_LAST 31
1413 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1414 #define GP_DBX_FIRST 0
1416 #define FP_REG_FIRST 32
1417 #define FP_REG_LAST 63
1418 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1419 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1421 #define MD_REG_FIRST 64
1422 #define MD_REG_LAST 65
1423 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1424 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1426 /* The DWARF 2 CFA column which tracks the return address from a
1427 signal handler context. This means that to maintain backwards
1428 compatibility, no hard register can be assigned this column if it
1429 would need to be handled by the DWARF unwinder. */
1430 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1432 #define ST_REG_FIRST 67
1433 #define ST_REG_LAST 74
1434 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1437 /* FIXME: renumber. */
1438 #define COP0_REG_FIRST 80
1439 #define COP0_REG_LAST 111
1440 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1442 #define COP2_REG_FIRST 112
1443 #define COP2_REG_LAST 143
1444 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1446 #define COP3_REG_FIRST 144
1447 #define COP3_REG_LAST 175
1448 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1449 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1450 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1452 #define DSP_ACC_REG_FIRST 176
1453 #define DSP_ACC_REG_LAST 181
1454 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1456 #define AT_REGNUM (GP_REG_FIRST + 1)
1457 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1458 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1460 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1461 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1462 should be used instead. */
1463 #define FPSW_REGNUM ST_REG_FIRST
1465 #define GP_REG_P(REGNO) \
1466 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1467 #define M16_REG_P(REGNO) \
1468 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1469 #define FP_REG_P(REGNO) \
1470 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1471 #define MD_REG_P(REGNO) \
1472 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1473 #define ST_REG_P(REGNO) \
1474 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1475 #define COP0_REG_P(REGNO) \
1476 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1477 #define COP2_REG_P(REGNO) \
1478 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1479 #define COP3_REG_P(REGNO) \
1480 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1481 #define ALL_COP_REG_P(REGNO) \
1482 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1483 /* Test if REGNO is one of the 6 new DSP accumulators. */
1484 #define DSP_ACC_REG_P(REGNO) \
1485 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1486 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1487 #define ACC_REG_P(REGNO) \
1488 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1490 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1492 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1493 to initialize the mips16 gp pseudo register. */
1494 #define CONST_GP_P(X) \
1495 (GET_CODE (X) == CONST \
1496 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1497 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1499 /* Return coprocessor number from register number. */
1501 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1502 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1503 : COP3_REG_P (REGNO) ? '3' : '?')
1506 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1508 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1509 array built in override_options. Because machmodes.h is not yet
1510 included before this file is processed, the MODE bound can't be
1513 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1515 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1516 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1518 /* Value is 1 if it is a good idea to tie two pseudo registers
1519 when one has mode MODE1 and one has mode MODE2.
1520 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1521 for any hard reg, then this must be 0 for correct output. */
1522 #define MODES_TIEABLE_P(MODE1, MODE2) \
1523 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1524 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1525 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1526 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1528 /* Register to use for pushing function arguments. */
1529 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1531 /* These two registers don't really exist: they get eliminated to either
1532 the stack or hard frame pointer. */
1533 #define ARG_POINTER_REGNUM 77
1534 #define FRAME_POINTER_REGNUM 78
1536 /* $30 is not available on the mips16, so we use $17 as the frame
1538 #define HARD_FRAME_POINTER_REGNUM \
1539 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1541 /* Value should be nonzero if functions must have frame pointers.
1542 Zero means the frame pointer need not be set up (and parms
1543 may be accessed via the stack pointer) in functions that seem suitable.
1544 This is computed in `reload', in reload1.c. */
1545 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1547 /* Register in which static-chain is passed to a function. */
1548 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1550 /* Registers used as temporaries in prologue/epilogue code. If we're
1551 generating mips16 code, these registers must come from the core set
1552 of 8. The prologue register mustn't conflict with any incoming
1553 arguments, the static chain pointer, or the frame pointer. The
1554 epilogue temporary mustn't conflict with the return registers, the
1555 frame pointer, the EH stack adjustment, or the EH data registers. */
1557 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1558 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1560 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1561 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1563 /* Define this macro if it is as good or better to call a constant
1564 function address than to call an address kept in a register. */
1565 #define NO_FUNCTION_CSE 1
1567 /* The ABI-defined global pointer. Sometimes we use a different
1568 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1569 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1571 /* We normally use $28 as the global pointer. However, when generating
1572 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1573 register instead. They can then avoid saving and restoring $28
1574 and perhaps avoid using a frame at all.
1576 When a leaf function uses something other than $28, mips_expand_prologue
1577 will modify pic_offset_table_rtx in place. Take the register number
1578 from there after reload. */
1579 #define PIC_OFFSET_TABLE_REGNUM \
1580 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1582 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1584 /* Define the classes of registers for register constraints in the
1585 machine description. Also define ranges of constants.
1587 One of the classes must always be named ALL_REGS and include all hard regs.
1588 If there is more than one class, another class must be named NO_REGS
1589 and contain no registers.
1591 The name GENERAL_REGS must be the name of a class (or an alias for
1592 another name such as ALL_REGS). This is the class of registers
1593 that is allowed by "g" or "r" in a register constraint.
1594 Also, registers outside this class are allocated only when
1595 instructions express preferences for them.
1597 The classes must be numbered in nondecreasing order; that is,
1598 a larger-numbered class must never be contained completely
1599 in a smaller-numbered class.
1601 For any two classes, it is very desirable that there be another
1602 class that represents their union. */
1606 NO_REGS, /* no registers in set */
1607 M16_NA_REGS, /* mips16 regs not used to pass args */
1608 M16_REGS, /* mips16 directly accessible registers */
1609 T_REG, /* mips16 T register ($24) */
1610 M16_T_REGS, /* mips16 registers plus T register */
1611 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1612 V1_REG, /* Register $v1 ($3) used for TLS access. */
1613 LEA_REGS, /* Every GPR except $25 */
1614 GR_REGS, /* integer registers */
1615 FP_REGS, /* floating point registers */
1616 MD0_REG, /* first multiply/divide register */
1617 MD1_REG, /* second multiply/divide register */
1618 MD_REGS, /* multiply/divide registers (hi/lo) */
1619 COP0_REGS, /* generic coprocessor classes */
1622 HI_AND_GR_REGS, /* union classes */
1629 ALL_COP_AND_GR_REGS,
1630 ST_REGS, /* status registers (fp status) */
1631 DSP_ACC_REGS, /* DSP accumulator registers */
1632 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1633 ALL_REGS, /* all registers */
1634 LIM_REG_CLASSES /* max value + 1 */
1637 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1639 #define GENERAL_REGS GR_REGS
1641 /* An initializer containing the names of the register classes as C
1642 string constants. These names are used in writing some of the
1645 #define REG_CLASS_NAMES \
1652 "PIC_FN_ADDR_REG", \
1660 /* coprocessor registers */ \
1667 "COP0_AND_GR_REGS", \
1668 "COP2_AND_GR_REGS", \
1669 "COP3_AND_GR_REGS", \
1671 "ALL_COP_AND_GR_REGS", \
1678 /* An initializer containing the contents of the register classes,
1679 as integers which are bit masks. The Nth integer specifies the
1680 contents of class N. The way the integer MASK is interpreted is
1681 that register R is in the class if `MASK & (1 << R)' is 1.
1683 When the machine has more than 32 registers, an integer does not
1684 suffice. Then the integers are replaced by sub-initializers,
1685 braced groupings containing several integers. Each
1686 sub-initializer must be suitable as an initializer for the type
1687 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1689 #define REG_CLASS_CONTENTS \
1691 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1692 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1693 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1694 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1695 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1696 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1697 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1698 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1699 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1700 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1701 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1702 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1703 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1704 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1705 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1706 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1707 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1708 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1709 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1710 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1711 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1712 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1713 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1714 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1715 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1716 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1717 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1718 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1722 /* A C expression whose value is a register class containing hard
1723 register REGNO. In general there is more that one such class;
1724 choose a class which is "minimal", meaning that no smaller class
1725 also contains the register. */
1727 extern const enum reg_class mips_regno_to_class[];
1729 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1731 /* A macro whose definition is the name of the class to which a
1732 valid base register must belong. A base register is one used in
1733 an address which is the register value plus a displacement. */
1735 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1737 /* A macro whose definition is the name of the class to which a
1738 valid index register must belong. An index register is one used
1739 in an address where its value is either multiplied by a scale
1740 factor or added to another register (as well as added to a
1743 #define INDEX_REG_CLASS NO_REGS
1745 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1746 registers explicitly used in the rtl to be used as spill registers
1747 but prevents the compiler from extending the lifetime of these
1750 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1752 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1753 is the default value (allocate the registers in numeric order). We
1754 define it just so that we can override it for the mips16 target in
1755 ORDER_REGS_FOR_LOCAL_ALLOC. */
1757 #define REG_ALLOC_ORDER \
1758 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1759 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1760 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1761 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1762 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1763 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1764 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1765 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1766 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1767 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1768 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1769 176,177,178,179,180,181,182,183,184,185,186,187 \
1772 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1773 to be rearranged based on a particular function. On the mips16, we
1774 want to allocate $24 (T_REG) before other registers for
1775 instructions for which it is possible. */
1777 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1779 /* True if VALUE is an unsigned 6-bit number. */
1781 #define UIMM6_OPERAND(VALUE) \
1782 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1784 /* True if VALUE is a signed 10-bit number. */
1786 #define IMM10_OPERAND(VALUE) \
1787 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1789 /* True if VALUE is a signed 16-bit number. */
1791 #define SMALL_OPERAND(VALUE) \
1792 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1794 /* True if VALUE is an unsigned 16-bit number. */
1796 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1797 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1799 /* True if VALUE can be loaded into a register using LUI. */
1801 #define LUI_OPERAND(VALUE) \
1802 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1803 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1805 /* Return a value X with the low 16 bits clear, and such that
1806 VALUE - X is a signed 16-bit value. */
1808 #define CONST_HIGH_PART(VALUE) \
1809 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1811 #define CONST_LOW_PART(VALUE) \
1812 ((VALUE) - CONST_HIGH_PART (VALUE))
1814 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1815 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1816 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1818 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1819 mips_preferred_reload_class (X, CLASS)
1821 /* The HI and LO registers can only be reloaded via the general
1822 registers. Condition code registers can only be loaded to the
1823 general registers, and from the floating point registers. */
1825 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1826 mips_secondary_reload_class (CLASS, MODE, X, 1)
1827 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1828 mips_secondary_reload_class (CLASS, MODE, X, 0)
1830 /* Return the maximum number of consecutive registers
1831 needed to represent mode MODE in a register of class CLASS. */
1833 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1835 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1836 mips_cannot_change_mode_class (FROM, TO, CLASS)
1838 /* Stack layout; function entry, exit and calling. */
1840 #define STACK_GROWS_DOWNWARD
1842 /* The offset of the first local variable from the beginning of the frame.
1843 See compute_frame_size for details about the frame layout.
1845 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1846 we assume that we will need 16 bytes of argument space. This is because
1847 the value profiling code may emit calls to cmpdi2 in leaf functions.
1848 Without this hack, the local variables will start at sp+8 and the gp save
1849 area will be at sp+16, and thus they will overlap. compute_frame_size is
1850 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1851 will end up as 24 instead of 8. This won't be needed if profiling code is
1852 inserted before virtual register instantiation. */
1854 #define STARTING_FRAME_OFFSET \
1855 ((flag_profile_values && ! TARGET_64BIT \
1856 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1857 : current_function_outgoing_args_size) \
1858 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1860 #define RETURN_ADDR_RTX mips_return_addr
1862 /* Since the mips16 ISA mode is encoded in the least-significant bit
1863 of the address, mask it off return addresses for purposes of
1864 finding exception handling regions. */
1866 #define MASK_RETURN_ADDR GEN_INT (-2)
1869 /* Similarly, don't use the least-significant bit to tell pointers to
1870 code from vtable index. */
1872 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1874 /* The eliminations to $17 are only used for mips16 code. See the
1875 definition of HARD_FRAME_POINTER_REGNUM. */
1877 #define ELIMINABLE_REGS \
1878 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1879 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1880 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1881 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1882 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1883 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1885 /* We can always eliminate to the hard frame pointer. We can eliminate
1886 to the stack pointer unless a frame pointer is needed.
1888 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1889 reload may be unable to compute the address of a local variable,
1890 since there is no way to add a large constant to the stack pointer
1891 without using a temporary register. */
1892 #define CAN_ELIMINATE(FROM, TO) \
1893 ((TO) == HARD_FRAME_POINTER_REGNUM \
1894 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1895 && (!TARGET_MIPS16 \
1896 || compute_frame_size (get_frame_size ()) < 32768)))
1898 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1899 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1901 /* Allocate stack space for arguments at the beginning of each function. */
1902 #define ACCUMULATE_OUTGOING_ARGS 1
1904 /* The argument pointer always points to the first argument. */
1905 #define FIRST_PARM_OFFSET(FNDECL) 0
1907 /* o32 and o64 reserve stack space for all argument registers. */
1908 #define REG_PARM_STACK_SPACE(FNDECL) \
1910 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1913 /* Define this if it is the responsibility of the caller to
1914 allocate the area reserved for arguments passed in registers.
1915 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1916 of this macro is to determine whether the space is included in
1917 `current_function_outgoing_args_size'. */
1918 #define OUTGOING_REG_PARM_STACK_SPACE 1
1920 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1922 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1924 /* Symbolic macros for the registers used to return integer and floating
1927 #define GP_RETURN (GP_REG_FIRST + 2)
1928 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1930 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1932 /* Symbolic macros for the first/last argument registers. */
1934 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1935 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1936 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1937 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1939 #define LIBCALL_VALUE(MODE) \
1940 mips_function_value (NULL_TREE, NULL, (MODE))
1942 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1943 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1945 /* 1 if N is a possible register number for a function value.
1946 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1947 Currently, R2 and F0 are only implemented here (C has no complex type) */
1949 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1950 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1951 && (N) == FP_RETURN + 2))
1953 /* 1 if N is a possible register number for function argument passing.
1954 We have no FP argument registers when soft-float. When FP registers
1955 are 32 bits, we can't directly reference the odd numbered ones. */
1957 #define FUNCTION_ARG_REGNO_P(N) \
1958 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1959 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1962 /* This structure has to cope with two different argument allocation
1963 schemes. Most MIPS ABIs view the arguments as a structure, of which
1964 the first N words go in registers and the rest go on the stack. If I
1965 < N, the Ith word might go in Ith integer argument register or in a
1966 floating-point register. For these ABIs, we only need to remember
1967 the offset of the current argument into the structure.
1969 The EABI instead allocates the integer and floating-point arguments
1970 separately. The first N words of FP arguments go in FP registers,
1971 the rest go on the stack. Likewise, the first N words of the other
1972 arguments go in integer registers, and the rest go on the stack. We
1973 need to maintain three counts: the number of integer registers used,
1974 the number of floating-point registers used, and the number of words
1975 passed on the stack.
1977 We could keep separate information for the two ABIs (a word count for
1978 the standard ABIs, and three separate counts for the EABI). But it
1979 seems simpler to view the standard ABIs as forms of EABI that do not
1980 allocate floating-point registers.
1982 So for the standard ABIs, the first N words are allocated to integer
1983 registers, and function_arg decides on an argument-by-argument basis
1984 whether that argument should really go in an integer register, or in
1985 a floating-point one. */
1987 typedef struct mips_args {
1988 /* Always true for varargs functions. Otherwise true if at least
1989 one argument has been passed in an integer register. */
1992 /* The number of arguments seen so far. */
1993 unsigned int arg_number;
1995 /* The number of integer registers used so far. For all ABIs except
1996 EABI, this is the number of words that have been added to the
1997 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1998 unsigned int num_gprs;
2000 /* For EABI, the number of floating-point registers used so far. */
2001 unsigned int num_fprs;
2003 /* The number of words passed on the stack. */
2004 unsigned int stack_words;
2006 /* On the mips16, we need to keep track of which floating point
2007 arguments were passed in general registers, but would have been
2008 passed in the FP regs if this were a 32-bit function, so that we
2009 can move them to the FP regs if we wind up calling a 32-bit
2010 function. We record this information in fp_code, encoded in base
2011 four. A zero digit means no floating point argument, a one digit
2012 means an SFmode argument, and a two digit means a DFmode argument,
2013 and a three digit is not used. The low order digit is the first
2014 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2015 an SFmode argument. ??? A more sophisticated approach will be
2016 needed if MIPS_ABI != ABI_32. */
2019 /* True if the function has a prototype. */
2023 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2024 for a call to a function whose data type is FNTYPE.
2025 For a library call, FNTYPE is 0. */
2027 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2028 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2030 /* Update the data in CUM to advance over an argument
2031 of mode MODE and data type TYPE.
2032 (TYPE is null for libcalls where that information may not be available.) */
2034 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2035 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2037 /* Determine where to put an argument to a function.
2038 Value is zero to push the argument on the stack,
2039 or a hard register in which to store the argument.
2041 MODE is the argument's machine mode.
2042 TYPE is the data type of the argument (as a tree).
2043 This is null for libcalls where that information may
2045 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2046 the preceding args and about the function being called.
2047 NAMED is nonzero if this argument is a named parameter
2048 (otherwise it is an extra parameter matching an ellipsis). */
2050 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2051 function_arg( &CUM, MODE, TYPE, NAMED)
2053 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2055 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2056 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2058 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2059 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2061 /* True if using EABI and varargs can be passed in floating-point
2062 registers. Under these conditions, we need a more complex form
2063 of va_list, which tracks GPR, FPR and stack arguments separately. */
2064 #define EABI_FLOAT_VARARGS_P \
2065 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2068 /* Say that the epilogue uses the return address register. Note that
2069 in the case of sibcalls, the values "used by the epilogue" are
2070 considered live at the start of the called function. */
2071 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2073 /* Treat LOC as a byte offset from the stack pointer and round it up
2074 to the next fully-aligned offset. */
2075 #define MIPS_STACK_ALIGN(LOC) \
2076 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2079 /* Implement `va_start' for varargs and stdarg. */
2080 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2081 mips_va_start (valist, nextarg)
2083 /* Output assembler code to FILE to increment profiler label # LABELNO
2084 for profiling a function entry. */
2086 #define FUNCTION_PROFILER(FILE, LABELNO) \
2088 if (TARGET_MIPS16) \
2089 sorry ("mips16 function profiling"); \
2090 fprintf (FILE, "\t.set\tnoat\n"); \
2091 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2092 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2093 if (!TARGET_NEWABI) \
2096 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2097 TARGET_64BIT ? "dsubu" : "subu", \
2098 reg_names[STACK_POINTER_REGNUM], \
2099 reg_names[STACK_POINTER_REGNUM], \
2100 Pmode == DImode ? 16 : 8); \
2102 fprintf (FILE, "\tjal\t_mcount\n"); \
2103 fprintf (FILE, "\t.set\tat\n"); \
2106 /* No mips port has ever used the profiler counter word, so don't emit it
2107 or the label for it. */
2109 #define NO_PROFILE_COUNTERS 1
2111 /* Define this macro if the code for function profiling should come
2112 before the function prologue. Normally, the profiling code comes
2115 /* #define PROFILE_BEFORE_PROLOGUE */
2117 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2118 the stack pointer does not matter. The value is tested only in
2119 functions that have frame pointers.
2120 No definition is equivalent to always zero. */
2122 #define EXIT_IGNORE_STACK 1
2125 /* A C statement to output, on the stream FILE, assembler code for a
2126 block of data that contains the constant parts of a trampoline.
2127 This code should not include a label--the label is taken care of
2130 #define TRAMPOLINE_TEMPLATE(STREAM) \
2132 if (ptr_mode == DImode) \
2133 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2135 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2136 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2137 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2138 if (ptr_mode == DImode) \
2140 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2141 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2142 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2146 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2147 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2148 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2150 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2151 if (ptr_mode == DImode) \
2153 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2154 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2155 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2159 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2160 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2161 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2165 /* A C expression for the size in bytes of the trampoline, as an
2168 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2170 /* Alignment required for trampolines, in bits. */
2172 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2174 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2175 program and data caches. */
2177 #ifndef CACHE_FLUSH_FUNC
2178 #define CACHE_FLUSH_FUNC "_flush_cache"
2181 /* A C statement to initialize the variable parts of a trampoline.
2182 ADDR is an RTX for the address of the trampoline; FNADDR is an
2183 RTX for the address of the nested function; STATIC_CHAIN is an
2184 RTX for the static chain value that should be passed to the
2185 function when it is called. */
2187 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2189 rtx func_addr, chain_addr, end_addr; \
2191 func_addr = plus_constant (ADDR, 32); \
2192 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2193 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2194 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2195 end_addr = gen_reg_rtx (Pmode); \
2196 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2197 GEN_INT (TRAMPOLINE_SIZE))); \
2198 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2201 /* Addressing modes, and classification of registers for them. */
2203 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2204 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2205 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2207 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2208 and check its validity for a certain class.
2209 We have two alternate definitions for each of them.
2210 The usual definition accepts all pseudo regs; the other rejects them all.
2211 The symbol REG_OK_STRICT causes the latter definition to be used.
2213 Most source files want to accept pseudo regs in the hope that
2214 they will get allocated to the class that the insn wants them to be in.
2215 Some source files that are used after register allocation
2216 need to be strict. */
2218 #ifndef REG_OK_STRICT
2219 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2220 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2222 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2223 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2226 #define REG_OK_FOR_INDEX_P(X) 0
2229 /* Maximum number of registers that can appear in a valid memory address. */
2231 #define MAX_REGS_PER_ADDRESS 1
2233 #ifdef REG_OK_STRICT
2234 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2236 if (mips_legitimate_address_p (MODE, X, 1)) \
2240 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2242 if (mips_legitimate_address_p (MODE, X, 0)) \
2247 /* Check for constness inline but use mips_legitimate_address_p
2248 to check whether a constant really is an address. */
2250 #define CONSTANT_ADDRESS_P(X) \
2251 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2253 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2255 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2257 if (mips_legitimize_address (&(X), MODE)) \
2262 /* A C statement or compound statement with a conditional `goto
2263 LABEL;' executed if memory address X (an RTX) can have different
2264 meanings depending on the machine mode of the memory reference it
2267 Autoincrement and autodecrement addresses typically have
2268 mode-dependent effects because the amount of the increment or
2269 decrement is the size of the operand being addressed. Some
2270 machines have other mode-dependent addresses. Many RISC machines
2271 have no mode-dependent addresses.
2273 You may assume that ADDR is a valid address for the machine. */
2275 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2277 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2278 'the start of the function that this code is output in'. */
2280 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2281 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2282 asm_fprintf ((FILE), "%U%s", \
2283 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2285 asm_fprintf ((FILE), "%U%s", (NAME))
2287 /* Flag to mark a function decl symbol that requires a long call. */
2288 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2289 #define SYMBOL_REF_LONG_CALL_P(X) \
2290 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2292 /* True if we're generating a form of MIPS16 code in which jump tables
2293 are stored in the text section and encoded as 16-bit PC-relative
2294 offsets. This is only possible when general text loads are allowed,
2295 since the table access itself will be an "lh" instruction. */
2296 /* ??? 16-bit offsets can overflow in large functions. */
2297 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2299 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2301 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2303 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2305 /* Define this as 1 if `char' should by default be signed; else as 0. */
2306 #ifndef DEFAULT_SIGNED_CHAR
2307 #define DEFAULT_SIGNED_CHAR 1
2310 /* Max number of bytes we can move from memory to memory
2311 in one reasonably fast instruction. */
2312 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2313 #define MAX_MOVE_MAX 8
2315 /* Define this macro as a C expression which is nonzero if
2316 accessing less than a word of memory (i.e. a `char' or a
2317 `short') is no faster than accessing a word of memory, i.e., if
2318 such access require more than one instruction or if there is no
2319 difference in cost between byte and (aligned) word loads.
2321 On RISC machines, it tends to generate better code to define
2322 this as 1, since it avoids making a QI or HI mode register.
2324 But, generating word accesses for -mips16 is generally bad as shifts
2325 (often extended) would be needed for byte accesses. */
2326 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2328 /* Define this to be nonzero if shift instructions ignore all but the low-order
2330 #define SHIFT_COUNT_TRUNCATED 1
2332 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2333 is done just by pretending it is already truncated. */
2334 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2335 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2338 /* Specify the machine mode that pointers have.
2339 After generation of rtl, the compiler makes no further distinction
2340 between pointers and any other objects of this machine mode. */
2343 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2346 /* Give call MEMs SImode since it is the "most permissive" mode
2347 for both 32-bit and 64-bit targets. */
2349 #define FUNCTION_MODE SImode
2352 /* The cost of loading values from the constant pool. It should be
2353 larger than the cost of any constant we want to synthesize in-line. */
2355 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2357 /* A C expression for the cost of moving data from a register in
2358 class FROM to one in class TO. The classes are expressed using
2359 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2360 the default; other values are interpreted relative to that.
2362 It is not required that the cost always equal 2 when FROM is the
2363 same as TO; on some machines it is expensive to move between
2364 registers if they are not general registers.
2366 If reload sees an insn consisting of a single `set' between two
2367 hard registers, and if `REGISTER_MOVE_COST' applied to their
2368 classes returns a value of 2, reload does not check to ensure
2369 that the constraints of the insn are met. Setting a cost of
2370 other than 2 will allow reload to verify that the constraints are
2371 met. You should do this if the `movM' pattern's constraints do
2372 not allow such copying. */
2374 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2375 mips_register_move_cost (MODE, FROM, TO)
2377 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2378 (mips_cost->memory_latency \
2379 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2381 /* Define if copies to/from condition code registers should be avoided.
2383 This is needed for the MIPS because reload_outcc is not complete;
2384 it needs to handle cases where the source is a general or another
2385 condition code register. */
2386 #define AVOID_CCMODE_COPIES
2388 /* A C expression for the cost of a branch instruction. A value of
2389 1 is the default; other values are interpreted relative to that. */
2391 #define BRANCH_COST mips_branch_cost
2392 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2394 /* If defined, modifies the length assigned to instruction INSN as a
2395 function of the context in which it is used. LENGTH is an lvalue
2396 that contains the initially computed length of the insn and should
2397 be updated with the correct length of the insn. */
2398 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2399 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2401 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2402 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2404 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2405 "%*" OPCODE "%?\t" OPERANDS "%/"
2407 /* Return the asm template for a call. INSN is the instruction's mnemonic
2408 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2411 When generating GOT code without explicit relocation operators,
2412 all calls should use assembly macros. Otherwise, all indirect
2413 calls should use "jr" or "jalr"; we will arrange to restore $gp
2414 afterwards if necessary. Finally, we can only generate direct
2415 calls for -mabicalls by temporarily switching to non-PIC mode. */
2416 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2417 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2418 ? "%*" INSN "\t%" #OPNO "%/" \
2419 : REG_P (OPERANDS[OPNO]) \
2420 ? "%*" INSN "r\t%" #OPNO "%/" \
2422 ? (".option\tpic0\n\t" \
2423 "%*" INSN "\t%" #OPNO "%/\n\t" \
2425 : "%*" INSN "\t%" #OPNO "%/")
2427 /* Control the assembler format that we output. */
2429 /* Output to assembler file text saying following lines
2430 may contain character constants, extra white space, comments, etc. */
2433 #define ASM_APP_ON " #APP\n"
2436 /* Output to assembler file text saying following lines
2437 no longer contain unusual constructs. */
2440 #define ASM_APP_OFF " #NO_APP\n"
2443 #define REGISTER_NAMES \
2444 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2445 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2446 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2447 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2448 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2449 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2450 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2451 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2452 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2453 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2454 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2455 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2456 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2457 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2458 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2459 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2460 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2461 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2462 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2463 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2464 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2465 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2466 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2467 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2469 /* List the "software" names for each register. Also list the numerical
2470 names for $fp and $sp. */
2472 #define ADDITIONAL_REGISTER_NAMES \
2474 { "$29", 29 + GP_REG_FIRST }, \
2475 { "$30", 30 + GP_REG_FIRST }, \
2476 { "at", 1 + GP_REG_FIRST }, \
2477 { "v0", 2 + GP_REG_FIRST }, \
2478 { "v1", 3 + GP_REG_FIRST }, \
2479 { "a0", 4 + GP_REG_FIRST }, \
2480 { "a1", 5 + GP_REG_FIRST }, \
2481 { "a2", 6 + GP_REG_FIRST }, \
2482 { "a3", 7 + GP_REG_FIRST }, \
2483 { "t0", 8 + GP_REG_FIRST }, \
2484 { "t1", 9 + GP_REG_FIRST }, \
2485 { "t2", 10 + GP_REG_FIRST }, \
2486 { "t3", 11 + GP_REG_FIRST }, \
2487 { "t4", 12 + GP_REG_FIRST }, \
2488 { "t5", 13 + GP_REG_FIRST }, \
2489 { "t6", 14 + GP_REG_FIRST }, \
2490 { "t7", 15 + GP_REG_FIRST }, \
2491 { "s0", 16 + GP_REG_FIRST }, \
2492 { "s1", 17 + GP_REG_FIRST }, \
2493 { "s2", 18 + GP_REG_FIRST }, \
2494 { "s3", 19 + GP_REG_FIRST }, \
2495 { "s4", 20 + GP_REG_FIRST }, \
2496 { "s5", 21 + GP_REG_FIRST }, \
2497 { "s6", 22 + GP_REG_FIRST }, \
2498 { "s7", 23 + GP_REG_FIRST }, \
2499 { "t8", 24 + GP_REG_FIRST }, \
2500 { "t9", 25 + GP_REG_FIRST }, \
2501 { "k0", 26 + GP_REG_FIRST }, \
2502 { "k1", 27 + GP_REG_FIRST }, \
2503 { "gp", 28 + GP_REG_FIRST }, \
2504 { "sp", 29 + GP_REG_FIRST }, \
2505 { "fp", 30 + GP_REG_FIRST }, \
2506 { "ra", 31 + GP_REG_FIRST }, \
2507 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2510 /* This is meant to be redefined in the host dependent files. It is a
2511 set of alternative names and regnums for mips coprocessors. */
2513 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2515 /* A C compound statement to output to stdio stream STREAM the
2516 assembler syntax for an instruction operand X. X is an RTL
2519 CODE is a value that can be used to specify one of several ways
2520 of printing the operand. It is used when identical operands
2521 must be printed differently depending on the context. CODE
2522 comes from the `%' specification that was used to request
2523 printing of the operand. If the specification was just `%DIGIT'
2524 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2525 is the ASCII code for LTR.
2527 If X is a register, this macro should print the register's name.
2528 The names can be found in an array `reg_names' whose type is
2529 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2531 When the machine description has a specification `%PUNCT' (a `%'
2532 followed by a punctuation character), this macro is called with
2533 a null pointer for X and the punctuation character for CODE.
2535 See mips.c for the MIPS specific codes. */
2537 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2539 /* A C expression which evaluates to true if CODE is a valid
2540 punctuation character for use in the `PRINT_OPERAND' macro. If
2541 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2542 punctuation characters (except for the standard one, `%') are
2543 used in this way. */
2545 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2547 /* A C compound statement to output to stdio stream STREAM the
2548 assembler syntax for an instruction operand that is a memory
2549 reference whose address is ADDR. ADDR is an RTL expression. */
2551 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2554 /* A C statement, to be executed after all slot-filler instructions
2555 have been output. If necessary, call `dbr_sequence_length' to
2556 determine the number of slots filled in a sequence (zero if not
2557 currently outputting a sequence), to decide how many no-ops to
2558 output, or whatever.
2560 Don't define this macro if it has nothing to do, but it is
2561 helpful in reading assembly output if the extent of the delay
2562 sequence is made explicit (e.g. with white space).
2564 Note that output routines for instructions with delay slots must
2565 be prepared to deal with not being output as part of a sequence
2566 (i.e. when the scheduling pass is not run, or when no slot
2567 fillers could be found.) The variable `final_sequence' is null
2568 when not processing a sequence, otherwise it contains the
2569 `sequence' rtx being output. */
2571 #define DBR_OUTPUT_SEQEND(STREAM) \
2574 if (set_nomacro > 0 && --set_nomacro == 0) \
2575 fputs ("\t.set\tmacro\n", STREAM); \
2577 if (set_noreorder > 0 && --set_noreorder == 0) \
2578 fputs ("\t.set\treorder\n", STREAM); \
2580 fputs ("\n", STREAM); \
2585 /* How to tell the debugger about changes of source files. */
2586 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2587 mips_output_filename (STREAM, NAME)
2589 /* mips-tfile does not understand .stabd directives. */
2590 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2591 dbxout_begin_stabn_sline (LINE); \
2592 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2595 /* Use .loc directives for SDB line numbers. */
2596 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2597 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2599 /* The MIPS implementation uses some labels for its own purpose. The
2600 following lists what labels are created, and are all formed by the
2601 pattern $L[a-z].*. The machine independent portion of GCC creates
2602 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2604 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2605 $Lb[0-9]+ Begin blocks for MIPS debug support
2606 $Lc[0-9]+ Label for use in s<xx> operation.
2607 $Le[0-9]+ End blocks for MIPS debug support */
2609 #undef ASM_DECLARE_OBJECT_NAME
2610 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2611 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2613 /* Globalizing directive for a label. */
2614 #define GLOBAL_ASM_OP "\t.globl\t"
2616 /* This says how to define a global common symbol. */
2618 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2620 /* This says how to define a local common symbol (i.e., not visible to
2623 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2624 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2625 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2628 /* This says how to output an external. It would be possible not to
2629 output anything and let undefined symbol become external. However
2630 the assembler uses length information on externals to allocate in
2631 data/sdata bss/sbss, thereby saving exec time. */
2633 #undef ASM_OUTPUT_EXTERNAL
2634 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2635 mips_output_external(STREAM,DECL,NAME)
2637 /* This is how to declare a function name. The actual work of
2638 emitting the label is moved to function_prologue, so that we can
2639 get the line number correctly emitted before the .ent directive,
2640 and after any .file directives. Define as empty so that the function
2641 is not declared before the .ent directive elsewhere. */
2643 #undef ASM_DECLARE_FUNCTION_NAME
2644 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2646 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2647 #define FUNCTION_NAME_ALREADY_DECLARED 0
2650 /* This is how to store into the string LABEL
2651 the symbol_ref name of an internal numbered label where
2652 PREFIX is the class of label and NUM is the number within the class.
2653 This is suitable for output with `assemble_name'. */
2655 #undef ASM_GENERATE_INTERNAL_LABEL
2656 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2657 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2659 /* This is how to output an element of a case-vector that is absolute. */
2661 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2662 fprintf (STREAM, "\t%s\t%sL%d\n", \
2663 ptr_mode == DImode ? ".dword" : ".word", \
2664 LOCAL_LABEL_PREFIX, \
2667 /* This is how to output an element of a case-vector. We can make the
2668 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2671 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2673 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2674 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2675 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2676 else if (TARGET_GPWORD) \
2677 fprintf (STREAM, "\t%s\t%sL%d\n", \
2678 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2679 LOCAL_LABEL_PREFIX, VALUE); \
2680 else if (TARGET_RTP_PIC) \
2682 /* Make the entry relative to the start of the function. */ \
2683 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2684 fprintf (STREAM, "\t%s\t%sL%d-", \
2685 Pmode == DImode ? ".dword" : ".word", \
2686 LOCAL_LABEL_PREFIX, VALUE); \
2687 assemble_name (STREAM, XSTR (fnsym, 0)); \
2688 fprintf (STREAM, "\n"); \
2691 fprintf (STREAM, "\t%s\t%sL%d\n", \
2692 ptr_mode == DImode ? ".dword" : ".word", \
2693 LOCAL_LABEL_PREFIX, VALUE); \
2696 /* This is how to output an assembler line
2697 that says to advance the location counter
2698 to a multiple of 2**LOG bytes. */
2700 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2701 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2703 /* This is how to output an assembler line to advance the location
2704 counter by SIZE bytes. */
2706 #undef ASM_OUTPUT_SKIP
2707 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2708 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2710 /* This is how to output a string. */
2711 #undef ASM_OUTPUT_ASCII
2712 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2713 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2715 /* Output #ident as a in the read-only data section. */
2716 #undef ASM_OUTPUT_IDENT
2717 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2719 const char *p = STRING; \
2720 int size = strlen (p) + 1; \
2721 switch_to_section (readonly_data_section); \
2722 assemble_string (p, size); \
2725 /* Default to -G 8 */
2726 #ifndef MIPS_DEFAULT_GVALUE
2727 #define MIPS_DEFAULT_GVALUE 8
2730 /* Define the strings to put out for each section in the object file. */
2731 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2732 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2734 #undef READONLY_DATA_SECTION_ASM_OP
2735 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2737 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2740 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2741 TARGET_64BIT ? "dsubu" : "subu", \
2742 reg_names[STACK_POINTER_REGNUM], \
2743 reg_names[STACK_POINTER_REGNUM], \
2744 TARGET_64BIT ? "sd" : "sw", \
2746 reg_names[STACK_POINTER_REGNUM]); \
2750 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2753 if (! set_noreorder) \
2754 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2756 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2757 TARGET_64BIT ? "ld" : "lw", \
2759 reg_names[STACK_POINTER_REGNUM], \
2760 TARGET_64BIT ? "daddu" : "addu", \
2761 reg_names[STACK_POINTER_REGNUM], \
2762 reg_names[STACK_POINTER_REGNUM]); \
2764 if (! set_noreorder) \
2765 fprintf (STREAM, "\t.set\treorder\n"); \
2769 /* How to start an assembler comment.
2770 The leading space is important (the mips native assembler requires it). */
2771 #ifndef ASM_COMMENT_START
2772 #define ASM_COMMENT_START " #"
2775 /* Default definitions for size_t and ptrdiff_t. We must override the
2776 definitions from ../svr4.h on mips-*-linux-gnu. */
2779 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2782 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2785 /* Since the bits of the _init and _fini function is spread across
2786 many object files, each potentially with its own GP, we must assume
2787 we need to load our GP. We don't preserve $gp or $ra, since each
2788 init/fini chunk is supposed to initialize $gp, and crti/crtn
2789 already take care of preserving $ra and, when appropriate, $gp. */
2790 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2791 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2792 asm (SECTION_OP "\n\
2798 jal " USER_LABEL_PREFIX #FUNC "\n\
2799 " TEXT_SECTION_ASM_OP);
2800 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2801 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2802 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2803 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2804 asm (SECTION_OP "\n\
2809 .cpsetup $31, $2, 1b\n\
2810 jal " USER_LABEL_PREFIX #FUNC "\n\
2811 " TEXT_SECTION_ASM_OP);
2816 #define HAVE_AS_TLS 0
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