1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern int target_flags;
31 /* MIPS external variables defined in mips.c. */
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
96 /* The ISA level that the processor implements. */
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern int mips_string_length; /* length of strings for mips16 */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
138 /* Run-time compilation parameters selecting different hardware subsets. */
140 /* Macros used in the machine description to test the flags. */
142 /* Bits for real switches */
143 #define MASK_INT64 0x00000001 /* ints are 64 bits */
144 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
145 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
146 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
147 multiply-add operations. */
148 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
149 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
150 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
151 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
152 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
153 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
154 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
155 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
156 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
157 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
158 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
159 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
160 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
161 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
162 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
163 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
164 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
165 #define MASK_NO_CHECK_ZERO_DIV \
166 0x00200000 /* divide by zero checking */
167 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
169 #define MASK_UNINIT_CONST_IN_RODATA \
170 0x00800000 /* Store uninitialized
172 #define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */
173 #define MASK_FIX_SB1 0x02000000 /* Work around SB-1 errata. */
175 /* Debug switches, not documented */
176 #define MASK_DEBUG 0 /* unused */
177 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
178 #define MASK_DEBUG_D 0 /* don't do define_split's */
179 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
181 /* Dummy switches used only in specs */
182 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
184 /* r4000 64 bit sizes */
185 #define TARGET_INT64 (target_flags & MASK_INT64)
186 #define TARGET_LONG64 (target_flags & MASK_LONG64)
187 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
188 #define TARGET_64BIT (target_flags & MASK_64BIT)
190 /* Mips vs. GNU linker */
191 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
193 /* Mips vs. GNU assembler */
194 #define TARGET_GAS (target_flags & MASK_GAS)
195 #define TARGET_MIPS_AS (!TARGET_GAS)
198 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
199 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
200 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
201 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
203 /* Reg. Naming in .s ($21 vs. $a0) */
204 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
206 /* call memcpy instead of inline code */
207 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
209 /* .abicalls, etc from Pyramid V.4 */
210 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
211 #define TARGET_XGOT (target_flags & MASK_XGOT)
213 /* software floating point */
214 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
215 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
217 /* always call through a register */
218 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
220 /* generate embedded PIC code;
222 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
224 /* for embedded systems, optimize for
225 reduced RAM space instead of for
227 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
229 /* always store uninitialized const
230 variables in rodata, requires
231 TARGET_EMBEDDED_DATA. */
232 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
234 /* generate big endian code. */
235 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
237 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
238 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
240 #define TARGET_MAD (target_flags & MASK_MAD)
242 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
244 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
246 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
248 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
250 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
252 /* Work around R4000 errata. */
253 #define TARGET_FIX_R4000 (target_flags & MASK_FIX_R4000)
255 /* True if we should use NewABI-style relocation operators for
256 symbolic addresses. This is never true for mips16 code,
257 which has its own conventions. */
259 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
262 /* True if the call patterns should be split into a jalr followed by
263 an instruction to restore $gp. This is only ever true for SVR4 PIC,
264 in which $gp is call-clobbered. It is only safe to split the load
265 from the call when every use of $gp is explicit. */
267 #define TARGET_SPLIT_CALLS \
268 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
270 /* True if we can optimize sibling calls. For simplicity, we only
271 handle cases in which call_insn_operand will reject invalid
272 sibcall addresses. There are two cases in which this isn't true:
274 - TARGET_MIPS16. call_insn_operand accepts constant addresses
275 but there is no direct jump instruction. It isn't worth
276 using sibling calls in this case anyway; they would usually
277 be longer than normal calls.
279 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
280 accepts global constants, but "jr $25" is the only allowed
283 #define TARGET_SIBCALLS \
284 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
286 /* True if .gpword or .gpdword should be used for switch tables.
287 There are some problems with using these directives with the
290 - It has been reported that some versions of the native n32
291 assembler mishandle .gpword, complaining that symbols are
292 global when they are in fact local.
294 - The native assemblers don't understand .gpdword.
296 - Although GAS does understand .gpdword, the native linker
297 mishandles the relocations GAS generates (R_MIPS_GPREL32
298 followed by R_MIPS_64).
300 We therefore disable GP-relative switch tables for n32 and n64
302 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
304 /* Generate mips16 code */
305 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
307 /* Generic ISA defines. */
308 #define ISA_MIPS1 (mips_isa == 1)
309 #define ISA_MIPS2 (mips_isa == 2)
310 #define ISA_MIPS3 (mips_isa == 3)
311 #define ISA_MIPS4 (mips_isa == 4)
312 #define ISA_MIPS32 (mips_isa == 32)
313 #define ISA_MIPS32R2 (mips_isa == 33)
314 #define ISA_MIPS64 (mips_isa == 64)
316 /* Architecture target defines. */
317 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
318 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
319 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
320 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
321 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
322 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
323 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
324 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
326 /* Scheduling target defines. */
327 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
328 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
329 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
330 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
331 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
332 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
333 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
334 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
335 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
337 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
338 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
340 /* IRIX specific stuff. */
341 #define TARGET_IRIX 0
342 #define TARGET_IRIX5 0
343 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
345 /* Define preprocessor macros for the -march and -mtune options.
346 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
347 processor. If INFO's canonical name is "foo", define PREFIX to
348 be "foo", and define an additional macro PREFIX_FOO. */
349 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
354 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
355 for (p = macro; *p != 0; p++) \
358 builtin_define (macro); \
359 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
364 /* Target CPU builtins. */
365 #define TARGET_CPU_CPP_BUILTINS() \
368 builtin_assert ("cpu=mips"); \
369 builtin_define ("__mips__"); \
370 builtin_define ("_mips"); \
372 /* We do this here because __mips is defined below \
373 and so we can't use builtin_define_std. */ \
375 builtin_define ("mips"); \
377 /* Treat _R3000 and _R4000 like register-size defines, \
378 which is how they've historically been used. */ \
381 builtin_define ("__mips64"); \
382 builtin_define_std ("R4000"); \
383 builtin_define ("_R4000"); \
387 builtin_define_std ("R3000"); \
388 builtin_define ("_R3000"); \
390 if (TARGET_FLOAT64) \
391 builtin_define ("__mips_fpr=64"); \
393 builtin_define ("__mips_fpr=32"); \
396 builtin_define ("__mips16"); \
398 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
399 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
403 builtin_define ("__mips=1"); \
404 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
406 else if (ISA_MIPS2) \
408 builtin_define ("__mips=2"); \
409 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
411 else if (ISA_MIPS3) \
413 builtin_define ("__mips=3"); \
414 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
416 else if (ISA_MIPS4) \
418 builtin_define ("__mips=4"); \
419 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
421 else if (ISA_MIPS32) \
423 builtin_define ("__mips=32"); \
424 builtin_define ("__mips_isa_rev=1"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
427 else if (ISA_MIPS32R2) \
429 builtin_define ("__mips=32"); \
430 builtin_define ("__mips_isa_rev=2"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
433 else if (ISA_MIPS64) \
435 builtin_define ("__mips=64"); \
436 builtin_define ("__mips_isa_rev=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
440 if (TARGET_HARD_FLOAT) \
441 builtin_define ("__mips_hard_float"); \
442 else if (TARGET_SOFT_FLOAT) \
443 builtin_define ("__mips_soft_float"); \
445 if (TARGET_SINGLE_FLOAT) \
446 builtin_define ("__mips_single_float"); \
448 if (TARGET_BIG_ENDIAN) \
450 builtin_define_std ("MIPSEB"); \
451 builtin_define ("_MIPSEB"); \
455 builtin_define_std ("MIPSEL"); \
456 builtin_define ("_MIPSEL"); \
459 /* Macros dependent on the C dialect. */ \
460 if (preprocessing_asm_p ()) \
462 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
463 builtin_define ("_LANGUAGE_ASSEMBLY"); \
465 else if (c_dialect_cxx ()) \
467 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
468 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
469 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
473 builtin_define_std ("LANGUAGE_C"); \
474 builtin_define ("_LANGUAGE_C"); \
476 if (c_dialect_objc ()) \
478 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
479 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
480 /* Bizarre, but needed at least for Irix. */ \
481 builtin_define_std ("LANGUAGE_C"); \
482 builtin_define ("_LANGUAGE_C"); \
485 if (mips_abi == ABI_EABI) \
486 builtin_define ("__mips_eabi"); \
492 /* Macro to define tables used to set the flags.
493 This is a list in braces of pairs in braces,
494 each pair being { "NAME", VALUE }
495 where VALUE is the bits to set or minus the bits to clear.
496 An empty string NAME is used to identify the default VALUE. */
498 #define TARGET_SWITCHES \
500 SUBTARGET_TARGET_SWITCHES \
501 {"int64", MASK_INT64 | MASK_LONG64, \
502 N_("Use 64-bit int type")}, \
503 {"long64", MASK_LONG64, \
504 N_("Use 64-bit long type")}, \
505 {"long32", -(MASK_LONG64 | MASK_INT64), \
506 N_("Use 32-bit long type")}, \
507 {"split-addresses", MASK_SPLIT_ADDR, \
508 N_("Optimize lui/addiu address loads")}, \
509 {"no-split-addresses", -MASK_SPLIT_ADDR, \
510 N_("Don't optimize lui/addiu address loads")}, \
511 {"mips-as", -MASK_GAS, \
512 N_("Use MIPS as")}, \
515 {"rnames", MASK_NAME_REGS, \
516 N_("Use symbolic register names")}, \
517 {"no-rnames", -MASK_NAME_REGS, \
518 N_("Don't use symbolic register names")}, \
520 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
522 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
524 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
526 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
528 N_("Output compiler statistics (now ignored)")}, \
530 N_("Don't output compiler statistics")}, \
531 {"memcpy", MASK_MEMCPY, \
532 N_("Don't optimize block moves")}, \
533 {"no-memcpy", -MASK_MEMCPY, \
534 N_("Optimize block moves")}, \
535 {"mips-tfile", MASK_MIPS_TFILE, \
536 N_("Use mips-tfile asm postpass")}, \
537 {"no-mips-tfile", -MASK_MIPS_TFILE, \
538 N_("Don't use mips-tfile asm postpass")}, \
539 {"soft-float", MASK_SOFT_FLOAT, \
540 N_("Use software floating point")}, \
541 {"hard-float", -MASK_SOFT_FLOAT, \
542 N_("Use hardware floating point")}, \
543 {"fp64", MASK_FLOAT64, \
544 N_("Use 64-bit FP registers")}, \
545 {"fp32", -MASK_FLOAT64, \
546 N_("Use 32-bit FP registers")}, \
547 {"gp64", MASK_64BIT, \
548 N_("Use 64-bit general registers")}, \
549 {"gp32", -MASK_64BIT, \
550 N_("Use 32-bit general registers")}, \
551 {"abicalls", MASK_ABICALLS, \
552 N_("Use Irix PIC")}, \
553 {"no-abicalls", -MASK_ABICALLS, \
554 N_("Don't use Irix PIC")}, \
555 {"long-calls", MASK_LONG_CALLS, \
556 N_("Use indirect calls")}, \
557 {"no-long-calls", -MASK_LONG_CALLS, \
558 N_("Don't use indirect calls")}, \
559 {"embedded-pic", MASK_EMBEDDED_PIC, \
560 N_("Use embedded PIC")}, \
561 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
562 N_("Don't use embedded PIC")}, \
563 {"embedded-data", MASK_EMBEDDED_DATA, \
564 N_("Use ROM instead of RAM")}, \
565 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
566 N_("Don't use ROM instead of RAM")}, \
567 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
568 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
569 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
570 N_("Don't put uninitialized constants in ROM")}, \
571 {"eb", MASK_BIG_ENDIAN, \
572 N_("Use big-endian byte order")}, \
573 {"el", -MASK_BIG_ENDIAN, \
574 N_("Use little-endian byte order")}, \
575 {"single-float", MASK_SINGLE_FLOAT, \
576 N_("Use single (32-bit) FP only")}, \
577 {"double-float", -MASK_SINGLE_FLOAT, \
578 N_("Don't use single (32-bit) FP only")}, \
580 N_("Use multiply accumulate")}, \
581 {"no-mad", -MASK_MAD, \
582 N_("Don't use multiply accumulate")}, \
583 {"no-fused-madd", MASK_NO_FUSED_MADD, \
584 N_("Don't generate fused multiply/add instructions")}, \
585 {"fused-madd", -MASK_NO_FUSED_MADD, \
586 N_("Generate fused multiply/add instructions")}, \
587 {"fix4300", MASK_4300_MUL_FIX, \
588 N_("Work around early 4300 hardware bug")}, \
589 {"no-fix4300", -MASK_4300_MUL_FIX, \
590 N_("Don't work around early 4300 hardware bug")}, \
591 {"fix-sb1", MASK_FIX_SB1, \
592 N_("Work around errata for early SB-1 revision 2 cores")}, \
593 {"no-fix-sb1", -MASK_FIX_SB1, \
594 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
595 {"fix-r4000", MASK_FIX_R4000, \
596 N_("Work around R4000 errata")}, \
597 {"no-fix-r4000", -MASK_FIX_R4000, \
598 N_("Don't work around R4000 errata")}, \
599 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
600 N_("Trap on integer divide by zero")}, \
601 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
602 N_("Don't trap on integer divide by zero")}, \
603 { "branch-likely", MASK_BRANCHLIKELY, \
604 N_("Use Branch Likely instructions, overriding default for arch")}, \
605 { "no-branch-likely", -MASK_BRANCHLIKELY, \
606 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
607 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
608 N_("Use NewABI-style %reloc() assembly operators")}, \
609 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
610 N_("Use assembler macros instead of relocation operators")}, \
611 {"ips16", MASK_MIPS16, \
612 N_("Generate mips16 code") }, \
613 {"no-mips16", -MASK_MIPS16, \
614 N_("Generate normal-mode code") }, \
615 {"xgot", MASK_XGOT, \
616 N_("Lift restrictions on GOT size") }, \
617 {"no-xgot", -MASK_XGOT, \
618 N_("Do not lift restrictions on GOT size") }, \
619 {"debug", MASK_DEBUG, \
621 {"debugc", MASK_DEBUG_C, \
623 {"debugd", MASK_DEBUG_D, \
625 {"debugg", MASK_DEBUG_G, \
627 {"", (TARGET_DEFAULT \
628 | TARGET_CPU_DEFAULT \
629 | TARGET_ENDIAN_DEFAULT), \
633 /* Default target_flags if no switches are specified */
635 #ifndef TARGET_DEFAULT
636 #define TARGET_DEFAULT 0
639 #ifndef TARGET_CPU_DEFAULT
640 #define TARGET_CPU_DEFAULT 0
643 #ifndef TARGET_ENDIAN_DEFAULT
644 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
647 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
648 #ifndef MIPS_ISA_DEFAULT
649 #ifndef MIPS_CPU_STRING_DEFAULT
650 #define MIPS_CPU_STRING_DEFAULT "from-abi"
656 /* Make this compile time constant for libgcc2 */
658 #define TARGET_64BIT 1
660 #define TARGET_64BIT 0
662 #endif /* IN_LIBGCC2 */
664 #ifndef MULTILIB_ENDIAN_DEFAULT
665 #if TARGET_ENDIAN_DEFAULT == 0
666 #define MULTILIB_ENDIAN_DEFAULT "EL"
668 #define MULTILIB_ENDIAN_DEFAULT "EB"
672 #ifndef MULTILIB_ISA_DEFAULT
673 # if MIPS_ISA_DEFAULT == 1
674 # define MULTILIB_ISA_DEFAULT "mips1"
676 # if MIPS_ISA_DEFAULT == 2
677 # define MULTILIB_ISA_DEFAULT "mips2"
679 # if MIPS_ISA_DEFAULT == 3
680 # define MULTILIB_ISA_DEFAULT "mips3"
682 # if MIPS_ISA_DEFAULT == 4
683 # define MULTILIB_ISA_DEFAULT "mips4"
685 # if MIPS_ISA_DEFAULT == 32
686 # define MULTILIB_ISA_DEFAULT "mips32"
688 # if MIPS_ISA_DEFAULT == 33
689 # define MULTILIB_ISA_DEFAULT "mips32r2"
691 # if MIPS_ISA_DEFAULT == 64
692 # define MULTILIB_ISA_DEFAULT "mips64"
694 # define MULTILIB_ISA_DEFAULT "mips1"
704 #ifndef MULTILIB_DEFAULTS
705 #define MULTILIB_DEFAULTS \
706 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
709 /* We must pass -EL to the linker by default for little endian embedded
710 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
711 linker will default to using big-endian output files. The OUTPUT_FORMAT
712 line must be in the linker script, otherwise -EB/-EL will not work. */
715 #if TARGET_ENDIAN_DEFAULT == 0
716 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
718 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
722 #define TARGET_OPTIONS \
724 SUBTARGET_TARGET_OPTIONS \
725 { "tune=", &mips_tune_string, \
726 N_("Specify CPU for scheduling purposes"), 0}, \
727 { "arch=", &mips_arch_string, \
728 N_("Specify CPU for code generation purposes"), 0}, \
729 { "abi=", &mips_abi_string, \
730 N_("Specify an ABI"), 0}, \
731 { "ips", &mips_isa_string, \
732 N_("Specify a Standard MIPS ISA"), 0}, \
733 { "no-flush-func", &mips_cache_flush_func, \
734 N_("Don't call any cache flush functions"), 0}, \
735 { "flush-func=", &mips_cache_flush_func, \
736 N_("Specify cache flush function"), 0}, \
739 /* This is meant to be redefined in the host dependent files. */
740 #define SUBTARGET_TARGET_OPTIONS
742 /* Support for a compile-time default CPU, et cetera. The rules are:
743 --with-arch is ignored if -march is specified or a -mips is specified
744 (other than -mips16).
745 --with-tune is ignored if -mtune is specified.
746 --with-abi is ignored if -mabi is specified.
747 --with-float is ignored if -mhard-float or -msoft-float are
749 #define OPTION_DEFAULT_SPECS \
750 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
751 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
752 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
753 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
756 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
760 /* Generate three-operand multiply instructions for SImode. */
761 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
771 /* Generate three-operand multiply instructions for DImode. */
772 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
775 /* Macros to decide whether certain features are available or not,
776 depending on the instruction set architecture level. */
778 #define HAVE_SQRT_P() (!ISA_MIPS1)
780 /* True if the ABI can only work with 64-bit integer registers. We
781 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
782 otherwise floating-point registers must also be 64-bit. */
783 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
785 /* Likewise for 32-bit regs. */
786 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
788 /* True if symbols are 64 bits wide. At present, n64 is the only
789 ABI for which this is true. */
790 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
792 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
793 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
797 /* ISA has branch likely instructions (eg. mips2). */
798 /* Disable branchlikely for tx39 until compare rewrite. They haven't
799 been generated up to this point. */
800 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
803 /* ISA has the conditional move instructions introduced in mips4. */
804 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
808 && !TARGET_MIPS5500 \
811 /* ISA has just the integer condition move instructions (movn,movz) */
812 #define ISA_HAS_INT_CONDMOVE 0
814 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
815 branch on CC, and move (both FP and non-FP) on CC. */
816 #define ISA_HAS_8CC (ISA_MIPS4 \
821 /* This is a catch all for other mips4 instructions: indexed load, the
822 FP madd and msub instructions, and the FP recip and recip sqrt
824 #define ISA_HAS_FP4 ((ISA_MIPS4 \
828 /* ISA has conditional trap instructions. */
829 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
832 /* ISA has integer multiply-accumulate instructions, madd and msub. */
833 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
838 /* ISA has floating-point nmadd and nmsub instructions. */
839 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
841 && (!TARGET_MIPS5400 || TARGET_MAD) \
844 /* ISA has count leading zeroes/ones instruction (not implemented). */
845 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
850 /* ISA has double-word count leading zeroes/ones instruction (not
852 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
855 /* ISA has three operand multiply instructions that put
856 the high part in an accumulator: mulhi or mulhiu. */
857 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
862 /* ISA has three operand multiply instructions that
863 negates the result and puts the result in an accumulator. */
864 #define ISA_HAS_MULS (TARGET_MIPS5400 \
869 /* ISA has three operand multiply instructions that subtracts the
870 result from a 4th operand and puts the result in an accumulator. */
871 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
875 /* ISA has three operand multiply instructions that the result
876 from a 4th operand and puts the result in an accumulator. */
877 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
883 /* ISA has 32-bit rotate right instruction. */
884 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
891 /* ISA has 64-bit rotate right instruction. */
892 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
894 && (TARGET_MIPS5400 \
899 /* ISA has data prefetch instructions. This controls use of 'pref'. */
900 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
906 /* ISA has data indexed prefetch instructions. This controls use of
907 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
908 (prefx is a cop1x instruction, so can only be used if FP is
910 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
914 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
915 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
916 also requires TARGET_DOUBLE_FLOAT. */
917 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
919 /* ISA includes the MIPS32r2 seb and seh instructions. */
920 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
924 /* True if the result of a load is not available to the next instruction.
925 A nop will then be needed between instructions like "lw $4,..."
926 and "addiu $4,$4,1". */
927 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
928 && !TARGET_MIPS3900 \
931 /* Likewise mtc1 and mfc1. */
932 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
934 /* Likewise floating-point comparisons. */
935 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
937 /* True if mflo and mfhi can be immediately followed by instructions
938 which write to the HI and LO registers.
940 According to MIPS specifications, MIPS ISAs I, II, and III need
941 (at least) two instructions between the reads of HI/LO and
942 instructions which write them, and later ISAs do not. Contradicting
943 the MIPS specifications, some MIPS IV processor user manuals (e.g.
944 the UM for the NEC Vr5000) document needing the instructions between
945 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
946 MIPS64 and later ISAs to have the interlocks, plus any specific
947 earlier-ISA CPUs for which CPU documentation declares that the
948 instructions are really interlocked. */
949 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
954 /* Add -G xx support. */
956 #undef SWITCH_TAKES_ARG
957 #define SWITCH_TAKES_ARG(CHAR) \
958 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
960 #define OVERRIDE_OPTIONS override_options ()
962 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
964 /* Show we can debug even without a frame pointer. */
965 #define CAN_DEBUG_WITHOUT_FP
967 /* Tell collect what flags to pass to nm. */
969 #define NM_FLAGS "-Bn"
973 /* Assembler specs. */
975 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
978 #define MIPS_AS_ASM_SPEC "\
979 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
980 %{pipe: %e-pipe is not supported} \
981 %{K} %(subtarget_mips_as_asm_spec)"
983 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
984 rather than gas. It may be overridden by subtargets. */
986 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
987 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
990 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
993 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
995 #define SUBTARGET_TARGET_SWITCHES
997 #ifndef MIPS_ABI_DEFAULT
998 #define MIPS_ABI_DEFAULT ABI_32
1001 /* Use the most portable ABI flag for the ASM specs. */
1003 #if MIPS_ABI_DEFAULT == ABI_32
1004 #define MULTILIB_ABI_DEFAULT "mabi=32"
1005 #define ASM_ABI_DEFAULT_SPEC "-32"
1008 #if MIPS_ABI_DEFAULT == ABI_O64
1009 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1010 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1013 #if MIPS_ABI_DEFAULT == ABI_N32
1014 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1015 #define ASM_ABI_DEFAULT_SPEC "-n32"
1018 #if MIPS_ABI_DEFAULT == ABI_64
1019 #define MULTILIB_ABI_DEFAULT "mabi=64"
1020 #define ASM_ABI_DEFAULT_SPEC "-64"
1023 #if MIPS_ABI_DEFAULT == ABI_EABI
1024 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1025 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1028 /* Only ELF targets can switch the ABI. */
1029 #ifndef OBJECT_FORMAT_ELF
1030 #undef ASM_ABI_DEFAULT_SPEC
1031 #define ASM_ABI_DEFAULT_SPEC ""
1034 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1035 GAS_ASM_SPEC as the default, depending upon the value of
1038 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1041 #define TARGET_ASM_SPEC "\
1042 %{mmips-as: %(mips_as_asm_spec)} \
1043 %{!mmips-as: %(gas_asm_spec)}"
1047 #define TARGET_ASM_SPEC "\
1048 %{!mgas: %(mips_as_asm_spec)} \
1049 %{mgas: %(gas_asm_spec)}"
1051 #endif /* not GAS */
1053 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1054 to the assembler. It may be overridden by subtargets. */
1055 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1056 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1058 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1061 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1062 the assembler. It may be overridden by subtargets. */
1063 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1064 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1065 %{g} %{g0} %{g1} %{g2} %{g3} \
1066 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1067 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1068 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1069 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1073 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1075 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1077 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1078 %{!gcoff*:-no-mdebug}"
1080 #define MDEBUG_ASM_SPEC ""
1081 #endif /* not GAS */
1083 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1084 overridden by subtargets. */
1086 #ifndef SUBTARGET_ASM_SPEC
1087 #define SUBTARGET_ASM_SPEC ""
1090 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1091 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1092 whether we're using GAS. These options can only be used properly
1093 with GAS, and it is better to get an error from a non-GAS assembler
1094 than to silently generate bad code. */
1098 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1099 %{mips32} %{mips32r2} %{mips64} \
1100 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1101 %(subtarget_asm_optimizing_spec) \
1102 %(subtarget_asm_debugging_spec) \
1104 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1105 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1106 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1107 %(target_asm_spec) \
1108 %(subtarget_asm_spec)"
1110 /* Extra switches sometimes passed to the linker. */
1111 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1112 will interpret it as a -b option. */
1115 #define LINK_SPEC "\
1117 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1118 %{bestGnum} %{shared} %{non_shared}"
1119 #endif /* LINK_SPEC defined */
1122 /* Specs for the compiler proper */
1124 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1125 overridden by subtargets. */
1126 #ifndef SUBTARGET_CC1_SPEC
1127 #define SUBTARGET_CC1_SPEC ""
1130 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1134 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1135 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1137 %(subtarget_cc1_spec)"
1140 /* Preprocessor specs. */
1142 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1143 overridden by subtargets. */
1144 #ifndef SUBTARGET_CPP_SPEC
1145 #define SUBTARGET_CPP_SPEC ""
1148 #define CPP_SPEC "%(subtarget_cpp_spec)"
1150 /* This macro defines names of additional specifications to put in the specs
1151 that can be used in various specifications like CC1_SPEC. Its definition
1152 is an initializer with a subgrouping for each command option.
1154 Each subgrouping contains a string constant, that defines the
1155 specification name, and a string constant that used by the GCC driver
1158 Do not define this macro if it does not need to do anything. */
1160 #define EXTRA_SPECS \
1161 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1162 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1163 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1164 { "gas_asm_spec", GAS_ASM_SPEC }, \
1165 { "target_asm_spec", TARGET_ASM_SPEC }, \
1166 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1167 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1168 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1169 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1170 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1171 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1172 { "endian_spec", ENDIAN_SPEC }, \
1173 SUBTARGET_EXTRA_SPECS
1175 #ifndef SUBTARGET_EXTRA_SPECS
1176 #define SUBTARGET_EXTRA_SPECS
1179 /* If defined, this macro is an additional prefix to try after
1180 `STANDARD_EXEC_PREFIX'. */
1182 #ifndef MD_EXEC_PREFIX
1183 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1186 #ifndef MD_STARTFILE_PREFIX
1187 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1191 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1192 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1193 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1195 #ifndef PREFERRED_DEBUGGING_TYPE
1196 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1199 /* By default, turn on GDB extensions. */
1200 #define DEFAULT_GDB_EXTENSIONS 1
1202 /* If we are passing smuggling stabs through the MIPS ECOFF object
1203 format, put a comment in front of the .stab<x> operation so
1204 that the MIPS assembler does not choke. The mips-tfile program
1205 will correctly put the stab into the object file. */
1207 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1208 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1209 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1211 /* Local compiler-generated symbols must have a prefix that the assembler
1212 understands. By default, this is $, although some targets (e.g.,
1213 NetBSD-ELF) need to override this. */
1215 #ifndef LOCAL_LABEL_PREFIX
1216 #define LOCAL_LABEL_PREFIX "$"
1219 /* By default on the mips, external symbols do not have an underscore
1220 prepended, but some targets (e.g., NetBSD) require this. */
1222 #ifndef USER_LABEL_PREFIX
1223 #define USER_LABEL_PREFIX ""
1226 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1227 since the length can run past this up to a continuation point. */
1228 #undef DBX_CONTIN_LENGTH
1229 #define DBX_CONTIN_LENGTH 1500
1231 /* How to renumber registers for dbx and gdb. */
1232 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1234 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1235 #define DWARF_FRAME_REGNUM(REG) (REG)
1237 /* The DWARF 2 CFA column which tracks the return address. */
1238 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1240 /* The DWARF 2 CFA column which tracks the return address from a
1241 signal handler context. */
1242 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1244 /* Before the prologue, RA lives in r31. */
1245 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1247 /* Describe how we implement __builtin_eh_return. */
1248 #define EH_RETURN_DATA_REGNO(N) \
1249 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1251 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1253 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1254 The default for this in 64-bit mode is 8, which causes problems with
1255 SFmode register saves. */
1256 #define DWARF_CIE_DATA_ALIGNMENT 4
1258 /* Correct the offset of automatic variables and arguments. Note that
1259 the MIPS debug format wants all automatic variables and arguments
1260 to be in terms of the virtual frame pointer (stack pointer before
1261 any adjustment in the function), while the MIPS 3.0 linker wants
1262 the frame pointer to be the stack pointer after the initial
1265 #define DEBUGGER_AUTO_OFFSET(X) \
1266 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1267 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1268 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1270 /* Target machine storage layout */
1272 #define BITS_BIG_ENDIAN 0
1273 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1274 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1276 /* Define this to set the endianness to use in libgcc2.c, which can
1277 not depend on target_flags. */
1278 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1279 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1281 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1284 #define MAX_BITS_PER_WORD 64
1286 /* Width of a word, in units (bytes). */
1287 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1288 #define MIN_UNITS_PER_WORD 4
1290 /* For MIPS, width of a floating point register. */
1291 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1293 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1294 the next available register. */
1295 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1297 /* The largest size of value that can be held in floating-point
1298 registers and moved with a single instruction. */
1299 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1301 /* The largest size of value that can be held in floating-point
1303 #define UNITS_PER_FPVALUE \
1304 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1306 /* The number of bytes in a double. */
1307 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1309 /* Set the sizes of the core types. */
1310 #define SHORT_TYPE_SIZE 16
1311 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1312 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1313 #define LONG_LONG_TYPE_SIZE 64
1315 #define FLOAT_TYPE_SIZE 32
1316 #define DOUBLE_TYPE_SIZE 64
1317 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1319 /* long double is not a fixed mode, but the idea is that, if we
1320 support long double, we also want a 128-bit integer type. */
1321 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1324 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1325 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1326 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1328 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1332 /* Width in bits of a pointer. */
1333 #ifndef POINTER_SIZE
1334 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1337 #define POINTERS_EXTEND_UNSIGNED 0
1339 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1340 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1342 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1345 /* Allocation boundary (in *bits*) for the code of a function. */
1346 #define FUNCTION_BOUNDARY 32
1348 /* Alignment of field after `int : 0' in a structure. */
1349 #define EMPTY_FIELD_BOUNDARY 32
1351 /* Every structure's size must be a multiple of this. */
1352 /* 8 is observed right on a DECstation and on riscos 4.02. */
1353 #define STRUCTURE_SIZE_BOUNDARY 8
1355 /* There is no point aligning anything to a rounder boundary than this. */
1356 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1358 /* All accesses must be aligned. */
1359 #define STRICT_ALIGNMENT 1
1361 /* Define this if you wish to imitate the way many other C compilers
1362 handle alignment of bitfields and the structures that contain
1365 The behavior is that the type written for a bit-field (`int',
1366 `short', or other integer type) imposes an alignment for the
1367 entire structure, as if the structure really did contain an
1368 ordinary field of that type. In addition, the bit-field is placed
1369 within the structure so that it would fit within such a field,
1370 not crossing a boundary for it.
1372 Thus, on most machines, a bit-field whose type is written as `int'
1373 would not cross a four-byte boundary, and would force four-byte
1374 alignment for the whole structure. (The alignment used may not
1375 be four bytes; it is controlled by the other alignment
1378 If the macro is defined, its definition should be a C expression;
1379 a nonzero value for the expression enables this behavior. */
1381 #define PCC_BITFIELD_TYPE_MATTERS 1
1383 /* If defined, a C expression to compute the alignment given to a
1384 constant that is being placed in memory. CONSTANT is the constant
1385 and ALIGN is the alignment that the object would ordinarily have.
1386 The value of this macro is used instead of that alignment to align
1389 If this macro is not defined, then ALIGN is used.
1391 The typical use of this macro is to increase alignment for string
1392 constants to be word aligned so that `strcpy' calls that copy
1393 constants can be done inline. */
1395 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1396 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1397 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1399 /* If defined, a C expression to compute the alignment for a static
1400 variable. TYPE is the data type, and ALIGN is the alignment that
1401 the object would ordinarily have. The value of this macro is used
1402 instead of that alignment to align the object.
1404 If this macro is not defined, then ALIGN is used.
1406 One use of this macro is to increase alignment of medium-size
1407 data to make it all fit in fewer cache lines. Another is to
1408 cause character arrays to be word-aligned so that `strcpy' calls
1409 that copy constants to character arrays can be done inline. */
1411 #undef DATA_ALIGNMENT
1412 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1413 ((((ALIGN) < BITS_PER_WORD) \
1414 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1415 || TREE_CODE (TYPE) == UNION_TYPE \
1416 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1419 #define PAD_VARARGS_DOWN \
1420 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1422 /* Define if operations between registers always perform the operation
1423 on the full register even if a narrower mode is specified. */
1424 #define WORD_REGISTER_OPERATIONS
1426 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1427 moves. All other references are zero extended. */
1428 #define LOAD_EXTEND_OP(MODE) \
1429 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1430 ? SIGN_EXTEND : ZERO_EXTEND)
1432 /* Define this macro if it is advisable to hold scalars in registers
1433 in a wider mode than that declared by the program. In such cases,
1434 the value is constrained to be within the bounds of the declared
1435 type, but kept valid in the wider mode. The signedness of the
1436 extension may differ from that of the type. */
1438 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1439 if (GET_MODE_CLASS (MODE) == MODE_INT \
1440 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1442 if ((MODE) == SImode) \
1447 /* Define if loading short immediate values into registers sign extends. */
1448 #define SHORT_IMMEDIATES_SIGN_EXTEND
1450 /* Standard register usage. */
1452 /* Number of hardware registers. We have:
1454 - 32 integer registers
1455 - 32 floating point registers
1456 - 8 condition code registers
1457 - 2 accumulator registers (hi and lo)
1458 - 32 registers each for coprocessors 0, 2 and 3
1460 - ARG_POINTER_REGNUM
1461 - FRAME_POINTER_REGNUM
1462 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1463 - 3 dummy entries that were used at various times in the past. */
1465 #define FIRST_PSEUDO_REGISTER 176
1467 /* By default, fix the kernel registers ($26 and $27), the global
1468 pointer ($28) and the stack pointer ($29). This can change
1469 depending on the command-line options.
1471 Regarding coprocessor registers: without evidence to the contrary,
1472 it's best to assume that each coprocessor register has a unique
1473 use. This can be overridden, in, e.g., override_options() or
1474 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1475 for a particular target. */
1477 #define FIXED_REGISTERS \
1479 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1480 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1481 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1482 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1483 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1484 /* COP0 registers */ \
1485 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1487 /* COP2 registers */ \
1488 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1489 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1490 /* COP3 registers */ \
1491 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1492 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1496 /* Set up this array for o32 by default.
1498 Note that we don't mark $31 as a call-clobbered register. The idea is
1499 that it's really the call instructions themselves which clobber $31.
1500 We don't care what the called function does with it afterwards.
1502 This approach makes it easier to implement sibcalls. Unlike normal
1503 calls, sibcalls don't clobber $31, so the register reaches the
1504 called function in tact. EPILOGUE_USES says that $31 is useful
1505 to the called function. */
1507 #define CALL_USED_REGISTERS \
1509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1512 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1514 /* COP0 registers */ \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1517 /* COP2 registers */ \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1520 /* COP3 registers */ \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1526 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1528 #define CALL_REALLY_USED_REGISTERS \
1529 { /* General registers. */ \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1532 /* Floating-point registers. */ \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 /* COP0 registers */ \
1538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1540 /* COP2 registers */ \
1541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1543 /* COP3 registers */ \
1544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1548 /* Internal macros to classify a register number as to whether it's a
1549 general purpose register, a floating point register, a
1550 multiply/divide register, or a status register. */
1552 #define GP_REG_FIRST 0
1553 #define GP_REG_LAST 31
1554 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1555 #define GP_DBX_FIRST 0
1557 #define FP_REG_FIRST 32
1558 #define FP_REG_LAST 63
1559 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1560 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1562 #define MD_REG_FIRST 64
1563 #define MD_REG_LAST 65
1564 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1565 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1567 #define ST_REG_FIRST 67
1568 #define ST_REG_LAST 74
1569 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1572 /* FIXME: renumber. */
1573 #define COP0_REG_FIRST 80
1574 #define COP0_REG_LAST 111
1575 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1577 #define COP2_REG_FIRST 112
1578 #define COP2_REG_LAST 143
1579 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1581 #define COP3_REG_FIRST 144
1582 #define COP3_REG_LAST 175
1583 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1584 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1585 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1587 #define AT_REGNUM (GP_REG_FIRST + 1)
1588 #define HI_REGNUM (MD_REG_FIRST + 0)
1589 #define LO_REGNUM (MD_REG_FIRST + 1)
1591 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1592 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1593 should be used instead. */
1594 #define FPSW_REGNUM ST_REG_FIRST
1596 #define GP_REG_P(REGNO) \
1597 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1598 #define M16_REG_P(REGNO) \
1599 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1600 #define FP_REG_P(REGNO) \
1601 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1602 #define MD_REG_P(REGNO) \
1603 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1604 #define ST_REG_P(REGNO) \
1605 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1606 #define COP0_REG_P(REGNO) \
1607 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1608 #define COP2_REG_P(REGNO) \
1609 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1610 #define COP3_REG_P(REGNO) \
1611 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1612 #define ALL_COP_REG_P(REGNO) \
1613 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1615 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1617 /* Return coprocessor number from register number. */
1619 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1620 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1621 : COP3_REG_P (REGNO) ? '3' : '?')
1624 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1626 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1627 array built in override_options. Because machmodes.h is not yet
1628 included before this file is processed, the MODE bound can't be
1631 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1633 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1634 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1636 /* Value is 1 if it is a good idea to tie two pseudo registers
1637 when one has mode MODE1 and one has mode MODE2.
1638 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1639 for any hard reg, then this must be 0 for correct output. */
1640 #define MODES_TIEABLE_P(MODE1, MODE2) \
1641 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1642 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1643 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1644 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1646 /* Register to use for pushing function arguments. */
1647 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1649 /* These two registers don't really exist: they get eliminated to either
1650 the stack or hard frame pointer. */
1651 #define ARG_POINTER_REGNUM 77
1652 #define FRAME_POINTER_REGNUM 78
1654 /* $30 is not available on the mips16, so we use $17 as the frame
1656 #define HARD_FRAME_POINTER_REGNUM \
1657 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1659 /* Value should be nonzero if functions must have frame pointers.
1660 Zero means the frame pointer need not be set up (and parms
1661 may be accessed via the stack pointer) in functions that seem suitable.
1662 This is computed in `reload', in reload1.c. */
1663 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1665 /* Register in which static-chain is passed to a function. */
1666 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1668 /* Registers used as temporaries in prologue/epilogue code. If we're
1669 generating mips16 code, these registers must come from the core set
1670 of 8. The prologue register mustn't conflict with any incoming
1671 arguments, the static chain pointer, or the frame pointer. The
1672 epilogue temporary mustn't conflict with the return registers, the
1673 frame pointer, the EH stack adjustment, or the EH data registers. */
1675 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1676 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1678 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1679 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1681 /* Define this macro if it is as good or better to call a constant
1682 function address than to call an address kept in a register. */
1683 #define NO_FUNCTION_CSE 1
1685 /* Define this macro if it is as good or better for a function to
1686 call itself with an explicit address than to call an address
1687 kept in a register. */
1688 #define NO_RECURSIVE_FUNCTION_CSE 1
1690 /* The ABI-defined global pointer. Sometimes we use a different
1691 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1692 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1694 /* We normally use $28 as the global pointer. However, when generating
1695 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1696 register instead. They can then avoid saving and restoring $28
1697 and perhaps avoid using a frame at all.
1699 When a leaf function uses something other than $28, mips_expand_prologue
1700 will modify pic_offset_table_rtx in place. Take the register number
1701 from there after reload. */
1702 #define PIC_OFFSET_TABLE_REGNUM \
1703 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1705 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1707 /* Define the classes of registers for register constraints in the
1708 machine description. Also define ranges of constants.
1710 One of the classes must always be named ALL_REGS and include all hard regs.
1711 If there is more than one class, another class must be named NO_REGS
1712 and contain no registers.
1714 The name GENERAL_REGS must be the name of a class (or an alias for
1715 another name such as ALL_REGS). This is the class of registers
1716 that is allowed by "g" or "r" in a register constraint.
1717 Also, registers outside this class are allocated only when
1718 instructions express preferences for them.
1720 The classes must be numbered in nondecreasing order; that is,
1721 a larger-numbered class must never be contained completely
1722 in a smaller-numbered class.
1724 For any two classes, it is very desirable that there be another
1725 class that represents their union. */
1729 NO_REGS, /* no registers in set */
1730 M16_NA_REGS, /* mips16 regs not used to pass args */
1731 M16_REGS, /* mips16 directly accessible registers */
1732 T_REG, /* mips16 T register ($24) */
1733 M16_T_REGS, /* mips16 registers plus T register */
1734 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1735 LEA_REGS, /* Every GPR except $25 */
1736 GR_REGS, /* integer registers */
1737 FP_REGS, /* floating point registers */
1738 HI_REG, /* hi register */
1739 LO_REG, /* lo register */
1740 MD_REGS, /* multiply/divide registers (hi/lo) */
1741 COP0_REGS, /* generic coprocessor classes */
1744 HI_AND_GR_REGS, /* union classes */
1751 ALL_COP_AND_GR_REGS,
1752 ST_REGS, /* status registers (fp status) */
1753 ALL_REGS, /* all registers */
1754 LIM_REG_CLASSES /* max value + 1 */
1757 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1759 #define GENERAL_REGS GR_REGS
1761 /* An initializer containing the names of the register classes as C
1762 string constants. These names are used in writing some of the
1765 #define REG_CLASS_NAMES \
1772 "PIC_FN_ADDR_REG", \
1779 /* coprocessor registers */ \
1786 "COP0_AND_GR_REGS", \
1787 "COP2_AND_GR_REGS", \
1788 "COP3_AND_GR_REGS", \
1790 "ALL_COP_AND_GR_REGS", \
1795 /* An initializer containing the contents of the register classes,
1796 as integers which are bit masks. The Nth integer specifies the
1797 contents of class N. The way the integer MASK is interpreted is
1798 that register R is in the class if `MASK & (1 << R)' is 1.
1800 When the machine has more than 32 registers, an integer does not
1801 suffice. Then the integers are replaced by sub-initializers,
1802 braced groupings containing several integers. Each
1803 sub-initializer must be suitable as an initializer for the type
1804 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1806 #define REG_CLASS_CONTENTS \
1808 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1809 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1810 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1811 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1812 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1813 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1814 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1815 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1816 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1817 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1818 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1819 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1820 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1821 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1822 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1823 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1824 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1825 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1826 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1827 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1828 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1829 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1830 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1831 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1832 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1836 /* A C expression whose value is a register class containing hard
1837 register REGNO. In general there is more that one such class;
1838 choose a class which is "minimal", meaning that no smaller class
1839 also contains the register. */
1841 extern const enum reg_class mips_regno_to_class[];
1843 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1845 /* A macro whose definition is the name of the class to which a
1846 valid base register must belong. A base register is one used in
1847 an address which is the register value plus a displacement. */
1849 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1851 /* A macro whose definition is the name of the class to which a
1852 valid index register must belong. An index register is one used
1853 in an address where its value is either multiplied by a scale
1854 factor or added to another register (as well as added to a
1857 #define INDEX_REG_CLASS NO_REGS
1859 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1860 registers explicitly used in the rtl to be used as spill registers
1861 but prevents the compiler from extending the lifetime of these
1864 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1866 /* This macro is used later on in the file. */
1867 #define GR_REG_CLASS_P(CLASS) \
1868 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1869 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1870 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1872 /* This macro is also used later on in the file. */
1873 #define COP_REG_CLASS_P(CLASS) \
1874 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1876 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1877 is the default value (allocate the registers in numeric order). We
1878 define it just so that we can override it for the mips16 target in
1879 ORDER_REGS_FOR_LOCAL_ALLOC. */
1881 #define REG_ALLOC_ORDER \
1882 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1883 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1884 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1885 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1886 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1887 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1888 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1889 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1890 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1891 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1892 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1895 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1896 to be rearranged based on a particular function. On the mips16, we
1897 want to allocate $24 (T_REG) before other registers for
1898 instructions for which it is possible. */
1900 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1902 /* REGISTER AND CONSTANT CLASSES */
1904 /* Get reg_class from a letter such as appears in the machine
1907 DEFINED REGISTER CLASSES:
1909 'd' General (aka integer) registers
1910 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1911 'y' General registers (in both mips16 and non mips16 mode)
1912 'e' Effective address registers (general registers except $25)
1913 't' mips16 temporary register ($24)
1914 'f' Floating point registers
1917 'x' Multiply/divide registers
1918 'z' FP Status register
1922 'b' All registers */
1924 extern enum reg_class mips_char_to_class[256];
1926 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1928 /* True if VALUE is a signed 16-bit number. */
1930 #define SMALL_OPERAND(VALUE) \
1931 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1933 /* True if VALUE is an unsigned 16-bit number. */
1935 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1936 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1938 /* True if VALUE can be loaded into a register using LUI. */
1940 #define LUI_OPERAND(VALUE) \
1941 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1942 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1944 /* Return a value X with the low 16 bits clear, and such that
1945 VALUE - X is a signed 16-bit value. */
1947 #define CONST_HIGH_PART(VALUE) \
1948 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1950 #define CONST_LOW_PART(VALUE) \
1951 ((VALUE) - CONST_HIGH_PART (VALUE))
1953 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1954 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1955 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1957 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1958 string can be used to stand for particular ranges of immediate
1959 operands. This macro defines what the ranges are. C is the
1960 letter, and VALUE is a constant value. Return 1 if VALUE is
1961 in the range specified by C. */
1965 `I' is used for the range of constants an arithmetic insn can
1966 actually contain (16 bits signed integers).
1968 `J' is used for the range which is just zero (ie, $r0).
1970 `K' is used for the range of constants a logical insn can actually
1971 contain (16 bit zero-extended integers).
1973 `L' is used for the range of constants that be loaded with lui
1974 (ie, the bottom 16 bits are zero).
1976 `M' is used for the range of constants that take two words to load
1977 (ie, not matched by `I', `K', and `L').
1979 `N' is used for negative 16 bit constants other than -65536.
1981 `O' is a 15 bit signed integer.
1983 `P' is used for positive 16 bit constants. */
1985 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1986 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1987 : (C) == 'J' ? ((VALUE) == 0) \
1988 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1989 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1990 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1991 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1992 && !LUI_OPERAND (VALUE)) \
1993 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1994 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1995 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1998 /* Similar, but for floating constants, and defining letters G and H.
1999 Here VALUE is the CONST_DOUBLE rtx itself. */
2003 'G' : Floating point 0 */
2005 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2007 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2009 /* Letters in the range `Q' through `U' may be defined in a
2010 machine-dependent fashion to stand for arbitrary operand types.
2011 The machine description macro `EXTRA_CONSTRAINT' is passed the
2012 operand as its first argument and the constraint letter as its
2015 `Q' is for signed 16-bit constants.
2016 `R' is for single-instruction memory references. Note that this
2017 constraint has often been used in linux and glibc code.
2018 `S' is for legitimate constant call addresses.
2019 `T' is for constant move_operands that cannot be safely loaded into $25.
2020 `U' is for constant move_operands that can be safely loaded into $25.
2021 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2022 This is true for all non-mips16 references (although it can somtimes
2023 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2024 stack and constant-pool references. */
2026 #define EXTRA_CONSTRAINT(OP,CODE) \
2027 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2028 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2029 && mips_fetch_insns (OP) == 1) \
2030 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2031 && call_insn_operand (OP, VOIDmode)) \
2032 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2033 && move_operand (OP, VOIDmode) \
2034 && mips_dangerous_for_la25_p (OP)) \
2035 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2036 && move_operand (OP, VOIDmode) \
2037 && !mips_dangerous_for_la25_p (OP)) \
2038 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2039 && memory_operand (OP, VOIDmode) \
2040 && (!TARGET_MIPS16 \
2041 || (!stack_operand (OP, VOIDmode) \
2042 && !CONSTANT_P (XEXP (OP, 0))))) \
2045 /* Say which of the above are memory constraints. */
2046 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2048 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2049 mips_preferred_reload_class (X, CLASS)
2051 /* Certain machines have the property that some registers cannot be
2052 copied to some other registers without using memory. Define this
2053 macro on those machines to be a C expression that is nonzero if
2054 objects of mode MODE in registers of CLASS1 can only be copied to
2055 registers of class CLASS2 by storing a register of CLASS1 into
2056 memory and loading that memory location into a register of CLASS2.
2058 Do not define this macro if its value would always be zero. */
2060 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2061 ((!TARGET_DEBUG_H_MODE \
2062 && GET_MODE_CLASS (MODE) == MODE_INT \
2063 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2064 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2065 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2066 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2067 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2069 /* The HI and LO registers can only be reloaded via the general
2070 registers. Condition code registers can only be loaded to the
2071 general registers, and from the floating point registers. */
2073 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2074 mips_secondary_reload_class (CLASS, MODE, X, 1)
2075 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2076 mips_secondary_reload_class (CLASS, MODE, X, 0)
2078 /* Return the maximum number of consecutive registers
2079 needed to represent mode MODE in a register of class CLASS. */
2081 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2083 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2084 mips_cannot_change_mode_class (FROM, TO, CLASS)
2086 /* Stack layout; function entry, exit and calling. */
2088 #define STACK_GROWS_DOWNWARD
2090 /* The offset of the first local variable from the beginning of the frame.
2091 See compute_frame_size for details about the frame layout. */
2092 #define STARTING_FRAME_OFFSET \
2093 (current_function_outgoing_args_size \
2094 + (TARGET_ABICALLS && !TARGET_NEWABI \
2095 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2097 #define RETURN_ADDR_RTX mips_return_addr
2099 /* Since the mips16 ISA mode is encoded in the least-significant bit
2100 of the address, mask it off return addresses for purposes of
2101 finding exception handling regions. */
2103 #define MASK_RETURN_ADDR GEN_INT (-2)
2106 /* Similarly, don't use the least-significant bit to tell pointers to
2107 code from vtable index. */
2109 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2111 /* The eliminations to $17 are only used for mips16 code. See the
2112 definition of HARD_FRAME_POINTER_REGNUM. */
2114 #define ELIMINABLE_REGS \
2115 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2116 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2117 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2118 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2119 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2120 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2122 /* We can always eliminate to the hard frame pointer. We can eliminate
2123 to the stack pointer unless a frame pointer is needed.
2125 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2126 reload may be unable to compute the address of a local variable,
2127 since there is no way to add a large constant to the stack pointer
2128 without using a temporary register. */
2129 #define CAN_ELIMINATE(FROM, TO) \
2130 ((TO) == HARD_FRAME_POINTER_REGNUM \
2131 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2132 && (!TARGET_MIPS16 \
2133 || compute_frame_size (get_frame_size ()) < 32768)))
2135 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2136 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2138 /* Allocate stack space for arguments at the beginning of each function. */
2139 #define ACCUMULATE_OUTGOING_ARGS 1
2141 /* The argument pointer always points to the first argument. */
2142 #define FIRST_PARM_OFFSET(FNDECL) 0
2144 /* o32 and o64 reserve stack space for all argument registers. */
2145 #define REG_PARM_STACK_SPACE(FNDECL) \
2147 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2150 /* Define this if it is the responsibility of the caller to
2151 allocate the area reserved for arguments passed in registers.
2152 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2153 of this macro is to determine whether the space is included in
2154 `current_function_outgoing_args_size'. */
2155 #define OUTGOING_REG_PARM_STACK_SPACE
2157 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2159 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2161 /* Symbolic macros for the registers used to return integer and floating
2164 #define GP_RETURN (GP_REG_FIRST + 2)
2165 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2167 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2169 /* Symbolic macros for the first/last argument registers. */
2171 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2172 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2173 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2174 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2176 #define LIBCALL_VALUE(MODE) \
2177 mips_function_value (NULL_TREE, NULL, (MODE))
2179 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2180 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2182 /* 1 if N is a possible register number for a function value.
2183 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2184 Currently, R2 and F0 are only implemented here (C has no complex type) */
2186 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2187 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2188 && (N) == FP_RETURN + 2))
2190 /* 1 if N is a possible register number for function argument passing.
2191 We have no FP argument registers when soft-float. When FP registers
2192 are 32 bits, we can't directly reference the odd numbered ones. */
2194 #define FUNCTION_ARG_REGNO_P(N) \
2195 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2196 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2197 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2200 /* This structure has to cope with two different argument allocation
2201 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2202 first N words go in registers and the rest go on the stack. If I < N,
2203 the Ith word might go in Ith integer argument register or the
2204 Ith floating-point one. For these ABIs, we only need to remember
2205 the number of words passed so far.
2207 The EABI instead allocates the integer and floating-point arguments
2208 separately. The first N words of FP arguments go in FP registers,
2209 the rest go on the stack. Likewise, the first N words of the other
2210 arguments go in integer registers, and the rest go on the stack. We
2211 need to maintain three counts: the number of integer registers used,
2212 the number of floating-point registers used, and the number of words
2213 passed on the stack.
2215 We could keep separate information for the two ABIs (a word count for
2216 the standard ABIs, and three separate counts for the EABI). But it
2217 seems simpler to view the standard ABIs as forms of EABI that do not
2218 allocate floating-point registers.
2220 So for the standard ABIs, the first N words are allocated to integer
2221 registers, and function_arg decides on an argument-by-argument basis
2222 whether that argument should really go in an integer register, or in
2223 a floating-point one. */
2225 typedef struct mips_args {
2226 /* Always true for varargs functions. Otherwise true if at least
2227 one argument has been passed in an integer register. */
2230 /* The number of arguments seen so far. */
2231 unsigned int arg_number;
2233 /* For EABI, the number of integer registers used so far. For other
2234 ABIs, the number of words passed in registers (whether integer
2235 or floating-point). */
2236 unsigned int num_gprs;
2238 /* For EABI, the number of floating-point registers used so far. */
2239 unsigned int num_fprs;
2241 /* The number of words passed on the stack. */
2242 unsigned int stack_words;
2244 /* On the mips16, we need to keep track of which floating point
2245 arguments were passed in general registers, but would have been
2246 passed in the FP regs if this were a 32 bit function, so that we
2247 can move them to the FP regs if we wind up calling a 32 bit
2248 function. We record this information in fp_code, encoded in base
2249 four. A zero digit means no floating point argument, a one digit
2250 means an SFmode argument, and a two digit means a DFmode argument,
2251 and a three digit is not used. The low order digit is the first
2252 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2253 an SFmode argument. ??? A more sophisticated approach will be
2254 needed if MIPS_ABI != ABI_32. */
2257 /* True if the function has a prototype. */
2261 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2262 for a call to a function whose data type is FNTYPE.
2263 For a library call, FNTYPE is 0. */
2265 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2266 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2268 /* Update the data in CUM to advance over an argument
2269 of mode MODE and data type TYPE.
2270 (TYPE is null for libcalls where that information may not be available.) */
2272 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2273 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2275 /* Determine where to put an argument to a function.
2276 Value is zero to push the argument on the stack,
2277 or a hard register in which to store the argument.
2279 MODE is the argument's machine mode.
2280 TYPE is the data type of the argument (as a tree).
2281 This is null for libcalls where that information may
2283 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2284 the preceding args and about the function being called.
2285 NAMED is nonzero if this argument is a named parameter
2286 (otherwise it is an extra parameter matching an ellipsis). */
2288 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2289 function_arg( &CUM, MODE, TYPE, NAMED)
2291 /* For an arg passed partly in registers and partly in memory,
2292 this is the number of registers used.
2293 For args passed entirely in registers or entirely in memory, zero. */
2295 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2296 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2298 /* If defined, a C expression that gives the alignment boundary, in
2299 bits, of an argument with the specified mode and type. If it is
2300 not defined, `PARM_BOUNDARY' is used for all arguments. */
2302 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2304 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2306 : TYPE_ALIGN(TYPE)) \
2307 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2309 : GET_MODE_ALIGNMENT(MODE)))
2311 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2312 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2314 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2315 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2317 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2318 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2320 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2321 (mips_abi == ABI_EABI && (NAMED) \
2322 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2324 /* Modified version of the macro in expr.h. Only return true if
2325 the type has a variable size or if the front end requires it
2326 to be passed by reference. */
2327 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2329 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2330 || TREE_ADDRESSABLE (TYPE)))
2332 /* True if using EABI and varargs can be passed in floating-point
2333 registers. Under these conditions, we need a more complex form
2334 of va_list, which tracks GPR, FPR and stack arguments separately. */
2335 #define EABI_FLOAT_VARARGS_P \
2336 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2339 /* Say that the epilogue uses the return address register. Note that
2340 in the case of sibcalls, the values "used by the epilogue" are
2341 considered live at the start of the called function. */
2342 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2344 /* Treat LOC as a byte offset from the stack pointer and round it up
2345 to the next fully-aligned offset. */
2346 #define MIPS_STACK_ALIGN(LOC) \
2347 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2348 ? ((LOC) + 7) & ~7 \
2349 : ((LOC) + 15) & ~15)
2352 /* Implement `va_start' for varargs and stdarg. */
2353 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2354 mips_va_start (valist, nextarg)
2356 /* Implement `va_arg'. */
2357 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2358 mips_va_arg (valist, type)
2360 /* Output assembler code to FILE to increment profiler label # LABELNO
2361 for profiling a function entry. */
2363 #define FUNCTION_PROFILER(FILE, LABELNO) \
2365 if (TARGET_MIPS16) \
2366 sorry ("mips16 function profiling"); \
2367 fprintf (FILE, "\t.set\tnoat\n"); \
2368 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2369 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2370 if (!TARGET_NEWABI) \
2373 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2374 TARGET_64BIT ? "dsubu" : "subu", \
2375 reg_names[STACK_POINTER_REGNUM], \
2376 reg_names[STACK_POINTER_REGNUM], \
2377 Pmode == DImode ? 16 : 8); \
2379 fprintf (FILE, "\tjal\t_mcount\n"); \
2380 fprintf (FILE, "\t.set\tat\n"); \
2383 /* Define this macro if the code for function profiling should come
2384 before the function prologue. Normally, the profiling code comes
2387 /* #define PROFILE_BEFORE_PROLOGUE */
2389 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2390 the stack pointer does not matter. The value is tested only in
2391 functions that have frame pointers.
2392 No definition is equivalent to always zero. */
2394 #define EXIT_IGNORE_STACK 1
2397 /* A C statement to output, on the stream FILE, assembler code for a
2398 block of data that contains the constant parts of a trampoline.
2399 This code should not include a label--the label is taken care of
2402 #define TRAMPOLINE_TEMPLATE(STREAM) \
2404 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2405 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2406 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2407 if (ptr_mode == DImode) \
2409 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2410 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2414 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2415 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2417 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2418 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2419 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2420 if (ptr_mode == DImode) \
2422 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2423 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2427 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2428 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2432 /* A C expression for the size in bytes of the trampoline, as an
2435 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2437 /* Alignment required for trampolines, in bits. */
2439 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2441 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2442 program and data caches. */
2444 #ifndef CACHE_FLUSH_FUNC
2445 #define CACHE_FLUSH_FUNC "_flush_cache"
2448 /* A C statement to initialize the variable parts of a trampoline.
2449 ADDR is an RTX for the address of the trampoline; FNADDR is an
2450 RTX for the address of the nested function; STATIC_CHAIN is an
2451 RTX for the static chain value that should be passed to the
2452 function when it is called. */
2454 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2456 rtx func_addr, chain_addr; \
2458 func_addr = plus_constant (ADDR, 32); \
2459 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2460 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2461 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2463 /* Flush both caches. We need to flush the data cache in case \
2464 the system has a write-back cache. */ \
2465 /* ??? Should check the return value for errors. */ \
2466 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2467 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2468 0, VOIDmode, 3, ADDR, Pmode, \
2469 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2470 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2473 /* Addressing modes, and classification of registers for them. */
2475 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2476 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2477 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2479 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2480 and check its validity for a certain class.
2481 We have two alternate definitions for each of them.
2482 The usual definition accepts all pseudo regs; the other rejects them all.
2483 The symbol REG_OK_STRICT causes the latter definition to be used.
2485 Most source files want to accept pseudo regs in the hope that
2486 they will get allocated to the class that the insn wants them to be in.
2487 Some source files that are used after register allocation
2488 need to be strict. */
2490 #ifndef REG_OK_STRICT
2491 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2492 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2494 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2495 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2498 #define REG_OK_FOR_INDEX_P(X) 0
2501 /* Maximum number of registers that can appear in a valid memory address. */
2503 #define MAX_REGS_PER_ADDRESS 1
2505 #ifdef REG_OK_STRICT
2506 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2508 if (mips_legitimate_address_p (MODE, X, 1)) \
2512 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2514 if (mips_legitimate_address_p (MODE, X, 0)) \
2519 /* Check for constness inline but use mips_legitimate_address_p
2520 to check whether a constant really is an address. */
2522 #define CONSTANT_ADDRESS_P(X) \
2523 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2525 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2527 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2529 if (mips_legitimize_address (&(X), MODE)) \
2534 /* A C statement or compound statement with a conditional `goto
2535 LABEL;' executed if memory address X (an RTX) can have different
2536 meanings depending on the machine mode of the memory reference it
2539 Autoincrement and autodecrement addresses typically have
2540 mode-dependent effects because the amount of the increment or
2541 decrement is the size of the operand being addressed. Some
2542 machines have other mode-dependent addresses. Many RISC machines
2543 have no mode-dependent addresses.
2545 You may assume that ADDR is a valid address for the machine. */
2547 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2549 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2550 'the start of the function that this code is output in'. */
2552 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2553 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2554 asm_fprintf ((FILE), "%U%s", \
2555 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2557 asm_fprintf ((FILE), "%U%s", (NAME))
2559 /* The mips16 wants the constant pool to be after the function,
2560 because the PC relative load instructions use unsigned offsets. */
2562 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2564 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2565 mips_string_length = 0;
2567 /* Specify the machine mode that this machine uses
2568 for the index in the tablejump instruction.
2569 ??? Using HImode in mips16 mode can cause overflow. */
2570 #define CASE_VECTOR_MODE \
2571 (TARGET_MIPS16 ? HImode : ptr_mode)
2573 /* Define as C expression which evaluates to nonzero if the tablejump
2574 instruction expects the table to contain offsets from the address of the
2576 Do not define this if the table should contain absolute addresses. */
2577 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2579 /* Define this as 1 if `char' should by default be signed; else as 0. */
2580 #ifndef DEFAULT_SIGNED_CHAR
2581 #define DEFAULT_SIGNED_CHAR 1
2584 /* Max number of bytes we can move from memory to memory
2585 in one reasonably fast instruction. */
2586 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2587 #define MAX_MOVE_MAX 8
2589 /* Define this macro as a C expression which is nonzero if
2590 accessing less than a word of memory (i.e. a `char' or a
2591 `short') is no faster than accessing a word of memory, i.e., if
2592 such access require more than one instruction or if there is no
2593 difference in cost between byte and (aligned) word loads.
2595 On RISC machines, it tends to generate better code to define
2596 this as 1, since it avoids making a QI or HI mode register. */
2597 #define SLOW_BYTE_ACCESS 1
2599 /* Define this to be nonzero if shift instructions ignore all but the low-order
2601 #define SHIFT_COUNT_TRUNCATED 1
2603 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2604 is done just by pretending it is already truncated. */
2605 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2606 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2609 /* Specify the machine mode that pointers have.
2610 After generation of rtl, the compiler makes no further distinction
2611 between pointers and any other objects of this machine mode. */
2614 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2617 /* Give call MEMs SImode since it is the "most permissive" mode
2618 for both 32-bit and 64-bit targets. */
2620 #define FUNCTION_MODE SImode
2623 /* The cost of loading values from the constant pool. It should be
2624 larger than the cost of any constant we want to synthesize in-line. */
2626 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2628 /* A C expression for the cost of moving data from a register in
2629 class FROM to one in class TO. The classes are expressed using
2630 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2631 the default; other values are interpreted relative to that.
2633 It is not required that the cost always equal 2 when FROM is the
2634 same as TO; on some machines it is expensive to move between
2635 registers if they are not general registers.
2637 If reload sees an insn consisting of a single `set' between two
2638 hard registers, and if `REGISTER_MOVE_COST' applied to their
2639 classes returns a value of 2, reload does not check to ensure
2640 that the constraints of the insn are met. Setting a cost of
2641 other than 2 will allow reload to verify that the constraints are
2642 met. You should do this if the `movM' pattern's constraints do
2643 not allow such copying. */
2645 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2646 mips_register_move_cost (MODE, FROM, TO)
2648 /* ??? Fix this to be right for the R8000. */
2649 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2650 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2651 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2653 /* Define if copies to/from condition code registers should be avoided.
2655 This is needed for the MIPS because reload_outcc is not complete;
2656 it needs to handle cases where the source is a general or another
2657 condition code register. */
2658 #define AVOID_CCMODE_COPIES
2660 /* A C expression for the cost of a branch instruction. A value of
2661 1 is the default; other values are interpreted relative to that. */
2663 /* ??? Fix this to be right for the R8000. */
2664 #define BRANCH_COST \
2666 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2669 /* If defined, modifies the length assigned to instruction INSN as a
2670 function of the context in which it is used. LENGTH is an lvalue
2671 that contains the initially computed length of the insn and should
2672 be updated with the correct length of the insn. */
2673 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2674 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2677 /* Optionally define this if you have added predicates to
2678 `MACHINE.c'. This macro is called within an initializer of an
2679 array of structures. The first field in the structure is the
2680 name of a predicate and the second field is an array of rtl
2681 codes. For each predicate, list all rtl codes that can be in
2682 expressions matched by the predicate. The list should have a
2683 trailing comma. Here is an example of two entries in the list
2684 for a typical RISC machine:
2686 #define PREDICATE_CODES \
2687 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2688 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2690 Defining this macro does not affect the generated code (however,
2691 incorrect definitions that omit an rtl code that may be matched
2692 by the predicate can cause the compiler to malfunction).
2693 Instead, it allows the table built by `genrecog' to be more
2694 compact and efficient, thus speeding up the compiler. The most
2695 important predicates to include in the list specified by this
2696 macro are thoses used in the most insn patterns. */
2698 #define PREDICATE_CODES \
2699 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2700 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2701 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2702 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2703 {"const_arith_operand", { CONST_INT }}, \
2704 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2705 UNSPEC_VOLATILE }}, \
2706 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2707 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2708 {"small_int", { CONST_INT }}, \
2709 {"const_float_1_operand", { CONST_DOUBLE }}, \
2710 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2711 {"equality_op", { EQ, NE }}, \
2712 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2714 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2715 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2716 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2717 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2718 SYMBOL_REF, LABEL_REF, SUBREG, \
2720 {"stack_operand", { MEM }}, \
2721 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2722 CONST_DOUBLE, CONST }}, \
2723 {"fcc_register_operand", { REG, SUBREG }}, \
2724 {"hilo_operand", { REG }}, \
2725 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2727 /* A list of predicates that do special things with modes, and so
2728 should not elicit warnings for VOIDmode match_operand. */
2730 #define SPECIAL_MODE_PREDICATES \
2731 "pc_or_label_operand",
2733 /* Control the assembler format that we output. */
2735 /* Output to assembler file text saying following lines
2736 may contain character constants, extra white space, comments, etc. */
2739 #define ASM_APP_ON " #APP\n"
2742 /* Output to assembler file text saying following lines
2743 no longer contain unusual constructs. */
2746 #define ASM_APP_OFF " #NO_APP\n"
2749 /* How to refer to registers in assembler output.
2750 This sequence is indexed by compiler's hard-register-number (see above).
2752 In order to support the two different conventions for register names,
2753 we use the name of a table set up in mips.c, which is overwritten
2754 if -mrnames is used. */
2756 #define REGISTER_NAMES \
2758 &mips_reg_names[ 0][0], \
2759 &mips_reg_names[ 1][0], \
2760 &mips_reg_names[ 2][0], \
2761 &mips_reg_names[ 3][0], \
2762 &mips_reg_names[ 4][0], \
2763 &mips_reg_names[ 5][0], \
2764 &mips_reg_names[ 6][0], \
2765 &mips_reg_names[ 7][0], \
2766 &mips_reg_names[ 8][0], \
2767 &mips_reg_names[ 9][0], \
2768 &mips_reg_names[10][0], \
2769 &mips_reg_names[11][0], \
2770 &mips_reg_names[12][0], \
2771 &mips_reg_names[13][0], \
2772 &mips_reg_names[14][0], \
2773 &mips_reg_names[15][0], \
2774 &mips_reg_names[16][0], \
2775 &mips_reg_names[17][0], \
2776 &mips_reg_names[18][0], \
2777 &mips_reg_names[19][0], \
2778 &mips_reg_names[20][0], \
2779 &mips_reg_names[21][0], \
2780 &mips_reg_names[22][0], \
2781 &mips_reg_names[23][0], \
2782 &mips_reg_names[24][0], \
2783 &mips_reg_names[25][0], \
2784 &mips_reg_names[26][0], \
2785 &mips_reg_names[27][0], \
2786 &mips_reg_names[28][0], \
2787 &mips_reg_names[29][0], \
2788 &mips_reg_names[30][0], \
2789 &mips_reg_names[31][0], \
2790 &mips_reg_names[32][0], \
2791 &mips_reg_names[33][0], \
2792 &mips_reg_names[34][0], \
2793 &mips_reg_names[35][0], \
2794 &mips_reg_names[36][0], \
2795 &mips_reg_names[37][0], \
2796 &mips_reg_names[38][0], \
2797 &mips_reg_names[39][0], \
2798 &mips_reg_names[40][0], \
2799 &mips_reg_names[41][0], \
2800 &mips_reg_names[42][0], \
2801 &mips_reg_names[43][0], \
2802 &mips_reg_names[44][0], \
2803 &mips_reg_names[45][0], \
2804 &mips_reg_names[46][0], \
2805 &mips_reg_names[47][0], \
2806 &mips_reg_names[48][0], \
2807 &mips_reg_names[49][0], \
2808 &mips_reg_names[50][0], \
2809 &mips_reg_names[51][0], \
2810 &mips_reg_names[52][0], \
2811 &mips_reg_names[53][0], \
2812 &mips_reg_names[54][0], \
2813 &mips_reg_names[55][0], \
2814 &mips_reg_names[56][0], \
2815 &mips_reg_names[57][0], \
2816 &mips_reg_names[58][0], \
2817 &mips_reg_names[59][0], \
2818 &mips_reg_names[60][0], \
2819 &mips_reg_names[61][0], \
2820 &mips_reg_names[62][0], \
2821 &mips_reg_names[63][0], \
2822 &mips_reg_names[64][0], \
2823 &mips_reg_names[65][0], \
2824 &mips_reg_names[66][0], \
2825 &mips_reg_names[67][0], \
2826 &mips_reg_names[68][0], \
2827 &mips_reg_names[69][0], \
2828 &mips_reg_names[70][0], \
2829 &mips_reg_names[71][0], \
2830 &mips_reg_names[72][0], \
2831 &mips_reg_names[73][0], \
2832 &mips_reg_names[74][0], \
2833 &mips_reg_names[75][0], \
2834 &mips_reg_names[76][0], \
2835 &mips_reg_names[77][0], \
2836 &mips_reg_names[78][0], \
2837 &mips_reg_names[79][0], \
2838 &mips_reg_names[80][0], \
2839 &mips_reg_names[81][0], \
2840 &mips_reg_names[82][0], \
2841 &mips_reg_names[83][0], \
2842 &mips_reg_names[84][0], \
2843 &mips_reg_names[85][0], \
2844 &mips_reg_names[86][0], \
2845 &mips_reg_names[87][0], \
2846 &mips_reg_names[88][0], \
2847 &mips_reg_names[89][0], \
2848 &mips_reg_names[90][0], \
2849 &mips_reg_names[91][0], \
2850 &mips_reg_names[92][0], \
2851 &mips_reg_names[93][0], \
2852 &mips_reg_names[94][0], \
2853 &mips_reg_names[95][0], \
2854 &mips_reg_names[96][0], \
2855 &mips_reg_names[97][0], \
2856 &mips_reg_names[98][0], \
2857 &mips_reg_names[99][0], \
2858 &mips_reg_names[100][0], \
2859 &mips_reg_names[101][0], \
2860 &mips_reg_names[102][0], \
2861 &mips_reg_names[103][0], \
2862 &mips_reg_names[104][0], \
2863 &mips_reg_names[105][0], \
2864 &mips_reg_names[106][0], \
2865 &mips_reg_names[107][0], \
2866 &mips_reg_names[108][0], \
2867 &mips_reg_names[109][0], \
2868 &mips_reg_names[110][0], \
2869 &mips_reg_names[111][0], \
2870 &mips_reg_names[112][0], \
2871 &mips_reg_names[113][0], \
2872 &mips_reg_names[114][0], \
2873 &mips_reg_names[115][0], \
2874 &mips_reg_names[116][0], \
2875 &mips_reg_names[117][0], \
2876 &mips_reg_names[118][0], \
2877 &mips_reg_names[119][0], \
2878 &mips_reg_names[120][0], \
2879 &mips_reg_names[121][0], \
2880 &mips_reg_names[122][0], \
2881 &mips_reg_names[123][0], \
2882 &mips_reg_names[124][0], \
2883 &mips_reg_names[125][0], \
2884 &mips_reg_names[126][0], \
2885 &mips_reg_names[127][0], \
2886 &mips_reg_names[128][0], \
2887 &mips_reg_names[129][0], \
2888 &mips_reg_names[130][0], \
2889 &mips_reg_names[131][0], \
2890 &mips_reg_names[132][0], \
2891 &mips_reg_names[133][0], \
2892 &mips_reg_names[134][0], \
2893 &mips_reg_names[135][0], \
2894 &mips_reg_names[136][0], \
2895 &mips_reg_names[137][0], \
2896 &mips_reg_names[138][0], \
2897 &mips_reg_names[139][0], \
2898 &mips_reg_names[140][0], \
2899 &mips_reg_names[141][0], \
2900 &mips_reg_names[142][0], \
2901 &mips_reg_names[143][0], \
2902 &mips_reg_names[144][0], \
2903 &mips_reg_names[145][0], \
2904 &mips_reg_names[146][0], \
2905 &mips_reg_names[147][0], \
2906 &mips_reg_names[148][0], \
2907 &mips_reg_names[149][0], \
2908 &mips_reg_names[150][0], \
2909 &mips_reg_names[151][0], \
2910 &mips_reg_names[152][0], \
2911 &mips_reg_names[153][0], \
2912 &mips_reg_names[154][0], \
2913 &mips_reg_names[155][0], \
2914 &mips_reg_names[156][0], \
2915 &mips_reg_names[157][0], \
2916 &mips_reg_names[158][0], \
2917 &mips_reg_names[159][0], \
2918 &mips_reg_names[160][0], \
2919 &mips_reg_names[161][0], \
2920 &mips_reg_names[162][0], \
2921 &mips_reg_names[163][0], \
2922 &mips_reg_names[164][0], \
2923 &mips_reg_names[165][0], \
2924 &mips_reg_names[166][0], \
2925 &mips_reg_names[167][0], \
2926 &mips_reg_names[168][0], \
2927 &mips_reg_names[169][0], \
2928 &mips_reg_names[170][0], \
2929 &mips_reg_names[171][0], \
2930 &mips_reg_names[172][0], \
2931 &mips_reg_names[173][0], \
2932 &mips_reg_names[174][0], \
2933 &mips_reg_names[175][0] \
2936 /* If defined, a C initializer for an array of structures
2937 containing a name and a register number. This macro defines
2938 additional names for hard registers, thus allowing the `asm'
2939 option in declarations to refer to registers using alternate
2942 We define both names for the integer registers here. */
2944 #define ADDITIONAL_REGISTER_NAMES \
2946 { "$0", 0 + GP_REG_FIRST }, \
2947 { "$1", 1 + GP_REG_FIRST }, \
2948 { "$2", 2 + GP_REG_FIRST }, \
2949 { "$3", 3 + GP_REG_FIRST }, \
2950 { "$4", 4 + GP_REG_FIRST }, \
2951 { "$5", 5 + GP_REG_FIRST }, \
2952 { "$6", 6 + GP_REG_FIRST }, \
2953 { "$7", 7 + GP_REG_FIRST }, \
2954 { "$8", 8 + GP_REG_FIRST }, \
2955 { "$9", 9 + GP_REG_FIRST }, \
2956 { "$10", 10 + GP_REG_FIRST }, \
2957 { "$11", 11 + GP_REG_FIRST }, \
2958 { "$12", 12 + GP_REG_FIRST }, \
2959 { "$13", 13 + GP_REG_FIRST }, \
2960 { "$14", 14 + GP_REG_FIRST }, \
2961 { "$15", 15 + GP_REG_FIRST }, \
2962 { "$16", 16 + GP_REG_FIRST }, \
2963 { "$17", 17 + GP_REG_FIRST }, \
2964 { "$18", 18 + GP_REG_FIRST }, \
2965 { "$19", 19 + GP_REG_FIRST }, \
2966 { "$20", 20 + GP_REG_FIRST }, \
2967 { "$21", 21 + GP_REG_FIRST }, \
2968 { "$22", 22 + GP_REG_FIRST }, \
2969 { "$23", 23 + GP_REG_FIRST }, \
2970 { "$24", 24 + GP_REG_FIRST }, \
2971 { "$25", 25 + GP_REG_FIRST }, \
2972 { "$26", 26 + GP_REG_FIRST }, \
2973 { "$27", 27 + GP_REG_FIRST }, \
2974 { "$28", 28 + GP_REG_FIRST }, \
2975 { "$29", 29 + GP_REG_FIRST }, \
2976 { "$30", 30 + GP_REG_FIRST }, \
2977 { "$31", 31 + GP_REG_FIRST }, \
2978 { "$sp", 29 + GP_REG_FIRST }, \
2979 { "$fp", 30 + GP_REG_FIRST }, \
2980 { "at", 1 + GP_REG_FIRST }, \
2981 { "v0", 2 + GP_REG_FIRST }, \
2982 { "v1", 3 + GP_REG_FIRST }, \
2983 { "a0", 4 + GP_REG_FIRST }, \
2984 { "a1", 5 + GP_REG_FIRST }, \
2985 { "a2", 6 + GP_REG_FIRST }, \
2986 { "a3", 7 + GP_REG_FIRST }, \
2987 { "t0", 8 + GP_REG_FIRST }, \
2988 { "t1", 9 + GP_REG_FIRST }, \
2989 { "t2", 10 + GP_REG_FIRST }, \
2990 { "t3", 11 + GP_REG_FIRST }, \
2991 { "t4", 12 + GP_REG_FIRST }, \
2992 { "t5", 13 + GP_REG_FIRST }, \
2993 { "t6", 14 + GP_REG_FIRST }, \
2994 { "t7", 15 + GP_REG_FIRST }, \
2995 { "s0", 16 + GP_REG_FIRST }, \
2996 { "s1", 17 + GP_REG_FIRST }, \
2997 { "s2", 18 + GP_REG_FIRST }, \
2998 { "s3", 19 + GP_REG_FIRST }, \
2999 { "s4", 20 + GP_REG_FIRST }, \
3000 { "s5", 21 + GP_REG_FIRST }, \
3001 { "s6", 22 + GP_REG_FIRST }, \
3002 { "s7", 23 + GP_REG_FIRST }, \
3003 { "t8", 24 + GP_REG_FIRST }, \
3004 { "t9", 25 + GP_REG_FIRST }, \
3005 { "k0", 26 + GP_REG_FIRST }, \
3006 { "k1", 27 + GP_REG_FIRST }, \
3007 { "gp", 28 + GP_REG_FIRST }, \
3008 { "sp", 29 + GP_REG_FIRST }, \
3009 { "fp", 30 + GP_REG_FIRST }, \
3010 { "ra", 31 + GP_REG_FIRST }, \
3011 { "$sp", 29 + GP_REG_FIRST }, \
3012 { "$fp", 30 + GP_REG_FIRST } \
3013 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3016 /* This is meant to be redefined in the host dependent files. It is a
3017 set of alternative names and regnums for mips coprocessors. */
3019 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3021 /* A C compound statement to output to stdio stream STREAM the
3022 assembler syntax for an instruction operand X. X is an RTL
3025 CODE is a value that can be used to specify one of several ways
3026 of printing the operand. It is used when identical operands
3027 must be printed differently depending on the context. CODE
3028 comes from the `%' specification that was used to request
3029 printing of the operand. If the specification was just `%DIGIT'
3030 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3031 is the ASCII code for LTR.
3033 If X is a register, this macro should print the register's name.
3034 The names can be found in an array `reg_names' whose type is
3035 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3037 When the machine description has a specification `%PUNCT' (a `%'
3038 followed by a punctuation character), this macro is called with
3039 a null pointer for X and the punctuation character for CODE.
3041 See mips.c for the MIPS specific codes. */
3043 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3045 /* A C expression which evaluates to true if CODE is a valid
3046 punctuation character for use in the `PRINT_OPERAND' macro. If
3047 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3048 punctuation characters (except for the standard one, `%') are
3049 used in this way. */
3051 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3053 /* A C compound statement to output to stdio stream STREAM the
3054 assembler syntax for an instruction operand that is a memory
3055 reference whose address is ADDR. ADDR is an RTL expression. */
3057 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3060 /* A C statement, to be executed after all slot-filler instructions
3061 have been output. If necessary, call `dbr_sequence_length' to
3062 determine the number of slots filled in a sequence (zero if not
3063 currently outputting a sequence), to decide how many no-ops to
3064 output, or whatever.
3066 Don't define this macro if it has nothing to do, but it is
3067 helpful in reading assembly output if the extent of the delay
3068 sequence is made explicit (e.g. with white space).
3070 Note that output routines for instructions with delay slots must
3071 be prepared to deal with not being output as part of a sequence
3072 (i.e. when the scheduling pass is not run, or when no slot
3073 fillers could be found.) The variable `final_sequence' is null
3074 when not processing a sequence, otherwise it contains the
3075 `sequence' rtx being output. */
3077 #define DBR_OUTPUT_SEQEND(STREAM) \
3080 if (set_nomacro > 0 && --set_nomacro == 0) \
3081 fputs ("\t.set\tmacro\n", STREAM); \
3083 if (set_noreorder > 0 && --set_noreorder == 0) \
3084 fputs ("\t.set\treorder\n", STREAM); \
3086 fputs ("\n", STREAM); \
3091 /* How to tell the debugger about changes of source files. */
3093 #ifndef SET_FILE_NUMBER
3094 #define SET_FILE_NUMBER() ++num_source_filenames
3097 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3098 mips_output_filename (STREAM, NAME)
3100 /* This is defined so that it can be overridden in iris6.h. */
3101 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3104 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3105 output_quoted_string (STREAM, NAME); \
3106 fputs ("\n", STREAM); \
3110 /* This is how to output a note the debugger telling it the line number
3111 to which the following sequence of instructions corresponds.
3112 Silicon graphics puts a label after each .loc. */
3114 #ifndef LABEL_AFTER_LOC
3115 #define LABEL_AFTER_LOC(STREAM)
3118 #ifndef ASM_OUTPUT_SOURCE_LINE
3119 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3120 mips_output_lineno (STREAM, LINE)
3123 /* The MIPS implementation uses some labels for its own purpose. The
3124 following lists what labels are created, and are all formed by the
3125 pattern $L[a-z].*. The machine independent portion of GCC creates
3126 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3128 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3129 $Lb[0-9]+ Begin blocks for MIPS debug support
3130 $Lc[0-9]+ Label for use in s<xx> operation.
3131 $Le[0-9]+ End blocks for MIPS debug support */
3133 #undef ASM_DECLARE_OBJECT_NAME
3134 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3135 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3137 /* Globalizing directive for a label. */
3138 #define GLOBAL_ASM_OP "\t.globl\t"
3140 /* This says how to define a global common symbol. */
3142 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
3144 /* This says how to define a local common symbol (ie, not visible to
3147 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3148 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3151 /* This says how to output an external. It would be possible not to
3152 output anything and let undefined symbol become external. However
3153 the assembler uses length information on externals to allocate in
3154 data/sdata bss/sbss, thereby saving exec time. */
3156 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3157 mips_output_external(STREAM,DECL,NAME)
3159 /* This is how to declare a function name. The actual work of
3160 emitting the label is moved to function_prologue, so that we can
3161 get the line number correctly emitted before the .ent directive,
3162 and after any .file directives. Define as empty so that the function
3163 is not declared before the .ent directive elsewhere. */
3165 #undef ASM_DECLARE_FUNCTION_NAME
3166 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3168 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3169 #define FUNCTION_NAME_ALREADY_DECLARED 0
3172 /* This is how to store into the string LABEL
3173 the symbol_ref name of an internal numbered label where
3174 PREFIX is the class of label and NUM is the number within the class.
3175 This is suitable for output with `assemble_name'. */
3177 #undef ASM_GENERATE_INTERNAL_LABEL
3178 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3179 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3181 /* This is how to output an element of a case-vector that is absolute. */
3183 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3184 fprintf (STREAM, "\t%s\t%sL%d\n", \
3185 ptr_mode == DImode ? ".dword" : ".word", \
3186 LOCAL_LABEL_PREFIX, \
3189 /* This is how to output an element of a case-vector that is relative.
3190 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3191 TARGET_EMBEDDED_PIC). */
3193 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3195 if (TARGET_MIPS16) \
3196 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3197 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3198 else if (TARGET_EMBEDDED_PIC) \
3199 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3200 ptr_mode == DImode ? ".dword" : ".word", \
3201 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3202 else if (TARGET_GPWORD) \
3203 fprintf (STREAM, "\t%s\t%sL%d\n", \
3204 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3205 LOCAL_LABEL_PREFIX, VALUE); \
3207 fprintf (STREAM, "\t%s\t%sL%d\n", \
3208 ptr_mode == DImode ? ".dword" : ".word", \
3209 LOCAL_LABEL_PREFIX, VALUE); \
3212 /* When generating embedded PIC or mips16 code we want to put the jump
3213 table in the .text section. In all other cases, we want to put the
3214 jump table in the .rdata section. Unfortunately, we can't use
3215 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3216 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3217 section if appropriate. */
3218 #undef ASM_OUTPUT_CASE_LABEL
3219 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3221 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3222 function_section (current_function_decl); \
3223 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3226 /* This is how to output an assembler line
3227 that says to advance the location counter
3228 to a multiple of 2**LOG bytes. */
3230 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3231 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3233 /* This is how to output an assembler line to advance the location
3234 counter by SIZE bytes. */
3236 #undef ASM_OUTPUT_SKIP
3237 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3238 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3240 /* This is how to output a string. */
3241 #undef ASM_OUTPUT_ASCII
3242 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3243 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3245 /* Output #ident as a in the read-only data section. */
3246 #undef ASM_OUTPUT_IDENT
3247 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3249 const char *p = STRING; \
3250 int size = strlen (p) + 1; \
3251 readonly_data_section (); \
3252 assemble_string (p, size); \
3255 /* Default to -G 8 */
3256 #ifndef MIPS_DEFAULT_GVALUE
3257 #define MIPS_DEFAULT_GVALUE 8
3260 /* Define the strings to put out for each section in the object file. */
3261 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3262 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3263 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3265 #undef READONLY_DATA_SECTION_ASM_OP
3266 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3268 /* Given a decl node or constant node, choose the section to output it in
3269 and select that section. */
3271 #undef TARGET_ASM_SELECT_SECTION
3272 #define TARGET_ASM_SELECT_SECTION mips_select_section
3274 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3277 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3278 TARGET_64BIT ? "dsubu" : "subu", \
3279 reg_names[STACK_POINTER_REGNUM], \
3280 reg_names[STACK_POINTER_REGNUM], \
3281 TARGET_64BIT ? "sd" : "sw", \
3283 reg_names[STACK_POINTER_REGNUM]); \
3287 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3290 if (! set_noreorder) \
3291 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3293 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3294 TARGET_64BIT ? "ld" : "lw", \
3296 reg_names[STACK_POINTER_REGNUM], \
3297 TARGET_64BIT ? "daddu" : "addu", \
3298 reg_names[STACK_POINTER_REGNUM], \
3299 reg_names[STACK_POINTER_REGNUM]); \
3301 if (! set_noreorder) \
3302 fprintf (STREAM, "\t.set\treorder\n"); \
3306 /* How to start an assembler comment.
3307 The leading space is important (the mips native assembler requires it). */
3308 #ifndef ASM_COMMENT_START
3309 #define ASM_COMMENT_START " #"
3312 /* Default definitions for size_t and ptrdiff_t. We must override the
3313 definitions from ../svr4.h on mips-*-linux-gnu. */
3316 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3319 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3321 /* See mips_expand_prologue's use of loadgp for when this should be
3324 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3326 /* Generate calls to memcpy, etc., not bcopy, etc. */
3327 #define TARGET_MEM_FUNCTIONS
3330 /* Since the bits of the _init and _fini function is spread across
3331 many object files, each potentially with its own GP, we must assume
3332 we need to load our GP. We don't preserve $gp or $ra, since each
3333 init/fini chunk is supposed to initialize $gp, and crti/crtn
3334 already take care of preserving $ra and, when appropriate, $gp. */
3335 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3336 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3337 asm (SECTION_OP "\n\
3343 jal " USER_LABEL_PREFIX #FUNC "\n\
3344 " TEXT_SECTION_ASM_OP);
3345 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3346 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3347 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3348 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3349 asm (SECTION_OP "\n\
3354 .cpsetup $31, $2, 1b\n\
3355 jal " USER_LABEL_PREFIX #FUNC "\n\
3356 " TEXT_SECTION_ASM_OP);
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