1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern int target_flags;
31 /* MIPS external variables defined in mips.c. */
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
74 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
75 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
76 to work on a 64 bit machine. */
84 /* Information about one recognized processor. Defined here for the
85 benefit of TARGET_CPU_CPP_BUILTINS. */
86 struct mips_cpu_info {
87 /* The 'canonical' name of the processor as far as GCC is concerned.
88 It's typically a manufacturer's prefix followed by a numerical
89 designation. It should be lower case. */
92 /* The internal processor number that most closely matches this
93 entry. Several processors can have the same value, if there's no
94 difference between them from GCC's point of view. */
95 enum processor_type cpu;
97 /* The ISA level that the processor implements. */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern const char *mips_arch_string; /* for -march=<xxx> */
120 extern const char *mips_tune_string; /* for -mtune=<xxx> */
121 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
122 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
123 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
124 extern const struct mips_cpu_info mips_cpu_info_table[];
125 extern const struct mips_cpu_info *mips_arch_info;
126 extern const struct mips_cpu_info *mips_tune_info;
128 /* Macros to silence warnings about numbers being signed in traditional
129 C and unsigned in ISO C when compiled on 32-bit hosts. */
131 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
132 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
133 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
136 /* Run-time compilation parameters selecting different hardware subsets. */
138 /* Macros used in the machine description to test the flags. */
140 /* Bits for real switches */
141 #define MASK_INT64 0x00000001 /* ints are 64 bits */
142 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
143 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
144 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
145 multiply-add operations. */
146 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
147 #define MASK_EXPLICIT_RELOCS 0x00000020 /* Use relocation operators. */
148 #define MASK_MEMCPY 0x00000040 /* call memcpy instead of inline code*/
149 #define MASK_SOFT_FLOAT 0x00000080 /* software floating point */
150 #define MASK_FLOAT64 0x00000100 /* fp registers are 64 bits */
151 #define MASK_ABICALLS 0x00000200 /* emit .abicalls/.cprestore/.cpload */
152 #define MASK_XGOT 0x00000400 /* emit big-got PIC */
153 #define MASK_LONG_CALLS 0x00000800 /* Always call through a register */
154 #define MASK_64BIT 0x00001000 /* Use 64 bit GP registers and insns */
155 #define MASK_EMBEDDED_DATA 0x00002000 /* Reduce RAM usage, not fast code */
156 #define MASK_BIG_ENDIAN 0x00004000 /* Generate big endian code */
157 #define MASK_SINGLE_FLOAT 0x00008000 /* Only single precision FPU. */
158 #define MASK_MAD 0x00010000 /* Generate mad/madu as on 4650. */
159 #define MASK_4300_MUL_FIX 0x00020000 /* Work-around early Vr4300 CPU bug */
160 #define MASK_MIPS16 0x00040000 /* Generate mips16 code */
161 #define MASK_NO_CHECK_ZERO_DIV \
162 0x00080000 /* divide by zero checking */
163 #define MASK_BRANCHLIKELY 0x00100000 /* Generate Branch Likely
165 #define MASK_UNINIT_CONST_IN_RODATA \
166 0x00200000 /* Store uninitialized
168 #define MASK_FIX_R4000 0x00400000 /* Work around R4000 errata. */
169 #define MASK_FIX_R4400 0x00800000 /* Work around R4400 errata. */
170 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
171 #define MASK_FIX_VR4120 0x02000000 /* Work around VR4120 errata. */
172 #define MASK_VR4130_ALIGN 0x04000000 /* Perform VR4130 alignment opts. */
173 #define MASK_FP_EXCEPTIONS 0x08000000 /* FP exceptions are enabled. */
175 /* Debug switches, not documented */
176 #define MASK_DEBUG 0 /* unused */
177 #define MASK_DEBUG_D 0 /* don't do define_split's */
179 /* Dummy switches used only in specs */
180 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
182 /* r4000 64 bit sizes */
183 #define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
184 #define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
185 #define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
186 #define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
188 /* Mips vs. GNU linker */
189 #define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
191 /* Mips vs. GNU assembler */
192 #define TARGET_GAS ((target_flags & MASK_GAS) != 0)
193 #define TARGET_MIPS_AS (!TARGET_GAS)
196 #define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
197 #define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
199 /* call memcpy instead of inline code */
200 #define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
202 /* .abicalls, etc from Pyramid V.4 */
203 #define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
204 #define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
206 /* software floating point */
207 #define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
208 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
210 /* always call through a register */
211 #define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
213 /* for embedded systems, optimize for
214 reduced RAM space instead of for
216 #define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
218 /* always store uninitialized const
219 variables in rodata, requires
220 TARGET_EMBEDDED_DATA. */
221 #define TARGET_UNINIT_CONST_IN_RODATA \
222 ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
224 /* generate big endian code. */
225 #define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
227 #define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
228 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
230 #define TARGET_MAD ((target_flags & MASK_MAD) != 0)
232 #define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
234 #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
236 #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
238 #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
240 #define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
242 /* Work around R4000 errata. */
243 #define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
245 /* Work around R4400 errata. */
246 #define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
247 #define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
248 #define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
250 #define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
252 /* True if we should use NewABI-style relocation operators for
253 symbolic addresses. This is never true for mips16 code,
254 which has its own conventions. */
256 #define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
259 /* True if the call patterns should be split into a jalr followed by
260 an instruction to restore $gp. This is only ever true for SVR4 PIC,
261 in which $gp is call-clobbered. It is only safe to split the load
262 from the call when every use of $gp is explicit. */
264 #define TARGET_SPLIT_CALLS \
265 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
267 /* True if we can optimize sibling calls. For simplicity, we only
268 handle cases in which call_insn_operand will reject invalid
269 sibcall addresses. There are two cases in which this isn't true:
271 - TARGET_MIPS16. call_insn_operand accepts constant addresses
272 but there is no direct jump instruction. It isn't worth
273 using sibling calls in this case anyway; they would usually
274 be longer than normal calls.
276 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
277 accepts global constants, but "jr $25" is the only allowed
280 #define TARGET_SIBCALLS \
281 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
283 /* True if .gpword or .gpdword should be used for switch tables.
284 There are some problems with using these directives with the
287 - It has been reported that some versions of the native n32
288 assembler mishandle .gpword, complaining that symbols are
289 global when they are in fact local.
291 - The native assemblers don't understand .gpdword.
293 - Although GAS does understand .gpdword, the native linker
294 mishandles the relocations GAS generates (R_MIPS_GPREL32
295 followed by R_MIPS_64).
297 We therefore disable GP-relative switch tables for n32 and n64
299 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
301 /* Generate mips16 code */
302 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
304 /* Generic ISA defines. */
305 #define ISA_MIPS1 (mips_isa == 1)
306 #define ISA_MIPS2 (mips_isa == 2)
307 #define ISA_MIPS3 (mips_isa == 3)
308 #define ISA_MIPS4 (mips_isa == 4)
309 #define ISA_MIPS32 (mips_isa == 32)
310 #define ISA_MIPS32R2 (mips_isa == 33)
311 #define ISA_MIPS64 (mips_isa == 64)
313 /* Architecture target defines. */
314 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
315 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
316 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
317 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
318 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
319 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
320 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
321 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
322 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
324 /* Scheduling target defines. */
325 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
326 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
327 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
328 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
329 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
330 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
331 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
332 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
333 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
334 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
335 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
336 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
338 /* True if the pre-reload scheduler should try to create chains of
339 multiply-add or multiply-subtract instructions. For example,
347 t1 will have a higher priority than t2 and t3 will have a higher
348 priority than t4. However, before reload, there is no dependence
349 between t1 and t3, and they can often have similar priorities.
350 The scheduler will then tend to prefer:
357 which stops us from making full use of macc/madd-style instructions.
358 This sort of situation occurs frequently in Fourier transforms and
361 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
362 queue so that chained multiply-add and multiply-subtract instructions
363 appear ahead of any other instruction that is likely to clobber lo.
364 In the example above, if t2 and t3 become ready at the same time,
365 the code ensures that t2 is scheduled first.
367 Multiply-accumulate instructions are a bigger win for some targets
368 than others, so this macro is defined on an opt-in basis. */
369 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
373 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
374 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
376 /* IRIX specific stuff. */
377 #define TARGET_IRIX 0
378 #define TARGET_IRIX5 0
379 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
381 /* Define preprocessor macros for the -march and -mtune options.
382 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
383 processor. If INFO's canonical name is "foo", define PREFIX to
384 be "foo", and define an additional macro PREFIX_FOO. */
385 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
390 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
391 for (p = macro; *p != 0; p++) \
394 builtin_define (macro); \
395 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
400 /* Target CPU builtins. */
401 #define TARGET_CPU_CPP_BUILTINS() \
404 builtin_assert ("cpu=mips"); \
405 builtin_define ("__mips__"); \
406 builtin_define ("_mips"); \
408 /* We do this here because __mips is defined below \
409 and so we can't use builtin_define_std. */ \
411 builtin_define ("mips"); \
413 /* Treat _R3000 and _R4000 like register-size defines, \
414 which is how they've historically been used. */ \
417 builtin_define ("__mips64"); \
418 builtin_define_std ("R4000"); \
419 builtin_define ("_R4000"); \
423 builtin_define_std ("R3000"); \
424 builtin_define ("_R3000"); \
426 if (TARGET_FLOAT64) \
427 builtin_define ("__mips_fpr=64"); \
429 builtin_define ("__mips_fpr=32"); \
432 builtin_define ("__mips16"); \
434 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
435 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
439 builtin_define ("__mips=1"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
442 else if (ISA_MIPS2) \
444 builtin_define ("__mips=2"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
447 else if (ISA_MIPS3) \
449 builtin_define ("__mips=3"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
452 else if (ISA_MIPS4) \
454 builtin_define ("__mips=4"); \
455 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
457 else if (ISA_MIPS32) \
459 builtin_define ("__mips=32"); \
460 builtin_define ("__mips_isa_rev=1"); \
461 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
463 else if (ISA_MIPS32R2) \
465 builtin_define ("__mips=32"); \
466 builtin_define ("__mips_isa_rev=2"); \
467 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
469 else if (ISA_MIPS64) \
471 builtin_define ("__mips=64"); \
472 builtin_define ("__mips_isa_rev=1"); \
473 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
476 if (TARGET_HARD_FLOAT) \
477 builtin_define ("__mips_hard_float"); \
478 else if (TARGET_SOFT_FLOAT) \
479 builtin_define ("__mips_soft_float"); \
481 if (TARGET_SINGLE_FLOAT) \
482 builtin_define ("__mips_single_float"); \
484 if (TARGET_BIG_ENDIAN) \
486 builtin_define_std ("MIPSEB"); \
487 builtin_define ("_MIPSEB"); \
491 builtin_define_std ("MIPSEL"); \
492 builtin_define ("_MIPSEL"); \
495 /* Macros dependent on the C dialect. */ \
496 if (preprocessing_asm_p ()) \
498 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
499 builtin_define ("_LANGUAGE_ASSEMBLY"); \
501 else if (c_dialect_cxx ()) \
503 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
504 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
505 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
509 builtin_define_std ("LANGUAGE_C"); \
510 builtin_define ("_LANGUAGE_C"); \
512 if (c_dialect_objc ()) \
514 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
515 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
516 /* Bizarre, but needed at least for Irix. */ \
517 builtin_define_std ("LANGUAGE_C"); \
518 builtin_define ("_LANGUAGE_C"); \
521 if (mips_abi == ABI_EABI) \
522 builtin_define ("__mips_eabi"); \
528 /* Macro to define tables used to set the flags.
529 This is a list in braces of pairs in braces,
530 each pair being { "NAME", VALUE }
531 where VALUE is the bits to set or minus the bits to clear.
532 An empty string NAME is used to identify the default VALUE. */
534 #define TARGET_SWITCHES \
536 SUBTARGET_TARGET_SWITCHES \
537 {"int64", MASK_INT64 | MASK_LONG64, \
538 N_("Use 64-bit int type")}, \
539 {"long64", MASK_LONG64, \
540 N_("Use 64-bit long type")}, \
541 {"long32", -(MASK_LONG64 | MASK_INT64), \
542 N_("Use 32-bit long type")}, \
543 {"split-addresses", MASK_SPLIT_ADDR, \
544 N_("Optimize lui/addiu address loads")}, \
545 {"no-split-addresses", -MASK_SPLIT_ADDR, \
546 N_("Don't optimize lui/addiu address loads")}, \
547 {"mips-as", -MASK_GAS, \
548 N_("Use MIPS as")}, \
552 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
554 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
556 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
558 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
560 N_("Output compiler statistics (now ignored)")}, \
562 N_("Don't output compiler statistics")}, \
563 {"memcpy", MASK_MEMCPY, \
564 N_("Don't optimize block moves")}, \
565 {"no-memcpy", -MASK_MEMCPY, \
566 N_("Optimize block moves")}, \
567 {"mips-tfile", MASK_MIPS_TFILE, \
568 N_("Use mips-tfile asm postpass")}, \
569 {"no-mips-tfile", -MASK_MIPS_TFILE, \
570 N_("Don't use mips-tfile asm postpass")}, \
571 {"soft-float", MASK_SOFT_FLOAT, \
572 N_("Use software floating point")}, \
573 {"hard-float", -MASK_SOFT_FLOAT, \
574 N_("Use hardware floating point")}, \
575 {"fp64", MASK_FLOAT64, \
576 N_("Use 64-bit FP registers")}, \
577 {"fp32", -MASK_FLOAT64, \
578 N_("Use 32-bit FP registers")}, \
579 {"gp64", MASK_64BIT, \
580 N_("Use 64-bit general registers")}, \
581 {"gp32", -MASK_64BIT, \
582 N_("Use 32-bit general registers")}, \
583 {"abicalls", MASK_ABICALLS, \
584 N_("Use Irix PIC")}, \
585 {"no-abicalls", -MASK_ABICALLS, \
586 N_("Don't use Irix PIC")}, \
587 {"long-calls", MASK_LONG_CALLS, \
588 N_("Use indirect calls")}, \
589 {"no-long-calls", -MASK_LONG_CALLS, \
590 N_("Don't use indirect calls")}, \
591 {"embedded-data", MASK_EMBEDDED_DATA, \
592 N_("Use ROM instead of RAM")}, \
593 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
594 N_("Don't use ROM instead of RAM")}, \
595 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
596 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
597 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
598 N_("Don't put uninitialized constants in ROM")}, \
599 {"eb", MASK_BIG_ENDIAN, \
600 N_("Use big-endian byte order")}, \
601 {"el", -MASK_BIG_ENDIAN, \
602 N_("Use little-endian byte order")}, \
603 {"single-float", MASK_SINGLE_FLOAT, \
604 N_("Use single (32-bit) FP only")}, \
605 {"double-float", -MASK_SINGLE_FLOAT, \
606 N_("Don't use single (32-bit) FP only")}, \
608 N_("Use multiply accumulate")}, \
609 {"no-mad", -MASK_MAD, \
610 N_("Don't use multiply accumulate")}, \
611 {"no-fused-madd", MASK_NO_FUSED_MADD, \
612 N_("Don't generate fused multiply/add instructions")}, \
613 {"fused-madd", -MASK_NO_FUSED_MADD, \
614 N_("Generate fused multiply/add instructions")}, \
615 {"vr4130-align", MASK_VR4130_ALIGN, \
616 N_("Perform VR4130-specific alignment optimizations")}, \
617 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
618 N_("Don't perform VR4130-specific alignment optimizations")}, \
619 {"fix4300", MASK_4300_MUL_FIX, \
620 N_("Work around early 4300 hardware bug")}, \
621 {"no-fix4300", -MASK_4300_MUL_FIX, \
622 N_("Don't work around early 4300 hardware bug")}, \
623 {"fix-sb1", MASK_FIX_SB1, \
624 N_("Work around errata for early SB-1 revision 2 cores")}, \
625 {"no-fix-sb1", -MASK_FIX_SB1, \
626 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
627 {"fix-r4000", MASK_FIX_R4000, \
628 N_("Work around R4000 errata")}, \
629 {"no-fix-r4000", -MASK_FIX_R4000, \
630 N_("Don't work around R4000 errata")}, \
631 {"fix-r4400", MASK_FIX_R4400, \
632 N_("Work around R4400 errata")}, \
633 {"no-fix-r4400", -MASK_FIX_R4400, \
634 N_("Don't work around R4400 errata")}, \
635 {"fix-vr4120", MASK_FIX_VR4120, \
636 N_("Work around certain VR4120 errata")}, \
637 {"no-fix-vr4120", -MASK_FIX_VR4120, \
638 N_("Don't work around certain VR4120 errata")}, \
639 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
640 N_("Trap on integer divide by zero")}, \
641 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
642 N_("Don't trap on integer divide by zero")}, \
643 { "branch-likely", MASK_BRANCHLIKELY, \
644 N_("Use Branch Likely instructions, overriding default for arch")}, \
645 { "no-branch-likely", -MASK_BRANCHLIKELY, \
646 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
647 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
648 N_("Use NewABI-style %reloc() assembly operators")}, \
649 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
650 N_("Use assembler macros instead of relocation operators")}, \
651 {"ips16", MASK_MIPS16, \
652 N_("Generate mips16 code") }, \
653 {"no-mips16", -MASK_MIPS16, \
654 N_("Generate normal-mode code") }, \
655 {"xgot", MASK_XGOT, \
656 N_("Lift restrictions on GOT size") }, \
657 {"no-xgot", -MASK_XGOT, \
658 N_("Do not lift restrictions on GOT size") }, \
659 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
660 N_("FP exceptions are enabled") }, \
661 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
662 N_("FP exceptions are not enabled") }, \
663 {"debug", MASK_DEBUG, \
665 {"debugd", MASK_DEBUG_D, \
667 {"", (TARGET_DEFAULT \
668 | TARGET_CPU_DEFAULT \
669 | TARGET_ENDIAN_DEFAULT \
670 | TARGET_FP_EXCEPTIONS_DEFAULT), \
674 /* Default target_flags if no switches are specified */
676 #ifndef TARGET_DEFAULT
677 #define TARGET_DEFAULT 0
680 #ifndef TARGET_CPU_DEFAULT
681 #define TARGET_CPU_DEFAULT 0
684 #ifndef TARGET_ENDIAN_DEFAULT
685 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
688 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
689 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
692 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
693 #ifndef MIPS_ISA_DEFAULT
694 #ifndef MIPS_CPU_STRING_DEFAULT
695 #define MIPS_CPU_STRING_DEFAULT "from-abi"
701 /* Make this compile time constant for libgcc2 */
703 #define TARGET_64BIT 1
705 #define TARGET_64BIT 0
707 #endif /* IN_LIBGCC2 */
709 #ifndef MULTILIB_ENDIAN_DEFAULT
710 #if TARGET_ENDIAN_DEFAULT == 0
711 #define MULTILIB_ENDIAN_DEFAULT "EL"
713 #define MULTILIB_ENDIAN_DEFAULT "EB"
717 #ifndef MULTILIB_ISA_DEFAULT
718 # if MIPS_ISA_DEFAULT == 1
719 # define MULTILIB_ISA_DEFAULT "mips1"
721 # if MIPS_ISA_DEFAULT == 2
722 # define MULTILIB_ISA_DEFAULT "mips2"
724 # if MIPS_ISA_DEFAULT == 3
725 # define MULTILIB_ISA_DEFAULT "mips3"
727 # if MIPS_ISA_DEFAULT == 4
728 # define MULTILIB_ISA_DEFAULT "mips4"
730 # if MIPS_ISA_DEFAULT == 32
731 # define MULTILIB_ISA_DEFAULT "mips32"
733 # if MIPS_ISA_DEFAULT == 33
734 # define MULTILIB_ISA_DEFAULT "mips32r2"
736 # if MIPS_ISA_DEFAULT == 64
737 # define MULTILIB_ISA_DEFAULT "mips64"
739 # define MULTILIB_ISA_DEFAULT "mips1"
749 #ifndef MULTILIB_DEFAULTS
750 #define MULTILIB_DEFAULTS \
751 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
754 /* We must pass -EL to the linker by default for little endian embedded
755 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
756 linker will default to using big-endian output files. The OUTPUT_FORMAT
757 line must be in the linker script, otherwise -EB/-EL will not work. */
760 #if TARGET_ENDIAN_DEFAULT == 0
761 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
763 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
767 #define TARGET_OPTIONS \
769 SUBTARGET_TARGET_OPTIONS \
770 { "tune=", &mips_tune_string, \
771 N_("Specify CPU for scheduling purposes"), 0}, \
772 { "arch=", &mips_arch_string, \
773 N_("Specify CPU for code generation purposes"), 0}, \
774 { "abi=", &mips_abi_string, \
775 N_("Specify an ABI"), 0}, \
776 { "ips", &mips_isa_string, \
777 N_("Specify a Standard MIPS ISA"), 0}, \
778 { "no-flush-func", &mips_cache_flush_func, \
779 N_("Don't call any cache flush functions"), 0}, \
780 { "flush-func=", &mips_cache_flush_func, \
781 N_("Specify cache flush function"), 0}, \
784 /* This is meant to be redefined in the host dependent files. */
785 #define SUBTARGET_TARGET_OPTIONS
787 /* Support for a compile-time default CPU, et cetera. The rules are:
788 --with-arch is ignored if -march is specified or a -mips is specified
789 (other than -mips16).
790 --with-tune is ignored if -mtune is specified.
791 --with-abi is ignored if -mabi is specified.
792 --with-float is ignored if -mhard-float or -msoft-float are
794 #define OPTION_DEFAULT_SPECS \
795 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
796 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
797 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
798 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
801 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
805 /* Generate three-operand multiply instructions for SImode. */
806 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
816 /* Generate three-operand multiply instructions for DImode. */
817 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
820 /* Macros to decide whether certain features are available or not,
821 depending on the instruction set architecture level. */
823 #define HAVE_SQRT_P() (!ISA_MIPS1)
825 /* True if the ABI can only work with 64-bit integer registers. We
826 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
827 otherwise floating-point registers must also be 64-bit. */
828 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
830 /* Likewise for 32-bit regs. */
831 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
833 /* True if symbols are 64 bits wide. At present, n64 is the only
834 ABI for which this is true. */
835 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
837 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
838 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
842 /* ISA has branch likely instructions (eg. mips2). */
843 /* Disable branchlikely for tx39 until compare rewrite. They haven't
844 been generated up to this point. */
845 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
847 /* ISA has the conditional move instructions introduced in mips4. */
848 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
852 && !TARGET_MIPS5500 \
855 /* ISA has just the integer condition move instructions (movn,movz) */
856 #define ISA_HAS_INT_CONDMOVE 0
858 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
859 branch on CC, and move (both FP and non-FP) on CC. */
860 #define ISA_HAS_8CC (ISA_MIPS4 \
865 /* This is a catch all for other mips4 instructions: indexed load, the
866 FP madd and msub instructions, and the FP recip and recip sqrt
868 #define ISA_HAS_FP4 ((ISA_MIPS4 \
872 /* ISA has conditional trap instructions. */
873 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
876 /* ISA has integer multiply-accumulate instructions, madd and msub. */
877 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
882 /* ISA has floating-point nmadd and nmsub instructions. */
883 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
885 && (!TARGET_MIPS5400 || TARGET_MAD) \
888 /* ISA has count leading zeroes/ones instruction (not implemented). */
889 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
894 /* ISA has double-word count leading zeroes/ones instruction (not
896 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
899 /* ISA has three operand multiply instructions that put
900 the high part in an accumulator: mulhi or mulhiu. */
901 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
906 /* ISA has three operand multiply instructions that
907 negates the result and puts the result in an accumulator. */
908 #define ISA_HAS_MULS (TARGET_MIPS5400 \
913 /* ISA has three operand multiply instructions that subtracts the
914 result from a 4th operand and puts the result in an accumulator. */
915 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
919 /* ISA has three operand multiply instructions that the result
920 from a 4th operand and puts the result in an accumulator. */
921 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
922 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
928 /* ISA has 32-bit rotate right instruction. */
929 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
936 /* ISA has 64-bit rotate right instruction. */
937 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
939 && (TARGET_MIPS5400 \
944 /* ISA has data prefetch instructions. This controls use of 'pref'. */
945 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
951 /* ISA has data indexed prefetch instructions. This controls use of
952 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
953 (prefx is a cop1x instruction, so can only be used if FP is
955 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
959 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
960 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
961 also requires TARGET_DOUBLE_FLOAT. */
962 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
964 /* ISA includes the MIPS32r2 seb and seh instructions. */
965 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
969 /* True if the result of a load is not available to the next instruction.
970 A nop will then be needed between instructions like "lw $4,..."
971 and "addiu $4,$4,1". */
972 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
973 && !TARGET_MIPS3900 \
976 /* Likewise mtc1 and mfc1. */
977 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
979 /* Likewise floating-point comparisons. */
980 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
982 /* True if mflo and mfhi can be immediately followed by instructions
983 which write to the HI and LO registers.
985 According to MIPS specifications, MIPS ISAs I, II, and III need
986 (at least) two instructions between the reads of HI/LO and
987 instructions which write them, and later ISAs do not. Contradicting
988 the MIPS specifications, some MIPS IV processor user manuals (e.g.
989 the UM for the NEC Vr5000) document needing the instructions between
990 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
991 MIPS64 and later ISAs to have the interlocks, plus any specific
992 earlier-ISA CPUs for which CPU documentation declares that the
993 instructions are really interlocked. */
994 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
999 /* Add -G xx support. */
1001 #undef SWITCH_TAKES_ARG
1002 #define SWITCH_TAKES_ARG(CHAR) \
1003 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1005 #define OVERRIDE_OPTIONS override_options ()
1007 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1009 /* Show we can debug even without a frame pointer. */
1010 #define CAN_DEBUG_WITHOUT_FP
1012 /* Tell collect what flags to pass to nm. */
1014 #define NM_FLAGS "-Bn"
1018 /* Assembler specs. */
1020 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1023 #define MIPS_AS_ASM_SPEC "\
1024 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1025 %{pipe: %e-pipe is not supported} \
1026 %{K} %(subtarget_mips_as_asm_spec)"
1028 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1029 rather than gas. It may be overridden by subtargets. */
1031 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1032 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1035 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1038 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1040 #define SUBTARGET_TARGET_SWITCHES
1042 #ifndef MIPS_ABI_DEFAULT
1043 #define MIPS_ABI_DEFAULT ABI_32
1046 /* Use the most portable ABI flag for the ASM specs. */
1048 #if MIPS_ABI_DEFAULT == ABI_32
1049 #define MULTILIB_ABI_DEFAULT "mabi=32"
1050 #define ASM_ABI_DEFAULT_SPEC "-32"
1053 #if MIPS_ABI_DEFAULT == ABI_O64
1054 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1055 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1058 #if MIPS_ABI_DEFAULT == ABI_N32
1059 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1060 #define ASM_ABI_DEFAULT_SPEC "-n32"
1063 #if MIPS_ABI_DEFAULT == ABI_64
1064 #define MULTILIB_ABI_DEFAULT "mabi=64"
1065 #define ASM_ABI_DEFAULT_SPEC "-64"
1068 #if MIPS_ABI_DEFAULT == ABI_EABI
1069 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1070 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1073 /* Only ELF targets can switch the ABI. */
1074 #ifndef OBJECT_FORMAT_ELF
1075 #undef ASM_ABI_DEFAULT_SPEC
1076 #define ASM_ABI_DEFAULT_SPEC ""
1079 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1080 GAS_ASM_SPEC as the default, depending upon the value of
1083 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1086 #define TARGET_ASM_SPEC "\
1087 %{mmips-as: %(mips_as_asm_spec)} \
1088 %{!mmips-as: %(gas_asm_spec)}"
1092 #define TARGET_ASM_SPEC "\
1093 %{!mgas: %(mips_as_asm_spec)} \
1094 %{mgas: %(gas_asm_spec)}"
1096 #endif /* not GAS */
1098 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1099 to the assembler. It may be overridden by subtargets. */
1100 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1101 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1103 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1106 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1107 the assembler. It may be overridden by subtargets. */
1108 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1109 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1110 %{g} %{g0} %{g1} %{g2} %{g3} \
1111 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1112 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1113 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1114 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1118 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1120 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1122 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1123 %{!gcoff*:-no-mdebug}"
1125 #define MDEBUG_ASM_SPEC ""
1126 #endif /* not GAS */
1128 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1129 overridden by subtargets. */
1131 #ifndef SUBTARGET_ASM_SPEC
1132 #define SUBTARGET_ASM_SPEC ""
1135 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1136 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1137 whether we're using GAS. These options can only be used properly
1138 with GAS, and it is better to get an error from a non-GAS assembler
1139 than to silently generate bad code. */
1143 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1144 %{mips32} %{mips32r2} %{mips64} \
1145 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1147 %(subtarget_asm_optimizing_spec) \
1148 %(subtarget_asm_debugging_spec) \
1149 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1150 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1151 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1152 %(target_asm_spec) \
1153 %(subtarget_asm_spec)"
1155 /* Extra switches sometimes passed to the linker. */
1156 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1157 will interpret it as a -b option. */
1160 #define LINK_SPEC "\
1162 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1163 %{bestGnum} %{shared} %{non_shared}"
1164 #endif /* LINK_SPEC defined */
1167 /* Specs for the compiler proper */
1169 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1170 overridden by subtargets. */
1171 #ifndef SUBTARGET_CC1_SPEC
1172 #define SUBTARGET_CC1_SPEC ""
1175 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1179 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1180 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1182 %(subtarget_cc1_spec)"
1185 /* Preprocessor specs. */
1187 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1188 overridden by subtargets. */
1189 #ifndef SUBTARGET_CPP_SPEC
1190 #define SUBTARGET_CPP_SPEC ""
1193 #define CPP_SPEC "%(subtarget_cpp_spec)"
1195 /* This macro defines names of additional specifications to put in the specs
1196 that can be used in various specifications like CC1_SPEC. Its definition
1197 is an initializer with a subgrouping for each command option.
1199 Each subgrouping contains a string constant, that defines the
1200 specification name, and a string constant that used by the GCC driver
1203 Do not define this macro if it does not need to do anything. */
1205 #define EXTRA_SPECS \
1206 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1207 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1208 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1209 { "gas_asm_spec", GAS_ASM_SPEC }, \
1210 { "target_asm_spec", TARGET_ASM_SPEC }, \
1211 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1212 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1213 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1214 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1215 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1216 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1217 { "endian_spec", ENDIAN_SPEC }, \
1218 SUBTARGET_EXTRA_SPECS
1220 #ifndef SUBTARGET_EXTRA_SPECS
1221 #define SUBTARGET_EXTRA_SPECS
1224 /* If defined, this macro is an additional prefix to try after
1225 `STANDARD_EXEC_PREFIX'. */
1227 #ifndef MD_EXEC_PREFIX
1228 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1231 #ifndef MD_STARTFILE_PREFIX
1232 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1236 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1237 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1238 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1240 #ifndef PREFERRED_DEBUGGING_TYPE
1241 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1244 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1246 /* By default, turn on GDB extensions. */
1247 #define DEFAULT_GDB_EXTENSIONS 1
1249 /* If we are passing smuggling stabs through the MIPS ECOFF object
1250 format, put a comment in front of the .stab<x> operation so
1251 that the MIPS assembler does not choke. The mips-tfile program
1252 will correctly put the stab into the object file. */
1254 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1255 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1256 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1258 /* Local compiler-generated symbols must have a prefix that the assembler
1259 understands. By default, this is $, although some targets (e.g.,
1260 NetBSD-ELF) need to override this. */
1262 #ifndef LOCAL_LABEL_PREFIX
1263 #define LOCAL_LABEL_PREFIX "$"
1266 /* By default on the mips, external symbols do not have an underscore
1267 prepended, but some targets (e.g., NetBSD) require this. */
1269 #ifndef USER_LABEL_PREFIX
1270 #define USER_LABEL_PREFIX ""
1273 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1274 since the length can run past this up to a continuation point. */
1275 #undef DBX_CONTIN_LENGTH
1276 #define DBX_CONTIN_LENGTH 1500
1278 /* How to renumber registers for dbx and gdb. */
1279 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1281 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1282 #define DWARF_FRAME_REGNUM(REG) (REG)
1284 /* The DWARF 2 CFA column which tracks the return address. */
1285 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1287 /* The DWARF 2 CFA column which tracks the return address from a
1288 signal handler context. */
1289 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1291 /* Before the prologue, RA lives in r31. */
1292 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1294 /* Describe how we implement __builtin_eh_return. */
1295 #define EH_RETURN_DATA_REGNO(N) \
1296 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1298 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1300 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1301 The default for this in 64-bit mode is 8, which causes problems with
1302 SFmode register saves. */
1303 #define DWARF_CIE_DATA_ALIGNMENT 4
1305 /* Correct the offset of automatic variables and arguments. Note that
1306 the MIPS debug format wants all automatic variables and arguments
1307 to be in terms of the virtual frame pointer (stack pointer before
1308 any adjustment in the function), while the MIPS 3.0 linker wants
1309 the frame pointer to be the stack pointer after the initial
1312 #define DEBUGGER_AUTO_OFFSET(X) \
1313 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1314 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1315 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1317 /* Target machine storage layout */
1319 #define BITS_BIG_ENDIAN 0
1320 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1321 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1323 /* Define this to set the endianness to use in libgcc2.c, which can
1324 not depend on target_flags. */
1325 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1326 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1328 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1331 #define MAX_BITS_PER_WORD 64
1333 /* Width of a word, in units (bytes). */
1334 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1335 #define MIN_UNITS_PER_WORD 4
1337 /* For MIPS, width of a floating point register. */
1338 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1340 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1341 the next available register. */
1342 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1344 /* The largest size of value that can be held in floating-point
1345 registers and moved with a single instruction. */
1346 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1348 /* The largest size of value that can be held in floating-point
1350 #define UNITS_PER_FPVALUE \
1351 (TARGET_SOFT_FLOAT ? 0 \
1352 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1353 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1355 /* The number of bytes in a double. */
1356 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1358 /* Set the sizes of the core types. */
1359 #define SHORT_TYPE_SIZE 16
1360 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1361 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1362 #define LONG_LONG_TYPE_SIZE 64
1364 #define FLOAT_TYPE_SIZE 32
1365 #define DOUBLE_TYPE_SIZE 64
1366 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1368 /* long double is not a fixed mode, but the idea is that, if we
1369 support long double, we also want a 128-bit integer type. */
1370 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1373 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1374 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1375 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1377 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1381 /* Width in bits of a pointer. */
1382 #ifndef POINTER_SIZE
1383 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1386 #define POINTERS_EXTEND_UNSIGNED 0
1388 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1389 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1391 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1394 /* Allocation boundary (in *bits*) for the code of a function. */
1395 #define FUNCTION_BOUNDARY 32
1397 /* Alignment of field after `int : 0' in a structure. */
1398 #define EMPTY_FIELD_BOUNDARY 32
1400 /* Every structure's size must be a multiple of this. */
1401 /* 8 is observed right on a DECstation and on riscos 4.02. */
1402 #define STRUCTURE_SIZE_BOUNDARY 8
1404 /* There is no point aligning anything to a rounder boundary than this. */
1405 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1407 /* All accesses must be aligned. */
1408 #define STRICT_ALIGNMENT 1
1410 /* Define this if you wish to imitate the way many other C compilers
1411 handle alignment of bitfields and the structures that contain
1414 The behavior is that the type written for a bit-field (`int',
1415 `short', or other integer type) imposes an alignment for the
1416 entire structure, as if the structure really did contain an
1417 ordinary field of that type. In addition, the bit-field is placed
1418 within the structure so that it would fit within such a field,
1419 not crossing a boundary for it.
1421 Thus, on most machines, a bit-field whose type is written as `int'
1422 would not cross a four-byte boundary, and would force four-byte
1423 alignment for the whole structure. (The alignment used may not
1424 be four bytes; it is controlled by the other alignment
1427 If the macro is defined, its definition should be a C expression;
1428 a nonzero value for the expression enables this behavior. */
1430 #define PCC_BITFIELD_TYPE_MATTERS 1
1432 /* If defined, a C expression to compute the alignment given to a
1433 constant that is being placed in memory. CONSTANT is the constant
1434 and ALIGN is the alignment that the object would ordinarily have.
1435 The value of this macro is used instead of that alignment to align
1438 If this macro is not defined, then ALIGN is used.
1440 The typical use of this macro is to increase alignment for string
1441 constants to be word aligned so that `strcpy' calls that copy
1442 constants can be done inline. */
1444 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1445 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1446 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1448 /* If defined, a C expression to compute the alignment for a static
1449 variable. TYPE is the data type, and ALIGN is the alignment that
1450 the object would ordinarily have. The value of this macro is used
1451 instead of that alignment to align the object.
1453 If this macro is not defined, then ALIGN is used.
1455 One use of this macro is to increase alignment of medium-size
1456 data to make it all fit in fewer cache lines. Another is to
1457 cause character arrays to be word-aligned so that `strcpy' calls
1458 that copy constants to character arrays can be done inline. */
1460 #undef DATA_ALIGNMENT
1461 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1462 ((((ALIGN) < BITS_PER_WORD) \
1463 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1464 || TREE_CODE (TYPE) == UNION_TYPE \
1465 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1468 #define PAD_VARARGS_DOWN \
1469 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1471 /* Define if operations between registers always perform the operation
1472 on the full register even if a narrower mode is specified. */
1473 #define WORD_REGISTER_OPERATIONS
1475 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1476 moves. All other references are zero extended. */
1477 #define LOAD_EXTEND_OP(MODE) \
1478 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1479 ? SIGN_EXTEND : ZERO_EXTEND)
1481 /* Define this macro if it is advisable to hold scalars in registers
1482 in a wider mode than that declared by the program. In such cases,
1483 the value is constrained to be within the bounds of the declared
1484 type, but kept valid in the wider mode. The signedness of the
1485 extension may differ from that of the type. */
1487 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1488 if (GET_MODE_CLASS (MODE) == MODE_INT \
1489 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1491 if ((MODE) == SImode) \
1496 /* Define if loading short immediate values into registers sign extends. */
1497 #define SHORT_IMMEDIATES_SIGN_EXTEND
1499 /* Standard register usage. */
1501 /* Number of hardware registers. We have:
1503 - 32 integer registers
1504 - 32 floating point registers
1505 - 8 condition code registers
1506 - 2 accumulator registers (hi and lo)
1507 - 32 registers each for coprocessors 0, 2 and 3
1509 - ARG_POINTER_REGNUM
1510 - FRAME_POINTER_REGNUM
1511 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1512 - 3 dummy entries that were used at various times in the past. */
1514 #define FIRST_PSEUDO_REGISTER 176
1516 /* By default, fix the kernel registers ($26 and $27), the global
1517 pointer ($28) and the stack pointer ($29). This can change
1518 depending on the command-line options.
1520 Regarding coprocessor registers: without evidence to the contrary,
1521 it's best to assume that each coprocessor register has a unique
1522 use. This can be overridden, in, e.g., override_options() or
1523 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1524 for a particular target. */
1526 #define FIXED_REGISTERS \
1528 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1532 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1533 /* COP0 registers */ \
1534 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 /* COP2 registers */ \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 /* COP3 registers */ \
1540 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1545 /* Set up this array for o32 by default.
1547 Note that we don't mark $31 as a call-clobbered register. The idea is
1548 that it's really the call instructions themselves which clobber $31.
1549 We don't care what the called function does with it afterwards.
1551 This approach makes it easier to implement sibcalls. Unlike normal
1552 calls, sibcalls don't clobber $31, so the register reaches the
1553 called function in tact. EPILOGUE_USES says that $31 is useful
1554 to the called function. */
1556 #define CALL_USED_REGISTERS \
1558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1559 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1561 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 /* COP0 registers */ \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1566 /* COP2 registers */ \
1567 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 /* COP3 registers */ \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1575 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1577 #define CALL_REALLY_USED_REGISTERS \
1578 { /* General registers. */ \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1580 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1581 /* Floating-point registers. */ \
1582 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1583 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 /* COP0 registers */ \
1587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1589 /* COP2 registers */ \
1590 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1591 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 /* COP3 registers */ \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1597 /* Internal macros to classify a register number as to whether it's a
1598 general purpose register, a floating point register, a
1599 multiply/divide register, or a status register. */
1601 #define GP_REG_FIRST 0
1602 #define GP_REG_LAST 31
1603 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1604 #define GP_DBX_FIRST 0
1606 #define FP_REG_FIRST 32
1607 #define FP_REG_LAST 63
1608 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1609 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1611 #define MD_REG_FIRST 64
1612 #define MD_REG_LAST 65
1613 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1614 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1616 #define ST_REG_FIRST 67
1617 #define ST_REG_LAST 74
1618 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1621 /* FIXME: renumber. */
1622 #define COP0_REG_FIRST 80
1623 #define COP0_REG_LAST 111
1624 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1626 #define COP2_REG_FIRST 112
1627 #define COP2_REG_LAST 143
1628 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1630 #define COP3_REG_FIRST 144
1631 #define COP3_REG_LAST 175
1632 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1633 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1634 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1636 #define AT_REGNUM (GP_REG_FIRST + 1)
1637 #define HI_REGNUM (MD_REG_FIRST + 0)
1638 #define LO_REGNUM (MD_REG_FIRST + 1)
1640 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1641 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1642 should be used instead. */
1643 #define FPSW_REGNUM ST_REG_FIRST
1645 #define GP_REG_P(REGNO) \
1646 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1647 #define M16_REG_P(REGNO) \
1648 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1649 #define FP_REG_P(REGNO) \
1650 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1651 #define MD_REG_P(REGNO) \
1652 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1653 #define ST_REG_P(REGNO) \
1654 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1655 #define COP0_REG_P(REGNO) \
1656 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1657 #define COP2_REG_P(REGNO) \
1658 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1659 #define COP3_REG_P(REGNO) \
1660 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1661 #define ALL_COP_REG_P(REGNO) \
1662 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1664 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1666 /* Return coprocessor number from register number. */
1668 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1669 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1670 : COP3_REG_P (REGNO) ? '3' : '?')
1673 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1675 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1676 array built in override_options. Because machmodes.h is not yet
1677 included before this file is processed, the MODE bound can't be
1680 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1682 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1683 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1685 /* Value is 1 if it is a good idea to tie two pseudo registers
1686 when one has mode MODE1 and one has mode MODE2.
1687 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1688 for any hard reg, then this must be 0 for correct output. */
1689 #define MODES_TIEABLE_P(MODE1, MODE2) \
1690 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1691 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1692 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1693 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1695 /* Register to use for pushing function arguments. */
1696 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1698 /* These two registers don't really exist: they get eliminated to either
1699 the stack or hard frame pointer. */
1700 #define ARG_POINTER_REGNUM 77
1701 #define FRAME_POINTER_REGNUM 78
1703 /* $30 is not available on the mips16, so we use $17 as the frame
1705 #define HARD_FRAME_POINTER_REGNUM \
1706 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1708 /* Value should be nonzero if functions must have frame pointers.
1709 Zero means the frame pointer need not be set up (and parms
1710 may be accessed via the stack pointer) in functions that seem suitable.
1711 This is computed in `reload', in reload1.c. */
1712 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1714 /* Register in which static-chain is passed to a function. */
1715 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1717 /* Registers used as temporaries in prologue/epilogue code. If we're
1718 generating mips16 code, these registers must come from the core set
1719 of 8. The prologue register mustn't conflict with any incoming
1720 arguments, the static chain pointer, or the frame pointer. The
1721 epilogue temporary mustn't conflict with the return registers, the
1722 frame pointer, the EH stack adjustment, or the EH data registers. */
1724 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1725 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1727 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1728 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1730 /* Define this macro if it is as good or better to call a constant
1731 function address than to call an address kept in a register. */
1732 #define NO_FUNCTION_CSE 1
1734 /* The ABI-defined global pointer. Sometimes we use a different
1735 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1736 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1738 /* We normally use $28 as the global pointer. However, when generating
1739 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1740 register instead. They can then avoid saving and restoring $28
1741 and perhaps avoid using a frame at all.
1743 When a leaf function uses something other than $28, mips_expand_prologue
1744 will modify pic_offset_table_rtx in place. Take the register number
1745 from there after reload. */
1746 #define PIC_OFFSET_TABLE_REGNUM \
1747 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1749 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1751 /* Define the classes of registers for register constraints in the
1752 machine description. Also define ranges of constants.
1754 One of the classes must always be named ALL_REGS and include all hard regs.
1755 If there is more than one class, another class must be named NO_REGS
1756 and contain no registers.
1758 The name GENERAL_REGS must be the name of a class (or an alias for
1759 another name such as ALL_REGS). This is the class of registers
1760 that is allowed by "g" or "r" in a register constraint.
1761 Also, registers outside this class are allocated only when
1762 instructions express preferences for them.
1764 The classes must be numbered in nondecreasing order; that is,
1765 a larger-numbered class must never be contained completely
1766 in a smaller-numbered class.
1768 For any two classes, it is very desirable that there be another
1769 class that represents their union. */
1773 NO_REGS, /* no registers in set */
1774 M16_NA_REGS, /* mips16 regs not used to pass args */
1775 M16_REGS, /* mips16 directly accessible registers */
1776 T_REG, /* mips16 T register ($24) */
1777 M16_T_REGS, /* mips16 registers plus T register */
1778 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1779 LEA_REGS, /* Every GPR except $25 */
1780 GR_REGS, /* integer registers */
1781 FP_REGS, /* floating point registers */
1782 HI_REG, /* hi register */
1783 LO_REG, /* lo register */
1784 MD_REGS, /* multiply/divide registers (hi/lo) */
1785 COP0_REGS, /* generic coprocessor classes */
1788 HI_AND_GR_REGS, /* union classes */
1795 ALL_COP_AND_GR_REGS,
1796 ST_REGS, /* status registers (fp status) */
1797 ALL_REGS, /* all registers */
1798 LIM_REG_CLASSES /* max value + 1 */
1801 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1803 #define GENERAL_REGS GR_REGS
1805 /* An initializer containing the names of the register classes as C
1806 string constants. These names are used in writing some of the
1809 #define REG_CLASS_NAMES \
1816 "PIC_FN_ADDR_REG", \
1823 /* coprocessor registers */ \
1830 "COP0_AND_GR_REGS", \
1831 "COP2_AND_GR_REGS", \
1832 "COP3_AND_GR_REGS", \
1834 "ALL_COP_AND_GR_REGS", \
1839 /* An initializer containing the contents of the register classes,
1840 as integers which are bit masks. The Nth integer specifies the
1841 contents of class N. The way the integer MASK is interpreted is
1842 that register R is in the class if `MASK & (1 << R)' is 1.
1844 When the machine has more than 32 registers, an integer does not
1845 suffice. Then the integers are replaced by sub-initializers,
1846 braced groupings containing several integers. Each
1847 sub-initializer must be suitable as an initializer for the type
1848 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1850 #define REG_CLASS_CONTENTS \
1852 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1853 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1854 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1855 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1856 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1857 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1858 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1859 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1860 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1861 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1862 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1863 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1864 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1865 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1866 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1867 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1868 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1869 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1870 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1871 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1872 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1873 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1874 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1875 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1876 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1880 /* A C expression whose value is a register class containing hard
1881 register REGNO. In general there is more that one such class;
1882 choose a class which is "minimal", meaning that no smaller class
1883 also contains the register. */
1885 extern const enum reg_class mips_regno_to_class[];
1887 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1889 /* A macro whose definition is the name of the class to which a
1890 valid base register must belong. A base register is one used in
1891 an address which is the register value plus a displacement. */
1893 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1895 /* A macro whose definition is the name of the class to which a
1896 valid index register must belong. An index register is one used
1897 in an address where its value is either multiplied by a scale
1898 factor or added to another register (as well as added to a
1901 #define INDEX_REG_CLASS NO_REGS
1903 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1904 registers explicitly used in the rtl to be used as spill registers
1905 but prevents the compiler from extending the lifetime of these
1908 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1910 /* This macro is used later on in the file. */
1911 #define GR_REG_CLASS_P(CLASS) \
1912 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1913 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1914 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1916 /* This macro is also used later on in the file. */
1917 #define COP_REG_CLASS_P(CLASS) \
1918 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1920 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1921 is the default value (allocate the registers in numeric order). We
1922 define it just so that we can override it for the mips16 target in
1923 ORDER_REGS_FOR_LOCAL_ALLOC. */
1925 #define REG_ALLOC_ORDER \
1926 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1927 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1928 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1929 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1930 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1931 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1932 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1933 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1934 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1935 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1936 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1939 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1940 to be rearranged based on a particular function. On the mips16, we
1941 want to allocate $24 (T_REG) before other registers for
1942 instructions for which it is possible. */
1944 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1946 /* REGISTER AND CONSTANT CLASSES */
1948 /* Get reg_class from a letter such as appears in the machine
1951 DEFINED REGISTER CLASSES:
1953 'd' General (aka integer) registers
1954 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1955 'y' General registers (in both mips16 and non mips16 mode)
1956 'e' Effective address registers (general registers except $25)
1957 't' mips16 temporary register ($24)
1958 'f' Floating point registers
1961 'x' Multiply/divide registers
1962 'z' FP Status register
1966 'b' All registers */
1968 extern enum reg_class mips_char_to_class[256];
1970 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1972 /* True if VALUE is a signed 16-bit number. */
1974 #define SMALL_OPERAND(VALUE) \
1975 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1977 /* True if VALUE is an unsigned 16-bit number. */
1979 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1980 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1982 /* True if VALUE can be loaded into a register using LUI. */
1984 #define LUI_OPERAND(VALUE) \
1985 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1986 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1988 /* Return a value X with the low 16 bits clear, and such that
1989 VALUE - X is a signed 16-bit value. */
1991 #define CONST_HIGH_PART(VALUE) \
1992 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1994 #define CONST_LOW_PART(VALUE) \
1995 ((VALUE) - CONST_HIGH_PART (VALUE))
1997 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1998 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1999 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2001 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2002 string can be used to stand for particular ranges of immediate
2003 operands. This macro defines what the ranges are. C is the
2004 letter, and VALUE is a constant value. Return 1 if VALUE is
2005 in the range specified by C. */
2009 `I' is used for the range of constants an arithmetic insn can
2010 actually contain (16 bits signed integers).
2012 `J' is used for the range which is just zero (ie, $r0).
2014 `K' is used for the range of constants a logical insn can actually
2015 contain (16 bit zero-extended integers).
2017 `L' is used for the range of constants that be loaded with lui
2018 (ie, the bottom 16 bits are zero).
2020 `M' is used for the range of constants that take two words to load
2021 (ie, not matched by `I', `K', and `L').
2023 `N' is used for negative 16 bit constants other than -65536.
2025 `O' is a 15 bit signed integer.
2027 `P' is used for positive 16 bit constants. */
2029 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2030 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2031 : (C) == 'J' ? ((VALUE) == 0) \
2032 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2033 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2034 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2035 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2036 && !LUI_OPERAND (VALUE)) \
2037 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2038 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2039 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2042 /* Similar, but for floating constants, and defining letters G and H.
2043 Here VALUE is the CONST_DOUBLE rtx itself. */
2047 'G' : Floating point 0 */
2049 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2051 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2053 /* Letters in the range `Q' through `U' may be defined in a
2054 machine-dependent fashion to stand for arbitrary operand types.
2055 The machine description macro `EXTRA_CONSTRAINT' is passed the
2056 operand as its first argument and the constraint letter as its
2059 `Q' is for signed 16-bit constants.
2060 `R' is for single-instruction memory references. Note that this
2061 constraint has often been used in linux and glibc code.
2062 `S' is for legitimate constant call addresses.
2063 `T' is for constant move_operands that cannot be safely loaded into $25.
2064 `U' is for constant move_operands that can be safely loaded into $25.
2065 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2066 This is true for all non-mips16 references (although it can sometimes
2067 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2068 stack and constant-pool references. */
2070 #define EXTRA_CONSTRAINT(OP,CODE) \
2071 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2072 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2073 && mips_fetch_insns (OP) == 1) \
2074 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2075 && call_insn_operand (OP, VOIDmode)) \
2076 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2077 && move_operand (OP, VOIDmode) \
2078 && mips_dangerous_for_la25_p (OP)) \
2079 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2080 && move_operand (OP, VOIDmode) \
2081 && !mips_dangerous_for_la25_p (OP)) \
2082 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2083 && memory_operand (OP, VOIDmode) \
2084 && (!TARGET_MIPS16 \
2085 || (!stack_operand (OP, VOIDmode) \
2086 && !CONSTANT_P (XEXP (OP, 0))))) \
2089 /* Say which of the above are memory constraints. */
2090 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2092 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2093 mips_preferred_reload_class (X, CLASS)
2095 /* Certain machines have the property that some registers cannot be
2096 copied to some other registers without using memory. Define this
2097 macro on those machines to be a C expression that is nonzero if
2098 objects of mode MODE in registers of CLASS1 can only be copied to
2099 registers of class CLASS2 by storing a register of CLASS1 into
2100 memory and loading that memory location into a register of CLASS2.
2102 Do not define this macro if its value would always be zero. */
2104 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2105 ((!TARGET_DEBUG_H_MODE \
2106 && GET_MODE_CLASS (MODE) == MODE_INT \
2107 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2108 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2109 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2110 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2111 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2113 /* The HI and LO registers can only be reloaded via the general
2114 registers. Condition code registers can only be loaded to the
2115 general registers, and from the floating point registers. */
2117 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2118 mips_secondary_reload_class (CLASS, MODE, X, 1)
2119 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2120 mips_secondary_reload_class (CLASS, MODE, X, 0)
2122 /* Return the maximum number of consecutive registers
2123 needed to represent mode MODE in a register of class CLASS. */
2125 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2127 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2128 mips_cannot_change_mode_class (FROM, TO, CLASS)
2130 /* Stack layout; function entry, exit and calling. */
2132 #define STACK_GROWS_DOWNWARD
2134 /* The offset of the first local variable from the beginning of the frame.
2135 See compute_frame_size for details about the frame layout. */
2136 #define STARTING_FRAME_OFFSET \
2137 (current_function_outgoing_args_size \
2138 + (TARGET_ABICALLS && !TARGET_NEWABI \
2139 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2141 #define RETURN_ADDR_RTX mips_return_addr
2143 /* Since the mips16 ISA mode is encoded in the least-significant bit
2144 of the address, mask it off return addresses for purposes of
2145 finding exception handling regions. */
2147 #define MASK_RETURN_ADDR GEN_INT (-2)
2150 /* Similarly, don't use the least-significant bit to tell pointers to
2151 code from vtable index. */
2153 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2155 /* The eliminations to $17 are only used for mips16 code. See the
2156 definition of HARD_FRAME_POINTER_REGNUM. */
2158 #define ELIMINABLE_REGS \
2159 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2160 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2161 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2162 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2163 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2164 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2166 /* We can always eliminate to the hard frame pointer. We can eliminate
2167 to the stack pointer unless a frame pointer is needed.
2169 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2170 reload may be unable to compute the address of a local variable,
2171 since there is no way to add a large constant to the stack pointer
2172 without using a temporary register. */
2173 #define CAN_ELIMINATE(FROM, TO) \
2174 ((TO) == HARD_FRAME_POINTER_REGNUM \
2175 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2176 && (!TARGET_MIPS16 \
2177 || compute_frame_size (get_frame_size ()) < 32768)))
2179 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2180 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2182 /* Allocate stack space for arguments at the beginning of each function. */
2183 #define ACCUMULATE_OUTGOING_ARGS 1
2185 /* The argument pointer always points to the first argument. */
2186 #define FIRST_PARM_OFFSET(FNDECL) 0
2188 /* o32 and o64 reserve stack space for all argument registers. */
2189 #define REG_PARM_STACK_SPACE(FNDECL) \
2191 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2194 /* Define this if it is the responsibility of the caller to
2195 allocate the area reserved for arguments passed in registers.
2196 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2197 of this macro is to determine whether the space is included in
2198 `current_function_outgoing_args_size'. */
2199 #define OUTGOING_REG_PARM_STACK_SPACE
2201 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2203 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2205 /* Symbolic macros for the registers used to return integer and floating
2208 #define GP_RETURN (GP_REG_FIRST + 2)
2209 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2211 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2213 /* Symbolic macros for the first/last argument registers. */
2215 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2216 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2217 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2218 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2220 #define LIBCALL_VALUE(MODE) \
2221 mips_function_value (NULL_TREE, NULL, (MODE))
2223 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2224 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2226 /* 1 if N is a possible register number for a function value.
2227 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2228 Currently, R2 and F0 are only implemented here (C has no complex type) */
2230 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2231 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2232 && (N) == FP_RETURN + 2))
2234 /* 1 if N is a possible register number for function argument passing.
2235 We have no FP argument registers when soft-float. When FP registers
2236 are 32 bits, we can't directly reference the odd numbered ones. */
2238 #define FUNCTION_ARG_REGNO_P(N) \
2239 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2240 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2243 /* This structure has to cope with two different argument allocation
2244 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2245 first N words go in registers and the rest go on the stack. If I < N,
2246 the Ith word might go in Ith integer argument register or the
2247 Ith floating-point one. For these ABIs, we only need to remember
2248 the number of words passed so far.
2250 The EABI instead allocates the integer and floating-point arguments
2251 separately. The first N words of FP arguments go in FP registers,
2252 the rest go on the stack. Likewise, the first N words of the other
2253 arguments go in integer registers, and the rest go on the stack. We
2254 need to maintain three counts: the number of integer registers used,
2255 the number of floating-point registers used, and the number of words
2256 passed on the stack.
2258 We could keep separate information for the two ABIs (a word count for
2259 the standard ABIs, and three separate counts for the EABI). But it
2260 seems simpler to view the standard ABIs as forms of EABI that do not
2261 allocate floating-point registers.
2263 So for the standard ABIs, the first N words are allocated to integer
2264 registers, and function_arg decides on an argument-by-argument basis
2265 whether that argument should really go in an integer register, or in
2266 a floating-point one. */
2268 typedef struct mips_args {
2269 /* Always true for varargs functions. Otherwise true if at least
2270 one argument has been passed in an integer register. */
2273 /* The number of arguments seen so far. */
2274 unsigned int arg_number;
2276 /* For EABI, the number of integer registers used so far. For other
2277 ABIs, the number of words passed in registers (whether integer
2278 or floating-point). */
2279 unsigned int num_gprs;
2281 /* For EABI, the number of floating-point registers used so far. */
2282 unsigned int num_fprs;
2284 /* The number of words passed on the stack. */
2285 unsigned int stack_words;
2287 /* On the mips16, we need to keep track of which floating point
2288 arguments were passed in general registers, but would have been
2289 passed in the FP regs if this were a 32 bit function, so that we
2290 can move them to the FP regs if we wind up calling a 32 bit
2291 function. We record this information in fp_code, encoded in base
2292 four. A zero digit means no floating point argument, a one digit
2293 means an SFmode argument, and a two digit means a DFmode argument,
2294 and a three digit is not used. The low order digit is the first
2295 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2296 an SFmode argument. ??? A more sophisticated approach will be
2297 needed if MIPS_ABI != ABI_32. */
2300 /* True if the function has a prototype. */
2304 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2305 for a call to a function whose data type is FNTYPE.
2306 For a library call, FNTYPE is 0. */
2308 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2309 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2311 /* Update the data in CUM to advance over an argument
2312 of mode MODE and data type TYPE.
2313 (TYPE is null for libcalls where that information may not be available.) */
2315 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2316 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2318 /* Determine where to put an argument to a function.
2319 Value is zero to push the argument on the stack,
2320 or a hard register in which to store the argument.
2322 MODE is the argument's machine mode.
2323 TYPE is the data type of the argument (as a tree).
2324 This is null for libcalls where that information may
2326 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2327 the preceding args and about the function being called.
2328 NAMED is nonzero if this argument is a named parameter
2329 (otherwise it is an extra parameter matching an ellipsis). */
2331 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2332 function_arg( &CUM, MODE, TYPE, NAMED)
2334 /* For an arg passed partly in registers and partly in memory,
2335 this is the number of registers used.
2336 For args passed entirely in registers or entirely in memory, zero. */
2338 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2339 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2341 /* If defined, a C expression that gives the alignment boundary, in
2342 bits, of an argument with the specified mode and type. If it is
2343 not defined, `PARM_BOUNDARY' is used for all arguments. */
2345 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2347 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2349 : TYPE_ALIGN(TYPE)) \
2350 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2352 : GET_MODE_ALIGNMENT(MODE)))
2354 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2355 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2357 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2358 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2360 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2361 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2363 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2364 (mips_abi == ABI_EABI && (NAMED) \
2365 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2367 /* True if using EABI and varargs can be passed in floating-point
2368 registers. Under these conditions, we need a more complex form
2369 of va_list, which tracks GPR, FPR and stack arguments separately. */
2370 #define EABI_FLOAT_VARARGS_P \
2371 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2374 /* Say that the epilogue uses the return address register. Note that
2375 in the case of sibcalls, the values "used by the epilogue" are
2376 considered live at the start of the called function. */
2377 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2379 /* Treat LOC as a byte offset from the stack pointer and round it up
2380 to the next fully-aligned offset. */
2381 #define MIPS_STACK_ALIGN(LOC) \
2382 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2383 ? ((LOC) + 7) & ~7 \
2384 : ((LOC) + 15) & ~15)
2387 /* Implement `va_start' for varargs and stdarg. */
2388 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2389 mips_va_start (valist, nextarg)
2391 /* Implement `va_arg'. */
2392 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2393 mips_va_arg (valist, type)
2395 /* Output assembler code to FILE to increment profiler label # LABELNO
2396 for profiling a function entry. */
2398 #define FUNCTION_PROFILER(FILE, LABELNO) \
2400 if (TARGET_MIPS16) \
2401 sorry ("mips16 function profiling"); \
2402 fprintf (FILE, "\t.set\tnoat\n"); \
2403 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2404 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2405 if (!TARGET_NEWABI) \
2408 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2409 TARGET_64BIT ? "dsubu" : "subu", \
2410 reg_names[STACK_POINTER_REGNUM], \
2411 reg_names[STACK_POINTER_REGNUM], \
2412 Pmode == DImode ? 16 : 8); \
2414 fprintf (FILE, "\tjal\t_mcount\n"); \
2415 fprintf (FILE, "\t.set\tat\n"); \
2418 /* Define this macro if the code for function profiling should come
2419 before the function prologue. Normally, the profiling code comes
2422 /* #define PROFILE_BEFORE_PROLOGUE */
2424 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2425 the stack pointer does not matter. The value is tested only in
2426 functions that have frame pointers.
2427 No definition is equivalent to always zero. */
2429 #define EXIT_IGNORE_STACK 1
2432 /* A C statement to output, on the stream FILE, assembler code for a
2433 block of data that contains the constant parts of a trampoline.
2434 This code should not include a label--the label is taken care of
2437 #define TRAMPOLINE_TEMPLATE(STREAM) \
2439 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2440 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2441 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2442 if (ptr_mode == DImode) \
2444 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2445 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2449 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2450 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2452 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2453 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2454 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2455 if (ptr_mode == DImode) \
2457 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2458 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2462 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2463 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2467 /* A C expression for the size in bytes of the trampoline, as an
2470 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2472 /* Alignment required for trampolines, in bits. */
2474 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2476 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2477 program and data caches. */
2479 #ifndef CACHE_FLUSH_FUNC
2480 #define CACHE_FLUSH_FUNC "_flush_cache"
2483 /* A C statement to initialize the variable parts of a trampoline.
2484 ADDR is an RTX for the address of the trampoline; FNADDR is an
2485 RTX for the address of the nested function; STATIC_CHAIN is an
2486 RTX for the static chain value that should be passed to the
2487 function when it is called. */
2489 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2491 rtx func_addr, chain_addr; \
2493 func_addr = plus_constant (ADDR, 32); \
2494 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2495 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2496 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2498 /* Flush both caches. We need to flush the data cache in case \
2499 the system has a write-back cache. */ \
2500 /* ??? Should check the return value for errors. */ \
2501 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2502 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2503 0, VOIDmode, 3, ADDR, Pmode, \
2504 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2505 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2508 /* Addressing modes, and classification of registers for them. */
2510 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2511 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2512 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2514 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2515 and check its validity for a certain class.
2516 We have two alternate definitions for each of them.
2517 The usual definition accepts all pseudo regs; the other rejects them all.
2518 The symbol REG_OK_STRICT causes the latter definition to be used.
2520 Most source files want to accept pseudo regs in the hope that
2521 they will get allocated to the class that the insn wants them to be in.
2522 Some source files that are used after register allocation
2523 need to be strict. */
2525 #ifndef REG_OK_STRICT
2526 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2527 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2529 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2530 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2533 #define REG_OK_FOR_INDEX_P(X) 0
2536 /* Maximum number of registers that can appear in a valid memory address. */
2538 #define MAX_REGS_PER_ADDRESS 1
2540 #ifdef REG_OK_STRICT
2541 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2543 if (mips_legitimate_address_p (MODE, X, 1)) \
2547 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2549 if (mips_legitimate_address_p (MODE, X, 0)) \
2554 /* Check for constness inline but use mips_legitimate_address_p
2555 to check whether a constant really is an address. */
2557 #define CONSTANT_ADDRESS_P(X) \
2558 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2560 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2562 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2564 if (mips_legitimize_address (&(X), MODE)) \
2569 /* A C statement or compound statement with a conditional `goto
2570 LABEL;' executed if memory address X (an RTX) can have different
2571 meanings depending on the machine mode of the memory reference it
2574 Autoincrement and autodecrement addresses typically have
2575 mode-dependent effects because the amount of the increment or
2576 decrement is the size of the operand being addressed. Some
2577 machines have other mode-dependent addresses. Many RISC machines
2578 have no mode-dependent addresses.
2580 You may assume that ADDR is a valid address for the machine. */
2582 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2584 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2585 'the start of the function that this code is output in'. */
2587 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2588 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2589 asm_fprintf ((FILE), "%U%s", \
2590 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2592 asm_fprintf ((FILE), "%U%s", (NAME))
2594 /* Specify the machine mode that this machine uses
2595 for the index in the tablejump instruction.
2596 ??? Using HImode in mips16 mode can cause overflow. */
2597 #define CASE_VECTOR_MODE \
2598 (TARGET_MIPS16 ? HImode : ptr_mode)
2600 /* Define as C expression which evaluates to nonzero if the tablejump
2601 instruction expects the table to contain offsets from the address of the
2603 Do not define this if the table should contain absolute addresses. */
2604 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2606 /* Define this as 1 if `char' should by default be signed; else as 0. */
2607 #ifndef DEFAULT_SIGNED_CHAR
2608 #define DEFAULT_SIGNED_CHAR 1
2611 /* Max number of bytes we can move from memory to memory
2612 in one reasonably fast instruction. */
2613 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2614 #define MAX_MOVE_MAX 8
2616 /* Define this macro as a C expression which is nonzero if
2617 accessing less than a word of memory (i.e. a `char' or a
2618 `short') is no faster than accessing a word of memory, i.e., if
2619 such access require more than one instruction or if there is no
2620 difference in cost between byte and (aligned) word loads.
2622 On RISC machines, it tends to generate better code to define
2623 this as 1, since it avoids making a QI or HI mode register. */
2624 #define SLOW_BYTE_ACCESS 1
2626 /* Define this to be nonzero if shift instructions ignore all but the low-order
2628 #define SHIFT_COUNT_TRUNCATED 1
2630 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2631 is done just by pretending it is already truncated. */
2632 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2633 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2636 /* Specify the machine mode that pointers have.
2637 After generation of rtl, the compiler makes no further distinction
2638 between pointers and any other objects of this machine mode. */
2641 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2644 /* Give call MEMs SImode since it is the "most permissive" mode
2645 for both 32-bit and 64-bit targets. */
2647 #define FUNCTION_MODE SImode
2650 /* The cost of loading values from the constant pool. It should be
2651 larger than the cost of any constant we want to synthesize in-line. */
2653 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2655 /* A C expression for the cost of moving data from a register in
2656 class FROM to one in class TO. The classes are expressed using
2657 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2658 the default; other values are interpreted relative to that.
2660 It is not required that the cost always equal 2 when FROM is the
2661 same as TO; on some machines it is expensive to move between
2662 registers if they are not general registers.
2664 If reload sees an insn consisting of a single `set' between two
2665 hard registers, and if `REGISTER_MOVE_COST' applied to their
2666 classes returns a value of 2, reload does not check to ensure
2667 that the constraints of the insn are met. Setting a cost of
2668 other than 2 will allow reload to verify that the constraints are
2669 met. You should do this if the `movM' pattern's constraints do
2670 not allow such copying. */
2672 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2673 mips_register_move_cost (MODE, FROM, TO)
2675 /* ??? Fix this to be right for the R8000. */
2676 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2677 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2678 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2680 /* Define if copies to/from condition code registers should be avoided.
2682 This is needed for the MIPS because reload_outcc is not complete;
2683 it needs to handle cases where the source is a general or another
2684 condition code register. */
2685 #define AVOID_CCMODE_COPIES
2687 /* A C expression for the cost of a branch instruction. A value of
2688 1 is the default; other values are interpreted relative to that. */
2690 /* ??? Fix this to be right for the R8000. */
2691 #define BRANCH_COST \
2693 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2696 /* If defined, modifies the length assigned to instruction INSN as a
2697 function of the context in which it is used. LENGTH is an lvalue
2698 that contains the initially computed length of the insn and should
2699 be updated with the correct length of the insn. */
2700 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2701 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2704 /* Optionally define this if you have added predicates to
2705 `MACHINE.c'. This macro is called within an initializer of an
2706 array of structures. The first field in the structure is the
2707 name of a predicate and the second field is an array of rtl
2708 codes. For each predicate, list all rtl codes that can be in
2709 expressions matched by the predicate. The list should have a
2710 trailing comma. Here is an example of two entries in the list
2711 for a typical RISC machine:
2713 #define PREDICATE_CODES \
2714 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2715 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2717 Defining this macro does not affect the generated code (however,
2718 incorrect definitions that omit an rtl code that may be matched
2719 by the predicate can cause the compiler to malfunction).
2720 Instead, it allows the table built by `genrecog' to be more
2721 compact and efficient, thus speeding up the compiler. The most
2722 important predicates to include in the list specified by this
2723 macro are thoses used in the most insn patterns. */
2725 #define PREDICATE_CODES \
2726 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
2727 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2728 {"general_symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2729 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2730 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2731 {"const_arith_operand", { CONST_INT }}, \
2732 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2733 UNSPEC_VOLATILE }}, \
2734 {"arith_operand", { REG, CONST_INT, CONST, SUBREG }}, \
2735 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
2736 {"small_int", { CONST_INT }}, \
2737 {"const_float_1_operand", { CONST_DOUBLE }}, \
2738 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2739 {"equality_op", { EQ, NE }}, \
2740 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2742 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2743 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2744 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2745 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2746 SYMBOL_REF, LABEL_REF, SUBREG, \
2748 {"stack_operand", { MEM }}, \
2749 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2750 CONST_DOUBLE, CONST }}, \
2751 {"fcc_register_operand", { REG, SUBREG }}, \
2752 {"hilo_operand", { REG }}, \
2753 {"macc_msac_operand", { PLUS, MINUS }}, \
2754 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2756 /* A list of predicates that do special things with modes, and so
2757 should not elicit warnings for VOIDmode match_operand. */
2759 #define SPECIAL_MODE_PREDICATES \
2760 "pc_or_label_operand",
2762 /* Control the assembler format that we output. */
2764 /* Output to assembler file text saying following lines
2765 may contain character constants, extra white space, comments, etc. */
2768 #define ASM_APP_ON " #APP\n"
2771 /* Output to assembler file text saying following lines
2772 no longer contain unusual constructs. */
2775 #define ASM_APP_OFF " #NO_APP\n"
2778 #define REGISTER_NAMES \
2779 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2780 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2781 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2782 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2783 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2784 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2785 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2786 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2787 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2788 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2789 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2790 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2791 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2792 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2793 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2794 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2795 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2796 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2797 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2798 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2799 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2800 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2802 /* List the "software" names for each register. Also list the numerical
2803 names for $fp and $sp. */
2805 #define ADDITIONAL_REGISTER_NAMES \
2807 { "$29", 29 + GP_REG_FIRST }, \
2808 { "$30", 30 + GP_REG_FIRST }, \
2809 { "at", 1 + GP_REG_FIRST }, \
2810 { "v0", 2 + GP_REG_FIRST }, \
2811 { "v1", 3 + GP_REG_FIRST }, \
2812 { "a0", 4 + GP_REG_FIRST }, \
2813 { "a1", 5 + GP_REG_FIRST }, \
2814 { "a2", 6 + GP_REG_FIRST }, \
2815 { "a3", 7 + GP_REG_FIRST }, \
2816 { "t0", 8 + GP_REG_FIRST }, \
2817 { "t1", 9 + GP_REG_FIRST }, \
2818 { "t2", 10 + GP_REG_FIRST }, \
2819 { "t3", 11 + GP_REG_FIRST }, \
2820 { "t4", 12 + GP_REG_FIRST }, \
2821 { "t5", 13 + GP_REG_FIRST }, \
2822 { "t6", 14 + GP_REG_FIRST }, \
2823 { "t7", 15 + GP_REG_FIRST }, \
2824 { "s0", 16 + GP_REG_FIRST }, \
2825 { "s1", 17 + GP_REG_FIRST }, \
2826 { "s2", 18 + GP_REG_FIRST }, \
2827 { "s3", 19 + GP_REG_FIRST }, \
2828 { "s4", 20 + GP_REG_FIRST }, \
2829 { "s5", 21 + GP_REG_FIRST }, \
2830 { "s6", 22 + GP_REG_FIRST }, \
2831 { "s7", 23 + GP_REG_FIRST }, \
2832 { "t8", 24 + GP_REG_FIRST }, \
2833 { "t9", 25 + GP_REG_FIRST }, \
2834 { "k0", 26 + GP_REG_FIRST }, \
2835 { "k1", 27 + GP_REG_FIRST }, \
2836 { "gp", 28 + GP_REG_FIRST }, \
2837 { "sp", 29 + GP_REG_FIRST }, \
2838 { "fp", 30 + GP_REG_FIRST }, \
2839 { "ra", 31 + GP_REG_FIRST }, \
2840 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2843 /* This is meant to be redefined in the host dependent files. It is a
2844 set of alternative names and regnums for mips coprocessors. */
2846 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2848 /* A C compound statement to output to stdio stream STREAM the
2849 assembler syntax for an instruction operand X. X is an RTL
2852 CODE is a value that can be used to specify one of several ways
2853 of printing the operand. It is used when identical operands
2854 must be printed differently depending on the context. CODE
2855 comes from the `%' specification that was used to request
2856 printing of the operand. If the specification was just `%DIGIT'
2857 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2858 is the ASCII code for LTR.
2860 If X is a register, this macro should print the register's name.
2861 The names can be found in an array `reg_names' whose type is
2862 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2864 When the machine description has a specification `%PUNCT' (a `%'
2865 followed by a punctuation character), this macro is called with
2866 a null pointer for X and the punctuation character for CODE.
2868 See mips.c for the MIPS specific codes. */
2870 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2872 /* A C expression which evaluates to true if CODE is a valid
2873 punctuation character for use in the `PRINT_OPERAND' macro. If
2874 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2875 punctuation characters (except for the standard one, `%') are
2876 used in this way. */
2878 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2880 /* A C compound statement to output to stdio stream STREAM the
2881 assembler syntax for an instruction operand that is a memory
2882 reference whose address is ADDR. ADDR is an RTL expression. */
2884 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2887 /* A C statement, to be executed after all slot-filler instructions
2888 have been output. If necessary, call `dbr_sequence_length' to
2889 determine the number of slots filled in a sequence (zero if not
2890 currently outputting a sequence), to decide how many no-ops to
2891 output, or whatever.
2893 Don't define this macro if it has nothing to do, but it is
2894 helpful in reading assembly output if the extent of the delay
2895 sequence is made explicit (e.g. with white space).
2897 Note that output routines for instructions with delay slots must
2898 be prepared to deal with not being output as part of a sequence
2899 (i.e. when the scheduling pass is not run, or when no slot
2900 fillers could be found.) The variable `final_sequence' is null
2901 when not processing a sequence, otherwise it contains the
2902 `sequence' rtx being output. */
2904 #define DBR_OUTPUT_SEQEND(STREAM) \
2907 if (set_nomacro > 0 && --set_nomacro == 0) \
2908 fputs ("\t.set\tmacro\n", STREAM); \
2910 if (set_noreorder > 0 && --set_noreorder == 0) \
2911 fputs ("\t.set\treorder\n", STREAM); \
2913 fputs ("\n", STREAM); \
2918 /* How to tell the debugger about changes of source files. */
2920 #ifndef SET_FILE_NUMBER
2921 #define SET_FILE_NUMBER() ++num_source_filenames
2924 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2925 mips_output_filename (STREAM, NAME)
2927 /* This is defined so that it can be overridden in iris6.h. */
2928 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
2931 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
2932 output_quoted_string (STREAM, NAME); \
2933 fputs ("\n", STREAM); \
2937 /* This is how to output a note the debugger telling it the line number
2938 to which the following sequence of instructions corresponds.
2939 Silicon graphics puts a label after each .loc. */
2941 #ifndef LABEL_AFTER_LOC
2942 #define LABEL_AFTER_LOC(STREAM)
2945 #ifndef ASM_OUTPUT_SOURCE_LINE
2946 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
2947 mips_output_lineno (STREAM, LINE)
2950 /* The MIPS implementation uses some labels for its own purpose. The
2951 following lists what labels are created, and are all formed by the
2952 pattern $L[a-z].*. The machine independent portion of GCC creates
2953 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2955 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2956 $Lb[0-9]+ Begin blocks for MIPS debug support
2957 $Lc[0-9]+ Label for use in s<xx> operation.
2958 $Le[0-9]+ End blocks for MIPS debug support */
2960 #undef ASM_DECLARE_OBJECT_NAME
2961 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2962 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2964 /* Globalizing directive for a label. */
2965 #define GLOBAL_ASM_OP "\t.globl\t"
2967 /* This says how to define a global common symbol. */
2969 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2971 /* This says how to define a local common symbol (ie, not visible to
2974 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2975 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2976 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2979 /* This says how to output an external. It would be possible not to
2980 output anything and let undefined symbol become external. However
2981 the assembler uses length information on externals to allocate in
2982 data/sdata bss/sbss, thereby saving exec time. */
2984 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2985 mips_output_external(STREAM,DECL,NAME)
2987 /* This is how to declare a function name. The actual work of
2988 emitting the label is moved to function_prologue, so that we can
2989 get the line number correctly emitted before the .ent directive,
2990 and after any .file directives. Define as empty so that the function
2991 is not declared before the .ent directive elsewhere. */
2993 #undef ASM_DECLARE_FUNCTION_NAME
2994 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2996 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2997 #define FUNCTION_NAME_ALREADY_DECLARED 0
3000 /* This is how to store into the string LABEL
3001 the symbol_ref name of an internal numbered label where
3002 PREFIX is the class of label and NUM is the number within the class.
3003 This is suitable for output with `assemble_name'. */
3005 #undef ASM_GENERATE_INTERNAL_LABEL
3006 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3007 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3009 /* This is how to output an element of a case-vector that is absolute. */
3011 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3012 fprintf (STREAM, "\t%s\t%sL%d\n", \
3013 ptr_mode == DImode ? ".dword" : ".word", \
3014 LOCAL_LABEL_PREFIX, \
3017 /* This is how to output an element of a case-vector. We can make the
3018 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
3021 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3023 if (TARGET_MIPS16) \
3024 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3025 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3026 else if (TARGET_GPWORD) \
3027 fprintf (STREAM, "\t%s\t%sL%d\n", \
3028 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3029 LOCAL_LABEL_PREFIX, VALUE); \
3031 fprintf (STREAM, "\t%s\t%sL%d\n", \
3032 ptr_mode == DImode ? ".dword" : ".word", \
3033 LOCAL_LABEL_PREFIX, VALUE); \
3036 /* When generating mips16 code we want to put the jump table in the .text
3037 section. In all other cases, we want to put the jump table in the .rdata
3038 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
3039 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
3040 to the .text section if appropriate. */
3041 #undef ASM_OUTPUT_CASE_LABEL
3042 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3044 if (TARGET_MIPS16) \
3045 function_section (current_function_decl); \
3046 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3049 /* This is how to output an assembler line
3050 that says to advance the location counter
3051 to a multiple of 2**LOG bytes. */
3053 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3054 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3056 /* This is how to output an assembler line to advance the location
3057 counter by SIZE bytes. */
3059 #undef ASM_OUTPUT_SKIP
3060 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3061 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3063 /* This is how to output a string. */
3064 #undef ASM_OUTPUT_ASCII
3065 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3066 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3068 /* Output #ident as a in the read-only data section. */
3069 #undef ASM_OUTPUT_IDENT
3070 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3072 const char *p = STRING; \
3073 int size = strlen (p) + 1; \
3074 readonly_data_section (); \
3075 assemble_string (p, size); \
3078 /* Default to -G 8 */
3079 #ifndef MIPS_DEFAULT_GVALUE
3080 #define MIPS_DEFAULT_GVALUE 8
3083 /* Define the strings to put out for each section in the object file. */
3084 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3085 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3086 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3088 #undef READONLY_DATA_SECTION_ASM_OP
3089 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3091 /* Given a decl node or constant node, choose the section to output it in
3092 and select that section. */
3094 #undef TARGET_ASM_SELECT_SECTION
3095 #define TARGET_ASM_SELECT_SECTION mips_select_section
3097 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3100 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3101 TARGET_64BIT ? "dsubu" : "subu", \
3102 reg_names[STACK_POINTER_REGNUM], \
3103 reg_names[STACK_POINTER_REGNUM], \
3104 TARGET_64BIT ? "sd" : "sw", \
3106 reg_names[STACK_POINTER_REGNUM]); \
3110 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3113 if (! set_noreorder) \
3114 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3116 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3117 TARGET_64BIT ? "ld" : "lw", \
3119 reg_names[STACK_POINTER_REGNUM], \
3120 TARGET_64BIT ? "daddu" : "addu", \
3121 reg_names[STACK_POINTER_REGNUM], \
3122 reg_names[STACK_POINTER_REGNUM]); \
3124 if (! set_noreorder) \
3125 fprintf (STREAM, "\t.set\treorder\n"); \
3129 /* How to start an assembler comment.
3130 The leading space is important (the mips native assembler requires it). */
3131 #ifndef ASM_COMMENT_START
3132 #define ASM_COMMENT_START " #"
3135 /* Default definitions for size_t and ptrdiff_t. We must override the
3136 definitions from ../svr4.h on mips-*-linux-gnu. */
3139 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3142 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3144 /* See mips_expand_prologue's use of loadgp for when this should be
3147 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3150 /* Since the bits of the _init and _fini function is spread across
3151 many object files, each potentially with its own GP, we must assume
3152 we need to load our GP. We don't preserve $gp or $ra, since each
3153 init/fini chunk is supposed to initialize $gp, and crti/crtn
3154 already take care of preserving $ra and, when appropriate, $gp. */
3155 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3156 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3157 asm (SECTION_OP "\n\
3163 jal " USER_LABEL_PREFIX #FUNC "\n\
3164 " TEXT_SECTION_ASM_OP);
3165 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3166 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3167 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3168 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3169 asm (SECTION_OP "\n\
3174 .cpsetup $31, $2, 1b\n\
3175 jal " USER_LABEL_PREFIX #FUNC "\n\
3176 " TEXT_SECTION_ASM_OP);