1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static int mips_symbol_insns (enum mips_symbol_type);
278 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
279 static rtx mips_force_temporary (rtx, rtx);
280 static rtx mips_split_symbol (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
289 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
290 static int m16_check_op (rtx, int, int, int);
291 static bool mips_rtx_costs (rtx, int, int, int *);
292 static int mips_address_cost (rtx);
293 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
294 static void mips_load_call_address (rtx, rtx, int);
295 static bool mips_function_ok_for_sibcall (tree, tree);
296 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
297 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
298 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
299 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
300 tree, int, struct mips_arg_info *);
301 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
302 static void mips_set_architecture (const struct mips_cpu_info *);
303 static void mips_set_tune (const struct mips_cpu_info *);
304 static bool mips_handle_option (size_t, const char *, int);
305 static struct machine_function *mips_init_machine_status (void);
306 static void print_operand_reloc (FILE *, rtx, const char **);
308 static void irix_output_external_libcall (rtx);
310 static void mips_file_start (void);
311 static void mips_file_end (void);
312 static bool mips_rewrite_small_data_p (rtx);
313 static int mips_small_data_pattern_1 (rtx *, void *);
314 static int mips_rewrite_small_data_1 (rtx *, void *);
315 static bool mips_function_has_gp_insn (void);
316 static unsigned int mips_global_pointer (void);
317 static bool mips_save_reg_p (unsigned int);
318 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
319 mips_save_restore_fn);
320 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
321 static void mips_output_cplocal (void);
322 static void mips_emit_loadgp (void);
323 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
324 static void mips_set_frame_expr (rtx);
325 static rtx mips_frame_set (rtx, rtx);
326 static void mips_save_reg (rtx, rtx);
327 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
328 static void mips_restore_reg (rtx, rtx);
329 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
330 HOST_WIDE_INT, tree);
331 static int symbolic_expression_p (rtx);
332 static section *mips_select_rtx_section (enum machine_mode, rtx,
333 unsigned HOST_WIDE_INT);
334 static section *mips_function_rodata_section (tree);
335 static bool mips_in_small_data_p (tree);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
413 /* Structure to be filled in by compute_frame_size with register
414 save masks, and offsets for the current function. */
416 struct mips_frame_info GTY(())
418 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
419 HOST_WIDE_INT var_size; /* # bytes that variables take up */
420 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
421 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
422 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
423 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
424 unsigned int mask; /* mask of saved gp registers */
425 unsigned int fmask; /* mask of saved fp registers */
426 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
427 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
428 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
429 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
430 bool initialized; /* true if frame size already calculated */
431 int num_gp; /* number of gp registers saved */
432 int num_fp; /* number of fp registers saved */
435 struct machine_function GTY(()) {
436 /* Pseudo-reg holding the value of $28 in a mips16 function which
437 refers to GP relative global variables. */
438 rtx mips16_gp_pseudo_rtx;
440 /* The number of extra stack bytes taken up by register varargs.
441 This area is allocated by the callee at the very top of the frame. */
444 /* Current frame information, calculated by compute_frame_size. */
445 struct mips_frame_info frame;
447 /* The register to use as the global pointer within this function. */
448 unsigned int global_pointer;
450 /* True if mips_adjust_insn_length should ignore an instruction's
452 bool ignore_hazard_length_p;
454 /* True if the whole function is suitable for .set noreorder and
456 bool all_noreorder_p;
458 /* True if the function is known to have an instruction that needs $gp. */
462 /* Information about a single argument. */
465 /* True if the argument is passed in a floating-point register, or
466 would have been if we hadn't run out of registers. */
469 /* The number of words passed in registers, rounded up. */
470 unsigned int reg_words;
472 /* For EABI, the offset of the first register from GP_ARG_FIRST or
473 FP_ARG_FIRST. For other ABIs, the offset of the first register from
474 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
475 comment for details).
477 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
479 unsigned int reg_offset;
481 /* The number of words that must be passed on the stack, rounded up. */
482 unsigned int stack_words;
484 /* The offset from the start of the stack overflow area of the argument's
485 first stack word. Only meaningful when STACK_WORDS is nonzero. */
486 unsigned int stack_offset;
490 /* Information about an address described by mips_address_type.
496 REG is the base register and OFFSET is the constant offset.
499 REG is the register that contains the high part of the address,
500 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
501 is the type of OFFSET's symbol.
504 SYMBOL_TYPE is the type of symbol being referenced. */
506 struct mips_address_info
508 enum mips_address_type type;
511 enum mips_symbol_type symbol_type;
515 /* One stage in a constant building sequence. These sequences have
519 A = A CODE[1] VALUE[1]
520 A = A CODE[2] VALUE[2]
523 where A is an accumulator, each CODE[i] is a binary rtl operation
524 and each VALUE[i] is a constant integer. */
525 struct mips_integer_op {
527 unsigned HOST_WIDE_INT value;
531 /* The largest number of operations needed to load an integer constant.
532 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
533 When the lowest bit is clear, we can try, but reject a sequence with
534 an extra SLL at the end. */
535 #define MIPS_MAX_INTEGER_OPS 7
538 /* Global variables for machine-dependent things. */
540 /* Threshold for data being put into the small data/bss area, instead
541 of the normal data area. */
542 int mips_section_threshold = -1;
544 /* Count the number of .file directives, so that .loc is up to date. */
545 int num_source_filenames = 0;
547 /* Count the number of sdb related labels are generated (to find block
548 start and end boundaries). */
549 int sdb_label_count = 0;
551 /* Next label # for each statement for Silicon Graphics IRIS systems. */
554 /* Linked list of all externals that are to be emitted when optimizing
555 for the global pointer if they haven't been declared by the end of
556 the program with an appropriate .comm or initialization. */
558 struct extern_list GTY (())
560 struct extern_list *next; /* next external */
561 const char *name; /* name of the external */
562 int size; /* size in bytes */
565 static GTY (()) struct extern_list *extern_head = 0;
567 /* Name of the file containing the current function. */
568 const char *current_function_file = "";
570 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
576 /* The next branch instruction is a branch likely, not branch normal. */
577 int mips_branch_likely;
579 /* The operands passed to the last cmpMM expander. */
582 /* The target cpu for code generation. */
583 enum processor_type mips_arch;
584 const struct mips_cpu_info *mips_arch_info;
586 /* The target cpu for optimization and scheduling. */
587 enum processor_type mips_tune;
588 const struct mips_cpu_info *mips_tune_info;
590 /* Which instruction set architecture to use. */
593 /* Which ABI to use. */
594 int mips_abi = MIPS_ABI_DEFAULT;
596 /* Cost information to use. */
597 const struct mips_rtx_cost_data *mips_cost;
599 /* Whether we are generating mips16 hard float code. In mips16 mode
600 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
601 -msoft-float was not specified by the user, which means that we
602 should arrange to call mips32 hard floating point code. */
603 int mips16_hard_float;
605 /* The architecture selected by -mipsN. */
606 static const struct mips_cpu_info *mips_isa_info;
608 /* If TRUE, we split addresses into their high and low parts in the RTL. */
609 int mips_split_addresses;
611 /* Mode used for saving/restoring general purpose registers. */
612 static enum machine_mode gpr_mode;
614 /* Array giving truth value on whether or not a given hard register
615 can support a given mode. */
616 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
618 /* List of all MIPS punctuation characters used by print_operand. */
619 char mips_print_operand_punct[256];
621 /* Map GCC register number to debugger register number. */
622 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
624 /* A copy of the original flag_delayed_branch: see override_options. */
625 static int mips_flag_delayed_branch;
627 static GTY (()) int mips_output_filename_first_time = 1;
629 /* mips_split_p[X] is true if symbols of type X can be split by
630 mips_split_symbol(). */
631 static bool mips_split_p[NUM_SYMBOL_TYPES];
633 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
634 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
635 if they are matched by a special .md file pattern. */
636 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
638 /* Likewise for HIGHs. */
639 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
641 /* Map hard register number to register class */
642 const enum reg_class mips_regno_to_class[] =
644 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
645 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
646 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
649 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
650 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
651 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
652 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 HI_REG, LO_REG, NO_REGS, ST_REGS,
661 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
663 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
664 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
690 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
693 /* Table of machine dependent attributes. */
694 const struct attribute_spec mips_attribute_table[] =
696 { "long_call", 0, 0, false, true, true, NULL },
697 { NULL, 0, 0, false, false, false, NULL }
700 /* A table describing all the processors gcc knows about. Names are
701 matched in the order listed. The first mention of an ISA level is
702 taken as the canonical name for that ISA.
704 To ease comparison, please keep this table in the same order as
705 gas's mips_cpu_info_table[]. */
706 const struct mips_cpu_info mips_cpu_info_table[] = {
707 /* Entries for generic ISAs */
708 { "mips1", PROCESSOR_R3000, 1 },
709 { "mips2", PROCESSOR_R6000, 2 },
710 { "mips3", PROCESSOR_R4000, 3 },
711 { "mips4", PROCESSOR_R8000, 4 },
712 { "mips32", PROCESSOR_4KC, 32 },
713 { "mips32r2", PROCESSOR_M4K, 33 },
714 { "mips64", PROCESSOR_5KC, 64 },
717 { "r3000", PROCESSOR_R3000, 1 },
718 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
719 { "r3900", PROCESSOR_R3900, 1 },
722 { "r6000", PROCESSOR_R6000, 2 },
725 { "r4000", PROCESSOR_R4000, 3 },
726 { "vr4100", PROCESSOR_R4100, 3 },
727 { "vr4111", PROCESSOR_R4111, 3 },
728 { "vr4120", PROCESSOR_R4120, 3 },
729 { "vr4130", PROCESSOR_R4130, 3 },
730 { "vr4300", PROCESSOR_R4300, 3 },
731 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
732 { "r4600", PROCESSOR_R4600, 3 },
733 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
734 { "r4650", PROCESSOR_R4650, 3 },
737 { "r8000", PROCESSOR_R8000, 4 },
738 { "vr5000", PROCESSOR_R5000, 4 },
739 { "vr5400", PROCESSOR_R5400, 4 },
740 { "vr5500", PROCESSOR_R5500, 4 },
741 { "rm7000", PROCESSOR_R7000, 4 },
742 { "rm9000", PROCESSOR_R9000, 4 },
745 { "4kc", PROCESSOR_4KC, 32 },
746 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
747 { "4kp", PROCESSOR_4KP, 32 },
749 /* MIPS32 Release 2 */
750 { "m4k", PROCESSOR_M4K, 33 },
751 { "24k", PROCESSOR_24K, 33 },
752 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
753 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
754 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
757 { "5kc", PROCESSOR_5KC, 64 },
758 { "5kf", PROCESSOR_5KF, 64 },
759 { "20kc", PROCESSOR_20KC, 64 },
760 { "sb1", PROCESSOR_SB1, 64 },
761 { "sr71000", PROCESSOR_SR71000, 64 },
767 /* Default costs. If these are used for a processor we should look
768 up the actual costs. */
769 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
770 COSTS_N_INSNS (7), /* fp_mult_sf */ \
771 COSTS_N_INSNS (8), /* fp_mult_df */ \
772 COSTS_N_INSNS (23), /* fp_div_sf */ \
773 COSTS_N_INSNS (36), /* fp_div_df */ \
774 COSTS_N_INSNS (10), /* int_mult_si */ \
775 COSTS_N_INSNS (10), /* int_mult_di */ \
776 COSTS_N_INSNS (69), /* int_div_si */ \
777 COSTS_N_INSNS (69), /* int_div_di */ \
778 2, /* branch_cost */ \
779 4 /* memory_latency */
781 /* Need to replace these with the costs of calling the appropriate
783 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
784 COSTS_N_INSNS (256), /* fp_mult_sf */ \
785 COSTS_N_INSNS (256), /* fp_mult_df */ \
786 COSTS_N_INSNS (256), /* fp_div_sf */ \
787 COSTS_N_INSNS (256) /* fp_div_df */
789 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
792 COSTS_N_INSNS (2), /* fp_add */
793 COSTS_N_INSNS (4), /* fp_mult_sf */
794 COSTS_N_INSNS (5), /* fp_mult_df */
795 COSTS_N_INSNS (12), /* fp_div_sf */
796 COSTS_N_INSNS (19), /* fp_div_df */
797 COSTS_N_INSNS (12), /* int_mult_si */
798 COSTS_N_INSNS (12), /* int_mult_di */
799 COSTS_N_INSNS (35), /* int_div_si */
800 COSTS_N_INSNS (35), /* int_div_di */
802 4 /* memory_latency */
807 COSTS_N_INSNS (6), /* int_mult_si */
808 COSTS_N_INSNS (6), /* int_mult_di */
809 COSTS_N_INSNS (36), /* int_div_si */
810 COSTS_N_INSNS (36), /* int_div_di */
812 4 /* memory_latency */
816 COSTS_N_INSNS (36), /* int_mult_si */
817 COSTS_N_INSNS (36), /* int_mult_di */
818 COSTS_N_INSNS (37), /* int_div_si */
819 COSTS_N_INSNS (37), /* int_div_di */
821 4 /* memory_latency */
825 COSTS_N_INSNS (4), /* int_mult_si */
826 COSTS_N_INSNS (11), /* int_mult_di */
827 COSTS_N_INSNS (36), /* int_div_si */
828 COSTS_N_INSNS (68), /* int_div_di */
830 4 /* memory_latency */
833 COSTS_N_INSNS (4), /* fp_add */
834 COSTS_N_INSNS (4), /* fp_mult_sf */
835 COSTS_N_INSNS (5), /* fp_mult_df */
836 COSTS_N_INSNS (17), /* fp_div_sf */
837 COSTS_N_INSNS (32), /* fp_div_df */
838 COSTS_N_INSNS (4), /* int_mult_si */
839 COSTS_N_INSNS (11), /* int_mult_di */
840 COSTS_N_INSNS (36), /* int_div_si */
841 COSTS_N_INSNS (68), /* int_div_di */
843 4 /* memory_latency */
849 COSTS_N_INSNS (8), /* fp_add */
850 COSTS_N_INSNS (8), /* fp_mult_sf */
851 COSTS_N_INSNS (10), /* fp_mult_df */
852 COSTS_N_INSNS (34), /* fp_div_sf */
853 COSTS_N_INSNS (64), /* fp_div_df */
854 COSTS_N_INSNS (5), /* int_mult_si */
855 COSTS_N_INSNS (5), /* int_mult_di */
856 COSTS_N_INSNS (41), /* int_div_si */
857 COSTS_N_INSNS (41), /* int_div_di */
859 4 /* memory_latency */
862 COSTS_N_INSNS (4), /* fp_add */
863 COSTS_N_INSNS (4), /* fp_mult_sf */
864 COSTS_N_INSNS (5), /* fp_mult_df */
865 COSTS_N_INSNS (17), /* fp_div_sf */
866 COSTS_N_INSNS (32), /* fp_div_df */
867 COSTS_N_INSNS (5), /* int_mult_si */
868 COSTS_N_INSNS (5), /* int_mult_di */
869 COSTS_N_INSNS (41), /* int_div_si */
870 COSTS_N_INSNS (41), /* int_div_di */
872 4 /* memory_latency */
878 COSTS_N_INSNS (2), /* fp_add */
879 COSTS_N_INSNS (4), /* fp_mult_sf */
880 COSTS_N_INSNS (5), /* fp_mult_df */
881 COSTS_N_INSNS (12), /* fp_div_sf */
882 COSTS_N_INSNS (19), /* fp_div_df */
883 COSTS_N_INSNS (2), /* int_mult_si */
884 COSTS_N_INSNS (2), /* int_mult_di */
885 COSTS_N_INSNS (35), /* int_div_si */
886 COSTS_N_INSNS (35), /* int_div_di */
888 4 /* memory_latency */
891 COSTS_N_INSNS (3), /* fp_add */
892 COSTS_N_INSNS (5), /* fp_mult_sf */
893 COSTS_N_INSNS (6), /* fp_mult_df */
894 COSTS_N_INSNS (15), /* fp_div_sf */
895 COSTS_N_INSNS (16), /* fp_div_df */
896 COSTS_N_INSNS (17), /* int_mult_si */
897 COSTS_N_INSNS (17), /* int_mult_di */
898 COSTS_N_INSNS (38), /* int_div_si */
899 COSTS_N_INSNS (38), /* int_div_di */
901 6 /* memory_latency */
904 COSTS_N_INSNS (6), /* fp_add */
905 COSTS_N_INSNS (7), /* fp_mult_sf */
906 COSTS_N_INSNS (8), /* fp_mult_df */
907 COSTS_N_INSNS (23), /* fp_div_sf */
908 COSTS_N_INSNS (36), /* fp_div_df */
909 COSTS_N_INSNS (10), /* int_mult_si */
910 COSTS_N_INSNS (10), /* int_mult_di */
911 COSTS_N_INSNS (69), /* int_div_si */
912 COSTS_N_INSNS (69), /* int_div_di */
914 6 /* memory_latency */
926 /* The only costs that appear to be updated here are
927 integer multiplication. */
929 COSTS_N_INSNS (4), /* int_mult_si */
930 COSTS_N_INSNS (6), /* int_mult_di */
931 COSTS_N_INSNS (69), /* int_div_si */
932 COSTS_N_INSNS (69), /* int_div_di */
934 4 /* memory_latency */
946 COSTS_N_INSNS (6), /* fp_add */
947 COSTS_N_INSNS (4), /* fp_mult_sf */
948 COSTS_N_INSNS (5), /* fp_mult_df */
949 COSTS_N_INSNS (23), /* fp_div_sf */
950 COSTS_N_INSNS (36), /* fp_div_df */
951 COSTS_N_INSNS (5), /* int_mult_si */
952 COSTS_N_INSNS (5), /* int_mult_di */
953 COSTS_N_INSNS (36), /* int_div_si */
954 COSTS_N_INSNS (36), /* int_div_di */
956 4 /* memory_latency */
959 COSTS_N_INSNS (6), /* fp_add */
960 COSTS_N_INSNS (5), /* fp_mult_sf */
961 COSTS_N_INSNS (6), /* fp_mult_df */
962 COSTS_N_INSNS (30), /* fp_div_sf */
963 COSTS_N_INSNS (59), /* fp_div_df */
964 COSTS_N_INSNS (3), /* int_mult_si */
965 COSTS_N_INSNS (4), /* int_mult_di */
966 COSTS_N_INSNS (42), /* int_div_si */
967 COSTS_N_INSNS (74), /* int_div_di */
969 4 /* memory_latency */
972 COSTS_N_INSNS (6), /* fp_add */
973 COSTS_N_INSNS (5), /* fp_mult_sf */
974 COSTS_N_INSNS (6), /* fp_mult_df */
975 COSTS_N_INSNS (30), /* fp_div_sf */
976 COSTS_N_INSNS (59), /* fp_div_df */
977 COSTS_N_INSNS (5), /* int_mult_si */
978 COSTS_N_INSNS (9), /* int_mult_di */
979 COSTS_N_INSNS (42), /* int_div_si */
980 COSTS_N_INSNS (74), /* int_div_di */
982 4 /* memory_latency */
985 /* The only costs that are changed here are
986 integer multiplication. */
987 COSTS_N_INSNS (6), /* fp_add */
988 COSTS_N_INSNS (7), /* fp_mult_sf */
989 COSTS_N_INSNS (8), /* fp_mult_df */
990 COSTS_N_INSNS (23), /* fp_div_sf */
991 COSTS_N_INSNS (36), /* fp_div_df */
992 COSTS_N_INSNS (5), /* int_mult_si */
993 COSTS_N_INSNS (9), /* int_mult_di */
994 COSTS_N_INSNS (69), /* int_div_si */
995 COSTS_N_INSNS (69), /* int_div_di */
997 4 /* memory_latency */
1003 /* The only costs that are changed here are
1004 integer multiplication. */
1005 COSTS_N_INSNS (6), /* fp_add */
1006 COSTS_N_INSNS (7), /* fp_mult_sf */
1007 COSTS_N_INSNS (8), /* fp_mult_df */
1008 COSTS_N_INSNS (23), /* fp_div_sf */
1009 COSTS_N_INSNS (36), /* fp_div_df */
1010 COSTS_N_INSNS (3), /* int_mult_si */
1011 COSTS_N_INSNS (8), /* int_mult_di */
1012 COSTS_N_INSNS (69), /* int_div_si */
1013 COSTS_N_INSNS (69), /* int_div_di */
1014 1, /* branch_cost */
1015 4 /* memory_latency */
1018 COSTS_N_INSNS (4), /* fp_add */
1019 COSTS_N_INSNS (4), /* fp_mult_sf */
1020 COSTS_N_INSNS (4), /* fp_mult_df */
1021 COSTS_N_INSNS (24), /* fp_div_sf */
1022 COSTS_N_INSNS (32), /* fp_div_df */
1023 COSTS_N_INSNS (3), /* int_mult_si */
1024 COSTS_N_INSNS (4), /* int_mult_di */
1025 COSTS_N_INSNS (36), /* int_div_si */
1026 COSTS_N_INSNS (68), /* int_div_di */
1027 1, /* branch_cost */
1028 4 /* memory_latency */
1036 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1037 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1038 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1041 /* Initialize the GCC target structure. */
1042 #undef TARGET_ASM_ALIGNED_HI_OP
1043 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1044 #undef TARGET_ASM_ALIGNED_SI_OP
1045 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1046 #undef TARGET_ASM_ALIGNED_DI_OP
1047 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1049 #undef TARGET_ASM_FUNCTION_PROLOGUE
1050 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1051 #undef TARGET_ASM_FUNCTION_EPILOGUE
1052 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1053 #undef TARGET_ASM_SELECT_RTX_SECTION
1054 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1055 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1056 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1058 #undef TARGET_SCHED_REORDER
1059 #define TARGET_SCHED_REORDER mips_sched_reorder
1060 #undef TARGET_SCHED_VARIABLE_ISSUE
1061 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1062 #undef TARGET_SCHED_ADJUST_COST
1063 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1064 #undef TARGET_SCHED_ISSUE_RATE
1065 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1066 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1067 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1068 mips_multipass_dfa_lookahead
1070 #undef TARGET_DEFAULT_TARGET_FLAGS
1071 #define TARGET_DEFAULT_TARGET_FLAGS \
1073 | TARGET_CPU_DEFAULT \
1074 | TARGET_ENDIAN_DEFAULT \
1075 | TARGET_FP_EXCEPTIONS_DEFAULT \
1076 | MASK_CHECK_ZERO_DIV \
1078 #undef TARGET_HANDLE_OPTION
1079 #define TARGET_HANDLE_OPTION mips_handle_option
1081 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1082 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1084 #undef TARGET_VALID_POINTER_MODE
1085 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1086 #undef TARGET_RTX_COSTS
1087 #define TARGET_RTX_COSTS mips_rtx_costs
1088 #undef TARGET_ADDRESS_COST
1089 #define TARGET_ADDRESS_COST mips_address_cost
1091 #undef TARGET_IN_SMALL_DATA_P
1092 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1094 #undef TARGET_MACHINE_DEPENDENT_REORG
1095 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1097 #undef TARGET_ASM_FILE_START
1098 #undef TARGET_ASM_FILE_END
1099 #define TARGET_ASM_FILE_START mips_file_start
1100 #define TARGET_ASM_FILE_END mips_file_end
1101 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1102 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1104 #undef TARGET_INIT_LIBFUNCS
1105 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1107 #undef TARGET_BUILD_BUILTIN_VA_LIST
1108 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1109 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1110 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1112 #undef TARGET_PROMOTE_FUNCTION_ARGS
1113 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1114 #undef TARGET_PROMOTE_FUNCTION_RETURN
1115 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1116 #undef TARGET_PROMOTE_PROTOTYPES
1117 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1119 #undef TARGET_RETURN_IN_MEMORY
1120 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1121 #undef TARGET_RETURN_IN_MSB
1122 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1124 #undef TARGET_ASM_OUTPUT_MI_THUNK
1125 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1126 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1127 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1129 #undef TARGET_SETUP_INCOMING_VARARGS
1130 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1131 #undef TARGET_STRICT_ARGUMENT_NAMING
1132 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1133 #undef TARGET_MUST_PASS_IN_STACK
1134 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1135 #undef TARGET_PASS_BY_REFERENCE
1136 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1137 #undef TARGET_CALLEE_COPIES
1138 #define TARGET_CALLEE_COPIES mips_callee_copies
1139 #undef TARGET_ARG_PARTIAL_BYTES
1140 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1142 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1143 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1145 #undef TARGET_INIT_BUILTINS
1146 #define TARGET_INIT_BUILTINS mips_init_builtins
1147 #undef TARGET_EXPAND_BUILTIN
1148 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1150 #undef TARGET_HAVE_TLS
1151 #define TARGET_HAVE_TLS HAVE_AS_TLS
1153 #undef TARGET_CANNOT_FORCE_CONST_MEM
1154 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1156 #undef TARGET_ENCODE_SECTION_INFO
1157 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1159 #undef TARGET_ATTRIBUTE_TABLE
1160 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1162 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1163 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1165 struct gcc_target targetm = TARGET_INITIALIZER;
1167 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1169 static enum mips_symbol_type
1170 mips_classify_symbol (rtx x)
1172 if (GET_CODE (x) == LABEL_REF)
1175 return SYMBOL_CONSTANT_POOL;
1176 if (TARGET_ABICALLS)
1177 return SYMBOL_GOT_LOCAL;
1178 return SYMBOL_GENERAL;
1181 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1183 if (SYMBOL_REF_TLS_MODEL (x))
1186 if (CONSTANT_POOL_ADDRESS_P (x))
1189 return SYMBOL_CONSTANT_POOL;
1191 if (TARGET_ABICALLS)
1192 return SYMBOL_GOT_LOCAL;
1194 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1195 return SYMBOL_SMALL_DATA;
1197 return SYMBOL_GENERAL;
1200 if (SYMBOL_REF_SMALL_P (x))
1201 return SYMBOL_SMALL_DATA;
1203 if (TARGET_ABICALLS)
1205 if (SYMBOL_REF_DECL (x) == 0)
1206 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
1208 /* There are three cases to consider:
1210 - o32 PIC (either with or without explicit relocs)
1211 - n32/n64 PIC without explicit relocs
1212 - n32/n64 PIC with explicit relocs
1214 In the first case, both local and global accesses will use an
1215 R_MIPS_GOT16 relocation. We must correctly predict which of
1216 the two semantics (local or global) the assembler and linker
1217 will apply. The choice doesn't depend on the symbol's
1218 visibility, so we deliberately ignore decl_visibility and
1221 In the second case, the assembler will not use R_MIPS_GOT16
1222 relocations, but it chooses between local and global accesses
1223 in the same way as for o32 PIC.
1225 In the third case we have more freedom since both forms of
1226 access will work for any kind of symbol. However, there seems
1227 little point in doing things differently. */
1228 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
1229 return SYMBOL_GOT_GLOBAL;
1231 return SYMBOL_GOT_LOCAL;
1234 return SYMBOL_GENERAL;
1238 /* Split X into a base and a constant offset, storing them in *BASE
1239 and *OFFSET respectively. */
1242 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1246 if (GET_CODE (x) == CONST)
1249 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1251 *offset += INTVAL (XEXP (x, 1));
1258 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1259 to the same object as SYMBOL. */
1262 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1264 if (GET_CODE (symbol) != SYMBOL_REF)
1267 if (CONSTANT_POOL_ADDRESS_P (symbol)
1269 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1272 if (SYMBOL_REF_DECL (symbol) != 0
1274 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1281 /* Return true if X is a symbolic constant that can be calculated in
1282 the same way as a bare symbol. If it is, store the type of the
1283 symbol in *SYMBOL_TYPE. */
1286 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1288 HOST_WIDE_INT offset;
1290 mips_split_const (x, &x, &offset);
1291 if (UNSPEC_ADDRESS_P (x))
1292 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1293 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1295 *symbol_type = mips_classify_symbol (x);
1296 if (*symbol_type == SYMBOL_TLS)
1305 /* Check whether a nonzero offset is valid for the underlying
1307 switch (*symbol_type)
1309 case SYMBOL_GENERAL:
1310 case SYMBOL_64_HIGH:
1313 /* If the target has 64-bit pointers and the object file only
1314 supports 32-bit symbols, the values of those symbols will be
1315 sign-extended. In this case we can't allow an arbitrary offset
1316 in case the 32-bit value X + OFFSET has a different sign from X. */
1317 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1318 return mips_offset_within_object_p (x, offset);
1320 /* In other cases the relocations can handle any offset. */
1323 case SYMBOL_CONSTANT_POOL:
1324 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1325 In this case, we no longer have access to the underlying constant,
1326 but the original symbol-based access was known to be valid. */
1327 if (GET_CODE (x) == LABEL_REF)
1332 case SYMBOL_SMALL_DATA:
1333 /* Make sure that the offset refers to something within the
1334 underlying object. This should guarantee that the final
1335 PC- or GP-relative offset is within the 16-bit limit. */
1336 return mips_offset_within_object_p (x, offset);
1338 case SYMBOL_GOT_LOCAL:
1339 case SYMBOL_GOTOFF_PAGE:
1340 /* The linker should provide enough local GOT entries for a
1341 16-bit offset. Larger offsets may lead to GOT overflow. */
1342 return SMALL_OPERAND (offset);
1344 case SYMBOL_GOT_GLOBAL:
1345 case SYMBOL_GOTOFF_GLOBAL:
1346 case SYMBOL_GOTOFF_CALL:
1347 case SYMBOL_GOTOFF_LOADGP:
1352 case SYMBOL_GOTTPREL:
1360 /* Return true if X is a symbolic constant whose value is not split
1361 into separate relocations. */
1364 mips_atomic_symbolic_constant_p (rtx x)
1366 enum mips_symbol_type type;
1367 return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
1371 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1374 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1376 if (regno >= FIRST_PSEUDO_REGISTER)
1380 regno = reg_renumber[regno];
1383 /* These fake registers will be eliminated to either the stack or
1384 hard frame pointer, both of which are usually valid base registers.
1385 Reload deals with the cases where the eliminated form isn't valid. */
1386 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1389 /* In mips16 mode, the stack pointer can only address word and doubleword
1390 values, nothing smaller. There are two problems here:
1392 (a) Instantiating virtual registers can introduce new uses of the
1393 stack pointer. If these virtual registers are valid addresses,
1394 the stack pointer should be too.
1396 (b) Most uses of the stack pointer are not made explicit until
1397 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1398 We don't know until that stage whether we'll be eliminating to the
1399 stack pointer (which needs the restriction) or the hard frame
1400 pointer (which doesn't).
1402 All in all, it seems more consistent to only enforce this restriction
1403 during and after reload. */
1404 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1405 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1407 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1411 /* Return true if X is a valid base register for the given mode.
1412 Allow only hard registers if STRICT. */
1415 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1417 if (!strict && GET_CODE (x) == SUBREG)
1421 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1425 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1426 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1429 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1430 enum machine_mode mode)
1432 switch (symbol_type)
1434 case SYMBOL_GENERAL:
1435 return !TARGET_MIPS16;
1437 case SYMBOL_SMALL_DATA:
1440 case SYMBOL_CONSTANT_POOL:
1441 /* PC-relative addressing is only available for lw and ld. */
1442 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1444 case SYMBOL_GOT_LOCAL:
1447 case SYMBOL_GOT_GLOBAL:
1448 /* The address will have to be loaded from the GOT first. */
1455 case SYMBOL_GOTTPREL:
1459 case SYMBOL_GOTOFF_PAGE:
1460 case SYMBOL_GOTOFF_GLOBAL:
1461 case SYMBOL_GOTOFF_CALL:
1462 case SYMBOL_GOTOFF_LOADGP:
1463 case SYMBOL_64_HIGH:
1472 /* Return true if X is a valid address for machine mode MODE. If it is,
1473 fill in INFO appropriately. STRICT is true if we should only accept
1474 hard base registers. */
1477 mips_classify_address (struct mips_address_info *info, rtx x,
1478 enum machine_mode mode, int strict)
1480 switch (GET_CODE (x))
1484 info->type = ADDRESS_REG;
1486 info->offset = const0_rtx;
1487 return mips_valid_base_register_p (info->reg, mode, strict);
1490 info->type = ADDRESS_REG;
1491 info->reg = XEXP (x, 0);
1492 info->offset = XEXP (x, 1);
1493 return (mips_valid_base_register_p (info->reg, mode, strict)
1494 && const_arith_operand (info->offset, VOIDmode));
1497 info->type = ADDRESS_LO_SUM;
1498 info->reg = XEXP (x, 0);
1499 info->offset = XEXP (x, 1);
1500 return (mips_valid_base_register_p (info->reg, mode, strict)
1501 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1502 && mips_symbolic_address_p (info->symbol_type, mode)
1503 && mips_lo_relocs[info->symbol_type] != 0);
1506 /* Small-integer addresses don't occur very often, but they
1507 are legitimate if $0 is a valid base register. */
1508 info->type = ADDRESS_CONST_INT;
1509 return !TARGET_MIPS16 && SMALL_INT (x);
1514 info->type = ADDRESS_SYMBOLIC;
1515 return (mips_symbolic_constant_p (x, &info->symbol_type)
1516 && mips_symbolic_address_p (info->symbol_type, mode)
1517 && !mips_split_p[info->symbol_type]);
1524 /* Return true if X is a thread-local symbol. */
1527 mips_tls_operand_p (rtx x)
1529 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1532 /* Return true if X can not be forced into a constant pool. */
1535 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1537 return mips_tls_operand_p (*x);
1540 /* Return true if X can not be forced into a constant pool. */
1543 mips_cannot_force_const_mem (rtx x)
1545 if (! TARGET_HAVE_TLS)
1548 return for_each_rtx (&x, &mips_tls_symbol_ref_1, 0);
1551 /* Return the number of instructions needed to load a symbol of the
1552 given type into a register. If valid in an address, the same number
1553 of instructions are needed for loads and stores. Treat extended
1554 mips16 instructions as two instructions. */
1557 mips_symbol_insns (enum mips_symbol_type type)
1561 case SYMBOL_GENERAL:
1562 /* In mips16 code, general symbols must be fetched from the
1567 /* When using 64-bit symbols, we need 5 preparatory instructions,
1570 lui $at,%highest(symbol)
1571 daddiu $at,$at,%higher(symbol)
1573 daddiu $at,$at,%hi(symbol)
1576 The final address is then $at + %lo(symbol). With 32-bit
1577 symbols we just need a preparatory lui. */
1578 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1580 case SYMBOL_SMALL_DATA:
1583 case SYMBOL_CONSTANT_POOL:
1584 /* This case is for mips16 only. Assume we'll need an
1585 extended instruction. */
1588 case SYMBOL_GOT_LOCAL:
1589 case SYMBOL_GOT_GLOBAL:
1590 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1591 the local/global classification is accurate. See override_options
1594 The worst cases are:
1596 (1) For local symbols when generating o32 or o64 code. The assembler
1602 ...and the final address will be $at + %lo(symbol).
1604 (2) For global symbols when -mxgot. The assembler will use:
1606 lui $at,%got_hi(symbol)
1609 ...and the final address will be $at + %got_lo(symbol). */
1612 case SYMBOL_GOTOFF_PAGE:
1613 case SYMBOL_GOTOFF_GLOBAL:
1614 case SYMBOL_GOTOFF_CALL:
1615 case SYMBOL_GOTOFF_LOADGP:
1616 case SYMBOL_64_HIGH:
1622 case SYMBOL_GOTTPREL:
1624 /* Check whether the offset is a 16- or 32-bit value. */
1625 return mips_split_p[type] ? 2 : 1;
1628 /* We don't treat a bare TLS symbol as a constant. */
1634 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1637 mips_stack_address_p (rtx x, enum machine_mode mode)
1639 struct mips_address_info addr;
1641 return (mips_classify_address (&addr, x, mode, false)
1642 && addr.type == ADDRESS_REG
1643 && addr.reg == stack_pointer_rtx);
1646 /* Return true if a value at OFFSET bytes from BASE can be accessed
1647 using an unextended mips16 instruction. MODE is the mode of the
1650 Usually the offset in an unextended instruction is a 5-bit field.
1651 The offset is unsigned and shifted left once for HIs, twice
1652 for SIs, and so on. An exception is SImode accesses off the
1653 stack pointer, which have an 8-bit immediate field. */
1656 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1659 && GET_CODE (offset) == CONST_INT
1660 && INTVAL (offset) >= 0
1661 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1663 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1664 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1665 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1671 /* Return the number of instructions needed to load or store a value
1672 of mode MODE at X. Return 0 if X isn't valid for MODE.
1674 For mips16 code, count extended instructions as two instructions. */
1677 mips_address_insns (rtx x, enum machine_mode mode)
1679 struct mips_address_info addr;
1682 if (mode == BLKmode)
1683 /* BLKmode is used for single unaligned loads and stores. */
1686 /* Each word of a multi-word value will be accessed individually. */
1687 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1689 if (mips_classify_address (&addr, x, mode, false))
1694 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1698 case ADDRESS_LO_SUM:
1699 return (TARGET_MIPS16 ? factor * 2 : factor);
1701 case ADDRESS_CONST_INT:
1704 case ADDRESS_SYMBOLIC:
1705 return factor * mips_symbol_insns (addr.symbol_type);
1711 /* Likewise for constant X. */
1714 mips_const_insns (rtx x)
1716 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1717 enum mips_symbol_type symbol_type;
1718 HOST_WIDE_INT offset;
1720 switch (GET_CODE (x))
1724 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1725 || !mips_split_p[symbol_type])
1732 /* Unsigned 8-bit constants can be loaded using an unextended
1733 LI instruction. Unsigned 16-bit constants can be loaded
1734 using an extended LI. Negative constants must be loaded
1735 using LI and then negated. */
1736 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1737 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1738 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1739 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1742 return mips_build_integer (codes, INTVAL (x));
1746 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1752 /* See if we can refer to X directly. */
1753 if (mips_symbolic_constant_p (x, &symbol_type))
1754 return mips_symbol_insns (symbol_type);
1756 /* Otherwise try splitting the constant into a base and offset.
1757 16-bit offsets can be added using an extra addiu. Larger offsets
1758 must be calculated separately and then added to the base. */
1759 mips_split_const (x, &x, &offset);
1762 int n = mips_const_insns (x);
1765 if (SMALL_OPERAND (offset))
1768 return n + 1 + mips_build_integer (codes, offset);
1775 return mips_symbol_insns (mips_classify_symbol (x));
1783 /* Return the number of instructions needed for memory reference X.
1784 Count extended mips16 instructions as two instructions. */
1787 mips_fetch_insns (rtx x)
1789 gcc_assert (MEM_P (x));
1790 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1794 /* Return the number of instructions needed for an integer division. */
1797 mips_idiv_insns (void)
1802 if (TARGET_CHECK_ZERO_DIV)
1804 if (GENERATE_DIVIDE_TRAPS)
1810 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1815 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1816 returns a nonzero value if X is a legitimate address for a memory
1817 operand of the indicated MODE. STRICT is nonzero if this function
1818 is called during reload. */
1821 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1823 struct mips_address_info addr;
1825 return mips_classify_address (&addr, x, mode, strict);
1829 /* Copy VALUE to a register and return that register. If new psuedos
1830 are allowed, copy it into a new register, otherwise use DEST. */
1833 mips_force_temporary (rtx dest, rtx value)
1835 if (!no_new_pseudos)
1836 return force_reg (Pmode, value);
1839 emit_move_insn (copy_rtx (dest), value);
1845 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1846 and is used to load the high part into a register. */
1849 mips_split_symbol (rtx temp, rtx addr)
1854 high = mips16_gp_pseudo_reg ();
1856 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1857 return gen_rtx_LO_SUM (Pmode, high, addr);
1861 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1862 type SYMBOL_TYPE. */
1865 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1868 HOST_WIDE_INT offset;
1870 mips_split_const (address, &base, &offset);
1871 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1872 UNSPEC_ADDRESS_FIRST + symbol_type);
1873 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1877 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1878 high part to BASE and return the result. Just return BASE otherwise.
1879 TEMP is available as a temporary register if needed.
1881 The returned expression can be used as the first operand to a LO_SUM. */
1884 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1885 enum mips_symbol_type symbol_type)
1887 if (mips_split_p[symbol_type])
1889 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1890 addr = mips_force_temporary (temp, addr);
1891 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1897 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1898 mips_force_temporary; it is only needed when OFFSET is not a
1902 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1904 if (!SMALL_OPERAND (offset))
1909 /* Load the full offset into a register so that we can use
1910 an unextended instruction for the address itself. */
1911 high = GEN_INT (offset);
1916 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1917 high = GEN_INT (CONST_HIGH_PART (offset));
1918 offset = CONST_LOW_PART (offset);
1920 high = mips_force_temporary (temp, high);
1921 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1923 return plus_constant (reg, offset);
1926 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1927 referencing, and TYPE is the symbol type to use (either global
1928 dynamic or local dynamic). V0 is an RTX for the return value
1929 location. The entire insn sequence is returned. */
1931 static GTY(()) rtx mips_tls_symbol;
1934 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1936 rtx insn, loc, tga, a0;
1938 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1940 if (!mips_tls_symbol)
1941 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1943 loc = mips_unspec_address (sym, type);
1947 emit_insn (gen_rtx_SET (Pmode, a0,
1948 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1949 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1950 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1951 CONST_OR_PURE_CALL_P (insn) = 1;
1952 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1953 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1954 insn = get_insns ();
1961 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1962 return value will be a valid address and move_operand (either a REG
1966 mips_legitimize_tls_address (rtx loc)
1968 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
1969 enum tls_model model;
1971 v0 = gen_rtx_REG (Pmode, GP_RETURN);
1972 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
1974 model = SYMBOL_REF_TLS_MODEL (loc);
1978 case TLS_MODEL_GLOBAL_DYNAMIC:
1979 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
1980 dest = gen_reg_rtx (Pmode);
1981 emit_libcall_block (insn, dest, v0, loc);
1984 case TLS_MODEL_LOCAL_DYNAMIC:
1985 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
1986 tmp1 = gen_reg_rtx (Pmode);
1988 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
1989 share the LDM result with other LD model accesses. */
1990 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1992 emit_libcall_block (insn, tmp1, v0, eqv);
1994 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
1995 dest = gen_rtx_LO_SUM (Pmode, tmp2,
1996 mips_unspec_address (loc, SYMBOL_DTPREL));
1999 case TLS_MODEL_INITIAL_EXEC:
2000 tmp1 = gen_reg_rtx (Pmode);
2001 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2002 if (Pmode == DImode)
2004 emit_insn (gen_tls_get_tp_di (v1));
2005 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2009 emit_insn (gen_tls_get_tp_si (v1));
2010 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2012 dest = gen_reg_rtx (Pmode);
2013 emit_insn (gen_add3_insn (dest, tmp1, v1));
2016 case TLS_MODEL_LOCAL_EXEC:
2018 if (Pmode == DImode)
2019 emit_insn (gen_tls_get_tp_di (v1));
2021 emit_insn (gen_tls_get_tp_si (v1));
2023 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2024 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2025 mips_unspec_address (loc, SYMBOL_TPREL));
2035 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2036 be legitimized in a way that the generic machinery might not expect,
2037 put the new address in *XLOC and return true. MODE is the mode of
2038 the memory being accessed. */
2041 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2043 enum mips_symbol_type symbol_type;
2045 if (mips_tls_operand_p (*xloc))
2047 *xloc = mips_legitimize_tls_address (*xloc);
2051 /* See if the address can split into a high part and a LO_SUM. */
2052 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2053 && mips_symbolic_address_p (symbol_type, mode)
2054 && mips_split_p[symbol_type])
2056 *xloc = mips_split_symbol (0, *xloc);
2060 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2062 /* Handle REG + CONSTANT using mips_add_offset. */
2065 reg = XEXP (*xloc, 0);
2066 if (!mips_valid_base_register_p (reg, mode, 0))
2067 reg = copy_to_mode_reg (Pmode, reg);
2068 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2076 /* Subroutine of mips_build_integer (with the same interface).
2077 Assume that the final action in the sequence should be a left shift. */
2080 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2082 unsigned int i, shift;
2084 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2085 since signed numbers are easier to load than unsigned ones. */
2087 while ((value & 1) == 0)
2088 value /= 2, shift++;
2090 i = mips_build_integer (codes, value);
2091 codes[i].code = ASHIFT;
2092 codes[i].value = shift;
2097 /* As for mips_build_shift, but assume that the final action will be
2098 an IOR or PLUS operation. */
2101 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2103 unsigned HOST_WIDE_INT high;
2106 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2107 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2109 /* The constant is too complex to load with a simple lui/ori pair
2110 so our goal is to clear as many trailing zeros as possible.
2111 In this case, we know bit 16 is set and that the low 16 bits
2112 form a negative number. If we subtract that number from VALUE,
2113 we will clear at least the lowest 17 bits, maybe more. */
2114 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2115 codes[i].code = PLUS;
2116 codes[i].value = CONST_LOW_PART (value);
2120 i = mips_build_integer (codes, high);
2121 codes[i].code = IOR;
2122 codes[i].value = value & 0xffff;
2128 /* Fill CODES with a sequence of rtl operations to load VALUE.
2129 Return the number of operations needed. */
2132 mips_build_integer (struct mips_integer_op *codes,
2133 unsigned HOST_WIDE_INT value)
2135 if (SMALL_OPERAND (value)
2136 || SMALL_OPERAND_UNSIGNED (value)
2137 || LUI_OPERAND (value))
2139 /* The value can be loaded with a single instruction. */
2140 codes[0].code = UNKNOWN;
2141 codes[0].value = value;
2144 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2146 /* Either the constant is a simple LUI/ORI combination or its
2147 lowest bit is set. We don't want to shift in this case. */
2148 return mips_build_lower (codes, value);
2150 else if ((value & 0xffff) == 0)
2152 /* The constant will need at least three actions. The lowest
2153 16 bits are clear, so the final action will be a shift. */
2154 return mips_build_shift (codes, value);
2158 /* The final action could be a shift, add or inclusive OR.
2159 Rather than use a complex condition to select the best
2160 approach, try both mips_build_shift and mips_build_lower
2161 and pick the one that gives the shortest sequence.
2162 Note that this case is only used once per constant. */
2163 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2164 unsigned int cost, alt_cost;
2166 cost = mips_build_shift (codes, value);
2167 alt_cost = mips_build_lower (alt_codes, value);
2168 if (alt_cost < cost)
2170 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2178 /* Move VALUE into register DEST. */
2181 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
2183 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2184 enum machine_mode mode;
2185 unsigned int i, cost;
2188 mode = GET_MODE (dest);
2189 cost = mips_build_integer (codes, value);
2191 /* Apply each binary operation to X. Invariant: X is a legitimate
2192 source operand for a SET pattern. */
2193 x = GEN_INT (codes[0].value);
2194 for (i = 1; i < cost; i++)
2197 emit_move_insn (dest, x), x = dest;
2199 x = force_reg (mode, x);
2200 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2203 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2207 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2208 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2212 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2215 HOST_WIDE_INT offset;
2216 enum mips_symbol_type symbol_type;
2218 /* Split moves of big integers into smaller pieces. In mips16 code,
2219 it's better to force the constant into memory instead. */
2220 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
2222 mips_move_integer (dest, INTVAL (src));
2226 if (mips_tls_operand_p (src))
2228 emit_move_insn (dest, mips_legitimize_tls_address (src));
2232 /* See if the symbol can be split. For mips16, this is often worse than
2233 forcing it in the constant pool since it needs the single-register form
2234 of addiu or daddiu. */
2236 && mips_symbolic_constant_p (src, &symbol_type)
2237 && mips_split_p[symbol_type])
2239 emit_move_insn (dest, mips_split_symbol (dest, src));
2243 /* If we have (const (plus symbol offset)), load the symbol first
2244 and then add in the offset. This is usually better than forcing
2245 the constant into memory, at least in non-mips16 code. */
2246 mips_split_const (src, &base, &offset);
2249 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2251 base = mips_force_temporary (dest, base);
2252 emit_move_insn (dest, mips_add_offset (0, base, offset));
2256 src = force_const_mem (mode, src);
2258 /* When using explicit relocs, constant pool references are sometimes
2259 not legitimate addresses. */
2260 if (!memory_operand (src, VOIDmode))
2261 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2262 emit_move_insn (dest, src);
2266 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2267 sequence that is valid. */
2270 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2272 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2274 emit_move_insn (dest, force_reg (mode, src));
2278 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2279 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2280 && REG_P (src) && MD_REG_P (REGNO (src))
2281 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2283 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2284 if (GET_MODE_SIZE (mode) <= 4)
2285 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2286 gen_rtx_REG (SImode, REGNO (src)),
2287 gen_rtx_REG (SImode, other_regno)));
2289 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2290 gen_rtx_REG (DImode, REGNO (src)),
2291 gen_rtx_REG (DImode, other_regno)));
2295 /* We need to deal with constants that would be legitimate
2296 immediate_operands but not legitimate move_operands. */
2297 if (CONSTANT_P (src) && !move_operand (src, mode))
2299 mips_legitimize_const_move (mode, dest, src);
2300 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2306 /* We need a lot of little routines to check constant values on the
2307 mips16. These are used to figure out how long the instruction will
2308 be. It would be much better to do this using constraints, but
2309 there aren't nearly enough letters available. */
2312 m16_check_op (rtx op, int low, int high, int mask)
2314 return (GET_CODE (op) == CONST_INT
2315 && INTVAL (op) >= low
2316 && INTVAL (op) <= high
2317 && (INTVAL (op) & mask) == 0);
2321 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2323 return m16_check_op (op, 0x1, 0x8, 0);
2327 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2329 return m16_check_op (op, - 0x8, 0x7, 0);
2333 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2335 return m16_check_op (op, - 0x7, 0x8, 0);
2339 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2341 return m16_check_op (op, - 0x10, 0xf, 0);
2345 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2347 return m16_check_op (op, - 0xf, 0x10, 0);
2351 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2353 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2357 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2359 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2363 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2365 return m16_check_op (op, - 0x80, 0x7f, 0);
2369 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2371 return m16_check_op (op, - 0x7f, 0x80, 0);
2375 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2377 return m16_check_op (op, 0x0, 0xff, 0);
2381 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2383 return m16_check_op (op, - 0xff, 0x0, 0);
2387 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2389 return m16_check_op (op, - 0x1, 0xfe, 0);
2393 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2395 return m16_check_op (op, 0x0, 0xff << 2, 3);
2399 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2401 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2405 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2407 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2411 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2413 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2417 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2419 enum machine_mode mode = GET_MODE (x);
2420 bool float_mode_p = FLOAT_MODE_P (mode);
2427 /* A number between 1 and 8 inclusive is efficient for a shift.
2428 Otherwise, we will need an extended instruction. */
2429 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2430 || (outer_code) == LSHIFTRT)
2432 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2435 *total = COSTS_N_INSNS (1);
2439 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2440 if ((outer_code) == XOR
2441 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2447 /* We may be able to use slt or sltu for a comparison with a
2448 signed 16 bit value. (The boundary conditions aren't quite
2449 right, but this is just a heuristic anyhow.) */
2450 if (((outer_code) == LT || (outer_code) == LE
2451 || (outer_code) == GE || (outer_code) == GT
2452 || (outer_code) == LTU || (outer_code) == LEU
2453 || (outer_code) == GEU || (outer_code) == GTU)
2454 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2460 /* Equality comparisons with 0 are cheap. */
2461 if (((outer_code) == EQ || (outer_code) == NE)
2468 /* Constants in the range 0...255 can be loaded with an unextended
2469 instruction. They are therefore as cheap as a register move.
2471 Given the choice between "li R1,0...255" and "move R1,R2"
2472 (where R2 is a known constant), it is usually better to use "li",
2473 since we do not want to unnecessarily extend the lifetime
2475 if (outer_code == SET
2477 && INTVAL (x) < 256)
2485 /* These can be used anywhere. */
2490 /* Otherwise fall through to the handling below because
2491 we'll need to construct the constant. */
2497 if (LEGITIMATE_CONSTANT_P (x))
2499 *total = COSTS_N_INSNS (1);
2504 /* The value will need to be fetched from the constant pool. */
2505 *total = CONSTANT_POOL_COST;
2511 /* If the address is legitimate, return the number of
2512 instructions it needs, otherwise use the default handling. */
2513 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2516 *total = COSTS_N_INSNS (n + 1);
2523 *total = COSTS_N_INSNS (6);
2527 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2533 if (mode == DImode && !TARGET_64BIT)
2535 *total = COSTS_N_INSNS (2);
2543 if (mode == DImode && !TARGET_64BIT)
2545 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2553 *total = COSTS_N_INSNS (1);
2555 *total = COSTS_N_INSNS (4);
2559 *total = COSTS_N_INSNS (1);
2566 *total = mips_cost->fp_add;
2570 else if (mode == DImode && !TARGET_64BIT)
2572 *total = COSTS_N_INSNS (4);
2578 if (mode == DImode && !TARGET_64BIT)
2580 *total = COSTS_N_INSNS (4);
2587 *total = mips_cost->fp_mult_sf;
2589 else if (mode == DFmode)
2590 *total = mips_cost->fp_mult_df;
2592 else if (mode == SImode)
2593 *total = mips_cost->int_mult_si;
2596 *total = mips_cost->int_mult_di;
2605 *total = mips_cost->fp_div_sf;
2607 *total = mips_cost->fp_div_df;
2616 *total = mips_cost->int_div_di;
2618 *total = mips_cost->int_div_si;
2623 /* A sign extend from SImode to DImode in 64 bit mode is often
2624 zero instructions, because the result can often be used
2625 directly by another instruction; we'll call it one. */
2626 if (TARGET_64BIT && mode == DImode
2627 && GET_MODE (XEXP (x, 0)) == SImode)
2628 *total = COSTS_N_INSNS (1);
2630 *total = COSTS_N_INSNS (2);
2634 if (TARGET_64BIT && mode == DImode
2635 && GET_MODE (XEXP (x, 0)) == SImode)
2636 *total = COSTS_N_INSNS (2);
2638 *total = COSTS_N_INSNS (1);
2642 case UNSIGNED_FLOAT:
2645 case FLOAT_TRUNCATE:
2647 *total = mips_cost->fp_add;
2655 /* Provide the costs of an addressing mode that contains ADDR.
2656 If ADDR is not a valid address, its cost is irrelevant. */
2659 mips_address_cost (rtx addr)
2661 return mips_address_insns (addr, SImode);
2664 /* Return one word of double-word value OP, taking into account the fixed
2665 endianness of certain registers. HIGH_P is true to select the high part,
2666 false to select the low part. */
2669 mips_subword (rtx op, int high_p)
2672 enum machine_mode mode;
2674 mode = GET_MODE (op);
2675 if (mode == VOIDmode)
2678 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2679 byte = UNITS_PER_WORD;
2685 if (FP_REG_P (REGNO (op)))
2686 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2687 if (ACC_HI_REG_P (REGNO (op)))
2688 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2692 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2694 return simplify_gen_subreg (word_mode, op, mode, byte);
2698 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2701 mips_split_64bit_move_p (rtx dest, rtx src)
2706 /* FP->FP moves can be done in a single instruction. */
2707 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2710 /* Check for floating-point loads and stores. They can be done using
2711 ldc1 and sdc1 on MIPS II and above. */
2714 if (FP_REG_RTX_P (dest) && MEM_P (src))
2716 if (FP_REG_RTX_P (src) && MEM_P (dest))
2723 /* Split a 64-bit move from SRC to DEST assuming that
2724 mips_split_64bit_move_p holds.
2726 Moves into and out of FPRs cause some difficulty here. Such moves
2727 will always be DFmode, since paired FPRs are not allowed to store
2728 DImode values. The most natural representation would be two separate
2729 32-bit moves, such as:
2731 (set (reg:SI $f0) (mem:SI ...))
2732 (set (reg:SI $f1) (mem:SI ...))
2734 However, the second insn is invalid because odd-numbered FPRs are
2735 not allowed to store independent values. Use the patterns load_df_low,
2736 load_df_high and store_df_high instead. */
2739 mips_split_64bit_move (rtx dest, rtx src)
2741 if (FP_REG_RTX_P (dest))
2743 /* Loading an FPR from memory or from GPRs. */
2744 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2745 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2748 else if (FP_REG_RTX_P (src))
2750 /* Storing an FPR into memory or GPRs. */
2751 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2752 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2756 /* The operation can be split into two normal moves. Decide in
2757 which order to do them. */
2760 low_dest = mips_subword (dest, 0);
2761 if (REG_P (low_dest)
2762 && reg_overlap_mentioned_p (low_dest, src))
2764 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2765 emit_move_insn (low_dest, mips_subword (src, 0));
2769 emit_move_insn (low_dest, mips_subword (src, 0));
2770 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2775 /* Return the appropriate instructions to move SRC into DEST. Assume
2776 that SRC is operand 1 and DEST is operand 0. */
2779 mips_output_move (rtx dest, rtx src)
2781 enum rtx_code dest_code, src_code;
2784 dest_code = GET_CODE (dest);
2785 src_code = GET_CODE (src);
2786 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2788 if (dbl_p && mips_split_64bit_move_p (dest, src))
2791 if ((src_code == REG && GP_REG_P (REGNO (src)))
2792 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2794 if (dest_code == REG)
2796 if (GP_REG_P (REGNO (dest)))
2797 return "move\t%0,%z1";
2799 if (MD_REG_P (REGNO (dest)))
2802 if (DSP_ACC_REG_P (REGNO (dest)))
2804 static char retval[] = "mt__\t%z1,%q0";
2805 retval[2] = reg_names[REGNO (dest)][4];
2806 retval[3] = reg_names[REGNO (dest)][5];
2810 if (FP_REG_P (REGNO (dest)))
2811 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2813 if (ALL_COP_REG_P (REGNO (dest)))
2815 static char retval[] = "dmtc_\t%z1,%0";
2817 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2818 return (dbl_p ? retval : retval + 1);
2821 if (dest_code == MEM)
2822 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2824 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2826 if (src_code == REG)
2828 if (DSP_ACC_REG_P (REGNO (src)))
2830 static char retval[] = "mf__\t%0,%q1";
2831 retval[2] = reg_names[REGNO (src)][4];
2832 retval[3] = reg_names[REGNO (src)][5];
2836 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2837 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2839 if (FP_REG_P (REGNO (src)))
2840 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2842 if (ALL_COP_REG_P (REGNO (src)))
2844 static char retval[] = "dmfc_\t%0,%1";
2846 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2847 return (dbl_p ? retval : retval + 1);
2851 if (src_code == MEM)
2852 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2854 if (src_code == CONST_INT)
2856 /* Don't use the X format, because that will give out of
2857 range numbers for 64 bit hosts and 32 bit targets. */
2859 return "li\t%0,%1\t\t\t# %X1";
2861 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2864 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2868 if (src_code == HIGH)
2869 return "lui\t%0,%h1";
2871 if (CONST_GP_P (src))
2872 return "move\t%0,%1";
2874 if (symbolic_operand (src, VOIDmode))
2875 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2877 if (src_code == REG && FP_REG_P (REGNO (src)))
2879 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2881 if (GET_MODE (dest) == V2SFmode)
2882 return "mov.ps\t%0,%1";
2884 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2887 if (dest_code == MEM)
2888 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2890 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2892 if (src_code == MEM)
2893 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2895 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2897 static char retval[] = "l_c_\t%0,%1";
2899 retval[1] = (dbl_p ? 'd' : 'w');
2900 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2903 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2905 static char retval[] = "s_c_\t%1,%0";
2907 retval[1] = (dbl_p ? 'd' : 'w');
2908 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2914 /* Restore $gp from its save slot. Valid only when using o32 or
2918 mips_restore_gp (void)
2922 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2924 address = mips_add_offset (pic_offset_table_rtx,
2925 frame_pointer_needed
2926 ? hard_frame_pointer_rtx
2927 : stack_pointer_rtx,
2928 current_function_outgoing_args_size);
2929 slot = gen_rtx_MEM (Pmode, address);
2931 emit_move_insn (pic_offset_table_rtx, slot);
2932 if (!TARGET_EXPLICIT_RELOCS)
2933 emit_insn (gen_blockage ());
2936 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2939 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2941 emit_insn (gen_rtx_SET (VOIDmode, target,
2942 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2945 /* Return true if CMP1 is a suitable second operand for relational
2946 operator CODE. See also the *sCC patterns in mips.md. */
2949 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2955 return reg_or_0_operand (cmp1, VOIDmode);
2959 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2963 return arith_operand (cmp1, VOIDmode);
2966 return sle_operand (cmp1, VOIDmode);
2969 return sleu_operand (cmp1, VOIDmode);
2976 /* Canonicalize LE or LEU comparisons into LT comparisons when
2977 possible to avoid extra instructions or inverting the
2981 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
2982 enum machine_mode mode)
2984 HOST_WIDE_INT original, plus_one;
2986 if (GET_CODE (*cmp1) != CONST_INT)
2989 original = INTVAL (*cmp1);
2990 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
2995 if (original < plus_one)
2998 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3007 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3020 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3021 result in TARGET. CMP0 and TARGET are register_operands that have
3022 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3023 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3026 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3027 rtx target, rtx cmp0, rtx cmp1)
3029 /* First see if there is a MIPS instruction that can do this operation
3030 with CMP1 in its current form. If not, try to canonicalize the
3031 comparison to LT. If that fails, try doing the same for the
3032 inverse operation. If that also fails, force CMP1 into a register
3034 if (mips_relational_operand_ok_p (code, cmp1))
3035 mips_emit_binary (code, target, cmp0, cmp1);
3036 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3037 mips_emit_binary (code, target, cmp0, cmp1);
3040 enum rtx_code inv_code = reverse_condition (code);
3041 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3043 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3044 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3046 else if (invert_ptr == 0)
3048 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3049 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3050 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3054 *invert_ptr = !*invert_ptr;
3055 mips_emit_binary (inv_code, target, cmp0, cmp1);
3060 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3061 The register will have the same mode as CMP0. */
3064 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3066 if (cmp1 == const0_rtx)
3069 if (uns_arith_operand (cmp1, VOIDmode))
3070 return expand_binop (GET_MODE (cmp0), xor_optab,
3071 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3073 return expand_binop (GET_MODE (cmp0), sub_optab,
3074 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3077 /* Convert a comparison into something that can be used in a branch or
3078 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3079 being compared and *CODE is the code used to compare them.
3081 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3082 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3083 otherwise any standard branch condition can be used. The standard branch
3086 - EQ/NE between two registers.
3087 - any comparison between a register and zero. */
3090 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3092 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3094 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3096 *op0 = cmp_operands[0];
3097 *op1 = cmp_operands[1];
3099 else if (*code == EQ || *code == NE)
3103 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3108 *op0 = cmp_operands[0];
3109 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3114 /* The comparison needs a separate scc instruction. Store the
3115 result of the scc in *OP0 and compare it against zero. */
3116 bool invert = false;
3117 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3119 mips_emit_int_relational (*code, &invert, *op0,
3120 cmp_operands[0], cmp_operands[1]);
3121 *code = (invert ? EQ : NE);
3126 enum rtx_code cmp_code;
3128 /* Floating-point tests use a separate c.cond.fmt comparison to
3129 set a condition code register. The branch or conditional move
3130 will then compare that register against zero.
3132 Set CMP_CODE to the code of the comparison instruction and
3133 *CODE to the code that the branch or move should use. */
3139 cmp_code = reverse_condition_maybe_unordered (*code);
3149 ? gen_reg_rtx (CCmode)
3150 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3152 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3156 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3157 Store the result in TARGET and return true if successful.
3159 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3162 mips_emit_scc (enum rtx_code code, rtx target)
3164 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3167 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3168 if (code == EQ || code == NE)
3170 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3171 mips_emit_binary (code, target, zie, const0_rtx);
3174 mips_emit_int_relational (code, 0, target,
3175 cmp_operands[0], cmp_operands[1]);
3179 /* Emit the common code for doing conditional branches.
3180 operand[0] is the label to jump to.
3181 The comparison operands are saved away by cmp{si,di,sf,df}. */
3184 gen_conditional_branch (rtx *operands, enum rtx_code code)
3186 rtx op0, op1, condition;
3188 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3189 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3190 emit_jump_insn (gen_condjump (condition, operands[0]));
3193 /* Emit the common code for conditional moves. OPERANDS is the array
3194 of operands passed to the conditional move define_expand. */
3197 gen_conditional_move (rtx *operands)
3202 code = GET_CODE (operands[1]);
3203 mips_emit_compare (&code, &op0, &op1, true);
3204 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3205 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3206 gen_rtx_fmt_ee (code,
3209 operands[2], operands[3])));
3212 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3213 the conditional_trap expander. */
3216 mips_gen_conditional_trap (rtx *operands)
3219 enum rtx_code cmp_code = GET_CODE (operands[0]);
3220 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3222 /* MIPS conditional trap machine instructions don't have GT or LE
3223 flavors, so we must invert the comparison and convert to LT and
3224 GE, respectively. */
3227 case GT: cmp_code = LT; break;
3228 case LE: cmp_code = GE; break;
3229 case GTU: cmp_code = LTU; break;
3230 case LEU: cmp_code = GEU; break;
3233 if (cmp_code == GET_CODE (operands[0]))
3235 op0 = cmp_operands[0];
3236 op1 = cmp_operands[1];
3240 op0 = cmp_operands[1];
3241 op1 = cmp_operands[0];
3243 op0 = force_reg (mode, op0);
3244 if (!arith_operand (op1, mode))
3245 op1 = force_reg (mode, op1);
3247 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3248 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3252 /* Load function address ADDR into register DEST. SIBCALL_P is true
3253 if the address is needed for a sibling call. */
3256 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3258 /* If we're generating PIC, and this call is to a global function,
3259 try to allow its address to be resolved lazily. This isn't
3260 possible for NewABI sibcalls since the value of $gp on entry
3261 to the stub would be our caller's gp, not ours. */
3262 if (TARGET_EXPLICIT_RELOCS
3263 && !(sibcall_p && TARGET_NEWABI)
3264 && global_got_operand (addr, VOIDmode))
3266 rtx high, lo_sum_symbol;
3268 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3269 addr, SYMBOL_GOTOFF_CALL);
3270 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3271 if (Pmode == SImode)
3272 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3274 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3277 emit_move_insn (dest, addr);
3281 /* Expand a call or call_value instruction. RESULT is where the
3282 result will go (null for calls), ADDR is the address of the
3283 function, ARGS_SIZE is the size of the arguments and AUX is
3284 the value passed to us by mips_function_arg. SIBCALL_P is true
3285 if we are expanding a sibling call, false if we're expanding
3289 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3291 rtx orig_addr, pattern, insn;
3294 if (!call_insn_operand (addr, VOIDmode))
3296 addr = gen_reg_rtx (Pmode);
3297 mips_load_call_address (addr, orig_addr, sibcall_p);
3301 && mips16_hard_float
3302 && build_mips16_call_stub (result, addr, args_size,
3303 aux == 0 ? 0 : (int) GET_MODE (aux)))
3307 pattern = (sibcall_p
3308 ? gen_sibcall_internal (addr, args_size)
3309 : gen_call_internal (addr, args_size));
3310 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3314 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3315 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3318 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3319 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3322 pattern = (sibcall_p
3323 ? gen_sibcall_value_internal (result, addr, args_size)
3324 : gen_call_value_internal (result, addr, args_size));
3326 insn = emit_call_insn (pattern);
3328 /* Lazy-binding stubs require $gp to be valid on entry. */
3329 if (global_got_operand (orig_addr, VOIDmode))
3330 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3334 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3337 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3338 tree exp ATTRIBUTE_UNUSED)
3340 return TARGET_SIBCALLS;
3343 /* Emit code to move general operand SRC into condition-code
3344 register DEST. SCRATCH is a scratch TFmode float register.
3351 where FP1 and FP2 are single-precision float registers
3352 taken from SCRATCH. */
3355 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3359 /* Change the source to SFmode. */
3361 src = adjust_address (src, SFmode, 0);
3362 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3363 src = gen_rtx_REG (SFmode, true_regnum (src));
3365 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3366 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3368 emit_move_insn (copy_rtx (fp1), src);
3369 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3370 emit_insn (gen_slt_sf (dest, fp2, fp1));
3373 /* Emit code to change the current function's return address to
3374 ADDRESS. SCRATCH is available as a scratch register, if needed.
3375 ADDRESS and SCRATCH are both word-mode GPRs. */
3378 mips_set_return_address (rtx address, rtx scratch)
3382 compute_frame_size (get_frame_size ());
3383 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3384 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3385 cfun->machine->frame.gp_sp_offset);
3387 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3390 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3391 Assume that the areas do not overlap. */
3394 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3396 HOST_WIDE_INT offset, delta;
3397 unsigned HOST_WIDE_INT bits;
3399 enum machine_mode mode;
3402 /* Work out how many bits to move at a time. If both operands have
3403 half-word alignment, it is usually better to move in half words.
3404 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3405 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3406 Otherwise move word-sized chunks. */
3407 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3408 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3409 bits = BITS_PER_WORD / 2;
3411 bits = BITS_PER_WORD;
3413 mode = mode_for_size (bits, MODE_INT, 0);
3414 delta = bits / BITS_PER_UNIT;
3416 /* Allocate a buffer for the temporary registers. */
3417 regs = alloca (sizeof (rtx) * length / delta);
3419 /* Load as many BITS-sized chunks as possible. Use a normal load if
3420 the source has enough alignment, otherwise use left/right pairs. */
3421 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3423 regs[i] = gen_reg_rtx (mode);
3424 if (MEM_ALIGN (src) >= bits)
3425 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3428 rtx part = adjust_address (src, BLKmode, offset);
3429 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3434 /* Copy the chunks to the destination. */
3435 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3436 if (MEM_ALIGN (dest) >= bits)
3437 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3440 rtx part = adjust_address (dest, BLKmode, offset);
3441 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3445 /* Mop up any left-over bytes. */
3446 if (offset < length)
3448 src = adjust_address (src, BLKmode, offset);
3449 dest = adjust_address (dest, BLKmode, offset);
3450 move_by_pieces (dest, src, length - offset,
3451 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3455 #define MAX_MOVE_REGS 4
3456 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3459 /* Helper function for doing a loop-based block operation on memory
3460 reference MEM. Each iteration of the loop will operate on LENGTH
3463 Create a new base register for use within the loop and point it to
3464 the start of MEM. Create a new memory reference that uses this
3465 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3468 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3469 rtx *loop_reg, rtx *loop_mem)
3471 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3473 /* Although the new mem does not refer to a known location,
3474 it does keep up to LENGTH bytes of alignment. */
3475 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3476 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3480 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3481 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3482 memory regions do not overlap. */
3485 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3487 rtx label, src_reg, dest_reg, final_src;
3488 HOST_WIDE_INT leftover;
3490 leftover = length % MAX_MOVE_BYTES;
3493 /* Create registers and memory references for use within the loop. */
3494 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3495 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3497 /* Calculate the value that SRC_REG should have after the last iteration
3499 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3502 /* Emit the start of the loop. */
3503 label = gen_label_rtx ();
3506 /* Emit the loop body. */
3507 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3509 /* Move on to the next block. */
3510 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3511 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3513 /* Emit the loop condition. */
3514 if (Pmode == DImode)
3515 emit_insn (gen_cmpdi (src_reg, final_src));
3517 emit_insn (gen_cmpsi (src_reg, final_src));
3518 emit_jump_insn (gen_bne (label));
3520 /* Mop up any left-over bytes. */
3522 mips_block_move_straight (dest, src, leftover);
3525 /* Expand a movmemsi instruction. */
3528 mips_expand_block_move (rtx dest, rtx src, rtx length)
3530 if (GET_CODE (length) == CONST_INT)
3532 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3534 mips_block_move_straight (dest, src, INTVAL (length));
3539 mips_block_move_loop (dest, src, INTVAL (length));
3546 /* Argument support functions. */
3548 /* Initialize CUMULATIVE_ARGS for a function. */
3551 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3552 rtx libname ATTRIBUTE_UNUSED)
3554 static CUMULATIVE_ARGS zero_cum;
3555 tree param, next_param;
3558 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3560 /* Determine if this function has variable arguments. This is
3561 indicated by the last argument being 'void_type_mode' if there
3562 are no variable arguments. The standard MIPS calling sequence
3563 passes all arguments in the general purpose registers in this case. */
3565 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3566 param != 0; param = next_param)
3568 next_param = TREE_CHAIN (param);
3569 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3570 cum->gp_reg_found = 1;
3575 /* Fill INFO with information about a single argument. CUM is the
3576 cumulative state for earlier arguments. MODE is the mode of this
3577 argument and TYPE is its type (if known). NAMED is true if this
3578 is a named (fixed) argument rather than a variable one. */
3581 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3582 tree type, int named, struct mips_arg_info *info)
3584 bool doubleword_aligned_p;
3585 unsigned int num_bytes, num_words, max_regs;
3587 /* Work out the size of the argument. */
3588 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3589 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3591 /* Decide whether it should go in a floating-point register, assuming
3592 one is free. Later code checks for availability.
3594 The checks against UNITS_PER_FPVALUE handle the soft-float and
3595 single-float cases. */
3599 /* The EABI conventions have traditionally been defined in terms
3600 of TYPE_MODE, regardless of the actual type. */
3601 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3602 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3603 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3608 /* Only leading floating-point scalars are passed in
3609 floating-point registers. We also handle vector floats the same
3610 say, which is OK because they are not covered by the standard ABI. */
3611 info->fpr_p = (!cum->gp_reg_found
3612 && cum->arg_number < 2
3613 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3614 || VECTOR_FLOAT_TYPE_P (type))
3615 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3616 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3617 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3622 /* Scalar and complex floating-point types are passed in
3623 floating-point registers. */
3624 info->fpr_p = (named
3625 && (type == 0 || FLOAT_TYPE_P (type))
3626 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3627 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3628 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3629 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3631 /* ??? According to the ABI documentation, the real and imaginary
3632 parts of complex floats should be passed in individual registers.
3633 The real and imaginary parts of stack arguments are supposed
3634 to be contiguous and there should be an extra word of padding
3637 This has two problems. First, it makes it impossible to use a
3638 single "void *" va_list type, since register and stack arguments
3639 are passed differently. (At the time of writing, MIPSpro cannot
3640 handle complex float varargs correctly.) Second, it's unclear
3641 what should happen when there is only one register free.
3643 For now, we assume that named complex floats should go into FPRs
3644 if there are two FPRs free, otherwise they should be passed in the
3645 same way as a struct containing two floats. */
3647 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3648 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3650 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3651 info->fpr_p = false;
3661 /* See whether the argument has doubleword alignment. */
3662 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3664 /* Set REG_OFFSET to the register count we're interested in.
3665 The EABI allocates the floating-point registers separately,
3666 but the other ABIs allocate them like integer registers. */
3667 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3671 /* Advance to an even register if the argument is doubleword-aligned. */
3672 if (doubleword_aligned_p)
3673 info->reg_offset += info->reg_offset & 1;
3675 /* Work out the offset of a stack argument. */
3676 info->stack_offset = cum->stack_words;
3677 if (doubleword_aligned_p)
3678 info->stack_offset += info->stack_offset & 1;
3680 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3682 /* Partition the argument between registers and stack. */
3683 info->reg_words = MIN (num_words, max_regs);
3684 info->stack_words = num_words - info->reg_words;
3688 /* Implement FUNCTION_ARG_ADVANCE. */
3691 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3692 tree type, int named)
3694 struct mips_arg_info info;
3696 mips_arg_info (cum, mode, type, named, &info);
3699 cum->gp_reg_found = true;
3701 /* See the comment above the cumulative args structure in mips.h
3702 for an explanation of what this code does. It assumes the O32
3703 ABI, which passes at most 2 arguments in float registers. */
3704 if (cum->arg_number < 2 && info.fpr_p)
3705 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3707 if (mips_abi != ABI_EABI || !info.fpr_p)
3708 cum->num_gprs = info.reg_offset + info.reg_words;
3709 else if (info.reg_words > 0)
3710 cum->num_fprs += FP_INC;
3712 if (info.stack_words > 0)
3713 cum->stack_words = info.stack_offset + info.stack_words;
3718 /* Implement FUNCTION_ARG. */
3721 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3722 tree type, int named)
3724 struct mips_arg_info info;
3726 /* We will be called with a mode of VOIDmode after the last argument
3727 has been seen. Whatever we return will be passed to the call
3728 insn. If we need a mips16 fp_code, return a REG with the code
3729 stored as the mode. */
3730 if (mode == VOIDmode)
3732 if (TARGET_MIPS16 && cum->fp_code != 0)
3733 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3739 mips_arg_info (cum, mode, type, named, &info);
3741 /* Return straight away if the whole argument is passed on the stack. */
3742 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3746 && TREE_CODE (type) == RECORD_TYPE
3748 && TYPE_SIZE_UNIT (type)
3749 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3752 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3753 structure contains a double in its entirety, then that 64 bit
3754 chunk is passed in a floating point register. */
3757 /* First check to see if there is any such field. */
3758 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3759 if (TREE_CODE (field) == FIELD_DECL
3760 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3761 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3762 && host_integerp (bit_position (field), 0)
3763 && int_bit_position (field) % BITS_PER_WORD == 0)
3768 /* Now handle the special case by returning a PARALLEL
3769 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3770 chunks are passed in registers. */
3772 HOST_WIDE_INT bitpos;
3775 /* assign_parms checks the mode of ENTRY_PARM, so we must
3776 use the actual mode here. */
3777 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3780 field = TYPE_FIELDS (type);
3781 for (i = 0; i < info.reg_words; i++)
3785 for (; field; field = TREE_CHAIN (field))
3786 if (TREE_CODE (field) == FIELD_DECL
3787 && int_bit_position (field) >= bitpos)
3791 && int_bit_position (field) == bitpos
3792 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3793 && !TARGET_SOFT_FLOAT
3794 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3795 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3797 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3800 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3801 GEN_INT (bitpos / BITS_PER_UNIT));
3803 bitpos += BITS_PER_WORD;
3809 /* Handle the n32/n64 conventions for passing complex floating-point
3810 arguments in FPR pairs. The real part goes in the lower register
3811 and the imaginary part goes in the upper register. */
3814 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3817 enum machine_mode inner;
3820 inner = GET_MODE_INNER (mode);
3821 reg = FP_ARG_FIRST + info.reg_offset;
3822 real = gen_rtx_EXPR_LIST (VOIDmode,
3823 gen_rtx_REG (inner, reg),
3825 imag = gen_rtx_EXPR_LIST (VOIDmode,
3826 gen_rtx_REG (inner, reg + info.reg_words / 2),
3827 GEN_INT (GET_MODE_SIZE (inner)));
3828 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3832 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3833 else if (info.reg_offset == 1)
3834 /* This code handles the special o32 case in which the second word
3835 of the argument structure is passed in floating-point registers. */
3836 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3838 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3842 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3845 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3846 enum machine_mode mode, tree type, bool named)
3848 struct mips_arg_info info;
3850 mips_arg_info (cum, mode, type, named, &info);
3851 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3855 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3856 PARM_BOUNDARY bits of alignment, but will be given anything up
3857 to STACK_BOUNDARY bits if the type requires it. */
3860 function_arg_boundary (enum machine_mode mode, tree type)
3862 unsigned int alignment;
3864 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3865 if (alignment < PARM_BOUNDARY)
3866 alignment = PARM_BOUNDARY;
3867 if (alignment > STACK_BOUNDARY)
3868 alignment = STACK_BOUNDARY;
3872 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3873 upward rather than downward. In other words, return true if the
3874 first byte of the stack slot has useful data, false if the last
3878 mips_pad_arg_upward (enum machine_mode mode, tree type)
3880 /* On little-endian targets, the first byte of every stack argument
3881 is passed in the first byte of the stack slot. */
3882 if (!BYTES_BIG_ENDIAN)
3885 /* Otherwise, integral types are padded downward: the last byte of a
3886 stack argument is passed in the last byte of the stack slot. */
3888 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3889 : GET_MODE_CLASS (mode) == MODE_INT)
3892 /* Big-endian o64 pads floating-point arguments downward. */
3893 if (mips_abi == ABI_O64)
3894 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3897 /* Other types are padded upward for o32, o64, n32 and n64. */
3898 if (mips_abi != ABI_EABI)
3901 /* Arguments smaller than a stack slot are padded downward. */
3902 if (mode != BLKmode)
3903 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3905 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3909 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3910 if the least significant byte of the register has useful data. Return
3911 the opposite if the most significant byte does. */
3914 mips_pad_reg_upward (enum machine_mode mode, tree type)
3916 /* No shifting is required for floating-point arguments. */
3917 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3918 return !BYTES_BIG_ENDIAN;
3920 /* Otherwise, apply the same padding to register arguments as we do
3921 to stack arguments. */
3922 return mips_pad_arg_upward (mode, type);
3926 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3927 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3930 CUMULATIVE_ARGS local_cum;
3931 int gp_saved, fp_saved;
3933 /* The caller has advanced CUM up to, but not beyond, the last named
3934 argument. Advance a local copy of CUM past the last "real" named
3935 argument, to find out how many registers are left over. */
3938 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3940 /* Found out how many registers we need to save. */
3941 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3942 fp_saved = (EABI_FLOAT_VARARGS_P
3943 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3952 ptr = plus_constant (virtual_incoming_args_rtx,
3953 REG_PARM_STACK_SPACE (cfun->decl)
3954 - gp_saved * UNITS_PER_WORD);
3955 mem = gen_rtx_MEM (BLKmode, ptr);
3956 set_mem_alias_set (mem, get_varargs_alias_set ());
3958 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3963 /* We can't use move_block_from_reg, because it will use
3965 enum machine_mode mode;
3968 /* Set OFF to the offset from virtual_incoming_args_rtx of
3969 the first float register. The FP save area lies below
3970 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3971 off = -gp_saved * UNITS_PER_WORD;
3972 off &= ~(UNITS_PER_FPVALUE - 1);
3973 off -= fp_saved * UNITS_PER_FPREG;
3975 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3977 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3981 ptr = plus_constant (virtual_incoming_args_rtx, off);
3982 mem = gen_rtx_MEM (mode, ptr);
3983 set_mem_alias_set (mem, get_varargs_alias_set ());
3984 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3985 off += UNITS_PER_HWFPVALUE;
3989 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
3990 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
3991 + fp_saved * UNITS_PER_FPREG);
3994 /* Create the va_list data type.
3995 We keep 3 pointers, and two offsets.
3996 Two pointers are to the overflow area, which starts at the CFA.
3997 One of these is constant, for addressing into the GPR save area below it.
3998 The other is advanced up the stack through the overflow region.
3999 The third pointer is to the GPR save area. Since the FPR save area
4000 is just below it, we can address FPR slots off this pointer.
4001 We also keep two one-byte offsets, which are to be subtracted from the
4002 constant pointers to yield addresses in the GPR and FPR save areas.
4003 These are downcounted as float or non-float arguments are used,
4004 and when they get to zero, the argument must be obtained from the
4006 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4007 pointer is enough. It's started at the GPR save area, and is
4009 Note that the GPR save area is not constant size, due to optimization
4010 in the prologue. Hence, we can't use a design with two pointers
4011 and two offsets, although we could have designed this with two pointers
4012 and three offsets. */
4015 mips_build_builtin_va_list (void)
4017 if (EABI_FLOAT_VARARGS_P)
4019 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4022 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4024 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4026 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4028 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4030 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4031 unsigned_char_type_node);
4032 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4033 unsigned_char_type_node);
4034 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4035 warn on every user file. */
4036 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4037 array = build_array_type (unsigned_char_type_node,
4038 build_index_type (index));
4039 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4041 DECL_FIELD_CONTEXT (f_ovfl) = record;
4042 DECL_FIELD_CONTEXT (f_gtop) = record;
4043 DECL_FIELD_CONTEXT (f_ftop) = record;
4044 DECL_FIELD_CONTEXT (f_goff) = record;
4045 DECL_FIELD_CONTEXT (f_foff) = record;
4046 DECL_FIELD_CONTEXT (f_res) = record;
4048 TYPE_FIELDS (record) = f_ovfl;
4049 TREE_CHAIN (f_ovfl) = f_gtop;
4050 TREE_CHAIN (f_gtop) = f_ftop;
4051 TREE_CHAIN (f_ftop) = f_goff;
4052 TREE_CHAIN (f_goff) = f_foff;
4053 TREE_CHAIN (f_foff) = f_res;
4055 layout_type (record);
4058 else if (TARGET_IRIX && TARGET_IRIX6)
4059 /* On IRIX 6, this type is 'char *'. */
4060 return build_pointer_type (char_type_node);
4062 /* Otherwise, we use 'void *'. */
4063 return ptr_type_node;
4066 /* Implement va_start. */
4069 mips_va_start (tree valist, rtx nextarg)
4071 if (EABI_FLOAT_VARARGS_P)
4073 const CUMULATIVE_ARGS *cum;
4074 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4075 tree ovfl, gtop, ftop, goff, foff;
4077 int gpr_save_area_size;
4078 int fpr_save_area_size;
4081 cum = ¤t_function_args_info;
4083 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4085 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4087 f_ovfl = TYPE_FIELDS (va_list_type_node);
4088 f_gtop = TREE_CHAIN (f_ovfl);
4089 f_ftop = TREE_CHAIN (f_gtop);
4090 f_goff = TREE_CHAIN (f_ftop);
4091 f_foff = TREE_CHAIN (f_goff);
4093 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4095 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4097 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4099 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4101 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4104 /* Emit code to initialize OVFL, which points to the next varargs
4105 stack argument. CUM->STACK_WORDS gives the number of stack
4106 words used by named arguments. */
4107 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4108 if (cum->stack_words > 0)
4109 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4110 build_int_cst (NULL_TREE,
4111 cum->stack_words * UNITS_PER_WORD));
4112 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4113 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4115 /* Emit code to initialize GTOP, the top of the GPR save area. */
4116 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4117 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4118 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4120 /* Emit code to initialize FTOP, the top of the FPR save area.
4121 This address is gpr_save_area_bytes below GTOP, rounded
4122 down to the next fp-aligned boundary. */
4123 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4124 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4125 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4127 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4128 build_int_cst (NULL_TREE, -fpr_offset));
4129 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4130 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4132 /* Emit code to initialize GOFF, the offset from GTOP of the
4133 next GPR argument. */
4134 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4135 build_int_cst (NULL_TREE, gpr_save_area_size));
4136 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4138 /* Likewise emit code to initialize FOFF, the offset from FTOP
4139 of the next FPR argument. */
4140 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4141 build_int_cst (NULL_TREE, fpr_save_area_size));
4142 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4146 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4147 std_expand_builtin_va_start (valist, nextarg);
4151 /* Implement va_arg. */
4154 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4156 HOST_WIDE_INT size, rsize;
4160 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4163 type = build_pointer_type (type);
4165 size = int_size_in_bytes (type);
4166 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4168 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4169 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4172 /* Not a simple merged stack. */
4174 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4175 tree ovfl, top, off, align;
4176 HOST_WIDE_INT osize;
4179 f_ovfl = TYPE_FIELDS (va_list_type_node);
4180 f_gtop = TREE_CHAIN (f_ovfl);
4181 f_ftop = TREE_CHAIN (f_gtop);
4182 f_goff = TREE_CHAIN (f_ftop);
4183 f_foff = TREE_CHAIN (f_goff);
4185 /* We maintain separate pointers and offsets for floating-point
4186 and integer arguments, but we need similar code in both cases.
4189 TOP be the top of the register save area;
4190 OFF be the offset from TOP of the next register;
4191 ADDR_RTX be the address of the argument;
4192 RSIZE be the number of bytes used to store the argument
4193 when it's in the register save area;
4194 OSIZE be the number of bytes used to store it when it's
4195 in the stack overflow area; and
4196 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4198 The code we want is:
4200 1: off &= -rsize; // round down
4203 4: addr_rtx = top - off;
4208 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4209 10: addr_rtx = ovfl + PADDING;
4213 [1] and [9] can sometimes be optimized away. */
4215 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4218 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4219 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4221 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4223 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4226 /* When floating-point registers are saved to the stack,
4227 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4228 of the float's precision. */
4229 rsize = UNITS_PER_HWFPVALUE;
4231 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4232 (= PARM_BOUNDARY bits). This can be different from RSIZE
4235 (1) On 32-bit targets when TYPE is a structure such as:
4237 struct s { float f; };
4239 Such structures are passed in paired FPRs, so RSIZE
4240 will be 8 bytes. However, the structure only takes
4241 up 4 bytes of memory, so OSIZE will only be 4.
4243 (2) In combinations such as -mgp64 -msingle-float
4244 -fshort-double. Doubles passed in registers
4245 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4246 but those passed on the stack take up
4247 UNITS_PER_WORD bytes. */
4248 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4252 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4254 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4256 if (rsize > UNITS_PER_WORD)
4258 /* [1] Emit code for: off &= -rsize. */
4259 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4260 build_int_cst (NULL_TREE, -rsize));
4261 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4262 gimplify_and_add (t, pre_p);
4267 /* [2] Emit code to branch if off == 0. */
4268 t = build2 (NE_EXPR, boolean_type_node, off,
4269 build_int_cst (TREE_TYPE (off), 0));
4270 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4272 /* [5] Emit code for: off -= rsize. We do this as a form of
4273 post-increment not available to C. Also widen for the
4274 coming pointer arithmetic. */
4275 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4276 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4277 t = fold_convert (sizetype, t);
4278 t = fold_convert (TREE_TYPE (top), t);
4280 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4281 the argument has RSIZE - SIZE bytes of leading padding. */
4282 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4283 if (BYTES_BIG_ENDIAN && rsize > size)
4285 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4287 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4289 COND_EXPR_THEN (addr) = t;
4291 if (osize > UNITS_PER_WORD)
4293 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4294 u = fold_convert (TREE_TYPE (ovfl),
4295 build_int_cst (NULL_TREE, osize - 1));
4296 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4297 u = fold_convert (TREE_TYPE (ovfl),
4298 build_int_cst (NULL_TREE, -osize));
4299 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4300 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4305 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4306 post-increment ovfl by osize. On big-endian machines,
4307 the argument has OSIZE - SIZE bytes of leading padding. */
4308 u = fold_convert (TREE_TYPE (ovfl),
4309 build_int_cst (NULL_TREE, osize));
4310 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4311 if (BYTES_BIG_ENDIAN && osize > size)
4313 u = fold_convert (TREE_TYPE (t),
4314 build_int_cst (NULL_TREE, osize - size));
4315 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4318 /* String [9] and [10,11] together. */
4320 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4321 COND_EXPR_ELSE (addr) = t;
4323 addr = fold_convert (build_pointer_type (type), addr);
4324 addr = build_va_arg_indirect_ref (addr);
4328 addr = build_va_arg_indirect_ref (addr);
4333 /* Return true if it is possible to use left/right accesses for a
4334 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4335 returning true, update *OP, *LEFT and *RIGHT as follows:
4337 *OP is a BLKmode reference to the whole field.
4339 *LEFT is a QImode reference to the first byte if big endian or
4340 the last byte if little endian. This address can be used in the
4341 left-side instructions (lwl, swl, ldl, sdl).
4343 *RIGHT is a QImode reference to the opposite end of the field and
4344 can be used in the patterning right-side instruction. */
4347 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4348 rtx *left, rtx *right)
4352 /* Check that the operand really is a MEM. Not all the extv and
4353 extzv predicates are checked. */
4357 /* Check that the size is valid. */
4358 if (width != 32 && (!TARGET_64BIT || width != 64))
4361 /* We can only access byte-aligned values. Since we are always passed
4362 a reference to the first byte of the field, it is not necessary to
4363 do anything with BITPOS after this check. */
4364 if (bitpos % BITS_PER_UNIT != 0)
4367 /* Reject aligned bitfields: we want to use a normal load or store
4368 instead of a left/right pair. */
4369 if (MEM_ALIGN (*op) >= width)
4372 /* Adjust *OP to refer to the whole field. This also has the effect
4373 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4374 *op = adjust_address (*op, BLKmode, 0);
4375 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4377 /* Get references to both ends of the field. We deliberately don't
4378 use the original QImode *OP for FIRST since the new BLKmode one
4379 might have a simpler address. */
4380 first = adjust_address (*op, QImode, 0);
4381 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4383 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4384 be the upper word and RIGHT the lower word. */
4385 if (TARGET_BIG_ENDIAN)
4386 *left = first, *right = last;
4388 *left = last, *right = first;
4394 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4395 Return true on success. We only handle cases where zero_extract is
4396 equivalent to sign_extract. */
4399 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4401 rtx left, right, temp;
4403 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4404 paradoxical word_mode subreg. This is the only case in which
4405 we allow the destination to be larger than the source. */
4406 if (GET_CODE (dest) == SUBREG
4407 && GET_MODE (dest) == DImode
4408 && SUBREG_BYTE (dest) == 0
4409 && GET_MODE (SUBREG_REG (dest)) == SImode)
4410 dest = SUBREG_REG (dest);
4412 /* After the above adjustment, the destination must be the same
4413 width as the source. */
4414 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4417 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4420 temp = gen_reg_rtx (GET_MODE (dest));
4421 if (GET_MODE (dest) == DImode)
4423 emit_insn (gen_mov_ldl (temp, src, left));
4424 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4428 emit_insn (gen_mov_lwl (temp, src, left));
4429 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4435 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4439 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4443 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4446 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4448 if (GET_MODE (src) == DImode)
4450 emit_insn (gen_mov_sdl (dest, src, left));
4451 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4455 emit_insn (gen_mov_swl (dest, src, left));
4456 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4461 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4462 source of an "ext" instruction or the destination of an "ins"
4463 instruction. OP must be a register operand and the following
4464 conditions must hold:
4466 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4467 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4468 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4470 Also reject lengths equal to a word as they are better handled
4471 by the move patterns. */
4474 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4476 HOST_WIDE_INT len, pos;
4478 if (!ISA_HAS_EXT_INS
4479 || !register_operand (op, VOIDmode)
4480 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4483 len = INTVAL (size);
4484 pos = INTVAL (position);
4486 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4487 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4493 /* Set up globals to generate code for the ISA or processor
4494 described by INFO. */
4497 mips_set_architecture (const struct mips_cpu_info *info)
4501 mips_arch_info = info;
4502 mips_arch = info->cpu;
4503 mips_isa = info->isa;
4508 /* Likewise for tuning. */
4511 mips_set_tune (const struct mips_cpu_info *info)
4515 mips_tune_info = info;
4516 mips_tune = info->cpu;
4520 /* Implement TARGET_HANDLE_OPTION. */
4523 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4528 if (strcmp (arg, "32") == 0)
4530 else if (strcmp (arg, "o64") == 0)
4532 else if (strcmp (arg, "n32") == 0)
4534 else if (strcmp (arg, "64") == 0)
4536 else if (strcmp (arg, "eabi") == 0)
4537 mips_abi = ABI_EABI;
4544 return mips_parse_cpu (arg) != 0;
4547 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4548 return mips_isa_info != 0;
4550 case OPT_mno_flush_func:
4551 mips_cache_flush_func = NULL;
4559 /* Set up the threshold for data to go into the small data area, instead
4560 of the normal data area, and detect any conflicts in the switches. */
4563 override_options (void)
4565 int i, start, regno;
4566 enum machine_mode mode;
4568 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4570 /* The following code determines the architecture and register size.
4571 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4572 The GAS and GCC code should be kept in sync as much as possible. */
4574 if (mips_arch_string != 0)
4575 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4577 if (mips_isa_info != 0)
4579 if (mips_arch_info == 0)
4580 mips_set_architecture (mips_isa_info);
4581 else if (mips_arch_info->isa != mips_isa_info->isa)
4582 error ("-%s conflicts with the other architecture options, "
4583 "which specify a %s processor",
4584 mips_isa_info->name,
4585 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4588 if (mips_arch_info == 0)
4590 #ifdef MIPS_CPU_STRING_DEFAULT
4591 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4593 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4597 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4598 error ("-march=%s is not compatible with the selected ABI",
4599 mips_arch_info->name);
4601 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4602 if (mips_tune_string != 0)
4603 mips_set_tune (mips_parse_cpu (mips_tune_string));
4605 if (mips_tune_info == 0)
4606 mips_set_tune (mips_arch_info);
4608 /* Set cost structure for the processor. */
4609 mips_cost = &mips_rtx_cost_data[mips_tune];
4611 if ((target_flags_explicit & MASK_64BIT) != 0)
4613 /* The user specified the size of the integer registers. Make sure
4614 it agrees with the ABI and ISA. */
4615 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4616 error ("-mgp64 used with a 32-bit processor");
4617 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4618 error ("-mgp32 used with a 64-bit ABI");
4619 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4620 error ("-mgp64 used with a 32-bit ABI");
4624 /* Infer the integer register size from the ABI and processor.
4625 Restrict ourselves to 32-bit registers if that's all the
4626 processor has, or if the ABI cannot handle 64-bit registers. */
4627 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4628 target_flags &= ~MASK_64BIT;
4630 target_flags |= MASK_64BIT;
4633 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4635 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4636 only one right answer here. */
4637 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4638 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4639 else if (!TARGET_64BIT && TARGET_FLOAT64)
4640 error ("unsupported combination: %s", "-mgp32 -mfp64");
4641 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4642 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4646 /* -msingle-float selects 32-bit float registers. Otherwise the
4647 float registers should be the same size as the integer ones. */
4648 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4649 target_flags |= MASK_FLOAT64;
4651 target_flags &= ~MASK_FLOAT64;
4654 /* End of code shared with GAS. */
4656 if ((target_flags_explicit & MASK_LONG64) == 0)
4658 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4659 target_flags |= MASK_LONG64;
4661 target_flags &= ~MASK_LONG64;
4664 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4665 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4667 /* For some configurations, it is useful to have -march control
4668 the default setting of MASK_SOFT_FLOAT. */
4669 switch ((int) mips_arch)
4671 case PROCESSOR_R4100:
4672 case PROCESSOR_R4111:
4673 case PROCESSOR_R4120:
4674 case PROCESSOR_R4130:
4675 target_flags |= MASK_SOFT_FLOAT;
4679 target_flags &= ~MASK_SOFT_FLOAT;
4685 flag_pcc_struct_return = 0;
4687 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4689 /* If neither -mbranch-likely nor -mno-branch-likely was given
4690 on the command line, set MASK_BRANCHLIKELY based on the target
4693 By default, we enable use of Branch Likely instructions on
4694 all architectures which support them with the following
4695 exceptions: when creating MIPS32 or MIPS64 code, and when
4696 tuning for architectures where their use tends to hurt
4699 The MIPS32 and MIPS64 architecture specifications say "Software
4700 is strongly encouraged to avoid use of Branch Likely
4701 instructions, as they will be removed from a future revision
4702 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4703 issue those instructions unless instructed to do so by
4705 if (ISA_HAS_BRANCHLIKELY
4706 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4707 && !(TUNE_MIPS5500 || TUNE_SB1))
4708 target_flags |= MASK_BRANCHLIKELY;
4710 target_flags &= ~MASK_BRANCHLIKELY;
4712 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4713 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4715 /* The effect of -mabicalls isn't defined for the EABI. */
4716 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4718 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4719 target_flags &= ~MASK_ABICALLS;
4722 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4723 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4724 /* ??? -non_shared turns off pic code generation, but this is not
4726 if (TARGET_ABICALLS)
4729 if (mips_section_threshold > 0)
4730 warning (0, "-G is incompatible with PIC code which is the default");
4733 /* mips_split_addresses is a half-way house between explicit
4734 relocations and the traditional assembler macros. It can
4735 split absolute 32-bit symbolic constants into a high/lo_sum
4736 pair but uses macros for other sorts of access.
4738 Like explicit relocation support for REL targets, it relies
4739 on GNU extensions in the assembler and the linker.
4741 Although this code should work for -O0, it has traditionally
4742 been treated as an optimization. */
4743 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4744 && optimize && !flag_pic
4745 && !ABI_HAS_64BIT_SYMBOLS)
4746 mips_split_addresses = 1;
4748 mips_split_addresses = 0;
4750 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4751 faster code, but at the expense of more nops. Enable it at -O3 and
4753 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4754 target_flags |= MASK_VR4130_ALIGN;
4756 /* When compiling for the mips16, we cannot use floating point. We
4757 record the original hard float value in mips16_hard_float. */
4760 if (TARGET_SOFT_FLOAT)
4761 mips16_hard_float = 0;
4763 mips16_hard_float = 1;
4764 target_flags |= MASK_SOFT_FLOAT;
4766 /* Don't run the scheduler before reload, since it tends to
4767 increase register pressure. */
4768 flag_schedule_insns = 0;
4770 /* Don't do hot/cold partitioning. The constant layout code expects
4771 the whole function to be in a single section. */
4772 flag_reorder_blocks_and_partition = 0;
4774 /* Silently disable -mexplicit-relocs since it doesn't apply
4775 to mips16 code. Even so, it would overly pedantic to warn
4776 about "-mips16 -mexplicit-relocs", especially given that
4777 we use a %gprel() operator. */
4778 target_flags &= ~MASK_EXPLICIT_RELOCS;
4781 /* When using explicit relocs, we call dbr_schedule from within
4783 if (TARGET_EXPLICIT_RELOCS)
4785 mips_flag_delayed_branch = flag_delayed_branch;
4786 flag_delayed_branch = 0;
4789 #ifdef MIPS_TFMODE_FORMAT
4790 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4793 /* Make sure that the user didn't turn off paired single support when
4794 MIPS-3D support is requested. */
4795 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4796 && !TARGET_PAIRED_SINGLE_FLOAT)
4797 error ("-mips3d requires -mpaired-single");
4799 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4801 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4803 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4804 and TARGET_HARD_FLOAT are both true. */
4805 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4806 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4808 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4810 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4811 error ("-mips3d/-mpaired-single must be used with -mips64");
4813 if (TARGET_MIPS16 && TARGET_DSP)
4814 error ("-mips16 and -mdsp cannot be used together");
4816 mips_print_operand_punct['?'] = 1;
4817 mips_print_operand_punct['#'] = 1;
4818 mips_print_operand_punct['/'] = 1;
4819 mips_print_operand_punct['&'] = 1;
4820 mips_print_operand_punct['!'] = 1;
4821 mips_print_operand_punct['*'] = 1;
4822 mips_print_operand_punct['@'] = 1;
4823 mips_print_operand_punct['.'] = 1;
4824 mips_print_operand_punct['('] = 1;
4825 mips_print_operand_punct[')'] = 1;
4826 mips_print_operand_punct['['] = 1;
4827 mips_print_operand_punct[']'] = 1;
4828 mips_print_operand_punct['<'] = 1;
4829 mips_print_operand_punct['>'] = 1;
4830 mips_print_operand_punct['{'] = 1;
4831 mips_print_operand_punct['}'] = 1;
4832 mips_print_operand_punct['^'] = 1;
4833 mips_print_operand_punct['$'] = 1;
4834 mips_print_operand_punct['+'] = 1;
4835 mips_print_operand_punct['~'] = 1;
4837 /* Set up array to map GCC register number to debug register number.
4838 Ignore the special purpose register numbers. */
4840 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4841 mips_dbx_regno[i] = -1;
4843 start = GP_DBX_FIRST - GP_REG_FIRST;
4844 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4845 mips_dbx_regno[i] = i + start;
4847 start = FP_DBX_FIRST - FP_REG_FIRST;
4848 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4849 mips_dbx_regno[i] = i + start;
4851 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4852 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4854 /* Set up array giving whether a given register can hold a given mode. */
4856 for (mode = VOIDmode;
4857 mode != MAX_MACHINE_MODE;
4858 mode = (enum machine_mode) ((int)mode + 1))
4860 register int size = GET_MODE_SIZE (mode);
4861 register enum mode_class class = GET_MODE_CLASS (mode);
4863 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4867 if (mode == CCV2mode)
4870 && (regno - ST_REG_FIRST) % 2 == 0);
4872 else if (mode == CCV4mode)
4875 && (regno - ST_REG_FIRST) % 4 == 0);
4877 else if (mode == CCmode)
4880 temp = (regno == FPSW_REGNUM);
4882 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4883 || FP_REG_P (regno));
4886 else if (GP_REG_P (regno))
4887 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4889 else if (FP_REG_P (regno))
4890 temp = ((regno % FP_INC) == 0)
4891 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4892 || class == MODE_VECTOR_FLOAT)
4893 && size <= UNITS_PER_FPVALUE)
4894 /* Allow integer modes that fit into a single
4895 register. We need to put integers into FPRs
4896 when using instructions like cvt and trunc.
4897 We can't allow sizes smaller than a word,
4898 the FPU has no appropriate load/store
4899 instructions for those. */
4900 || (class == MODE_INT
4901 && size >= MIN_UNITS_PER_WORD
4902 && size <= UNITS_PER_FPREG)
4903 /* Allow TFmode for CCmode reloads. */
4904 || (ISA_HAS_8CC && mode == TFmode));
4906 else if (ACC_REG_P (regno))
4907 temp = (INTEGRAL_MODE_P (mode)
4908 && (size <= UNITS_PER_WORD
4909 || (ACC_HI_REG_P (regno)
4910 && size == 2 * UNITS_PER_WORD)));
4912 else if (ALL_COP_REG_P (regno))
4913 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4917 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4921 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4922 initialized yet, so we can't use that here. */
4923 gpr_mode = TARGET_64BIT ? DImode : SImode;
4925 /* Provide default values for align_* for 64-bit targets. */
4926 if (TARGET_64BIT && !TARGET_MIPS16)
4928 if (align_loops == 0)
4930 if (align_jumps == 0)
4932 if (align_functions == 0)
4933 align_functions = 8;
4936 /* Function to allocate machine-dependent function status. */
4937 init_machine_status = &mips_init_machine_status;
4939 if (ABI_HAS_64BIT_SYMBOLS)
4941 if (TARGET_EXPLICIT_RELOCS)
4943 mips_split_p[SYMBOL_64_HIGH] = true;
4944 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4945 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4947 mips_split_p[SYMBOL_64_MID] = true;
4948 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4949 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4951 mips_split_p[SYMBOL_64_LOW] = true;
4952 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4953 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4955 mips_split_p[SYMBOL_GENERAL] = true;
4956 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4961 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4963 mips_split_p[SYMBOL_GENERAL] = true;
4964 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4965 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4971 /* The high part is provided by a pseudo copy of $gp. */
4972 mips_split_p[SYMBOL_SMALL_DATA] = true;
4973 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4976 if (TARGET_EXPLICIT_RELOCS)
4978 /* Small data constants are kept whole until after reload,
4979 then lowered by mips_rewrite_small_data. */
4980 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
4982 mips_split_p[SYMBOL_GOT_LOCAL] = true;
4985 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
4986 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
4990 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
4991 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
4996 /* The HIGH and LO_SUM are matched by special .md patterns. */
4997 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
4999 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5000 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5001 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5003 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5004 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5005 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5010 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5012 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5013 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5019 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5020 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5021 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5024 /* Thread-local relocation operators. */
5025 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5026 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5027 mips_split_p[SYMBOL_DTPREL] = 1;
5028 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5029 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5030 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5031 mips_split_p[SYMBOL_TPREL] = 1;
5032 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5033 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5035 /* We don't have a thread pointer access instruction on MIPS16, or
5036 appropriate TLS relocations. */
5038 targetm.have_tls = false;
5040 /* Default to working around R4000 errata only if the processor
5041 was selected explicitly. */
5042 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5043 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5044 target_flags |= MASK_FIX_R4000;
5046 /* Default to working around R4400 errata only if the processor
5047 was selected explicitly. */
5048 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5049 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5050 target_flags |= MASK_FIX_R4400;
5053 /* Implement CONDITIONAL_REGISTER_USAGE. */
5056 mips_conditional_register_usage (void)
5062 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5063 fixed_regs[regno] = call_used_regs[regno] = 1;
5065 if (!TARGET_HARD_FLOAT)
5069 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5070 fixed_regs[regno] = call_used_regs[regno] = 1;
5071 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5072 fixed_regs[regno] = call_used_regs[regno] = 1;
5074 else if (! ISA_HAS_8CC)
5078 /* We only have a single condition code register. We
5079 implement this by hiding all the condition code registers,
5080 and generating RTL that refers directly to ST_REG_FIRST. */
5081 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5082 fixed_regs[regno] = call_used_regs[regno] = 1;
5084 /* In mips16 mode, we permit the $t temporary registers to be used
5085 for reload. We prohibit the unused $s registers, since they
5086 are caller saved, and saving them via a mips16 register would
5087 probably waste more time than just reloading the value. */
5090 fixed_regs[18] = call_used_regs[18] = 1;
5091 fixed_regs[19] = call_used_regs[19] = 1;
5092 fixed_regs[20] = call_used_regs[20] = 1;
5093 fixed_regs[21] = call_used_regs[21] = 1;
5094 fixed_regs[22] = call_used_regs[22] = 1;
5095 fixed_regs[23] = call_used_regs[23] = 1;
5096 fixed_regs[26] = call_used_regs[26] = 1;
5097 fixed_regs[27] = call_used_regs[27] = 1;
5098 fixed_regs[30] = call_used_regs[30] = 1;
5100 /* fp20-23 are now caller saved. */
5101 if (mips_abi == ABI_64)
5104 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5105 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5107 /* Odd registers from fp21 to fp31 are now caller saved. */
5108 if (mips_abi == ABI_N32)
5111 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5112 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5116 /* Allocate a chunk of memory for per-function machine-dependent data. */
5117 static struct machine_function *
5118 mips_init_machine_status (void)
5120 return ((struct machine_function *)
5121 ggc_alloc_cleared (sizeof (struct machine_function)));
5124 /* On the mips16, we want to allocate $24 (T_REG) before other
5125 registers for instructions for which it is possible. This helps
5126 avoid shuffling registers around in order to set up for an xor,
5127 encouraging the compiler to use a cmp instead. */
5130 mips_order_regs_for_local_alloc (void)
5134 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5135 reg_alloc_order[i] = i;
5139 /* It really doesn't matter where we put register 0, since it is
5140 a fixed register anyhow. */
5141 reg_alloc_order[0] = 24;
5142 reg_alloc_order[24] = 0;
5147 /* The MIPS debug format wants all automatic variables and arguments
5148 to be in terms of the virtual frame pointer (stack pointer before
5149 any adjustment in the function), while the MIPS 3.0 linker wants
5150 the frame pointer to be the stack pointer after the initial
5151 adjustment. So, we do the adjustment here. The arg pointer (which
5152 is eliminated) points to the virtual frame pointer, while the frame
5153 pointer (which may be eliminated) points to the stack pointer after
5154 the initial adjustments. */
5157 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5159 rtx offset2 = const0_rtx;
5160 rtx reg = eliminate_constant_term (addr, &offset2);
5163 offset = INTVAL (offset2);
5165 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5166 || reg == hard_frame_pointer_rtx)
5168 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5169 ? compute_frame_size (get_frame_size ())
5170 : cfun->machine->frame.total_size;
5172 /* MIPS16 frame is smaller */
5173 if (frame_pointer_needed && TARGET_MIPS16)
5174 frame_size -= cfun->machine->frame.args_size;
5176 offset = offset - frame_size;
5179 /* sdbout_parms does not want this to crash for unrecognized cases. */
5181 else if (reg != arg_pointer_rtx)
5182 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5189 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5191 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5192 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5193 'h' OP is HIGH, prints %hi(X),
5194 'd' output integer constant in decimal,
5195 'z' if the operand is 0, use $0 instead of normal operand.
5196 'D' print second part of double-word register or memory operand.
5197 'L' print low-order register of double-word register operand.
5198 'M' print high-order register of double-word register operand.
5199 'C' print part of opcode for a branch condition.
5200 'F' print part of opcode for a floating-point branch condition.
5201 'N' print part of opcode for a branch condition, inverted.
5202 'W' print part of opcode for a floating-point branch condition, inverted.
5203 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5204 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5205 't' like 'T', but with the EQ/NE cases reversed
5206 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5207 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5208 'R' print the reloc associated with LO_SUM
5209 'q' print DSP accumulator registers
5211 The punctuation characters are:
5213 '(' Turn on .set noreorder
5214 ')' Turn on .set reorder
5215 '[' Turn on .set noat
5217 '<' Turn on .set nomacro
5218 '>' Turn on .set macro
5219 '{' Turn on .set volatile (not GAS)
5220 '}' Turn on .set novolatile (not GAS)
5221 '&' Turn on .set noreorder if filling delay slots
5222 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5223 '!' Turn on .set nomacro if filling delay slots
5224 '#' Print nop if in a .set noreorder section.
5225 '/' Like '#', but does nothing within a delayed branch sequence
5226 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5227 '@' Print the name of the assembler temporary register (at or $1).
5228 '.' Print the name of the register with a hard-wired zero (zero or $0).
5229 '^' Print the name of the pic call-through register (t9 or $25).
5230 '$' Print the name of the stack pointer register (sp or $29).
5231 '+' Print the name of the gp register (usually gp or $28).
5232 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5235 print_operand (FILE *file, rtx op, int letter)
5237 register enum rtx_code code;
5239 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5244 if (mips_branch_likely)
5249 fputs (reg_names [GP_REG_FIRST + 1], file);
5253 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5257 fputs (reg_names [GP_REG_FIRST + 0], file);
5261 fputs (reg_names[STACK_POINTER_REGNUM], file);
5265 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5269 if (final_sequence != 0 && set_noreorder++ == 0)
5270 fputs (".set\tnoreorder\n\t", file);
5274 if (final_sequence != 0)
5276 if (set_noreorder++ == 0)
5277 fputs (".set\tnoreorder\n\t", file);
5279 if (set_nomacro++ == 0)
5280 fputs (".set\tnomacro\n\t", file);
5285 if (final_sequence != 0 && set_nomacro++ == 0)
5286 fputs ("\n\t.set\tnomacro", file);
5290 if (set_noreorder != 0)
5291 fputs ("\n\tnop", file);
5295 /* Print an extra newline so that the delayed insn is separated
5296 from the following ones. This looks neater and is consistent
5297 with non-nop delayed sequences. */
5298 if (set_noreorder != 0 && final_sequence == 0)
5299 fputs ("\n\tnop\n", file);
5303 if (set_noreorder++ == 0)
5304 fputs (".set\tnoreorder\n\t", file);
5308 if (set_noreorder == 0)
5309 error ("internal error: %%) found without a %%( in assembler pattern");
5311 else if (--set_noreorder == 0)
5312 fputs ("\n\t.set\treorder", file);
5317 if (set_noat++ == 0)
5318 fputs (".set\tnoat\n\t", file);
5323 error ("internal error: %%] found without a %%[ in assembler pattern");
5324 else if (--set_noat == 0)
5325 fputs ("\n\t.set\tat", file);
5330 if (set_nomacro++ == 0)
5331 fputs (".set\tnomacro\n\t", file);
5335 if (set_nomacro == 0)
5336 error ("internal error: %%> found without a %%< in assembler pattern");
5337 else if (--set_nomacro == 0)
5338 fputs ("\n\t.set\tmacro", file);
5343 if (set_volatile++ == 0)
5344 fputs ("#.set\tvolatile\n\t", file);
5348 if (set_volatile == 0)
5349 error ("internal error: %%} found without a %%{ in assembler pattern");
5350 else if (--set_volatile == 0)
5351 fputs ("\n\t#.set\tnovolatile", file);
5357 if (align_labels_log > 0)
5358 ASM_OUTPUT_ALIGN (file, align_labels_log);
5363 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5372 error ("PRINT_OPERAND null pointer");
5376 code = GET_CODE (op);
5381 case EQ: fputs ("eq", file); break;
5382 case NE: fputs ("ne", file); break;
5383 case GT: fputs ("gt", file); break;
5384 case GE: fputs ("ge", file); break;
5385 case LT: fputs ("lt", file); break;
5386 case LE: fputs ("le", file); break;
5387 case GTU: fputs ("gtu", file); break;
5388 case GEU: fputs ("geu", file); break;
5389 case LTU: fputs ("ltu", file); break;
5390 case LEU: fputs ("leu", file); break;
5392 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5395 else if (letter == 'N')
5398 case EQ: fputs ("ne", file); break;
5399 case NE: fputs ("eq", file); break;
5400 case GT: fputs ("le", file); break;
5401 case GE: fputs ("lt", file); break;
5402 case LT: fputs ("ge", file); break;
5403 case LE: fputs ("gt", file); break;
5404 case GTU: fputs ("leu", file); break;
5405 case GEU: fputs ("ltu", file); break;
5406 case LTU: fputs ("geu", file); break;
5407 case LEU: fputs ("gtu", file); break;
5409 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5412 else if (letter == 'F')
5415 case EQ: fputs ("c1f", file); break;
5416 case NE: fputs ("c1t", file); break;
5418 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5421 else if (letter == 'W')
5424 case EQ: fputs ("c1t", file); break;
5425 case NE: fputs ("c1f", file); break;
5427 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5430 else if (letter == 'h')
5432 if (GET_CODE (op) == HIGH)
5435 print_operand_reloc (file, op, mips_hi_relocs);
5438 else if (letter == 'R')
5439 print_operand_reloc (file, op, mips_lo_relocs);
5441 else if (letter == 'Y')
5443 if (GET_CODE (op) == CONST_INT
5444 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5445 < ARRAY_SIZE (mips_fp_conditions)))
5446 fputs (mips_fp_conditions[INTVAL (op)], file);
5448 output_operand_lossage ("invalid %%Y value");
5451 else if (letter == 'Z')
5455 print_operand (file, op, 0);
5460 else if (letter == 'q')
5465 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5467 regnum = REGNO (op);
5468 if (MD_REG_P (regnum))
5469 fprintf (file, "$ac0");
5470 else if (DSP_ACC_REG_P (regnum))
5471 fprintf (file, "$ac%c", reg_names[regnum][3]);
5473 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5476 else if (code == REG || code == SUBREG)
5478 register int regnum;
5481 regnum = REGNO (op);
5483 regnum = true_regnum (op);
5485 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5486 || (letter == 'L' && WORDS_BIG_ENDIAN)
5490 fprintf (file, "%s", reg_names[regnum]);
5493 else if (code == MEM)
5496 output_address (plus_constant (XEXP (op, 0), 4));
5498 output_address (XEXP (op, 0));
5501 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5502 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5504 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5505 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5507 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5508 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5510 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5511 fputs (reg_names[GP_REG_FIRST], file);
5513 else if (letter == 'd' || letter == 'x' || letter == 'X')
5514 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5516 else if (letter == 'T' || letter == 't')
5518 int truth = (code == NE) == (letter == 'T');
5519 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5522 else if (CONST_GP_P (op))
5523 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5526 output_addr_const (file, op);
5530 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5531 RELOCS is the array of relocations to use. */
5534 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5536 enum mips_symbol_type symbol_type;
5539 HOST_WIDE_INT offset;
5541 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5542 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5544 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5545 mips_split_const (op, &base, &offset);
5546 if (UNSPEC_ADDRESS_P (base))
5547 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5549 fputs (relocs[symbol_type], file);
5550 output_addr_const (file, op);
5551 for (p = relocs[symbol_type]; *p != 0; p++)
5556 /* Output address operand X to FILE. */
5559 print_operand_address (FILE *file, rtx x)
5561 struct mips_address_info addr;
5563 if (mips_classify_address (&addr, x, word_mode, true))
5567 print_operand (file, addr.offset, 0);
5568 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5571 case ADDRESS_LO_SUM:
5572 print_operand (file, addr.offset, 'R');
5573 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5576 case ADDRESS_CONST_INT:
5577 output_addr_const (file, x);
5578 fprintf (file, "(%s)", reg_names[0]);
5581 case ADDRESS_SYMBOLIC:
5582 output_addr_const (file, x);
5588 /* When using assembler macros, keep track of all of small-data externs
5589 so that mips_file_end can emit the appropriate declarations for them.
5591 In most cases it would be safe (though pointless) to emit .externs
5592 for other symbols too. One exception is when an object is within
5593 the -G limit but declared by the user to be in a section other
5594 than .sbss or .sdata. */
5597 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5599 register struct extern_list *p;
5601 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5603 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5604 p->next = extern_head;
5606 p->size = int_size_in_bytes (TREE_TYPE (decl));
5610 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5612 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5613 p->next = extern_head;
5624 irix_output_external_libcall (rtx fun)
5626 register struct extern_list *p;
5628 if (mips_abi == ABI_32)
5630 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5631 p->next = extern_head;
5632 p->name = XSTR (fun, 0);
5639 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5640 put out a MIPS ECOFF file and a stab. */
5643 mips_output_filename (FILE *stream, const char *name)
5646 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5648 if (write_symbols == DWARF2_DEBUG)
5650 else if (mips_output_filename_first_time)
5652 mips_output_filename_first_time = 0;
5653 num_source_filenames += 1;
5654 current_function_file = name;
5655 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5656 output_quoted_string (stream, name);
5657 putc ('\n', stream);
5660 /* If we are emitting stabs, let dbxout.c handle this (except for
5661 the mips_output_filename_first_time case). */
5662 else if (write_symbols == DBX_DEBUG)
5665 else if (name != current_function_file
5666 && strcmp (name, current_function_file) != 0)
5668 num_source_filenames += 1;
5669 current_function_file = name;
5670 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5671 output_quoted_string (stream, name);
5672 putc ('\n', stream);
5676 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5677 that should be written before the opening quote, such as "\t.ascii\t"
5678 for real string data or "\t# " for a comment. */
5681 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5686 register const unsigned char *string =
5687 (const unsigned char *)string_param;
5689 fprintf (stream, "%s\"", prefix);
5690 for (i = 0; i < len; i++)
5692 register int c = string[i];
5696 if (c == '\\' || c == '\"')
5698 putc ('\\', stream);
5706 fprintf (stream, "\\%03o", c);
5710 if (cur_pos > 72 && i+1 < len)
5713 fprintf (stream, "\"\n%s\"", prefix);
5716 fprintf (stream, "\"\n");
5719 /* Implement TARGET_ASM_FILE_START. */
5722 mips_file_start (void)
5724 default_file_start ();
5728 /* Generate a special section to describe the ABI switches used to
5729 produce the resultant binary. This used to be done by the assembler
5730 setting bits in the ELF header's flags field, but we have run out of
5731 bits. GDB needs this information in order to be able to correctly
5732 debug these binaries. See the function mips_gdbarch_init() in
5733 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5734 causes unnecessary IRIX 6 ld warnings. */
5735 const char * abi_string = NULL;
5739 case ABI_32: abi_string = "abi32"; break;
5740 case ABI_N32: abi_string = "abiN32"; break;
5741 case ABI_64: abi_string = "abi64"; break;
5742 case ABI_O64: abi_string = "abiO64"; break;
5743 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5747 /* Note - we use fprintf directly rather than calling switch_to_section
5748 because in this way we can avoid creating an allocated section. We
5749 do not want this section to take up any space in the running
5751 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5753 /* There is no ELF header flag to distinguish long32 forms of the
5754 EABI from long64 forms. Emit a special section to help tools
5756 if (mips_abi == ABI_EABI)
5757 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5758 TARGET_LONG64 ? 64 : 32);
5760 /* Restore the default section. */
5761 fprintf (asm_out_file, "\t.previous\n");
5764 /* Generate the pseudo ops that System V.4 wants. */
5765 if (TARGET_ABICALLS)
5766 /* ??? but do not want this (or want pic0) if -non-shared? */
5767 fprintf (asm_out_file, "\t.abicalls\n");
5770 fprintf (asm_out_file, "\t.set\tmips16\n");
5772 if (flag_verbose_asm)
5773 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5775 mips_section_threshold, mips_arch_info->name, mips_isa);
5778 #ifdef BSS_SECTION_ASM_OP
5779 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5780 in the use of sbss. */
5783 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5784 unsigned HOST_WIDE_INT size, int align)
5786 extern tree last_assemble_variable_decl;
5788 if (mips_in_small_data_p (decl))
5789 switch_to_section (get_named_section (NULL, ".sbss", 0));
5791 switch_to_section (bss_section);
5792 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5793 last_assemble_variable_decl = decl;
5794 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5795 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5799 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5800 .externs for any small-data variables that turned out to be external. */
5803 mips_file_end (void)
5806 struct extern_list *p;
5810 fputs ("\n", asm_out_file);
5812 for (p = extern_head; p != 0; p = p->next)
5814 name_tree = get_identifier (p->name);
5816 /* Positively ensure only one .extern for any given symbol. */
5817 if (!TREE_ASM_WRITTEN (name_tree)
5818 && TREE_SYMBOL_REFERENCED (name_tree))
5820 TREE_ASM_WRITTEN (name_tree) = 1;
5821 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5822 `.global name .text' directive for every used but
5823 undefined function. If we don't, the linker may perform
5824 an optimization (skipping over the insns that set $gp)
5825 when it is unsafe. */
5826 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5828 fputs ("\t.globl ", asm_out_file);
5829 assemble_name (asm_out_file, p->name);
5830 fputs (" .text\n", asm_out_file);
5834 fputs ("\t.extern\t", asm_out_file);
5835 assemble_name (asm_out_file, p->name);
5836 fprintf (asm_out_file, ", %d\n", p->size);
5843 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5844 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5847 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5848 unsigned HOST_WIDE_INT size,
5851 /* If the target wants uninitialized const declarations in
5852 .rdata then don't put them in .comm. */
5853 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5854 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5855 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5857 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5858 targetm.asm_out.globalize_label (stream, name);
5860 switch_to_section (readonly_data_section);
5861 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5862 mips_declare_object (stream, name, "",
5863 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5867 mips_declare_common_object (stream, name, "\n\t.comm\t",
5871 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5872 NAME is the name of the object and ALIGN is the required alignment
5873 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5874 alignment argument. */
5877 mips_declare_common_object (FILE *stream, const char *name,
5878 const char *init_string,
5879 unsigned HOST_WIDE_INT size,
5880 unsigned int align, bool takes_alignment_p)
5882 if (!takes_alignment_p)
5884 size += (align / BITS_PER_UNIT) - 1;
5885 size -= size % (align / BITS_PER_UNIT);
5886 mips_declare_object (stream, name, init_string,
5887 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5890 mips_declare_object (stream, name, init_string,
5891 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5892 size, align / BITS_PER_UNIT);
5895 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5896 macros, mark the symbol as written so that mips_file_end won't emit an
5897 .extern for it. STREAM is the output file, NAME is the name of the
5898 symbol, INIT_STRING is the string that should be written before the
5899 symbol and FINAL_STRING is the string that should be written after it.
5900 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5903 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5904 const char *final_string, ...)
5908 fputs (init_string, stream);
5909 assemble_name (stream, name);
5910 va_start (ap, final_string);
5911 vfprintf (stream, final_string, ap);
5914 if (!TARGET_EXPLICIT_RELOCS)
5916 tree name_tree = get_identifier (name);
5917 TREE_ASM_WRITTEN (name_tree) = 1;
5921 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5922 extern int size_directive_output;
5924 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5925 definitions except that it uses mips_declare_object() to emit the label. */
5928 mips_declare_object_name (FILE *stream, const char *name,
5929 tree decl ATTRIBUTE_UNUSED)
5931 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5932 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5935 size_directive_output = 0;
5936 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5940 size_directive_output = 1;
5941 size = int_size_in_bytes (TREE_TYPE (decl));
5942 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5945 mips_declare_object (stream, name, "", ":\n");
5948 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5951 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5955 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5956 if (!flag_inhibit_size_directive
5957 && DECL_SIZE (decl) != 0
5958 && !at_end && top_level
5959 && DECL_INITIAL (decl) == error_mark_node
5960 && !size_directive_output)
5964 size_directive_output = 1;
5965 size = int_size_in_bytes (TREE_TYPE (decl));
5966 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5971 /* Return true if X is a small data address that can be rewritten
5975 mips_rewrite_small_data_p (rtx x)
5977 enum mips_symbol_type symbol_type;
5979 return (TARGET_EXPLICIT_RELOCS
5980 && mips_symbolic_constant_p (x, &symbol_type)
5981 && symbol_type == SYMBOL_SMALL_DATA);
5985 /* A for_each_rtx callback for mips_small_data_pattern_p. */
5988 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5990 if (GET_CODE (*loc) == LO_SUM)
5993 return mips_rewrite_small_data_p (*loc);
5996 /* Return true if OP refers to small data symbols directly, not through
6000 mips_small_data_pattern_p (rtx op)
6002 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6005 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6008 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6010 if (mips_rewrite_small_data_p (*loc))
6011 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6013 if (GET_CODE (*loc) == LO_SUM)
6019 /* If possible, rewrite OP so that it refers to small data using
6020 explicit relocations. */
6023 mips_rewrite_small_data (rtx op)
6025 op = copy_insn (op);
6026 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6030 /* Return true if the current function has an insn that implicitly
6034 mips_function_has_gp_insn (void)
6036 /* Don't bother rechecking if we found one last time. */
6037 if (!cfun->machine->has_gp_insn_p)
6041 push_topmost_sequence ();
6042 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6044 && GET_CODE (PATTERN (insn)) != USE
6045 && GET_CODE (PATTERN (insn)) != CLOBBER
6046 && (get_attr_got (insn) != GOT_UNSET
6047 || small_data_pattern (PATTERN (insn), VOIDmode)))
6049 pop_topmost_sequence ();
6051 cfun->machine->has_gp_insn_p = (insn != 0);
6053 return cfun->machine->has_gp_insn_p;
6057 /* Return the register that should be used as the global pointer
6058 within this function. Return 0 if the function doesn't need
6059 a global pointer. */
6062 mips_global_pointer (void)
6066 /* $gp is always available in non-abicalls code. */
6067 if (!TARGET_ABICALLS)
6068 return GLOBAL_POINTER_REGNUM;
6070 /* We must always provide $gp when it is used implicitly. */
6071 if (!TARGET_EXPLICIT_RELOCS)
6072 return GLOBAL_POINTER_REGNUM;
6074 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6076 if (current_function_profile)
6077 return GLOBAL_POINTER_REGNUM;
6079 /* If the function has a nonlocal goto, $gp must hold the correct
6080 global pointer for the target function. */
6081 if (current_function_has_nonlocal_goto)
6082 return GLOBAL_POINTER_REGNUM;
6084 /* If the gp is never referenced, there's no need to initialize it.
6085 Note that reload can sometimes introduce constant pool references
6086 into a function that otherwise didn't need them. For example,
6087 suppose we have an instruction like:
6089 (set (reg:DF R1) (float:DF (reg:SI R2)))
6091 If R2 turns out to be constant such as 1, the instruction may have a
6092 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6093 using this constant if R2 doesn't get allocated to a register.
6095 In cases like these, reload will have added the constant to the pool
6096 but no instruction will yet refer to it. */
6097 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6098 && !current_function_uses_const_pool
6099 && !mips_function_has_gp_insn ())
6102 /* We need a global pointer, but perhaps we can use a call-clobbered
6103 register instead of $gp. */
6104 if (TARGET_NEWABI && current_function_is_leaf)
6105 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6106 if (!regs_ever_live[regno]
6107 && call_used_regs[regno]
6108 && !fixed_regs[regno]
6109 && regno != PIC_FUNCTION_ADDR_REGNUM)
6112 return GLOBAL_POINTER_REGNUM;
6116 /* Return true if the current function must save REGNO. */
6119 mips_save_reg_p (unsigned int regno)
6121 /* We only need to save $gp for NewABI PIC. */
6122 if (regno == GLOBAL_POINTER_REGNUM)
6123 return (TARGET_ABICALLS && TARGET_NEWABI
6124 && cfun->machine->global_pointer == regno);
6126 /* Check call-saved registers. */
6127 if (regs_ever_live[regno] && !call_used_regs[regno])
6130 /* We need to save the old frame pointer before setting up a new one. */
6131 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6134 /* We need to save the incoming return address if it is ever clobbered
6135 within the function. */
6136 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6143 return_type = DECL_RESULT (current_function_decl);
6145 /* $18 is a special case in mips16 code. It may be used to call
6146 a function which returns a floating point value, but it is
6147 marked in call_used_regs. */
6148 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6151 /* $31 is also a special case. It will be used to copy a return
6152 value into the floating point registers if the return value is
6154 if (regno == GP_REG_FIRST + 31
6155 && mips16_hard_float
6156 && !aggregate_value_p (return_type, current_function_decl)
6157 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6158 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6166 /* Return the bytes needed to compute the frame pointer from the current
6167 stack pointer. SIZE is the size (in bytes) of the local variables.
6169 MIPS stack frames look like:
6171 Before call After call
6172 +-----------------------+ +-----------------------+
6175 | caller's temps. | | caller's temps. |
6177 +-----------------------+ +-----------------------+
6179 | arguments on stack. | | arguments on stack. |
6181 +-----------------------+ +-----------------------+
6182 | 4 words to save | | 4 words to save |
6183 | arguments passed | | arguments passed |
6184 | in registers, even | | in registers, even |
6185 SP->| if not passed. | VFP->| if not passed. |
6186 +-----------------------+ +-----------------------+
6188 | fp register save |
6190 +-----------------------+
6192 | gp register save |
6194 +-----------------------+
6198 +-----------------------+
6200 | alloca allocations |
6202 +-----------------------+
6204 | GP save for V.4 abi |
6206 +-----------------------+
6208 | arguments on stack |
6210 +-----------------------+
6212 | arguments passed |
6213 | in registers, even |
6214 low SP->| if not passed. |
6215 memory +-----------------------+
6220 compute_frame_size (HOST_WIDE_INT size)
6223 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6224 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6225 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6226 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6227 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6228 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6229 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6230 unsigned int mask; /* mask of saved gp registers */
6231 unsigned int fmask; /* mask of saved fp registers */
6233 cfun->machine->global_pointer = mips_global_pointer ();
6239 var_size = MIPS_STACK_ALIGN (size);
6240 args_size = current_function_outgoing_args_size;
6241 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6243 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6244 functions. If the function has local variables, we're committed
6245 to allocating it anyway. Otherwise reclaim it here. */
6246 if (var_size == 0 && current_function_is_leaf)
6247 cprestore_size = args_size = 0;
6249 /* The MIPS 3.0 linker does not like functions that dynamically
6250 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6251 looks like we are trying to create a second frame pointer to the
6252 function, so allocate some stack space to make it happy. */
6254 if (args_size == 0 && current_function_calls_alloca)
6255 args_size = 4 * UNITS_PER_WORD;
6257 total_size = var_size + args_size + cprestore_size;
6259 /* Calculate space needed for gp registers. */
6260 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6261 if (mips_save_reg_p (regno))
6263 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6264 mask |= 1 << (regno - GP_REG_FIRST);
6267 /* We need to restore these for the handler. */
6268 if (current_function_calls_eh_return)
6273 regno = EH_RETURN_DATA_REGNO (i);
6274 if (regno == INVALID_REGNUM)
6276 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6277 mask |= 1 << (regno - GP_REG_FIRST);
6281 /* This loop must iterate over the same space as its companion in
6282 save_restore_insns. */
6283 for (regno = (FP_REG_LAST - FP_INC + 1);
6284 regno >= FP_REG_FIRST;
6287 if (mips_save_reg_p (regno))
6289 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6290 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6294 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6295 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6297 /* Add in the space required for saving incoming register arguments. */
6298 total_size += current_function_pretend_args_size;
6299 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6301 /* Save other computed information. */
6302 cfun->machine->frame.total_size = total_size;
6303 cfun->machine->frame.var_size = var_size;
6304 cfun->machine->frame.args_size = args_size;
6305 cfun->machine->frame.cprestore_size = cprestore_size;
6306 cfun->machine->frame.gp_reg_size = gp_reg_size;
6307 cfun->machine->frame.fp_reg_size = fp_reg_size;
6308 cfun->machine->frame.mask = mask;
6309 cfun->machine->frame.fmask = fmask;
6310 cfun->machine->frame.initialized = reload_completed;
6311 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6312 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6316 HOST_WIDE_INT offset;
6318 offset = (args_size + cprestore_size + var_size
6319 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6320 cfun->machine->frame.gp_sp_offset = offset;
6321 cfun->machine->frame.gp_save_offset = offset - total_size;
6325 cfun->machine->frame.gp_sp_offset = 0;
6326 cfun->machine->frame.gp_save_offset = 0;
6331 HOST_WIDE_INT offset;
6333 offset = (args_size + cprestore_size + var_size
6334 + gp_reg_rounded + fp_reg_size
6335 - FP_INC * UNITS_PER_FPREG);
6336 cfun->machine->frame.fp_sp_offset = offset;
6337 cfun->machine->frame.fp_save_offset = offset - total_size;
6341 cfun->machine->frame.fp_sp_offset = 0;
6342 cfun->machine->frame.fp_save_offset = 0;
6345 /* Ok, we're done. */
6349 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6350 pointer or argument pointer. TO is either the stack pointer or
6351 hard frame pointer. */
6354 mips_initial_elimination_offset (int from, int to)
6356 HOST_WIDE_INT offset;
6358 compute_frame_size (get_frame_size ());
6360 /* Set OFFSET to the offset from the stack pointer. */
6363 case FRAME_POINTER_REGNUM:
6367 case ARG_POINTER_REGNUM:
6368 offset = (cfun->machine->frame.total_size
6369 - current_function_pretend_args_size);
6376 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6377 offset -= cfun->machine->frame.args_size;
6382 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6383 back to a previous frame. */
6385 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6390 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6393 /* Use FN to save or restore register REGNO. MODE is the register's
6394 mode and OFFSET is the offset of its save slot from the current
6398 mips_save_restore_reg (enum machine_mode mode, int regno,
6399 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6403 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6405 fn (gen_rtx_REG (mode, regno), mem);
6409 /* Call FN for each register that is saved by the current function.
6410 SP_OFFSET is the offset of the current stack pointer from the start
6414 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6416 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6418 enum machine_mode fpr_mode;
6419 HOST_WIDE_INT offset;
6422 /* Save registers starting from high to low. The debuggers prefer at least
6423 the return register be stored at func+4, and also it allows us not to
6424 need a nop in the epilog if at least one register is reloaded in
6425 addition to return address. */
6426 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6427 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6428 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6430 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6431 offset -= GET_MODE_SIZE (gpr_mode);
6434 /* This loop must iterate over the same space as its companion in
6435 compute_frame_size. */
6436 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6437 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6438 for (regno = (FP_REG_LAST - FP_INC + 1);
6439 regno >= FP_REG_FIRST;
6441 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6443 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6444 offset -= GET_MODE_SIZE (fpr_mode);
6449 /* If we're generating n32 or n64 abicalls, and the current function
6450 does not use $28 as its global pointer, emit a cplocal directive.
6451 Use pic_offset_table_rtx as the argument to the directive. */
6454 mips_output_cplocal (void)
6456 if (!TARGET_EXPLICIT_RELOCS
6457 && cfun->machine->global_pointer > 0
6458 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6459 output_asm_insn (".cplocal %+", 0);
6462 /* If we're generating n32 or n64 abicalls, emit instructions
6463 to set up the global pointer. */
6466 mips_emit_loadgp (void)
6468 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6470 rtx addr, offset, incoming_address;
6472 addr = XEXP (DECL_RTL (current_function_decl), 0);
6473 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6474 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6475 emit_insn (gen_loadgp (offset, incoming_address));
6476 if (!TARGET_EXPLICIT_RELOCS)
6477 emit_insn (gen_loadgp_blockage ());
6481 /* Set up the stack and frame (if desired) for the function. */
6484 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6487 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6489 #ifdef SDB_DEBUGGING_INFO
6490 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6491 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6494 /* In mips16 mode, we may need to generate a 32 bit to handle
6495 floating point arguments. The linker will arrange for any 32 bit
6496 functions to call this stub, which will then jump to the 16 bit
6498 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6499 && current_function_args_info.fp_code != 0)
6500 build_mips16_function_stub (file);
6502 if (!FUNCTION_NAME_ALREADY_DECLARED)
6504 /* Get the function name the same way that toplev.c does before calling
6505 assemble_start_function. This is needed so that the name used here
6506 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6507 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6509 if (!flag_inhibit_size_directive)
6511 fputs ("\t.ent\t", file);
6512 assemble_name (file, fnname);
6516 assemble_name (file, fnname);
6517 fputs (":\n", file);
6520 /* Stop mips_file_end from treating this function as external. */
6521 if (TARGET_IRIX && mips_abi == ABI_32)
6522 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6524 if (!flag_inhibit_size_directive)
6526 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6528 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6529 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6530 ", args= " HOST_WIDE_INT_PRINT_DEC
6531 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6532 (reg_names[(frame_pointer_needed)
6533 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6534 ((frame_pointer_needed && TARGET_MIPS16)
6535 ? tsize - cfun->machine->frame.args_size
6537 reg_names[GP_REG_FIRST + 31],
6538 cfun->machine->frame.var_size,
6539 cfun->machine->frame.num_gp,
6540 cfun->machine->frame.num_fp,
6541 cfun->machine->frame.args_size,
6542 cfun->machine->frame.cprestore_size);
6544 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6545 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6546 cfun->machine->frame.mask,
6547 cfun->machine->frame.gp_save_offset);
6548 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6549 cfun->machine->frame.fmask,
6550 cfun->machine->frame.fp_save_offset);
6553 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6554 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6557 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6559 /* Handle the initialization of $gp for SVR4 PIC. */
6560 if (!cfun->machine->all_noreorder_p)
6561 output_asm_insn ("%(.cpload\t%^%)", 0);
6563 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6565 else if (cfun->machine->all_noreorder_p)
6566 output_asm_insn ("%(%<", 0);
6568 /* Tell the assembler which register we're using as the global
6569 pointer. This is needed for thunks, since they can use either
6570 explicit relocs or assembler macros. */
6571 mips_output_cplocal ();
6574 /* Make the last instruction frame related and note that it performs
6575 the operation described by FRAME_PATTERN. */
6578 mips_set_frame_expr (rtx frame_pattern)
6582 insn = get_last_insn ();
6583 RTX_FRAME_RELATED_P (insn) = 1;
6584 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6590 /* Return a frame-related rtx that stores REG at MEM.
6591 REG must be a single register. */
6594 mips_frame_set (rtx mem, rtx reg)
6598 /* If we're saving the return address register and the dwarf return
6599 address column differs from the hard register number, adjust the
6600 note reg to refer to the former. */
6601 if (REGNO (reg) == GP_REG_FIRST + 31
6602 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6603 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6605 set = gen_rtx_SET (VOIDmode, mem, reg);
6606 RTX_FRAME_RELATED_P (set) = 1;
6612 /* Save register REG to MEM. Make the instruction frame-related. */
6615 mips_save_reg (rtx reg, rtx mem)
6617 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6621 if (mips_split_64bit_move_p (mem, reg))
6622 mips_split_64bit_move (mem, reg);
6624 emit_move_insn (mem, reg);
6626 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6627 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6628 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6633 && REGNO (reg) != GP_REG_FIRST + 31
6634 && !M16_REG_P (REGNO (reg)))
6636 /* Save a non-mips16 register by moving it through a temporary.
6637 We don't need to do this for $31 since there's a special
6638 instruction for it. */
6639 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6640 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6643 emit_move_insn (mem, reg);
6645 mips_set_frame_expr (mips_frame_set (mem, reg));
6650 /* Expand the prologue into a bunch of separate insns. */
6653 mips_expand_prologue (void)
6657 if (cfun->machine->global_pointer > 0)
6658 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6660 size = compute_frame_size (get_frame_size ());
6662 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6663 bytes beforehand; this is enough to cover the register save area
6664 without going out of range. */
6665 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6667 HOST_WIDE_INT step1;
6669 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6670 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6672 GEN_INT (-step1)))) = 1;
6674 mips_for_each_saved_reg (size, mips_save_reg);
6677 /* Allocate the rest of the frame. */
6680 if (SMALL_OPERAND (-size))
6681 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6683 GEN_INT (-size)))) = 1;
6686 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6689 /* There are no instructions to add or subtract registers
6690 from the stack pointer, so use the frame pointer as a
6691 temporary. We should always be using a frame pointer
6692 in this case anyway. */
6693 gcc_assert (frame_pointer_needed);
6694 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6695 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6696 hard_frame_pointer_rtx,
6697 MIPS_PROLOGUE_TEMP (Pmode)));
6698 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6701 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6703 MIPS_PROLOGUE_TEMP (Pmode)));
6705 /* Describe the combined effect of the previous instructions. */
6707 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6708 plus_constant (stack_pointer_rtx, -size)));
6712 /* Set up the frame pointer, if we're using one. In mips16 code,
6713 we point the frame pointer ahead of the outgoing argument area.
6714 This should allow more variables & incoming arguments to be
6715 accessed with unextended instructions. */
6716 if (frame_pointer_needed)
6718 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6720 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6721 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6723 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6728 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6729 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6730 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6731 hard_frame_pointer_rtx,
6732 MIPS_PROLOGUE_TEMP (Pmode)));
6734 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6735 plus_constant (stack_pointer_rtx,
6736 cfun->machine->frame.args_size)));
6740 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6741 stack_pointer_rtx)) = 1;
6744 /* If generating o32/o64 abicalls, save $gp on the stack. */
6745 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6746 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6748 mips_emit_loadgp ();
6750 /* If we are profiling, make sure no instructions are scheduled before
6751 the call to mcount. */
6753 if (current_function_profile)
6754 emit_insn (gen_blockage ());
6757 /* Do any necessary cleanup after a function to restore stack, frame,
6760 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6763 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6764 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6766 /* Reinstate the normal $gp. */
6767 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6768 mips_output_cplocal ();
6770 if (cfun->machine->all_noreorder_p)
6772 /* Avoid using %>%) since it adds excess whitespace. */
6773 output_asm_insn (".set\tmacro", 0);
6774 output_asm_insn (".set\treorder", 0);
6775 set_noreorder = set_nomacro = 0;
6778 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6782 /* Get the function name the same way that toplev.c does before calling
6783 assemble_start_function. This is needed so that the name used here
6784 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6785 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6786 fputs ("\t.end\t", file);
6787 assemble_name (file, fnname);
6792 /* Emit instructions to restore register REG from slot MEM. */
6795 mips_restore_reg (rtx reg, rtx mem)
6797 /* There's no mips16 instruction to load $31 directly. Load into
6798 $7 instead and adjust the return insn appropriately. */
6799 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6800 reg = gen_rtx_REG (GET_MODE (reg), 7);
6802 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6804 /* Can't restore directly; move through a temporary. */
6805 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6806 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6809 emit_move_insn (reg, mem);
6813 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6814 if this epilogue precedes a sibling call, false if it is for a normal
6815 "epilogue" pattern. */
6818 mips_expand_epilogue (int sibcall_p)
6820 HOST_WIDE_INT step1, step2;
6823 if (!sibcall_p && mips_can_use_return_insn ())
6825 emit_jump_insn (gen_return ());
6829 /* Split the frame into two. STEP1 is the amount of stack we should
6830 deallocate before restoring the registers. STEP2 is the amount we
6831 should deallocate afterwards.
6833 Start off by assuming that no registers need to be restored. */
6834 step1 = cfun->machine->frame.total_size;
6837 /* Work out which register holds the frame address. Account for the
6838 frame pointer offset used by mips16 code. */
6839 if (!frame_pointer_needed)
6840 base = stack_pointer_rtx;
6843 base = hard_frame_pointer_rtx;
6845 step1 -= cfun->machine->frame.args_size;
6848 /* If we need to restore registers, deallocate as much stack as
6849 possible in the second step without going out of range. */
6850 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6852 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6856 /* Set TARGET to BASE + STEP1. */
6862 /* Get an rtx for STEP1 that we can add to BASE. */
6863 adjust = GEN_INT (step1);
6864 if (!SMALL_OPERAND (step1))
6866 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6867 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6870 /* Normal mode code can copy the result straight into $sp. */
6872 target = stack_pointer_rtx;
6874 emit_insn (gen_add3_insn (target, base, adjust));
6877 /* Copy TARGET into the stack pointer. */
6878 if (target != stack_pointer_rtx)
6879 emit_move_insn (stack_pointer_rtx, target);
6881 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6882 implicitly used by all SYMBOL_REFs. We must emit a blockage
6883 insn before restoring it. */
6884 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6885 emit_insn (gen_blockage ());
6887 /* Restore the registers. */
6888 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6891 /* Deallocate the final bit of the frame. */
6893 emit_insn (gen_add3_insn (stack_pointer_rtx,
6897 /* Add in the __builtin_eh_return stack adjustment. We need to
6898 use a temporary in mips16 code. */
6899 if (current_function_calls_eh_return)
6903 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6904 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6905 MIPS_EPILOGUE_TEMP (Pmode),
6906 EH_RETURN_STACKADJ_RTX));
6907 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6910 emit_insn (gen_add3_insn (stack_pointer_rtx,
6912 EH_RETURN_STACKADJ_RTX));
6917 /* The mips16 loads the return address into $7, not $31. */
6918 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6919 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6920 GP_REG_FIRST + 7)));
6922 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6923 GP_REG_FIRST + 31)));
6927 /* Return nonzero if this function is known to have a null epilogue.
6928 This allows the optimizer to omit jumps to jumps if no stack
6932 mips_can_use_return_insn (void)
6936 if (! reload_completed)
6939 if (regs_ever_live[31] || current_function_profile)
6942 return_type = DECL_RESULT (current_function_decl);
6944 /* In mips16 mode, a function which returns a floating point value
6945 needs to arrange to copy the return value into the floating point
6948 && mips16_hard_float
6949 && ! aggregate_value_p (return_type, current_function_decl)
6950 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6951 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6954 if (cfun->machine->frame.initialized)
6955 return cfun->machine->frame.total_size == 0;
6957 return compute_frame_size (get_frame_size ()) == 0;
6960 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6961 in order to avoid duplicating too much logic from elsewhere. */
6964 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6965 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6968 rtx this, temp1, temp2, insn, fnaddr;
6970 /* Pretend to be a post-reload pass while generating rtl. */
6972 reload_completed = 1;
6973 reset_block_changes ();
6975 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6976 for TARGET_NEWABI since the latter is a call-saved register. */
6977 if (TARGET_ABICALLS)
6978 cfun->machine->global_pointer
6979 = REGNO (pic_offset_table_rtx)
6980 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6982 /* Set up the global pointer for n32 or n64 abicalls. */
6983 mips_emit_loadgp ();
6985 /* We need two temporary registers in some cases. */
6986 temp1 = gen_rtx_REG (Pmode, 2);
6987 temp2 = gen_rtx_REG (Pmode, 3);
6989 /* Find out which register contains the "this" pointer. */
6990 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6991 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6993 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6995 /* Add DELTA to THIS. */
6998 rtx offset = GEN_INT (delta);
6999 if (!SMALL_OPERAND (delta))
7001 emit_move_insn (temp1, offset);
7004 emit_insn (gen_add3_insn (this, this, offset));
7007 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7008 if (vcall_offset != 0)
7012 /* Set TEMP1 to *THIS. */
7013 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7015 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7016 addr = mips_add_offset (temp2, temp1, vcall_offset);
7018 /* Load the offset and add it to THIS. */
7019 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7020 emit_insn (gen_add3_insn (this, this, temp1));
7023 /* Jump to the target function. Use a sibcall if direct jumps are
7024 allowed, otherwise load the address into a register first. */
7025 fnaddr = XEXP (DECL_RTL (function), 0);
7026 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7028 /* This is messy. gas treats "la $25,foo" as part of a call
7029 sequence and may allow a global "foo" to be lazily bound.
7030 The general move patterns therefore reject this combination.
7032 In this context, lazy binding would actually be OK for o32 and o64,
7033 but it's still wrong for n32 and n64; see mips_load_call_address.
7034 We must therefore load the address via a temporary register if
7035 mips_dangerous_for_la25_p.
7037 If we jump to the temporary register rather than $25, the assembler
7038 can use the move insn to fill the jump's delay slot. */
7039 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7040 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7041 mips_load_call_address (temp1, fnaddr, true);
7043 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7044 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7045 emit_jump_insn (gen_indirect_jump (temp1));
7049 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7050 SIBLING_CALL_P (insn) = 1;
7053 /* Run just enough of rest_of_compilation. This sequence was
7054 "borrowed" from alpha.c. */
7055 insn = get_insns ();
7056 insn_locators_initialize ();
7057 split_all_insns_noflow ();
7059 mips16_lay_out_constants ();
7060 shorten_branches (insn);
7061 final_start_function (insn, file, 1);
7062 final (insn, file, 1);
7063 final_end_function ();
7065 /* Clean up the vars set above. Note that final_end_function resets
7066 the global pointer for us. */
7067 reload_completed = 0;
7071 /* Returns nonzero if X contains a SYMBOL_REF. */
7074 symbolic_expression_p (rtx x)
7076 if (GET_CODE (x) == SYMBOL_REF)
7079 if (GET_CODE (x) == CONST)
7080 return symbolic_expression_p (XEXP (x, 0));
7083 return symbolic_expression_p (XEXP (x, 0));
7085 if (ARITHMETIC_P (x))
7086 return (symbolic_expression_p (XEXP (x, 0))
7087 || symbolic_expression_p (XEXP (x, 1)));
7092 /* Choose the section to use for the constant rtx expression X that has
7096 mips_select_rtx_section (enum machine_mode mode, rtx x,
7097 unsigned HOST_WIDE_INT align)
7101 /* In mips16 mode, the constant table always goes in the same section
7102 as the function, so that constants can be loaded using PC relative
7104 return function_section (current_function_decl);
7106 else if (TARGET_EMBEDDED_DATA)
7108 /* For embedded applications, always put constants in read-only data,
7109 in order to reduce RAM usage. */
7110 return mergeable_constant_section (mode, align, 0);
7114 /* For hosted applications, always put constants in small data if
7115 possible, as this gives the best performance. */
7116 /* ??? Consider using mergeable small data sections. */
7118 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7119 && mips_section_threshold > 0)
7120 return get_named_section (NULL, ".sdata", 0);
7121 else if (flag_pic && symbolic_expression_p (x))
7122 return get_named_section (NULL, ".data.rel.ro", 3);
7124 return mergeable_constant_section (mode, align, 0);
7128 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7130 The complication here is that, with the combination TARGET_ABICALLS
7131 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7132 therefore not be included in the read-only part of a DSO. Handle such
7133 cases by selecting a normal data section instead of a read-only one.
7134 The logic apes that in default_function_rodata_section. */
7137 mips_function_rodata_section (tree decl)
7139 if (!TARGET_ABICALLS || TARGET_GPWORD)
7140 return default_function_rodata_section (decl);
7142 if (decl && DECL_SECTION_NAME (decl))
7144 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7145 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7147 char *rname = ASTRDUP (name);
7149 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7151 else if (flag_function_sections && flag_data_sections
7152 && strncmp (name, ".text.", 6) == 0)
7154 char *rname = ASTRDUP (name);
7155 memcpy (rname + 1, "data", 4);
7156 return get_section (rname, SECTION_WRITE, decl);
7159 return data_section;
7162 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7163 access DECL using %gp_rel(...)($gp). */
7166 mips_in_small_data_p (tree decl)
7170 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7173 /* We don't yet generate small-data references for -mabicalls. See related
7174 -G handling in override_options. */
7175 if (TARGET_ABICALLS)
7178 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7182 /* Reject anything that isn't in a known small-data section. */
7183 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7184 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7187 /* If a symbol is defined externally, the assembler will use the
7188 usual -G rules when deciding how to implement macros. */
7189 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7192 else if (TARGET_EMBEDDED_DATA)
7194 /* Don't put constants into the small data section: we want them
7195 to be in ROM rather than RAM. */
7196 if (TREE_CODE (decl) != VAR_DECL)
7199 if (TREE_READONLY (decl)
7200 && !TREE_SIDE_EFFECTS (decl)
7201 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7205 size = int_size_in_bytes (TREE_TYPE (decl));
7206 return (size > 0 && size <= mips_section_threshold);
7209 /* See whether VALTYPE is a record whose fields should be returned in
7210 floating-point registers. If so, return the number of fields and
7211 list them in FIELDS (which should have two elements). Return 0
7214 For n32 & n64, a structure with one or two fields is returned in
7215 floating-point registers as long as every field has a floating-point
7219 mips_fpr_return_fields (tree valtype, tree *fields)
7227 if (TREE_CODE (valtype) != RECORD_TYPE)
7231 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7233 if (TREE_CODE (field) != FIELD_DECL)
7236 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7242 fields[i++] = field;
7248 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7249 a value in the most significant part of $2/$3 if:
7251 - the target is big-endian;
7253 - the value has a structure or union type (we generalize this to
7254 cover aggregates from other languages too); and
7256 - the structure is not returned in floating-point registers. */
7259 mips_return_in_msb (tree valtype)
7263 return (TARGET_NEWABI
7264 && TARGET_BIG_ENDIAN
7265 && AGGREGATE_TYPE_P (valtype)
7266 && mips_fpr_return_fields (valtype, fields) == 0);
7270 /* Return a composite value in a pair of floating-point registers.
7271 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7272 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7275 For n32 & n64, $f0 always holds the first value and $f2 the second.
7276 Otherwise the values are packed together as closely as possible. */
7279 mips_return_fpr_pair (enum machine_mode mode,
7280 enum machine_mode mode1, HOST_WIDE_INT offset1,
7281 enum machine_mode mode2, HOST_WIDE_INT offset2)
7285 inc = (TARGET_NEWABI ? 2 : FP_INC);
7286 return gen_rtx_PARALLEL
7289 gen_rtx_EXPR_LIST (VOIDmode,
7290 gen_rtx_REG (mode1, FP_RETURN),
7292 gen_rtx_EXPR_LIST (VOIDmode,
7293 gen_rtx_REG (mode2, FP_RETURN + inc),
7294 GEN_INT (offset2))));
7299 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7300 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7301 VALTYPE is null and MODE is the mode of the return value. */
7304 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7305 enum machine_mode mode)
7312 mode = TYPE_MODE (valtype);
7313 unsignedp = TYPE_UNSIGNED (valtype);
7315 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7316 true, we must promote the mode just as PROMOTE_MODE does. */
7317 mode = promote_mode (valtype, mode, &unsignedp, 1);
7319 /* Handle structures whose fields are returned in $f0/$f2. */
7320 switch (mips_fpr_return_fields (valtype, fields))
7323 return gen_rtx_REG (mode, FP_RETURN);
7326 return mips_return_fpr_pair (mode,
7327 TYPE_MODE (TREE_TYPE (fields[0])),
7328 int_byte_position (fields[0]),
7329 TYPE_MODE (TREE_TYPE (fields[1])),
7330 int_byte_position (fields[1]));
7333 /* If a value is passed in the most significant part of a register, see
7334 whether we have to round the mode up to a whole number of words. */
7335 if (mips_return_in_msb (valtype))
7337 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7338 if (size % UNITS_PER_WORD != 0)
7340 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7341 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7345 /* For EABI, the class of return register depends entirely on MODE.
7346 For example, "struct { some_type x; }" and "union { some_type x; }"
7347 are returned in the same way as a bare "some_type" would be.
7348 Other ABIs only use FPRs for scalar, complex or vector types. */
7349 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7350 return gen_rtx_REG (mode, GP_RETURN);
7353 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7354 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7355 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7356 return gen_rtx_REG (mode, FP_RETURN);
7358 /* Handle long doubles for n32 & n64. */
7360 return mips_return_fpr_pair (mode,
7362 DImode, GET_MODE_SIZE (mode) / 2);
7364 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7365 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7366 return mips_return_fpr_pair (mode,
7367 GET_MODE_INNER (mode), 0,
7368 GET_MODE_INNER (mode),
7369 GET_MODE_SIZE (mode) / 2);
7371 return gen_rtx_REG (mode, GP_RETURN);
7374 /* Return nonzero when an argument must be passed by reference. */
7377 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7378 enum machine_mode mode, tree type,
7379 bool named ATTRIBUTE_UNUSED)
7381 if (mips_abi == ABI_EABI)
7385 /* ??? How should SCmode be handled? */
7386 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7389 size = int_size_in_bytes (type);
7390 return size == -1 || size > UNITS_PER_WORD;
7394 /* If we have a variable-sized parameter, we have no choice. */
7395 return targetm.calls.must_pass_in_stack (mode, type);
7400 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7401 enum machine_mode mode ATTRIBUTE_UNUSED,
7402 tree type ATTRIBUTE_UNUSED, bool named)
7404 return mips_abi == ABI_EABI && named;
7407 /* Return true if registers of class CLASS cannot change from mode FROM
7411 mips_cannot_change_mode_class (enum machine_mode from,
7412 enum machine_mode to, enum reg_class class)
7414 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7415 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7417 if (TARGET_BIG_ENDIAN)
7419 /* When a multi-word value is stored in paired floating-point
7420 registers, the first register always holds the low word.
7421 We therefore can't allow FPRs to change between single-word
7422 and multi-word modes. */
7423 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7428 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7429 in LO and HI, the high word always comes first. We therefore
7430 can't allow values stored in HI to change between single-word
7431 and multi-word modes.
7432 This rule applies to both the original HI/LO pair and the new
7433 DSP accumulators. */
7434 if (reg_classes_intersect_p (ACC_REGS, class))
7438 /* Loading a 32-bit value into a 64-bit floating-point register
7439 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7440 We can't allow 64-bit float registers to change from SImode to
7444 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7445 && reg_classes_intersect_p (FP_REGS, class))
7450 /* Return true if X should not be moved directly into register $25.
7451 We need this because many versions of GAS will treat "la $25,foo" as
7452 part of a call sequence and so allow a global "foo" to be lazily bound. */
7455 mips_dangerous_for_la25_p (rtx x)
7457 HOST_WIDE_INT offset;
7459 if (TARGET_EXPLICIT_RELOCS)
7462 mips_split_const (x, &x, &offset);
7463 return global_got_operand (x, VOIDmode);
7466 /* Implement PREFERRED_RELOAD_CLASS. */
7469 mips_preferred_reload_class (rtx x, enum reg_class class)
7471 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7474 if (TARGET_HARD_FLOAT
7475 && FLOAT_MODE_P (GET_MODE (x))
7476 && reg_class_subset_p (FP_REGS, class))
7479 if (reg_class_subset_p (GR_REGS, class))
7482 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7488 /* This function returns the register class required for a secondary
7489 register when copying between one of the registers in CLASS, and X,
7490 using MODE. If IN_P is nonzero, the copy is going from X to the
7491 register, otherwise the register is the source. A return value of
7492 NO_REGS means that no secondary register is required. */
7495 mips_secondary_reload_class (enum reg_class class,
7496 enum machine_mode mode, rtx x, int in_p)
7498 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7502 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7503 regno = true_regnum (x);
7505 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7507 if (mips_dangerous_for_la25_p (x))
7510 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7514 /* Copying from HI or LO to anywhere other than a general register
7515 requires a general register.
7516 This rule applies to both the original HI/LO pair and the new
7517 DSP accumulators. */
7518 if (reg_class_subset_p (class, ACC_REGS))
7520 if (TARGET_MIPS16 && in_p)
7522 /* We can't really copy to HI or LO at all in mips16 mode. */
7525 return gp_reg_p ? NO_REGS : gr_regs;
7527 if (ACC_REG_P (regno))
7529 if (TARGET_MIPS16 && ! in_p)
7531 /* We can't really copy to HI or LO at all in mips16 mode. */
7534 return class == gr_regs ? NO_REGS : gr_regs;
7537 /* We can only copy a value to a condition code register from a
7538 floating point register, and even then we require a scratch
7539 floating point register. We can only copy a value out of a
7540 condition code register into a general register. */
7541 if (class == ST_REGS)
7545 return gp_reg_p ? NO_REGS : gr_regs;
7547 if (ST_REG_P (regno))
7551 return class == gr_regs ? NO_REGS : gr_regs;
7554 if (class == FP_REGS)
7558 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7561 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7563 /* We can use the l.s and l.d macros to load floating-point
7564 constants. ??? For l.s, we could probably get better
7565 code by returning GR_REGS here. */
7568 else if (gp_reg_p || x == CONST0_RTX (mode))
7570 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7573 else if (FP_REG_P (regno))
7575 /* In this case we can use mov.s or mov.d. */
7580 /* Otherwise, we need to reload through an integer register. */
7585 /* In mips16 mode, going between memory and anything but M16_REGS
7586 requires an M16_REG. */
7589 if (class != M16_REGS && class != M16_NA_REGS)
7597 if (class == M16_REGS || class == M16_NA_REGS)
7606 /* Implement CLASS_MAX_NREGS.
7608 Usually all registers are word-sized. The only supported exception
7609 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7610 registers. A word-based calculation is correct even in that case,
7611 since -msingle-float disallows multi-FPR values.
7613 The FP status registers are an exception to this rule. They are always
7614 4 bytes wide as they only hold condition code modes, and CCmode is always
7615 considered to be 4 bytes wide. */
7618 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7619 enum machine_mode mode)
7621 if (class == ST_REGS)
7622 return (GET_MODE_SIZE (mode) + 3) / 4;
7624 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7628 mips_valid_pointer_mode (enum machine_mode mode)
7630 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7633 /* Target hook for vector_mode_supported_p. */
7636 mips_vector_mode_supported_p (enum machine_mode mode)
7641 return TARGET_PAIRED_SINGLE_FLOAT;
7652 /* If we can access small data directly (using gp-relative relocation
7653 operators) return the small data pointer, otherwise return null.
7655 For each mips16 function which refers to GP relative symbols, we
7656 use a pseudo register, initialized at the start of the function, to
7657 hold the $gp value. */
7660 mips16_gp_pseudo_reg (void)
7662 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7667 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7669 /* We want to initialize this to a value which gcc will believe
7672 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7673 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7674 gen_rtx_CONST (Pmode, unspec));
7675 insn = get_insns ();
7678 push_topmost_sequence ();
7679 /* We need to emit the initialization after the FUNCTION_BEG
7680 note, so that it will be integrated. */
7681 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7683 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7685 if (scan == NULL_RTX)
7686 scan = get_insns ();
7687 insn = emit_insn_after (insn, scan);
7688 pop_topmost_sequence ();
7691 return cfun->machine->mips16_gp_pseudo_rtx;
7694 /* Write out code to move floating point arguments in or out of
7695 general registers. Output the instructions to FILE. FP_CODE is
7696 the code describing which arguments are present (see the comment at
7697 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7698 we are copying from the floating point registers. */
7701 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7707 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7708 gcc_assert (TARGET_OLDABI);
7714 gparg = GP_ARG_FIRST;
7715 fparg = FP_ARG_FIRST;
7716 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7720 if ((fparg & 1) != 0)
7722 fprintf (file, "\t%s\t%s,%s\n", s,
7723 reg_names[gparg], reg_names[fparg]);
7725 else if ((f & 3) == 2)
7728 fprintf (file, "\td%s\t%s,%s\n", s,
7729 reg_names[gparg], reg_names[fparg]);
7732 if ((fparg & 1) != 0)
7734 if (TARGET_BIG_ENDIAN)
7735 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7736 reg_names[gparg], reg_names[fparg + 1], s,
7737 reg_names[gparg + 1], reg_names[fparg]);
7739 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7740 reg_names[gparg], reg_names[fparg], s,
7741 reg_names[gparg + 1], reg_names[fparg + 1]);
7754 /* Build a mips16 function stub. This is used for functions which
7755 take arguments in the floating point registers. It is 32 bit code
7756 that moves the floating point args into the general registers, and
7757 then jumps to the 16 bit code. */
7760 build_mips16_function_stub (FILE *file)
7763 char *secname, *stubname;
7764 tree stubid, stubdecl;
7768 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7769 secname = (char *) alloca (strlen (fnname) + 20);
7770 sprintf (secname, ".mips16.fn.%s", fnname);
7771 stubname = (char *) alloca (strlen (fnname) + 20);
7772 sprintf (stubname, "__fn_stub_%s", fnname);
7773 stubid = get_identifier (stubname);
7774 stubdecl = build_decl (FUNCTION_DECL, stubid,
7775 build_function_type (void_type_node, NULL_TREE));
7776 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7778 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7780 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7782 fprintf (file, "%s%s",
7783 need_comma ? ", " : "",
7784 (f & 3) == 1 ? "float" : "double");
7787 fprintf (file, ")\n");
7789 fprintf (file, "\t.set\tnomips16\n");
7790 switch_to_section (function_section (stubdecl));
7791 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7793 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7794 within a .ent, and we cannot emit another .ent. */
7795 if (!FUNCTION_NAME_ALREADY_DECLARED)
7797 fputs ("\t.ent\t", file);
7798 assemble_name (file, stubname);
7802 assemble_name (file, stubname);
7803 fputs (":\n", file);
7805 /* We don't want the assembler to insert any nops here. */
7806 fprintf (file, "\t.set\tnoreorder\n");
7808 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7810 fprintf (asm_out_file, "\t.set\tnoat\n");
7811 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7812 assemble_name (file, fnname);
7813 fprintf (file, "\n");
7814 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7815 fprintf (asm_out_file, "\t.set\tat\n");
7817 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7818 with one of the mfc1 instructions, because the result is not
7819 available for one instruction, so if the very first instruction
7820 in the function refers to the register, it will see the wrong
7822 fprintf (file, "\tnop\n");
7824 fprintf (file, "\t.set\treorder\n");
7826 if (!FUNCTION_NAME_ALREADY_DECLARED)
7828 fputs ("\t.end\t", file);
7829 assemble_name (file, stubname);
7833 fprintf (file, "\t.set\tmips16\n");
7835 switch_to_section (function_section (current_function_decl));
7838 /* We keep a list of functions for which we have already built stubs
7839 in build_mips16_call_stub. */
7843 struct mips16_stub *next;
7848 static struct mips16_stub *mips16_stubs;
7850 /* Build a call stub for a mips16 call. A stub is needed if we are
7851 passing any floating point values which should go into the floating
7852 point registers. If we are, and the call turns out to be to a 32
7853 bit function, the stub will be used to move the values into the
7854 floating point registers before calling the 32 bit function. The
7855 linker will magically adjust the function call to either the 16 bit
7856 function or the 32 bit stub, depending upon where the function call
7857 is actually defined.
7859 Similarly, we need a stub if the return value might come back in a
7860 floating point register.
7862 RETVAL is the location of the return value, or null if this is
7863 a call rather than a call_value. FN is the address of the
7864 function and ARG_SIZE is the size of the arguments. FP_CODE
7865 is the code built by function_arg. This function returns a nonzero
7866 value if it builds the call instruction itself. */
7869 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7873 char *secname, *stubname;
7874 struct mips16_stub *l;
7875 tree stubid, stubdecl;
7879 /* We don't need to do anything if we aren't in mips16 mode, or if
7880 we were invoked with the -msoft-float option. */
7881 if (! TARGET_MIPS16 || ! mips16_hard_float)
7884 /* Figure out whether the value might come back in a floating point
7886 fpret = (retval != 0
7887 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7888 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7890 /* We don't need to do anything if there were no floating point
7891 arguments and the value will not be returned in a floating point
7893 if (fp_code == 0 && ! fpret)
7896 /* We don't need to do anything if this is a call to a special
7897 mips16 support function. */
7898 if (GET_CODE (fn) == SYMBOL_REF
7899 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7902 /* This code will only work for o32 and o64 abis. The other ABI's
7903 require more sophisticated support. */
7904 gcc_assert (TARGET_OLDABI);
7906 /* We can only handle SFmode and DFmode floating point return
7909 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
7911 /* If we're calling via a function pointer, then we must always call
7912 via a stub. There are magic stubs provided in libgcc.a for each
7913 of the required cases. Each of them expects the function address
7914 to arrive in register $2. */
7916 if (GET_CODE (fn) != SYMBOL_REF)
7922 /* ??? If this code is modified to support other ABI's, we need
7923 to handle PARALLEL return values here. */
7925 sprintf (buf, "__mips16_call_stub_%s%d",
7927 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7930 id = get_identifier (buf);
7931 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7933 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7935 if (retval == NULL_RTX)
7936 insn = gen_call_internal (stub_fn, arg_size);
7938 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7939 insn = emit_call_insn (insn);
7941 /* Put the register usage information on the CALL. */
7942 CALL_INSN_FUNCTION_USAGE (insn) =
7943 gen_rtx_EXPR_LIST (VOIDmode,
7944 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7945 CALL_INSN_FUNCTION_USAGE (insn));
7947 /* If we are handling a floating point return value, we need to
7948 save $18 in the function prologue. Putting a note on the
7949 call will mean that regs_ever_live[$18] will be true if the
7950 call is not eliminated, and we can check that in the prologue
7953 CALL_INSN_FUNCTION_USAGE (insn) =
7954 gen_rtx_EXPR_LIST (VOIDmode,
7955 gen_rtx_USE (VOIDmode,
7956 gen_rtx_REG (word_mode, 18)),
7957 CALL_INSN_FUNCTION_USAGE (insn));
7959 /* Return 1 to tell the caller that we've generated the call
7964 /* We know the function we are going to call. If we have already
7965 built a stub, we don't need to do anything further. */
7967 fnname = XSTR (fn, 0);
7968 for (l = mips16_stubs; l != NULL; l = l->next)
7969 if (strcmp (l->name, fnname) == 0)
7974 /* Build a special purpose stub. When the linker sees a
7975 function call in mips16 code, it will check where the target
7976 is defined. If the target is a 32 bit call, the linker will
7977 search for the section defined here. It can tell which
7978 symbol this section is associated with by looking at the
7979 relocation information (the name is unreliable, since this
7980 might be a static function). If such a section is found, the
7981 linker will redirect the call to the start of the magic
7984 If the function does not return a floating point value, the
7985 special stub section is named
7988 If the function does return a floating point value, the stub
7990 .mips16.call.fp.FNNAME
7993 secname = (char *) alloca (strlen (fnname) + 40);
7994 sprintf (secname, ".mips16.call.%s%s",
7997 stubname = (char *) alloca (strlen (fnname) + 20);
7998 sprintf (stubname, "__call_stub_%s%s",
8001 stubid = get_identifier (stubname);
8002 stubdecl = build_decl (FUNCTION_DECL, stubid,
8003 build_function_type (void_type_node, NULL_TREE));
8004 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8006 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8008 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8012 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8014 fprintf (asm_out_file, "%s%s",
8015 need_comma ? ", " : "",
8016 (f & 3) == 1 ? "float" : "double");
8019 fprintf (asm_out_file, ")\n");
8021 fprintf (asm_out_file, "\t.set\tnomips16\n");
8022 assemble_start_function (stubdecl, stubname);
8024 if (!FUNCTION_NAME_ALREADY_DECLARED)
8026 fputs ("\t.ent\t", asm_out_file);
8027 assemble_name (asm_out_file, stubname);
8028 fputs ("\n", asm_out_file);
8030 assemble_name (asm_out_file, stubname);
8031 fputs (":\n", asm_out_file);
8034 /* We build the stub code by hand. That's the only way we can
8035 do it, since we can't generate 32 bit code during a 16 bit
8038 /* We don't want the assembler to insert any nops here. */
8039 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8041 mips16_fp_args (asm_out_file, fp_code, 0);
8045 fprintf (asm_out_file, "\t.set\tnoat\n");
8046 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8048 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8049 fprintf (asm_out_file, "\t.set\tat\n");
8050 /* Unfortunately, we can't fill the jump delay slot. We
8051 can't fill with one of the mtc1 instructions, because the
8052 result is not available for one instruction, so if the
8053 very first instruction in the function refers to the
8054 register, it will see the wrong value. */
8055 fprintf (asm_out_file, "\tnop\n");
8059 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8060 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8061 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8062 /* As above, we can't fill the delay slot. */
8063 fprintf (asm_out_file, "\tnop\n");
8064 if (GET_MODE (retval) == SFmode)
8065 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8066 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8069 if (TARGET_BIG_ENDIAN)
8071 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8072 reg_names[GP_REG_FIRST + 2],
8073 reg_names[FP_REG_FIRST + 1]);
8074 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8075 reg_names[GP_REG_FIRST + 3],
8076 reg_names[FP_REG_FIRST + 0]);
8080 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8081 reg_names[GP_REG_FIRST + 2],
8082 reg_names[FP_REG_FIRST + 0]);
8083 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8084 reg_names[GP_REG_FIRST + 3],
8085 reg_names[FP_REG_FIRST + 1]);
8088 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8089 /* As above, we can't fill the delay slot. */
8090 fprintf (asm_out_file, "\tnop\n");
8093 fprintf (asm_out_file, "\t.set\treorder\n");
8095 #ifdef ASM_DECLARE_FUNCTION_SIZE
8096 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8099 if (!FUNCTION_NAME_ALREADY_DECLARED)
8101 fputs ("\t.end\t", asm_out_file);
8102 assemble_name (asm_out_file, stubname);
8103 fputs ("\n", asm_out_file);
8106 fprintf (asm_out_file, "\t.set\tmips16\n");
8108 /* Record this stub. */
8109 l = (struct mips16_stub *) xmalloc (sizeof *l);
8110 l->name = xstrdup (fnname);
8112 l->next = mips16_stubs;
8116 /* If we expect a floating point return value, but we've built a
8117 stub which does not expect one, then we're in trouble. We can't
8118 use the existing stub, because it won't handle the floating point
8119 value. We can't build a new stub, because the linker won't know
8120 which stub to use for the various calls in this object file.
8121 Fortunately, this case is illegal, since it means that a function
8122 was declared in two different ways in a single compilation. */
8123 if (fpret && ! l->fpret)
8124 error ("cannot handle inconsistent calls to %qs", fnname);
8126 /* If we are calling a stub which handles a floating point return
8127 value, we need to arrange to save $18 in the prologue. We do
8128 this by marking the function call as using the register. The
8129 prologue will later see that it is used, and emit code to save
8136 if (retval == NULL_RTX)
8137 insn = gen_call_internal (fn, arg_size);
8139 insn = gen_call_value_internal (retval, fn, arg_size);
8140 insn = emit_call_insn (insn);
8142 CALL_INSN_FUNCTION_USAGE (insn) =
8143 gen_rtx_EXPR_LIST (VOIDmode,
8144 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8145 CALL_INSN_FUNCTION_USAGE (insn));
8147 /* Return 1 to tell the caller that we've generated the call
8152 /* Return 0 to let the caller generate the call insn. */
8156 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8157 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8159 struct mips16_constant {
8160 struct mips16_constant *next;
8163 enum machine_mode mode;
8166 /* Information about an incomplete mips16 constant pool. FIRST is the
8167 first constant, HIGHEST_ADDRESS is the highest address that the first
8168 byte of the pool can have, and INSN_ADDRESS is the current instruction
8171 struct mips16_constant_pool {
8172 struct mips16_constant *first;
8173 int highest_address;
8177 /* Add constant VALUE to POOL and return its label. MODE is the
8178 value's mode (used for CONST_INTs, etc.). */
8181 add_constant (struct mips16_constant_pool *pool,
8182 rtx value, enum machine_mode mode)
8184 struct mips16_constant **p, *c;
8185 bool first_of_size_p;
8187 /* See whether the constant is already in the pool. If so, return the
8188 existing label, otherwise leave P pointing to the place where the
8189 constant should be added.
8191 Keep the pool sorted in increasing order of mode size so that we can
8192 reduce the number of alignments needed. */
8193 first_of_size_p = true;
8194 for (p = &pool->first; *p != 0; p = &(*p)->next)
8196 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8198 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8200 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8201 first_of_size_p = false;
8204 /* In the worst case, the constant needed by the earliest instruction
8205 will end up at the end of the pool. The entire pool must then be
8206 accessible from that instruction.
8208 When adding the first constant, set the pool's highest address to
8209 the address of the first out-of-range byte. Adjust this address
8210 downwards each time a new constant is added. */
8211 if (pool->first == 0)
8212 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8213 is the address of the instruction with the lowest two bits clear.
8214 The base PC value for ld has the lowest three bits clear. Assume
8215 the worst case here. */
8216 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8217 pool->highest_address -= GET_MODE_SIZE (mode);
8218 if (first_of_size_p)
8219 /* Take into account the worst possible padding due to alignment. */
8220 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8222 /* Create a new entry. */
8223 c = (struct mips16_constant *) xmalloc (sizeof *c);
8226 c->label = gen_label_rtx ();
8233 /* Output constant VALUE after instruction INSN and return the last
8234 instruction emitted. MODE is the mode of the constant. */
8237 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8239 switch (GET_MODE_CLASS (mode))
8243 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8244 return emit_insn_after (gen_consttable_int (value, size), insn);
8248 return emit_insn_after (gen_consttable_float (value), insn);
8250 case MODE_VECTOR_FLOAT:
8251 case MODE_VECTOR_INT:
8254 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8255 insn = dump_constants_1 (GET_MODE_INNER (mode),
8256 CONST_VECTOR_ELT (value, i), insn);
8266 /* Dump out the constants in CONSTANTS after INSN. */
8269 dump_constants (struct mips16_constant *constants, rtx insn)
8271 struct mips16_constant *c, *next;
8275 for (c = constants; c != NULL; c = next)
8277 /* If necessary, increase the alignment of PC. */
8278 if (align < GET_MODE_SIZE (c->mode))
8280 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8281 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8283 align = GET_MODE_SIZE (c->mode);
8285 insn = emit_label_after (c->label, insn);
8286 insn = dump_constants_1 (c->mode, c->value, insn);
8292 emit_barrier_after (insn);
8295 /* Return the length of instruction INSN. */
8298 mips16_insn_length (rtx insn)
8302 rtx body = PATTERN (insn);
8303 if (GET_CODE (body) == ADDR_VEC)
8304 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8305 if (GET_CODE (body) == ADDR_DIFF_VEC)
8306 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8308 return get_attr_length (insn);
8311 /* Rewrite *X so that constant pool references refer to the constant's
8312 label instead. DATA points to the constant pool structure. */
8315 mips16_rewrite_pool_refs (rtx *x, void *data)
8317 struct mips16_constant_pool *pool = data;
8318 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8319 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8320 get_pool_constant (*x),
8321 get_pool_mode (*x)));
8325 /* Build MIPS16 constant pools. */
8328 mips16_lay_out_constants (void)
8330 struct mips16_constant_pool pool;
8334 memset (&pool, 0, sizeof (pool));
8335 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8337 /* Rewrite constant pool references in INSN. */
8339 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8341 pool.insn_address += mips16_insn_length (insn);
8343 if (pool.first != NULL)
8345 /* If there are no natural barriers between the first user of
8346 the pool and the highest acceptable address, we'll need to
8347 create a new instruction to jump around the constant pool.
8348 In the worst case, this instruction will be 4 bytes long.
8350 If it's too late to do this transformation after INSN,
8351 do it immediately before INSN. */
8352 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8356 label = gen_label_rtx ();
8358 jump = emit_jump_insn_before (gen_jump (label), insn);
8359 JUMP_LABEL (jump) = label;
8360 LABEL_NUSES (label) = 1;
8361 barrier = emit_barrier_after (jump);
8363 emit_label_after (label, barrier);
8364 pool.insn_address += 4;
8367 /* See whether the constant pool is now out of range of the first
8368 user. If so, output the constants after the previous barrier.
8369 Note that any instructions between BARRIER and INSN (inclusive)
8370 will use negative offsets to refer to the pool. */
8371 if (pool.insn_address > pool.highest_address)
8373 dump_constants (pool.first, barrier);
8377 else if (BARRIER_P (insn))
8381 dump_constants (pool.first, get_last_insn ());
8384 /* A temporary variable used by for_each_rtx callbacks, etc. */
8385 static rtx mips_sim_insn;
8387 /* A structure representing the state of the processor pipeline.
8388 Used by the mips_sim_* family of functions. */
8390 /* The maximum number of instructions that can be issued in a cycle.
8391 (Caches mips_issue_rate.) */
8392 unsigned int issue_rate;
8394 /* The current simulation time. */
8397 /* How many more instructions can be issued in the current cycle. */
8398 unsigned int insns_left;
8400 /* LAST_SET[X].INSN is the last instruction to set register X.
8401 LAST_SET[X].TIME is the time at which that instruction was issued.
8402 INSN is null if no instruction has yet set register X. */
8406 } last_set[FIRST_PSEUDO_REGISTER];
8408 /* The pipeline's current DFA state. */
8412 /* Reset STATE to the initial simulation state. */
8415 mips_sim_reset (struct mips_sim *state)
8418 state->insns_left = state->issue_rate;
8419 memset (&state->last_set, 0, sizeof (state->last_set));
8420 state_reset (state->dfa_state);
8423 /* Initialize STATE before its first use. DFA_STATE points to an
8424 allocated but uninitialized DFA state. */
8427 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8429 state->issue_rate = mips_issue_rate ();
8430 state->dfa_state = dfa_state;
8431 mips_sim_reset (state);
8434 /* Advance STATE by one clock cycle. */
8437 mips_sim_next_cycle (struct mips_sim *state)
8440 state->insns_left = state->issue_rate;
8441 state_transition (state->dfa_state, 0);
8444 /* Advance simulation state STATE until instruction INSN can read
8448 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8452 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8453 if (state->last_set[REGNO (reg) + i].insn != 0)
8457 t = state->last_set[REGNO (reg) + i].time;
8458 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8459 while (state->time < t)
8460 mips_sim_next_cycle (state);
8464 /* A for_each_rtx callback. If *X is a register, advance simulation state
8465 DATA until mips_sim_insn can read the register's value. */
8468 mips_sim_wait_regs_2 (rtx *x, void *data)
8471 mips_sim_wait_reg (data, mips_sim_insn, *x);
8475 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8478 mips_sim_wait_regs_1 (rtx *x, void *data)
8480 for_each_rtx (x, mips_sim_wait_regs_2, data);
8483 /* Advance simulation state STATE until all of INSN's register
8484 dependencies are satisfied. */
8487 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8489 mips_sim_insn = insn;
8490 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8493 /* Advance simulation state STATE until the units required by
8494 instruction INSN are available. */
8497 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8501 tmp_state = alloca (state_size ());
8502 while (state->insns_left == 0
8503 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8504 state_transition (tmp_state, insn) >= 0))
8505 mips_sim_next_cycle (state);
8508 /* Advance simulation state STATE until INSN is ready to issue. */
8511 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8513 mips_sim_wait_regs (state, insn);
8514 mips_sim_wait_units (state, insn);
8517 /* mips_sim_insn has just set X. Update the LAST_SET array
8518 in simulation state DATA. */
8521 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8523 struct mips_sim *state;
8528 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8530 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8531 state->last_set[REGNO (x) + i].time = state->time;
8535 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8536 can issue immediately (i.e., that mips_sim_wait_insn has already
8540 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8542 state_transition (state->dfa_state, insn);
8543 state->insns_left--;
8545 mips_sim_insn = insn;
8546 note_stores (PATTERN (insn), mips_sim_record_set, state);
8549 /* Simulate issuing a NOP in state STATE. */
8552 mips_sim_issue_nop (struct mips_sim *state)
8554 if (state->insns_left == 0)
8555 mips_sim_next_cycle (state);
8556 state->insns_left--;
8559 /* Update simulation state STATE so that it's ready to accept the instruction
8560 after INSN. INSN should be part of the main rtl chain, not a member of a
8564 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8566 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8568 mips_sim_issue_nop (state);
8570 switch (GET_CODE (SEQ_BEGIN (insn)))
8574 /* We can't predict the processor state after a call or label. */
8575 mips_sim_reset (state);
8579 /* The delay slots of branch likely instructions are only executed
8580 when the branch is taken. Therefore, if the caller has simulated
8581 the delay slot instruction, STATE does not really reflect the state
8582 of the pipeline for the instruction after the delay slot. Also,
8583 branch likely instructions tend to incur a penalty when not taken,
8584 so there will probably be an extra delay between the branch and
8585 the instruction after the delay slot. */
8586 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8587 mips_sim_reset (state);
8595 /* The VR4130 pipeline issues aligned pairs of instructions together,
8596 but it stalls the second instruction if it depends on the first.
8597 In order to cut down the amount of logic required, this dependence
8598 check is not based on a full instruction decode. Instead, any non-SPECIAL
8599 instruction is assumed to modify the register specified by bits 20-16
8600 (which is usually the "rt" field).
8602 In beq, beql, bne and bnel instructions, the rt field is actually an
8603 input, so we can end up with a false dependence between the branch
8604 and its delay slot. If this situation occurs in instruction INSN,
8605 try to avoid it by swapping rs and rt. */
8608 vr4130_avoid_branch_rt_conflict (rtx insn)
8612 first = SEQ_BEGIN (insn);
8613 second = SEQ_END (insn);
8615 && NONJUMP_INSN_P (second)
8616 && GET_CODE (PATTERN (first)) == SET
8617 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8618 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8620 /* Check for the right kind of condition. */
8621 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8622 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8623 && REG_P (XEXP (cond, 0))
8624 && REG_P (XEXP (cond, 1))
8625 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8626 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8628 /* SECOND mentions the rt register but not the rs register. */
8629 rtx tmp = XEXP (cond, 0);
8630 XEXP (cond, 0) = XEXP (cond, 1);
8631 XEXP (cond, 1) = tmp;
8636 /* Implement -mvr4130-align. Go through each basic block and simulate the
8637 processor pipeline. If we find that a pair of instructions could execute
8638 in parallel, and the first of those instruction is not 8-byte aligned,
8639 insert a nop to make it aligned. */
8642 vr4130_align_insns (void)
8644 struct mips_sim state;
8645 rtx insn, subinsn, last, last2, next;
8650 /* LAST is the last instruction before INSN to have a nonzero length.
8651 LAST2 is the last such instruction before LAST. */
8655 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8658 mips_sim_init (&state, alloca (state_size ()));
8659 for (insn = get_insns (); insn != 0; insn = next)
8661 unsigned int length;
8663 next = NEXT_INSN (insn);
8665 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8666 This isn't really related to the alignment pass, but we do it on
8667 the fly to avoid a separate instruction walk. */
8668 vr4130_avoid_branch_rt_conflict (insn);
8670 if (USEFUL_INSN_P (insn))
8671 FOR_EACH_SUBINSN (subinsn, insn)
8673 mips_sim_wait_insn (&state, subinsn);
8675 /* If we want this instruction to issue in parallel with the
8676 previous one, make sure that the previous instruction is
8677 aligned. There are several reasons why this isn't worthwhile
8678 when the second instruction is a call:
8680 - Calls are less likely to be performance critical,
8681 - There's a good chance that the delay slot can execute
8682 in parallel with the call.
8683 - The return address would then be unaligned.
8685 In general, if we're going to insert a nop between instructions
8686 X and Y, it's better to insert it immediately after X. That
8687 way, if the nop makes Y aligned, it will also align any labels
8689 if (state.insns_left != state.issue_rate
8690 && !CALL_P (subinsn))
8692 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8694 /* SUBINSN is the first instruction in INSN and INSN is
8695 aligned. We want to align the previous instruction
8696 instead, so insert a nop between LAST2 and LAST.
8698 Note that LAST could be either a single instruction
8699 or a branch with a delay slot. In the latter case,
8700 LAST, like INSN, is already aligned, but the delay
8701 slot must have some extra delay that stops it from
8702 issuing at the same time as the branch. We therefore
8703 insert a nop before the branch in order to align its
8705 emit_insn_after (gen_nop (), last2);
8708 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8710 /* SUBINSN is the delay slot of INSN, but INSN is
8711 currently unaligned. Insert a nop between
8712 LAST and INSN to align it. */
8713 emit_insn_after (gen_nop (), last);
8717 mips_sim_issue_insn (&state, subinsn);
8719 mips_sim_finish_insn (&state, insn);
8721 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8722 length = get_attr_length (insn);
8725 /* If the instruction is an asm statement or multi-instruction
8726 mips.md patern, the length is only an estimate. Insert an
8727 8 byte alignment after it so that the following instructions
8728 can be handled correctly. */
8729 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8730 && (recog_memoized (insn) < 0 || length >= 8))
8732 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8733 next = NEXT_INSN (next);
8734 mips_sim_next_cycle (&state);
8737 else if (length & 4)
8738 aligned_p = !aligned_p;
8743 /* See whether INSN is an aligned label. */
8744 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8750 /* Subroutine of mips_reorg. If there is a hazard between INSN
8751 and a previous instruction, avoid it by inserting nops after
8754 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8755 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8756 before using the value of that register. *HILO_DELAY counts the
8757 number of instructions since the last hilo hazard (that is,
8758 the number of instructions since the last mflo or mfhi).
8760 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8761 for the next instruction.
8763 LO_REG is an rtx for the LO register, used in dependence checking. */
8766 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8767 rtx *delayed_reg, rtx lo_reg)
8775 pattern = PATTERN (insn);
8777 /* Do not put the whole function in .set noreorder if it contains
8778 an asm statement. We don't know whether there will be hazards
8779 between the asm statement and the gcc-generated code. */
8780 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8781 cfun->machine->all_noreorder_p = false;
8783 /* Ignore zero-length instructions (barriers and the like). */
8784 ninsns = get_attr_length (insn) / 4;
8788 /* Work out how many nops are needed. Note that we only care about
8789 registers that are explicitly mentioned in the instruction's pattern.
8790 It doesn't matter that calls use the argument registers or that they
8791 clobber hi and lo. */
8792 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8793 nops = 2 - *hilo_delay;
8794 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8799 /* Insert the nops between this instruction and the previous one.
8800 Each new nop takes us further from the last hilo hazard. */
8801 *hilo_delay += nops;
8803 emit_insn_after (gen_hazard_nop (), after);
8805 /* Set up the state for the next instruction. */
8806 *hilo_delay += ninsns;
8808 if (INSN_CODE (insn) >= 0)
8809 switch (get_attr_hazard (insn))
8819 set = single_set (insn);
8820 gcc_assert (set != 0);
8821 *delayed_reg = SET_DEST (set);
8827 /* Go through the instruction stream and insert nops where necessary.
8828 See if the whole function can then be put into .set noreorder &
8832 mips_avoid_hazards (void)
8834 rtx insn, last_insn, lo_reg, delayed_reg;
8837 /* Force all instructions to be split into their final form. */
8838 split_all_insns_noflow ();
8840 /* Recalculate instruction lengths without taking nops into account. */
8841 cfun->machine->ignore_hazard_length_p = true;
8842 shorten_branches (get_insns ());
8844 cfun->machine->all_noreorder_p = true;
8846 /* Profiled functions can't be all noreorder because the profiler
8847 support uses assembler macros. */
8848 if (current_function_profile)
8849 cfun->machine->all_noreorder_p = false;
8851 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8852 we rely on the assembler to work around some errata. */
8853 if (TARGET_FIX_VR4120)
8854 cfun->machine->all_noreorder_p = false;
8856 /* The same is true for -mfix-vr4130 if we might generate mflo or
8857 mfhi instructions. Note that we avoid using mflo and mfhi if
8858 the VR4130 macc and dmacc instructions are available instead;
8859 see the *mfhilo_{si,di}_macc patterns. */
8860 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8861 cfun->machine->all_noreorder_p = false;
8866 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8868 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8871 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8872 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8873 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8874 &hilo_delay, &delayed_reg, lo_reg);
8876 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8877 &delayed_reg, lo_reg);
8884 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8890 mips16_lay_out_constants ();
8891 else if (TARGET_EXPLICIT_RELOCS)
8893 if (mips_flag_delayed_branch)
8894 dbr_schedule (get_insns ());
8895 mips_avoid_hazards ();
8896 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8897 vr4130_align_insns ();
8901 /* This function does three things:
8903 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8904 - Register the mips16 hardware floating point stubs.
8905 - Register the gofast functions if selected using --enable-gofast. */
8907 #include "config/gofast.h"
8910 mips_init_libfuncs (void)
8912 if (TARGET_FIX_VR4120)
8914 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8915 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8918 if (TARGET_MIPS16 && mips16_hard_float)
8920 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8921 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8922 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8923 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8925 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8926 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8927 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8928 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8929 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8930 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8932 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8933 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8935 if (TARGET_DOUBLE_FLOAT)
8937 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8938 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8939 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8940 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8942 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8943 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8944 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8945 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8946 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8947 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8949 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8950 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8952 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8953 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8957 gofast_maybe_init_libfuncs ();
8960 /* Return a number assessing the cost of moving a register in class
8961 FROM to class TO. The classes are expressed using the enumeration
8962 values such as `GENERAL_REGS'. A value of 2 is the default; other
8963 values are interpreted relative to that.
8965 It is not required that the cost always equal 2 when FROM is the
8966 same as TO; on some machines it is expensive to move between
8967 registers if they are not general registers.
8969 If reload sees an insn consisting of a single `set' between two
8970 hard registers, and if `REGISTER_MOVE_COST' applied to their
8971 classes returns a value of 2, reload does not check to ensure that
8972 the constraints of the insn are met. Setting a cost of other than
8973 2 will allow reload to verify that the constraints are met. You
8974 should do this if the `movM' pattern's constraints do not allow
8977 ??? We make the cost of moving from HI/LO into general
8978 registers the same as for one of moving general registers to
8979 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8980 pseudo to HI/LO. This might hurt optimizations though, it
8981 isn't clear if it is wise. And it might not work in all cases. We
8982 could solve the DImode LO reg problem by using a multiply, just
8983 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8984 problem by using divide instructions. divu puts the remainder in
8985 the HI reg, so doing a divide by -1 will move the value in the HI
8986 reg for all values except -1. We could handle that case by using a
8987 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8988 a compare/branch to test the input value to see which instruction
8989 we need to use. This gets pretty messy, but it is feasible. */
8992 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8993 enum reg_class to, enum reg_class from)
8995 if (from == M16_REGS && GR_REG_CLASS_P (to))
8997 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8999 else if (GR_REG_CLASS_P (from))
9003 else if (to == M16_NA_REGS)
9005 else if (GR_REG_CLASS_P (to))
9012 else if (to == FP_REGS)
9014 else if (reg_class_subset_p (to, ACC_REGS))
9021 else if (COP_REG_CLASS_P (to))
9026 else if (from == FP_REGS)
9028 if (GR_REG_CLASS_P (to))
9030 else if (to == FP_REGS)
9032 else if (to == ST_REGS)
9035 else if (reg_class_subset_p (from, ACC_REGS))
9037 if (GR_REG_CLASS_P (to))
9045 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9047 else if (COP_REG_CLASS_P (from))
9053 ??? What cases are these? Shouldn't we return 2 here? */
9058 /* Return the length of INSN. LENGTH is the initial length computed by
9059 attributes in the machine-description file. */
9062 mips_adjust_insn_length (rtx insn, int length)
9064 /* A unconditional jump has an unfilled delay slot if it is not part
9065 of a sequence. A conditional jump normally has a delay slot, but
9066 does not on MIPS16. */
9067 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9070 /* See how many nops might be needed to avoid hardware hazards. */
9071 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9072 switch (get_attr_hazard (insn))
9086 /* All MIPS16 instructions are a measly two bytes. */
9094 /* Return an asm sequence to start a noat block and load the address
9095 of a label into $1. */
9098 mips_output_load_label (void)
9100 if (TARGET_EXPLICIT_RELOCS)
9104 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9107 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9110 if (ISA_HAS_LOAD_DELAY)
9111 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9112 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9116 if (Pmode == DImode)
9117 return "%[dla\t%@,%0";
9119 return "%[la\t%@,%0";
9123 /* Return the assembly code for INSN, which has the operands given by
9124 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9125 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9126 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9127 version of BRANCH_IF_TRUE. */
9130 mips_output_conditional_branch (rtx insn, rtx *operands,
9131 const char *branch_if_true,
9132 const char *branch_if_false)
9134 unsigned int length;
9135 rtx taken, not_taken;
9137 length = get_attr_length (insn);
9140 /* Just a simple conditional branch. */
9141 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9142 return branch_if_true;
9145 /* Generate a reversed branch around a direct jump. This fallback does
9146 not use branch-likely instructions. */
9147 mips_branch_likely = false;
9148 not_taken = gen_label_rtx ();
9149 taken = operands[1];
9151 /* Generate the reversed branch to NOT_TAKEN. */
9152 operands[1] = not_taken;
9153 output_asm_insn (branch_if_false, operands);
9155 /* If INSN has a delay slot, we must provide delay slots for both the
9156 branch to NOT_TAKEN and the conditional jump. We must also ensure
9157 that INSN's delay slot is executed in the appropriate cases. */
9160 /* This first delay slot will always be executed, so use INSN's
9161 delay slot if is not annulled. */
9162 if (!INSN_ANNULLED_BRANCH_P (insn))
9164 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9165 asm_out_file, optimize, 1, NULL);
9166 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9169 output_asm_insn ("nop", 0);
9170 fprintf (asm_out_file, "\n");
9173 /* Output the unconditional branch to TAKEN. */
9175 output_asm_insn ("j\t%0%/", &taken);
9178 output_asm_insn (mips_output_load_label (), &taken);
9179 output_asm_insn ("jr\t%@%]%/", 0);
9182 /* Now deal with its delay slot; see above. */
9185 /* This delay slot will only be executed if the branch is taken.
9186 Use INSN's delay slot if is annulled. */
9187 if (INSN_ANNULLED_BRANCH_P (insn))
9189 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9190 asm_out_file, optimize, 1, NULL);
9191 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9194 output_asm_insn ("nop", 0);
9195 fprintf (asm_out_file, "\n");
9198 /* Output NOT_TAKEN. */
9199 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9200 CODE_LABEL_NUMBER (not_taken));
9204 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9205 if some ordered condition is true. The condition is given by
9206 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9207 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9208 its second is always zero. */
9211 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9213 const char *branch[2];
9215 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9216 Make BRANCH[0] branch on the inverse condition. */
9217 switch (GET_CODE (operands[0]))
9219 /* These cases are equivalent to comparisons against zero. */
9221 inverted_p = !inverted_p;
9224 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9225 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9228 /* These cases are always true or always false. */
9230 inverted_p = !inverted_p;
9233 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9234 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9238 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9239 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9242 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9245 /* Used to output div or ddiv instruction DIVISION, which has the operands
9246 given by OPERANDS. Add in a divide-by-zero check if needed.
9248 When working around R4000 and R4400 errata, we need to make sure that
9249 the division is not immediately followed by a shift[1][2]. We also
9250 need to stop the division from being put into a branch delay slot[3].
9251 The easiest way to avoid both problems is to add a nop after the
9252 division. When a divide-by-zero check is needed, this nop can be
9253 used to fill the branch delay slot.
9255 [1] If a double-word or a variable shift executes immediately
9256 after starting an integer division, the shift may give an
9257 incorrect result. See quotations of errata #16 and #28 from
9258 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9259 in mips.md for details.
9261 [2] A similar bug to [1] exists for all revisions of the
9262 R4000 and the R4400 when run in an MC configuration.
9263 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9265 "19. In this following sequence:
9267 ddiv (or ddivu or div or divu)
9268 dsll32 (or dsrl32, dsra32)
9270 if an MPT stall occurs, while the divide is slipping the cpu
9271 pipeline, then the following double shift would end up with an
9274 Workaround: The compiler needs to avoid generating any
9275 sequence with divide followed by extended double shift."
9277 This erratum is also present in "MIPS R4400MC Errata, Processor
9278 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9279 & 3.0" as errata #10 and #4, respectively.
9281 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9282 (also valid for MIPS R4000MC processors):
9284 "52. R4000SC: This bug does not apply for the R4000PC.
9286 There are two flavors of this bug:
9288 1) If the instruction just after divide takes an RF exception
9289 (tlb-refill, tlb-invalid) and gets an instruction cache
9290 miss (both primary and secondary) and the line which is
9291 currently in secondary cache at this index had the first
9292 data word, where the bits 5..2 are set, then R4000 would
9293 get a wrong result for the div.
9298 ------------------- # end-of page. -tlb-refill
9303 ------------------- # end-of page. -tlb-invalid
9306 2) If the divide is in the taken branch delay slot, where the
9307 target takes RF exception and gets an I-cache miss for the
9308 exception vector or where I-cache miss occurs for the
9309 target address, under the above mentioned scenarios, the
9310 div would get wrong results.
9313 j r2 # to next page mapped or unmapped
9314 div r8,r9 # this bug would be there as long
9315 # as there is an ICache miss and
9316 nop # the "data pattern" is present
9319 beq r0, r0, NextPage # to Next page
9323 This bug is present for div, divu, ddiv, and ddivu
9326 Workaround: For item 1), OS could make sure that the next page
9327 after the divide instruction is also mapped. For item 2), the
9328 compiler could make sure that the divide instruction is not in
9329 the branch delay slot."
9331 These processors have PRId values of 0x00004220 and 0x00004300 for
9332 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9335 mips_output_division (const char *division, rtx *operands)
9340 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9342 output_asm_insn (s, operands);
9345 if (TARGET_CHECK_ZERO_DIV)
9349 output_asm_insn (s, operands);
9350 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9352 else if (GENERATE_DIVIDE_TRAPS)
9354 output_asm_insn (s, operands);
9359 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9360 output_asm_insn (s, operands);
9361 s = "break\t7%)\n1:";
9367 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9368 with a final "000" replaced by "k". Ignore case.
9370 Note: this function is shared between GCC and GAS. */
9373 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9375 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9376 given++, canonical++;
9378 return ((*given == 0 && *canonical == 0)
9379 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9383 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9384 CPU name. We've traditionally allowed a lot of variation here.
9386 Note: this function is shared between GCC and GAS. */
9389 mips_matching_cpu_name_p (const char *canonical, const char *given)
9391 /* First see if the name matches exactly, or with a final "000"
9393 if (mips_strict_matching_cpu_name_p (canonical, given))
9396 /* If not, try comparing based on numerical designation alone.
9397 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9398 if (TOLOWER (*given) == 'r')
9400 if (!ISDIGIT (*given))
9403 /* Skip over some well-known prefixes in the canonical name,
9404 hoping to find a number there too. */
9405 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9407 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9409 else if (TOLOWER (canonical[0]) == 'r')
9412 return mips_strict_matching_cpu_name_p (canonical, given);
9416 /* Return the mips_cpu_info entry for the processor or ISA given
9417 by CPU_STRING. Return null if the string isn't recognized.
9419 A similar function exists in GAS. */
9421 static const struct mips_cpu_info *
9422 mips_parse_cpu (const char *cpu_string)
9424 const struct mips_cpu_info *p;
9427 /* In the past, we allowed upper-case CPU names, but it doesn't
9428 work well with the multilib machinery. */
9429 for (s = cpu_string; *s != 0; s++)
9432 warning (0, "the cpu name must be lower case");
9436 /* 'from-abi' selects the most compatible architecture for the given
9437 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9438 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9439 version. Look first at the -mgp options, if given, otherwise base
9440 the choice on MASK_64BIT in TARGET_DEFAULT. */
9441 if (strcasecmp (cpu_string, "from-abi") == 0)
9442 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9443 : ABI_NEEDS_64BIT_REGS ? 3
9444 : (TARGET_64BIT ? 3 : 1));
9446 /* 'default' has traditionally been a no-op. Probably not very useful. */
9447 if (strcasecmp (cpu_string, "default") == 0)
9450 for (p = mips_cpu_info_table; p->name != 0; p++)
9451 if (mips_matching_cpu_name_p (p->name, cpu_string))
9458 /* Return the processor associated with the given ISA level, or null
9459 if the ISA isn't valid. */
9461 static const struct mips_cpu_info *
9462 mips_cpu_info_from_isa (int isa)
9464 const struct mips_cpu_info *p;
9466 for (p = mips_cpu_info_table; p->name != 0; p++)
9473 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9474 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9475 they only hold condition code modes, and CCmode is always considered to
9476 be 4 bytes wide. All other registers are word sized. */
9479 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9481 if (ST_REG_P (regno))
9482 return ((GET_MODE_SIZE (mode) + 3) / 4);
9483 else if (! FP_REG_P (regno))
9484 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9486 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9489 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9490 all BLKmode objects are returned in memory. Under the new (N32 and
9491 64-bit MIPS ABIs) small structures are returned in a register.
9492 Objects with varying size must still be returned in memory, of
9496 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9499 return (TYPE_MODE (type) == BLKmode);
9501 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9502 || (int_size_in_bytes (type) == -1));
9506 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9508 return !TARGET_OLDABI;
9511 /* Return true if INSN is a multiply-add or multiply-subtract
9512 instruction and PREV assigns to the accumulator operand. */
9515 mips_linked_madd_p (rtx prev, rtx insn)
9519 x = single_set (insn);
9525 if (GET_CODE (x) == PLUS
9526 && GET_CODE (XEXP (x, 0)) == MULT
9527 && reg_set_p (XEXP (x, 1), prev))
9530 if (GET_CODE (x) == MINUS
9531 && GET_CODE (XEXP (x, 1)) == MULT
9532 && reg_set_p (XEXP (x, 0), prev))
9538 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9539 that may clobber hi or lo. */
9541 static rtx mips_macc_chains_last_hilo;
9543 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9544 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9547 mips_macc_chains_record (rtx insn)
9549 if (get_attr_may_clobber_hilo (insn))
9550 mips_macc_chains_last_hilo = insn;
9553 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9554 has NREADY elements, looking for a multiply-add or multiply-subtract
9555 instruction that is cumulative with mips_macc_chains_last_hilo.
9556 If there is one, promote it ahead of anything else that might
9557 clobber hi or lo. */
9560 mips_macc_chains_reorder (rtx *ready, int nready)
9564 if (mips_macc_chains_last_hilo != 0)
9565 for (i = nready - 1; i >= 0; i--)
9566 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9568 for (j = nready - 1; j > i; j--)
9569 if (recog_memoized (ready[j]) >= 0
9570 && get_attr_may_clobber_hilo (ready[j]))
9572 mips_promote_ready (ready, i, j);
9579 /* The last instruction to be scheduled. */
9581 static rtx vr4130_last_insn;
9583 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9584 points to an rtx that is initially an instruction. Nullify the rtx
9585 if the instruction uses the value of register X. */
9588 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9590 rtx *insn_ptr = data;
9593 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9597 /* Return true if there is true register dependence between vr4130_last_insn
9601 vr4130_true_reg_dependence_p (rtx insn)
9603 note_stores (PATTERN (vr4130_last_insn),
9604 vr4130_true_reg_dependence_p_1, &insn);
9608 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9609 the ready queue and that INSN2 is the instruction after it, return
9610 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9611 in which INSN1 and INSN2 can probably issue in parallel, but for
9612 which (INSN2, INSN1) should be less sensitive to instruction
9613 alignment than (INSN1, INSN2). See 4130.md for more details. */
9616 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9620 /* Check for the following case:
9622 1) there is some other instruction X with an anti dependence on INSN1;
9623 2) X has a higher priority than INSN2; and
9624 3) X is an arithmetic instruction (and thus has no unit restrictions).
9626 If INSN1 is the last instruction blocking X, it would better to
9627 choose (INSN1, X) over (INSN2, INSN1). */
9628 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9629 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9630 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9631 && recog_memoized (XEXP (dep, 0)) >= 0
9632 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9635 if (vr4130_last_insn != 0
9636 && recog_memoized (insn1) >= 0
9637 && recog_memoized (insn2) >= 0)
9639 /* See whether INSN1 and INSN2 use different execution units,
9640 or if they are both ALU-type instructions. If so, they can
9641 probably execute in parallel. */
9642 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9643 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9644 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9646 /* If only one of the instructions has a dependence on
9647 vr4130_last_insn, prefer to schedule the other one first. */
9648 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9649 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9653 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9654 is not an ALU-type instruction and if INSN1 uses the same
9655 execution unit. (Note that if this condition holds, we already
9656 know that INSN2 uses a different execution unit.) */
9657 if (class1 != VR4130_CLASS_ALU
9658 && recog_memoized (vr4130_last_insn) >= 0
9659 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9666 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9667 queue with at least two instructions. Swap the first two if
9668 vr4130_swap_insns_p says that it could be worthwhile. */
9671 vr4130_reorder (rtx *ready, int nready)
9673 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9674 mips_promote_ready (ready, nready - 2, nready - 1);
9677 /* Remove the instruction at index LOWER from ready queue READY and
9678 reinsert it in front of the instruction at index HIGHER. LOWER must
9682 mips_promote_ready (rtx *ready, int lower, int higher)
9687 new_head = ready[lower];
9688 for (i = lower; i < higher; i++)
9689 ready[i] = ready[i + 1];
9690 ready[i] = new_head;
9693 /* Implement TARGET_SCHED_REORDER. */
9696 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9697 rtx *ready, int *nreadyp, int cycle)
9699 if (!reload_completed && TUNE_MACC_CHAINS)
9702 mips_macc_chains_last_hilo = 0;
9704 mips_macc_chains_reorder (ready, *nreadyp);
9706 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9709 vr4130_last_insn = 0;
9711 vr4130_reorder (ready, *nreadyp);
9713 return mips_issue_rate ();
9716 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9719 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9722 switch (GET_CODE (PATTERN (insn)))
9726 /* Don't count USEs and CLOBBERs against the issue rate. */
9731 if (!reload_completed && TUNE_MACC_CHAINS)
9732 mips_macc_chains_record (insn);
9733 vr4130_last_insn = insn;
9739 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9740 dependencies have no cost. */
9743 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9744 rtx dep ATTRIBUTE_UNUSED, int cost)
9746 if (REG_NOTE_KIND (link) != 0)
9751 /* Return the number of instructions that can be issued per cycle. */
9754 mips_issue_rate (void)
9758 case PROCESSOR_R4130:
9759 case PROCESSOR_R5400:
9760 case PROCESSOR_R5500:
9761 case PROCESSOR_R7000:
9762 case PROCESSOR_R9000:
9766 /* This is actually 4, but we get better performance if we claim 3.
9767 This is partly because of unwanted speculative code motion with the
9768 larger number, and partly because in most common cases we can't
9769 reach the theoretical max of 4. */
9777 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9778 be as wide as the scheduling freedom in the DFA. */
9781 mips_multipass_dfa_lookahead (void)
9783 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9784 if (mips_tune == PROCESSOR_SB1)
9790 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9791 return the first operand of the associated "pref" or "prefx" insn. */
9794 mips_prefetch_cookie (rtx write, rtx locality)
9796 /* store_streamed / load_streamed. */
9797 if (INTVAL (locality) <= 0)
9798 return GEN_INT (INTVAL (write) + 4);
9801 if (INTVAL (locality) <= 2)
9804 /* store_retained / load_retained. */
9805 return GEN_INT (INTVAL (write) + 6);
9808 /* MIPS builtin function support. */
9810 struct builtin_description
9812 /* The code of the main .md file instruction. See mips_builtin_type
9813 for more information. */
9814 enum insn_code icode;
9816 /* The floating-point comparison code to use with ICODE, if any. */
9817 enum mips_fp_condition cond;
9819 /* The name of the builtin function. */
9822 /* Specifies how the function should be expanded. */
9823 enum mips_builtin_type builtin_type;
9825 /* The function's prototype. */
9826 enum mips_function_type function_type;
9828 /* The target flags required for this function. */
9832 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9833 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9834 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9835 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9836 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9838 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9840 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9841 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9842 "__builtin_mips_" #INSN "_" #COND "_s", \
9843 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9844 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9845 "__builtin_mips_" #INSN "_" #COND "_d", \
9846 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9848 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9849 The lower and upper forms require TARGET_FLAGS while the any and all
9850 forms require MASK_MIPS3D. */
9851 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9852 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9853 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9854 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9855 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9856 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9857 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9858 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9859 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9860 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9861 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9862 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9863 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9865 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9866 require MASK_MIPS3D. */
9867 #define CMP_4S_BUILTINS(INSN, COND) \
9868 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9869 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9870 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9872 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9873 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9874 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9877 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9878 instruction requires TARGET_FLAGS. */
9879 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9880 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9881 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9882 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9884 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9885 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9886 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9889 /* Define all the builtins related to c.cond.fmt condition COND. */
9890 #define CMP_BUILTINS(COND) \
9891 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9892 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9893 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9894 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9895 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9896 CMP_4S_BUILTINS (c, COND), \
9897 CMP_4S_BUILTINS (cabs, COND)
9899 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
9900 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
9902 static const struct builtin_description mips_bdesc[] =
9904 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9905 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9906 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9907 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9908 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
9909 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9910 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9911 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9913 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
9914 MASK_PAIRED_SINGLE_FLOAT),
9915 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9916 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9917 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9918 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9920 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9921 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9922 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9923 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9924 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9925 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9927 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9928 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9929 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9930 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9931 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9932 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9934 MIPS_FP_CONDITIONS (CMP_BUILTINS)
9937 /* Builtin functions for the SB-1 processor. */
9939 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
9941 static const struct builtin_description sb1_bdesc[] =
9943 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
9946 /* Builtin functions for DSP ASE. */
9948 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
9949 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
9950 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
9951 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
9953 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
9954 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
9955 builtin_description fields. */
9956 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9957 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9958 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
9960 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
9961 branch instruction. TARGET_FLAGS is a builtin_description field. */
9962 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
9963 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
9964 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
9966 static const struct builtin_description dsp_bdesc[] =
9968 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9969 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9970 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9971 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9972 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9973 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9974 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9975 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9976 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9977 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9978 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9979 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9980 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9981 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
9982 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
9983 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
9984 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
9985 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
9986 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
9987 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
9988 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
9989 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
9990 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9991 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9992 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9993 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9994 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9995 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9996 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9997 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9998 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
9999 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10000 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10001 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10002 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10003 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10004 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10005 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10006 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10007 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10008 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10009 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10010 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10011 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10012 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10013 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10014 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10015 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10016 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10017 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10018 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10019 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10020 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10021 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10022 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10023 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10024 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10025 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10026 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10027 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10028 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10029 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10030 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10031 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10032 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10033 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10034 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10035 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10036 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10037 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10038 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10039 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10040 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10041 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10042 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10043 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10044 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10045 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10046 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10047 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10048 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10049 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10050 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10051 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10052 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10053 BPOSGE_BUILTIN (32, MASK_DSP)
10056 /* This helps provide a mapping from builtin function codes to bdesc
10061 /* The builtin function table that this entry describes. */
10062 const struct builtin_description *bdesc;
10064 /* The number of entries in the builtin function table. */
10067 /* The target processor that supports these builtin functions.
10068 PROCESSOR_MAX means we enable them for all processors. */
10069 enum processor_type proc;
10072 static const struct bdesc_map bdesc_arrays[] =
10074 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10075 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10076 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10079 /* Take the head of argument list *ARGLIST and convert it into a form
10080 suitable for input operand OP of instruction ICODE. Return the value
10081 and point *ARGLIST at the next element of the list. */
10084 mips_prepare_builtin_arg (enum insn_code icode,
10085 unsigned int op, tree *arglist)
10088 enum machine_mode mode;
10090 value = expand_normal (TREE_VALUE (*arglist));
10091 mode = insn_data[icode].operand[op].mode;
10092 if (!insn_data[icode].operand[op].predicate (value, mode))
10094 value = copy_to_mode_reg (mode, value);
10095 /* Check the predicate again. */
10096 if (!insn_data[icode].operand[op].predicate (value, mode))
10098 error ("invalid argument to builtin function");
10103 *arglist = TREE_CHAIN (*arglist);
10107 /* Return an rtx suitable for output operand OP of instruction ICODE.
10108 If TARGET is non-null, try to use it where possible. */
10111 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10113 enum machine_mode mode;
10115 mode = insn_data[icode].operand[op].mode;
10116 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10117 target = gen_reg_rtx (mode);
10122 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10125 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10126 enum machine_mode mode ATTRIBUTE_UNUSED,
10127 int ignore ATTRIBUTE_UNUSED)
10129 enum insn_code icode;
10130 enum mips_builtin_type type;
10131 tree fndecl, arglist;
10132 unsigned int fcode;
10133 const struct builtin_description *bdesc;
10134 const struct bdesc_map *m;
10136 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10137 arglist = TREE_OPERAND (exp, 1);
10138 fcode = DECL_FUNCTION_CODE (fndecl);
10141 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10143 if (fcode < m->size)
10146 icode = bdesc[fcode].icode;
10147 type = bdesc[fcode].builtin_type;
10157 case MIPS_BUILTIN_DIRECT:
10158 return mips_expand_builtin_direct (icode, target, arglist, true);
10160 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10161 return mips_expand_builtin_direct (icode, target, arglist, false);
10163 case MIPS_BUILTIN_MOVT:
10164 case MIPS_BUILTIN_MOVF:
10165 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10168 case MIPS_BUILTIN_CMP_ANY:
10169 case MIPS_BUILTIN_CMP_ALL:
10170 case MIPS_BUILTIN_CMP_UPPER:
10171 case MIPS_BUILTIN_CMP_LOWER:
10172 case MIPS_BUILTIN_CMP_SINGLE:
10173 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10176 case MIPS_BUILTIN_BPOSGE32:
10177 return mips_expand_builtin_bposge (type, target);
10184 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10187 mips_init_builtins (void)
10189 const struct builtin_description *d;
10190 const struct bdesc_map *m;
10191 tree types[(int) MIPS_MAX_FTYPE_MAX];
10192 tree V2SF_type_node;
10193 tree V2HI_type_node;
10194 tree V4QI_type_node;
10195 unsigned int offset;
10197 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10198 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10201 if (TARGET_PAIRED_SINGLE_FLOAT)
10203 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10205 types[MIPS_V2SF_FTYPE_V2SF]
10206 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10208 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10209 = build_function_type_list (V2SF_type_node,
10210 V2SF_type_node, V2SF_type_node, NULL_TREE);
10212 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10213 = build_function_type_list (V2SF_type_node,
10214 V2SF_type_node, V2SF_type_node,
10215 integer_type_node, NULL_TREE);
10217 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10218 = build_function_type_list (V2SF_type_node,
10219 V2SF_type_node, V2SF_type_node,
10220 V2SF_type_node, V2SF_type_node, NULL_TREE);
10222 types[MIPS_V2SF_FTYPE_SF_SF]
10223 = build_function_type_list (V2SF_type_node,
10224 float_type_node, float_type_node, NULL_TREE);
10226 types[MIPS_INT_FTYPE_V2SF_V2SF]
10227 = build_function_type_list (integer_type_node,
10228 V2SF_type_node, V2SF_type_node, NULL_TREE);
10230 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10231 = build_function_type_list (integer_type_node,
10232 V2SF_type_node, V2SF_type_node,
10233 V2SF_type_node, V2SF_type_node, NULL_TREE);
10235 types[MIPS_INT_FTYPE_SF_SF]
10236 = build_function_type_list (integer_type_node,
10237 float_type_node, float_type_node, NULL_TREE);
10239 types[MIPS_INT_FTYPE_DF_DF]
10240 = build_function_type_list (integer_type_node,
10241 double_type_node, double_type_node, NULL_TREE);
10243 types[MIPS_SF_FTYPE_V2SF]
10244 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10246 types[MIPS_SF_FTYPE_SF]
10247 = build_function_type_list (float_type_node,
10248 float_type_node, NULL_TREE);
10250 types[MIPS_SF_FTYPE_SF_SF]
10251 = build_function_type_list (float_type_node,
10252 float_type_node, float_type_node, NULL_TREE);
10254 types[MIPS_DF_FTYPE_DF]
10255 = build_function_type_list (double_type_node,
10256 double_type_node, NULL_TREE);
10258 types[MIPS_DF_FTYPE_DF_DF]
10259 = build_function_type_list (double_type_node,
10260 double_type_node, double_type_node, NULL_TREE);
10265 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10266 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10268 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10269 = build_function_type_list (V2HI_type_node,
10270 V2HI_type_node, V2HI_type_node,
10273 types[MIPS_SI_FTYPE_SI_SI]
10274 = build_function_type_list (intSI_type_node,
10275 intSI_type_node, intSI_type_node,
10278 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10279 = build_function_type_list (V4QI_type_node,
10280 V4QI_type_node, V4QI_type_node,
10283 types[MIPS_SI_FTYPE_V4QI]
10284 = build_function_type_list (intSI_type_node,
10288 types[MIPS_V2HI_FTYPE_V2HI]
10289 = build_function_type_list (V2HI_type_node,
10293 types[MIPS_SI_FTYPE_SI]
10294 = build_function_type_list (intSI_type_node,
10298 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10299 = build_function_type_list (V4QI_type_node,
10300 V2HI_type_node, V2HI_type_node,
10303 types[MIPS_V2HI_FTYPE_SI_SI]
10304 = build_function_type_list (V2HI_type_node,
10305 intSI_type_node, intSI_type_node,
10308 types[MIPS_SI_FTYPE_V2HI]
10309 = build_function_type_list (intSI_type_node,
10313 types[MIPS_V2HI_FTYPE_V4QI]
10314 = build_function_type_list (V2HI_type_node,
10318 types[MIPS_V4QI_FTYPE_V4QI_SI]
10319 = build_function_type_list (V4QI_type_node,
10320 V4QI_type_node, intSI_type_node,
10323 types[MIPS_V2HI_FTYPE_V2HI_SI]
10324 = build_function_type_list (V2HI_type_node,
10325 V2HI_type_node, intSI_type_node,
10328 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10329 = build_function_type_list (V2HI_type_node,
10330 V4QI_type_node, V2HI_type_node,
10333 types[MIPS_SI_FTYPE_V2HI_V2HI]
10334 = build_function_type_list (intSI_type_node,
10335 V2HI_type_node, V2HI_type_node,
10338 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10339 = build_function_type_list (intDI_type_node,
10340 intDI_type_node, V4QI_type_node, V4QI_type_node,
10343 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10344 = build_function_type_list (intDI_type_node,
10345 intDI_type_node, V2HI_type_node, V2HI_type_node,
10348 types[MIPS_DI_FTYPE_DI_SI_SI]
10349 = build_function_type_list (intDI_type_node,
10350 intDI_type_node, intSI_type_node, intSI_type_node,
10353 types[MIPS_V4QI_FTYPE_SI]
10354 = build_function_type_list (V4QI_type_node,
10358 types[MIPS_V2HI_FTYPE_SI]
10359 = build_function_type_list (V2HI_type_node,
10363 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10364 = build_function_type_list (void_type_node,
10365 V4QI_type_node, V4QI_type_node,
10368 types[MIPS_SI_FTYPE_V4QI_V4QI]
10369 = build_function_type_list (intSI_type_node,
10370 V4QI_type_node, V4QI_type_node,
10373 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10374 = build_function_type_list (void_type_node,
10375 V2HI_type_node, V2HI_type_node,
10378 types[MIPS_SI_FTYPE_DI_SI]
10379 = build_function_type_list (intSI_type_node,
10380 intDI_type_node, intSI_type_node,
10383 types[MIPS_DI_FTYPE_DI_SI]
10384 = build_function_type_list (intDI_type_node,
10385 intDI_type_node, intSI_type_node,
10388 types[MIPS_VOID_FTYPE_SI_SI]
10389 = build_function_type_list (void_type_node,
10390 intSI_type_node, intSI_type_node,
10393 types[MIPS_SI_FTYPE_PTR_SI]
10394 = build_function_type_list (intSI_type_node,
10395 ptr_type_node, intSI_type_node,
10398 types[MIPS_SI_FTYPE_VOID]
10399 = build_function_type (intSI_type_node, void_list_node);
10402 /* Iterate through all of the bdesc arrays, initializing all of the
10403 builtin functions. */
10406 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10408 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10409 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10410 if ((d->target_flags & target_flags) == d->target_flags)
10411 lang_hooks.builtin_function (d->name, types[d->function_type],
10412 d - m->bdesc + offset,
10413 BUILT_IN_MD, NULL, NULL);
10418 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10419 .md pattern and ARGLIST is the list of function arguments. TARGET,
10420 if nonnull, suggests a good place to put the result.
10421 HAS_TARGET indicates the function must return something. */
10424 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10427 rtx ops[MAX_RECOG_OPERANDS];
10432 /* We save target to ops[0]. */
10433 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10437 /* We need to test if arglist is not zero. Some instructions have extra
10438 clobber registers. */
10439 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10440 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10445 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10449 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10453 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10457 gcc_unreachable ();
10462 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10463 function (TYPE says which). ARGLIST is the list of arguments to the
10464 function, ICODE is the instruction that should be used to compare
10465 the first two arguments, and COND is the condition it should test.
10466 TARGET, if nonnull, suggests a good place to put the result. */
10469 mips_expand_builtin_movtf (enum mips_builtin_type type,
10470 enum insn_code icode, enum mips_fp_condition cond,
10471 rtx target, tree arglist)
10473 rtx cmp_result, op0, op1;
10475 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10476 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10477 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10478 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10480 icode = CODE_FOR_mips_cond_move_tf_ps;
10481 target = mips_prepare_builtin_target (icode, 0, target);
10482 if (type == MIPS_BUILTIN_MOVT)
10484 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10485 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10489 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10490 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10492 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10496 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10497 into TARGET otherwise. Return TARGET. */
10500 mips_builtin_branch_and_move (rtx condition, rtx target,
10501 rtx value_if_true, rtx value_if_false)
10503 rtx true_label, done_label;
10505 true_label = gen_label_rtx ();
10506 done_label = gen_label_rtx ();
10508 /* First assume that CONDITION is false. */
10509 emit_move_insn (target, value_if_false);
10511 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10512 emit_jump_insn (gen_condjump (condition, true_label));
10513 emit_jump_insn (gen_jump (done_label));
10516 /* Fix TARGET if CONDITION is true. */
10517 emit_label (true_label);
10518 emit_move_insn (target, value_if_true);
10520 emit_label (done_label);
10524 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10525 of the comparison instruction and COND is the condition it should test.
10526 ARGLIST is the list of function arguments and TARGET, if nonnull,
10527 suggests a good place to put the boolean result. */
10530 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10531 enum insn_code icode, enum mips_fp_condition cond,
10532 rtx target, tree arglist)
10534 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10537 if (target == 0 || GET_MODE (target) != SImode)
10538 target = gen_reg_rtx (SImode);
10540 /* Prepare the operands to the comparison. */
10541 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10542 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10543 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10545 switch (insn_data[icode].n_operands)
10548 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10552 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10553 ops[3], ops[4], GEN_INT (cond)));
10557 gcc_unreachable ();
10560 /* If the comparison sets more than one register, we define the result
10561 to be 0 if all registers are false and -1 if all registers are true.
10562 The value of the complete result is indeterminate otherwise. */
10563 switch (builtin_type)
10565 case MIPS_BUILTIN_CMP_ALL:
10566 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10567 return mips_builtin_branch_and_move (condition, target,
10568 const0_rtx, const1_rtx);
10570 case MIPS_BUILTIN_CMP_UPPER:
10571 case MIPS_BUILTIN_CMP_LOWER:
10572 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10573 condition = gen_single_cc (cmp_result, offset);
10574 return mips_builtin_branch_and_move (condition, target,
10575 const1_rtx, const0_rtx);
10578 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10579 return mips_builtin_branch_and_move (condition, target,
10580 const1_rtx, const0_rtx);
10584 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10585 suggests a good place to put the boolean result. */
10588 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10590 rtx condition, cmp_result;
10593 if (target == 0 || GET_MODE (target) != SImode)
10594 target = gen_reg_rtx (SImode);
10596 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10598 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10603 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10604 return mips_builtin_branch_and_move (condition, target,
10605 const1_rtx, const0_rtx);
10608 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10609 FIRST is true if this is the first time handling this decl. */
10612 mips_encode_section_info (tree decl, rtx rtl, int first)
10614 default_encode_section_info (decl, rtl, first);
10616 if (TREE_CODE (decl) == FUNCTION_DECL
10617 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10619 rtx symbol = XEXP (rtl, 0);
10620 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10624 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. TARGET_ABICALLS makes
10625 PIC_FUNCTION_ADDR_REGNUM live on entry to a function. */
10628 mips_extra_live_on_entry (bitmap regs)
10630 if (!TARGET_ABICALLS)
10631 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10635 #include "gt-mips.h"