1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 #include "diagnostic.h"
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type {
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a builtin function. */
157 enum mips_function_type
159 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
160 #include "config/mips/mips-ftypes.def"
161 #undef DEF_MIPS_FTYPE
165 /* Specifies how a builtin function should be converted into rtl. */
166 enum mips_builtin_type
168 /* The builtin corresponds directly to an .md pattern. The return
169 value is mapped to operand 0 and the arguments are mapped to
170 operands 1 and above. */
173 /* The builtin corresponds directly to an .md pattern. There is no return
174 value and the arguments are mapped to operands 0 and above. */
175 MIPS_BUILTIN_DIRECT_NO_TARGET,
177 /* The builtin corresponds to a comparison instruction followed by
178 a mips_cond_move_tf_ps pattern. The first two arguments are the
179 values to compare and the second two arguments are the vector
180 operands for the movt.ps or movf.ps instruction (in assembly order). */
184 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
185 of this instruction is the result of the comparison, which has mode
186 CCV2 or CCV4. The function arguments are mapped to operands 1 and
187 above. The function's return value is an SImode boolean that is
188 true under the following conditions:
190 MIPS_BUILTIN_CMP_ANY: one of the registers is true
191 MIPS_BUILTIN_CMP_ALL: all of the registers are true
192 MIPS_BUILTIN_CMP_LOWER: the first register is true
193 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
194 MIPS_BUILTIN_CMP_ANY,
195 MIPS_BUILTIN_CMP_ALL,
196 MIPS_BUILTIN_CMP_UPPER,
197 MIPS_BUILTIN_CMP_LOWER,
199 /* As above, but the instruction only sets a single $fcc register. */
200 MIPS_BUILTIN_CMP_SINGLE,
202 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
203 MIPS_BUILTIN_BPOSGE32
206 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
207 #define MIPS_FP_CONDITIONS(MACRO) \
225 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
226 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
227 enum mips_fp_condition {
228 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
231 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
232 #define STRINGIFY(X) #X
233 static const char *const mips_fp_conditions[] = {
234 MIPS_FP_CONDITIONS (STRINGIFY)
237 /* Information about a function's frame layout. */
238 struct mips_frame_info GTY(())
240 /* The size of the frame in bytes. */
241 HOST_WIDE_INT total_size;
243 /* The number of bytes allocated to variables. */
244 HOST_WIDE_INT var_size;
246 /* The number of bytes allocated to outgoing function arguments. */
247 HOST_WIDE_INT args_size;
249 /* The number of bytes allocated to the .cprestore slot, or 0 if there
251 HOST_WIDE_INT cprestore_size;
253 /* Bit X is set if the function saves or restores GPR X. */
256 /* Likewise FPR X. */
259 /* The number of GPRs and FPRs saved. */
263 /* The offset of the topmost GPR and FPR save slots from the top of
264 the frame, or zero if no such slots are needed. */
265 HOST_WIDE_INT gp_save_offset;
266 HOST_WIDE_INT fp_save_offset;
268 /* Likewise, but giving offsets from the bottom of the frame. */
269 HOST_WIDE_INT gp_sp_offset;
270 HOST_WIDE_INT fp_sp_offset;
272 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT arg_pointer_offset;
275 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
276 HOST_WIDE_INT hard_frame_pointer_offset;
279 struct machine_function GTY(()) {
280 /* Pseudo-reg holding the value of $28 in a mips16 function which
281 refers to GP relative global variables. */
282 rtx mips16_gp_pseudo_rtx;
284 /* The number of extra stack bytes taken up by register varargs.
285 This area is allocated by the callee at the very top of the frame. */
288 /* Current frame information, calculated by mips_compute_frame_info. */
289 struct mips_frame_info frame;
291 /* The register to use as the global pointer within this function. */
292 unsigned int global_pointer;
294 /* True if mips_adjust_insn_length should ignore an instruction's
296 bool ignore_hazard_length_p;
298 /* True if the whole function is suitable for .set noreorder and
300 bool all_noreorder_p;
302 /* True if the function is known to have an instruction that needs $gp. */
305 /* True if we have emitted an instruction to initialize
306 mips16_gp_pseudo_rtx. */
307 bool initialized_mips16_gp_pseudo_p;
310 /* Information about a single argument. */
313 /* True if the argument is passed in a floating-point register, or
314 would have been if we hadn't run out of registers. */
317 /* The number of words passed in registers, rounded up. */
318 unsigned int reg_words;
320 /* For EABI, the offset of the first register from GP_ARG_FIRST or
321 FP_ARG_FIRST. For other ABIs, the offset of the first register from
322 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
323 comment for details).
325 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
327 unsigned int reg_offset;
329 /* The number of words that must be passed on the stack, rounded up. */
330 unsigned int stack_words;
332 /* The offset from the start of the stack overflow area of the argument's
333 first stack word. Only meaningful when STACK_WORDS is nonzero. */
334 unsigned int stack_offset;
338 /* Information about an address described by mips_address_type.
344 REG is the base register and OFFSET is the constant offset.
347 REG is the register that contains the high part of the address,
348 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
349 is the type of OFFSET's symbol.
352 SYMBOL_TYPE is the type of symbol being referenced. */
354 struct mips_address_info
356 enum mips_address_type type;
359 enum mips_symbol_type symbol_type;
363 /* One stage in a constant building sequence. These sequences have
367 A = A CODE[1] VALUE[1]
368 A = A CODE[2] VALUE[2]
371 where A is an accumulator, each CODE[i] is a binary rtl operation
372 and each VALUE[i] is a constant integer. */
373 struct mips_integer_op {
375 unsigned HOST_WIDE_INT value;
379 /* The largest number of operations needed to load an integer constant.
380 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
381 When the lowest bit is clear, we can try, but reject a sequence with
382 an extra SLL at the end. */
383 #define MIPS_MAX_INTEGER_OPS 7
385 /* Information about a MIPS16e SAVE or RESTORE instruction. */
386 struct mips16e_save_restore_info {
387 /* The number of argument registers saved by a SAVE instruction.
388 0 for RESTORE instructions. */
391 /* Bit X is set if the instruction saves or restores GPR X. */
394 /* The total number of bytes to allocate. */
398 /* Global variables for machine-dependent things. */
400 /* Threshold for data being put into the small data/bss area, instead
401 of the normal data area. */
402 int mips_section_threshold = -1;
404 /* Count the number of .file directives, so that .loc is up to date. */
405 int num_source_filenames = 0;
407 /* Name of the file containing the current function. */
408 const char *current_function_file = "";
410 /* Count the number of sdb related labels are generated (to find block
411 start and end boundaries). */
412 int sdb_label_count = 0;
414 /* Next label # for each statement for Silicon Graphics IRIS systems. */
417 /* Map GCC register number to debugger register number. */
418 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
419 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
421 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
426 /* The next branch instruction is a branch likely, not branch normal. */
427 int mips_branch_likely;
429 /* The operands passed to the last cmpMM expander. */
432 /* The target cpu for code generation. */
433 enum processor_type mips_arch;
434 const struct mips_cpu_info *mips_arch_info;
436 /* The target cpu for optimization and scheduling. */
437 enum processor_type mips_tune;
438 const struct mips_cpu_info *mips_tune_info;
440 /* Which instruction set architecture to use. */
443 /* The architecture selected by -mipsN. */
444 static const struct mips_cpu_info *mips_isa_info;
446 /* Which ABI to use. */
447 int mips_abi = MIPS_ABI_DEFAULT;
449 /* Cost information to use. */
450 const struct mips_rtx_cost_data *mips_cost;
452 /* Remember the ambient target flags, excluding mips16. */
453 static int mips_base_target_flags;
454 /* The mips16 command-line target flags only. */
455 static bool mips_base_mips16;
456 /* Similar copies of option settings. */
457 static int mips_flag_delayed_branch; /* flag_delayed_branch */
458 static int mips_base_schedule_insns; /* flag_schedule_insns */
459 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
460 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
461 static int mips_base_align_loops; /* align_loops */
462 static int mips_base_align_jumps; /* align_jumps */
463 static int mips_base_align_functions; /* align_functions */
465 /* The -mtext-loads setting. */
466 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
468 /* If TRUE, we split addresses into their high and low parts in the RTL. */
469 int mips_split_addresses;
471 /* Array giving truth value on whether or not a given hard register
472 can support a given mode. */
473 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
475 /* List of all MIPS punctuation characters used by print_operand. */
476 char mips_print_operand_punct[256];
478 static GTY (()) int mips_output_filename_first_time = 1;
480 /* mips_split_p[X] is true if symbols of type X can be split by
481 mips_split_symbol(). */
482 bool mips_split_p[NUM_SYMBOL_TYPES];
484 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
485 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
486 if they are matched by a special .md file pattern. */
487 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
489 /* Likewise for HIGHs. */
490 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
492 /* Map hard register number to register class */
493 const enum reg_class mips_regno_to_class[] =
495 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
496 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
497 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
498 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
499 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
500 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
501 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
502 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
503 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
504 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
505 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
506 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
507 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
508 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
509 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
510 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
511 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
512 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
513 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
514 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
515 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
516 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
517 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
518 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
519 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
520 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
521 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
522 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
523 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
524 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
525 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
526 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
527 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
528 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
529 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
530 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
531 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
532 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
533 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
534 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
535 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
536 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
537 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
538 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
539 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
540 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
541 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
544 /* Table of machine dependent attributes. */
545 const struct attribute_spec mips_attribute_table[] =
547 { "long_call", 0, 0, false, true, true, NULL },
548 { "far", 0, 0, false, true, true, NULL },
549 { "near", 0, 0, false, true, true, NULL },
550 /* Switch MIPS16 ASE on and off per-function. We would really like
551 to make these type attributes, but GCC doesn't provide the hooks
552 we need to support the right conversion rules. As declaration
553 attributes, they affect code generation but don't carry other
555 { "mips16", 0, 0, true, false, false, NULL },
556 { "nomips16", 0, 0, true, false, false, NULL },
557 { NULL, 0, 0, false, false, false, NULL }
560 /* A table describing all the processors gcc knows about. Names are
561 matched in the order listed. The first mention of an ISA level is
562 taken as the canonical name for that ISA.
564 To ease comparison, please keep this table in the same order
565 as gas's mips_cpu_info_table[]. Please also make sure that
566 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
567 options correctly. */
568 const struct mips_cpu_info mips_cpu_info_table[] = {
569 /* Entries for generic ISAs */
570 { "mips1", PROCESSOR_R3000, 1, 0 },
571 { "mips2", PROCESSOR_R6000, 2, 0 },
572 { "mips3", PROCESSOR_R4000, 3, 0 },
573 { "mips4", PROCESSOR_R8000, 4, 0 },
574 /* Prefer not to use branch-likely instructions for generic MIPS32rX
575 and MIPS64rX code. The instructions were officially deprecated
576 in revisions 2 and earlier, but revision 3 is likely to downgrade
577 that to a recommendation to avoid the instructions in code that
578 isn't tuned to a specific processor. */
579 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
580 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
581 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
584 { "r3000", PROCESSOR_R3000, 1, 0 },
585 { "r2000", PROCESSOR_R3000, 1, 0 }, /* = r3000 */
586 { "r3900", PROCESSOR_R3900, 1, 0 },
589 { "r6000", PROCESSOR_R6000, 2, 0 },
592 { "r4000", PROCESSOR_R4000, 3, 0 },
593 { "vr4100", PROCESSOR_R4100, 3, 0 },
594 { "vr4111", PROCESSOR_R4111, 3, 0 },
595 { "vr4120", PROCESSOR_R4120, 3, 0 },
596 { "vr4130", PROCESSOR_R4130, 3, 0 },
597 { "vr4300", PROCESSOR_R4300, 3, 0 },
598 { "r4400", PROCESSOR_R4000, 3, 0 }, /* = r4000 */
599 { "r4600", PROCESSOR_R4600, 3, 0 },
600 { "orion", PROCESSOR_R4600, 3, 0 }, /* = r4600 */
601 { "r4650", PROCESSOR_R4650, 3, 0 },
604 { "r8000", PROCESSOR_R8000, 4, 0 },
605 { "vr5000", PROCESSOR_R5000, 4, 0 },
606 { "vr5400", PROCESSOR_R5400, 4, 0 },
607 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
608 { "rm7000", PROCESSOR_R7000, 4, 0 },
609 { "rm9000", PROCESSOR_R9000, 4, 0 },
612 { "4kc", PROCESSOR_4KC, 32, 0 },
613 { "4km", PROCESSOR_4KC, 32, 0 }, /* = 4kc */
614 { "4kp", PROCESSOR_4KP, 32, 0 },
615 { "4ksc", PROCESSOR_4KC, 32, 0 },
617 /* MIPS32 Release 2 */
618 { "m4k", PROCESSOR_M4K, 33, 0 },
619 { "4kec", PROCESSOR_4KC, 33, 0 },
620 { "4kem", PROCESSOR_4KC, 33, 0 },
621 { "4kep", PROCESSOR_4KP, 33, 0 },
622 { "4ksd", PROCESSOR_4KC, 33, 0 },
624 { "24kc", PROCESSOR_24KC, 33, 0 },
625 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
626 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
627 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
628 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
629 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
631 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP */
632 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
633 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
634 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
635 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
636 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
638 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP */
639 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
640 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
641 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
642 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
643 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
645 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2 */
646 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
647 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
648 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
649 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
650 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
651 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
654 { "5kc", PROCESSOR_5KC, 64, 0 },
655 { "5kf", PROCESSOR_5KF, 64, 0 },
656 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
657 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
658 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
659 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
662 /* Default costs. If these are used for a processor we should look
663 up the actual costs. */
664 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
665 COSTS_N_INSNS (7), /* fp_mult_sf */ \
666 COSTS_N_INSNS (8), /* fp_mult_df */ \
667 COSTS_N_INSNS (23), /* fp_div_sf */ \
668 COSTS_N_INSNS (36), /* fp_div_df */ \
669 COSTS_N_INSNS (10), /* int_mult_si */ \
670 COSTS_N_INSNS (10), /* int_mult_di */ \
671 COSTS_N_INSNS (69), /* int_div_si */ \
672 COSTS_N_INSNS (69), /* int_div_di */ \
673 2, /* branch_cost */ \
674 4 /* memory_latency */
676 /* Need to replace these with the costs of calling the appropriate
678 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
679 COSTS_N_INSNS (256), /* fp_mult_sf */ \
680 COSTS_N_INSNS (256), /* fp_mult_df */ \
681 COSTS_N_INSNS (256), /* fp_div_sf */ \
682 COSTS_N_INSNS (256) /* fp_div_df */
684 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
686 COSTS_N_INSNS (1), /* fp_add */
687 COSTS_N_INSNS (1), /* fp_mult_sf */
688 COSTS_N_INSNS (1), /* fp_mult_df */
689 COSTS_N_INSNS (1), /* fp_div_sf */
690 COSTS_N_INSNS (1), /* fp_div_df */
691 COSTS_N_INSNS (1), /* int_mult_si */
692 COSTS_N_INSNS (1), /* int_mult_di */
693 COSTS_N_INSNS (1), /* int_div_si */
694 COSTS_N_INSNS (1), /* int_div_di */
696 4 /* memory_latency */
699 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
702 COSTS_N_INSNS (2), /* fp_add */
703 COSTS_N_INSNS (4), /* fp_mult_sf */
704 COSTS_N_INSNS (5), /* fp_mult_df */
705 COSTS_N_INSNS (12), /* fp_div_sf */
706 COSTS_N_INSNS (19), /* fp_div_df */
707 COSTS_N_INSNS (12), /* int_mult_si */
708 COSTS_N_INSNS (12), /* int_mult_di */
709 COSTS_N_INSNS (35), /* int_div_si */
710 COSTS_N_INSNS (35), /* int_div_di */
712 4 /* memory_latency */
717 COSTS_N_INSNS (6), /* int_mult_si */
718 COSTS_N_INSNS (6), /* int_mult_di */
719 COSTS_N_INSNS (36), /* int_div_si */
720 COSTS_N_INSNS (36), /* int_div_di */
722 4 /* memory_latency */
726 COSTS_N_INSNS (36), /* int_mult_si */
727 COSTS_N_INSNS (36), /* int_mult_di */
728 COSTS_N_INSNS (37), /* int_div_si */
729 COSTS_N_INSNS (37), /* int_div_di */
731 4 /* memory_latency */
735 COSTS_N_INSNS (4), /* int_mult_si */
736 COSTS_N_INSNS (11), /* int_mult_di */
737 COSTS_N_INSNS (36), /* int_div_si */
738 COSTS_N_INSNS (68), /* int_div_di */
740 4 /* memory_latency */
743 COSTS_N_INSNS (4), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (17), /* fp_div_sf */
747 COSTS_N_INSNS (32), /* fp_div_df */
748 COSTS_N_INSNS (4), /* int_mult_si */
749 COSTS_N_INSNS (11), /* int_mult_di */
750 COSTS_N_INSNS (36), /* int_div_si */
751 COSTS_N_INSNS (68), /* int_div_di */
753 4 /* memory_latency */
756 COSTS_N_INSNS (4), /* fp_add */
757 COSTS_N_INSNS (4), /* fp_mult_sf */
758 COSTS_N_INSNS (5), /* fp_mult_df */
759 COSTS_N_INSNS (17), /* fp_div_sf */
760 COSTS_N_INSNS (32), /* fp_div_df */
761 COSTS_N_INSNS (4), /* int_mult_si */
762 COSTS_N_INSNS (7), /* int_mult_di */
763 COSTS_N_INSNS (42), /* int_div_si */
764 COSTS_N_INSNS (72), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (5), /* int_mult_si */
771 COSTS_N_INSNS (5), /* int_mult_di */
772 COSTS_N_INSNS (41), /* int_div_si */
773 COSTS_N_INSNS (41), /* int_div_di */
775 4 /* memory_latency */
778 COSTS_N_INSNS (8), /* fp_add */
779 COSTS_N_INSNS (8), /* fp_mult_sf */
780 COSTS_N_INSNS (10), /* fp_mult_df */
781 COSTS_N_INSNS (34), /* fp_div_sf */
782 COSTS_N_INSNS (64), /* fp_div_df */
783 COSTS_N_INSNS (5), /* int_mult_si */
784 COSTS_N_INSNS (5), /* int_mult_di */
785 COSTS_N_INSNS (41), /* int_div_si */
786 COSTS_N_INSNS (41), /* int_div_di */
788 4 /* memory_latency */
791 COSTS_N_INSNS (4), /* fp_add */
792 COSTS_N_INSNS (4), /* fp_mult_sf */
793 COSTS_N_INSNS (5), /* fp_mult_df */
794 COSTS_N_INSNS (17), /* fp_div_sf */
795 COSTS_N_INSNS (32), /* fp_div_df */
796 COSTS_N_INSNS (5), /* int_mult_si */
797 COSTS_N_INSNS (5), /* int_mult_di */
798 COSTS_N_INSNS (41), /* int_div_si */
799 COSTS_N_INSNS (41), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
810 4 /* memory_latency */
813 COSTS_N_INSNS (8), /* fp_add */
814 COSTS_N_INSNS (8), /* fp_mult_sf */
815 COSTS_N_INSNS (10), /* fp_mult_df */
816 COSTS_N_INSNS (34), /* fp_div_sf */
817 COSTS_N_INSNS (64), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (17), /* fp_div_sf */
830 COSTS_N_INSNS (32), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
839 COSTS_N_INSNS (6), /* fp_add */
840 COSTS_N_INSNS (6), /* fp_mult_sf */
841 COSTS_N_INSNS (7), /* fp_mult_df */
842 COSTS_N_INSNS (25), /* fp_div_sf */
843 COSTS_N_INSNS (48), /* fp_div_df */
844 COSTS_N_INSNS (5), /* int_mult_si */
845 COSTS_N_INSNS (5), /* int_mult_di */
846 COSTS_N_INSNS (41), /* int_div_si */
847 COSTS_N_INSNS (41), /* int_div_di */
849 4 /* memory_latency */
855 COSTS_N_INSNS (2), /* fp_add */
856 COSTS_N_INSNS (4), /* fp_mult_sf */
857 COSTS_N_INSNS (5), /* fp_mult_df */
858 COSTS_N_INSNS (12), /* fp_div_sf */
859 COSTS_N_INSNS (19), /* fp_div_df */
860 COSTS_N_INSNS (2), /* int_mult_si */
861 COSTS_N_INSNS (2), /* int_mult_di */
862 COSTS_N_INSNS (35), /* int_div_si */
863 COSTS_N_INSNS (35), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (3), /* fp_add */
869 COSTS_N_INSNS (5), /* fp_mult_sf */
870 COSTS_N_INSNS (6), /* fp_mult_df */
871 COSTS_N_INSNS (15), /* fp_div_sf */
872 COSTS_N_INSNS (16), /* fp_div_df */
873 COSTS_N_INSNS (17), /* int_mult_si */
874 COSTS_N_INSNS (17), /* int_mult_di */
875 COSTS_N_INSNS (38), /* int_div_si */
876 COSTS_N_INSNS (38), /* int_div_di */
878 6 /* memory_latency */
881 COSTS_N_INSNS (6), /* fp_add */
882 COSTS_N_INSNS (7), /* fp_mult_sf */
883 COSTS_N_INSNS (8), /* fp_mult_df */
884 COSTS_N_INSNS (23), /* fp_div_sf */
885 COSTS_N_INSNS (36), /* fp_div_df */
886 COSTS_N_INSNS (10), /* int_mult_si */
887 COSTS_N_INSNS (10), /* int_mult_di */
888 COSTS_N_INSNS (69), /* int_div_si */
889 COSTS_N_INSNS (69), /* int_div_di */
891 6 /* memory_latency */
903 /* The only costs that appear to be updated here are
904 integer multiplication. */
906 COSTS_N_INSNS (4), /* int_mult_si */
907 COSTS_N_INSNS (6), /* int_mult_di */
908 COSTS_N_INSNS (69), /* int_div_si */
909 COSTS_N_INSNS (69), /* int_div_di */
911 4 /* memory_latency */
923 COSTS_N_INSNS (6), /* fp_add */
924 COSTS_N_INSNS (4), /* fp_mult_sf */
925 COSTS_N_INSNS (5), /* fp_mult_df */
926 COSTS_N_INSNS (23), /* fp_div_sf */
927 COSTS_N_INSNS (36), /* fp_div_df */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (36), /* int_div_si */
931 COSTS_N_INSNS (36), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (6), /* fp_add */
937 COSTS_N_INSNS (5), /* fp_mult_sf */
938 COSTS_N_INSNS (6), /* fp_mult_df */
939 COSTS_N_INSNS (30), /* fp_div_sf */
940 COSTS_N_INSNS (59), /* fp_div_df */
941 COSTS_N_INSNS (3), /* int_mult_si */
942 COSTS_N_INSNS (4), /* int_mult_di */
943 COSTS_N_INSNS (42), /* int_div_si */
944 COSTS_N_INSNS (74), /* int_div_di */
946 4 /* memory_latency */
949 COSTS_N_INSNS (6), /* fp_add */
950 COSTS_N_INSNS (5), /* fp_mult_sf */
951 COSTS_N_INSNS (6), /* fp_mult_df */
952 COSTS_N_INSNS (30), /* fp_div_sf */
953 COSTS_N_INSNS (59), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (9), /* int_mult_di */
956 COSTS_N_INSNS (42), /* int_div_si */
957 COSTS_N_INSNS (74), /* int_div_di */
959 4 /* memory_latency */
962 /* The only costs that are changed here are
963 integer multiplication. */
964 COSTS_N_INSNS (6), /* fp_add */
965 COSTS_N_INSNS (7), /* fp_mult_sf */
966 COSTS_N_INSNS (8), /* fp_mult_df */
967 COSTS_N_INSNS (23), /* fp_div_sf */
968 COSTS_N_INSNS (36), /* fp_div_df */
969 COSTS_N_INSNS (5), /* int_mult_si */
970 COSTS_N_INSNS (9), /* int_mult_di */
971 COSTS_N_INSNS (69), /* int_div_si */
972 COSTS_N_INSNS (69), /* int_div_di */
974 4 /* memory_latency */
980 /* The only costs that are changed here are
981 integer multiplication. */
982 COSTS_N_INSNS (6), /* fp_add */
983 COSTS_N_INSNS (7), /* fp_mult_sf */
984 COSTS_N_INSNS (8), /* fp_mult_df */
985 COSTS_N_INSNS (23), /* fp_div_sf */
986 COSTS_N_INSNS (36), /* fp_div_df */
987 COSTS_N_INSNS (3), /* int_mult_si */
988 COSTS_N_INSNS (8), /* int_mult_di */
989 COSTS_N_INSNS (69), /* int_div_si */
990 COSTS_N_INSNS (69), /* int_div_di */
992 4 /* memory_latency */
995 /* These costs are the same as the SB-1A below. */
996 COSTS_N_INSNS (4), /* fp_add */
997 COSTS_N_INSNS (4), /* fp_mult_sf */
998 COSTS_N_INSNS (4), /* fp_mult_df */
999 COSTS_N_INSNS (24), /* fp_div_sf */
1000 COSTS_N_INSNS (32), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (4), /* int_mult_di */
1003 COSTS_N_INSNS (36), /* int_div_si */
1004 COSTS_N_INSNS (68), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 /* These costs are the same as the SB-1 above. */
1010 COSTS_N_INSNS (4), /* fp_add */
1011 COSTS_N_INSNS (4), /* fp_mult_sf */
1012 COSTS_N_INSNS (4), /* fp_mult_df */
1013 COSTS_N_INSNS (24), /* fp_div_sf */
1014 COSTS_N_INSNS (32), /* fp_div_df */
1015 COSTS_N_INSNS (3), /* int_mult_si */
1016 COSTS_N_INSNS (4), /* int_mult_di */
1017 COSTS_N_INSNS (36), /* int_div_si */
1018 COSTS_N_INSNS (68), /* int_div_di */
1019 1, /* branch_cost */
1020 4 /* memory_latency */
1027 /* Use a hash table to keep track of implicit mips16/nomips16 attributes
1028 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1030 struct mflip_mips16_entry GTY (()) {
1034 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1036 /* Hash table callbacks for mflip_mips16_htab. */
1039 mflip_mips16_htab_hash (const void *entry)
1041 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1045 mflip_mips16_htab_eq (const void *entry, const void *name)
1047 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1048 (const char *) name) == 0;
1051 static GTY(()) int mips16_flipper;
1053 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1054 for -mflip-mips16. Return true if it should use "mips16" and false if
1055 it should use "nomips16". */
1058 mflip_mips16_use_mips16_p (tree decl)
1060 struct mflip_mips16_entry *entry;
1065 /* Use the opposite of the command-line setting for anonymous decls. */
1066 if (!DECL_NAME (decl))
1067 return !mips_base_mips16;
1069 if (!mflip_mips16_htab)
1070 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1071 mflip_mips16_htab_eq, NULL);
1073 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1074 hash = htab_hash_string (name);
1075 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1076 entry = (struct mflip_mips16_entry *) *slot;
1079 mips16_flipper = !mips16_flipper;
1080 entry = GGC_NEW (struct mflip_mips16_entry);
1082 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1085 return entry->mips16_p;
1088 /* Predicates to test for presence of "near" and "far"/"long_call"
1089 attributes on the given TYPE. */
1092 mips_near_type_p (const_tree type)
1094 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1098 mips_far_type_p (const_tree type)
1100 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1101 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1104 /* Similar predicates for "mips16"/"nomips16" attributes. */
1107 mips_mips16_decl_p (const_tree decl)
1109 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1113 mips_nomips16_decl_p (const_tree decl)
1115 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1118 /* Return true if function DECL is a MIPS16 function. Return the ambient
1119 setting if DECL is null. */
1122 mips_use_mips16_mode_p (tree decl)
1126 /* Nested functions must use the same frame pointer as their
1127 parent and must therefore use the same ISA mode. */
1128 tree parent = decl_function_context (decl);
1131 if (mips_mips16_decl_p (decl))
1133 if (mips_nomips16_decl_p (decl))
1136 return mips_base_mips16;
1139 /* Return 0 if the attributes for two types are incompatible, 1 if they
1140 are compatible, and 2 if they are nearly compatible (which causes a
1141 warning to be generated). */
1144 mips_comp_type_attributes (const_tree type1, const_tree type2)
1146 /* Check for mismatch of non-default calling convention. */
1147 if (TREE_CODE (type1) != FUNCTION_TYPE)
1150 /* Disallow mixed near/far attributes. */
1151 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1153 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1159 /* Implement TARGET_INSERT_ATTRIBUTES. */
1162 mips_insert_attributes (tree decl, tree *attributes)
1165 bool mips16_p, nomips16_p;
1167 /* Check for "mips16" and "nomips16" attributes. */
1168 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1169 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1170 if (TREE_CODE (decl) != FUNCTION_DECL)
1173 error ("%qs attribute only applies to functions", "mips16");
1175 error ("%qs attribute only applies to functions", "nomips16");
1179 mips16_p |= mips_mips16_decl_p (decl);
1180 nomips16_p |= mips_nomips16_decl_p (decl);
1181 if (mips16_p || nomips16_p)
1183 /* DECL cannot be simultaneously mips16 and nomips16. */
1184 if (mips16_p && nomips16_p)
1185 error ("%qs cannot have both %<mips16%> and "
1186 "%<nomips16%> attributes",
1187 IDENTIFIER_POINTER (DECL_NAME (decl)));
1189 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1191 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1192 "mips16" attribute, arbitrarily pick one. We must pick the same
1193 setting for duplicate declarations of a function. */
1194 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1195 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1200 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1203 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1205 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1206 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1207 error ("%qs redeclared with conflicting %qs attributes",
1208 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1209 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1210 error ("%qs redeclared with conflicting %qs attributes",
1211 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1213 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1214 DECL_ATTRIBUTES (newdecl));
1217 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1218 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1221 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1223 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1225 *base_ptr = XEXP (x, 0);
1226 *offset_ptr = INTVAL (XEXP (x, 1));
1235 static unsigned int mips_build_integer (struct mips_integer_op *,
1236 unsigned HOST_WIDE_INT);
1238 /* Subroutine of mips_build_integer (with the same interface).
1239 Assume that the final action in the sequence should be a left shift. */
1242 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1244 unsigned int i, shift;
1246 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1247 since signed numbers are easier to load than unsigned ones. */
1249 while ((value & 1) == 0)
1250 value /= 2, shift++;
1252 i = mips_build_integer (codes, value);
1253 codes[i].code = ASHIFT;
1254 codes[i].value = shift;
1259 /* As for mips_build_shift, but assume that the final action will be
1260 an IOR or PLUS operation. */
1263 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1265 unsigned HOST_WIDE_INT high;
1268 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1269 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1271 /* The constant is too complex to load with a simple lui/ori pair
1272 so our goal is to clear as many trailing zeros as possible.
1273 In this case, we know bit 16 is set and that the low 16 bits
1274 form a negative number. If we subtract that number from VALUE,
1275 we will clear at least the lowest 17 bits, maybe more. */
1276 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1277 codes[i].code = PLUS;
1278 codes[i].value = CONST_LOW_PART (value);
1282 i = mips_build_integer (codes, high);
1283 codes[i].code = IOR;
1284 codes[i].value = value & 0xffff;
1290 /* Fill CODES with a sequence of rtl operations to load VALUE.
1291 Return the number of operations needed. */
1294 mips_build_integer (struct mips_integer_op *codes,
1295 unsigned HOST_WIDE_INT value)
1297 if (SMALL_OPERAND (value)
1298 || SMALL_OPERAND_UNSIGNED (value)
1299 || LUI_OPERAND (value))
1301 /* The value can be loaded with a single instruction. */
1302 codes[0].code = UNKNOWN;
1303 codes[0].value = value;
1306 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1308 /* Either the constant is a simple LUI/ORI combination or its
1309 lowest bit is set. We don't want to shift in this case. */
1310 return mips_build_lower (codes, value);
1312 else if ((value & 0xffff) == 0)
1314 /* The constant will need at least three actions. The lowest
1315 16 bits are clear, so the final action will be a shift. */
1316 return mips_build_shift (codes, value);
1320 /* The final action could be a shift, add or inclusive OR.
1321 Rather than use a complex condition to select the best
1322 approach, try both mips_build_shift and mips_build_lower
1323 and pick the one that gives the shortest sequence.
1324 Note that this case is only used once per constant. */
1325 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1326 unsigned int cost, alt_cost;
1328 cost = mips_build_shift (codes, value);
1329 alt_cost = mips_build_lower (alt_codes, value);
1330 if (alt_cost < cost)
1332 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1339 /* Return true if X is a thread-local symbol. */
1342 mips_tls_operand_p (rtx x)
1344 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1347 /* Return true if SYMBOL_REF X is associated with a global symbol
1348 (in the STB_GLOBAL sense). */
1351 mips_global_symbol_p (const_rtx x)
1353 const_tree const decl = SYMBOL_REF_DECL (x);
1356 return !SYMBOL_REF_LOCAL_P (x);
1358 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1359 or weak symbols. Relocations in the object file will be against
1360 the target symbol, so it's that symbol's binding that matters here. */
1361 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1364 /* Return true if SYMBOL_REF X binds locally. */
1367 mips_symbol_binds_local_p (const_rtx x)
1369 return (SYMBOL_REF_DECL (x)
1370 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1371 : SYMBOL_REF_LOCAL_P (x));
1374 /* Return true if rtx constants of mode MODE should be put into a small
1378 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1380 return (!TARGET_EMBEDDED_DATA
1381 && TARGET_LOCAL_SDATA
1382 && GET_MODE_SIZE (mode) <= mips_section_threshold);
1385 /* Return true if X should not be moved directly into register $25.
1386 We need this because many versions of GAS will treat "la $25,foo" as
1387 part of a call sequence and so allow a global "foo" to be lazily bound. */
1390 mips_dangerous_for_la25_p (rtx x)
1392 return (!TARGET_EXPLICIT_RELOCS
1394 && GET_CODE (x) == SYMBOL_REF
1395 && mips_global_symbol_p (x));
1398 /* Return the method that should be used to access SYMBOL_REF or
1399 LABEL_REF X in context CONTEXT. */
1401 static enum mips_symbol_type
1402 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1405 return SYMBOL_GOT_DISP;
1407 if (GET_CODE (x) == LABEL_REF)
1409 /* LABEL_REFs are used for jump tables as well as text labels.
1410 Only return SYMBOL_PC_RELATIVE if we know the label is in
1411 the text section. */
1412 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1413 return SYMBOL_PC_RELATIVE;
1414 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1415 return SYMBOL_GOT_PAGE_OFST;
1416 return SYMBOL_ABSOLUTE;
1419 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1421 if (SYMBOL_REF_TLS_MODEL (x))
1424 if (CONSTANT_POOL_ADDRESS_P (x))
1426 if (TARGET_MIPS16_TEXT_LOADS)
1427 return SYMBOL_PC_RELATIVE;
1429 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1430 return SYMBOL_PC_RELATIVE;
1432 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1433 return SYMBOL_GP_RELATIVE;
1436 /* Do not use small-data accesses for weak symbols; they may end up
1439 && SYMBOL_REF_SMALL_P (x)
1440 && !SYMBOL_REF_WEAK (x))
1441 return SYMBOL_GP_RELATIVE;
1443 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1446 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1448 /* There are three cases to consider:
1450 - o32 PIC (either with or without explicit relocs)
1451 - n32/n64 PIC without explicit relocs
1452 - n32/n64 PIC with explicit relocs
1454 In the first case, both local and global accesses will use an
1455 R_MIPS_GOT16 relocation. We must correctly predict which of
1456 the two semantics (local or global) the assembler and linker
1457 will apply. The choice depends on the symbol's binding rather
1458 than its visibility.
1460 In the second case, the assembler will not use R_MIPS_GOT16
1461 relocations, but it chooses between local and global accesses
1462 in the same way as for o32 PIC.
1464 In the third case we have more freedom since both forms of
1465 access will work for any kind of symbol. However, there seems
1466 little point in doing things differently. */
1467 if (mips_global_symbol_p (x))
1468 return SYMBOL_GOT_DISP;
1470 return SYMBOL_GOT_PAGE_OFST;
1473 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1474 return SYMBOL_FORCE_TO_MEM;
1475 return SYMBOL_ABSOLUTE;
1478 /* Classify symbolic expression X, given that it appears in context
1481 static enum mips_symbol_type
1482 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1486 split_const (x, &x, &offset);
1487 if (UNSPEC_ADDRESS_P (x))
1488 return UNSPEC_ADDRESS_TYPE (x);
1490 return mips_classify_symbol (x, context);
1493 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1494 is the alignment (in bytes) of SYMBOL_REF X. */
1497 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1499 /* If for some reason we can't get the alignment for the
1500 symbol, initializing this to one means we will only accept
1502 HOST_WIDE_INT align = 1;
1505 /* Get the alignment of the symbol we're referring to. */
1506 t = SYMBOL_REF_DECL (x);
1508 align = DECL_ALIGN_UNIT (t);
1510 return offset >= 0 && offset < align;
1513 /* Return true if X is a symbolic constant that can be used in context
1514 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1517 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1518 enum mips_symbol_type *symbol_type)
1522 split_const (x, &x, &offset);
1523 if (UNSPEC_ADDRESS_P (x))
1525 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1526 x = UNSPEC_ADDRESS (x);
1528 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1530 *symbol_type = mips_classify_symbol (x, context);
1531 if (*symbol_type == SYMBOL_TLS)
1537 if (offset == const0_rtx)
1540 /* Check whether a nonzero offset is valid for the underlying
1542 switch (*symbol_type)
1544 case SYMBOL_ABSOLUTE:
1545 case SYMBOL_FORCE_TO_MEM:
1546 case SYMBOL_32_HIGH:
1547 case SYMBOL_64_HIGH:
1550 /* If the target has 64-bit pointers and the object file only
1551 supports 32-bit symbols, the values of those symbols will be
1552 sign-extended. In this case we can't allow an arbitrary offset
1553 in case the 32-bit value X + OFFSET has a different sign from X. */
1554 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1555 return offset_within_block_p (x, INTVAL (offset));
1557 /* In other cases the relocations can handle any offset. */
1560 case SYMBOL_PC_RELATIVE:
1561 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1562 In this case, we no longer have access to the underlying constant,
1563 but the original symbol-based access was known to be valid. */
1564 if (GET_CODE (x) == LABEL_REF)
1569 case SYMBOL_GP_RELATIVE:
1570 /* Make sure that the offset refers to something within the
1571 same object block. This should guarantee that the final
1572 PC- or GP-relative offset is within the 16-bit limit. */
1573 return offset_within_block_p (x, INTVAL (offset));
1575 case SYMBOL_GOT_PAGE_OFST:
1576 case SYMBOL_GOTOFF_PAGE:
1577 /* If the symbol is global, the GOT entry will contain the symbol's
1578 address, and we will apply a 16-bit offset after loading it.
1579 If the symbol is local, the linker should provide enough local
1580 GOT entries for a 16-bit offset, but larger offsets may lead
1582 return SMALL_INT (offset);
1586 /* There is no carry between the HI and LO REL relocations, so the
1587 offset is only valid if we know it won't lead to such a carry. */
1588 return mips_offset_within_alignment_p (x, INTVAL (offset));
1590 case SYMBOL_GOT_DISP:
1591 case SYMBOL_GOTOFF_DISP:
1592 case SYMBOL_GOTOFF_CALL:
1593 case SYMBOL_GOTOFF_LOADGP:
1596 case SYMBOL_GOTTPREL:
1604 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1605 single instruction. We rely on the fact that, in the worst case,
1606 all instructions involved in a MIPS16 address calculation are usually
1610 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1614 case SYMBOL_ABSOLUTE:
1615 /* When using 64-bit symbols, we need 5 preparatory instructions,
1618 lui $at,%highest(symbol)
1619 daddiu $at,$at,%higher(symbol)
1621 daddiu $at,$at,%hi(symbol)
1624 The final address is then $at + %lo(symbol). With 32-bit
1625 symbols we just need a preparatory lui for normal mode and
1626 a preparatory "li; sll" for MIPS16. */
1627 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1629 case SYMBOL_GP_RELATIVE:
1630 /* Treat GP-relative accesses as taking a single instruction on
1631 MIPS16 too; the copy of $gp can often be shared. */
1634 case SYMBOL_PC_RELATIVE:
1635 /* PC-relative constants can be only be used with addiupc,
1637 if (mode == MAX_MACHINE_MODE
1638 || GET_MODE_SIZE (mode) == 4
1639 || GET_MODE_SIZE (mode) == 8)
1642 /* The constant must be loaded using addiupc first. */
1645 case SYMBOL_FORCE_TO_MEM:
1646 /* LEAs will be converted into constant-pool references by
1648 if (mode == MAX_MACHINE_MODE)
1651 /* The constant must be loaded from the constant pool. */
1654 case SYMBOL_GOT_DISP:
1655 /* The constant will have to be loaded from the GOT before it
1656 is used in an address. */
1657 if (mode != MAX_MACHINE_MODE)
1662 case SYMBOL_GOT_PAGE_OFST:
1663 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1664 the local/global classification is accurate. See override_options
1667 The worst cases are:
1669 (1) For local symbols when generating o32 or o64 code. The assembler
1675 ...and the final address will be $at + %lo(symbol).
1677 (2) For global symbols when -mxgot. The assembler will use:
1679 lui $at,%got_hi(symbol)
1682 ...and the final address will be $at + %got_lo(symbol). */
1685 case SYMBOL_GOTOFF_PAGE:
1686 case SYMBOL_GOTOFF_DISP:
1687 case SYMBOL_GOTOFF_CALL:
1688 case SYMBOL_GOTOFF_LOADGP:
1689 case SYMBOL_32_HIGH:
1690 case SYMBOL_64_HIGH:
1696 case SYMBOL_GOTTPREL:
1699 /* A 16-bit constant formed by a single relocation, or a 32-bit
1700 constant formed from a high 16-bit relocation and a low 16-bit
1701 relocation. Use mips_split_p to determine which. */
1702 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1705 /* We don't treat a bare TLS symbol as a constant. */
1711 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1712 to load symbols of type TYPE into a register. Return 0 if the given
1713 type of symbol cannot be used as an immediate operand.
1715 Otherwise, return the number of instructions needed to load or store
1716 values of mode MODE to or from addresses of type TYPE. Return 0 if
1717 the given type of symbol is not valid in addresses.
1719 In both cases, treat extended MIPS16 instructions as two instructions. */
1722 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1724 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1727 /* Return true if X can not be forced into a constant pool. */
1730 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1732 return mips_tls_operand_p (*x);
1735 /* Return true if X can not be forced into a constant pool. */
1738 mips_cannot_force_const_mem (rtx x)
1744 /* As an optimization, reject constants that mips_legitimize_move
1747 Suppose we have a multi-instruction sequence that loads constant C
1748 into register R. If R does not get allocated a hard register, and
1749 R is used in an operand that allows both registers and memory
1750 references, reload will consider forcing C into memory and using
1751 one of the instruction's memory alternatives. Returning false
1752 here will force it to use an input reload instead. */
1753 if (GET_CODE (x) == CONST_INT)
1756 split_const (x, &base, &offset);
1757 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1761 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1767 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1768 constants when we're using a per-function constant pool. */
1771 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1772 const_rtx x ATTRIBUTE_UNUSED)
1774 return !TARGET_MIPS16_PCREL_LOADS;
1777 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1780 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1782 if (!HARD_REGISTER_NUM_P (regno))
1786 regno = reg_renumber[regno];
1789 /* These fake registers will be eliminated to either the stack or
1790 hard frame pointer, both of which are usually valid base registers.
1791 Reload deals with the cases where the eliminated form isn't valid. */
1792 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1795 /* In mips16 mode, the stack pointer can only address word and doubleword
1796 values, nothing smaller. There are two problems here:
1798 (a) Instantiating virtual registers can introduce new uses of the
1799 stack pointer. If these virtual registers are valid addresses,
1800 the stack pointer should be too.
1802 (b) Most uses of the stack pointer are not made explicit until
1803 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1804 We don't know until that stage whether we'll be eliminating to the
1805 stack pointer (which needs the restriction) or the hard frame
1806 pointer (which doesn't).
1808 All in all, it seems more consistent to only enforce this restriction
1809 during and after reload. */
1810 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1811 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1813 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1817 /* Return true if X is a valid base register for the given mode.
1818 Allow only hard registers if STRICT. */
1821 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1823 if (!strict && GET_CODE (x) == SUBREG)
1827 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1831 /* Return true if X is a valid address for machine mode MODE. If it is,
1832 fill in INFO appropriately. STRICT is true if we should only accept
1833 hard base registers. */
1836 mips_classify_address (struct mips_address_info *info, rtx x,
1837 enum machine_mode mode, int strict)
1839 switch (GET_CODE (x))
1843 info->type = ADDRESS_REG;
1845 info->offset = const0_rtx;
1846 return mips_valid_base_register_p (info->reg, mode, strict);
1849 info->type = ADDRESS_REG;
1850 info->reg = XEXP (x, 0);
1851 info->offset = XEXP (x, 1);
1852 return (mips_valid_base_register_p (info->reg, mode, strict)
1853 && const_arith_operand (info->offset, VOIDmode));
1856 info->type = ADDRESS_LO_SUM;
1857 info->reg = XEXP (x, 0);
1858 info->offset = XEXP (x, 1);
1859 /* We have to trust the creator of the LO_SUM to do something vaguely
1860 sane. Target-independent code that creates a LO_SUM should also
1861 create and verify the matching HIGH. Target-independent code that
1862 adds an offset to a LO_SUM must prove that the offset will not
1863 induce a carry. Failure to do either of these things would be
1864 a bug, and we are not required to check for it here. The MIPS
1865 backend itself should only create LO_SUMs for valid symbolic
1866 constants, with the high part being either a HIGH or a copy
1869 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
1870 return (mips_valid_base_register_p (info->reg, mode, strict)
1871 && mips_symbol_insns (info->symbol_type, mode) > 0
1872 && mips_lo_relocs[info->symbol_type] != 0);
1875 /* Small-integer addresses don't occur very often, but they
1876 are legitimate if $0 is a valid base register. */
1877 info->type = ADDRESS_CONST_INT;
1878 return !TARGET_MIPS16 && SMALL_INT (x);
1883 info->type = ADDRESS_SYMBOLIC;
1884 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
1886 && mips_symbol_insns (info->symbol_type, mode) > 0
1887 && !mips_split_p[info->symbol_type]);
1894 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1895 returns a nonzero value if X is a legitimate address for a memory
1896 operand of the indicated MODE. STRICT is nonzero if this function
1897 is called during reload. */
1900 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1902 struct mips_address_info addr;
1904 return mips_classify_address (&addr, x, mode, strict);
1907 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1910 mips_stack_address_p (rtx x, enum machine_mode mode)
1912 struct mips_address_info addr;
1914 return (mips_classify_address (&addr, x, mode, false)
1915 && addr.type == ADDRESS_REG
1916 && addr.reg == stack_pointer_rtx);
1919 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
1920 address instruction. */
1923 mips_lwxs_address_p (rtx addr)
1926 && GET_CODE (addr) == PLUS
1927 && REG_P (XEXP (addr, 1)))
1929 rtx offset = XEXP (addr, 0);
1930 if (GET_CODE (offset) == MULT
1931 && REG_P (XEXP (offset, 0))
1932 && GET_CODE (XEXP (offset, 1)) == CONST_INT
1933 && INTVAL (XEXP (offset, 1)) == 4)
1939 /* Return true if a value at OFFSET bytes from BASE can be accessed
1940 using an unextended mips16 instruction. MODE is the mode of the
1943 Usually the offset in an unextended instruction is a 5-bit field.
1944 The offset is unsigned and shifted left once for HIs, twice
1945 for SIs, and so on. An exception is SImode accesses off the
1946 stack pointer, which have an 8-bit immediate field. */
1949 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1952 && GET_CODE (offset) == CONST_INT
1953 && INTVAL (offset) >= 0
1954 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1956 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1957 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1958 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1964 /* Return the number of instructions needed to load or store a value
1965 of mode MODE at X. Return 0 if X isn't valid for MODE. Assume that
1966 multiword moves may need to be split into word moves if MIGHT_SPLIT_P,
1967 otherwise assume that a single load or store is enough.
1969 For mips16 code, count extended instructions as two instructions. */
1972 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
1974 struct mips_address_info addr;
1977 /* BLKmode is used for single unaligned loads and stores and should
1978 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
1979 meaningless, so we have to single it out as a special case one way
1981 if (mode != BLKmode && might_split_p)
1982 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1986 if (mips_classify_address (&addr, x, mode, false))
1991 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1995 case ADDRESS_LO_SUM:
1996 return (TARGET_MIPS16 ? factor * 2 : factor);
1998 case ADDRESS_CONST_INT:
2001 case ADDRESS_SYMBOLIC:
2002 return factor * mips_symbol_insns (addr.symbol_type, mode);
2008 /* Likewise for constant X. */
2011 mips_const_insns (rtx x)
2013 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2014 enum mips_symbol_type symbol_type;
2017 switch (GET_CODE (x))
2020 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2022 || !mips_split_p[symbol_type])
2025 /* This is simply an lui for normal mode. It is an extended
2026 "li" followed by an extended "sll" for MIPS16. */
2027 return TARGET_MIPS16 ? 4 : 1;
2031 /* Unsigned 8-bit constants can be loaded using an unextended
2032 LI instruction. Unsigned 16-bit constants can be loaded
2033 using an extended LI. Negative constants must be loaded
2034 using LI and then negated. */
2035 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
2036 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2037 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
2038 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2041 return mips_build_integer (codes, INTVAL (x));
2045 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
2051 /* See if we can refer to X directly. */
2052 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2053 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2055 /* Otherwise try splitting the constant into a base and offset.
2056 16-bit offsets can be added using an extra addiu. Larger offsets
2057 must be calculated separately and then added to the base. */
2058 split_const (x, &x, &offset);
2061 int n = mips_const_insns (x);
2064 if (SMALL_INT (offset))
2067 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2074 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2083 /* Return the number of instructions needed to implement INSN,
2084 given that it loads from or stores to MEM. Count extended
2085 mips16 instructions as two instructions. */
2088 mips_load_store_insns (rtx mem, rtx insn)
2090 enum machine_mode mode;
2094 gcc_assert (MEM_P (mem));
2095 mode = GET_MODE (mem);
2097 /* Try to prove that INSN does not need to be split. */
2098 might_split_p = true;
2099 if (GET_MODE_BITSIZE (mode) == 64)
2101 set = single_set (insn);
2102 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2103 might_split_p = false;
2106 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2110 /* Return the number of instructions needed for an integer division. */
2113 mips_idiv_insns (void)
2118 if (TARGET_CHECK_ZERO_DIV)
2120 if (GENERATE_DIVIDE_TRAPS)
2126 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2131 /* Emit a move from SRC to DEST. Assume that the move expanders can
2132 handle all moves if !can_create_pseudo_p (). The distinction is
2133 important because, unlike emit_move_insn, the move expanders know
2134 how to force Pmode objects into the constant pool even when the
2135 constant pool address is not itself legitimate. */
2138 mips_emit_move (rtx dest, rtx src)
2140 return (can_create_pseudo_p ()
2141 ? emit_move_insn (dest, src)
2142 : emit_move_insn_1 (dest, src));
2145 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2148 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2150 emit_insn (gen_rtx_SET (VOIDmode, target,
2151 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2154 /* Copy VALUE to a register and return that register. If new psuedos
2155 are allowed, copy it into a new register, otherwise use DEST. */
2158 mips_force_temporary (rtx dest, rtx value)
2160 if (can_create_pseudo_p ())
2161 return force_reg (Pmode, value);
2164 mips_emit_move (copy_rtx (dest), value);
2169 /* If we can access small data directly (using gp-relative relocation
2170 operators) return the small data pointer, otherwise return null.
2172 For each mips16 function which refers to GP relative symbols, we
2173 use a pseudo register, initialized at the start of the function, to
2174 hold the $gp value. */
2177 mips16_gp_pseudo_reg (void)
2179 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2180 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2182 /* Don't initialize the pseudo register if we are being called from
2183 the tree optimizers' cost-calculation routines. */
2184 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2185 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2189 /* We want to initialize this to a value which gcc will believe
2191 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2193 push_topmost_sequence ();
2194 /* We need to emit the initialization after the FUNCTION_BEG
2195 note, so that it will be integrated. */
2196 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
2198 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
2200 if (scan == NULL_RTX)
2201 scan = get_insns ();
2202 insn = emit_insn_after (insn, scan);
2203 pop_topmost_sequence ();
2205 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2208 return cfun->machine->mips16_gp_pseudo_rtx;
2211 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2212 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2213 constant in that context and can be split into a high part and a LO_SUM.
2214 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2215 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2217 TEMP is as for mips_force_temporary and is used to load the high
2218 part into a register. */
2221 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
2223 enum mips_symbol_context context;
2224 enum mips_symbol_type symbol_type;
2227 context = (mode == MAX_MACHINE_MODE
2228 ? SYMBOL_CONTEXT_LEA
2229 : SYMBOL_CONTEXT_MEM);
2230 if (!mips_symbolic_constant_p (addr, context, &symbol_type)
2231 || mips_symbol_insns (symbol_type, mode) == 0
2232 || !mips_split_p[symbol_type])
2237 if (symbol_type == SYMBOL_GP_RELATIVE)
2239 if (!can_create_pseudo_p ())
2241 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2245 high = mips16_gp_pseudo_reg ();
2249 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2250 high = mips_force_temporary (temp, high);
2252 *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
2258 /* Wrap symbol or label BASE in an unspec address of type SYMBOL_TYPE
2259 and add CONST_INT OFFSET to the result. */
2262 mips_unspec_address_offset (rtx base, rtx offset,
2263 enum mips_symbol_type symbol_type)
2265 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2266 UNSPEC_ADDRESS_FIRST + symbol_type);
2267 if (offset != const0_rtx)
2268 base = gen_rtx_PLUS (Pmode, base, offset);
2269 return gen_rtx_CONST (Pmode, base);
2272 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2273 type SYMBOL_TYPE. */
2276 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2280 split_const (address, &base, &offset);
2281 return mips_unspec_address_offset (base, offset, symbol_type);
2285 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2286 high part to BASE and return the result. Just return BASE otherwise.
2287 TEMP is available as a temporary register if needed.
2289 The returned expression can be used as the first operand to a LO_SUM. */
2292 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2293 enum mips_symbol_type symbol_type)
2295 if (mips_split_p[symbol_type])
2297 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2298 addr = mips_force_temporary (temp, addr);
2299 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2305 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2306 mips_force_temporary; it is only needed when OFFSET is not a
2310 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2312 if (!SMALL_OPERAND (offset))
2317 /* Load the full offset into a register so that we can use
2318 an unextended instruction for the address itself. */
2319 high = GEN_INT (offset);
2324 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2325 high = GEN_INT (CONST_HIGH_PART (offset));
2326 offset = CONST_LOW_PART (offset);
2328 high = mips_force_temporary (temp, high);
2329 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2331 return plus_constant (reg, offset);
2334 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2335 referencing, and TYPE is the symbol type to use (either global
2336 dynamic or local dynamic). V0 is an RTX for the return value
2337 location. The entire insn sequence is returned. */
2339 static GTY(()) rtx mips_tls_symbol;
2342 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2344 rtx insn, loc, tga, a0;
2346 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2348 if (!mips_tls_symbol)
2349 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2351 loc = mips_unspec_address (sym, type);
2355 emit_insn (gen_rtx_SET (Pmode, a0,
2356 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2357 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2358 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2359 CONST_OR_PURE_CALL_P (insn) = 1;
2360 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2361 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2362 insn = get_insns ();
2369 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2370 return value will be a valid address and move_operand (either a REG
2374 mips_legitimize_tls_address (rtx loc)
2376 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2377 enum tls_model model;
2381 sorry ("MIPS16 TLS");
2382 return gen_reg_rtx (Pmode);
2385 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2386 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2388 model = SYMBOL_REF_TLS_MODEL (loc);
2389 /* Only TARGET_ABICALLS code can have more than one module; other
2390 code must be be static and should not use a GOT. All TLS models
2391 reduce to local exec in this situation. */
2392 if (!TARGET_ABICALLS)
2393 model = TLS_MODEL_LOCAL_EXEC;
2397 case TLS_MODEL_GLOBAL_DYNAMIC:
2398 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2399 dest = gen_reg_rtx (Pmode);
2400 emit_libcall_block (insn, dest, v0, loc);
2403 case TLS_MODEL_LOCAL_DYNAMIC:
2404 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2405 tmp1 = gen_reg_rtx (Pmode);
2407 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2408 share the LDM result with other LD model accesses. */
2409 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2411 emit_libcall_block (insn, tmp1, v0, eqv);
2413 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2414 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2415 mips_unspec_address (loc, SYMBOL_DTPREL));
2418 case TLS_MODEL_INITIAL_EXEC:
2419 tmp1 = gen_reg_rtx (Pmode);
2420 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2421 if (Pmode == DImode)
2423 emit_insn (gen_tls_get_tp_di (v1));
2424 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2428 emit_insn (gen_tls_get_tp_si (v1));
2429 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2431 dest = gen_reg_rtx (Pmode);
2432 emit_insn (gen_add3_insn (dest, tmp1, v1));
2435 case TLS_MODEL_LOCAL_EXEC:
2436 if (Pmode == DImode)
2437 emit_insn (gen_tls_get_tp_di (v1));
2439 emit_insn (gen_tls_get_tp_si (v1));
2441 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2442 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2443 mips_unspec_address (loc, SYMBOL_TPREL));
2453 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2454 be legitimized in a way that the generic machinery might not expect,
2455 put the new address in *XLOC and return true. MODE is the mode of
2456 the memory being accessed. */
2459 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2461 if (mips_tls_operand_p (*xloc))
2463 *xloc = mips_legitimize_tls_address (*xloc);
2467 /* See if the address can split into a high part and a LO_SUM. */
2468 if (mips_split_symbol (NULL, *xloc, mode, xloc))
2471 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2473 /* Handle REG + CONSTANT using mips_add_offset. */
2476 reg = XEXP (*xloc, 0);
2477 if (!mips_valid_base_register_p (reg, mode, 0))
2478 reg = copy_to_mode_reg (Pmode, reg);
2479 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2487 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2490 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2492 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2493 enum machine_mode mode;
2494 unsigned int i, cost;
2497 mode = GET_MODE (dest);
2498 cost = mips_build_integer (codes, value);
2500 /* Apply each binary operation to X. Invariant: X is a legitimate
2501 source operand for a SET pattern. */
2502 x = GEN_INT (codes[0].value);
2503 for (i = 1; i < cost; i++)
2505 if (!can_create_pseudo_p ())
2507 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2511 x = force_reg (mode, x);
2512 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2515 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2519 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2520 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2524 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2528 /* Split moves of big integers into smaller pieces. */
2529 if (splittable_const_int_operand (src, mode))
2531 mips_move_integer (dest, dest, INTVAL (src));
2535 /* Split moves of symbolic constants into high/low pairs. */
2536 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2538 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2542 if (mips_tls_operand_p (src))
2544 mips_emit_move (dest, mips_legitimize_tls_address (src));
2548 /* If we have (const (plus symbol offset)), and that expression cannot
2549 be forced into memory, load the symbol first and add in the offset.
2550 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2551 forced into memory, as it usually produces better code. */
2552 split_const (src, &base, &offset);
2553 if (offset != const0_rtx
2554 && (targetm.cannot_force_const_mem (src)
2555 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2557 base = mips_force_temporary (dest, base);
2558 mips_emit_move (dest, mips_add_offset (0, base, INTVAL (offset)));
2562 src = force_const_mem (mode, src);
2564 /* When using explicit relocs, constant pool references are sometimes
2565 not legitimate addresses. */
2566 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2567 mips_emit_move (dest, src);
2571 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2572 sequence that is valid. */
2575 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2577 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2579 mips_emit_move (dest, force_reg (mode, src));
2583 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2584 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2585 && REG_P (src) && MD_REG_P (REGNO (src))
2586 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2588 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2589 if (GET_MODE_SIZE (mode) <= 4)
2590 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2591 gen_rtx_REG (SImode, REGNO (src)),
2592 gen_rtx_REG (SImode, other_regno)));
2594 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2595 gen_rtx_REG (DImode, REGNO (src)),
2596 gen_rtx_REG (DImode, other_regno)));
2600 /* We need to deal with constants that would be legitimate
2601 immediate_operands but not legitimate move_operands. */
2602 if (CONSTANT_P (src) && !move_operand (src, mode))
2604 mips_legitimize_const_move (mode, dest, src);
2605 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2611 /* Return true if X in context CONTEXT is a small data address that can
2612 be rewritten as a LO_SUM. */
2615 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2617 enum mips_symbol_type symbol_type;
2619 return (TARGET_EXPLICIT_RELOCS
2620 && mips_symbolic_constant_p (x, context, &symbol_type)
2621 && symbol_type == SYMBOL_GP_RELATIVE);
2625 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2626 containing MEM, or null if none. */
2629 mips_small_data_pattern_1 (rtx *loc, void *data)
2631 enum mips_symbol_context context;
2633 if (GET_CODE (*loc) == LO_SUM)
2638 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2643 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2644 return mips_rewrite_small_data_p (*loc, context);
2647 /* Return true if OP refers to small data symbols directly, not through
2651 mips_small_data_pattern_p (rtx op)
2653 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
2656 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2657 DATA is the containing MEM, or null if none. */
2660 mips_rewrite_small_data_1 (rtx *loc, void *data)
2662 enum mips_symbol_context context;
2666 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2670 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2671 if (mips_rewrite_small_data_p (*loc, context))
2672 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2674 if (GET_CODE (*loc) == LO_SUM)
2680 /* If possible, rewrite OP so that it refers to small data using
2681 explicit relocations. */
2684 mips_rewrite_small_data (rtx op)
2686 op = copy_insn (op);
2687 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
2691 /* We need a lot of little routines to check constant values on the
2692 mips16. These are used to figure out how long the instruction will
2693 be. It would be much better to do this using constraints, but
2694 there aren't nearly enough letters available. */
2697 m16_check_op (rtx op, int low, int high, int mask)
2699 return (GET_CODE (op) == CONST_INT
2700 && INTVAL (op) >= low
2701 && INTVAL (op) <= high
2702 && (INTVAL (op) & mask) == 0);
2706 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2708 return m16_check_op (op, 0x1, 0x8, 0);
2712 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2714 return m16_check_op (op, - 0x8, 0x7, 0);
2718 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2720 return m16_check_op (op, - 0x7, 0x8, 0);
2724 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2726 return m16_check_op (op, - 0x10, 0xf, 0);
2730 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2732 return m16_check_op (op, - 0xf, 0x10, 0);
2736 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2738 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2742 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2744 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2748 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2750 return m16_check_op (op, - 0x80, 0x7f, 0);
2754 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2756 return m16_check_op (op, - 0x7f, 0x80, 0);
2760 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2762 return m16_check_op (op, 0x0, 0xff, 0);
2766 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2768 return m16_check_op (op, - 0xff, 0x0, 0);
2772 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2774 return m16_check_op (op, - 0x1, 0xfe, 0);
2778 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2780 return m16_check_op (op, 0x0, 0xff << 2, 3);
2784 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2786 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2790 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2792 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2796 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2798 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2801 /* The cost of loading values from the constant pool. It should be
2802 larger than the cost of any constant we want to synthesize inline. */
2804 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2806 /* Return the cost of X when used as an operand to the MIPS16 instruction
2807 that implements CODE. Return -1 if there is no such instruction, or if
2808 X is not a valid immediate operand for it. */
2811 mips16_constant_cost (int code, HOST_WIDE_INT x)
2818 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2819 other shifts are extended. The shift patterns truncate the shift
2820 count to the right size, so there are no out-of-range values. */
2821 if (IN_RANGE (x, 1, 8))
2823 return COSTS_N_INSNS (1);
2826 if (IN_RANGE (x, -128, 127))
2828 if (SMALL_OPERAND (x))
2829 return COSTS_N_INSNS (1);
2833 /* Like LE, but reject the always-true case. */
2837 /* We add 1 to the immediate and use SLT. */
2840 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2843 if (IN_RANGE (x, 0, 255))
2845 if (SMALL_OPERAND_UNSIGNED (x))
2846 return COSTS_N_INSNS (1);
2851 /* Equality comparisons with 0 are cheap. */
2861 /* Return true if there is a non-MIPS16 instruction that implements CODE
2862 and if that instruction accepts X as an immediate operand. */
2865 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2872 /* All shift counts are truncated to a valid constant. */
2877 /* Likewise rotates, if the target supports rotates at all. */
2883 /* These instructions take 16-bit unsigned immediates. */
2884 return SMALL_OPERAND_UNSIGNED (x);
2889 /* These instructions take 16-bit signed immediates. */
2890 return SMALL_OPERAND (x);
2896 /* The "immediate" forms of these instructions are really
2897 implemented as comparisons with register 0. */
2902 /* Likewise, meaning that the only valid immediate operand is 1. */
2906 /* We add 1 to the immediate and use SLT. */
2907 return SMALL_OPERAND (x + 1);
2910 /* Likewise SLTU, but reject the always-true case. */
2911 return SMALL_OPERAND (x + 1) && x + 1 != 0;
2915 /* The bit position and size are immediate operands. */
2916 return ISA_HAS_EXT_INS;
2919 /* By default assume that $0 can be used for 0. */
2924 /* Return the cost of binary operation X, given that the instruction
2925 sequence for a word-sized or smaller operation has cost SINGLE_COST
2926 and that the sequence of a double-word operation has cost DOUBLE_COST. */
2929 mips_binary_cost (rtx x, int single_cost, int double_cost)
2933 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
2938 + rtx_cost (XEXP (x, 0), 0)
2939 + rtx_cost (XEXP (x, 1), GET_CODE (x)));
2942 /* Return the cost of floating-point multiplications of mode MODE. */
2945 mips_fp_mult_cost (enum machine_mode mode)
2947 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
2950 /* Return the cost of floating-point divisions of mode MODE. */
2953 mips_fp_div_cost (enum machine_mode mode)
2955 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
2958 /* Return the cost of sign-extending OP to mode MODE, not including the
2959 cost of OP itself. */
2962 mips_sign_extend_cost (enum machine_mode mode, rtx op)
2965 /* Extended loads are as cheap as unextended ones. */
2968 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2969 /* A sign extension from SImode to DImode in 64-bit mode is free. */
2972 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
2973 /* We can use SEB or SEH. */
2974 return COSTS_N_INSNS (1);
2976 /* We need to use a shift left and a shift right. */
2977 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2980 /* Return the cost of zero-extending OP to mode MODE, not including the
2981 cost of OP itself. */
2984 mips_zero_extend_cost (enum machine_mode mode, rtx op)
2987 /* Extended loads are as cheap as unextended ones. */
2990 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2991 /* We need a shift left by 32 bits and a shift right by 32 bits. */
2992 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2994 if (GENERATE_MIPS16E)
2995 /* We can use ZEB or ZEH. */
2996 return COSTS_N_INSNS (1);
2999 /* We need to load 0xff or 0xffff into a register and use AND. */
3000 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3002 /* We can use ANDI. */
3003 return COSTS_N_INSNS (1);
3006 /* Implement TARGET_RTX_COSTS. */
3009 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
3011 enum machine_mode mode = GET_MODE (x);
3012 bool float_mode_p = FLOAT_MODE_P (mode);
3016 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3017 appear in the instruction stream, and the cost of a comparison is
3018 really the cost of the branch or scc condition. At the time of
3019 writing, gcc only uses an explicit outer COMPARE code when optabs
3020 is testing whether a constant is expensive enough to force into a
3021 register. We want optabs to pass such constants through the MIPS
3022 expanders instead, so make all constants very cheap here. */
3023 if (outer_code == COMPARE)
3025 gcc_assert (CONSTANT_P (x));
3033 /* Treat *clear_upper32-style ANDs as having zero cost in the
3034 second operand. The cost is entirely in the first operand.
3036 ??? This is needed because we would otherwise try to CSE
3037 the constant operand. Although that's the right thing for
3038 instructions that continue to be a register operation throughout
3039 compilation, it is disastrous for instructions that could
3040 later be converted into a memory operation. */
3042 && outer_code == AND
3043 && UINTVAL (x) == 0xffffffff)
3051 cost = mips16_constant_cost (outer_code, INTVAL (x));
3060 /* When not optimizing for size, we care more about the cost
3061 of hot code, and hot code is often in a loop. If a constant
3062 operand needs to be forced into a register, we will often be
3063 able to hoist the constant load out of the loop, so the load
3064 should not contribute to the cost. */
3066 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3078 if (force_to_mem_operand (x, VOIDmode))
3080 *total = COSTS_N_INSNS (1);
3083 cost = mips_const_insns (x);
3086 /* If the constant is likely to be stored in a GPR, SETs of
3087 single-insn constants are as cheap as register sets; we
3088 never want to CSE them.
3090 Don't reduce the cost of storing a floating-point zero in
3091 FPRs. If we have a zero in an FPR for other reasons, we
3092 can get better cfg-cleanup and delayed-branch results by
3093 using it consistently, rather than using $0 sometimes and
3094 an FPR at other times. Also, moves between floating-point
3095 registers are sometimes cheaper than (D)MTC1 $0. */
3097 && outer_code == SET
3098 && !(float_mode_p && TARGET_HARD_FLOAT))
3100 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3101 want to CSE the constant itself. It is usually better to
3102 have N copies of the last operation in the sequence and one
3103 shared copy of the other operations. (Note that this is
3104 not true for MIPS16 code, where the final operation in the
3105 sequence is often an extended instruction.)
3107 Also, if we have a CONST_INT, we don't know whether it is
3108 for a word or doubleword operation, so we cannot rely on
3109 the result of mips_build_integer. */
3110 else if (!TARGET_MIPS16
3111 && (outer_code == SET || mode == VOIDmode))
3113 *total = COSTS_N_INSNS (cost);
3116 /* The value will need to be fetched from the constant pool. */
3117 *total = CONSTANT_POOL_COST;
3121 /* If the address is legitimate, return the number of
3122 instructions it needs. */
3124 cost = mips_address_insns (addr, mode, true);
3127 *total = COSTS_N_INSNS (cost + 1);
3130 /* Check for a scaled indexed address. */
3131 if (mips_lwxs_address_p (addr))
3133 *total = COSTS_N_INSNS (2);
3136 /* Otherwise use the default handling. */
3140 *total = COSTS_N_INSNS (6);
3144 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3148 /* Check for a *clear_upper32 pattern and treat it like a zero
3149 extension. See the pattern's comment for details. */
3152 && CONST_INT_P (XEXP (x, 1))
3153 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3155 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3156 + rtx_cost (XEXP (x, 0), 0));
3163 /* Double-word operations use two single-word operations. */
3164 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3172 if (CONSTANT_P (XEXP (x, 1)))
3173 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3175 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3180 *total = mips_cost->fp_add;
3182 *total = COSTS_N_INSNS (4);
3186 /* Low-part immediates need an extended MIPS16 instruction. */
3187 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3188 + rtx_cost (XEXP (x, 0), 0));
3203 /* Branch comparisons have VOIDmode, so use the first operand's
3205 mode = GET_MODE (XEXP (x, 0));
3206 if (FLOAT_MODE_P (mode))
3208 *total = mips_cost->fp_add;
3211 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3216 && ISA_HAS_NMADD_NMSUB
3217 && TARGET_FUSED_MADD
3218 && !HONOR_NANS (mode)
3219 && !HONOR_SIGNED_ZEROS (mode))
3221 /* See if we can use NMADD or NMSUB. See mips.md for the
3222 associated patterns. */
3223 rtx op0 = XEXP (x, 0);
3224 rtx op1 = XEXP (x, 1);
3225 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3227 *total = (mips_fp_mult_cost (mode)
3228 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
3229 + rtx_cost (XEXP (op0, 1), 0)
3230 + rtx_cost (op1, 0));
3233 if (GET_CODE (op1) == MULT)
3235 *total = (mips_fp_mult_cost (mode)
3237 + rtx_cost (XEXP (op1, 0), 0)
3238 + rtx_cost (XEXP (op1, 1), 0));
3248 && TARGET_FUSED_MADD
3249 && GET_CODE (XEXP (x, 0)) == MULT)
3252 *total = mips_cost->fp_add;
3256 /* Double-word operations require three single-word operations and
3257 an SLTU. The MIPS16 version then needs to move the result of
3258 the SLTU from $24 to a MIPS16 register. */
3259 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3260 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3265 && ISA_HAS_NMADD_NMSUB
3266 && TARGET_FUSED_MADD
3267 && !HONOR_NANS (mode)
3268 && HONOR_SIGNED_ZEROS (mode))
3270 /* See if we can use NMADD or NMSUB. See mips.md for the
3271 associated patterns. */
3272 rtx op = XEXP (x, 0);
3273 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3274 && GET_CODE (XEXP (op, 0)) == MULT)
3276 *total = (mips_fp_mult_cost (mode)
3277 + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
3278 + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
3279 + rtx_cost (XEXP (op, 1), 0));
3285 *total = mips_cost->fp_add;
3287 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3292 *total = mips_fp_mult_cost (mode);
3293 else if (mode == DImode && !TARGET_64BIT)
3294 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3295 where the mulsidi3 always includes an MFHI and an MFLO. */
3296 *total = (optimize_size
3297 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3298 : mips_cost->int_mult_si * 3 + 6);
3299 else if (optimize_size)
3300 *total = (ISA_HAS_MUL3 ? 1 : 2);
3301 else if (mode == DImode)
3302 *total = mips_cost->int_mult_di;
3304 *total = mips_cost->int_mult_si;
3308 /* Check for a reciprocal. */
3309 if (float_mode_p && XEXP (x, 0) == CONST1_RTX (mode))
3312 && flag_unsafe_math_optimizations
3313 && (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT))
3315 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3316 division as being free. */
3317 *total = rtx_cost (XEXP (x, 1), 0);
3322 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
3332 *total = mips_fp_div_cost (mode);
3341 /* It is our responsibility to make division by a power of 2
3342 as cheap as 2 register additions if we want the division
3343 expanders to be used for such operations; see the setting
3344 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3345 should always produce shorter code than using
3346 expand_sdiv2_pow2. */
3348 && CONST_INT_P (XEXP (x, 1))
3349 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3351 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
3354 *total = COSTS_N_INSNS (mips_idiv_insns ());
3356 else if (mode == DImode)
3357 *total = mips_cost->int_div_di;
3359 *total = mips_cost->int_div_si;
3363 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3367 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3371 case UNSIGNED_FLOAT:
3374 case FLOAT_TRUNCATE:
3375 *total = mips_cost->fp_add;
3383 /* Provide the costs of an addressing mode that contains ADDR.
3384 If ADDR is not a valid address, its cost is irrelevant. */
3387 mips_address_cost (rtx addr)
3389 return mips_address_insns (addr, SImode, false);
3392 /* Return one word of double-word value OP, taking into account the fixed
3393 endianness of certain registers. HIGH_P is true to select the high part,
3394 false to select the low part. */
3397 mips_subword (rtx op, int high_p)
3399 unsigned int byte, offset;
3400 enum machine_mode mode;
3402 mode = GET_MODE (op);
3403 if (mode == VOIDmode)
3406 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3407 byte = UNITS_PER_WORD;
3411 if (FP_REG_RTX_P (op))
3413 /* Paired FPRs are always ordered little-endian. */
3414 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3415 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3419 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3421 return simplify_gen_subreg (word_mode, op, mode, byte);
3425 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3428 mips_split_64bit_move_p (rtx dest, rtx src)
3433 /* FP->FP moves can be done in a single instruction. */
3434 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3437 /* Check for floating-point loads and stores. They can be done using
3438 ldc1 and sdc1 on MIPS II and above. */
3441 if (FP_REG_RTX_P (dest) && MEM_P (src))
3443 if (FP_REG_RTX_P (src) && MEM_P (dest))
3450 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3451 this function handles 64-bit moves for which mips_split_64bit_move_p
3452 holds. For 64-bit targets, this function handles 128-bit moves. */
3455 mips_split_doubleword_move (rtx dest, rtx src)
3457 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3459 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3460 emit_insn (gen_move_doubleword_fprdi (dest, src));
3461 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3462 emit_insn (gen_move_doubleword_fprdf (dest, src));
3463 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3464 emit_insn (gen_move_doubleword_fprtf (dest, src));
3470 /* The operation can be split into two normal moves. Decide in
3471 which order to do them. */
3474 low_dest = mips_subword (dest, 0);
3475 if (REG_P (low_dest)
3476 && reg_overlap_mentioned_p (low_dest, src))
3478 mips_emit_move (mips_subword (dest, 1), mips_subword (src, 1));
3479 mips_emit_move (low_dest, mips_subword (src, 0));
3483 mips_emit_move (low_dest, mips_subword (src, 0));
3484 mips_emit_move (mips_subword (dest, 1), mips_subword (src, 1));
3489 /* Return the appropriate instructions to move SRC into DEST. Assume
3490 that SRC is operand 1 and DEST is operand 0. */
3493 mips_output_move (rtx dest, rtx src)
3495 enum rtx_code dest_code, src_code;
3496 enum mips_symbol_type symbol_type;
3499 dest_code = GET_CODE (dest);
3500 src_code = GET_CODE (src);
3501 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
3503 if (dbl_p && mips_split_64bit_move_p (dest, src))
3506 if ((src_code == REG && GP_REG_P (REGNO (src)))
3507 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3509 if (dest_code == REG)
3511 if (GP_REG_P (REGNO (dest)))
3512 return "move\t%0,%z1";
3514 if (MD_REG_P (REGNO (dest)))
3517 if (DSP_ACC_REG_P (REGNO (dest)))
3519 static char retval[] = "mt__\t%z1,%q0";
3520 retval[2] = reg_names[REGNO (dest)][4];
3521 retval[3] = reg_names[REGNO (dest)][5];
3525 if (FP_REG_P (REGNO (dest)))
3526 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3528 if (ALL_COP_REG_P (REGNO (dest)))
3530 static char retval[] = "dmtc_\t%z1,%0";
3532 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3533 return (dbl_p ? retval : retval + 1);
3536 if (dest_code == MEM)
3537 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3539 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3541 if (src_code == REG)
3543 if (DSP_ACC_REG_P (REGNO (src)))
3545 static char retval[] = "mf__\t%0,%q1";
3546 retval[2] = reg_names[REGNO (src)][4];
3547 retval[3] = reg_names[REGNO (src)][5];
3551 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3552 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3554 if (FP_REG_P (REGNO (src)))
3555 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3557 if (ALL_COP_REG_P (REGNO (src)))
3559 static char retval[] = "dmfc_\t%0,%1";
3561 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3562 return (dbl_p ? retval : retval + 1);
3566 if (src_code == MEM)
3567 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3569 if (src_code == CONST_INT)
3571 /* Don't use the X format, because that will give out of
3572 range numbers for 64-bit hosts and 32-bit targets. */
3574 return "li\t%0,%1\t\t\t# %X1";
3576 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3579 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3583 if (src_code == HIGH)
3584 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3586 if (CONST_GP_P (src))
3587 return "move\t%0,%1";
3589 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3590 && mips_lo_relocs[symbol_type] != 0)
3592 /* A signed 16-bit constant formed by applying a relocation
3593 operator to a symbolic address. */
3594 gcc_assert (!mips_split_p[symbol_type]);
3595 return "li\t%0,%R1";
3598 if (symbolic_operand (src, VOIDmode))
3600 gcc_assert (TARGET_MIPS16
3601 ? TARGET_MIPS16_TEXT_LOADS
3602 : !TARGET_EXPLICIT_RELOCS);
3603 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3606 if (src_code == REG && FP_REG_P (REGNO (src)))
3608 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3610 if (GET_MODE (dest) == V2SFmode)
3611 return "mov.ps\t%0,%1";
3613 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3616 if (dest_code == MEM)
3617 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3619 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3621 if (src_code == MEM)
3622 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3624 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3626 static char retval[] = "l_c_\t%0,%1";
3628 retval[1] = (dbl_p ? 'd' : 'w');
3629 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3632 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3634 static char retval[] = "s_c_\t%1,%0";
3636 retval[1] = (dbl_p ? 'd' : 'w');
3637 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3643 /* Return true if CMP1 is a suitable second operand for relational
3644 operator CODE. See also the *sCC patterns in mips.md. */
3647 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3653 return reg_or_0_operand (cmp1, VOIDmode);
3657 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3661 return arith_operand (cmp1, VOIDmode);
3664 return sle_operand (cmp1, VOIDmode);
3667 return sleu_operand (cmp1, VOIDmode);
3674 /* Canonicalize LE or LEU comparisons into LT comparisons when
3675 possible to avoid extra instructions or inverting the
3679 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3680 enum machine_mode mode)
3682 HOST_WIDE_INT original, plus_one;
3684 if (GET_CODE (*cmp1) != CONST_INT)
3687 original = INTVAL (*cmp1);
3688 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3693 if (original < plus_one)
3696 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3705 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3718 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3719 result in TARGET. CMP0 and TARGET are register_operands that have
3720 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3721 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3724 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3725 rtx target, rtx cmp0, rtx cmp1)
3727 /* First see if there is a MIPS instruction that can do this operation
3728 with CMP1 in its current form. If not, try to canonicalize the
3729 comparison to LT. If that fails, try doing the same for the
3730 inverse operation. If that also fails, force CMP1 into a register
3732 if (mips_relational_operand_ok_p (code, cmp1))
3733 mips_emit_binary (code, target, cmp0, cmp1);
3734 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3735 mips_emit_binary (code, target, cmp0, cmp1);
3738 enum rtx_code inv_code = reverse_condition (code);
3739 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3741 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3742 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3744 else if (invert_ptr == 0)
3746 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3747 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3748 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3752 *invert_ptr = !*invert_ptr;
3753 mips_emit_binary (inv_code, target, cmp0, cmp1);
3758 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3759 The register will have the same mode as CMP0. */
3762 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3764 if (cmp1 == const0_rtx)
3767 if (uns_arith_operand (cmp1, VOIDmode))
3768 return expand_binop (GET_MODE (cmp0), xor_optab,
3769 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3771 return expand_binop (GET_MODE (cmp0), sub_optab,
3772 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3775 /* Convert *CODE into a code that can be used in a floating-point
3776 scc instruction (c.<cond>.<fmt>). Return true if the values of
3777 the condition code registers will be inverted, with 0 indicating
3778 that the condition holds. */
3781 mips_reverse_fp_cond_p (enum rtx_code *code)
3788 *code = reverse_condition_maybe_unordered (*code);
3796 /* Convert a comparison into something that can be used in a branch or
3797 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3798 being compared and *CODE is the code used to compare them.
3800 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3801 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3802 otherwise any standard branch condition can be used. The standard branch
3805 - EQ/NE between two registers.
3806 - any comparison between a register and zero. */
3809 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3811 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3813 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3815 *op0 = cmp_operands[0];
3816 *op1 = cmp_operands[1];
3818 else if (*code == EQ || *code == NE)
3822 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3827 *op0 = cmp_operands[0];
3828 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3833 /* The comparison needs a separate scc instruction. Store the
3834 result of the scc in *OP0 and compare it against zero. */
3835 bool invert = false;
3836 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3838 mips_emit_int_relational (*code, &invert, *op0,
3839 cmp_operands[0], cmp_operands[1]);
3840 *code = (invert ? EQ : NE);
3843 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
3845 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
3846 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
3852 enum rtx_code cmp_code;
3854 /* Floating-point tests use a separate c.cond.fmt comparison to
3855 set a condition code register. The branch or conditional move
3856 will then compare that register against zero.
3858 Set CMP_CODE to the code of the comparison instruction and
3859 *CODE to the code that the branch or move should use. */
3861 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3863 ? gen_reg_rtx (CCmode)
3864 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3866 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3870 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3871 Store the result in TARGET and return true if successful.
3873 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3876 mips_emit_scc (enum rtx_code code, rtx target)
3878 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3881 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3882 if (code == EQ || code == NE)
3884 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3885 mips_emit_binary (code, target, zie, const0_rtx);
3888 mips_emit_int_relational (code, 0, target,
3889 cmp_operands[0], cmp_operands[1]);
3893 /* Emit the common code for doing conditional branches.
3894 operand[0] is the label to jump to.
3895 The comparison operands are saved away by cmp{si,di,sf,df}. */
3898 gen_conditional_branch (rtx *operands, enum rtx_code code)
3900 rtx op0, op1, condition;
3902 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3903 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3904 emit_jump_insn (gen_condjump (condition, operands[0]));
3909 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3910 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3913 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3914 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3919 reversed_p = mips_reverse_fp_cond_p (&cond);
3920 cmp_result = gen_reg_rtx (CCV2mode);
3921 emit_insn (gen_scc_ps (cmp_result,
3922 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3924 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3927 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3931 /* Emit the common code for conditional moves. OPERANDS is the array
3932 of operands passed to the conditional move define_expand. */
3935 gen_conditional_move (rtx *operands)
3940 code = GET_CODE (operands[1]);
3941 mips_emit_compare (&code, &op0, &op1, true);
3942 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3943 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3944 gen_rtx_fmt_ee (code,
3947 operands[2], operands[3])));
3950 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3951 the conditional_trap expander. */
3954 mips_gen_conditional_trap (rtx *operands)
3957 enum rtx_code cmp_code = GET_CODE (operands[0]);
3958 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3960 /* MIPS conditional trap machine instructions don't have GT or LE
3961 flavors, so we must invert the comparison and convert to LT and
3962 GE, respectively. */
3965 case GT: cmp_code = LT; break;
3966 case LE: cmp_code = GE; break;
3967 case GTU: cmp_code = LTU; break;
3968 case LEU: cmp_code = GEU; break;
3971 if (cmp_code == GET_CODE (operands[0]))
3973 op0 = cmp_operands[0];
3974 op1 = cmp_operands[1];
3978 op0 = cmp_operands[1];
3979 op1 = cmp_operands[0];
3981 op0 = force_reg (mode, op0);
3982 if (!arith_operand (op1, mode))
3983 op1 = force_reg (mode, op1);
3985 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3986 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3990 /* Argument support functions. */
3992 /* Initialize CUMULATIVE_ARGS for a function. */
3995 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3996 rtx libname ATTRIBUTE_UNUSED)
3998 static CUMULATIVE_ARGS zero_cum;
3999 tree param, next_param;
4002 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4004 /* Determine if this function has variable arguments. This is
4005 indicated by the last argument being 'void_type_mode' if there
4006 are no variable arguments. The standard MIPS calling sequence
4007 passes all arguments in the general purpose registers in this case. */
4009 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
4010 param != 0; param = next_param)
4012 next_param = TREE_CHAIN (param);
4013 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
4014 cum->gp_reg_found = 1;
4019 /* Fill INFO with information about a single argument. CUM is the
4020 cumulative state for earlier arguments. MODE is the mode of this
4021 argument and TYPE is its type (if known). NAMED is true if this
4022 is a named (fixed) argument rather than a variable one. */
4025 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4026 tree type, int named, struct mips_arg_info *info)
4028 bool doubleword_aligned_p;
4029 unsigned int num_bytes, num_words, max_regs;
4031 /* Work out the size of the argument. */
4032 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4033 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4035 /* Decide whether it should go in a floating-point register, assuming
4036 one is free. Later code checks for availability.
4038 The checks against UNITS_PER_FPVALUE handle the soft-float and
4039 single-float cases. */
4043 /* The EABI conventions have traditionally been defined in terms
4044 of TYPE_MODE, regardless of the actual type. */
4045 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4046 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4047 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4052 /* Only leading floating-point scalars are passed in
4053 floating-point registers. We also handle vector floats the same
4054 say, which is OK because they are not covered by the standard ABI. */
4055 info->fpr_p = (!cum->gp_reg_found
4056 && cum->arg_number < 2
4057 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
4058 || VECTOR_FLOAT_TYPE_P (type))
4059 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4060 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4061 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4066 /* Scalar and complex floating-point types are passed in
4067 floating-point registers. */
4068 info->fpr_p = (named
4069 && (type == 0 || FLOAT_TYPE_P (type))
4070 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4071 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4072 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4073 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4075 /* ??? According to the ABI documentation, the real and imaginary
4076 parts of complex floats should be passed in individual registers.
4077 The real and imaginary parts of stack arguments are supposed
4078 to be contiguous and there should be an extra word of padding
4081 This has two problems. First, it makes it impossible to use a
4082 single "void *" va_list type, since register and stack arguments
4083 are passed differently. (At the time of writing, MIPSpro cannot
4084 handle complex float varargs correctly.) Second, it's unclear
4085 what should happen when there is only one register free.
4087 For now, we assume that named complex floats should go into FPRs
4088 if there are two FPRs free, otherwise they should be passed in the
4089 same way as a struct containing two floats. */
4091 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4092 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4094 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4095 info->fpr_p = false;
4105 /* See whether the argument has doubleword alignment. */
4106 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4108 /* Set REG_OFFSET to the register count we're interested in.
4109 The EABI allocates the floating-point registers separately,
4110 but the other ABIs allocate them like integer registers. */
4111 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4115 /* Advance to an even register if the argument is doubleword-aligned. */
4116 if (doubleword_aligned_p)
4117 info->reg_offset += info->reg_offset & 1;
4119 /* Work out the offset of a stack argument. */
4120 info->stack_offset = cum->stack_words;
4121 if (doubleword_aligned_p)
4122 info->stack_offset += info->stack_offset & 1;
4124 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4126 /* Partition the argument between registers and stack. */
4127 info->reg_words = MIN (num_words, max_regs);
4128 info->stack_words = num_words - info->reg_words;
4131 /* INFO describes an argument that is passed in a single-register value.
4132 Return the register it uses, assuming that FPRs are available if
4136 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4138 if (!info->fpr_p || !hard_float_p)
4139 return GP_ARG_FIRST + info->reg_offset;
4140 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4141 /* In o32, the second argument is always passed in $f14
4142 for TARGET_DOUBLE_FLOAT, regardless of whether the
4143 first argument was a word or doubleword. */
4144 return FP_ARG_FIRST + 2;
4146 return FP_ARG_FIRST + info->reg_offset;
4150 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4152 return !TARGET_OLDABI;
4155 /* Implement FUNCTION_ARG. */
4158 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4159 tree type, int named)
4161 struct mips_arg_info info;
4163 /* We will be called with a mode of VOIDmode after the last argument
4164 has been seen. Whatever we return will be passed to the call
4165 insn. If we need a mips16 fp_code, return a REG with the code
4166 stored as the mode. */
4167 if (mode == VOIDmode)
4169 if (TARGET_MIPS16 && cum->fp_code != 0)
4170 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4176 mips_arg_info (cum, mode, type, named, &info);
4178 /* Return straight away if the whole argument is passed on the stack. */
4179 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4183 && TREE_CODE (type) == RECORD_TYPE
4185 && TYPE_SIZE_UNIT (type)
4186 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4189 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4190 structure contains a double in its entirety, then that 64-bit
4191 chunk is passed in a floating point register. */
4194 /* First check to see if there is any such field. */
4195 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4196 if (TREE_CODE (field) == FIELD_DECL
4197 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4198 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4199 && host_integerp (bit_position (field), 0)
4200 && int_bit_position (field) % BITS_PER_WORD == 0)
4205 /* Now handle the special case by returning a PARALLEL
4206 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4207 chunks are passed in registers. */
4209 HOST_WIDE_INT bitpos;
4212 /* assign_parms checks the mode of ENTRY_PARM, so we must
4213 use the actual mode here. */
4214 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4217 field = TYPE_FIELDS (type);
4218 for (i = 0; i < info.reg_words; i++)
4222 for (; field; field = TREE_CHAIN (field))
4223 if (TREE_CODE (field) == FIELD_DECL
4224 && int_bit_position (field) >= bitpos)
4228 && int_bit_position (field) == bitpos
4229 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4230 && !TARGET_SOFT_FLOAT
4231 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4232 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4234 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4237 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4238 GEN_INT (bitpos / BITS_PER_UNIT));
4240 bitpos += BITS_PER_WORD;
4246 /* Handle the n32/n64 conventions for passing complex floating-point
4247 arguments in FPR pairs. The real part goes in the lower register
4248 and the imaginary part goes in the upper register. */
4251 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4254 enum machine_mode inner;
4257 inner = GET_MODE_INNER (mode);
4258 reg = FP_ARG_FIRST + info.reg_offset;
4259 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4261 /* Real part in registers, imaginary part on stack. */
4262 gcc_assert (info.stack_words == info.reg_words);
4263 return gen_rtx_REG (inner, reg);
4267 gcc_assert (info.stack_words == 0);
4268 real = gen_rtx_EXPR_LIST (VOIDmode,
4269 gen_rtx_REG (inner, reg),
4271 imag = gen_rtx_EXPR_LIST (VOIDmode,
4273 reg + info.reg_words / 2),
4274 GEN_INT (GET_MODE_SIZE (inner)));
4275 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4279 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4282 /* Implement FUNCTION_ARG_ADVANCE. */
4285 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4286 tree type, int named)
4288 struct mips_arg_info info;
4290 mips_arg_info (cum, mode, type, named, &info);
4293 cum->gp_reg_found = true;
4295 /* See the comment above the cumulative args structure in mips.h
4296 for an explanation of what this code does. It assumes the O32
4297 ABI, which passes at most 2 arguments in float registers. */
4298 if (cum->arg_number < 2 && info.fpr_p)
4299 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4301 if (mips_abi != ABI_EABI || !info.fpr_p)
4302 cum->num_gprs = info.reg_offset + info.reg_words;
4303 else if (info.reg_words > 0)
4304 cum->num_fprs += MAX_FPRS_PER_FMT;
4306 if (info.stack_words > 0)
4307 cum->stack_words = info.stack_offset + info.stack_words;
4312 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4315 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4316 enum machine_mode mode, tree type, bool named)
4318 struct mips_arg_info info;
4320 mips_arg_info (cum, mode, type, named, &info);
4321 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4325 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4326 PARM_BOUNDARY bits of alignment, but will be given anything up
4327 to STACK_BOUNDARY bits if the type requires it. */
4330 function_arg_boundary (enum machine_mode mode, tree type)
4332 unsigned int alignment;
4334 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4335 if (alignment < PARM_BOUNDARY)
4336 alignment = PARM_BOUNDARY;
4337 if (alignment > STACK_BOUNDARY)
4338 alignment = STACK_BOUNDARY;
4342 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4343 upward rather than downward. In other words, return true if the
4344 first byte of the stack slot has useful data, false if the last
4348 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4350 /* On little-endian targets, the first byte of every stack argument
4351 is passed in the first byte of the stack slot. */
4352 if (!BYTES_BIG_ENDIAN)
4355 /* Otherwise, integral types are padded downward: the last byte of a
4356 stack argument is passed in the last byte of the stack slot. */
4358 ? (INTEGRAL_TYPE_P (type)
4359 || POINTER_TYPE_P (type)
4360 || FIXED_POINT_TYPE_P (type))
4361 : (GET_MODE_CLASS (mode) == MODE_INT
4362 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4365 /* Big-endian o64 pads floating-point arguments downward. */
4366 if (mips_abi == ABI_O64)
4367 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4370 /* Other types are padded upward for o32, o64, n32 and n64. */
4371 if (mips_abi != ABI_EABI)
4374 /* Arguments smaller than a stack slot are padded downward. */
4375 if (mode != BLKmode)
4376 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4378 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4382 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4383 if the least significant byte of the register has useful data. Return
4384 the opposite if the most significant byte does. */
4387 mips_pad_reg_upward (enum machine_mode mode, tree type)
4389 /* No shifting is required for floating-point arguments. */
4390 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4391 return !BYTES_BIG_ENDIAN;
4393 /* Otherwise, apply the same padding to register arguments as we do
4394 to stack arguments. */
4395 return mips_pad_arg_upward (mode, type);
4399 /* Return nonzero when an argument must be passed by reference. */
4402 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4403 enum machine_mode mode, const_tree type,
4404 bool named ATTRIBUTE_UNUSED)
4406 if (mips_abi == ABI_EABI)
4410 /* ??? How should SCmode be handled? */
4411 if (mode == DImode || mode == DFmode
4412 || mode == DQmode || mode == UDQmode
4413 || mode == DAmode || mode == UDAmode)
4416 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4417 return size == -1 || size > UNITS_PER_WORD;
4421 /* If we have a variable-sized parameter, we have no choice. */
4422 return targetm.calls.must_pass_in_stack (mode, type);
4427 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4428 enum machine_mode mode ATTRIBUTE_UNUSED,
4429 const_tree type ATTRIBUTE_UNUSED, bool named)
4431 return mips_abi == ABI_EABI && named;
4434 /* See whether VALTYPE is a record whose fields should be returned in
4435 floating-point registers. If so, return the number of fields and
4436 list them in FIELDS (which should have two elements). Return 0
4439 For n32 & n64, a structure with one or two fields is returned in
4440 floating-point registers as long as every field has a floating-point
4444 mips_fpr_return_fields (const_tree valtype, tree *fields)
4452 if (TREE_CODE (valtype) != RECORD_TYPE)
4456 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4458 if (TREE_CODE (field) != FIELD_DECL)
4461 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
4467 fields[i++] = field;
4473 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4474 a value in the most significant part of $2/$3 if:
4476 - the target is big-endian;
4478 - the value has a structure or union type (we generalize this to
4479 cover aggregates from other languages too); and
4481 - the structure is not returned in floating-point registers. */
4484 mips_return_in_msb (const_tree valtype)
4488 return (TARGET_NEWABI
4489 && TARGET_BIG_ENDIAN
4490 && AGGREGATE_TYPE_P (valtype)
4491 && mips_fpr_return_fields (valtype, fields) == 0);
4495 /* Return true if the function return value MODE will get returned in a
4496 floating-point register. */
4499 mips_return_mode_in_fpr_p (enum machine_mode mode)
4501 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4502 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4503 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4504 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4507 /* Return a composite value in a pair of floating-point registers.
4508 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4509 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4512 For n32 & n64, $f0 always holds the first value and $f2 the second.
4513 Otherwise the values are packed together as closely as possible. */
4516 mips_return_fpr_pair (enum machine_mode mode,
4517 enum machine_mode mode1, HOST_WIDE_INT offset1,
4518 enum machine_mode mode2, HOST_WIDE_INT offset2)
4522 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4523 return gen_rtx_PARALLEL
4526 gen_rtx_EXPR_LIST (VOIDmode,
4527 gen_rtx_REG (mode1, FP_RETURN),
4529 gen_rtx_EXPR_LIST (VOIDmode,
4530 gen_rtx_REG (mode2, FP_RETURN + inc),
4531 GEN_INT (offset2))));
4536 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4537 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4538 VALTYPE is null and MODE is the mode of the return value. */
4541 mips_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
4542 enum machine_mode mode)
4549 mode = TYPE_MODE (valtype);
4550 unsignedp = TYPE_UNSIGNED (valtype);
4552 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
4553 true, we must promote the mode just as PROMOTE_MODE does. */
4554 mode = promote_mode (valtype, mode, &unsignedp, 1);
4556 /* Handle structures whose fields are returned in $f0/$f2. */
4557 switch (mips_fpr_return_fields (valtype, fields))
4560 return gen_rtx_REG (mode, FP_RETURN);
4563 return mips_return_fpr_pair (mode,
4564 TYPE_MODE (TREE_TYPE (fields[0])),
4565 int_byte_position (fields[0]),
4566 TYPE_MODE (TREE_TYPE (fields[1])),
4567 int_byte_position (fields[1]));
4570 /* If a value is passed in the most significant part of a register, see
4571 whether we have to round the mode up to a whole number of words. */
4572 if (mips_return_in_msb (valtype))
4574 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4575 if (size % UNITS_PER_WORD != 0)
4577 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4578 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4582 /* For EABI, the class of return register depends entirely on MODE.
4583 For example, "struct { some_type x; }" and "union { some_type x; }"
4584 are returned in the same way as a bare "some_type" would be.
4585 Other ABIs only use FPRs for scalar, complex or vector types. */
4586 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4587 return gen_rtx_REG (mode, GP_RETURN);
4592 /* Handle long doubles for n32 & n64. */
4594 return mips_return_fpr_pair (mode,
4596 DImode, GET_MODE_SIZE (mode) / 2);
4598 if (mips_return_mode_in_fpr_p (mode))
4600 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4601 return mips_return_fpr_pair (mode,
4602 GET_MODE_INNER (mode), 0,
4603 GET_MODE_INNER (mode),
4604 GET_MODE_SIZE (mode) / 2);
4606 return gen_rtx_REG (mode, FP_RETURN);
4610 return gen_rtx_REG (mode, GP_RETURN);
4613 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
4614 all BLKmode objects are returned in memory. Under the new (N32 and
4615 64-bit MIPS ABIs) small structures are returned in a register.
4616 Objects with varying size must still be returned in memory, of
4620 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4623 return (TYPE_MODE (type) == BLKmode);
4625 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
4626 || (int_size_in_bytes (type) == -1));
4630 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4631 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4634 CUMULATIVE_ARGS local_cum;
4635 int gp_saved, fp_saved;
4637 /* The caller has advanced CUM up to, but not beyond, the last named
4638 argument. Advance a local copy of CUM past the last "real" named
4639 argument, to find out how many registers are left over. */
4642 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4644 /* Found out how many registers we need to save. */
4645 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4646 fp_saved = (EABI_FLOAT_VARARGS_P
4647 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4656 ptr = plus_constant (virtual_incoming_args_rtx,
4657 REG_PARM_STACK_SPACE (cfun->decl)
4658 - gp_saved * UNITS_PER_WORD);
4659 mem = gen_rtx_MEM (BLKmode, ptr);
4660 set_mem_alias_set (mem, get_varargs_alias_set ());
4662 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4667 /* We can't use move_block_from_reg, because it will use
4669 enum machine_mode mode;
4672 /* Set OFF to the offset from virtual_incoming_args_rtx of
4673 the first float register. The FP save area lies below
4674 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4675 off = -gp_saved * UNITS_PER_WORD;
4676 off &= ~(UNITS_PER_FPVALUE - 1);
4677 off -= fp_saved * UNITS_PER_FPREG;
4679 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4681 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4682 i += MAX_FPRS_PER_FMT)
4686 ptr = plus_constant (virtual_incoming_args_rtx, off);
4687 mem = gen_rtx_MEM (mode, ptr);
4688 set_mem_alias_set (mem, get_varargs_alias_set ());
4689 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4690 off += UNITS_PER_HWFPVALUE;
4694 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4695 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4696 + fp_saved * UNITS_PER_FPREG);
4699 /* Create the va_list data type.
4700 We keep 3 pointers, and two offsets.
4701 Two pointers are to the overflow area, which starts at the CFA.
4702 One of these is constant, for addressing into the GPR save area below it.
4703 The other is advanced up the stack through the overflow region.
4704 The third pointer is to the GPR save area. Since the FPR save area
4705 is just below it, we can address FPR slots off this pointer.
4706 We also keep two one-byte offsets, which are to be subtracted from the
4707 constant pointers to yield addresses in the GPR and FPR save areas.
4708 These are downcounted as float or non-float arguments are used,
4709 and when they get to zero, the argument must be obtained from the
4711 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4712 pointer is enough. It's started at the GPR save area, and is
4714 Note that the GPR save area is not constant size, due to optimization
4715 in the prologue. Hence, we can't use a design with two pointers
4716 and two offsets, although we could have designed this with two pointers
4717 and three offsets. */
4720 mips_build_builtin_va_list (void)
4722 if (EABI_FLOAT_VARARGS_P)
4724 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4727 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4729 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4731 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4733 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4735 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4736 unsigned_char_type_node);
4737 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4738 unsigned_char_type_node);
4739 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4740 warn on every user file. */
4741 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4742 array = build_array_type (unsigned_char_type_node,
4743 build_index_type (index));
4744 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4746 DECL_FIELD_CONTEXT (f_ovfl) = record;
4747 DECL_FIELD_CONTEXT (f_gtop) = record;
4748 DECL_FIELD_CONTEXT (f_ftop) = record;
4749 DECL_FIELD_CONTEXT (f_goff) = record;
4750 DECL_FIELD_CONTEXT (f_foff) = record;
4751 DECL_FIELD_CONTEXT (f_res) = record;
4753 TYPE_FIELDS (record) = f_ovfl;
4754 TREE_CHAIN (f_ovfl) = f_gtop;
4755 TREE_CHAIN (f_gtop) = f_ftop;
4756 TREE_CHAIN (f_ftop) = f_goff;
4757 TREE_CHAIN (f_goff) = f_foff;
4758 TREE_CHAIN (f_foff) = f_res;
4760 layout_type (record);
4763 else if (TARGET_IRIX && TARGET_IRIX6)
4764 /* On IRIX 6, this type is 'char *'. */
4765 return build_pointer_type (char_type_node);
4767 /* Otherwise, we use 'void *'. */
4768 return ptr_type_node;
4771 /* Implement va_start. */
4774 mips_va_start (tree valist, rtx nextarg)
4776 if (EABI_FLOAT_VARARGS_P)
4778 const CUMULATIVE_ARGS *cum;
4779 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4780 tree ovfl, gtop, ftop, goff, foff;
4782 int gpr_save_area_size;
4783 int fpr_save_area_size;
4786 cum = ¤t_function_args_info;
4788 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4790 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4792 f_ovfl = TYPE_FIELDS (va_list_type_node);
4793 f_gtop = TREE_CHAIN (f_ovfl);
4794 f_ftop = TREE_CHAIN (f_gtop);
4795 f_goff = TREE_CHAIN (f_ftop);
4796 f_foff = TREE_CHAIN (f_goff);
4798 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4800 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4802 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4804 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4806 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4809 /* Emit code to initialize OVFL, which points to the next varargs
4810 stack argument. CUM->STACK_WORDS gives the number of stack
4811 words used by named arguments. */
4812 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4813 if (cum->stack_words > 0)
4814 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4815 size_int (cum->stack_words * UNITS_PER_WORD));
4816 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4817 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4819 /* Emit code to initialize GTOP, the top of the GPR save area. */
4820 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4821 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4822 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4824 /* Emit code to initialize FTOP, the top of the FPR save area.
4825 This address is gpr_save_area_bytes below GTOP, rounded
4826 down to the next fp-aligned boundary. */
4827 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4828 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4829 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4831 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4832 size_int (-fpr_offset));
4833 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4834 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4836 /* Emit code to initialize GOFF, the offset from GTOP of the
4837 next GPR argument. */
4838 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4839 build_int_cst (NULL_TREE, gpr_save_area_size));
4840 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4842 /* Likewise emit code to initialize FOFF, the offset from FTOP
4843 of the next FPR argument. */
4844 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4845 build_int_cst (NULL_TREE, fpr_save_area_size));
4846 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4850 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4851 std_expand_builtin_va_start (valist, nextarg);
4855 /* Implement va_arg. */
4858 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4860 HOST_WIDE_INT size, rsize;
4864 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4867 type = build_pointer_type (type);
4869 size = int_size_in_bytes (type);
4870 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4872 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4873 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4876 /* Not a simple merged stack. */
4878 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4879 tree ovfl, top, off, align;
4880 HOST_WIDE_INT osize;
4883 f_ovfl = TYPE_FIELDS (va_list_type_node);
4884 f_gtop = TREE_CHAIN (f_ovfl);
4885 f_ftop = TREE_CHAIN (f_gtop);
4886 f_goff = TREE_CHAIN (f_ftop);
4887 f_foff = TREE_CHAIN (f_goff);
4889 /* We maintain separate pointers and offsets for floating-point
4890 and integer arguments, but we need similar code in both cases.
4893 TOP be the top of the register save area;
4894 OFF be the offset from TOP of the next register;
4895 ADDR_RTX be the address of the argument;
4896 RSIZE be the number of bytes used to store the argument
4897 when it's in the register save area;
4898 OSIZE be the number of bytes used to store it when it's
4899 in the stack overflow area; and
4900 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4902 The code we want is:
4904 1: off &= -rsize; // round down
4907 4: addr_rtx = top - off;
4912 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4913 10: addr_rtx = ovfl + PADDING;
4917 [1] and [9] can sometimes be optimized away. */
4919 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4922 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4923 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4925 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4927 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4930 /* When floating-point registers are saved to the stack,
4931 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4932 of the float's precision. */
4933 rsize = UNITS_PER_HWFPVALUE;
4935 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4936 (= PARM_BOUNDARY bits). This can be different from RSIZE
4939 (1) On 32-bit targets when TYPE is a structure such as:
4941 struct s { float f; };
4943 Such structures are passed in paired FPRs, so RSIZE
4944 will be 8 bytes. However, the structure only takes
4945 up 4 bytes of memory, so OSIZE will only be 4.
4947 (2) In combinations such as -mgp64 -msingle-float
4948 -fshort-double. Doubles passed in registers
4949 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4950 but those passed on the stack take up
4951 UNITS_PER_WORD bytes. */
4952 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4956 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4958 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4960 if (rsize > UNITS_PER_WORD)
4962 /* [1] Emit code for: off &= -rsize. */
4963 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4964 build_int_cst (NULL_TREE, -rsize));
4965 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4966 gimplify_and_add (t, pre_p);
4971 /* [2] Emit code to branch if off == 0. */
4972 t = build2 (NE_EXPR, boolean_type_node, off,
4973 build_int_cst (TREE_TYPE (off), 0));
4974 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4976 /* [5] Emit code for: off -= rsize. We do this as a form of
4977 post-increment not available to C. Also widen for the
4978 coming pointer arithmetic. */
4979 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4980 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4981 t = fold_convert (sizetype, t);
4982 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4984 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4985 the argument has RSIZE - SIZE bytes of leading padding. */
4986 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4987 if (BYTES_BIG_ENDIAN && rsize > size)
4989 u = size_int (rsize - size);
4990 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4992 COND_EXPR_THEN (addr) = t;
4994 if (osize > UNITS_PER_WORD)
4996 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4997 u = size_int (osize - 1);
4998 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4999 t = fold_convert (sizetype, t);
5000 u = size_int (-osize);
5001 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5002 t = fold_convert (TREE_TYPE (ovfl), t);
5003 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
5008 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
5009 post-increment ovfl by osize. On big-endian machines,
5010 the argument has OSIZE - SIZE bytes of leading padding. */
5011 u = fold_convert (TREE_TYPE (ovfl),
5012 build_int_cst (NULL_TREE, osize));
5013 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5014 if (BYTES_BIG_ENDIAN && osize > size)
5016 u = size_int (osize - size);
5017 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5020 /* String [9] and [10,11] together. */
5022 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5023 COND_EXPR_ELSE (addr) = t;
5025 addr = fold_convert (build_pointer_type (type), addr);
5026 addr = build_va_arg_indirect_ref (addr);
5030 addr = build_va_arg_indirect_ref (addr);
5035 /* We keep a list of functions for which we have already built stubs
5036 in build_mips16_call_stub. */
5040 struct mips16_stub *next;
5045 static struct mips16_stub *mips16_stubs;
5047 /* Return a two-character string representing a function floating-point
5048 return mode, used to name MIPS16 function stubs. */
5051 mips16_call_stub_mode_suffix (enum machine_mode mode)
5055 else if (mode == DFmode)
5057 else if (mode == SCmode)
5059 else if (mode == DCmode)
5061 else if (mode == V2SFmode)
5067 /* Write instructions to move a 32-bit value between general register
5068 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5069 from GPREG to FPREG and 'f' to move in the opposite direction. */
5072 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5074 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5075 reg_names[gpreg], reg_names[fpreg]);
5078 /* Likewise for 64-bit values. */
5081 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5084 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5085 reg_names[gpreg], reg_names[fpreg]);
5086 else if (TARGET_FLOAT64)
5088 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5089 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5090 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5091 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5095 /* Move the least-significant word. */
5096 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5097 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5098 /* ...then the most significant word. */
5099 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5100 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5104 /* Write out code to move floating-point arguments into or out of
5105 general registers. FP_CODE is the code describing which arguments
5106 are present (see the comment above the definition of CUMULATIVE_ARGS
5107 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5110 mips_output_args_xfer (int fp_code, char direction)
5112 unsigned int gparg, fparg, f;
5113 CUMULATIVE_ARGS cum;
5115 /* This code only works for the original 32-bit ABI and the O64 ABI. */
5116 gcc_assert (TARGET_OLDABI);
5118 init_cumulative_args (&cum, NULL, NULL);
5120 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5122 enum machine_mode mode;
5123 struct mips_arg_info info;
5127 else if ((f & 3) == 2)
5132 mips_arg_info (&cum, mode, NULL, true, &info);
5133 gparg = mips_arg_regno (&info, false);
5134 fparg = mips_arg_regno (&info, true);
5137 mips_output_32bit_xfer (direction, gparg, fparg);
5139 mips_output_64bit_xfer (direction, gparg, fparg);
5141 function_arg_advance (&cum, mode, NULL, true);
5145 /* Build a mips16 function stub. This is used for functions which
5146 take arguments in the floating point registers. It is 32-bit code
5147 that moves the floating point args into the general registers, and
5148 then jumps to the 16-bit code. */
5151 build_mips16_function_stub (void)
5154 char *secname, *stubname;
5155 tree stubid, stubdecl;
5159 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5160 fnname = targetm.strip_name_encoding (fnname);
5161 secname = (char *) alloca (strlen (fnname) + 20);
5162 sprintf (secname, ".mips16.fn.%s", fnname);
5163 stubname = (char *) alloca (strlen (fnname) + 20);
5164 sprintf (stubname, "__fn_stub_%s", fnname);
5165 stubid = get_identifier (stubname);
5166 stubdecl = build_decl (FUNCTION_DECL, stubid,
5167 build_function_type (void_type_node, NULL_TREE));
5168 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5169 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5171 fprintf (asm_out_file, "\t# Stub function for %s (",
5172 current_function_name ());
5174 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
5176 fprintf (asm_out_file, "%s%s",
5177 need_comma ? ", " : "",
5178 (f & 3) == 1 ? "float" : "double");
5181 fprintf (asm_out_file, ")\n");
5183 fprintf (asm_out_file, "\t.set\tnomips16\n");
5184 switch_to_section (function_section (stubdecl));
5185 ASM_OUTPUT_ALIGN (asm_out_file,
5186 floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
5188 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5189 within a .ent, and we cannot emit another .ent. */
5190 if (!FUNCTION_NAME_ALREADY_DECLARED)
5192 fputs ("\t.ent\t", asm_out_file);
5193 assemble_name (asm_out_file, stubname);
5194 fputs ("\n", asm_out_file);
5197 assemble_name (asm_out_file, stubname);
5198 fputs (":\n", asm_out_file);
5200 /* Load the address of the MIPS16 function into $at. Do this first so
5201 that targets with coprocessor interlocks can use an MFC1 to fill the
5203 fprintf (asm_out_file, "\t.set\tnoat\n");
5204 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
5205 assemble_name (asm_out_file, fnname);
5206 fprintf (asm_out_file, "\n");
5208 mips_output_args_xfer (current_function_args_info.fp_code, 'f');
5210 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5211 fprintf (asm_out_file, "\t.set\tat\n");
5213 if (!FUNCTION_NAME_ALREADY_DECLARED)
5215 fputs ("\t.end\t", asm_out_file);
5216 assemble_name (asm_out_file, stubname);
5217 fputs ("\n", asm_out_file);
5220 switch_to_section (function_section (current_function_decl));
5223 /* The current function is a MIPS16 function that returns a value in an FPR.
5224 Copy the return value from its soft-float to its hard-float location.
5225 libgcc2 has special non-MIPS16 helper functions for each case. */
5228 mips16_copy_fpr_return_value (void)
5230 rtx fn, insn, arg, call;
5231 tree id, return_type;
5232 enum machine_mode return_mode;
5234 return_type = DECL_RESULT (current_function_decl);
5235 return_mode = DECL_MODE (return_type);
5237 id = get_identifier (ACONCAT (("__mips16_ret_",
5238 mips16_call_stub_mode_suffix (return_mode),
5240 fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5241 arg = gen_rtx_REG (return_mode, GP_RETURN);
5242 call = gen_call_value_internal (arg, fn, const0_rtx);
5243 insn = emit_call_insn (call);
5244 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
5247 /* Build a call stub for a mips16 call. A stub is needed if we are
5248 passing any floating point values which should go into the floating
5249 point registers. If we are, and the call turns out to be to a
5250 32-bit function, the stub will be used to move the values into the
5251 floating point registers before calling the 32-bit function. The
5252 linker will magically adjust the function call to either the 16-bit
5253 function or the 32-bit stub, depending upon where the function call
5254 is actually defined.
5256 Similarly, we need a stub if the return value might come back in a
5257 floating point register.
5259 RETVAL is the location of the return value, or null if this is
5260 a call rather than a call_value. FN is the address of the
5261 function and ARG_SIZE is the size of the arguments. FP_CODE
5262 is the code built by function_arg. This function returns a nonzero
5263 value if it builds the call instruction itself. */
5266 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
5270 char *secname, *stubname;
5271 struct mips16_stub *l;
5272 tree stubid, stubdecl;
5277 /* We don't need to do anything if we aren't in mips16 mode, or if
5278 we were invoked with the -msoft-float option. */
5279 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5282 /* Figure out whether the value might come back in a floating point
5285 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
5287 /* We don't need to do anything if there were no floating point
5288 arguments and the value will not be returned in a floating point
5290 if (fp_code == 0 && ! fpret)
5293 /* We don't need to do anything if this is a call to a special
5294 mips16 support function. */
5295 if (GET_CODE (fn) == SYMBOL_REF
5296 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
5299 /* This code will only work for o32 and o64 abis. The other ABI's
5300 require more sophisticated support. */
5301 gcc_assert (TARGET_OLDABI);
5303 /* If we're calling via a function pointer, then we must always call
5304 via a stub. There are magic stubs provided in libgcc.a for each
5305 of the required cases. Each of them expects the function address
5306 to arrive in register $2. */
5308 if (GET_CODE (fn) != SYMBOL_REF)
5314 /* ??? If this code is modified to support other ABI's, we need
5315 to handle PARALLEL return values here. */
5318 sprintf (buf, "__mips16_call_stub_%s_%d",
5319 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5322 sprintf (buf, "__mips16_call_stub_%d",
5325 id = get_identifier (buf);
5326 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5328 mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
5330 if (retval == NULL_RTX)
5331 insn = gen_call_internal (stub_fn, arg_size);
5333 insn = gen_call_value_internal (retval, stub_fn, arg_size);
5334 insn = emit_call_insn (insn);
5336 /* Put the register usage information on the CALL. */
5337 CALL_INSN_FUNCTION_USAGE (insn) =
5338 gen_rtx_EXPR_LIST (VOIDmode,
5339 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
5340 CALL_INSN_FUNCTION_USAGE (insn));
5342 /* If we are handling a floating point return value, we need to
5343 save $18 in the function prologue. Putting a note on the
5344 call will mean that df_regs_ever_live_p ($18) will be true if the
5345 call is not eliminated, and we can check that in the prologue
5348 CALL_INSN_FUNCTION_USAGE (insn) =
5349 gen_rtx_EXPR_LIST (VOIDmode,
5350 gen_rtx_USE (VOIDmode,
5351 gen_rtx_REG (word_mode, 18)),
5352 CALL_INSN_FUNCTION_USAGE (insn));
5354 /* Return 1 to tell the caller that we've generated the call
5359 /* We know the function we are going to call. If we have already
5360 built a stub, we don't need to do anything further. */
5362 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5363 for (l = mips16_stubs; l != NULL; l = l->next)
5364 if (strcmp (l->name, fnname) == 0)
5369 /* Build a special purpose stub. When the linker sees a
5370 function call in mips16 code, it will check where the target
5371 is defined. If the target is a 32-bit call, the linker will
5372 search for the section defined here. It can tell which
5373 symbol this section is associated with by looking at the
5374 relocation information (the name is unreliable, since this
5375 might be a static function). If such a section is found, the
5376 linker will redirect the call to the start of the magic
5379 If the function does not return a floating point value, the
5380 special stub section is named
5383 If the function does return a floating point value, the stub
5385 .mips16.call.fp.FNNAME
5388 secname = (char *) alloca (strlen (fnname) + 40);
5389 sprintf (secname, ".mips16.call.%s%s",
5392 stubname = (char *) alloca (strlen (fnname) + 20);
5393 sprintf (stubname, "__call_stub_%s%s",
5396 stubid = get_identifier (stubname);
5397 stubdecl = build_decl (FUNCTION_DECL, stubid,
5398 build_function_type (void_type_node, NULL_TREE));
5399 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5400 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5402 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5404 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5408 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5410 fprintf (asm_out_file, "%s%s",
5411 need_comma ? ", " : "",
5412 (f & 3) == 1 ? "float" : "double");
5415 fprintf (asm_out_file, ")\n");
5417 fprintf (asm_out_file, "\t.set\tnomips16\n");
5418 assemble_start_function (stubdecl, stubname);
5420 if (!FUNCTION_NAME_ALREADY_DECLARED)
5422 fputs ("\t.ent\t", asm_out_file);
5423 assemble_name (asm_out_file, stubname);
5424 fputs ("\n", asm_out_file);
5426 assemble_name (asm_out_file, stubname);
5427 fputs (":\n", asm_out_file);
5430 /* We build the stub code by hand. That's the only way we can
5431 do it, since we can't generate 32-bit code during a 16-bit
5436 /* Load the address of the MIPS16 function into $at. Do this
5437 first so that targets with coprocessor interlocks can use
5438 an MFC1 to fill the delay slot. */
5439 fprintf (asm_out_file, "\t.set\tnoat\n");
5440 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
5444 mips_output_args_xfer (fp_code, 't');
5448 /* Jump to the previously-loaded address. */
5449 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5450 fprintf (asm_out_file, "\t.set\tat\n");
5454 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5455 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5456 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
5457 switch (GET_MODE (retval))
5460 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5461 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5464 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5465 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5467 /* On 64-bit targets, complex floats are returned in
5468 a single GPR, such that "sd" on a suitably-aligned
5469 target would store the value correctly. */
5470 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5471 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5472 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5473 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5474 reg_names[GP_RETURN],
5475 reg_names[GP_RETURN],
5476 reg_names[GP_RETURN + 1]);
5481 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
5482 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5486 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5492 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
5495 #ifdef ASM_DECLARE_FUNCTION_SIZE
5496 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
5499 if (!FUNCTION_NAME_ALREADY_DECLARED)
5501 fputs ("\t.end\t", asm_out_file);
5502 assemble_name (asm_out_file, stubname);
5503 fputs ("\n", asm_out_file);
5506 /* Record this stub. */
5507 l = (struct mips16_stub *) xmalloc (sizeof *l);
5508 l->name = xstrdup (fnname);
5510 l->next = mips16_stubs;
5514 /* If we expect a floating point return value, but we've built a
5515 stub which does not expect one, then we're in trouble. We can't
5516 use the existing stub, because it won't handle the floating point
5517 value. We can't build a new stub, because the linker won't know
5518 which stub to use for the various calls in this object file.
5519 Fortunately, this case is illegal, since it means that a function
5520 was declared in two different ways in a single compilation. */
5521 if (fpret && ! l->fpret)
5522 error ("cannot handle inconsistent calls to %qs", fnname);
5524 if (retval == NULL_RTX)
5525 insn = gen_call_internal_direct (fn, arg_size);
5527 insn = gen_call_value_internal_direct (retval, fn, arg_size);
5528 insn = emit_call_insn (insn);
5530 /* If we are calling a stub which handles a floating point return
5531 value, we need to arrange to save $18 in the prologue. We do
5532 this by marking the function call as using the register. The
5533 prologue will later see that it is used, and emit code to save
5536 CALL_INSN_FUNCTION_USAGE (insn) =
5537 gen_rtx_EXPR_LIST (VOIDmode,
5538 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
5539 CALL_INSN_FUNCTION_USAGE (insn));
5541 /* Return 1 to tell the caller that we've generated the call
5546 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5549 mips_ok_for_lazy_binding_p (rtx x)
5551 return (TARGET_USE_GOT
5552 && GET_CODE (x) == SYMBOL_REF
5553 && !mips_symbol_binds_local_p (x));
5556 /* Load function address ADDR into register DEST. SIBCALL_P is true
5557 if the address is needed for a sibling call. Return true if we
5558 used an explicit lazy-binding sequence. */
5561 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
5563 /* If we're generating PIC, and this call is to a global function,
5564 try to allow its address to be resolved lazily. This isn't
5565 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
5566 to the stub would be our caller's gp, not ours. */
5567 if (TARGET_EXPLICIT_RELOCS
5568 && !(sibcall_p && TARGET_CALL_SAVED_GP)
5569 && mips_ok_for_lazy_binding_p (addr))
5571 rtx high, lo_sum_symbol;
5573 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
5574 addr, SYMBOL_GOTOFF_CALL);
5575 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
5576 if (Pmode == SImode)
5577 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
5579 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
5584 mips_emit_move (dest, addr);
5590 /* Expand a call or call_value instruction. RESULT is where the
5591 result will go (null for calls), ADDR is the address of the
5592 function, ARGS_SIZE is the size of the arguments and AUX is
5593 the value passed to us by mips_function_arg. SIBCALL_P is true
5594 if we are expanding a sibling call, false if we're expanding
5598 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
5600 rtx orig_addr, pattern, insn;
5605 if (!call_insn_operand (addr, VOIDmode))
5607 addr = gen_reg_rtx (Pmode);
5608 lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
5612 && TARGET_HARD_FLOAT_ABI
5613 && build_mips16_call_stub (result, addr, args_size,
5614 aux == 0 ? 0 : (int) GET_MODE (aux)))
5618 pattern = (sibcall_p
5619 ? gen_sibcall_internal (addr, args_size)
5620 : gen_call_internal (addr, args_size));
5621 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
5625 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
5626 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
5629 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
5630 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
5633 pattern = (sibcall_p
5634 ? gen_sibcall_value_internal (result, addr, args_size)
5635 : gen_call_value_internal (result, addr, args_size));
5637 insn = emit_call_insn (pattern);
5639 /* Lazy-binding stubs require $gp to be valid on entry. We also pretend
5640 that they use FAKE_CALL_REGNO; see the load_call<mode> patterns for
5644 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
5645 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
5646 gen_rtx_REG (Pmode, FAKE_CALL_REGNO));
5651 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5654 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5656 if (!TARGET_SIBCALLS)
5659 /* We can't do a sibcall if the called function is a MIPS16 function
5660 because there is no direct "jx" instruction equivalent to "jalx" to
5661 switch the ISA mode. */
5662 if (mips_use_mips16_mode_p (decl))
5665 /* ...and when -minterlink-mips16 is in effect, assume that external
5666 functions could be MIPS16 ones unless an attribute explicitly
5667 tells us otherwise. We only care about cases where the sibling
5668 and normal calls would both be direct. */
5669 if (TARGET_INTERLINK_MIPS16
5671 && DECL_EXTERNAL (decl)
5672 && !mips_nomips16_decl_p (decl)
5673 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5680 /* Emit code to move general operand SRC into condition-code
5681 register DEST. SCRATCH is a scratch TFmode float register.
5688 where FP1 and FP2 are single-precision float registers
5689 taken from SCRATCH. */
5692 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
5696 /* Change the source to SFmode. */
5698 src = adjust_address (src, SFmode, 0);
5699 else if (REG_P (src) || GET_CODE (src) == SUBREG)
5700 src = gen_rtx_REG (SFmode, true_regnum (src));
5702 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
5703 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
5705 mips_emit_move (copy_rtx (fp1), src);
5706 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
5707 emit_insn (gen_slt_sf (dest, fp2, fp1));
5710 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5711 Assume that the areas do not overlap. */
5714 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
5716 HOST_WIDE_INT offset, delta;
5717 unsigned HOST_WIDE_INT bits;
5719 enum machine_mode mode;
5722 /* Work out how many bits to move at a time. If both operands have
5723 half-word alignment, it is usually better to move in half words.
5724 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5725 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5726 Otherwise move word-sized chunks. */
5727 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
5728 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
5729 bits = BITS_PER_WORD / 2;
5731 bits = BITS_PER_WORD;
5733 mode = mode_for_size (bits, MODE_INT, 0);
5734 delta = bits / BITS_PER_UNIT;
5736 /* Allocate a buffer for the temporary registers. */
5737 regs = alloca (sizeof (rtx) * length / delta);
5739 /* Load as many BITS-sized chunks as possible. Use a normal load if
5740 the source has enough alignment, otherwise use left/right pairs. */
5741 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5743 regs[i] = gen_reg_rtx (mode);
5744 if (MEM_ALIGN (src) >= bits)
5745 mips_emit_move (regs[i], adjust_address (src, mode, offset));
5748 rtx part = adjust_address (src, BLKmode, offset);
5749 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
5754 /* Copy the chunks to the destination. */
5755 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5756 if (MEM_ALIGN (dest) >= bits)
5757 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
5760 rtx part = adjust_address (dest, BLKmode, offset);
5761 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
5765 /* Mop up any left-over bytes. */
5766 if (offset < length)
5768 src = adjust_address (src, BLKmode, offset);
5769 dest = adjust_address (dest, BLKmode, offset);
5770 move_by_pieces (dest, src, length - offset,
5771 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
5775 #define MAX_MOVE_REGS 4
5776 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
5779 /* Helper function for doing a loop-based block operation on memory
5780 reference MEM. Each iteration of the loop will operate on LENGTH
5783 Create a new base register for use within the loop and point it to
5784 the start of MEM. Create a new memory reference that uses this
5785 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5788 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
5789 rtx *loop_reg, rtx *loop_mem)
5791 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
5793 /* Although the new mem does not refer to a known location,
5794 it does keep up to LENGTH bytes of alignment. */
5795 *loop_mem = change_address (mem, BLKmode, *loop_reg);
5796 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
5800 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
5801 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
5802 memory regions do not overlap. */
5805 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
5807 rtx label, src_reg, dest_reg, final_src;
5808 HOST_WIDE_INT leftover;
5810 leftover = length % MAX_MOVE_BYTES;
5813 /* Create registers and memory references for use within the loop. */
5814 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
5815 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
5817 /* Calculate the value that SRC_REG should have after the last iteration
5819 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
5822 /* Emit the start of the loop. */
5823 label = gen_label_rtx ();
5826 /* Emit the loop body. */
5827 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
5829 /* Move on to the next block. */
5830 mips_emit_move (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
5831 mips_emit_move (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
5833 /* Emit the loop condition. */
5834 if (Pmode == DImode)
5835 emit_insn (gen_cmpdi (src_reg, final_src));
5837 emit_insn (gen_cmpsi (src_reg, final_src));
5838 emit_jump_insn (gen_bne (label));
5840 /* Mop up any left-over bytes. */
5842 mips_block_move_straight (dest, src, leftover);
5845 /* Expand a movmemsi instruction. */
5848 mips_expand_block_move (rtx dest, rtx src, rtx length)
5850 if (GET_CODE (length) == CONST_INT)
5852 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
5854 mips_block_move_straight (dest, src, INTVAL (length));
5859 mips_block_move_loop (dest, src, INTVAL (length));
5867 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5870 mips_expand_synci_loop (rtx begin, rtx end)
5872 rtx inc, label, cmp, cmp_result;
5874 /* Load INC with the cache line size (rdhwr INC,$1). */
5875 inc = gen_reg_rtx (SImode);
5876 emit_insn (gen_rdhwr (inc, const1_rtx));
5878 /* Loop back to here. */
5879 label = gen_label_rtx ();
5882 emit_insn (gen_synci (begin));
5884 cmp = gen_reg_rtx (Pmode);
5885 mips_emit_binary (GTU, cmp, begin, end);
5887 mips_emit_binary (PLUS, begin, begin, inc);
5889 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
5890 emit_jump_insn (gen_condjump (cmp_result, label));
5893 /* Return true if it is possible to use left/right accesses for a
5894 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5895 returning true, update *OP, *LEFT and *RIGHT as follows:
5897 *OP is a BLKmode reference to the whole field.
5899 *LEFT is a QImode reference to the first byte if big endian or
5900 the last byte if little endian. This address can be used in the
5901 left-side instructions (lwl, swl, ldl, sdl).
5903 *RIGHT is a QImode reference to the opposite end of the field and
5904 can be used in the patterning right-side instruction. */
5907 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
5908 rtx *left, rtx *right)
5912 /* Check that the operand really is a MEM. Not all the extv and
5913 extzv predicates are checked. */
5917 /* Check that the size is valid. */
5918 if (width != 32 && (!TARGET_64BIT || width != 64))
5921 /* We can only access byte-aligned values. Since we are always passed
5922 a reference to the first byte of the field, it is not necessary to
5923 do anything with BITPOS after this check. */
5924 if (bitpos % BITS_PER_UNIT != 0)
5927 /* Reject aligned bitfields: we want to use a normal load or store
5928 instead of a left/right pair. */
5929 if (MEM_ALIGN (*op) >= width)
5932 /* Adjust *OP to refer to the whole field. This also has the effect
5933 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5934 *op = adjust_address (*op, BLKmode, 0);
5935 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
5937 /* Get references to both ends of the field. We deliberately don't
5938 use the original QImode *OP for FIRST since the new BLKmode one
5939 might have a simpler address. */
5940 first = adjust_address (*op, QImode, 0);
5941 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
5943 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
5944 be the upper word and RIGHT the lower word. */
5945 if (TARGET_BIG_ENDIAN)
5946 *left = first, *right = last;
5948 *left = last, *right = first;
5954 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
5955 Return true on success. We only handle cases where zero_extract is
5956 equivalent to sign_extract. */
5959 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
5961 rtx left, right, temp;
5963 /* If TARGET_64BIT, the destination of a 32-bit load will be a
5964 paradoxical word_mode subreg. This is the only case in which
5965 we allow the destination to be larger than the source. */
5966 if (GET_CODE (dest) == SUBREG
5967 && GET_MODE (dest) == DImode
5968 && SUBREG_BYTE (dest) == 0
5969 && GET_MODE (SUBREG_REG (dest)) == SImode)
5970 dest = SUBREG_REG (dest);
5972 /* After the above adjustment, the destination must be the same
5973 width as the source. */
5974 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
5977 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
5980 temp = gen_reg_rtx (GET_MODE (dest));
5981 if (GET_MODE (dest) == DImode)
5983 emit_insn (gen_mov_ldl (temp, src, left));
5984 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
5988 emit_insn (gen_mov_lwl (temp, src, left));
5989 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
5995 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
5999 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
6002 enum machine_mode mode;
6004 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6007 mode = mode_for_size (width, MODE_INT, 0);
6008 src = gen_lowpart (mode, src);
6012 emit_insn (gen_mov_sdl (dest, src, left));
6013 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6017 emit_insn (gen_mov_swl (dest, src, left));
6018 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6023 /* Return true if X is a MEM with the same size as MODE. */
6026 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6033 size = MEM_SIZE (x);
6034 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6037 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
6038 source of an "ext" instruction or the destination of an "ins"
6039 instruction. OP must be a register operand and the following
6040 conditions must hold:
6042 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
6043 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
6044 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
6046 Also reject lengths equal to a word as they are better handled
6047 by the move patterns. */
6050 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
6052 HOST_WIDE_INT len, pos;
6054 if (!ISA_HAS_EXT_INS
6055 || !register_operand (op, VOIDmode)
6056 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6059 len = INTVAL (size);
6060 pos = INTVAL (position);
6062 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
6063 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
6069 /* Initialize mips_split_addresses from the associated command-line
6072 mips_split_addresses is a half-way house between explicit
6073 relocations and the traditional assembler macros. It can
6074 split absolute 32-bit symbolic constants into a high/lo_sum
6075 pair but uses macros for other sorts of access.
6077 Like explicit relocation support for REL targets, it relies
6078 on GNU extensions in the assembler and the linker.
6080 Although this code should work for -O0, it has traditionally
6081 been treated as an optimization. */
6084 mips_init_split_addresses (void)
6086 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
6087 && optimize && !flag_pic
6088 && !ABI_HAS_64BIT_SYMBOLS)
6089 mips_split_addresses = 1;
6091 mips_split_addresses = 0;
6094 /* (Re-)Initialize information about relocs. */
6097 mips_init_relocs (void)
6099 memset (mips_split_p, '\0', sizeof (mips_split_p));
6100 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6101 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6103 if (ABI_HAS_64BIT_SYMBOLS)
6105 if (TARGET_EXPLICIT_RELOCS)
6107 mips_split_p[SYMBOL_64_HIGH] = true;
6108 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6109 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6111 mips_split_p[SYMBOL_64_MID] = true;
6112 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6113 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6115 mips_split_p[SYMBOL_64_LOW] = true;
6116 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6117 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6119 mips_split_p[SYMBOL_ABSOLUTE] = true;
6120 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6125 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses || TARGET_MIPS16)
6127 mips_split_p[SYMBOL_ABSOLUTE] = true;
6128 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6129 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6131 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6137 /* The high part is provided by a pseudo copy of $gp. */
6138 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6139 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6142 if (TARGET_EXPLICIT_RELOCS)
6144 /* Small data constants are kept whole until after reload,
6145 then lowered by mips_rewrite_small_data. */
6146 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6148 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6151 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6152 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6156 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6157 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6162 /* The HIGH and LO_SUM are matched by special .md patterns. */
6163 mips_split_p[SYMBOL_GOT_DISP] = true;
6165 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6166 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6167 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6169 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6170 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6171 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6176 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6178 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6179 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6185 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6186 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6187 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6190 /* Thread-local relocation operators. */
6191 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6192 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6193 mips_split_p[SYMBOL_DTPREL] = 1;
6194 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6195 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6196 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6197 mips_split_p[SYMBOL_TPREL] = 1;
6198 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6199 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6201 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6204 /* If OP is an UNSPEC address, return the address to which it refers,
6205 otherwise return OP itself. */
6208 mips_strip_unspec_address (rtx op)
6212 split_const (op, &base, &offset);
6213 if (UNSPEC_ADDRESS_P (base))
6214 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6218 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6219 in context CONTEXT. RELOCS is the array of relocations to use. */
6222 print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6223 const char **relocs)
6225 enum mips_symbol_type symbol_type;
6228 symbol_type = mips_classify_symbolic_expression (op, context);
6229 if (relocs[symbol_type] == 0)
6230 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
6232 fputs (relocs[symbol_type], file);
6233 output_addr_const (file, mips_strip_unspec_address (op));
6234 for (p = relocs[symbol_type]; *p != 0; p++)
6239 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6240 The punctuation characters are:
6242 '(' Start a nested ".set noreorder" block.
6243 ')' End a nested ".set noreorder" block.
6244 '[' Start a nested ".set noat" block.
6245 ']' End a nested ".set noat" block.
6246 '<' Start a nested ".set nomacro" block.
6247 '>' End a nested ".set nomacro" block.
6248 '*' Behave like %(%< if generating a delayed-branch sequence.
6249 '#' Print a nop if in a ".set noreorder" block.
6250 '/' Like '#', but do nothing within a delayed-branch sequence.
6251 '?' Print "l" if mips_branch_likely is true
6252 '.' Print the name of the register with a hard-wired zero (zero or $0).
6253 '@' Print the name of the assembler temporary register (at or $1).
6254 '^' Print the name of the pic call-through register (t9 or $25).
6255 '+' Print the name of the gp register (usually gp or $28).
6256 '$' Print the name of the stack pointer register (sp or $29).
6257 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6258 '-' Print ".set pop" under the same conditions for '|'.
6260 See also mips_init_print_operand_pucnt. */
6263 mips_print_operand_punctuation (FILE *file, int ch)
6268 if (set_noreorder++ == 0)
6269 fputs (".set\tnoreorder\n\t", file);
6273 gcc_assert (set_noreorder > 0);
6274 if (--set_noreorder == 0)
6275 fputs ("\n\t.set\treorder", file);
6279 if (set_noat++ == 0)
6280 fputs (".set\tnoat\n\t", file);
6284 gcc_assert (set_noat > 0);
6285 if (--set_noat == 0)
6286 fputs ("\n\t.set\tat", file);
6290 if (set_nomacro++ == 0)
6291 fputs (".set\tnomacro\n\t", file);
6295 gcc_assert (set_nomacro > 0);
6296 if (--set_nomacro == 0)
6297 fputs ("\n\t.set\tmacro", file);
6301 if (final_sequence != 0)
6303 mips_print_operand_punctuation (file, '(');
6304 mips_print_operand_punctuation (file, '<');
6309 if (set_noreorder != 0)
6310 fputs ("\n\tnop", file);
6314 /* Print an extra newline so that the delayed insn is separated
6315 from the following ones. This looks neater and is consistent
6316 with non-nop delayed sequences. */
6317 if (set_noreorder != 0 && final_sequence == 0)
6318 fputs ("\n\tnop\n", file);
6322 if (mips_branch_likely)
6327 fputs (reg_names[GP_REG_FIRST + 0], file);
6331 fputs (reg_names[GP_REG_FIRST + 1], file);
6335 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6339 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6343 fputs (reg_names[STACK_POINTER_REGNUM], file);
6348 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6353 fputs ("\n\t.set\tpop", file);
6362 /* Initialize mips_print_operand_punct. */
6365 mips_init_print_operand_punct (void)
6369 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
6370 mips_print_operand_punct[(unsigned char) *p] = true;
6373 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6374 associated with condition CODE. Print the condition part of the
6378 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
6392 /* Conveniently, the MIPS names for these conditions are the same
6393 as their RTL equivalents. */
6394 fputs (GET_RTX_NAME (code), file);
6398 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6403 /* Likewise floating-point branches. */
6406 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
6411 fputs ("c1f", file);
6415 fputs ("c1t", file);
6419 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6424 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6426 'X' Print CONST_INT OP in hexadecimal format.
6427 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6428 'd' Print CONST_INT OP in decimal.
6429 'h' Print the high-part relocation associated with OP, after stripping
6431 'R' Print the low-part relocation associated with OP.
6432 'C' Print the integer branch condition for comparison OP.
6433 'N' Print the inverse of the integer branch condition for comparison OP.
6434 'F' Print the FPU branch condition for comparison OP.
6435 'W' Print the inverse of the FPU branch condition for comparison OP.
6436 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6437 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6438 't' Like 'T', but with the EQ/NE cases reversed
6439 'Y' Print mips_fp_conditions[INTVAL (OP)]
6440 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6441 'q' Print a DSP accumulator register.
6442 'D' Print the second part of a double-word register or memory operand.
6443 'L' Print the low-order register in a double-word register operand.
6444 'M' Print high-order register in a double-word register operand.
6445 'z' Print $0 if OP is zero, otherwise print OP normally. */
6448 print_operand (FILE *file, rtx op, int letter)
6452 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6454 mips_print_operand_punctuation (file, letter);
6459 code = GET_CODE (op);
6464 if (GET_CODE (op) == CONST_INT)
6465 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6467 output_operand_lossage ("invalid use of '%%%c'", letter);
6471 if (GET_CODE (op) == CONST_INT)
6472 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
6474 output_operand_lossage ("invalid use of '%%%c'", letter);
6478 if (GET_CODE (op) == CONST_INT)
6479 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
6481 output_operand_lossage ("invalid use of '%%%c'", letter);
6487 print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
6491 print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
6495 mips_print_int_branch_condition (file, code, letter);
6499 mips_print_int_branch_condition (file, reverse_condition (code), letter);
6503 mips_print_float_branch_condition (file, code, letter);
6507 mips_print_float_branch_condition (file, reverse_condition (code),
6514 int truth = (code == NE) == (letter == 'T');
6515 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6520 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
6521 fputs (mips_fp_conditions[UINTVAL (op)], file);
6523 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6530 print_operand (file, op, 0);
6536 if (code == REG && MD_REG_P (REGNO (op)))
6537 fprintf (file, "$ac0");
6538 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
6539 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
6541 output_operand_lossage ("invalid use of '%%%c'", letter);
6549 unsigned int regno = REGNO (op);
6550 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
6551 || (letter == 'L' && TARGET_BIG_ENDIAN)
6554 fprintf (file, "%s", reg_names[regno]);
6560 output_address (plus_constant (XEXP (op, 0), 4));
6562 output_address (XEXP (op, 0));
6566 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6567 fputs (reg_names[GP_REG_FIRST], file);
6568 else if (CONST_GP_P (op))
6569 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6571 output_addr_const (file, mips_strip_unspec_address (op));
6577 /* Output address operand X to FILE. */
6580 print_operand_address (FILE *file, rtx x)
6582 struct mips_address_info addr;
6584 if (mips_classify_address (&addr, x, word_mode, true))
6588 print_operand (file, addr.offset, 0);
6589 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6592 case ADDRESS_LO_SUM:
6593 print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
6595 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6598 case ADDRESS_CONST_INT:
6599 output_addr_const (file, x);
6600 fprintf (file, "(%s)", reg_names[0]);
6603 case ADDRESS_SYMBOLIC:
6604 output_addr_const (file, mips_strip_unspec_address (x));
6610 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
6611 FIRST is true if this is the first time handling this decl. */
6614 mips_encode_section_info (tree decl, rtx rtl, int first)
6616 default_encode_section_info (decl, rtl, first);
6618 if (TREE_CODE (decl) == FUNCTION_DECL)
6620 rtx symbol = XEXP (rtl, 0);
6621 tree type = TREE_TYPE (decl);
6623 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
6624 || mips_far_type_p (type))
6625 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
6629 /* Implement TARGET_SELECT_RTX_SECTION. */
6632 mips_select_rtx_section (enum machine_mode mode, rtx x,
6633 unsigned HOST_WIDE_INT align)
6635 /* ??? Consider using mergeable small data sections. */
6636 if (mips_rtx_constant_in_small_data_p (mode))
6637 return get_named_section (NULL, ".sdata", 0);
6639 return default_elf_select_rtx_section (mode, x, align);
6642 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6644 The complication here is that, with the combination TARGET_ABICALLS
6645 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6646 therefore not be included in the read-only part of a DSO. Handle such
6647 cases by selecting a normal data section instead of a read-only one.
6648 The logic apes that in default_function_rodata_section. */
6651 mips_function_rodata_section (tree decl)
6653 if (!TARGET_ABICALLS || TARGET_GPWORD)
6654 return default_function_rodata_section (decl);
6656 if (decl && DECL_SECTION_NAME (decl))
6658 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6659 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6661 char *rname = ASTRDUP (name);
6663 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6665 else if (flag_function_sections && flag_data_sections
6666 && strncmp (name, ".text.", 6) == 0)
6668 char *rname = ASTRDUP (name);
6669 memcpy (rname + 1, "data", 4);
6670 return get_section (rname, SECTION_WRITE, decl);
6673 return data_section;
6676 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
6677 locally-defined objects go in a small data section. It also controls
6678 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
6679 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
6682 mips_in_small_data_p (const_tree decl)
6686 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6689 /* We don't yet generate small-data references for -mabicalls or
6690 VxWorks RTP code. See the related -G handling in override_options. */
6691 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
6694 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6698 /* Reject anything that isn't in a known small-data section. */
6699 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6700 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6703 /* If a symbol is defined externally, the assembler will use the
6704 usual -G rules when deciding how to implement macros. */
6705 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
6708 else if (TARGET_EMBEDDED_DATA)
6710 /* Don't put constants into the small data section: we want them
6711 to be in ROM rather than RAM. */
6712 if (TREE_CODE (decl) != VAR_DECL)
6715 if (TREE_READONLY (decl)
6716 && !TREE_SIDE_EFFECTS (decl)
6717 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6721 /* Enforce -mlocal-sdata. */
6722 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
6725 /* Enforce -mextern-sdata. */
6726 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
6728 if (DECL_EXTERNAL (decl))
6730 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
6734 size = int_size_in_bytes (TREE_TYPE (decl));
6735 return (size > 0 && size <= mips_section_threshold);
6738 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6739 anchors for small data: the GP register acts as an anchor in that
6740 case. We also don't want to use them for PC-relative accesses,
6741 where the PC acts as an anchor. */
6744 mips_use_anchors_for_symbol_p (const_rtx symbol)
6746 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
6748 case SYMBOL_PC_RELATIVE:
6749 case SYMBOL_GP_RELATIVE:
6753 return default_use_anchors_for_symbol_p (symbol);
6757 /* The MIPS debug format wants all automatic variables and arguments
6758 to be in terms of the virtual frame pointer (stack pointer before
6759 any adjustment in the function), while the MIPS 3.0 linker wants
6760 the frame pointer to be the stack pointer after the initial
6761 adjustment. So, we do the adjustment here. The arg pointer (which
6762 is eliminated) points to the virtual frame pointer, while the frame
6763 pointer (which may be eliminated) points to the stack pointer after
6764 the initial adjustments. */
6767 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
6769 rtx offset2 = const0_rtx;
6770 rtx reg = eliminate_constant_term (addr, &offset2);
6773 offset = INTVAL (offset2);
6775 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
6776 || reg == hard_frame_pointer_rtx)
6778 offset -= cfun->machine->frame.total_size;
6779 if (reg == hard_frame_pointer_rtx)
6780 offset += cfun->machine->frame.hard_frame_pointer_offset;
6783 /* sdbout_parms does not want this to crash for unrecognized cases. */
6785 else if (reg != arg_pointer_rtx)
6786 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6793 /* When using assembler macros, keep track of all of small-data externs
6794 so that mips_file_end can emit the appropriate declarations for them.
6796 In most cases it would be safe (though pointless) to emit .externs
6797 for other symbols too. One exception is when an object is within
6798 the -G limit but declared by the user to be in a section other
6799 than .sbss or .sdata. */
6802 mips_output_external (FILE *file, tree decl, const char *name)
6804 default_elf_asm_output_external (file, decl, name);
6806 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6807 set in order to avoid putting out names that are never really
6809 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6811 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6813 fputs ("\t.extern\t", file);
6814 assemble_name (file, name);
6815 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6816 int_size_in_bytes (TREE_TYPE (decl)));
6818 else if (TARGET_IRIX
6819 && mips_abi == ABI_32
6820 && TREE_CODE (decl) == FUNCTION_DECL)
6822 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6823 `.global name .text' directive for every used but
6824 undefined function. If we don't, the linker may perform
6825 an optimization (skipping over the insns that set $gp)
6826 when it is unsafe. */
6827 fputs ("\t.globl ", file);
6828 assemble_name (file, name);
6829 fputs (" .text\n", file);
6834 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6835 put out a MIPS ECOFF file and a stab. */
6838 mips_output_filename (FILE *stream, const char *name)
6841 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6843 if (write_symbols == DWARF2_DEBUG)
6845 else if (mips_output_filename_first_time)
6847 mips_output_filename_first_time = 0;
6848 num_source_filenames += 1;
6849 current_function_file = name;
6850 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6851 output_quoted_string (stream, name);
6852 putc ('\n', stream);
6855 /* If we are emitting stabs, let dbxout.c handle this (except for
6856 the mips_output_filename_first_time case). */
6857 else if (write_symbols == DBX_DEBUG)
6860 else if (name != current_function_file
6861 && strcmp (name, current_function_file) != 0)
6863 num_source_filenames += 1;
6864 current_function_file = name;
6865 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6866 output_quoted_string (stream, name);
6867 putc ('\n', stream);
6871 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
6874 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
6879 fputs ("\t.dtprelword\t", file);
6883 fputs ("\t.dtpreldword\t", file);
6889 output_addr_const (file, x);
6890 fputs ("+0x8000", file);
6893 /* Implement TARGET_DWARF_REGISTER_SPAN. */
6896 mips_dwarf_register_span (rtx reg)
6899 enum machine_mode mode;
6901 /* By default, GCC maps increasing register numbers to increasing
6902 memory locations, but paired FPRs are always little-endian,
6903 regardless of the prevailing endianness. */
6904 mode = GET_MODE (reg);
6905 if (FP_REG_P (REGNO (reg))
6906 && TARGET_BIG_ENDIAN
6907 && MAX_FPRS_PER_FMT > 1
6908 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
6910 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
6911 high = mips_subword (reg, true);
6912 low = mips_subword (reg, false);
6913 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
6919 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6920 that should be written before the opening quote, such as "\t.ascii\t"
6921 for real string data or "\t# " for a comment. */
6924 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
6929 register const unsigned char *string =
6930 (const unsigned char *)string_param;
6932 fprintf (stream, "%s\"", prefix);
6933 for (i = 0; i < len; i++)
6935 register int c = string[i];
6939 if (c == '\\' || c == '\"')
6941 putc ('\\', stream);
6949 fprintf (stream, "\\%03o", c);
6953 if (cur_pos > 72 && i+1 < len)
6956 fprintf (stream, "\"\n%s\"", prefix);
6959 fprintf (stream, "\"\n");
6962 #ifdef BSS_SECTION_ASM_OP
6963 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6964 in the use of sbss. */
6967 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6968 unsigned HOST_WIDE_INT size, int align)
6970 extern tree last_assemble_variable_decl;
6972 if (mips_in_small_data_p (decl))
6973 switch_to_section (get_named_section (NULL, ".sbss", 0));
6975 switch_to_section (bss_section);
6976 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6977 last_assemble_variable_decl = decl;
6978 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6979 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6983 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6984 macros, mark the symbol as written so that mips_file_end won't emit an
6985 .extern for it. STREAM is the output file, NAME is the name of the
6986 symbol, INIT_STRING is the string that should be written before the
6987 symbol and FINAL_STRING is the string that should be written after it.
6988 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6991 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6992 const char *final_string, ...)
6996 fputs (init_string, stream);
6997 assemble_name (stream, name);
6998 va_start (ap, final_string);
6999 vfprintf (stream, final_string, ap);
7002 if (!TARGET_EXPLICIT_RELOCS)
7004 tree name_tree = get_identifier (name);
7005 TREE_ASM_WRITTEN (name_tree) = 1;
7009 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7010 NAME is the name of the object and ALIGN is the required alignment
7011 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7012 alignment argument. */
7015 mips_declare_common_object (FILE *stream, const char *name,
7016 const char *init_string,
7017 unsigned HOST_WIDE_INT size,
7018 unsigned int align, bool takes_alignment_p)
7020 if (!takes_alignment_p)
7022 size += (align / BITS_PER_UNIT) - 1;
7023 size -= size % (align / BITS_PER_UNIT);
7024 mips_declare_object (stream, name, init_string,
7025 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7028 mips_declare_object (stream, name, init_string,
7029 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7030 size, align / BITS_PER_UNIT);
7033 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7034 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7037 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7038 unsigned HOST_WIDE_INT size,
7041 /* If the target wants uninitialized const declarations in
7042 .rdata then don't put them in .comm. */
7043 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
7044 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
7045 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7047 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7048 targetm.asm_out.globalize_label (stream, name);
7050 switch_to_section (readonly_data_section);
7051 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7052 mips_declare_object (stream, name, "",
7053 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7057 mips_declare_common_object (stream, name, "\n\t.comm\t",
7061 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7062 extern int size_directive_output;
7064 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7065 definitions except that it uses mips_declare_object() to emit the label. */
7068 mips_declare_object_name (FILE *stream, const char *name,
7069 tree decl ATTRIBUTE_UNUSED)
7071 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7072 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7075 size_directive_output = 0;
7076 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7080 size_directive_output = 1;
7081 size = int_size_in_bytes (TREE_TYPE (decl));
7082 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7085 mips_declare_object (stream, name, "", ":\n");
7088 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7091 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7095 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7096 if (!flag_inhibit_size_directive
7097 && DECL_SIZE (decl) != 0
7098 && !at_end && top_level
7099 && DECL_INITIAL (decl) == error_mark_node
7100 && !size_directive_output)
7104 size_directive_output = 1;
7105 size = int_size_in_bytes (TREE_TYPE (decl));
7106 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7111 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7112 with the current ABI. */
7115 mips_mdebug_abi_name (void)
7128 return TARGET_64BIT ? "eabi64" : "eabi32";
7134 /* Implement TARGET_ASM_FILE_START. */
7137 mips_file_start (void)
7139 default_file_start ();
7143 /* Generate a special section to describe the ABI switches used to
7144 produce the resultant binary. This used to be done by the assembler
7145 setting bits in the ELF header's flags field, but we have run out of
7146 bits. GDB needs this information in order to be able to correctly
7147 debug these binaries. See the function mips_gdbarch_init() in
7148 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
7149 causes unnecessary IRIX 6 ld warnings. */
7150 /* Note - we use fprintf directly rather than calling switch_to_section
7151 because in this way we can avoid creating an allocated section. We
7152 do not want this section to take up any space in the running
7154 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7155 mips_mdebug_abi_name ());
7157 /* There is no ELF header flag to distinguish long32 forms of the
7158 EABI from long64 forms. Emit a special section to help tools
7159 such as GDB. Do the same for o64, which is sometimes used with
7161 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7162 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7163 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7165 #ifdef HAVE_AS_GNU_ATTRIBUTE
7166 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7167 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
7171 /* Generate the pseudo ops that System V.4 wants. */
7172 if (TARGET_ABICALLS)
7173 fprintf (asm_out_file, "\t.abicalls\n");
7175 if (flag_verbose_asm)
7176 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7178 mips_section_threshold, mips_arch_info->name, mips_isa);
7182 /* Make the last instruction frame related and note that it performs
7183 the operation described by FRAME_PATTERN. */
7186 mips_set_frame_expr (rtx frame_pattern)
7190 insn = get_last_insn ();
7191 RTX_FRAME_RELATED_P (insn) = 1;
7192 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7198 /* Return a frame-related rtx that stores REG at MEM.
7199 REG must be a single register. */
7202 mips_frame_set (rtx mem, rtx reg)
7206 /* If we're saving the return address register and the dwarf return
7207 address column differs from the hard register number, adjust the
7208 note reg to refer to the former. */
7209 if (REGNO (reg) == GP_REG_FIRST + 31
7210 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7211 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7213 set = gen_rtx_SET (VOIDmode, mem, reg);
7214 RTX_FRAME_RELATED_P (set) = 1;
7219 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7220 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7221 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7222 static const unsigned char mips16e_s2_s8_regs[] = {
7223 30, 23, 22, 21, 20, 19, 18
7225 static const unsigned char mips16e_a0_a3_regs[] = {
7229 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7230 ordered from the uppermost in memory to the lowest in memory. */
7231 static const unsigned char mips16e_save_restore_regs[] = {
7232 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7235 /* Return the index of the lowest X in the range [0, SIZE) for which
7236 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7239 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7244 for (i = 0; i < size; i++)
7245 if (BITSET_P (mask, regs[i]))
7251 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7252 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7253 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7254 is true for all indexes (X, SIZE). */
7257 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7258 unsigned int size, unsigned int *num_regs_ptr)
7262 i = mips16e_find_first_register (*mask_ptr, regs, size);
7263 for (i++; i < size; i++)
7264 if (!BITSET_P (*mask_ptr, regs[i]))
7267 *mask_ptr |= 1 << regs[i];
7271 /* Return a simplified form of X using the register values in REG_VALUES.
7272 REG_VALUES[R] is the last value assigned to hard register R, or null
7273 if R has not been modified.
7275 This function is rather limited, but is good enough for our purposes. */
7278 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7282 x = avoid_constant_pool_reference (x);
7286 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7287 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7288 x0, GET_MODE (XEXP (x, 0)));
7291 if (ARITHMETIC_P (x))
7293 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7294 x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7295 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7299 && reg_values[REGNO (x)]
7300 && !rtx_unstable_p (reg_values[REGNO (x)]))
7301 return reg_values[REGNO (x)];
7306 /* Return true if (set DEST SRC) stores an argument register into its
7307 caller-allocated save slot, storing the number of that argument
7308 register in *REGNO_PTR if so. REG_VALUES is as for
7309 mips16e_collect_propagate_value. */
7312 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7313 unsigned int *regno_ptr)
7315 unsigned int argno, regno;
7316 HOST_WIDE_INT offset, required_offset;
7319 /* Check that this is a word-mode store. */
7320 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7323 /* Check that the register being saved is an unmodified argument
7325 regno = REGNO (src);
7326 if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
7328 argno = regno - GP_ARG_FIRST;
7330 /* Check whether the address is an appropriate stack pointer or
7331 frame pointer access. */
7332 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7333 mips_split_plus (addr, &base, &offset);
7334 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7335 if (base == hard_frame_pointer_rtx)
7336 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7337 else if (base != stack_pointer_rtx)
7339 if (offset != required_offset)
7346 /* A subroutine of mips_expand_prologue, called only when generating
7347 MIPS16e SAVE instructions. Search the start of the function for any
7348 instructions that save argument registers into their caller-allocated
7349 save slots. Delete such instructions and return a value N such that
7350 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7351 instructions redundant. */
7354 mips16e_collect_argument_saves (void)
7356 rtx reg_values[FIRST_PSEUDO_REGISTER];
7357 rtx insn, next, set, dest, src;
7358 unsigned int nargs, regno;
7360 push_topmost_sequence ();
7362 memset (reg_values, 0, sizeof (reg_values));
7363 for (insn = get_insns (); insn; insn = next)
7365 next = NEXT_INSN (insn);
7372 set = PATTERN (insn);
7373 if (GET_CODE (set) != SET)
7376 dest = SET_DEST (set);
7377 src = SET_SRC (set);
7378 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
7380 if (!BITSET_P (cfun->machine->frame.mask, regno))
7383 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7386 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7387 reg_values[REGNO (dest)]
7388 = mips16e_collect_propagate_value (src, reg_values);
7392 pop_topmost_sequence ();
7397 /* Return a move between register REGNO and memory location SP + OFFSET.
7398 Make the move a load if RESTORE_P, otherwise make it a frame-related
7402 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7407 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7408 reg = gen_rtx_REG (SImode, regno);
7410 ? gen_rtx_SET (VOIDmode, reg, mem)
7411 : mips_frame_set (mem, reg));
7414 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7415 The instruction must:
7417 - Allocate or deallocate SIZE bytes in total; SIZE is known
7420 - Save or restore as many registers in *MASK_PTR as possible.
7421 The instruction saves the first registers at the top of the
7422 allocated area, with the other registers below it.
7424 - Save NARGS argument registers above the allocated area.
7426 (NARGS is always zero if RESTORE_P.)
7428 The SAVE and RESTORE instructions cannot save and restore all general
7429 registers, so there may be some registers left over for the caller to
7430 handle. Destructively modify *MASK_PTR so that it contains the registers
7431 that still need to be saved or restored. The caller can save these
7432 registers in the memory immediately below *OFFSET_PTR, which is a
7433 byte offset from the bottom of the allocated stack area. */
7436 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7437 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7441 HOST_WIDE_INT offset, top_offset;
7442 unsigned int i, regno;
7445 gcc_assert (cfun->machine->frame.num_fp == 0);
7447 /* Calculate the number of elements in the PARALLEL. We need one element
7448 for the stack adjustment, one for each argument register save, and one
7449 for each additional register move. */
7451 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7452 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7455 /* Create the final PARALLEL. */
7456 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7459 /* Add the stack pointer adjustment. */
7460 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7461 plus_constant (stack_pointer_rtx,
7462 restore_p ? size : -size));
7463 RTX_FRAME_RELATED_P (set) = 1;
7464 XVECEXP (pattern, 0, n++) = set;
7466 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7467 top_offset = restore_p ? size : 0;
7469 /* Save the arguments. */
7470 for (i = 0; i < nargs; i++)
7472 offset = top_offset + i * UNITS_PER_WORD;
7473 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7474 XVECEXP (pattern, 0, n++) = set;
7477 /* Then fill in the other register moves. */
7478 offset = top_offset;
7479 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7481 regno = mips16e_save_restore_regs[i];
7482 if (BITSET_P (*mask_ptr, regno))
7484 offset -= UNITS_PER_WORD;
7485 set = mips16e_save_restore_reg (restore_p, offset, regno);
7486 XVECEXP (pattern, 0, n++) = set;
7487 *mask_ptr &= ~(1 << regno);
7491 /* Tell the caller what offset it should use for the remaining registers. */
7492 *offset_ptr = size + (offset - top_offset) + size;
7494 gcc_assert (n == XVECLEN (pattern, 0));
7499 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7500 pointer. Return true if PATTERN matches the kind of instruction
7501 generated by mips16e_build_save_restore. If INFO is nonnull,
7502 initialize it when returning true. */
7505 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7506 struct mips16e_save_restore_info *info)
7508 unsigned int i, nargs, mask, extra;
7509 HOST_WIDE_INT top_offset, save_offset, offset;
7510 rtx set, reg, mem, base;
7513 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7516 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7517 top_offset = adjust > 0 ? adjust : 0;
7519 /* Interpret all other members of the PARALLEL. */
7520 save_offset = top_offset - UNITS_PER_WORD;
7524 for (n = 1; n < XVECLEN (pattern, 0); n++)
7526 /* Check that we have a SET. */
7527 set = XVECEXP (pattern, 0, n);
7528 if (GET_CODE (set) != SET)
7531 /* Check that the SET is a load (if restoring) or a store
7533 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7537 /* Check that the address is the sum of the stack pointer and a
7538 possibly-zero constant offset. */
7539 mips_split_plus (XEXP (mem, 0), &base, &offset);
7540 if (base != stack_pointer_rtx)
7543 /* Check that SET's other operand is a register. */
7544 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7548 /* Check for argument saves. */
7549 if (offset == top_offset + nargs * UNITS_PER_WORD
7550 && REGNO (reg) == GP_ARG_FIRST + nargs)
7552 else if (offset == save_offset)
7554 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7555 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7558 mask |= 1 << REGNO (reg);
7559 save_offset -= UNITS_PER_WORD;
7565 /* Check that the restrictions on register ranges are met. */
7567 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7568 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7569 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7570 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7574 /* Make sure that the topmost argument register is not saved twice.
7575 The checks above ensure that the same is then true for the other
7576 argument registers. */
7577 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7580 /* Pass back information, if requested. */
7583 info->nargs = nargs;
7585 info->size = (adjust > 0 ? adjust : -adjust);
7591 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7592 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7593 the null terminator. */
7596 mips16e_add_register_range (char *s, unsigned int min_reg,
7597 unsigned int max_reg)
7599 if (min_reg != max_reg)
7600 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7602 s += sprintf (s, ",%s", reg_names[min_reg]);
7606 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7607 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7610 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7612 static char buffer[300];
7614 struct mips16e_save_restore_info info;
7615 unsigned int i, end;
7618 /* Parse the pattern. */
7619 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7622 /* Add the mnemonic. */
7623 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7626 /* Save the arguments. */
7628 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7629 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7630 else if (info.nargs == 1)
7631 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7633 /* Emit the amount of stack space to allocate or deallocate. */
7634 s += sprintf (s, "%d", (int) info.size);
7636 /* Save or restore $16. */
7637 if (BITSET_P (info.mask, 16))
7638 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7640 /* Save or restore $17. */
7641 if (BITSET_P (info.mask, 17))
7642 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7644 /* Save or restore registers in the range $s2...$s8, which
7645 mips16e_s2_s8_regs lists in decreasing order. Note that this
7646 is a software register range; the hardware registers are not
7647 numbered consecutively. */
7648 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7649 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7651 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7652 mips16e_s2_s8_regs[i]);
7654 /* Save or restore registers in the range $a0...$a3. */
7655 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7656 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7658 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7659 mips16e_a0_a3_regs[end - 1]);
7661 /* Save or restore $31. */
7662 if (BITSET_P (info.mask, 31))
7663 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7668 /* Return true if the current function has an insn that implicitly
7672 mips_function_has_gp_insn (void)
7674 /* Don't bother rechecking if we found one last time. */
7675 if (!cfun->machine->has_gp_insn_p)
7679 push_topmost_sequence ();
7680 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7682 && GET_CODE (PATTERN (insn)) != USE
7683 && GET_CODE (PATTERN (insn)) != CLOBBER
7684 && (get_attr_got (insn) != GOT_UNSET
7685 || small_data_pattern (PATTERN (insn), VOIDmode)))
7687 pop_topmost_sequence ();
7689 cfun->machine->has_gp_insn_p = (insn != 0);
7691 return cfun->machine->has_gp_insn_p;
7695 /* Return the register that should be used as the global pointer
7696 within this function. Return 0 if the function doesn't need
7697 a global pointer. */
7700 mips_global_pointer (void)
7704 /* $gp is always available unless we're using a GOT. */
7705 if (!TARGET_USE_GOT)
7706 return GLOBAL_POINTER_REGNUM;
7708 /* We must always provide $gp when it is used implicitly. */
7709 if (!TARGET_EXPLICIT_RELOCS)
7710 return GLOBAL_POINTER_REGNUM;
7712 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7714 if (current_function_profile)
7715 return GLOBAL_POINTER_REGNUM;
7717 /* If the function has a nonlocal goto, $gp must hold the correct
7718 global pointer for the target function. */
7719 if (current_function_has_nonlocal_goto)
7720 return GLOBAL_POINTER_REGNUM;
7722 /* If the gp is never referenced, there's no need to initialize it.
7723 Note that reload can sometimes introduce constant pool references
7724 into a function that otherwise didn't need them. For example,
7725 suppose we have an instruction like:
7727 (set (reg:DF R1) (float:DF (reg:SI R2)))
7729 If R2 turns out to be constant such as 1, the instruction may have a
7730 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7731 using this constant if R2 doesn't get allocated to a register.
7733 In cases like these, reload will have added the constant to the pool
7734 but no instruction will yet refer to it. */
7735 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
7736 && !current_function_uses_const_pool
7737 && !mips_function_has_gp_insn ())
7740 /* We need a global pointer, but perhaps we can use a call-clobbered
7741 register instead of $gp. */
7742 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
7743 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7744 if (!df_regs_ever_live_p (regno)
7745 && call_really_used_regs[regno]
7746 && !fixed_regs[regno]
7747 && regno != PIC_FUNCTION_ADDR_REGNUM)
7750 return GLOBAL_POINTER_REGNUM;
7753 /* Return true if the current function returns its value in a floating-point
7754 register in MIPS16 mode. */
7757 mips16_cfun_returns_in_fpr_p (void)
7759 tree return_type = DECL_RESULT (current_function_decl);
7760 return (TARGET_MIPS16
7761 && TARGET_HARD_FLOAT_ABI
7762 && !aggregate_value_p (return_type, current_function_decl)
7763 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
7767 /* Return true if the current function must save REGNO. */
7770 mips_save_reg_p (unsigned int regno)
7772 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7773 if we have not chosen a call-clobbered substitute. */
7774 if (regno == GLOBAL_POINTER_REGNUM)
7775 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
7777 /* Check call-saved registers. */
7778 if ((current_function_saves_all_registers || df_regs_ever_live_p (regno))
7779 && !call_really_used_regs[regno])
7782 /* Save both registers in an FPR pair if either one is used. This is
7783 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7784 register to be used without the even register. */
7785 if (FP_REG_P (regno)
7786 && MAX_FPRS_PER_FMT == 2
7787 && df_regs_ever_live_p (regno + 1)
7788 && !call_really_used_regs[regno + 1])
7791 /* We need to save the old frame pointer before setting up a new one. */
7792 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7795 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7796 if (current_function_profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
7799 /* We need to save the incoming return address if it is ever clobbered
7800 within the function, if __builtin_eh_return is being used to set a
7801 different return address, or if a stub is being used to return a
7803 if (regno == GP_REG_FIRST + 31
7804 && (df_regs_ever_live_p (regno)
7805 || current_function_calls_eh_return
7806 || mips16_cfun_returns_in_fpr_p ()))
7812 /* Populate the current function's mips_frame_info structure.
7814 MIPS stack frames look like:
7816 +-------------------------------+
7818 | incoming stack arguments |
7820 +-------------------------------+
7822 | caller-allocated save area |
7823 A | for register arguments |
7825 +-------------------------------+ <-- incoming stack pointer
7827 | callee-allocated save area |
7828 B | for arguments that are |
7829 | split between registers and |
7832 +-------------------------------+ <-- arg_pointer_rtx
7834 C | callee-allocated save area |
7835 | for register varargs |
7837 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7838 | | + UNITS_PER_HWFPVALUE
7841 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7842 | | + UNITS_PER_WORD
7845 +-------------------------------+
7847 | local variables | | var_size
7849 +-------------------------------+
7851 | $gp save area | | cprestore_size
7853 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7855 | outgoing stack arguments |
7857 +-------------------------------+
7859 | caller-allocated save area |
7860 | for register arguments |
7862 +-------------------------------+ <-- stack_pointer_rtx
7864 hard_frame_pointer_rtx for
7867 At least two of A, B and C will be empty.
7869 Dynamic stack allocations such as alloca insert data at point P.
7870 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7871 hard_frame_pointer_rtx unchanged. */
7874 mips_compute_frame_info (void)
7876 struct mips_frame_info *frame;
7877 HOST_WIDE_INT offset, size;
7878 unsigned int regno, i;
7880 frame = &cfun->machine->frame;
7881 memset (frame, 0, sizeof (*frame));
7882 size = get_frame_size ();
7884 cfun->machine->global_pointer = mips_global_pointer ();
7886 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
7887 area and the $gp save slot. This area isn't needed in leaf functions,
7888 but if the target-independent frame size is nonzero, we're committed
7889 to allocating it anyway. */
7890 if (size == 0 && current_function_is_leaf)
7892 /* The MIPS 3.0 linker does not like functions that dynamically
7893 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7894 looks like we are trying to create a second frame pointer to the
7895 function, so allocate some stack space to make it happy. */
7896 if (current_function_calls_alloca)
7897 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
7899 frame->args_size = 0;
7900 frame->cprestore_size = 0;
7904 frame->args_size = current_function_outgoing_args_size;
7905 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
7907 offset = frame->args_size + frame->cprestore_size;
7909 /* Move above the local variables. */
7910 frame->var_size = MIPS_STACK_ALIGN (size);
7911 offset += frame->var_size;
7913 /* Find out which GPRs we need to save. */
7914 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7915 if (mips_save_reg_p (regno))
7918 frame->mask |= 1 << (regno - GP_REG_FIRST);
7921 /* If this function calls eh_return, we must also save and restore the
7922 EH data registers. */
7923 if (current_function_calls_eh_return)
7924 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
7927 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
7930 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7931 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7932 save all later registers too. */
7933 if (GENERATE_MIPS16E_SAVE_RESTORE)
7935 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
7936 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
7937 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
7938 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
7941 /* Move above the GPR save area. */
7942 if (frame->num_gp > 0)
7944 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
7945 frame->gp_sp_offset = offset - UNITS_PER_WORD;
7948 /* Find out which FPRs we need to save. This loop must iterate over
7949 the same space as its companion in mips_for_each_saved_reg. */
7950 if (TARGET_HARD_FLOAT)
7951 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
7952 if (mips_save_reg_p (regno))
7954 frame->num_fp += MAX_FPRS_PER_FMT;
7955 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
7958 /* Move above the FPR save area. */
7959 if (frame->num_fp > 0)
7961 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
7962 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
7965 /* Move above the callee-allocated varargs save area. */
7966 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
7967 frame->arg_pointer_offset = offset;
7969 /* Move above the callee-allocated area for pretend stack arguments. */
7970 offset += current_function_pretend_args_size;
7971 frame->total_size = offset;
7973 /* Work out the offsets of the save areas from the top of the frame. */
7974 if (frame->gp_sp_offset > 0)
7975 frame->gp_save_offset = frame->gp_sp_offset - offset;
7976 if (frame->fp_sp_offset > 0)
7977 frame->fp_save_offset = frame->fp_sp_offset - offset;
7979 /* MIPS16 code offsets the frame pointer by the size of the outgoing
7980 arguments. This tends to increase the chances of using unextended
7981 instructions for local variables and incoming arguments. */
7983 frame->hard_frame_pointer_offset = frame->args_size;
7986 /* Return the style of GP load sequence that is being used for the
7987 current function. */
7989 enum mips_loadgp_style
7990 mips_current_loadgp_style (void)
7992 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
7998 if (TARGET_ABSOLUTE_ABICALLS)
7999 return LOADGP_ABSOLUTE;
8001 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8004 /* Implement FRAME_POINTER_REQUIRED. */
8007 mips_frame_pointer_required (void)
8009 /* If the function contains dynamic stack allocations, we need to
8010 use the frame pointer to access the static parts of the frame. */
8011 if (current_function_calls_alloca)
8014 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8015 reload may be unable to compute the address of a local variable,
8016 since there is no way to add a large constant to the stack pointer
8017 without using a second temporary register. */
8020 mips_compute_frame_info ();
8021 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8028 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
8029 pointer or argument pointer. TO is either the stack pointer or
8030 hard frame pointer. */
8033 mips_initial_elimination_offset (int from, int to)
8035 HOST_WIDE_INT offset;
8037 mips_compute_frame_info ();
8039 /* Set OFFSET to the offset from the soft frame pointer, which is also
8040 the offset from the end-of-prologue stack pointer. */
8043 case FRAME_POINTER_REGNUM:
8047 case ARG_POINTER_REGNUM:
8048 offset = cfun->machine->frame.arg_pointer_offset;
8055 if (to == HARD_FRAME_POINTER_REGNUM)
8056 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8061 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
8062 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
8065 mips_extra_live_on_entry (bitmap regs)
8067 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
8068 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8071 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
8072 back to a previous frame. */
8075 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8080 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8083 /* Emit code to change the current function's return address to
8084 ADDRESS. SCRATCH is available as a scratch register, if needed.
8085 ADDRESS and SCRATCH are both word-mode GPRs. */
8088 mips_set_return_address (rtx address, rtx scratch)
8092 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
8093 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8094 cfun->machine->frame.gp_sp_offset);
8096 mips_emit_move (gen_rtx_MEM (GET_MODE (address), slot_address), address);
8099 /* Restore $gp from its save slot. Valid only when using o32 or
8103 mips_restore_gp (void)
8107 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8109 address = mips_add_offset (pic_offset_table_rtx,
8110 frame_pointer_needed
8111 ? hard_frame_pointer_rtx
8112 : stack_pointer_rtx,
8113 current_function_outgoing_args_size);
8114 slot = gen_rtx_MEM (Pmode, address);
8116 mips_emit_move (pic_offset_table_rtx, slot);
8117 if (!TARGET_EXPLICIT_RELOCS)
8118 emit_insn (gen_blockage ());
8121 /* A function to save or store a register. The first argument is the
8122 register and the second is the stack slot. */
8123 typedef void (*mips_save_restore_fn) (rtx, rtx);
8125 /* Use FN to save or restore register REGNO. MODE is the register's
8126 mode and OFFSET is the offset of its save slot from the current
8130 mips_save_restore_reg (enum machine_mode mode, int regno,
8131 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8135 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8137 fn (gen_rtx_REG (mode, regno), mem);
8141 /* Call FN for each register that is saved by the current function.
8142 SP_OFFSET is the offset of the current stack pointer from the start
8146 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8148 enum machine_mode fpr_mode;
8149 HOST_WIDE_INT offset;
8152 /* Save registers starting from high to low. The debuggers prefer at least
8153 the return register be stored at func+4, and also it allows us not to
8154 need a nop in the epilogue if at least one register is reloaded in
8155 addition to return address. */
8156 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8157 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8158 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8160 mips_save_restore_reg (word_mode, regno, offset, fn);
8161 offset -= UNITS_PER_WORD;
8164 /* This loop must iterate over the same space as its companion in
8165 mips_compute_frame_info. */
8166 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8167 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8168 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
8169 regno >= FP_REG_FIRST;
8170 regno -= MAX_FPRS_PER_FMT)
8171 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8173 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8174 offset -= GET_MODE_SIZE (fpr_mode);
8178 /* If we're generating n32 or n64 abicalls, and the current function
8179 does not use $28 as its global pointer, emit a cplocal directive.
8180 Use pic_offset_table_rtx as the argument to the directive. */
8183 mips_output_cplocal (void)
8185 if (!TARGET_EXPLICIT_RELOCS
8186 && cfun->machine->global_pointer > 0
8187 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8188 output_asm_insn (".cplocal %+", 0);
8191 /* Set up the stack and frame (if desired) for the function. */
8194 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8197 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
8199 #ifdef SDB_DEBUGGING_INFO
8200 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8201 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8204 /* In mips16 mode, we may need to generate a 32 bit to handle
8205 floating point arguments. The linker will arrange for any 32-bit
8206 functions to call this stub, which will then jump to the 16-bit
8209 && TARGET_HARD_FLOAT_ABI
8210 && current_function_args_info.fp_code != 0)
8211 build_mips16_function_stub ();
8213 /* Select the mips16 mode for this function. */
8215 fprintf (file, "\t.set\tmips16\n");
8217 fprintf (file, "\t.set\tnomips16\n");
8219 if (!FUNCTION_NAME_ALREADY_DECLARED)
8221 /* Get the function name the same way that toplev.c does before calling
8222 assemble_start_function. This is needed so that the name used here
8223 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8224 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8226 if (!flag_inhibit_size_directive)
8228 fputs ("\t.ent\t", file);
8229 assemble_name (file, fnname);
8233 assemble_name (file, fnname);
8234 fputs (":\n", file);
8237 /* Stop mips_file_end from treating this function as external. */
8238 if (TARGET_IRIX && mips_abi == ABI_32)
8239 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8241 if (!flag_inhibit_size_directive)
8243 /* .frame FRAMEREG, FRAMESIZE, RETREG */
8245 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8246 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
8247 ", args= " HOST_WIDE_INT_PRINT_DEC
8248 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8249 (reg_names[(frame_pointer_needed)
8250 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
8251 (frame_pointer_needed
8252 ? tsize - cfun->machine->frame.hard_frame_pointer_offset
8254 reg_names[GP_REG_FIRST + 31],
8255 cfun->machine->frame.var_size,
8256 cfun->machine->frame.num_gp,
8257 cfun->machine->frame.num_fp,
8258 cfun->machine->frame.args_size,
8259 cfun->machine->frame.cprestore_size);
8261 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
8262 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8263 cfun->machine->frame.mask,
8264 cfun->machine->frame.gp_save_offset);
8265 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8266 cfun->machine->frame.fmask,
8267 cfun->machine->frame.fp_save_offset);
8270 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
8271 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
8274 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8276 /* Handle the initialization of $gp for SVR4 PIC. */
8277 if (!cfun->machine->all_noreorder_p)
8278 output_asm_insn ("%(.cpload\t%^%)", 0);
8280 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8282 else if (cfun->machine->all_noreorder_p)
8283 output_asm_insn ("%(%<", 0);
8285 /* Tell the assembler which register we're using as the global
8286 pointer. This is needed for thunks, since they can use either
8287 explicit relocs or assembler macros. */
8288 mips_output_cplocal ();
8291 /* Do any necessary cleanup after a function to restore stack, frame,
8294 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
8297 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8298 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8300 /* Reinstate the normal $gp. */
8301 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8302 mips_output_cplocal ();
8304 if (cfun->machine->all_noreorder_p)
8306 /* Avoid using %>%) since it adds excess whitespace. */
8307 output_asm_insn (".set\tmacro", 0);
8308 output_asm_insn (".set\treorder", 0);
8309 set_noreorder = set_nomacro = 0;
8312 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
8316 /* Get the function name the same way that toplev.c does before calling
8317 assemble_start_function. This is needed so that the name used here
8318 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8319 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8320 fputs ("\t.end\t", file);
8321 assemble_name (file, fnname);
8326 /* Save register REG to MEM. Make the instruction frame-related. */
8329 mips_save_reg (rtx reg, rtx mem)
8331 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
8335 if (mips_split_64bit_move_p (mem, reg))
8336 mips_split_doubleword_move (mem, reg);
8338 mips_emit_move (mem, reg);
8340 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
8341 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
8342 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
8347 && REGNO (reg) != GP_REG_FIRST + 31
8348 && !M16_REG_P (REGNO (reg)))
8350 /* Save a non-mips16 register by moving it through a temporary.
8351 We don't need to do this for $31 since there's a special
8352 instruction for it. */
8353 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
8354 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
8357 mips_emit_move (mem, reg);
8359 mips_set_frame_expr (mips_frame_set (mem, reg));
8363 /* The __gnu_local_gp symbol. */
8365 static GTY(()) rtx mips_gnu_local_gp;
8367 /* If we're generating n32 or n64 abicalls, emit instructions
8368 to set up the global pointer. */
8371 mips_emit_loadgp (void)
8373 rtx addr, offset, incoming_address, base, index;
8375 switch (mips_current_loadgp_style ())
8377 case LOADGP_ABSOLUTE:
8378 if (mips_gnu_local_gp == NULL)
8380 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
8381 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
8383 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
8387 addr = XEXP (DECL_RTL (current_function_decl), 0);
8388 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
8389 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8390 emit_insn (gen_loadgp_newabi (offset, incoming_address));
8391 if (!TARGET_EXPLICIT_RELOCS)
8392 emit_insn (gen_loadgp_blockage ());
8396 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
8397 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
8398 emit_insn (gen_loadgp_rtp (base, index));
8399 if (!TARGET_EXPLICIT_RELOCS)
8400 emit_insn (gen_loadgp_blockage ());
8408 /* Expand the prologue into a bunch of separate insns. */
8411 mips_expand_prologue (void)
8417 if (cfun->machine->global_pointer > 0)
8418 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8420 size = cfun->machine->frame.total_size;
8422 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8423 bytes beforehand; this is enough to cover the register save area
8424 without going out of range. */
8425 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
8427 HOST_WIDE_INT step1;
8429 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
8431 if (GENERATE_MIPS16E_SAVE_RESTORE)
8433 HOST_WIDE_INT offset;
8434 unsigned int mask, regno;
8436 /* Try to merge argument stores into the save instruction. */
8437 nargs = mips16e_collect_argument_saves ();
8439 /* Build the save instruction. */
8440 mask = cfun->machine->frame.mask;
8441 insn = mips16e_build_save_restore (false, &mask, &offset,
8443 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8446 /* Check if we need to save other registers. */
8447 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8448 if (BITSET_P (mask, regno - GP_REG_FIRST))
8450 offset -= UNITS_PER_WORD;
8451 mips_save_restore_reg (word_mode, regno,
8452 offset, mips_save_reg);
8457 insn = gen_add3_insn (stack_pointer_rtx,
8460 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8462 mips_for_each_saved_reg (size, mips_save_reg);
8466 /* Allocate the rest of the frame. */
8469 if (SMALL_OPERAND (-size))
8470 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
8472 GEN_INT (-size)))) = 1;
8475 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
8478 /* There are no instructions to add or subtract registers
8479 from the stack pointer, so use the frame pointer as a
8480 temporary. We should always be using a frame pointer
8481 in this case anyway. */
8482 gcc_assert (frame_pointer_needed);
8483 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8484 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
8485 hard_frame_pointer_rtx,
8486 MIPS_PROLOGUE_TEMP (Pmode)));
8487 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
8490 emit_insn (gen_sub3_insn (stack_pointer_rtx,
8492 MIPS_PROLOGUE_TEMP (Pmode)));
8494 /* Describe the combined effect of the previous instructions. */
8496 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8497 plus_constant (stack_pointer_rtx, -size)));
8501 /* Set up the frame pointer, if we're using one. */
8502 if (frame_pointer_needed)
8504 HOST_WIDE_INT offset;
8506 offset = cfun->machine->frame.hard_frame_pointer_offset;
8509 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8510 RTX_FRAME_RELATED_P (insn) = 1;
8512 else if (SMALL_OPERAND (offset))
8514 insn = gen_add3_insn (hard_frame_pointer_rtx,
8515 stack_pointer_rtx, GEN_INT (offset));
8516 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8520 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
8521 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8522 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
8523 hard_frame_pointer_rtx,
8524 MIPS_PROLOGUE_TEMP (Pmode)));
8526 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
8527 plus_constant (stack_pointer_rtx, offset)));
8531 mips_emit_loadgp ();
8533 /* If generating o32/o64 abicalls, save $gp on the stack. */
8534 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
8535 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
8537 /* If we are profiling, make sure no instructions are scheduled before
8538 the call to mcount. */
8540 if (current_function_profile)
8541 emit_insn (gen_blockage ());
8544 /* Emit instructions to restore register REG from slot MEM. */
8547 mips_restore_reg (rtx reg, rtx mem)
8549 /* There's no mips16 instruction to load $31 directly. Load into
8550 $7 instead and adjust the return insn appropriately. */
8551 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
8552 reg = gen_rtx_REG (GET_MODE (reg), 7);
8554 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
8556 /* Can't restore directly; move through a temporary. */
8557 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
8558 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
8561 mips_emit_move (reg, mem);
8565 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
8566 if this epilogue precedes a sibling call, false if it is for a normal
8567 "epilogue" pattern. */
8570 mips_expand_epilogue (int sibcall_p)
8572 HOST_WIDE_INT step1, step2;
8575 if (!sibcall_p && mips_can_use_return_insn ())
8577 emit_jump_insn (gen_return ());
8581 /* In mips16 mode, if the return value should go into a floating-point
8582 register, we need to call a helper routine to copy it over. */
8583 if (mips16_cfun_returns_in_fpr_p ())
8584 mips16_copy_fpr_return_value ();
8586 /* Split the frame into two. STEP1 is the amount of stack we should
8587 deallocate before restoring the registers. STEP2 is the amount we
8588 should deallocate afterwards.
8590 Start off by assuming that no registers need to be restored. */
8591 step1 = cfun->machine->frame.total_size;
8594 /* Work out which register holds the frame address. */
8595 if (!frame_pointer_needed)
8596 base = stack_pointer_rtx;
8599 base = hard_frame_pointer_rtx;
8600 step1 -= cfun->machine->frame.hard_frame_pointer_offset;
8603 /* If we need to restore registers, deallocate as much stack as
8604 possible in the second step without going out of range. */
8605 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
8607 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
8611 /* Set TARGET to BASE + STEP1. */
8617 /* Get an rtx for STEP1 that we can add to BASE. */
8618 adjust = GEN_INT (step1);
8619 if (!SMALL_OPERAND (step1))
8621 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
8622 adjust = MIPS_EPILOGUE_TEMP (Pmode);
8625 /* Normal mode code can copy the result straight into $sp. */
8627 target = stack_pointer_rtx;
8629 emit_insn (gen_add3_insn (target, base, adjust));
8632 /* Copy TARGET into the stack pointer. */
8633 if (target != stack_pointer_rtx)
8634 mips_emit_move (stack_pointer_rtx, target);
8636 /* If we're using addressing macros, $gp is implicitly used by all
8637 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8639 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
8640 emit_insn (gen_blockage ());
8642 if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
8644 unsigned int regno, mask;
8645 HOST_WIDE_INT offset;
8648 /* Generate the restore instruction. */
8649 mask = cfun->machine->frame.mask;
8650 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
8652 /* Restore any other registers manually. */
8653 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8654 if (BITSET_P (mask, regno - GP_REG_FIRST))
8656 offset -= UNITS_PER_WORD;
8657 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
8660 /* Restore the remaining registers and deallocate the final bit
8662 emit_insn (restore);
8666 /* Restore the registers. */
8667 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
8670 /* Deallocate the final bit of the frame. */
8672 emit_insn (gen_add3_insn (stack_pointer_rtx,
8677 /* Add in the __builtin_eh_return stack adjustment. We need to
8678 use a temporary in mips16 code. */
8679 if (current_function_calls_eh_return)
8683 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
8684 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
8685 MIPS_EPILOGUE_TEMP (Pmode),
8686 EH_RETURN_STACKADJ_RTX));
8687 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
8690 emit_insn (gen_add3_insn (stack_pointer_rtx,
8692 EH_RETURN_STACKADJ_RTX));
8697 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8698 path will restore the return address into $7 rather than $31. */
8700 && !GENERATE_MIPS16E_SAVE_RESTORE
8701 && (cfun->machine->frame.mask & RA_MASK) != 0)
8702 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
8703 GP_REG_FIRST + 7)));
8705 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
8706 GP_REG_FIRST + 31)));
8710 /* Return nonzero if this function is known to have a null epilogue.
8711 This allows the optimizer to omit jumps to jumps if no stack
8715 mips_can_use_return_insn (void)
8717 if (! reload_completed)
8720 if (current_function_profile)
8723 /* In mips16 mode, a function that returns a floating point value
8724 needs to arrange to copy the return value into the floating point
8726 if (mips16_cfun_returns_in_fpr_p ())
8729 return cfun->machine->frame.total_size == 0;
8732 /* Return true if register REGNO can store a value of mode MODE.
8733 The result of this function is cached in mips_hard_regno_mode_ok. */
8736 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
8739 enum mode_class class;
8741 if (mode == CCV2mode)
8744 && (regno - ST_REG_FIRST) % 2 == 0);
8746 if (mode == CCV4mode)
8749 && (regno - ST_REG_FIRST) % 4 == 0);
8754 return regno == FPSW_REGNUM;
8756 return (ST_REG_P (regno)
8758 || FP_REG_P (regno));
8761 size = GET_MODE_SIZE (mode);
8762 class = GET_MODE_CLASS (mode);
8764 if (GP_REG_P (regno))
8765 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
8767 if (FP_REG_P (regno)
8768 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
8769 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
8771 /* Allow TFmode for CCmode reloads. */
8772 if (mode == TFmode && ISA_HAS_8CC)
8775 if (class == MODE_FLOAT
8776 || class == MODE_COMPLEX_FLOAT
8777 || class == MODE_VECTOR_FLOAT)
8778 return size <= UNITS_PER_FPVALUE;
8780 /* Allow integer modes that fit into a single register. We need
8781 to put integers into FPRs when using instructions like CVT
8782 and TRUNC. There's no point allowing sizes smaller than a word,
8783 because the FPU has no appropriate load/store instructions. */
8784 if (class == MODE_INT)
8785 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
8788 if (ACC_REG_P (regno)
8789 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
8791 if (size <= UNITS_PER_WORD)
8794 if (size <= UNITS_PER_WORD * 2)
8795 return (DSP_ACC_REG_P (regno)
8796 ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0
8797 : regno == MD_REG_FIRST);
8800 if (ALL_COP_REG_P (regno))
8801 return class == MODE_INT && size <= UNITS_PER_WORD;
8806 /* Implement HARD_REGNO_NREGS. */
8809 mips_hard_regno_nregs (int regno, enum machine_mode mode)
8811 if (ST_REG_P (regno))
8812 /* The size of FP status registers is always 4, because they only hold
8813 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8814 return (GET_MODE_SIZE (mode) + 3) / 4;
8816 if (FP_REG_P (regno))
8817 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8819 /* All other registers are word-sized. */
8820 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8823 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8824 in mips_hard_regno_nregs. */
8827 mips_class_max_nregs (enum reg_class class, enum machine_mode mode)
8833 COPY_HARD_REG_SET (left, reg_class_contents[(int) class]);
8834 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
8836 size = MIN (size, 4);
8837 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
8839 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
8841 size = MIN (size, UNITS_PER_FPREG);
8842 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
8844 if (!hard_reg_set_empty_p (left))
8845 size = MIN (size, UNITS_PER_WORD);
8846 return (GET_MODE_SIZE (mode) + size - 1) / size;
8849 /* Return true if registers of class CLASS cannot change from mode FROM
8853 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
8854 enum machine_mode to ATTRIBUTE_UNUSED,
8855 enum reg_class class)
8857 /* There are several problems with changing the modes of values
8858 in floating-point registers:
8860 - When a multi-word value is stored in paired floating-point
8861 registers, the first register always holds the low word.
8862 We therefore can't allow FPRs to change between single-word
8863 and multi-word modes on big-endian targets.
8865 - GCC assumes that each word of a multiword register can be accessed
8866 individually using SUBREGs. This is not true for floating-point
8867 registers if they are bigger than a word.
8869 - Loading a 32-bit value into a 64-bit floating-point register
8870 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8871 We can't allow FPRs to change from SImode to to a wider mode on
8874 - If the FPU has already interpreted a value in one format, we must
8875 not ask it to treat the value as having a different format.
8877 We therefore only allow changes between 4-byte and smaller integer
8878 values, all of which have the "W" format as far as the FPU is
8880 return (reg_classes_intersect_p (FP_REGS, class)
8881 && (GET_MODE_CLASS (from) != MODE_INT
8882 || GET_MODE_CLASS (to) != MODE_INT
8883 || GET_MODE_SIZE (from) > 4
8884 || GET_MODE_SIZE (to) > 4));
8887 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
8890 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
8895 return TARGET_HARD_FLOAT;
8898 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
8901 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
8908 /* Implement PREFERRED_RELOAD_CLASS. */
8911 mips_preferred_reload_class (rtx x, enum reg_class class)
8913 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8916 if (reg_class_subset_p (FP_REGS, class)
8917 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
8920 if (reg_class_subset_p (GR_REGS, class))
8923 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8929 /* Return a number assessing the cost of moving a register in class
8930 FROM to class TO. The classes are expressed using the enumeration
8931 values such as `GENERAL_REGS'. A value of 2 is the default; other
8932 values are interpreted relative to that.
8934 It is not required that the cost always equal 2 when FROM is the
8935 same as TO; on some machines it is expensive to move between
8936 registers if they are not general registers.
8938 If reload sees an insn consisting of a single `set' between two
8939 hard registers, and if `REGISTER_MOVE_COST' applied to their
8940 classes returns a value of 2, reload does not check to ensure that
8941 the constraints of the insn are met. Setting a cost of other than
8942 2 will allow reload to verify that the constraints are met. You
8943 should do this if the `movM' pattern's constraints do not allow
8946 ??? We make the cost of moving from HI/LO into general
8947 registers the same as for one of moving general registers to
8948 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8949 pseudo to HI/LO. This might hurt optimizations though, it
8950 isn't clear if it is wise. And it might not work in all cases. We
8951 could solve the DImode LO reg problem by using a multiply, just
8952 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8953 problem by using divide instructions. divu puts the remainder in
8954 the HI reg, so doing a divide by -1 will move the value in the HI
8955 reg for all values except -1. We could handle that case by using a
8956 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8957 a compare/branch to test the input value to see which instruction
8958 we need to use. This gets pretty messy, but it is feasible. */
8961 mips_register_move_cost (enum machine_mode mode,
8962 enum reg_class to, enum reg_class from)
8966 if (reg_class_subset_p (from, GENERAL_REGS)
8967 && reg_class_subset_p (to, GENERAL_REGS))
8969 if (reg_class_subset_p (from, M16_REGS)
8970 || reg_class_subset_p (to, M16_REGS))
8976 else if (reg_class_subset_p (from, GENERAL_REGS))
8978 if (reg_class_subset_p (to, GENERAL_REGS))
8980 if (reg_class_subset_p (to, FP_REGS))
8982 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
8984 if (reg_class_subset_p (to, ACC_REGS))
8987 else if (reg_class_subset_p (to, GENERAL_REGS))
8989 if (reg_class_subset_p (from, FP_REGS))
8991 if (reg_class_subset_p (from, ST_REGS))
8992 /* LUI followed by MOVF. */
8994 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
8996 if (reg_class_subset_p (from, ACC_REGS))
8999 else if (reg_class_subset_p (from, FP_REGS))
9001 if (reg_class_subset_p (to, FP_REGS)
9002 && mips_mode_ok_for_mov_fmt_p (mode))
9004 if (reg_class_subset_p (to, ST_REGS))
9005 /* An expensive sequence. */
9012 /* This function returns the register class required for a secondary
9013 register when copying between one of the registers in CLASS, and X,
9014 using MODE. If IN_P is nonzero, the copy is going from X to the
9015 register, otherwise the register is the source. A return value of
9016 NO_REGS means that no secondary register is required. */
9019 mips_secondary_reload_class (enum reg_class class,
9020 enum machine_mode mode, rtx x, int in_p)
9024 /* If X is a constant that cannot be loaded into $25, it must be loaded
9025 into some other GPR. No other register class allows a direct move. */
9026 if (mips_dangerous_for_la25_p (x))
9027 return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
9029 regno = true_regnum (x);
9032 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9033 if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
9036 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9037 if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
9043 /* Copying from accumulator registers to anywhere other than a general
9044 register requires a temporary general register. */
9045 if (reg_class_subset_p (class, ACC_REGS))
9046 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9047 if (ACC_REG_P (regno))
9048 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9050 /* We can only copy a value to a condition code register from a
9051 floating point register, and even then we require a scratch
9052 floating point register. We can only copy a value out of a
9053 condition code register into a general register. */
9054 if (reg_class_subset_p (class, ST_REGS))
9058 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9060 if (ST_REG_P (regno))
9064 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9067 if (reg_class_subset_p (class, FP_REGS))
9070 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9071 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9072 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9075 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9076 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9079 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9080 /* We can force the constant to memory and use lwc1
9081 and ldc1. As above, we will use pairs of lwc1s if
9082 ldc1 is not supported. */
9085 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9086 /* In this case we can use mov.fmt. */
9089 /* Otherwise, we need to reload through an integer register. */
9092 if (FP_REG_P (regno))
9093 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9098 /* SImode values are represented as sign-extended to DImode. */
9101 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9103 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9110 mips_valid_pointer_mode (enum machine_mode mode)
9112 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9115 /* Target hook for vector_mode_supported_p. */
9118 mips_vector_mode_supported_p (enum machine_mode mode)
9123 return TARGET_PAIRED_SINGLE_FLOAT;
9140 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9143 mips_scalar_mode_supported_p (enum machine_mode mode)
9145 if (ALL_FIXED_POINT_MODE_P (mode)
9146 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9149 return default_scalar_mode_supported_p (mode);
9151 /* This function does three things:
9153 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9154 - Register the mips16 hardware floating point stubs.
9155 - Register the gofast functions if selected using --enable-gofast. */
9157 #include "config/gofast.h"
9160 mips_init_libfuncs (void)
9162 if (TARGET_FIX_VR4120)
9164 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9165 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9168 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9170 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9171 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9172 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9173 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9175 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9176 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9177 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9178 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9179 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9180 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9181 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9183 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9184 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9185 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9187 if (TARGET_DOUBLE_FLOAT)
9189 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9190 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9191 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9192 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9194 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9195 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9196 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9197 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9198 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9199 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9200 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9202 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9203 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9205 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9206 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9207 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__mips16_floatunsidf");
9211 gofast_maybe_init_libfuncs ();
9214 /* Return the length of INSN. LENGTH is the initial length computed by
9215 attributes in the machine-description file. */
9218 mips_adjust_insn_length (rtx insn, int length)
9220 /* A unconditional jump has an unfilled delay slot if it is not part
9221 of a sequence. A conditional jump normally has a delay slot, but
9222 does not on MIPS16. */
9223 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9226 /* See how many nops might be needed to avoid hardware hazards. */
9227 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9228 switch (get_attr_hazard (insn))
9242 /* All MIPS16 instructions are a measly two bytes. */
9250 /* Return an asm sequence to start a noat block and load the address
9251 of a label into $1. */
9254 mips_output_load_label (void)
9256 if (TARGET_EXPLICIT_RELOCS)
9260 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9263 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9266 if (ISA_HAS_LOAD_DELAY)
9267 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9268 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9272 if (Pmode == DImode)
9273 return "%[dla\t%@,%0";
9275 return "%[la\t%@,%0";
9279 /* Return the assembly code for INSN, which has the operands given by
9280 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9281 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9282 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9283 version of BRANCH_IF_TRUE. */
9286 mips_output_conditional_branch (rtx insn, rtx *operands,
9287 const char *branch_if_true,
9288 const char *branch_if_false)
9290 unsigned int length;
9291 rtx taken, not_taken;
9293 length = get_attr_length (insn);
9296 /* Just a simple conditional branch. */
9297 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9298 return branch_if_true;
9301 /* Generate a reversed branch around a direct jump. This fallback does
9302 not use branch-likely instructions. */
9303 mips_branch_likely = false;
9304 not_taken = gen_label_rtx ();
9305 taken = operands[1];
9307 /* Generate the reversed branch to NOT_TAKEN. */
9308 operands[1] = not_taken;
9309 output_asm_insn (branch_if_false, operands);
9311 /* If INSN has a delay slot, we must provide delay slots for both the
9312 branch to NOT_TAKEN and the conditional jump. We must also ensure
9313 that INSN's delay slot is executed in the appropriate cases. */
9316 /* This first delay slot will always be executed, so use INSN's
9317 delay slot if is not annulled. */
9318 if (!INSN_ANNULLED_BRANCH_P (insn))
9320 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9321 asm_out_file, optimize, 1, NULL);
9322 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9325 output_asm_insn ("nop", 0);
9326 fprintf (asm_out_file, "\n");
9329 /* Output the unconditional branch to TAKEN. */
9331 output_asm_insn ("j\t%0%/", &taken);
9334 output_asm_insn (mips_output_load_label (), &taken);
9335 output_asm_insn ("jr\t%@%]%/", 0);
9338 /* Now deal with its delay slot; see above. */
9341 /* This delay slot will only be executed if the branch is taken.
9342 Use INSN's delay slot if is annulled. */
9343 if (INSN_ANNULLED_BRANCH_P (insn))
9345 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9346 asm_out_file, optimize, 1, NULL);
9347 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9350 output_asm_insn ("nop", 0);
9351 fprintf (asm_out_file, "\n");
9354 /* Output NOT_TAKEN. */
9355 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9356 CODE_LABEL_NUMBER (not_taken));
9360 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9361 if some ordered condition is true. The condition is given by
9362 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9363 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9364 its second is always zero. */
9367 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9369 const char *branch[2];
9371 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9372 Make BRANCH[0] branch on the inverse condition. */
9373 switch (GET_CODE (operands[0]))
9375 /* These cases are equivalent to comparisons against zero. */
9377 inverted_p = !inverted_p;
9380 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9381 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9384 /* These cases are always true or always false. */
9386 inverted_p = !inverted_p;
9389 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9390 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9394 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9395 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9398 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9401 /* Used to output div or ddiv instruction DIVISION, which has the operands
9402 given by OPERANDS. Add in a divide-by-zero check if needed.
9404 When working around R4000 and R4400 errata, we need to make sure that
9405 the division is not immediately followed by a shift[1][2]. We also
9406 need to stop the division from being put into a branch delay slot[3].
9407 The easiest way to avoid both problems is to add a nop after the
9408 division. When a divide-by-zero check is needed, this nop can be
9409 used to fill the branch delay slot.
9411 [1] If a double-word or a variable shift executes immediately
9412 after starting an integer division, the shift may give an
9413 incorrect result. See quotations of errata #16 and #28 from
9414 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9415 in mips.md for details.
9417 [2] A similar bug to [1] exists for all revisions of the
9418 R4000 and the R4400 when run in an MC configuration.
9419 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9421 "19. In this following sequence:
9423 ddiv (or ddivu or div or divu)
9424 dsll32 (or dsrl32, dsra32)
9426 if an MPT stall occurs, while the divide is slipping the cpu
9427 pipeline, then the following double shift would end up with an
9430 Workaround: The compiler needs to avoid generating any
9431 sequence with divide followed by extended double shift."
9433 This erratum is also present in "MIPS R4400MC Errata, Processor
9434 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9435 & 3.0" as errata #10 and #4, respectively.
9437 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9438 (also valid for MIPS R4000MC processors):
9440 "52. R4000SC: This bug does not apply for the R4000PC.
9442 There are two flavors of this bug:
9444 1) If the instruction just after divide takes an RF exception
9445 (tlb-refill, tlb-invalid) and gets an instruction cache
9446 miss (both primary and secondary) and the line which is
9447 currently in secondary cache at this index had the first
9448 data word, where the bits 5..2 are set, then R4000 would
9449 get a wrong result for the div.
9454 ------------------- # end-of page. -tlb-refill
9459 ------------------- # end-of page. -tlb-invalid
9462 2) If the divide is in the taken branch delay slot, where the
9463 target takes RF exception and gets an I-cache miss for the
9464 exception vector or where I-cache miss occurs for the
9465 target address, under the above mentioned scenarios, the
9466 div would get wrong results.
9469 j r2 # to next page mapped or unmapped
9470 div r8,r9 # this bug would be there as long
9471 # as there is an ICache miss and
9472 nop # the "data pattern" is present
9475 beq r0, r0, NextPage # to Next page
9479 This bug is present for div, divu, ddiv, and ddivu
9482 Workaround: For item 1), OS could make sure that the next page
9483 after the divide instruction is also mapped. For item 2), the
9484 compiler could make sure that the divide instruction is not in
9485 the branch delay slot."
9487 These processors have PRId values of 0x00004220 and 0x00004300 for
9488 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9491 mips_output_division (const char *division, rtx *operands)
9496 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9498 output_asm_insn (s, operands);
9501 if (TARGET_CHECK_ZERO_DIV)
9505 output_asm_insn (s, operands);
9506 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9508 else if (GENERATE_DIVIDE_TRAPS)
9510 output_asm_insn (s, operands);
9515 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9516 output_asm_insn (s, operands);
9517 s = "break\t7%)\n1:";
9523 /* Return true if INSN is a multiply-add or multiply-subtract
9524 instruction and PREV assigns to the accumulator operand. */
9527 mips_linked_madd_p (rtx prev, rtx insn)
9531 x = single_set (insn);
9537 if (GET_CODE (x) == PLUS
9538 && GET_CODE (XEXP (x, 0)) == MULT
9539 && reg_set_p (XEXP (x, 1), prev))
9542 if (GET_CODE (x) == MINUS
9543 && GET_CODE (XEXP (x, 1)) == MULT
9544 && reg_set_p (XEXP (x, 0), prev))
9550 /* Implements a store data bypass check. We need this because the cprestore
9551 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9552 default routine to abort. We just return false for that case. */
9553 /* ??? Should try to give a better result here than assuming false. */
9556 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9558 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9561 return ! store_data_bypass_p (out_insn, in_insn);
9564 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9565 dependencies have no cost, except on the 20Kc where output-dependence
9566 is treated like input-dependence. */
9569 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9570 rtx dep ATTRIBUTE_UNUSED, int cost)
9572 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
9575 if (REG_NOTE_KIND (link) != 0)
9580 /* Return the number of instructions that can be issued per cycle. */
9583 mips_issue_rate (void)
9587 case PROCESSOR_74KC:
9588 case PROCESSOR_74KF2_1:
9589 case PROCESSOR_74KF1_1:
9590 case PROCESSOR_74KF3_2:
9591 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9592 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9593 but in reality only a maximum of 3 insns can be issued as the
9594 floating point load/stores also require a slot in the AGEN pipe. */
9597 case PROCESSOR_20KC:
9598 case PROCESSOR_R4130:
9599 case PROCESSOR_R5400:
9600 case PROCESSOR_R5500:
9601 case PROCESSOR_R7000:
9602 case PROCESSOR_R9000:
9606 case PROCESSOR_SB1A:
9607 /* This is actually 4, but we get better performance if we claim 3.
9608 This is partly because of unwanted speculative code motion with the
9609 larger number, and partly because in most common cases we can't
9610 reach the theoretical max of 4. */
9618 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9619 be as wide as the scheduling freedom in the DFA. */
9622 mips_multipass_dfa_lookahead (void)
9624 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9631 /* Remove the instruction at index LOWER from ready queue READY and
9632 reinsert it in front of the instruction at index HIGHER. LOWER must
9636 mips_promote_ready (rtx *ready, int lower, int higher)
9641 new_head = ready[lower];
9642 for (i = lower; i < higher; i++)
9643 ready[i] = ready[i + 1];
9644 ready[i] = new_head;
9647 /* If the priority of the instruction at POS2 in the ready queue READY
9648 is within LIMIT units of that of the instruction at POS1, swap the
9649 instructions if POS2 is not already less than POS1. */
9652 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
9655 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
9659 ready[pos1] = ready[pos2];
9664 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9665 that may clobber hi or lo. */
9667 static rtx mips_macc_chains_last_hilo;
9669 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9670 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9673 mips_macc_chains_record (rtx insn)
9675 if (get_attr_may_clobber_hilo (insn))
9676 mips_macc_chains_last_hilo = insn;
9679 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9680 has NREADY elements, looking for a multiply-add or multiply-subtract
9681 instruction that is cumulative with mips_macc_chains_last_hilo.
9682 If there is one, promote it ahead of anything else that might
9683 clobber hi or lo. */
9686 mips_macc_chains_reorder (rtx *ready, int nready)
9690 if (mips_macc_chains_last_hilo != 0)
9691 for (i = nready - 1; i >= 0; i--)
9692 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9694 for (j = nready - 1; j > i; j--)
9695 if (recog_memoized (ready[j]) >= 0
9696 && get_attr_may_clobber_hilo (ready[j]))
9698 mips_promote_ready (ready, i, j);
9705 /* The last instruction to be scheduled. */
9707 static rtx vr4130_last_insn;
9709 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9710 points to an rtx that is initially an instruction. Nullify the rtx
9711 if the instruction uses the value of register X. */
9714 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9716 rtx *insn_ptr = data;
9719 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9723 /* Return true if there is true register dependence between vr4130_last_insn
9727 vr4130_true_reg_dependence_p (rtx insn)
9729 note_stores (PATTERN (vr4130_last_insn),
9730 vr4130_true_reg_dependence_p_1, &insn);
9734 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9735 the ready queue and that INSN2 is the instruction after it, return
9736 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9737 in which INSN1 and INSN2 can probably issue in parallel, but for
9738 which (INSN2, INSN1) should be less sensitive to instruction
9739 alignment than (INSN1, INSN2). See 4130.md for more details. */
9742 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9744 sd_iterator_def sd_it;
9747 /* Check for the following case:
9749 1) there is some other instruction X with an anti dependence on INSN1;
9750 2) X has a higher priority than INSN2; and
9751 3) X is an arithmetic instruction (and thus has no unit restrictions).
9753 If INSN1 is the last instruction blocking X, it would better to
9754 choose (INSN1, X) over (INSN2, INSN1). */
9755 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
9756 if (DEP_TYPE (dep) == REG_DEP_ANTI
9757 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
9758 && recog_memoized (DEP_CON (dep)) >= 0
9759 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
9762 if (vr4130_last_insn != 0
9763 && recog_memoized (insn1) >= 0
9764 && recog_memoized (insn2) >= 0)
9766 /* See whether INSN1 and INSN2 use different execution units,
9767 or if they are both ALU-type instructions. If so, they can
9768 probably execute in parallel. */
9769 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9770 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9771 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9773 /* If only one of the instructions has a dependence on
9774 vr4130_last_insn, prefer to schedule the other one first. */
9775 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9776 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9780 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9781 is not an ALU-type instruction and if INSN1 uses the same
9782 execution unit. (Note that if this condition holds, we already
9783 know that INSN2 uses a different execution unit.) */
9784 if (class1 != VR4130_CLASS_ALU
9785 && recog_memoized (vr4130_last_insn) >= 0
9786 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9793 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9794 queue with at least two instructions. Swap the first two if
9795 vr4130_swap_insns_p says that it could be worthwhile. */
9798 vr4130_reorder (rtx *ready, int nready)
9800 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9801 mips_promote_ready (ready, nready - 2, nready - 1);
9804 /* Record whether last 74k AGEN instruction was a load or store. */
9806 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
9808 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9809 resets to TYPE_UNKNOWN state. */
9812 mips_74k_agen_init (rtx insn)
9814 if (!insn || !NONJUMP_INSN_P (insn))
9815 mips_last_74k_agen_insn = TYPE_UNKNOWN;
9816 else if (USEFUL_INSN_P (insn))
9818 enum attr_type type = get_attr_type (insn);
9819 if (type == TYPE_LOAD || type == TYPE_STORE)
9820 mips_last_74k_agen_insn = type;
9824 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9825 loads to be grouped together, and multiple stores to be grouped
9826 together. Swap things around in the ready queue to make this happen. */
9829 mips_74k_agen_reorder (rtx *ready, int nready)
9832 int store_pos, load_pos;
9837 for (i = nready - 1; i >= 0; i--)
9839 rtx insn = ready[i];
9840 if (USEFUL_INSN_P (insn))
9841 switch (get_attr_type (insn))
9844 if (store_pos == -1)
9858 if (load_pos == -1 || store_pos == -1)
9861 switch (mips_last_74k_agen_insn)
9864 /* Prefer to schedule loads since they have a higher latency. */
9866 /* Swap loads to the front of the queue. */
9867 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
9870 /* Swap stores to the front of the queue. */
9871 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
9878 /* Implement TARGET_SCHED_INIT. */
9881 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9882 int max_ready ATTRIBUTE_UNUSED)
9884 mips_macc_chains_last_hilo = 0;
9885 vr4130_last_insn = 0;
9886 mips_74k_agen_init (NULL_RTX);
9889 /* Implement TARGET_SCHED_REORDER and TARG_SCHED_REORDER2. */
9892 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9893 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
9895 if (!reload_completed
9898 mips_macc_chains_reorder (ready, *nreadyp);
9899 if (reload_completed
9901 && !TARGET_VR4130_ALIGN
9903 vr4130_reorder (ready, *nreadyp);
9905 mips_74k_agen_reorder (ready, *nreadyp);
9906 return mips_issue_rate ();
9909 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9912 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9916 mips_74k_agen_init (insn);
9917 switch (GET_CODE (PATTERN (insn)))
9921 /* Don't count USEs and CLOBBERs against the issue rate. */
9926 if (!reload_completed && TUNE_MACC_CHAINS)
9927 mips_macc_chains_record (insn);
9928 vr4130_last_insn = insn;
9934 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9935 return the first operand of the associated "pref" or "prefx" insn. */
9938 mips_prefetch_cookie (rtx write, rtx locality)
9940 /* store_streamed / load_streamed. */
9941 if (INTVAL (locality) <= 0)
9942 return GEN_INT (INTVAL (write) + 4);
9945 if (INTVAL (locality) <= 2)
9948 /* store_retained / load_retained. */
9949 return GEN_INT (INTVAL (write) + 6);
9952 /* MIPS builtin function support. */
9954 struct builtin_description
9956 /* The code of the main .md file instruction. See mips_builtin_type
9957 for more information. */
9958 enum insn_code icode;
9960 /* The floating-point comparison code to use with ICODE, if any. */
9961 enum mips_fp_condition cond;
9963 /* The name of the builtin function. */
9966 /* Specifies how the function should be expanded. */
9967 enum mips_builtin_type builtin_type;
9969 /* The function's prototype. */
9970 enum mips_function_type function_type;
9972 /* The target flags required for this function. */
9976 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9977 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9978 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9979 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9980 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9982 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9984 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9985 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9986 "__builtin_mips_" #INSN "_" #COND "_s", \
9987 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9988 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9989 "__builtin_mips_" #INSN "_" #COND "_d", \
9990 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9992 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9993 The lower and upper forms require TARGET_FLAGS while the any and all
9994 forms require MASK_MIPS3D. */
9995 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9996 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9997 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9998 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9999 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10000 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10001 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10002 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10003 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10004 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10005 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10006 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10007 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10009 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10010 require MASK_MIPS3D. */
10011 #define CMP_4S_BUILTINS(INSN, COND) \
10012 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10013 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10014 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10016 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10017 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10018 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10021 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10022 instruction requires TARGET_FLAGS. */
10023 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10024 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10025 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10026 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10028 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10029 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10030 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10033 /* Define all the builtins related to c.cond.fmt condition COND. */
10034 #define CMP_BUILTINS(COND) \
10035 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10036 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10037 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10038 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10039 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10040 CMP_4S_BUILTINS (c, COND), \
10041 CMP_4S_BUILTINS (cabs, COND)
10043 static const struct builtin_description mips_bdesc[] =
10045 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10046 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10047 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10048 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10049 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10050 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10051 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10052 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10054 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10055 MASK_PAIRED_SINGLE_FLOAT),
10056 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10057 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10058 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10059 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10061 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10062 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10063 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10064 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10065 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10066 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10068 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10069 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10070 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10071 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10072 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10073 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10075 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10078 /* Builtin functions for the SB-1 processor. */
10080 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10082 static const struct builtin_description sb1_bdesc[] =
10084 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10087 /* Builtin functions for DSP ASE. */
10089 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10090 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10091 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10092 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10093 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10095 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10096 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10097 builtin_description fields. */
10098 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10099 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10100 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10102 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10103 branch instruction. TARGET_FLAGS is a builtin_description field. */
10104 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10105 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10106 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10108 static const struct builtin_description dsp_bdesc[] =
10110 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10111 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10112 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10113 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10114 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10115 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10116 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10117 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10118 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10119 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10120 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10121 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10122 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10123 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10124 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10125 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10126 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10127 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10128 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10129 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10130 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10131 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10132 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10133 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10134 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10135 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10136 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10137 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10138 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10139 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10140 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10141 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10142 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10143 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10144 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10145 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10146 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10147 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10148 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10149 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10150 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10151 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10152 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10153 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10154 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10155 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10156 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10157 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10158 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10159 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10160 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10161 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10162 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10163 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10164 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10165 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10166 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10167 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10168 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10169 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10170 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10171 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10172 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10173 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10174 BPOSGE_BUILTIN (32, MASK_DSP),
10176 /* The following are for the MIPS DSP ASE REV 2. */
10177 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
10178 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10179 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10180 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10181 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10182 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10183 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10184 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10185 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10186 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10187 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10188 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10189 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10190 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10191 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10192 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10193 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10194 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10195 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10196 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10197 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10198 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
10199 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10200 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10201 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10202 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10203 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10204 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10205 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10206 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10207 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10208 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10209 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10210 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
10213 static const struct builtin_description dsp_32only_bdesc[] =
10215 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10216 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10217 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10218 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10219 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10220 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10221 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10222 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10223 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10224 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10225 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10226 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10227 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10228 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10229 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10230 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10231 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10232 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10233 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10234 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10235 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10237 /* The following are for the MIPS DSP ASE REV 2. */
10238 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10239 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10240 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10241 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10242 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10243 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10244 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10245 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
10246 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
10247 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10248 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10249 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10250 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10251 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10252 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
10255 /* This helps provide a mapping from builtin function codes to bdesc
10260 /* The builtin function table that this entry describes. */
10261 const struct builtin_description *bdesc;
10263 /* The number of entries in the builtin function table. */
10266 /* The target processor that supports these builtin functions.
10267 PROCESSOR_MAX means we enable them for all processors. */
10268 enum processor_type proc;
10270 /* If the target has these flags, this builtin function table
10271 will not be supported. */
10272 int unsupported_target_flags;
10275 static const struct bdesc_map bdesc_arrays[] =
10277 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
10278 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
10279 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
10280 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
10284 /* MODE is a vector mode whose elements have type TYPE. Return the type
10285 of the vector itself. */
10288 mips_builtin_vector_type (tree type, enum machine_mode mode)
10290 static tree types[(int) MAX_MACHINE_MODE];
10292 if (types[(int) mode] == NULL_TREE)
10293 types[(int) mode] = build_vector_type_for_mode (type, mode);
10294 return types[(int) mode];
10297 /* Source-level argument types. */
10298 #define MIPS_ATYPE_VOID void_type_node
10299 #define MIPS_ATYPE_INT integer_type_node
10300 #define MIPS_ATYPE_POINTER ptr_type_node
10302 /* Standard mode-based argument types. */
10303 #define MIPS_ATYPE_SI intSI_type_node
10304 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10305 #define MIPS_ATYPE_DI intDI_type_node
10306 #define MIPS_ATYPE_SF float_type_node
10307 #define MIPS_ATYPE_DF double_type_node
10309 /* Vector argument types. */
10310 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10311 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10312 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10314 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10315 their associated MIPS_ATYPEs. */
10316 #define MIPS_FTYPE_ATYPES1(A, B) \
10317 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10319 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10320 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10322 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10323 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10325 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10326 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10329 /* Return the function type associated with function prototype TYPE. */
10332 mips_build_function_type (enum mips_function_type type)
10334 static tree types[(int) MIPS_MAX_FTYPE_MAX];
10336 if (types[(int) type] == NULL_TREE)
10339 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10340 case MIPS_FTYPE_NAME##NUM ARGS: \
10341 types[(int) type] \
10342 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10345 #include "config/mips/mips-ftypes.def"
10346 #undef DEF_MIPS_FTYPE
10348 gcc_unreachable ();
10351 return types[(int) type];
10354 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10357 mips_init_builtins (void)
10359 const struct builtin_description *d;
10360 const struct bdesc_map *m;
10361 unsigned int offset;
10363 /* Iterate through all of the bdesc arrays, initializing all of the
10364 builtin functions. */
10367 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10369 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10370 && (m->unsupported_target_flags & target_flags) == 0)
10371 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10372 if ((d->target_flags & target_flags) == d->target_flags)
10373 add_builtin_function (d->name,
10374 mips_build_function_type (d->function_type),
10375 d - m->bdesc + offset,
10376 BUILT_IN_MD, NULL, NULL);
10381 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
10382 suitable for input operand OP of instruction ICODE. Return the value. */
10385 mips_prepare_builtin_arg (enum insn_code icode,
10386 unsigned int op, tree exp, unsigned int argnum)
10389 enum machine_mode mode;
10391 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
10392 mode = insn_data[icode].operand[op].mode;
10393 if (!insn_data[icode].operand[op].predicate (value, mode))
10395 value = copy_to_mode_reg (mode, value);
10396 /* Check the predicate again. */
10397 if (!insn_data[icode].operand[op].predicate (value, mode))
10399 error ("invalid argument to builtin function");
10407 /* Return an rtx suitable for output operand OP of instruction ICODE.
10408 If TARGET is non-null, try to use it where possible. */
10411 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10413 enum machine_mode mode;
10415 mode = insn_data[icode].operand[op].mode;
10416 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10417 target = gen_reg_rtx (mode);
10422 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10423 .md pattern and CALL is the function expr with arguments. TARGET,
10424 if nonnull, suggests a good place to put the result.
10425 HAS_TARGET indicates the function must return something. */
10428 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
10431 rtx ops[MAX_RECOG_OPERANDS];
10437 /* We save target to ops[0]. */
10438 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10442 /* We need to test if the arglist is not zero. Some instructions have extra
10443 clobber registers. */
10444 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
10445 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
10450 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10454 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10458 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10462 gcc_unreachable ();
10467 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10468 function (TYPE says which). EXP is the tree for the function
10469 function, ICODE is the instruction that should be used to compare
10470 the first two arguments, and COND is the condition it should test.
10471 TARGET, if nonnull, suggests a good place to put the result. */
10474 mips_expand_builtin_movtf (enum mips_builtin_type type,
10475 enum insn_code icode, enum mips_fp_condition cond,
10476 rtx target, tree exp)
10478 rtx cmp_result, op0, op1;
10480 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10481 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
10482 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
10483 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10485 icode = CODE_FOR_mips_cond_move_tf_ps;
10486 target = mips_prepare_builtin_target (icode, 0, target);
10487 if (type == MIPS_BUILTIN_MOVT)
10489 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
10490 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
10494 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
10495 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
10497 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10501 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10502 into TARGET otherwise. Return TARGET. */
10505 mips_builtin_branch_and_move (rtx condition, rtx target,
10506 rtx value_if_true, rtx value_if_false)
10508 rtx true_label, done_label;
10510 true_label = gen_label_rtx ();
10511 done_label = gen_label_rtx ();
10513 /* First assume that CONDITION is false. */
10514 mips_emit_move (target, value_if_false);
10516 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10517 emit_jump_insn (gen_condjump (condition, true_label));
10518 emit_jump_insn (gen_jump (done_label));
10521 /* Fix TARGET if CONDITION is true. */
10522 emit_label (true_label);
10523 mips_emit_move (target, value_if_true);
10525 emit_label (done_label);
10529 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10530 of the comparison instruction and COND is the condition it should test.
10531 EXP is the function call and arguments and TARGET, if nonnull,
10532 suggests a good place to put the boolean result. */
10535 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10536 enum insn_code icode, enum mips_fp_condition cond,
10537 rtx target, tree exp)
10539 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10543 if (target == 0 || GET_MODE (target) != SImode)
10544 target = gen_reg_rtx (SImode);
10546 /* Prepare the operands to the comparison. */
10547 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10548 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
10549 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
10551 switch (insn_data[icode].n_operands)
10554 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10558 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10559 ops[3], ops[4], GEN_INT (cond)));
10563 gcc_unreachable ();
10566 /* If the comparison sets more than one register, we define the result
10567 to be 0 if all registers are false and -1 if all registers are true.
10568 The value of the complete result is indeterminate otherwise. */
10569 switch (builtin_type)
10571 case MIPS_BUILTIN_CMP_ALL:
10572 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10573 return mips_builtin_branch_and_move (condition, target,
10574 const0_rtx, const1_rtx);
10576 case MIPS_BUILTIN_CMP_UPPER:
10577 case MIPS_BUILTIN_CMP_LOWER:
10578 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10579 condition = gen_single_cc (cmp_result, offset);
10580 return mips_builtin_branch_and_move (condition, target,
10581 const1_rtx, const0_rtx);
10584 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10585 return mips_builtin_branch_and_move (condition, target,
10586 const1_rtx, const0_rtx);
10590 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10591 suggests a good place to put the boolean result. */
10594 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10596 rtx condition, cmp_result;
10599 if (target == 0 || GET_MODE (target) != SImode)
10600 target = gen_reg_rtx (SImode);
10602 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10604 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10609 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10610 return mips_builtin_branch_and_move (condition, target,
10611 const1_rtx, const0_rtx);
10614 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10615 Expand the call and return an rtx for its return value.
10616 TARGET, if nonnull, suggests a good place to put this value. */
10619 mips_expand_builtin_1 (const struct builtin_description *bdesc,
10620 tree exp, rtx target)
10622 switch (bdesc->builtin_type)
10624 case MIPS_BUILTIN_DIRECT:
10625 return mips_expand_builtin_direct (bdesc->icode, target, exp, true);
10627 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10628 return mips_expand_builtin_direct (bdesc->icode, target, exp, false);
10630 case MIPS_BUILTIN_MOVT:
10631 case MIPS_BUILTIN_MOVF:
10632 return mips_expand_builtin_movtf (bdesc->builtin_type, bdesc->icode,
10633 bdesc->cond, target, exp);
10635 case MIPS_BUILTIN_CMP_ANY:
10636 case MIPS_BUILTIN_CMP_ALL:
10637 case MIPS_BUILTIN_CMP_UPPER:
10638 case MIPS_BUILTIN_CMP_LOWER:
10639 case MIPS_BUILTIN_CMP_SINGLE:
10640 return mips_expand_builtin_compare (bdesc->builtin_type, bdesc->icode,
10641 bdesc->cond, target, exp);
10643 case MIPS_BUILTIN_BPOSGE32:
10644 return mips_expand_builtin_bposge (bdesc->builtin_type, target);
10646 gcc_unreachable ();
10649 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10652 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10653 enum machine_mode mode ATTRIBUTE_UNUSED,
10654 int ignore ATTRIBUTE_UNUSED)
10657 unsigned int fcode;
10658 const struct bdesc_map *m;
10660 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10661 fcode = DECL_FUNCTION_CODE (fndecl);
10665 error ("built-in function %qs not supported for MIPS16",
10666 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
10670 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10672 if (fcode < m->size)
10673 return mips_expand_builtin_1 (m->bdesc + fcode, exp, target);
10676 gcc_unreachable ();
10679 /* An entry in the mips16 constant pool. VALUE is the pool constant,
10680 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10682 struct mips16_constant {
10683 struct mips16_constant *next;
10686 enum machine_mode mode;
10689 /* Information about an incomplete mips16 constant pool. FIRST is the
10690 first constant, HIGHEST_ADDRESS is the highest address that the first
10691 byte of the pool can have, and INSN_ADDRESS is the current instruction
10694 struct mips16_constant_pool {
10695 struct mips16_constant *first;
10696 int highest_address;
10700 /* Add constant VALUE to POOL and return its label. MODE is the
10701 value's mode (used for CONST_INTs, etc.). */
10704 add_constant (struct mips16_constant_pool *pool,
10705 rtx value, enum machine_mode mode)
10707 struct mips16_constant **p, *c;
10708 bool first_of_size_p;
10710 /* See whether the constant is already in the pool. If so, return the
10711 existing label, otherwise leave P pointing to the place where the
10712 constant should be added.
10714 Keep the pool sorted in increasing order of mode size so that we can
10715 reduce the number of alignments needed. */
10716 first_of_size_p = true;
10717 for (p = &pool->first; *p != 0; p = &(*p)->next)
10719 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
10720 return (*p)->label;
10721 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
10723 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
10724 first_of_size_p = false;
10727 /* In the worst case, the constant needed by the earliest instruction
10728 will end up at the end of the pool. The entire pool must then be
10729 accessible from that instruction.
10731 When adding the first constant, set the pool's highest address to
10732 the address of the first out-of-range byte. Adjust this address
10733 downwards each time a new constant is added. */
10734 if (pool->first == 0)
10735 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
10736 is the address of the instruction with the lowest two bits clear.
10737 The base PC value for ld has the lowest three bits clear. Assume
10738 the worst case here. */
10739 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
10740 pool->highest_address -= GET_MODE_SIZE (mode);
10741 if (first_of_size_p)
10742 /* Take into account the worst possible padding due to alignment. */
10743 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
10745 /* Create a new entry. */
10746 c = (struct mips16_constant *) xmalloc (sizeof *c);
10749 c->label = gen_label_rtx ();
10756 /* Output constant VALUE after instruction INSN and return the last
10757 instruction emitted. MODE is the mode of the constant. */
10760 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
10762 if (SCALAR_INT_MODE_P (mode)
10763 || ALL_SCALAR_FRACT_MODE_P (mode)
10764 || ALL_SCALAR_ACCUM_MODE_P (mode))
10766 rtx size = GEN_INT (GET_MODE_SIZE (mode));
10767 return emit_insn_after (gen_consttable_int (value, size), insn);
10770 if (SCALAR_FLOAT_MODE_P (mode))
10771 return emit_insn_after (gen_consttable_float (value), insn);
10773 if (VECTOR_MODE_P (mode))
10777 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
10778 insn = dump_constants_1 (GET_MODE_INNER (mode),
10779 CONST_VECTOR_ELT (value, i), insn);
10783 gcc_unreachable ();
10787 /* Dump out the constants in CONSTANTS after INSN. */
10790 dump_constants (struct mips16_constant *constants, rtx insn)
10792 struct mips16_constant *c, *next;
10796 for (c = constants; c != NULL; c = next)
10798 /* If necessary, increase the alignment of PC. */
10799 if (align < GET_MODE_SIZE (c->mode))
10801 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
10802 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
10804 align = GET_MODE_SIZE (c->mode);
10806 insn = emit_label_after (c->label, insn);
10807 insn = dump_constants_1 (c->mode, c->value, insn);
10813 emit_barrier_after (insn);
10816 /* Return the length of instruction INSN. */
10819 mips16_insn_length (rtx insn)
10823 rtx body = PATTERN (insn);
10824 if (GET_CODE (body) == ADDR_VEC)
10825 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
10826 if (GET_CODE (body) == ADDR_DIFF_VEC)
10827 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
10829 return get_attr_length (insn);
10832 /* If *X is a symbolic constant that refers to the constant pool, add
10833 the constant to POOL and rewrite *X to use the constant's label. */
10836 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
10838 rtx base, offset, label;
10840 split_const (*x, &base, &offset);
10841 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
10843 label = add_constant (pool, get_pool_constant (base),
10844 get_pool_mode (base));
10845 base = gen_rtx_LABEL_REF (Pmode, label);
10846 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
10850 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10851 INSN is the instruction we're rewriting and POOL points to the current
10853 struct mips16_rewrite_pool_refs_info {
10855 struct mips16_constant_pool *pool;
10858 /* Rewrite *X so that constant pool references refer to the constant's
10859 label instead. DATA points to a mips16_rewrite_pool_refs_info
10863 mips16_rewrite_pool_refs (rtx *x, void *data)
10865 struct mips16_rewrite_pool_refs_info *info = data;
10867 if (force_to_mem_operand (*x, Pmode))
10869 rtx mem = force_const_mem (GET_MODE (*x), *x);
10870 validate_change (info->insn, x, mem, false);
10875 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
10879 if (TARGET_MIPS16_TEXT_LOADS)
10880 mips16_rewrite_pool_constant (info->pool, x);
10882 return GET_CODE (*x) == CONST ? -1 : 0;
10885 /* Build MIPS16 constant pools. */
10888 mips16_lay_out_constants (void)
10890 struct mips16_constant_pool pool;
10891 struct mips16_rewrite_pool_refs_info info;
10894 if (!TARGET_MIPS16_PCREL_LOADS)
10898 memset (&pool, 0, sizeof (pool));
10899 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10901 /* Rewrite constant pool references in INSN. */
10906 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
10909 pool.insn_address += mips16_insn_length (insn);
10911 if (pool.first != NULL)
10913 /* If there are no natural barriers between the first user of
10914 the pool and the highest acceptable address, we'll need to
10915 create a new instruction to jump around the constant pool.
10916 In the worst case, this instruction will be 4 bytes long.
10918 If it's too late to do this transformation after INSN,
10919 do it immediately before INSN. */
10920 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
10924 label = gen_label_rtx ();
10926 jump = emit_jump_insn_before (gen_jump (label), insn);
10927 JUMP_LABEL (jump) = label;
10928 LABEL_NUSES (label) = 1;
10929 barrier = emit_barrier_after (jump);
10931 emit_label_after (label, barrier);
10932 pool.insn_address += 4;
10935 /* See whether the constant pool is now out of range of the first
10936 user. If so, output the constants after the previous barrier.
10937 Note that any instructions between BARRIER and INSN (inclusive)
10938 will use negative offsets to refer to the pool. */
10939 if (pool.insn_address > pool.highest_address)
10941 dump_constants (pool.first, barrier);
10945 else if (BARRIER_P (insn))
10949 dump_constants (pool.first, get_last_insn ());
10952 /* A temporary variable used by for_each_rtx callbacks, etc. */
10953 static rtx mips_sim_insn;
10955 /* A structure representing the state of the processor pipeline.
10956 Used by the mips_sim_* family of functions. */
10958 /* The maximum number of instructions that can be issued in a cycle.
10959 (Caches mips_issue_rate.) */
10960 unsigned int issue_rate;
10962 /* The current simulation time. */
10965 /* How many more instructions can be issued in the current cycle. */
10966 unsigned int insns_left;
10968 /* LAST_SET[X].INSN is the last instruction to set register X.
10969 LAST_SET[X].TIME is the time at which that instruction was issued.
10970 INSN is null if no instruction has yet set register X. */
10974 } last_set[FIRST_PSEUDO_REGISTER];
10976 /* The pipeline's current DFA state. */
10980 /* Reset STATE to the initial simulation state. */
10983 mips_sim_reset (struct mips_sim *state)
10986 state->insns_left = state->issue_rate;
10987 memset (&state->last_set, 0, sizeof (state->last_set));
10988 state_reset (state->dfa_state);
10991 /* Initialize STATE before its first use. DFA_STATE points to an
10992 allocated but uninitialized DFA state. */
10995 mips_sim_init (struct mips_sim *state, state_t dfa_state)
10997 state->issue_rate = mips_issue_rate ();
10998 state->dfa_state = dfa_state;
10999 mips_sim_reset (state);
11002 /* Advance STATE by one clock cycle. */
11005 mips_sim_next_cycle (struct mips_sim *state)
11008 state->insns_left = state->issue_rate;
11009 state_transition (state->dfa_state, 0);
11012 /* Advance simulation state STATE until instruction INSN can read
11016 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
11020 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
11021 if (state->last_set[REGNO (reg) + i].insn != 0)
11025 t = state->last_set[REGNO (reg) + i].time;
11026 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
11027 while (state->time < t)
11028 mips_sim_next_cycle (state);
11032 /* A for_each_rtx callback. If *X is a register, advance simulation state
11033 DATA until mips_sim_insn can read the register's value. */
11036 mips_sim_wait_regs_2 (rtx *x, void *data)
11039 mips_sim_wait_reg (data, mips_sim_insn, *x);
11043 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11046 mips_sim_wait_regs_1 (rtx *x, void *data)
11048 for_each_rtx (x, mips_sim_wait_regs_2, data);
11051 /* Advance simulation state STATE until all of INSN's register
11052 dependencies are satisfied. */
11055 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
11057 mips_sim_insn = insn;
11058 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
11061 /* Advance simulation state STATE until the units required by
11062 instruction INSN are available. */
11065 mips_sim_wait_units (struct mips_sim *state, rtx insn)
11069 tmp_state = alloca (state_size ());
11070 while (state->insns_left == 0
11071 || (memcpy (tmp_state, state->dfa_state, state_size ()),
11072 state_transition (tmp_state, insn) >= 0))
11073 mips_sim_next_cycle (state);
11076 /* Advance simulation state STATE until INSN is ready to issue. */
11079 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
11081 mips_sim_wait_regs (state, insn);
11082 mips_sim_wait_units (state, insn);
11085 /* mips_sim_insn has just set X. Update the LAST_SET array
11086 in simulation state DATA. */
11089 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
11091 struct mips_sim *state;
11096 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
11098 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
11099 state->last_set[REGNO (x) + i].time = state->time;
11103 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11104 can issue immediately (i.e., that mips_sim_wait_insn has already
11108 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
11110 state_transition (state->dfa_state, insn);
11111 state->insns_left--;
11113 mips_sim_insn = insn;
11114 note_stores (PATTERN (insn), mips_sim_record_set, state);
11117 /* Simulate issuing a NOP in state STATE. */
11120 mips_sim_issue_nop (struct mips_sim *state)
11122 if (state->insns_left == 0)
11123 mips_sim_next_cycle (state);
11124 state->insns_left--;
11127 /* Update simulation state STATE so that it's ready to accept the instruction
11128 after INSN. INSN should be part of the main rtl chain, not a member of a
11132 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
11134 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11136 mips_sim_issue_nop (state);
11138 switch (GET_CODE (SEQ_BEGIN (insn)))
11142 /* We can't predict the processor state after a call or label. */
11143 mips_sim_reset (state);
11147 /* The delay slots of branch likely instructions are only executed
11148 when the branch is taken. Therefore, if the caller has simulated
11149 the delay slot instruction, STATE does not really reflect the state
11150 of the pipeline for the instruction after the delay slot. Also,
11151 branch likely instructions tend to incur a penalty when not taken,
11152 so there will probably be an extra delay between the branch and
11153 the instruction after the delay slot. */
11154 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
11155 mips_sim_reset (state);
11163 /* The VR4130 pipeline issues aligned pairs of instructions together,
11164 but it stalls the second instruction if it depends on the first.
11165 In order to cut down the amount of logic required, this dependence
11166 check is not based on a full instruction decode. Instead, any non-SPECIAL
11167 instruction is assumed to modify the register specified by bits 20-16
11168 (which is usually the "rt" field).
11170 In beq, beql, bne and bnel instructions, the rt field is actually an
11171 input, so we can end up with a false dependence between the branch
11172 and its delay slot. If this situation occurs in instruction INSN,
11173 try to avoid it by swapping rs and rt. */
11176 vr4130_avoid_branch_rt_conflict (rtx insn)
11180 first = SEQ_BEGIN (insn);
11181 second = SEQ_END (insn);
11183 && NONJUMP_INSN_P (second)
11184 && GET_CODE (PATTERN (first)) == SET
11185 && GET_CODE (SET_DEST (PATTERN (first))) == PC
11186 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
11188 /* Check for the right kind of condition. */
11189 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
11190 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
11191 && REG_P (XEXP (cond, 0))
11192 && REG_P (XEXP (cond, 1))
11193 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
11194 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
11196 /* SECOND mentions the rt register but not the rs register. */
11197 rtx tmp = XEXP (cond, 0);
11198 XEXP (cond, 0) = XEXP (cond, 1);
11199 XEXP (cond, 1) = tmp;
11204 /* Implement -mvr4130-align. Go through each basic block and simulate the
11205 processor pipeline. If we find that a pair of instructions could execute
11206 in parallel, and the first of those instruction is not 8-byte aligned,
11207 insert a nop to make it aligned. */
11210 vr4130_align_insns (void)
11212 struct mips_sim state;
11213 rtx insn, subinsn, last, last2, next;
11218 /* LAST is the last instruction before INSN to have a nonzero length.
11219 LAST2 is the last such instruction before LAST. */
11223 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11226 mips_sim_init (&state, alloca (state_size ()));
11227 for (insn = get_insns (); insn != 0; insn = next)
11229 unsigned int length;
11231 next = NEXT_INSN (insn);
11233 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11234 This isn't really related to the alignment pass, but we do it on
11235 the fly to avoid a separate instruction walk. */
11236 vr4130_avoid_branch_rt_conflict (insn);
11238 if (USEFUL_INSN_P (insn))
11239 FOR_EACH_SUBINSN (subinsn, insn)
11241 mips_sim_wait_insn (&state, subinsn);
11243 /* If we want this instruction to issue in parallel with the
11244 previous one, make sure that the previous instruction is
11245 aligned. There are several reasons why this isn't worthwhile
11246 when the second instruction is a call:
11248 - Calls are less likely to be performance critical,
11249 - There's a good chance that the delay slot can execute
11250 in parallel with the call.
11251 - The return address would then be unaligned.
11253 In general, if we're going to insert a nop between instructions
11254 X and Y, it's better to insert it immediately after X. That
11255 way, if the nop makes Y aligned, it will also align any labels
11256 between X and Y. */
11257 if (state.insns_left != state.issue_rate
11258 && !CALL_P (subinsn))
11260 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
11262 /* SUBINSN is the first instruction in INSN and INSN is
11263 aligned. We want to align the previous instruction
11264 instead, so insert a nop between LAST2 and LAST.
11266 Note that LAST could be either a single instruction
11267 or a branch with a delay slot. In the latter case,
11268 LAST, like INSN, is already aligned, but the delay
11269 slot must have some extra delay that stops it from
11270 issuing at the same time as the branch. We therefore
11271 insert a nop before the branch in order to align its
11273 emit_insn_after (gen_nop (), last2);
11276 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
11278 /* SUBINSN is the delay slot of INSN, but INSN is
11279 currently unaligned. Insert a nop between
11280 LAST and INSN to align it. */
11281 emit_insn_after (gen_nop (), last);
11285 mips_sim_issue_insn (&state, subinsn);
11287 mips_sim_finish_insn (&state, insn);
11289 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11290 length = get_attr_length (insn);
11293 /* If the instruction is an asm statement or multi-instruction
11294 mips.md patern, the length is only an estimate. Insert an
11295 8 byte alignment after it so that the following instructions
11296 can be handled correctly. */
11297 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
11298 && (recog_memoized (insn) < 0 || length >= 8))
11300 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
11301 next = NEXT_INSN (next);
11302 mips_sim_next_cycle (&state);
11305 else if (length & 4)
11306 aligned_p = !aligned_p;
11311 /* See whether INSN is an aligned label. */
11312 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
11318 /* Subroutine of mips_reorg. If there is a hazard between INSN
11319 and a previous instruction, avoid it by inserting nops after
11322 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11323 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11324 before using the value of that register. *HILO_DELAY counts the
11325 number of instructions since the last hilo hazard (that is,
11326 the number of instructions since the last mflo or mfhi).
11328 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11329 for the next instruction.
11331 LO_REG is an rtx for the LO register, used in dependence checking. */
11334 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
11335 rtx *delayed_reg, rtx lo_reg)
11338 int nops, ninsns, hazard_set;
11340 if (!INSN_P (insn))
11343 pattern = PATTERN (insn);
11345 /* Do not put the whole function in .set noreorder if it contains
11346 an asm statement. We don't know whether there will be hazards
11347 between the asm statement and the gcc-generated code. */
11348 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
11349 cfun->machine->all_noreorder_p = false;
11351 /* Ignore zero-length instructions (barriers and the like). */
11352 ninsns = get_attr_length (insn) / 4;
11356 /* Work out how many nops are needed. Note that we only care about
11357 registers that are explicitly mentioned in the instruction's pattern.
11358 It doesn't matter that calls use the argument registers or that they
11359 clobber hi and lo. */
11360 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
11361 nops = 2 - *hilo_delay;
11362 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
11367 /* Insert the nops between this instruction and the previous one.
11368 Each new nop takes us further from the last hilo hazard. */
11369 *hilo_delay += nops;
11371 emit_insn_after (gen_hazard_nop (), after);
11373 /* Set up the state for the next instruction. */
11374 *hilo_delay += ninsns;
11376 if (INSN_CODE (insn) >= 0)
11377 switch (get_attr_hazard (insn))
11387 hazard_set = (int) get_attr_hazard_set (insn);
11388 if (hazard_set == 0)
11389 set = single_set (insn);
11392 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
11393 set = XVECEXP (PATTERN (insn), 0, hazard_set - 1);
11395 gcc_assert (set && GET_CODE (set) == SET);
11396 *delayed_reg = SET_DEST (set);
11402 /* Go through the instruction stream and insert nops where necessary.
11403 See if the whole function can then be put into .set noreorder &
11407 mips_avoid_hazards (void)
11409 rtx insn, last_insn, lo_reg, delayed_reg;
11412 /* Force all instructions to be split into their final form. */
11413 split_all_insns_noflow ();
11415 /* Recalculate instruction lengths without taking nops into account. */
11416 cfun->machine->ignore_hazard_length_p = true;
11417 shorten_branches (get_insns ());
11419 cfun->machine->all_noreorder_p = true;
11421 /* Profiled functions can't be all noreorder because the profiler
11422 support uses assembler macros. */
11423 if (current_function_profile)
11424 cfun->machine->all_noreorder_p = false;
11426 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11427 we rely on the assembler to work around some errata. */
11428 if (TARGET_FIX_VR4120)
11429 cfun->machine->all_noreorder_p = false;
11431 /* The same is true for -mfix-vr4130 if we might generate mflo or
11432 mfhi instructions. Note that we avoid using mflo and mfhi if
11433 the VR4130 macc and dmacc instructions are available instead;
11434 see the *mfhilo_{si,di}_macc patterns. */
11435 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
11436 cfun->machine->all_noreorder_p = false;
11441 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
11443 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11446 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11447 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
11448 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
11449 &hilo_delay, &delayed_reg, lo_reg);
11451 mips_avoid_hazard (last_insn, insn, &hilo_delay,
11452 &delayed_reg, lo_reg);
11459 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11464 mips16_lay_out_constants ();
11465 if (TARGET_EXPLICIT_RELOCS)
11467 if (mips_flag_delayed_branch)
11468 dbr_schedule (get_insns ());
11469 mips_avoid_hazards ();
11470 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
11471 vr4130_align_insns ();
11475 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11476 in order to avoid duplicating too much logic from elsewhere. */
11479 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11480 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11483 rtx this, temp1, temp2, insn, fnaddr;
11484 bool use_sibcall_p;
11486 /* Pretend to be a post-reload pass while generating rtl. */
11487 reload_completed = 1;
11489 /* Mark the end of the (empty) prologue. */
11490 emit_note (NOTE_INSN_PROLOGUE_END);
11492 /* Determine if we can use a sibcall to call FUNCTION directly. */
11493 fnaddr = XEXP (DECL_RTL (function), 0);
11494 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
11495 && const_call_insn_operand (fnaddr, Pmode));
11497 /* Determine if we need to load FNADDR from the GOT. */
11498 if (!use_sibcall_p)
11499 switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
11501 case SYMBOL_GOT_PAGE_OFST:
11502 case SYMBOL_GOT_DISP:
11503 /* Pick a global pointer. Use a call-clobbered register if
11504 TARGET_CALL_SAVED_GP. */
11505 cfun->machine->global_pointer =
11506 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
11507 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11509 /* Set up the global pointer for n32 or n64 abicalls. */
11510 mips_emit_loadgp ();
11517 /* We need two temporary registers in some cases. */
11518 temp1 = gen_rtx_REG (Pmode, 2);
11519 temp2 = gen_rtx_REG (Pmode, 3);
11521 /* Find out which register contains the "this" pointer. */
11522 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11523 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
11525 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
11527 /* Add DELTA to THIS. */
11530 rtx offset = GEN_INT (delta);
11531 if (!SMALL_OPERAND (delta))
11533 mips_emit_move (temp1, offset);
11536 emit_insn (gen_add3_insn (this, this, offset));
11539 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11540 if (vcall_offset != 0)
11544 /* Set TEMP1 to *THIS. */
11545 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
11547 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11548 addr = mips_add_offset (temp2, temp1, vcall_offset);
11550 /* Load the offset and add it to THIS. */
11551 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
11552 emit_insn (gen_add3_insn (this, this, temp1));
11555 /* Jump to the target function. Use a sibcall if direct jumps are
11556 allowed, otherwise load the address into a register first. */
11559 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
11560 SIBLING_CALL_P (insn) = 1;
11564 /* This is messy. gas treats "la $25,foo" as part of a call
11565 sequence and may allow a global "foo" to be lazily bound.
11566 The general move patterns therefore reject this combination.
11568 In this context, lazy binding would actually be OK
11569 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11570 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11571 We must therefore load the address via a temporary
11572 register if mips_dangerous_for_la25_p.
11574 If we jump to the temporary register rather than $25, the assembler
11575 can use the move insn to fill the jump's delay slot. */
11576 if (TARGET_USE_PIC_FN_ADDR_REG
11577 && !mips_dangerous_for_la25_p (fnaddr))
11578 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11579 mips_load_call_address (temp1, fnaddr, true);
11581 if (TARGET_USE_PIC_FN_ADDR_REG
11582 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
11583 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
11584 emit_jump_insn (gen_indirect_jump (temp1));
11587 /* Run just enough of rest_of_compilation. This sequence was
11588 "borrowed" from alpha.c. */
11589 insn = get_insns ();
11590 insn_locators_alloc ();
11591 split_all_insns_noflow ();
11592 mips16_lay_out_constants ();
11593 shorten_branches (insn);
11594 final_start_function (insn, file, 1);
11595 final (insn, file, 1);
11596 final_end_function ();
11598 /* Clean up the vars set above. Note that final_end_function resets
11599 the global pointer for us. */
11600 reload_completed = 0;
11603 static GTY(()) int was_mips16_p = -1;
11605 /* Set up the target-dependent global state so that it matches the
11606 current function's ISA mode. */
11609 mips_set_mips16_mode (int mips16_p)
11611 if (mips16_p == was_mips16_p)
11614 /* Restore base settings of various flags. */
11615 target_flags = mips_base_target_flags;
11616 flag_delayed_branch = mips_flag_delayed_branch;
11617 flag_schedule_insns = mips_base_schedule_insns;
11618 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
11619 flag_move_loop_invariants = mips_base_move_loop_invariants;
11620 align_loops = mips_base_align_loops;
11621 align_jumps = mips_base_align_jumps;
11622 align_functions = mips_base_align_functions;
11626 /* Select mips16 instruction set. */
11627 target_flags |= MASK_MIPS16;
11629 /* Don't run the scheduler before reload, since it tends to
11630 increase register pressure. */
11631 flag_schedule_insns = 0;
11633 /* Don't do hot/cold partitioning. The constant layout code expects
11634 the whole function to be in a single section. */
11635 flag_reorder_blocks_and_partition = 0;
11637 /* Don't move loop invariants, because it tends to increase
11638 register pressure. It also introduces an extra move in cases
11639 where the constant is the first operand in a two-operand binary
11640 instruction, or when it forms a register argument to a functon
11642 flag_move_loop_invariants = 0;
11644 /* Silently disable -mexplicit-relocs since it doesn't apply
11645 to mips16 code. Even so, it would overly pedantic to warn
11646 about "-mips16 -mexplicit-relocs", especially given that
11647 we use a %gprel() operator. */
11648 target_flags &= ~MASK_EXPLICIT_RELOCS;
11650 /* Experiments suggest we get the best overall results from using
11651 the range of an unextended lw or sw. Code that makes heavy use
11652 of byte or short accesses can do better with ranges of 0...31
11653 and 0...63 respectively, but most code is sensitive to the range
11654 of lw and sw instead. */
11655 targetm.min_anchor_offset = 0;
11656 targetm.max_anchor_offset = 127;
11658 if (flag_pic || TARGET_ABICALLS)
11659 sorry ("MIPS16 PIC");
11663 /* Reset to select base non-mips16 ISA. */
11664 target_flags &= ~MASK_MIPS16;
11666 /* When using explicit relocs, we call dbr_schedule from within
11668 if (TARGET_EXPLICIT_RELOCS)
11669 flag_delayed_branch = 0;
11671 /* Provide default values for align_* for 64-bit targets. */
11674 if (align_loops == 0)
11676 if (align_jumps == 0)
11678 if (align_functions == 0)
11679 align_functions = 8;
11682 targetm.min_anchor_offset = -32768;
11683 targetm.max_anchor_offset = 32767;
11686 /* (Re)initialize mips target internals for new ISA. */
11687 mips_init_split_addresses ();
11688 mips_init_relocs ();
11690 if (was_mips16_p >= 0)
11691 /* Reinitialize target-dependent state. */
11694 was_mips16_p = TARGET_MIPS16;
11697 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11698 function should use the MIPS16 ISA and switch modes accordingly. */
11701 mips_set_current_function (tree fndecl)
11703 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
11706 /* Allocate a chunk of memory for per-function machine-dependent data. */
11707 static struct machine_function *
11708 mips_init_machine_status (void)
11710 return ((struct machine_function *)
11711 ggc_alloc_cleared (sizeof (struct machine_function)));
11714 /* Return the processor associated with the given ISA level, or null
11715 if the ISA isn't valid. */
11717 static const struct mips_cpu_info *
11718 mips_cpu_info_from_isa (int isa)
11722 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11723 if (mips_cpu_info_table[i].isa == isa)
11724 return mips_cpu_info_table + i;
11729 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11730 with a final "000" replaced by "k". Ignore case.
11732 Note: this function is shared between GCC and GAS. */
11735 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
11737 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
11738 given++, canonical++;
11740 return ((*given == 0 && *canonical == 0)
11741 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
11745 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11746 CPU name. We've traditionally allowed a lot of variation here.
11748 Note: this function is shared between GCC and GAS. */
11751 mips_matching_cpu_name_p (const char *canonical, const char *given)
11753 /* First see if the name matches exactly, or with a final "000"
11754 turned into "k". */
11755 if (mips_strict_matching_cpu_name_p (canonical, given))
11758 /* If not, try comparing based on numerical designation alone.
11759 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11760 if (TOLOWER (*given) == 'r')
11762 if (!ISDIGIT (*given))
11765 /* Skip over some well-known prefixes in the canonical name,
11766 hoping to find a number there too. */
11767 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
11769 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
11771 else if (TOLOWER (canonical[0]) == 'r')
11774 return mips_strict_matching_cpu_name_p (canonical, given);
11778 /* Return the mips_cpu_info entry for the processor or ISA given
11779 by CPU_STRING. Return null if the string isn't recognized.
11781 A similar function exists in GAS. */
11783 static const struct mips_cpu_info *
11784 mips_parse_cpu (const char *cpu_string)
11789 /* In the past, we allowed upper-case CPU names, but it doesn't
11790 work well with the multilib machinery. */
11791 for (s = cpu_string; *s != 0; s++)
11794 warning (0, "the cpu name must be lower case");
11798 /* 'from-abi' selects the most compatible architecture for the given
11799 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
11800 EABIs, we have to decide whether we're using the 32-bit or 64-bit
11801 version. Look first at the -mgp options, if given, otherwise base
11802 the choice on MASK_64BIT in TARGET_DEFAULT. */
11803 if (strcasecmp (cpu_string, "from-abi") == 0)
11804 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
11805 : ABI_NEEDS_64BIT_REGS ? 3
11806 : (TARGET_64BIT ? 3 : 1));
11808 /* 'default' has traditionally been a no-op. Probably not very useful. */
11809 if (strcasecmp (cpu_string, "default") == 0)
11812 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11813 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
11814 return mips_cpu_info_table + i;
11820 /* Set up globals to generate code for the ISA or processor
11821 described by INFO. */
11824 mips_set_architecture (const struct mips_cpu_info *info)
11828 mips_arch_info = info;
11829 mips_arch = info->cpu;
11830 mips_isa = info->isa;
11835 /* Likewise for tuning. */
11838 mips_set_tune (const struct mips_cpu_info *info)
11842 mips_tune_info = info;
11843 mips_tune = info->cpu;
11847 /* Implement TARGET_HANDLE_OPTION. */
11850 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
11855 if (strcmp (arg, "32") == 0)
11857 else if (strcmp (arg, "o64") == 0)
11858 mips_abi = ABI_O64;
11859 else if (strcmp (arg, "n32") == 0)
11860 mips_abi = ABI_N32;
11861 else if (strcmp (arg, "64") == 0)
11863 else if (strcmp (arg, "eabi") == 0)
11864 mips_abi = ABI_EABI;
11871 return mips_parse_cpu (arg) != 0;
11874 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
11875 return mips_isa_info != 0;
11877 case OPT_mno_flush_func:
11878 mips_cache_flush_func = NULL;
11881 case OPT_mcode_readable_:
11882 if (strcmp (arg, "yes") == 0)
11883 mips_code_readable = CODE_READABLE_YES;
11884 else if (strcmp (arg, "pcrel") == 0)
11885 mips_code_readable = CODE_READABLE_PCREL;
11886 else if (strcmp (arg, "no") == 0)
11887 mips_code_readable = CODE_READABLE_NO;
11897 /* Set up the threshold for data to go into the small data area, instead
11898 of the normal data area, and detect any conflicts in the switches. */
11901 override_options (void)
11903 int i, start, regno;
11904 enum machine_mode mode;
11906 #ifdef SUBTARGET_OVERRIDE_OPTIONS
11907 SUBTARGET_OVERRIDE_OPTIONS;
11910 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
11912 /* The following code determines the architecture and register size.
11913 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
11914 The GAS and GCC code should be kept in sync as much as possible. */
11916 if (mips_arch_string != 0)
11917 mips_set_architecture (mips_parse_cpu (mips_arch_string));
11919 if (mips_isa_info != 0)
11921 if (mips_arch_info == 0)
11922 mips_set_architecture (mips_isa_info);
11923 else if (mips_arch_info->isa != mips_isa_info->isa)
11924 error ("-%s conflicts with the other architecture options, "
11925 "which specify a %s processor",
11926 mips_isa_info->name,
11927 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
11930 if (mips_arch_info == 0)
11932 #ifdef MIPS_CPU_STRING_DEFAULT
11933 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
11935 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
11939 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
11940 error ("-march=%s is not compatible with the selected ABI",
11941 mips_arch_info->name);
11943 /* Optimize for mips_arch, unless -mtune selects a different processor. */
11944 if (mips_tune_string != 0)
11945 mips_set_tune (mips_parse_cpu (mips_tune_string));
11947 if (mips_tune_info == 0)
11948 mips_set_tune (mips_arch_info);
11950 /* Set cost structure for the processor. */
11952 mips_cost = &mips_rtx_cost_optimize_size;
11954 mips_cost = &mips_rtx_cost_data[mips_tune];
11956 /* If the user hasn't specified a branch cost, use the processor's
11958 if (mips_branch_cost == 0)
11959 mips_branch_cost = mips_cost->branch_cost;
11961 if ((target_flags_explicit & MASK_64BIT) != 0)
11963 /* The user specified the size of the integer registers. Make sure
11964 it agrees with the ABI and ISA. */
11965 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
11966 error ("-mgp64 used with a 32-bit processor");
11967 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
11968 error ("-mgp32 used with a 64-bit ABI");
11969 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
11970 error ("-mgp64 used with a 32-bit ABI");
11974 /* Infer the integer register size from the ABI and processor.
11975 Restrict ourselves to 32-bit registers if that's all the
11976 processor has, or if the ABI cannot handle 64-bit registers. */
11977 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
11978 target_flags &= ~MASK_64BIT;
11980 target_flags |= MASK_64BIT;
11983 if ((target_flags_explicit & MASK_FLOAT64) != 0)
11985 /* Really, -mfp32 and -mfp64 are ornamental options. There's
11986 only one right answer here. */
11987 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
11988 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
11989 else if (!TARGET_64BIT && TARGET_FLOAT64
11990 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
11991 error ("-mgp32 and -mfp64 can only be combined if the target"
11992 " supports the mfhc1 and mthc1 instructions");
11993 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
11994 error ("unsupported combination: %s", "-mfp64 -msingle-float");
11998 /* -msingle-float selects 32-bit float registers. Otherwise the
11999 float registers should be the same size as the integer ones. */
12000 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
12001 target_flags |= MASK_FLOAT64;
12003 target_flags &= ~MASK_FLOAT64;
12006 /* End of code shared with GAS. */
12008 if ((target_flags_explicit & MASK_LONG64) == 0)
12010 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
12011 target_flags |= MASK_LONG64;
12013 target_flags &= ~MASK_LONG64;
12016 if (!TARGET_OLDABI)
12017 flag_pcc_struct_return = 0;
12019 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
12021 /* If neither -mbranch-likely nor -mno-branch-likely was given
12022 on the command line, set MASK_BRANCHLIKELY based on the target
12023 architecture and tuning flags. Annulled delay slots are a
12024 size win, so we only consider the processor-specific tuning
12025 for !optimize_size. */
12026 if (ISA_HAS_BRANCHLIKELY
12028 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
12029 target_flags |= MASK_BRANCHLIKELY;
12031 target_flags &= ~MASK_BRANCHLIKELY;
12033 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
12034 warning (0, "the %qs architecture does not support branch-likely"
12035 " instructions", mips_arch_info->name);
12037 /* The effect of -mabicalls isn't defined for the EABI. */
12038 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
12040 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12041 target_flags &= ~MASK_ABICALLS;
12044 /* MIPS16 cannot generate PIC yet. */
12045 if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
12047 sorry ("MIPS16 PIC");
12048 target_flags &= ~MASK_ABICALLS;
12049 flag_pic = flag_pie = flag_shlib = 0;
12052 if (TARGET_ABICALLS)
12053 /* We need to set flag_pic for executables as well as DSOs
12054 because we may reference symbols that are not defined in
12055 the final executable. (MIPS does not use things like
12056 copy relocs, for example.)
12058 Also, there is a body of code that uses __PIC__ to distinguish
12059 between -mabicalls and -mno-abicalls code. */
12062 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12063 faster code, but at the expense of more nops. Enable it at -O3 and
12065 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
12066 target_flags |= MASK_VR4130_ALIGN;
12068 /* Prefer a call to memcpy over inline code when optimizing for size,
12069 though see MOVE_RATIO in mips.h. */
12070 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
12071 target_flags |= MASK_MEMCPY;
12073 /* If we have a nonzero small-data limit, check that the -mgpopt
12074 setting is consistent with the other target flags. */
12075 if (mips_section_threshold > 0)
12079 if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
12080 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12082 TARGET_LOCAL_SDATA = false;
12083 TARGET_EXTERN_SDATA = false;
12087 if (TARGET_VXWORKS_RTP)
12088 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12090 if (TARGET_ABICALLS)
12091 warning (0, "cannot use small-data accesses for %qs",
12096 #ifdef MIPS_TFMODE_FORMAT
12097 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
12100 /* Make sure that the user didn't turn off paired single support when
12101 MIPS-3D support is requested. */
12102 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
12103 && !TARGET_PAIRED_SINGLE_FLOAT)
12104 error ("-mips3d requires -mpaired-single");
12106 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12108 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
12110 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12111 and TARGET_HARD_FLOAT_ABI are both true. */
12112 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
12113 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
12115 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12117 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
12118 error ("-mips3d/-mpaired-single must be used with -mips64");
12120 /* If TARGET_DSPR2, enable MASK_DSP. */
12122 target_flags |= MASK_DSP;
12124 mips_init_print_operand_punct ();
12126 /* Set up array to map GCC register number to debug register number.
12127 Ignore the special purpose register numbers. */
12129 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12131 mips_dbx_regno[i] = INVALID_REGNUM;
12132 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
12133 mips_dwarf_regno[i] = i;
12135 mips_dwarf_regno[i] = INVALID_REGNUM;
12138 start = GP_DBX_FIRST - GP_REG_FIRST;
12139 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
12140 mips_dbx_regno[i] = i + start;
12142 start = FP_DBX_FIRST - FP_REG_FIRST;
12143 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
12144 mips_dbx_regno[i] = i + start;
12146 /* HI and LO debug registers use big-endian ordering. */
12147 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
12148 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
12149 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
12150 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
12151 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
12153 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
12154 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
12157 /* Set up mips_hard_regno_mode_ok. */
12158 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
12159 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12160 mips_hard_regno_mode_ok[(int)mode][regno]
12161 = mips_hard_regno_mode_ok_p (regno, mode);
12163 /* Function to allocate machine-dependent function status. */
12164 init_machine_status = &mips_init_machine_status;
12166 /* Default to working around R4000 errata only if the processor
12167 was selected explicitly. */
12168 if ((target_flags_explicit & MASK_FIX_R4000) == 0
12169 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
12170 target_flags |= MASK_FIX_R4000;
12172 /* Default to working around R4400 errata only if the processor
12173 was selected explicitly. */
12174 if ((target_flags_explicit & MASK_FIX_R4400) == 0
12175 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
12176 target_flags |= MASK_FIX_R4400;
12178 /* Save base state of options. */
12179 mips_base_mips16 = TARGET_MIPS16;
12180 mips_base_target_flags = target_flags;
12181 mips_flag_delayed_branch = flag_delayed_branch;
12182 mips_base_schedule_insns = flag_schedule_insns;
12183 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
12184 mips_base_move_loop_invariants = flag_move_loop_invariants;
12185 mips_base_align_loops = align_loops;
12186 mips_base_align_jumps = align_jumps;
12187 mips_base_align_functions = align_functions;
12189 /* Now select the mips16 or 32-bit instruction set, as requested. */
12190 mips_set_mips16_mode (mips_base_mips16);
12193 /* Swap the register information for registers I and I + 1, which
12194 currently have the wrong endianness. Note that the registers'
12195 fixedness and call-clobberedness might have been set on the
12199 mips_swap_registers (unsigned int i)
12204 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12205 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12207 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
12208 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
12209 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
12210 SWAP_STRING (reg_names[i], reg_names[i + 1]);
12216 /* Implement CONDITIONAL_REGISTER_USAGE. */
12219 mips_conditional_register_usage (void)
12225 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
12226 fixed_regs[regno] = call_used_regs[regno] = 1;
12228 if (!TARGET_HARD_FLOAT)
12232 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
12233 fixed_regs[regno] = call_used_regs[regno] = 1;
12234 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12235 fixed_regs[regno] = call_used_regs[regno] = 1;
12237 else if (! ISA_HAS_8CC)
12241 /* We only have a single condition code register. We
12242 implement this by hiding all the condition code registers,
12243 and generating RTL that refers directly to ST_REG_FIRST. */
12244 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12245 fixed_regs[regno] = call_used_regs[regno] = 1;
12247 /* In mips16 mode, we permit the $t temporary registers to be used
12248 for reload. We prohibit the unused $s registers, since they
12249 are caller saved, and saving them via a mips16 register would
12250 probably waste more time than just reloading the value. */
12253 fixed_regs[18] = call_used_regs[18] = 1;
12254 fixed_regs[19] = call_used_regs[19] = 1;
12255 fixed_regs[20] = call_used_regs[20] = 1;
12256 fixed_regs[21] = call_used_regs[21] = 1;
12257 fixed_regs[22] = call_used_regs[22] = 1;
12258 fixed_regs[23] = call_used_regs[23] = 1;
12259 fixed_regs[26] = call_used_regs[26] = 1;
12260 fixed_regs[27] = call_used_regs[27] = 1;
12261 fixed_regs[30] = call_used_regs[30] = 1;
12263 /* fp20-23 are now caller saved. */
12264 if (mips_abi == ABI_64)
12267 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
12268 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12270 /* Odd registers from fp21 to fp31 are now caller saved. */
12271 if (mips_abi == ABI_N32)
12274 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
12275 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12277 /* Make sure that double-register accumulator values are correctly
12278 ordered for the current endianness. */
12279 if (TARGET_LITTLE_ENDIAN)
12282 mips_swap_registers (MD_REG_FIRST);
12283 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
12284 mips_swap_registers (regno);
12288 /* On the mips16, we want to allocate $24 (T_REG) before other
12289 registers for instructions for which it is possible. This helps
12290 avoid shuffling registers around in order to set up for an xor,
12291 encouraging the compiler to use a cmp instead. */
12294 mips_order_regs_for_local_alloc (void)
12298 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12299 reg_alloc_order[i] = i;
12303 /* It really doesn't matter where we put register 0, since it is
12304 a fixed register anyhow. */
12305 reg_alloc_order[0] = 24;
12306 reg_alloc_order[24] = 0;
12310 /* Initialize the GCC target structure. */
12311 #undef TARGET_ASM_ALIGNED_HI_OP
12312 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12313 #undef TARGET_ASM_ALIGNED_SI_OP
12314 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12315 #undef TARGET_ASM_ALIGNED_DI_OP
12316 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12318 #undef TARGET_ASM_FUNCTION_PROLOGUE
12319 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12320 #undef TARGET_ASM_FUNCTION_EPILOGUE
12321 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12322 #undef TARGET_ASM_SELECT_RTX_SECTION
12323 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12324 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12325 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12327 #undef TARGET_SCHED_INIT
12328 #define TARGET_SCHED_INIT mips_sched_init
12329 #undef TARGET_SCHED_REORDER
12330 #define TARGET_SCHED_REORDER mips_sched_reorder
12331 #undef TARGET_SCHED_REORDER2
12332 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12333 #undef TARGET_SCHED_VARIABLE_ISSUE
12334 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12335 #undef TARGET_SCHED_ADJUST_COST
12336 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12337 #undef TARGET_SCHED_ISSUE_RATE
12338 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12339 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12340 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12341 mips_multipass_dfa_lookahead
12343 #undef TARGET_DEFAULT_TARGET_FLAGS
12344 #define TARGET_DEFAULT_TARGET_FLAGS \
12346 | TARGET_CPU_DEFAULT \
12347 | TARGET_ENDIAN_DEFAULT \
12348 | TARGET_FP_EXCEPTIONS_DEFAULT \
12349 | MASK_CHECK_ZERO_DIV \
12351 #undef TARGET_HANDLE_OPTION
12352 #define TARGET_HANDLE_OPTION mips_handle_option
12354 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12355 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12357 #undef TARGET_INSERT_ATTRIBUTES
12358 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12359 #undef TARGET_MERGE_DECL_ATTRIBUTES
12360 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12361 #undef TARGET_SET_CURRENT_FUNCTION
12362 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12364 #undef TARGET_VALID_POINTER_MODE
12365 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12366 #undef TARGET_RTX_COSTS
12367 #define TARGET_RTX_COSTS mips_rtx_costs
12368 #undef TARGET_ADDRESS_COST
12369 #define TARGET_ADDRESS_COST mips_address_cost
12371 #undef TARGET_IN_SMALL_DATA_P
12372 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12374 #undef TARGET_MACHINE_DEPENDENT_REORG
12375 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12377 #undef TARGET_ASM_FILE_START
12378 #define TARGET_ASM_FILE_START mips_file_start
12379 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12380 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12382 #undef TARGET_INIT_LIBFUNCS
12383 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12385 #undef TARGET_BUILD_BUILTIN_VA_LIST
12386 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12387 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12388 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12390 #undef TARGET_PROMOTE_FUNCTION_ARGS
12391 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12392 #undef TARGET_PROMOTE_FUNCTION_RETURN
12393 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12394 #undef TARGET_PROMOTE_PROTOTYPES
12395 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12397 #undef TARGET_RETURN_IN_MEMORY
12398 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12399 #undef TARGET_RETURN_IN_MSB
12400 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12402 #undef TARGET_ASM_OUTPUT_MI_THUNK
12403 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12404 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12405 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12407 #undef TARGET_SETUP_INCOMING_VARARGS
12408 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12409 #undef TARGET_STRICT_ARGUMENT_NAMING
12410 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12411 #undef TARGET_MUST_PASS_IN_STACK
12412 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12413 #undef TARGET_PASS_BY_REFERENCE
12414 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12415 #undef TARGET_CALLEE_COPIES
12416 #define TARGET_CALLEE_COPIES mips_callee_copies
12417 #undef TARGET_ARG_PARTIAL_BYTES
12418 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12420 #undef TARGET_MODE_REP_EXTENDED
12421 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12423 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12424 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12426 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12427 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12429 #undef TARGET_INIT_BUILTINS
12430 #define TARGET_INIT_BUILTINS mips_init_builtins
12431 #undef TARGET_EXPAND_BUILTIN
12432 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12434 #undef TARGET_HAVE_TLS
12435 #define TARGET_HAVE_TLS HAVE_AS_TLS
12437 #undef TARGET_CANNOT_FORCE_CONST_MEM
12438 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12440 #undef TARGET_ENCODE_SECTION_INFO
12441 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12443 #undef TARGET_ATTRIBUTE_TABLE
12444 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12445 /* All our function attributes are related to how out-of-line copies should
12446 be compiled or called. They don't in themselves prevent inlining. */
12447 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12448 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12450 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12451 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12453 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12454 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12455 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12456 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12458 #undef TARGET_COMP_TYPE_ATTRIBUTES
12459 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12461 #ifdef HAVE_AS_DTPRELWORD
12462 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12463 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12465 #undef TARGET_DWARF_REGISTER_SPAN
12466 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12468 struct gcc_target targetm = TARGET_INITIALIZER;
12470 #include "gt-mips.h"