1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting {
153 R10K_CACHE_BARRIER_NONE,
154 R10K_CACHE_BARRIER_STORE,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type {
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type {
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY,
201 MIPS_BUILTIN_CMP_ALL,
202 MIPS_BUILTIN_CMP_UPPER,
203 MIPS_BUILTIN_CMP_LOWER,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition {
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY)
243 /* Information about a function's frame layout. */
244 struct GTY(()) mips_frame_info {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* Likewise doubleword accumulator X ($acX). */
265 unsigned int acc_mask;
267 /* The number of GPRs, FPRs, doubleword accumulators and COP0
271 unsigned int num_acc;
272 unsigned int num_cop0_regs;
274 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
275 save slots from the top of the frame, or zero if no such slots are
277 HOST_WIDE_INT gp_save_offset;
278 HOST_WIDE_INT fp_save_offset;
279 HOST_WIDE_INT acc_save_offset;
280 HOST_WIDE_INT cop0_save_offset;
282 /* Likewise, but giving offsets from the bottom of the frame. */
283 HOST_WIDE_INT gp_sp_offset;
284 HOST_WIDE_INT fp_sp_offset;
285 HOST_WIDE_INT acc_sp_offset;
286 HOST_WIDE_INT cop0_sp_offset;
288 /* The offset of arg_pointer_rtx from the bottom of the frame. */
289 HOST_WIDE_INT arg_pointer_offset;
291 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
292 HOST_WIDE_INT hard_frame_pointer_offset;
295 struct GTY(()) machine_function {
296 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
297 rtx mips16_gp_pseudo_rtx;
299 /* The number of extra stack bytes taken up by register varargs.
300 This area is allocated by the callee at the very top of the frame. */
303 /* The current frame information, calculated by mips_compute_frame_info. */
304 struct mips_frame_info frame;
306 /* The register to use as the function's global pointer, or INVALID_REGNUM
307 if the function doesn't need one. */
308 unsigned int global_pointer;
310 /* True if mips_adjust_insn_length should ignore an instruction's
312 bool ignore_hazard_length_p;
314 /* True if the whole function is suitable for .set noreorder and
316 bool all_noreorder_p;
318 /* True if the function is known to have an instruction that needs $gp. */
321 /* True if we have emitted an instruction to initialize
322 mips16_gp_pseudo_rtx. */
323 bool initialized_mips16_gp_pseudo_p;
325 /* True if this is an interrupt handler. */
326 bool interrupt_handler_p;
328 /* True if this is an interrupt handler that uses shadow registers. */
329 bool use_shadow_register_set_p;
331 /* True if this is an interrupt handler that should keep interrupts
333 bool keep_interrupts_masked_p;
335 /* True if this is an interrupt handler that should use DERET
337 bool use_debug_exception_return_p;
340 /* Information about a single argument. */
341 struct mips_arg_info {
342 /* True if the argument is passed in a floating-point register, or
343 would have been if we hadn't run out of registers. */
346 /* The number of words passed in registers, rounded up. */
347 unsigned int reg_words;
349 /* For EABI, the offset of the first register from GP_ARG_FIRST or
350 FP_ARG_FIRST. For other ABIs, the offset of the first register from
351 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
352 comment for details).
354 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
356 unsigned int reg_offset;
358 /* The number of words that must be passed on the stack, rounded up. */
359 unsigned int stack_words;
361 /* The offset from the start of the stack overflow area of the argument's
362 first stack word. Only meaningful when STACK_WORDS is nonzero. */
363 unsigned int stack_offset;
366 /* Information about an address described by mips_address_type.
372 REG is the base register and OFFSET is the constant offset.
375 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
376 is the type of symbol it references.
379 SYMBOL_TYPE is the type of symbol that the address references. */
380 struct mips_address_info {
381 enum mips_address_type type;
384 enum mips_symbol_type symbol_type;
387 /* One stage in a constant building sequence. These sequences have
391 A = A CODE[1] VALUE[1]
392 A = A CODE[2] VALUE[2]
395 where A is an accumulator, each CODE[i] is a binary rtl operation
396 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
397 struct mips_integer_op {
399 unsigned HOST_WIDE_INT value;
402 /* The largest number of operations needed to load an integer constant.
403 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
404 When the lowest bit is clear, we can try, but reject a sequence with
405 an extra SLL at the end. */
406 #define MIPS_MAX_INTEGER_OPS 7
408 /* Information about a MIPS16e SAVE or RESTORE instruction. */
409 struct mips16e_save_restore_info {
410 /* The number of argument registers saved by a SAVE instruction.
411 0 for RESTORE instructions. */
414 /* Bit X is set if the instruction saves or restores GPR X. */
417 /* The total number of bytes to allocate. */
421 /* Global variables for machine-dependent things. */
423 /* The -G setting, or the configuration's default small-data limit if
424 no -G option is given. */
425 static unsigned int mips_small_data_threshold;
427 /* The number of file directives written by mips_output_filename. */
428 int num_source_filenames;
430 /* The name that appeared in the last .file directive written by
431 mips_output_filename, or "" if mips_output_filename hasn't
432 written anything yet. */
433 const char *current_function_file = "";
435 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
438 /* Arrays that map GCC register numbers to debugger register numbers. */
439 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
440 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
442 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
443 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
444 struct mips_asm_switch mips_nomacro = { "macro", 0 };
445 struct mips_asm_switch mips_noat = { "at", 0 };
447 /* True if we're writing out a branch-likely instruction rather than a
449 static bool mips_branch_likely;
451 /* The current instruction-set architecture. */
452 enum processor_type mips_arch;
453 const struct mips_cpu_info *mips_arch_info;
455 /* The processor that we should tune the code for. */
456 enum processor_type mips_tune;
457 const struct mips_cpu_info *mips_tune_info;
459 /* The ISA level associated with mips_arch. */
462 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
463 static const struct mips_cpu_info *mips_isa_option_info;
465 /* Which ABI to use. */
466 int mips_abi = MIPS_ABI_DEFAULT;
468 /* Which cost information to use. */
469 const struct mips_rtx_cost_data *mips_cost;
471 /* The ambient target flags, excluding MASK_MIPS16. */
472 static int mips_base_target_flags;
474 /* True if MIPS16 is the default mode. */
475 bool mips_base_mips16;
477 /* The ambient values of other global variables. */
478 static int mips_base_schedule_insns; /* flag_schedule_insns */
479 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
480 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
481 static int mips_base_align_loops; /* align_loops */
482 static int mips_base_align_jumps; /* align_jumps */
483 static int mips_base_align_functions; /* align_functions */
485 /* The -mcode-readable setting. */
486 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
488 /* The -mr10k-cache-barrier setting. */
489 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
491 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
492 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
494 /* Index C is true if character C is a valid PRINT_OPERAND punctation
496 bool mips_print_operand_punct[256];
498 static GTY (()) int mips_output_filename_first_time = 1;
500 /* mips_split_p[X] is true if symbols of type X can be split by
501 mips_split_symbol. */
502 bool mips_split_p[NUM_SYMBOL_TYPES];
504 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
505 can be split by mips_split_symbol. */
506 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
508 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
509 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
510 if they are matched by a special .md file pattern. */
511 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
513 /* Likewise for HIGHs. */
514 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
516 /* Index R is the smallest register class that contains register R. */
517 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
518 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
519 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
520 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
521 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
522 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
523 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
524 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
525 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
526 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
527 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
528 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
529 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
530 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
531 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
532 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
533 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
534 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
535 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
536 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
537 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
538 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
539 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
540 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
541 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
542 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
543 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
544 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
545 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
546 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
547 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
548 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
549 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
550 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
551 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
552 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
553 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
554 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
555 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
556 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
557 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
558 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
559 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
560 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
561 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
562 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
563 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
564 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
567 /* The value of TARGET_ATTRIBUTE_TABLE. */
568 static const struct attribute_spec mips_attribute_table[] = {
569 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
570 { "long_call", 0, 0, false, true, true, NULL },
571 { "far", 0, 0, false, true, true, NULL },
572 { "near", 0, 0, false, true, true, NULL },
573 /* We would really like to treat "mips16" and "nomips16" as type
574 attributes, but GCC doesn't provide the hooks we need to support
575 the right conversion rules. As declaration attributes, they affect
576 code generation but don't carry other semantics. */
577 { "mips16", 0, 0, true, false, false, NULL },
578 { "nomips16", 0, 0, true, false, false, NULL },
579 /* Allow functions to be specified as interrupt handlers */
580 { "interrupt", 0, 0, false, true, true, NULL },
581 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
582 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
583 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
584 { NULL, 0, 0, false, false, false, NULL }
587 /* A table describing all the processors GCC knows about. Names are
588 matched in the order listed. The first mention of an ISA level is
589 taken as the canonical name for that ISA.
591 To ease comparison, please keep this table in the same order
592 as GAS's mips_cpu_info_table. Please also make sure that
593 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
594 options correctly. */
595 static const struct mips_cpu_info mips_cpu_info_table[] = {
596 /* Entries for generic ISAs. */
597 { "mips1", PROCESSOR_R3000, 1, 0 },
598 { "mips2", PROCESSOR_R6000, 2, 0 },
599 { "mips3", PROCESSOR_R4000, 3, 0 },
600 { "mips4", PROCESSOR_R8000, 4, 0 },
601 /* Prefer not to use branch-likely instructions for generic MIPS32rX
602 and MIPS64rX code. The instructions were officially deprecated
603 in revisions 2 and earlier, but revision 3 is likely to downgrade
604 that to a recommendation to avoid the instructions in code that
605 isn't tuned to a specific processor. */
606 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
607 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
608 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
609 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
610 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
612 /* MIPS I processors. */
613 { "r3000", PROCESSOR_R3000, 1, 0 },
614 { "r2000", PROCESSOR_R3000, 1, 0 },
615 { "r3900", PROCESSOR_R3900, 1, 0 },
617 /* MIPS II processors. */
618 { "r6000", PROCESSOR_R6000, 2, 0 },
620 /* MIPS III processors. */
621 { "r4000", PROCESSOR_R4000, 3, 0 },
622 { "vr4100", PROCESSOR_R4100, 3, 0 },
623 { "vr4111", PROCESSOR_R4111, 3, 0 },
624 { "vr4120", PROCESSOR_R4120, 3, 0 },
625 { "vr4130", PROCESSOR_R4130, 3, 0 },
626 { "vr4300", PROCESSOR_R4300, 3, 0 },
627 { "r4400", PROCESSOR_R4000, 3, 0 },
628 { "r4600", PROCESSOR_R4600, 3, 0 },
629 { "orion", PROCESSOR_R4600, 3, 0 },
630 { "r4650", PROCESSOR_R4650, 3, 0 },
631 /* ST Loongson 2E/2F processors. */
632 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
633 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
635 /* MIPS IV processors. */
636 { "r8000", PROCESSOR_R8000, 4, 0 },
637 { "r10000", PROCESSOR_R10000, 4, 0 },
638 { "r12000", PROCESSOR_R10000, 4, 0 },
639 { "r14000", PROCESSOR_R10000, 4, 0 },
640 { "r16000", PROCESSOR_R10000, 4, 0 },
641 { "vr5000", PROCESSOR_R5000, 4, 0 },
642 { "vr5400", PROCESSOR_R5400, 4, 0 },
643 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
644 { "rm7000", PROCESSOR_R7000, 4, 0 },
645 { "rm9000", PROCESSOR_R9000, 4, 0 },
647 /* MIPS32 processors. */
648 { "4kc", PROCESSOR_4KC, 32, 0 },
649 { "4km", PROCESSOR_4KC, 32, 0 },
650 { "4kp", PROCESSOR_4KP, 32, 0 },
651 { "4ksc", PROCESSOR_4KC, 32, 0 },
653 /* MIPS32 Release 2 processors. */
654 { "m4k", PROCESSOR_M4K, 33, 0 },
655 { "4kec", PROCESSOR_4KC, 33, 0 },
656 { "4kem", PROCESSOR_4KC, 33, 0 },
657 { "4kep", PROCESSOR_4KP, 33, 0 },
658 { "4ksd", PROCESSOR_4KC, 33, 0 },
660 { "24kc", PROCESSOR_24KC, 33, 0 },
661 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
662 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
663 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
664 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
665 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
667 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
668 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
669 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
670 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
671 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
672 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
674 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
675 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
676 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
677 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
678 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
679 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
681 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
682 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
683 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
684 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
685 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
686 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
687 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
689 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
690 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
691 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
692 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
694 /* MIPS64 processors. */
695 { "5kc", PROCESSOR_5KC, 64, 0 },
696 { "5kf", PROCESSOR_5KF, 64, 0 },
697 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
698 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
699 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
700 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
701 { "xlr", PROCESSOR_XLR, 64, 0 },
703 /* MIPS64 Release 2 processors. */
704 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
707 /* Default costs. If these are used for a processor we should look
708 up the actual costs. */
709 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
710 COSTS_N_INSNS (7), /* fp_mult_sf */ \
711 COSTS_N_INSNS (8), /* fp_mult_df */ \
712 COSTS_N_INSNS (23), /* fp_div_sf */ \
713 COSTS_N_INSNS (36), /* fp_div_df */ \
714 COSTS_N_INSNS (10), /* int_mult_si */ \
715 COSTS_N_INSNS (10), /* int_mult_di */ \
716 COSTS_N_INSNS (69), /* int_div_si */ \
717 COSTS_N_INSNS (69), /* int_div_di */ \
718 2, /* branch_cost */ \
719 4 /* memory_latency */
721 /* Floating-point costs for processors without an FPU. Just assume that
722 all floating-point libcalls are very expensive. */
723 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
724 COSTS_N_INSNS (256), /* fp_mult_sf */ \
725 COSTS_N_INSNS (256), /* fp_mult_df */ \
726 COSTS_N_INSNS (256), /* fp_div_sf */ \
727 COSTS_N_INSNS (256) /* fp_div_df */
729 /* Costs to use when optimizing for size. */
730 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
731 COSTS_N_INSNS (1), /* fp_add */
732 COSTS_N_INSNS (1), /* fp_mult_sf */
733 COSTS_N_INSNS (1), /* fp_mult_df */
734 COSTS_N_INSNS (1), /* fp_div_sf */
735 COSTS_N_INSNS (1), /* fp_div_df */
736 COSTS_N_INSNS (1), /* int_mult_si */
737 COSTS_N_INSNS (1), /* int_mult_di */
738 COSTS_N_INSNS (1), /* int_div_si */
739 COSTS_N_INSNS (1), /* int_div_di */
741 4 /* memory_latency */
744 /* Costs to use when optimizing for speed, indexed by processor. */
745 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
747 COSTS_N_INSNS (2), /* fp_add */
748 COSTS_N_INSNS (4), /* fp_mult_sf */
749 COSTS_N_INSNS (5), /* fp_mult_df */
750 COSTS_N_INSNS (12), /* fp_div_sf */
751 COSTS_N_INSNS (19), /* fp_div_df */
752 COSTS_N_INSNS (12), /* int_mult_si */
753 COSTS_N_INSNS (12), /* int_mult_di */
754 COSTS_N_INSNS (35), /* int_div_si */
755 COSTS_N_INSNS (35), /* int_div_di */
757 4 /* memory_latency */
761 COSTS_N_INSNS (6), /* int_mult_si */
762 COSTS_N_INSNS (6), /* int_mult_di */
763 COSTS_N_INSNS (36), /* int_div_si */
764 COSTS_N_INSNS (36), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (36), /* int_mult_si */
771 COSTS_N_INSNS (36), /* int_mult_di */
772 COSTS_N_INSNS (37), /* int_div_si */
773 COSTS_N_INSNS (37), /* int_div_di */
775 4 /* memory_latency */
779 COSTS_N_INSNS (4), /* int_mult_si */
780 COSTS_N_INSNS (11), /* int_mult_di */
781 COSTS_N_INSNS (36), /* int_div_si */
782 COSTS_N_INSNS (68), /* int_div_di */
784 4 /* memory_latency */
787 COSTS_N_INSNS (4), /* fp_add */
788 COSTS_N_INSNS (4), /* fp_mult_sf */
789 COSTS_N_INSNS (5), /* fp_mult_df */
790 COSTS_N_INSNS (17), /* fp_div_sf */
791 COSTS_N_INSNS (32), /* fp_div_df */
792 COSTS_N_INSNS (4), /* int_mult_si */
793 COSTS_N_INSNS (11), /* int_mult_di */
794 COSTS_N_INSNS (36), /* int_div_si */
795 COSTS_N_INSNS (68), /* int_div_di */
797 4 /* memory_latency */
800 COSTS_N_INSNS (4), /* fp_add */
801 COSTS_N_INSNS (4), /* fp_mult_sf */
802 COSTS_N_INSNS (5), /* fp_mult_df */
803 COSTS_N_INSNS (17), /* fp_div_sf */
804 COSTS_N_INSNS (32), /* fp_div_df */
805 COSTS_N_INSNS (4), /* int_mult_si */
806 COSTS_N_INSNS (7), /* int_mult_di */
807 COSTS_N_INSNS (42), /* int_div_si */
808 COSTS_N_INSNS (72), /* int_div_di */
810 4 /* memory_latency */
814 COSTS_N_INSNS (5), /* int_mult_si */
815 COSTS_N_INSNS (5), /* int_mult_di */
816 COSTS_N_INSNS (41), /* int_div_si */
817 COSTS_N_INSNS (41), /* int_div_di */
819 4 /* memory_latency */
822 COSTS_N_INSNS (8), /* fp_add */
823 COSTS_N_INSNS (8), /* fp_mult_sf */
824 COSTS_N_INSNS (10), /* fp_mult_df */
825 COSTS_N_INSNS (34), /* fp_div_sf */
826 COSTS_N_INSNS (64), /* fp_div_df */
827 COSTS_N_INSNS (5), /* int_mult_si */
828 COSTS_N_INSNS (5), /* int_mult_di */
829 COSTS_N_INSNS (41), /* int_div_si */
830 COSTS_N_INSNS (41), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (5), /* int_mult_si */
841 COSTS_N_INSNS (5), /* int_mult_di */
842 COSTS_N_INSNS (41), /* int_div_si */
843 COSTS_N_INSNS (41), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (5), /* int_mult_si */
850 COSTS_N_INSNS (5), /* int_mult_di */
851 COSTS_N_INSNS (41), /* int_div_si */
852 COSTS_N_INSNS (41), /* int_div_di */
854 4 /* memory_latency */
857 COSTS_N_INSNS (8), /* fp_add */
858 COSTS_N_INSNS (8), /* fp_mult_sf */
859 COSTS_N_INSNS (10), /* fp_mult_df */
860 COSTS_N_INSNS (34), /* fp_div_sf */
861 COSTS_N_INSNS (64), /* fp_div_df */
862 COSTS_N_INSNS (5), /* int_mult_si */
863 COSTS_N_INSNS (5), /* int_mult_di */
864 COSTS_N_INSNS (41), /* int_div_si */
865 COSTS_N_INSNS (41), /* int_div_di */
867 4 /* memory_latency */
870 COSTS_N_INSNS (4), /* fp_add */
871 COSTS_N_INSNS (4), /* fp_mult_sf */
872 COSTS_N_INSNS (5), /* fp_mult_df */
873 COSTS_N_INSNS (17), /* fp_div_sf */
874 COSTS_N_INSNS (32), /* fp_div_df */
875 COSTS_N_INSNS (5), /* int_mult_si */
876 COSTS_N_INSNS (5), /* int_mult_di */
877 COSTS_N_INSNS (41), /* int_div_si */
878 COSTS_N_INSNS (41), /* int_div_di */
880 4 /* memory_latency */
883 COSTS_N_INSNS (6), /* fp_add */
884 COSTS_N_INSNS (6), /* fp_mult_sf */
885 COSTS_N_INSNS (7), /* fp_mult_df */
886 COSTS_N_INSNS (25), /* fp_div_sf */
887 COSTS_N_INSNS (48), /* fp_div_df */
888 COSTS_N_INSNS (5), /* int_mult_si */
889 COSTS_N_INSNS (5), /* int_mult_di */
890 COSTS_N_INSNS (41), /* int_div_si */
891 COSTS_N_INSNS (41), /* int_div_di */
893 4 /* memory_latency */
907 COSTS_N_INSNS (5), /* int_mult_si */
908 COSTS_N_INSNS (5), /* int_mult_di */
909 COSTS_N_INSNS (72), /* int_div_si */
910 COSTS_N_INSNS (72), /* int_div_di */
912 4 /* memory_latency */
915 COSTS_N_INSNS (2), /* fp_add */
916 COSTS_N_INSNS (4), /* fp_mult_sf */
917 COSTS_N_INSNS (5), /* fp_mult_df */
918 COSTS_N_INSNS (12), /* fp_div_sf */
919 COSTS_N_INSNS (19), /* fp_div_df */
920 COSTS_N_INSNS (2), /* int_mult_si */
921 COSTS_N_INSNS (2), /* int_mult_di */
922 COSTS_N_INSNS (35), /* int_div_si */
923 COSTS_N_INSNS (35), /* int_div_di */
925 4 /* memory_latency */
928 COSTS_N_INSNS (3), /* fp_add */
929 COSTS_N_INSNS (5), /* fp_mult_sf */
930 COSTS_N_INSNS (6), /* fp_mult_df */
931 COSTS_N_INSNS (15), /* fp_div_sf */
932 COSTS_N_INSNS (16), /* fp_div_df */
933 COSTS_N_INSNS (17), /* int_mult_si */
934 COSTS_N_INSNS (17), /* int_mult_di */
935 COSTS_N_INSNS (38), /* int_div_si */
936 COSTS_N_INSNS (38), /* int_div_di */
938 6 /* memory_latency */
941 COSTS_N_INSNS (6), /* fp_add */
942 COSTS_N_INSNS (7), /* fp_mult_sf */
943 COSTS_N_INSNS (8), /* fp_mult_df */
944 COSTS_N_INSNS (23), /* fp_div_sf */
945 COSTS_N_INSNS (36), /* fp_div_df */
946 COSTS_N_INSNS (10), /* int_mult_si */
947 COSTS_N_INSNS (10), /* int_mult_di */
948 COSTS_N_INSNS (69), /* int_div_si */
949 COSTS_N_INSNS (69), /* int_div_di */
951 6 /* memory_latency */
963 /* The only costs that appear to be updated here are
964 integer multiplication. */
966 COSTS_N_INSNS (4), /* int_mult_si */
967 COSTS_N_INSNS (6), /* int_mult_di */
968 COSTS_N_INSNS (69), /* int_div_si */
969 COSTS_N_INSNS (69), /* int_div_di */
971 4 /* memory_latency */
983 COSTS_N_INSNS (6), /* fp_add */
984 COSTS_N_INSNS (4), /* fp_mult_sf */
985 COSTS_N_INSNS (5), /* fp_mult_df */
986 COSTS_N_INSNS (23), /* fp_div_sf */
987 COSTS_N_INSNS (36), /* fp_div_df */
988 COSTS_N_INSNS (5), /* int_mult_si */
989 COSTS_N_INSNS (5), /* int_mult_di */
990 COSTS_N_INSNS (36), /* int_div_si */
991 COSTS_N_INSNS (36), /* int_div_di */
993 4 /* memory_latency */
996 COSTS_N_INSNS (6), /* fp_add */
997 COSTS_N_INSNS (5), /* fp_mult_sf */
998 COSTS_N_INSNS (6), /* fp_mult_df */
999 COSTS_N_INSNS (30), /* fp_div_sf */
1000 COSTS_N_INSNS (59), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (4), /* int_mult_di */
1003 COSTS_N_INSNS (42), /* int_div_si */
1004 COSTS_N_INSNS (74), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 COSTS_N_INSNS (6), /* fp_add */
1010 COSTS_N_INSNS (5), /* fp_mult_sf */
1011 COSTS_N_INSNS (6), /* fp_mult_df */
1012 COSTS_N_INSNS (30), /* fp_div_sf */
1013 COSTS_N_INSNS (59), /* fp_div_df */
1014 COSTS_N_INSNS (5), /* int_mult_si */
1015 COSTS_N_INSNS (9), /* int_mult_di */
1016 COSTS_N_INSNS (42), /* int_div_si */
1017 COSTS_N_INSNS (74), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1022 /* The only costs that are changed here are
1023 integer multiplication. */
1024 COSTS_N_INSNS (6), /* fp_add */
1025 COSTS_N_INSNS (7), /* fp_mult_sf */
1026 COSTS_N_INSNS (8), /* fp_mult_df */
1027 COSTS_N_INSNS (23), /* fp_div_sf */
1028 COSTS_N_INSNS (36), /* fp_div_df */
1029 COSTS_N_INSNS (5), /* int_mult_si */
1030 COSTS_N_INSNS (9), /* int_mult_di */
1031 COSTS_N_INSNS (69), /* int_div_si */
1032 COSTS_N_INSNS (69), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1040 /* The only costs that are changed here are
1041 integer multiplication. */
1042 COSTS_N_INSNS (6), /* fp_add */
1043 COSTS_N_INSNS (7), /* fp_mult_sf */
1044 COSTS_N_INSNS (8), /* fp_mult_df */
1045 COSTS_N_INSNS (23), /* fp_div_sf */
1046 COSTS_N_INSNS (36), /* fp_div_df */
1047 COSTS_N_INSNS (3), /* int_mult_si */
1048 COSTS_N_INSNS (8), /* int_mult_di */
1049 COSTS_N_INSNS (69), /* int_div_si */
1050 COSTS_N_INSNS (69), /* int_div_di */
1051 1, /* branch_cost */
1052 4 /* memory_latency */
1055 COSTS_N_INSNS (2), /* fp_add */
1056 COSTS_N_INSNS (2), /* fp_mult_sf */
1057 COSTS_N_INSNS (2), /* fp_mult_df */
1058 COSTS_N_INSNS (12), /* fp_div_sf */
1059 COSTS_N_INSNS (19), /* fp_div_df */
1060 COSTS_N_INSNS (5), /* int_mult_si */
1061 COSTS_N_INSNS (9), /* int_mult_di */
1062 COSTS_N_INSNS (34), /* int_div_si */
1063 COSTS_N_INSNS (66), /* int_div_di */
1064 1, /* branch_cost */
1065 4 /* memory_latency */
1068 /* These costs are the same as the SB-1A below. */
1069 COSTS_N_INSNS (4), /* fp_add */
1070 COSTS_N_INSNS (4), /* fp_mult_sf */
1071 COSTS_N_INSNS (4), /* fp_mult_df */
1072 COSTS_N_INSNS (24), /* fp_div_sf */
1073 COSTS_N_INSNS (32), /* fp_div_df */
1074 COSTS_N_INSNS (3), /* int_mult_si */
1075 COSTS_N_INSNS (4), /* int_mult_di */
1076 COSTS_N_INSNS (36), /* int_div_si */
1077 COSTS_N_INSNS (68), /* int_div_di */
1078 1, /* branch_cost */
1079 4 /* memory_latency */
1082 /* These costs are the same as the SB-1 above. */
1083 COSTS_N_INSNS (4), /* fp_add */
1084 COSTS_N_INSNS (4), /* fp_mult_sf */
1085 COSTS_N_INSNS (4), /* fp_mult_df */
1086 COSTS_N_INSNS (24), /* fp_div_sf */
1087 COSTS_N_INSNS (32), /* fp_div_df */
1088 COSTS_N_INSNS (3), /* int_mult_si */
1089 COSTS_N_INSNS (4), /* int_mult_di */
1090 COSTS_N_INSNS (36), /* int_div_si */
1091 COSTS_N_INSNS (68), /* int_div_di */
1092 1, /* branch_cost */
1093 4 /* memory_latency */
1100 COSTS_N_INSNS (8), /* int_mult_si */
1101 COSTS_N_INSNS (8), /* int_mult_di */
1102 COSTS_N_INSNS (72), /* int_div_si */
1103 COSTS_N_INSNS (72), /* int_div_di */
1104 1, /* branch_cost */
1105 4 /* memory_latency */
1109 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1110 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1111 struct GTY (()) mflip_mips16_entry {
1115 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1117 /* Hash table callbacks for mflip_mips16_htab. */
1120 mflip_mips16_htab_hash (const void *entry)
1122 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1126 mflip_mips16_htab_eq (const void *entry, const void *name)
1128 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1129 (const char *) name) == 0;
1132 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1133 mode, false if it should next add an attribute for the opposite mode. */
1134 static GTY(()) bool mips16_flipper;
1136 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1137 for -mflip-mips16. Return true if it should use "mips16" and false if
1138 it should use "nomips16". */
1141 mflip_mips16_use_mips16_p (tree decl)
1143 struct mflip_mips16_entry *entry;
1148 /* Use the opposite of the command-line setting for anonymous decls. */
1149 if (!DECL_NAME (decl))
1150 return !mips_base_mips16;
1152 if (!mflip_mips16_htab)
1153 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1154 mflip_mips16_htab_eq, NULL);
1156 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1157 hash = htab_hash_string (name);
1158 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1159 entry = (struct mflip_mips16_entry *) *slot;
1162 mips16_flipper = !mips16_flipper;
1163 entry = GGC_NEW (struct mflip_mips16_entry);
1165 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1168 return entry->mips16_p;
1171 /* Predicates to test for presence of "near" and "far"/"long_call"
1172 attributes on the given TYPE. */
1175 mips_near_type_p (const_tree type)
1177 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1181 mips_far_type_p (const_tree type)
1183 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1184 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1187 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1190 mips_mips16_decl_p (const_tree decl)
1192 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1196 mips_nomips16_decl_p (const_tree decl)
1198 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1201 /* Check if the interrupt attribute is set for a function. */
1204 mips_interrupt_type_p (tree type)
1206 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1209 /* Check if the attribute to use shadow register set is set for a function. */
1212 mips_use_shadow_register_set_p (tree type)
1214 return lookup_attribute ("use_shadow_register_set",
1215 TYPE_ATTRIBUTES (type)) != NULL;
1218 /* Check if the attribute to keep interrupts masked is set for a function. */
1221 mips_keep_interrupts_masked_p (tree type)
1223 return lookup_attribute ("keep_interrupts_masked",
1224 TYPE_ATTRIBUTES (type)) != NULL;
1227 /* Check if the attribute to use debug exception return is set for
1231 mips_use_debug_exception_return_p (tree type)
1233 return lookup_attribute ("use_debug_exception_return",
1234 TYPE_ATTRIBUTES (type)) != NULL;
1237 /* Return true if function DECL is a MIPS16 function. Return the ambient
1238 setting if DECL is null. */
1241 mips_use_mips16_mode_p (tree decl)
1245 /* Nested functions must use the same frame pointer as their
1246 parent and must therefore use the same ISA mode. */
1247 tree parent = decl_function_context (decl);
1250 if (mips_mips16_decl_p (decl))
1252 if (mips_nomips16_decl_p (decl))
1255 return mips_base_mips16;
1258 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1261 mips_comp_type_attributes (const_tree type1, const_tree type2)
1263 /* Disallow mixed near/far attributes. */
1264 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1266 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1271 /* Implement TARGET_INSERT_ATTRIBUTES. */
1274 mips_insert_attributes (tree decl, tree *attributes)
1277 bool mips16_p, nomips16_p;
1279 /* Check for "mips16" and "nomips16" attributes. */
1280 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1281 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1282 if (TREE_CODE (decl) != FUNCTION_DECL)
1285 error ("%qs attribute only applies to functions", "mips16");
1287 error ("%qs attribute only applies to functions", "nomips16");
1291 mips16_p |= mips_mips16_decl_p (decl);
1292 nomips16_p |= mips_nomips16_decl_p (decl);
1293 if (mips16_p || nomips16_p)
1295 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1296 if (mips16_p && nomips16_p)
1297 error ("%qE cannot have both %<mips16%> and "
1298 "%<nomips16%> attributes",
1301 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1303 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1304 "mips16" attribute, arbitrarily pick one. We must pick the same
1305 setting for duplicate declarations of a function. */
1306 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1307 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1312 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1315 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1317 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1318 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1319 error ("%qE redeclared with conflicting %qs attributes",
1320 DECL_NAME (newdecl), "mips16");
1321 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1322 error ("%qE redeclared with conflicting %qs attributes",
1323 DECL_NAME (newdecl), "nomips16");
1325 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1326 DECL_ATTRIBUTES (newdecl));
1329 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1330 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1333 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1335 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1337 *base_ptr = XEXP (x, 0);
1338 *offset_ptr = INTVAL (XEXP (x, 1));
1347 static unsigned int mips_build_integer (struct mips_integer_op *,
1348 unsigned HOST_WIDE_INT);
1350 /* A subroutine of mips_build_integer, with the same interface.
1351 Assume that the final action in the sequence should be a left shift. */
1354 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1356 unsigned int i, shift;
1358 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1359 since signed numbers are easier to load than unsigned ones. */
1361 while ((value & 1) == 0)
1362 value /= 2, shift++;
1364 i = mips_build_integer (codes, value);
1365 codes[i].code = ASHIFT;
1366 codes[i].value = shift;
1370 /* As for mips_build_shift, but assume that the final action will be
1371 an IOR or PLUS operation. */
1374 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1376 unsigned HOST_WIDE_INT high;
1379 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1380 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1382 /* The constant is too complex to load with a simple LUI/ORI pair,
1383 so we want to give the recursive call as many trailing zeros as
1384 possible. In this case, we know bit 16 is set and that the
1385 low 16 bits form a negative number. If we subtract that number
1386 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1387 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1388 codes[i].code = PLUS;
1389 codes[i].value = CONST_LOW_PART (value);
1393 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1394 bits gives a value with at least 17 trailing zeros. */
1395 i = mips_build_integer (codes, high);
1396 codes[i].code = IOR;
1397 codes[i].value = value & 0xffff;
1402 /* Fill CODES with a sequence of rtl operations to load VALUE.
1403 Return the number of operations needed. */
1406 mips_build_integer (struct mips_integer_op *codes,
1407 unsigned HOST_WIDE_INT value)
1409 if (SMALL_OPERAND (value)
1410 || SMALL_OPERAND_UNSIGNED (value)
1411 || LUI_OPERAND (value))
1413 /* The value can be loaded with a single instruction. */
1414 codes[0].code = UNKNOWN;
1415 codes[0].value = value;
1418 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1420 /* Either the constant is a simple LUI/ORI combination or its
1421 lowest bit is set. We don't want to shift in this case. */
1422 return mips_build_lower (codes, value);
1424 else if ((value & 0xffff) == 0)
1426 /* The constant will need at least three actions. The lowest
1427 16 bits are clear, so the final action will be a shift. */
1428 return mips_build_shift (codes, value);
1432 /* The final action could be a shift, add or inclusive OR.
1433 Rather than use a complex condition to select the best
1434 approach, try both mips_build_shift and mips_build_lower
1435 and pick the one that gives the shortest sequence.
1436 Note that this case is only used once per constant. */
1437 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1438 unsigned int cost, alt_cost;
1440 cost = mips_build_shift (codes, value);
1441 alt_cost = mips_build_lower (alt_codes, value);
1442 if (alt_cost < cost)
1444 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1451 /* Return true if symbols of type TYPE require a GOT access. */
1454 mips_got_symbol_type_p (enum mips_symbol_type type)
1458 case SYMBOL_GOT_PAGE_OFST:
1459 case SYMBOL_GOT_DISP:
1467 /* Return true if X is a thread-local symbol. */
1470 mips_tls_symbol_p (rtx x)
1472 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1475 /* Return true if SYMBOL_REF X is associated with a global symbol
1476 (in the STB_GLOBAL sense). */
1479 mips_global_symbol_p (const_rtx x)
1481 const_tree decl = SYMBOL_REF_DECL (x);
1484 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1486 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1487 or weak symbols. Relocations in the object file will be against
1488 the target symbol, so it's that symbol's binding that matters here. */
1489 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1492 /* Return true if function X is a libgcc MIPS16 stub function. */
1495 mips16_stub_function_p (const_rtx x)
1497 return (GET_CODE (x) == SYMBOL_REF
1498 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1501 /* Return true if function X is a locally-defined and locally-binding
1505 mips16_local_function_p (const_rtx x)
1507 return (GET_CODE (x) == SYMBOL_REF
1508 && SYMBOL_REF_LOCAL_P (x)
1509 && !SYMBOL_REF_EXTERNAL_P (x)
1510 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1513 /* Return true if SYMBOL_REF X binds locally. */
1516 mips_symbol_binds_local_p (const_rtx x)
1518 return (SYMBOL_REF_DECL (x)
1519 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1520 : SYMBOL_REF_LOCAL_P (x));
1523 /* Return true if rtx constants of mode MODE should be put into a small
1527 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1529 return (!TARGET_EMBEDDED_DATA
1530 && TARGET_LOCAL_SDATA
1531 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1534 /* Return true if X should not be moved directly into register $25.
1535 We need this because many versions of GAS will treat "la $25,foo" as
1536 part of a call sequence and so allow a global "foo" to be lazily bound. */
1539 mips_dangerous_for_la25_p (rtx x)
1541 return (!TARGET_EXPLICIT_RELOCS
1543 && GET_CODE (x) == SYMBOL_REF
1544 && mips_global_symbol_p (x));
1547 /* Return true if calls to X might need $25 to be valid on entry. */
1550 mips_use_pic_fn_addr_reg_p (const_rtx x)
1552 if (!TARGET_USE_PIC_FN_ADDR_REG)
1555 /* MIPS16 stub functions are guaranteed not to use $25. */
1556 if (mips16_stub_function_p (x))
1559 if (GET_CODE (x) == SYMBOL_REF)
1561 /* If PLTs and copy relocations are available, the static linker
1562 will make sure that $25 is valid on entry to the target function. */
1563 if (TARGET_ABICALLS_PIC0)
1566 /* Locally-defined functions use absolute accesses to set up
1567 the global pointer. */
1568 if (TARGET_ABSOLUTE_ABICALLS
1569 && mips_symbol_binds_local_p (x)
1570 && !SYMBOL_REF_EXTERNAL_P (x))
1577 /* Return the method that should be used to access SYMBOL_REF or
1578 LABEL_REF X in context CONTEXT. */
1580 static enum mips_symbol_type
1581 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1584 return SYMBOL_GOT_DISP;
1586 if (GET_CODE (x) == LABEL_REF)
1588 /* LABEL_REFs are used for jump tables as well as text labels.
1589 Only return SYMBOL_PC_RELATIVE if we know the label is in
1590 the text section. */
1591 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1592 return SYMBOL_PC_RELATIVE;
1594 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1595 return SYMBOL_GOT_PAGE_OFST;
1597 return SYMBOL_ABSOLUTE;
1600 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1602 if (SYMBOL_REF_TLS_MODEL (x))
1605 if (CONSTANT_POOL_ADDRESS_P (x))
1607 if (TARGET_MIPS16_TEXT_LOADS)
1608 return SYMBOL_PC_RELATIVE;
1610 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1611 return SYMBOL_PC_RELATIVE;
1613 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1614 return SYMBOL_GP_RELATIVE;
1617 /* Do not use small-data accesses for weak symbols; they may end up
1619 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1620 return SYMBOL_GP_RELATIVE;
1622 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1624 if (TARGET_ABICALLS_PIC2
1625 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1627 /* There are three cases to consider:
1629 - o32 PIC (either with or without explicit relocs)
1630 - n32/n64 PIC without explicit relocs
1631 - n32/n64 PIC with explicit relocs
1633 In the first case, both local and global accesses will use an
1634 R_MIPS_GOT16 relocation. We must correctly predict which of
1635 the two semantics (local or global) the assembler and linker
1636 will apply. The choice depends on the symbol's binding rather
1637 than its visibility.
1639 In the second case, the assembler will not use R_MIPS_GOT16
1640 relocations, but it chooses between local and global accesses
1641 in the same way as for o32 PIC.
1643 In the third case we have more freedom since both forms of
1644 access will work for any kind of symbol. However, there seems
1645 little point in doing things differently. */
1646 if (mips_global_symbol_p (x))
1647 return SYMBOL_GOT_DISP;
1649 return SYMBOL_GOT_PAGE_OFST;
1652 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1653 return SYMBOL_FORCE_TO_MEM;
1655 return SYMBOL_ABSOLUTE;
1658 /* Classify the base of symbolic expression X, given that X appears in
1661 static enum mips_symbol_type
1662 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1666 split_const (x, &x, &offset);
1667 if (UNSPEC_ADDRESS_P (x))
1668 return UNSPEC_ADDRESS_TYPE (x);
1670 return mips_classify_symbol (x, context);
1673 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1674 is the alignment in bytes of SYMBOL_REF X. */
1677 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1679 HOST_WIDE_INT align;
1681 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1682 return IN_RANGE (offset, 0, align - 1);
1685 /* Return true if X is a symbolic constant that can be used in context
1686 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1689 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1690 enum mips_symbol_type *symbol_type)
1694 split_const (x, &x, &offset);
1695 if (UNSPEC_ADDRESS_P (x))
1697 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1698 x = UNSPEC_ADDRESS (x);
1700 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1702 *symbol_type = mips_classify_symbol (x, context);
1703 if (*symbol_type == SYMBOL_TLS)
1709 if (offset == const0_rtx)
1712 /* Check whether a nonzero offset is valid for the underlying
1714 switch (*symbol_type)
1716 case SYMBOL_ABSOLUTE:
1717 case SYMBOL_FORCE_TO_MEM:
1718 case SYMBOL_32_HIGH:
1719 case SYMBOL_64_HIGH:
1722 /* If the target has 64-bit pointers and the object file only
1723 supports 32-bit symbols, the values of those symbols will be
1724 sign-extended. In this case we can't allow an arbitrary offset
1725 in case the 32-bit value X + OFFSET has a different sign from X. */
1726 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1727 return offset_within_block_p (x, INTVAL (offset));
1729 /* In other cases the relocations can handle any offset. */
1732 case SYMBOL_PC_RELATIVE:
1733 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1734 In this case, we no longer have access to the underlying constant,
1735 but the original symbol-based access was known to be valid. */
1736 if (GET_CODE (x) == LABEL_REF)
1741 case SYMBOL_GP_RELATIVE:
1742 /* Make sure that the offset refers to something within the
1743 same object block. This should guarantee that the final
1744 PC- or GP-relative offset is within the 16-bit limit. */
1745 return offset_within_block_p (x, INTVAL (offset));
1747 case SYMBOL_GOT_PAGE_OFST:
1748 case SYMBOL_GOTOFF_PAGE:
1749 /* If the symbol is global, the GOT entry will contain the symbol's
1750 address, and we will apply a 16-bit offset after loading it.
1751 If the symbol is local, the linker should provide enough local
1752 GOT entries for a 16-bit offset, but larger offsets may lead
1754 return SMALL_INT (offset);
1758 /* There is no carry between the HI and LO REL relocations, so the
1759 offset is only valid if we know it won't lead to such a carry. */
1760 return mips_offset_within_alignment_p (x, INTVAL (offset));
1762 case SYMBOL_GOT_DISP:
1763 case SYMBOL_GOTOFF_DISP:
1764 case SYMBOL_GOTOFF_CALL:
1765 case SYMBOL_GOTOFF_LOADGP:
1768 case SYMBOL_GOTTPREL:
1776 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1777 single instruction. We rely on the fact that, in the worst case,
1778 all instructions involved in a MIPS16 address calculation are usually
1782 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1786 case SYMBOL_ABSOLUTE:
1787 /* When using 64-bit symbols, we need 5 preparatory instructions,
1790 lui $at,%highest(symbol)
1791 daddiu $at,$at,%higher(symbol)
1793 daddiu $at,$at,%hi(symbol)
1796 The final address is then $at + %lo(symbol). With 32-bit
1797 symbols we just need a preparatory LUI for normal mode and
1798 a preparatory LI and SLL for MIPS16. */
1799 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1801 case SYMBOL_GP_RELATIVE:
1802 /* Treat GP-relative accesses as taking a single instruction on
1803 MIPS16 too; the copy of $gp can often be shared. */
1806 case SYMBOL_PC_RELATIVE:
1807 /* PC-relative constants can be only be used with ADDIUPC,
1808 DADDIUPC, LWPC and LDPC. */
1809 if (mode == MAX_MACHINE_MODE
1810 || GET_MODE_SIZE (mode) == 4
1811 || GET_MODE_SIZE (mode) == 8)
1814 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1817 case SYMBOL_FORCE_TO_MEM:
1818 /* LEAs will be converted into constant-pool references by
1820 if (mode == MAX_MACHINE_MODE)
1823 /* The constant must be loaded and then dereferenced. */
1826 case SYMBOL_GOT_DISP:
1827 /* The constant will have to be loaded from the GOT before it
1828 is used in an address. */
1829 if (mode != MAX_MACHINE_MODE)
1834 case SYMBOL_GOT_PAGE_OFST:
1835 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1836 local/global classification is accurate. The worst cases are:
1838 (1) For local symbols when generating o32 or o64 code. The assembler
1844 ...and the final address will be $at + %lo(symbol).
1846 (2) For global symbols when -mxgot. The assembler will use:
1848 lui $at,%got_hi(symbol)
1851 ...and the final address will be $at + %got_lo(symbol). */
1854 case SYMBOL_GOTOFF_PAGE:
1855 case SYMBOL_GOTOFF_DISP:
1856 case SYMBOL_GOTOFF_CALL:
1857 case SYMBOL_GOTOFF_LOADGP:
1858 case SYMBOL_32_HIGH:
1859 case SYMBOL_64_HIGH:
1865 case SYMBOL_GOTTPREL:
1868 /* A 16-bit constant formed by a single relocation, or a 32-bit
1869 constant formed from a high 16-bit relocation and a low 16-bit
1870 relocation. Use mips_split_p to determine which. 32-bit
1871 constants need an "lui; addiu" sequence for normal mode and
1872 an "li; sll; addiu" sequence for MIPS16 mode. */
1873 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1876 /* We don't treat a bare TLS symbol as a constant. */
1882 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1883 to load symbols of type TYPE into a register. Return 0 if the given
1884 type of symbol cannot be used as an immediate operand.
1886 Otherwise, return the number of instructions needed to load or store
1887 values of mode MODE to or from addresses of type TYPE. Return 0 if
1888 the given type of symbol is not valid in addresses.
1890 In both cases, treat extended MIPS16 instructions as two instructions. */
1893 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1895 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1898 /* A for_each_rtx callback. Stop the search if *X references a
1899 thread-local symbol. */
1902 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1904 return mips_tls_symbol_p (*x);
1907 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1910 mips_cannot_force_const_mem (rtx x)
1912 enum mips_symbol_type type;
1915 /* There is no assembler syntax for expressing an address-sized
1917 if (GET_CODE (x) == HIGH)
1920 /* As an optimization, reject constants that mips_legitimize_move
1923 Suppose we have a multi-instruction sequence that loads constant C
1924 into register R. If R does not get allocated a hard register, and
1925 R is used in an operand that allows both registers and memory
1926 references, reload will consider forcing C into memory and using
1927 one of the instruction's memory alternatives. Returning false
1928 here will force it to use an input reload instead. */
1929 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1932 split_const (x, &base, &offset);
1933 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1934 && type != SYMBOL_FORCE_TO_MEM)
1936 /* The same optimization as for CONST_INT. */
1937 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1940 /* If MIPS16 constant pools live in the text section, they should
1941 not refer to anything that might need run-time relocation. */
1942 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1946 /* TLS symbols must be computed by mips_legitimize_move. */
1947 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1953 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1954 constants when we're using a per-function constant pool. */
1957 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1958 const_rtx x ATTRIBUTE_UNUSED)
1960 return !TARGET_MIPS16_PCREL_LOADS;
1963 /* Return true if register REGNO is a valid base register for mode MODE.
1964 STRICT_P is true if REG_OK_STRICT is in effect. */
1967 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1970 if (!HARD_REGISTER_NUM_P (regno))
1974 regno = reg_renumber[regno];
1977 /* These fake registers will be eliminated to either the stack or
1978 hard frame pointer, both of which are usually valid base registers.
1979 Reload deals with the cases where the eliminated form isn't valid. */
1980 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1983 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1984 values, nothing smaller. There are two problems here:
1986 (a) Instantiating virtual registers can introduce new uses of the
1987 stack pointer. If these virtual registers are valid addresses,
1988 the stack pointer should be too.
1990 (b) Most uses of the stack pointer are not made explicit until
1991 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1992 We don't know until that stage whether we'll be eliminating to the
1993 stack pointer (which needs the restriction) or the hard frame
1994 pointer (which doesn't).
1996 All in all, it seems more consistent to only enforce this restriction
1997 during and after reload. */
1998 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1999 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2001 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2004 /* Return true if X is a valid base register for mode MODE.
2005 STRICT_P is true if REG_OK_STRICT is in effect. */
2008 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2010 if (!strict_p && GET_CODE (x) == SUBREG)
2014 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2017 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2018 can address a value of mode MODE. */
2021 mips_valid_offset_p (rtx x, enum machine_mode mode)
2023 /* Check that X is a signed 16-bit number. */
2024 if (!const_arith_operand (x, Pmode))
2027 /* We may need to split multiword moves, so make sure that every word
2029 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2030 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2036 /* Return true if a LO_SUM can address a value of mode MODE when the
2037 LO_SUM symbol has type SYMBOL_TYPE. */
2040 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2042 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2044 if (mips_symbol_insns (symbol_type, mode) == 0)
2047 /* Check that there is a known low-part relocation. */
2048 if (mips_lo_relocs[symbol_type] == NULL)
2051 /* We may need to split multiword moves, so make sure that each word
2052 can be accessed without inducing a carry. This is mainly needed
2053 for o64, which has historically only guaranteed 64-bit alignment
2054 for 128-bit types. */
2055 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2056 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2062 /* Return true if X is a valid address for machine mode MODE. If it is,
2063 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2067 mips_classify_address (struct mips_address_info *info, rtx x,
2068 enum machine_mode mode, bool strict_p)
2070 switch (GET_CODE (x))
2074 info->type = ADDRESS_REG;
2076 info->offset = const0_rtx;
2077 return mips_valid_base_register_p (info->reg, mode, strict_p);
2080 info->type = ADDRESS_REG;
2081 info->reg = XEXP (x, 0);
2082 info->offset = XEXP (x, 1);
2083 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2084 && mips_valid_offset_p (info->offset, mode));
2087 info->type = ADDRESS_LO_SUM;
2088 info->reg = XEXP (x, 0);
2089 info->offset = XEXP (x, 1);
2090 /* We have to trust the creator of the LO_SUM to do something vaguely
2091 sane. Target-independent code that creates a LO_SUM should also
2092 create and verify the matching HIGH. Target-independent code that
2093 adds an offset to a LO_SUM must prove that the offset will not
2094 induce a carry. Failure to do either of these things would be
2095 a bug, and we are not required to check for it here. The MIPS
2096 backend itself should only create LO_SUMs for valid symbolic
2097 constants, with the high part being either a HIGH or a copy
2100 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2101 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2102 && mips_valid_lo_sum_p (info->symbol_type, mode));
2105 /* Small-integer addresses don't occur very often, but they
2106 are legitimate if $0 is a valid base register. */
2107 info->type = ADDRESS_CONST_INT;
2108 return !TARGET_MIPS16 && SMALL_INT (x);
2113 info->type = ADDRESS_SYMBOLIC;
2114 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2116 && mips_symbol_insns (info->symbol_type, mode) > 0
2117 && !mips_split_p[info->symbol_type]);
2124 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2127 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2129 struct mips_address_info addr;
2131 return mips_classify_address (&addr, x, mode, strict_p);
2134 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2137 mips_stack_address_p (rtx x, enum machine_mode mode)
2139 struct mips_address_info addr;
2141 return (mips_classify_address (&addr, x, mode, false)
2142 && addr.type == ADDRESS_REG
2143 && addr.reg == stack_pointer_rtx);
2146 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2147 address instruction. Note that such addresses are not considered
2148 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2149 is so restricted. */
2152 mips_lwxs_address_p (rtx addr)
2155 && GET_CODE (addr) == PLUS
2156 && REG_P (XEXP (addr, 1)))
2158 rtx offset = XEXP (addr, 0);
2159 if (GET_CODE (offset) == MULT
2160 && REG_P (XEXP (offset, 0))
2161 && CONST_INT_P (XEXP (offset, 1))
2162 && INTVAL (XEXP (offset, 1)) == 4)
2168 /* Return true if a value at OFFSET bytes from base register BASE can be
2169 accessed using an unextended MIPS16 instruction. MODE is the mode of
2172 Usually the offset in an unextended instruction is a 5-bit field.
2173 The offset is unsigned and shifted left once for LH and SH, twice
2174 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2175 an 8-bit immediate field that's shifted left twice. */
2178 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2179 unsigned HOST_WIDE_INT offset)
2181 if (offset % GET_MODE_SIZE (mode) == 0)
2183 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2184 return offset < 256U * GET_MODE_SIZE (mode);
2185 return offset < 32U * GET_MODE_SIZE (mode);
2190 /* Return the number of instructions needed to load or store a value
2191 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2192 Assume that multiword moves may need to be split into word moves
2193 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2196 For MIPS16 code, count extended instructions as two instructions. */
2199 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2201 struct mips_address_info addr;
2204 /* BLKmode is used for single unaligned loads and stores and should
2205 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2206 meaningless, so we have to single it out as a special case one way
2208 if (mode != BLKmode && might_split_p)
2209 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2213 if (mips_classify_address (&addr, x, mode, false))
2218 && !mips16_unextended_reference_p (mode, addr.reg,
2219 UINTVAL (addr.offset)))
2223 case ADDRESS_LO_SUM:
2224 return TARGET_MIPS16 ? factor * 2 : factor;
2226 case ADDRESS_CONST_INT:
2229 case ADDRESS_SYMBOLIC:
2230 return factor * mips_symbol_insns (addr.symbol_type, mode);
2235 /* Return the number of instructions needed to load constant X.
2236 Return 0 if X isn't a valid constant. */
2239 mips_const_insns (rtx x)
2241 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2242 enum mips_symbol_type symbol_type;
2245 switch (GET_CODE (x))
2248 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2250 || !mips_split_p[symbol_type])
2253 /* This is simply an LUI for normal mode. It is an extended
2254 LI followed by an extended SLL for MIPS16. */
2255 return TARGET_MIPS16 ? 4 : 1;
2259 /* Unsigned 8-bit constants can be loaded using an unextended
2260 LI instruction. Unsigned 16-bit constants can be loaded
2261 using an extended LI. Negative constants must be loaded
2262 using LI and then negated. */
2263 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2264 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2265 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2266 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2269 return mips_build_integer (codes, INTVAL (x));
2273 /* Allow zeros for normal mode, where we can use $0. */
2274 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2280 /* See if we can refer to X directly. */
2281 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2282 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2284 /* Otherwise try splitting the constant into a base and offset.
2285 If the offset is a 16-bit value, we can load the base address
2286 into a register and then use (D)ADDIU to add in the offset.
2287 If the offset is larger, we can load the base and offset
2288 into separate registers and add them together with (D)ADDU.
2289 However, the latter is only possible before reload; during
2290 and after reload, we must have the option of forcing the
2291 constant into the pool instead. */
2292 split_const (x, &x, &offset);
2295 int n = mips_const_insns (x);
2298 if (SMALL_INT (offset))
2300 else if (!targetm.cannot_force_const_mem (x))
2301 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2308 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2316 /* X is a doubleword constant that can be handled by splitting it into
2317 two words and loading each word separately. Return the number of
2318 instructions required to do this. */
2321 mips_split_const_insns (rtx x)
2323 unsigned int low, high;
2325 low = mips_const_insns (mips_subword (x, false));
2326 high = mips_const_insns (mips_subword (x, true));
2327 gcc_assert (low > 0 && high > 0);
2331 /* Return the number of instructions needed to implement INSN,
2332 given that it loads from or stores to MEM. Count extended
2333 MIPS16 instructions as two instructions. */
2336 mips_load_store_insns (rtx mem, rtx insn)
2338 enum machine_mode mode;
2342 gcc_assert (MEM_P (mem));
2343 mode = GET_MODE (mem);
2345 /* Try to prove that INSN does not need to be split. */
2346 might_split_p = true;
2347 if (GET_MODE_BITSIZE (mode) == 64)
2349 set = single_set (insn);
2350 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2351 might_split_p = false;
2354 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2357 /* Return the number of instructions needed for an integer division. */
2360 mips_idiv_insns (void)
2365 if (TARGET_CHECK_ZERO_DIV)
2367 if (GENERATE_DIVIDE_TRAPS)
2373 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2378 /* Emit a move from SRC to DEST. Assume that the move expanders can
2379 handle all moves if !can_create_pseudo_p (). The distinction is
2380 important because, unlike emit_move_insn, the move expanders know
2381 how to force Pmode objects into the constant pool even when the
2382 constant pool address is not itself legitimate. */
2385 mips_emit_move (rtx dest, rtx src)
2387 return (can_create_pseudo_p ()
2388 ? emit_move_insn (dest, src)
2389 : emit_move_insn_1 (dest, src));
2392 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2395 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2397 emit_insn (gen_rtx_SET (VOIDmode, target,
2398 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2401 /* Compute (CODE OP0 OP1) and store the result in a new register
2402 of mode MODE. Return that new register. */
2405 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2409 reg = gen_reg_rtx (mode);
2410 mips_emit_binary (code, reg, op0, op1);
2414 /* Copy VALUE to a register and return that register. If new pseudos
2415 are allowed, copy it into a new register, otherwise use DEST. */
2418 mips_force_temporary (rtx dest, rtx value)
2420 if (can_create_pseudo_p ())
2421 return force_reg (Pmode, value);
2424 mips_emit_move (dest, value);
2429 /* Emit a call sequence with call pattern PATTERN and return the call
2430 instruction itself (which is not necessarily the last instruction
2431 emitted). ORIG_ADDR is the original, unlegitimized address,
2432 ADDR is the legitimized form, and LAZY_P is true if the call
2433 address is lazily-bound. */
2436 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2440 insn = emit_call_insn (pattern);
2442 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2444 /* MIPS16 JALRs only take MIPS16 registers. If the target
2445 function requires $25 to be valid on entry, we must copy it
2446 there separately. The move instruction can be put in the
2447 call's delay slot. */
2448 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2449 emit_insn_before (gen_move_insn (reg, addr), insn);
2450 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2454 /* Lazy-binding stubs require $gp to be valid on entry. */
2455 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2459 /* See the comment above load_call<mode> for details. */
2460 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2461 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2462 emit_insn (gen_update_got_version ());
2467 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2468 then add CONST_INT OFFSET to the result. */
2471 mips_unspec_address_offset (rtx base, rtx offset,
2472 enum mips_symbol_type symbol_type)
2474 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2475 UNSPEC_ADDRESS_FIRST + symbol_type);
2476 if (offset != const0_rtx)
2477 base = gen_rtx_PLUS (Pmode, base, offset);
2478 return gen_rtx_CONST (Pmode, base);
2481 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2482 type SYMBOL_TYPE. */
2485 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2489 split_const (address, &base, &offset);
2490 return mips_unspec_address_offset (base, offset, symbol_type);
2493 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2494 high part to BASE and return the result. Just return BASE otherwise.
2495 TEMP is as for mips_force_temporary.
2497 The returned expression can be used as the first operand to a LO_SUM. */
2500 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2501 enum mips_symbol_type symbol_type)
2503 if (mips_split_p[symbol_type])
2505 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2506 addr = mips_force_temporary (temp, addr);
2507 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2512 /* Return an instruction that copies $gp into register REG. We want
2513 GCC to treat the register's value as constant, so that its value
2514 can be rematerialized on demand. */
2517 gen_load_const_gp (rtx reg)
2519 return (Pmode == SImode
2520 ? gen_load_const_gp_si (reg)
2521 : gen_load_const_gp_di (reg));
2524 /* Return a pseudo register that contains the value of $gp throughout
2525 the current function. Such registers are needed by MIPS16 functions,
2526 for which $gp itself is not a valid base register or addition operand. */
2529 mips16_gp_pseudo_reg (void)
2531 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2532 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2534 /* Don't emit an instruction to initialize the pseudo register if
2535 we are being called from the tree optimizers' cost-calculation
2537 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2538 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2542 push_topmost_sequence ();
2544 scan = get_insns ();
2545 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2546 scan = NEXT_INSN (scan);
2548 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2549 emit_insn_after (insn, scan);
2551 pop_topmost_sequence ();
2553 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2556 return cfun->machine->mips16_gp_pseudo_rtx;
2559 /* Return a base register that holds pic_offset_table_rtx.
2560 TEMP, if nonnull, is a scratch Pmode base register. */
2563 mips_pic_base_register (rtx temp)
2566 return pic_offset_table_rtx;
2568 if (can_create_pseudo_p ())
2569 return mips16_gp_pseudo_reg ();
2572 /* The first post-reload split exposes all references to $gp
2573 (both uses and definitions). All references must remain
2574 explicit after that point.
2576 It is safe to introduce uses of $gp at any time, so for
2577 simplicity, we do that before the split too. */
2578 mips_emit_move (temp, pic_offset_table_rtx);
2580 emit_insn (gen_load_const_gp (temp));
2584 /* Create and return a GOT reference of type TYPE for address ADDR.
2585 TEMP, if nonnull, is a scratch Pmode base register. */
2588 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2590 rtx base, high, lo_sum_symbol;
2592 base = mips_pic_base_register (temp);
2594 /* If we used the temporary register to load $gp, we can't use
2595 it for the high part as well. */
2596 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2599 high = mips_unspec_offset_high (temp, base, addr, type);
2600 lo_sum_symbol = mips_unspec_address (addr, type);
2602 if (type == SYMBOL_GOTOFF_CALL)
2603 return (Pmode == SImode
2604 ? gen_unspec_callsi (high, lo_sum_symbol)
2605 : gen_unspec_calldi (high, lo_sum_symbol));
2607 return (Pmode == SImode
2608 ? gen_unspec_gotsi (high, lo_sum_symbol)
2609 : gen_unspec_gotdi (high, lo_sum_symbol));
2612 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2613 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2614 constant in that context and can be split into high and low parts.
2615 If so, and if LOW_OUT is nonnull, emit the high part and store the
2616 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2618 TEMP is as for mips_force_temporary and is used to load the high
2619 part into a register.
2621 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2622 a legitimize SET_SRC for an .md pattern, otherwise the low part
2623 is guaranteed to be a legitimate address for mode MODE. */
2626 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2628 enum mips_symbol_context context;
2629 enum mips_symbol_type symbol_type;
2632 context = (mode == MAX_MACHINE_MODE
2633 ? SYMBOL_CONTEXT_LEA
2634 : SYMBOL_CONTEXT_MEM);
2635 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2637 addr = XEXP (addr, 0);
2638 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2639 && mips_symbol_insns (symbol_type, mode) > 0
2640 && mips_split_hi_p[symbol_type])
2643 switch (symbol_type)
2645 case SYMBOL_GOT_PAGE_OFST:
2646 /* The high part of a page/ofst pair is loaded from the GOT. */
2647 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2658 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2659 && mips_symbol_insns (symbol_type, mode) > 0
2660 && mips_split_p[symbol_type])
2663 switch (symbol_type)
2665 case SYMBOL_GOT_DISP:
2666 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2667 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2670 case SYMBOL_GP_RELATIVE:
2671 high = mips_pic_base_register (temp);
2672 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2676 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2677 high = mips_force_temporary (temp, high);
2678 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2687 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2688 mips_force_temporary; it is only needed when OFFSET is not a
2692 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2694 if (!SMALL_OPERAND (offset))
2700 /* Load the full offset into a register so that we can use
2701 an unextended instruction for the address itself. */
2702 high = GEN_INT (offset);
2707 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2708 The addition inside the macro CONST_HIGH_PART may cause an
2709 overflow, so we need to force a sign-extension check. */
2710 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2711 offset = CONST_LOW_PART (offset);
2713 high = mips_force_temporary (temp, high);
2714 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2716 return plus_constant (reg, offset);
2719 /* The __tls_get_attr symbol. */
2720 static GTY(()) rtx mips_tls_symbol;
2722 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2723 the TLS symbol we are referencing and TYPE is the symbol type to use
2724 (either global dynamic or local dynamic). V0 is an RTX for the
2725 return value location. */
2728 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2732 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2734 if (!mips_tls_symbol)
2735 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2737 loc = mips_unspec_address (sym, type);
2741 emit_insn (gen_rtx_SET (Pmode, a0,
2742 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2743 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2744 const0_rtx, NULL_RTX, false);
2745 RTL_CONST_CALL_P (insn) = 1;
2746 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2747 insn = get_insns ();
2754 /* Return a pseudo register that contains the current thread pointer. */
2761 tp = gen_reg_rtx (Pmode);
2762 if (Pmode == DImode)
2763 emit_insn (gen_tls_get_tp_di (tp));
2765 emit_insn (gen_tls_get_tp_si (tp));
2769 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2770 its address. The return value will be both a valid address and a valid
2771 SET_SRC (either a REG or a LO_SUM). */
2774 mips_legitimize_tls_address (rtx loc)
2776 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2777 enum tls_model model;
2781 sorry ("MIPS16 TLS");
2782 return gen_reg_rtx (Pmode);
2785 model = SYMBOL_REF_TLS_MODEL (loc);
2786 /* Only TARGET_ABICALLS code can have more than one module; other
2787 code must be be static and should not use a GOT. All TLS models
2788 reduce to local exec in this situation. */
2789 if (!TARGET_ABICALLS)
2790 model = TLS_MODEL_LOCAL_EXEC;
2794 case TLS_MODEL_GLOBAL_DYNAMIC:
2795 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2796 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2797 dest = gen_reg_rtx (Pmode);
2798 emit_libcall_block (insn, dest, v0, loc);
2801 case TLS_MODEL_LOCAL_DYNAMIC:
2802 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2803 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2804 tmp1 = gen_reg_rtx (Pmode);
2806 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2807 share the LDM result with other LD model accesses. */
2808 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2810 emit_libcall_block (insn, tmp1, v0, eqv);
2812 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2813 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2814 mips_unspec_address (loc, SYMBOL_DTPREL));
2817 case TLS_MODEL_INITIAL_EXEC:
2818 tp = mips_get_tp ();
2819 tmp1 = gen_reg_rtx (Pmode);
2820 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2821 if (Pmode == DImode)
2822 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2824 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2825 dest = gen_reg_rtx (Pmode);
2826 emit_insn (gen_add3_insn (dest, tmp1, tp));
2829 case TLS_MODEL_LOCAL_EXEC:
2830 tp = mips_get_tp ();
2831 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2832 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2833 mips_unspec_address (loc, SYMBOL_TPREL));
2842 /* If X is not a valid address for mode MODE, force it into a register. */
2845 mips_force_address (rtx x, enum machine_mode mode)
2847 if (!mips_legitimate_address_p (mode, x, false))
2848 x = force_reg (Pmode, x);
2852 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2853 be legitimized in a way that the generic machinery might not expect,
2854 return a new address, otherwise return NULL. MODE is the mode of
2855 the memory being accessed. */
2858 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2859 enum machine_mode mode)
2862 HOST_WIDE_INT offset;
2864 if (mips_tls_symbol_p (x))
2865 return mips_legitimize_tls_address (x);
2867 /* See if the address can split into a high part and a LO_SUM. */
2868 if (mips_split_symbol (NULL, x, mode, &addr))
2869 return mips_force_address (addr, mode);
2871 /* Handle BASE + OFFSET using mips_add_offset. */
2872 mips_split_plus (x, &base, &offset);
2875 if (!mips_valid_base_register_p (base, mode, false))
2876 base = copy_to_mode_reg (Pmode, base);
2877 addr = mips_add_offset (NULL, base, offset);
2878 return mips_force_address (addr, mode);
2884 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2887 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2889 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2890 enum machine_mode mode;
2891 unsigned int i, num_ops;
2894 mode = GET_MODE (dest);
2895 num_ops = mips_build_integer (codes, value);
2897 /* Apply each binary operation to X. Invariant: X is a legitimate
2898 source operand for a SET pattern. */
2899 x = GEN_INT (codes[0].value);
2900 for (i = 1; i < num_ops; i++)
2902 if (!can_create_pseudo_p ())
2904 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2908 x = force_reg (mode, x);
2909 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2912 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2915 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2916 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2920 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2924 /* Split moves of big integers into smaller pieces. */
2925 if (splittable_const_int_operand (src, mode))
2927 mips_move_integer (dest, dest, INTVAL (src));
2931 /* Split moves of symbolic constants into high/low pairs. */
2932 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2934 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2938 /* Generate the appropriate access sequences for TLS symbols. */
2939 if (mips_tls_symbol_p (src))
2941 mips_emit_move (dest, mips_legitimize_tls_address (src));
2945 /* If we have (const (plus symbol offset)), and that expression cannot
2946 be forced into memory, load the symbol first and add in the offset.
2947 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2948 forced into memory, as it usually produces better code. */
2949 split_const (src, &base, &offset);
2950 if (offset != const0_rtx
2951 && (targetm.cannot_force_const_mem (src)
2952 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2954 base = mips_force_temporary (dest, base);
2955 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2959 src = force_const_mem (mode, src);
2961 /* When using explicit relocs, constant pool references are sometimes
2962 not legitimate addresses. */
2963 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2964 mips_emit_move (dest, src);
2967 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2968 sequence that is valid. */
2971 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2973 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2975 mips_emit_move (dest, force_reg (mode, src));
2979 /* We need to deal with constants that would be legitimate
2980 immediate_operands but aren't legitimate move_operands. */
2981 if (CONSTANT_P (src) && !move_operand (src, mode))
2983 mips_legitimize_const_move (mode, dest, src);
2984 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2990 /* Return true if value X in context CONTEXT is a small-data address
2991 that can be rewritten as a LO_SUM. */
2994 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2996 enum mips_symbol_type symbol_type;
2998 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
2999 && !mips_split_p[SYMBOL_GP_RELATIVE]
3000 && mips_symbolic_constant_p (x, context, &symbol_type)
3001 && symbol_type == SYMBOL_GP_RELATIVE);
3004 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3005 containing MEM, or null if none. */
3008 mips_small_data_pattern_1 (rtx *loc, void *data)
3010 enum mips_symbol_context context;
3012 if (GET_CODE (*loc) == LO_SUM)
3017 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3022 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3023 return mips_rewrite_small_data_p (*loc, context);
3026 /* Return true if OP refers to small data symbols directly, not through
3030 mips_small_data_pattern_p (rtx op)
3032 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3035 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3036 DATA is the containing MEM, or null if none. */
3039 mips_rewrite_small_data_1 (rtx *loc, void *data)
3041 enum mips_symbol_context context;
3045 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3049 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3050 if (mips_rewrite_small_data_p (*loc, context))
3051 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3053 if (GET_CODE (*loc) == LO_SUM)
3059 /* Rewrite instruction pattern PATTERN so that it refers to small data
3060 using explicit relocations. */
3063 mips_rewrite_small_data (rtx pattern)
3065 pattern = copy_insn (pattern);
3066 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3070 /* We need a lot of little routines to check the range of MIPS16 immediate
3074 m16_check_op (rtx op, int low, int high, int mask)
3076 return (CONST_INT_P (op)
3077 && IN_RANGE (INTVAL (op), low, high)
3078 && (INTVAL (op) & mask) == 0);
3082 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3084 return m16_check_op (op, 0x1, 0x8, 0);
3088 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3090 return m16_check_op (op, -0x8, 0x7, 0);
3094 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3096 return m16_check_op (op, -0x7, 0x8, 0);
3100 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3102 return m16_check_op (op, -0x10, 0xf, 0);
3106 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3108 return m16_check_op (op, -0xf, 0x10, 0);
3112 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3114 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3118 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3120 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3124 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3126 return m16_check_op (op, -0x80, 0x7f, 0);
3130 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3132 return m16_check_op (op, -0x7f, 0x80, 0);
3136 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3138 return m16_check_op (op, 0x0, 0xff, 0);
3142 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3144 return m16_check_op (op, -0xff, 0x0, 0);
3148 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3150 return m16_check_op (op, -0x1, 0xfe, 0);
3154 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3156 return m16_check_op (op, 0x0, 0xff << 2, 3);
3160 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3162 return m16_check_op (op, -0xff << 2, 0x0, 3);
3166 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3168 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3172 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3174 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3177 /* The cost of loading values from the constant pool. It should be
3178 larger than the cost of any constant we want to synthesize inline. */
3179 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3181 /* Return the cost of X when used as an operand to the MIPS16 instruction
3182 that implements CODE. Return -1 if there is no such instruction, or if
3183 X is not a valid immediate operand for it. */
3186 mips16_constant_cost (int code, HOST_WIDE_INT x)
3193 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3194 other shifts are extended. The shift patterns truncate the shift
3195 count to the right size, so there are no out-of-range values. */
3196 if (IN_RANGE (x, 1, 8))
3198 return COSTS_N_INSNS (1);
3201 if (IN_RANGE (x, -128, 127))
3203 if (SMALL_OPERAND (x))
3204 return COSTS_N_INSNS (1);
3208 /* Like LE, but reject the always-true case. */
3212 /* We add 1 to the immediate and use SLT. */
3215 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3218 if (IN_RANGE (x, 0, 255))
3220 if (SMALL_OPERAND_UNSIGNED (x))
3221 return COSTS_N_INSNS (1);
3226 /* Equality comparisons with 0 are cheap. */
3236 /* Return true if there is a non-MIPS16 instruction that implements CODE
3237 and if that instruction accepts X as an immediate operand. */
3240 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3247 /* All shift counts are truncated to a valid constant. */
3252 /* Likewise rotates, if the target supports rotates at all. */
3258 /* These instructions take 16-bit unsigned immediates. */
3259 return SMALL_OPERAND_UNSIGNED (x);
3264 /* These instructions take 16-bit signed immediates. */
3265 return SMALL_OPERAND (x);
3271 /* The "immediate" forms of these instructions are really
3272 implemented as comparisons with register 0. */
3277 /* Likewise, meaning that the only valid immediate operand is 1. */
3281 /* We add 1 to the immediate and use SLT. */
3282 return SMALL_OPERAND (x + 1);
3285 /* Likewise SLTU, but reject the always-true case. */
3286 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3290 /* The bit position and size are immediate operands. */
3291 return ISA_HAS_EXT_INS;
3294 /* By default assume that $0 can be used for 0. */
3299 /* Return the cost of binary operation X, given that the instruction
3300 sequence for a word-sized or smaller operation has cost SINGLE_COST
3301 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3304 mips_binary_cost (rtx x, int single_cost, int double_cost)
3308 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3313 + rtx_cost (XEXP (x, 0), SET, !optimize_size)
3314 + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size));
3317 /* Return the cost of floating-point multiplications of mode MODE. */
3320 mips_fp_mult_cost (enum machine_mode mode)
3322 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3325 /* Return the cost of floating-point divisions of mode MODE. */
3328 mips_fp_div_cost (enum machine_mode mode)
3330 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3333 /* Return the cost of sign-extending OP to mode MODE, not including the
3334 cost of OP itself. */
3337 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3340 /* Extended loads are as cheap as unextended ones. */
3343 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3344 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3347 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3348 /* We can use SEB or SEH. */
3349 return COSTS_N_INSNS (1);
3351 /* We need to use a shift left and a shift right. */
3352 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3355 /* Return the cost of zero-extending OP to mode MODE, not including the
3356 cost of OP itself. */
3359 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3362 /* Extended loads are as cheap as unextended ones. */
3365 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3366 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3367 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3369 if (GENERATE_MIPS16E)
3370 /* We can use ZEB or ZEH. */
3371 return COSTS_N_INSNS (1);
3374 /* We need to load 0xff or 0xffff into a register and use AND. */
3375 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3377 /* We can use ANDI. */
3378 return COSTS_N_INSNS (1);
3381 /* Implement TARGET_RTX_COSTS. */
3384 mips_rtx_costs (rtx x, int code, int outer_code, int *total,
3387 enum machine_mode mode = GET_MODE (x);
3388 bool float_mode_p = FLOAT_MODE_P (mode);
3392 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3393 appear in the instruction stream, and the cost of a comparison is
3394 really the cost of the branch or scc condition. At the time of
3395 writing, GCC only uses an explicit outer COMPARE code when optabs
3396 is testing whether a constant is expensive enough to force into a
3397 register. We want optabs to pass such constants through the MIPS
3398 expanders instead, so make all constants very cheap here. */
3399 if (outer_code == COMPARE)
3401 gcc_assert (CONSTANT_P (x));
3409 /* Treat *clear_upper32-style ANDs as having zero cost in the
3410 second operand. The cost is entirely in the first operand.
3412 ??? This is needed because we would otherwise try to CSE
3413 the constant operand. Although that's the right thing for
3414 instructions that continue to be a register operation throughout
3415 compilation, it is disastrous for instructions that could
3416 later be converted into a memory operation. */
3418 && outer_code == AND
3419 && UINTVAL (x) == 0xffffffff)
3427 cost = mips16_constant_cost (outer_code, INTVAL (x));
3436 /* When not optimizing for size, we care more about the cost
3437 of hot code, and hot code is often in a loop. If a constant
3438 operand needs to be forced into a register, we will often be
3439 able to hoist the constant load out of the loop, so the load
3440 should not contribute to the cost. */
3442 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3454 if (force_to_mem_operand (x, VOIDmode))
3456 *total = COSTS_N_INSNS (1);
3459 cost = mips_const_insns (x);
3462 /* If the constant is likely to be stored in a GPR, SETs of
3463 single-insn constants are as cheap as register sets; we
3464 never want to CSE them.
3466 Don't reduce the cost of storing a floating-point zero in
3467 FPRs. If we have a zero in an FPR for other reasons, we
3468 can get better cfg-cleanup and delayed-branch results by
3469 using it consistently, rather than using $0 sometimes and
3470 an FPR at other times. Also, moves between floating-point
3471 registers are sometimes cheaper than (D)MTC1 $0. */
3473 && outer_code == SET
3474 && !(float_mode_p && TARGET_HARD_FLOAT))
3476 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3477 want to CSE the constant itself. It is usually better to
3478 have N copies of the last operation in the sequence and one
3479 shared copy of the other operations. (Note that this is
3480 not true for MIPS16 code, where the final operation in the
3481 sequence is often an extended instruction.)
3483 Also, if we have a CONST_INT, we don't know whether it is
3484 for a word or doubleword operation, so we cannot rely on
3485 the result of mips_build_integer. */
3486 else if (!TARGET_MIPS16
3487 && (outer_code == SET || mode == VOIDmode))
3489 *total = COSTS_N_INSNS (cost);
3492 /* The value will need to be fetched from the constant pool. */
3493 *total = CONSTANT_POOL_COST;
3497 /* If the address is legitimate, return the number of
3498 instructions it needs. */
3500 cost = mips_address_insns (addr, mode, true);
3503 *total = COSTS_N_INSNS (cost + 1);
3506 /* Check for a scaled indexed address. */
3507 if (mips_lwxs_address_p (addr))
3509 *total = COSTS_N_INSNS (2);
3512 /* Otherwise use the default handling. */
3516 *total = COSTS_N_INSNS (6);
3520 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3524 /* Check for a *clear_upper32 pattern and treat it like a zero
3525 extension. See the pattern's comment for details. */
3528 && CONST_INT_P (XEXP (x, 1))
3529 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3531 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3532 + rtx_cost (XEXP (x, 0), SET, speed));
3539 /* Double-word operations use two single-word operations. */
3540 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3548 if (CONSTANT_P (XEXP (x, 1)))
3549 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3551 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3556 *total = mips_cost->fp_add;
3558 *total = COSTS_N_INSNS (4);
3562 /* Low-part immediates need an extended MIPS16 instruction. */
3563 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3564 + rtx_cost (XEXP (x, 0), SET, speed));
3579 /* Branch comparisons have VOIDmode, so use the first operand's
3581 mode = GET_MODE (XEXP (x, 0));
3582 if (FLOAT_MODE_P (mode))
3584 *total = mips_cost->fp_add;
3587 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3592 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3593 && TARGET_FUSED_MADD
3594 && !HONOR_NANS (mode)
3595 && !HONOR_SIGNED_ZEROS (mode))
3597 /* See if we can use NMADD or NMSUB. See mips.md for the
3598 associated patterns. */
3599 rtx op0 = XEXP (x, 0);
3600 rtx op1 = XEXP (x, 1);
3601 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3603 *total = (mips_fp_mult_cost (mode)
3604 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3605 + rtx_cost (XEXP (op0, 1), SET, speed)
3606 + rtx_cost (op1, SET, speed));
3609 if (GET_CODE (op1) == MULT)
3611 *total = (mips_fp_mult_cost (mode)
3612 + rtx_cost (op0, SET, speed)
3613 + rtx_cost (XEXP (op1, 0), SET, speed)
3614 + rtx_cost (XEXP (op1, 1), SET, speed));
3623 /* If this is part of a MADD or MSUB, treat the PLUS as
3626 && TARGET_FUSED_MADD
3627 && GET_CODE (XEXP (x, 0)) == MULT)
3630 *total = mips_cost->fp_add;
3634 /* Double-word operations require three single-word operations and
3635 an SLTU. The MIPS16 version then needs to move the result of
3636 the SLTU from $24 to a MIPS16 register. */
3637 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3638 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3643 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3644 && TARGET_FUSED_MADD
3645 && !HONOR_NANS (mode)
3646 && HONOR_SIGNED_ZEROS (mode))
3648 /* See if we can use NMADD or NMSUB. See mips.md for the
3649 associated patterns. */
3650 rtx op = XEXP (x, 0);
3651 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3652 && GET_CODE (XEXP (op, 0)) == MULT)
3654 *total = (mips_fp_mult_cost (mode)
3655 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3656 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3657 + rtx_cost (XEXP (op, 1), SET, speed));
3663 *total = mips_cost->fp_add;
3665 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3670 *total = mips_fp_mult_cost (mode);
3671 else if (mode == DImode && !TARGET_64BIT)
3672 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3673 where the mulsidi3 always includes an MFHI and an MFLO. */
3674 *total = (optimize_size
3675 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3676 : mips_cost->int_mult_si * 3 + 6);
3677 else if (optimize_size)
3678 *total = (ISA_HAS_MUL3 ? 1 : 2);
3679 else if (mode == DImode)
3680 *total = mips_cost->int_mult_di;
3682 *total = mips_cost->int_mult_si;
3686 /* Check for a reciprocal. */
3689 && flag_unsafe_math_optimizations
3690 && XEXP (x, 0) == CONST1_RTX (mode))
3692 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3693 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3694 division as being free. */
3695 *total = rtx_cost (XEXP (x, 1), SET, speed);
3697 *total = (mips_fp_div_cost (mode)
3698 + rtx_cost (XEXP (x, 1), SET, speed));
3707 *total = mips_fp_div_cost (mode);
3716 /* It is our responsibility to make division by a power of 2
3717 as cheap as 2 register additions if we want the division
3718 expanders to be used for such operations; see the setting
3719 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3720 should always produce shorter code than using
3721 expand_sdiv2_pow2. */
3723 && CONST_INT_P (XEXP (x, 1))
3724 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3726 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3729 *total = COSTS_N_INSNS (mips_idiv_insns ());
3731 else if (mode == DImode)
3732 *total = mips_cost->int_div_di;
3734 *total = mips_cost->int_div_si;
3738 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3742 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3746 case UNSIGNED_FLOAT:
3749 case FLOAT_TRUNCATE:
3750 *total = mips_cost->fp_add;
3758 /* Implement TARGET_ADDRESS_COST. */
3761 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3763 return mips_address_insns (addr, SImode, false);
3766 /* Information about a single instruction in a multi-instruction
3768 struct mips_multi_member {
3769 /* True if this is a label, false if it is code. */
3772 /* The output_asm_insn format of the instruction. */
3775 /* The operands to the instruction. */
3776 rtx operands[MAX_RECOG_OPERANDS];
3778 typedef struct mips_multi_member mips_multi_member;
3780 /* Vector definitions for the above. */
3781 DEF_VEC_O(mips_multi_member);
3782 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3784 /* The instructions that make up the current multi-insn sequence. */
3785 static VEC (mips_multi_member, heap) *mips_multi_members;
3787 /* How many instructions (as opposed to labels) are in the current
3788 multi-insn sequence. */
3789 static unsigned int mips_multi_num_insns;
3791 /* Start a new multi-insn sequence. */
3794 mips_multi_start (void)
3796 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3797 mips_multi_num_insns = 0;
3800 /* Add a new, uninitialized member to the current multi-insn sequence. */
3802 static struct mips_multi_member *
3803 mips_multi_add (void)
3805 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3808 /* Add a normal insn with the given asm format to the current multi-insn
3809 sequence. The other arguments are a null-terminated list of operands. */
3812 mips_multi_add_insn (const char *format, ...)
3814 struct mips_multi_member *member;
3819 member = mips_multi_add ();
3820 member->is_label_p = false;
3821 member->format = format;
3822 va_start (ap, format);
3824 while ((op = va_arg (ap, rtx)))
3825 member->operands[i++] = op;
3827 mips_multi_num_insns++;
3830 /* Add the given label definition to the current multi-insn sequence.
3831 The definition should include the colon. */
3834 mips_multi_add_label (const char *label)
3836 struct mips_multi_member *member;
3838 member = mips_multi_add ();
3839 member->is_label_p = true;
3840 member->format = label;
3843 /* Return the index of the last member of the current multi-insn sequence. */
3846 mips_multi_last_index (void)
3848 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3851 /* Add a copy of an existing instruction to the current multi-insn
3852 sequence. I is the index of the instruction that should be copied. */
3855 mips_multi_copy_insn (unsigned int i)
3857 struct mips_multi_member *member;
3859 member = mips_multi_add ();
3860 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3862 gcc_assert (!member->is_label_p);
3865 /* Change the operand of an existing instruction in the current
3866 multi-insn sequence. I is the index of the instruction,
3867 OP is the index of the operand, and X is the new value. */
3870 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3872 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3875 /* Write out the asm code for the current multi-insn sequence. */
3878 mips_multi_write (void)
3880 struct mips_multi_member *member;
3884 VEC_iterate (mips_multi_member, mips_multi_members, i, member);
3886 if (member->is_label_p)
3887 fprintf (asm_out_file, "%s\n", member->format);
3889 output_asm_insn (member->format, member->operands);
3892 /* Return one word of double-word value OP, taking into account the fixed
3893 endianness of certain registers. HIGH_P is true to select the high part,
3894 false to select the low part. */
3897 mips_subword (rtx op, bool high_p)
3899 unsigned int byte, offset;
3900 enum machine_mode mode;
3902 mode = GET_MODE (op);
3903 if (mode == VOIDmode)
3904 mode = TARGET_64BIT ? TImode : DImode;
3906 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3907 byte = UNITS_PER_WORD;
3911 if (FP_REG_RTX_P (op))
3913 /* Paired FPRs are always ordered little-endian. */
3914 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3915 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3919 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3921 return simplify_gen_subreg (word_mode, op, mode, byte);
3924 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3927 mips_split_64bit_move_p (rtx dest, rtx src)
3932 /* FPR-to-FPR moves can be done in a single instruction, if they're
3934 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3937 /* Check for floating-point loads and stores. */
3938 if (ISA_HAS_LDC1_SDC1)
3940 if (FP_REG_RTX_P (dest) && MEM_P (src))
3942 if (FP_REG_RTX_P (src) && MEM_P (dest))
3948 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3949 this function handles 64-bit moves for which mips_split_64bit_move_p
3950 holds. For 64-bit targets, this function handles 128-bit moves. */
3953 mips_split_doubleword_move (rtx dest, rtx src)
3957 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3959 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3960 emit_insn (gen_move_doubleword_fprdi (dest, src));
3961 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3962 emit_insn (gen_move_doubleword_fprdf (dest, src));
3963 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3964 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3965 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3966 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3967 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3968 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3969 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3970 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3971 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3972 emit_insn (gen_move_doubleword_fprtf (dest, src));
3976 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3978 low_dest = mips_subword (dest, false);
3979 mips_emit_move (low_dest, mips_subword (src, false));
3981 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3983 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3985 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3987 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3989 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3991 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3995 /* The operation can be split into two normal moves. Decide in
3996 which order to do them. */
3997 low_dest = mips_subword (dest, false);
3998 if (REG_P (low_dest)
3999 && reg_overlap_mentioned_p (low_dest, src))
4001 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4002 mips_emit_move (low_dest, mips_subword (src, false));
4006 mips_emit_move (low_dest, mips_subword (src, false));
4007 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4012 /* Return the appropriate instructions to move SRC into DEST. Assume
4013 that SRC is operand 1 and DEST is operand 0. */
4016 mips_output_move (rtx dest, rtx src)
4018 enum rtx_code dest_code, src_code;
4019 enum machine_mode mode;
4020 enum mips_symbol_type symbol_type;
4023 dest_code = GET_CODE (dest);
4024 src_code = GET_CODE (src);
4025 mode = GET_MODE (dest);
4026 dbl_p = (GET_MODE_SIZE (mode) == 8);
4028 if (dbl_p && mips_split_64bit_move_p (dest, src))
4031 if ((src_code == REG && GP_REG_P (REGNO (src)))
4032 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4034 if (dest_code == REG)
4036 if (GP_REG_P (REGNO (dest)))
4037 return "move\t%0,%z1";
4039 /* Moves to HI are handled by special .md insns. */
4040 if (REGNO (dest) == LO_REGNUM)
4043 if (DSP_ACC_REG_P (REGNO (dest)))
4045 static char retval[] = "mt__\t%z1,%q0";
4047 retval[2] = reg_names[REGNO (dest)][4];
4048 retval[3] = reg_names[REGNO (dest)][5];
4052 if (FP_REG_P (REGNO (dest)))
4053 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4055 if (ALL_COP_REG_P (REGNO (dest)))
4057 static char retval[] = "dmtc_\t%z1,%0";
4059 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4060 return dbl_p ? retval : retval + 1;
4063 if (dest_code == MEM)
4064 switch (GET_MODE_SIZE (mode))
4066 case 1: return "sb\t%z1,%0";
4067 case 2: return "sh\t%z1,%0";
4068 case 4: return "sw\t%z1,%0";
4069 case 8: return "sd\t%z1,%0";
4072 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4074 if (src_code == REG)
4076 /* Moves from HI are handled by special .md insns. */
4077 if (REGNO (src) == LO_REGNUM)
4079 /* When generating VR4120 or VR4130 code, we use MACC and
4080 DMACC instead of MFLO. This avoids both the normal
4081 MIPS III HI/LO hazards and the errata related to
4084 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4088 if (DSP_ACC_REG_P (REGNO (src)))
4090 static char retval[] = "mf__\t%0,%q1";
4092 retval[2] = reg_names[REGNO (src)][4];
4093 retval[3] = reg_names[REGNO (src)][5];
4097 if (FP_REG_P (REGNO (src)))
4098 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4100 if (ALL_COP_REG_P (REGNO (src)))
4102 static char retval[] = "dmfc_\t%0,%1";
4104 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4105 return dbl_p ? retval : retval + 1;
4108 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4109 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4112 if (src_code == MEM)
4113 switch (GET_MODE_SIZE (mode))
4115 case 1: return "lbu\t%0,%1";
4116 case 2: return "lhu\t%0,%1";
4117 case 4: return "lw\t%0,%1";
4118 case 8: return "ld\t%0,%1";
4121 if (src_code == CONST_INT)
4123 /* Don't use the X format for the operand itself, because that
4124 will give out-of-range numbers for 64-bit hosts and 32-bit
4127 return "li\t%0,%1\t\t\t# %X1";
4129 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4132 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4136 if (src_code == HIGH)
4137 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4139 if (CONST_GP_P (src))
4140 return "move\t%0,%1";
4142 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4143 && mips_lo_relocs[symbol_type] != 0)
4145 /* A signed 16-bit constant formed by applying a relocation
4146 operator to a symbolic address. */
4147 gcc_assert (!mips_split_p[symbol_type]);
4148 return "li\t%0,%R1";
4151 if (symbolic_operand (src, VOIDmode))
4153 gcc_assert (TARGET_MIPS16
4154 ? TARGET_MIPS16_TEXT_LOADS
4155 : !TARGET_EXPLICIT_RELOCS);
4156 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4159 if (src_code == REG && FP_REG_P (REGNO (src)))
4161 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4163 if (GET_MODE (dest) == V2SFmode)
4164 return "mov.ps\t%0,%1";
4166 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4169 if (dest_code == MEM)
4170 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4172 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4174 if (src_code == MEM)
4175 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4177 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4179 static char retval[] = "l_c_\t%0,%1";
4181 retval[1] = (dbl_p ? 'd' : 'w');
4182 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4185 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4187 static char retval[] = "s_c_\t%1,%0";
4189 retval[1] = (dbl_p ? 'd' : 'w');
4190 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4196 /* Return true if CMP1 is a suitable second operand for integer ordering
4197 test CODE. See also the *sCC patterns in mips.md. */
4200 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4206 return reg_or_0_operand (cmp1, VOIDmode);
4210 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4214 return arith_operand (cmp1, VOIDmode);
4217 return sle_operand (cmp1, VOIDmode);
4220 return sleu_operand (cmp1, VOIDmode);
4227 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4228 integer ordering test *CODE, or if an equivalent combination can
4229 be formed by adjusting *CODE and *CMP1. When returning true, update
4230 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4234 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4235 enum machine_mode mode)
4237 HOST_WIDE_INT plus_one;
4239 if (mips_int_order_operand_ok_p (*code, *cmp1))
4242 if (CONST_INT_P (*cmp1))
4246 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4247 if (INTVAL (*cmp1) < plus_one)
4250 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4256 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4260 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4271 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4272 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4273 is nonnull, it's OK to set TARGET to the inverse of the result and
4274 flip *INVERT_PTR instead. */
4277 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4278 rtx target, rtx cmp0, rtx cmp1)
4280 enum machine_mode mode;
4282 /* First see if there is a MIPS instruction that can do this operation.
4283 If not, try doing the same for the inverse operation. If that also
4284 fails, force CMP1 into a register and try again. */
4285 mode = GET_MODE (cmp0);
4286 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4287 mips_emit_binary (code, target, cmp0, cmp1);
4290 enum rtx_code inv_code = reverse_condition (code);
4291 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4293 cmp1 = force_reg (mode, cmp1);
4294 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4296 else if (invert_ptr == 0)
4300 inv_target = mips_force_binary (GET_MODE (target),
4301 inv_code, cmp0, cmp1);
4302 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4306 *invert_ptr = !*invert_ptr;
4307 mips_emit_binary (inv_code, target, cmp0, cmp1);
4312 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4313 The register will have the same mode as CMP0. */
4316 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4318 if (cmp1 == const0_rtx)
4321 if (uns_arith_operand (cmp1, VOIDmode))
4322 return expand_binop (GET_MODE (cmp0), xor_optab,
4323 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4325 return expand_binop (GET_MODE (cmp0), sub_optab,
4326 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4329 /* Convert *CODE into a code that can be used in a floating-point
4330 scc instruction (C.cond.fmt). Return true if the values of
4331 the condition code registers will be inverted, with 0 indicating
4332 that the condition holds. */
4335 mips_reversed_fp_cond (enum rtx_code *code)
4342 *code = reverse_condition_maybe_unordered (*code);
4350 /* Convert a comparison into something that can be used in a branch or
4351 conditional move. On entry, *OP0 and *OP1 are the values being
4352 compared and *CODE is the code used to compare them.
4354 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4355 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4356 otherwise any standard branch condition can be used. The standard branch
4359 - EQ or NE between two registers.
4360 - any comparison between a register and zero. */
4363 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4368 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4370 if (!need_eq_ne_p && *op1 == const0_rtx)
4372 else if (*code == EQ || *code == NE)
4376 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4380 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4384 /* The comparison needs a separate scc instruction. Store the
4385 result of the scc in *OP0 and compare it against zero. */
4386 bool invert = false;
4387 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4388 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4389 *code = (invert ? EQ : NE);
4393 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4395 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4396 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4402 enum rtx_code cmp_code;
4404 /* Floating-point tests use a separate C.cond.fmt comparison to
4405 set a condition code register. The branch or conditional move
4406 will then compare that register against zero.
4408 Set CMP_CODE to the code of the comparison instruction and
4409 *CODE to the code that the branch or move should use. */
4411 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4413 ? gen_reg_rtx (CCmode)
4414 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4416 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4420 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4421 and OPERAND[3]. Store the result in OPERANDS[0].
4423 On 64-bit targets, the mode of the comparison and target will always be
4424 SImode, thus possibly narrower than that of the comparison's operands. */
4427 mips_expand_scc (rtx operands[])
4429 rtx target = operands[0];
4430 enum rtx_code code = GET_CODE (operands[1]);
4431 rtx op0 = operands[2];
4432 rtx op1 = operands[3];
4434 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4436 if (code == EQ || code == NE)
4439 && reg_imm10_operand (op1, GET_MODE (op1)))
4440 mips_emit_binary (code, target, op0, op1);
4443 rtx zie = mips_zero_if_equal (op0, op1);
4444 mips_emit_binary (code, target, zie, const0_rtx);
4448 mips_emit_int_order_test (code, 0, target, op0, op1);
4451 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4452 CODE and jump to OPERANDS[3] if the condition holds. */
4455 mips_expand_conditional_branch (rtx *operands)
4457 enum rtx_code code = GET_CODE (operands[0]);
4458 rtx op0 = operands[1];
4459 rtx op1 = operands[2];
4462 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4463 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4464 emit_jump_insn (gen_condjump (condition, operands[3]));
4469 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4470 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4473 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4474 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4479 reversed_p = mips_reversed_fp_cond (&cond);
4480 cmp_result = gen_reg_rtx (CCV2mode);
4481 emit_insn (gen_scc_ps (cmp_result,
4482 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4484 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4487 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4491 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4492 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4495 mips_expand_conditional_move (rtx *operands)
4498 enum rtx_code code = GET_CODE (operands[1]);
4499 rtx op0 = XEXP (operands[1], 0);
4500 rtx op1 = XEXP (operands[1], 1);
4502 mips_emit_compare (&code, &op0, &op1, true);
4503 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4504 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4505 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4506 operands[2], operands[3])));
4509 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4512 mips_expand_conditional_trap (rtx comparison)
4515 enum machine_mode mode;
4518 /* MIPS conditional trap instructions don't have GT or LE flavors,
4519 so we must swap the operands and convert to LT and GE respectively. */
4520 code = GET_CODE (comparison);
4527 code = swap_condition (code);
4528 op0 = XEXP (comparison, 1);
4529 op1 = XEXP (comparison, 0);
4533 op0 = XEXP (comparison, 0);
4534 op1 = XEXP (comparison, 1);
4538 mode = GET_MODE (XEXP (comparison, 0));
4539 op0 = force_reg (mode, op0);
4540 if (!arith_operand (op1, mode))
4541 op1 = force_reg (mode, op1);
4543 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4544 gen_rtx_fmt_ee (code, mode, op0, op1),
4548 /* Initialize *CUM for a call to a function of type FNTYPE. */
4551 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4553 memset (cum, 0, sizeof (*cum));
4554 cum->prototype = (fntype && prototype_p (fntype));
4555 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4558 /* Fill INFO with information about a single argument. CUM is the
4559 cumulative state for earlier arguments. MODE is the mode of this
4560 argument and TYPE is its type (if known). NAMED is true if this
4561 is a named (fixed) argument rather than a variable one. */
4564 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4565 enum machine_mode mode, tree type, int named)
4567 bool doubleword_aligned_p;
4568 unsigned int num_bytes, num_words, max_regs;
4570 /* Work out the size of the argument. */
4571 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4572 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4574 /* Decide whether it should go in a floating-point register, assuming
4575 one is free. Later code checks for availability.
4577 The checks against UNITS_PER_FPVALUE handle the soft-float and
4578 single-float cases. */
4582 /* The EABI conventions have traditionally been defined in terms
4583 of TYPE_MODE, regardless of the actual type. */
4584 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4585 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4586 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4591 /* Only leading floating-point scalars are passed in
4592 floating-point registers. We also handle vector floats the same
4593 say, which is OK because they are not covered by the standard ABI. */
4594 info->fpr_p = (!cum->gp_reg_found
4595 && cum->arg_number < 2
4597 || SCALAR_FLOAT_TYPE_P (type)
4598 || VECTOR_FLOAT_TYPE_P (type))
4599 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4600 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4601 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4606 /* Scalar, complex and vector floating-point types are passed in
4607 floating-point registers, as long as this is a named rather
4608 than a variable argument. */
4609 info->fpr_p = (named
4610 && (type == 0 || FLOAT_TYPE_P (type))
4611 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4612 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4613 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4614 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4616 /* ??? According to the ABI documentation, the real and imaginary
4617 parts of complex floats should be passed in individual registers.
4618 The real and imaginary parts of stack arguments are supposed
4619 to be contiguous and there should be an extra word of padding
4622 This has two problems. First, it makes it impossible to use a
4623 single "void *" va_list type, since register and stack arguments
4624 are passed differently. (At the time of writing, MIPSpro cannot
4625 handle complex float varargs correctly.) Second, it's unclear
4626 what should happen when there is only one register free.
4628 For now, we assume that named complex floats should go into FPRs
4629 if there are two FPRs free, otherwise they should be passed in the
4630 same way as a struct containing two floats. */
4632 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4633 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4635 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4636 info->fpr_p = false;
4646 /* See whether the argument has doubleword alignment. */
4647 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4649 /* Set REG_OFFSET to the register count we're interested in.
4650 The EABI allocates the floating-point registers separately,
4651 but the other ABIs allocate them like integer registers. */
4652 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4656 /* Advance to an even register if the argument is doubleword-aligned. */
4657 if (doubleword_aligned_p)
4658 info->reg_offset += info->reg_offset & 1;
4660 /* Work out the offset of a stack argument. */
4661 info->stack_offset = cum->stack_words;
4662 if (doubleword_aligned_p)
4663 info->stack_offset += info->stack_offset & 1;
4665 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4667 /* Partition the argument between registers and stack. */
4668 info->reg_words = MIN (num_words, max_regs);
4669 info->stack_words = num_words - info->reg_words;
4672 /* INFO describes a register argument that has the normal format for the
4673 argument's mode. Return the register it uses, assuming that FPRs are
4674 available if HARD_FLOAT_P. */
4677 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4679 if (!info->fpr_p || !hard_float_p)
4680 return GP_ARG_FIRST + info->reg_offset;
4681 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4682 /* In o32, the second argument is always passed in $f14
4683 for TARGET_DOUBLE_FLOAT, regardless of whether the
4684 first argument was a word or doubleword. */
4685 return FP_ARG_FIRST + 2;
4687 return FP_ARG_FIRST + info->reg_offset;
4690 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4693 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4695 return !TARGET_OLDABI;
4698 /* Implement FUNCTION_ARG. */
4701 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4702 tree type, int named)
4704 struct mips_arg_info info;
4706 /* We will be called with a mode of VOIDmode after the last argument
4707 has been seen. Whatever we return will be passed to the call expander.
4708 If we need a MIPS16 fp_code, return a REG with the code stored as
4710 if (mode == VOIDmode)
4712 if (TARGET_MIPS16 && cum->fp_code != 0)
4713 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4718 mips_get_arg_info (&info, cum, mode, type, named);
4720 /* Return straight away if the whole argument is passed on the stack. */
4721 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4724 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4725 contains a double in its entirety, then that 64-bit chunk is passed
4726 in a floating-point register. */
4728 && TARGET_HARD_FLOAT
4731 && TREE_CODE (type) == RECORD_TYPE
4732 && TYPE_SIZE_UNIT (type)
4733 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4737 /* First check to see if there is any such field. */
4738 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4739 if (TREE_CODE (field) == FIELD_DECL
4740 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4741 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4742 && host_integerp (bit_position (field), 0)
4743 && int_bit_position (field) % BITS_PER_WORD == 0)
4748 /* Now handle the special case by returning a PARALLEL
4749 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4750 chunks are passed in registers. */
4752 HOST_WIDE_INT bitpos;
4755 /* assign_parms checks the mode of ENTRY_PARM, so we must
4756 use the actual mode here. */
4757 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4760 field = TYPE_FIELDS (type);
4761 for (i = 0; i < info.reg_words; i++)
4765 for (; field; field = TREE_CHAIN (field))
4766 if (TREE_CODE (field) == FIELD_DECL
4767 && int_bit_position (field) >= bitpos)
4771 && int_bit_position (field) == bitpos
4772 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4773 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4774 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4776 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4779 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4780 GEN_INT (bitpos / BITS_PER_UNIT));
4782 bitpos += BITS_PER_WORD;
4788 /* Handle the n32/n64 conventions for passing complex floating-point
4789 arguments in FPR pairs. The real part goes in the lower register
4790 and the imaginary part goes in the upper register. */
4793 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4796 enum machine_mode inner;
4799 inner = GET_MODE_INNER (mode);
4800 regno = FP_ARG_FIRST + info.reg_offset;
4801 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4803 /* Real part in registers, imaginary part on stack. */
4804 gcc_assert (info.stack_words == info.reg_words);
4805 return gen_rtx_REG (inner, regno);
4809 gcc_assert (info.stack_words == 0);
4810 real = gen_rtx_EXPR_LIST (VOIDmode,
4811 gen_rtx_REG (inner, regno),
4813 imag = gen_rtx_EXPR_LIST (VOIDmode,
4815 regno + info.reg_words / 2),
4816 GEN_INT (GET_MODE_SIZE (inner)));
4817 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4821 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4824 /* Implement FUNCTION_ARG_ADVANCE. */
4827 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4828 tree type, int named)
4830 struct mips_arg_info info;
4832 mips_get_arg_info (&info, cum, mode, type, named);
4835 cum->gp_reg_found = true;
4837 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4838 an explanation of what this code does. It assumes that we're using
4839 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4841 if (cum->arg_number < 2 && info.fpr_p)
4842 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4844 /* Advance the register count. This has the effect of setting
4845 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4846 argument required us to skip the final GPR and pass the whole
4847 argument on the stack. */
4848 if (mips_abi != ABI_EABI || !info.fpr_p)
4849 cum->num_gprs = info.reg_offset + info.reg_words;
4850 else if (info.reg_words > 0)
4851 cum->num_fprs += MAX_FPRS_PER_FMT;
4853 /* Advance the stack word count. */
4854 if (info.stack_words > 0)
4855 cum->stack_words = info.stack_offset + info.stack_words;
4860 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4863 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4864 enum machine_mode mode, tree type, bool named)
4866 struct mips_arg_info info;
4868 mips_get_arg_info (&info, cum, mode, type, named);
4869 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4872 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4873 PARM_BOUNDARY bits of alignment, but will be given anything up
4874 to STACK_BOUNDARY bits if the type requires it. */
4877 mips_function_arg_boundary (enum machine_mode mode, tree type)
4879 unsigned int alignment;
4881 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4882 if (alignment < PARM_BOUNDARY)
4883 alignment = PARM_BOUNDARY;
4884 if (alignment > STACK_BOUNDARY)
4885 alignment = STACK_BOUNDARY;
4889 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4890 upward rather than downward. In other words, return true if the
4891 first byte of the stack slot has useful data, false if the last
4895 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4897 /* On little-endian targets, the first byte of every stack argument
4898 is passed in the first byte of the stack slot. */
4899 if (!BYTES_BIG_ENDIAN)
4902 /* Otherwise, integral types are padded downward: the last byte of a
4903 stack argument is passed in the last byte of the stack slot. */
4905 ? (INTEGRAL_TYPE_P (type)
4906 || POINTER_TYPE_P (type)
4907 || FIXED_POINT_TYPE_P (type))
4908 : (SCALAR_INT_MODE_P (mode)
4909 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4912 /* Big-endian o64 pads floating-point arguments downward. */
4913 if (mips_abi == ABI_O64)
4914 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4917 /* Other types are padded upward for o32, o64, n32 and n64. */
4918 if (mips_abi != ABI_EABI)
4921 /* Arguments smaller than a stack slot are padded downward. */
4922 if (mode != BLKmode)
4923 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4925 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4928 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4929 if the least significant byte of the register has useful data. Return
4930 the opposite if the most significant byte does. */
4933 mips_pad_reg_upward (enum machine_mode mode, tree type)
4935 /* No shifting is required for floating-point arguments. */
4936 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4937 return !BYTES_BIG_ENDIAN;
4939 /* Otherwise, apply the same padding to register arguments as we do
4940 to stack arguments. */
4941 return mips_pad_arg_upward (mode, type);
4944 /* Return nonzero when an argument must be passed by reference. */
4947 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4948 enum machine_mode mode, const_tree type,
4949 bool named ATTRIBUTE_UNUSED)
4951 if (mips_abi == ABI_EABI)
4955 /* ??? How should SCmode be handled? */
4956 if (mode == DImode || mode == DFmode
4957 || mode == DQmode || mode == UDQmode
4958 || mode == DAmode || mode == UDAmode)
4961 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4962 return size == -1 || size > UNITS_PER_WORD;
4966 /* If we have a variable-sized parameter, we have no choice. */
4967 return targetm.calls.must_pass_in_stack (mode, type);
4971 /* Implement TARGET_CALLEE_COPIES. */
4974 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4975 enum machine_mode mode ATTRIBUTE_UNUSED,
4976 const_tree type ATTRIBUTE_UNUSED, bool named)
4978 return mips_abi == ABI_EABI && named;
4981 /* See whether VALTYPE is a record whose fields should be returned in
4982 floating-point registers. If so, return the number of fields and
4983 list them in FIELDS (which should have two elements). Return 0
4986 For n32 & n64, a structure with one or two fields is returned in
4987 floating-point registers as long as every field has a floating-point
4991 mips_fpr_return_fields (const_tree valtype, tree *fields)
4999 if (TREE_CODE (valtype) != RECORD_TYPE)
5003 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
5005 if (TREE_CODE (field) != FIELD_DECL)
5008 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5014 fields[i++] = field;
5019 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5020 a value in the most significant part of $2/$3 if:
5022 - the target is big-endian;
5024 - the value has a structure or union type (we generalize this to
5025 cover aggregates from other languages too); and
5027 - the structure is not returned in floating-point registers. */
5030 mips_return_in_msb (const_tree valtype)
5034 return (TARGET_NEWABI
5035 && TARGET_BIG_ENDIAN
5036 && AGGREGATE_TYPE_P (valtype)
5037 && mips_fpr_return_fields (valtype, fields) == 0);
5040 /* Return true if the function return value MODE will get returned in a
5041 floating-point register. */
5044 mips_return_mode_in_fpr_p (enum machine_mode mode)
5046 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5047 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5048 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5049 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5052 /* Return the representation of an FPR return register when the
5053 value being returned in FP_RETURN has mode VALUE_MODE and the
5054 return type itself has mode TYPE_MODE. On NewABI targets,
5055 the two modes may be different for structures like:
5057 struct __attribute__((packed)) foo { float f; }
5059 where we return the SFmode value of "f" in FP_RETURN, but where
5060 the structure itself has mode BLKmode. */
5063 mips_return_fpr_single (enum machine_mode type_mode,
5064 enum machine_mode value_mode)
5068 x = gen_rtx_REG (value_mode, FP_RETURN);
5069 if (type_mode != value_mode)
5071 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5072 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5077 /* Return a composite value in a pair of floating-point registers.
5078 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5079 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5082 For n32 & n64, $f0 always holds the first value and $f2 the second.
5083 Otherwise the values are packed together as closely as possible. */
5086 mips_return_fpr_pair (enum machine_mode mode,
5087 enum machine_mode mode1, HOST_WIDE_INT offset1,
5088 enum machine_mode mode2, HOST_WIDE_INT offset2)
5092 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5093 return gen_rtx_PARALLEL
5096 gen_rtx_EXPR_LIST (VOIDmode,
5097 gen_rtx_REG (mode1, FP_RETURN),
5099 gen_rtx_EXPR_LIST (VOIDmode,
5100 gen_rtx_REG (mode2, FP_RETURN + inc),
5101 GEN_INT (offset2))));
5105 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5106 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5107 VALTYPE is null and MODE is the mode of the return value. */
5110 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5117 mode = TYPE_MODE (valtype);
5118 unsigned_p = TYPE_UNSIGNED (valtype);
5120 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5121 return values, promote the mode here too. */
5122 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5124 /* Handle structures whose fields are returned in $f0/$f2. */
5125 switch (mips_fpr_return_fields (valtype, fields))
5128 return mips_return_fpr_single (mode,
5129 TYPE_MODE (TREE_TYPE (fields[0])));
5132 return mips_return_fpr_pair (mode,
5133 TYPE_MODE (TREE_TYPE (fields[0])),
5134 int_byte_position (fields[0]),
5135 TYPE_MODE (TREE_TYPE (fields[1])),
5136 int_byte_position (fields[1]));
5139 /* If a value is passed in the most significant part of a register, see
5140 whether we have to round the mode up to a whole number of words. */
5141 if (mips_return_in_msb (valtype))
5143 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5144 if (size % UNITS_PER_WORD != 0)
5146 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5147 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5151 /* For EABI, the class of return register depends entirely on MODE.
5152 For example, "struct { some_type x; }" and "union { some_type x; }"
5153 are returned in the same way as a bare "some_type" would be.
5154 Other ABIs only use FPRs for scalar, complex or vector types. */
5155 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5156 return gen_rtx_REG (mode, GP_RETURN);
5161 /* Handle long doubles for n32 & n64. */
5163 return mips_return_fpr_pair (mode,
5165 DImode, GET_MODE_SIZE (mode) / 2);
5167 if (mips_return_mode_in_fpr_p (mode))
5169 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5170 return mips_return_fpr_pair (mode,
5171 GET_MODE_INNER (mode), 0,
5172 GET_MODE_INNER (mode),
5173 GET_MODE_SIZE (mode) / 2);
5175 return gen_rtx_REG (mode, FP_RETURN);
5179 return gen_rtx_REG (mode, GP_RETURN);
5182 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5183 all BLKmode objects are returned in memory. Under the n32, n64
5184 and embedded ABIs, small structures are returned in a register.
5185 Objects with varying size must still be returned in memory, of
5189 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5191 return (TARGET_OLDABI
5192 ? TYPE_MODE (type) == BLKmode
5193 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5196 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5199 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5200 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5203 CUMULATIVE_ARGS local_cum;
5204 int gp_saved, fp_saved;
5206 /* The caller has advanced CUM up to, but not beyond, the last named
5207 argument. Advance a local copy of CUM past the last "real" named
5208 argument, to find out how many registers are left over. */
5210 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5212 /* Found out how many registers we need to save. */
5213 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5214 fp_saved = (EABI_FLOAT_VARARGS_P
5215 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5224 ptr = plus_constant (virtual_incoming_args_rtx,
5225 REG_PARM_STACK_SPACE (cfun->decl)
5226 - gp_saved * UNITS_PER_WORD);
5227 mem = gen_frame_mem (BLKmode, ptr);
5228 set_mem_alias_set (mem, get_varargs_alias_set ());
5230 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5235 /* We can't use move_block_from_reg, because it will use
5237 enum machine_mode mode;
5240 /* Set OFF to the offset from virtual_incoming_args_rtx of
5241 the first float register. The FP save area lies below
5242 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5243 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5244 off -= fp_saved * UNITS_PER_FPREG;
5246 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5248 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5249 i += MAX_FPRS_PER_FMT)
5253 ptr = plus_constant (virtual_incoming_args_rtx, off);
5254 mem = gen_frame_mem (mode, ptr);
5255 set_mem_alias_set (mem, get_varargs_alias_set ());
5256 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5257 off += UNITS_PER_HWFPVALUE;
5261 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5262 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5263 + fp_saved * UNITS_PER_FPREG);
5266 /* Implement TARGET_BUILTIN_VA_LIST. */
5269 mips_build_builtin_va_list (void)
5271 if (EABI_FLOAT_VARARGS_P)
5273 /* We keep 3 pointers, and two offsets.
5275 Two pointers are to the overflow area, which starts at the CFA.
5276 One of these is constant, for addressing into the GPR save area
5277 below it. The other is advanced up the stack through the
5280 The third pointer is to the bottom of the GPR save area.
5281 Since the FPR save area is just below it, we can address
5282 FPR slots off this pointer.
5284 We also keep two one-byte offsets, which are to be subtracted
5285 from the constant pointers to yield addresses in the GPR and
5286 FPR save areas. These are downcounted as float or non-float
5287 arguments are used, and when they get to zero, the argument
5288 must be obtained from the overflow region. */
5289 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5292 record = lang_hooks.types.make_type (RECORD_TYPE);
5294 f_ovfl = build_decl (BUILTINS_LOCATION,
5295 FIELD_DECL, get_identifier ("__overflow_argptr"),
5297 f_gtop = build_decl (BUILTINS_LOCATION,
5298 FIELD_DECL, get_identifier ("__gpr_top"),
5300 f_ftop = build_decl (BUILTINS_LOCATION,
5301 FIELD_DECL, get_identifier ("__fpr_top"),
5303 f_goff = build_decl (BUILTINS_LOCATION,
5304 FIELD_DECL, get_identifier ("__gpr_offset"),
5305 unsigned_char_type_node);
5306 f_foff = build_decl (BUILTINS_LOCATION,
5307 FIELD_DECL, get_identifier ("__fpr_offset"),
5308 unsigned_char_type_node);
5309 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5310 warn on every user file. */
5311 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5312 array = build_array_type (unsigned_char_type_node,
5313 build_index_type (index));
5314 f_res = build_decl (BUILTINS_LOCATION,
5315 FIELD_DECL, get_identifier ("__reserved"), array);
5317 DECL_FIELD_CONTEXT (f_ovfl) = record;
5318 DECL_FIELD_CONTEXT (f_gtop) = record;
5319 DECL_FIELD_CONTEXT (f_ftop) = record;
5320 DECL_FIELD_CONTEXT (f_goff) = record;
5321 DECL_FIELD_CONTEXT (f_foff) = record;
5322 DECL_FIELD_CONTEXT (f_res) = record;
5324 TYPE_FIELDS (record) = f_ovfl;
5325 TREE_CHAIN (f_ovfl) = f_gtop;
5326 TREE_CHAIN (f_gtop) = f_ftop;
5327 TREE_CHAIN (f_ftop) = f_goff;
5328 TREE_CHAIN (f_goff) = f_foff;
5329 TREE_CHAIN (f_foff) = f_res;
5331 layout_type (record);
5334 else if (TARGET_IRIX && TARGET_IRIX6)
5335 /* On IRIX 6, this type is 'char *'. */
5336 return build_pointer_type (char_type_node);
5338 /* Otherwise, we use 'void *'. */
5339 return ptr_type_node;
5342 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5345 mips_va_start (tree valist, rtx nextarg)
5347 if (EABI_FLOAT_VARARGS_P)
5349 const CUMULATIVE_ARGS *cum;
5350 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5351 tree ovfl, gtop, ftop, goff, foff;
5353 int gpr_save_area_size;
5354 int fpr_save_area_size;
5357 cum = &crtl->args.info;
5359 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5361 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5363 f_ovfl = TYPE_FIELDS (va_list_type_node);
5364 f_gtop = TREE_CHAIN (f_ovfl);
5365 f_ftop = TREE_CHAIN (f_gtop);
5366 f_goff = TREE_CHAIN (f_ftop);
5367 f_foff = TREE_CHAIN (f_goff);
5369 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5371 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5373 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5375 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5377 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5380 /* Emit code to initialize OVFL, which points to the next varargs
5381 stack argument. CUM->STACK_WORDS gives the number of stack
5382 words used by named arguments. */
5383 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5384 if (cum->stack_words > 0)
5385 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5386 size_int (cum->stack_words * UNITS_PER_WORD));
5387 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5388 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5390 /* Emit code to initialize GTOP, the top of the GPR save area. */
5391 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5392 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5393 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5395 /* Emit code to initialize FTOP, the top of the FPR save area.
5396 This address is gpr_save_area_bytes below GTOP, rounded
5397 down to the next fp-aligned boundary. */
5398 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5399 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5400 fpr_offset &= -UNITS_PER_FPVALUE;
5402 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5403 size_int (-fpr_offset));
5404 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5405 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5407 /* Emit code to initialize GOFF, the offset from GTOP of the
5408 next GPR argument. */
5409 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5410 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5411 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5413 /* Likewise emit code to initialize FOFF, the offset from FTOP
5414 of the next FPR argument. */
5415 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5416 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5417 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5421 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5422 std_expand_builtin_va_start (valist, nextarg);
5426 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5429 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5435 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5437 type = build_pointer_type (type);
5439 if (!EABI_FLOAT_VARARGS_P)
5440 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5443 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5444 tree ovfl, top, off, align;
5445 HOST_WIDE_INT size, rsize, osize;
5448 f_ovfl = TYPE_FIELDS (va_list_type_node);
5449 f_gtop = TREE_CHAIN (f_ovfl);
5450 f_ftop = TREE_CHAIN (f_gtop);
5451 f_goff = TREE_CHAIN (f_ftop);
5452 f_foff = TREE_CHAIN (f_goff);
5456 TOP be the top of the GPR or FPR save area;
5457 OFF be the offset from TOP of the next register;
5458 ADDR_RTX be the address of the argument;
5459 SIZE be the number of bytes in the argument type;
5460 RSIZE be the number of bytes used to store the argument
5461 when it's in the register save area; and
5462 OSIZE be the number of bytes used to store it when it's
5463 in the stack overflow area.
5465 The code we want is:
5467 1: off &= -rsize; // round down
5470 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5475 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5476 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5480 [1] and [9] can sometimes be optimized away. */
5482 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5484 size = int_size_in_bytes (type);
5486 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5487 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5489 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5490 unshare_expr (valist), f_ftop, NULL_TREE);
5491 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5492 unshare_expr (valist), f_foff, NULL_TREE);
5494 /* When va_start saves FPR arguments to the stack, each slot
5495 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5496 argument's precision. */
5497 rsize = UNITS_PER_HWFPVALUE;
5499 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5500 (= PARM_BOUNDARY bits). This can be different from RSIZE
5503 (1) On 32-bit targets when TYPE is a structure such as:
5505 struct s { float f; };
5507 Such structures are passed in paired FPRs, so RSIZE
5508 will be 8 bytes. However, the structure only takes
5509 up 4 bytes of memory, so OSIZE will only be 4.
5511 (2) In combinations such as -mgp64 -msingle-float
5512 -fshort-double. Doubles passed in registers will then take
5513 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5514 stack take up UNITS_PER_WORD bytes. */
5515 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5519 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5520 unshare_expr (valist), f_gtop, NULL_TREE);
5521 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5522 unshare_expr (valist), f_goff, NULL_TREE);
5523 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5524 if (rsize > UNITS_PER_WORD)
5526 /* [1] Emit code for: off &= -rsize. */
5527 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5528 build_int_cst (TREE_TYPE (off), -rsize));
5529 gimplify_assign (unshare_expr (off), t, pre_p);
5534 /* [2] Emit code to branch if off == 0. */
5535 t = build2 (NE_EXPR, boolean_type_node, off,
5536 build_int_cst (TREE_TYPE (off), 0));
5537 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5539 /* [5] Emit code for: off -= rsize. We do this as a form of
5540 post-decrement not available to C. */
5541 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5542 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5544 /* [4] Emit code for:
5545 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5546 t = fold_convert (sizetype, t);
5547 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5548 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5549 if (BYTES_BIG_ENDIAN && rsize > size)
5551 u = size_int (rsize - size);
5552 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5554 COND_EXPR_THEN (addr) = t;
5556 if (osize > UNITS_PER_WORD)
5558 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5559 u = size_int (osize - 1);
5560 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5561 unshare_expr (ovfl), u);
5562 t = fold_convert (sizetype, t);
5563 u = size_int (-osize);
5564 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5565 t = fold_convert (TREE_TYPE (ovfl), t);
5566 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5567 unshare_expr (ovfl), t);
5572 /* [10, 11] Emit code for:
5573 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5575 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5576 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5577 if (BYTES_BIG_ENDIAN && osize > size)
5579 u = size_int (osize - size);
5580 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5583 /* String [9] and [10, 11] together. */
5585 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5586 COND_EXPR_ELSE (addr) = t;
5588 addr = fold_convert (build_pointer_type (type), addr);
5589 addr = build_va_arg_indirect_ref (addr);
5593 addr = build_va_arg_indirect_ref (addr);
5598 /* Start a definition of function NAME. MIPS16_P indicates whether the
5599 function contains MIPS16 code. */
5602 mips_start_function_definition (const char *name, bool mips16_p)
5605 fprintf (asm_out_file, "\t.set\tmips16\n");
5607 fprintf (asm_out_file, "\t.set\tnomips16\n");
5609 if (!flag_inhibit_size_directive)
5611 fputs ("\t.ent\t", asm_out_file);
5612 assemble_name (asm_out_file, name);
5613 fputs ("\n", asm_out_file);
5616 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5618 /* Start the definition proper. */
5619 assemble_name (asm_out_file, name);
5620 fputs (":\n", asm_out_file);
5623 /* End a function definition started by mips_start_function_definition. */
5626 mips_end_function_definition (const char *name)
5628 if (!flag_inhibit_size_directive)
5630 fputs ("\t.end\t", asm_out_file);
5631 assemble_name (asm_out_file, name);
5632 fputs ("\n", asm_out_file);
5636 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5639 mips_ok_for_lazy_binding_p (rtx x)
5641 return (TARGET_USE_GOT
5642 && GET_CODE (x) == SYMBOL_REF
5643 && !SYMBOL_REF_BIND_NOW_P (x)
5644 && !mips_symbol_binds_local_p (x));
5647 /* Load function address ADDR into register DEST. TYPE is as for
5648 mips_expand_call. Return true if we used an explicit lazy-binding
5652 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5654 /* If we're generating PIC, and this call is to a global function,
5655 try to allow its address to be resolved lazily. This isn't
5656 possible for sibcalls when $gp is call-saved because the value
5657 of $gp on entry to the stub would be our caller's gp, not ours. */
5658 if (TARGET_EXPLICIT_RELOCS
5659 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5660 && mips_ok_for_lazy_binding_p (addr))
5662 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5663 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5668 mips_emit_move (dest, addr);
5673 /* Each locally-defined hard-float MIPS16 function has a local symbol
5674 associated with it. This hash table maps the function symbol (FUNC)
5675 to the local symbol (LOCAL). */
5676 struct GTY(()) mips16_local_alias {
5680 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5682 /* Hash table callbacks for mips16_local_aliases. */
5685 mips16_local_aliases_hash (const void *entry)
5687 const struct mips16_local_alias *alias;
5689 alias = (const struct mips16_local_alias *) entry;
5690 return htab_hash_string (XSTR (alias->func, 0));
5694 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5696 const struct mips16_local_alias *alias1, *alias2;
5698 alias1 = (const struct mips16_local_alias *) entry1;
5699 alias2 = (const struct mips16_local_alias *) entry2;
5700 return rtx_equal_p (alias1->func, alias2->func);
5703 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5704 Return a local alias for it, creating a new one if necessary. */
5707 mips16_local_alias (rtx func)
5709 struct mips16_local_alias *alias, tmp_alias;
5712 /* Create the hash table if this is the first call. */
5713 if (mips16_local_aliases == NULL)
5714 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5715 mips16_local_aliases_eq, NULL);
5717 /* Look up the function symbol, creating a new entry if need be. */
5718 tmp_alias.func = func;
5719 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5720 gcc_assert (slot != NULL);
5722 alias = (struct mips16_local_alias *) *slot;
5725 const char *func_name, *local_name;
5728 /* Create a new SYMBOL_REF for the local symbol. The choice of
5729 __fn_local_* is based on the __fn_stub_* names that we've
5730 traditionally used for the non-MIPS16 stub. */
5731 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5732 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5733 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5734 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5736 /* Create a new structure to represent the mapping. */
5737 alias = GGC_NEW (struct mips16_local_alias);
5739 alias->local = local;
5742 return alias->local;
5745 /* A chained list of functions for which mips16_build_call_stub has already
5746 generated a stub. NAME is the name of the function and FP_RET_P is true
5747 if the function returns a value in floating-point registers. */
5748 struct mips16_stub {
5749 struct mips16_stub *next;
5753 static struct mips16_stub *mips16_stubs;
5755 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5758 mips16_stub_function (const char *name)
5762 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5763 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5767 /* Return the two-character string that identifies floating-point
5768 return mode MODE in the name of a MIPS16 function stub. */
5771 mips16_call_stub_mode_suffix (enum machine_mode mode)
5775 else if (mode == DFmode)
5777 else if (mode == SCmode)
5779 else if (mode == DCmode)
5781 else if (mode == V2SFmode)
5787 /* Write instructions to move a 32-bit value between general register
5788 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5789 from GPREG to FPREG and 'f' to move in the opposite direction. */
5792 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5794 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5795 reg_names[gpreg], reg_names[fpreg]);
5798 /* Likewise for 64-bit values. */
5801 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5804 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5805 reg_names[gpreg], reg_names[fpreg]);
5806 else if (TARGET_FLOAT64)
5808 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5809 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5810 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5811 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5815 /* Move the least-significant word. */
5816 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5817 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5818 /* ...then the most significant word. */
5819 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5820 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5824 /* Write out code to move floating-point arguments into or out of
5825 general registers. FP_CODE is the code describing which arguments
5826 are present (see the comment above the definition of CUMULATIVE_ARGS
5827 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5830 mips_output_args_xfer (int fp_code, char direction)
5832 unsigned int gparg, fparg, f;
5833 CUMULATIVE_ARGS cum;
5835 /* This code only works for o32 and o64. */
5836 gcc_assert (TARGET_OLDABI);
5838 mips_init_cumulative_args (&cum, NULL);
5840 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5842 enum machine_mode mode;
5843 struct mips_arg_info info;
5847 else if ((f & 3) == 2)
5852 mips_get_arg_info (&info, &cum, mode, NULL, true);
5853 gparg = mips_arg_regno (&info, false);
5854 fparg = mips_arg_regno (&info, true);
5857 mips_output_32bit_xfer (direction, gparg, fparg);
5859 mips_output_64bit_xfer (direction, gparg, fparg);
5861 mips_function_arg_advance (&cum, mode, NULL, true);
5865 /* Write a MIPS16 stub for the current function. This stub is used
5866 for functions which take arguments in the floating-point registers.
5867 It is normal-mode code that moves the floating-point arguments
5868 into the general registers and then jumps to the MIPS16 code. */
5871 mips16_build_function_stub (void)
5873 const char *fnname, *alias_name, *separator;
5874 char *secname, *stubname;
5879 /* Create the name of the stub, and its unique section. */
5880 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5881 alias = mips16_local_alias (symbol);
5883 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5884 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5885 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5886 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5888 /* Build a decl for the stub. */
5889 stubdecl = build_decl (BUILTINS_LOCATION,
5890 FUNCTION_DECL, get_identifier (stubname),
5891 build_function_type (void_type_node, NULL_TREE));
5892 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5893 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
5894 RESULT_DECL, NULL_TREE, void_type_node);
5896 /* Output a comment. */
5897 fprintf (asm_out_file, "\t# Stub function for %s (",
5898 current_function_name ());
5900 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5902 fprintf (asm_out_file, "%s%s", separator,
5903 (f & 3) == 1 ? "float" : "double");
5906 fprintf (asm_out_file, ")\n");
5908 /* Start the function definition. */
5909 assemble_start_function (stubdecl, stubname);
5910 mips_start_function_definition (stubname, false);
5912 /* If generating pic2 code, either set up the global pointer or
5914 if (TARGET_ABICALLS_PIC2)
5916 if (TARGET_ABSOLUTE_ABICALLS)
5917 fprintf (asm_out_file, "\t.option\tpic0\n");
5920 output_asm_insn ("%(.cpload\t%^%)", NULL);
5921 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5922 target function is. Use a local GOT access when loading the
5923 symbol, to cut down on the number of unnecessary GOT entries
5924 for stubs that aren't needed. */
5925 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5930 /* Load the address of the MIPS16 function into $25. Do this first so
5931 that targets with coprocessor interlocks can use an MFC1 to fill the
5933 output_asm_insn ("la\t%^,%0", &symbol);
5935 /* Move the arguments from floating-point registers to general registers. */
5936 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5938 /* Jump to the MIPS16 function. */
5939 output_asm_insn ("jr\t%^", NULL);
5941 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
5942 fprintf (asm_out_file, "\t.option\tpic2\n");
5944 mips_end_function_definition (stubname);
5946 /* If the linker needs to create a dynamic symbol for the target
5947 function, it will associate the symbol with the stub (which,
5948 unlike the target function, follows the proper calling conventions).
5949 It is therefore useful to have a local alias for the target function,
5950 so that it can still be identified as MIPS16 code. As an optimization,
5951 this symbol can also be used for indirect MIPS16 references from
5952 within this file. */
5953 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
5955 switch_to_section (function_section (current_function_decl));
5958 /* The current function is a MIPS16 function that returns a value in an FPR.
5959 Copy the return value from its soft-float to its hard-float location.
5960 libgcc2 has special non-MIPS16 helper functions for each case. */
5963 mips16_copy_fpr_return_value (void)
5965 rtx fn, insn, retval;
5967 enum machine_mode return_mode;
5970 return_type = DECL_RESULT (current_function_decl);
5971 return_mode = DECL_MODE (return_type);
5973 name = ACONCAT (("__mips16_ret_",
5974 mips16_call_stub_mode_suffix (return_mode),
5976 fn = mips16_stub_function (name);
5978 /* The function takes arguments in $2 (and possibly $3), so calls
5979 to it cannot be lazily bound. */
5980 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
5982 /* Model the call as something that takes the GPR return value as
5983 argument and returns an "updated" value. */
5984 retval = gen_rtx_REG (return_mode, GP_RETURN);
5985 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
5986 const0_rtx, NULL_RTX, false);
5987 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
5990 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
5991 RETVAL is the location of the return value, or null if this is
5992 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5993 arguments and FP_CODE is the code built by mips_function_arg;
5994 see the comment above CUMULATIVE_ARGS for details.
5996 There are three alternatives:
5998 - If a stub was needed, emit the call and return the call insn itself.
6000 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6001 to the new target and return null.
6003 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6006 A stub is needed for calls to functions that, in normal mode,
6007 receive arguments in FPRs or return values in FPRs. The stub
6008 copies the arguments from their soft-float positions to their
6009 hard-float positions, calls the real function, then copies the
6010 return value from its hard-float position to its soft-float
6013 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6014 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6015 automatically redirects the JAL to the stub, otherwise the JAL
6016 continues to call FN directly. */
6019 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6023 struct mips16_stub *l;
6026 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6027 we were invoked with the -msoft-float option. */
6028 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6031 /* Figure out whether the value might come back in a floating-point
6033 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6035 /* We don't need to do anything if there were no floating-point
6036 arguments and the value will not be returned in a floating-point
6038 if (fp_code == 0 && !fp_ret_p)
6041 /* We don't need to do anything if this is a call to a special
6042 MIPS16 support function. */
6044 if (mips16_stub_function_p (fn))
6047 /* This code will only work for o32 and o64 abis. The other ABI's
6048 require more sophisticated support. */
6049 gcc_assert (TARGET_OLDABI);
6051 /* If we're calling via a function pointer, use one of the magic
6052 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6053 Each stub expects the function address to arrive in register $2. */
6054 if (GET_CODE (fn) != SYMBOL_REF
6055 || !call_insn_operand (fn, VOIDmode))
6058 rtx stub_fn, insn, addr;
6061 /* If this is a locally-defined and locally-binding function,
6062 avoid the stub by calling the local alias directly. */
6063 if (mips16_local_function_p (fn))
6065 *fn_ptr = mips16_local_alias (fn);
6069 /* Create a SYMBOL_REF for the libgcc.a function. */
6071 sprintf (buf, "__mips16_call_stub_%s_%d",
6072 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6075 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6076 stub_fn = mips16_stub_function (buf);
6078 /* The function uses $2 as an argument, so calls to it
6079 cannot be lazily bound. */
6080 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6082 /* Load the target function into $2. */
6083 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6084 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6086 /* Emit the call. */
6087 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6088 args_size, NULL_RTX, lazy_p);
6090 /* Tell GCC that this call does indeed use the value of $2. */
6091 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6093 /* If we are handling a floating-point return value, we need to
6094 save $18 in the function prologue. Putting a note on the
6095 call will mean that df_regs_ever_live_p ($18) will be true if the
6096 call is not eliminated, and we can check that in the prologue
6099 CALL_INSN_FUNCTION_USAGE (insn) =
6100 gen_rtx_EXPR_LIST (VOIDmode,
6101 gen_rtx_CLOBBER (VOIDmode,
6102 gen_rtx_REG (word_mode, 18)),
6103 CALL_INSN_FUNCTION_USAGE (insn));
6108 /* We know the function we are going to call. If we have already
6109 built a stub, we don't need to do anything further. */
6110 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6111 for (l = mips16_stubs; l != NULL; l = l->next)
6112 if (strcmp (l->name, fnname) == 0)
6117 const char *separator;
6118 char *secname, *stubname;
6119 tree stubid, stubdecl;
6122 /* If the function does not return in FPRs, the special stub
6126 If the function does return in FPRs, the stub section is named
6127 .mips16.call.fp.FNNAME
6129 Build a decl for the stub. */
6130 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6132 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6134 stubid = get_identifier (stubname);
6135 stubdecl = build_decl (BUILTINS_LOCATION,
6136 FUNCTION_DECL, stubid,
6137 build_function_type (void_type_node, NULL_TREE));
6138 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6139 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6140 RESULT_DECL, NULL_TREE,
6143 /* Output a comment. */
6144 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6146 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6150 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6152 fprintf (asm_out_file, "%s%s", separator,
6153 (f & 3) == 1 ? "float" : "double");
6156 fprintf (asm_out_file, ")\n");
6158 /* Start the function definition. */
6159 assemble_start_function (stubdecl, stubname);
6160 mips_start_function_definition (stubname, false);
6164 /* Load the address of the MIPS16 function into $25. Do this
6165 first so that targets with coprocessor interlocks can use
6166 an MFC1 to fill the delay slot. */
6167 if (TARGET_EXPLICIT_RELOCS)
6169 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6170 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6173 output_asm_insn ("la\t%^,%0", &fn);
6176 /* Move the arguments from general registers to floating-point
6178 mips_output_args_xfer (fp_code, 't');
6182 /* Jump to the previously-loaded address. */
6183 output_asm_insn ("jr\t%^", NULL);
6187 /* Save the return address in $18 and call the non-MIPS16 function.
6188 The stub's caller knows that $18 might be clobbered, even though
6189 $18 is usually a call-saved register. */
6190 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6191 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
6192 output_asm_insn (MIPS_CALL ("jal", &fn, 0), &fn);
6194 /* Move the result from floating-point registers to
6195 general registers. */
6196 switch (GET_MODE (retval))
6199 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6200 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6203 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6204 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6206 /* On 64-bit targets, complex floats are returned in
6207 a single GPR, such that "sd" on a suitably-aligned
6208 target would store the value correctly. */
6209 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6210 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6211 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6212 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6213 reg_names[GP_RETURN],
6214 reg_names[GP_RETURN],
6215 reg_names[GP_RETURN + 1]);
6220 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6221 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6225 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6231 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6234 #ifdef ASM_DECLARE_FUNCTION_SIZE
6235 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6238 mips_end_function_definition (stubname);
6240 /* Record this stub. */
6241 l = XNEW (struct mips16_stub);
6242 l->name = xstrdup (fnname);
6243 l->fp_ret_p = fp_ret_p;
6244 l->next = mips16_stubs;
6248 /* If we expect a floating-point return value, but we've built a
6249 stub which does not expect one, then we're in trouble. We can't
6250 use the existing stub, because it won't handle the floating-point
6251 value. We can't build a new stub, because the linker won't know
6252 which stub to use for the various calls in this object file.
6253 Fortunately, this case is illegal, since it means that a function
6254 was declared in two different ways in a single compilation. */
6255 if (fp_ret_p && !l->fp_ret_p)
6256 error ("cannot handle inconsistent calls to %qs", fnname);
6258 if (retval == NULL_RTX)
6259 insn = gen_call_internal_direct (fn, args_size);
6261 insn = gen_call_value_internal_direct (retval, fn, args_size);
6262 insn = mips_emit_call_insn (insn, fn, fn, false);
6264 /* If we are calling a stub which handles a floating-point return
6265 value, we need to arrange to save $18 in the prologue. We do this
6266 by marking the function call as using the register. The prologue
6267 will later see that it is used, and emit code to save it. */
6269 CALL_INSN_FUNCTION_USAGE (insn) =
6270 gen_rtx_EXPR_LIST (VOIDmode,
6271 gen_rtx_CLOBBER (VOIDmode,
6272 gen_rtx_REG (word_mode, 18)),
6273 CALL_INSN_FUNCTION_USAGE (insn));
6278 /* Expand a call of type TYPE. RESULT is where the result will go (null
6279 for "call"s and "sibcall"s), ADDR is the address of the function,
6280 ARGS_SIZE is the size of the arguments and AUX is the value passed
6281 to us by mips_function_arg. LAZY_P is true if this call already
6282 involves a lazily-bound function address (such as when calling
6283 functions through a MIPS16 hard-float stub).
6285 Return the call itself. */
6288 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6289 rtx args_size, rtx aux, bool lazy_p)
6291 rtx orig_addr, pattern, insn;
6294 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6295 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6298 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6303 if (!call_insn_operand (addr, VOIDmode))
6305 if (type == MIPS_CALL_EPILOGUE)
6306 addr = MIPS_EPILOGUE_TEMP (Pmode);
6308 addr = gen_reg_rtx (Pmode);
6309 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6314 rtx (*fn) (rtx, rtx);
6316 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6317 fn = gen_call_split;
6318 else if (type == MIPS_CALL_SIBCALL)
6319 fn = gen_sibcall_internal;
6321 fn = gen_call_internal;
6323 pattern = fn (addr, args_size);
6325 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6327 /* Handle return values created by mips_return_fpr_pair. */
6328 rtx (*fn) (rtx, rtx, rtx, rtx);
6331 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6332 fn = gen_call_value_multiple_split;
6333 else if (type == MIPS_CALL_SIBCALL)
6334 fn = gen_sibcall_value_multiple_internal;
6336 fn = gen_call_value_multiple_internal;
6338 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6339 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6340 pattern = fn (reg1, addr, args_size, reg2);
6344 rtx (*fn) (rtx, rtx, rtx);
6346 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6347 fn = gen_call_value_split;
6348 else if (type == MIPS_CALL_SIBCALL)
6349 fn = gen_sibcall_value_internal;
6351 fn = gen_call_value_internal;
6353 /* Handle return values created by mips_return_fpr_single. */
6354 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6355 result = XEXP (XVECEXP (result, 0, 0), 0);
6356 pattern = fn (result, addr, args_size);
6359 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6362 /* Split call instruction INSN into a $gp-clobbering call and
6363 (where necessary) an instruction to restore $gp from its save slot.
6364 CALL_PATTERN is the pattern of the new call. */
6367 mips_split_call (rtx insn, rtx call_pattern)
6371 new_insn = emit_call_insn (call_pattern);
6372 CALL_INSN_FUNCTION_USAGE (new_insn)
6373 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6374 if (!find_reg_note (insn, REG_NORETURN, 0))
6375 /* Pick a temporary register that is suitable for both MIPS16 and
6376 non-MIPS16 code. $4 and $5 are used for returning complex double
6377 values in soft-float code, so $6 is the first suitable candidate. */
6378 mips_restore_gp (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6381 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6384 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6386 if (!TARGET_SIBCALLS)
6389 /* Interrupt handlers need special epilogue code and therefore can't
6391 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6394 /* We can't do a sibcall if the called function is a MIPS16 function
6395 because there is no direct "jx" instruction equivalent to "jalx" to
6396 switch the ISA mode. We only care about cases where the sibling
6397 and normal calls would both be direct. */
6399 && mips_use_mips16_mode_p (decl)
6400 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6403 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6404 functions could be MIPS16 ones unless an attribute explicitly tells
6406 if (TARGET_INTERLINK_MIPS16
6408 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6409 && !mips_nomips16_decl_p (decl)
6410 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6417 /* Emit code to move general operand SRC into condition-code
6418 register DEST given that SCRATCH is a scratch TFmode FPR.
6425 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6428 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6432 /* Change the source to SFmode. */
6434 src = adjust_address (src, SFmode, 0);
6435 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6436 src = gen_rtx_REG (SFmode, true_regnum (src));
6438 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6439 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6441 mips_emit_move (copy_rtx (fp1), src);
6442 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6443 emit_insn (gen_slt_sf (dest, fp2, fp1));
6446 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6447 Assume that the areas do not overlap. */
6450 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6452 HOST_WIDE_INT offset, delta;
6453 unsigned HOST_WIDE_INT bits;
6455 enum machine_mode mode;
6458 /* Work out how many bits to move at a time. If both operands have
6459 half-word alignment, it is usually better to move in half words.
6460 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6461 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6462 Otherwise move word-sized chunks. */
6463 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6464 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6465 bits = BITS_PER_WORD / 2;
6467 bits = BITS_PER_WORD;
6469 mode = mode_for_size (bits, MODE_INT, 0);
6470 delta = bits / BITS_PER_UNIT;
6472 /* Allocate a buffer for the temporary registers. */
6473 regs = XALLOCAVEC (rtx, length / delta);
6475 /* Load as many BITS-sized chunks as possible. Use a normal load if
6476 the source has enough alignment, otherwise use left/right pairs. */
6477 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6479 regs[i] = gen_reg_rtx (mode);
6480 if (MEM_ALIGN (src) >= bits)
6481 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6484 rtx part = adjust_address (src, BLKmode, offset);
6485 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6490 /* Copy the chunks to the destination. */
6491 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6492 if (MEM_ALIGN (dest) >= bits)
6493 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6496 rtx part = adjust_address (dest, BLKmode, offset);
6497 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6501 /* Mop up any left-over bytes. */
6502 if (offset < length)
6504 src = adjust_address (src, BLKmode, offset);
6505 dest = adjust_address (dest, BLKmode, offset);
6506 move_by_pieces (dest, src, length - offset,
6507 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6511 /* Helper function for doing a loop-based block operation on memory
6512 reference MEM. Each iteration of the loop will operate on LENGTH
6515 Create a new base register for use within the loop and point it to
6516 the start of MEM. Create a new memory reference that uses this
6517 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6520 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6521 rtx *loop_reg, rtx *loop_mem)
6523 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6525 /* Although the new mem does not refer to a known location,
6526 it does keep up to LENGTH bytes of alignment. */
6527 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6528 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6531 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6532 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6533 the memory regions do not overlap. */
6536 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6537 HOST_WIDE_INT bytes_per_iter)
6539 rtx label, src_reg, dest_reg, final_src, test;
6540 HOST_WIDE_INT leftover;
6542 leftover = length % bytes_per_iter;
6545 /* Create registers and memory references for use within the loop. */
6546 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6547 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6549 /* Calculate the value that SRC_REG should have after the last iteration
6551 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6554 /* Emit the start of the loop. */
6555 label = gen_label_rtx ();
6558 /* Emit the loop body. */
6559 mips_block_move_straight (dest, src, bytes_per_iter);
6561 /* Move on to the next block. */
6562 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6563 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6565 /* Emit the loop condition. */
6566 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6567 if (Pmode == DImode)
6568 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6570 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6572 /* Mop up any left-over bytes. */
6574 mips_block_move_straight (dest, src, leftover);
6577 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6578 memory reference SRC to memory reference DEST. */
6581 mips_expand_block_move (rtx dest, rtx src, rtx length)
6583 if (CONST_INT_P (length))
6585 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6587 mips_block_move_straight (dest, src, INTVAL (length));
6592 mips_block_move_loop (dest, src, INTVAL (length),
6593 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6600 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6603 mips_expand_synci_loop (rtx begin, rtx end)
6605 rtx inc, label, cmp, cmp_result;
6607 /* Load INC with the cache line size (rdhwr INC,$1). */
6608 inc = gen_reg_rtx (Pmode);
6609 emit_insn (Pmode == SImode
6610 ? gen_rdhwr_synci_step_si (inc)
6611 : gen_rdhwr_synci_step_di (inc));
6613 /* Loop back to here. */
6614 label = gen_label_rtx ();
6617 emit_insn (gen_synci (begin));
6619 cmp = mips_force_binary (Pmode, GTU, begin, end);
6621 mips_emit_binary (PLUS, begin, begin, inc);
6623 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6624 emit_jump_insn (gen_condjump (cmp_result, label));
6627 /* Expand a QI or HI mode atomic memory operation.
6629 GENERATOR contains a pointer to the gen_* function that generates
6630 the SI mode underlying atomic operation using masks that we
6633 RESULT is the return register for the operation. Its value is NULL
6636 MEM is the location of the atomic access.
6638 OLDVAL is the first operand for the operation.
6640 NEWVAL is the optional second operand for the operation. Its value
6641 is NULL if unused. */
6644 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6645 rtx result, rtx mem, rtx oldval, rtx newval)
6647 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6648 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6650 enum machine_mode mode;
6652 mode = GET_MODE (mem);
6654 /* Compute the address of the containing SImode value. */
6655 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6656 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6657 force_reg (Pmode, GEN_INT (-4)));
6659 /* Create a memory reference for it. */
6660 memsi = gen_rtx_MEM (SImode, memsi_addr);
6661 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6662 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6664 /* Work out the byte offset of the QImode or HImode value,
6665 counting from the least significant byte. */
6666 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6667 if (TARGET_BIG_ENDIAN)
6668 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6670 /* Multiply by eight to convert the shift value from bytes to bits. */
6671 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6673 /* Make the final shift an SImode value, so that it can be used in
6674 SImode operations. */
6675 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6677 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6678 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6679 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6680 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6682 /* Compute the equivalent exclusive mask. */
6683 inverted_mask = gen_reg_rtx (SImode);
6684 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6685 gen_rtx_NOT (SImode, mask)));
6687 /* Shift the old value into place. */
6688 if (oldval != const0_rtx)
6690 oldval = convert_modes (SImode, mode, oldval, true);
6691 oldval = force_reg (SImode, oldval);
6692 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6695 /* Do the same for the new value. */
6696 if (newval && newval != const0_rtx)
6698 newval = convert_modes (SImode, mode, newval, true);
6699 newval = force_reg (SImode, newval);
6700 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6703 /* Do the SImode atomic access. */
6705 res = gen_reg_rtx (SImode);
6707 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6709 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6711 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6717 /* Shift and convert the result. */
6718 mips_emit_binary (AND, res, res, mask);
6719 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6720 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6724 /* Return true if it is possible to use left/right accesses for a
6725 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6726 returning true, update *OP, *LEFT and *RIGHT as follows:
6728 *OP is a BLKmode reference to the whole field.
6730 *LEFT is a QImode reference to the first byte if big endian or
6731 the last byte if little endian. This address can be used in the
6732 left-side instructions (LWL, SWL, LDL, SDL).
6734 *RIGHT is a QImode reference to the opposite end of the field and
6735 can be used in the patterning right-side instruction. */
6738 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6739 rtx *left, rtx *right)
6743 /* Check that the operand really is a MEM. Not all the extv and
6744 extzv predicates are checked. */
6748 /* Check that the size is valid. */
6749 if (width != 32 && (!TARGET_64BIT || width != 64))
6752 /* We can only access byte-aligned values. Since we are always passed
6753 a reference to the first byte of the field, it is not necessary to
6754 do anything with BITPOS after this check. */
6755 if (bitpos % BITS_PER_UNIT != 0)
6758 /* Reject aligned bitfields: we want to use a normal load or store
6759 instead of a left/right pair. */
6760 if (MEM_ALIGN (*op) >= width)
6763 /* Adjust *OP to refer to the whole field. This also has the effect
6764 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6765 *op = adjust_address (*op, BLKmode, 0);
6766 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6768 /* Get references to both ends of the field. We deliberately don't
6769 use the original QImode *OP for FIRST since the new BLKmode one
6770 might have a simpler address. */
6771 first = adjust_address (*op, QImode, 0);
6772 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6774 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6775 correspond to the MSB and RIGHT to the LSB. */
6776 if (TARGET_BIG_ENDIAN)
6777 *left = first, *right = last;
6779 *left = last, *right = first;
6784 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6785 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6786 the operation is the equivalent of:
6788 (set DEST (*_extract SRC WIDTH BITPOS))
6790 Return true on success. */
6793 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6794 HOST_WIDE_INT bitpos)
6796 rtx left, right, temp;
6798 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6799 be a paradoxical word_mode subreg. This is the only case in which
6800 we allow the destination to be larger than the source. */
6801 if (GET_CODE (dest) == SUBREG
6802 && GET_MODE (dest) == DImode
6803 && GET_MODE (SUBREG_REG (dest)) == SImode)
6804 dest = SUBREG_REG (dest);
6806 /* After the above adjustment, the destination must be the same
6807 width as the source. */
6808 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6811 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6814 temp = gen_reg_rtx (GET_MODE (dest));
6815 if (GET_MODE (dest) == DImode)
6817 emit_insn (gen_mov_ldl (temp, src, left));
6818 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6822 emit_insn (gen_mov_lwl (temp, src, left));
6823 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6828 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6829 BITPOS and SRC are the operands passed to the expander; the operation
6830 is the equivalent of:
6832 (set (zero_extract DEST WIDTH BITPOS) SRC)
6834 Return true on success. */
6837 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6838 HOST_WIDE_INT bitpos)
6841 enum machine_mode mode;
6843 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6846 mode = mode_for_size (width, MODE_INT, 0);
6847 src = gen_lowpart (mode, src);
6850 emit_insn (gen_mov_sdl (dest, src, left));
6851 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6855 emit_insn (gen_mov_swl (dest, src, left));
6856 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6861 /* Return true if X is a MEM with the same size as MODE. */
6864 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6871 size = MEM_SIZE (x);
6872 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6875 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6876 source of an "ext" instruction or the destination of an "ins"
6877 instruction. OP must be a register operand and the following
6878 conditions must hold:
6880 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6881 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6882 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6884 Also reject lengths equal to a word as they are better handled
6885 by the move patterns. */
6888 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6890 if (!ISA_HAS_EXT_INS
6891 || !register_operand (op, VOIDmode)
6892 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6895 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6898 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6904 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6905 operation if MAXLEN is the maxium length of consecutive bits that
6906 can make up MASK. MODE is the mode of the operation. See
6907 mask_low_and_shift_len for the actual definition. */
6910 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6912 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
6915 /* Return true iff OP1 and OP2 are valid operands together for the
6916 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
6917 see the table in the comment before the pattern. */
6920 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
6922 return (memory_operand (op1, mode)
6923 ? and_load_operand (op2, mode)
6924 : and_reg_operand (op2, mode));
6927 /* The canonical form of a mask-low-and-shift-left operation is
6928 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6929 cleared. Thus we need to shift MASK to the right before checking if it
6930 is a valid mask value. MODE is the mode of the operation. If true
6931 return the length of the mask, otherwise return -1. */
6934 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
6936 HOST_WIDE_INT shval;
6938 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
6939 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
6942 /* Return true if -msplit-addresses is selected and should be honored.
6944 -msplit-addresses is a half-way house between explicit relocations
6945 and the traditional assembler macros. It can split absolute 32-bit
6946 symbolic constants into a high/lo_sum pair but uses macros for other
6949 Like explicit relocation support for REL targets, it relies
6950 on GNU extensions in the assembler and the linker.
6952 Although this code should work for -O0, it has traditionally
6953 been treated as an optimization. */
6956 mips_split_addresses_p (void)
6958 return (TARGET_SPLIT_ADDRESSES
6962 && !ABI_HAS_64BIT_SYMBOLS);
6965 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6968 mips_init_relocs (void)
6970 memset (mips_split_p, '\0', sizeof (mips_split_p));
6971 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
6972 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6973 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6975 if (ABI_HAS_64BIT_SYMBOLS)
6977 if (TARGET_EXPLICIT_RELOCS)
6979 mips_split_p[SYMBOL_64_HIGH] = true;
6980 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6981 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6983 mips_split_p[SYMBOL_64_MID] = true;
6984 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6985 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6987 mips_split_p[SYMBOL_64_LOW] = true;
6988 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6989 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6991 mips_split_p[SYMBOL_ABSOLUTE] = true;
6992 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6997 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6999 mips_split_p[SYMBOL_ABSOLUTE] = true;
7000 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7001 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7003 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7009 /* The high part is provided by a pseudo copy of $gp. */
7010 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7011 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7013 else if (TARGET_EXPLICIT_RELOCS)
7014 /* Small data constants are kept whole until after reload,
7015 then lowered by mips_rewrite_small_data. */
7016 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7018 if (TARGET_EXPLICIT_RELOCS)
7020 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7023 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7024 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7028 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7029 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7032 /* Expose the use of $28 as soon as possible. */
7033 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7037 /* The HIGH and LO_SUM are matched by special .md patterns. */
7038 mips_split_p[SYMBOL_GOT_DISP] = true;
7040 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7041 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7042 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7044 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7045 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7046 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7051 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7053 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7054 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7056 /* Expose the use of $28 as soon as possible. */
7057 mips_split_p[SYMBOL_GOT_DISP] = true;
7063 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7064 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7065 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7068 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7069 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7071 mips_split_p[SYMBOL_DTPREL] = true;
7072 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7073 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7075 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7077 mips_split_p[SYMBOL_TPREL] = true;
7078 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7079 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7081 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7084 /* If OP is an UNSPEC address, return the address to which it refers,
7085 otherwise return OP itself. */
7088 mips_strip_unspec_address (rtx op)
7092 split_const (op, &base, &offset);
7093 if (UNSPEC_ADDRESS_P (base))
7094 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
7098 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7099 in context CONTEXT. RELOCS is the array of relocations to use. */
7102 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7103 const char **relocs)
7105 enum mips_symbol_type symbol_type;
7108 symbol_type = mips_classify_symbolic_expression (op, context);
7109 gcc_assert (relocs[symbol_type]);
7111 fputs (relocs[symbol_type], file);
7112 output_addr_const (file, mips_strip_unspec_address (op));
7113 for (p = relocs[symbol_type]; *p != 0; p++)
7118 /* Start a new block with the given asm switch enabled. If we need
7119 to print a directive, emit PREFIX before it and SUFFIX after it. */
7122 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7123 const char *prefix, const char *suffix)
7125 if (asm_switch->nesting_level == 0)
7126 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7127 asm_switch->nesting_level++;
7130 /* Likewise, but end a block. */
7133 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7134 const char *prefix, const char *suffix)
7136 gcc_assert (asm_switch->nesting_level);
7137 asm_switch->nesting_level--;
7138 if (asm_switch->nesting_level == 0)
7139 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7142 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7143 that either print a complete line or print nothing. */
7146 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7148 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7152 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7154 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7157 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7158 The punctuation characters are:
7160 '(' Start a nested ".set noreorder" block.
7161 ')' End a nested ".set noreorder" block.
7162 '[' Start a nested ".set noat" block.
7163 ']' End a nested ".set noat" block.
7164 '<' Start a nested ".set nomacro" block.
7165 '>' End a nested ".set nomacro" block.
7166 '*' Behave like %(%< if generating a delayed-branch sequence.
7167 '#' Print a nop if in a ".set noreorder" block.
7168 '/' Like '#', but do nothing within a delayed-branch sequence.
7169 '?' Print "l" if mips_branch_likely is true
7170 '~' Print a nop if mips_branch_likely is true
7171 '.' Print the name of the register with a hard-wired zero (zero or $0).
7172 '@' Print the name of the assembler temporary register (at or $1).
7173 '^' Print the name of the pic call-through register (t9 or $25).
7174 '+' Print the name of the gp register (usually gp or $28).
7175 '$' Print the name of the stack pointer register (sp or $29).
7177 See also mips_init_print_operand_pucnt. */
7180 mips_print_operand_punctuation (FILE *file, int ch)
7185 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7189 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7193 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7197 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7201 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7205 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7209 if (final_sequence != 0)
7211 mips_print_operand_punctuation (file, '(');
7212 mips_print_operand_punctuation (file, '<');
7217 if (mips_noreorder.nesting_level > 0)
7218 fputs ("\n\tnop", file);
7222 /* Print an extra newline so that the delayed insn is separated
7223 from the following ones. This looks neater and is consistent
7224 with non-nop delayed sequences. */
7225 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7226 fputs ("\n\tnop\n", file);
7230 if (mips_branch_likely)
7235 if (mips_branch_likely)
7236 fputs ("\n\tnop", file);
7240 fputs (reg_names[GP_REG_FIRST + 0], file);
7244 fputs (reg_names[GP_REG_FIRST + 1], file);
7248 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7252 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7256 fputs (reg_names[STACK_POINTER_REGNUM], file);
7265 /* Initialize mips_print_operand_punct. */
7268 mips_init_print_operand_punct (void)
7272 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7273 mips_print_operand_punct[(unsigned char) *p] = true;
7276 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7277 associated with condition CODE. Print the condition part of the
7281 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7295 /* Conveniently, the MIPS names for these conditions are the same
7296 as their RTL equivalents. */
7297 fputs (GET_RTX_NAME (code), file);
7301 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7306 /* Likewise floating-point branches. */
7309 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7314 fputs ("c1f", file);
7318 fputs ("c1t", file);
7322 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7327 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7329 'X' Print CONST_INT OP in hexadecimal format.
7330 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7331 'd' Print CONST_INT OP in decimal.
7332 'm' Print one less than CONST_INT OP in decimal.
7333 'h' Print the high-part relocation associated with OP, after stripping
7335 'R' Print the low-part relocation associated with OP.
7336 'C' Print the integer branch condition for comparison OP.
7337 'N' Print the inverse of the integer branch condition for comparison OP.
7338 'F' Print the FPU branch condition for comparison OP.
7339 'W' Print the inverse of the FPU branch condition for comparison OP.
7340 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7341 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7342 't' Like 'T', but with the EQ/NE cases reversed
7343 'Y' Print mips_fp_conditions[INTVAL (OP)]
7344 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7345 'q' Print a DSP accumulator register.
7346 'D' Print the second part of a double-word register or memory operand.
7347 'L' Print the low-order register in a double-word register operand.
7348 'M' Print high-order register in a double-word register operand.
7349 'z' Print $0 if OP is zero, otherwise print OP normally. */
7352 mips_print_operand (FILE *file, rtx op, int letter)
7356 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7358 mips_print_operand_punctuation (file, letter);
7363 code = GET_CODE (op);
7368 if (CONST_INT_P (op))
7369 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7371 output_operand_lossage ("invalid use of '%%%c'", letter);
7375 if (CONST_INT_P (op))
7376 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7378 output_operand_lossage ("invalid use of '%%%c'", letter);
7382 if (CONST_INT_P (op))
7383 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7385 output_operand_lossage ("invalid use of '%%%c'", letter);
7389 if (CONST_INT_P (op))
7390 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7392 output_operand_lossage ("invalid use of '%%%c'", letter);
7398 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7402 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7406 mips_print_int_branch_condition (file, code, letter);
7410 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7414 mips_print_float_branch_condition (file, code, letter);
7418 mips_print_float_branch_condition (file, reverse_condition (code),
7425 int truth = (code == NE) == (letter == 'T');
7426 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7431 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7432 fputs (mips_fp_conditions[UINTVAL (op)], file);
7434 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7441 mips_print_operand (file, op, 0);
7447 if (code == REG && MD_REG_P (REGNO (op)))
7448 fprintf (file, "$ac0");
7449 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7450 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7452 output_operand_lossage ("invalid use of '%%%c'", letter);
7460 unsigned int regno = REGNO (op);
7461 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7462 || (letter == 'L' && TARGET_BIG_ENDIAN)
7465 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7466 output_operand_lossage ("invalid use of '%%%c'", letter);
7467 /* We need to print $0 .. $31 for COP0 registers. */
7468 if (COP0_REG_P (regno))
7469 fprintf (file, "$%s", ®_names[regno][4]);
7471 fprintf (file, "%s", reg_names[regno]);
7477 output_address (plus_constant (XEXP (op, 0), 4));
7478 else if (letter && letter != 'z')
7479 output_operand_lossage ("invalid use of '%%%c'", letter);
7481 output_address (XEXP (op, 0));
7485 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7486 fputs (reg_names[GP_REG_FIRST], file);
7487 else if (letter && letter != 'z')
7488 output_operand_lossage ("invalid use of '%%%c'", letter);
7489 else if (CONST_GP_P (op))
7490 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7492 output_addr_const (file, mips_strip_unspec_address (op));
7498 /* Output address operand X to FILE. */
7501 mips_print_operand_address (FILE *file, rtx x)
7503 struct mips_address_info addr;
7505 if (mips_classify_address (&addr, x, word_mode, true))
7509 mips_print_operand (file, addr.offset, 0);
7510 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7513 case ADDRESS_LO_SUM:
7514 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7516 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7519 case ADDRESS_CONST_INT:
7520 output_addr_const (file, x);
7521 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7524 case ADDRESS_SYMBOLIC:
7525 output_addr_const (file, mips_strip_unspec_address (x));
7531 /* Implement TARGET_ENCODE_SECTION_INFO. */
7534 mips_encode_section_info (tree decl, rtx rtl, int first)
7536 default_encode_section_info (decl, rtl, first);
7538 if (TREE_CODE (decl) == FUNCTION_DECL)
7540 rtx symbol = XEXP (rtl, 0);
7541 tree type = TREE_TYPE (decl);
7543 /* Encode whether the symbol is short or long. */
7544 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7545 || mips_far_type_p (type))
7546 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7550 /* Implement TARGET_SELECT_RTX_SECTION. */
7553 mips_select_rtx_section (enum machine_mode mode, rtx x,
7554 unsigned HOST_WIDE_INT align)
7556 /* ??? Consider using mergeable small data sections. */
7557 if (mips_rtx_constant_in_small_data_p (mode))
7558 return get_named_section (NULL, ".sdata", 0);
7560 return default_elf_select_rtx_section (mode, x, align);
7563 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7565 The complication here is that, with the combination TARGET_ABICALLS
7566 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7567 absolute addresses, and should therefore not be included in the
7568 read-only part of a DSO. Handle such cases by selecting a normal
7569 data section instead of a read-only one. The logic apes that in
7570 default_function_rodata_section. */
7573 mips_function_rodata_section (tree decl)
7575 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7576 return default_function_rodata_section (decl);
7578 if (decl && DECL_SECTION_NAME (decl))
7580 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7581 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7583 char *rname = ASTRDUP (name);
7585 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7587 else if (flag_function_sections
7588 && flag_data_sections
7589 && strncmp (name, ".text.", 6) == 0)
7591 char *rname = ASTRDUP (name);
7592 memcpy (rname + 1, "data", 4);
7593 return get_section (rname, SECTION_WRITE, decl);
7596 return data_section;
7599 /* Implement TARGET_IN_SMALL_DATA_P. */
7602 mips_in_small_data_p (const_tree decl)
7604 unsigned HOST_WIDE_INT size;
7606 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7609 /* We don't yet generate small-data references for -mabicalls
7610 or VxWorks RTP code. See the related -G handling in
7611 mips_override_options. */
7612 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7615 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7619 /* Reject anything that isn't in a known small-data section. */
7620 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7621 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7624 /* If a symbol is defined externally, the assembler will use the
7625 usual -G rules when deciding how to implement macros. */
7626 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7629 else if (TARGET_EMBEDDED_DATA)
7631 /* Don't put constants into the small data section: we want them
7632 to be in ROM rather than RAM. */
7633 if (TREE_CODE (decl) != VAR_DECL)
7636 if (TREE_READONLY (decl)
7637 && !TREE_SIDE_EFFECTS (decl)
7638 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7642 /* Enforce -mlocal-sdata. */
7643 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7646 /* Enforce -mextern-sdata. */
7647 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7649 if (DECL_EXTERNAL (decl))
7651 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7655 /* We have traditionally not treated zero-sized objects as small data,
7656 so this is now effectively part of the ABI. */
7657 size = int_size_in_bytes (TREE_TYPE (decl));
7658 return size > 0 && size <= mips_small_data_threshold;
7661 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7662 anchors for small data: the GP register acts as an anchor in that
7663 case. We also don't want to use them for PC-relative accesses,
7664 where the PC acts as an anchor. */
7667 mips_use_anchors_for_symbol_p (const_rtx symbol)
7669 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7671 case SYMBOL_PC_RELATIVE:
7672 case SYMBOL_GP_RELATIVE:
7676 return default_use_anchors_for_symbol_p (symbol);
7680 /* The MIPS debug format wants all automatic variables and arguments
7681 to be in terms of the virtual frame pointer (stack pointer before
7682 any adjustment in the function), while the MIPS 3.0 linker wants
7683 the frame pointer to be the stack pointer after the initial
7684 adjustment. So, we do the adjustment here. The arg pointer (which
7685 is eliminated) points to the virtual frame pointer, while the frame
7686 pointer (which may be eliminated) points to the stack pointer after
7687 the initial adjustments. */
7690 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7692 rtx offset2 = const0_rtx;
7693 rtx reg = eliminate_constant_term (addr, &offset2);
7696 offset = INTVAL (offset2);
7698 if (reg == stack_pointer_rtx
7699 || reg == frame_pointer_rtx
7700 || reg == hard_frame_pointer_rtx)
7702 offset -= cfun->machine->frame.total_size;
7703 if (reg == hard_frame_pointer_rtx)
7704 offset += cfun->machine->frame.hard_frame_pointer_offset;
7707 /* sdbout_parms does not want this to crash for unrecognized cases. */
7709 else if (reg != arg_pointer_rtx)
7710 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7717 /* Implement ASM_OUTPUT_EXTERNAL. */
7720 mips_output_external (FILE *file, tree decl, const char *name)
7722 default_elf_asm_output_external (file, decl, name);
7724 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7725 set in order to avoid putting out names that are never really
7727 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7729 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7731 /* When using assembler macros, emit .extern directives for
7732 all small-data externs so that the assembler knows how
7735 In most cases it would be safe (though pointless) to emit
7736 .externs for other symbols too. One exception is when an
7737 object is within the -G limit but declared by the user to
7738 be in a section other than .sbss or .sdata. */
7739 fputs ("\t.extern\t", file);
7740 assemble_name (file, name);
7741 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7742 int_size_in_bytes (TREE_TYPE (decl)));
7744 else if (TARGET_IRIX
7745 && mips_abi == ABI_32
7746 && TREE_CODE (decl) == FUNCTION_DECL)
7748 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7749 `.global name .text' directive for every used but
7750 undefined function. If we don't, the linker may perform
7751 an optimization (skipping over the insns that set $gp)
7752 when it is unsafe. */
7753 fputs ("\t.globl ", file);
7754 assemble_name (file, name);
7755 fputs (" .text\n", file);
7760 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7763 mips_output_filename (FILE *stream, const char *name)
7765 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7767 if (write_symbols == DWARF2_DEBUG)
7769 else if (mips_output_filename_first_time)
7771 mips_output_filename_first_time = 0;
7772 num_source_filenames += 1;
7773 current_function_file = name;
7774 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7775 output_quoted_string (stream, name);
7776 putc ('\n', stream);
7778 /* If we are emitting stabs, let dbxout.c handle this (except for
7779 the mips_output_filename_first_time case). */
7780 else if (write_symbols == DBX_DEBUG)
7782 else if (name != current_function_file
7783 && strcmp (name, current_function_file) != 0)
7785 num_source_filenames += 1;
7786 current_function_file = name;
7787 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7788 output_quoted_string (stream, name);
7789 putc ('\n', stream);
7793 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7795 static void ATTRIBUTE_UNUSED
7796 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7801 fputs ("\t.dtprelword\t", file);
7805 fputs ("\t.dtpreldword\t", file);
7811 output_addr_const (file, x);
7812 fputs ("+0x8000", file);
7815 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7818 mips_dwarf_register_span (rtx reg)
7821 enum machine_mode mode;
7823 /* By default, GCC maps increasing register numbers to increasing
7824 memory locations, but paired FPRs are always little-endian,
7825 regardless of the prevailing endianness. */
7826 mode = GET_MODE (reg);
7827 if (FP_REG_P (REGNO (reg))
7828 && TARGET_BIG_ENDIAN
7829 && MAX_FPRS_PER_FMT > 1
7830 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7832 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7833 high = mips_subword (reg, true);
7834 low = mips_subword (reg, false);
7835 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7841 /* Implement ASM_OUTPUT_ASCII. */
7844 mips_output_ascii (FILE *stream, const char *string, size_t len)
7850 fprintf (stream, "\t.ascii\t\"");
7851 for (i = 0; i < len; i++)
7855 c = (unsigned char) string[i];
7858 if (c == '\\' || c == '\"')
7860 putc ('\\', stream);
7868 fprintf (stream, "\\%03o", c);
7872 if (cur_pos > 72 && i+1 < len)
7875 fprintf (stream, "\"\n\t.ascii\t\"");
7878 fprintf (stream, "\"\n");
7881 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7882 macros, mark the symbol as written so that mips_asm_output_external
7883 won't emit an .extern for it. STREAM is the output file, NAME is the
7884 name of the symbol, INIT_STRING is the string that should be written
7885 before the symbol and FINAL_STRING is the string that should be
7886 written after it. FINAL_STRING is a printf format that consumes the
7887 remaining arguments. */
7890 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7891 const char *final_string, ...)
7895 fputs (init_string, stream);
7896 assemble_name (stream, name);
7897 va_start (ap, final_string);
7898 vfprintf (stream, final_string, ap);
7901 if (!TARGET_EXPLICIT_RELOCS)
7903 tree name_tree = get_identifier (name);
7904 TREE_ASM_WRITTEN (name_tree) = 1;
7908 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7909 NAME is the name of the object and ALIGN is the required alignment
7910 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7911 alignment argument. */
7914 mips_declare_common_object (FILE *stream, const char *name,
7915 const char *init_string,
7916 unsigned HOST_WIDE_INT size,
7917 unsigned int align, bool takes_alignment_p)
7919 if (!takes_alignment_p)
7921 size += (align / BITS_PER_UNIT) - 1;
7922 size -= size % (align / BITS_PER_UNIT);
7923 mips_declare_object (stream, name, init_string,
7924 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7927 mips_declare_object (stream, name, init_string,
7928 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7929 size, align / BITS_PER_UNIT);
7932 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7933 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7936 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7937 unsigned HOST_WIDE_INT size,
7940 /* If the target wants uninitialized const declarations in
7941 .rdata then don't put them in .comm. */
7942 if (TARGET_EMBEDDED_DATA
7943 && TARGET_UNINIT_CONST_IN_RODATA
7944 && TREE_CODE (decl) == VAR_DECL
7945 && TREE_READONLY (decl)
7946 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7948 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7949 targetm.asm_out.globalize_label (stream, name);
7951 switch_to_section (readonly_data_section);
7952 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7953 mips_declare_object (stream, name, "",
7954 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7958 mips_declare_common_object (stream, name, "\n\t.comm\t",
7962 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7963 extern int size_directive_output;
7965 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7966 definitions except that it uses mips_declare_object to emit the label. */
7969 mips_declare_object_name (FILE *stream, const char *name,
7970 tree decl ATTRIBUTE_UNUSED)
7972 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7973 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7976 size_directive_output = 0;
7977 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7981 size_directive_output = 1;
7982 size = int_size_in_bytes (TREE_TYPE (decl));
7983 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7986 mips_declare_object (stream, name, "", ":\n");
7989 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7992 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7996 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7997 if (!flag_inhibit_size_directive
7998 && DECL_SIZE (decl) != 0
8001 && DECL_INITIAL (decl) == error_mark_node
8002 && !size_directive_output)
8006 size_directive_output = 1;
8007 size = int_size_in_bytes (TREE_TYPE (decl));
8008 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8013 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8014 with the current ABI. */
8017 mips_mdebug_abi_name (void)
8030 return TARGET_64BIT ? "eabi64" : "eabi32";
8036 /* Implement TARGET_ASM_FILE_START. */
8039 mips_file_start (void)
8041 default_file_start ();
8043 /* Generate a special section to describe the ABI switches used to
8044 produce the resultant binary. This is unnecessary on IRIX and
8045 causes unwanted warnings from the native linker. */
8048 /* Record the ABI itself. Modern versions of binutils encode
8049 this information in the ELF header flags, but GDB needs the
8050 information in order to correctly debug binaries produced by
8051 older binutils. See the function mips_gdbarch_init in
8053 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8054 mips_mdebug_abi_name ());
8056 /* There is no ELF header flag to distinguish long32 forms of the
8057 EABI from long64 forms. Emit a special section to help tools
8058 such as GDB. Do the same for o64, which is sometimes used with
8060 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8061 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8062 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8064 #ifdef HAVE_AS_GNU_ATTRIBUTE
8065 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
8066 (TARGET_HARD_FLOAT_ABI
8067 ? (TARGET_DOUBLE_FLOAT
8068 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
8072 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8073 if (TARGET_ABICALLS)
8075 fprintf (asm_out_file, "\t.abicalls\n");
8076 if (TARGET_ABICALLS_PIC0)
8077 fprintf (asm_out_file, "\t.option\tpic0\n");
8080 if (flag_verbose_asm)
8081 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8083 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8086 /* Make the last instruction frame-related and note that it performs
8087 the operation described by FRAME_PATTERN. */
8090 mips_set_frame_expr (rtx frame_pattern)
8094 insn = get_last_insn ();
8095 RTX_FRAME_RELATED_P (insn) = 1;
8096 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8101 /* Return a frame-related rtx that stores REG at MEM.
8102 REG must be a single register. */
8105 mips_frame_set (rtx mem, rtx reg)
8109 /* If we're saving the return address register and the DWARF return
8110 address column differs from the hard register number, adjust the
8111 note reg to refer to the former. */
8112 if (REGNO (reg) == GP_REG_FIRST + 31
8113 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
8114 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8116 set = gen_rtx_SET (VOIDmode, mem, reg);
8117 RTX_FRAME_RELATED_P (set) = 1;
8122 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8123 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8124 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8125 static const unsigned char mips16e_s2_s8_regs[] = {
8126 30, 23, 22, 21, 20, 19, 18
8128 static const unsigned char mips16e_a0_a3_regs[] = {
8132 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8133 ordered from the uppermost in memory to the lowest in memory. */
8134 static const unsigned char mips16e_save_restore_regs[] = {
8135 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8138 /* Return the index of the lowest X in the range [0, SIZE) for which
8139 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8142 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8147 for (i = 0; i < size; i++)
8148 if (BITSET_P (mask, regs[i]))
8154 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8155 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8156 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8157 is true for all indexes (X, SIZE). */
8160 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8161 unsigned int size, unsigned int *num_regs_ptr)
8165 i = mips16e_find_first_register (*mask_ptr, regs, size);
8166 for (i++; i < size; i++)
8167 if (!BITSET_P (*mask_ptr, regs[i]))
8170 *mask_ptr |= 1 << regs[i];
8174 /* Return a simplified form of X using the register values in REG_VALUES.
8175 REG_VALUES[R] is the last value assigned to hard register R, or null
8176 if R has not been modified.
8178 This function is rather limited, but is good enough for our purposes. */
8181 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8183 x = avoid_constant_pool_reference (x);
8187 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8188 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8189 x0, GET_MODE (XEXP (x, 0)));
8192 if (ARITHMETIC_P (x))
8194 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8195 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8196 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8200 && reg_values[REGNO (x)]
8201 && !rtx_unstable_p (reg_values[REGNO (x)]))
8202 return reg_values[REGNO (x)];
8207 /* Return true if (set DEST SRC) stores an argument register into its
8208 caller-allocated save slot, storing the number of that argument
8209 register in *REGNO_PTR if so. REG_VALUES is as for
8210 mips16e_collect_propagate_value. */
8213 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8214 unsigned int *regno_ptr)
8216 unsigned int argno, regno;
8217 HOST_WIDE_INT offset, required_offset;
8220 /* Check that this is a word-mode store. */
8221 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8224 /* Check that the register being saved is an unmodified argument
8226 regno = REGNO (src);
8227 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8229 argno = regno - GP_ARG_FIRST;
8231 /* Check whether the address is an appropriate stack-pointer or
8232 frame-pointer access. */
8233 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8234 mips_split_plus (addr, &base, &offset);
8235 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8236 if (base == hard_frame_pointer_rtx)
8237 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8238 else if (base != stack_pointer_rtx)
8240 if (offset != required_offset)
8247 /* A subroutine of mips_expand_prologue, called only when generating
8248 MIPS16e SAVE instructions. Search the start of the function for any
8249 instructions that save argument registers into their caller-allocated
8250 save slots. Delete such instructions and return a value N such that
8251 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8252 instructions redundant. */
8255 mips16e_collect_argument_saves (void)
8257 rtx reg_values[FIRST_PSEUDO_REGISTER];
8258 rtx insn, next, set, dest, src;
8259 unsigned int nargs, regno;
8261 push_topmost_sequence ();
8263 memset (reg_values, 0, sizeof (reg_values));
8264 for (insn = get_insns (); insn; insn = next)
8266 next = NEXT_INSN (insn);
8273 set = PATTERN (insn);
8274 if (GET_CODE (set) != SET)
8277 dest = SET_DEST (set);
8278 src = SET_SRC (set);
8279 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8281 if (!BITSET_P (cfun->machine->frame.mask, regno))
8284 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8287 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8288 reg_values[REGNO (dest)]
8289 = mips16e_collect_propagate_value (src, reg_values);
8293 pop_topmost_sequence ();
8298 /* Return a move between register REGNO and memory location SP + OFFSET.
8299 Make the move a load if RESTORE_P, otherwise make it a frame-related
8303 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8308 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8309 reg = gen_rtx_REG (SImode, regno);
8311 ? gen_rtx_SET (VOIDmode, reg, mem)
8312 : mips_frame_set (mem, reg));
8315 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8316 The instruction must:
8318 - Allocate or deallocate SIZE bytes in total; SIZE is known
8321 - Save or restore as many registers in *MASK_PTR as possible.
8322 The instruction saves the first registers at the top of the
8323 allocated area, with the other registers below it.
8325 - Save NARGS argument registers above the allocated area.
8327 (NARGS is always zero if RESTORE_P.)
8329 The SAVE and RESTORE instructions cannot save and restore all general
8330 registers, so there may be some registers left over for the caller to
8331 handle. Destructively modify *MASK_PTR so that it contains the registers
8332 that still need to be saved or restored. The caller can save these
8333 registers in the memory immediately below *OFFSET_PTR, which is a
8334 byte offset from the bottom of the allocated stack area. */
8337 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8338 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8342 HOST_WIDE_INT offset, top_offset;
8343 unsigned int i, regno;
8346 gcc_assert (cfun->machine->frame.num_fp == 0);
8348 /* Calculate the number of elements in the PARALLEL. We need one element
8349 for the stack adjustment, one for each argument register save, and one
8350 for each additional register move. */
8352 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8353 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8356 /* Create the final PARALLEL. */
8357 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8360 /* Add the stack pointer adjustment. */
8361 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8362 plus_constant (stack_pointer_rtx,
8363 restore_p ? size : -size));
8364 RTX_FRAME_RELATED_P (set) = 1;
8365 XVECEXP (pattern, 0, n++) = set;
8367 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8368 top_offset = restore_p ? size : 0;
8370 /* Save the arguments. */
8371 for (i = 0; i < nargs; i++)
8373 offset = top_offset + i * UNITS_PER_WORD;
8374 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8375 XVECEXP (pattern, 0, n++) = set;
8378 /* Then fill in the other register moves. */
8379 offset = top_offset;
8380 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8382 regno = mips16e_save_restore_regs[i];
8383 if (BITSET_P (*mask_ptr, regno))
8385 offset -= UNITS_PER_WORD;
8386 set = mips16e_save_restore_reg (restore_p, offset, regno);
8387 XVECEXP (pattern, 0, n++) = set;
8388 *mask_ptr &= ~(1 << regno);
8392 /* Tell the caller what offset it should use for the remaining registers. */
8393 *offset_ptr = size + (offset - top_offset);
8395 gcc_assert (n == XVECLEN (pattern, 0));
8400 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8401 pointer. Return true if PATTERN matches the kind of instruction
8402 generated by mips16e_build_save_restore. If INFO is nonnull,
8403 initialize it when returning true. */
8406 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8407 struct mips16e_save_restore_info *info)
8409 unsigned int i, nargs, mask, extra;
8410 HOST_WIDE_INT top_offset, save_offset, offset;
8411 rtx set, reg, mem, base;
8414 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8417 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8418 top_offset = adjust > 0 ? adjust : 0;
8420 /* Interpret all other members of the PARALLEL. */
8421 save_offset = top_offset - UNITS_PER_WORD;
8425 for (n = 1; n < XVECLEN (pattern, 0); n++)
8427 /* Check that we have a SET. */
8428 set = XVECEXP (pattern, 0, n);
8429 if (GET_CODE (set) != SET)
8432 /* Check that the SET is a load (if restoring) or a store
8434 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8438 /* Check that the address is the sum of the stack pointer and a
8439 possibly-zero constant offset. */
8440 mips_split_plus (XEXP (mem, 0), &base, &offset);
8441 if (base != stack_pointer_rtx)
8444 /* Check that SET's other operand is a register. */
8445 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8449 /* Check for argument saves. */
8450 if (offset == top_offset + nargs * UNITS_PER_WORD
8451 && REGNO (reg) == GP_ARG_FIRST + nargs)
8453 else if (offset == save_offset)
8455 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8456 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8459 mask |= 1 << REGNO (reg);
8460 save_offset -= UNITS_PER_WORD;
8466 /* Check that the restrictions on register ranges are met. */
8468 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8469 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8470 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8471 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8475 /* Make sure that the topmost argument register is not saved twice.
8476 The checks above ensure that the same is then true for the other
8477 argument registers. */
8478 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8481 /* Pass back information, if requested. */
8484 info->nargs = nargs;
8486 info->size = (adjust > 0 ? adjust : -adjust);
8492 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8493 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8494 the null terminator. */
8497 mips16e_add_register_range (char *s, unsigned int min_reg,
8498 unsigned int max_reg)
8500 if (min_reg != max_reg)
8501 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8503 s += sprintf (s, ",%s", reg_names[min_reg]);
8507 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8508 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8511 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8513 static char buffer[300];
8515 struct mips16e_save_restore_info info;
8516 unsigned int i, end;
8519 /* Parse the pattern. */
8520 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8523 /* Add the mnemonic. */
8524 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8527 /* Save the arguments. */
8529 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8530 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8531 else if (info.nargs == 1)
8532 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8534 /* Emit the amount of stack space to allocate or deallocate. */
8535 s += sprintf (s, "%d", (int) info.size);
8537 /* Save or restore $16. */
8538 if (BITSET_P (info.mask, 16))
8539 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8541 /* Save or restore $17. */
8542 if (BITSET_P (info.mask, 17))
8543 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8545 /* Save or restore registers in the range $s2...$s8, which
8546 mips16e_s2_s8_regs lists in decreasing order. Note that this
8547 is a software register range; the hardware registers are not
8548 numbered consecutively. */
8549 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8550 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8552 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8553 mips16e_s2_s8_regs[i]);
8555 /* Save or restore registers in the range $a0...$a3. */
8556 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8557 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8559 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8560 mips16e_a0_a3_regs[end - 1]);
8562 /* Save or restore $31. */
8563 if (BITSET_P (info.mask, 31))
8564 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
8569 /* Return true if the current function has an insn that implicitly
8573 mips_function_has_gp_insn (void)
8575 /* Don't bother rechecking if we found one last time. */
8576 if (!cfun->machine->has_gp_insn_p)
8580 push_topmost_sequence ();
8581 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8582 if (USEFUL_INSN_P (insn)
8583 && (get_attr_got (insn) != GOT_UNSET
8584 || mips_small_data_pattern_p (PATTERN (insn))))
8586 cfun->machine->has_gp_insn_p = true;
8589 pop_topmost_sequence ();
8591 return cfun->machine->has_gp_insn_p;
8594 /* Return true if the current function returns its value in a floating-point
8595 register in MIPS16 mode. */
8598 mips16_cfun_returns_in_fpr_p (void)
8600 tree return_type = DECL_RESULT (current_function_decl);
8601 return (TARGET_MIPS16
8602 && TARGET_HARD_FLOAT_ABI
8603 && !aggregate_value_p (return_type, current_function_decl)
8604 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8607 /* Return the register that should be used as the global pointer
8608 within this function. Return INVALID_REGNUM if the function
8609 doesn't need a global pointer. */
8612 mips_global_pointer (void)
8616 /* $gp is always available unless we're using a GOT. */
8617 if (!TARGET_USE_GOT)
8618 return GLOBAL_POINTER_REGNUM;
8620 /* We must always provide $gp when it is used implicitly. */
8621 if (!TARGET_EXPLICIT_RELOCS)
8622 return GLOBAL_POINTER_REGNUM;
8624 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
8627 return GLOBAL_POINTER_REGNUM;
8629 /* If the function has a nonlocal goto, $gp must hold the correct
8630 global pointer for the target function. */
8631 if (crtl->has_nonlocal_goto)
8632 return GLOBAL_POINTER_REGNUM;
8634 /* There's no need to initialize $gp if it isn't referenced now,
8635 and if we can be sure that no new references will be added during
8637 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
8638 && !mips_function_has_gp_insn ())
8640 /* The function doesn't use $gp at the moment. If we're generating
8641 -call_nonpic code, no new uses will be introduced during or after
8643 if (TARGET_ABICALLS_PIC0)
8644 return INVALID_REGNUM;
8646 /* We need to handle the following implicit gp references:
8648 - Reload can sometimes introduce constant pool references
8649 into a function that otherwise didn't need them. For example,
8650 suppose we have an instruction like:
8652 (set (reg:DF R1) (float:DF (reg:SI R2)))
8654 If R2 turns out to be constant such as 1, the instruction may
8655 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8656 the option of using this constant if R2 doesn't get allocated
8659 In cases like these, reload will have added the constant to the
8660 pool but no instruction will yet refer to it.
8662 - MIPS16 functions that return in FPRs need to call an
8663 external libgcc routine. */
8664 if (!crtl->uses_const_pool
8665 && !mips16_cfun_returns_in_fpr_p ())
8666 return INVALID_REGNUM;
8669 /* We need a global pointer, but perhaps we can use a call-clobbered
8670 register instead of $gp. */
8671 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8672 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8673 if (!df_regs_ever_live_p (regno)
8674 && call_really_used_regs[regno]
8675 && !fixed_regs[regno]
8676 && regno != PIC_FUNCTION_ADDR_REGNUM)
8679 return GLOBAL_POINTER_REGNUM;
8682 /* Return true if REGNO is a register that is ordinarily call-clobbered
8683 but must nevertheless be preserved by an interrupt handler. */
8686 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8688 if (MD_REG_P (regno))
8691 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8694 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8696 /* $0 is hard-wired. */
8697 if (regno == GP_REG_FIRST)
8700 /* The interrupt handler can treat kernel registers as
8701 scratch registers. */
8702 if (KERNEL_REG_P (regno))
8705 /* The function will return the stack pointer to its original value
8707 if (regno == STACK_POINTER_REGNUM)
8710 /* Otherwise, return true for registers that aren't ordinarily
8712 return call_really_used_regs[regno];
8718 /* Return true if the current function should treat register REGNO
8722 mips_cfun_call_saved_reg_p (unsigned int regno)
8724 /* Interrupt handlers need to save extra registers. */
8725 if (cfun->machine->interrupt_handler_p
8726 && mips_interrupt_extra_call_saved_reg_p (regno))
8729 /* call_insns preserve $28 unless they explicitly say otherwise,
8730 so call_really_used_regs[] treats $28 as call-saved. However,
8731 we want the ABI property rather than the default call_insn
8733 return (regno == GLOBAL_POINTER_REGNUM
8734 ? TARGET_CALL_SAVED_GP
8735 : !call_really_used_regs[regno]);
8738 /* Return true if the function body might clobber register REGNO.
8739 We know that REGNO is call-saved. */
8742 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
8744 /* Some functions should be treated as clobbering all call-saved
8746 if (crtl->saves_all_registers)
8749 /* DF handles cases where a register is explicitly referenced in
8750 the rtl. Incoming values are passed in call-clobbered registers,
8751 so we can assume that any live call-saved register is set within
8753 if (df_regs_ever_live_p (regno))
8756 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8757 These clobbers are not explicit in the rtl. */
8758 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8761 /* If we're using a call-saved global pointer, the function's
8762 prologue will need to set it up. */
8763 if (cfun->machine->global_pointer == regno)
8766 /* The function's prologue will need to set the frame pointer if
8767 frame_pointer_needed. */
8768 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
8771 /* If a MIPS16 function returns a value in FPRs, its epilogue
8772 will need to call an external libgcc routine. This yet-to-be
8773 generated call_insn will clobber $31. */
8774 if (regno == GP_REG_FIRST + 31 && mips16_cfun_returns_in_fpr_p ())
8777 /* If REGNO is ordinarily call-clobbered, we must assume that any
8778 called function could modify it. */
8779 if (cfun->machine->interrupt_handler_p
8780 && !current_function_is_leaf
8781 && mips_interrupt_extra_call_saved_reg_p (regno))
8787 /* Return true if the current function must save register REGNO. */
8790 mips_save_reg_p (unsigned int regno)
8792 if (mips_cfun_call_saved_reg_p (regno))
8794 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
8797 /* Save both registers in an FPR pair if either one is used. This is
8798 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8799 register to be used without the even register. */
8800 if (FP_REG_P (regno)
8801 && MAX_FPRS_PER_FMT == 2
8802 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
8806 /* We need to save the incoming return address if __builtin_eh_return
8807 is being used to set a different return address. */
8808 if (regno == GP_REG_FIRST + 31 && crtl->calls_eh_return)
8814 /* Populate the current function's mips_frame_info structure.
8816 MIPS stack frames look like:
8818 +-------------------------------+
8820 | incoming stack arguments |
8822 +-------------------------------+
8824 | caller-allocated save area |
8825 A | for register arguments |
8827 +-------------------------------+ <-- incoming stack pointer
8829 | callee-allocated save area |
8830 B | for arguments that are |
8831 | split between registers and |
8834 +-------------------------------+ <-- arg_pointer_rtx
8836 C | callee-allocated save area |
8837 | for register varargs |
8839 +-------------------------------+ <-- frame_pointer_rtx
8840 | | + cop0_sp_offset
8841 | COP0 reg save area | + UNITS_PER_WORD
8843 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
8844 | | + UNITS_PER_WORD
8845 | accumulator save area |
8847 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
8848 | | + UNITS_PER_HWFPVALUE
8851 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
8852 | | + UNITS_PER_WORD
8855 +-------------------------------+ <-- frame_pointer_rtx with
8856 | | \ -fstack-protector
8857 | local variables | | var_size
8859 +-------------------------------+
8861 | $gp save area | | cprestore_size
8863 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8865 | outgoing stack arguments | |
8867 +-------------------------------+ | args_size
8869 | caller-allocated save area | |
8870 | for register arguments | |
8872 +-------------------------------+ <-- stack_pointer_rtx
8873 frame_pointer_rtx without
8875 hard_frame_pointer_rtx for
8878 At least two of A, B and C will be empty.
8880 Dynamic stack allocations such as alloca insert data at point P.
8881 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8882 hard_frame_pointer_rtx unchanged. */
8885 mips_compute_frame_info (void)
8887 struct mips_frame_info *frame;
8888 HOST_WIDE_INT offset, size;
8889 unsigned int regno, i;
8891 /* Set this function's interrupt properties. */
8892 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
8895 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
8896 else if (TARGET_HARD_FLOAT)
8897 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
8898 else if (TARGET_MIPS16)
8899 error ("interrupt handlers cannot be MIPS16 functions");
8902 cfun->machine->interrupt_handler_p = true;
8903 cfun->machine->use_shadow_register_set_p =
8904 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
8905 cfun->machine->keep_interrupts_masked_p =
8906 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
8907 cfun->machine->use_debug_exception_return_p =
8908 mips_use_debug_exception_return_p (TREE_TYPE
8909 (current_function_decl));
8913 frame = &cfun->machine->frame;
8914 memset (frame, 0, sizeof (*frame));
8915 size = get_frame_size ();
8917 cfun->machine->global_pointer = mips_global_pointer ();
8919 /* The first two blocks contain the outgoing argument area and the $gp save
8920 slot. This area isn't needed in leaf functions, but if the
8921 target-independent frame size is nonzero, we have already committed to
8922 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
8923 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
8925 /* The MIPS 3.0 linker does not like functions that dynamically
8926 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8927 looks like we are trying to create a second frame pointer to the
8928 function, so allocate some stack space to make it happy. */
8929 if (cfun->calls_alloca)
8930 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8932 frame->args_size = 0;
8933 frame->cprestore_size = 0;
8937 frame->args_size = crtl->outgoing_args_size;
8938 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
8940 offset = frame->args_size + frame->cprestore_size;
8942 /* Move above the local variables. */
8943 frame->var_size = MIPS_STACK_ALIGN (size);
8944 offset += frame->var_size;
8946 /* Find out which GPRs we need to save. */
8947 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8948 if (mips_save_reg_p (regno))
8951 frame->mask |= 1 << (regno - GP_REG_FIRST);
8954 /* If this function calls eh_return, we must also save and restore the
8955 EH data registers. */
8956 if (crtl->calls_eh_return)
8957 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8960 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8963 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8964 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8965 save all later registers too. */
8966 if (GENERATE_MIPS16E_SAVE_RESTORE)
8968 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8969 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8970 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8971 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8974 /* Move above the GPR save area. */
8975 if (frame->num_gp > 0)
8977 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8978 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8981 /* Find out which FPRs we need to save. This loop must iterate over
8982 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
8983 if (TARGET_HARD_FLOAT)
8984 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8985 if (mips_save_reg_p (regno))
8987 frame->num_fp += MAX_FPRS_PER_FMT;
8988 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8991 /* Move above the FPR save area. */
8992 if (frame->num_fp > 0)
8994 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8995 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8998 /* Add in space for the interrupt context information. */
8999 if (cfun->machine->interrupt_handler_p)
9002 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9005 frame->acc_mask |= (1 << 0);
9008 /* Check accumulators 1, 2, 3. */
9009 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9010 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9013 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9016 /* All interrupt context functions need space to preserve STATUS. */
9017 frame->num_cop0_regs++;
9019 /* If we don't keep interrupts masked, we need to save EPC. */
9020 if (!cfun->machine->keep_interrupts_masked_p)
9021 frame->num_cop0_regs++;
9024 /* Move above the accumulator save area. */
9025 if (frame->num_acc > 0)
9027 /* Each accumulator needs 2 words. */
9028 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9029 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9032 /* Move above the COP0 register save area. */
9033 if (frame->num_cop0_regs > 0)
9035 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9036 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9039 /* Move above the callee-allocated varargs save area. */
9040 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9041 frame->arg_pointer_offset = offset;
9043 /* Move above the callee-allocated area for pretend stack arguments. */
9044 offset += crtl->args.pretend_args_size;
9045 frame->total_size = offset;
9047 /* Work out the offsets of the save areas from the top of the frame. */
9048 if (frame->gp_sp_offset > 0)
9049 frame->gp_save_offset = frame->gp_sp_offset - offset;
9050 if (frame->fp_sp_offset > 0)
9051 frame->fp_save_offset = frame->fp_sp_offset - offset;
9052 if (frame->acc_sp_offset > 0)
9053 frame->acc_save_offset = frame->acc_sp_offset - offset;
9054 if (frame->num_cop0_regs > 0)
9055 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9057 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9058 arguments. This tends to increase the chances of using unextended
9059 instructions for local variables and incoming arguments. */
9061 frame->hard_frame_pointer_offset = frame->args_size;
9064 /* Return the style of GP load sequence that is being used for the
9065 current function. */
9067 enum mips_loadgp_style
9068 mips_current_loadgp_style (void)
9070 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9076 if (TARGET_ABSOLUTE_ABICALLS)
9077 return LOADGP_ABSOLUTE;
9079 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9082 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9085 mips_frame_pointer_required (void)
9087 /* If the function contains dynamic stack allocations, we need to
9088 use the frame pointer to access the static parts of the frame. */
9089 if (cfun->calls_alloca)
9092 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9093 reload may be unable to compute the address of a local variable,
9094 since there is no way to add a large constant to the stack pointer
9095 without using a second temporary register. */
9098 mips_compute_frame_info ();
9099 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9106 /* Make sure that we're not trying to eliminate to the wrong hard frame
9110 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9112 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9115 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9116 or argument pointer. TO is either the stack pointer or hard frame
9120 mips_initial_elimination_offset (int from, int to)
9122 HOST_WIDE_INT offset;
9124 mips_compute_frame_info ();
9126 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9129 case FRAME_POINTER_REGNUM:
9130 if (FRAME_GROWS_DOWNWARD)
9131 offset = (cfun->machine->frame.args_size
9132 + cfun->machine->frame.cprestore_size
9133 + cfun->machine->frame.var_size);
9138 case ARG_POINTER_REGNUM:
9139 offset = cfun->machine->frame.arg_pointer_offset;
9146 if (to == HARD_FRAME_POINTER_REGNUM)
9147 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9152 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9155 mips_extra_live_on_entry (bitmap regs)
9159 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9160 the global pointer. */
9161 if (!TARGET_ABSOLUTE_ABICALLS)
9162 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9164 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9165 the global pointer. */
9167 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9169 /* See the comment above load_call<mode> for details. */
9170 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9174 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9178 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9183 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
9186 /* Emit code to change the current function's return address to
9187 ADDRESS. SCRATCH is available as a scratch register, if needed.
9188 ADDRESS and SCRATCH are both word-mode GPRs. */
9191 mips_set_return_address (rtx address, rtx scratch)
9195 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
9196 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9197 cfun->machine->frame.gp_sp_offset);
9198 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9201 /* Return a MEM rtx for the cprestore slot, using TEMP as a temporary base
9202 register if need be. */
9205 mips_cprestore_slot (rtx temp)
9207 const struct mips_frame_info *frame;
9209 HOST_WIDE_INT offset;
9211 frame = &cfun->machine->frame;
9212 if (frame_pointer_needed)
9214 base = hard_frame_pointer_rtx;
9215 offset = frame->args_size - frame->hard_frame_pointer_offset;
9219 base = stack_pointer_rtx;
9220 offset = frame->args_size;
9222 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9225 /* Restore $gp from its save slot, using TEMP as a temporary base register
9226 if need be. This function is for o32 and o64 abicalls only. */
9229 mips_restore_gp (rtx temp)
9231 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
9233 if (cfun->machine->global_pointer == INVALID_REGNUM)
9238 mips_emit_move (temp, mips_cprestore_slot (temp));
9239 mips_emit_move (pic_offset_table_rtx, temp);
9242 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp));
9243 if (!TARGET_EXPLICIT_RELOCS)
9244 emit_insn (gen_blockage ());
9247 /* A function to save or store a register. The first argument is the
9248 register and the second is the stack slot. */
9249 typedef void (*mips_save_restore_fn) (rtx, rtx);
9251 /* Use FN to save or restore register REGNO. MODE is the register's
9252 mode and OFFSET is the offset of its save slot from the current
9256 mips_save_restore_reg (enum machine_mode mode, int regno,
9257 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9261 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9262 fn (gen_rtx_REG (mode, regno), mem);
9265 /* Call FN for each accumlator that is saved by the current function.
9266 SP_OFFSET is the offset of the current stack pointer from the start
9270 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9272 HOST_WIDE_INT offset;
9275 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9276 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9278 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9279 offset -= UNITS_PER_WORD;
9280 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9281 offset -= UNITS_PER_WORD;
9284 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9285 if (BITSET_P (cfun->machine->frame.acc_mask,
9286 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9288 mips_save_restore_reg (word_mode, regno, offset, fn);
9289 offset -= UNITS_PER_WORD;
9293 /* Call FN for each register that is saved by the current function.
9294 SP_OFFSET is the offset of the current stack pointer from the start
9298 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9299 mips_save_restore_fn fn)
9301 enum machine_mode fpr_mode;
9302 HOST_WIDE_INT offset;
9305 /* Save registers starting from high to low. The debuggers prefer at least
9306 the return register be stored at func+4, and also it allows us not to
9307 need a nop in the epilogue if at least one register is reloaded in
9308 addition to return address. */
9309 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9310 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9311 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9313 mips_save_restore_reg (word_mode, regno, offset, fn);
9314 offset -= UNITS_PER_WORD;
9317 /* This loop must iterate over the same space as its companion in
9318 mips_compute_frame_info. */
9319 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9320 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9321 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9322 regno >= FP_REG_FIRST;
9323 regno -= MAX_FPRS_PER_FMT)
9324 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9326 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9327 offset -= GET_MODE_SIZE (fpr_mode);
9331 /* If we're generating n32 or n64 abicalls, and the current function
9332 does not use $28 as its global pointer, emit a cplocal directive.
9333 Use pic_offset_table_rtx as the argument to the directive. */
9336 mips_output_cplocal (void)
9338 if (!TARGET_EXPLICIT_RELOCS
9339 && cfun->machine->global_pointer != INVALID_REGNUM
9340 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9341 output_asm_insn (".cplocal %+", 0);
9344 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9347 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9351 #ifdef SDB_DEBUGGING_INFO
9352 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9353 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9356 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9357 floating-point arguments. */
9359 && TARGET_HARD_FLOAT_ABI
9360 && crtl->args.info.fp_code != 0)
9361 mips16_build_function_stub ();
9363 /* Get the function name the same way that toplev.c does before calling
9364 assemble_start_function. This is needed so that the name used here
9365 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9366 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9367 mips_start_function_definition (fnname, TARGET_MIPS16);
9369 /* Stop mips_file_end from treating this function as external. */
9370 if (TARGET_IRIX && mips_abi == ABI_32)
9371 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
9373 /* Output MIPS-specific frame information. */
9374 if (!flag_inhibit_size_directive)
9376 const struct mips_frame_info *frame;
9378 frame = &cfun->machine->frame;
9380 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9382 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9383 "# vars= " HOST_WIDE_INT_PRINT_DEC
9385 ", args= " HOST_WIDE_INT_PRINT_DEC
9386 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9387 reg_names[frame_pointer_needed
9388 ? HARD_FRAME_POINTER_REGNUM
9389 : STACK_POINTER_REGNUM],
9390 (frame_pointer_needed
9391 ? frame->total_size - frame->hard_frame_pointer_offset
9392 : frame->total_size),
9393 reg_names[GP_REG_FIRST + 31],
9395 frame->num_gp, frame->num_fp,
9397 frame->cprestore_size);
9399 /* .mask MASK, OFFSET. */
9400 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9401 frame->mask, frame->gp_save_offset);
9403 /* .fmask MASK, OFFSET. */
9404 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9405 frame->fmask, frame->fp_save_offset);
9408 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9409 Also emit the ".set noreorder; .set nomacro" sequence for functions
9411 if (mips_current_loadgp_style () == LOADGP_OLDABI)
9415 /* This is a fixed-form sequence. The position of the
9416 first two instructions is important because of the
9417 way _gp_disp is defined. */
9418 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9419 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9420 output_asm_insn ("sll\t$2,16", 0);
9421 output_asm_insn ("addu\t$2,$3", 0);
9425 /* .cpload must be in a .set noreorder but not a
9426 .set nomacro block. */
9427 mips_push_asm_switch (&mips_noreorder);
9428 output_asm_insn (".cpload\t%^", 0);
9429 if (!cfun->machine->all_noreorder_p)
9430 mips_pop_asm_switch (&mips_noreorder);
9432 mips_push_asm_switch (&mips_nomacro);
9435 else if (cfun->machine->all_noreorder_p)
9437 mips_push_asm_switch (&mips_noreorder);
9438 mips_push_asm_switch (&mips_nomacro);
9441 /* Tell the assembler which register we're using as the global
9442 pointer. This is needed for thunks, since they can use either
9443 explicit relocs or assembler macros. */
9444 mips_output_cplocal ();
9447 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9450 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9451 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9455 /* Reinstate the normal $gp. */
9456 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9457 mips_output_cplocal ();
9459 if (cfun->machine->all_noreorder_p)
9461 mips_pop_asm_switch (&mips_nomacro);
9462 mips_pop_asm_switch (&mips_noreorder);
9465 /* Get the function name the same way that toplev.c does before calling
9466 assemble_start_function. This is needed so that the name used here
9467 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9468 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9469 mips_end_function_definition (fnname);
9472 /* Save register REG to MEM. Make the instruction frame-related. */
9475 mips_save_reg (rtx reg, rtx mem)
9477 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9481 if (mips_split_64bit_move_p (mem, reg))
9482 mips_split_doubleword_move (mem, reg);
9484 mips_emit_move (mem, reg);
9486 x1 = mips_frame_set (mips_subword (mem, false),
9487 mips_subword (reg, false));
9488 x2 = mips_frame_set (mips_subword (mem, true),
9489 mips_subword (reg, true));
9490 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9494 if (REGNO (reg) == HI_REGNUM)
9497 emit_insn (gen_mfhidi_ti (MIPS_PROLOGUE_TEMP (DImode),
9498 gen_rtx_REG (TImode, MD_REG_FIRST)));
9500 emit_insn (gen_mfhisi_di (MIPS_PROLOGUE_TEMP (SImode),
9501 gen_rtx_REG (DImode, MD_REG_FIRST)));
9502 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9504 else if ((TARGET_MIPS16
9505 && REGNO (reg) != GP_REG_FIRST + 31
9506 && !M16_REG_P (REGNO (reg)))
9507 || ACC_REG_P (REGNO (reg)))
9509 /* If the register has no direct store instruction, move it
9510 through a temporary. Note that there's a special MIPS16
9511 instruction to save $31. */
9512 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
9513 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9516 mips_emit_move (mem, reg);
9518 mips_set_frame_expr (mips_frame_set (mem, reg));
9522 /* The __gnu_local_gp symbol. */
9524 static GTY(()) rtx mips_gnu_local_gp;
9526 /* If we're generating n32 or n64 abicalls, emit instructions
9527 to set up the global pointer. */
9530 mips_emit_loadgp (void)
9532 rtx addr, offset, incoming_address, base, index, pic_reg;
9534 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9535 switch (mips_current_loadgp_style ())
9537 case LOADGP_ABSOLUTE:
9538 if (mips_gnu_local_gp == NULL)
9540 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9541 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9543 emit_insn (Pmode == SImode
9544 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9545 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9549 /* Added by mips_output_function_prologue. */
9553 addr = XEXP (DECL_RTL (current_function_decl), 0);
9554 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9555 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9556 emit_insn (Pmode == SImode
9557 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9558 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9562 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9563 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9564 emit_insn (Pmode == SImode
9565 ? gen_loadgp_rtp_si (pic_reg, base, index)
9566 : gen_loadgp_rtp_di (pic_reg, base, index));
9574 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9576 /* Emit a blockage if there are implicit uses of the GP register.
9577 This includes profiled functions, because FUNCTION_PROFILE uses
9579 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9580 emit_insn (gen_loadgp_blockage ());
9583 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9586 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9588 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9591 /* Expand the "prologue" pattern. */
9594 mips_expand_prologue (void)
9596 const struct mips_frame_info *frame;
9601 if (cfun->machine->global_pointer != INVALID_REGNUM)
9602 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9604 frame = &cfun->machine->frame;
9605 size = frame->total_size;
9607 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9608 bytes beforehand; this is enough to cover the register save area
9609 without going out of range. */
9610 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
9611 || frame->num_cop0_regs > 0)
9613 HOST_WIDE_INT step1;
9615 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9616 if (GENERATE_MIPS16E_SAVE_RESTORE)
9618 HOST_WIDE_INT offset;
9619 unsigned int mask, regno;
9621 /* Try to merge argument stores into the save instruction. */
9622 nargs = mips16e_collect_argument_saves ();
9624 /* Build the save instruction. */
9626 insn = mips16e_build_save_restore (false, &mask, &offset,
9628 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9631 /* Check if we need to save other registers. */
9632 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9633 if (BITSET_P (mask, regno - GP_REG_FIRST))
9635 offset -= UNITS_PER_WORD;
9636 mips_save_restore_reg (word_mode, regno,
9637 offset, mips_save_reg);
9642 if (cfun->machine->interrupt_handler_p)
9644 HOST_WIDE_INT offset;
9647 /* If this interrupt is using a shadow register set, we need to
9648 get the stack pointer from the previous register set. */
9649 if (cfun->machine->use_shadow_register_set_p)
9650 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
9651 stack_pointer_rtx));
9653 if (!cfun->machine->keep_interrupts_masked_p)
9655 /* Move from COP0 Cause to K0. */
9656 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
9657 gen_rtx_REG (SImode,
9658 COP0_CAUSE_REG_NUM)));
9659 /* Move from COP0 EPC to K1. */
9660 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9661 gen_rtx_REG (SImode,
9662 COP0_EPC_REG_NUM)));
9665 /* Allocate the first part of the frame. */
9666 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
9668 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9671 /* Start at the uppermost location for saving. */
9672 offset = frame->cop0_sp_offset - size;
9673 if (!cfun->machine->keep_interrupts_masked_p)
9675 /* Push EPC into its stack slot. */
9676 mem = gen_frame_mem (word_mode,
9677 plus_constant (stack_pointer_rtx,
9679 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
9680 offset -= UNITS_PER_WORD;
9683 /* Move from COP0 Status to K1. */
9684 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9685 gen_rtx_REG (SImode,
9686 COP0_STATUS_REG_NUM)));
9688 /* Right justify the RIPL in k0. */
9689 if (!cfun->machine->keep_interrupts_masked_p)
9690 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
9691 gen_rtx_REG (SImode, K0_REG_NUM),
9692 GEN_INT (CAUSE_IPL)));
9694 /* Push Status into its stack slot. */
9695 mem = gen_frame_mem (word_mode,
9696 plus_constant (stack_pointer_rtx, offset));
9697 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
9698 offset -= UNITS_PER_WORD;
9700 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
9701 if (!cfun->machine->keep_interrupts_masked_p)
9702 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9705 gen_rtx_REG (SImode, K0_REG_NUM)));
9707 if (!cfun->machine->keep_interrupts_masked_p)
9708 /* Enable interrupts by clearing the KSU ERL and EXL bits.
9709 IE is already the correct value, so we don't have to do
9710 anything explicit. */
9711 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9714 gen_rtx_REG (SImode, GP_REG_FIRST)));
9716 /* Disable interrupts by clearing the KSU, ERL, EXL,
9718 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9721 gen_rtx_REG (SImode, GP_REG_FIRST)));
9725 insn = gen_add3_insn (stack_pointer_rtx,
9728 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9731 mips_for_each_saved_acc (size, mips_save_reg);
9732 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
9736 /* Allocate the rest of the frame. */
9739 if (SMALL_OPERAND (-size))
9740 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
9742 GEN_INT (-size)))) = 1;
9745 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
9748 /* There are no instructions to add or subtract registers
9749 from the stack pointer, so use the frame pointer as a
9750 temporary. We should always be using a frame pointer
9751 in this case anyway. */
9752 gcc_assert (frame_pointer_needed);
9753 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9754 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
9755 hard_frame_pointer_rtx,
9756 MIPS_PROLOGUE_TEMP (Pmode)));
9757 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
9760 emit_insn (gen_sub3_insn (stack_pointer_rtx,
9762 MIPS_PROLOGUE_TEMP (Pmode)));
9764 /* Describe the combined effect of the previous instructions. */
9766 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9767 plus_constant (stack_pointer_rtx, -size)));
9771 /* Set up the frame pointer, if we're using one. */
9772 if (frame_pointer_needed)
9774 HOST_WIDE_INT offset;
9776 offset = frame->hard_frame_pointer_offset;
9779 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9780 RTX_FRAME_RELATED_P (insn) = 1;
9782 else if (SMALL_OPERAND (offset))
9784 insn = gen_add3_insn (hard_frame_pointer_rtx,
9785 stack_pointer_rtx, GEN_INT (offset));
9786 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9790 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
9791 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9792 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
9793 hard_frame_pointer_rtx,
9794 MIPS_PROLOGUE_TEMP (Pmode)));
9796 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
9797 plus_constant (stack_pointer_rtx, offset)));
9801 mips_emit_loadgp ();
9803 /* Initialize the $gp save slot. */
9804 if (frame->cprestore_size > 0
9805 && cfun->machine->global_pointer != INVALID_REGNUM)
9808 mips_emit_move (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9810 else if (TARGET_ABICALLS_PIC2)
9811 emit_insn (gen_cprestore (GEN_INT (frame->args_size)));
9813 emit_move_insn (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9814 pic_offset_table_rtx);
9817 /* We need to search back to the last use of K0 or K1. */
9818 if (cfun->machine->interrupt_handler_p)
9820 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
9822 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
9824 /* Emit a move from K1 to COP0 Status after insn. */
9825 gcc_assert (insn != NULL_RTX);
9826 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
9827 gen_rtx_REG (SImode, K1_REG_NUM)),
9831 /* If we are profiling, make sure no instructions are scheduled before
9832 the call to mcount. */
9834 emit_insn (gen_blockage ());
9837 /* Emit instructions to restore register REG from slot MEM. */
9840 mips_restore_reg (rtx reg, rtx mem)
9842 /* There's no MIPS16 instruction to load $31 directly. Load into
9843 $7 instead and adjust the return insn appropriately. */
9844 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
9845 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
9847 if (REGNO (reg) == HI_REGNUM)
9849 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9851 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9852 MIPS_EPILOGUE_TEMP (DImode),
9853 gen_rtx_REG (DImode, LO_REGNUM)));
9855 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9856 MIPS_EPILOGUE_TEMP (SImode),
9857 gen_rtx_REG (SImode, LO_REGNUM)));
9859 else if ((TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
9860 || ACC_REG_P (REGNO (reg)))
9862 /* Can't restore directly; move through a temporary. */
9863 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9864 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
9867 mips_emit_move (reg, mem);
9870 /* Emit any instructions needed before a return. */
9873 mips_expand_before_return (void)
9875 /* When using a call-clobbered gp, we start out with unified call
9876 insns that include instructions to restore the gp. We then split
9877 these unified calls after reload. These split calls explicitly
9878 clobber gp, so there is no need to define
9879 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
9881 For consistency, we should also insert an explicit clobber of $28
9882 before return insns, so that the post-reload optimizers know that
9883 the register is not live on exit. */
9884 if (TARGET_CALL_CLOBBERED_GP)
9885 emit_clobber (pic_offset_table_rtx);
9888 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
9892 mips_expand_epilogue (bool sibcall_p)
9894 const struct mips_frame_info *frame;
9895 HOST_WIDE_INT step1, step2;
9896 rtx base, target, insn;
9898 if (!sibcall_p && mips_can_use_return_insn ())
9900 emit_jump_insn (gen_return ());
9904 /* In MIPS16 mode, if the return value should go into a floating-point
9905 register, we need to call a helper routine to copy it over. */
9906 if (mips16_cfun_returns_in_fpr_p ())
9907 mips16_copy_fpr_return_value ();
9909 /* Split the frame into two. STEP1 is the amount of stack we should
9910 deallocate before restoring the registers. STEP2 is the amount we
9911 should deallocate afterwards.
9913 Start off by assuming that no registers need to be restored. */
9914 frame = &cfun->machine->frame;
9915 step1 = frame->total_size;
9918 /* Work out which register holds the frame address. */
9919 if (!frame_pointer_needed)
9920 base = stack_pointer_rtx;
9923 base = hard_frame_pointer_rtx;
9924 step1 -= frame->hard_frame_pointer_offset;
9927 /* If we need to restore registers, deallocate as much stack as
9928 possible in the second step without going out of range. */
9929 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
9930 || frame->num_cop0_regs > 0)
9932 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
9936 /* Set TARGET to BASE + STEP1. */
9942 /* Get an rtx for STEP1 that we can add to BASE. */
9943 adjust = GEN_INT (step1);
9944 if (!SMALL_OPERAND (step1))
9946 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
9947 adjust = MIPS_EPILOGUE_TEMP (Pmode);
9950 /* Normal mode code can copy the result straight into $sp. */
9952 target = stack_pointer_rtx;
9954 emit_insn (gen_add3_insn (target, base, adjust));
9957 /* Copy TARGET into the stack pointer. */
9958 if (target != stack_pointer_rtx)
9959 mips_emit_move (stack_pointer_rtx, target);
9961 /* If we're using addressing macros, $gp is implicitly used by all
9962 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
9964 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
9965 emit_insn (gen_blockage ());
9967 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
9969 unsigned int regno, mask;
9970 HOST_WIDE_INT offset;
9973 /* Generate the restore instruction. */
9975 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
9977 /* Restore any other registers manually. */
9978 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9979 if (BITSET_P (mask, regno - GP_REG_FIRST))
9981 offset -= UNITS_PER_WORD;
9982 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
9985 /* Restore the remaining registers and deallocate the final bit
9987 emit_insn (restore);
9991 /* Restore the registers. */
9992 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
9993 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
9996 if (cfun->machine->interrupt_handler_p)
9998 HOST_WIDE_INT offset;
10001 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10002 if (!cfun->machine->keep_interrupts_masked_p)
10004 /* Restore the original EPC. */
10005 mem = gen_frame_mem (word_mode,
10006 plus_constant (stack_pointer_rtx, offset));
10007 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10008 offset -= UNITS_PER_WORD;
10010 /* Move to COP0 EPC. */
10011 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10012 gen_rtx_REG (SImode, K0_REG_NUM)));
10015 /* Restore the original Status. */
10016 mem = gen_frame_mem (word_mode,
10017 plus_constant (stack_pointer_rtx, offset));
10018 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10019 offset -= UNITS_PER_WORD;
10021 /* If we don't use shoadow register set, we need to update SP. */
10022 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10023 emit_insn (gen_add3_insn (stack_pointer_rtx,
10027 /* Move to COP0 Status. */
10028 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10029 gen_rtx_REG (SImode, K0_REG_NUM)));
10033 /* Deallocate the final bit of the frame. */
10035 emit_insn (gen_add3_insn (stack_pointer_rtx,
10041 /* Add in the __builtin_eh_return stack adjustment. We need to
10042 use a temporary in MIPS16 code. */
10043 if (crtl->calls_eh_return)
10047 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10048 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10049 MIPS_EPILOGUE_TEMP (Pmode),
10050 EH_RETURN_STACKADJ_RTX));
10051 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10054 emit_insn (gen_add3_insn (stack_pointer_rtx,
10056 EH_RETURN_STACKADJ_RTX));
10061 mips_expand_before_return ();
10062 if (cfun->machine->interrupt_handler_p)
10064 /* Interrupt handlers generate eret or deret. */
10065 if (cfun->machine->use_debug_exception_return_p)
10066 emit_jump_insn (gen_mips_deret ());
10068 emit_jump_insn (gen_mips_eret ());
10072 unsigned int regno;
10074 /* When generating MIPS16 code, the normal
10075 mips_for_each_saved_gpr_and_fpr path will restore the return
10076 address into $7 rather than $31. */
10078 && !GENERATE_MIPS16E_SAVE_RESTORE
10079 && BITSET_P (frame->mask, 31))
10080 regno = GP_REG_FIRST + 7;
10082 regno = GP_REG_FIRST + 31;
10083 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10087 /* Search from the beginning to the first use of K0 or K1. */
10088 if (cfun->machine->interrupt_handler_p
10089 && !cfun->machine->keep_interrupts_masked_p)
10091 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10093 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10095 gcc_assert (insn != NULL_RTX);
10096 /* Insert disable interrupts before the first use of K0 or K1. */
10097 emit_insn_before (gen_mips_di (), insn);
10098 emit_insn_before (gen_mips_ehb (), insn);
10102 /* Return nonzero if this function is known to have a null epilogue.
10103 This allows the optimizer to omit jumps to jumps if no stack
10107 mips_can_use_return_insn (void)
10109 /* Interrupt handlers need to go through the epilogue. */
10110 if (cfun->machine->interrupt_handler_p)
10113 if (!reload_completed)
10119 /* In MIPS16 mode, a function that returns a floating-point value
10120 needs to arrange to copy the return value into the floating-point
10122 if (mips16_cfun_returns_in_fpr_p ())
10125 return cfun->machine->frame.total_size == 0;
10128 /* Return true if register REGNO can store a value of mode MODE.
10129 The result of this function is cached in mips_hard_regno_mode_ok. */
10132 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10135 enum mode_class mclass;
10137 if (mode == CCV2mode)
10138 return (ISA_HAS_8CC
10139 && ST_REG_P (regno)
10140 && (regno - ST_REG_FIRST) % 2 == 0);
10142 if (mode == CCV4mode)
10143 return (ISA_HAS_8CC
10144 && ST_REG_P (regno)
10145 && (regno - ST_REG_FIRST) % 4 == 0);
10147 if (mode == CCmode)
10150 return regno == FPSW_REGNUM;
10152 return (ST_REG_P (regno)
10153 || GP_REG_P (regno)
10154 || FP_REG_P (regno));
10157 size = GET_MODE_SIZE (mode);
10158 mclass = GET_MODE_CLASS (mode);
10160 if (GP_REG_P (regno))
10161 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10163 if (FP_REG_P (regno)
10164 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10165 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10167 /* Allow TFmode for CCmode reloads. */
10168 if (mode == TFmode && ISA_HAS_8CC)
10171 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10172 if (TARGET_LOONGSON_VECTORS
10173 && (mode == V2SImode
10174 || mode == V4HImode
10175 || mode == V8QImode
10176 || mode == DImode))
10179 if (mclass == MODE_FLOAT
10180 || mclass == MODE_COMPLEX_FLOAT
10181 || mclass == MODE_VECTOR_FLOAT)
10182 return size <= UNITS_PER_FPVALUE;
10184 /* Allow integer modes that fit into a single register. We need
10185 to put integers into FPRs when using instructions like CVT
10186 and TRUNC. There's no point allowing sizes smaller than a word,
10187 because the FPU has no appropriate load/store instructions. */
10188 if (mclass == MODE_INT)
10189 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10192 if (ACC_REG_P (regno)
10193 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10195 if (MD_REG_P (regno))
10197 /* After a multiplication or division, clobbering HI makes
10198 the value of LO unpredictable, and vice versa. This means
10199 that, for all interesting cases, HI and LO are effectively
10202 We model this by requiring that any value that uses HI
10204 if (size <= UNITS_PER_WORD * 2)
10205 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10209 /* DSP accumulators do not have the same restrictions as
10210 HI and LO, so we can treat them as normal doubleword
10212 if (size <= UNITS_PER_WORD)
10215 if (size <= UNITS_PER_WORD * 2
10216 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10221 if (ALL_COP_REG_P (regno))
10222 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10224 if (regno == GOT_VERSION_REGNUM)
10225 return mode == SImode;
10230 /* Implement HARD_REGNO_NREGS. */
10233 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10235 if (ST_REG_P (regno))
10236 /* The size of FP status registers is always 4, because they only hold
10237 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10238 return (GET_MODE_SIZE (mode) + 3) / 4;
10240 if (FP_REG_P (regno))
10241 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10243 /* All other registers are word-sized. */
10244 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10247 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10248 in mips_hard_regno_nregs. */
10251 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10257 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10258 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10260 size = MIN (size, 4);
10261 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10263 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10265 size = MIN (size, UNITS_PER_FPREG);
10266 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10268 if (!hard_reg_set_empty_p (left))
10269 size = MIN (size, UNITS_PER_WORD);
10270 return (GET_MODE_SIZE (mode) + size - 1) / size;
10273 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10276 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10277 enum machine_mode to ATTRIBUTE_UNUSED,
10278 enum reg_class rclass)
10280 /* There are several problems with changing the modes of values
10281 in floating-point registers:
10283 - When a multi-word value is stored in paired floating-point
10284 registers, the first register always holds the low word.
10285 We therefore can't allow FPRs to change between single-word
10286 and multi-word modes on big-endian targets.
10288 - GCC assumes that each word of a multiword register can be accessed
10289 individually using SUBREGs. This is not true for floating-point
10290 registers if they are bigger than a word.
10292 - Loading a 32-bit value into a 64-bit floating-point register
10293 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10294 We can't allow FPRs to change from SImode to to a wider mode on
10297 - If the FPU has already interpreted a value in one format, we must
10298 not ask it to treat the value as having a different format.
10300 We therefore disallow all mode changes involving FPRs. */
10301 return reg_classes_intersect_p (FP_REGS, rclass);
10304 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10307 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10312 return TARGET_HARD_FLOAT;
10315 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10318 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10325 /* Implement MODES_TIEABLE_P. */
10328 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10330 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10331 prefer to put one of them in FPRs. */
10332 return (mode1 == mode2
10333 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10334 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10337 /* Implement PREFERRED_RELOAD_CLASS. */
10340 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10342 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10345 if (reg_class_subset_p (FP_REGS, rclass)
10346 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10349 if (reg_class_subset_p (GR_REGS, rclass))
10352 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10358 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10359 Return a "canonical" class to represent it in later calculations. */
10361 static enum reg_class
10362 mips_canonicalize_move_class (enum reg_class rclass)
10364 /* All moves involving accumulator registers have the same cost. */
10365 if (reg_class_subset_p (rclass, ACC_REGS))
10368 /* Likewise promote subclasses of general registers to the most
10369 interesting containing class. */
10370 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10372 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10373 rclass = GENERAL_REGS;
10378 /* Return the cost of moving a value of mode MODE from a register of
10379 class FROM to a GPR. Return 0 for classes that are unions of other
10380 classes handled by this function. */
10383 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10384 enum reg_class from)
10389 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10393 /* MFLO and MFHI. */
10401 /* LUI followed by MOVF. */
10407 /* This choice of value is historical. */
10415 /* Return the cost of moving a value of mode MODE from a GPR to a
10416 register of class TO. Return 0 for classes that are unions of
10417 other classes handled by this function. */
10420 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10425 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10429 /* MTLO and MTHI. */
10437 /* A secondary reload through an FPR scratch. */
10438 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10439 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10444 /* This choice of value is historical. */
10452 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10453 maximum of the move costs for subclasses; regclass will work out
10454 the maximum for us. */
10457 mips_register_move_cost (enum machine_mode mode,
10458 enum reg_class from, enum reg_class to)
10460 enum reg_class dregs;
10463 from = mips_canonicalize_move_class (from);
10464 to = mips_canonicalize_move_class (to);
10466 /* Handle moves that can be done without using general-purpose registers. */
10467 if (from == FP_REGS)
10469 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10473 /* The sequence generated by mips_expand_fcc_reload. */
10477 /* Handle cases in which only one class deviates from the ideal. */
10478 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10480 return mips_move_from_gpr_cost (mode, to);
10482 return mips_move_to_gpr_cost (mode, from);
10484 /* Handles cases that require a GPR temporary. */
10485 cost1 = mips_move_to_gpr_cost (mode, from);
10488 cost2 = mips_move_from_gpr_cost (mode, to);
10490 return cost1 + cost2;
10496 /* Implement TARGET_IRA_COVER_CLASSES. */
10498 static const enum reg_class *
10499 mips_ira_cover_classes (void)
10501 static const enum reg_class acc_classes[] = {
10502 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10503 ST_REGS, LIM_REG_CLASSES
10505 static const enum reg_class no_acc_classes[] = {
10506 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10507 ST_REGS, LIM_REG_CLASSES
10510 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10511 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10512 as a cover class only works well when we keep per-register costs.
10513 Using it when not optimizing can cause us to think accumulators
10514 have the same cost as GPRs in cases where GPRs are actually much
10516 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10519 /* Return the register class required for a secondary register when
10520 copying between one of the registers in RCLASS and value X, which
10521 has mode MODE. X is the source of the move if IN_P, otherwise it
10522 is the destination. Return NO_REGS if no secondary register is
10526 mips_secondary_reload_class (enum reg_class rclass,
10527 enum machine_mode mode, rtx x, bool in_p)
10531 /* If X is a constant that cannot be loaded into $25, it must be loaded
10532 into some other GPR. No other register class allows a direct move. */
10533 if (mips_dangerous_for_la25_p (x))
10534 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10536 regno = true_regnum (x);
10539 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10540 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10546 /* Copying from accumulator registers to anywhere other than a general
10547 register requires a temporary general register. */
10548 if (reg_class_subset_p (rclass, ACC_REGS))
10549 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10550 if (ACC_REG_P (regno))
10551 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10553 /* We can only copy a value to a condition code register from a
10554 floating-point register, and even then we require a scratch
10555 floating-point register. We can only copy a value out of a
10556 condition-code register into a general register. */
10557 if (reg_class_subset_p (rclass, ST_REGS))
10561 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10563 if (ST_REG_P (regno))
10567 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10570 if (reg_class_subset_p (rclass, FP_REGS))
10573 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10574 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10575 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10578 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10579 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10582 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
10583 /* We can force the constant to memory and use lwc1
10584 and ldc1. As above, we will use pairs of lwc1s if
10585 ldc1 is not supported. */
10588 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10589 /* In this case we can use mov.fmt. */
10592 /* Otherwise, we need to reload through an integer register. */
10595 if (FP_REG_P (regno))
10596 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10601 /* Implement TARGET_MODE_REP_EXTENDED. */
10604 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10606 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10607 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10608 return SIGN_EXTEND;
10613 /* Implement TARGET_VALID_POINTER_MODE. */
10616 mips_valid_pointer_mode (enum machine_mode mode)
10618 return mode == SImode || (TARGET_64BIT && mode == DImode);
10621 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10624 mips_vector_mode_supported_p (enum machine_mode mode)
10629 return TARGET_PAIRED_SINGLE_FLOAT;
10644 return TARGET_LOONGSON_VECTORS;
10651 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10654 mips_scalar_mode_supported_p (enum machine_mode mode)
10656 if (ALL_FIXED_POINT_MODE_P (mode)
10657 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
10660 return default_scalar_mode_supported_p (mode);
10663 /* Implement TARGET_INIT_LIBFUNCS. */
10665 #include "config/gofast.h"
10668 mips_init_libfuncs (void)
10670 if (TARGET_FIX_VR4120)
10672 /* Register the special divsi3 and modsi3 functions needed to work
10673 around VR4120 division errata. */
10674 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10675 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10678 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
10680 /* Register the MIPS16 -mhard-float stubs. */
10681 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10682 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10683 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10684 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10686 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10687 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10688 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10689 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10690 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10691 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10692 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
10694 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10695 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10696 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
10698 if (TARGET_DOUBLE_FLOAT)
10700 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10701 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10702 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10703 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10705 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10706 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10707 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10708 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10709 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10710 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10711 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
10713 set_conv_libfunc (sext_optab, DFmode, SFmode,
10714 "__mips16_extendsfdf2");
10715 set_conv_libfunc (trunc_optab, SFmode, DFmode,
10716 "__mips16_truncdfsf2");
10717 set_conv_libfunc (sfix_optab, SImode, DFmode,
10718 "__mips16_fix_truncdfsi");
10719 set_conv_libfunc (sfloat_optab, DFmode, SImode,
10720 "__mips16_floatsidf");
10721 set_conv_libfunc (ufloat_optab, DFmode, SImode,
10722 "__mips16_floatunsidf");
10726 /* Register the gofast functions if selected using --enable-gofast. */
10727 gofast_maybe_init_libfuncs ();
10729 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
10730 on an external non-MIPS16 routine to implement __sync_synchronize. */
10732 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
10735 /* Return the length of INSN. LENGTH is the initial length computed by
10736 attributes in the machine-description file. */
10739 mips_adjust_insn_length (rtx insn, int length)
10741 /* A unconditional jump has an unfilled delay slot if it is not part
10742 of a sequence. A conditional jump normally has a delay slot, but
10743 does not on MIPS16. */
10744 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10747 /* See how many nops might be needed to avoid hardware hazards. */
10748 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10749 switch (get_attr_hazard (insn))
10763 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
10764 the .md file length attributes are 4-based for both modes.
10765 Adjust the MIPS16 ones here. */
10772 /* Return an asm sequence to start a noat block and load the address
10773 of a label into $1. */
10776 mips_output_load_label (void)
10778 if (TARGET_EXPLICIT_RELOCS)
10782 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10785 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10788 if (ISA_HAS_LOAD_DELAY)
10789 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10790 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10794 if (Pmode == DImode)
10795 return "%[dla\t%@,%0";
10797 return "%[la\t%@,%0";
10801 /* Return the assembly code for INSN, which has the operands given by
10802 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10803 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10804 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10805 version of BRANCH_IF_TRUE. */
10808 mips_output_conditional_branch (rtx insn, rtx *operands,
10809 const char *branch_if_true,
10810 const char *branch_if_false)
10812 unsigned int length;
10813 rtx taken, not_taken;
10815 gcc_assert (LABEL_P (operands[1]));
10817 length = get_attr_length (insn);
10820 /* Just a simple conditional branch. */
10821 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10822 return branch_if_true;
10825 /* Generate a reversed branch around a direct jump. This fallback does
10826 not use branch-likely instructions. */
10827 mips_branch_likely = false;
10828 not_taken = gen_label_rtx ();
10829 taken = operands[1];
10831 /* Generate the reversed branch to NOT_TAKEN. */
10832 operands[1] = not_taken;
10833 output_asm_insn (branch_if_false, operands);
10835 /* If INSN has a delay slot, we must provide delay slots for both the
10836 branch to NOT_TAKEN and the conditional jump. We must also ensure
10837 that INSN's delay slot is executed in the appropriate cases. */
10838 if (final_sequence)
10840 /* This first delay slot will always be executed, so use INSN's
10841 delay slot if is not annulled. */
10842 if (!INSN_ANNULLED_BRANCH_P (insn))
10844 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10845 asm_out_file, optimize, 1, NULL);
10846 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10849 output_asm_insn ("nop", 0);
10850 fprintf (asm_out_file, "\n");
10853 /* Output the unconditional branch to TAKEN. */
10855 output_asm_insn ("j\t%0%/", &taken);
10858 output_asm_insn (mips_output_load_label (), &taken);
10859 output_asm_insn ("jr\t%@%]%/", 0);
10862 /* Now deal with its delay slot; see above. */
10863 if (final_sequence)
10865 /* This delay slot will only be executed if the branch is taken.
10866 Use INSN's delay slot if is annulled. */
10867 if (INSN_ANNULLED_BRANCH_P (insn))
10869 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10870 asm_out_file, optimize, 1, NULL);
10871 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10874 output_asm_insn ("nop", 0);
10875 fprintf (asm_out_file, "\n");
10878 /* Output NOT_TAKEN. */
10879 targetm.asm_out.internal_label (asm_out_file, "L",
10880 CODE_LABEL_NUMBER (not_taken));
10884 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10885 if some ordering condition is true. The condition is given by
10886 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10887 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10888 its second is always zero. */
10891 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10893 const char *branch[2];
10895 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10896 Make BRANCH[0] branch on the inverse condition. */
10897 switch (GET_CODE (operands[0]))
10899 /* These cases are equivalent to comparisons against zero. */
10901 inverted_p = !inverted_p;
10902 /* Fall through. */
10904 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10905 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10908 /* These cases are always true or always false. */
10910 inverted_p = !inverted_p;
10911 /* Fall through. */
10913 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10914 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10918 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10919 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10922 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10925 /* Start a block of code that needs access to the LL, SC and SYNC
10929 mips_start_ll_sc_sync_block (void)
10931 if (!ISA_HAS_LL_SC)
10933 output_asm_insn (".set\tpush", 0);
10934 output_asm_insn (".set\tmips2", 0);
10938 /* End a block started by mips_start_ll_sc_sync_block. */
10941 mips_end_ll_sc_sync_block (void)
10943 if (!ISA_HAS_LL_SC)
10944 output_asm_insn (".set\tpop", 0);
10947 /* Output and/or return the asm template for a sync instruction. */
10950 mips_output_sync (void)
10952 mips_start_ll_sc_sync_block ();
10953 output_asm_insn ("sync", 0);
10954 mips_end_ll_sc_sync_block ();
10958 /* Return the asm template associated with sync_insn1 value TYPE.
10959 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
10961 static const char *
10962 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
10966 case SYNC_INSN1_MOVE:
10967 return "move\t%0,%z2";
10968 case SYNC_INSN1_LI:
10969 return "li\t%0,%2";
10970 case SYNC_INSN1_ADDU:
10971 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
10972 case SYNC_INSN1_ADDIU:
10973 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
10974 case SYNC_INSN1_SUBU:
10975 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
10976 case SYNC_INSN1_AND:
10977 return "and\t%0,%1,%z2";
10978 case SYNC_INSN1_ANDI:
10979 return "andi\t%0,%1,%2";
10980 case SYNC_INSN1_OR:
10981 return "or\t%0,%1,%z2";
10982 case SYNC_INSN1_ORI:
10983 return "ori\t%0,%1,%2";
10984 case SYNC_INSN1_XOR:
10985 return "xor\t%0,%1,%z2";
10986 case SYNC_INSN1_XORI:
10987 return "xori\t%0,%1,%2";
10989 gcc_unreachable ();
10992 /* Return the asm template associated with sync_insn2 value TYPE. */
10994 static const char *
10995 mips_sync_insn2_template (enum attr_sync_insn2 type)
10999 case SYNC_INSN2_NOP:
11000 gcc_unreachable ();
11001 case SYNC_INSN2_AND:
11002 return "and\t%0,%1,%z2";
11003 case SYNC_INSN2_XOR:
11004 return "xor\t%0,%1,%z2";
11005 case SYNC_INSN2_NOT:
11006 return "nor\t%0,%1,%.";
11008 gcc_unreachable ();
11011 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11012 the value of the one of the sync_* attributes. Return the operand
11013 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11014 have the associated attribute. */
11017 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11020 default_value = operands[index - 1];
11021 return default_value;
11024 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11025 sequence for it. */
11028 mips_process_sync_loop (rtx insn, rtx *operands)
11030 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11031 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11032 unsigned int tmp3_insn;
11033 enum attr_sync_insn1 insn1;
11034 enum attr_sync_insn2 insn2;
11037 /* Read an operand from the sync_WHAT attribute and store it in
11038 variable WHAT. DEFAULT is the default value if no attribute
11040 #define READ_OPERAND(WHAT, DEFAULT) \
11041 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11044 /* Read the memory. */
11045 READ_OPERAND (mem, 0);
11047 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11049 /* Read the other attributes. */
11050 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11051 READ_OPERAND (oldval, at);
11052 READ_OPERAND (newval, at);
11053 READ_OPERAND (inclusive_mask, 0);
11054 READ_OPERAND (exclusive_mask, 0);
11055 READ_OPERAND (required_oldval, 0);
11056 READ_OPERAND (insn1_op2, 0);
11057 insn1 = get_attr_sync_insn1 (insn);
11058 insn2 = get_attr_sync_insn2 (insn);
11060 mips_multi_start ();
11062 /* Output the release side of the memory barrier. */
11063 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11064 mips_multi_add_insn ("sync", NULL);
11066 /* Output the branch-back label. */
11067 mips_multi_add_label ("1:");
11069 /* OLDVAL = *MEM. */
11070 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11071 oldval, mem, NULL);
11073 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11074 if (required_oldval)
11076 if (inclusive_mask == 0)
11080 gcc_assert (oldval != at);
11081 mips_multi_add_insn ("and\t%0,%1,%2",
11082 at, oldval, inclusive_mask, NULL);
11085 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11088 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11089 if (exclusive_mask == 0)
11093 gcc_assert (oldval != at);
11094 mips_multi_add_insn ("and\t%0,%1,%z2",
11095 at, oldval, exclusive_mask, NULL);
11099 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11101 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11102 at least one instruction in that case. */
11103 if (insn1 == SYNC_INSN1_MOVE
11104 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11108 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11109 newval, oldval, insn1_op2, NULL);
11113 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11114 if (insn2 == SYNC_INSN2_NOP)
11118 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11119 newval, tmp2, inclusive_mask, NULL);
11122 tmp3_insn = mips_multi_last_index ();
11124 /* $AT = $TMP1 | $TMP3. */
11125 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11127 mips_multi_set_operand (tmp3_insn, 0, at);
11132 gcc_assert (tmp1 != tmp3);
11133 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11136 /* if (!commit (*MEM = $AT)) goto 1.
11138 This will sometimes be a delayed branch; see the write code below
11140 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11141 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11143 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11144 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11146 mips_multi_copy_insn (tmp3_insn);
11147 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11150 mips_multi_add_insn ("nop", NULL);
11152 /* Output the acquire side of the memory barrier. */
11153 if (TARGET_SYNC_AFTER_SC)
11154 mips_multi_add_insn ("sync", NULL);
11156 /* Output the exit label, if needed. */
11157 if (required_oldval)
11158 mips_multi_add_label ("2:");
11160 #undef READ_OPERAND
11163 /* Output and/or return the asm template for sync loop INSN, which has
11164 the operands given by OPERANDS. */
11167 mips_output_sync_loop (rtx insn, rtx *operands)
11169 mips_process_sync_loop (insn, operands);
11171 /* Use branch-likely instructions to work around the LL/SC R10000
11173 mips_branch_likely = TARGET_FIX_R10000;
11175 mips_push_asm_switch (&mips_noreorder);
11176 mips_push_asm_switch (&mips_nomacro);
11177 mips_push_asm_switch (&mips_noat);
11178 mips_start_ll_sc_sync_block ();
11180 mips_multi_write ();
11182 mips_end_ll_sc_sync_block ();
11183 mips_pop_asm_switch (&mips_noat);
11184 mips_pop_asm_switch (&mips_nomacro);
11185 mips_pop_asm_switch (&mips_noreorder);
11190 /* Return the number of individual instructions in sync loop INSN,
11191 which has the operands given by OPERANDS. */
11194 mips_sync_loop_insns (rtx insn, rtx *operands)
11196 mips_process_sync_loop (insn, operands);
11197 return mips_multi_num_insns;
11200 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11201 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11203 When working around R4000 and R4400 errata, we need to make sure that
11204 the division is not immediately followed by a shift[1][2]. We also
11205 need to stop the division from being put into a branch delay slot[3].
11206 The easiest way to avoid both problems is to add a nop after the
11207 division. When a divide-by-zero check is needed, this nop can be
11208 used to fill the branch delay slot.
11210 [1] If a double-word or a variable shift executes immediately
11211 after starting an integer division, the shift may give an
11212 incorrect result. See quotations of errata #16 and #28 from
11213 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11214 in mips.md for details.
11216 [2] A similar bug to [1] exists for all revisions of the
11217 R4000 and the R4400 when run in an MC configuration.
11218 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11220 "19. In this following sequence:
11222 ddiv (or ddivu or div or divu)
11223 dsll32 (or dsrl32, dsra32)
11225 if an MPT stall occurs, while the divide is slipping the cpu
11226 pipeline, then the following double shift would end up with an
11229 Workaround: The compiler needs to avoid generating any
11230 sequence with divide followed by extended double shift."
11232 This erratum is also present in "MIPS R4400MC Errata, Processor
11233 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11234 & 3.0" as errata #10 and #4, respectively.
11236 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11237 (also valid for MIPS R4000MC processors):
11239 "52. R4000SC: This bug does not apply for the R4000PC.
11241 There are two flavors of this bug:
11243 1) If the instruction just after divide takes an RF exception
11244 (tlb-refill, tlb-invalid) and gets an instruction cache
11245 miss (both primary and secondary) and the line which is
11246 currently in secondary cache at this index had the first
11247 data word, where the bits 5..2 are set, then R4000 would
11248 get a wrong result for the div.
11253 ------------------- # end-of page. -tlb-refill
11258 ------------------- # end-of page. -tlb-invalid
11261 2) If the divide is in the taken branch delay slot, where the
11262 target takes RF exception and gets an I-cache miss for the
11263 exception vector or where I-cache miss occurs for the
11264 target address, under the above mentioned scenarios, the
11265 div would get wrong results.
11268 j r2 # to next page mapped or unmapped
11269 div r8,r9 # this bug would be there as long
11270 # as there is an ICache miss and
11271 nop # the "data pattern" is present
11274 beq r0, r0, NextPage # to Next page
11278 This bug is present for div, divu, ddiv, and ddivu
11281 Workaround: For item 1), OS could make sure that the next page
11282 after the divide instruction is also mapped. For item 2), the
11283 compiler could make sure that the divide instruction is not in
11284 the branch delay slot."
11286 These processors have PRId values of 0x00004220 and 0x00004300 for
11287 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11290 mips_output_division (const char *division, rtx *operands)
11295 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11297 output_asm_insn (s, operands);
11300 if (TARGET_CHECK_ZERO_DIV)
11304 output_asm_insn (s, operands);
11305 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11307 else if (GENERATE_DIVIDE_TRAPS)
11309 output_asm_insn (s, operands);
11310 s = "teq\t%2,%.,7";
11314 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11315 output_asm_insn (s, operands);
11316 s = "break\t7%)\n1:";
11322 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11323 instruction and if OUT_INSN assigns to the accumulator operand. */
11326 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11330 x = single_set (in_insn);
11336 if (GET_CODE (x) == PLUS
11337 && GET_CODE (XEXP (x, 0)) == MULT
11338 && reg_set_p (XEXP (x, 1), out_insn))
11341 if (GET_CODE (x) == MINUS
11342 && GET_CODE (XEXP (x, 1)) == MULT
11343 && reg_set_p (XEXP (x, 0), out_insn))
11349 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11350 data rather than the address. We need this because the cprestore
11351 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11352 which causes the default routine to abort. We just return false
11356 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11358 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11361 return !store_data_bypass_p (out_insn, in_insn);
11365 /* Variables and flags used in scheduler hooks when tuning for
11369 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11372 /* If true, then next ALU1/2 instruction will go to ALU1. */
11375 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11378 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11379 int alu1_core_unit_code;
11380 int alu2_core_unit_code;
11381 int falu1_core_unit_code;
11382 int falu2_core_unit_code;
11384 /* True if current cycle has a multi instruction.
11385 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11386 bool cycle_has_multi_p;
11388 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11389 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11391 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11392 instruction to go ALU1. */
11393 rtx alu1_turn_enabled_insn;
11394 rtx alu2_turn_enabled_insn;
11395 rtx falu1_turn_enabled_insn;
11396 rtx falu2_turn_enabled_insn;
11399 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11400 dependencies have no cost, except on the 20Kc where output-dependence
11401 is treated like input-dependence. */
11404 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11405 rtx dep ATTRIBUTE_UNUSED, int cost)
11407 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11410 if (REG_NOTE_KIND (link) != 0)
11415 /* Return the number of instructions that can be issued per cycle. */
11418 mips_issue_rate (void)
11422 case PROCESSOR_74KC:
11423 case PROCESSOR_74KF2_1:
11424 case PROCESSOR_74KF1_1:
11425 case PROCESSOR_74KF3_2:
11426 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11427 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11428 but in reality only a maximum of 3 insns can be issued as
11429 floating-point loads and stores also require a slot in the
11431 case PROCESSOR_R10000:
11432 /* All R10K Processors are quad-issue (being the first MIPS
11433 processors to support this feature). */
11436 case PROCESSOR_20KC:
11437 case PROCESSOR_R4130:
11438 case PROCESSOR_R5400:
11439 case PROCESSOR_R5500:
11440 case PROCESSOR_R7000:
11441 case PROCESSOR_R9000:
11442 case PROCESSOR_OCTEON:
11445 case PROCESSOR_SB1:
11446 case PROCESSOR_SB1A:
11447 /* This is actually 4, but we get better performance if we claim 3.
11448 This is partly because of unwanted speculative code motion with the
11449 larger number, and partly because in most common cases we can't
11450 reach the theoretical max of 4. */
11453 case PROCESSOR_LOONGSON_2E:
11454 case PROCESSOR_LOONGSON_2F:
11462 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11465 mips_ls2_init_dfa_post_cycle_insn (void)
11468 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11469 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11473 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11474 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11478 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11479 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11483 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11484 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11487 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11488 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11489 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11490 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11493 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11494 Init data used in mips_dfa_post_advance_cycle. */
11497 mips_init_dfa_post_cycle_insn (void)
11499 if (TUNE_LOONGSON_2EF)
11500 mips_ls2_init_dfa_post_cycle_insn ();
11503 /* Initialize STATE when scheduling for Loongson 2E/2F.
11504 Support round-robin dispatch scheme by enabling only one of
11505 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11509 mips_ls2_dfa_post_advance_cycle (state_t state)
11511 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
11513 /* Though there are no non-pipelined ALU1 insns,
11514 we can get an instruction of type 'multi' before reload. */
11515 gcc_assert (mips_ls2.cycle_has_multi_p);
11516 mips_ls2.alu1_turn_p = false;
11519 mips_ls2.cycle_has_multi_p = false;
11521 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
11522 /* We have a non-pipelined alu instruction in the core,
11523 adjust round-robin counter. */
11524 mips_ls2.alu1_turn_p = true;
11526 if (mips_ls2.alu1_turn_p)
11528 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
11529 gcc_unreachable ();
11533 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
11534 gcc_unreachable ();
11537 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
11539 /* There are no non-pipelined FALU1 insns. */
11540 gcc_unreachable ();
11541 mips_ls2.falu1_turn_p = false;
11544 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
11545 /* We have a non-pipelined falu instruction in the core,
11546 adjust round-robin counter. */
11547 mips_ls2.falu1_turn_p = true;
11549 if (mips_ls2.falu1_turn_p)
11551 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
11552 gcc_unreachable ();
11556 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
11557 gcc_unreachable ();
11561 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
11562 This hook is being called at the start of each cycle. */
11565 mips_dfa_post_advance_cycle (void)
11567 if (TUNE_LOONGSON_2EF)
11568 mips_ls2_dfa_post_advance_cycle (curr_state);
11571 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
11572 be as wide as the scheduling freedom in the DFA. */
11575 mips_multipass_dfa_lookahead (void)
11577 /* Can schedule up to 4 of the 6 function units in any one cycle. */
11581 if (TUNE_LOONGSON_2EF)
11590 /* Remove the instruction at index LOWER from ready queue READY and
11591 reinsert it in front of the instruction at index HIGHER. LOWER must
11595 mips_promote_ready (rtx *ready, int lower, int higher)
11600 new_head = ready[lower];
11601 for (i = lower; i < higher; i++)
11602 ready[i] = ready[i + 1];
11603 ready[i] = new_head;
11606 /* If the priority of the instruction at POS2 in the ready queue READY
11607 is within LIMIT units of that of the instruction at POS1, swap the
11608 instructions if POS2 is not already less than POS1. */
11611 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
11614 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
11618 temp = ready[pos1];
11619 ready[pos1] = ready[pos2];
11620 ready[pos2] = temp;
11624 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
11625 that may clobber hi or lo. */
11626 static rtx mips_macc_chains_last_hilo;
11628 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
11629 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
11632 mips_macc_chains_record (rtx insn)
11634 if (get_attr_may_clobber_hilo (insn))
11635 mips_macc_chains_last_hilo = insn;
11638 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
11639 has NREADY elements, looking for a multiply-add or multiply-subtract
11640 instruction that is cumulative with mips_macc_chains_last_hilo.
11641 If there is one, promote it ahead of anything else that might
11642 clobber hi or lo. */
11645 mips_macc_chains_reorder (rtx *ready, int nready)
11649 if (mips_macc_chains_last_hilo != 0)
11650 for (i = nready - 1; i >= 0; i--)
11651 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
11653 for (j = nready - 1; j > i; j--)
11654 if (recog_memoized (ready[j]) >= 0
11655 && get_attr_may_clobber_hilo (ready[j]))
11657 mips_promote_ready (ready, i, j);
11664 /* The last instruction to be scheduled. */
11665 static rtx vr4130_last_insn;
11667 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
11668 points to an rtx that is initially an instruction. Nullify the rtx
11669 if the instruction uses the value of register X. */
11672 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
11677 insn_ptr = (rtx *) data;
11680 && reg_referenced_p (x, PATTERN (*insn_ptr)))
11684 /* Return true if there is true register dependence between vr4130_last_insn
11688 vr4130_true_reg_dependence_p (rtx insn)
11690 note_stores (PATTERN (vr4130_last_insn),
11691 vr4130_true_reg_dependence_p_1, &insn);
11695 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
11696 the ready queue and that INSN2 is the instruction after it, return
11697 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
11698 in which INSN1 and INSN2 can probably issue in parallel, but for
11699 which (INSN2, INSN1) should be less sensitive to instruction
11700 alignment than (INSN1, INSN2). See 4130.md for more details. */
11703 vr4130_swap_insns_p (rtx insn1, rtx insn2)
11705 sd_iterator_def sd_it;
11708 /* Check for the following case:
11710 1) there is some other instruction X with an anti dependence on INSN1;
11711 2) X has a higher priority than INSN2; and
11712 3) X is an arithmetic instruction (and thus has no unit restrictions).
11714 If INSN1 is the last instruction blocking X, it would better to
11715 choose (INSN1, X) over (INSN2, INSN1). */
11716 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
11717 if (DEP_TYPE (dep) == REG_DEP_ANTI
11718 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
11719 && recog_memoized (DEP_CON (dep)) >= 0
11720 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
11723 if (vr4130_last_insn != 0
11724 && recog_memoized (insn1) >= 0
11725 && recog_memoized (insn2) >= 0)
11727 /* See whether INSN1 and INSN2 use different execution units,
11728 or if they are both ALU-type instructions. If so, they can
11729 probably execute in parallel. */
11730 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
11731 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
11732 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
11734 /* If only one of the instructions has a dependence on
11735 vr4130_last_insn, prefer to schedule the other one first. */
11736 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
11737 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
11738 if (dep1_p != dep2_p)
11741 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
11742 is not an ALU-type instruction and if INSN1 uses the same
11743 execution unit. (Note that if this condition holds, we already
11744 know that INSN2 uses a different execution unit.) */
11745 if (class1 != VR4130_CLASS_ALU
11746 && recog_memoized (vr4130_last_insn) >= 0
11747 && class1 == get_attr_vr4130_class (vr4130_last_insn))
11754 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
11755 queue with at least two instructions. Swap the first two if
11756 vr4130_swap_insns_p says that it could be worthwhile. */
11759 vr4130_reorder (rtx *ready, int nready)
11761 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
11762 mips_promote_ready (ready, nready - 2, nready - 1);
11765 /* Record whether last 74k AGEN instruction was a load or store. */
11766 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
11768 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
11769 resets to TYPE_UNKNOWN state. */
11772 mips_74k_agen_init (rtx insn)
11774 if (!insn || !NONJUMP_INSN_P (insn))
11775 mips_last_74k_agen_insn = TYPE_UNKNOWN;
11778 enum attr_type type = get_attr_type (insn);
11779 if (type == TYPE_LOAD || type == TYPE_STORE)
11780 mips_last_74k_agen_insn = type;
11784 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
11785 loads to be grouped together, and multiple stores to be grouped
11786 together. Swap things around in the ready queue to make this happen. */
11789 mips_74k_agen_reorder (rtx *ready, int nready)
11792 int store_pos, load_pos;
11797 for (i = nready - 1; i >= 0; i--)
11799 rtx insn = ready[i];
11800 if (USEFUL_INSN_P (insn))
11801 switch (get_attr_type (insn))
11804 if (store_pos == -1)
11809 if (load_pos == -1)
11818 if (load_pos == -1 || store_pos == -1)
11821 switch (mips_last_74k_agen_insn)
11824 /* Prefer to schedule loads since they have a higher latency. */
11826 /* Swap loads to the front of the queue. */
11827 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
11830 /* Swap stores to the front of the queue. */
11831 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
11838 /* Implement TARGET_SCHED_INIT. */
11841 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11842 int max_ready ATTRIBUTE_UNUSED)
11844 mips_macc_chains_last_hilo = 0;
11845 vr4130_last_insn = 0;
11846 mips_74k_agen_init (NULL_RTX);
11848 /* When scheduling for Loongson2, branch instructions go to ALU1,
11849 therefore basic block is most likely to start with round-robin counter
11850 pointed to ALU2. */
11851 mips_ls2.alu1_turn_p = false;
11852 mips_ls2.falu1_turn_p = true;
11855 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
11858 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11859 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
11861 if (!reload_completed
11862 && TUNE_MACC_CHAINS
11864 mips_macc_chains_reorder (ready, *nreadyp);
11866 if (reload_completed
11868 && !TARGET_VR4130_ALIGN
11870 vr4130_reorder (ready, *nreadyp);
11873 mips_74k_agen_reorder (ready, *nreadyp);
11875 return mips_issue_rate ();
11878 /* Update round-robin counters for ALU1/2 and FALU1/2. */
11881 mips_ls2_variable_issue (rtx insn)
11883 if (mips_ls2.alu1_turn_p)
11885 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
11886 mips_ls2.alu1_turn_p = false;
11890 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
11891 mips_ls2.alu1_turn_p = true;
11894 if (mips_ls2.falu1_turn_p)
11896 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
11897 mips_ls2.falu1_turn_p = false;
11901 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
11902 mips_ls2.falu1_turn_p = true;
11905 if (recog_memoized (insn) >= 0)
11906 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
11909 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
11912 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11913 rtx insn, int more)
11915 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
11916 if (USEFUL_INSN_P (insn))
11919 if (!reload_completed && TUNE_MACC_CHAINS)
11920 mips_macc_chains_record (insn);
11921 vr4130_last_insn = insn;
11923 mips_74k_agen_init (insn);
11924 else if (TUNE_LOONGSON_2EF)
11925 mips_ls2_variable_issue (insn);
11928 /* Instructions of type 'multi' should all be split before
11929 the second scheduling pass. */
11930 gcc_assert (!reload_completed
11931 || recog_memoized (insn) < 0
11932 || get_attr_type (insn) != TYPE_MULTI);
11937 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
11938 return the first operand of the associated PREF or PREFX insn. */
11941 mips_prefetch_cookie (rtx write, rtx locality)
11943 /* store_streamed / load_streamed. */
11944 if (INTVAL (locality) <= 0)
11945 return GEN_INT (INTVAL (write) + 4);
11947 /* store / load. */
11948 if (INTVAL (locality) <= 2)
11951 /* store_retained / load_retained. */
11952 return GEN_INT (INTVAL (write) + 6);
11955 /* Flags that indicate when a built-in function is available.
11957 BUILTIN_AVAIL_NON_MIPS16
11958 The function is available on the current target, but only
11959 in non-MIPS16 mode. */
11960 #define BUILTIN_AVAIL_NON_MIPS16 1
11962 /* Declare an availability predicate for built-in functions that
11963 require non-MIPS16 mode and also require COND to be true.
11964 NAME is the main part of the predicate's name. */
11965 #define AVAIL_NON_MIPS16(NAME, COND) \
11966 static unsigned int \
11967 mips_builtin_avail_##NAME (void) \
11969 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
11972 /* This structure describes a single built-in function. */
11973 struct mips_builtin_description {
11974 /* The code of the main .md file instruction. See mips_builtin_type
11975 for more information. */
11976 enum insn_code icode;
11978 /* The floating-point comparison code to use with ICODE, if any. */
11979 enum mips_fp_condition cond;
11981 /* The name of the built-in function. */
11984 /* Specifies how the function should be expanded. */
11985 enum mips_builtin_type builtin_type;
11987 /* The function's prototype. */
11988 enum mips_function_type function_type;
11990 /* Whether the function is available. */
11991 unsigned int (*avail) (void);
11994 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
11995 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
11996 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
11997 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
11998 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
11999 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12000 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12001 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12002 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12004 /* Construct a mips_builtin_description from the given arguments.
12006 INSN is the name of the associated instruction pattern, without the
12007 leading CODE_FOR_mips_.
12009 CODE is the floating-point condition code associated with the
12010 function. It can be 'f' if the field is not applicable.
12012 NAME is the name of the function itself, without the leading
12015 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12017 AVAIL is the name of the availability predicate, without the leading
12018 mips_builtin_avail_. */
12019 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12020 FUNCTION_TYPE, AVAIL) \
12021 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12022 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12023 mips_builtin_avail_ ## AVAIL }
12025 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12026 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12027 are as for MIPS_BUILTIN. */
12028 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12029 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12031 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12032 are subject to mips_builtin_avail_<AVAIL>. */
12033 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12034 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12035 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12036 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12037 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12039 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12040 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12041 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12042 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12043 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12044 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12046 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12047 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12049 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12050 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12052 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12053 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12056 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12057 are subject to mips_builtin_avail_mips3d. */
12058 #define CMP_4S_BUILTINS(INSN, COND) \
12059 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12060 MIPS_BUILTIN_CMP_ANY, \
12061 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12062 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12063 MIPS_BUILTIN_CMP_ALL, \
12064 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12066 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12067 instruction requires mips_builtin_avail_<AVAIL>. */
12068 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12069 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12070 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12072 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12073 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12076 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12077 #define CMP_BUILTINS(COND) \
12078 MOVTF_BUILTINS (c, COND, paired_single), \
12079 MOVTF_BUILTINS (cabs, COND, mips3d), \
12080 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12081 CMP_PS_BUILTINS (c, COND, paired_single), \
12082 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12083 CMP_4S_BUILTINS (c, COND), \
12084 CMP_4S_BUILTINS (cabs, COND)
12086 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12087 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12088 and AVAIL are as for MIPS_BUILTIN. */
12089 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12090 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12091 FUNCTION_TYPE, AVAIL)
12093 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12094 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12095 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12096 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12097 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12099 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12100 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12101 builtin_description field. */
12102 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12103 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12104 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12105 FUNCTION_TYPE, mips_builtin_avail_loongson }
12107 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12108 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12109 builtin_description field. */
12110 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12111 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12113 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12114 We use functions of this form when the same insn can be usefully applied
12115 to more than one datatype. */
12116 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12117 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12119 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12120 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12121 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12122 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12123 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12124 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12126 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12127 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12128 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12129 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12130 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12131 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12132 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12133 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12134 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12135 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12136 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12137 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12138 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12139 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12140 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12141 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12142 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12143 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12144 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12145 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12146 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12147 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12148 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12149 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12150 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12151 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12152 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12153 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12154 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12156 static const struct mips_builtin_description mips_builtins[] = {
12157 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12158 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12159 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12160 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12161 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12162 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12163 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12164 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12166 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12167 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12168 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12169 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12170 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12172 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12173 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12174 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12175 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12176 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12177 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12179 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12180 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12181 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12182 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12183 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12184 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12186 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12188 /* Built-in functions for the SB-1 processor. */
12189 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12191 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12192 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12193 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12194 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12195 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12196 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12197 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12198 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12199 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12200 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12201 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12202 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12203 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12204 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12205 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12206 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12207 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12208 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12209 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12210 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12211 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12212 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12213 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12214 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12215 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12216 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12217 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12218 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12219 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12220 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12221 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12222 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12223 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12224 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12225 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12226 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12227 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12228 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12229 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12230 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12231 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12232 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12233 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12234 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12235 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12236 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12237 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12238 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12239 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12240 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12241 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12242 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12243 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12244 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12245 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12246 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12247 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12248 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12249 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12250 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12251 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12252 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12253 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12254 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12255 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12256 BPOSGE_BUILTIN (32, dsp),
12258 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12259 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12260 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12261 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12262 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12263 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12264 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12265 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12266 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12267 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12268 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12269 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12270 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12271 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12272 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12273 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12274 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12275 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12276 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12277 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12278 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12279 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12280 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12281 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12282 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12283 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12284 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12285 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12286 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12287 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12288 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12289 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12290 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12291 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12292 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12294 /* Built-in functions for the DSP ASE (32-bit only). */
12295 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12296 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12297 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12298 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12299 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12300 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12301 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12302 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12303 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12304 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12305 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12306 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12307 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12308 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12309 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12310 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12311 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12312 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12313 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12314 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12315 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12317 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12318 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12319 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12320 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12321 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12322 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12323 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12324 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12325 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
12326 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
12327 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12328 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12329 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12330 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12331 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12332 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12334 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12335 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12336 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12337 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12338 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12339 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12340 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12341 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12342 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12343 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12344 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12345 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12346 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12347 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12348 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12349 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12350 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12351 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12352 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12353 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12354 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12355 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12356 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12357 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12358 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12359 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12360 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12361 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12362 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12363 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12364 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12365 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12366 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12367 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12368 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12369 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12370 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12371 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12372 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12373 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12374 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12375 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12376 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12377 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12378 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12379 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12380 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12381 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12382 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12383 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12384 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12385 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12386 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12387 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12388 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12389 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12390 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12391 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12392 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
12393 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12394 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
12395 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
12396 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
12397 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
12398 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12399 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12400 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12401 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12402 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12403 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12404 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12405 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12406 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12407 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12408 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12409 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12410 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12411 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12412 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12413 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12414 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12415 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12416 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
12417 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
12418 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12419 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12420 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12421 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12422 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12423 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12424 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12425 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12426 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12427 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12428 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12429 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12430 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12431 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12432 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12433 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12435 /* Sundry other built-in functions. */
12436 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12439 /* MODE is a vector mode whose elements have type TYPE. Return the type
12440 of the vector itself. */
12443 mips_builtin_vector_type (tree type, enum machine_mode mode)
12445 static tree types[2 * (int) MAX_MACHINE_MODE];
12448 mode_index = (int) mode;
12450 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12451 mode_index += MAX_MACHINE_MODE;
12453 if (types[mode_index] == NULL_TREE)
12454 types[mode_index] = build_vector_type_for_mode (type, mode);
12455 return types[mode_index];
12458 /* Return a type for 'const volatile void *'. */
12461 mips_build_cvpointer_type (void)
12465 if (cache == NULL_TREE)
12466 cache = build_pointer_type (build_qualified_type
12468 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12472 /* Source-level argument types. */
12473 #define MIPS_ATYPE_VOID void_type_node
12474 #define MIPS_ATYPE_INT integer_type_node
12475 #define MIPS_ATYPE_POINTER ptr_type_node
12476 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12478 /* Standard mode-based argument types. */
12479 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12480 #define MIPS_ATYPE_SI intSI_type_node
12481 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12482 #define MIPS_ATYPE_DI intDI_type_node
12483 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12484 #define MIPS_ATYPE_SF float_type_node
12485 #define MIPS_ATYPE_DF double_type_node
12487 /* Vector argument types. */
12488 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12489 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12490 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12491 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12492 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12493 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12494 #define MIPS_ATYPE_UV2SI \
12495 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12496 #define MIPS_ATYPE_UV4HI \
12497 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
12498 #define MIPS_ATYPE_UV8QI \
12499 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
12501 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
12502 their associated MIPS_ATYPEs. */
12503 #define MIPS_FTYPE_ATYPES1(A, B) \
12504 MIPS_ATYPE_##A, MIPS_ATYPE_##B
12506 #define MIPS_FTYPE_ATYPES2(A, B, C) \
12507 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
12509 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
12510 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
12512 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
12513 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
12516 /* Return the function type associated with function prototype TYPE. */
12519 mips_build_function_type (enum mips_function_type type)
12521 static tree types[(int) MIPS_MAX_FTYPE_MAX];
12523 if (types[(int) type] == NULL_TREE)
12526 #define DEF_MIPS_FTYPE(NUM, ARGS) \
12527 case MIPS_FTYPE_NAME##NUM ARGS: \
12528 types[(int) type] \
12529 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
12532 #include "config/mips/mips-ftypes.def"
12533 #undef DEF_MIPS_FTYPE
12535 gcc_unreachable ();
12538 return types[(int) type];
12541 /* Implement TARGET_INIT_BUILTINS. */
12544 mips_init_builtins (void)
12546 const struct mips_builtin_description *d;
12549 /* Iterate through all of the bdesc arrays, initializing all of the
12550 builtin functions. */
12551 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
12553 d = &mips_builtins[i];
12555 add_builtin_function (d->name,
12556 mips_build_function_type (d->function_type),
12557 i, BUILT_IN_MD, NULL, NULL);
12561 /* Take argument ARGNO from EXP's argument list and convert it into a
12562 form suitable for input operand OPNO of instruction ICODE. Return the
12566 mips_prepare_builtin_arg (enum insn_code icode,
12567 unsigned int opno, tree exp, unsigned int argno)
12571 enum machine_mode mode;
12573 arg = CALL_EXPR_ARG (exp, argno);
12574 value = expand_normal (arg);
12575 mode = insn_data[icode].operand[opno].mode;
12576 if (!insn_data[icode].operand[opno].predicate (value, mode))
12578 /* We need to get the mode from ARG for two reasons:
12580 - to cope with address operands, where MODE is the mode of the
12581 memory, rather than of VALUE itself.
12583 - to cope with special predicates like pmode_register_operand,
12584 where MODE is VOIDmode. */
12585 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
12587 /* Check the predicate again. */
12588 if (!insn_data[icode].operand[opno].predicate (value, mode))
12590 error ("invalid argument to built-in function");
12598 /* Return an rtx suitable for output operand OP of instruction ICODE.
12599 If TARGET is non-null, try to use it where possible. */
12602 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
12604 enum machine_mode mode;
12606 mode = insn_data[icode].operand[op].mode;
12607 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
12608 target = gen_reg_rtx (mode);
12613 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
12614 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
12615 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
12616 suggests a good place to put the result. */
12619 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
12622 rtx ops[MAX_RECOG_OPERANDS];
12625 /* Map any target to operand 0. */
12629 target = mips_prepare_builtin_target (icode, opno, target);
12630 ops[opno] = target;
12634 /* Map the arguments to the other operands. The n_operands value
12635 for an expander includes match_dups and match_scratches as well as
12636 match_operands, so n_operands is only an upper bound on the number
12637 of arguments to the expander function. */
12638 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
12639 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
12640 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
12645 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
12649 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
12653 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
12657 gcc_unreachable ();
12662 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
12663 function; TYPE says which. EXP is the CALL_EXPR that calls the
12664 function, ICODE is the instruction that should be used to compare
12665 the first two arguments, and COND is the condition it should test.
12666 TARGET, if nonnull, suggests a good place to put the result. */
12669 mips_expand_builtin_movtf (enum mips_builtin_type type,
12670 enum insn_code icode, enum mips_fp_condition cond,
12671 rtx target, tree exp)
12673 rtx cmp_result, op0, op1;
12675 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
12676 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
12677 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
12678 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
12680 icode = CODE_FOR_mips_cond_move_tf_ps;
12681 target = mips_prepare_builtin_target (icode, 0, target);
12682 if (type == MIPS_BUILTIN_MOVT)
12684 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
12685 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
12689 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
12690 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
12692 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
12696 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
12697 into TARGET otherwise. Return TARGET. */
12700 mips_builtin_branch_and_move (rtx condition, rtx target,
12701 rtx value_if_true, rtx value_if_false)
12703 rtx true_label, done_label;
12705 true_label = gen_label_rtx ();
12706 done_label = gen_label_rtx ();
12708 /* First assume that CONDITION is false. */
12709 mips_emit_move (target, value_if_false);
12711 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
12712 emit_jump_insn (gen_condjump (condition, true_label));
12713 emit_jump_insn (gen_jump (done_label));
12716 /* Fix TARGET if CONDITION is true. */
12717 emit_label (true_label);
12718 mips_emit_move (target, value_if_true);
12720 emit_label (done_label);
12724 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
12725 the CALL_EXPR that calls the function, ICODE is the code of the
12726 comparison instruction, and COND is the condition it should test.
12727 TARGET, if nonnull, suggests a good place to put the boolean result. */
12730 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
12731 enum insn_code icode, enum mips_fp_condition cond,
12732 rtx target, tree exp)
12734 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
12737 if (target == 0 || GET_MODE (target) != SImode)
12738 target = gen_reg_rtx (SImode);
12740 /* The instruction should have a target operand, an operand for each
12741 argument, and an operand for COND. */
12742 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
12744 /* Prepare the operands to the comparison. */
12745 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
12746 for (argno = 0; argno < call_expr_nargs (exp); argno++)
12747 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
12749 switch (insn_data[icode].n_operands)
12752 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
12757 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
12758 args[2], args[3], GEN_INT (cond)));
12762 gcc_unreachable ();
12765 /* If the comparison sets more than one register, we define the result
12766 to be 0 if all registers are false and -1 if all registers are true.
12767 The value of the complete result is indeterminate otherwise. */
12768 switch (builtin_type)
12770 case MIPS_BUILTIN_CMP_ALL:
12771 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
12772 return mips_builtin_branch_and_move (condition, target,
12773 const0_rtx, const1_rtx);
12775 case MIPS_BUILTIN_CMP_UPPER:
12776 case MIPS_BUILTIN_CMP_LOWER:
12777 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
12778 condition = gen_single_cc (cmp_result, offset);
12779 return mips_builtin_branch_and_move (condition, target,
12780 const1_rtx, const0_rtx);
12783 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
12784 return mips_builtin_branch_and_move (condition, target,
12785 const1_rtx, const0_rtx);
12789 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
12790 if nonnull, suggests a good place to put the boolean result. */
12793 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
12795 rtx condition, cmp_result;
12798 if (target == 0 || GET_MODE (target) != SImode)
12799 target = gen_reg_rtx (SImode);
12801 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
12803 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
12808 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
12809 return mips_builtin_branch_and_move (condition, target,
12810 const1_rtx, const0_rtx);
12813 /* Implement TARGET_EXPAND_BUILTIN. */
12816 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
12817 enum machine_mode mode, int ignore)
12820 unsigned int fcode, avail;
12821 const struct mips_builtin_description *d;
12823 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12824 fcode = DECL_FUNCTION_CODE (fndecl);
12825 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
12826 d = &mips_builtins[fcode];
12827 avail = d->avail ();
12828 gcc_assert (avail != 0);
12831 error ("built-in function %qE not supported for MIPS16",
12832 DECL_NAME (fndecl));
12833 return ignore ? const0_rtx : CONST0_RTX (mode);
12835 switch (d->builtin_type)
12837 case MIPS_BUILTIN_DIRECT:
12838 return mips_expand_builtin_direct (d->icode, target, exp, true);
12840 case MIPS_BUILTIN_DIRECT_NO_TARGET:
12841 return mips_expand_builtin_direct (d->icode, target, exp, false);
12843 case MIPS_BUILTIN_MOVT:
12844 case MIPS_BUILTIN_MOVF:
12845 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
12846 d->cond, target, exp);
12848 case MIPS_BUILTIN_CMP_ANY:
12849 case MIPS_BUILTIN_CMP_ALL:
12850 case MIPS_BUILTIN_CMP_UPPER:
12851 case MIPS_BUILTIN_CMP_LOWER:
12852 case MIPS_BUILTIN_CMP_SINGLE:
12853 return mips_expand_builtin_compare (d->builtin_type, d->icode,
12854 d->cond, target, exp);
12856 case MIPS_BUILTIN_BPOSGE32:
12857 return mips_expand_builtin_bposge (d->builtin_type, target);
12859 gcc_unreachable ();
12862 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
12863 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
12864 struct mips16_constant {
12865 struct mips16_constant *next;
12868 enum machine_mode mode;
12871 /* Information about an incomplete MIPS16 constant pool. FIRST is the
12872 first constant, HIGHEST_ADDRESS is the highest address that the first
12873 byte of the pool can have, and INSN_ADDRESS is the current instruction
12875 struct mips16_constant_pool {
12876 struct mips16_constant *first;
12877 int highest_address;
12881 /* Add constant VALUE to POOL and return its label. MODE is the
12882 value's mode (used for CONST_INTs, etc.). */
12885 mips16_add_constant (struct mips16_constant_pool *pool,
12886 rtx value, enum machine_mode mode)
12888 struct mips16_constant **p, *c;
12889 bool first_of_size_p;
12891 /* See whether the constant is already in the pool. If so, return the
12892 existing label, otherwise leave P pointing to the place where the
12893 constant should be added.
12895 Keep the pool sorted in increasing order of mode size so that we can
12896 reduce the number of alignments needed. */
12897 first_of_size_p = true;
12898 for (p = &pool->first; *p != 0; p = &(*p)->next)
12900 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
12901 return (*p)->label;
12902 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
12904 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
12905 first_of_size_p = false;
12908 /* In the worst case, the constant needed by the earliest instruction
12909 will end up at the end of the pool. The entire pool must then be
12910 accessible from that instruction.
12912 When adding the first constant, set the pool's highest address to
12913 the address of the first out-of-range byte. Adjust this address
12914 downwards each time a new constant is added. */
12915 if (pool->first == 0)
12916 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
12917 of the instruction with the lowest two bits clear. The base PC
12918 value for LDPC has the lowest three bits clear. Assume the worst
12919 case here; namely that the PC-relative instruction occupies the
12920 last 2 bytes in an aligned word. */
12921 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
12922 pool->highest_address -= GET_MODE_SIZE (mode);
12923 if (first_of_size_p)
12924 /* Take into account the worst possible padding due to alignment. */
12925 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
12927 /* Create a new entry. */
12928 c = XNEW (struct mips16_constant);
12931 c->label = gen_label_rtx ();
12938 /* Output constant VALUE after instruction INSN and return the last
12939 instruction emitted. MODE is the mode of the constant. */
12942 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
12944 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
12946 rtx size = GEN_INT (GET_MODE_SIZE (mode));
12947 return emit_insn_after (gen_consttable_int (value, size), insn);
12950 if (SCALAR_FLOAT_MODE_P (mode))
12951 return emit_insn_after (gen_consttable_float (value), insn);
12953 if (VECTOR_MODE_P (mode))
12957 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
12958 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
12959 CONST_VECTOR_ELT (value, i), insn);
12963 gcc_unreachable ();
12966 /* Dump out the constants in CONSTANTS after INSN. */
12969 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
12971 struct mips16_constant *c, *next;
12975 for (c = constants; c != NULL; c = next)
12977 /* If necessary, increase the alignment of PC. */
12978 if (align < GET_MODE_SIZE (c->mode))
12980 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
12981 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
12983 align = GET_MODE_SIZE (c->mode);
12985 insn = emit_label_after (c->label, insn);
12986 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
12992 emit_barrier_after (insn);
12995 /* Return the length of instruction INSN. */
12998 mips16_insn_length (rtx insn)
13002 rtx body = PATTERN (insn);
13003 if (GET_CODE (body) == ADDR_VEC)
13004 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13005 if (GET_CODE (body) == ADDR_DIFF_VEC)
13006 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13008 return get_attr_length (insn);
13011 /* If *X is a symbolic constant that refers to the constant pool, add
13012 the constant to POOL and rewrite *X to use the constant's label. */
13015 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13017 rtx base, offset, label;
13019 split_const (*x, &base, &offset);
13020 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13022 label = mips16_add_constant (pool, get_pool_constant (base),
13023 get_pool_mode (base));
13024 base = gen_rtx_LABEL_REF (Pmode, label);
13025 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13029 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13030 INSN is the instruction we're rewriting and POOL points to the current
13032 struct mips16_rewrite_pool_refs_info {
13034 struct mips16_constant_pool *pool;
13037 /* Rewrite *X so that constant pool references refer to the constant's
13038 label instead. DATA points to a mips16_rewrite_pool_refs_info
13042 mips16_rewrite_pool_refs (rtx *x, void *data)
13044 struct mips16_rewrite_pool_refs_info *info =
13045 (struct mips16_rewrite_pool_refs_info *) data;
13047 if (force_to_mem_operand (*x, Pmode))
13049 rtx mem = force_const_mem (GET_MODE (*x), *x);
13050 validate_change (info->insn, x, mem, false);
13055 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13059 if (TARGET_MIPS16_TEXT_LOADS)
13060 mips16_rewrite_pool_constant (info->pool, x);
13062 return GET_CODE (*x) == CONST ? -1 : 0;
13065 /* Build MIPS16 constant pools. */
13068 mips16_lay_out_constants (void)
13070 struct mips16_constant_pool pool;
13071 struct mips16_rewrite_pool_refs_info info;
13074 if (!TARGET_MIPS16_PCREL_LOADS)
13077 split_all_insns_noflow ();
13079 memset (&pool, 0, sizeof (pool));
13080 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13082 /* Rewrite constant pool references in INSN. */
13087 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13090 pool.insn_address += mips16_insn_length (insn);
13092 if (pool.first != NULL)
13094 /* If there are no natural barriers between the first user of
13095 the pool and the highest acceptable address, we'll need to
13096 create a new instruction to jump around the constant pool.
13097 In the worst case, this instruction will be 4 bytes long.
13099 If it's too late to do this transformation after INSN,
13100 do it immediately before INSN. */
13101 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13105 label = gen_label_rtx ();
13107 jump = emit_jump_insn_before (gen_jump (label), insn);
13108 JUMP_LABEL (jump) = label;
13109 LABEL_NUSES (label) = 1;
13110 barrier = emit_barrier_after (jump);
13112 emit_label_after (label, barrier);
13113 pool.insn_address += 4;
13116 /* See whether the constant pool is now out of range of the first
13117 user. If so, output the constants after the previous barrier.
13118 Note that any instructions between BARRIER and INSN (inclusive)
13119 will use negative offsets to refer to the pool. */
13120 if (pool.insn_address > pool.highest_address)
13122 mips16_emit_constants (pool.first, barrier);
13126 else if (BARRIER_P (insn))
13130 mips16_emit_constants (pool.first, get_last_insn ());
13133 /* Return true if it is worth r10k_simplify_address's while replacing
13134 an address with X. We are looking for constants, and for addresses
13135 at a known offset from the incoming stack pointer. */
13138 r10k_simplified_address_p (rtx x)
13140 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13142 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13145 /* X is an expression that appears in INSN. Try to use the UD chains
13146 to simplify it, returning the simplified form on success and the
13147 original form otherwise. Replace the incoming value of $sp with
13148 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13151 r10k_simplify_address (rtx x, rtx insn)
13153 rtx newx, op0, op1, set, def_insn, note;
13155 struct df_link *defs;
13160 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13161 if (op0 != XEXP (x, 0))
13162 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13163 op0, GET_MODE (XEXP (x, 0)));
13165 else if (BINARY_P (x))
13167 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13168 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13169 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13170 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13172 else if (GET_CODE (x) == LO_SUM)
13174 /* LO_SUMs can be offset from HIGHs, if we know they won't
13175 overflow. See mips_classify_address for the rationale behind
13177 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13178 if (GET_CODE (op0) == HIGH)
13179 newx = XEXP (x, 1);
13181 else if (REG_P (x))
13183 /* Uses are recorded by regno_reg_rtx, not X itself. */
13184 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13186 defs = DF_REF_CHAIN (use);
13188 /* Require a single definition. */
13189 if (defs && defs->next == NULL)
13192 if (DF_REF_IS_ARTIFICIAL (def))
13194 /* Replace the incoming value of $sp with
13195 virtual_incoming_args_rtx. */
13196 if (x == stack_pointer_rtx
13197 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13198 newx = virtual_incoming_args_rtx;
13200 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13203 /* Make sure that DEF_INSN is a single set of REG. */
13204 def_insn = DF_REF_INSN (def);
13205 if (NONJUMP_INSN_P (def_insn))
13207 set = single_set (def_insn);
13208 if (set && rtx_equal_p (SET_DEST (set), x))
13210 /* Prefer to use notes, since the def-use chains
13211 are often shorter. */
13212 note = find_reg_equal_equiv_note (def_insn);
13214 newx = XEXP (note, 0);
13216 newx = SET_SRC (set);
13217 newx = r10k_simplify_address (newx, def_insn);
13223 if (newx && r10k_simplified_address_p (newx))
13228 /* Return true if ADDRESS is known to be an uncached address
13229 on R10K systems. */
13232 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13234 unsigned HOST_WIDE_INT upper;
13236 /* Check for KSEG1. */
13237 if (address + 0x60000000 < 0x20000000)
13240 /* Check for uncached XKPHYS addresses. */
13241 if (Pmode == DImode)
13243 upper = (address >> 40) & 0xf9ffff;
13244 if (upper == 0x900000 || upper == 0xb80000)
13250 /* Return true if we can prove that an access to address X in instruction
13251 INSN would be safe from R10K speculation. This X is a general
13252 expression; it might not be a legitimate address. */
13255 r10k_safe_address_p (rtx x, rtx insn)
13258 HOST_WIDE_INT offset_val;
13260 x = r10k_simplify_address (x, insn);
13262 /* Check for references to the stack frame. It doesn't really matter
13263 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13264 allows us to assume that accesses to any part of the eventual frame
13265 is safe from speculation at any point in the function. */
13266 mips_split_plus (x, &base, &offset_val);
13267 if (base == virtual_incoming_args_rtx
13268 && offset_val >= -cfun->machine->frame.total_size
13269 && offset_val < cfun->machine->frame.args_size)
13272 /* Check for uncached addresses. */
13273 if (CONST_INT_P (x))
13274 return r10k_uncached_address_p (INTVAL (x));
13276 /* Check for accesses to a static object. */
13277 split_const (x, &base, &offset);
13278 return offset_within_block_p (base, INTVAL (offset));
13281 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13282 an in-range access to an automatic variable, or to an object with
13283 a link-time-constant address. */
13286 r10k_safe_mem_expr_p (tree expr, rtx offset)
13288 if (expr == NULL_TREE
13289 || offset == NULL_RTX
13290 || !CONST_INT_P (offset)
13291 || INTVAL (offset) < 0
13292 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13295 while (TREE_CODE (expr) == COMPONENT_REF)
13297 expr = TREE_OPERAND (expr, 0);
13298 if (expr == NULL_TREE)
13302 return DECL_P (expr);
13305 /* A for_each_rtx callback for which DATA points to the instruction
13306 containing *X. Stop the search if we find a MEM that is not safe
13307 from R10K speculation. */
13310 r10k_needs_protection_p_1 (rtx *loc, void *data)
13318 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13321 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13327 /* A note_stores callback for which DATA points to an instruction pointer.
13328 If *DATA is nonnull, make it null if it X contains a MEM that is not
13329 safe from R10K speculation. */
13332 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13337 insn_ptr = (rtx *) data;
13338 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13339 *insn_ptr = NULL_RTX;
13342 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13343 Return nonzero if the call is not to a declared function. */
13346 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13355 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13361 /* Return true if instruction INSN needs to be protected by an R10K
13365 r10k_needs_protection_p (rtx insn)
13368 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13370 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13372 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13373 return insn == NULL_RTX;
13376 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13379 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13380 edge is unconditional. */
13383 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13388 FOR_EACH_EDGE (e, ei, bb->preds)
13389 if (!single_succ_p (e->src)
13390 || !TEST_BIT (protected_bbs, e->src->index)
13391 || (e->flags & EDGE_COMPLEX) != 0)
13396 /* Implement -mr10k-cache-barrier= for the current function. */
13399 r10k_insert_cache_barriers (void)
13401 int *rev_post_order;
13404 sbitmap protected_bbs;
13405 rtx insn, end, unprotected_region;
13409 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13413 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
13414 compute_bb_for_insn ();
13416 /* Create def-use chains. */
13417 df_set_flags (DF_EQ_NOTES);
13418 df_chain_add_problem (DF_UD_CHAIN);
13421 /* Calculate dominators. */
13422 calculate_dominance_info (CDI_DOMINATORS);
13424 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13425 X is protected by a cache barrier. */
13426 protected_bbs = sbitmap_alloc (last_basic_block);
13427 sbitmap_zero (protected_bbs);
13429 /* Iterate over the basic blocks in reverse post-order. */
13430 rev_post_order = XNEWVEC (int, last_basic_block);
13431 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13432 for (i = 0; i < n; i++)
13434 bb = BASIC_BLOCK (rev_post_order[i]);
13436 /* If this block is only reached by unconditional edges, and if the
13437 source of every edge is protected, the beginning of the block is
13439 if (r10k_protected_bb_p (bb, protected_bbs))
13440 unprotected_region = NULL_RTX;
13442 unprotected_region = pc_rtx;
13443 end = NEXT_INSN (BB_END (bb));
13445 /* UNPROTECTED_REGION is:
13447 - null if we are processing a protected region,
13448 - pc_rtx if we are processing an unprotected region but have
13449 not yet found the first instruction in it
13450 - the first instruction in an unprotected region otherwise. */
13451 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13453 if (unprotected_region && INSN_P (insn))
13455 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13456 /* This CACHE instruction protects the following code. */
13457 unprotected_region = NULL_RTX;
13460 /* See if INSN is the first instruction in this
13461 unprotected region. */
13462 if (unprotected_region == pc_rtx)
13463 unprotected_region = insn;
13465 /* See if INSN needs to be protected. If so,
13466 we must insert a cache barrier somewhere between
13467 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13468 clear which position is better performance-wise,
13469 but as a tie-breaker, we assume that it is better
13470 to allow delay slots to be back-filled where
13471 possible, and that it is better not to insert
13472 barriers in the middle of already-scheduled code.
13473 We therefore insert the barrier at the beginning
13475 if (r10k_needs_protection_p (insn))
13477 emit_insn_before (gen_r10k_cache_barrier (),
13478 unprotected_region);
13479 unprotected_region = NULL_RTX;
13485 /* The called function is not required to protect the exit path.
13486 The code that follows a call is therefore unprotected. */
13487 unprotected_region = pc_rtx;
13490 /* Record whether the end of this block is protected. */
13491 if (unprotected_region == NULL_RTX)
13492 SET_BIT (protected_bbs, bb->index);
13494 XDELETEVEC (rev_post_order);
13496 sbitmap_free (protected_bbs);
13498 free_dominance_info (CDI_DOMINATORS);
13500 df_finish_pass (false);
13502 free_bb_for_insn ();
13505 /* A temporary variable used by for_each_rtx callbacks, etc. */
13506 static rtx mips_sim_insn;
13508 /* A structure representing the state of the processor pipeline.
13509 Used by the mips_sim_* family of functions. */
13511 /* The maximum number of instructions that can be issued in a cycle.
13512 (Caches mips_issue_rate.) */
13513 unsigned int issue_rate;
13515 /* The current simulation time. */
13518 /* How many more instructions can be issued in the current cycle. */
13519 unsigned int insns_left;
13521 /* LAST_SET[X].INSN is the last instruction to set register X.
13522 LAST_SET[X].TIME is the time at which that instruction was issued.
13523 INSN is null if no instruction has yet set register X. */
13527 } last_set[FIRST_PSEUDO_REGISTER];
13529 /* The pipeline's current DFA state. */
13533 /* Reset STATE to the initial simulation state. */
13536 mips_sim_reset (struct mips_sim *state)
13539 state->insns_left = state->issue_rate;
13540 memset (&state->last_set, 0, sizeof (state->last_set));
13541 state_reset (state->dfa_state);
13544 /* Initialize STATE before its first use. DFA_STATE points to an
13545 allocated but uninitialized DFA state. */
13548 mips_sim_init (struct mips_sim *state, state_t dfa_state)
13550 state->issue_rate = mips_issue_rate ();
13551 state->dfa_state = dfa_state;
13552 mips_sim_reset (state);
13555 /* Advance STATE by one clock cycle. */
13558 mips_sim_next_cycle (struct mips_sim *state)
13561 state->insns_left = state->issue_rate;
13562 state_transition (state->dfa_state, 0);
13565 /* Advance simulation state STATE until instruction INSN can read
13569 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
13571 unsigned int regno, end_regno;
13573 end_regno = END_REGNO (reg);
13574 for (regno = REGNO (reg); regno < end_regno; regno++)
13575 if (state->last_set[regno].insn != 0)
13579 t = (state->last_set[regno].time
13580 + insn_latency (state->last_set[regno].insn, insn));
13581 while (state->time < t)
13582 mips_sim_next_cycle (state);
13586 /* A for_each_rtx callback. If *X is a register, advance simulation state
13587 DATA until mips_sim_insn can read the register's value. */
13590 mips_sim_wait_regs_2 (rtx *x, void *data)
13593 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
13597 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
13600 mips_sim_wait_regs_1 (rtx *x, void *data)
13602 for_each_rtx (x, mips_sim_wait_regs_2, data);
13605 /* Advance simulation state STATE until all of INSN's register
13606 dependencies are satisfied. */
13609 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
13611 mips_sim_insn = insn;
13612 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
13615 /* Advance simulation state STATE until the units required by
13616 instruction INSN are available. */
13619 mips_sim_wait_units (struct mips_sim *state, rtx insn)
13623 tmp_state = alloca (state_size ());
13624 while (state->insns_left == 0
13625 || (memcpy (tmp_state, state->dfa_state, state_size ()),
13626 state_transition (tmp_state, insn) >= 0))
13627 mips_sim_next_cycle (state);
13630 /* Advance simulation state STATE until INSN is ready to issue. */
13633 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
13635 mips_sim_wait_regs (state, insn);
13636 mips_sim_wait_units (state, insn);
13639 /* mips_sim_insn has just set X. Update the LAST_SET array
13640 in simulation state DATA. */
13643 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
13645 struct mips_sim *state;
13647 state = (struct mips_sim *) data;
13650 unsigned int regno, end_regno;
13652 end_regno = END_REGNO (x);
13653 for (regno = REGNO (x); regno < end_regno; regno++)
13655 state->last_set[regno].insn = mips_sim_insn;
13656 state->last_set[regno].time = state->time;
13661 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
13662 can issue immediately (i.e., that mips_sim_wait_insn has already
13666 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
13668 state_transition (state->dfa_state, insn);
13669 state->insns_left--;
13671 mips_sim_insn = insn;
13672 note_stores (PATTERN (insn), mips_sim_record_set, state);
13675 /* Simulate issuing a NOP in state STATE. */
13678 mips_sim_issue_nop (struct mips_sim *state)
13680 if (state->insns_left == 0)
13681 mips_sim_next_cycle (state);
13682 state->insns_left--;
13685 /* Update simulation state STATE so that it's ready to accept the instruction
13686 after INSN. INSN should be part of the main rtl chain, not a member of a
13690 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
13692 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
13694 mips_sim_issue_nop (state);
13696 switch (GET_CODE (SEQ_BEGIN (insn)))
13700 /* We can't predict the processor state after a call or label. */
13701 mips_sim_reset (state);
13705 /* The delay slots of branch likely instructions are only executed
13706 when the branch is taken. Therefore, if the caller has simulated
13707 the delay slot instruction, STATE does not really reflect the state
13708 of the pipeline for the instruction after the delay slot. Also,
13709 branch likely instructions tend to incur a penalty when not taken,
13710 so there will probably be an extra delay between the branch and
13711 the instruction after the delay slot. */
13712 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
13713 mips_sim_reset (state);
13721 /* The VR4130 pipeline issues aligned pairs of instructions together,
13722 but it stalls the second instruction if it depends on the first.
13723 In order to cut down the amount of logic required, this dependence
13724 check is not based on a full instruction decode. Instead, any non-SPECIAL
13725 instruction is assumed to modify the register specified by bits 20-16
13726 (which is usually the "rt" field).
13728 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
13729 input, so we can end up with a false dependence between the branch
13730 and its delay slot. If this situation occurs in instruction INSN,
13731 try to avoid it by swapping rs and rt. */
13734 vr4130_avoid_branch_rt_conflict (rtx insn)
13738 first = SEQ_BEGIN (insn);
13739 second = SEQ_END (insn);
13741 && NONJUMP_INSN_P (second)
13742 && GET_CODE (PATTERN (first)) == SET
13743 && GET_CODE (SET_DEST (PATTERN (first))) == PC
13744 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
13746 /* Check for the right kind of condition. */
13747 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
13748 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
13749 && REG_P (XEXP (cond, 0))
13750 && REG_P (XEXP (cond, 1))
13751 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
13752 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
13754 /* SECOND mentions the rt register but not the rs register. */
13755 rtx tmp = XEXP (cond, 0);
13756 XEXP (cond, 0) = XEXP (cond, 1);
13757 XEXP (cond, 1) = tmp;
13762 /* Implement -mvr4130-align. Go through each basic block and simulate the
13763 processor pipeline. If we find that a pair of instructions could execute
13764 in parallel, and the first of those instructions is not 8-byte aligned,
13765 insert a nop to make it aligned. */
13768 vr4130_align_insns (void)
13770 struct mips_sim state;
13771 rtx insn, subinsn, last, last2, next;
13776 /* LAST is the last instruction before INSN to have a nonzero length.
13777 LAST2 is the last such instruction before LAST. */
13781 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
13784 mips_sim_init (&state, alloca (state_size ()));
13785 for (insn = get_insns (); insn != 0; insn = next)
13787 unsigned int length;
13789 next = NEXT_INSN (insn);
13791 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
13792 This isn't really related to the alignment pass, but we do it on
13793 the fly to avoid a separate instruction walk. */
13794 vr4130_avoid_branch_rt_conflict (insn);
13796 if (USEFUL_INSN_P (insn))
13797 FOR_EACH_SUBINSN (subinsn, insn)
13799 mips_sim_wait_insn (&state, subinsn);
13801 /* If we want this instruction to issue in parallel with the
13802 previous one, make sure that the previous instruction is
13803 aligned. There are several reasons why this isn't worthwhile
13804 when the second instruction is a call:
13806 - Calls are less likely to be performance critical,
13807 - There's a good chance that the delay slot can execute
13808 in parallel with the call.
13809 - The return address would then be unaligned.
13811 In general, if we're going to insert a nop between instructions
13812 X and Y, it's better to insert it immediately after X. That
13813 way, if the nop makes Y aligned, it will also align any labels
13814 between X and Y. */
13815 if (state.insns_left != state.issue_rate
13816 && !CALL_P (subinsn))
13818 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
13820 /* SUBINSN is the first instruction in INSN and INSN is
13821 aligned. We want to align the previous instruction
13822 instead, so insert a nop between LAST2 and LAST.
13824 Note that LAST could be either a single instruction
13825 or a branch with a delay slot. In the latter case,
13826 LAST, like INSN, is already aligned, but the delay
13827 slot must have some extra delay that stops it from
13828 issuing at the same time as the branch. We therefore
13829 insert a nop before the branch in order to align its
13831 emit_insn_after (gen_nop (), last2);
13834 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
13836 /* SUBINSN is the delay slot of INSN, but INSN is
13837 currently unaligned. Insert a nop between
13838 LAST and INSN to align it. */
13839 emit_insn_after (gen_nop (), last);
13843 mips_sim_issue_insn (&state, subinsn);
13845 mips_sim_finish_insn (&state, insn);
13847 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
13848 length = get_attr_length (insn);
13851 /* If the instruction is an asm statement or multi-instruction
13852 mips.md patern, the length is only an estimate. Insert an
13853 8 byte alignment after it so that the following instructions
13854 can be handled correctly. */
13855 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
13856 && (recog_memoized (insn) < 0 || length >= 8))
13858 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
13859 next = NEXT_INSN (next);
13860 mips_sim_next_cycle (&state);
13863 else if (length & 4)
13864 aligned_p = !aligned_p;
13869 /* See whether INSN is an aligned label. */
13870 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
13876 /* This structure records that the current function has a LO_SUM
13877 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
13878 the largest offset applied to BASE by all such LO_SUMs. */
13879 struct mips_lo_sum_offset {
13881 HOST_WIDE_INT offset;
13884 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
13887 mips_hash_base (rtx base)
13889 int do_not_record_p;
13891 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
13894 /* Hash-table callbacks for mips_lo_sum_offsets. */
13897 mips_lo_sum_offset_hash (const void *entry)
13899 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
13903 mips_lo_sum_offset_eq (const void *entry, const void *value)
13905 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
13906 (const_rtx) value);
13909 /* Look up symbolic constant X in HTAB, which is a hash table of
13910 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
13911 paired with a recorded LO_SUM, otherwise record X in the table. */
13914 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
13918 struct mips_lo_sum_offset *entry;
13920 /* Split X into a base and offset. */
13921 split_const (x, &base, &offset);
13922 if (UNSPEC_ADDRESS_P (base))
13923 base = UNSPEC_ADDRESS (base);
13925 /* Look up the base in the hash table. */
13926 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
13930 entry = (struct mips_lo_sum_offset *) *slot;
13931 if (option == INSERT)
13935 entry = XNEW (struct mips_lo_sum_offset);
13936 entry->base = base;
13937 entry->offset = INTVAL (offset);
13942 if (INTVAL (offset) > entry->offset)
13943 entry->offset = INTVAL (offset);
13946 return INTVAL (offset) <= entry->offset;
13949 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
13950 Record every LO_SUM in *LOC. */
13953 mips_record_lo_sum (rtx *loc, void *data)
13955 if (GET_CODE (*loc) == LO_SUM)
13956 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
13960 /* Return true if INSN is a SET of an orphaned high-part relocation.
13961 HTAB is a hash table of mips_lo_sum_offsets that describes all the
13962 LO_SUMs in the current function. */
13965 mips_orphaned_high_part_p (htab_t htab, rtx insn)
13967 enum mips_symbol_type type;
13970 set = single_set (insn);
13973 /* Check for %his. */
13975 if (GET_CODE (x) == HIGH
13976 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
13977 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
13979 /* Check for local %gots (and %got_pages, which is redundant but OK). */
13980 if (GET_CODE (x) == UNSPEC
13981 && XINT (x, 1) == UNSPEC_LOAD_GOT
13982 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
13983 SYMBOL_CONTEXT_LEA, &type)
13984 && type == SYMBOL_GOTOFF_PAGE)
13985 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
13990 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
13991 INSN and a previous instruction, avoid it by inserting nops after
13994 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
13995 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
13996 before using the value of that register. *HILO_DELAY counts the
13997 number of instructions since the last hilo hazard (that is,
13998 the number of instructions since the last MFLO or MFHI).
14000 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14001 for the next instruction.
14003 LO_REG is an rtx for the LO register, used in dependence checking. */
14006 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14007 rtx *delayed_reg, rtx lo_reg)
14012 pattern = PATTERN (insn);
14014 /* Do not put the whole function in .set noreorder if it contains
14015 an asm statement. We don't know whether there will be hazards
14016 between the asm statement and the gcc-generated code. */
14017 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14018 cfun->machine->all_noreorder_p = false;
14020 /* Ignore zero-length instructions (barriers and the like). */
14021 ninsns = get_attr_length (insn) / 4;
14025 /* Work out how many nops are needed. Note that we only care about
14026 registers that are explicitly mentioned in the instruction's pattern.
14027 It doesn't matter that calls use the argument registers or that they
14028 clobber hi and lo. */
14029 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14030 nops = 2 - *hilo_delay;
14031 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14036 /* Insert the nops between this instruction and the previous one.
14037 Each new nop takes us further from the last hilo hazard. */
14038 *hilo_delay += nops;
14040 emit_insn_after (gen_hazard_nop (), after);
14042 /* Set up the state for the next instruction. */
14043 *hilo_delay += ninsns;
14045 if (INSN_CODE (insn) >= 0)
14046 switch (get_attr_hazard (insn))
14056 set = single_set (insn);
14058 *delayed_reg = SET_DEST (set);
14063 /* Go through the instruction stream and insert nops where necessary.
14064 Also delete any high-part relocations whose partnering low parts
14065 are now all dead. See if the whole function can then be put into
14066 .set noreorder and .set nomacro. */
14069 mips_reorg_process_insns (void)
14071 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14075 /* Force all instructions to be split into their final form. */
14076 split_all_insns_noflow ();
14078 /* Recalculate instruction lengths without taking nops into account. */
14079 cfun->machine->ignore_hazard_length_p = true;
14080 shorten_branches (get_insns ());
14082 cfun->machine->all_noreorder_p = true;
14084 /* We don't track MIPS16 PC-relative offsets closely enough to make
14085 a good job of "set .noreorder" code in MIPS16 mode. */
14087 cfun->machine->all_noreorder_p = false;
14089 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14090 if (!TARGET_EXPLICIT_RELOCS)
14091 cfun->machine->all_noreorder_p = false;
14093 /* Profiled functions can't be all noreorder because the profiler
14094 support uses assembler macros. */
14096 cfun->machine->all_noreorder_p = false;
14098 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14099 we rely on the assembler to work around some errata. */
14100 if (TARGET_FIX_VR4120)
14101 cfun->machine->all_noreorder_p = false;
14103 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14104 MFHI instructions. Note that we avoid using MFLO and MFHI if
14105 the VR4130 MACC and DMACC instructions are available instead;
14106 see the *mfhilo_{si,di}_macc patterns. */
14107 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14108 cfun->machine->all_noreorder_p = false;
14110 htab = htab_create (37, mips_lo_sum_offset_hash,
14111 mips_lo_sum_offset_eq, free);
14113 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14114 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14115 FOR_EACH_SUBINSN (subinsn, insn)
14116 if (INSN_P (subinsn))
14117 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14122 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14124 /* Make a second pass over the instructions. Delete orphaned
14125 high-part relocations or turn them into NOPs. Avoid hazards
14126 by inserting NOPs. */
14127 for (insn = get_insns (); insn != 0; insn = next_insn)
14129 next_insn = NEXT_INSN (insn);
14132 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14134 /* If we find an orphaned high-part relocation in a delay
14135 slot, it's easier to turn that instruction into a NOP than
14136 to delete it. The delay slot will be a NOP either way. */
14137 FOR_EACH_SUBINSN (subinsn, insn)
14138 if (INSN_P (subinsn))
14140 if (mips_orphaned_high_part_p (htab, subinsn))
14142 PATTERN (subinsn) = gen_nop ();
14143 INSN_CODE (subinsn) = CODE_FOR_nop;
14145 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14146 &delayed_reg, lo_reg);
14152 /* INSN is a single instruction. Delete it if it's an
14153 orphaned high-part relocation. */
14154 if (mips_orphaned_high_part_p (htab, insn))
14155 delete_insn (insn);
14156 /* Also delete cache barriers if the last instruction
14157 was an annulled branch. INSN will not be speculatively
14159 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14161 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14162 delete_insn (insn);
14165 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14166 &delayed_reg, lo_reg);
14173 htab_delete (htab);
14176 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14181 mips16_lay_out_constants ();
14182 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
14183 r10k_insert_cache_barriers ();
14184 if (optimize > 0 && flag_delayed_branch)
14185 dbr_schedule (get_insns ());
14186 mips_reorg_process_insns ();
14188 && TARGET_EXPLICIT_RELOCS
14190 && TARGET_VR4130_ALIGN)
14191 vr4130_align_insns ();
14194 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14195 in order to avoid duplicating too much logic from elsewhere. */
14198 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14199 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14202 rtx this_rtx, temp1, temp2, insn, fnaddr;
14203 bool use_sibcall_p;
14205 /* Pretend to be a post-reload pass while generating rtl. */
14206 reload_completed = 1;
14208 /* Mark the end of the (empty) prologue. */
14209 emit_note (NOTE_INSN_PROLOGUE_END);
14211 /* Determine if we can use a sibcall to call FUNCTION directly. */
14212 fnaddr = XEXP (DECL_RTL (function), 0);
14213 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
14214 && const_call_insn_operand (fnaddr, Pmode));
14216 /* Determine if we need to load FNADDR from the GOT. */
14218 && (mips_got_symbol_type_p
14219 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
14221 /* Pick a global pointer. Use a call-clobbered register if
14222 TARGET_CALL_SAVED_GP. */
14223 cfun->machine->global_pointer
14224 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
14225 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
14227 /* Set up the global pointer for n32 or n64 abicalls. */
14228 mips_emit_loadgp ();
14231 /* We need two temporary registers in some cases. */
14232 temp1 = gen_rtx_REG (Pmode, 2);
14233 temp2 = gen_rtx_REG (Pmode, 3);
14235 /* Find out which register contains the "this" pointer. */
14236 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14237 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
14239 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
14241 /* Add DELTA to THIS_RTX. */
14244 rtx offset = GEN_INT (delta);
14245 if (!SMALL_OPERAND (delta))
14247 mips_emit_move (temp1, offset);
14250 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
14253 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
14254 if (vcall_offset != 0)
14258 /* Set TEMP1 to *THIS_RTX. */
14259 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
14261 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
14262 addr = mips_add_offset (temp2, temp1, vcall_offset);
14264 /* Load the offset and add it to THIS_RTX. */
14265 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
14266 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
14269 /* Jump to the target function. Use a sibcall if direct jumps are
14270 allowed, otherwise load the address into a register first. */
14273 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
14274 SIBLING_CALL_P (insn) = 1;
14278 /* This is messy. GAS treats "la $25,foo" as part of a call
14279 sequence and may allow a global "foo" to be lazily bound.
14280 The general move patterns therefore reject this combination.
14282 In this context, lazy binding would actually be OK
14283 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
14284 TARGET_CALL_SAVED_GP; see mips_load_call_address.
14285 We must therefore load the address via a temporary
14286 register if mips_dangerous_for_la25_p.
14288 If we jump to the temporary register rather than $25,
14289 the assembler can use the move insn to fill the jump's
14292 We can use the same technique for MIPS16 code, where $25
14293 is not a valid JR register. */
14294 if (TARGET_USE_PIC_FN_ADDR_REG
14296 && !mips_dangerous_for_la25_p (fnaddr))
14297 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
14298 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
14300 if (TARGET_USE_PIC_FN_ADDR_REG
14301 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
14302 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
14303 emit_jump_insn (gen_indirect_jump (temp1));
14306 /* Run just enough of rest_of_compilation. This sequence was
14307 "borrowed" from alpha.c. */
14308 insn = get_insns ();
14309 insn_locators_alloc ();
14310 split_all_insns_noflow ();
14311 mips16_lay_out_constants ();
14312 shorten_branches (insn);
14313 final_start_function (insn, file, 1);
14314 final (insn, file, 1);
14315 final_end_function ();
14317 /* Clean up the vars set above. Note that final_end_function resets
14318 the global pointer for us. */
14319 reload_completed = 0;
14322 /* The last argument passed to mips_set_mips16_mode, or negative if the
14323 function hasn't been called yet.
14325 There are two copies of this information. One is saved and restored
14326 by the PCH process while the other is specific to this compiler
14327 invocation. The information calculated by mips_set_mips16_mode
14328 is invalid unless the two variables are the same. */
14329 static int was_mips16_p = -1;
14330 static GTY(()) int was_mips16_pch_p = -1;
14332 /* Set up the target-dependent global state so that it matches the
14333 current function's ISA mode. */
14336 mips_set_mips16_mode (int mips16_p)
14338 if (mips16_p == was_mips16_p
14339 && mips16_p == was_mips16_pch_p)
14342 /* Restore base settings of various flags. */
14343 target_flags = mips_base_target_flags;
14344 flag_schedule_insns = mips_base_schedule_insns;
14345 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
14346 flag_move_loop_invariants = mips_base_move_loop_invariants;
14347 align_loops = mips_base_align_loops;
14348 align_jumps = mips_base_align_jumps;
14349 align_functions = mips_base_align_functions;
14353 /* Switch to MIPS16 mode. */
14354 target_flags |= MASK_MIPS16;
14356 /* Don't run the scheduler before reload, since it tends to
14357 increase register pressure. */
14358 flag_schedule_insns = 0;
14360 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
14361 the whole function to be in a single section. */
14362 flag_reorder_blocks_and_partition = 0;
14364 /* Don't move loop invariants, because it tends to increase
14365 register pressure. It also introduces an extra move in cases
14366 where the constant is the first operand in a two-operand binary
14367 instruction, or when it forms a register argument to a functon
14369 flag_move_loop_invariants = 0;
14371 target_flags |= MASK_EXPLICIT_RELOCS;
14373 /* Experiments suggest we get the best overall section-anchor
14374 results from using the range of an unextended LW or SW. Code
14375 that makes heavy use of byte or short accesses can do better
14376 with ranges of 0...31 and 0...63 respectively, but most code is
14377 sensitive to the range of LW and SW instead. */
14378 targetm.min_anchor_offset = 0;
14379 targetm.max_anchor_offset = 127;
14381 targetm.const_anchor = 0;
14383 if (flag_pic && !TARGET_OLDABI)
14384 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
14387 sorry ("MIPS16 -mxgot code");
14389 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
14390 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
14394 /* Switch to normal (non-MIPS16) mode. */
14395 target_flags &= ~MASK_MIPS16;
14397 /* Provide default values for align_* for 64-bit targets. */
14400 if (align_loops == 0)
14402 if (align_jumps == 0)
14404 if (align_functions == 0)
14405 align_functions = 8;
14408 targetm.min_anchor_offset = -32768;
14409 targetm.max_anchor_offset = 32767;
14411 targetm.const_anchor = 0x8000;
14414 /* (Re)initialize MIPS target internals for new ISA. */
14415 mips_init_relocs ();
14417 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
14418 /* Reinitialize target-dependent state. */
14421 was_mips16_p = mips16_p;
14422 was_mips16_pch_p = mips16_p;
14425 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
14426 function should use the MIPS16 ISA and switch modes accordingly. */
14429 mips_set_current_function (tree fndecl)
14431 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
14434 /* Allocate a chunk of memory for per-function machine-dependent data. */
14436 static struct machine_function *
14437 mips_init_machine_status (void)
14439 return ((struct machine_function *)
14440 ggc_alloc_cleared (sizeof (struct machine_function)));
14443 /* Return the processor associated with the given ISA level, or null
14444 if the ISA isn't valid. */
14446 static const struct mips_cpu_info *
14447 mips_cpu_info_from_isa (int isa)
14451 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
14452 if (mips_cpu_info_table[i].isa == isa)
14453 return mips_cpu_info_table + i;
14458 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14459 with a final "000" replaced by "k". Ignore case.
14461 Note: this function is shared between GCC and GAS. */
14464 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14466 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14467 given++, canonical++;
14469 return ((*given == 0 && *canonical == 0)
14470 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14473 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14474 CPU name. We've traditionally allowed a lot of variation here.
14476 Note: this function is shared between GCC and GAS. */
14479 mips_matching_cpu_name_p (const char *canonical, const char *given)
14481 /* First see if the name matches exactly, or with a final "000"
14482 turned into "k". */
14483 if (mips_strict_matching_cpu_name_p (canonical, given))
14486 /* If not, try comparing based on numerical designation alone.
14487 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14488 if (TOLOWER (*given) == 'r')
14490 if (!ISDIGIT (*given))
14493 /* Skip over some well-known prefixes in the canonical name,
14494 hoping to find a number there too. */
14495 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14497 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14499 else if (TOLOWER (canonical[0]) == 'r')
14502 return mips_strict_matching_cpu_name_p (canonical, given);
14505 /* Return the mips_cpu_info entry for the processor or ISA given
14506 by CPU_STRING. Return null if the string isn't recognized.
14508 A similar function exists in GAS. */
14510 static const struct mips_cpu_info *
14511 mips_parse_cpu (const char *cpu_string)
14516 /* In the past, we allowed upper-case CPU names, but it doesn't
14517 work well with the multilib machinery. */
14518 for (s = cpu_string; *s != 0; s++)
14521 warning (0, "CPU names must be lower case");
14525 /* 'from-abi' selects the most compatible architecture for the given
14526 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14527 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14529 if (strcasecmp (cpu_string, "from-abi") == 0)
14530 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
14531 : ABI_NEEDS_64BIT_REGS ? 3
14532 : (TARGET_64BIT ? 3 : 1));
14534 /* 'default' has traditionally been a no-op. Probably not very useful. */
14535 if (strcasecmp (cpu_string, "default") == 0)
14538 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
14539 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
14540 return mips_cpu_info_table + i;
14545 /* Set up globals to generate code for the ISA or processor
14546 described by INFO. */
14549 mips_set_architecture (const struct mips_cpu_info *info)
14553 mips_arch_info = info;
14554 mips_arch = info->cpu;
14555 mips_isa = info->isa;
14559 /* Likewise for tuning. */
14562 mips_set_tune (const struct mips_cpu_info *info)
14566 mips_tune_info = info;
14567 mips_tune = info->cpu;
14571 /* Implement TARGET_HANDLE_OPTION. */
14574 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
14579 if (strcmp (arg, "32") == 0)
14581 else if (strcmp (arg, "o64") == 0)
14582 mips_abi = ABI_O64;
14583 else if (strcmp (arg, "n32") == 0)
14584 mips_abi = ABI_N32;
14585 else if (strcmp (arg, "64") == 0)
14587 else if (strcmp (arg, "eabi") == 0)
14588 mips_abi = ABI_EABI;
14595 return mips_parse_cpu (arg) != 0;
14598 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
14599 return mips_isa_option_info != 0;
14601 case OPT_mno_flush_func:
14602 mips_cache_flush_func = NULL;
14605 case OPT_mcode_readable_:
14606 if (strcmp (arg, "yes") == 0)
14607 mips_code_readable = CODE_READABLE_YES;
14608 else if (strcmp (arg, "pcrel") == 0)
14609 mips_code_readable = CODE_READABLE_PCREL;
14610 else if (strcmp (arg, "no") == 0)
14611 mips_code_readable = CODE_READABLE_NO;
14616 case OPT_mr10k_cache_barrier_:
14617 if (strcmp (arg, "load-store") == 0)
14618 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
14619 else if (strcmp (arg, "store") == 0)
14620 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
14621 else if (strcmp (arg, "none") == 0)
14622 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
14632 /* Implement OVERRIDE_OPTIONS. */
14635 mips_override_options (void)
14637 int i, start, regno, mode;
14639 /* Process flags as though we were generating non-MIPS16 code. */
14640 mips_base_mips16 = TARGET_MIPS16;
14641 target_flags &= ~MASK_MIPS16;
14643 #ifdef SUBTARGET_OVERRIDE_OPTIONS
14644 SUBTARGET_OVERRIDE_OPTIONS;
14647 /* Set the small data limit. */
14648 mips_small_data_threshold = (g_switch_set
14650 : MIPS_DEFAULT_GVALUE);
14652 /* The following code determines the architecture and register size.
14653 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
14654 The GAS and GCC code should be kept in sync as much as possible. */
14656 if (mips_arch_string != 0)
14657 mips_set_architecture (mips_parse_cpu (mips_arch_string));
14659 if (mips_isa_option_info != 0)
14661 if (mips_arch_info == 0)
14662 mips_set_architecture (mips_isa_option_info);
14663 else if (mips_arch_info->isa != mips_isa_option_info->isa)
14664 error ("%<-%s%> conflicts with the other architecture options, "
14665 "which specify a %s processor",
14666 mips_isa_option_info->name,
14667 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
14670 if (mips_arch_info == 0)
14672 #ifdef MIPS_CPU_STRING_DEFAULT
14673 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
14675 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
14679 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
14680 error ("%<-march=%s%> is not compatible with the selected ABI",
14681 mips_arch_info->name);
14683 /* Optimize for mips_arch, unless -mtune selects a different processor. */
14684 if (mips_tune_string != 0)
14685 mips_set_tune (mips_parse_cpu (mips_tune_string));
14687 if (mips_tune_info == 0)
14688 mips_set_tune (mips_arch_info);
14690 if ((target_flags_explicit & MASK_64BIT) != 0)
14692 /* The user specified the size of the integer registers. Make sure
14693 it agrees with the ABI and ISA. */
14694 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
14695 error ("%<-mgp64%> used with a 32-bit processor");
14696 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
14697 error ("%<-mgp32%> used with a 64-bit ABI");
14698 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
14699 error ("%<-mgp64%> used with a 32-bit ABI");
14703 /* Infer the integer register size from the ABI and processor.
14704 Restrict ourselves to 32-bit registers if that's all the
14705 processor has, or if the ABI cannot handle 64-bit registers. */
14706 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
14707 target_flags &= ~MASK_64BIT;
14709 target_flags |= MASK_64BIT;
14712 if ((target_flags_explicit & MASK_FLOAT64) != 0)
14714 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
14715 error ("unsupported combination: %s", "-mfp64 -msingle-float");
14716 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
14717 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
14718 else if (!TARGET_64BIT && TARGET_FLOAT64)
14720 if (!ISA_HAS_MXHC1)
14721 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
14722 " the target supports the mfhc1 and mthc1 instructions");
14723 else if (mips_abi != ABI_32)
14724 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
14730 /* -msingle-float selects 32-bit float registers. Otherwise the
14731 float registers should be the same size as the integer ones. */
14732 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
14733 target_flags |= MASK_FLOAT64;
14735 target_flags &= ~MASK_FLOAT64;
14738 /* End of code shared with GAS. */
14740 /* If no -mlong* option was given, infer it from the other options. */
14741 if ((target_flags_explicit & MASK_LONG64) == 0)
14743 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
14744 target_flags |= MASK_LONG64;
14746 target_flags &= ~MASK_LONG64;
14749 if (!TARGET_OLDABI)
14750 flag_pcc_struct_return = 0;
14752 /* Decide which rtx_costs structure to use. */
14754 mips_cost = &mips_rtx_cost_optimize_size;
14756 mips_cost = &mips_rtx_cost_data[mips_tune];
14758 /* If the user hasn't specified a branch cost, use the processor's
14760 if (mips_branch_cost == 0)
14761 mips_branch_cost = mips_cost->branch_cost;
14763 /* If neither -mbranch-likely nor -mno-branch-likely was given
14764 on the command line, set MASK_BRANCHLIKELY based on the target
14765 architecture and tuning flags. Annulled delay slots are a
14766 size win, so we only consider the processor-specific tuning
14767 for !optimize_size. */
14768 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
14770 if (ISA_HAS_BRANCHLIKELY
14772 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
14773 target_flags |= MASK_BRANCHLIKELY;
14775 target_flags &= ~MASK_BRANCHLIKELY;
14777 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
14778 warning (0, "the %qs architecture does not support branch-likely"
14779 " instructions", mips_arch_info->name);
14781 /* The effect of -mabicalls isn't defined for the EABI. */
14782 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
14784 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
14785 target_flags &= ~MASK_ABICALLS;
14788 if (TARGET_ABICALLS_PIC2)
14789 /* We need to set flag_pic for executables as well as DSOs
14790 because we may reference symbols that are not defined in
14791 the final executable. (MIPS does not use things like
14792 copy relocs, for example.)
14794 There is a body of code that uses __PIC__ to distinguish
14795 between -mabicalls and -mno-abicalls code. The non-__PIC__
14796 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
14797 long as any indirect jumps use $25. */
14800 /* -mvr4130-align is a "speed over size" optimization: it usually produces
14801 faster code, but at the expense of more nops. Enable it at -O3 and
14803 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
14804 target_flags |= MASK_VR4130_ALIGN;
14806 /* Prefer a call to memcpy over inline code when optimizing for size,
14807 though see MOVE_RATIO in mips.h. */
14808 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
14809 target_flags |= MASK_MEMCPY;
14811 /* If we have a nonzero small-data limit, check that the -mgpopt
14812 setting is consistent with the other target flags. */
14813 if (mips_small_data_threshold > 0)
14817 if (!TARGET_EXPLICIT_RELOCS)
14818 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
14820 TARGET_LOCAL_SDATA = false;
14821 TARGET_EXTERN_SDATA = false;
14825 if (TARGET_VXWORKS_RTP)
14826 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
14828 if (TARGET_ABICALLS)
14829 warning (0, "cannot use small-data accesses for %qs",
14834 #ifdef MIPS_TFMODE_FORMAT
14835 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
14838 /* Make sure that the user didn't turn off paired single support when
14839 MIPS-3D support is requested. */
14841 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
14842 && !TARGET_PAIRED_SINGLE_FLOAT)
14843 error ("%<-mips3d%> requires %<-mpaired-single%>");
14845 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
14847 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
14849 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
14850 and TARGET_HARD_FLOAT_ABI are both true. */
14851 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
14852 error ("%qs must be used with %qs",
14853 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
14854 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
14856 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
14858 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
14859 warning (0, "the %qs architecture does not support paired-single"
14860 " instructions", mips_arch_info->name);
14862 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14863 && !TARGET_CACHE_BUILTIN)
14865 error ("%qs requires a target that provides the %qs instruction",
14866 "-mr10k-cache-barrier", "cache");
14867 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
14870 /* If TARGET_DSPR2, enable MASK_DSP. */
14872 target_flags |= MASK_DSP;
14874 /* .eh_frame addresses should be the same width as a C pointer.
14875 Most MIPS ABIs support only one pointer size, so the assembler
14876 will usually know exactly how big an .eh_frame address is.
14878 Unfortunately, this is not true of the 64-bit EABI. The ABI was
14879 originally defined to use 64-bit pointers (i.e. it is LP64), and
14880 this is still the default mode. However, we also support an n32-like
14881 ILP32 mode, which is selected by -mlong32. The problem is that the
14882 assembler has traditionally not had an -mlong option, so it has
14883 traditionally not known whether we're using the ILP32 or LP64 form.
14885 As it happens, gas versions up to and including 2.19 use _32-bit_
14886 addresses for EABI64 .cfi_* directives. This is wrong for the
14887 default LP64 mode, so we can't use the directives by default.
14888 Moreover, since gas's current behavior is at odds with gcc's
14889 default behavior, it seems unwise to rely on future versions
14890 of gas behaving the same way. We therefore avoid using .cfi
14891 directives for -mlong32 as well. */
14892 if (mips_abi == ABI_EABI && TARGET_64BIT)
14893 flag_dwarf2_cfi_asm = 0;
14895 mips_init_print_operand_punct ();
14897 /* Set up array to map GCC register number to debug register number.
14898 Ignore the special purpose register numbers. */
14900 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14902 mips_dbx_regno[i] = INVALID_REGNUM;
14903 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
14904 mips_dwarf_regno[i] = i;
14906 mips_dwarf_regno[i] = INVALID_REGNUM;
14909 start = GP_DBX_FIRST - GP_REG_FIRST;
14910 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
14911 mips_dbx_regno[i] = i + start;
14913 start = FP_DBX_FIRST - FP_REG_FIRST;
14914 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
14915 mips_dbx_regno[i] = i + start;
14917 /* Accumulator debug registers use big-endian ordering. */
14918 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
14919 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
14920 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
14921 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
14922 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
14924 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
14925 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
14928 /* Set up mips_hard_regno_mode_ok. */
14929 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
14930 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
14931 mips_hard_regno_mode_ok[mode][regno]
14932 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
14934 /* Function to allocate machine-dependent function status. */
14935 init_machine_status = &mips_init_machine_status;
14937 /* Default to working around R4000 errata only if the processor
14938 was selected explicitly. */
14939 if ((target_flags_explicit & MASK_FIX_R4000) == 0
14940 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
14941 target_flags |= MASK_FIX_R4000;
14943 /* Default to working around R4400 errata only if the processor
14944 was selected explicitly. */
14945 if ((target_flags_explicit & MASK_FIX_R4400) == 0
14946 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
14947 target_flags |= MASK_FIX_R4400;
14949 /* Default to working around R10000 errata only if the processor
14950 was selected explicitly. */
14951 if ((target_flags_explicit & MASK_FIX_R10000) == 0
14952 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
14953 target_flags |= MASK_FIX_R10000;
14955 /* Make sure that branch-likely instructions available when using
14956 -mfix-r10000. The instructions are not available if either:
14958 1. -mno-branch-likely was passed.
14959 2. The selected ISA does not support branch-likely and
14960 the command line does not include -mbranch-likely. */
14961 if (TARGET_FIX_R10000
14962 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
14963 ? !ISA_HAS_BRANCHLIKELY
14964 : !TARGET_BRANCHLIKELY))
14965 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
14967 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
14969 warning (0, "the %qs architecture does not support the synci "
14970 "instruction", mips_arch_info->name);
14971 target_flags &= ~MASK_SYNCI;
14974 /* Save base state of options. */
14975 mips_base_target_flags = target_flags;
14976 mips_base_schedule_insns = flag_schedule_insns;
14977 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
14978 mips_base_move_loop_invariants = flag_move_loop_invariants;
14979 mips_base_align_loops = align_loops;
14980 mips_base_align_jumps = align_jumps;
14981 mips_base_align_functions = align_functions;
14983 /* Now select the ISA mode.
14985 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
14986 MIPS16 mode afterwards if need be. */
14987 mips_set_mips16_mode (false);
14990 /* Swap the register information for registers I and I + 1, which
14991 currently have the wrong endianness. Note that the registers'
14992 fixedness and call-clobberedness might have been set on the
14996 mips_swap_registers (unsigned int i)
15001 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15002 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15004 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15005 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15006 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15007 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15013 /* Implement CONDITIONAL_REGISTER_USAGE. */
15016 mips_conditional_register_usage (void)
15021 /* These DSP control register fields are global. */
15022 global_regs[CCDSP_PO_REGNUM] = 1;
15023 global_regs[CCDSP_SC_REGNUM] = 1;
15029 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15030 fixed_regs[regno] = call_used_regs[regno] = 1;
15032 if (!TARGET_HARD_FLOAT)
15036 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15037 fixed_regs[regno] = call_used_regs[regno] = 1;
15038 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15039 fixed_regs[regno] = call_used_regs[regno] = 1;
15041 else if (! ISA_HAS_8CC)
15045 /* We only have a single condition-code register. We implement
15046 this by fixing all the condition-code registers and generating
15047 RTL that refers directly to ST_REG_FIRST. */
15048 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15049 fixed_regs[regno] = call_used_regs[regno] = 1;
15051 /* In MIPS16 mode, we permit the $t temporary registers to be used
15052 for reload. We prohibit the unused $s registers, since they
15053 are call-saved, and saving them via a MIPS16 register would
15054 probably waste more time than just reloading the value. */
15057 fixed_regs[18] = call_used_regs[18] = 1;
15058 fixed_regs[19] = call_used_regs[19] = 1;
15059 fixed_regs[20] = call_used_regs[20] = 1;
15060 fixed_regs[21] = call_used_regs[21] = 1;
15061 fixed_regs[22] = call_used_regs[22] = 1;
15062 fixed_regs[23] = call_used_regs[23] = 1;
15063 fixed_regs[26] = call_used_regs[26] = 1;
15064 fixed_regs[27] = call_used_regs[27] = 1;
15065 fixed_regs[30] = call_used_regs[30] = 1;
15067 /* $f20-$f23 are call-clobbered for n64. */
15068 if (mips_abi == ABI_64)
15071 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15072 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15074 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15076 if (mips_abi == ABI_N32)
15079 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15080 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15082 /* Make sure that double-register accumulator values are correctly
15083 ordered for the current endianness. */
15084 if (TARGET_LITTLE_ENDIAN)
15086 unsigned int regno;
15088 mips_swap_registers (MD_REG_FIRST);
15089 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15090 mips_swap_registers (regno);
15094 /* Initialize vector TARGET to VALS. */
15097 mips_expand_vector_init (rtx target, rtx vals)
15099 enum machine_mode mode;
15100 enum machine_mode inner;
15101 unsigned int i, n_elts;
15104 mode = GET_MODE (target);
15105 inner = GET_MODE_INNER (mode);
15106 n_elts = GET_MODE_NUNITS (mode);
15108 gcc_assert (VECTOR_MODE_P (mode));
15110 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15111 for (i = 0; i < n_elts; i++)
15112 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15113 XVECEXP (vals, 0, i));
15115 emit_move_insn (target, mem);
15118 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15119 other registers for instructions for which it is possible. This
15120 encourages the compiler to use CMP in cases where an XOR would
15121 require some register shuffling. */
15124 mips_order_regs_for_local_alloc (void)
15128 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15129 reg_alloc_order[i] = i;
15133 /* It really doesn't matter where we put register 0, since it is
15134 a fixed register anyhow. */
15135 reg_alloc_order[0] = 24;
15136 reg_alloc_order[24] = 0;
15140 /* Implement EPILOGUE_USES. */
15143 mips_epilogue_uses (unsigned int regno)
15145 /* Say that the epilogue uses the return address register. Note that
15146 in the case of sibcalls, the values "used by the epilogue" are
15147 considered live at the start of the called function. */
15151 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15152 See the comment above load_call<mode> for details. */
15153 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
15156 /* An interrupt handler must preserve some registers that are
15157 ordinarily call-clobbered. */
15158 if (cfun->machine->interrupt_handler_p
15159 && mips_interrupt_extra_call_saved_reg_p (regno))
15165 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15168 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
15170 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
15173 /* Return true if INSN needs to be wrapped in ".set noat".
15174 INSN has NOPERANDS operands, stored in OPVEC. */
15177 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
15181 if (recog_memoized (insn) >= 0)
15182 for (i = 0; i < noperands; i++)
15183 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
15188 /* Implement FINAL_PRESCAN_INSN. */
15191 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
15193 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15194 mips_push_asm_switch (&mips_noat);
15197 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
15200 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
15201 rtx *opvec, int noperands)
15203 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15204 mips_pop_asm_switch (&mips_noat);
15207 /* Initialize the GCC target structure. */
15208 #undef TARGET_ASM_ALIGNED_HI_OP
15209 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
15210 #undef TARGET_ASM_ALIGNED_SI_OP
15211 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
15212 #undef TARGET_ASM_ALIGNED_DI_OP
15213 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
15215 #undef TARGET_LEGITIMIZE_ADDRESS
15216 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
15218 #undef TARGET_ASM_FUNCTION_PROLOGUE
15219 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
15220 #undef TARGET_ASM_FUNCTION_EPILOGUE
15221 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
15222 #undef TARGET_ASM_SELECT_RTX_SECTION
15223 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
15224 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
15225 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
15227 #undef TARGET_SCHED_INIT
15228 #define TARGET_SCHED_INIT mips_sched_init
15229 #undef TARGET_SCHED_REORDER
15230 #define TARGET_SCHED_REORDER mips_sched_reorder
15231 #undef TARGET_SCHED_REORDER2
15232 #define TARGET_SCHED_REORDER2 mips_sched_reorder
15233 #undef TARGET_SCHED_VARIABLE_ISSUE
15234 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
15235 #undef TARGET_SCHED_ADJUST_COST
15236 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
15237 #undef TARGET_SCHED_ISSUE_RATE
15238 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
15239 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
15240 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
15241 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
15242 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
15243 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15244 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15245 mips_multipass_dfa_lookahead
15247 #undef TARGET_DEFAULT_TARGET_FLAGS
15248 #define TARGET_DEFAULT_TARGET_FLAGS \
15250 | TARGET_CPU_DEFAULT \
15251 | TARGET_ENDIAN_DEFAULT \
15252 | TARGET_FP_EXCEPTIONS_DEFAULT \
15253 | MASK_CHECK_ZERO_DIV \
15255 #undef TARGET_HANDLE_OPTION
15256 #define TARGET_HANDLE_OPTION mips_handle_option
15258 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
15259 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
15261 #undef TARGET_INSERT_ATTRIBUTES
15262 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
15263 #undef TARGET_MERGE_DECL_ATTRIBUTES
15264 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
15265 #undef TARGET_SET_CURRENT_FUNCTION
15266 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
15268 #undef TARGET_VALID_POINTER_MODE
15269 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
15270 #undef TARGET_RTX_COSTS
15271 #define TARGET_RTX_COSTS mips_rtx_costs
15272 #undef TARGET_ADDRESS_COST
15273 #define TARGET_ADDRESS_COST mips_address_cost
15275 #undef TARGET_IN_SMALL_DATA_P
15276 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
15278 #undef TARGET_MACHINE_DEPENDENT_REORG
15279 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
15281 #undef TARGET_ASM_FILE_START
15282 #define TARGET_ASM_FILE_START mips_file_start
15283 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
15284 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
15286 #undef TARGET_INIT_LIBFUNCS
15287 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
15289 #undef TARGET_BUILD_BUILTIN_VA_LIST
15290 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
15291 #undef TARGET_EXPAND_BUILTIN_VA_START
15292 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
15293 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
15294 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
15296 #undef TARGET_PROMOTE_FUNCTION_MODE
15297 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
15298 #undef TARGET_PROMOTE_PROTOTYPES
15299 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
15301 #undef TARGET_RETURN_IN_MEMORY
15302 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
15303 #undef TARGET_RETURN_IN_MSB
15304 #define TARGET_RETURN_IN_MSB mips_return_in_msb
15306 #undef TARGET_ASM_OUTPUT_MI_THUNK
15307 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
15308 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
15309 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
15311 #undef TARGET_SETUP_INCOMING_VARARGS
15312 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
15313 #undef TARGET_STRICT_ARGUMENT_NAMING
15314 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
15315 #undef TARGET_MUST_PASS_IN_STACK
15316 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
15317 #undef TARGET_PASS_BY_REFERENCE
15318 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
15319 #undef TARGET_CALLEE_COPIES
15320 #define TARGET_CALLEE_COPIES mips_callee_copies
15321 #undef TARGET_ARG_PARTIAL_BYTES
15322 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
15324 #undef TARGET_MODE_REP_EXTENDED
15325 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
15327 #undef TARGET_VECTOR_MODE_SUPPORTED_P
15328 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
15330 #undef TARGET_SCALAR_MODE_SUPPORTED_P
15331 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
15333 #undef TARGET_INIT_BUILTINS
15334 #define TARGET_INIT_BUILTINS mips_init_builtins
15335 #undef TARGET_EXPAND_BUILTIN
15336 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
15338 #undef TARGET_HAVE_TLS
15339 #define TARGET_HAVE_TLS HAVE_AS_TLS
15341 #undef TARGET_CANNOT_FORCE_CONST_MEM
15342 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
15344 #undef TARGET_ENCODE_SECTION_INFO
15345 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
15347 #undef TARGET_ATTRIBUTE_TABLE
15348 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
15349 /* All our function attributes are related to how out-of-line copies should
15350 be compiled or called. They don't in themselves prevent inlining. */
15351 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
15352 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
15354 #undef TARGET_EXTRA_LIVE_ON_ENTRY
15355 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
15357 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
15358 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
15359 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
15360 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
15362 #undef TARGET_COMP_TYPE_ATTRIBUTES
15363 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
15365 #ifdef HAVE_AS_DTPRELWORD
15366 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
15367 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
15369 #undef TARGET_DWARF_REGISTER_SPAN
15370 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
15372 #undef TARGET_IRA_COVER_CLASSES
15373 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
15375 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
15376 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
15378 #undef TARGET_LEGITIMATE_ADDRESS_P
15379 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
15381 #undef TARGET_FRAME_POINTER_REQUIRED
15382 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
15384 #undef TARGET_CAN_ELIMINATE
15385 #define TARGET_CAN_ELIMINATE mips_can_eliminate
15387 struct gcc_target targetm = TARGET_INITIALIZER;
15389 #include "gt-mips.h"