1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save & restore registers.
77 Use a maximum gap of 0x100 in the mips16 case. We can then use
78 unextended instructions to save and restore registers, and to
79 allocate and deallocate the top part of the frame.
81 The value in the !mips16 case must be a SMALL_OPERAND and must
82 preserve the maximum stack alignment. */
83 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
85 /* True if INSN is a mips.md pattern or asm statement. */
86 #define USEFUL_INSN_P(INSN) \
88 && GET_CODE (PATTERN (INSN)) != USE \
89 && GET_CODE (PATTERN (INSN)) != CLOBBER \
90 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
91 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
93 /* If INSN is a delayed branch sequence, return the first instruction
94 in the sequence, otherwise return INSN itself. */
95 #define SEQ_BEGIN(INSN) \
96 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
97 ? XVECEXP (PATTERN (INSN), 0, 0) \
100 /* Likewise for the last instruction in a delayed branch sequence. */
101 #define SEQ_END(INSN) \
102 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
103 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
106 /* Execute the following loop body with SUBINSN set to each instruction
107 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
108 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
109 for ((SUBINSN) = SEQ_BEGIN (INSN); \
110 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
111 (SUBINSN) = NEXT_INSN (SUBINSN))
113 /* Classifies an address.
116 A natural register + offset address. The register satisfies
117 mips_valid_base_register_p and the offset is a const_arith_operand.
120 A LO_SUM rtx. The first operand is a valid base register and
121 the second operand is a symbolic address.
124 A signed 16-bit constant address.
127 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
128 enum mips_address_type {
135 /* Classifies the prototype of a builtin function. */
136 enum mips_function_type
138 MIPS_V2SF_FTYPE_V2SF,
139 MIPS_V2SF_FTYPE_V2SF_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
142 MIPS_V2SF_FTYPE_SF_SF,
143 MIPS_INT_FTYPE_V2SF_V2SF,
144 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
145 MIPS_INT_FTYPE_SF_SF,
146 MIPS_INT_FTYPE_DF_DF,
157 /* Specifies how a builtin function should be converted into rtl. */
158 enum mips_builtin_type
160 /* The builtin corresponds directly to an .md pattern. The return
161 value is mapped to operand 0 and the arguments are mapped to
162 operands 1 and above. */
165 /* The builtin corresponds to a comparison instruction followed by
166 a mips_cond_move_tf_ps pattern. The first two arguments are the
167 values to compare and the second two arguments are the vector
168 operands for the movt.ps or movf.ps instruction (in assembly order). */
172 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
173 of this instruction is the result of the comparison, which has mode
174 CCV2 or CCV4. The function arguments are mapped to operands 1 and
175 above. The function's return value is an SImode boolean that is
176 true under the following conditions:
178 MIPS_BUILTIN_CMP_ANY: one of the registers is true
179 MIPS_BUILTIN_CMP_ALL: all of the registers are true
180 MIPS_BUILTIN_CMP_LOWER: the first register is true
181 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
182 MIPS_BUILTIN_CMP_ANY,
183 MIPS_BUILTIN_CMP_ALL,
184 MIPS_BUILTIN_CMP_UPPER,
185 MIPS_BUILTIN_CMP_LOWER,
187 /* As above, but the instruction only sets a single $fcc register. */
188 MIPS_BUILTIN_CMP_SINGLE
191 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
192 #define MIPS_FP_CONDITIONS(MACRO) \
210 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
211 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
212 enum mips_fp_condition {
213 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
216 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
217 #define STRINGIFY(X) #X
218 static const char *const mips_fp_conditions[] = {
219 MIPS_FP_CONDITIONS (STRINGIFY)
222 /* A function to save or store a register. The first argument is the
223 register and the second is the stack slot. */
224 typedef void (*mips_save_restore_fn) (rtx, rtx);
226 struct mips16_constant;
227 struct mips_arg_info;
228 struct mips_address_info;
229 struct mips_integer_op;
232 static enum mips_symbol_type mips_classify_symbol (rtx);
233 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
234 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
235 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
236 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
237 static bool mips_classify_address (struct mips_address_info *, rtx,
238 enum machine_mode, int);
239 static bool mips_cannot_force_const_mem (rtx);
240 static int mips_symbol_insns (enum mips_symbol_type);
241 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
242 static rtx mips_force_temporary (rtx, rtx);
243 static rtx mips_split_symbol (rtx, rtx);
244 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
245 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
246 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
247 static unsigned int mips_build_lower (struct mips_integer_op *,
248 unsigned HOST_WIDE_INT);
249 static unsigned int mips_build_integer (struct mips_integer_op *,
250 unsigned HOST_WIDE_INT);
251 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
252 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
253 static int m16_check_op (rtx, int, int, int);
254 static bool mips_rtx_costs (rtx, int, int, int *);
255 static int mips_address_cost (rtx);
256 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
257 static void mips_load_call_address (rtx, rtx, int);
258 static bool mips_function_ok_for_sibcall (tree, tree);
259 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
260 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
261 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
262 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
263 tree, int, struct mips_arg_info *);
264 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
265 static void mips_set_architecture (const struct mips_cpu_info *);
266 static void mips_set_tune (const struct mips_cpu_info *);
267 static bool mips_handle_option (size_t, const char *, int);
268 static struct machine_function *mips_init_machine_status (void);
269 static void print_operand_reloc (FILE *, rtx, const char **);
271 static void irix_output_external_libcall (rtx);
273 static void mips_file_start (void);
274 static void mips_file_end (void);
275 static bool mips_rewrite_small_data_p (rtx);
276 static int mips_small_data_pattern_1 (rtx *, void *);
277 static int mips_rewrite_small_data_1 (rtx *, void *);
278 static bool mips_function_has_gp_insn (void);
279 static unsigned int mips_global_pointer (void);
280 static bool mips_save_reg_p (unsigned int);
281 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
282 mips_save_restore_fn);
283 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
284 static void mips_output_cplocal (void);
285 static void mips_emit_loadgp (void);
286 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
287 static void mips_set_frame_expr (rtx);
288 static rtx mips_frame_set (rtx, rtx);
289 static void mips_save_reg (rtx, rtx);
290 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
291 static void mips_restore_reg (rtx, rtx);
292 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
293 HOST_WIDE_INT, tree);
294 static int symbolic_expression_p (rtx);
295 static void mips_select_rtx_section (enum machine_mode, rtx,
296 unsigned HOST_WIDE_INT);
297 static void mips_function_rodata_section (tree);
298 static bool mips_in_small_data_p (tree);
299 static int mips_fpr_return_fields (tree, tree *);
300 static bool mips_return_in_msb (tree);
301 static rtx mips_return_fpr_pair (enum machine_mode mode,
302 enum machine_mode mode1, HOST_WIDE_INT,
303 enum machine_mode mode2, HOST_WIDE_INT);
304 static rtx mips16_gp_pseudo_reg (void);
305 static void mips16_fp_args (FILE *, int, int);
306 static void build_mips16_function_stub (FILE *);
307 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
308 static void dump_constants (struct mips16_constant *, rtx);
309 static int mips16_insn_length (rtx);
310 static int mips16_rewrite_pool_refs (rtx *, void *);
311 static void mips16_lay_out_constants (void);
312 static void mips_sim_reset (struct mips_sim *);
313 static void mips_sim_init (struct mips_sim *, state_t);
314 static void mips_sim_next_cycle (struct mips_sim *);
315 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
316 static int mips_sim_wait_regs_2 (rtx *, void *);
317 static void mips_sim_wait_regs_1 (rtx *, void *);
318 static void mips_sim_wait_regs (struct mips_sim *, rtx);
319 static void mips_sim_wait_units (struct mips_sim *, rtx);
320 static void mips_sim_wait_insn (struct mips_sim *, rtx);
321 static void mips_sim_record_set (rtx, rtx, void *);
322 static void mips_sim_issue_insn (struct mips_sim *, rtx);
323 static void mips_sim_issue_nop (struct mips_sim *);
324 static void mips_sim_finish_insn (struct mips_sim *, rtx);
325 static void vr4130_avoid_branch_rt_conflict (rtx);
326 static void vr4130_align_insns (void);
327 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
328 static void mips_avoid_hazards (void);
329 static void mips_reorg (void);
330 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
331 static bool mips_matching_cpu_name_p (const char *, const char *);
332 static const struct mips_cpu_info *mips_parse_cpu (const char *);
333 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
334 static bool mips_return_in_memory (tree, tree);
335 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
336 static void mips_macc_chains_record (rtx);
337 static void mips_macc_chains_reorder (rtx *, int);
338 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
339 static bool vr4130_true_reg_dependence_p (rtx);
340 static bool vr4130_swap_insns_p (rtx, rtx);
341 static void vr4130_reorder (rtx *, int);
342 static void mips_promote_ready (rtx *, int, int);
343 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
344 static int mips_variable_issue (FILE *, int, rtx, int);
345 static int mips_adjust_cost (rtx, rtx, rtx, int);
346 static int mips_issue_rate (void);
347 static int mips_multipass_dfa_lookahead (void);
348 static void mips_init_libfuncs (void);
349 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
351 static tree mips_build_builtin_va_list (void);
352 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
353 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
355 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
357 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
359 static bool mips_valid_pointer_mode (enum machine_mode);
360 static bool mips_vector_mode_supported_p (enum machine_mode);
361 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
362 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
363 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
364 static void mips_init_builtins (void);
365 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree);
366 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
367 enum insn_code, enum mips_fp_condition,
369 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
370 enum insn_code, enum mips_fp_condition,
373 /* Structure to be filled in by compute_frame_size with register
374 save masks, and offsets for the current function. */
376 struct mips_frame_info GTY(())
378 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
379 HOST_WIDE_INT var_size; /* # bytes that variables take up */
380 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
381 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
382 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
383 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
384 unsigned int mask; /* mask of saved gp registers */
385 unsigned int fmask; /* mask of saved fp registers */
386 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
387 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
388 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
389 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
390 bool initialized; /* true if frame size already calculated */
391 int num_gp; /* number of gp registers saved */
392 int num_fp; /* number of fp registers saved */
395 struct machine_function GTY(()) {
396 /* Pseudo-reg holding the value of $28 in a mips16 function which
397 refers to GP relative global variables. */
398 rtx mips16_gp_pseudo_rtx;
400 /* Current frame information, calculated by compute_frame_size. */
401 struct mips_frame_info frame;
403 /* The register to use as the global pointer within this function. */
404 unsigned int global_pointer;
406 /* True if mips_adjust_insn_length should ignore an instruction's
408 bool ignore_hazard_length_p;
410 /* True if the whole function is suitable for .set noreorder and
412 bool all_noreorder_p;
414 /* True if the function is known to have an instruction that needs $gp. */
418 /* Information about a single argument. */
421 /* True if the argument is passed in a floating-point register, or
422 would have been if we hadn't run out of registers. */
425 /* The number of words passed in registers, rounded up. */
426 unsigned int reg_words;
428 /* For EABI, the offset of the first register from GP_ARG_FIRST or
429 FP_ARG_FIRST. For other ABIs, the offset of the first register from
430 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
431 comment for details).
433 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
435 unsigned int reg_offset;
437 /* The number of words that must be passed on the stack, rounded up. */
438 unsigned int stack_words;
440 /* The offset from the start of the stack overflow area of the argument's
441 first stack word. Only meaningful when STACK_WORDS is nonzero. */
442 unsigned int stack_offset;
446 /* Information about an address described by mips_address_type.
452 REG is the base register and OFFSET is the constant offset.
455 REG is the register that contains the high part of the address,
456 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
457 is the type of OFFSET's symbol.
460 SYMBOL_TYPE is the type of symbol being referenced. */
462 struct mips_address_info
464 enum mips_address_type type;
467 enum mips_symbol_type symbol_type;
471 /* One stage in a constant building sequence. These sequences have
475 A = A CODE[1] VALUE[1]
476 A = A CODE[2] VALUE[2]
479 where A is an accumulator, each CODE[i] is a binary rtl operation
480 and each VALUE[i] is a constant integer. */
481 struct mips_integer_op {
483 unsigned HOST_WIDE_INT value;
487 /* The largest number of operations needed to load an integer constant.
488 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
489 When the lowest bit is clear, we can try, but reject a sequence with
490 an extra SLL at the end. */
491 #define MIPS_MAX_INTEGER_OPS 7
494 /* Global variables for machine-dependent things. */
496 /* Threshold for data being put into the small data/bss area, instead
497 of the normal data area. */
498 int mips_section_threshold = -1;
500 /* Count the number of .file directives, so that .loc is up to date. */
501 int num_source_filenames = 0;
503 /* Count the number of sdb related labels are generated (to find block
504 start and end boundaries). */
505 int sdb_label_count = 0;
507 /* Next label # for each statement for Silicon Graphics IRIS systems. */
510 /* Linked list of all externals that are to be emitted when optimizing
511 for the global pointer if they haven't been declared by the end of
512 the program with an appropriate .comm or initialization. */
514 struct extern_list GTY (())
516 struct extern_list *next; /* next external */
517 const char *name; /* name of the external */
518 int size; /* size in bytes */
521 static GTY (()) struct extern_list *extern_head = 0;
523 /* Name of the file containing the current function. */
524 const char *current_function_file = "";
526 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
532 /* The next branch instruction is a branch likely, not branch normal. */
533 int mips_branch_likely;
535 /* The operands passed to the last cmpMM expander. */
538 /* The target cpu for code generation. */
539 enum processor_type mips_arch;
540 const struct mips_cpu_info *mips_arch_info;
542 /* The target cpu for optimization and scheduling. */
543 enum processor_type mips_tune;
544 const struct mips_cpu_info *mips_tune_info;
546 /* Which instruction set architecture to use. */
549 /* Which ABI to use. */
550 int mips_abi = MIPS_ABI_DEFAULT;
552 /* Whether we are generating mips16 hard float code. In mips16 mode
553 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
554 -msoft-float was not specified by the user, which means that we
555 should arrange to call mips32 hard floating point code. */
556 int mips16_hard_float;
558 /* The arguments passed to -march and -mtune. */
559 static const char *mips_arch_string;
560 static const char *mips_tune_string;
562 /* The architecture selected by -mipsN. */
563 static const struct mips_cpu_info *mips_isa_info;
565 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
567 /* If TRUE, we split addresses into their high and low parts in the RTL. */
568 int mips_split_addresses;
570 /* Mode used for saving/restoring general purpose registers. */
571 static enum machine_mode gpr_mode;
573 /* Array giving truth value on whether or not a given hard register
574 can support a given mode. */
575 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
577 /* List of all MIPS punctuation characters used by print_operand. */
578 char mips_print_operand_punct[256];
580 /* Map GCC register number to debugger register number. */
581 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
583 /* A copy of the original flag_delayed_branch: see override_options. */
584 static int mips_flag_delayed_branch;
586 static GTY (()) int mips_output_filename_first_time = 1;
588 /* mips_split_p[X] is true if symbols of type X can be split by
589 mips_split_symbol(). */
590 static bool mips_split_p[NUM_SYMBOL_TYPES];
592 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
593 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
594 if they are matched by a special .md file pattern. */
595 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
597 /* Likewise for HIGHs. */
598 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
600 /* Map hard register number to register class */
601 const enum reg_class mips_regno_to_class[] =
603 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
604 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
605 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
606 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
607 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
608 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
609 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
610 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
611 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
612 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
613 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
614 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
615 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
616 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
617 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
618 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
619 HI_REG, LO_REG, NO_REGS, ST_REGS,
620 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
621 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
622 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
623 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
624 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
625 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
626 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
627 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
628 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
629 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
630 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
631 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
632 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
633 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
634 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
635 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
636 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
637 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
638 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
639 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
640 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
641 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
642 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
643 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
644 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
645 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
646 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
649 /* Map register constraint character to register class. */
650 enum reg_class mips_char_to_class[256];
652 /* A table describing all the processors gcc knows about. Names are
653 matched in the order listed. The first mention of an ISA level is
654 taken as the canonical name for that ISA.
656 To ease comparison, please keep this table in the same order as
657 gas's mips_cpu_info_table[]. */
658 const struct mips_cpu_info mips_cpu_info_table[] = {
659 /* Entries for generic ISAs */
660 { "mips1", PROCESSOR_R3000, 1 },
661 { "mips2", PROCESSOR_R6000, 2 },
662 { "mips3", PROCESSOR_R4000, 3 },
663 { "mips4", PROCESSOR_R8000, 4 },
664 { "mips32", PROCESSOR_4KC, 32 },
665 { "mips32r2", PROCESSOR_M4K, 33 },
666 { "mips64", PROCESSOR_5KC, 64 },
669 { "r3000", PROCESSOR_R3000, 1 },
670 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
671 { "r3900", PROCESSOR_R3900, 1 },
674 { "r6000", PROCESSOR_R6000, 2 },
677 { "r4000", PROCESSOR_R4000, 3 },
678 { "vr4100", PROCESSOR_R4100, 3 },
679 { "vr4111", PROCESSOR_R4111, 3 },
680 { "vr4120", PROCESSOR_R4120, 3 },
681 { "vr4130", PROCESSOR_R4130, 3 },
682 { "vr4300", PROCESSOR_R4300, 3 },
683 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
684 { "r4600", PROCESSOR_R4600, 3 },
685 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
686 { "r4650", PROCESSOR_R4650, 3 },
689 { "r8000", PROCESSOR_R8000, 4 },
690 { "vr5000", PROCESSOR_R5000, 4 },
691 { "vr5400", PROCESSOR_R5400, 4 },
692 { "vr5500", PROCESSOR_R5500, 4 },
693 { "rm7000", PROCESSOR_R7000, 4 },
694 { "rm9000", PROCESSOR_R9000, 4 },
697 { "4kc", PROCESSOR_4KC, 32 },
698 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
700 /* MIPS32 Release 2 */
701 { "m4k", PROCESSOR_M4K, 33 },
704 { "5kc", PROCESSOR_5KC, 64 },
705 { "20kc", PROCESSOR_20KC, 64 },
706 { "sb1", PROCESSOR_SB1, 64 },
707 { "sr71000", PROCESSOR_SR71000, 64 },
713 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
714 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
715 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
718 /* Initialize the GCC target structure. */
719 #undef TARGET_ASM_ALIGNED_HI_OP
720 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
721 #undef TARGET_ASM_ALIGNED_SI_OP
722 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
723 #undef TARGET_ASM_ALIGNED_DI_OP
724 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
726 #undef TARGET_ASM_FUNCTION_PROLOGUE
727 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
728 #undef TARGET_ASM_FUNCTION_EPILOGUE
729 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
730 #undef TARGET_ASM_SELECT_RTX_SECTION
731 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
732 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
733 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
735 #undef TARGET_SCHED_REORDER
736 #define TARGET_SCHED_REORDER mips_sched_reorder
737 #undef TARGET_SCHED_VARIABLE_ISSUE
738 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
739 #undef TARGET_SCHED_ADJUST_COST
740 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
741 #undef TARGET_SCHED_ISSUE_RATE
742 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
743 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
744 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
745 mips_multipass_dfa_lookahead
747 #undef TARGET_DEFAULT_TARGET_FLAGS
748 #define TARGET_DEFAULT_TARGET_FLAGS \
750 | TARGET_CPU_DEFAULT \
751 | TARGET_ENDIAN_DEFAULT \
752 | TARGET_FP_EXCEPTIONS_DEFAULT \
753 | MASK_CHECK_ZERO_DIV \
755 #undef TARGET_HANDLE_OPTION
756 #define TARGET_HANDLE_OPTION mips_handle_option
758 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
759 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
761 #undef TARGET_VALID_POINTER_MODE
762 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
763 #undef TARGET_RTX_COSTS
764 #define TARGET_RTX_COSTS mips_rtx_costs
765 #undef TARGET_ADDRESS_COST
766 #define TARGET_ADDRESS_COST mips_address_cost
768 #undef TARGET_IN_SMALL_DATA_P
769 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
771 #undef TARGET_MACHINE_DEPENDENT_REORG
772 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
774 #undef TARGET_ASM_FILE_START
775 #undef TARGET_ASM_FILE_END
776 #define TARGET_ASM_FILE_START mips_file_start
777 #define TARGET_ASM_FILE_END mips_file_end
778 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
779 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
781 #undef TARGET_INIT_LIBFUNCS
782 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
784 #undef TARGET_BUILD_BUILTIN_VA_LIST
785 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
786 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
787 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
789 #undef TARGET_PROMOTE_FUNCTION_ARGS
790 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
791 #undef TARGET_PROMOTE_FUNCTION_RETURN
792 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
793 #undef TARGET_PROMOTE_PROTOTYPES
794 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
796 #undef TARGET_RETURN_IN_MEMORY
797 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
798 #undef TARGET_RETURN_IN_MSB
799 #define TARGET_RETURN_IN_MSB mips_return_in_msb
801 #undef TARGET_ASM_OUTPUT_MI_THUNK
802 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
803 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
804 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
806 #undef TARGET_SETUP_INCOMING_VARARGS
807 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
808 #undef TARGET_STRICT_ARGUMENT_NAMING
809 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
810 #undef TARGET_MUST_PASS_IN_STACK
811 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
812 #undef TARGET_PASS_BY_REFERENCE
813 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
814 #undef TARGET_CALLEE_COPIES
815 #define TARGET_CALLEE_COPIES mips_callee_copies
816 #undef TARGET_ARG_PARTIAL_BYTES
817 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
819 #undef TARGET_VECTOR_MODE_SUPPORTED_P
820 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
822 #undef TARGET_INIT_BUILTINS
823 #define TARGET_INIT_BUILTINS mips_init_builtins
824 #undef TARGET_EXPAND_BUILTIN
825 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
827 #undef TARGET_HAVE_TLS
828 #define TARGET_HAVE_TLS HAVE_AS_TLS
830 #undef TARGET_CANNOT_FORCE_CONST_MEM
831 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
833 struct gcc_target targetm = TARGET_INITIALIZER;
835 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
837 static enum mips_symbol_type
838 mips_classify_symbol (rtx x)
840 if (GET_CODE (x) == LABEL_REF)
843 return SYMBOL_CONSTANT_POOL;
845 return SYMBOL_GOT_LOCAL;
846 return SYMBOL_GENERAL;
849 gcc_assert (GET_CODE (x) == SYMBOL_REF);
851 if (SYMBOL_REF_TLS_MODEL (x))
854 if (CONSTANT_POOL_ADDRESS_P (x))
857 return SYMBOL_CONSTANT_POOL;
860 return SYMBOL_GOT_LOCAL;
862 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
863 return SYMBOL_SMALL_DATA;
865 return SYMBOL_GENERAL;
868 if (SYMBOL_REF_SMALL_P (x))
869 return SYMBOL_SMALL_DATA;
873 if (SYMBOL_REF_DECL (x) == 0)
874 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
876 /* There are three cases to consider:
878 - o32 PIC (either with or without explicit relocs)
879 - n32/n64 PIC without explicit relocs
880 - n32/n64 PIC with explicit relocs
882 In the first case, both local and global accesses will use an
883 R_MIPS_GOT16 relocation. We must correctly predict which of
884 the two semantics (local or global) the assembler and linker
885 will apply. The choice doesn't depend on the symbol's
886 visibility, so we deliberately ignore decl_visibility and
889 In the second case, the assembler will not use R_MIPS_GOT16
890 relocations, but it chooses between local and global accesses
891 in the same way as for o32 PIC.
893 In the third case we have more freedom since both forms of
894 access will work for any kind of symbol. However, there seems
895 little point in doing things differently. */
896 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
897 return SYMBOL_GOT_GLOBAL;
899 return SYMBOL_GOT_LOCAL;
902 return SYMBOL_GENERAL;
906 /* Split X into a base and a constant offset, storing them in *BASE
907 and *OFFSET respectively. */
910 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
914 if (GET_CODE (x) == CONST)
917 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
919 *offset += INTVAL (XEXP (x, 1));
926 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
927 to the same object as SYMBOL. */
930 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
932 if (GET_CODE (symbol) != SYMBOL_REF)
935 if (CONSTANT_POOL_ADDRESS_P (symbol)
937 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
940 if (SYMBOL_REF_DECL (symbol) != 0
942 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
949 /* Return true if X is a symbolic constant that can be calculated in
950 the same way as a bare symbol. If it is, store the type of the
951 symbol in *SYMBOL_TYPE. */
954 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
956 HOST_WIDE_INT offset;
958 mips_split_const (x, &x, &offset);
959 if (UNSPEC_ADDRESS_P (x))
960 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
961 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
963 *symbol_type = mips_classify_symbol (x);
964 if (*symbol_type == SYMBOL_TLS)
973 /* Check whether a nonzero offset is valid for the underlying
975 switch (*symbol_type)
981 /* If the target has 64-bit pointers and the object file only
982 supports 32-bit symbols, the values of those symbols will be
983 sign-extended. In this case we can't allow an arbitrary offset
984 in case the 32-bit value X + OFFSET has a different sign from X. */
985 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
986 return mips_offset_within_object_p (x, offset);
988 /* In other cases the relocations can handle any offset. */
991 case SYMBOL_CONSTANT_POOL:
992 /* Allow constant pool references to be converted to LABEL+CONSTANT.
993 In this case, we no longer have access to the underlying constant,
994 but the original symbol-based access was known to be valid. */
995 if (GET_CODE (x) == LABEL_REF)
1000 case SYMBOL_SMALL_DATA:
1001 /* Make sure that the offset refers to something within the
1002 underlying object. This should guarantee that the final
1003 PC- or GP-relative offset is within the 16-bit limit. */
1004 return mips_offset_within_object_p (x, offset);
1006 case SYMBOL_GOT_LOCAL:
1007 case SYMBOL_GOTOFF_PAGE:
1008 /* The linker should provide enough local GOT entries for a
1009 16-bit offset. Larger offsets may lead to GOT overflow. */
1010 return SMALL_OPERAND (offset);
1012 case SYMBOL_GOT_GLOBAL:
1013 case SYMBOL_GOTOFF_GLOBAL:
1014 case SYMBOL_GOTOFF_CALL:
1015 case SYMBOL_GOTOFF_LOADGP:
1020 case SYMBOL_GOTTPREL:
1028 /* Return true if X is a symbolic constant whose value is not split
1029 into separate relocations. */
1032 mips_atomic_symbolic_constant_p (rtx x)
1034 enum mips_symbol_type type;
1035 return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
1039 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1042 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1044 if (regno >= FIRST_PSEUDO_REGISTER)
1048 regno = reg_renumber[regno];
1051 /* These fake registers will be eliminated to either the stack or
1052 hard frame pointer, both of which are usually valid base registers.
1053 Reload deals with the cases where the eliminated form isn't valid. */
1054 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1057 /* In mips16 mode, the stack pointer can only address word and doubleword
1058 values, nothing smaller. There are two problems here:
1060 (a) Instantiating virtual registers can introduce new uses of the
1061 stack pointer. If these virtual registers are valid addresses,
1062 the stack pointer should be too.
1064 (b) Most uses of the stack pointer are not made explicit until
1065 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1066 We don't know until that stage whether we'll be eliminating to the
1067 stack pointer (which needs the restriction) or the hard frame
1068 pointer (which doesn't).
1070 All in all, it seems more consistent to only enforce this restriction
1071 during and after reload. */
1072 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1073 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1075 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1079 /* Return true if X is a valid base register for the given mode.
1080 Allow only hard registers if STRICT. */
1083 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1085 if (!strict && GET_CODE (x) == SUBREG)
1089 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1093 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1094 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1097 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1098 enum machine_mode mode)
1100 switch (symbol_type)
1102 case SYMBOL_GENERAL:
1103 return !TARGET_MIPS16;
1105 case SYMBOL_SMALL_DATA:
1108 case SYMBOL_CONSTANT_POOL:
1109 /* PC-relative addressing is only available for lw and ld. */
1110 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1112 case SYMBOL_GOT_LOCAL:
1115 case SYMBOL_GOT_GLOBAL:
1116 /* The address will have to be loaded from the GOT first. */
1123 case SYMBOL_GOTTPREL:
1127 case SYMBOL_GOTOFF_PAGE:
1128 case SYMBOL_GOTOFF_GLOBAL:
1129 case SYMBOL_GOTOFF_CALL:
1130 case SYMBOL_GOTOFF_LOADGP:
1131 case SYMBOL_64_HIGH:
1140 /* Return true if X is a valid address for machine mode MODE. If it is,
1141 fill in INFO appropriately. STRICT is true if we should only accept
1142 hard base registers. */
1145 mips_classify_address (struct mips_address_info *info, rtx x,
1146 enum machine_mode mode, int strict)
1148 switch (GET_CODE (x))
1152 info->type = ADDRESS_REG;
1154 info->offset = const0_rtx;
1155 return mips_valid_base_register_p (info->reg, mode, strict);
1158 info->type = ADDRESS_REG;
1159 info->reg = XEXP (x, 0);
1160 info->offset = XEXP (x, 1);
1161 return (mips_valid_base_register_p (info->reg, mode, strict)
1162 && const_arith_operand (info->offset, VOIDmode));
1165 info->type = ADDRESS_LO_SUM;
1166 info->reg = XEXP (x, 0);
1167 info->offset = XEXP (x, 1);
1168 return (mips_valid_base_register_p (info->reg, mode, strict)
1169 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1170 && mips_symbolic_address_p (info->symbol_type, mode)
1171 && mips_lo_relocs[info->symbol_type] != 0);
1174 /* Small-integer addresses don't occur very often, but they
1175 are legitimate if $0 is a valid base register. */
1176 info->type = ADDRESS_CONST_INT;
1177 return !TARGET_MIPS16 && SMALL_INT (x);
1182 info->type = ADDRESS_SYMBOLIC;
1183 return (mips_symbolic_constant_p (x, &info->symbol_type)
1184 && mips_symbolic_address_p (info->symbol_type, mode)
1185 && !mips_split_p[info->symbol_type]);
1192 /* Return true if X is a thread-local symbol. */
1195 mips_tls_operand_p (rtx x)
1197 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1200 /* Return true if X can not be forced into a constant pool. */
1203 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1205 return mips_tls_operand_p (*x);
1208 /* Return true if X can not be forced into a constant pool. */
1211 mips_cannot_force_const_mem (rtx x)
1213 if (! TARGET_HAVE_TLS)
1216 return for_each_rtx (&x, &mips_tls_symbol_ref_1, 0);
1219 /* Return the number of instructions needed to load a symbol of the
1220 given type into a register. If valid in an address, the same number
1221 of instructions are needed for loads and stores. Treat extended
1222 mips16 instructions as two instructions. */
1225 mips_symbol_insns (enum mips_symbol_type type)
1229 case SYMBOL_GENERAL:
1230 /* In mips16 code, general symbols must be fetched from the
1235 /* When using 64-bit symbols, we need 5 preparatory instructions,
1238 lui $at,%highest(symbol)
1239 daddiu $at,$at,%higher(symbol)
1241 daddiu $at,$at,%hi(symbol)
1244 The final address is then $at + %lo(symbol). With 32-bit
1245 symbols we just need a preparatory lui. */
1246 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1248 case SYMBOL_SMALL_DATA:
1251 case SYMBOL_CONSTANT_POOL:
1252 /* This case is for mips16 only. Assume we'll need an
1253 extended instruction. */
1256 case SYMBOL_GOT_LOCAL:
1257 case SYMBOL_GOT_GLOBAL:
1258 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1259 the local/global classification is accurate. See override_options
1262 The worst cases are:
1264 (1) For local symbols when generating o32 or o64 code. The assembler
1270 ...and the final address will be $at + %lo(symbol).
1272 (2) For global symbols when -mxgot. The assembler will use:
1274 lui $at,%got_hi(symbol)
1277 ...and the final address will be $at + %got_lo(symbol). */
1280 case SYMBOL_GOTOFF_PAGE:
1281 case SYMBOL_GOTOFF_GLOBAL:
1282 case SYMBOL_GOTOFF_CALL:
1283 case SYMBOL_GOTOFF_LOADGP:
1284 case SYMBOL_64_HIGH:
1290 case SYMBOL_GOTTPREL:
1292 /* Check whether the offset is a 16- or 32-bit value. */
1293 return mips_split_p[type] ? 2 : 1;
1296 /* We don't treat a bare TLS symbol as a constant. */
1302 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1305 mips_stack_address_p (rtx x, enum machine_mode mode)
1307 struct mips_address_info addr;
1309 return (mips_classify_address (&addr, x, mode, false)
1310 && addr.type == ADDRESS_REG
1311 && addr.reg == stack_pointer_rtx);
1314 /* Return true if a value at OFFSET bytes from BASE can be accessed
1315 using an unextended mips16 instruction. MODE is the mode of the
1318 Usually the offset in an unextended instruction is a 5-bit field.
1319 The offset is unsigned and shifted left once for HIs, twice
1320 for SIs, and so on. An exception is SImode accesses off the
1321 stack pointer, which have an 8-bit immediate field. */
1324 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1327 && GET_CODE (offset) == CONST_INT
1328 && INTVAL (offset) >= 0
1329 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1331 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1332 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1333 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1339 /* Return the number of instructions needed to load or store a value
1340 of mode MODE at X. Return 0 if X isn't valid for MODE.
1342 For mips16 code, count extended instructions as two instructions. */
1345 mips_address_insns (rtx x, enum machine_mode mode)
1347 struct mips_address_info addr;
1350 if (mode == BLKmode)
1351 /* BLKmode is used for single unaligned loads and stores. */
1354 /* Each word of a multi-word value will be accessed individually. */
1355 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1357 if (mips_classify_address (&addr, x, mode, false))
1362 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1366 case ADDRESS_LO_SUM:
1367 return (TARGET_MIPS16 ? factor * 2 : factor);
1369 case ADDRESS_CONST_INT:
1372 case ADDRESS_SYMBOLIC:
1373 return factor * mips_symbol_insns (addr.symbol_type);
1379 /* Likewise for constant X. */
1382 mips_const_insns (rtx x)
1384 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1385 enum mips_symbol_type symbol_type;
1386 HOST_WIDE_INT offset;
1388 switch (GET_CODE (x))
1392 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1393 || !mips_split_p[symbol_type])
1400 /* Unsigned 8-bit constants can be loaded using an unextended
1401 LI instruction. Unsigned 16-bit constants can be loaded
1402 using an extended LI. Negative constants must be loaded
1403 using LI and then negated. */
1404 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1405 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1406 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1407 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1410 return mips_build_integer (codes, INTVAL (x));
1414 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1420 /* See if we can refer to X directly. */
1421 if (mips_symbolic_constant_p (x, &symbol_type))
1422 return mips_symbol_insns (symbol_type);
1424 /* Otherwise try splitting the constant into a base and offset.
1425 16-bit offsets can be added using an extra addiu. Larger offsets
1426 must be calculated separately and then added to the base. */
1427 mips_split_const (x, &x, &offset);
1430 int n = mips_const_insns (x);
1433 if (SMALL_OPERAND (offset))
1436 return n + 1 + mips_build_integer (codes, offset);
1443 return mips_symbol_insns (mips_classify_symbol (x));
1451 /* Return the number of instructions needed for memory reference X.
1452 Count extended mips16 instructions as two instructions. */
1455 mips_fetch_insns (rtx x)
1457 gcc_assert (MEM_P (x));
1458 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1462 /* Return the number of instructions needed for an integer division. */
1465 mips_idiv_insns (void)
1470 if (TARGET_CHECK_ZERO_DIV)
1472 if (GENERATE_DIVIDE_TRAPS)
1478 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1483 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1484 returns a nonzero value if X is a legitimate address for a memory
1485 operand of the indicated MODE. STRICT is nonzero if this function
1486 is called during reload. */
1489 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1491 struct mips_address_info addr;
1493 return mips_classify_address (&addr, x, mode, strict);
1497 /* Copy VALUE to a register and return that register. If new psuedos
1498 are allowed, copy it into a new register, otherwise use DEST. */
1501 mips_force_temporary (rtx dest, rtx value)
1503 if (!no_new_pseudos)
1504 return force_reg (Pmode, value);
1507 emit_move_insn (copy_rtx (dest), value);
1513 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1514 and is used to load the high part into a register. */
1517 mips_split_symbol (rtx temp, rtx addr)
1522 high = mips16_gp_pseudo_reg ();
1524 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1525 return gen_rtx_LO_SUM (Pmode, high, addr);
1529 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1530 type SYMBOL_TYPE. */
1533 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1536 HOST_WIDE_INT offset;
1538 mips_split_const (address, &base, &offset);
1539 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1540 UNSPEC_ADDRESS_FIRST + symbol_type);
1541 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1545 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1546 high part to BASE and return the result. Just return BASE otherwise.
1547 TEMP is available as a temporary register if needed.
1549 The returned expression can be used as the first operand to a LO_SUM. */
1552 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1553 enum mips_symbol_type symbol_type)
1555 if (mips_split_p[symbol_type])
1557 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1558 addr = mips_force_temporary (temp, addr);
1559 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1565 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1566 mips_force_temporary; it is only needed when OFFSET is not a
1570 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1572 if (!SMALL_OPERAND (offset))
1577 /* Load the full offset into a register so that we can use
1578 an unextended instruction for the address itself. */
1579 high = GEN_INT (offset);
1584 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1585 high = GEN_INT (CONST_HIGH_PART (offset));
1586 offset = CONST_LOW_PART (offset);
1588 high = mips_force_temporary (temp, high);
1589 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1591 return plus_constant (reg, offset);
1594 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1595 referencing, and TYPE is the symbol type to use (either global
1596 dynamic or local dynamic). V0 is an RTX for the return value
1597 location. The entire insn sequence is returned. */
1599 static GTY(()) rtx mips_tls_symbol;
1602 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1604 rtx insn, loc, tga, a0;
1606 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1608 if (!mips_tls_symbol)
1609 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1611 loc = mips_unspec_address (sym, type);
1615 emit_insn (gen_rtx_SET (Pmode, a0,
1616 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1617 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1618 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1619 CONST_OR_PURE_CALL_P (insn) = 1;
1620 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1621 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1622 insn = get_insns ();
1629 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1630 return value will be a valid address and move_operand (either a REG
1634 mips_legitimize_tls_address (rtx loc)
1636 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
1637 enum tls_model model;
1639 v0 = gen_rtx_REG (Pmode, GP_RETURN);
1640 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
1642 model = SYMBOL_REF_TLS_MODEL (loc);
1646 case TLS_MODEL_GLOBAL_DYNAMIC:
1647 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
1648 dest = gen_reg_rtx (Pmode);
1649 emit_libcall_block (insn, dest, v0, loc);
1652 case TLS_MODEL_LOCAL_DYNAMIC:
1653 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
1654 tmp1 = gen_reg_rtx (Pmode);
1656 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
1657 share the LDM result with other LD model accesses. */
1658 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1660 emit_libcall_block (insn, tmp1, v0, eqv);
1662 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
1663 dest = gen_rtx_LO_SUM (Pmode, tmp2,
1664 mips_unspec_address (loc, SYMBOL_DTPREL));
1667 case TLS_MODEL_INITIAL_EXEC:
1668 tmp1 = gen_reg_rtx (Pmode);
1669 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
1670 if (Pmode == DImode)
1672 emit_insn (gen_tls_get_tp_di (v1));
1673 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
1677 emit_insn (gen_tls_get_tp_si (v1));
1678 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
1680 dest = gen_reg_rtx (Pmode);
1681 emit_insn (gen_add3_insn (dest, tmp1, v1));
1684 case TLS_MODEL_LOCAL_EXEC:
1686 if (Pmode == DImode)
1687 emit_insn (gen_tls_get_tp_di (v1));
1689 emit_insn (gen_tls_get_tp_si (v1));
1691 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
1692 dest = gen_rtx_LO_SUM (Pmode, tmp1,
1693 mips_unspec_address (loc, SYMBOL_TPREL));
1703 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1704 be legitimized in a way that the generic machinery might not expect,
1705 put the new address in *XLOC and return true. MODE is the mode of
1706 the memory being accessed. */
1709 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1711 enum mips_symbol_type symbol_type;
1713 if (mips_tls_operand_p (*xloc))
1715 *xloc = mips_legitimize_tls_address (*xloc);
1719 /* See if the address can split into a high part and a LO_SUM. */
1720 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1721 && mips_symbolic_address_p (symbol_type, mode)
1722 && mips_split_p[symbol_type])
1724 *xloc = mips_split_symbol (0, *xloc);
1728 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1730 /* Handle REG + CONSTANT using mips_add_offset. */
1733 reg = XEXP (*xloc, 0);
1734 if (!mips_valid_base_register_p (reg, mode, 0))
1735 reg = copy_to_mode_reg (Pmode, reg);
1736 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
1744 /* Subroutine of mips_build_integer (with the same interface).
1745 Assume that the final action in the sequence should be a left shift. */
1748 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1750 unsigned int i, shift;
1752 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1753 since signed numbers are easier to load than unsigned ones. */
1755 while ((value & 1) == 0)
1756 value /= 2, shift++;
1758 i = mips_build_integer (codes, value);
1759 codes[i].code = ASHIFT;
1760 codes[i].value = shift;
1765 /* As for mips_build_shift, but assume that the final action will be
1766 an IOR or PLUS operation. */
1769 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1771 unsigned HOST_WIDE_INT high;
1774 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1775 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1777 /* The constant is too complex to load with a simple lui/ori pair
1778 so our goal is to clear as many trailing zeros as possible.
1779 In this case, we know bit 16 is set and that the low 16 bits
1780 form a negative number. If we subtract that number from VALUE,
1781 we will clear at least the lowest 17 bits, maybe more. */
1782 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1783 codes[i].code = PLUS;
1784 codes[i].value = CONST_LOW_PART (value);
1788 i = mips_build_integer (codes, high);
1789 codes[i].code = IOR;
1790 codes[i].value = value & 0xffff;
1796 /* Fill CODES with a sequence of rtl operations to load VALUE.
1797 Return the number of operations needed. */
1800 mips_build_integer (struct mips_integer_op *codes,
1801 unsigned HOST_WIDE_INT value)
1803 if (SMALL_OPERAND (value)
1804 || SMALL_OPERAND_UNSIGNED (value)
1805 || LUI_OPERAND (value))
1807 /* The value can be loaded with a single instruction. */
1808 codes[0].code = UNKNOWN;
1809 codes[0].value = value;
1812 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1814 /* Either the constant is a simple LUI/ORI combination or its
1815 lowest bit is set. We don't want to shift in this case. */
1816 return mips_build_lower (codes, value);
1818 else if ((value & 0xffff) == 0)
1820 /* The constant will need at least three actions. The lowest
1821 16 bits are clear, so the final action will be a shift. */
1822 return mips_build_shift (codes, value);
1826 /* The final action could be a shift, add or inclusive OR.
1827 Rather than use a complex condition to select the best
1828 approach, try both mips_build_shift and mips_build_lower
1829 and pick the one that gives the shortest sequence.
1830 Note that this case is only used once per constant. */
1831 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1832 unsigned int cost, alt_cost;
1834 cost = mips_build_shift (codes, value);
1835 alt_cost = mips_build_lower (alt_codes, value);
1836 if (alt_cost < cost)
1838 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1846 /* Move VALUE into register DEST. */
1849 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1851 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1852 enum machine_mode mode;
1853 unsigned int i, cost;
1856 mode = GET_MODE (dest);
1857 cost = mips_build_integer (codes, value);
1859 /* Apply each binary operation to X. Invariant: X is a legitimate
1860 source operand for a SET pattern. */
1861 x = GEN_INT (codes[0].value);
1862 for (i = 1; i < cost; i++)
1865 emit_move_insn (dest, x), x = dest;
1867 x = force_reg (mode, x);
1868 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1871 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1875 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1876 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1880 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1883 HOST_WIDE_INT offset;
1884 enum mips_symbol_type symbol_type;
1886 /* Split moves of big integers into smaller pieces. In mips16 code,
1887 it's better to force the constant into memory instead. */
1888 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1890 mips_move_integer (dest, INTVAL (src));
1894 if (mips_tls_operand_p (src))
1896 emit_move_insn (dest, mips_legitimize_tls_address (src));
1900 /* See if the symbol can be split. For mips16, this is often worse than
1901 forcing it in the constant pool since it needs the single-register form
1902 of addiu or daddiu. */
1904 && mips_symbolic_constant_p (src, &symbol_type)
1905 && mips_split_p[symbol_type])
1907 emit_move_insn (dest, mips_split_symbol (dest, src));
1911 /* If we have (const (plus symbol offset)), load the symbol first
1912 and then add in the offset. This is usually better than forcing
1913 the constant into memory, at least in non-mips16 code. */
1914 mips_split_const (src, &base, &offset);
1917 && (!no_new_pseudos || SMALL_OPERAND (offset)))
1919 base = mips_force_temporary (dest, base);
1920 emit_move_insn (dest, mips_add_offset (0, base, offset));
1924 src = force_const_mem (mode, src);
1926 /* When using explicit relocs, constant pool references are sometimes
1927 not legitimate addresses. */
1928 if (!memory_operand (src, VOIDmode))
1929 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1930 emit_move_insn (dest, src);
1934 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1935 sequence that is valid. */
1938 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
1940 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1942 emit_move_insn (dest, force_reg (mode, src));
1946 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
1947 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1948 && REG_P (src) && MD_REG_P (REGNO (src))
1949 && REG_P (dest) && GP_REG_P (REGNO (dest)))
1951 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
1952 if (GET_MODE_SIZE (mode) <= 4)
1953 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
1954 gen_rtx_REG (SImode, REGNO (src)),
1955 gen_rtx_REG (SImode, other_regno)));
1957 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
1958 gen_rtx_REG (DImode, REGNO (src)),
1959 gen_rtx_REG (DImode, other_regno)));
1963 /* We need to deal with constants that would be legitimate
1964 immediate_operands but not legitimate move_operands. */
1965 if (CONSTANT_P (src) && !move_operand (src, mode))
1967 mips_legitimize_const_move (mode, dest, src);
1968 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
1974 /* We need a lot of little routines to check constant values on the
1975 mips16. These are used to figure out how long the instruction will
1976 be. It would be much better to do this using constraints, but
1977 there aren't nearly enough letters available. */
1980 m16_check_op (rtx op, int low, int high, int mask)
1982 return (GET_CODE (op) == CONST_INT
1983 && INTVAL (op) >= low
1984 && INTVAL (op) <= high
1985 && (INTVAL (op) & mask) == 0);
1989 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1991 return m16_check_op (op, 0x1, 0x8, 0);
1995 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1997 return m16_check_op (op, - 0x8, 0x7, 0);
2001 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2003 return m16_check_op (op, - 0x7, 0x8, 0);
2007 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2009 return m16_check_op (op, - 0x10, 0xf, 0);
2013 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2015 return m16_check_op (op, - 0xf, 0x10, 0);
2019 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2021 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2025 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2027 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2031 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2033 return m16_check_op (op, - 0x80, 0x7f, 0);
2037 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2039 return m16_check_op (op, - 0x7f, 0x80, 0);
2043 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2045 return m16_check_op (op, 0x0, 0xff, 0);
2049 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2051 return m16_check_op (op, - 0xff, 0x0, 0);
2055 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2057 return m16_check_op (op, - 0x1, 0xfe, 0);
2061 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2063 return m16_check_op (op, 0x0, 0xff << 2, 3);
2067 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2069 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2073 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2075 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2079 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2081 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2085 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2087 enum machine_mode mode = GET_MODE (x);
2094 /* Always return 0, since we don't have different sized
2095 instructions, hence different costs according to Richard
2101 /* A number between 1 and 8 inclusive is efficient for a shift.
2102 Otherwise, we will need an extended instruction. */
2103 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2104 || (outer_code) == LSHIFTRT)
2106 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2109 *total = COSTS_N_INSNS (1);
2113 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2114 if ((outer_code) == XOR
2115 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2121 /* We may be able to use slt or sltu for a comparison with a
2122 signed 16 bit value. (The boundary conditions aren't quite
2123 right, but this is just a heuristic anyhow.) */
2124 if (((outer_code) == LT || (outer_code) == LE
2125 || (outer_code) == GE || (outer_code) == GT
2126 || (outer_code) == LTU || (outer_code) == LEU
2127 || (outer_code) == GEU || (outer_code) == GTU)
2128 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2134 /* Equality comparisons with 0 are cheap. */
2135 if (((outer_code) == EQ || (outer_code) == NE)
2142 /* Constants in the range 0...255 can be loaded with an unextended
2143 instruction. They are therefore as cheap as a register move.
2145 Given the choice between "li R1,0...255" and "move R1,R2"
2146 (where R2 is a known constant), it is usually better to use "li",
2147 since we do not want to unnecessarily extend the lifetime of R2. */
2148 if (outer_code == SET
2150 && INTVAL (x) < 256)
2156 /* Otherwise fall through to the handling below. */
2162 if (LEGITIMATE_CONSTANT_P (x))
2164 *total = COSTS_N_INSNS (1);
2169 /* The value will need to be fetched from the constant pool. */
2170 *total = CONSTANT_POOL_COST;
2176 /* If the address is legitimate, return the number of
2177 instructions it needs, otherwise use the default handling. */
2178 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2181 *total = COSTS_N_INSNS (1 + n);
2188 *total = COSTS_N_INSNS (6);
2192 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2198 if (mode == DImode && !TARGET_64BIT)
2200 *total = COSTS_N_INSNS (2);
2208 if (mode == DImode && !TARGET_64BIT)
2210 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2217 if (mode == SFmode || mode == DFmode)
2218 *total = COSTS_N_INSNS (1);
2220 *total = COSTS_N_INSNS (4);
2224 *total = COSTS_N_INSNS (1);
2229 if (mode == SFmode || mode == DFmode)
2231 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2232 *total = COSTS_N_INSNS (2);
2233 else if (TUNE_MIPS6000)
2234 *total = COSTS_N_INSNS (3);
2236 *total = COSTS_N_INSNS (4);
2238 *total = COSTS_N_INSNS (6);
2241 if (mode == DImode && !TARGET_64BIT)
2243 *total = COSTS_N_INSNS (4);
2249 if (mode == DImode && !TARGET_64BIT)
2263 *total = COSTS_N_INSNS (4);
2264 else if (TUNE_MIPS6000
2267 *total = COSTS_N_INSNS (5);
2269 *total = COSTS_N_INSNS (7);
2276 *total = COSTS_N_INSNS (4);
2277 else if (TUNE_MIPS3000
2280 *total = COSTS_N_INSNS (5);
2281 else if (TUNE_MIPS6000
2284 *total = COSTS_N_INSNS (6);
2286 *total = COSTS_N_INSNS (8);
2291 *total = COSTS_N_INSNS (12);
2292 else if (TUNE_MIPS3900)
2293 *total = COSTS_N_INSNS (2);
2294 else if (TUNE_MIPS4130)
2295 *total = COSTS_N_INSNS (mode == DImode ? 6 : 4);
2296 else if (TUNE_MIPS5400 || TUNE_SB1)
2297 *total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
2298 else if (TUNE_MIPS5500 || TUNE_MIPS7000)
2299 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2300 else if (TUNE_MIPS9000)
2301 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2302 else if (TUNE_MIPS6000)
2303 *total = COSTS_N_INSNS (17);
2304 else if (TUNE_MIPS5000)
2305 *total = COSTS_N_INSNS (5);
2307 *total = COSTS_N_INSNS (10);
2316 *total = COSTS_N_INSNS (12);
2317 else if (TUNE_MIPS6000)
2318 *total = COSTS_N_INSNS (15);
2320 *total = COSTS_N_INSNS (24);
2321 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2322 *total = COSTS_N_INSNS (30);
2324 *total = COSTS_N_INSNS (23);
2332 *total = COSTS_N_INSNS (19);
2333 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2334 *total = COSTS_N_INSNS (59);
2335 else if (TUNE_MIPS6000)
2336 *total = COSTS_N_INSNS (16);
2338 *total = COSTS_N_INSNS (32);
2340 *total = COSTS_N_INSNS (36);
2349 *total = COSTS_N_INSNS (35);
2350 else if (TUNE_MIPS6000)
2351 *total = COSTS_N_INSNS (38);
2352 else if (TUNE_MIPS5000)
2353 *total = COSTS_N_INSNS (36);
2355 *total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
2356 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2357 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2359 *total = COSTS_N_INSNS (69);
2363 /* A sign extend from SImode to DImode in 64 bit mode is often
2364 zero instructions, because the result can often be used
2365 directly by another instruction; we'll call it one. */
2366 if (TARGET_64BIT && mode == DImode
2367 && GET_MODE (XEXP (x, 0)) == SImode)
2368 *total = COSTS_N_INSNS (1);
2370 *total = COSTS_N_INSNS (2);
2374 if (TARGET_64BIT && mode == DImode
2375 && GET_MODE (XEXP (x, 0)) == SImode)
2376 *total = COSTS_N_INSNS (2);
2378 *total = COSTS_N_INSNS (1);
2386 /* Provide the costs of an addressing mode that contains ADDR.
2387 If ADDR is not a valid address, its cost is irrelevant. */
2390 mips_address_cost (rtx addr)
2392 return mips_address_insns (addr, SImode);
2395 /* Return one word of double-word value OP, taking into account the fixed
2396 endianness of certain registers. HIGH_P is true to select the high part,
2397 false to select the low part. */
2400 mips_subword (rtx op, int high_p)
2403 enum machine_mode mode;
2405 mode = GET_MODE (op);
2406 if (mode == VOIDmode)
2409 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2410 byte = UNITS_PER_WORD;
2416 if (FP_REG_P (REGNO (op)))
2417 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2418 if (REGNO (op) == HI_REGNUM)
2419 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2423 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2425 return simplify_gen_subreg (word_mode, op, mode, byte);
2429 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2432 mips_split_64bit_move_p (rtx dest, rtx src)
2437 /* FP->FP moves can be done in a single instruction. */
2438 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2441 /* Check for floating-point loads and stores. They can be done using
2442 ldc1 and sdc1 on MIPS II and above. */
2445 if (FP_REG_RTX_P (dest) && MEM_P (src))
2447 if (FP_REG_RTX_P (src) && MEM_P (dest))
2454 /* Split a 64-bit move from SRC to DEST assuming that
2455 mips_split_64bit_move_p holds.
2457 Moves into and out of FPRs cause some difficulty here. Such moves
2458 will always be DFmode, since paired FPRs are not allowed to store
2459 DImode values. The most natural representation would be two separate
2460 32-bit moves, such as:
2462 (set (reg:SI $f0) (mem:SI ...))
2463 (set (reg:SI $f1) (mem:SI ...))
2465 However, the second insn is invalid because odd-numbered FPRs are
2466 not allowed to store independent values. Use the patterns load_df_low,
2467 load_df_high and store_df_high instead. */
2470 mips_split_64bit_move (rtx dest, rtx src)
2472 if (FP_REG_RTX_P (dest))
2474 /* Loading an FPR from memory or from GPRs. */
2475 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2476 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2479 else if (FP_REG_RTX_P (src))
2481 /* Storing an FPR into memory or GPRs. */
2482 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2483 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2487 /* The operation can be split into two normal moves. Decide in
2488 which order to do them. */
2491 low_dest = mips_subword (dest, 0);
2492 if (REG_P (low_dest)
2493 && reg_overlap_mentioned_p (low_dest, src))
2495 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2496 emit_move_insn (low_dest, mips_subword (src, 0));
2500 emit_move_insn (low_dest, mips_subword (src, 0));
2501 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2506 /* Return the appropriate instructions to move SRC into DEST. Assume
2507 that SRC is operand 1 and DEST is operand 0. */
2510 mips_output_move (rtx dest, rtx src)
2512 enum rtx_code dest_code, src_code;
2515 dest_code = GET_CODE (dest);
2516 src_code = GET_CODE (src);
2517 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2519 if (dbl_p && mips_split_64bit_move_p (dest, src))
2522 if ((src_code == REG && GP_REG_P (REGNO (src)))
2523 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2525 if (dest_code == REG)
2527 if (GP_REG_P (REGNO (dest)))
2528 return "move\t%0,%z1";
2530 if (MD_REG_P (REGNO (dest)))
2533 if (FP_REG_P (REGNO (dest)))
2534 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2536 if (ALL_COP_REG_P (REGNO (dest)))
2538 static char retval[] = "dmtc_\t%z1,%0";
2540 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2541 return (dbl_p ? retval : retval + 1);
2544 if (dest_code == MEM)
2545 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2547 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2549 if (src_code == REG)
2551 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2552 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2554 if (FP_REG_P (REGNO (src)))
2555 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2557 if (ALL_COP_REG_P (REGNO (src)))
2559 static char retval[] = "dmfc_\t%0,%1";
2561 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2562 return (dbl_p ? retval : retval + 1);
2566 if (src_code == MEM)
2567 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2569 if (src_code == CONST_INT)
2571 /* Don't use the X format, because that will give out of
2572 range numbers for 64 bit hosts and 32 bit targets. */
2574 return "li\t%0,%1\t\t\t# %X1";
2576 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2579 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2583 if (src_code == HIGH)
2584 return "lui\t%0,%h1";
2586 if (CONST_GP_P (src))
2587 return "move\t%0,%1";
2589 if (symbolic_operand (src, VOIDmode))
2590 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2592 if (src_code == REG && FP_REG_P (REGNO (src)))
2594 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2596 if (GET_MODE (dest) == V2SFmode)
2597 return "mov.ps\t%0,%1";
2599 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2602 if (dest_code == MEM)
2603 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2605 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2607 if (src_code == MEM)
2608 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2610 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2612 static char retval[] = "l_c_\t%0,%1";
2614 retval[1] = (dbl_p ? 'd' : 'w');
2615 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2618 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2620 static char retval[] = "s_c_\t%1,%0";
2622 retval[1] = (dbl_p ? 'd' : 'w');
2623 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2629 /* Restore $gp from its save slot. Valid only when using o32 or
2633 mips_restore_gp (void)
2637 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2639 address = mips_add_offset (pic_offset_table_rtx,
2640 frame_pointer_needed
2641 ? hard_frame_pointer_rtx
2642 : stack_pointer_rtx,
2643 current_function_outgoing_args_size);
2644 slot = gen_rtx_MEM (Pmode, address);
2646 emit_move_insn (pic_offset_table_rtx, slot);
2647 if (!TARGET_EXPLICIT_RELOCS)
2648 emit_insn (gen_blockage ());
2651 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2654 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2656 emit_insn (gen_rtx_SET (VOIDmode, target,
2657 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2660 /* Return true if CMP1 is a suitable second operand for relational
2661 operator CODE. See also the *sCC patterns in mips.md. */
2664 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2670 return reg_or_0_operand (cmp1, VOIDmode);
2674 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2678 return arith_operand (cmp1, VOIDmode);
2681 return sle_operand (cmp1, VOIDmode);
2684 return sleu_operand (cmp1, VOIDmode);
2691 /* Compare CMP0 and CMP1 using relational operator CODE and store the
2692 result in TARGET. CMP0 and TARGET are register_operands that have
2693 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
2694 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
2697 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
2698 rtx target, rtx cmp0, rtx cmp1)
2700 /* First see if there is a MIPS instruction that can do this operation
2701 with CMP1 in its current form. If not, try doing the same for the
2702 inverse operation. If that also fails, force CMP1 into a register
2704 if (mips_relational_operand_ok_p (code, cmp1))
2705 mips_emit_binary (code, target, cmp0, cmp1);
2708 enum rtx_code inv_code = reverse_condition (code);
2709 if (!mips_relational_operand_ok_p (inv_code, cmp1))
2711 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
2712 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
2714 else if (invert_ptr == 0)
2716 rtx inv_target = gen_reg_rtx (GET_MODE (target));
2717 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
2718 mips_emit_binary (XOR, target, inv_target, const1_rtx);
2722 *invert_ptr = !*invert_ptr;
2723 mips_emit_binary (inv_code, target, cmp0, cmp1);
2728 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2729 The register will have the same mode as CMP0. */
2732 mips_zero_if_equal (rtx cmp0, rtx cmp1)
2734 if (cmp1 == const0_rtx)
2737 if (uns_arith_operand (cmp1, VOIDmode))
2738 return expand_binop (GET_MODE (cmp0), xor_optab,
2739 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2741 return expand_binop (GET_MODE (cmp0), sub_optab,
2742 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2745 /* Convert a comparison into something that can be used in a branch or
2746 conditional move. cmp_operands[0] and cmp_operands[1] are the values
2747 being compared and *CODE is the code used to compare them.
2749 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
2750 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
2751 otherwise any standard branch condition can be used. The standard branch
2754 - EQ/NE between two registers.
2755 - any comparison between a register and zero. */
2758 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
2760 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
2762 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
2764 *op0 = cmp_operands[0];
2765 *op1 = cmp_operands[1];
2767 else if (*code == EQ || *code == NE)
2771 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2776 *op0 = cmp_operands[0];
2777 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
2782 /* The comparison needs a separate scc instruction. Store the
2783 result of the scc in *OP0 and compare it against zero. */
2784 bool invert = false;
2785 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
2787 mips_emit_int_relational (*code, &invert, *op0,
2788 cmp_operands[0], cmp_operands[1]);
2789 *code = (invert ? EQ : NE);
2794 enum rtx_code cmp_code;
2796 /* Floating-point tests use a separate c.cond.fmt comparison to
2797 set a condition code register. The branch or conditional move
2798 will then compare that register against zero.
2800 Set CMP_CODE to the code of the comparison instruction and
2801 *CODE to the code that the branch or move should use. */
2809 cmp_code = reverse_condition_maybe_unordered (*code);
2819 ? gen_reg_rtx (CCmode)
2820 : gen_rtx_REG (CCmode, FPSW_REGNUM));
2822 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
2826 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
2827 Store the result in TARGET and return true if successful.
2829 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
2832 mips_emit_scc (enum rtx_code code, rtx target)
2834 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
2837 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
2838 if (code == EQ || code == NE)
2840 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2841 mips_emit_binary (code, target, zie, const0_rtx);
2844 mips_emit_int_relational (code, 0, target,
2845 cmp_operands[0], cmp_operands[1]);
2849 /* Emit the common code for doing conditional branches.
2850 operand[0] is the label to jump to.
2851 The comparison operands are saved away by cmp{si,di,sf,df}. */
2854 gen_conditional_branch (rtx *operands, enum rtx_code code)
2856 rtx op0, op1, target;
2858 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
2859 target = gen_rtx_IF_THEN_ELSE (VOIDmode,
2860 gen_rtx_fmt_ee (code, GET_MODE (op0),
2862 gen_rtx_LABEL_REF (VOIDmode, operands[0]),
2864 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
2867 /* Emit the common code for conditional moves. OPERANDS is the array
2868 of operands passed to the conditional move define_expand. */
2871 gen_conditional_move (rtx *operands)
2876 code = GET_CODE (operands[1]);
2877 mips_emit_compare (&code, &op0, &op1, true);
2878 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2879 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2880 gen_rtx_fmt_ee (code,
2883 operands[2], operands[3])));
2886 /* Emit a conditional trap. OPERANDS is the array of operands passed to
2887 the conditional_trap expander. */
2890 mips_gen_conditional_trap (rtx *operands)
2893 enum rtx_code cmp_code = GET_CODE (operands[0]);
2894 enum machine_mode mode = GET_MODE (cmp_operands[0]);
2896 /* MIPS conditional trap machine instructions don't have GT or LE
2897 flavors, so we must invert the comparison and convert to LT and
2898 GE, respectively. */
2901 case GT: cmp_code = LT; break;
2902 case LE: cmp_code = GE; break;
2903 case GTU: cmp_code = LTU; break;
2904 case LEU: cmp_code = GEU; break;
2907 if (cmp_code == GET_CODE (operands[0]))
2909 op0 = cmp_operands[0];
2910 op1 = cmp_operands[1];
2914 op0 = cmp_operands[1];
2915 op1 = cmp_operands[0];
2917 op0 = force_reg (mode, op0);
2918 if (!arith_operand (op1, mode))
2919 op1 = force_reg (mode, op1);
2921 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
2922 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
2926 /* Load function address ADDR into register DEST. SIBCALL_P is true
2927 if the address is needed for a sibling call. */
2930 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
2932 /* If we're generating PIC, and this call is to a global function,
2933 try to allow its address to be resolved lazily. This isn't
2934 possible for NewABI sibcalls since the value of $gp on entry
2935 to the stub would be our caller's gp, not ours. */
2936 if (TARGET_EXPLICIT_RELOCS
2937 && !(sibcall_p && TARGET_NEWABI)
2938 && global_got_operand (addr, VOIDmode))
2940 rtx high, lo_sum_symbol;
2942 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
2943 addr, SYMBOL_GOTOFF_CALL);
2944 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
2945 if (Pmode == SImode)
2946 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
2948 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
2951 emit_move_insn (dest, addr);
2955 /* Expand a call or call_value instruction. RESULT is where the
2956 result will go (null for calls), ADDR is the address of the
2957 function, ARGS_SIZE is the size of the arguments and AUX is
2958 the value passed to us by mips_function_arg. SIBCALL_P is true
2959 if we are expanding a sibling call, false if we're expanding
2963 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
2965 rtx orig_addr, pattern, insn;
2968 if (!call_insn_operand (addr, VOIDmode))
2970 addr = gen_reg_rtx (Pmode);
2971 mips_load_call_address (addr, orig_addr, sibcall_p);
2975 && mips16_hard_float
2976 && build_mips16_call_stub (result, addr, args_size,
2977 aux == 0 ? 0 : (int) GET_MODE (aux)))
2981 pattern = (sibcall_p
2982 ? gen_sibcall_internal (addr, args_size)
2983 : gen_call_internal (addr, args_size));
2984 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
2988 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
2989 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
2992 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
2993 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
2996 pattern = (sibcall_p
2997 ? gen_sibcall_value_internal (result, addr, args_size)
2998 : gen_call_value_internal (result, addr, args_size));
3000 insn = emit_call_insn (pattern);
3002 /* Lazy-binding stubs require $gp to be valid on entry. */
3003 if (global_got_operand (orig_addr, VOIDmode))
3004 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3008 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3011 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3012 tree exp ATTRIBUTE_UNUSED)
3014 return TARGET_SIBCALLS;
3017 /* Emit code to move general operand SRC into condition-code
3018 register DEST. SCRATCH is a scratch TFmode float register.
3025 where FP1 and FP2 are single-precision float registers
3026 taken from SCRATCH. */
3029 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3033 /* Change the source to SFmode. */
3035 src = adjust_address (src, SFmode, 0);
3036 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3037 src = gen_rtx_REG (SFmode, true_regnum (src));
3039 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3040 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3042 emit_move_insn (copy_rtx (fp1), src);
3043 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3044 emit_insn (gen_slt_sf (dest, fp2, fp1));
3047 /* Emit code to change the current function's return address to
3048 ADDRESS. SCRATCH is available as a scratch register, if needed.
3049 ADDRESS and SCRATCH are both word-mode GPRs. */
3052 mips_set_return_address (rtx address, rtx scratch)
3056 compute_frame_size (get_frame_size ());
3057 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3058 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3059 cfun->machine->frame.gp_sp_offset);
3061 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3064 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3065 Assume that the areas do not overlap. */
3068 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3070 HOST_WIDE_INT offset, delta;
3071 unsigned HOST_WIDE_INT bits;
3073 enum machine_mode mode;
3076 /* Work out how many bits to move at a time. If both operands have
3077 half-word alignment, it is usually better to move in half words.
3078 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3079 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3080 Otherwise move word-sized chunks. */
3081 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3082 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3083 bits = BITS_PER_WORD / 2;
3085 bits = BITS_PER_WORD;
3087 mode = mode_for_size (bits, MODE_INT, 0);
3088 delta = bits / BITS_PER_UNIT;
3090 /* Allocate a buffer for the temporary registers. */
3091 regs = alloca (sizeof (rtx) * length / delta);
3093 /* Load as many BITS-sized chunks as possible. Use a normal load if
3094 the source has enough alignment, otherwise use left/right pairs. */
3095 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3097 regs[i] = gen_reg_rtx (mode);
3098 if (MEM_ALIGN (src) >= bits)
3099 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3102 rtx part = adjust_address (src, BLKmode, offset);
3103 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3108 /* Copy the chunks to the destination. */
3109 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3110 if (MEM_ALIGN (dest) >= bits)
3111 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3114 rtx part = adjust_address (dest, BLKmode, offset);
3115 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3119 /* Mop up any left-over bytes. */
3120 if (offset < length)
3122 src = adjust_address (src, BLKmode, offset);
3123 dest = adjust_address (dest, BLKmode, offset);
3124 move_by_pieces (dest, src, length - offset,
3125 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3129 #define MAX_MOVE_REGS 4
3130 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3133 /* Helper function for doing a loop-based block operation on memory
3134 reference MEM. Each iteration of the loop will operate on LENGTH
3137 Create a new base register for use within the loop and point it to
3138 the start of MEM. Create a new memory reference that uses this
3139 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3142 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3143 rtx *loop_reg, rtx *loop_mem)
3145 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3147 /* Although the new mem does not refer to a known location,
3148 it does keep up to LENGTH bytes of alignment. */
3149 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3150 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3154 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3155 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3156 memory regions do not overlap. */
3159 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3161 rtx label, src_reg, dest_reg, final_src;
3162 HOST_WIDE_INT leftover;
3164 leftover = length % MAX_MOVE_BYTES;
3167 /* Create registers and memory references for use within the loop. */
3168 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3169 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3171 /* Calculate the value that SRC_REG should have after the last iteration
3173 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3176 /* Emit the start of the loop. */
3177 label = gen_label_rtx ();
3180 /* Emit the loop body. */
3181 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3183 /* Move on to the next block. */
3184 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3185 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3187 /* Emit the loop condition. */
3188 if (Pmode == DImode)
3189 emit_insn (gen_cmpdi (src_reg, final_src));
3191 emit_insn (gen_cmpsi (src_reg, final_src));
3192 emit_jump_insn (gen_bne (label));
3194 /* Mop up any left-over bytes. */
3196 mips_block_move_straight (dest, src, leftover);
3199 /* Expand a movmemsi instruction. */
3202 mips_expand_block_move (rtx dest, rtx src, rtx length)
3204 if (GET_CODE (length) == CONST_INT)
3206 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3208 mips_block_move_straight (dest, src, INTVAL (length));
3213 mips_block_move_loop (dest, src, INTVAL (length));
3220 /* Argument support functions. */
3222 /* Initialize CUMULATIVE_ARGS for a function. */
3225 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3226 rtx libname ATTRIBUTE_UNUSED)
3228 static CUMULATIVE_ARGS zero_cum;
3229 tree param, next_param;
3232 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3234 /* Determine if this function has variable arguments. This is
3235 indicated by the last argument being 'void_type_mode' if there
3236 are no variable arguments. The standard MIPS calling sequence
3237 passes all arguments in the general purpose registers in this case. */
3239 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3240 param != 0; param = next_param)
3242 next_param = TREE_CHAIN (param);
3243 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3244 cum->gp_reg_found = 1;
3249 /* Fill INFO with information about a single argument. CUM is the
3250 cumulative state for earlier arguments. MODE is the mode of this
3251 argument and TYPE is its type (if known). NAMED is true if this
3252 is a named (fixed) argument rather than a variable one. */
3255 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3256 tree type, int named, struct mips_arg_info *info)
3258 bool doubleword_aligned_p;
3259 unsigned int num_bytes, num_words, max_regs;
3261 /* Work out the size of the argument. */
3262 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3263 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3265 /* Decide whether it should go in a floating-point register, assuming
3266 one is free. Later code checks for availability.
3268 The checks against UNITS_PER_FPVALUE handle the soft-float and
3269 single-float cases. */
3273 /* The EABI conventions have traditionally been defined in terms
3274 of TYPE_MODE, regardless of the actual type. */
3275 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3276 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3277 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3282 /* Only leading floating-point scalars are passed in
3283 floating-point registers. We also handle vector floats the same
3284 say, which is OK because they are not covered by the standard ABI. */
3285 info->fpr_p = (!cum->gp_reg_found
3286 && cum->arg_number < 2
3287 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3288 || VECTOR_FLOAT_TYPE_P (type))
3289 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3290 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3291 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3296 /* Scalar and complex floating-point types are passed in
3297 floating-point registers. */
3298 info->fpr_p = (named
3299 && (type == 0 || FLOAT_TYPE_P (type))
3300 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3301 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3302 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3303 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3305 /* ??? According to the ABI documentation, the real and imaginary
3306 parts of complex floats should be passed in individual registers.
3307 The real and imaginary parts of stack arguments are supposed
3308 to be contiguous and there should be an extra word of padding
3311 This has two problems. First, it makes it impossible to use a
3312 single "void *" va_list type, since register and stack arguments
3313 are passed differently. (At the time of writing, MIPSpro cannot
3314 handle complex float varargs correctly.) Second, it's unclear
3315 what should happen when there is only one register free.
3317 For now, we assume that named complex floats should go into FPRs
3318 if there are two FPRs free, otherwise they should be passed in the
3319 same way as a struct containing two floats. */
3321 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3322 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3324 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3325 info->fpr_p = false;
3335 /* See whether the argument has doubleword alignment. */
3336 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3338 /* Set REG_OFFSET to the register count we're interested in.
3339 The EABI allocates the floating-point registers separately,
3340 but the other ABIs allocate them like integer registers. */
3341 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3345 /* Advance to an even register if the argument is doubleword-aligned. */
3346 if (doubleword_aligned_p)
3347 info->reg_offset += info->reg_offset & 1;
3349 /* Work out the offset of a stack argument. */
3350 info->stack_offset = cum->stack_words;
3351 if (doubleword_aligned_p)
3352 info->stack_offset += info->stack_offset & 1;
3354 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3356 /* Partition the argument between registers and stack. */
3357 info->reg_words = MIN (num_words, max_regs);
3358 info->stack_words = num_words - info->reg_words;
3362 /* Implement FUNCTION_ARG_ADVANCE. */
3365 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3366 tree type, int named)
3368 struct mips_arg_info info;
3370 mips_arg_info (cum, mode, type, named, &info);
3373 cum->gp_reg_found = true;
3375 /* See the comment above the cumulative args structure in mips.h
3376 for an explanation of what this code does. It assumes the O32
3377 ABI, which passes at most 2 arguments in float registers. */
3378 if (cum->arg_number < 2 && info.fpr_p)
3379 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3381 if (mips_abi != ABI_EABI || !info.fpr_p)
3382 cum->num_gprs = info.reg_offset + info.reg_words;
3383 else if (info.reg_words > 0)
3384 cum->num_fprs += FP_INC;
3386 if (info.stack_words > 0)
3387 cum->stack_words = info.stack_offset + info.stack_words;
3392 /* Implement FUNCTION_ARG. */
3395 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3396 tree type, int named)
3398 struct mips_arg_info info;
3400 /* We will be called with a mode of VOIDmode after the last argument
3401 has been seen. Whatever we return will be passed to the call
3402 insn. If we need a mips16 fp_code, return a REG with the code
3403 stored as the mode. */
3404 if (mode == VOIDmode)
3406 if (TARGET_MIPS16 && cum->fp_code != 0)
3407 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3413 mips_arg_info (cum, mode, type, named, &info);
3415 /* Return straight away if the whole argument is passed on the stack. */
3416 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3420 && TREE_CODE (type) == RECORD_TYPE
3422 && TYPE_SIZE_UNIT (type)
3423 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3426 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3427 structure contains a double in its entirety, then that 64 bit
3428 chunk is passed in a floating point register. */
3431 /* First check to see if there is any such field. */
3432 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3433 if (TREE_CODE (field) == FIELD_DECL
3434 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3435 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3436 && host_integerp (bit_position (field), 0)
3437 && int_bit_position (field) % BITS_PER_WORD == 0)
3442 /* Now handle the special case by returning a PARALLEL
3443 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3444 chunks are passed in registers. */
3446 HOST_WIDE_INT bitpos;
3449 /* assign_parms checks the mode of ENTRY_PARM, so we must
3450 use the actual mode here. */
3451 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3454 field = TYPE_FIELDS (type);
3455 for (i = 0; i < info.reg_words; i++)
3459 for (; field; field = TREE_CHAIN (field))
3460 if (TREE_CODE (field) == FIELD_DECL
3461 && int_bit_position (field) >= bitpos)
3465 && int_bit_position (field) == bitpos
3466 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3467 && !TARGET_SOFT_FLOAT
3468 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3469 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3471 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3474 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3475 GEN_INT (bitpos / BITS_PER_UNIT));
3477 bitpos += BITS_PER_WORD;
3483 /* Handle the n32/n64 conventions for passing complex floating-point
3484 arguments in FPR pairs. The real part goes in the lower register
3485 and the imaginary part goes in the upper register. */
3488 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3491 enum machine_mode inner;
3494 inner = GET_MODE_INNER (mode);
3495 reg = FP_ARG_FIRST + info.reg_offset;
3496 real = gen_rtx_EXPR_LIST (VOIDmode,
3497 gen_rtx_REG (inner, reg),
3499 imag = gen_rtx_EXPR_LIST (VOIDmode,
3500 gen_rtx_REG (inner, reg + info.reg_words / 2),
3501 GEN_INT (GET_MODE_SIZE (inner)));
3502 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3506 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3507 else if (info.reg_offset == 1)
3508 /* This code handles the special o32 case in which the second word
3509 of the argument structure is passed in floating-point registers. */
3510 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3512 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3516 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3519 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3520 enum machine_mode mode, tree type, bool named)
3522 struct mips_arg_info info;
3524 mips_arg_info (cum, mode, type, named, &info);
3525 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3529 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3530 PARM_BOUNDARY bits of alignment, but will be given anything up
3531 to STACK_BOUNDARY bits if the type requires it. */
3534 function_arg_boundary (enum machine_mode mode, tree type)
3536 unsigned int alignment;
3538 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3539 if (alignment < PARM_BOUNDARY)
3540 alignment = PARM_BOUNDARY;
3541 if (alignment > STACK_BOUNDARY)
3542 alignment = STACK_BOUNDARY;
3546 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3547 upward rather than downward. In other words, return true if the
3548 first byte of the stack slot has useful data, false if the last
3552 mips_pad_arg_upward (enum machine_mode mode, tree type)
3554 /* On little-endian targets, the first byte of every stack argument
3555 is passed in the first byte of the stack slot. */
3556 if (!BYTES_BIG_ENDIAN)
3559 /* Otherwise, integral types are padded downward: the last byte of a
3560 stack argument is passed in the last byte of the stack slot. */
3562 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3563 : GET_MODE_CLASS (mode) == MODE_INT)
3566 /* Big-endian o64 pads floating-point arguments downward. */
3567 if (mips_abi == ABI_O64)
3568 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3571 /* Other types are padded upward for o32, o64, n32 and n64. */
3572 if (mips_abi != ABI_EABI)
3575 /* Arguments smaller than a stack slot are padded downward. */
3576 if (mode != BLKmode)
3577 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3579 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3583 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3584 if the least significant byte of the register has useful data. Return
3585 the opposite if the most significant byte does. */
3588 mips_pad_reg_upward (enum machine_mode mode, tree type)
3590 /* No shifting is required for floating-point arguments. */
3591 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3592 return !BYTES_BIG_ENDIAN;
3594 /* Otherwise, apply the same padding to register arguments as we do
3595 to stack arguments. */
3596 return mips_pad_arg_upward (mode, type);
3600 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3601 tree type, int *pretend_size, int no_rtl)
3603 CUMULATIVE_ARGS local_cum;
3604 int gp_saved, fp_saved;
3606 /* The caller has advanced CUM up to, but not beyond, the last named
3607 argument. Advance a local copy of CUM past the last "real" named
3608 argument, to find out how many registers are left over. */
3611 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3613 /* Found out how many registers we need to save. */
3614 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3615 fp_saved = (EABI_FLOAT_VARARGS_P
3616 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3625 ptr = virtual_incoming_args_rtx;
3630 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3634 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3637 mem = gen_rtx_MEM (BLKmode, ptr);
3638 set_mem_alias_set (mem, get_varargs_alias_set ());
3640 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3645 /* We can't use move_block_from_reg, because it will use
3647 enum machine_mode mode;
3650 /* Set OFF to the offset from virtual_incoming_args_rtx of
3651 the first float register. The FP save area lies below
3652 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3653 off = -gp_saved * UNITS_PER_WORD;
3654 off &= ~(UNITS_PER_FPVALUE - 1);
3655 off -= fp_saved * UNITS_PER_FPREG;
3657 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3659 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3663 ptr = plus_constant (virtual_incoming_args_rtx, off);
3664 mem = gen_rtx_MEM (mode, ptr);
3665 set_mem_alias_set (mem, get_varargs_alias_set ());
3666 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3667 off += UNITS_PER_HWFPVALUE;
3673 /* No need for pretend arguments: the register parameter area was
3674 allocated by the caller. */
3678 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3681 /* Create the va_list data type.
3682 We keep 3 pointers, and two offsets.
3683 Two pointers are to the overflow area, which starts at the CFA.
3684 One of these is constant, for addressing into the GPR save area below it.
3685 The other is advanced up the stack through the overflow region.
3686 The third pointer is to the GPR save area. Since the FPR save area
3687 is just below it, we can address FPR slots off this pointer.
3688 We also keep two one-byte offsets, which are to be subtracted from the
3689 constant pointers to yield addresses in the GPR and FPR save areas.
3690 These are downcounted as float or non-float arguments are used,
3691 and when they get to zero, the argument must be obtained from the
3693 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3694 pointer is enough. It's started at the GPR save area, and is
3696 Note that the GPR save area is not constant size, due to optimization
3697 in the prologue. Hence, we can't use a design with two pointers
3698 and two offsets, although we could have designed this with two pointers
3699 and three offsets. */
3702 mips_build_builtin_va_list (void)
3704 if (EABI_FLOAT_VARARGS_P)
3706 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3709 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3711 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3713 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3715 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3717 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3718 unsigned_char_type_node);
3719 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3720 unsigned_char_type_node);
3721 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3722 warn on every user file. */
3723 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
3724 array = build_array_type (unsigned_char_type_node,
3725 build_index_type (index));
3726 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3728 DECL_FIELD_CONTEXT (f_ovfl) = record;
3729 DECL_FIELD_CONTEXT (f_gtop) = record;
3730 DECL_FIELD_CONTEXT (f_ftop) = record;
3731 DECL_FIELD_CONTEXT (f_goff) = record;
3732 DECL_FIELD_CONTEXT (f_foff) = record;
3733 DECL_FIELD_CONTEXT (f_res) = record;
3735 TYPE_FIELDS (record) = f_ovfl;
3736 TREE_CHAIN (f_ovfl) = f_gtop;
3737 TREE_CHAIN (f_gtop) = f_ftop;
3738 TREE_CHAIN (f_ftop) = f_goff;
3739 TREE_CHAIN (f_goff) = f_foff;
3740 TREE_CHAIN (f_foff) = f_res;
3742 layout_type (record);
3745 else if (TARGET_IRIX && TARGET_IRIX6)
3746 /* On IRIX 6, this type is 'char *'. */
3747 return build_pointer_type (char_type_node);
3749 /* Otherwise, we use 'void *'. */
3750 return ptr_type_node;
3753 /* Implement va_start. */
3756 mips_va_start (tree valist, rtx nextarg)
3758 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
3760 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
3761 since the stack is aligned for a pair of argument-passing slots,
3762 and the beginning of a variable argument list may be an odd slot,
3763 we have to decrease its alignment. */
3764 if (cfun && cfun->emit->regno_pointer_align)
3765 while (((current_function_pretend_args_size * BITS_PER_UNIT)
3766 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
3767 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
3769 if (mips_abi == ABI_EABI)
3771 int gpr_save_area_size;
3774 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
3776 if (EABI_FLOAT_VARARGS_P)
3778 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3779 tree ovfl, gtop, ftop, goff, foff;
3782 int fpr_save_area_size;
3784 f_ovfl = TYPE_FIELDS (va_list_type_node);
3785 f_gtop = TREE_CHAIN (f_ovfl);
3786 f_ftop = TREE_CHAIN (f_gtop);
3787 f_goff = TREE_CHAIN (f_ftop);
3788 f_foff = TREE_CHAIN (f_goff);
3790 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3792 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3794 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3796 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3798 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3801 /* Emit code to initialize OVFL, which points to the next varargs
3802 stack argument. CUM->STACK_WORDS gives the number of stack
3803 words used by named arguments. */
3804 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
3805 if (cum->stack_words > 0)
3806 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
3807 build_int_cst (NULL_TREE,
3808 cum->stack_words * UNITS_PER_WORD));
3809 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
3810 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3812 /* Emit code to initialize GTOP, the top of the GPR save area. */
3813 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
3814 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
3815 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3817 /* Emit code to initialize FTOP, the top of the FPR save area.
3818 This address is gpr_save_area_bytes below GTOP, rounded
3819 down to the next fp-aligned boundary. */
3820 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
3821 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
3822 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
3824 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
3825 build_int_cst (NULL_TREE, -fpr_offset));
3826 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
3827 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3829 /* Emit code to initialize GOFF, the offset from GTOP of the
3830 next GPR argument. */
3831 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
3832 build_int_cst (NULL_TREE, gpr_save_area_size));
3833 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3835 /* Likewise emit code to initialize FOFF, the offset from FTOP
3836 of the next FPR argument. */
3838 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
3839 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
3840 build_int_cst (NULL_TREE, fpr_save_area_size));
3841 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3845 /* Everything is in the GPR save area, or in the overflow
3846 area which is contiguous with it. */
3847 nextarg = plus_constant (nextarg, -gpr_save_area_size);
3848 std_expand_builtin_va_start (valist, nextarg);
3852 std_expand_builtin_va_start (valist, nextarg);
3855 /* Implement va_arg. */
3858 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
3860 HOST_WIDE_INT size, rsize;
3864 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
3867 type = build_pointer_type (type);
3869 size = int_size_in_bytes (type);
3870 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
3872 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
3873 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
3876 /* Not a simple merged stack. */
3878 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3879 tree ovfl, top, off, align;
3880 HOST_WIDE_INT osize;
3883 f_ovfl = TYPE_FIELDS (va_list_type_node);
3884 f_gtop = TREE_CHAIN (f_ovfl);
3885 f_ftop = TREE_CHAIN (f_gtop);
3886 f_goff = TREE_CHAIN (f_ftop);
3887 f_foff = TREE_CHAIN (f_goff);
3889 /* We maintain separate pointers and offsets for floating-point
3890 and integer arguments, but we need similar code in both cases.
3893 TOP be the top of the register save area;
3894 OFF be the offset from TOP of the next register;
3895 ADDR_RTX be the address of the argument;
3896 RSIZE be the number of bytes used to store the argument
3897 when it's in the register save area;
3898 OSIZE be the number of bytes used to store it when it's
3899 in the stack overflow area; and
3900 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
3902 The code we want is:
3904 1: off &= -rsize; // round down
3907 4: addr_rtx = top - off;
3912 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
3913 10: addr_rtx = ovfl + PADDING;
3917 [1] and [9] can sometimes be optimized away. */
3919 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3922 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
3923 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
3925 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3927 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3930 /* When floating-point registers are saved to the stack,
3931 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
3932 of the float's precision. */
3933 rsize = UNITS_PER_HWFPVALUE;
3935 /* Overflow arguments are padded to UNITS_PER_WORD bytes
3936 (= PARM_BOUNDARY bits). This can be different from RSIZE
3939 (1) On 32-bit targets when TYPE is a structure such as:
3941 struct s { float f; };
3943 Such structures are passed in paired FPRs, so RSIZE
3944 will be 8 bytes. However, the structure only takes
3945 up 4 bytes of memory, so OSIZE will only be 4.
3947 (2) In combinations such as -mgp64 -msingle-float
3948 -fshort-double. Doubles passed in registers
3949 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
3950 but those passed on the stack take up
3951 UNITS_PER_WORD bytes. */
3952 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
3956 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3958 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3960 if (rsize > UNITS_PER_WORD)
3962 /* [1] Emit code for: off &= -rsize. */
3963 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
3964 build_int_cst (NULL_TREE, -rsize));
3965 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
3966 gimplify_and_add (t, pre_p);
3971 /* [2] Emit code to branch if off == 0. */
3972 t = build (NE_EXPR, boolean_type_node, off,
3973 build_int_cst (TREE_TYPE (off), 0));
3974 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
3976 /* [5] Emit code for: off -= rsize. We do this as a form of
3977 post-increment not available to C. Also widen for the
3978 coming pointer arithmetic. */
3979 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
3980 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
3981 t = fold_convert (sizetype, t);
3982 t = fold_convert (TREE_TYPE (top), t);
3984 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
3985 the argument has RSIZE - SIZE bytes of leading padding. */
3986 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
3987 if (BYTES_BIG_ENDIAN && rsize > size)
3989 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
3991 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
3993 COND_EXPR_THEN (addr) = t;
3995 if (osize > UNITS_PER_WORD)
3997 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
3998 u = fold_convert (TREE_TYPE (ovfl),
3999 build_int_cst (NULL_TREE, osize - 1));
4000 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4001 u = fold_convert (TREE_TYPE (ovfl),
4002 build_int_cst (NULL_TREE, -osize));
4003 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4004 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4009 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4010 post-increment ovfl by osize. On big-endian machines,
4011 the argument has OSIZE - SIZE bytes of leading padding. */
4012 u = fold_convert (TREE_TYPE (ovfl),
4013 build_int_cst (NULL_TREE, osize));
4014 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4015 if (BYTES_BIG_ENDIAN && osize > size)
4017 u = fold_convert (TREE_TYPE (t),
4018 build_int_cst (NULL_TREE, osize - size));
4019 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4022 /* String [9] and [10,11] together. */
4024 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4025 COND_EXPR_ELSE (addr) = t;
4027 addr = fold_convert (build_pointer_type (type), addr);
4028 addr = build_fold_indirect_ref (addr);
4032 addr = build_fold_indirect_ref (addr);
4037 /* Return true if it is possible to use left/right accesses for a
4038 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4039 returning true, update *OP, *LEFT and *RIGHT as follows:
4041 *OP is a BLKmode reference to the whole field.
4043 *LEFT is a QImode reference to the first byte if big endian or
4044 the last byte if little endian. This address can be used in the
4045 left-side instructions (lwl, swl, ldl, sdl).
4047 *RIGHT is a QImode reference to the opposite end of the field and
4048 can be used in the parterning right-side instruction. */
4051 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4052 rtx *left, rtx *right)
4056 /* Check that the operand really is a MEM. Not all the extv and
4057 extzv predicates are checked. */
4061 /* Check that the size is valid. */
4062 if (width != 32 && (!TARGET_64BIT || width != 64))
4065 /* We can only access byte-aligned values. Since we are always passed
4066 a reference to the first byte of the field, it is not necessary to
4067 do anything with BITPOS after this check. */
4068 if (bitpos % BITS_PER_UNIT != 0)
4071 /* Reject aligned bitfields: we want to use a normal load or store
4072 instead of a left/right pair. */
4073 if (MEM_ALIGN (*op) >= width)
4076 /* Adjust *OP to refer to the whole field. This also has the effect
4077 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4078 *op = adjust_address (*op, BLKmode, 0);
4079 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4081 /* Get references to both ends of the field. We deliberately don't
4082 use the original QImode *OP for FIRST since the new BLKmode one
4083 might have a simpler address. */
4084 first = adjust_address (*op, QImode, 0);
4085 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4087 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4088 be the upper word and RIGHT the lower word. */
4089 if (TARGET_BIG_ENDIAN)
4090 *left = first, *right = last;
4092 *left = last, *right = first;
4098 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4099 Return true on success. We only handle cases where zero_extract is
4100 equivalent to sign_extract. */
4103 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4105 rtx left, right, temp;
4107 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4108 paradoxical word_mode subreg. This is the only case in which
4109 we allow the destination to be larger than the source. */
4110 if (GET_CODE (dest) == SUBREG
4111 && GET_MODE (dest) == DImode
4112 && SUBREG_BYTE (dest) == 0
4113 && GET_MODE (SUBREG_REG (dest)) == SImode)
4114 dest = SUBREG_REG (dest);
4116 /* After the above adjustment, the destination must be the same
4117 width as the source. */
4118 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4121 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4124 temp = gen_reg_rtx (GET_MODE (dest));
4125 if (GET_MODE (dest) == DImode)
4127 emit_insn (gen_mov_ldl (temp, src, left));
4128 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4132 emit_insn (gen_mov_lwl (temp, src, left));
4133 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4139 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4143 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4147 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4150 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4152 if (GET_MODE (src) == DImode)
4154 emit_insn (gen_mov_sdl (dest, src, left));
4155 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4159 emit_insn (gen_mov_swl (dest, src, left));
4160 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4165 /* Set up globals to generate code for the ISA or processor
4166 described by INFO. */
4169 mips_set_architecture (const struct mips_cpu_info *info)
4173 mips_arch_info = info;
4174 mips_arch = info->cpu;
4175 mips_isa = info->isa;
4180 /* Likewise for tuning. */
4183 mips_set_tune (const struct mips_cpu_info *info)
4187 mips_tune_info = info;
4188 mips_tune = info->cpu;
4192 /* Implement TARGET_HANDLE_OPTION. */
4195 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4200 if (strcmp (arg, "32") == 0)
4202 else if (strcmp (arg, "o64") == 0)
4204 else if (strcmp (arg, "n32") == 0)
4206 else if (strcmp (arg, "64") == 0)
4208 else if (strcmp (arg, "eabi") == 0)
4209 mips_abi = ABI_EABI;
4215 mips_arch_string = arg;
4216 return mips_parse_cpu (arg) != 0;
4219 mips_tune_string = arg;
4220 return mips_parse_cpu (arg) != 0;
4223 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4224 return mips_isa_info != 0;
4226 case OPT_mflush_func_:
4227 mips_cache_flush_func = arg;
4230 case OPT_mno_flush_func:
4231 mips_cache_flush_func = NULL;
4239 /* Set up the threshold for data to go into the small data area, instead
4240 of the normal data area, and detect any conflicts in the switches. */
4243 override_options (void)
4245 int i, start, regno;
4246 enum machine_mode mode;
4248 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4250 /* The following code determines the architecture and register size.
4251 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4252 The GAS and GCC code should be kept in sync as much as possible. */
4254 if (mips_arch_string != 0)
4255 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4257 if (mips_isa_info != 0)
4259 if (mips_arch_info == 0)
4260 mips_set_architecture (mips_isa_info);
4261 else if (mips_arch_info->isa != mips_isa_info->isa)
4262 error ("-%s conflicts with the other architecture options, "
4263 "which specify a %s processor",
4264 mips_isa_info->name,
4265 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4268 if (mips_arch_info == 0)
4270 #ifdef MIPS_CPU_STRING_DEFAULT
4271 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4273 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4277 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4278 error ("-march=%s is not compatible with the selected ABI",
4279 mips_arch_info->name);
4281 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4282 if (mips_tune_string != 0)
4283 mips_set_tune (mips_parse_cpu (mips_tune_string));
4285 if (mips_tune_info == 0)
4286 mips_set_tune (mips_arch_info);
4288 if ((target_flags_explicit & MASK_64BIT) != 0)
4290 /* The user specified the size of the integer registers. Make sure
4291 it agrees with the ABI and ISA. */
4292 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4293 error ("-mgp64 used with a 32-bit processor");
4294 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4295 error ("-mgp32 used with a 64-bit ABI");
4296 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4297 error ("-mgp64 used with a 32-bit ABI");
4301 /* Infer the integer register size from the ABI and processor.
4302 Restrict ourselves to 32-bit registers if that's all the
4303 processor has, or if the ABI cannot handle 64-bit registers. */
4304 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4305 target_flags &= ~MASK_64BIT;
4307 target_flags |= MASK_64BIT;
4310 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4312 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4313 only one right answer here. */
4314 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4315 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4316 else if (!TARGET_64BIT && TARGET_FLOAT64)
4317 error ("unsupported combination: %s", "-mgp32 -mfp64");
4318 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4319 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4323 /* -msingle-float selects 32-bit float registers. Otherwise the
4324 float registers should be the same size as the integer ones. */
4325 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4326 target_flags |= MASK_FLOAT64;
4328 target_flags &= ~MASK_FLOAT64;
4331 /* End of code shared with GAS. */
4333 if ((target_flags_explicit & MASK_LONG64) == 0)
4335 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4336 target_flags |= MASK_LONG64;
4338 target_flags &= ~MASK_LONG64;
4341 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4342 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4344 /* For some configurations, it is useful to have -march control
4345 the default setting of MASK_SOFT_FLOAT. */
4346 switch ((int) mips_arch)
4348 case PROCESSOR_R4100:
4349 case PROCESSOR_R4111:
4350 case PROCESSOR_R4120:
4351 case PROCESSOR_R4130:
4352 target_flags |= MASK_SOFT_FLOAT;
4356 target_flags &= ~MASK_SOFT_FLOAT;
4362 flag_pcc_struct_return = 0;
4364 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4366 /* If neither -mbranch-likely nor -mno-branch-likely was given
4367 on the command line, set MASK_BRANCHLIKELY based on the target
4370 By default, we enable use of Branch Likely instructions on
4371 all architectures which support them with the following
4372 exceptions: when creating MIPS32 or MIPS64 code, and when
4373 tuning for architectures where their use tends to hurt
4376 The MIPS32 and MIPS64 architecture specifications say "Software
4377 is strongly encouraged to avoid use of Branch Likely
4378 instructions, as they will be removed from a future revision
4379 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4380 issue those instructions unless instructed to do so by
4382 if (ISA_HAS_BRANCHLIKELY
4383 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4384 && !(TUNE_MIPS5500 || TUNE_SB1))
4385 target_flags |= MASK_BRANCHLIKELY;
4387 target_flags &= ~MASK_BRANCHLIKELY;
4389 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4390 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4392 /* The effect of -mabicalls isn't defined for the EABI. */
4393 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4395 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4396 target_flags &= ~MASK_ABICALLS;
4399 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4400 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4401 /* ??? -non_shared turns off pic code generation, but this is not
4403 if (TARGET_ABICALLS)
4406 if (mips_section_threshold > 0)
4407 warning (0, "-G is incompatible with PIC code which is the default");
4410 /* mips_split_addresses is a half-way house between explicit
4411 relocations and the traditional assembler macros. It can
4412 split absolute 32-bit symbolic constants into a high/lo_sum
4413 pair but uses macros for other sorts of access.
4415 Like explicit relocation support for REL targets, it relies
4416 on GNU extensions in the assembler and the linker.
4418 Although this code should work for -O0, it has traditionally
4419 been treated as an optimization. */
4420 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4421 && optimize && !flag_pic
4422 && !ABI_HAS_64BIT_SYMBOLS)
4423 mips_split_addresses = 1;
4425 mips_split_addresses = 0;
4427 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4428 faster code, but at the expense of more nops. Enable it at -O3 and
4430 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4431 target_flags |= MASK_VR4130_ALIGN;
4433 /* When compiling for the mips16, we cannot use floating point. We
4434 record the original hard float value in mips16_hard_float. */
4437 if (TARGET_SOFT_FLOAT)
4438 mips16_hard_float = 0;
4440 mips16_hard_float = 1;
4441 target_flags |= MASK_SOFT_FLOAT;
4443 /* Don't run the scheduler before reload, since it tends to
4444 increase register pressure. */
4445 flag_schedule_insns = 0;
4447 /* Don't do hot/cold partitioning. The constant layout code expects
4448 the whole function to be in a single section. */
4449 flag_reorder_blocks_and_partition = 0;
4451 /* Silently disable -mexplicit-relocs since it doesn't apply
4452 to mips16 code. Even so, it would overly pedantic to warn
4453 about "-mips16 -mexplicit-relocs", especially given that
4454 we use a %gprel() operator. */
4455 target_flags &= ~MASK_EXPLICIT_RELOCS;
4458 /* When using explicit relocs, we call dbr_schedule from within
4460 if (TARGET_EXPLICIT_RELOCS)
4462 mips_flag_delayed_branch = flag_delayed_branch;
4463 flag_delayed_branch = 0;
4466 #ifdef MIPS_TFMODE_FORMAT
4467 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4470 /* Make sure that the user didn't turn off paired single support when
4471 MIPS-3D support is requested. */
4472 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4473 && !TARGET_PAIRED_SINGLE_FLOAT)
4474 error ("-mips3d requires -mpaired-single");
4476 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4478 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4480 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4481 and TARGET_HARD_FLOAT are both true. */
4482 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4483 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4485 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4487 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4488 error ("-mips3d/-mpaired-single must be used with -mips64");
4490 mips_print_operand_punct['?'] = 1;
4491 mips_print_operand_punct['#'] = 1;
4492 mips_print_operand_punct['/'] = 1;
4493 mips_print_operand_punct['&'] = 1;
4494 mips_print_operand_punct['!'] = 1;
4495 mips_print_operand_punct['*'] = 1;
4496 mips_print_operand_punct['@'] = 1;
4497 mips_print_operand_punct['.'] = 1;
4498 mips_print_operand_punct['('] = 1;
4499 mips_print_operand_punct[')'] = 1;
4500 mips_print_operand_punct['['] = 1;
4501 mips_print_operand_punct[']'] = 1;
4502 mips_print_operand_punct['<'] = 1;
4503 mips_print_operand_punct['>'] = 1;
4504 mips_print_operand_punct['{'] = 1;
4505 mips_print_operand_punct['}'] = 1;
4506 mips_print_operand_punct['^'] = 1;
4507 mips_print_operand_punct['$'] = 1;
4508 mips_print_operand_punct['+'] = 1;
4509 mips_print_operand_punct['~'] = 1;
4511 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4512 mips_char_to_class['t'] = T_REG;
4513 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4514 mips_char_to_class['h'] = HI_REG;
4515 mips_char_to_class['l'] = LO_REG;
4516 mips_char_to_class['x'] = MD_REGS;
4517 mips_char_to_class['b'] = ALL_REGS;
4518 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4519 TARGET_MIPS16 ? M16_NA_REGS :
4521 mips_char_to_class['e'] = LEA_REGS;
4522 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4523 mips_char_to_class['v'] = V1_REG;
4524 mips_char_to_class['y'] = GR_REGS;
4525 mips_char_to_class['z'] = ST_REGS;
4526 mips_char_to_class['B'] = COP0_REGS;
4527 mips_char_to_class['C'] = COP2_REGS;
4528 mips_char_to_class['D'] = COP3_REGS;
4530 /* Set up array to map GCC register number to debug register number.
4531 Ignore the special purpose register numbers. */
4533 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4534 mips_dbx_regno[i] = -1;
4536 start = GP_DBX_FIRST - GP_REG_FIRST;
4537 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4538 mips_dbx_regno[i] = i + start;
4540 start = FP_DBX_FIRST - FP_REG_FIRST;
4541 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4542 mips_dbx_regno[i] = i + start;
4544 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4545 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4547 /* Set up array giving whether a given register can hold a given mode. */
4549 for (mode = VOIDmode;
4550 mode != MAX_MACHINE_MODE;
4551 mode = (enum machine_mode) ((int)mode + 1))
4553 register int size = GET_MODE_SIZE (mode);
4554 register enum mode_class class = GET_MODE_CLASS (mode);
4556 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4560 if (mode == CCV2mode)
4563 && (regno - ST_REG_FIRST) % 2 == 0);
4565 else if (mode == CCV4mode)
4568 && (regno - ST_REG_FIRST) % 4 == 0);
4570 else if (mode == CCmode)
4573 temp = (regno == FPSW_REGNUM);
4575 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4576 || FP_REG_P (regno));
4579 else if (GP_REG_P (regno))
4580 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4582 else if (FP_REG_P (regno))
4583 temp = ((regno % FP_INC) == 0)
4584 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4585 || class == MODE_VECTOR_FLOAT)
4586 && size <= UNITS_PER_FPVALUE)
4587 /* Allow integer modes that fit into a single
4588 register. We need to put integers into FPRs
4589 when using instructions like cvt and trunc. */
4590 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4591 /* Allow TFmode for CCmode reloads. */
4592 || (ISA_HAS_8CC && mode == TFmode));
4594 else if (MD_REG_P (regno))
4595 temp = (INTEGRAL_MODE_P (mode)
4596 && (size <= UNITS_PER_WORD
4597 || (regno == MD_REG_FIRST
4598 && size == 2 * UNITS_PER_WORD)));
4600 else if (ALL_COP_REG_P (regno))
4601 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4605 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4609 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4610 initialized yet, so we can't use that here. */
4611 gpr_mode = TARGET_64BIT ? DImode : SImode;
4613 /* Provide default values for align_* for 64-bit targets. */
4614 if (TARGET_64BIT && !TARGET_MIPS16)
4616 if (align_loops == 0)
4618 if (align_jumps == 0)
4620 if (align_functions == 0)
4621 align_functions = 8;
4624 /* Function to allocate machine-dependent function status. */
4625 init_machine_status = &mips_init_machine_status;
4627 if (ABI_HAS_64BIT_SYMBOLS)
4629 if (TARGET_EXPLICIT_RELOCS)
4631 mips_split_p[SYMBOL_64_HIGH] = true;
4632 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4633 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4635 mips_split_p[SYMBOL_64_MID] = true;
4636 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4637 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4639 mips_split_p[SYMBOL_64_LOW] = true;
4640 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4641 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4643 mips_split_p[SYMBOL_GENERAL] = true;
4644 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4649 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4651 mips_split_p[SYMBOL_GENERAL] = true;
4652 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4653 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4659 /* The high part is provided by a pseudo copy of $gp. */
4660 mips_split_p[SYMBOL_SMALL_DATA] = true;
4661 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4664 if (TARGET_EXPLICIT_RELOCS)
4666 /* Small data constants are kept whole until after reload,
4667 then lowered by mips_rewrite_small_data. */
4668 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
4670 mips_split_p[SYMBOL_GOT_LOCAL] = true;
4673 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
4674 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
4678 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
4679 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
4684 /* The HIGH and LO_SUM are matched by special .md patterns. */
4685 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
4687 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
4688 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
4689 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
4691 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
4692 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
4693 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
4698 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
4700 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
4701 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
4707 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
4708 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
4709 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
4712 /* Thread-local relocation operators. */
4713 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
4714 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
4715 mips_split_p[SYMBOL_DTPREL] = 1;
4716 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
4717 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
4718 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
4719 mips_split_p[SYMBOL_TPREL] = 1;
4720 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
4721 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
4723 /* We don't have a thread pointer access instruction on MIPS16, or
4724 appropriate TLS relocations. */
4726 targetm.have_tls = false;
4728 /* Default to working around R4000 errata only if the processor
4729 was selected explicitly. */
4730 if ((target_flags_explicit & MASK_FIX_R4000) == 0
4731 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
4732 target_flags |= MASK_FIX_R4000;
4734 /* Default to working around R4400 errata only if the processor
4735 was selected explicitly. */
4736 if ((target_flags_explicit & MASK_FIX_R4400) == 0
4737 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
4738 target_flags |= MASK_FIX_R4400;
4741 /* Implement CONDITIONAL_REGISTER_USAGE. */
4744 mips_conditional_register_usage (void)
4746 if (!TARGET_HARD_FLOAT)
4750 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4751 fixed_regs[regno] = call_used_regs[regno] = 1;
4752 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4753 fixed_regs[regno] = call_used_regs[regno] = 1;
4755 else if (! ISA_HAS_8CC)
4759 /* We only have a single condition code register. We
4760 implement this by hiding all the condition code registers,
4761 and generating RTL that refers directly to ST_REG_FIRST. */
4762 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4763 fixed_regs[regno] = call_used_regs[regno] = 1;
4765 /* In mips16 mode, we permit the $t temporary registers to be used
4766 for reload. We prohibit the unused $s registers, since they
4767 are caller saved, and saving them via a mips16 register would
4768 probably waste more time than just reloading the value. */
4771 fixed_regs[18] = call_used_regs[18] = 1;
4772 fixed_regs[19] = call_used_regs[19] = 1;
4773 fixed_regs[20] = call_used_regs[20] = 1;
4774 fixed_regs[21] = call_used_regs[21] = 1;
4775 fixed_regs[22] = call_used_regs[22] = 1;
4776 fixed_regs[23] = call_used_regs[23] = 1;
4777 fixed_regs[26] = call_used_regs[26] = 1;
4778 fixed_regs[27] = call_used_regs[27] = 1;
4779 fixed_regs[30] = call_used_regs[30] = 1;
4781 /* fp20-23 are now caller saved. */
4782 if (mips_abi == ABI_64)
4785 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
4786 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4788 /* Odd registers from fp21 to fp31 are now caller saved. */
4789 if (mips_abi == ABI_N32)
4792 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
4793 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4797 /* Allocate a chunk of memory for per-function machine-dependent data. */
4798 static struct machine_function *
4799 mips_init_machine_status (void)
4801 return ((struct machine_function *)
4802 ggc_alloc_cleared (sizeof (struct machine_function)));
4805 /* On the mips16, we want to allocate $24 (T_REG) before other
4806 registers for instructions for which it is possible. This helps
4807 avoid shuffling registers around in order to set up for an xor,
4808 encouraging the compiler to use a cmp instead. */
4811 mips_order_regs_for_local_alloc (void)
4815 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4816 reg_alloc_order[i] = i;
4820 /* It really doesn't matter where we put register 0, since it is
4821 a fixed register anyhow. */
4822 reg_alloc_order[0] = 24;
4823 reg_alloc_order[24] = 0;
4828 /* The MIPS debug format wants all automatic variables and arguments
4829 to be in terms of the virtual frame pointer (stack pointer before
4830 any adjustment in the function), while the MIPS 3.0 linker wants
4831 the frame pointer to be the stack pointer after the initial
4832 adjustment. So, we do the adjustment here. The arg pointer (which
4833 is eliminated) points to the virtual frame pointer, while the frame
4834 pointer (which may be eliminated) points to the stack pointer after
4835 the initial adjustments. */
4838 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
4840 rtx offset2 = const0_rtx;
4841 rtx reg = eliminate_constant_term (addr, &offset2);
4844 offset = INTVAL (offset2);
4846 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4847 || reg == hard_frame_pointer_rtx)
4849 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
4850 ? compute_frame_size (get_frame_size ())
4851 : cfun->machine->frame.total_size;
4853 /* MIPS16 frame is smaller */
4854 if (frame_pointer_needed && TARGET_MIPS16)
4855 frame_size -= cfun->machine->frame.args_size;
4857 offset = offset - frame_size;
4860 /* sdbout_parms does not want this to crash for unrecognized cases. */
4862 else if (reg != arg_pointer_rtx)
4863 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
4870 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
4872 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4873 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4874 'h' OP is HIGH, prints %hi(X),
4875 'd' output integer constant in decimal,
4876 'z' if the operand is 0, use $0 instead of normal operand.
4877 'D' print second part of double-word register or memory operand.
4878 'L' print low-order register of double-word register operand.
4879 'M' print high-order register of double-word register operand.
4880 'C' print part of opcode for a branch condition.
4881 'F' print part of opcode for a floating-point branch condition.
4882 'N' print part of opcode for a branch condition, inverted.
4883 'W' print part of opcode for a floating-point branch condition, inverted.
4884 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
4885 'z' for (eq:?I ...), 'n' for (ne:?I ...).
4886 't' like 'T', but with the EQ/NE cases reversed
4887 'Y' for a CONST_INT X, print mips_fp_conditions[X]
4888 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
4889 'R' print the reloc associated with LO_SUM
4891 The punctuation characters are:
4893 '(' Turn on .set noreorder
4894 ')' Turn on .set reorder
4895 '[' Turn on .set noat
4897 '<' Turn on .set nomacro
4898 '>' Turn on .set macro
4899 '{' Turn on .set volatile (not GAS)
4900 '}' Turn on .set novolatile (not GAS)
4901 '&' Turn on .set noreorder if filling delay slots
4902 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4903 '!' Turn on .set nomacro if filling delay slots
4904 '#' Print nop if in a .set noreorder section.
4905 '/' Like '#', but does nothing within a delayed branch sequence
4906 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4907 '@' Print the name of the assembler temporary register (at or $1).
4908 '.' Print the name of the register with a hard-wired zero (zero or $0).
4909 '^' Print the name of the pic call-through register (t9 or $25).
4910 '$' Print the name of the stack pointer register (sp or $29).
4911 '+' Print the name of the gp register (usually gp or $28).
4912 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
4915 print_operand (FILE *file, rtx op, int letter)
4917 register enum rtx_code code;
4919 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4924 if (mips_branch_likely)
4929 fputs (reg_names [GP_REG_FIRST + 1], file);
4933 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4937 fputs (reg_names [GP_REG_FIRST + 0], file);
4941 fputs (reg_names[STACK_POINTER_REGNUM], file);
4945 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
4949 if (final_sequence != 0 && set_noreorder++ == 0)
4950 fputs (".set\tnoreorder\n\t", file);
4954 if (final_sequence != 0)
4956 if (set_noreorder++ == 0)
4957 fputs (".set\tnoreorder\n\t", file);
4959 if (set_nomacro++ == 0)
4960 fputs (".set\tnomacro\n\t", file);
4965 if (final_sequence != 0 && set_nomacro++ == 0)
4966 fputs ("\n\t.set\tnomacro", file);
4970 if (set_noreorder != 0)
4971 fputs ("\n\tnop", file);
4975 /* Print an extra newline so that the delayed insn is separated
4976 from the following ones. This looks neater and is consistent
4977 with non-nop delayed sequences. */
4978 if (set_noreorder != 0 && final_sequence == 0)
4979 fputs ("\n\tnop\n", file);
4983 if (set_noreorder++ == 0)
4984 fputs (".set\tnoreorder\n\t", file);
4988 if (set_noreorder == 0)
4989 error ("internal error: %%) found without a %%( in assembler pattern");
4991 else if (--set_noreorder == 0)
4992 fputs ("\n\t.set\treorder", file);
4997 if (set_noat++ == 0)
4998 fputs (".set\tnoat\n\t", file);
5003 error ("internal error: %%] found without a %%[ in assembler pattern");
5004 else if (--set_noat == 0)
5005 fputs ("\n\t.set\tat", file);
5010 if (set_nomacro++ == 0)
5011 fputs (".set\tnomacro\n\t", file);
5015 if (set_nomacro == 0)
5016 error ("internal error: %%> found without a %%< in assembler pattern");
5017 else if (--set_nomacro == 0)
5018 fputs ("\n\t.set\tmacro", file);
5023 if (set_volatile++ == 0)
5024 fputs ("#.set\tvolatile\n\t", file);
5028 if (set_volatile == 0)
5029 error ("internal error: %%} found without a %%{ in assembler pattern");
5030 else if (--set_volatile == 0)
5031 fputs ("\n\t#.set\tnovolatile", file);
5037 if (align_labels_log > 0)
5038 ASM_OUTPUT_ALIGN (file, align_labels_log);
5043 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5052 error ("PRINT_OPERAND null pointer");
5056 code = GET_CODE (op);
5061 case EQ: fputs ("eq", file); break;
5062 case NE: fputs ("ne", file); break;
5063 case GT: fputs ("gt", file); break;
5064 case GE: fputs ("ge", file); break;
5065 case LT: fputs ("lt", file); break;
5066 case LE: fputs ("le", file); break;
5067 case GTU: fputs ("gtu", file); break;
5068 case GEU: fputs ("geu", file); break;
5069 case LTU: fputs ("ltu", file); break;
5070 case LEU: fputs ("leu", file); break;
5072 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5075 else if (letter == 'N')
5078 case EQ: fputs ("ne", file); break;
5079 case NE: fputs ("eq", file); break;
5080 case GT: fputs ("le", file); break;
5081 case GE: fputs ("lt", file); break;
5082 case LT: fputs ("ge", file); break;
5083 case LE: fputs ("gt", file); break;
5084 case GTU: fputs ("leu", file); break;
5085 case GEU: fputs ("ltu", file); break;
5086 case LTU: fputs ("geu", file); break;
5087 case LEU: fputs ("gtu", file); break;
5089 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5092 else if (letter == 'F')
5095 case EQ: fputs ("c1f", file); break;
5096 case NE: fputs ("c1t", file); break;
5098 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5101 else if (letter == 'W')
5104 case EQ: fputs ("c1t", file); break;
5105 case NE: fputs ("c1f", file); break;
5107 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5110 else if (letter == 'h')
5112 if (GET_CODE (op) == HIGH)
5115 print_operand_reloc (file, op, mips_hi_relocs);
5118 else if (letter == 'R')
5119 print_operand_reloc (file, op, mips_lo_relocs);
5121 else if (letter == 'Y')
5123 if (GET_CODE (op) == CONST_INT
5124 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5125 < ARRAY_SIZE (mips_fp_conditions)))
5126 fputs (mips_fp_conditions[INTVAL (op)], file);
5128 output_operand_lossage ("invalid %%Y value");
5131 else if (letter == 'Z')
5135 print_operand (file, op, 0);
5140 else if (code == REG || code == SUBREG)
5142 register int regnum;
5145 regnum = REGNO (op);
5147 regnum = true_regnum (op);
5149 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5150 || (letter == 'L' && WORDS_BIG_ENDIAN)
5154 fprintf (file, "%s", reg_names[regnum]);
5157 else if (code == MEM)
5160 output_address (plus_constant (XEXP (op, 0), 4));
5162 output_address (XEXP (op, 0));
5165 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5166 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5168 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5169 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5171 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5172 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5174 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5175 fputs (reg_names[GP_REG_FIRST], file);
5177 else if (letter == 'd' || letter == 'x' || letter == 'X')
5178 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5180 else if (letter == 'T' || letter == 't')
5182 int truth = (code == NE) == (letter == 'T');
5183 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5186 else if (CONST_GP_P (op))
5187 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5190 output_addr_const (file, op);
5194 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5195 RELOCS is the array of relocations to use. */
5198 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5200 enum mips_symbol_type symbol_type;
5203 HOST_WIDE_INT offset;
5205 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5206 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5208 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5209 mips_split_const (op, &base, &offset);
5210 if (UNSPEC_ADDRESS_P (base))
5211 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5213 fputs (relocs[symbol_type], file);
5214 output_addr_const (file, op);
5215 for (p = relocs[symbol_type]; *p != 0; p++)
5220 /* Output address operand X to FILE. */
5223 print_operand_address (FILE *file, rtx x)
5225 struct mips_address_info addr;
5227 if (mips_classify_address (&addr, x, word_mode, true))
5231 print_operand (file, addr.offset, 0);
5232 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5235 case ADDRESS_LO_SUM:
5236 print_operand (file, addr.offset, 'R');
5237 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5240 case ADDRESS_CONST_INT:
5241 output_addr_const (file, x);
5242 fprintf (file, "(%s)", reg_names[0]);
5245 case ADDRESS_SYMBOLIC:
5246 output_addr_const (file, x);
5252 /* When using assembler macros, keep track of all of small-data externs
5253 so that mips_file_end can emit the appropriate declarations for them.
5255 In most cases it would be safe (though pointless) to emit .externs
5256 for other symbols too. One exception is when an object is within
5257 the -G limit but declared by the user to be in a section other
5258 than .sbss or .sdata. */
5261 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5263 register struct extern_list *p;
5265 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5267 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5268 p->next = extern_head;
5270 p->size = int_size_in_bytes (TREE_TYPE (decl));
5274 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5276 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5277 p->next = extern_head;
5288 irix_output_external_libcall (rtx fun)
5290 register struct extern_list *p;
5292 if (mips_abi == ABI_32)
5294 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5295 p->next = extern_head;
5296 p->name = XSTR (fun, 0);
5303 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5304 put out a MIPS ECOFF file and a stab. */
5307 mips_output_filename (FILE *stream, const char *name)
5310 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5312 if (write_symbols == DWARF2_DEBUG)
5314 else if (mips_output_filename_first_time)
5316 mips_output_filename_first_time = 0;
5317 num_source_filenames += 1;
5318 current_function_file = name;
5319 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5320 output_quoted_string (stream, name);
5321 putc ('\n', stream);
5324 /* If we are emitting stabs, let dbxout.c handle this (except for
5325 the mips_output_filename_first_time case). */
5326 else if (write_symbols == DBX_DEBUG)
5329 else if (name != current_function_file
5330 && strcmp (name, current_function_file) != 0)
5332 num_source_filenames += 1;
5333 current_function_file = name;
5334 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5335 output_quoted_string (stream, name);
5336 putc ('\n', stream);
5340 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5341 that should be written before the opening quote, such as "\t.ascii\t"
5342 for real string data or "\t# " for a comment. */
5345 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5350 register const unsigned char *string =
5351 (const unsigned char *)string_param;
5353 fprintf (stream, "%s\"", prefix);
5354 for (i = 0; i < len; i++)
5356 register int c = string[i];
5360 if (c == '\\' || c == '\"')
5362 putc ('\\', stream);
5370 fprintf (stream, "\\%03o", c);
5374 if (cur_pos > 72 && i+1 < len)
5377 fprintf (stream, "\"\n%s\"", prefix);
5380 fprintf (stream, "\"\n");
5383 /* Implement TARGET_ASM_FILE_START. */
5386 mips_file_start (void)
5388 default_file_start ();
5392 /* Generate a special section to describe the ABI switches used to
5393 produce the resultant binary. This used to be done by the assembler
5394 setting bits in the ELF header's flags field, but we have run out of
5395 bits. GDB needs this information in order to be able to correctly
5396 debug these binaries. See the function mips_gdbarch_init() in
5397 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5398 causes unnecessary IRIX 6 ld warnings. */
5399 const char * abi_string = NULL;
5403 case ABI_32: abi_string = "abi32"; break;
5404 case ABI_N32: abi_string = "abiN32"; break;
5405 case ABI_64: abi_string = "abi64"; break;
5406 case ABI_O64: abi_string = "abiO64"; break;
5407 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5411 /* Note - we use fprintf directly rather than called named_section()
5412 because in this way we can avoid creating an allocated section. We
5413 do not want this section to take up any space in the running
5415 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5417 /* There is no ELF header flag to distinguish long32 forms of the
5418 EABI from long64 forms. Emit a special section to help tools
5420 if (mips_abi == ABI_EABI)
5421 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5422 TARGET_LONG64 ? 64 : 32);
5424 /* Restore the default section. */
5425 fprintf (asm_out_file, "\t.previous\n");
5428 /* Generate the pseudo ops that System V.4 wants. */
5429 if (TARGET_ABICALLS)
5430 /* ??? but do not want this (or want pic0) if -non-shared? */
5431 fprintf (asm_out_file, "\t.abicalls\n");
5434 fprintf (asm_out_file, "\t.set\tmips16\n");
5436 if (flag_verbose_asm)
5437 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5439 mips_section_threshold, mips_arch_info->name, mips_isa);
5442 #ifdef BSS_SECTION_ASM_OP
5443 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5444 in the use of sbss. */
5447 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5448 unsigned HOST_WIDE_INT size, int align)
5450 extern tree last_assemble_variable_decl;
5452 if (mips_in_small_data_p (decl))
5453 named_section (0, ".sbss", 0);
5456 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5457 last_assemble_variable_decl = decl;
5458 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5459 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5463 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5464 .externs for any small-data variables that turned out to be external. */
5467 mips_file_end (void)
5470 struct extern_list *p;
5474 fputs ("\n", asm_out_file);
5476 for (p = extern_head; p != 0; p = p->next)
5478 name_tree = get_identifier (p->name);
5480 /* Positively ensure only one .extern for any given symbol. */
5481 if (!TREE_ASM_WRITTEN (name_tree)
5482 && TREE_SYMBOL_REFERENCED (name_tree))
5484 TREE_ASM_WRITTEN (name_tree) = 1;
5485 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5486 `.global name .text' directive for every used but
5487 undefined function. If we don't, the linker may perform
5488 an optimization (skipping over the insns that set $gp)
5489 when it is unsafe. */
5490 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5492 fputs ("\t.globl ", asm_out_file);
5493 assemble_name (asm_out_file, p->name);
5494 fputs (" .text\n", asm_out_file);
5498 fputs ("\t.extern\t", asm_out_file);
5499 assemble_name (asm_out_file, p->name);
5500 fprintf (asm_out_file, ", %d\n", p->size);
5507 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5508 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5511 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5512 unsigned HOST_WIDE_INT size,
5515 /* If the target wants uninitialized const declarations in
5516 .rdata then don't put them in .comm. */
5517 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5518 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5519 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5521 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5522 targetm.asm_out.globalize_label (stream, name);
5524 readonly_data_section ();
5525 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5526 mips_declare_object (stream, name, "",
5527 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5531 mips_declare_common_object (stream, name, "\n\t.comm\t",
5535 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5536 NAME is the name of the object and ALIGN is the required alignment
5537 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5538 alignment argument. */
5541 mips_declare_common_object (FILE *stream, const char *name,
5542 const char *init_string,
5543 unsigned HOST_WIDE_INT size,
5544 unsigned int align, bool takes_alignment_p)
5546 if (!takes_alignment_p)
5548 size += (align / BITS_PER_UNIT) - 1;
5549 size -= size % (align / BITS_PER_UNIT);
5550 mips_declare_object (stream, name, init_string,
5551 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5554 mips_declare_object (stream, name, init_string,
5555 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5556 size, align / BITS_PER_UNIT);
5559 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5560 macros, mark the symbol as written so that mips_file_end won't emit an
5561 .extern for it. STREAM is the output file, NAME is the name of the
5562 symbol, INIT_STRING is the string that should be written before the
5563 symbol and FINAL_STRING is the string that should be written after it.
5564 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5567 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5568 const char *final_string, ...)
5572 fputs (init_string, stream);
5573 assemble_name (stream, name);
5574 va_start (ap, final_string);
5575 vfprintf (stream, final_string, ap);
5578 if (!TARGET_EXPLICIT_RELOCS)
5580 tree name_tree = get_identifier (name);
5581 TREE_ASM_WRITTEN (name_tree) = 1;
5585 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5586 extern int size_directive_output;
5588 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5589 definitions except that it uses mips_declare_object() to emit the label. */
5592 mips_declare_object_name (FILE *stream, const char *name,
5593 tree decl ATTRIBUTE_UNUSED)
5595 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5596 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5599 size_directive_output = 0;
5600 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5604 size_directive_output = 1;
5605 size = int_size_in_bytes (TREE_TYPE (decl));
5606 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5609 mips_declare_object (stream, name, "", ":\n", 0);
5612 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5615 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5619 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5620 if (!flag_inhibit_size_directive
5621 && DECL_SIZE (decl) != 0
5622 && !at_end && top_level
5623 && DECL_INITIAL (decl) == error_mark_node
5624 && !size_directive_output)
5628 size_directive_output = 1;
5629 size = int_size_in_bytes (TREE_TYPE (decl));
5630 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5635 /* Return true if X is a small data address that can be rewritten
5639 mips_rewrite_small_data_p (rtx x)
5641 enum mips_symbol_type symbol_type;
5643 return (TARGET_EXPLICIT_RELOCS
5644 && mips_symbolic_constant_p (x, &symbol_type)
5645 && symbol_type == SYMBOL_SMALL_DATA);
5649 /* A for_each_rtx callback for mips_small_data_pattern_p. */
5652 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5654 if (GET_CODE (*loc) == LO_SUM)
5657 return mips_rewrite_small_data_p (*loc);
5660 /* Return true if OP refers to small data symbols directly, not through
5664 mips_small_data_pattern_p (rtx op)
5666 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
5669 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
5672 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5674 if (mips_rewrite_small_data_p (*loc))
5675 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
5677 if (GET_CODE (*loc) == LO_SUM)
5683 /* If possible, rewrite OP so that it refers to small data using
5684 explicit relocations. */
5687 mips_rewrite_small_data (rtx op)
5689 op = copy_insn (op);
5690 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
5694 /* Return true if the current function has an insn that implicitly
5698 mips_function_has_gp_insn (void)
5700 /* Don't bother rechecking if we found one last time. */
5701 if (!cfun->machine->has_gp_insn_p)
5705 push_topmost_sequence ();
5706 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5708 && GET_CODE (PATTERN (insn)) != USE
5709 && GET_CODE (PATTERN (insn)) != CLOBBER
5710 && (get_attr_got (insn) != GOT_UNSET
5711 || small_data_pattern (PATTERN (insn), VOIDmode)))
5713 pop_topmost_sequence ();
5715 cfun->machine->has_gp_insn_p = (insn != 0);
5717 return cfun->machine->has_gp_insn_p;
5721 /* Return the register that should be used as the global pointer
5722 within this function. Return 0 if the function doesn't need
5723 a global pointer. */
5726 mips_global_pointer (void)
5730 /* $gp is always available in non-abicalls code. */
5731 if (!TARGET_ABICALLS)
5732 return GLOBAL_POINTER_REGNUM;
5734 /* We must always provide $gp when it is used implicitly. */
5735 if (!TARGET_EXPLICIT_RELOCS)
5736 return GLOBAL_POINTER_REGNUM;
5738 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
5740 if (current_function_profile)
5741 return GLOBAL_POINTER_REGNUM;
5743 /* If the function has a nonlocal goto, $gp must hold the correct
5744 global pointer for the target function. */
5745 if (current_function_has_nonlocal_goto)
5746 return GLOBAL_POINTER_REGNUM;
5748 /* If the gp is never referenced, there's no need to initialize it.
5749 Note that reload can sometimes introduce constant pool references
5750 into a function that otherwise didn't need them. For example,
5751 suppose we have an instruction like:
5753 (set (reg:DF R1) (float:DF (reg:SI R2)))
5755 If R2 turns out to be constant such as 1, the instruction may have a
5756 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
5757 using this constant if R2 doesn't get allocated to a register.
5759 In cases like these, reload will have added the constant to the pool
5760 but no instruction will yet refer to it. */
5761 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
5762 && !current_function_uses_const_pool
5763 && !mips_function_has_gp_insn ())
5766 /* We need a global pointer, but perhaps we can use a call-clobbered
5767 register instead of $gp. */
5768 if (TARGET_NEWABI && current_function_is_leaf)
5769 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5770 if (!regs_ever_live[regno]
5771 && call_used_regs[regno]
5772 && !fixed_regs[regno]
5773 && regno != PIC_FUNCTION_ADDR_REGNUM)
5776 return GLOBAL_POINTER_REGNUM;
5780 /* Return true if the current function must save REGNO. */
5783 mips_save_reg_p (unsigned int regno)
5785 /* We only need to save $gp for NewABI PIC. */
5786 if (regno == GLOBAL_POINTER_REGNUM)
5787 return (TARGET_ABICALLS && TARGET_NEWABI
5788 && cfun->machine->global_pointer == regno);
5790 /* Check call-saved registers. */
5791 if (regs_ever_live[regno] && !call_used_regs[regno])
5794 /* We need to save the old frame pointer before setting up a new one. */
5795 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
5798 /* We need to save the incoming return address if it is ever clobbered
5799 within the function. */
5800 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
5807 return_type = DECL_RESULT (current_function_decl);
5809 /* $18 is a special case in mips16 code. It may be used to call
5810 a function which returns a floating point value, but it is
5811 marked in call_used_regs. */
5812 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
5815 /* $31 is also a special case. It will be used to copy a return
5816 value into the floating point registers if the return value is
5818 if (regno == GP_REG_FIRST + 31
5819 && mips16_hard_float
5820 && !aggregate_value_p (return_type, current_function_decl)
5821 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
5822 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
5830 /* Return the bytes needed to compute the frame pointer from the current
5831 stack pointer. SIZE is the size (in bytes) of the local variables.
5833 Mips stack frames look like:
5835 Before call After call
5836 +-----------------------+ +-----------------------+
5839 | caller's temps. | | caller's temps. |
5841 +-----------------------+ +-----------------------+
5843 | arguments on stack. | | arguments on stack. |
5845 +-----------------------+ +-----------------------+
5846 | 4 words to save | | 4 words to save |
5847 | arguments passed | | arguments passed |
5848 | in registers, even | | in registers, even |
5849 SP->| if not passed. | VFP->| if not passed. |
5850 +-----------------------+ +-----------------------+
5852 | fp register save |
5854 +-----------------------+
5856 | gp register save |
5858 +-----------------------+
5862 +-----------------------+
5864 | alloca allocations |
5866 +-----------------------+
5868 | GP save for V.4 abi |
5870 +-----------------------+
5872 | arguments on stack |
5874 +-----------------------+
5876 | arguments passed |
5877 | in registers, even |
5878 low SP->| if not passed. |
5879 memory +-----------------------+
5884 compute_frame_size (HOST_WIDE_INT size)
5887 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5888 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5889 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5890 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
5891 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5892 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5893 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5894 unsigned int mask; /* mask of saved gp registers */
5895 unsigned int fmask; /* mask of saved fp registers */
5897 cfun->machine->global_pointer = mips_global_pointer ();
5903 var_size = MIPS_STACK_ALIGN (size);
5904 args_size = current_function_outgoing_args_size;
5905 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
5907 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
5908 functions. If the function has local variables, we're committed
5909 to allocating it anyway. Otherwise reclaim it here. */
5910 if (var_size == 0 && current_function_is_leaf)
5911 cprestore_size = args_size = 0;
5913 /* The MIPS 3.0 linker does not like functions that dynamically
5914 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5915 looks like we are trying to create a second frame pointer to the
5916 function, so allocate some stack space to make it happy. */
5918 if (args_size == 0 && current_function_calls_alloca)
5919 args_size = 4 * UNITS_PER_WORD;
5921 total_size = var_size + args_size + cprestore_size;
5923 /* Calculate space needed for gp registers. */
5924 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5925 if (mips_save_reg_p (regno))
5927 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5928 mask |= 1 << (regno - GP_REG_FIRST);
5931 /* We need to restore these for the handler. */
5932 if (current_function_calls_eh_return)
5937 regno = EH_RETURN_DATA_REGNO (i);
5938 if (regno == INVALID_REGNUM)
5940 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5941 mask |= 1 << (regno - GP_REG_FIRST);
5945 /* This loop must iterate over the same space as its companion in
5946 save_restore_insns. */
5947 for (regno = (FP_REG_LAST - FP_INC + 1);
5948 regno >= FP_REG_FIRST;
5951 if (mips_save_reg_p (regno))
5953 fp_reg_size += FP_INC * UNITS_PER_FPREG;
5954 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
5958 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5959 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
5961 /* Add in space reserved on the stack by the callee for storing arguments
5962 passed in registers. */
5964 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5966 /* Save other computed information. */
5967 cfun->machine->frame.total_size = total_size;
5968 cfun->machine->frame.var_size = var_size;
5969 cfun->machine->frame.args_size = args_size;
5970 cfun->machine->frame.cprestore_size = cprestore_size;
5971 cfun->machine->frame.gp_reg_size = gp_reg_size;
5972 cfun->machine->frame.fp_reg_size = fp_reg_size;
5973 cfun->machine->frame.mask = mask;
5974 cfun->machine->frame.fmask = fmask;
5975 cfun->machine->frame.initialized = reload_completed;
5976 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
5977 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
5981 HOST_WIDE_INT offset;
5983 offset = (args_size + cprestore_size + var_size
5984 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
5985 cfun->machine->frame.gp_sp_offset = offset;
5986 cfun->machine->frame.gp_save_offset = offset - total_size;
5990 cfun->machine->frame.gp_sp_offset = 0;
5991 cfun->machine->frame.gp_save_offset = 0;
5996 HOST_WIDE_INT offset;
5998 offset = (args_size + cprestore_size + var_size
5999 + gp_reg_rounded + fp_reg_size
6000 - FP_INC * UNITS_PER_FPREG);
6001 cfun->machine->frame.fp_sp_offset = offset;
6002 cfun->machine->frame.fp_save_offset = offset - total_size;
6006 cfun->machine->frame.fp_sp_offset = 0;
6007 cfun->machine->frame.fp_save_offset = 0;
6010 /* Ok, we're done. */
6014 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6015 pointer or argument pointer. TO is either the stack pointer or
6016 hard frame pointer. */
6019 mips_initial_elimination_offset (int from, int to)
6021 HOST_WIDE_INT offset;
6023 compute_frame_size (get_frame_size ());
6025 /* Set OFFSET to the offset from the stack pointer. */
6028 case FRAME_POINTER_REGNUM:
6032 case ARG_POINTER_REGNUM:
6033 offset = cfun->machine->frame.total_size;
6035 offset -= current_function_pretend_args_size;
6042 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6043 offset -= cfun->machine->frame.args_size;
6048 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6049 back to a previous frame. */
6051 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6056 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6059 /* Use FN to save or restore register REGNO. MODE is the register's
6060 mode and OFFSET is the offset of its save slot from the current
6064 mips_save_restore_reg (enum machine_mode mode, int regno,
6065 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6069 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6071 fn (gen_rtx_REG (mode, regno), mem);
6075 /* Call FN for each register that is saved by the current function.
6076 SP_OFFSET is the offset of the current stack pointer from the start
6080 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6082 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6084 enum machine_mode fpr_mode;
6085 HOST_WIDE_INT offset;
6088 /* Save registers starting from high to low. The debuggers prefer at least
6089 the return register be stored at func+4, and also it allows us not to
6090 need a nop in the epilog if at least one register is reloaded in
6091 addition to return address. */
6092 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6093 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6094 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6096 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6097 offset -= GET_MODE_SIZE (gpr_mode);
6100 /* This loop must iterate over the same space as its companion in
6101 compute_frame_size. */
6102 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6103 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6104 for (regno = (FP_REG_LAST - FP_INC + 1);
6105 regno >= FP_REG_FIRST;
6107 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6109 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6110 offset -= GET_MODE_SIZE (fpr_mode);
6115 /* If we're generating n32 or n64 abicalls, and the current function
6116 does not use $28 as its global pointer, emit a cplocal directive.
6117 Use pic_offset_table_rtx as the argument to the directive. */
6120 mips_output_cplocal (void)
6122 if (!TARGET_EXPLICIT_RELOCS
6123 && cfun->machine->global_pointer > 0
6124 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6125 output_asm_insn (".cplocal %+", 0);
6128 /* If we're generating n32 or n64 abicalls, emit instructions
6129 to set up the global pointer. */
6132 mips_emit_loadgp (void)
6134 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6136 rtx addr, offset, incoming_address;
6138 addr = XEXP (DECL_RTL (current_function_decl), 0);
6139 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6140 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6141 emit_insn (gen_loadgp (offset, incoming_address));
6142 if (!TARGET_EXPLICIT_RELOCS)
6143 emit_insn (gen_loadgp_blockage ());
6147 /* Set up the stack and frame (if desired) for the function. */
6150 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6153 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6155 #ifdef SDB_DEBUGGING_INFO
6156 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6157 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6160 /* In mips16 mode, we may need to generate a 32 bit to handle
6161 floating point arguments. The linker will arrange for any 32 bit
6162 functions to call this stub, which will then jump to the 16 bit
6164 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6165 && current_function_args_info.fp_code != 0)
6166 build_mips16_function_stub (file);
6168 if (!FUNCTION_NAME_ALREADY_DECLARED)
6170 /* Get the function name the same way that toplev.c does before calling
6171 assemble_start_function. This is needed so that the name used here
6172 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6173 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6175 if (!flag_inhibit_size_directive)
6177 fputs ("\t.ent\t", file);
6178 assemble_name (file, fnname);
6182 assemble_name (file, fnname);
6183 fputs (":\n", file);
6186 /* Stop mips_file_end from treating this function as external. */
6187 if (TARGET_IRIX && mips_abi == ABI_32)
6188 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6190 if (!flag_inhibit_size_directive)
6192 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6194 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6195 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6196 ", args= " HOST_WIDE_INT_PRINT_DEC
6197 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6198 (reg_names[(frame_pointer_needed)
6199 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6200 ((frame_pointer_needed && TARGET_MIPS16)
6201 ? tsize - cfun->machine->frame.args_size
6203 reg_names[GP_REG_FIRST + 31],
6204 cfun->machine->frame.var_size,
6205 cfun->machine->frame.num_gp,
6206 cfun->machine->frame.num_fp,
6207 cfun->machine->frame.args_size,
6208 cfun->machine->frame.cprestore_size);
6210 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6211 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6212 cfun->machine->frame.mask,
6213 cfun->machine->frame.gp_save_offset);
6214 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6215 cfun->machine->frame.fmask,
6216 cfun->machine->frame.fp_save_offset);
6219 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6220 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6223 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6225 /* Handle the initialization of $gp for SVR4 PIC. */
6226 if (!cfun->machine->all_noreorder_p)
6227 output_asm_insn ("%(.cpload\t%^%)", 0);
6229 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6231 else if (cfun->machine->all_noreorder_p)
6232 output_asm_insn ("%(%<", 0);
6234 /* Tell the assembler which register we're using as the global
6235 pointer. This is needed for thunks, since they can use either
6236 explicit relocs or assembler macros. */
6237 mips_output_cplocal ();
6240 /* Make the last instruction frame related and note that it performs
6241 the operation described by FRAME_PATTERN. */
6244 mips_set_frame_expr (rtx frame_pattern)
6248 insn = get_last_insn ();
6249 RTX_FRAME_RELATED_P (insn) = 1;
6250 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6256 /* Return a frame-related rtx that stores REG at MEM.
6257 REG must be a single register. */
6260 mips_frame_set (rtx mem, rtx reg)
6264 /* If we're saving the return address register and the dwarf return
6265 address column differs from the hard register number, adjust the
6266 note reg to refer to the former. */
6267 if (REGNO (reg) == GP_REG_FIRST + 31
6268 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6269 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6271 set = gen_rtx_SET (VOIDmode, mem, reg);
6272 RTX_FRAME_RELATED_P (set) = 1;
6278 /* Save register REG to MEM. Make the instruction frame-related. */
6281 mips_save_reg (rtx reg, rtx mem)
6283 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6287 if (mips_split_64bit_move_p (mem, reg))
6288 mips_split_64bit_move (mem, reg);
6290 emit_move_insn (mem, reg);
6292 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6293 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6294 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6299 && REGNO (reg) != GP_REG_FIRST + 31
6300 && !M16_REG_P (REGNO (reg)))
6302 /* Save a non-mips16 register by moving it through a temporary.
6303 We don't need to do this for $31 since there's a special
6304 instruction for it. */
6305 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6306 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6309 emit_move_insn (mem, reg);
6311 mips_set_frame_expr (mips_frame_set (mem, reg));
6316 /* Expand the prologue into a bunch of separate insns. */
6319 mips_expand_prologue (void)
6323 if (cfun->machine->global_pointer > 0)
6324 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6326 size = compute_frame_size (get_frame_size ());
6328 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6329 bytes beforehand; this is enough to cover the register save area
6330 without going out of range. */
6331 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6333 HOST_WIDE_INT step1;
6335 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6336 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6338 GEN_INT (-step1)))) = 1;
6340 mips_for_each_saved_reg (size, mips_save_reg);
6343 /* Allocate the rest of the frame. */
6346 if (SMALL_OPERAND (-size))
6347 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6349 GEN_INT (-size)))) = 1;
6352 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6355 /* There are no instructions to add or subtract registers
6356 from the stack pointer, so use the frame pointer as a
6357 temporary. We should always be using a frame pointer
6358 in this case anyway. */
6359 gcc_assert (frame_pointer_needed);
6360 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6361 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6362 hard_frame_pointer_rtx,
6363 MIPS_PROLOGUE_TEMP (Pmode)));
6364 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6367 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6369 MIPS_PROLOGUE_TEMP (Pmode)));
6371 /* Describe the combined effect of the previous instructions. */
6373 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6374 plus_constant (stack_pointer_rtx, -size)));
6378 /* Set up the frame pointer, if we're using one. In mips16 code,
6379 we point the frame pointer ahead of the outgoing argument area.
6380 This should allow more variables & incoming arguments to be
6381 accessed with unextended instructions. */
6382 if (frame_pointer_needed)
6384 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6386 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6388 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6393 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6394 stack_pointer_rtx)) = 1;
6397 /* If generating o32/o64 abicalls, save $gp on the stack. */
6398 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6399 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6401 mips_emit_loadgp ();
6403 /* If we are profiling, make sure no instructions are scheduled before
6404 the call to mcount. */
6406 if (current_function_profile)
6407 emit_insn (gen_blockage ());
6410 /* Do any necessary cleanup after a function to restore stack, frame,
6413 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6416 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6417 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6419 /* Reinstate the normal $gp. */
6420 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6421 mips_output_cplocal ();
6423 if (cfun->machine->all_noreorder_p)
6425 /* Avoid using %>%) since it adds excess whitespace. */
6426 output_asm_insn (".set\tmacro", 0);
6427 output_asm_insn (".set\treorder", 0);
6428 set_noreorder = set_nomacro = 0;
6431 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6435 /* Get the function name the same way that toplev.c does before calling
6436 assemble_start_function. This is needed so that the name used here
6437 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6438 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6439 fputs ("\t.end\t", file);
6440 assemble_name (file, fnname);
6445 /* Emit instructions to restore register REG from slot MEM. */
6448 mips_restore_reg (rtx reg, rtx mem)
6450 /* There's no mips16 instruction to load $31 directly. Load into
6451 $7 instead and adjust the return insn appropriately. */
6452 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6453 reg = gen_rtx_REG (GET_MODE (reg), 7);
6455 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6457 /* Can't restore directly; move through a temporary. */
6458 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6459 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6462 emit_move_insn (reg, mem);
6466 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6467 if this epilogue precedes a sibling call, false if it is for a normal
6468 "epilogue" pattern. */
6471 mips_expand_epilogue (int sibcall_p)
6473 HOST_WIDE_INT step1, step2;
6476 if (!sibcall_p && mips_can_use_return_insn ())
6478 emit_jump_insn (gen_return ());
6482 /* Split the frame into two. STEP1 is the amount of stack we should
6483 deallocate before restoring the registers. STEP2 is the amount we
6484 should deallocate afterwards.
6486 Start off by assuming that no registers need to be restored. */
6487 step1 = cfun->machine->frame.total_size;
6490 /* Work out which register holds the frame address. Account for the
6491 frame pointer offset used by mips16 code. */
6492 if (!frame_pointer_needed)
6493 base = stack_pointer_rtx;
6496 base = hard_frame_pointer_rtx;
6498 step1 -= cfun->machine->frame.args_size;
6501 /* If we need to restore registers, deallocate as much stack as
6502 possible in the second step without going out of range. */
6503 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6505 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6509 /* Set TARGET to BASE + STEP1. */
6515 /* Get an rtx for STEP1 that we can add to BASE. */
6516 adjust = GEN_INT (step1);
6517 if (!SMALL_OPERAND (step1))
6519 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6520 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6523 /* Normal mode code can copy the result straight into $sp. */
6525 target = stack_pointer_rtx;
6527 emit_insn (gen_add3_insn (target, base, adjust));
6530 /* Copy TARGET into the stack pointer. */
6531 if (target != stack_pointer_rtx)
6532 emit_move_insn (stack_pointer_rtx, target);
6534 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6535 implicitly used by all SYMBOL_REFs. We must emit a blockage
6536 insn before restoring it. */
6537 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6538 emit_insn (gen_blockage ());
6540 /* Restore the registers. */
6541 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6544 /* Deallocate the final bit of the frame. */
6546 emit_insn (gen_add3_insn (stack_pointer_rtx,
6550 /* Add in the __builtin_eh_return stack adjustment. We need to
6551 use a temporary in mips16 code. */
6552 if (current_function_calls_eh_return)
6556 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6557 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6558 MIPS_EPILOGUE_TEMP (Pmode),
6559 EH_RETURN_STACKADJ_RTX));
6560 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6563 emit_insn (gen_add3_insn (stack_pointer_rtx,
6565 EH_RETURN_STACKADJ_RTX));
6570 /* The mips16 loads the return address into $7, not $31. */
6571 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6572 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6573 GP_REG_FIRST + 7)));
6575 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6576 GP_REG_FIRST + 31)));
6580 /* Return nonzero if this function is known to have a null epilogue.
6581 This allows the optimizer to omit jumps to jumps if no stack
6585 mips_can_use_return_insn (void)
6589 if (! reload_completed)
6592 if (regs_ever_live[31] || current_function_profile)
6595 return_type = DECL_RESULT (current_function_decl);
6597 /* In mips16 mode, a function which returns a floating point value
6598 needs to arrange to copy the return value into the floating point
6601 && mips16_hard_float
6602 && ! aggregate_value_p (return_type, current_function_decl)
6603 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6604 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6607 if (cfun->machine->frame.initialized)
6608 return cfun->machine->frame.total_size == 0;
6610 return compute_frame_size (get_frame_size ()) == 0;
6613 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6614 in order to avoid duplicating too much logic from elsewhere. */
6617 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6618 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6621 rtx this, temp1, temp2, insn, fnaddr;
6623 /* Pretend to be a post-reload pass while generating rtl. */
6625 reload_completed = 1;
6626 reset_block_changes ();
6628 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6629 for TARGET_NEWABI since the latter is a call-saved register. */
6630 if (TARGET_ABICALLS)
6631 cfun->machine->global_pointer
6632 = REGNO (pic_offset_table_rtx)
6633 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6635 /* Set up the global pointer for n32 or n64 abicalls. */
6636 mips_emit_loadgp ();
6638 /* We need two temporary registers in some cases. */
6639 temp1 = gen_rtx_REG (Pmode, 2);
6640 temp2 = gen_rtx_REG (Pmode, 3);
6642 /* Find out which register contains the "this" pointer. */
6643 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6644 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6646 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6648 /* Add DELTA to THIS. */
6651 rtx offset = GEN_INT (delta);
6652 if (!SMALL_OPERAND (delta))
6654 emit_move_insn (temp1, offset);
6657 emit_insn (gen_add3_insn (this, this, offset));
6660 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6661 if (vcall_offset != 0)
6665 /* Set TEMP1 to *THIS. */
6666 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
6668 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
6669 addr = mips_add_offset (temp2, temp1, vcall_offset);
6671 /* Load the offset and add it to THIS. */
6672 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
6673 emit_insn (gen_add3_insn (this, this, temp1));
6676 /* Jump to the target function. Use a sibcall if direct jumps are
6677 allowed, otherwise load the address into a register first. */
6678 fnaddr = XEXP (DECL_RTL (function), 0);
6679 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
6681 /* This is messy. gas treats "la $25,foo" as part of a call
6682 sequence and may allow a global "foo" to be lazily bound.
6683 The general move patterns therefore reject this combination.
6685 In this context, lazy binding would actually be OK for o32 and o64,
6686 but it's still wrong for n32 and n64; see mips_load_call_address.
6687 We must therefore load the address via a temporary register if
6688 mips_dangerous_for_la25_p.
6690 If we jump to the temporary register rather than $25, the assembler
6691 can use the move insn to fill the jump's delay slot. */
6692 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
6693 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6694 mips_load_call_address (temp1, fnaddr, true);
6696 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
6697 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
6698 emit_jump_insn (gen_indirect_jump (temp1));
6702 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
6703 SIBLING_CALL_P (insn) = 1;
6706 /* Run just enough of rest_of_compilation. This sequence was
6707 "borrowed" from alpha.c. */
6708 insn = get_insns ();
6709 insn_locators_initialize ();
6710 split_all_insns_noflow ();
6712 mips16_lay_out_constants ();
6713 shorten_branches (insn);
6714 final_start_function (insn, file, 1);
6715 final (insn, file, 1);
6716 final_end_function ();
6718 /* Clean up the vars set above. Note that final_end_function resets
6719 the global pointer for us. */
6720 reload_completed = 0;
6724 /* Returns nonzero if X contains a SYMBOL_REF. */
6727 symbolic_expression_p (rtx x)
6729 if (GET_CODE (x) == SYMBOL_REF)
6732 if (GET_CODE (x) == CONST)
6733 return symbolic_expression_p (XEXP (x, 0));
6736 return symbolic_expression_p (XEXP (x, 0));
6738 if (ARITHMETIC_P (x))
6739 return (symbolic_expression_p (XEXP (x, 0))
6740 || symbolic_expression_p (XEXP (x, 1)));
6745 /* Choose the section to use for the constant rtx expression X that has
6749 mips_select_rtx_section (enum machine_mode mode, rtx x,
6750 unsigned HOST_WIDE_INT align)
6754 /* In mips16 mode, the constant table always goes in the same section
6755 as the function, so that constants can be loaded using PC relative
6757 function_section (current_function_decl);
6759 else if (TARGET_EMBEDDED_DATA)
6761 /* For embedded applications, always put constants in read-only data,
6762 in order to reduce RAM usage. */
6763 mergeable_constant_section (mode, align, 0);
6767 /* For hosted applications, always put constants in small data if
6768 possible, as this gives the best performance. */
6769 /* ??? Consider using mergeable small data sections. */
6771 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
6772 && mips_section_threshold > 0)
6773 named_section (0, ".sdata", 0);
6774 else if (flag_pic && symbolic_expression_p (x))
6775 named_section (0, ".data.rel.ro", 3);
6777 mergeable_constant_section (mode, align, 0);
6781 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6783 The complication here is that, with the combination TARGET_ABICALLS
6784 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6785 therefore not be included in the read-only part of a DSO. Handle such
6786 cases by selecting a normal data section instead of a read-only one.
6787 The logic apes that in default_function_rodata_section. */
6790 mips_function_rodata_section (tree decl)
6792 if (!TARGET_ABICALLS || TARGET_GPWORD)
6793 default_function_rodata_section (decl);
6794 else if (decl && DECL_SECTION_NAME (decl))
6796 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6797 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6799 char *rname = ASTRDUP (name);
6801 named_section_real (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6803 else if (flag_function_sections && flag_data_sections
6804 && strncmp (name, ".text.", 6) == 0)
6806 char *rname = ASTRDUP (name);
6807 memcpy (rname + 1, "data", 4);
6808 named_section_flags (rname, SECTION_WRITE);
6817 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
6818 access DECL using %gp_rel(...)($gp). */
6821 mips_in_small_data_p (tree decl)
6825 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6828 /* We don't yet generate small-data references for -mabicalls. See related
6829 -G handling in override_options. */
6830 if (TARGET_ABICALLS)
6833 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6837 /* Reject anything that isn't in a known small-data section. */
6838 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6839 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6842 /* If a symbol is defined externally, the assembler will use the
6843 usual -G rules when deciding how to implement macros. */
6844 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
6847 else if (TARGET_EMBEDDED_DATA)
6849 /* Don't put constants into the small data section: we want them
6850 to be in ROM rather than RAM. */
6851 if (TREE_CODE (decl) != VAR_DECL)
6854 if (TREE_READONLY (decl)
6855 && !TREE_SIDE_EFFECTS (decl)
6856 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6860 size = int_size_in_bytes (TREE_TYPE (decl));
6861 return (size > 0 && size <= mips_section_threshold);
6864 /* See whether VALTYPE is a record whose fields should be returned in
6865 floating-point registers. If so, return the number of fields and
6866 list them in FIELDS (which should have two elements). Return 0
6869 For n32 & n64, a structure with one or two fields is returned in
6870 floating-point registers as long as every field has a floating-point
6874 mips_fpr_return_fields (tree valtype, tree *fields)
6882 if (TREE_CODE (valtype) != RECORD_TYPE)
6886 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
6888 if (TREE_CODE (field) != FIELD_DECL)
6891 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
6897 fields[i++] = field;
6903 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6904 a value in the most significant part of $2/$3 if:
6906 - the target is big-endian;
6908 - the value has a structure or union type (we generalize this to
6909 cover aggregates from other languages too); and
6911 - the structure is not returned in floating-point registers. */
6914 mips_return_in_msb (tree valtype)
6918 return (TARGET_NEWABI
6919 && TARGET_BIG_ENDIAN
6920 && AGGREGATE_TYPE_P (valtype)
6921 && mips_fpr_return_fields (valtype, fields) == 0);
6925 /* Return a composite value in a pair of floating-point registers.
6926 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6927 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6930 For n32 & n64, $f0 always holds the first value and $f2 the second.
6931 Otherwise the values are packed together as closely as possible. */
6934 mips_return_fpr_pair (enum machine_mode mode,
6935 enum machine_mode mode1, HOST_WIDE_INT offset1,
6936 enum machine_mode mode2, HOST_WIDE_INT offset2)
6940 inc = (TARGET_NEWABI ? 2 : FP_INC);
6941 return gen_rtx_PARALLEL
6944 gen_rtx_EXPR_LIST (VOIDmode,
6945 gen_rtx_REG (mode1, FP_RETURN),
6947 gen_rtx_EXPR_LIST (VOIDmode,
6948 gen_rtx_REG (mode2, FP_RETURN + inc),
6949 GEN_INT (offset2))));
6954 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
6955 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
6956 VALTYPE is null and MODE is the mode of the return value. */
6959 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
6960 enum machine_mode mode)
6967 mode = TYPE_MODE (valtype);
6968 unsignedp = TYPE_UNSIGNED (valtype);
6970 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
6971 true, we must promote the mode just as PROMOTE_MODE does. */
6972 mode = promote_mode (valtype, mode, &unsignedp, 1);
6974 /* Handle structures whose fields are returned in $f0/$f2. */
6975 switch (mips_fpr_return_fields (valtype, fields))
6978 return gen_rtx_REG (mode, FP_RETURN);
6981 return mips_return_fpr_pair (mode,
6982 TYPE_MODE (TREE_TYPE (fields[0])),
6983 int_byte_position (fields[0]),
6984 TYPE_MODE (TREE_TYPE (fields[1])),
6985 int_byte_position (fields[1]));
6988 /* If a value is passed in the most significant part of a register, see
6989 whether we have to round the mode up to a whole number of words. */
6990 if (mips_return_in_msb (valtype))
6992 HOST_WIDE_INT size = int_size_in_bytes (valtype);
6993 if (size % UNITS_PER_WORD != 0)
6995 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
6996 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7000 /* For EABI, the class of return register depends entirely on MODE.
7001 For example, "struct { some_type x; }" and "union { some_type x; }"
7002 are returned in the same way as a bare "some_type" would be.
7003 Other ABIs only use FPRs for scalar, complex or vector types. */
7004 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7005 return gen_rtx_REG (mode, GP_RETURN);
7008 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7009 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7010 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7011 return gen_rtx_REG (mode, FP_RETURN);
7013 /* Handle long doubles for n32 & n64. */
7015 return mips_return_fpr_pair (mode,
7017 DImode, GET_MODE_SIZE (mode) / 2);
7019 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7020 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7021 return mips_return_fpr_pair (mode,
7022 GET_MODE_INNER (mode), 0,
7023 GET_MODE_INNER (mode),
7024 GET_MODE_SIZE (mode) / 2);
7026 return gen_rtx_REG (mode, GP_RETURN);
7029 /* Return nonzero when an argument must be passed by reference. */
7032 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7033 enum machine_mode mode, tree type,
7034 bool named ATTRIBUTE_UNUSED)
7036 if (mips_abi == ABI_EABI)
7040 /* ??? How should SCmode be handled? */
7041 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7044 size = int_size_in_bytes (type);
7045 return size == -1 || size > UNITS_PER_WORD;
7049 /* If we have a variable-sized parameter, we have no choice. */
7050 return targetm.calls.must_pass_in_stack (mode, type);
7055 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7056 enum machine_mode mode ATTRIBUTE_UNUSED,
7057 tree type ATTRIBUTE_UNUSED, bool named)
7059 return mips_abi == ABI_EABI && named;
7062 /* Return true if registers of class CLASS cannot change from mode FROM
7066 mips_cannot_change_mode_class (enum machine_mode from,
7067 enum machine_mode to, enum reg_class class)
7069 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7070 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7072 if (TARGET_BIG_ENDIAN)
7074 /* When a multi-word value is stored in paired floating-point
7075 registers, the first register always holds the low word.
7076 We therefore can't allow FPRs to change between single-word
7077 and multi-word modes. */
7078 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7083 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7084 in LO and HI, the high word always comes first. We therefore
7085 can't allow values stored in HI to change between single-word
7086 and multi-word modes. */
7087 if (reg_classes_intersect_p (HI_REG, class))
7091 /* Loading a 32-bit value into a 64-bit floating-point register
7092 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7093 We can't allow 64-bit float registers to change from SImode to
7097 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7098 && reg_classes_intersect_p (FP_REGS, class))
7103 /* Return true if X should not be moved directly into register $25.
7104 We need this because many versions of GAS will treat "la $25,foo" as
7105 part of a call sequence and so allow a global "foo" to be lazily bound. */
7108 mips_dangerous_for_la25_p (rtx x)
7110 HOST_WIDE_INT offset;
7112 if (TARGET_EXPLICIT_RELOCS)
7115 mips_split_const (x, &x, &offset);
7116 return global_got_operand (x, VOIDmode);
7119 /* Implement PREFERRED_RELOAD_CLASS. */
7122 mips_preferred_reload_class (rtx x, enum reg_class class)
7124 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7127 if (TARGET_HARD_FLOAT
7128 && FLOAT_MODE_P (GET_MODE (x))
7129 && reg_class_subset_p (FP_REGS, class))
7132 if (reg_class_subset_p (GR_REGS, class))
7135 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7141 /* This function returns the register class required for a secondary
7142 register when copying between one of the registers in CLASS, and X,
7143 using MODE. If IN_P is nonzero, the copy is going from X to the
7144 register, otherwise the register is the source. A return value of
7145 NO_REGS means that no secondary register is required. */
7148 mips_secondary_reload_class (enum reg_class class,
7149 enum machine_mode mode, rtx x, int in_p)
7151 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7155 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7156 regno = true_regnum (x);
7158 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7160 if (mips_dangerous_for_la25_p (x))
7163 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7167 /* Copying from HI or LO to anywhere other than a general register
7168 requires a general register. */
7169 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7171 if (TARGET_MIPS16 && in_p)
7173 /* We can't really copy to HI or LO at all in mips16 mode. */
7176 return gp_reg_p ? NO_REGS : gr_regs;
7178 if (MD_REG_P (regno))
7180 if (TARGET_MIPS16 && ! in_p)
7182 /* We can't really copy to HI or LO at all in mips16 mode. */
7185 return class == gr_regs ? NO_REGS : gr_regs;
7188 /* We can only copy a value to a condition code register from a
7189 floating point register, and even then we require a scratch
7190 floating point register. We can only copy a value out of a
7191 condition code register into a general register. */
7192 if (class == ST_REGS)
7196 return gp_reg_p ? NO_REGS : gr_regs;
7198 if (ST_REG_P (regno))
7202 return class == gr_regs ? NO_REGS : gr_regs;
7205 if (class == FP_REGS)
7209 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7212 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7214 /* We can use the l.s and l.d macros to load floating-point
7215 constants. ??? For l.s, we could probably get better
7216 code by returning GR_REGS here. */
7219 else if (gp_reg_p || x == CONST0_RTX (mode))
7221 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7224 else if (FP_REG_P (regno))
7226 /* In this case we can use mov.s or mov.d. */
7231 /* Otherwise, we need to reload through an integer register. */
7236 /* In mips16 mode, going between memory and anything but M16_REGS
7237 requires an M16_REG. */
7240 if (class != M16_REGS && class != M16_NA_REGS)
7248 if (class == M16_REGS || class == M16_NA_REGS)
7257 /* Implement CLASS_MAX_NREGS.
7259 Usually all registers are word-sized. The only supported exception
7260 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7261 registers. A word-based calculation is correct even in that case,
7262 since -msingle-float disallows multi-FPR values.
7264 The FP status registers are an exception to this rule. They are always
7265 4 bytes wide as they only hold condition code modes, and CCmode is always
7266 considered to be 4 bytes wide. */
7269 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7270 enum machine_mode mode)
7272 if (class == ST_REGS)
7273 return (GET_MODE_SIZE (mode) + 3) / 4;
7275 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7279 mips_valid_pointer_mode (enum machine_mode mode)
7281 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7284 /* Target hook for vector_mode_supported_p. */
7287 mips_vector_mode_supported_p (enum machine_mode mode)
7289 if (mode == V2SFmode && TARGET_PAIRED_SINGLE_FLOAT)
7295 /* If we can access small data directly (using gp-relative relocation
7296 operators) return the small data pointer, otherwise return null.
7298 For each mips16 function which refers to GP relative symbols, we
7299 use a pseudo register, initialized at the start of the function, to
7300 hold the $gp value. */
7303 mips16_gp_pseudo_reg (void)
7305 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7310 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7312 /* We want to initialize this to a value which gcc will believe
7315 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7316 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7317 gen_rtx_CONST (Pmode, unspec));
7318 insn = get_insns ();
7321 push_topmost_sequence ();
7322 /* We need to emit the initialization after the FUNCTION_BEG
7323 note, so that it will be integrated. */
7324 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7326 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7328 if (scan == NULL_RTX)
7329 scan = get_insns ();
7330 insn = emit_insn_after (insn, scan);
7331 pop_topmost_sequence ();
7334 return cfun->machine->mips16_gp_pseudo_rtx;
7337 /* Write out code to move floating point arguments in or out of
7338 general registers. Output the instructions to FILE. FP_CODE is
7339 the code describing which arguments are present (see the comment at
7340 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7341 we are copying from the floating point registers. */
7344 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7350 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7351 gcc_assert (TARGET_OLDABI);
7357 gparg = GP_ARG_FIRST;
7358 fparg = FP_ARG_FIRST;
7359 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7363 if ((fparg & 1) != 0)
7365 fprintf (file, "\t%s\t%s,%s\n", s,
7366 reg_names[gparg], reg_names[fparg]);
7368 else if ((f & 3) == 2)
7371 fprintf (file, "\td%s\t%s,%s\n", s,
7372 reg_names[gparg], reg_names[fparg]);
7375 if ((fparg & 1) != 0)
7377 if (TARGET_BIG_ENDIAN)
7378 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7379 reg_names[gparg], reg_names[fparg + 1], s,
7380 reg_names[gparg + 1], reg_names[fparg]);
7382 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7383 reg_names[gparg], reg_names[fparg], s,
7384 reg_names[gparg + 1], reg_names[fparg + 1]);
7397 /* Build a mips16 function stub. This is used for functions which
7398 take arguments in the floating point registers. It is 32 bit code
7399 that moves the floating point args into the general registers, and
7400 then jumps to the 16 bit code. */
7403 build_mips16_function_stub (FILE *file)
7406 char *secname, *stubname;
7407 tree stubid, stubdecl;
7411 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7412 secname = (char *) alloca (strlen (fnname) + 20);
7413 sprintf (secname, ".mips16.fn.%s", fnname);
7414 stubname = (char *) alloca (strlen (fnname) + 20);
7415 sprintf (stubname, "__fn_stub_%s", fnname);
7416 stubid = get_identifier (stubname);
7417 stubdecl = build_decl (FUNCTION_DECL, stubid,
7418 build_function_type (void_type_node, NULL_TREE));
7419 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7421 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7423 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7425 fprintf (file, "%s%s",
7426 need_comma ? ", " : "",
7427 (f & 3) == 1 ? "float" : "double");
7430 fprintf (file, ")\n");
7432 fprintf (file, "\t.set\tnomips16\n");
7433 function_section (stubdecl);
7434 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7436 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7437 within a .ent, and we cannot emit another .ent. */
7438 if (!FUNCTION_NAME_ALREADY_DECLARED)
7440 fputs ("\t.ent\t", file);
7441 assemble_name (file, stubname);
7445 assemble_name (file, stubname);
7446 fputs (":\n", file);
7448 /* We don't want the assembler to insert any nops here. */
7449 fprintf (file, "\t.set\tnoreorder\n");
7451 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7453 fprintf (asm_out_file, "\t.set\tnoat\n");
7454 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7455 assemble_name (file, fnname);
7456 fprintf (file, "\n");
7457 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7458 fprintf (asm_out_file, "\t.set\tat\n");
7460 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7461 with one of the mfc1 instructions, because the result is not
7462 available for one instruction, so if the very first instruction
7463 in the function refers to the register, it will see the wrong
7465 fprintf (file, "\tnop\n");
7467 fprintf (file, "\t.set\treorder\n");
7469 if (!FUNCTION_NAME_ALREADY_DECLARED)
7471 fputs ("\t.end\t", file);
7472 assemble_name (file, stubname);
7476 fprintf (file, "\t.set\tmips16\n");
7478 function_section (current_function_decl);
7481 /* We keep a list of functions for which we have already built stubs
7482 in build_mips16_call_stub. */
7486 struct mips16_stub *next;
7491 static struct mips16_stub *mips16_stubs;
7493 /* Build a call stub for a mips16 call. A stub is needed if we are
7494 passing any floating point values which should go into the floating
7495 point registers. If we are, and the call turns out to be to a 32
7496 bit function, the stub will be used to move the values into the
7497 floating point registers before calling the 32 bit function. The
7498 linker will magically adjust the function call to either the 16 bit
7499 function or the 32 bit stub, depending upon where the function call
7500 is actually defined.
7502 Similarly, we need a stub if the return value might come back in a
7503 floating point register.
7505 RETVAL is the location of the return value, or null if this is
7506 a call rather than a call_value. FN is the address of the
7507 function and ARG_SIZE is the size of the arguments. FP_CODE
7508 is the code built by function_arg. This function returns a nonzero
7509 value if it builds the call instruction itself. */
7512 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7516 char *secname, *stubname;
7517 struct mips16_stub *l;
7518 tree stubid, stubdecl;
7522 /* We don't need to do anything if we aren't in mips16 mode, or if
7523 we were invoked with the -msoft-float option. */
7524 if (! TARGET_MIPS16 || ! mips16_hard_float)
7527 /* Figure out whether the value might come back in a floating point
7529 fpret = (retval != 0
7530 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7531 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7533 /* We don't need to do anything if there were no floating point
7534 arguments and the value will not be returned in a floating point
7536 if (fp_code == 0 && ! fpret)
7539 /* We don't need to do anything if this is a call to a special
7540 mips16 support function. */
7541 if (GET_CODE (fn) == SYMBOL_REF
7542 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7545 /* This code will only work for o32 and o64 abis. The other ABI's
7546 require more sophisticated support. */
7547 gcc_assert (TARGET_OLDABI);
7549 /* We can only handle SFmode and DFmode floating point return
7552 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
7554 /* If we're calling via a function pointer, then we must always call
7555 via a stub. There are magic stubs provided in libgcc.a for each
7556 of the required cases. Each of them expects the function address
7557 to arrive in register $2. */
7559 if (GET_CODE (fn) != SYMBOL_REF)
7565 /* ??? If this code is modified to support other ABI's, we need
7566 to handle PARALLEL return values here. */
7568 sprintf (buf, "__mips16_call_stub_%s%d",
7570 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7573 id = get_identifier (buf);
7574 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7576 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7578 if (retval == NULL_RTX)
7579 insn = gen_call_internal (stub_fn, arg_size);
7581 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7582 insn = emit_call_insn (insn);
7584 /* Put the register usage information on the CALL. */
7585 CALL_INSN_FUNCTION_USAGE (insn) =
7586 gen_rtx_EXPR_LIST (VOIDmode,
7587 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7588 CALL_INSN_FUNCTION_USAGE (insn));
7590 /* If we are handling a floating point return value, we need to
7591 save $18 in the function prologue. Putting a note on the
7592 call will mean that regs_ever_live[$18] will be true if the
7593 call is not eliminated, and we can check that in the prologue
7596 CALL_INSN_FUNCTION_USAGE (insn) =
7597 gen_rtx_EXPR_LIST (VOIDmode,
7598 gen_rtx_USE (VOIDmode,
7599 gen_rtx_REG (word_mode, 18)),
7600 CALL_INSN_FUNCTION_USAGE (insn));
7602 /* Return 1 to tell the caller that we've generated the call
7607 /* We know the function we are going to call. If we have already
7608 built a stub, we don't need to do anything further. */
7610 fnname = XSTR (fn, 0);
7611 for (l = mips16_stubs; l != NULL; l = l->next)
7612 if (strcmp (l->name, fnname) == 0)
7617 /* Build a special purpose stub. When the linker sees a
7618 function call in mips16 code, it will check where the target
7619 is defined. If the target is a 32 bit call, the linker will
7620 search for the section defined here. It can tell which
7621 symbol this section is associated with by looking at the
7622 relocation information (the name is unreliable, since this
7623 might be a static function). If such a section is found, the
7624 linker will redirect the call to the start of the magic
7627 If the function does not return a floating point value, the
7628 special stub section is named
7631 If the function does return a floating point value, the stub
7633 .mips16.call.fp.FNNAME
7636 secname = (char *) alloca (strlen (fnname) + 40);
7637 sprintf (secname, ".mips16.call.%s%s",
7640 stubname = (char *) alloca (strlen (fnname) + 20);
7641 sprintf (stubname, "__call_stub_%s%s",
7644 stubid = get_identifier (stubname);
7645 stubdecl = build_decl (FUNCTION_DECL, stubid,
7646 build_function_type (void_type_node, NULL_TREE));
7647 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7649 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7651 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7655 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7657 fprintf (asm_out_file, "%s%s",
7658 need_comma ? ", " : "",
7659 (f & 3) == 1 ? "float" : "double");
7662 fprintf (asm_out_file, ")\n");
7664 fprintf (asm_out_file, "\t.set\tnomips16\n");
7665 assemble_start_function (stubdecl, stubname);
7667 if (!FUNCTION_NAME_ALREADY_DECLARED)
7669 fputs ("\t.ent\t", asm_out_file);
7670 assemble_name (asm_out_file, stubname);
7671 fputs ("\n", asm_out_file);
7673 assemble_name (asm_out_file, stubname);
7674 fputs (":\n", asm_out_file);
7677 /* We build the stub code by hand. That's the only way we can
7678 do it, since we can't generate 32 bit code during a 16 bit
7681 /* We don't want the assembler to insert any nops here. */
7682 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7684 mips16_fp_args (asm_out_file, fp_code, 0);
7688 fprintf (asm_out_file, "\t.set\tnoat\n");
7689 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7691 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7692 fprintf (asm_out_file, "\t.set\tat\n");
7693 /* Unfortunately, we can't fill the jump delay slot. We
7694 can't fill with one of the mtc1 instructions, because the
7695 result is not available for one instruction, so if the
7696 very first instruction in the function refers to the
7697 register, it will see the wrong value. */
7698 fprintf (asm_out_file, "\tnop\n");
7702 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7703 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7704 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7705 /* As above, we can't fill the delay slot. */
7706 fprintf (asm_out_file, "\tnop\n");
7707 if (GET_MODE (retval) == SFmode)
7708 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7709 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7712 if (TARGET_BIG_ENDIAN)
7714 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7715 reg_names[GP_REG_FIRST + 2],
7716 reg_names[FP_REG_FIRST + 1]);
7717 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7718 reg_names[GP_REG_FIRST + 3],
7719 reg_names[FP_REG_FIRST + 0]);
7723 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7724 reg_names[GP_REG_FIRST + 2],
7725 reg_names[FP_REG_FIRST + 0]);
7726 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7727 reg_names[GP_REG_FIRST + 3],
7728 reg_names[FP_REG_FIRST + 1]);
7731 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7732 /* As above, we can't fill the delay slot. */
7733 fprintf (asm_out_file, "\tnop\n");
7736 fprintf (asm_out_file, "\t.set\treorder\n");
7738 #ifdef ASM_DECLARE_FUNCTION_SIZE
7739 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7742 if (!FUNCTION_NAME_ALREADY_DECLARED)
7744 fputs ("\t.end\t", asm_out_file);
7745 assemble_name (asm_out_file, stubname);
7746 fputs ("\n", asm_out_file);
7749 fprintf (asm_out_file, "\t.set\tmips16\n");
7751 /* Record this stub. */
7752 l = (struct mips16_stub *) xmalloc (sizeof *l);
7753 l->name = xstrdup (fnname);
7755 l->next = mips16_stubs;
7759 /* If we expect a floating point return value, but we've built a
7760 stub which does not expect one, then we're in trouble. We can't
7761 use the existing stub, because it won't handle the floating point
7762 value. We can't build a new stub, because the linker won't know
7763 which stub to use for the various calls in this object file.
7764 Fortunately, this case is illegal, since it means that a function
7765 was declared in two different ways in a single compilation. */
7766 if (fpret && ! l->fpret)
7767 error ("cannot handle inconsistent calls to %qs", fnname);
7769 /* If we are calling a stub which handles a floating point return
7770 value, we need to arrange to save $18 in the prologue. We do
7771 this by marking the function call as using the register. The
7772 prologue will later see that it is used, and emit code to save
7779 if (retval == NULL_RTX)
7780 insn = gen_call_internal (fn, arg_size);
7782 insn = gen_call_value_internal (retval, fn, arg_size);
7783 insn = emit_call_insn (insn);
7785 CALL_INSN_FUNCTION_USAGE (insn) =
7786 gen_rtx_EXPR_LIST (VOIDmode,
7787 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
7788 CALL_INSN_FUNCTION_USAGE (insn));
7790 /* Return 1 to tell the caller that we've generated the call
7795 /* Return 0 to let the caller generate the call insn. */
7799 /* An entry in the mips16 constant pool. VALUE is the pool constant,
7800 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
7802 struct mips16_constant {
7803 struct mips16_constant *next;
7806 enum machine_mode mode;
7809 /* Information about an incomplete mips16 constant pool. FIRST is the
7810 first constant, HIGHEST_ADDRESS is the highest address that the first
7811 byte of the pool can have, and INSN_ADDRESS is the current instruction
7814 struct mips16_constant_pool {
7815 struct mips16_constant *first;
7816 int highest_address;
7820 /* Add constant VALUE to POOL and return its label. MODE is the
7821 value's mode (used for CONST_INTs, etc.). */
7824 add_constant (struct mips16_constant_pool *pool,
7825 rtx value, enum machine_mode mode)
7827 struct mips16_constant **p, *c;
7828 bool first_of_size_p;
7830 /* See whether the constant is already in the pool. If so, return the
7831 existing label, otherwise leave P pointing to the place where the
7832 constant should be added.
7834 Keep the pool sorted in increasing order of mode size so that we can
7835 reduce the number of alignments needed. */
7836 first_of_size_p = true;
7837 for (p = &pool->first; *p != 0; p = &(*p)->next)
7839 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
7841 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
7843 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
7844 first_of_size_p = false;
7847 /* In the worst case, the constant needed by the earliest instruction
7848 will end up at the end of the pool. The entire pool must then be
7849 accessible from that instruction.
7851 When adding the first constant, set the pool's highest address to
7852 the address of the first out-of-range byte. Adjust this address
7853 downwards each time a new constant is added. */
7854 if (pool->first == 0)
7855 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
7856 is the address of the instruction with the lowest two bits clear.
7857 The base PC value for ld has the lowest three bits clear. Assume
7858 the worst case here. */
7859 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
7860 pool->highest_address -= GET_MODE_SIZE (mode);
7861 if (first_of_size_p)
7862 /* Take into account the worst possible padding due to alignment. */
7863 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
7865 /* Create a new entry. */
7866 c = (struct mips16_constant *) xmalloc (sizeof *c);
7869 c->label = gen_label_rtx ();
7876 /* Output constant VALUE after instruction INSN and return the last
7877 instruction emitted. MODE is the mode of the constant. */
7880 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
7882 switch (GET_MODE_CLASS (mode))
7886 rtx size = GEN_INT (GET_MODE_SIZE (mode));
7887 return emit_insn_after (gen_consttable_int (value, size), insn);
7891 return emit_insn_after (gen_consttable_float (value), insn);
7893 case MODE_VECTOR_FLOAT:
7894 case MODE_VECTOR_INT:
7897 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
7898 insn = dump_constants_1 (GET_MODE_INNER (mode),
7899 CONST_VECTOR_ELT (value, i), insn);
7909 /* Dump out the constants in CONSTANTS after INSN. */
7912 dump_constants (struct mips16_constant *constants, rtx insn)
7914 struct mips16_constant *c, *next;
7918 for (c = constants; c != NULL; c = next)
7920 /* If necessary, increase the alignment of PC. */
7921 if (align < GET_MODE_SIZE (c->mode))
7923 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
7924 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
7926 align = GET_MODE_SIZE (c->mode);
7928 insn = emit_label_after (c->label, insn);
7929 insn = dump_constants_1 (c->mode, c->value, insn);
7935 emit_barrier_after (insn);
7938 /* Return the length of instruction INSN. */
7941 mips16_insn_length (rtx insn)
7945 rtx body = PATTERN (insn);
7946 if (GET_CODE (body) == ADDR_VEC)
7947 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
7948 if (GET_CODE (body) == ADDR_DIFF_VEC)
7949 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
7951 return get_attr_length (insn);
7954 /* Rewrite *X so that constant pool references refer to the constant's
7955 label instead. DATA points to the constant pool structure. */
7958 mips16_rewrite_pool_refs (rtx *x, void *data)
7960 struct mips16_constant_pool *pool = data;
7961 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
7962 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
7963 get_pool_constant (*x),
7964 get_pool_mode (*x)));
7968 /* Build MIPS16 constant pools. */
7971 mips16_lay_out_constants (void)
7973 struct mips16_constant_pool pool;
7977 memset (&pool, 0, sizeof (pool));
7978 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7980 /* Rewrite constant pool references in INSN. */
7982 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
7984 pool.insn_address += mips16_insn_length (insn);
7986 if (pool.first != NULL)
7988 /* If there are no natural barriers between the first user of
7989 the pool and the highest acceptable address, we'll need to
7990 create a new instruction to jump around the constant pool.
7991 In the worst case, this instruction will be 4 bytes long.
7993 If it's too late to do this transformation after INSN,
7994 do it immediately before INSN. */
7995 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
7999 label = gen_label_rtx ();
8001 jump = emit_jump_insn_before (gen_jump (label), insn);
8002 JUMP_LABEL (jump) = label;
8003 LABEL_NUSES (label) = 1;
8004 barrier = emit_barrier_after (jump);
8006 emit_label_after (label, barrier);
8007 pool.insn_address += 4;
8010 /* See whether the constant pool is now out of range of the first
8011 user. If so, output the constants after the previous barrier.
8012 Note that any instructions between BARRIER and INSN (inclusive)
8013 will use negative offsets to refer to the pool. */
8014 if (pool.insn_address > pool.highest_address)
8016 dump_constants (pool.first, barrier);
8020 else if (BARRIER_P (insn))
8024 dump_constants (pool.first, get_last_insn ());
8027 /* A temporary variable used by for_each_rtx callbacks, etc. */
8028 static rtx mips_sim_insn;
8030 /* A structure representing the state of the processor pipeline.
8031 Used by the mips_sim_* family of functions. */
8033 /* The maximum number of instructions that can be issued in a cycle.
8034 (Caches mips_issue_rate.) */
8035 unsigned int issue_rate;
8037 /* The current simulation time. */
8040 /* How many more instructions can be issued in the current cycle. */
8041 unsigned int insns_left;
8043 /* LAST_SET[X].INSN is the last instruction to set register X.
8044 LAST_SET[X].TIME is the time at which that instruction was issued.
8045 INSN is null if no instruction has yet set register X. */
8049 } last_set[FIRST_PSEUDO_REGISTER];
8051 /* The pipeline's current DFA state. */
8055 /* Reset STATE to the initial simulation state. */
8058 mips_sim_reset (struct mips_sim *state)
8061 state->insns_left = state->issue_rate;
8062 memset (&state->last_set, 0, sizeof (state->last_set));
8063 state_reset (state->dfa_state);
8066 /* Initialize STATE before its first use. DFA_STATE points to an
8067 allocated but uninitialized DFA state. */
8070 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8072 state->issue_rate = mips_issue_rate ();
8073 state->dfa_state = dfa_state;
8074 mips_sim_reset (state);
8077 /* Advance STATE by one clock cycle. */
8080 mips_sim_next_cycle (struct mips_sim *state)
8083 state->insns_left = state->issue_rate;
8084 state_transition (state->dfa_state, 0);
8087 /* Advance simulation state STATE until instruction INSN can read
8091 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8095 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8096 if (state->last_set[REGNO (reg) + i].insn != 0)
8100 t = state->last_set[REGNO (reg) + i].time;
8101 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8102 while (state->time < t)
8103 mips_sim_next_cycle (state);
8107 /* A for_each_rtx callback. If *X is a register, advance simulation state
8108 DATA until mips_sim_insn can read the register's value. */
8111 mips_sim_wait_regs_2 (rtx *x, void *data)
8114 mips_sim_wait_reg (data, mips_sim_insn, *x);
8118 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8121 mips_sim_wait_regs_1 (rtx *x, void *data)
8123 for_each_rtx (x, mips_sim_wait_regs_2, data);
8126 /* Advance simulation state STATE until all of INSN's register
8127 dependencies are satisfied. */
8130 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8132 mips_sim_insn = insn;
8133 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8136 /* Advance simulation state STATE until the units required by
8137 instruction INSN are available. */
8140 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8144 tmp_state = alloca (state_size ());
8145 while (state->insns_left == 0
8146 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8147 state_transition (tmp_state, insn) >= 0))
8148 mips_sim_next_cycle (state);
8151 /* Advance simulation state STATE until INSN is ready to issue. */
8154 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8156 mips_sim_wait_regs (state, insn);
8157 mips_sim_wait_units (state, insn);
8160 /* mips_sim_insn has just set X. Update the LAST_SET array
8161 in simulation state DATA. */
8164 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8166 struct mips_sim *state;
8171 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8173 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8174 state->last_set[REGNO (x) + i].time = state->time;
8178 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8179 can issue immediately (i.e., that mips_sim_wait_insn has already
8183 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8185 state_transition (state->dfa_state, insn);
8186 state->insns_left--;
8188 mips_sim_insn = insn;
8189 note_stores (PATTERN (insn), mips_sim_record_set, state);
8192 /* Simulate issuing a NOP in state STATE. */
8195 mips_sim_issue_nop (struct mips_sim *state)
8197 if (state->insns_left == 0)
8198 mips_sim_next_cycle (state);
8199 state->insns_left--;
8202 /* Update simulation state STATE so that it's ready to accept the instruction
8203 after INSN. INSN should be part of the main rtl chain, not a member of a
8207 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8209 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8211 mips_sim_issue_nop (state);
8213 switch (GET_CODE (SEQ_BEGIN (insn)))
8217 /* We can't predict the processor state after a call or label. */
8218 mips_sim_reset (state);
8222 /* The delay slots of branch likely instructions are only executed
8223 when the branch is taken. Therefore, if the caller has simulated
8224 the delay slot instruction, STATE does not really reflect the state
8225 of the pipeline for the instruction after the delay slot. Also,
8226 branch likely instructions tend to incur a penalty when not taken,
8227 so there will probably be an extra delay between the branch and
8228 the instruction after the delay slot. */
8229 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8230 mips_sim_reset (state);
8238 /* The VR4130 pipeline issues aligned pairs of instructions together,
8239 but it stalls the second instruction if it depends on the first.
8240 In order to cut down the amount of logic required, this dependence
8241 check is not based on a full instruction decode. Instead, any non-SPECIAL
8242 instruction is assumed to modify the register specified by bits 20-16
8243 (which is usually the "rt" field).
8245 In beq, beql, bne and bnel instructions, the rt field is actually an
8246 input, so we can end up with a false dependence between the branch
8247 and its delay slot. If this situation occurs in instruction INSN,
8248 try to avoid it by swapping rs and rt. */
8251 vr4130_avoid_branch_rt_conflict (rtx insn)
8255 first = SEQ_BEGIN (insn);
8256 second = SEQ_END (insn);
8258 && NONJUMP_INSN_P (second)
8259 && GET_CODE (PATTERN (first)) == SET
8260 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8261 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8263 /* Check for the right kind of condition. */
8264 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8265 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8266 && REG_P (XEXP (cond, 0))
8267 && REG_P (XEXP (cond, 1))
8268 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8269 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8271 /* SECOND mentions the rt register but not the rs register. */
8272 rtx tmp = XEXP (cond, 0);
8273 XEXP (cond, 0) = XEXP (cond, 1);
8274 XEXP (cond, 1) = tmp;
8279 /* Implement -mvr4130-align. Go through each basic block and simulate the
8280 processor pipeline. If we find that a pair of instructions could execute
8281 in parallel, and the first of those instruction is not 8-byte aligned,
8282 insert a nop to make it aligned. */
8285 vr4130_align_insns (void)
8287 struct mips_sim state;
8288 rtx insn, subinsn, last, last2, next;
8293 /* LAST is the last instruction before INSN to have a nonzero length.
8294 LAST2 is the last such instruction before LAST. */
8298 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8301 mips_sim_init (&state, alloca (state_size ()));
8302 for (insn = get_insns (); insn != 0; insn = next)
8304 unsigned int length;
8306 next = NEXT_INSN (insn);
8308 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8309 This isn't really related to the alignment pass, but we do it on
8310 the fly to avoid a separate instruction walk. */
8311 vr4130_avoid_branch_rt_conflict (insn);
8313 if (USEFUL_INSN_P (insn))
8314 FOR_EACH_SUBINSN (subinsn, insn)
8316 mips_sim_wait_insn (&state, subinsn);
8318 /* If we want this instruction to issue in parallel with the
8319 previous one, make sure that the previous instruction is
8320 aligned. There are several reasons why this isn't worthwhile
8321 when the second instruction is a call:
8323 - Calls are less likely to be performance critical,
8324 - There's a good chance that the delay slot can execute
8325 in parallel with the call.
8326 - The return address would then be unaligned.
8328 In general, if we're going to insert a nop between instructions
8329 X and Y, it's better to insert it immediately after X. That
8330 way, if the nop makes Y aligned, it will also align any labels
8332 if (state.insns_left != state.issue_rate
8333 && !CALL_P (subinsn))
8335 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8337 /* SUBINSN is the first instruction in INSN and INSN is
8338 aligned. We want to align the previous instruction
8339 instead, so insert a nop between LAST2 and LAST.
8341 Note that LAST could be either a single instruction
8342 or a branch with a delay slot. In the latter case,
8343 LAST, like INSN, is already aligned, but the delay
8344 slot must have some extra delay that stops it from
8345 issuing at the same time as the branch. We therefore
8346 insert a nop before the branch in order to align its
8348 emit_insn_after (gen_nop (), last2);
8351 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8353 /* SUBINSN is the delay slot of INSN, but INSN is
8354 currently unaligned. Insert a nop between
8355 LAST and INSN to align it. */
8356 emit_insn_after (gen_nop (), last);
8360 mips_sim_issue_insn (&state, subinsn);
8362 mips_sim_finish_insn (&state, insn);
8364 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8365 length = get_attr_length (insn);
8368 /* If the instruction is an asm statement or multi-instruction
8369 mips.md patern, the length is only an estimate. Insert an
8370 8 byte alignment after it so that the following instructions
8371 can be handled correctly. */
8372 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8373 && (recog_memoized (insn) < 0 || length >= 8))
8375 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8376 next = NEXT_INSN (next);
8377 mips_sim_next_cycle (&state);
8380 else if (length & 4)
8381 aligned_p = !aligned_p;
8386 /* See whether INSN is an aligned label. */
8387 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8393 /* Subroutine of mips_reorg. If there is a hazard between INSN
8394 and a previous instruction, avoid it by inserting nops after
8397 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8398 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8399 before using the value of that register. *HILO_DELAY counts the
8400 number of instructions since the last hilo hazard (that is,
8401 the number of instructions since the last mflo or mfhi).
8403 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8404 for the next instruction.
8406 LO_REG is an rtx for the LO register, used in dependence checking. */
8409 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8410 rtx *delayed_reg, rtx lo_reg)
8418 pattern = PATTERN (insn);
8420 /* Do not put the whole function in .set noreorder if it contains
8421 an asm statement. We don't know whether there will be hazards
8422 between the asm statement and the gcc-generated code. */
8423 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8424 cfun->machine->all_noreorder_p = false;
8426 /* Ignore zero-length instructions (barriers and the like). */
8427 ninsns = get_attr_length (insn) / 4;
8431 /* Work out how many nops are needed. Note that we only care about
8432 registers that are explicitly mentioned in the instruction's pattern.
8433 It doesn't matter that calls use the argument registers or that they
8434 clobber hi and lo. */
8435 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8436 nops = 2 - *hilo_delay;
8437 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8442 /* Insert the nops between this instruction and the previous one.
8443 Each new nop takes us further from the last hilo hazard. */
8444 *hilo_delay += nops;
8446 emit_insn_after (gen_hazard_nop (), after);
8448 /* Set up the state for the next instruction. */
8449 *hilo_delay += ninsns;
8451 if (INSN_CODE (insn) >= 0)
8452 switch (get_attr_hazard (insn))
8462 set = single_set (insn);
8463 gcc_assert (set != 0);
8464 *delayed_reg = SET_DEST (set);
8470 /* Go through the instruction stream and insert nops where necessary.
8471 See if the whole function can then be put into .set noreorder &
8475 mips_avoid_hazards (void)
8477 rtx insn, last_insn, lo_reg, delayed_reg;
8480 /* Force all instructions to be split into their final form. */
8481 split_all_insns_noflow ();
8483 /* Recalculate instruction lengths without taking nops into account. */
8484 cfun->machine->ignore_hazard_length_p = true;
8485 shorten_branches (get_insns ());
8487 cfun->machine->all_noreorder_p = true;
8489 /* Profiled functions can't be all noreorder because the profiler
8490 support uses assembler macros. */
8491 if (current_function_profile)
8492 cfun->machine->all_noreorder_p = false;
8494 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8495 we rely on the assembler to work around some errata. */
8496 if (TARGET_FIX_VR4120)
8497 cfun->machine->all_noreorder_p = false;
8499 /* The same is true for -mfix-vr4130 if we might generate mflo or
8500 mfhi instructions. Note that we avoid using mflo and mfhi if
8501 the VR4130 macc and dmacc instructions are available instead;
8502 see the *mfhilo_{si,di}_macc patterns. */
8503 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8504 cfun->machine->all_noreorder_p = false;
8509 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8511 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8514 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8515 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8516 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8517 &hilo_delay, &delayed_reg, lo_reg);
8519 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8520 &delayed_reg, lo_reg);
8527 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8533 mips16_lay_out_constants ();
8534 else if (TARGET_EXPLICIT_RELOCS)
8536 if (mips_flag_delayed_branch)
8537 dbr_schedule (get_insns (), dump_file);
8538 mips_avoid_hazards ();
8539 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8540 vr4130_align_insns ();
8544 /* This function does three things:
8546 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8547 - Register the mips16 hardware floating point stubs.
8548 - Register the gofast functions if selected using --enable-gofast. */
8550 #include "config/gofast.h"
8553 mips_init_libfuncs (void)
8555 if (TARGET_FIX_VR4120)
8557 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8558 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8561 if (TARGET_MIPS16 && mips16_hard_float)
8563 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8564 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8565 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8566 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8568 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8569 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8570 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8571 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8572 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8573 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8575 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8576 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8578 if (TARGET_DOUBLE_FLOAT)
8580 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8581 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8582 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8583 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8585 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8586 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8587 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8588 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8589 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8590 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8592 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8593 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8595 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8596 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8600 gofast_maybe_init_libfuncs ();
8603 /* Return a number assessing the cost of moving a register in class
8604 FROM to class TO. The classes are expressed using the enumeration
8605 values such as `GENERAL_REGS'. A value of 2 is the default; other
8606 values are interpreted relative to that.
8608 It is not required that the cost always equal 2 when FROM is the
8609 same as TO; on some machines it is expensive to move between
8610 registers if they are not general registers.
8612 If reload sees an insn consisting of a single `set' between two
8613 hard registers, and if `REGISTER_MOVE_COST' applied to their
8614 classes returns a value of 2, reload does not check to ensure that
8615 the constraints of the insn are met. Setting a cost of other than
8616 2 will allow reload to verify that the constraints are met. You
8617 should do this if the `movM' pattern's constraints do not allow
8620 ??? We make the cost of moving from HI/LO into general
8621 registers the same as for one of moving general registers to
8622 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8623 pseudo to HI/LO. This might hurt optimizations though, it
8624 isn't clear if it is wise. And it might not work in all cases. We
8625 could solve the DImode LO reg problem by using a multiply, just
8626 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8627 problem by using divide instructions. divu puts the remainder in
8628 the HI reg, so doing a divide by -1 will move the value in the HI
8629 reg for all values except -1. We could handle that case by using a
8630 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8631 a compare/branch to test the input value to see which instruction
8632 we need to use. This gets pretty messy, but it is feasible. */
8635 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8636 enum reg_class to, enum reg_class from)
8638 if (from == M16_REGS && GR_REG_CLASS_P (to))
8640 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8642 else if (GR_REG_CLASS_P (from))
8646 else if (to == M16_NA_REGS)
8648 else if (GR_REG_CLASS_P (to))
8655 else if (to == FP_REGS)
8657 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8664 else if (COP_REG_CLASS_P (to))
8668 } /* GR_REG_CLASS_P (from) */
8669 else if (from == FP_REGS)
8671 if (GR_REG_CLASS_P (to))
8673 else if (to == FP_REGS)
8675 else if (to == ST_REGS)
8677 } /* from == FP_REGS */
8678 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8680 if (GR_REG_CLASS_P (to))
8687 } /* from == HI_REG, etc. */
8688 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8690 else if (COP_REG_CLASS_P (from))
8693 } /* COP_REG_CLASS_P (from) */
8700 /* Return the length of INSN. LENGTH is the initial length computed by
8701 attributes in the machine-description file. */
8704 mips_adjust_insn_length (rtx insn, int length)
8706 /* A unconditional jump has an unfilled delay slot if it is not part
8707 of a sequence. A conditional jump normally has a delay slot, but
8708 does not on MIPS16. */
8709 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
8712 /* See how many nops might be needed to avoid hardware hazards. */
8713 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8714 switch (get_attr_hazard (insn))
8728 /* All MIPS16 instructions are a measly two bytes. */
8736 /* Return an asm sequence to start a noat block and load the address
8737 of a label into $1. */
8740 mips_output_load_label (void)
8742 if (TARGET_EXPLICIT_RELOCS)
8746 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8749 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8752 if (ISA_HAS_LOAD_DELAY)
8753 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8754 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8758 if (Pmode == DImode)
8759 return "%[dla\t%@,%0";
8761 return "%[la\t%@,%0";
8766 /* Output assembly instructions to peform a conditional branch.
8768 INSN is the branch instruction. OPERANDS[0] is the condition.
8769 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8770 of the first operand to the condition. If TWO_OPERANDS_P is
8771 nonzero the comparison takes two operands; OPERANDS[3] will be the
8774 If INVERTED_P is nonzero we are to branch if the condition does
8775 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8777 LENGTH is the length (in bytes) of the sequence we are to generate.
8778 That tells us whether to generate a simple conditional branch, or a
8779 reversed conditional branch around a `jr' instruction. */
8781 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8782 int float_p, int inverted_p, int length)
8784 static char buffer[200];
8785 /* The kind of comparison we are doing. */
8786 enum rtx_code code = GET_CODE (operands[0]);
8787 /* Nonzero if the opcode for the comparison needs a `z' indicating
8788 that it is a comparison against zero. */
8790 /* A string to use in the assembly output to represent the first
8792 const char *op1 = "%z2";
8793 /* A string to use in the assembly output to represent the second
8794 operand. Use the hard-wired zero register if there's no second
8796 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
8797 /* The operand-printing string for the comparison. */
8798 const char *const comp = (float_p ? "%F0" : "%C0");
8799 /* The operand-printing string for the inverted comparison. */
8800 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
8802 /* The MIPS processors (for levels of the ISA at least two), have
8803 "likely" variants of each branch instruction. These instructions
8804 annul the instruction in the delay slot if the branch is not
8806 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8808 if (!two_operands_p)
8810 /* To compute whether than A > B, for example, we normally
8811 subtract B from A and then look at the sign bit. But, if we
8812 are doing an unsigned comparison, and B is zero, we don't
8813 have to do the subtraction. Instead, we can just check to
8814 see if A is nonzero. Thus, we change the CODE here to
8815 reflect the simpler comparison operation. */
8827 /* A condition which will always be true. */
8833 /* A condition which will always be false. */
8839 /* Not a special case. */
8844 /* Relative comparisons are always done against zero. But
8845 equality comparisons are done between two operands, and therefore
8846 do not require a `z' in the assembly language output. */
8847 need_z_p = (!float_p && code != EQ && code != NE);
8848 /* For comparisons against zero, the zero is not provided
8853 /* Begin by terminating the buffer. That way we can always use
8854 strcat to add to it. */
8861 /* Just a simple conditional branch. */
8863 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
8864 inverted_p ? inverted_comp : comp);
8866 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
8867 inverted_p ? inverted_comp : comp,
8868 need_z_p ? "z" : "",
8878 /* Generate a reversed conditional branch around ` j'
8891 If the original branch was a likely branch, the delay slot
8892 must be executed only if the branch is taken, so generate:
8904 When generating PIC, instead of:
8917 rtx target = gen_label_rtx ();
8919 orig_target = operands[1];
8920 operands[1] = target;
8921 /* Generate the reversed comparison. This takes four
8924 sprintf (buffer, "%%*b%s\t%%Z2%%1",
8925 inverted_p ? comp : inverted_comp);
8927 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
8928 inverted_p ? comp : inverted_comp,
8929 need_z_p ? "z" : "",
8932 output_asm_insn (buffer, operands);
8934 if (length != 16 && length != 28 && ! mips_branch_likely)
8936 /* Output delay slot instruction. */
8937 rtx insn = final_sequence;
8938 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8940 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8943 output_asm_insn ("%#", 0);
8946 output_asm_insn ("j\t%0", &orig_target);
8949 output_asm_insn (mips_output_load_label (), &orig_target);
8950 output_asm_insn ("jr\t%@%]", 0);
8953 if (length != 16 && length != 28 && mips_branch_likely)
8955 /* Output delay slot instruction. */
8956 rtx insn = final_sequence;
8957 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8959 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8962 output_asm_insn ("%#", 0);
8964 (*targetm.asm_out.internal_label) (asm_out_file, "L",
8965 CODE_LABEL_NUMBER (target));
8978 /* Used to output div or ddiv instruction DIVISION, which has the operands
8979 given by OPERANDS. Add in a divide-by-zero check if needed.
8981 When working around R4000 and R4400 errata, we need to make sure that
8982 the division is not immediately followed by a shift[1][2]. We also
8983 need to stop the division from being put into a branch delay slot[3].
8984 The easiest way to avoid both problems is to add a nop after the
8985 division. When a divide-by-zero check is needed, this nop can be
8986 used to fill the branch delay slot.
8988 [1] If a double-word or a variable shift executes immediately
8989 after starting an integer division, the shift may give an
8990 incorrect result. See quotations of errata #16 and #28 from
8991 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
8992 in mips.md for details.
8994 [2] A similar bug to [1] exists for all revisions of the
8995 R4000 and the R4400 when run in an MC configuration.
8996 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
8998 "19. In this following sequence:
9000 ddiv (or ddivu or div or divu)
9001 dsll32 (or dsrl32, dsra32)
9003 if an MPT stall occurs, while the divide is slipping the cpu
9004 pipeline, then the following double shift would end up with an
9007 Workaround: The compiler needs to avoid generating any
9008 sequence with divide followed by extended double shift."
9010 This erratum is also present in "MIPS R4400MC Errata, Processor
9011 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9012 & 3.0" as errata #10 and #4, respectively.
9014 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9015 (also valid for MIPS R4000MC processors):
9017 "52. R4000SC: This bug does not apply for the R4000PC.
9019 There are two flavors of this bug:
9021 1) If the instruction just after divide takes an RF exception
9022 (tlb-refill, tlb-invalid) and gets an instruction cache
9023 miss (both primary and secondary) and the line which is
9024 currently in secondary cache at this index had the first
9025 data word, where the bits 5..2 are set, then R4000 would
9026 get a wrong result for the div.
9031 ------------------- # end-of page. -tlb-refill
9036 ------------------- # end-of page. -tlb-invalid
9039 2) If the divide is in the taken branch delay slot, where the
9040 target takes RF exception and gets an I-cache miss for the
9041 exception vector or where I-cache miss occurs for the
9042 target address, under the above mentioned scenarios, the
9043 div would get wrong results.
9046 j r2 # to next page mapped or unmapped
9047 div r8,r9 # this bug would be there as long
9048 # as there is an ICache miss and
9049 nop # the "data pattern" is present
9052 beq r0, r0, NextPage # to Next page
9056 This bug is present for div, divu, ddiv, and ddivu
9059 Workaround: For item 1), OS could make sure that the next page
9060 after the divide instruction is also mapped. For item 2), the
9061 compiler could make sure that the divide instruction is not in
9062 the branch delay slot."
9064 These processors have PRId values of 0x00004220 and 0x00004300 for
9065 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9068 mips_output_division (const char *division, rtx *operands)
9073 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9075 output_asm_insn (s, operands);
9078 if (TARGET_CHECK_ZERO_DIV)
9082 output_asm_insn (s, operands);
9083 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9085 else if (GENERATE_DIVIDE_TRAPS)
9087 output_asm_insn (s, operands);
9092 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9093 output_asm_insn (s, operands);
9094 s = "break\t7%)\n1:";
9100 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9101 with a final "000" replaced by "k". Ignore case.
9103 Note: this function is shared between GCC and GAS. */
9106 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9108 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9109 given++, canonical++;
9111 return ((*given == 0 && *canonical == 0)
9112 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9116 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9117 CPU name. We've traditionally allowed a lot of variation here.
9119 Note: this function is shared between GCC and GAS. */
9122 mips_matching_cpu_name_p (const char *canonical, const char *given)
9124 /* First see if the name matches exactly, or with a final "000"
9126 if (mips_strict_matching_cpu_name_p (canonical, given))
9129 /* If not, try comparing based on numerical designation alone.
9130 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9131 if (TOLOWER (*given) == 'r')
9133 if (!ISDIGIT (*given))
9136 /* Skip over some well-known prefixes in the canonical name,
9137 hoping to find a number there too. */
9138 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9140 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9142 else if (TOLOWER (canonical[0]) == 'r')
9145 return mips_strict_matching_cpu_name_p (canonical, given);
9149 /* Return the mips_cpu_info entry for the processor or ISA given
9150 by CPU_STRING. Return null if the string isn't recognized.
9152 A similar function exists in GAS. */
9154 static const struct mips_cpu_info *
9155 mips_parse_cpu (const char *cpu_string)
9157 const struct mips_cpu_info *p;
9160 /* In the past, we allowed upper-case CPU names, but it doesn't
9161 work well with the multilib machinery. */
9162 for (s = cpu_string; *s != 0; s++)
9165 warning (0, "the cpu name must be lower case");
9169 /* 'from-abi' selects the most compatible architecture for the given
9170 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9171 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9172 version. Look first at the -mgp options, if given, otherwise base
9173 the choice on MASK_64BIT in TARGET_DEFAULT. */
9174 if (strcasecmp (cpu_string, "from-abi") == 0)
9175 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9176 : ABI_NEEDS_64BIT_REGS ? 3
9177 : (TARGET_64BIT ? 3 : 1));
9179 /* 'default' has traditionally been a no-op. Probably not very useful. */
9180 if (strcasecmp (cpu_string, "default") == 0)
9183 for (p = mips_cpu_info_table; p->name != 0; p++)
9184 if (mips_matching_cpu_name_p (p->name, cpu_string))
9191 /* Return the processor associated with the given ISA level, or null
9192 if the ISA isn't valid. */
9194 static const struct mips_cpu_info *
9195 mips_cpu_info_from_isa (int isa)
9197 const struct mips_cpu_info *p;
9199 for (p = mips_cpu_info_table; p->name != 0; p++)
9206 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9207 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9208 they only hold condition code modes, and CCmode is always considered to
9209 be 4 bytes wide. All other registers are word sized. */
9212 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9214 if (ST_REG_P (regno))
9215 return ((GET_MODE_SIZE (mode) + 3) / 4);
9216 else if (! FP_REG_P (regno))
9217 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9219 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9222 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9223 all BLKmode objects are returned in memory. Under the new (N32 and
9224 64-bit MIPS ABIs) small structures are returned in a register.
9225 Objects with varying size must still be returned in memory, of
9229 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9232 return (TYPE_MODE (type) == BLKmode);
9234 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9235 || (int_size_in_bytes (type) == -1));
9239 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9241 return !TARGET_OLDABI;
9244 /* Return true if INSN is a multiply-add or multiply-subtract
9245 instruction and PREV assigns to the accumulator operand. */
9248 mips_linked_madd_p (rtx prev, rtx insn)
9252 x = single_set (insn);
9258 if (GET_CODE (x) == PLUS
9259 && GET_CODE (XEXP (x, 0)) == MULT
9260 && reg_set_p (XEXP (x, 1), prev))
9263 if (GET_CODE (x) == MINUS
9264 && GET_CODE (XEXP (x, 1)) == MULT
9265 && reg_set_p (XEXP (x, 0), prev))
9271 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9272 that may clobber hi or lo. */
9274 static rtx mips_macc_chains_last_hilo;
9276 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9277 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9280 mips_macc_chains_record (rtx insn)
9282 if (get_attr_may_clobber_hilo (insn))
9283 mips_macc_chains_last_hilo = insn;
9286 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9287 has NREADY elements, looking for a multiply-add or multiply-subtract
9288 instruction that is cumulative with mips_macc_chains_last_hilo.
9289 If there is one, promote it ahead of anything else that might
9290 clobber hi or lo. */
9293 mips_macc_chains_reorder (rtx *ready, int nready)
9297 if (mips_macc_chains_last_hilo != 0)
9298 for (i = nready - 1; i >= 0; i--)
9299 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9301 for (j = nready - 1; j > i; j--)
9302 if (recog_memoized (ready[j]) >= 0
9303 && get_attr_may_clobber_hilo (ready[j]))
9305 mips_promote_ready (ready, i, j);
9312 /* The last instruction to be scheduled. */
9314 static rtx vr4130_last_insn;
9316 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9317 points to an rtx that is initially an instruction. Nullify the rtx
9318 if the instruction uses the value of register X. */
9321 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9323 rtx *insn_ptr = data;
9326 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9330 /* Return true if there is true register dependence between vr4130_last_insn
9334 vr4130_true_reg_dependence_p (rtx insn)
9336 note_stores (PATTERN (vr4130_last_insn),
9337 vr4130_true_reg_dependence_p_1, &insn);
9341 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9342 the ready queue and that INSN2 is the instruction after it, return
9343 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9344 in which INSN1 and INSN2 can probably issue in parallel, but for
9345 which (INSN2, INSN1) should be less sensitive to instruction
9346 alignment than (INSN1, INSN2). See 4130.md for more details. */
9349 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9353 /* Check for the following case:
9355 1) there is some other instruction X with an anti dependence on INSN1;
9356 2) X has a higher priority than INSN2; and
9357 3) X is an arithmetic instruction (and thus has no unit restrictions).
9359 If INSN1 is the last instruction blocking X, it would better to
9360 choose (INSN1, X) over (INSN2, INSN1). */
9361 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9362 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9363 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9364 && recog_memoized (XEXP (dep, 0)) >= 0
9365 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9368 if (vr4130_last_insn != 0
9369 && recog_memoized (insn1) >= 0
9370 && recog_memoized (insn2) >= 0)
9372 /* See whether INSN1 and INSN2 use different execution units,
9373 or if they are both ALU-type instructions. If so, they can
9374 probably execute in parallel. */
9375 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9376 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9377 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9379 /* If only one of the instructions has a dependence on
9380 vr4130_last_insn, prefer to schedule the other one first. */
9381 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9382 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9386 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9387 is not an ALU-type instruction and if INSN1 uses the same
9388 execution unit. (Note that if this condition holds, we already
9389 know that INSN2 uses a different execution unit.) */
9390 if (class1 != VR4130_CLASS_ALU
9391 && recog_memoized (vr4130_last_insn) >= 0
9392 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9399 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9400 queue with at least two instructions. Swap the first two if
9401 vr4130_swap_insns_p says that it could be worthwhile. */
9404 vr4130_reorder (rtx *ready, int nready)
9406 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9407 mips_promote_ready (ready, nready - 2, nready - 1);
9410 /* Remove the instruction at index LOWER from ready queue READY and
9411 reinsert it in front of the instruction at index HIGHER. LOWER must
9415 mips_promote_ready (rtx *ready, int lower, int higher)
9420 new_head = ready[lower];
9421 for (i = lower; i < higher; i++)
9422 ready[i] = ready[i + 1];
9423 ready[i] = new_head;
9426 /* Implement TARGET_SCHED_REORDER. */
9429 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9430 rtx *ready, int *nreadyp, int cycle)
9432 if (!reload_completed && TUNE_MACC_CHAINS)
9435 mips_macc_chains_last_hilo = 0;
9437 mips_macc_chains_reorder (ready, *nreadyp);
9439 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9442 vr4130_last_insn = 0;
9444 vr4130_reorder (ready, *nreadyp);
9446 return mips_issue_rate ();
9449 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9452 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9455 switch (GET_CODE (PATTERN (insn)))
9459 /* Don't count USEs and CLOBBERs against the issue rate. */
9464 if (!reload_completed && TUNE_MACC_CHAINS)
9465 mips_macc_chains_record (insn);
9466 vr4130_last_insn = insn;
9472 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9473 dependencies have no cost. */
9476 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9477 rtx dep ATTRIBUTE_UNUSED, int cost)
9479 if (REG_NOTE_KIND (link) != 0)
9484 /* Return the number of instructions that can be issued per cycle. */
9487 mips_issue_rate (void)
9491 case PROCESSOR_R4130:
9492 case PROCESSOR_R5400:
9493 case PROCESSOR_R5500:
9494 case PROCESSOR_R7000:
9495 case PROCESSOR_R9000:
9499 /* This is actually 4, but we get better performance if we claim 3.
9500 This is partly because of unwanted speculative code motion with the
9501 larger number, and partly because in most common cases we can't
9502 reach the theoretical max of 4. */
9510 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9511 be as wide as the scheduling freedom in the DFA. */
9514 mips_multipass_dfa_lookahead (void)
9516 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9517 if (mips_tune == PROCESSOR_SB1)
9523 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9524 return the first operand of the associated "pref" or "prefx" insn. */
9527 mips_prefetch_cookie (rtx write, rtx locality)
9529 /* store_streamed / load_streamed. */
9530 if (INTVAL (locality) <= 0)
9531 return GEN_INT (INTVAL (write) + 4);
9534 if (INTVAL (locality) <= 2)
9537 /* store_retained / load_retained. */
9538 return GEN_INT (INTVAL (write) + 6);
9541 /* MIPS builtin function support. */
9543 struct builtin_description
9545 /* The code of the main .md file instruction. See mips_builtin_type
9546 for more information. */
9547 enum insn_code icode;
9549 /* The floating-point comparison code to use with ICODE, if any. */
9550 enum mips_fp_condition cond;
9552 /* The name of the builtin function. */
9555 /* Specifies how the function should be expanded. */
9556 enum mips_builtin_type builtin_type;
9558 /* The function's prototype. */
9559 enum mips_function_type function_type;
9561 /* The target flags required for this function. */
9565 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9566 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9567 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9568 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9569 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9571 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9573 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9574 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9575 "__builtin_mips_" #INSN "_" #COND "_s", \
9576 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9577 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9578 "__builtin_mips_" #INSN "_" #COND "_d", \
9579 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9581 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9582 The lower and upper forms require TARGET_FLAGS while the any and all
9583 forms require MASK_MIPS3D. */
9584 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9585 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9586 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9587 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9588 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9589 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9590 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9591 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9592 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9593 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9594 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9595 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9596 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9598 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9599 require MASK_MIPS3D. */
9600 #define CMP_4S_BUILTINS(INSN, COND) \
9601 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9602 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9603 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9605 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9606 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9607 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9610 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9611 instruction requires TARGET_FLAGS. */
9612 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9613 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9614 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9615 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9617 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9618 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9619 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9622 /* Define all the builtins related to c.cond.fmt condition COND. */
9623 #define CMP_BUILTINS(COND) \
9624 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9625 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9626 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9627 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9628 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9629 CMP_4S_BUILTINS (c, COND), \
9630 CMP_4S_BUILTINS (cabs, COND)
9632 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
9633 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
9635 static const struct builtin_description mips_bdesc[] =
9637 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9638 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9639 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9640 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9641 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
9642 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9643 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9644 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9646 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
9647 MASK_PAIRED_SINGLE_FLOAT),
9648 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9649 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9650 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9651 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9653 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9654 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9655 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9656 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9657 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9658 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9660 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9661 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9662 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9663 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9664 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9665 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9667 MIPS_FP_CONDITIONS (CMP_BUILTINS)
9670 /* Builtin functions for the SB-1 processor. */
9672 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
9674 static const struct builtin_description sb1_bdesc[] =
9676 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
9679 /* This helps provide a mapping from builtin function codes to bdesc
9684 /* The builtin function table that this entry describes. */
9685 const struct builtin_description *bdesc;
9687 /* The number of entries in the builtin function table. */
9690 /* The target processor that supports these builtin functions.
9691 PROCESSOR_DEFAULT means we enable them for all processors. */
9692 enum processor_type proc;
9695 static const struct bdesc_map bdesc_arrays[] =
9697 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_DEFAULT },
9698 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }
9701 /* Take the head of argument list *ARGLIST and convert it into a form
9702 suitable for input operand OP of instruction ICODE. Return the value
9703 and point *ARGLIST at the next element of the list. */
9706 mips_prepare_builtin_arg (enum insn_code icode,
9707 unsigned int op, tree *arglist)
9710 enum machine_mode mode;
9712 value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0);
9713 mode = insn_data[icode].operand[op].mode;
9714 if (!insn_data[icode].operand[op].predicate (value, mode))
9715 value = copy_to_mode_reg (mode, value);
9717 *arglist = TREE_CHAIN (*arglist);
9721 /* Return an rtx suitable for output operand OP of instruction ICODE.
9722 If TARGET is non-null, try to use it where possible. */
9725 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
9727 enum machine_mode mode;
9729 mode = insn_data[icode].operand[op].mode;
9730 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
9731 target = gen_reg_rtx (mode);
9736 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
9739 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9740 enum machine_mode mode ATTRIBUTE_UNUSED,
9741 int ignore ATTRIBUTE_UNUSED)
9743 enum insn_code icode;
9744 enum mips_builtin_type type;
9745 tree fndecl, arglist;
9747 const struct builtin_description *bdesc;
9748 const struct bdesc_map *m;
9750 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9751 arglist = TREE_OPERAND (exp, 1);
9752 fcode = DECL_FUNCTION_CODE (fndecl);
9755 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
9757 if (fcode < m->size)
9760 icode = bdesc[fcode].icode;
9761 type = bdesc[fcode].builtin_type;
9771 case MIPS_BUILTIN_DIRECT:
9772 return mips_expand_builtin_direct (icode, target, arglist);
9774 case MIPS_BUILTIN_MOVT:
9775 case MIPS_BUILTIN_MOVF:
9776 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
9779 case MIPS_BUILTIN_CMP_ANY:
9780 case MIPS_BUILTIN_CMP_ALL:
9781 case MIPS_BUILTIN_CMP_UPPER:
9782 case MIPS_BUILTIN_CMP_LOWER:
9783 case MIPS_BUILTIN_CMP_SINGLE:
9784 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
9792 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
9795 mips_init_builtins (void)
9797 const struct builtin_description *d;
9798 const struct bdesc_map *m;
9799 tree types[(int) MIPS_MAX_FTYPE_MAX];
9800 tree V2SF_type_node;
9801 unsigned int offset;
9803 /* We have only builtins for -mpaired-single and -mips3d. */
9804 if (!TARGET_PAIRED_SINGLE_FLOAT)
9807 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
9809 types[MIPS_V2SF_FTYPE_V2SF]
9810 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
9812 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
9813 = build_function_type_list (V2SF_type_node,
9814 V2SF_type_node, V2SF_type_node, NULL_TREE);
9816 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
9817 = build_function_type_list (V2SF_type_node,
9818 V2SF_type_node, V2SF_type_node,
9819 integer_type_node, NULL_TREE);
9821 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
9822 = build_function_type_list (V2SF_type_node,
9823 V2SF_type_node, V2SF_type_node,
9824 V2SF_type_node, V2SF_type_node, NULL_TREE);
9826 types[MIPS_V2SF_FTYPE_SF_SF]
9827 = build_function_type_list (V2SF_type_node,
9828 float_type_node, float_type_node, NULL_TREE);
9830 types[MIPS_INT_FTYPE_V2SF_V2SF]
9831 = build_function_type_list (integer_type_node,
9832 V2SF_type_node, V2SF_type_node, NULL_TREE);
9834 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
9835 = build_function_type_list (integer_type_node,
9836 V2SF_type_node, V2SF_type_node,
9837 V2SF_type_node, V2SF_type_node, NULL_TREE);
9839 types[MIPS_INT_FTYPE_SF_SF]
9840 = build_function_type_list (integer_type_node,
9841 float_type_node, float_type_node, NULL_TREE);
9843 types[MIPS_INT_FTYPE_DF_DF]
9844 = build_function_type_list (integer_type_node,
9845 double_type_node, double_type_node, NULL_TREE);
9847 types[MIPS_SF_FTYPE_V2SF]
9848 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
9850 types[MIPS_SF_FTYPE_SF]
9851 = build_function_type_list (float_type_node,
9852 float_type_node, NULL_TREE);
9854 types[MIPS_SF_FTYPE_SF_SF]
9855 = build_function_type_list (float_type_node,
9856 float_type_node, float_type_node, NULL_TREE);
9858 types[MIPS_DF_FTYPE_DF]
9859 = build_function_type_list (double_type_node,
9860 double_type_node, NULL_TREE);
9862 types[MIPS_DF_FTYPE_DF_DF]
9863 = build_function_type_list (double_type_node,
9864 double_type_node, double_type_node, NULL_TREE);
9866 /* Iterate through all of the bdesc arrays, initializing all of the
9867 builtin functions. */
9870 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
9872 if (m->proc == PROCESSOR_DEFAULT || (m->proc == mips_arch))
9873 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
9874 if ((d->target_flags & target_flags) == d->target_flags)
9875 lang_hooks.builtin_function (d->name, types[d->function_type],
9876 d - m->bdesc + offset,
9877 BUILT_IN_MD, NULL, NULL);
9882 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
9883 .md pattern and ARGLIST is the list of function arguments. TARGET,
9884 if nonnull, suggests a good place to put the result. */
9887 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist)
9889 rtx ops[MAX_RECOG_OPERANDS];
9892 target = mips_prepare_builtin_target (icode, 0, target);
9893 for (i = 1; i < insn_data[icode].n_operands; i++)
9894 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
9896 switch (insn_data[icode].n_operands)
9899 emit_insn (GEN_FCN (icode) (target, ops[1]));
9903 emit_insn (GEN_FCN (icode) (target, ops[1], ops[2]));
9907 emit_insn (GEN_FCN (icode) (target, ops[1], ops[2], ops[3]));
9916 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
9917 function (TYPE says which). ARGLIST is the list of arguments to the
9918 function, ICODE is the instruction that should be used to compare
9919 the first two arguments, and COND is the condition it should test.
9920 TARGET, if nonnull, suggests a good place to put the result. */
9923 mips_expand_builtin_movtf (enum mips_builtin_type type,
9924 enum insn_code icode, enum mips_fp_condition cond,
9925 rtx target, tree arglist)
9927 rtx cmp_result, op0, op1;
9929 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
9930 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
9931 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
9932 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
9934 icode = CODE_FOR_mips_cond_move_tf_ps;
9935 target = mips_prepare_builtin_target (icode, 0, target);
9936 if (type == MIPS_BUILTIN_MOVT)
9938 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
9939 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
9943 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
9944 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
9946 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
9950 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
9951 of the comparison instruction and COND is the condition it should test.
9952 ARGLIST is the list of function arguments and TARGET, if nonnull,
9953 suggests a good place to put the boolean result. */
9956 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
9957 enum insn_code icode, enum mips_fp_condition cond,
9958 rtx target, tree arglist)
9960 rtx label1, label2, if_then_else;
9961 rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
9962 rtx target_if_equal, target_if_unequal;
9965 if (target == 0 || GET_MODE (target) != SImode)
9966 target = gen_reg_rtx (SImode);
9968 /* Prepare the operands to the comparison. */
9969 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
9970 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
9971 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
9973 switch (insn_data[icode].n_operands)
9976 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
9980 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
9981 ops[3], ops[4], GEN_INT (cond));
9988 /* If the comparison sets more than one register, we define the result
9989 to be 0 if all registers are false and -1 if all registers are true.
9990 The value of the complete result is indeterminate otherwise. It is
9991 possible to test individual registers using SUBREGs.
9993 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
9994 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
9995 and TARGET_IF_UNEQUAL otherwise. */
9996 if (builtin_type == MIPS_BUILTIN_CMP_ALL)
9999 target_if_equal = const1_rtx;
10000 target_if_unequal = const0_rtx;
10005 target_if_equal = const0_rtx;
10006 target_if_unequal = const1_rtx;
10007 if (builtin_type == MIPS_BUILTIN_CMP_UPPER)
10008 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 4);
10009 else if (builtin_type == MIPS_BUILTIN_CMP_LOWER)
10010 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 0);
10013 /* First assume that CMP_RESULT == CMP_VALUE. */
10014 emit_move_insn (target, target_if_equal);
10016 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
10018 label1 = gen_label_rtx ();
10019 label2 = gen_label_rtx ();
10021 = gen_rtx_IF_THEN_ELSE (VOIDmode,
10022 gen_rtx_fmt_ee (NE, GET_MODE (cmp_result),
10023 cmp_result, GEN_INT (cmp_value)),
10024 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
10025 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
10026 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10027 gen_rtx_LABEL_REF (VOIDmode, label2)));
10029 emit_label (label1);
10031 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
10032 emit_move_insn (target, target_if_unequal);
10033 emit_label (label2);
10038 #include "gt-mips.h"