1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 #include "diagnostic.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address. */
143 enum mips_address_type {
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a built-in function. */
157 enum mips_function_type {
158 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
159 #include "config/mips/mips-ftypes.def"
160 #undef DEF_MIPS_FTYPE
164 /* Specifies how a built-in function should be converted into rtl. */
165 enum mips_builtin_type {
166 /* The function corresponds directly to an .md pattern. The return
167 value is mapped to operand 0 and the arguments are mapped to
168 operands 1 and above. */
171 /* The function corresponds directly to an .md pattern. There is no return
172 value and the arguments are mapped to operands 0 and above. */
173 MIPS_BUILTIN_DIRECT_NO_TARGET,
175 /* The function corresponds to a comparison instruction followed by
176 a mips_cond_move_tf_ps pattern. The first two arguments are the
177 values to compare and the second two arguments are the vector
178 operands for the movt.ps or movf.ps instruction (in assembly order). */
182 /* The function corresponds to a V2SF comparison instruction. Operand 0
183 of this instruction is the result of the comparison, which has mode
184 CCV2 or CCV4. The function arguments are mapped to operands 1 and
185 above. The function's return value is an SImode boolean that is
186 true under the following conditions:
188 MIPS_BUILTIN_CMP_ANY: one of the registers is true
189 MIPS_BUILTIN_CMP_ALL: all of the registers are true
190 MIPS_BUILTIN_CMP_LOWER: the first register is true
191 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
192 MIPS_BUILTIN_CMP_ANY,
193 MIPS_BUILTIN_CMP_ALL,
194 MIPS_BUILTIN_CMP_UPPER,
195 MIPS_BUILTIN_CMP_LOWER,
197 /* As above, but the instruction only sets a single $fcc register. */
198 MIPS_BUILTIN_CMP_SINGLE,
200 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
201 MIPS_BUILTIN_BPOSGE32
204 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
205 #define MIPS_FP_CONDITIONS(MACRO) \
223 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
224 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
225 enum mips_fp_condition {
226 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
229 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
230 #define STRINGIFY(X) #X
231 static const char *const mips_fp_conditions[] = {
232 MIPS_FP_CONDITIONS (STRINGIFY)
235 /* Information about a function's frame layout. */
236 struct mips_frame_info GTY(()) {
237 /* The size of the frame in bytes. */
238 HOST_WIDE_INT total_size;
240 /* The number of bytes allocated to variables. */
241 HOST_WIDE_INT var_size;
243 /* The number of bytes allocated to outgoing function arguments. */
244 HOST_WIDE_INT args_size;
246 /* The number of bytes allocated to the .cprestore slot, or 0 if there
248 HOST_WIDE_INT cprestore_size;
250 /* Bit X is set if the function saves or restores GPR X. */
253 /* Likewise FPR X. */
256 /* The number of GPRs and FPRs saved. */
260 /* The offset of the topmost GPR and FPR save slots from the top of
261 the frame, or zero if no such slots are needed. */
262 HOST_WIDE_INT gp_save_offset;
263 HOST_WIDE_INT fp_save_offset;
265 /* Likewise, but giving offsets from the bottom of the frame. */
266 HOST_WIDE_INT gp_sp_offset;
267 HOST_WIDE_INT fp_sp_offset;
269 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
270 HOST_WIDE_INT arg_pointer_offset;
272 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT hard_frame_pointer_offset;
276 struct machine_function GTY(()) {
277 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
278 rtx mips16_gp_pseudo_rtx;
280 /* The number of extra stack bytes taken up by register varargs.
281 This area is allocated by the callee at the very top of the frame. */
284 /* The current frame information, calculated by mips_compute_frame_info. */
285 struct mips_frame_info frame;
287 /* The register to use as the function's global pointer. */
288 unsigned int global_pointer;
290 /* True if mips_adjust_insn_length should ignore an instruction's
292 bool ignore_hazard_length_p;
294 /* True if the whole function is suitable for .set noreorder and
296 bool all_noreorder_p;
298 /* True if the function is known to have an instruction that needs $gp. */
301 /* True if we have emitted an instruction to initialize
302 mips16_gp_pseudo_rtx. */
303 bool initialized_mips16_gp_pseudo_p;
306 /* Information about a single argument. */
307 struct mips_arg_info {
308 /* True if the argument is passed in a floating-point register, or
309 would have been if we hadn't run out of registers. */
312 /* The number of words passed in registers, rounded up. */
313 unsigned int reg_words;
315 /* For EABI, the offset of the first register from GP_ARG_FIRST or
316 FP_ARG_FIRST. For other ABIs, the offset of the first register from
317 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
318 comment for details).
320 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
322 unsigned int reg_offset;
324 /* The number of words that must be passed on the stack, rounded up. */
325 unsigned int stack_words;
327 /* The offset from the start of the stack overflow area of the argument's
328 first stack word. Only meaningful when STACK_WORDS is nonzero. */
329 unsigned int stack_offset;
332 /* Information about an address described by mips_address_type.
338 REG is the base register and OFFSET is the constant offset.
341 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
342 is the type of symbol it references.
345 SYMBOL_TYPE is the type of symbol that the address references. */
346 struct mips_address_info {
347 enum mips_address_type type;
350 enum mips_symbol_type symbol_type;
353 /* One stage in a constant building sequence. These sequences have
357 A = A CODE[1] VALUE[1]
358 A = A CODE[2] VALUE[2]
361 where A is an accumulator, each CODE[i] is a binary rtl operation
362 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
363 struct mips_integer_op {
365 unsigned HOST_WIDE_INT value;
368 /* The largest number of operations needed to load an integer constant.
369 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
370 When the lowest bit is clear, we can try, but reject a sequence with
371 an extra SLL at the end. */
372 #define MIPS_MAX_INTEGER_OPS 7
374 /* Information about a MIPS16e SAVE or RESTORE instruction. */
375 struct mips16e_save_restore_info {
376 /* The number of argument registers saved by a SAVE instruction.
377 0 for RESTORE instructions. */
380 /* Bit X is set if the instruction saves or restores GPR X. */
383 /* The total number of bytes to allocate. */
387 /* Global variables for machine-dependent things. */
389 /* The -G setting, or the configuration's default small-data limit if
390 no -G option is given. */
391 static unsigned int mips_small_data_threshold;
393 /* The number of file directives written by mips_output_filename. */
394 int num_source_filenames;
396 /* The name that appeared in the last .file directive written by
397 mips_output_filename, or "" if mips_output_filename hasn't
398 written anything yet. */
399 const char *current_function_file = "";
401 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
404 /* Arrays that map GCC register numbers to debugger register numbers. */
405 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
406 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
408 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
413 /* True if we're writing out a branch-likely instruction rather than a
415 static bool mips_branch_likely;
417 /* The operands passed to the last cmpMM expander. */
420 /* The current instruction-set architecture. */
421 enum processor_type mips_arch;
422 const struct mips_cpu_info *mips_arch_info;
424 /* The processor that we should tune the code for. */
425 enum processor_type mips_tune;
426 const struct mips_cpu_info *mips_tune_info;
428 /* The ISA level associated with mips_arch. */
431 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
432 static const struct mips_cpu_info *mips_isa_option_info;
434 /* Which ABI to use. */
435 int mips_abi = MIPS_ABI_DEFAULT;
437 /* Which cost information to use. */
438 const struct mips_rtx_cost_data *mips_cost;
440 /* The ambient target flags, excluding MASK_MIPS16. */
441 static int mips_base_target_flags;
443 /* True if MIPS16 is the default mode. */
444 static bool mips_base_mips16;
446 /* The ambient values of other global variables. */
447 static int mips_base_delayed_branch; /* flag_delayed_branch */
448 static int mips_base_schedule_insns; /* flag_schedule_insns */
449 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
450 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
451 static int mips_base_align_loops; /* align_loops */
452 static int mips_base_align_jumps; /* align_jumps */
453 static int mips_base_align_functions; /* align_functions */
455 /* The -mcode-readable setting. */
456 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
458 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
459 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
461 /* Index C is true if character C is a valid PRINT_OPERAND punctation
463 bool mips_print_operand_punct[256];
465 static GTY (()) int mips_output_filename_first_time = 1;
467 /* mips_split_p[X] is true if symbols of type X can be split by
468 mips_split_symbol. */
469 bool mips_split_p[NUM_SYMBOL_TYPES];
471 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
472 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
473 if they are matched by a special .md file pattern. */
474 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
476 /* Likewise for HIGHs. */
477 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
479 /* Index R is the smallest register class that contains register R. */
480 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
481 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
482 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
483 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
484 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
485 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
486 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
487 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
488 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
489 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
490 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
491 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
492 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
493 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
494 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
495 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
496 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
497 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
498 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
499 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
500 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
501 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
502 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
503 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
504 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
505 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
506 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
507 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
508 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
509 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
510 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
511 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
512 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
513 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
514 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
515 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
516 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
517 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
518 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
519 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
520 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
521 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
522 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
523 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
524 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
525 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
526 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
527 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
530 /* The value of TARGET_ATTRIBUTE_TABLE. */
531 const struct attribute_spec mips_attribute_table[] = {
532 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
533 { "long_call", 0, 0, false, true, true, NULL },
534 { "far", 0, 0, false, true, true, NULL },
535 { "near", 0, 0, false, true, true, NULL },
536 /* We would really like to treat "mips16" and "nomips16" as type
537 attributes, but GCC doesn't provide the hooks we need to support
538 the right conversion rules. As declaration attributes, they affect
539 code generation but don't carry other semantics. */
540 { "mips16", 0, 0, true, false, false, NULL },
541 { "nomips16", 0, 0, true, false, false, NULL },
542 { NULL, 0, 0, false, false, false, NULL }
545 /* A table describing all the processors GCC knows about. Names are
546 matched in the order listed. The first mention of an ISA level is
547 taken as the canonical name for that ISA.
549 To ease comparison, please keep this table in the same order
550 as GAS's mips_cpu_info_table. Please also make sure that
551 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
552 options correctly. */
553 static const struct mips_cpu_info mips_cpu_info_table[] = {
554 /* Entries for generic ISAs. */
555 { "mips1", PROCESSOR_R3000, 1, 0 },
556 { "mips2", PROCESSOR_R6000, 2, 0 },
557 { "mips3", PROCESSOR_R4000, 3, 0 },
558 { "mips4", PROCESSOR_R8000, 4, 0 },
559 /* Prefer not to use branch-likely instructions for generic MIPS32rX
560 and MIPS64rX code. The instructions were officially deprecated
561 in revisions 2 and earlier, but revision 3 is likely to downgrade
562 that to a recommendation to avoid the instructions in code that
563 isn't tuned to a specific processor. */
564 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
565 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
566 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
568 /* MIPS I processors. */
569 { "r3000", PROCESSOR_R3000, 1, 0 },
570 { "r2000", PROCESSOR_R3000, 1, 0 },
571 { "r3900", PROCESSOR_R3900, 1, 0 },
573 /* MIPS II processors. */
574 { "r6000", PROCESSOR_R6000, 2, 0 },
576 /* MIPS III processors. */
577 { "r4000", PROCESSOR_R4000, 3, 0 },
578 { "vr4100", PROCESSOR_R4100, 3, 0 },
579 { "vr4111", PROCESSOR_R4111, 3, 0 },
580 { "vr4120", PROCESSOR_R4120, 3, 0 },
581 { "vr4130", PROCESSOR_R4130, 3, 0 },
582 { "vr4300", PROCESSOR_R4300, 3, 0 },
583 { "r4400", PROCESSOR_R4000, 3, 0 },
584 { "r4600", PROCESSOR_R4600, 3, 0 },
585 { "orion", PROCESSOR_R4600, 3, 0 },
586 { "r4650", PROCESSOR_R4650, 3, 0 },
588 /* MIPS IV processors. */
589 { "r8000", PROCESSOR_R8000, 4, 0 },
590 { "vr5000", PROCESSOR_R5000, 4, 0 },
591 { "vr5400", PROCESSOR_R5400, 4, 0 },
592 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
593 { "rm7000", PROCESSOR_R7000, 4, 0 },
594 { "rm9000", PROCESSOR_R9000, 4, 0 },
596 /* MIPS32 processors. */
597 { "4kc", PROCESSOR_4KC, 32, 0 },
598 { "4km", PROCESSOR_4KC, 32, 0 },
599 { "4kp", PROCESSOR_4KP, 32, 0 },
600 { "4ksc", PROCESSOR_4KC, 32, 0 },
602 /* MIPS32 Release 2 processors. */
603 { "m4k", PROCESSOR_M4K, 33, 0 },
604 { "4kec", PROCESSOR_4KC, 33, 0 },
605 { "4kem", PROCESSOR_4KC, 33, 0 },
606 { "4kep", PROCESSOR_4KP, 33, 0 },
607 { "4ksd", PROCESSOR_4KC, 33, 0 },
609 { "24kc", PROCESSOR_24KC, 33, 0 },
610 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
611 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
612 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
613 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
614 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
616 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
617 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
618 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
619 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
620 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
621 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
623 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
624 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
625 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
626 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
627 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
628 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
630 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
631 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
632 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
633 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
634 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
635 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
636 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
638 /* MIPS64 processors. */
639 { "5kc", PROCESSOR_5KC, 64, 0 },
640 { "5kf", PROCESSOR_5KF, 64, 0 },
641 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
642 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
643 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
644 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
647 /* Default costs. If these are used for a processor we should look
648 up the actual costs. */
649 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
650 COSTS_N_INSNS (7), /* fp_mult_sf */ \
651 COSTS_N_INSNS (8), /* fp_mult_df */ \
652 COSTS_N_INSNS (23), /* fp_div_sf */ \
653 COSTS_N_INSNS (36), /* fp_div_df */ \
654 COSTS_N_INSNS (10), /* int_mult_si */ \
655 COSTS_N_INSNS (10), /* int_mult_di */ \
656 COSTS_N_INSNS (69), /* int_div_si */ \
657 COSTS_N_INSNS (69), /* int_div_di */ \
658 2, /* branch_cost */ \
659 4 /* memory_latency */
661 /* Floating-point costs for processors without an FPU. Just assume that
662 all floating-point libcalls are very expensive. */
663 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
664 COSTS_N_INSNS (256), /* fp_mult_sf */ \
665 COSTS_N_INSNS (256), /* fp_mult_df */ \
666 COSTS_N_INSNS (256), /* fp_div_sf */ \
667 COSTS_N_INSNS (256) /* fp_div_df */
669 /* Costs to use when optimizing for size. */
670 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
671 COSTS_N_INSNS (1), /* fp_add */
672 COSTS_N_INSNS (1), /* fp_mult_sf */
673 COSTS_N_INSNS (1), /* fp_mult_df */
674 COSTS_N_INSNS (1), /* fp_div_sf */
675 COSTS_N_INSNS (1), /* fp_div_df */
676 COSTS_N_INSNS (1), /* int_mult_si */
677 COSTS_N_INSNS (1), /* int_mult_di */
678 COSTS_N_INSNS (1), /* int_div_si */
679 COSTS_N_INSNS (1), /* int_div_di */
681 4 /* memory_latency */
684 /* Costs to use when optimizing for speed, indexed by processor. */
685 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
687 COSTS_N_INSNS (2), /* fp_add */
688 COSTS_N_INSNS (4), /* fp_mult_sf */
689 COSTS_N_INSNS (5), /* fp_mult_df */
690 COSTS_N_INSNS (12), /* fp_div_sf */
691 COSTS_N_INSNS (19), /* fp_div_df */
692 COSTS_N_INSNS (12), /* int_mult_si */
693 COSTS_N_INSNS (12), /* int_mult_di */
694 COSTS_N_INSNS (35), /* int_div_si */
695 COSTS_N_INSNS (35), /* int_div_di */
697 4 /* memory_latency */
701 COSTS_N_INSNS (6), /* int_mult_si */
702 COSTS_N_INSNS (6), /* int_mult_di */
703 COSTS_N_INSNS (36), /* int_div_si */
704 COSTS_N_INSNS (36), /* int_div_di */
706 4 /* memory_latency */
710 COSTS_N_INSNS (36), /* int_mult_si */
711 COSTS_N_INSNS (36), /* int_mult_di */
712 COSTS_N_INSNS (37), /* int_div_si */
713 COSTS_N_INSNS (37), /* int_div_di */
715 4 /* memory_latency */
719 COSTS_N_INSNS (4), /* int_mult_si */
720 COSTS_N_INSNS (11), /* int_mult_di */
721 COSTS_N_INSNS (36), /* int_div_si */
722 COSTS_N_INSNS (68), /* int_div_di */
724 4 /* memory_latency */
727 COSTS_N_INSNS (4), /* fp_add */
728 COSTS_N_INSNS (4), /* fp_mult_sf */
729 COSTS_N_INSNS (5), /* fp_mult_df */
730 COSTS_N_INSNS (17), /* fp_div_sf */
731 COSTS_N_INSNS (32), /* fp_div_df */
732 COSTS_N_INSNS (4), /* int_mult_si */
733 COSTS_N_INSNS (11), /* int_mult_di */
734 COSTS_N_INSNS (36), /* int_div_si */
735 COSTS_N_INSNS (68), /* int_div_di */
737 4 /* memory_latency */
740 COSTS_N_INSNS (4), /* fp_add */
741 COSTS_N_INSNS (4), /* fp_mult_sf */
742 COSTS_N_INSNS (5), /* fp_mult_df */
743 COSTS_N_INSNS (17), /* fp_div_sf */
744 COSTS_N_INSNS (32), /* fp_div_df */
745 COSTS_N_INSNS (4), /* int_mult_si */
746 COSTS_N_INSNS (7), /* int_mult_di */
747 COSTS_N_INSNS (42), /* int_div_si */
748 COSTS_N_INSNS (72), /* int_div_di */
750 4 /* memory_latency */
754 COSTS_N_INSNS (5), /* int_mult_si */
755 COSTS_N_INSNS (5), /* int_mult_di */
756 COSTS_N_INSNS (41), /* int_div_si */
757 COSTS_N_INSNS (41), /* int_div_di */
759 4 /* memory_latency */
762 COSTS_N_INSNS (8), /* fp_add */
763 COSTS_N_INSNS (8), /* fp_mult_sf */
764 COSTS_N_INSNS (10), /* fp_mult_df */
765 COSTS_N_INSNS (34), /* fp_div_sf */
766 COSTS_N_INSNS (64), /* fp_div_df */
767 COSTS_N_INSNS (5), /* int_mult_si */
768 COSTS_N_INSNS (5), /* int_mult_di */
769 COSTS_N_INSNS (41), /* int_div_si */
770 COSTS_N_INSNS (41), /* int_div_di */
772 4 /* memory_latency */
775 COSTS_N_INSNS (4), /* fp_add */
776 COSTS_N_INSNS (4), /* fp_mult_sf */
777 COSTS_N_INSNS (5), /* fp_mult_df */
778 COSTS_N_INSNS (17), /* fp_div_sf */
779 COSTS_N_INSNS (32), /* fp_div_df */
780 COSTS_N_INSNS (5), /* int_mult_si */
781 COSTS_N_INSNS (5), /* int_mult_di */
782 COSTS_N_INSNS (41), /* int_div_si */
783 COSTS_N_INSNS (41), /* int_div_di */
785 4 /* memory_latency */
789 COSTS_N_INSNS (5), /* int_mult_si */
790 COSTS_N_INSNS (5), /* int_mult_di */
791 COSTS_N_INSNS (41), /* int_div_si */
792 COSTS_N_INSNS (41), /* int_div_di */
794 4 /* memory_latency */
797 COSTS_N_INSNS (8), /* fp_add */
798 COSTS_N_INSNS (8), /* fp_mult_sf */
799 COSTS_N_INSNS (10), /* fp_mult_df */
800 COSTS_N_INSNS (34), /* fp_div_sf */
801 COSTS_N_INSNS (64), /* fp_div_df */
802 COSTS_N_INSNS (5), /* int_mult_si */
803 COSTS_N_INSNS (5), /* int_mult_di */
804 COSTS_N_INSNS (41), /* int_div_si */
805 COSTS_N_INSNS (41), /* int_div_di */
807 4 /* memory_latency */
810 COSTS_N_INSNS (4), /* fp_add */
811 COSTS_N_INSNS (4), /* fp_mult_sf */
812 COSTS_N_INSNS (5), /* fp_mult_df */
813 COSTS_N_INSNS (17), /* fp_div_sf */
814 COSTS_N_INSNS (32), /* fp_div_df */
815 COSTS_N_INSNS (5), /* int_mult_si */
816 COSTS_N_INSNS (5), /* int_mult_di */
817 COSTS_N_INSNS (41), /* int_div_si */
818 COSTS_N_INSNS (41), /* int_div_di */
820 4 /* memory_latency */
823 COSTS_N_INSNS (6), /* fp_add */
824 COSTS_N_INSNS (6), /* fp_mult_sf */
825 COSTS_N_INSNS (7), /* fp_mult_df */
826 COSTS_N_INSNS (25), /* fp_div_sf */
827 COSTS_N_INSNS (48), /* fp_div_df */
828 COSTS_N_INSNS (5), /* int_mult_si */
829 COSTS_N_INSNS (5), /* int_mult_di */
830 COSTS_N_INSNS (41), /* int_div_si */
831 COSTS_N_INSNS (41), /* int_div_di */
833 4 /* memory_latency */
839 COSTS_N_INSNS (2), /* fp_add */
840 COSTS_N_INSNS (4), /* fp_mult_sf */
841 COSTS_N_INSNS (5), /* fp_mult_df */
842 COSTS_N_INSNS (12), /* fp_div_sf */
843 COSTS_N_INSNS (19), /* fp_div_df */
844 COSTS_N_INSNS (2), /* int_mult_si */
845 COSTS_N_INSNS (2), /* int_mult_di */
846 COSTS_N_INSNS (35), /* int_div_si */
847 COSTS_N_INSNS (35), /* int_div_di */
849 4 /* memory_latency */
852 COSTS_N_INSNS (3), /* fp_add */
853 COSTS_N_INSNS (5), /* fp_mult_sf */
854 COSTS_N_INSNS (6), /* fp_mult_df */
855 COSTS_N_INSNS (15), /* fp_div_sf */
856 COSTS_N_INSNS (16), /* fp_div_df */
857 COSTS_N_INSNS (17), /* int_mult_si */
858 COSTS_N_INSNS (17), /* int_mult_di */
859 COSTS_N_INSNS (38), /* int_div_si */
860 COSTS_N_INSNS (38), /* int_div_di */
862 6 /* memory_latency */
865 COSTS_N_INSNS (6), /* fp_add */
866 COSTS_N_INSNS (7), /* fp_mult_sf */
867 COSTS_N_INSNS (8), /* fp_mult_df */
868 COSTS_N_INSNS (23), /* fp_div_sf */
869 COSTS_N_INSNS (36), /* fp_div_df */
870 COSTS_N_INSNS (10), /* int_mult_si */
871 COSTS_N_INSNS (10), /* int_mult_di */
872 COSTS_N_INSNS (69), /* int_div_si */
873 COSTS_N_INSNS (69), /* int_div_di */
875 6 /* memory_latency */
887 /* The only costs that appear to be updated here are
888 integer multiplication. */
890 COSTS_N_INSNS (4), /* int_mult_si */
891 COSTS_N_INSNS (6), /* int_mult_di */
892 COSTS_N_INSNS (69), /* int_div_si */
893 COSTS_N_INSNS (69), /* int_div_di */
895 4 /* memory_latency */
907 COSTS_N_INSNS (6), /* fp_add */
908 COSTS_N_INSNS (4), /* fp_mult_sf */
909 COSTS_N_INSNS (5), /* fp_mult_df */
910 COSTS_N_INSNS (23), /* fp_div_sf */
911 COSTS_N_INSNS (36), /* fp_div_df */
912 COSTS_N_INSNS (5), /* int_mult_si */
913 COSTS_N_INSNS (5), /* int_mult_di */
914 COSTS_N_INSNS (36), /* int_div_si */
915 COSTS_N_INSNS (36), /* int_div_di */
917 4 /* memory_latency */
920 COSTS_N_INSNS (6), /* fp_add */
921 COSTS_N_INSNS (5), /* fp_mult_sf */
922 COSTS_N_INSNS (6), /* fp_mult_df */
923 COSTS_N_INSNS (30), /* fp_div_sf */
924 COSTS_N_INSNS (59), /* fp_div_df */
925 COSTS_N_INSNS (3), /* int_mult_si */
926 COSTS_N_INSNS (4), /* int_mult_di */
927 COSTS_N_INSNS (42), /* int_div_si */
928 COSTS_N_INSNS (74), /* int_div_di */
930 4 /* memory_latency */
933 COSTS_N_INSNS (6), /* fp_add */
934 COSTS_N_INSNS (5), /* fp_mult_sf */
935 COSTS_N_INSNS (6), /* fp_mult_df */
936 COSTS_N_INSNS (30), /* fp_div_sf */
937 COSTS_N_INSNS (59), /* fp_div_df */
938 COSTS_N_INSNS (5), /* int_mult_si */
939 COSTS_N_INSNS (9), /* int_mult_di */
940 COSTS_N_INSNS (42), /* int_div_si */
941 COSTS_N_INSNS (74), /* int_div_di */
943 4 /* memory_latency */
946 /* The only costs that are changed here are
947 integer multiplication. */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (7), /* fp_mult_sf */
950 COSTS_N_INSNS (8), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (9), /* int_mult_di */
955 COSTS_N_INSNS (69), /* int_div_si */
956 COSTS_N_INSNS (69), /* int_div_di */
958 4 /* memory_latency */
964 /* The only costs that are changed here are
965 integer multiplication. */
966 COSTS_N_INSNS (6), /* fp_add */
967 COSTS_N_INSNS (7), /* fp_mult_sf */
968 COSTS_N_INSNS (8), /* fp_mult_df */
969 COSTS_N_INSNS (23), /* fp_div_sf */
970 COSTS_N_INSNS (36), /* fp_div_df */
971 COSTS_N_INSNS (3), /* int_mult_si */
972 COSTS_N_INSNS (8), /* int_mult_di */
973 COSTS_N_INSNS (69), /* int_div_si */
974 COSTS_N_INSNS (69), /* int_div_di */
976 4 /* memory_latency */
979 /* These costs are the same as the SB-1A below. */
980 COSTS_N_INSNS (4), /* fp_add */
981 COSTS_N_INSNS (4), /* fp_mult_sf */
982 COSTS_N_INSNS (4), /* fp_mult_df */
983 COSTS_N_INSNS (24), /* fp_div_sf */
984 COSTS_N_INSNS (32), /* fp_div_df */
985 COSTS_N_INSNS (3), /* int_mult_si */
986 COSTS_N_INSNS (4), /* int_mult_di */
987 COSTS_N_INSNS (36), /* int_div_si */
988 COSTS_N_INSNS (68), /* int_div_di */
990 4 /* memory_latency */
993 /* These costs are the same as the SB-1 above. */
994 COSTS_N_INSNS (4), /* fp_add */
995 COSTS_N_INSNS (4), /* fp_mult_sf */
996 COSTS_N_INSNS (4), /* fp_mult_df */
997 COSTS_N_INSNS (24), /* fp_div_sf */
998 COSTS_N_INSNS (32), /* fp_div_df */
999 COSTS_N_INSNS (3), /* int_mult_si */
1000 COSTS_N_INSNS (4), /* int_mult_di */
1001 COSTS_N_INSNS (36), /* int_div_si */
1002 COSTS_N_INSNS (68), /* int_div_di */
1003 1, /* branch_cost */
1004 4 /* memory_latency */
1011 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1012 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1013 struct mflip_mips16_entry GTY (()) {
1017 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1019 /* Hash table callbacks for mflip_mips16_htab. */
1022 mflip_mips16_htab_hash (const void *entry)
1024 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1028 mflip_mips16_htab_eq (const void *entry, const void *name)
1030 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1031 (const char *) name) == 0;
1034 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1035 mode, false if it should next add an attribute for the opposite mode. */
1036 static GTY(()) bool mips16_flipper;
1038 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1039 for -mflip-mips16. Return true if it should use "mips16" and false if
1040 it should use "nomips16". */
1043 mflip_mips16_use_mips16_p (tree decl)
1045 struct mflip_mips16_entry *entry;
1050 /* Use the opposite of the command-line setting for anonymous decls. */
1051 if (!DECL_NAME (decl))
1052 return !mips_base_mips16;
1054 if (!mflip_mips16_htab)
1055 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1056 mflip_mips16_htab_eq, NULL);
1058 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1059 hash = htab_hash_string (name);
1060 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1061 entry = (struct mflip_mips16_entry *) *slot;
1064 mips16_flipper = !mips16_flipper;
1065 entry = GGC_NEW (struct mflip_mips16_entry);
1067 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1070 return entry->mips16_p;
1073 /* Predicates to test for presence of "near" and "far"/"long_call"
1074 attributes on the given TYPE. */
1077 mips_near_type_p (const_tree type)
1079 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1083 mips_far_type_p (const_tree type)
1085 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1086 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1089 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1092 mips_mips16_decl_p (const_tree decl)
1094 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1098 mips_nomips16_decl_p (const_tree decl)
1100 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1103 /* Return true if function DECL is a MIPS16 function. Return the ambient
1104 setting if DECL is null. */
1107 mips_use_mips16_mode_p (tree decl)
1111 /* Nested functions must use the same frame pointer as their
1112 parent and must therefore use the same ISA mode. */
1113 tree parent = decl_function_context (decl);
1116 if (mips_mips16_decl_p (decl))
1118 if (mips_nomips16_decl_p (decl))
1121 return mips_base_mips16;
1124 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1127 mips_comp_type_attributes (const_tree type1, const_tree type2)
1129 /* Disallow mixed near/far attributes. */
1130 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1132 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1137 /* Implement TARGET_INSERT_ATTRIBUTES. */
1140 mips_insert_attributes (tree decl, tree *attributes)
1143 bool mips16_p, nomips16_p;
1145 /* Check for "mips16" and "nomips16" attributes. */
1146 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1147 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1148 if (TREE_CODE (decl) != FUNCTION_DECL)
1151 error ("%qs attribute only applies to functions", "mips16");
1153 error ("%qs attribute only applies to functions", "nomips16");
1157 mips16_p |= mips_mips16_decl_p (decl);
1158 nomips16_p |= mips_nomips16_decl_p (decl);
1159 if (mips16_p || nomips16_p)
1161 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1162 if (mips16_p && nomips16_p)
1163 error ("%qs cannot have both %<mips16%> and "
1164 "%<nomips16%> attributes",
1165 IDENTIFIER_POINTER (DECL_NAME (decl)));
1167 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1169 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1170 "mips16" attribute, arbitrarily pick one. We must pick the same
1171 setting for duplicate declarations of a function. */
1172 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1173 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1178 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1181 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1183 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1184 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1185 error ("%qs redeclared with conflicting %qs attributes",
1186 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1187 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1188 error ("%qs redeclared with conflicting %qs attributes",
1189 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1191 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1192 DECL_ATTRIBUTES (newdecl));
1195 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1196 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1199 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1201 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1203 *base_ptr = XEXP (x, 0);
1204 *offset_ptr = INTVAL (XEXP (x, 1));
1213 static unsigned int mips_build_integer (struct mips_integer_op *,
1214 unsigned HOST_WIDE_INT);
1216 /* A subroutine of mips_build_integer, with the same interface.
1217 Assume that the final action in the sequence should be a left shift. */
1220 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1222 unsigned int i, shift;
1224 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1225 since signed numbers are easier to load than unsigned ones. */
1227 while ((value & 1) == 0)
1228 value /= 2, shift++;
1230 i = mips_build_integer (codes, value);
1231 codes[i].code = ASHIFT;
1232 codes[i].value = shift;
1236 /* As for mips_build_shift, but assume that the final action will be
1237 an IOR or PLUS operation. */
1240 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1242 unsigned HOST_WIDE_INT high;
1245 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1246 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1248 /* The constant is too complex to load with a simple LUI/ORI pair,
1249 so we want to give the recursive call as many trailing zeros as
1250 possible. In this case, we know bit 16 is set and that the
1251 low 16 bits form a negative number. If we subtract that number
1252 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1253 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1254 codes[i].code = PLUS;
1255 codes[i].value = CONST_LOW_PART (value);
1259 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1260 bits gives a value with at least 17 trailing zeros. */
1261 i = mips_build_integer (codes, high);
1262 codes[i].code = IOR;
1263 codes[i].value = value & 0xffff;
1268 /* Fill CODES with a sequence of rtl operations to load VALUE.
1269 Return the number of operations needed. */
1272 mips_build_integer (struct mips_integer_op *codes,
1273 unsigned HOST_WIDE_INT value)
1275 if (SMALL_OPERAND (value)
1276 || SMALL_OPERAND_UNSIGNED (value)
1277 || LUI_OPERAND (value))
1279 /* The value can be loaded with a single instruction. */
1280 codes[0].code = UNKNOWN;
1281 codes[0].value = value;
1284 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1286 /* Either the constant is a simple LUI/ORI combination or its
1287 lowest bit is set. We don't want to shift in this case. */
1288 return mips_build_lower (codes, value);
1290 else if ((value & 0xffff) == 0)
1292 /* The constant will need at least three actions. The lowest
1293 16 bits are clear, so the final action will be a shift. */
1294 return mips_build_shift (codes, value);
1298 /* The final action could be a shift, add or inclusive OR.
1299 Rather than use a complex condition to select the best
1300 approach, try both mips_build_shift and mips_build_lower
1301 and pick the one that gives the shortest sequence.
1302 Note that this case is only used once per constant. */
1303 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1304 unsigned int cost, alt_cost;
1306 cost = mips_build_shift (codes, value);
1307 alt_cost = mips_build_lower (alt_codes, value);
1308 if (alt_cost < cost)
1310 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1317 /* Return true if X is a thread-local symbol. */
1320 mips_tls_symbol_p (rtx x)
1322 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1325 /* Return true if SYMBOL_REF X is associated with a global symbol
1326 (in the STB_GLOBAL sense). */
1329 mips_global_symbol_p (const_rtx x)
1331 const_tree decl = SYMBOL_REF_DECL (x);
1334 return !SYMBOL_REF_LOCAL_P (x);
1336 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1337 or weak symbols. Relocations in the object file will be against
1338 the target symbol, so it's that symbol's binding that matters here. */
1339 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1342 /* Return true if SYMBOL_REF X binds locally. */
1345 mips_symbol_binds_local_p (const_rtx x)
1347 return (SYMBOL_REF_DECL (x)
1348 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1349 : SYMBOL_REF_LOCAL_P (x));
1352 /* Return true if rtx constants of mode MODE should be put into a small
1356 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1358 return (!TARGET_EMBEDDED_DATA
1359 && TARGET_LOCAL_SDATA
1360 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1363 /* Return true if X should not be moved directly into register $25.
1364 We need this because many versions of GAS will treat "la $25,foo" as
1365 part of a call sequence and so allow a global "foo" to be lazily bound. */
1368 mips_dangerous_for_la25_p (rtx x)
1370 return (!TARGET_EXPLICIT_RELOCS
1372 && GET_CODE (x) == SYMBOL_REF
1373 && mips_global_symbol_p (x));
1376 /* Return the method that should be used to access SYMBOL_REF or
1377 LABEL_REF X in context CONTEXT. */
1379 static enum mips_symbol_type
1380 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1383 return SYMBOL_GOT_DISP;
1385 if (GET_CODE (x) == LABEL_REF)
1387 /* LABEL_REFs are used for jump tables as well as text labels.
1388 Only return SYMBOL_PC_RELATIVE if we know the label is in
1389 the text section. */
1390 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1391 return SYMBOL_PC_RELATIVE;
1393 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1394 return SYMBOL_GOT_PAGE_OFST;
1396 return SYMBOL_ABSOLUTE;
1399 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1401 if (SYMBOL_REF_TLS_MODEL (x))
1404 if (CONSTANT_POOL_ADDRESS_P (x))
1406 if (TARGET_MIPS16_TEXT_LOADS)
1407 return SYMBOL_PC_RELATIVE;
1409 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1410 return SYMBOL_PC_RELATIVE;
1412 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1413 return SYMBOL_GP_RELATIVE;
1416 /* Do not use small-data accesses for weak symbols; they may end up
1418 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1419 return SYMBOL_GP_RELATIVE;
1421 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1424 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1426 /* There are three cases to consider:
1428 - o32 PIC (either with or without explicit relocs)
1429 - n32/n64 PIC without explicit relocs
1430 - n32/n64 PIC with explicit relocs
1432 In the first case, both local and global accesses will use an
1433 R_MIPS_GOT16 relocation. We must correctly predict which of
1434 the two semantics (local or global) the assembler and linker
1435 will apply. The choice depends on the symbol's binding rather
1436 than its visibility.
1438 In the second case, the assembler will not use R_MIPS_GOT16
1439 relocations, but it chooses between local and global accesses
1440 in the same way as for o32 PIC.
1442 In the third case we have more freedom since both forms of
1443 access will work for any kind of symbol. However, there seems
1444 little point in doing things differently. */
1445 if (mips_global_symbol_p (x))
1446 return SYMBOL_GOT_DISP;
1448 return SYMBOL_GOT_PAGE_OFST;
1451 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1452 return SYMBOL_FORCE_TO_MEM;
1454 return SYMBOL_ABSOLUTE;
1457 /* Classify the base of symbolic expression X, given that X appears in
1460 static enum mips_symbol_type
1461 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1465 split_const (x, &x, &offset);
1466 if (UNSPEC_ADDRESS_P (x))
1467 return UNSPEC_ADDRESS_TYPE (x);
1469 return mips_classify_symbol (x, context);
1472 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1473 is the alignment in bytes of SYMBOL_REF X. */
1476 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1478 HOST_WIDE_INT align;
1480 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1481 return IN_RANGE (offset, 0, align - 1);
1484 /* Return true if X is a symbolic constant that can be used in context
1485 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1488 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1489 enum mips_symbol_type *symbol_type)
1493 split_const (x, &x, &offset);
1494 if (UNSPEC_ADDRESS_P (x))
1496 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1497 x = UNSPEC_ADDRESS (x);
1499 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1501 *symbol_type = mips_classify_symbol (x, context);
1502 if (*symbol_type == SYMBOL_TLS)
1508 if (offset == const0_rtx)
1511 /* Check whether a nonzero offset is valid for the underlying
1513 switch (*symbol_type)
1515 case SYMBOL_ABSOLUTE:
1516 case SYMBOL_FORCE_TO_MEM:
1517 case SYMBOL_32_HIGH:
1518 case SYMBOL_64_HIGH:
1521 /* If the target has 64-bit pointers and the object file only
1522 supports 32-bit symbols, the values of those symbols will be
1523 sign-extended. In this case we can't allow an arbitrary offset
1524 in case the 32-bit value X + OFFSET has a different sign from X. */
1525 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1526 return offset_within_block_p (x, INTVAL (offset));
1528 /* In other cases the relocations can handle any offset. */
1531 case SYMBOL_PC_RELATIVE:
1532 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1533 In this case, we no longer have access to the underlying constant,
1534 but the original symbol-based access was known to be valid. */
1535 if (GET_CODE (x) == LABEL_REF)
1540 case SYMBOL_GP_RELATIVE:
1541 /* Make sure that the offset refers to something within the
1542 same object block. This should guarantee that the final
1543 PC- or GP-relative offset is within the 16-bit limit. */
1544 return offset_within_block_p (x, INTVAL (offset));
1546 case SYMBOL_GOT_PAGE_OFST:
1547 case SYMBOL_GOTOFF_PAGE:
1548 /* If the symbol is global, the GOT entry will contain the symbol's
1549 address, and we will apply a 16-bit offset after loading it.
1550 If the symbol is local, the linker should provide enough local
1551 GOT entries for a 16-bit offset, but larger offsets may lead
1553 return SMALL_INT (offset);
1557 /* There is no carry between the HI and LO REL relocations, so the
1558 offset is only valid if we know it won't lead to such a carry. */
1559 return mips_offset_within_alignment_p (x, INTVAL (offset));
1561 case SYMBOL_GOT_DISP:
1562 case SYMBOL_GOTOFF_DISP:
1563 case SYMBOL_GOTOFF_CALL:
1564 case SYMBOL_GOTOFF_LOADGP:
1567 case SYMBOL_GOTTPREL:
1575 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1576 single instruction. We rely on the fact that, in the worst case,
1577 all instructions involved in a MIPS16 address calculation are usually
1581 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1585 case SYMBOL_ABSOLUTE:
1586 /* When using 64-bit symbols, we need 5 preparatory instructions,
1589 lui $at,%highest(symbol)
1590 daddiu $at,$at,%higher(symbol)
1592 daddiu $at,$at,%hi(symbol)
1595 The final address is then $at + %lo(symbol). With 32-bit
1596 symbols we just need a preparatory LUI for normal mode and
1597 a preparatory LI and SLL for MIPS16. */
1598 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1600 case SYMBOL_GP_RELATIVE:
1601 /* Treat GP-relative accesses as taking a single instruction on
1602 MIPS16 too; the copy of $gp can often be shared. */
1605 case SYMBOL_PC_RELATIVE:
1606 /* PC-relative constants can be only be used with ADDIUPC,
1607 DADDIUPC, LWPC and LDPC. */
1608 if (mode == MAX_MACHINE_MODE
1609 || GET_MODE_SIZE (mode) == 4
1610 || GET_MODE_SIZE (mode) == 8)
1613 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1616 case SYMBOL_FORCE_TO_MEM:
1617 /* LEAs will be converted into constant-pool references by
1619 if (mode == MAX_MACHINE_MODE)
1622 /* The constant must be loaded and then dereferenced. */
1625 case SYMBOL_GOT_DISP:
1626 /* The constant will have to be loaded from the GOT before it
1627 is used in an address. */
1628 if (mode != MAX_MACHINE_MODE)
1633 case SYMBOL_GOT_PAGE_OFST:
1634 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1635 local/global classification is accurate. The worst cases are:
1637 (1) For local symbols when generating o32 or o64 code. The assembler
1643 ...and the final address will be $at + %lo(symbol).
1645 (2) For global symbols when -mxgot. The assembler will use:
1647 lui $at,%got_hi(symbol)
1650 ...and the final address will be $at + %got_lo(symbol). */
1653 case SYMBOL_GOTOFF_PAGE:
1654 case SYMBOL_GOTOFF_DISP:
1655 case SYMBOL_GOTOFF_CALL:
1656 case SYMBOL_GOTOFF_LOADGP:
1657 case SYMBOL_32_HIGH:
1658 case SYMBOL_64_HIGH:
1664 case SYMBOL_GOTTPREL:
1667 /* A 16-bit constant formed by a single relocation, or a 32-bit
1668 constant formed from a high 16-bit relocation and a low 16-bit
1669 relocation. Use mips_split_p to determine which. 32-bit
1670 constants need an "lui; addiu" sequence for normal mode and
1671 an "li; sll; addiu" sequence for MIPS16 mode. */
1672 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1675 /* We don't treat a bare TLS symbol as a constant. */
1681 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1682 to load symbols of type TYPE into a register. Return 0 if the given
1683 type of symbol cannot be used as an immediate operand.
1685 Otherwise, return the number of instructions needed to load or store
1686 values of mode MODE to or from addresses of type TYPE. Return 0 if
1687 the given type of symbol is not valid in addresses.
1689 In both cases, treat extended MIPS16 instructions as two instructions. */
1692 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1694 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1697 /* A for_each_rtx callback. Stop the search if *X references a
1698 thread-local symbol. */
1701 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1703 return mips_tls_symbol_p (*x);
1706 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1709 mips_cannot_force_const_mem (rtx x)
1715 /* As an optimization, reject constants that mips_legitimize_move
1718 Suppose we have a multi-instruction sequence that loads constant C
1719 into register R. If R does not get allocated a hard register, and
1720 R is used in an operand that allows both registers and memory
1721 references, reload will consider forcing C into memory and using
1722 one of the instruction's memory alternatives. Returning false
1723 here will force it to use an input reload instead. */
1724 if (GET_CODE (x) == CONST_INT)
1727 split_const (x, &base, &offset);
1728 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1732 /* TLS symbols must be computed by mips_legitimize_move. */
1733 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1739 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1740 constants when we're using a per-function constant pool. */
1743 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1744 const_rtx x ATTRIBUTE_UNUSED)
1746 return !TARGET_MIPS16_PCREL_LOADS;
1749 /* Return true if register REGNO is a valid base register for mode MODE.
1750 STRICT_P is true if REG_OK_STRICT is in effect. */
1753 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1756 if (!HARD_REGISTER_NUM_P (regno))
1760 regno = reg_renumber[regno];
1763 /* These fake registers will be eliminated to either the stack or
1764 hard frame pointer, both of which are usually valid base registers.
1765 Reload deals with the cases where the eliminated form isn't valid. */
1766 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1769 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1770 values, nothing smaller. There are two problems here:
1772 (a) Instantiating virtual registers can introduce new uses of the
1773 stack pointer. If these virtual registers are valid addresses,
1774 the stack pointer should be too.
1776 (b) Most uses of the stack pointer are not made explicit until
1777 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1778 We don't know until that stage whether we'll be eliminating to the
1779 stack pointer (which needs the restriction) or the hard frame
1780 pointer (which doesn't).
1782 All in all, it seems more consistent to only enforce this restriction
1783 during and after reload. */
1784 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1785 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1787 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1790 /* Return true if X is a valid base register for mode MODE.
1791 STRICT_P is true if REG_OK_STRICT is in effect. */
1794 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
1796 if (!strict_p && GET_CODE (x) == SUBREG)
1800 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
1803 /* Return true if X is a valid address for machine mode MODE. If it is,
1804 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1808 mips_classify_address (struct mips_address_info *info, rtx x,
1809 enum machine_mode mode, bool strict_p)
1811 switch (GET_CODE (x))
1815 info->type = ADDRESS_REG;
1817 info->offset = const0_rtx;
1818 return mips_valid_base_register_p (info->reg, mode, strict_p);
1821 info->type = ADDRESS_REG;
1822 info->reg = XEXP (x, 0);
1823 info->offset = XEXP (x, 1);
1824 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1825 && const_arith_operand (info->offset, VOIDmode));
1828 info->type = ADDRESS_LO_SUM;
1829 info->reg = XEXP (x, 0);
1830 info->offset = XEXP (x, 1);
1831 /* We have to trust the creator of the LO_SUM to do something vaguely
1832 sane. Target-independent code that creates a LO_SUM should also
1833 create and verify the matching HIGH. Target-independent code that
1834 adds an offset to a LO_SUM must prove that the offset will not
1835 induce a carry. Failure to do either of these things would be
1836 a bug, and we are not required to check for it here. The MIPS
1837 backend itself should only create LO_SUMs for valid symbolic
1838 constants, with the high part being either a HIGH or a copy
1841 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
1842 return (mips_valid_base_register_p (info->reg, mode, strict_p)
1843 && mips_symbol_insns (info->symbol_type, mode) > 0
1844 && mips_lo_relocs[info->symbol_type] != 0);
1847 /* Small-integer addresses don't occur very often, but they
1848 are legitimate if $0 is a valid base register. */
1849 info->type = ADDRESS_CONST_INT;
1850 return !TARGET_MIPS16 && SMALL_INT (x);
1855 info->type = ADDRESS_SYMBOLIC;
1856 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
1858 && mips_symbol_insns (info->symbol_type, mode) > 0
1859 && !mips_split_p[info->symbol_type]);
1866 /* Return true if X is a legitimate address for a memory operand of mode
1867 MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
1870 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
1872 struct mips_address_info addr;
1874 return mips_classify_address (&addr, x, mode, strict_p);
1877 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1880 mips_stack_address_p (rtx x, enum machine_mode mode)
1882 struct mips_address_info addr;
1884 return (mips_classify_address (&addr, x, mode, false)
1885 && addr.type == ADDRESS_REG
1886 && addr.reg == stack_pointer_rtx);
1889 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
1890 address instruction. Note that such addresses are not considered
1891 legitimate in the GO_IF_LEGITIMATE_ADDRESS sense, because their use
1892 is so restricted. */
1895 mips_lwxs_address_p (rtx addr)
1898 && GET_CODE (addr) == PLUS
1899 && REG_P (XEXP (addr, 1)))
1901 rtx offset = XEXP (addr, 0);
1902 if (GET_CODE (offset) == MULT
1903 && REG_P (XEXP (offset, 0))
1904 && GET_CODE (XEXP (offset, 1)) == CONST_INT
1905 && INTVAL (XEXP (offset, 1)) == 4)
1911 /* Return true if a value at OFFSET bytes from base register BASE can be
1912 accessed using an unextended MIPS16 instruction. MODE is the mode of
1915 Usually the offset in an unextended instruction is a 5-bit field.
1916 The offset is unsigned and shifted left once for LH and SH, twice
1917 for LW and SW, and so on. An exception is LWSP and SWSP, which have
1918 an 8-bit immediate field that's shifted left twice. */
1921 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
1922 unsigned HOST_WIDE_INT offset)
1924 if (offset % GET_MODE_SIZE (mode) == 0)
1926 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1927 return offset < 256U * GET_MODE_SIZE (mode);
1928 return offset < 32U * GET_MODE_SIZE (mode);
1933 /* Return the number of instructions needed to load or store a value
1934 of mode MODE at address X. Return 0 if X isn't valid for MODE.
1935 Assume that multiword moves may need to be split into word moves
1936 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
1939 For MIPS16 code, count extended instructions as two instructions. */
1942 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
1944 struct mips_address_info addr;
1947 /* BLKmode is used for single unaligned loads and stores and should
1948 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
1949 meaningless, so we have to single it out as a special case one way
1951 if (mode != BLKmode && might_split_p)
1952 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1956 if (mips_classify_address (&addr, x, mode, false))
1961 && !mips16_unextended_reference_p (mode, addr.reg,
1962 UINTVAL (addr.offset)))
1966 case ADDRESS_LO_SUM:
1967 return TARGET_MIPS16 ? factor * 2 : factor;
1969 case ADDRESS_CONST_INT:
1972 case ADDRESS_SYMBOLIC:
1973 return factor * mips_symbol_insns (addr.symbol_type, mode);
1978 /* Return the number of instructions needed to load constant X.
1979 Return 0 if X isn't a valid constant. */
1982 mips_const_insns (rtx x)
1984 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1985 enum mips_symbol_type symbol_type;
1988 switch (GET_CODE (x))
1991 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
1993 || !mips_split_p[symbol_type])
1996 /* This is simply an LUI for normal mode. It is an extended
1997 LI followed by an extended SLL for MIPS16. */
1998 return TARGET_MIPS16 ? 4 : 1;
2002 /* Unsigned 8-bit constants can be loaded using an unextended
2003 LI instruction. Unsigned 16-bit constants can be loaded
2004 using an extended LI. Negative constants must be loaded
2005 using LI and then negated. */
2006 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2007 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2008 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2009 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2012 return mips_build_integer (codes, INTVAL (x));
2016 /* Allow zeros for normal mode, where we can use $0. */
2017 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2023 /* See if we can refer to X directly. */
2024 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2025 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2027 /* Otherwise try splitting the constant into a base and offset.
2028 16-bit offsets can be added using an extra ADDIU. Larger offsets
2029 must be calculated separately and then added to the base. */
2030 split_const (x, &x, &offset);
2033 int n = mips_const_insns (x);
2036 if (SMALL_INT (offset))
2039 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2046 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2054 /* Return the number of instructions needed to implement INSN,
2055 given that it loads from or stores to MEM. Count extended
2056 MIPS16 instructions as two instructions. */
2059 mips_load_store_insns (rtx mem, rtx insn)
2061 enum machine_mode mode;
2065 gcc_assert (MEM_P (mem));
2066 mode = GET_MODE (mem);
2068 /* Try to prove that INSN does not need to be split. */
2069 might_split_p = true;
2070 if (GET_MODE_BITSIZE (mode) == 64)
2072 set = single_set (insn);
2073 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2074 might_split_p = false;
2077 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2080 /* Return the number of instructions needed for an integer division. */
2083 mips_idiv_insns (void)
2088 if (TARGET_CHECK_ZERO_DIV)
2090 if (GENERATE_DIVIDE_TRAPS)
2096 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2101 /* Emit a move from SRC to DEST. Assume that the move expanders can
2102 handle all moves if !can_create_pseudo_p (). The distinction is
2103 important because, unlike emit_move_insn, the move expanders know
2104 how to force Pmode objects into the constant pool even when the
2105 constant pool address is not itself legitimate. */
2108 mips_emit_move (rtx dest, rtx src)
2110 return (can_create_pseudo_p ()
2111 ? emit_move_insn (dest, src)
2112 : emit_move_insn_1 (dest, src));
2115 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2118 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2120 emit_insn (gen_rtx_SET (VOIDmode, target,
2121 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2124 /* Copy VALUE to a register and return that register. If new pseudos
2125 are allowed, copy it into a new register, otherwise use DEST. */
2128 mips_force_temporary (rtx dest, rtx value)
2130 if (can_create_pseudo_p ())
2131 return force_reg (Pmode, value);
2134 mips_emit_move (dest, value);
2139 /* Return a pseudo register that contains the value of $gp throughout
2140 the current function. Such registers are needed by MIPS16 functions,
2141 for which $gp itself is not a valid base register or addition operand. */
2144 mips16_gp_pseudo_reg (void)
2146 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2147 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2149 /* Don't emit an instruction to initialize the pseudo register if
2150 we are being called from the tree optimizers' cost-calculation
2152 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2153 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2155 rtx insn, scan, after;
2157 /* We want GCC to treat the register's value as constant, so that
2158 it can be rematerialized on demand. */
2159 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2161 push_topmost_sequence ();
2162 /* We need to emit the initialization after the FUNCTION_BEG
2163 note, so that it will be integrated. */
2164 after = get_insns ();
2165 for (scan = after; scan != NULL_RTX; scan = NEXT_INSN (scan))
2166 if (NOTE_P (scan) && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
2171 insn = emit_insn_after (insn, after);
2172 pop_topmost_sequence ();
2174 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2177 return cfun->machine->mips16_gp_pseudo_rtx;
2180 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2181 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2182 constant in that context and can be split into a high part and a LO_SUM.
2183 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2184 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2186 TEMP is as for mips_force_temporary and is used to load the high
2187 part into a register. */
2190 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
2192 enum mips_symbol_context context;
2193 enum mips_symbol_type symbol_type;
2196 context = (mode == MAX_MACHINE_MODE
2197 ? SYMBOL_CONTEXT_LEA
2198 : SYMBOL_CONTEXT_MEM);
2199 if (!mips_symbolic_constant_p (addr, context, &symbol_type)
2200 || mips_symbol_insns (symbol_type, mode) == 0
2201 || !mips_split_p[symbol_type])
2206 if (symbol_type == SYMBOL_GP_RELATIVE)
2208 if (!can_create_pseudo_p ())
2210 emit_insn (gen_load_const_gp (temp));
2214 high = mips16_gp_pseudo_reg ();
2218 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2219 high = mips_force_temporary (temp, high);
2221 *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
2226 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2227 then add CONST_INT OFFSET to the result. */
2230 mips_unspec_address_offset (rtx base, rtx offset,
2231 enum mips_symbol_type symbol_type)
2233 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2234 UNSPEC_ADDRESS_FIRST + symbol_type);
2235 if (offset != const0_rtx)
2236 base = gen_rtx_PLUS (Pmode, base, offset);
2237 return gen_rtx_CONST (Pmode, base);
2240 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2241 type SYMBOL_TYPE. */
2244 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2248 split_const (address, &base, &offset);
2249 return mips_unspec_address_offset (base, offset, symbol_type);
2252 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2253 high part to BASE and return the result. Just return BASE otherwise.
2254 TEMP is as for mips_force_temporary.
2256 The returned expression can be used as the first operand to a LO_SUM. */
2259 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2260 enum mips_symbol_type symbol_type)
2262 if (mips_split_p[symbol_type])
2264 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2265 addr = mips_force_temporary (temp, addr);
2266 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2271 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2272 mips_force_temporary; it is only needed when OFFSET is not a
2276 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2278 if (!SMALL_OPERAND (offset))
2284 /* Load the full offset into a register so that we can use
2285 an unextended instruction for the address itself. */
2286 high = GEN_INT (offset);
2291 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2292 high = GEN_INT (CONST_HIGH_PART (offset));
2293 offset = CONST_LOW_PART (offset);
2295 high = mips_force_temporary (temp, high);
2296 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2298 return plus_constant (reg, offset);
2301 /* The __tls_get_attr symbol. */
2302 static GTY(()) rtx mips_tls_symbol;
2304 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2305 the TLS symbol we are referencing and TYPE is the symbol type to use
2306 (either global dynamic or local dynamic). V0 is an RTX for the
2307 return value location. */
2310 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2312 rtx insn, loc, tga, a0;
2314 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2316 if (!mips_tls_symbol)
2317 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2319 loc = mips_unspec_address (sym, type);
2323 emit_insn (gen_rtx_SET (Pmode, a0,
2324 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2325 tga = gen_const_mem (Pmode, mips_tls_symbol);
2326 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2327 CONST_OR_PURE_CALL_P (insn) = 1;
2328 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2329 insn = get_insns ();
2336 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2337 its address. The return value will be both a valid address and a valid
2338 SET_SRC (either a REG or a LO_SUM). */
2341 mips_legitimize_tls_address (rtx loc)
2343 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2344 enum tls_model model;
2348 sorry ("MIPS16 TLS");
2349 return gen_reg_rtx (Pmode);
2352 model = SYMBOL_REF_TLS_MODEL (loc);
2353 /* Only TARGET_ABICALLS code can have more than one module; other
2354 code must be be static and should not use a GOT. All TLS models
2355 reduce to local exec in this situation. */
2356 if (!TARGET_ABICALLS)
2357 model = TLS_MODEL_LOCAL_EXEC;
2361 case TLS_MODEL_GLOBAL_DYNAMIC:
2362 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2363 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2364 dest = gen_reg_rtx (Pmode);
2365 emit_libcall_block (insn, dest, v0, loc);
2368 case TLS_MODEL_LOCAL_DYNAMIC:
2369 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2370 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2371 tmp1 = gen_reg_rtx (Pmode);
2373 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2374 share the LDM result with other LD model accesses. */
2375 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2377 emit_libcall_block (insn, tmp1, v0, eqv);
2379 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2380 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2381 mips_unspec_address (loc, SYMBOL_DTPREL));
2384 case TLS_MODEL_INITIAL_EXEC:
2385 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2386 tmp1 = gen_reg_rtx (Pmode);
2387 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2388 if (Pmode == DImode)
2390 emit_insn (gen_tls_get_tp_di (v1));
2391 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2395 emit_insn (gen_tls_get_tp_si (v1));
2396 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2398 dest = gen_reg_rtx (Pmode);
2399 emit_insn (gen_add3_insn (dest, tmp1, v1));
2402 case TLS_MODEL_LOCAL_EXEC:
2403 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2404 if (Pmode == DImode)
2405 emit_insn (gen_tls_get_tp_di (v1));
2407 emit_insn (gen_tls_get_tp_si (v1));
2409 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2410 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2411 mips_unspec_address (loc, SYMBOL_TPREL));
2420 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2421 be legitimized in a way that the generic machinery might not expect,
2422 put the new address in *XLOC and return true. MODE is the mode of
2423 the memory being accessed. */
2426 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2429 HOST_WIDE_INT offset;
2431 if (mips_tls_symbol_p (*xloc))
2433 *xloc = mips_legitimize_tls_address (*xloc);
2437 /* See if the address can split into a high part and a LO_SUM. */
2438 if (mips_split_symbol (NULL, *xloc, mode, xloc))
2441 /* Handle BASE + OFFSET using mips_add_offset. */
2442 mips_split_plus (*xloc, &base, &offset);
2445 if (!mips_valid_base_register_p (base, mode, false))
2446 base = copy_to_mode_reg (Pmode, base);
2447 *xloc = mips_add_offset (NULL, base, offset);
2453 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2456 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2458 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2459 enum machine_mode mode;
2460 unsigned int i, num_ops;
2463 mode = GET_MODE (dest);
2464 num_ops = mips_build_integer (codes, value);
2466 /* Apply each binary operation to X. Invariant: X is a legitimate
2467 source operand for a SET pattern. */
2468 x = GEN_INT (codes[0].value);
2469 for (i = 1; i < num_ops; i++)
2471 if (!can_create_pseudo_p ())
2473 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2477 x = force_reg (mode, x);
2478 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2481 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2484 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2485 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2489 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2493 /* Split moves of big integers into smaller pieces. */
2494 if (splittable_const_int_operand (src, mode))
2496 mips_move_integer (dest, dest, INTVAL (src));
2500 /* Split moves of symbolic constants into high/low pairs. */
2501 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2503 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2507 /* Generate the appropriate access sequences for TLS symbols. */
2508 if (mips_tls_symbol_p (src))
2510 mips_emit_move (dest, mips_legitimize_tls_address (src));
2514 /* If we have (const (plus symbol offset)), and that expression cannot
2515 be forced into memory, load the symbol first and add in the offset.
2516 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2517 forced into memory, as it usually produces better code. */
2518 split_const (src, &base, &offset);
2519 if (offset != const0_rtx
2520 && (targetm.cannot_force_const_mem (src)
2521 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2523 base = mips_force_temporary (dest, base);
2524 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2528 src = force_const_mem (mode, src);
2530 /* When using explicit relocs, constant pool references are sometimes
2531 not legitimate addresses. */
2532 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2533 mips_emit_move (dest, src);
2536 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2537 sequence that is valid. */
2540 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2542 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2544 mips_emit_move (dest, force_reg (mode, src));
2548 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2549 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2550 && REG_P (src) && MD_REG_P (REGNO (src))
2551 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2553 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2554 if (GET_MODE_SIZE (mode) <= 4)
2555 emit_insn (gen_mfhilo_si (gen_lowpart (SImode, dest),
2556 gen_lowpart (SImode, src),
2557 gen_rtx_REG (SImode, other_regno)));
2559 emit_insn (gen_mfhilo_di (gen_lowpart (DImode, dest),
2560 gen_lowpart (DImode, src),
2561 gen_rtx_REG (DImode, other_regno)));
2565 /* We need to deal with constants that would be legitimate
2566 immediate_operands but aren't legitimate move_operands. */
2567 if (CONSTANT_P (src) && !move_operand (src, mode))
2569 mips_legitimize_const_move (mode, dest, src);
2570 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2576 /* Return true if value X in context CONTEXT is a small-data address
2577 that can be rewritten as a LO_SUM. */
2580 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2582 enum mips_symbol_type symbol_type;
2584 return (TARGET_EXPLICIT_RELOCS
2585 && mips_symbolic_constant_p (x, context, &symbol_type)
2586 && symbol_type == SYMBOL_GP_RELATIVE);
2589 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2590 containing MEM, or null if none. */
2593 mips_small_data_pattern_1 (rtx *loc, void *data)
2595 enum mips_symbol_context context;
2597 if (GET_CODE (*loc) == LO_SUM)
2602 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2607 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2608 return mips_rewrite_small_data_p (*loc, context);
2611 /* Return true if OP refers to small data symbols directly, not through
2615 mips_small_data_pattern_p (rtx op)
2617 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
2620 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2621 DATA is the containing MEM, or null if none. */
2624 mips_rewrite_small_data_1 (rtx *loc, void *data)
2626 enum mips_symbol_context context;
2630 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2634 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2635 if (mips_rewrite_small_data_p (*loc, context))
2636 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2638 if (GET_CODE (*loc) == LO_SUM)
2644 /* Rewrite instruction pattern PATTERN so that it refers to small data
2645 using explicit relocations. */
2648 mips_rewrite_small_data (rtx pattern)
2650 pattern = copy_insn (pattern);
2651 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
2655 /* We need a lot of little routines to check the range of MIPS16 immediate
2659 m16_check_op (rtx op, int low, int high, int mask)
2661 return (GET_CODE (op) == CONST_INT
2662 && IN_RANGE (INTVAL (op), low, high)
2663 && (INTVAL (op) & mask) == 0);
2667 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2669 return m16_check_op (op, 0x1, 0x8, 0);
2673 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2675 return m16_check_op (op, -0x8, 0x7, 0);
2679 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2681 return m16_check_op (op, -0x7, 0x8, 0);
2685 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2687 return m16_check_op (op, -0x10, 0xf, 0);
2691 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2693 return m16_check_op (op, -0xf, 0x10, 0);
2697 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2699 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
2703 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2705 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
2709 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2711 return m16_check_op (op, -0x80, 0x7f, 0);
2715 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2717 return m16_check_op (op, -0x7f, 0x80, 0);
2721 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2723 return m16_check_op (op, 0x0, 0xff, 0);
2727 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2729 return m16_check_op (op, -0xff, 0x0, 0);
2733 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2735 return m16_check_op (op, -0x1, 0xfe, 0);
2739 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2741 return m16_check_op (op, 0x0, 0xff << 2, 3);
2745 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2747 return m16_check_op (op, -0xff << 2, 0x0, 3);
2751 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2753 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
2757 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2759 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
2762 /* The cost of loading values from the constant pool. It should be
2763 larger than the cost of any constant we want to synthesize inline. */
2764 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2766 /* Return the cost of X when used as an operand to the MIPS16 instruction
2767 that implements CODE. Return -1 if there is no such instruction, or if
2768 X is not a valid immediate operand for it. */
2771 mips16_constant_cost (int code, HOST_WIDE_INT x)
2778 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2779 other shifts are extended. The shift patterns truncate the shift
2780 count to the right size, so there are no out-of-range values. */
2781 if (IN_RANGE (x, 1, 8))
2783 return COSTS_N_INSNS (1);
2786 if (IN_RANGE (x, -128, 127))
2788 if (SMALL_OPERAND (x))
2789 return COSTS_N_INSNS (1);
2793 /* Like LE, but reject the always-true case. */
2797 /* We add 1 to the immediate and use SLT. */
2800 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2803 if (IN_RANGE (x, 0, 255))
2805 if (SMALL_OPERAND_UNSIGNED (x))
2806 return COSTS_N_INSNS (1);
2811 /* Equality comparisons with 0 are cheap. */
2821 /* Return true if there is a non-MIPS16 instruction that implements CODE
2822 and if that instruction accepts X as an immediate operand. */
2825 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2832 /* All shift counts are truncated to a valid constant. */
2837 /* Likewise rotates, if the target supports rotates at all. */
2843 /* These instructions take 16-bit unsigned immediates. */
2844 return SMALL_OPERAND_UNSIGNED (x);
2849 /* These instructions take 16-bit signed immediates. */
2850 return SMALL_OPERAND (x);
2856 /* The "immediate" forms of these instructions are really
2857 implemented as comparisons with register 0. */
2862 /* Likewise, meaning that the only valid immediate operand is 1. */
2866 /* We add 1 to the immediate and use SLT. */
2867 return SMALL_OPERAND (x + 1);
2870 /* Likewise SLTU, but reject the always-true case. */
2871 return SMALL_OPERAND (x + 1) && x + 1 != 0;
2875 /* The bit position and size are immediate operands. */
2876 return ISA_HAS_EXT_INS;
2879 /* By default assume that $0 can be used for 0. */
2884 /* Return the cost of binary operation X, given that the instruction
2885 sequence for a word-sized or smaller operation has cost SINGLE_COST
2886 and that the sequence of a double-word operation has cost DOUBLE_COST. */
2889 mips_binary_cost (rtx x, int single_cost, int double_cost)
2893 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
2898 + rtx_cost (XEXP (x, 0), 0)
2899 + rtx_cost (XEXP (x, 1), GET_CODE (x)));
2902 /* Return the cost of floating-point multiplications of mode MODE. */
2905 mips_fp_mult_cost (enum machine_mode mode)
2907 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
2910 /* Return the cost of floating-point divisions of mode MODE. */
2913 mips_fp_div_cost (enum machine_mode mode)
2915 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
2918 /* Return the cost of sign-extending OP to mode MODE, not including the
2919 cost of OP itself. */
2922 mips_sign_extend_cost (enum machine_mode mode, rtx op)
2925 /* Extended loads are as cheap as unextended ones. */
2928 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2929 /* A sign extension from SImode to DImode in 64-bit mode is free. */
2932 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
2933 /* We can use SEB or SEH. */
2934 return COSTS_N_INSNS (1);
2936 /* We need to use a shift left and a shift right. */
2937 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2940 /* Return the cost of zero-extending OP to mode MODE, not including the
2941 cost of OP itself. */
2944 mips_zero_extend_cost (enum machine_mode mode, rtx op)
2947 /* Extended loads are as cheap as unextended ones. */
2950 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2951 /* We need a shift left by 32 bits and a shift right by 32 bits. */
2952 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2954 if (GENERATE_MIPS16E)
2955 /* We can use ZEB or ZEH. */
2956 return COSTS_N_INSNS (1);
2959 /* We need to load 0xff or 0xffff into a register and use AND. */
2960 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
2962 /* We can use ANDI. */
2963 return COSTS_N_INSNS (1);
2966 /* Implement TARGET_RTX_COSTS. */
2969 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2971 enum machine_mode mode = GET_MODE (x);
2972 bool float_mode_p = FLOAT_MODE_P (mode);
2976 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
2977 appear in the instruction stream, and the cost of a comparison is
2978 really the cost of the branch or scc condition. At the time of
2979 writing, GCC only uses an explicit outer COMPARE code when optabs
2980 is testing whether a constant is expensive enough to force into a
2981 register. We want optabs to pass such constants through the MIPS
2982 expanders instead, so make all constants very cheap here. */
2983 if (outer_code == COMPARE)
2985 gcc_assert (CONSTANT_P (x));
2993 /* Treat *clear_upper32-style ANDs as having zero cost in the
2994 second operand. The cost is entirely in the first operand.
2996 ??? This is needed because we would otherwise try to CSE
2997 the constant operand. Although that's the right thing for
2998 instructions that continue to be a register operation throughout
2999 compilation, it is disastrous for instructions that could
3000 later be converted into a memory operation. */
3002 && outer_code == AND
3003 && UINTVAL (x) == 0xffffffff)
3011 cost = mips16_constant_cost (outer_code, INTVAL (x));
3020 /* When not optimizing for size, we care more about the cost
3021 of hot code, and hot code is often in a loop. If a constant
3022 operand needs to be forced into a register, we will often be
3023 able to hoist the constant load out of the loop, so the load
3024 should not contribute to the cost. */
3026 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3038 if (force_to_mem_operand (x, VOIDmode))
3040 *total = COSTS_N_INSNS (1);
3043 cost = mips_const_insns (x);
3046 /* If the constant is likely to be stored in a GPR, SETs of
3047 single-insn constants are as cheap as register sets; we
3048 never want to CSE them.
3050 Don't reduce the cost of storing a floating-point zero in
3051 FPRs. If we have a zero in an FPR for other reasons, we
3052 can get better cfg-cleanup and delayed-branch results by
3053 using it consistently, rather than using $0 sometimes and
3054 an FPR at other times. Also, moves between floating-point
3055 registers are sometimes cheaper than (D)MTC1 $0. */
3057 && outer_code == SET
3058 && !(float_mode_p && TARGET_HARD_FLOAT))
3060 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3061 want to CSE the constant itself. It is usually better to
3062 have N copies of the last operation in the sequence and one
3063 shared copy of the other operations. (Note that this is
3064 not true for MIPS16 code, where the final operation in the
3065 sequence is often an extended instruction.)
3067 Also, if we have a CONST_INT, we don't know whether it is
3068 for a word or doubleword operation, so we cannot rely on
3069 the result of mips_build_integer. */
3070 else if (!TARGET_MIPS16
3071 && (outer_code == SET || mode == VOIDmode))
3073 *total = COSTS_N_INSNS (cost);
3076 /* The value will need to be fetched from the constant pool. */
3077 *total = CONSTANT_POOL_COST;
3081 /* If the address is legitimate, return the number of
3082 instructions it needs. */
3084 cost = mips_address_insns (addr, mode, true);
3087 *total = COSTS_N_INSNS (cost + 1);
3090 /* Check for a scaled indexed address. */
3091 if (mips_lwxs_address_p (addr))
3093 *total = COSTS_N_INSNS (2);
3096 /* Otherwise use the default handling. */
3100 *total = COSTS_N_INSNS (6);
3104 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3108 /* Check for a *clear_upper32 pattern and treat it like a zero
3109 extension. See the pattern's comment for details. */
3112 && CONST_INT_P (XEXP (x, 1))
3113 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3115 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3116 + rtx_cost (XEXP (x, 0), 0));
3123 /* Double-word operations use two single-word operations. */
3124 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3132 if (CONSTANT_P (XEXP (x, 1)))
3133 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3135 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3140 *total = mips_cost->fp_add;
3142 *total = COSTS_N_INSNS (4);
3146 /* Low-part immediates need an extended MIPS16 instruction. */
3147 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3148 + rtx_cost (XEXP (x, 0), 0));
3163 /* Branch comparisons have VOIDmode, so use the first operand's
3165 mode = GET_MODE (XEXP (x, 0));
3166 if (FLOAT_MODE_P (mode))
3168 *total = mips_cost->fp_add;
3171 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3176 && ISA_HAS_NMADD_NMSUB (mode)
3177 && TARGET_FUSED_MADD
3178 && !HONOR_NANS (mode)
3179 && !HONOR_SIGNED_ZEROS (mode))
3181 /* See if we can use NMADD or NMSUB. See mips.md for the
3182 associated patterns. */
3183 rtx op0 = XEXP (x, 0);
3184 rtx op1 = XEXP (x, 1);
3185 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3187 *total = (mips_fp_mult_cost (mode)
3188 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
3189 + rtx_cost (XEXP (op0, 1), 0)
3190 + rtx_cost (op1, 0));
3193 if (GET_CODE (op1) == MULT)
3195 *total = (mips_fp_mult_cost (mode)
3197 + rtx_cost (XEXP (op1, 0), 0)
3198 + rtx_cost (XEXP (op1, 1), 0));
3207 /* If this is part of a MADD or MSUB, treat the PLUS as
3210 && TARGET_FUSED_MADD
3211 && GET_CODE (XEXP (x, 0)) == MULT)
3214 *total = mips_cost->fp_add;
3218 /* Double-word operations require three single-word operations and
3219 an SLTU. The MIPS16 version then needs to move the result of
3220 the SLTU from $24 to a MIPS16 register. */
3221 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3222 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3227 && ISA_HAS_NMADD_NMSUB (mode)
3228 && TARGET_FUSED_MADD
3229 && !HONOR_NANS (mode)
3230 && HONOR_SIGNED_ZEROS (mode))
3232 /* See if we can use NMADD or NMSUB. See mips.md for the
3233 associated patterns. */
3234 rtx op = XEXP (x, 0);
3235 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3236 && GET_CODE (XEXP (op, 0)) == MULT)
3238 *total = (mips_fp_mult_cost (mode)
3239 + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
3240 + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
3241 + rtx_cost (XEXP (op, 1), 0));
3247 *total = mips_cost->fp_add;
3249 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3254 *total = mips_fp_mult_cost (mode);
3255 else if (mode == DImode && !TARGET_64BIT)
3256 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3257 where the mulsidi3 always includes an MFHI and an MFLO. */
3258 *total = (optimize_size
3259 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3260 : mips_cost->int_mult_si * 3 + 6);
3261 else if (optimize_size)
3262 *total = (ISA_HAS_MUL3 ? 1 : 2);
3263 else if (mode == DImode)
3264 *total = mips_cost->int_mult_di;
3266 *total = mips_cost->int_mult_si;
3270 /* Check for a reciprocal. */
3273 && flag_unsafe_math_optimizations
3274 && XEXP (x, 0) == CONST1_RTX (mode))
3276 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3277 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3278 division as being free. */
3279 *total = rtx_cost (XEXP (x, 1), 0);
3281 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
3290 *total = mips_fp_div_cost (mode);
3299 /* It is our responsibility to make division by a power of 2
3300 as cheap as 2 register additions if we want the division
3301 expanders to be used for such operations; see the setting
3302 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3303 should always produce shorter code than using
3304 expand_sdiv2_pow2. */
3306 && CONST_INT_P (XEXP (x, 1))
3307 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3309 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
3312 *total = COSTS_N_INSNS (mips_idiv_insns ());
3314 else if (mode == DImode)
3315 *total = mips_cost->int_div_di;
3317 *total = mips_cost->int_div_si;
3321 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3325 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3329 case UNSIGNED_FLOAT:
3332 case FLOAT_TRUNCATE:
3333 *total = mips_cost->fp_add;
3341 /* Implement TARGET_ADDRESS_COST. */
3344 mips_address_cost (rtx addr)
3346 return mips_address_insns (addr, SImode, false);
3349 /* Return one word of double-word value OP, taking into account the fixed
3350 endianness of certain registers. HIGH_P is true to select the high part,
3351 false to select the low part. */
3354 mips_subword (rtx op, bool high_p)
3356 unsigned int byte, offset;
3357 enum machine_mode mode;
3359 mode = GET_MODE (op);
3360 if (mode == VOIDmode)
3363 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3364 byte = UNITS_PER_WORD;
3368 if (FP_REG_RTX_P (op))
3370 /* Paired FPRs are always ordered little-endian. */
3371 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3372 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3376 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3378 return simplify_gen_subreg (word_mode, op, mode, byte);
3381 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3384 mips_split_64bit_move_p (rtx dest, rtx src)
3389 /* FPR-to-FPR moves can be done in a single instruction, if they're
3391 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3394 /* Check for floating-point loads and stores. */
3395 if (ISA_HAS_LDC1_SDC1)
3397 if (FP_REG_RTX_P (dest) && MEM_P (src))
3399 if (FP_REG_RTX_P (src) && MEM_P (dest))
3405 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3406 this function handles 64-bit moves for which mips_split_64bit_move_p
3407 holds. For 64-bit targets, this function handles 128-bit moves. */
3410 mips_split_doubleword_move (rtx dest, rtx src)
3412 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3414 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3415 emit_insn (gen_move_doubleword_fprdi (dest, src));
3416 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3417 emit_insn (gen_move_doubleword_fprdf (dest, src));
3418 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3419 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3420 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3421 emit_insn (gen_move_doubleword_fprtf (dest, src));
3427 /* The operation can be split into two normal moves. Decide in
3428 which order to do them. */
3431 low_dest = mips_subword (dest, false);
3432 if (REG_P (low_dest)
3433 && reg_overlap_mentioned_p (low_dest, src))
3435 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3436 mips_emit_move (low_dest, mips_subword (src, false));
3440 mips_emit_move (low_dest, mips_subword (src, false));
3441 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3446 /* Return the appropriate instructions to move SRC into DEST. Assume
3447 that SRC is operand 1 and DEST is operand 0. */
3450 mips_output_move (rtx dest, rtx src)
3452 enum rtx_code dest_code, src_code;
3453 enum machine_mode mode;
3454 enum mips_symbol_type symbol_type;
3457 dest_code = GET_CODE (dest);
3458 src_code = GET_CODE (src);
3459 mode = GET_MODE (dest);
3460 dbl_p = (GET_MODE_SIZE (mode) == 8);
3462 if (dbl_p && mips_split_64bit_move_p (dest, src))
3465 if ((src_code == REG && GP_REG_P (REGNO (src)))
3466 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3468 if (dest_code == REG)
3470 if (GP_REG_P (REGNO (dest)))
3471 return "move\t%0,%z1";
3473 if (MD_REG_P (REGNO (dest)))
3476 if (DSP_ACC_REG_P (REGNO (dest)))
3478 static char retval[] = "mt__\t%z1,%q0";
3480 retval[2] = reg_names[REGNO (dest)][4];
3481 retval[3] = reg_names[REGNO (dest)][5];
3485 if (FP_REG_P (REGNO (dest)))
3486 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3488 if (ALL_COP_REG_P (REGNO (dest)))
3490 static char retval[] = "dmtc_\t%z1,%0";
3492 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3493 return dbl_p ? retval : retval + 1;
3496 if (dest_code == MEM)
3497 return dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0";
3499 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3501 if (src_code == REG)
3503 /* Handled by separate patterns. */
3504 gcc_assert (!MD_REG_P (REGNO (src)));
3506 if (DSP_ACC_REG_P (REGNO (src)))
3508 static char retval[] = "mf__\t%0,%q1";
3510 retval[2] = reg_names[REGNO (src)][4];
3511 retval[3] = reg_names[REGNO (src)][5];
3515 if (FP_REG_P (REGNO (src)))
3516 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3518 if (ALL_COP_REG_P (REGNO (src)))
3520 static char retval[] = "dmfc_\t%0,%1";
3522 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3523 return dbl_p ? retval : retval + 1;
3526 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3527 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3530 if (src_code == MEM)
3531 return dbl_p ? "ld\t%0,%1" : "lw\t%0,%1";
3533 if (src_code == CONST_INT)
3535 /* Don't use the X format for the operand itself, because that
3536 will give out-of-range numbers for 64-bit hosts and 32-bit
3539 return "li\t%0,%1\t\t\t# %X1";
3541 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
3544 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
3548 if (src_code == HIGH)
3549 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3551 if (CONST_GP_P (src))
3552 return "move\t%0,%1";
3554 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3555 && mips_lo_relocs[symbol_type] != 0)
3557 /* A signed 16-bit constant formed by applying a relocation
3558 operator to a symbolic address. */
3559 gcc_assert (!mips_split_p[symbol_type]);
3560 return "li\t%0,%R1";
3563 if (symbolic_operand (src, VOIDmode))
3565 gcc_assert (TARGET_MIPS16
3566 ? TARGET_MIPS16_TEXT_LOADS
3567 : !TARGET_EXPLICIT_RELOCS);
3568 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
3571 if (src_code == REG && FP_REG_P (REGNO (src)))
3573 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3575 if (GET_MODE (dest) == V2SFmode)
3576 return "mov.ps\t%0,%1";
3578 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
3581 if (dest_code == MEM)
3582 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
3584 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3586 if (src_code == MEM)
3587 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
3589 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3591 static char retval[] = "l_c_\t%0,%1";
3593 retval[1] = (dbl_p ? 'd' : 'w');
3594 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3597 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3599 static char retval[] = "s_c_\t%1,%0";
3601 retval[1] = (dbl_p ? 'd' : 'w');
3602 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3608 /* Return true if CMP1 is a suitable second operand for integer ordering
3609 test CODE. See also the *sCC patterns in mips.md. */
3612 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
3618 return reg_or_0_operand (cmp1, VOIDmode);
3622 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3626 return arith_operand (cmp1, VOIDmode);
3629 return sle_operand (cmp1, VOIDmode);
3632 return sleu_operand (cmp1, VOIDmode);
3639 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
3640 integer ordering test *CODE, or if an equivalent combination can
3641 be formed by adjusting *CODE and *CMP1. When returning true, update
3642 *CODE and *CMP1 with the chosen code and operand, otherwise leave
3646 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
3647 enum machine_mode mode)
3649 HOST_WIDE_INT plus_one;
3651 if (mips_int_order_operand_ok_p (*code, *cmp1))
3654 if (GET_CODE (*cmp1) == CONST_INT)
3658 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3659 if (INTVAL (*cmp1) < plus_one)
3662 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3668 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3672 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3683 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
3684 in TARGET. CMP0 and TARGET are register_operands that have the same
3685 integer mode. If INVERT_PTR is nonnull, it's OK to set TARGET to the
3686 inverse of the result and flip *INVERT_PTR instead. */
3689 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
3690 rtx target, rtx cmp0, rtx cmp1)
3692 enum machine_mode mode;
3694 /* First see if there is a MIPS instruction that can do this operation.
3695 If not, try doing the same for the inverse operation. If that also
3696 fails, force CMP1 into a register and try again. */
3697 mode = GET_MODE (target);
3698 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
3699 mips_emit_binary (code, target, cmp0, cmp1);
3702 enum rtx_code inv_code = reverse_condition (code);
3703 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
3705 cmp1 = force_reg (mode, cmp1);
3706 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
3708 else if (invert_ptr == 0)
3710 rtx inv_target = gen_reg_rtx (mode);
3711 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3712 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3716 *invert_ptr = !*invert_ptr;
3717 mips_emit_binary (inv_code, target, cmp0, cmp1);
3722 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3723 The register will have the same mode as CMP0. */
3726 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3728 if (cmp1 == const0_rtx)
3731 if (uns_arith_operand (cmp1, VOIDmode))
3732 return expand_binop (GET_MODE (cmp0), xor_optab,
3733 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3735 return expand_binop (GET_MODE (cmp0), sub_optab,
3736 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3739 /* Convert *CODE into a code that can be used in a floating-point
3740 scc instruction (C.cond.fmt). Return true if the values of
3741 the condition code registers will be inverted, with 0 indicating
3742 that the condition holds. */
3745 mips_reversed_fp_cond (enum rtx_code *code)
3752 *code = reverse_condition_maybe_unordered (*code);
3760 /* Convert a comparison into something that can be used in a branch or
3761 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3762 being compared and *CODE is the code used to compare them.
3764 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3765 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
3766 otherwise any standard branch condition can be used. The standard branch
3769 - EQ or NE between two registers.
3770 - any comparison between a register and zero. */
3773 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3775 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3777 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3779 *op0 = cmp_operands[0];
3780 *op1 = cmp_operands[1];
3782 else if (*code == EQ || *code == NE)
3786 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3791 *op0 = cmp_operands[0];
3792 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3797 /* The comparison needs a separate scc instruction. Store the
3798 result of the scc in *OP0 and compare it against zero. */
3799 bool invert = false;
3800 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3801 mips_emit_int_order_test (*code, &invert, *op0,
3802 cmp_operands[0], cmp_operands[1]);
3803 *code = (invert ? EQ : NE);
3807 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
3809 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
3810 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
3816 enum rtx_code cmp_code;
3818 /* Floating-point tests use a separate C.cond.fmt comparison to
3819 set a condition code register. The branch or conditional move
3820 will then compare that register against zero.
3822 Set CMP_CODE to the code of the comparison instruction and
3823 *CODE to the code that the branch or move should use. */
3825 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
3827 ? gen_reg_rtx (CCmode)
3828 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3830 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3834 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3835 Store the result in TARGET and return true if successful.
3837 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3840 mips_expand_scc (enum rtx_code code, rtx target)
3842 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3845 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3846 if (code == EQ || code == NE)
3848 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3849 mips_emit_binary (code, target, zie, const0_rtx);
3852 mips_emit_int_order_test (code, 0, target,
3853 cmp_operands[0], cmp_operands[1]);
3857 /* Compare cmp_operands[0] with cmp_operands[1] using comparison code
3858 CODE and jump to OPERANDS[0] if the condition holds. */
3861 mips_expand_conditional_branch (rtx *operands, enum rtx_code code)
3863 rtx op0, op1, condition;
3865 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3866 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3867 emit_jump_insn (gen_condjump (condition, operands[0]));
3872 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3873 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3876 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3877 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3882 reversed_p = mips_reversed_fp_cond (&cond);
3883 cmp_result = gen_reg_rtx (CCV2mode);
3884 emit_insn (gen_scc_ps (cmp_result,
3885 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3887 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3890 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3894 /* Compare cmp_operands[0] with cmp_operands[1] using the code of
3895 OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] if the condition
3896 holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
3899 mips_expand_conditional_move (rtx *operands)
3904 code = GET_CODE (operands[1]);
3905 mips_emit_compare (&code, &op0, &op1, true);
3906 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1),
3907 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3908 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
3909 operands[2], operands[3])));
3912 /* Compare cmp_operands[0] with cmp_operands[1] using rtl code CODE,
3913 then trap if the condition holds. */
3916 mips_expand_conditional_trap (enum rtx_code code)
3919 enum machine_mode mode;
3921 /* MIPS conditional trap instructions don't have GT or LE flavors,
3922 so we must swap the operands and convert to LT and GE respectively. */
3929 code = swap_condition (code);
3930 op0 = cmp_operands[1];
3931 op1 = cmp_operands[0];
3935 op0 = cmp_operands[0];
3936 op1 = cmp_operands[1];
3940 mode = GET_MODE (cmp_operands[0]);
3941 op0 = force_reg (mode, op0);
3942 if (!arith_operand (op1, mode))
3943 op1 = force_reg (mode, op1);
3945 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3946 gen_rtx_fmt_ee (code, mode, op0, op1),
3950 /* Initialize *CUM for a call to a function of type FNTYPE. */
3953 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
3955 memset (cum, 0, sizeof (*cum));
3956 cum->prototype = (fntype && prototype_p (fntype));
3957 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
3960 /* Fill INFO with information about a single argument. CUM is the
3961 cumulative state for earlier arguments. MODE is the mode of this
3962 argument and TYPE is its type (if known). NAMED is true if this
3963 is a named (fixed) argument rather than a variable one. */
3966 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
3967 enum machine_mode mode, tree type, int named)
3969 bool doubleword_aligned_p;
3970 unsigned int num_bytes, num_words, max_regs;
3972 /* Work out the size of the argument. */
3973 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3974 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3976 /* Decide whether it should go in a floating-point register, assuming
3977 one is free. Later code checks for availability.
3979 The checks against UNITS_PER_FPVALUE handle the soft-float and
3980 single-float cases. */
3984 /* The EABI conventions have traditionally been defined in terms
3985 of TYPE_MODE, regardless of the actual type. */
3986 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3987 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3988 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3993 /* Only leading floating-point scalars are passed in
3994 floating-point registers. We also handle vector floats the same
3995 say, which is OK because they are not covered by the standard ABI. */
3996 info->fpr_p = (!cum->gp_reg_found
3997 && cum->arg_number < 2
3999 || SCALAR_FLOAT_TYPE_P (type)
4000 || VECTOR_FLOAT_TYPE_P (type))
4001 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4002 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4003 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4008 /* Scalar, complex and vector floating-point types are passed in
4009 floating-point registers, as long as this is a named rather
4010 than a variable argument. */
4011 info->fpr_p = (named
4012 && (type == 0 || FLOAT_TYPE_P (type))
4013 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4014 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4015 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4016 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4018 /* ??? According to the ABI documentation, the real and imaginary
4019 parts of complex floats should be passed in individual registers.
4020 The real and imaginary parts of stack arguments are supposed
4021 to be contiguous and there should be an extra word of padding
4024 This has two problems. First, it makes it impossible to use a
4025 single "void *" va_list type, since register and stack arguments
4026 are passed differently. (At the time of writing, MIPSpro cannot
4027 handle complex float varargs correctly.) Second, it's unclear
4028 what should happen when there is only one register free.
4030 For now, we assume that named complex floats should go into FPRs
4031 if there are two FPRs free, otherwise they should be passed in the
4032 same way as a struct containing two floats. */
4034 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4035 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4037 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4038 info->fpr_p = false;
4048 /* See whether the argument has doubleword alignment. */
4049 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4051 /* Set REG_OFFSET to the register count we're interested in.
4052 The EABI allocates the floating-point registers separately,
4053 but the other ABIs allocate them like integer registers. */
4054 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4058 /* Advance to an even register if the argument is doubleword-aligned. */
4059 if (doubleword_aligned_p)
4060 info->reg_offset += info->reg_offset & 1;
4062 /* Work out the offset of a stack argument. */
4063 info->stack_offset = cum->stack_words;
4064 if (doubleword_aligned_p)
4065 info->stack_offset += info->stack_offset & 1;
4067 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4069 /* Partition the argument between registers and stack. */
4070 info->reg_words = MIN (num_words, max_regs);
4071 info->stack_words = num_words - info->reg_words;
4074 /* INFO describes a register argument that has the normal format for the
4075 argument's mode. Return the register it uses, assuming that FPRs are
4076 available if HARD_FLOAT_P. */
4079 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4081 if (!info->fpr_p || !hard_float_p)
4082 return GP_ARG_FIRST + info->reg_offset;
4083 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4084 /* In o32, the second argument is always passed in $f14
4085 for TARGET_DOUBLE_FLOAT, regardless of whether the
4086 first argument was a word or doubleword. */
4087 return FP_ARG_FIRST + 2;
4089 return FP_ARG_FIRST + info->reg_offset;
4092 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4095 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4097 return !TARGET_OLDABI;
4100 /* Implement FUNCTION_ARG. */
4103 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4104 tree type, int named)
4106 struct mips_arg_info info;
4108 /* We will be called with a mode of VOIDmode after the last argument
4109 has been seen. Whatever we return will be passed to the call expander.
4110 If we need a MIPS16 fp_code, return a REG with the code stored as
4112 if (mode == VOIDmode)
4114 if (TARGET_MIPS16 && cum->fp_code != 0)
4115 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4120 mips_get_arg_info (&info, cum, mode, type, named);
4122 /* Return straight away if the whole argument is passed on the stack. */
4123 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4126 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4127 contains a double in its entirety, then that 64-bit chunk is passed
4128 in a floating-point register. */
4130 && TARGET_HARD_FLOAT
4133 && TREE_CODE (type) == RECORD_TYPE
4134 && TYPE_SIZE_UNIT (type)
4135 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4139 /* First check to see if there is any such field. */
4140 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4141 if (TREE_CODE (field) == FIELD_DECL
4142 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4143 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4144 && host_integerp (bit_position (field), 0)
4145 && int_bit_position (field) % BITS_PER_WORD == 0)
4150 /* Now handle the special case by returning a PARALLEL
4151 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4152 chunks are passed in registers. */
4154 HOST_WIDE_INT bitpos;
4157 /* assign_parms checks the mode of ENTRY_PARM, so we must
4158 use the actual mode here. */
4159 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4162 field = TYPE_FIELDS (type);
4163 for (i = 0; i < info.reg_words; i++)
4167 for (; field; field = TREE_CHAIN (field))
4168 if (TREE_CODE (field) == FIELD_DECL
4169 && int_bit_position (field) >= bitpos)
4173 && int_bit_position (field) == bitpos
4174 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4175 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4176 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4178 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4181 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4182 GEN_INT (bitpos / BITS_PER_UNIT));
4184 bitpos += BITS_PER_WORD;
4190 /* Handle the n32/n64 conventions for passing complex floating-point
4191 arguments in FPR pairs. The real part goes in the lower register
4192 and the imaginary part goes in the upper register. */
4195 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4198 enum machine_mode inner;
4201 inner = GET_MODE_INNER (mode);
4202 regno = FP_ARG_FIRST + info.reg_offset;
4203 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4205 /* Real part in registers, imaginary part on stack. */
4206 gcc_assert (info.stack_words == info.reg_words);
4207 return gen_rtx_REG (inner, regno);
4211 gcc_assert (info.stack_words == 0);
4212 real = gen_rtx_EXPR_LIST (VOIDmode,
4213 gen_rtx_REG (inner, regno),
4215 imag = gen_rtx_EXPR_LIST (VOIDmode,
4217 regno + info.reg_words / 2),
4218 GEN_INT (GET_MODE_SIZE (inner)));
4219 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4223 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4226 /* Implement FUNCTION_ARG_ADVANCE. */
4229 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4230 tree type, int named)
4232 struct mips_arg_info info;
4234 mips_get_arg_info (&info, cum, mode, type, named);
4237 cum->gp_reg_found = true;
4239 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4240 an explanation of what this code does. It assumes that we're using
4241 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4243 if (cum->arg_number < 2 && info.fpr_p)
4244 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4246 /* Advance the register count. This has the effect of setting
4247 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4248 argument required us to skip the final GPR and pass the whole
4249 argument on the stack. */
4250 if (mips_abi != ABI_EABI || !info.fpr_p)
4251 cum->num_gprs = info.reg_offset + info.reg_words;
4252 else if (info.reg_words > 0)
4253 cum->num_fprs += MAX_FPRS_PER_FMT;
4255 /* Advance the stack word count. */
4256 if (info.stack_words > 0)
4257 cum->stack_words = info.stack_offset + info.stack_words;
4262 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4265 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4266 enum machine_mode mode, tree type, bool named)
4268 struct mips_arg_info info;
4270 mips_get_arg_info (&info, cum, mode, type, named);
4271 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4274 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4275 PARM_BOUNDARY bits of alignment, but will be given anything up
4276 to STACK_BOUNDARY bits if the type requires it. */
4279 mips_function_arg_boundary (enum machine_mode mode, tree type)
4281 unsigned int alignment;
4283 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4284 if (alignment < PARM_BOUNDARY)
4285 alignment = PARM_BOUNDARY;
4286 if (alignment > STACK_BOUNDARY)
4287 alignment = STACK_BOUNDARY;
4291 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4292 upward rather than downward. In other words, return true if the
4293 first byte of the stack slot has useful data, false if the last
4297 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4299 /* On little-endian targets, the first byte of every stack argument
4300 is passed in the first byte of the stack slot. */
4301 if (!BYTES_BIG_ENDIAN)
4304 /* Otherwise, integral types are padded downward: the last byte of a
4305 stack argument is passed in the last byte of the stack slot. */
4307 ? (INTEGRAL_TYPE_P (type)
4308 || POINTER_TYPE_P (type)
4309 || FIXED_POINT_TYPE_P (type))
4310 : (SCALAR_INT_MODE_P (mode)
4311 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4314 /* Big-endian o64 pads floating-point arguments downward. */
4315 if (mips_abi == ABI_O64)
4316 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4319 /* Other types are padded upward for o32, o64, n32 and n64. */
4320 if (mips_abi != ABI_EABI)
4323 /* Arguments smaller than a stack slot are padded downward. */
4324 if (mode != BLKmode)
4325 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4327 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4330 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4331 if the least significant byte of the register has useful data. Return
4332 the opposite if the most significant byte does. */
4335 mips_pad_reg_upward (enum machine_mode mode, tree type)
4337 /* No shifting is required for floating-point arguments. */
4338 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4339 return !BYTES_BIG_ENDIAN;
4341 /* Otherwise, apply the same padding to register arguments as we do
4342 to stack arguments. */
4343 return mips_pad_arg_upward (mode, type);
4346 /* Return nonzero when an argument must be passed by reference. */
4349 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4350 enum machine_mode mode, const_tree type,
4351 bool named ATTRIBUTE_UNUSED)
4353 if (mips_abi == ABI_EABI)
4357 /* ??? How should SCmode be handled? */
4358 if (mode == DImode || mode == DFmode
4359 || mode == DQmode || mode == UDQmode
4360 || mode == DAmode || mode == UDAmode)
4363 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4364 return size == -1 || size > UNITS_PER_WORD;
4368 /* If we have a variable-sized parameter, we have no choice. */
4369 return targetm.calls.must_pass_in_stack (mode, type);
4373 /* Implement TARGET_CALLEE_COPIES. */
4376 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4377 enum machine_mode mode ATTRIBUTE_UNUSED,
4378 const_tree type ATTRIBUTE_UNUSED, bool named)
4380 return mips_abi == ABI_EABI && named;
4383 /* See whether VALTYPE is a record whose fields should be returned in
4384 floating-point registers. If so, return the number of fields and
4385 list them in FIELDS (which should have two elements). Return 0
4388 For n32 & n64, a structure with one or two fields is returned in
4389 floating-point registers as long as every field has a floating-point
4393 mips_fpr_return_fields (const_tree valtype, tree *fields)
4401 if (TREE_CODE (valtype) != RECORD_TYPE)
4405 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4407 if (TREE_CODE (field) != FIELD_DECL)
4410 if (SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4416 fields[i++] = field;
4421 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4422 a value in the most significant part of $2/$3 if:
4424 - the target is big-endian;
4426 - the value has a structure or union type (we generalize this to
4427 cover aggregates from other languages too); and
4429 - the structure is not returned in floating-point registers. */
4432 mips_return_in_msb (const_tree valtype)
4436 return (TARGET_NEWABI
4437 && TARGET_BIG_ENDIAN
4438 && AGGREGATE_TYPE_P (valtype)
4439 && mips_fpr_return_fields (valtype, fields) == 0);
4442 /* Return true if the function return value MODE will get returned in a
4443 floating-point register. */
4446 mips_return_mode_in_fpr_p (enum machine_mode mode)
4448 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4449 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4450 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4451 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4454 /* Return a composite value in a pair of floating-point registers.
4455 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4456 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4459 For n32 & n64, $f0 always holds the first value and $f2 the second.
4460 Otherwise the values are packed together as closely as possible. */
4463 mips_return_fpr_pair (enum machine_mode mode,
4464 enum machine_mode mode1, HOST_WIDE_INT offset1,
4465 enum machine_mode mode2, HOST_WIDE_INT offset2)
4469 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4470 return gen_rtx_PARALLEL
4473 gen_rtx_EXPR_LIST (VOIDmode,
4474 gen_rtx_REG (mode1, FP_RETURN),
4476 gen_rtx_EXPR_LIST (VOIDmode,
4477 gen_rtx_REG (mode2, FP_RETURN + inc),
4478 GEN_INT (offset2))));
4482 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4483 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4484 VALTYPE is null and MODE is the mode of the return value. */
4487 mips_function_value (const_tree valtype, enum machine_mode mode)
4494 mode = TYPE_MODE (valtype);
4495 unsigned_p = TYPE_UNSIGNED (valtype);
4497 /* Since TARGET_PROMOTE_FUNCTION_RETURN unconditionally returns true,
4498 we must promote the mode just as PROMOTE_MODE does. */
4499 mode = promote_mode (valtype, mode, &unsigned_p, 1);
4501 /* Handle structures whose fields are returned in $f0/$f2. */
4502 switch (mips_fpr_return_fields (valtype, fields))
4505 return gen_rtx_REG (mode, FP_RETURN);
4508 return mips_return_fpr_pair (mode,
4509 TYPE_MODE (TREE_TYPE (fields[0])),
4510 int_byte_position (fields[0]),
4511 TYPE_MODE (TREE_TYPE (fields[1])),
4512 int_byte_position (fields[1]));
4515 /* If a value is passed in the most significant part of a register, see
4516 whether we have to round the mode up to a whole number of words. */
4517 if (mips_return_in_msb (valtype))
4519 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4520 if (size % UNITS_PER_WORD != 0)
4522 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4523 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4527 /* For EABI, the class of return register depends entirely on MODE.
4528 For example, "struct { some_type x; }" and "union { some_type x; }"
4529 are returned in the same way as a bare "some_type" would be.
4530 Other ABIs only use FPRs for scalar, complex or vector types. */
4531 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4532 return gen_rtx_REG (mode, GP_RETURN);
4537 /* Handle long doubles for n32 & n64. */
4539 return mips_return_fpr_pair (mode,
4541 DImode, GET_MODE_SIZE (mode) / 2);
4543 if (mips_return_mode_in_fpr_p (mode))
4545 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4546 return mips_return_fpr_pair (mode,
4547 GET_MODE_INNER (mode), 0,
4548 GET_MODE_INNER (mode),
4549 GET_MODE_SIZE (mode) / 2);
4551 return gen_rtx_REG (mode, FP_RETURN);
4555 return gen_rtx_REG (mode, GP_RETURN);
4558 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
4559 all BLKmode objects are returned in memory. Under the n32, n64
4560 and embedded ABIs, small structures are returned in a register.
4561 Objects with varying size must still be returned in memory, of
4565 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4567 return (TARGET_OLDABI
4568 ? TYPE_MODE (type) == BLKmode
4569 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
4572 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
4575 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4576 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4579 CUMULATIVE_ARGS local_cum;
4580 int gp_saved, fp_saved;
4582 /* The caller has advanced CUM up to, but not beyond, the last named
4583 argument. Advance a local copy of CUM past the last "real" named
4584 argument, to find out how many registers are left over. */
4586 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
4588 /* Found out how many registers we need to save. */
4589 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4590 fp_saved = (EABI_FLOAT_VARARGS_P
4591 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4600 ptr = plus_constant (virtual_incoming_args_rtx,
4601 REG_PARM_STACK_SPACE (cfun->decl)
4602 - gp_saved * UNITS_PER_WORD);
4603 mem = gen_frame_mem (BLKmode, ptr);
4604 set_mem_alias_set (mem, get_varargs_alias_set ());
4606 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4611 /* We can't use move_block_from_reg, because it will use
4613 enum machine_mode mode;
4616 /* Set OFF to the offset from virtual_incoming_args_rtx of
4617 the first float register. The FP save area lies below
4618 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4619 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
4620 off -= fp_saved * UNITS_PER_FPREG;
4622 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4624 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4625 i += MAX_FPRS_PER_FMT)
4629 ptr = plus_constant (virtual_incoming_args_rtx, off);
4630 mem = gen_frame_mem (mode, ptr);
4631 set_mem_alias_set (mem, get_varargs_alias_set ());
4632 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4633 off += UNITS_PER_HWFPVALUE;
4637 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4638 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4639 + fp_saved * UNITS_PER_FPREG);
4642 /* Implement TARGET_BUILTIN_VA_LIST. */
4645 mips_build_builtin_va_list (void)
4647 if (EABI_FLOAT_VARARGS_P)
4649 /* We keep 3 pointers, and two offsets.
4651 Two pointers are to the overflow area, which starts at the CFA.
4652 One of these is constant, for addressing into the GPR save area
4653 below it. The other is advanced up the stack through the
4656 The third pointer is to the bottom of the GPR save area.
4657 Since the FPR save area is just below it, we can address
4658 FPR slots off this pointer.
4660 We also keep two one-byte offsets, which are to be subtracted
4661 from the constant pointers to yield addresses in the GPR and
4662 FPR save areas. These are downcounted as float or non-float
4663 arguments are used, and when they get to zero, the argument
4664 must be obtained from the overflow region. */
4665 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4668 record = lang_hooks.types.make_type (RECORD_TYPE);
4670 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4672 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4674 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4676 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4677 unsigned_char_type_node);
4678 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4679 unsigned_char_type_node);
4680 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4681 warn on every user file. */
4682 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4683 array = build_array_type (unsigned_char_type_node,
4684 build_index_type (index));
4685 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4687 DECL_FIELD_CONTEXT (f_ovfl) = record;
4688 DECL_FIELD_CONTEXT (f_gtop) = record;
4689 DECL_FIELD_CONTEXT (f_ftop) = record;
4690 DECL_FIELD_CONTEXT (f_goff) = record;
4691 DECL_FIELD_CONTEXT (f_foff) = record;
4692 DECL_FIELD_CONTEXT (f_res) = record;
4694 TYPE_FIELDS (record) = f_ovfl;
4695 TREE_CHAIN (f_ovfl) = f_gtop;
4696 TREE_CHAIN (f_gtop) = f_ftop;
4697 TREE_CHAIN (f_ftop) = f_goff;
4698 TREE_CHAIN (f_goff) = f_foff;
4699 TREE_CHAIN (f_foff) = f_res;
4701 layout_type (record);
4704 else if (TARGET_IRIX && TARGET_IRIX6)
4705 /* On IRIX 6, this type is 'char *'. */
4706 return build_pointer_type (char_type_node);
4708 /* Otherwise, we use 'void *'. */
4709 return ptr_type_node;
4712 /* Implement EXPAND_BUILTIN_VA_START. */
4715 mips_va_start (tree valist, rtx nextarg)
4717 if (EABI_FLOAT_VARARGS_P)
4719 const CUMULATIVE_ARGS *cum;
4720 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4721 tree ovfl, gtop, ftop, goff, foff;
4723 int gpr_save_area_size;
4724 int fpr_save_area_size;
4727 cum = ¤t_function_args_info;
4729 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4731 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4733 f_ovfl = TYPE_FIELDS (va_list_type_node);
4734 f_gtop = TREE_CHAIN (f_ovfl);
4735 f_ftop = TREE_CHAIN (f_gtop);
4736 f_goff = TREE_CHAIN (f_ftop);
4737 f_foff = TREE_CHAIN (f_goff);
4739 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4741 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4743 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4745 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4747 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4750 /* Emit code to initialize OVFL, which points to the next varargs
4751 stack argument. CUM->STACK_WORDS gives the number of stack
4752 words used by named arguments. */
4753 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4754 if (cum->stack_words > 0)
4755 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4756 size_int (cum->stack_words * UNITS_PER_WORD));
4757 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4758 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4760 /* Emit code to initialize GTOP, the top of the GPR save area. */
4761 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4762 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4763 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4765 /* Emit code to initialize FTOP, the top of the FPR save area.
4766 This address is gpr_save_area_bytes below GTOP, rounded
4767 down to the next fp-aligned boundary. */
4768 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4769 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4770 fpr_offset &= -UNITS_PER_FPVALUE;
4772 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4773 size_int (-fpr_offset));
4774 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4775 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4777 /* Emit code to initialize GOFF, the offset from GTOP of the
4778 next GPR argument. */
4779 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4780 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
4781 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4783 /* Likewise emit code to initialize FOFF, the offset from FTOP
4784 of the next FPR argument. */
4785 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4786 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
4787 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4791 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4792 std_expand_builtin_va_start (valist, nextarg);
4796 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
4799 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4804 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4806 type = build_pointer_type (type);
4808 if (!EABI_FLOAT_VARARGS_P)
4809 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4812 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4813 tree ovfl, top, off, align;
4814 HOST_WIDE_INT size, rsize, osize;
4817 f_ovfl = TYPE_FIELDS (va_list_type_node);
4818 f_gtop = TREE_CHAIN (f_ovfl);
4819 f_ftop = TREE_CHAIN (f_gtop);
4820 f_goff = TREE_CHAIN (f_ftop);
4821 f_foff = TREE_CHAIN (f_goff);
4825 TOP be the top of the GPR or FPR save area;
4826 OFF be the offset from TOP of the next register;
4827 ADDR_RTX be the address of the argument;
4828 SIZE be the number of bytes in the argument type;
4829 RSIZE be the number of bytes used to store the argument
4830 when it's in the register save area; and
4831 OSIZE be the number of bytes used to store it when it's
4832 in the stack overflow area.
4834 The code we want is:
4836 1: off &= -rsize; // round down
4839 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
4844 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
4845 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
4849 [1] and [9] can sometimes be optimized away. */
4851 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4853 size = int_size_in_bytes (type);
4855 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4856 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4858 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4860 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4863 /* When va_start saves FPR arguments to the stack, each slot
4864 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
4865 argument's precision. */
4866 rsize = UNITS_PER_HWFPVALUE;
4868 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4869 (= PARM_BOUNDARY bits). This can be different from RSIZE
4872 (1) On 32-bit targets when TYPE is a structure such as:
4874 struct s { float f; };
4876 Such structures are passed in paired FPRs, so RSIZE
4877 will be 8 bytes. However, the structure only takes
4878 up 4 bytes of memory, so OSIZE will only be 4.
4880 (2) In combinations such as -mgp64 -msingle-float
4881 -fshort-double. Doubles passed in registers will then take
4882 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
4883 stack take up UNITS_PER_WORD bytes. */
4884 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4888 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4890 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4892 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4893 if (rsize > UNITS_PER_WORD)
4895 /* [1] Emit code for: off &= -rsize. */
4896 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4897 build_int_cst (NULL_TREE, -rsize));
4898 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4899 gimplify_and_add (t, pre_p);
4904 /* [2] Emit code to branch if off == 0. */
4905 t = build2 (NE_EXPR, boolean_type_node, off,
4906 build_int_cst (TREE_TYPE (off), 0));
4907 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4909 /* [5] Emit code for: off -= rsize. We do this as a form of
4910 post-decrement not available to C. */
4911 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4912 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4914 /* [4] Emit code for:
4915 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
4916 t = fold_convert (sizetype, t);
4917 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4918 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4919 if (BYTES_BIG_ENDIAN && rsize > size)
4921 u = size_int (rsize - size);
4922 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4924 COND_EXPR_THEN (addr) = t;
4926 if (osize > UNITS_PER_WORD)
4928 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
4929 u = size_int (osize - 1);
4930 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4931 t = fold_convert (sizetype, t);
4932 u = size_int (-osize);
4933 t = build2 (BIT_AND_EXPR, sizetype, t, u);
4934 t = fold_convert (TREE_TYPE (ovfl), t);
4935 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4940 /* [10, 11] Emit code for:
4941 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
4943 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
4944 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4945 if (BYTES_BIG_ENDIAN && osize > size)
4947 u = size_int (osize - size);
4948 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4951 /* String [9] and [10, 11] together. */
4953 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4954 COND_EXPR_ELSE (addr) = t;
4956 addr = fold_convert (build_pointer_type (type), addr);
4957 addr = build_va_arg_indirect_ref (addr);
4961 addr = build_va_arg_indirect_ref (addr);
4966 /* A chained list of functions for which mips16_build_call_stub has already
4967 generated a stub. NAME is the name of the function and FP_RET_P is true
4968 if the function returns a value in floating-point registers. */
4969 struct mips16_stub {
4970 struct mips16_stub *next;
4974 static struct mips16_stub *mips16_stubs;
4976 /* Return the two-character string that identifies floating-point
4977 return mode MODE in the name of a MIPS16 function stub. */
4980 mips16_call_stub_mode_suffix (enum machine_mode mode)
4984 else if (mode == DFmode)
4986 else if (mode == SCmode)
4988 else if (mode == DCmode)
4990 else if (mode == V2SFmode)
4996 /* Write instructions to move a 32-bit value between general register
4997 GPREG and floating-point register FPREG. DIRECTION is 't' to move
4998 from GPREG to FPREG and 'f' to move in the opposite direction. */
5001 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5003 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5004 reg_names[gpreg], reg_names[fpreg]);
5007 /* Likewise for 64-bit values. */
5010 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5013 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5014 reg_names[gpreg], reg_names[fpreg]);
5015 else if (TARGET_FLOAT64)
5017 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5018 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5019 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5020 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5024 /* Move the least-significant word. */
5025 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5026 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5027 /* ...then the most significant word. */
5028 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5029 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5033 /* Write out code to move floating-point arguments into or out of
5034 general registers. FP_CODE is the code describing which arguments
5035 are present (see the comment above the definition of CUMULATIVE_ARGS
5036 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5039 mips_output_args_xfer (int fp_code, char direction)
5041 unsigned int gparg, fparg, f;
5042 CUMULATIVE_ARGS cum;
5044 /* This code only works for o32 and o64. */
5045 gcc_assert (TARGET_OLDABI);
5047 mips_init_cumulative_args (&cum, NULL);
5049 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5051 enum machine_mode mode;
5052 struct mips_arg_info info;
5056 else if ((f & 3) == 2)
5061 mips_get_arg_info (&info, &cum, mode, NULL, true);
5062 gparg = mips_arg_regno (&info, false);
5063 fparg = mips_arg_regno (&info, true);
5066 mips_output_32bit_xfer (direction, gparg, fparg);
5068 mips_output_64bit_xfer (direction, gparg, fparg);
5070 mips_function_arg_advance (&cum, mode, NULL, true);
5074 /* Write a MIPS16 stub for the current function. This stub is used
5075 for functions which take arguments in the floating-point registers.
5076 It is normal-mode code that moves the floating-point arguments
5077 into the general registers and then jumps to the MIPS16 code. */
5080 mips16_build_function_stub (void)
5082 const char *fnname, *separator;
5083 char *secname, *stubname;
5087 /* Create the name of the stub, and its unique section. */
5088 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5089 fnname = targetm.strip_name_encoding (fnname);
5090 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5091 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5093 /* Build a decl for the stub. */
5094 stubdecl = build_decl (FUNCTION_DECL, get_identifier (stubname),
5095 build_function_type (void_type_node, NULL_TREE));
5096 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5097 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5099 /* Output a comment. */
5100 fprintf (asm_out_file, "\t# Stub function for %s (",
5101 current_function_name ());
5103 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
5105 fprintf (asm_out_file, "%s%s", separator,
5106 (f & 3) == 1 ? "float" : "double");
5109 fprintf (asm_out_file, ")\n");
5111 /* Write the preamble leading up to the function declaration. */
5112 fprintf (asm_out_file, "\t.set\tnomips16\n");
5113 switch_to_section (function_section (stubdecl));
5114 ASM_OUTPUT_ALIGN (asm_out_file,
5115 floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
5117 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5118 within a .ent, and we cannot emit another .ent. */
5119 if (!FUNCTION_NAME_ALREADY_DECLARED)
5121 fputs ("\t.ent\t", asm_out_file);
5122 assemble_name (asm_out_file, stubname);
5123 fputs ("\n", asm_out_file);
5126 /* Start the definition proper. */
5127 assemble_name (asm_out_file, stubname);
5128 fputs (":\n", asm_out_file);
5130 /* Load the address of the MIPS16 function into $at. Do this first so
5131 that targets with coprocessor interlocks can use an MFC1 to fill the
5133 fprintf (asm_out_file, "\t.set\tnoat\n");
5134 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
5135 assemble_name (asm_out_file, fnname);
5136 fprintf (asm_out_file, "\n");
5138 /* Move the arguments from floating-point registers to general registers. */
5139 mips_output_args_xfer (current_function_args_info.fp_code, 'f');
5141 /* Jump to the MIPS16 function. */
5142 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5143 fprintf (asm_out_file, "\t.set\tat\n");
5145 if (!FUNCTION_NAME_ALREADY_DECLARED)
5147 fputs ("\t.end\t", asm_out_file);
5148 assemble_name (asm_out_file, stubname);
5149 fputs ("\n", asm_out_file);
5152 switch_to_section (function_section (current_function_decl));
5155 /* The current function is a MIPS16 function that returns a value in an FPR.
5156 Copy the return value from its soft-float to its hard-float location.
5157 libgcc2 has special non-MIPS16 helper functions for each case. */
5160 mips16_copy_fpr_return_value (void)
5162 rtx fn, insn, arg, call;
5163 tree id, return_type;
5164 enum machine_mode return_mode;
5166 return_type = DECL_RESULT (current_function_decl);
5167 return_mode = DECL_MODE (return_type);
5169 id = get_identifier (ACONCAT (("__mips16_ret_",
5170 mips16_call_stub_mode_suffix (return_mode),
5172 fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5173 arg = gen_rtx_REG (return_mode, GP_RETURN);
5174 call = gen_call_value_internal (arg, fn, const0_rtx);
5175 insn = emit_call_insn (call);
5176 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
5179 /* Consider building a stub for a MIPS16 call to function FN.
5180 RETVAL is the location of the return value, or null if this is
5181 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5182 arguments and FP_CODE is the code built by mips_function_arg;
5183 see the comment above CUMULATIVE_ARGS for details.
5185 Return true if a stub was needed, and emit the call if so.
5187 A stub is needed for calls to functions that, in normal mode,
5188 receive arguments in FPRs or return values in FPRs. The stub
5189 copies the arguments from their soft-float positions to their
5190 hard-float positions, calls the real function, then copies the
5191 return value from its hard-float position to its soft-float
5194 We emit a JAL to FN even when FN might need a stub. If FN turns out
5195 to be to a non-MIPS16 function, the linker automatically redirects
5196 the JAL to the stub, otherwise the JAL continues to call FN directly. */
5199 mips16_build_call_stub (rtx retval, rtx fn, rtx args_size, int fp_code)
5203 struct mips16_stub *l;
5206 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5207 we were invoked with the -msoft-float option. */
5208 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5211 /* Figure out whether the value might come back in a floating-point
5213 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5215 /* We don't need to do anything if there were no floating-point
5216 arguments and the value will not be returned in a floating-point
5218 if (fp_code == 0 && !fp_ret_p)
5221 /* We don't need to do anything if this is a call to a special
5222 MIPS16 support function. */
5223 if (GET_CODE (fn) == SYMBOL_REF
5224 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
5227 /* This code will only work for o32 and o64 abis. The other ABI's
5228 require more sophisticated support. */
5229 gcc_assert (TARGET_OLDABI);
5231 /* If we're calling via a function pointer, use one of the magic
5232 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5233 Each stub expects the function address to arrive in register $2. */
5234 if (GET_CODE (fn) != SYMBOL_REF)
5240 /* Create a SYMBOL_REF for the libgcc.a function. */
5242 sprintf (buf, "__mips16_call_stub_%s_%d",
5243 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5246 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5247 id = get_identifier (buf);
5248 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5250 /* Load the target function into $2. */
5251 mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
5253 /* Emit the call. */
5254 if (retval == NULL_RTX)
5255 insn = gen_call_internal (stub_fn, args_size);
5257 insn = gen_call_value_internal (retval, stub_fn, args_size);
5258 insn = emit_call_insn (insn);
5260 /* Tell GCC that this call does indeed use the value of $2. */
5261 CALL_INSN_FUNCTION_USAGE (insn) =
5262 gen_rtx_EXPR_LIST (VOIDmode,
5263 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
5264 CALL_INSN_FUNCTION_USAGE (insn));
5266 /* If we are handling a floating-point return value, we need to
5267 save $18 in the function prologue. Putting a note on the
5268 call will mean that df_regs_ever_live_p ($18) will be true if the
5269 call is not eliminated, and we can check that in the prologue
5272 CALL_INSN_FUNCTION_USAGE (insn) =
5273 gen_rtx_EXPR_LIST (VOIDmode,
5274 gen_rtx_USE (VOIDmode,
5275 gen_rtx_REG (word_mode, 18)),
5276 CALL_INSN_FUNCTION_USAGE (insn));
5281 /* We know the function we are going to call. If we have already
5282 built a stub, we don't need to do anything further. */
5283 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5284 for (l = mips16_stubs; l != NULL; l = l->next)
5285 if (strcmp (l->name, fnname) == 0)
5290 const char *separator;
5291 char *secname, *stubname;
5292 tree stubid, stubdecl;
5295 /* If the function does not return in FPRs, the special stub
5299 If the function does return in FPRs, the stub section is named
5300 .mips16.call.fp.FNNAME
5302 Build a decl for the stub. */
5303 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
5305 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
5307 stubid = get_identifier (stubname);
5308 stubdecl = build_decl (FUNCTION_DECL, stubid,
5309 build_function_type (void_type_node, NULL_TREE));
5310 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5311 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE,
5314 /* Output a comment. */
5315 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5317 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5321 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5323 fprintf (asm_out_file, "%s%s", separator,
5324 (f & 3) == 1 ? "float" : "double");
5327 fprintf (asm_out_file, ")\n");
5329 /* Write the preamble leading up to the function declaration. */
5330 fprintf (asm_out_file, "\t.set\tnomips16\n");
5331 assemble_start_function (stubdecl, stubname);
5333 if (!FUNCTION_NAME_ALREADY_DECLARED)
5335 fputs ("\t.ent\t", asm_out_file);
5336 assemble_name (asm_out_file, stubname);
5337 fputs ("\n", asm_out_file);
5339 assemble_name (asm_out_file, stubname);
5340 fputs (":\n", asm_out_file);
5345 /* Load the address of the MIPS16 function into $at. Do this
5346 first so that targets with coprocessor interlocks can use
5347 an MFC1 to fill the delay slot. */
5348 fprintf (asm_out_file, "\t.set\tnoat\n");
5349 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
5353 /* Move the arguments from general registers to floating-point
5355 mips_output_args_xfer (fp_code, 't');
5359 /* Jump to the previously-loaded address. */
5360 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5361 fprintf (asm_out_file, "\t.set\tat\n");
5365 /* Save the return address in $18 and call the non-MIPS16 function.
5366 The stub's caller knows that $18 might be clobbered, even though
5367 $18 is usually a call-saved register. */
5368 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5369 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5370 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
5372 /* Move the result from floating-point registers to
5373 general registers. */
5374 switch (GET_MODE (retval))
5377 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5378 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5381 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5382 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5384 /* On 64-bit targets, complex floats are returned in
5385 a single GPR, such that "sd" on a suitably-aligned
5386 target would store the value correctly. */
5387 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5388 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5389 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5390 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5391 reg_names[GP_RETURN],
5392 reg_names[GP_RETURN],
5393 reg_names[GP_RETURN + 1]);
5398 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
5399 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5403 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5409 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
5412 #ifdef ASM_DECLARE_FUNCTION_SIZE
5413 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
5416 if (!FUNCTION_NAME_ALREADY_DECLARED)
5418 fputs ("\t.end\t", asm_out_file);
5419 assemble_name (asm_out_file, stubname);
5420 fputs ("\n", asm_out_file);
5423 /* Record this stub. */
5424 l = XNEW (struct mips16_stub);
5425 l->name = xstrdup (fnname);
5426 l->fp_ret_p = fp_ret_p;
5427 l->next = mips16_stubs;
5431 /* If we expect a floating-point return value, but we've built a
5432 stub which does not expect one, then we're in trouble. We can't
5433 use the existing stub, because it won't handle the floating-point
5434 value. We can't build a new stub, because the linker won't know
5435 which stub to use for the various calls in this object file.
5436 Fortunately, this case is illegal, since it means that a function
5437 was declared in two different ways in a single compilation. */
5438 if (fp_ret_p && !l->fp_ret_p)
5439 error ("cannot handle inconsistent calls to %qs", fnname);
5441 if (retval == NULL_RTX)
5442 insn = gen_call_internal_direct (fn, args_size);
5444 insn = gen_call_value_internal_direct (retval, fn, args_size);
5445 insn = emit_call_insn (insn);
5447 /* If we are calling a stub which handles a floating-point return
5448 value, we need to arrange to save $18 in the prologue. We do this
5449 by marking the function call as using the register. The prologue
5450 will later see that it is used, and emit code to save it. */
5452 CALL_INSN_FUNCTION_USAGE (insn) =
5453 gen_rtx_EXPR_LIST (VOIDmode,
5454 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
5455 CALL_INSN_FUNCTION_USAGE (insn));
5460 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5463 mips_ok_for_lazy_binding_p (rtx x)
5465 return (TARGET_USE_GOT
5466 && GET_CODE (x) == SYMBOL_REF
5467 && !mips_symbol_binds_local_p (x));
5470 /* Load function address ADDR into register DEST. SIBCALL_P is true
5471 if the address is needed for a sibling call. Return true if we
5472 used an explicit lazy-binding sequence. */
5475 mips_load_call_address (rtx dest, rtx addr, bool sibcall_p)
5477 /* If we're generating PIC, and this call is to a global function,
5478 try to allow its address to be resolved lazily. This isn't
5479 possible for sibcalls when $gp is call-saved because the value
5480 of $gp on entry to the stub would be our caller's gp, not ours. */
5481 if (TARGET_EXPLICIT_RELOCS
5482 && !(sibcall_p && TARGET_CALL_SAVED_GP)
5483 && mips_ok_for_lazy_binding_p (addr))
5485 rtx high, lo_sum_symbol;
5487 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
5488 addr, SYMBOL_GOTOFF_CALL);
5489 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
5490 if (Pmode == SImode)
5491 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
5493 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
5498 mips_emit_move (dest, addr);
5503 /* Expand a "call", "sibcall", "call_value" or "sibcall_value" instruction.
5504 RESULT is where the result will go (null for "call"s and "sibcall"s),
5505 ADDR is the address of the function, ARGS_SIZE is the size of the
5506 arguments and AUX is the value passed to us by mips_function_arg.
5507 SIBCALL_P is true if we are expanding a sibling call, false if we're
5508 expanding a normal call. */
5511 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, bool sibcall_p)
5513 rtx orig_addr, pattern, insn;
5518 if (!call_insn_operand (addr, VOIDmode))
5520 addr = gen_reg_rtx (Pmode);
5521 lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
5525 && TARGET_HARD_FLOAT_ABI
5526 && mips16_build_call_stub (result, addr, args_size,
5527 aux == 0 ? 0 : (int) GET_MODE (aux)))
5529 gcc_assert (!sibcall_p);
5534 pattern = (sibcall_p
5535 ? gen_sibcall_internal (addr, args_size)
5536 : gen_call_internal (addr, args_size));
5537 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
5541 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
5542 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
5545 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
5546 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
5549 pattern = (sibcall_p
5550 ? gen_sibcall_value_internal (result, addr, args_size)
5551 : gen_call_value_internal (result, addr, args_size));
5553 insn = emit_call_insn (pattern);
5555 /* Lazy-binding stubs require $gp to be valid on entry. We also pretend
5556 that they use FAKE_CALL_REGNO; see the load_call<mode> patterns for
5560 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
5561 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
5562 gen_rtx_REG (Pmode, FAKE_CALL_REGNO));
5566 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5569 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5571 if (!TARGET_SIBCALLS)
5574 /* We can't do a sibcall if the called function is a MIPS16 function
5575 because there is no direct "jx" instruction equivalent to "jalx" to
5576 switch the ISA mode. We only care about cases where the sibling
5577 and normal calls would both be direct. */
5578 if (mips_use_mips16_mode_p (decl)
5579 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5582 /* When -minterlink-mips16 is in effect, assume that external
5583 functions could be MIPS16 ones unless an attribute explicitly
5584 tells us otherwise. */
5585 if (TARGET_INTERLINK_MIPS16
5587 && DECL_EXTERNAL (decl)
5588 && !mips_nomips16_decl_p (decl)
5589 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5596 /* Emit code to move general operand SRC into condition-code
5597 register DEST given that SCRATCH is a scratch TFmode FPR.
5604 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
5607 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
5611 /* Change the source to SFmode. */
5613 src = adjust_address (src, SFmode, 0);
5614 else if (REG_P (src) || GET_CODE (src) == SUBREG)
5615 src = gen_rtx_REG (SFmode, true_regnum (src));
5617 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
5618 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
5620 mips_emit_move (copy_rtx (fp1), src);
5621 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
5622 emit_insn (gen_slt_sf (dest, fp2, fp1));
5625 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5626 Assume that the areas do not overlap. */
5629 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
5631 HOST_WIDE_INT offset, delta;
5632 unsigned HOST_WIDE_INT bits;
5634 enum machine_mode mode;
5637 /* Work out how many bits to move at a time. If both operands have
5638 half-word alignment, it is usually better to move in half words.
5639 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5640 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5641 Otherwise move word-sized chunks. */
5642 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
5643 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
5644 bits = BITS_PER_WORD / 2;
5646 bits = BITS_PER_WORD;
5648 mode = mode_for_size (bits, MODE_INT, 0);
5649 delta = bits / BITS_PER_UNIT;
5651 /* Allocate a buffer for the temporary registers. */
5652 regs = alloca (sizeof (rtx) * length / delta);
5654 /* Load as many BITS-sized chunks as possible. Use a normal load if
5655 the source has enough alignment, otherwise use left/right pairs. */
5656 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5658 regs[i] = gen_reg_rtx (mode);
5659 if (MEM_ALIGN (src) >= bits)
5660 mips_emit_move (regs[i], adjust_address (src, mode, offset));
5663 rtx part = adjust_address (src, BLKmode, offset);
5664 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
5669 /* Copy the chunks to the destination. */
5670 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5671 if (MEM_ALIGN (dest) >= bits)
5672 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
5675 rtx part = adjust_address (dest, BLKmode, offset);
5676 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
5680 /* Mop up any left-over bytes. */
5681 if (offset < length)
5683 src = adjust_address (src, BLKmode, offset);
5684 dest = adjust_address (dest, BLKmode, offset);
5685 move_by_pieces (dest, src, length - offset,
5686 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
5690 /* Helper function for doing a loop-based block operation on memory
5691 reference MEM. Each iteration of the loop will operate on LENGTH
5694 Create a new base register for use within the loop and point it to
5695 the start of MEM. Create a new memory reference that uses this
5696 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5699 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
5700 rtx *loop_reg, rtx *loop_mem)
5702 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
5704 /* Although the new mem does not refer to a known location,
5705 it does keep up to LENGTH bytes of alignment. */
5706 *loop_mem = change_address (mem, BLKmode, *loop_reg);
5707 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
5710 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
5711 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
5712 the memory regions do not overlap. */
5715 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
5716 HOST_WIDE_INT bytes_per_iter)
5718 rtx label, src_reg, dest_reg, final_src;
5719 HOST_WIDE_INT leftover;
5721 leftover = length % bytes_per_iter;
5724 /* Create registers and memory references for use within the loop. */
5725 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
5726 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
5728 /* Calculate the value that SRC_REG should have after the last iteration
5730 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
5733 /* Emit the start of the loop. */
5734 label = gen_label_rtx ();
5737 /* Emit the loop body. */
5738 mips_block_move_straight (dest, src, bytes_per_iter);
5740 /* Move on to the next block. */
5741 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
5742 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
5744 /* Emit the loop condition. */
5745 if (Pmode == DImode)
5746 emit_insn (gen_cmpdi (src_reg, final_src));
5748 emit_insn (gen_cmpsi (src_reg, final_src));
5749 emit_jump_insn (gen_bne (label));
5751 /* Mop up any left-over bytes. */
5753 mips_block_move_straight (dest, src, leftover);
5756 /* Expand a movmemsi instruction, which copies LENGTH bytes from
5757 memory reference SRC to memory reference DEST. */
5760 mips_expand_block_move (rtx dest, rtx src, rtx length)
5762 if (GET_CODE (length) == CONST_INT)
5764 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
5766 mips_block_move_straight (dest, src, INTVAL (length));
5771 mips_block_move_loop (dest, src, INTVAL (length),
5772 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
5779 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5782 mips_expand_synci_loop (rtx begin, rtx end)
5784 rtx inc, label, cmp, cmp_result;
5786 /* Load INC with the cache line size (rdhwr INC,$1). */
5787 inc = gen_reg_rtx (SImode);
5788 emit_insn (gen_rdhwr (inc, const1_rtx));
5790 /* Loop back to here. */
5791 label = gen_label_rtx ();
5794 emit_insn (gen_synci (begin));
5796 cmp = gen_reg_rtx (Pmode);
5797 mips_emit_binary (GTU, cmp, begin, end);
5799 mips_emit_binary (PLUS, begin, begin, inc);
5801 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
5802 emit_jump_insn (gen_condjump (cmp_result, label));
5805 /* Return true if it is possible to use left/right accesses for a
5806 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5807 returning true, update *OP, *LEFT and *RIGHT as follows:
5809 *OP is a BLKmode reference to the whole field.
5811 *LEFT is a QImode reference to the first byte if big endian or
5812 the last byte if little endian. This address can be used in the
5813 left-side instructions (LWL, SWL, LDL, SDL).
5815 *RIGHT is a QImode reference to the opposite end of the field and
5816 can be used in the patterning right-side instruction. */
5819 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
5820 rtx *left, rtx *right)
5824 /* Check that the operand really is a MEM. Not all the extv and
5825 extzv predicates are checked. */
5829 /* Check that the size is valid. */
5830 if (width != 32 && (!TARGET_64BIT || width != 64))
5833 /* We can only access byte-aligned values. Since we are always passed
5834 a reference to the first byte of the field, it is not necessary to
5835 do anything with BITPOS after this check. */
5836 if (bitpos % BITS_PER_UNIT != 0)
5839 /* Reject aligned bitfields: we want to use a normal load or store
5840 instead of a left/right pair. */
5841 if (MEM_ALIGN (*op) >= width)
5844 /* Adjust *OP to refer to the whole field. This also has the effect
5845 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5846 *op = adjust_address (*op, BLKmode, 0);
5847 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
5849 /* Get references to both ends of the field. We deliberately don't
5850 use the original QImode *OP for FIRST since the new BLKmode one
5851 might have a simpler address. */
5852 first = adjust_address (*op, QImode, 0);
5853 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
5855 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
5856 correspond to the MSB and RIGHT to the LSB. */
5857 if (TARGET_BIG_ENDIAN)
5858 *left = first, *right = last;
5860 *left = last, *right = first;
5865 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
5866 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
5867 the operation is the equivalent of:
5869 (set DEST (*_extract SRC WIDTH BITPOS))
5871 Return true on success. */
5874 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
5875 HOST_WIDE_INT bitpos)
5877 rtx left, right, temp;
5879 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
5880 be a paradoxical word_mode subreg. This is the only case in which
5881 we allow the destination to be larger than the source. */
5882 if (GET_CODE (dest) == SUBREG
5883 && GET_MODE (dest) == DImode
5884 && GET_MODE (SUBREG_REG (dest)) == SImode)
5885 dest = SUBREG_REG (dest);
5887 /* After the above adjustment, the destination must be the same
5888 width as the source. */
5889 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
5892 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
5895 temp = gen_reg_rtx (GET_MODE (dest));
5896 if (GET_MODE (dest) == DImode)
5898 emit_insn (gen_mov_ldl (temp, src, left));
5899 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
5903 emit_insn (gen_mov_lwl (temp, src, left));
5904 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
5909 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
5910 BITPOS and SRC are the operands passed to the expander; the operation
5911 is the equivalent of:
5913 (set (zero_extract DEST WIDTH BITPOS) SRC)
5915 Return true on success. */
5918 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
5919 HOST_WIDE_INT bitpos)
5922 enum machine_mode mode;
5924 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
5927 mode = mode_for_size (width, MODE_INT, 0);
5928 src = gen_lowpart (mode, src);
5931 emit_insn (gen_mov_sdl (dest, src, left));
5932 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
5936 emit_insn (gen_mov_swl (dest, src, left));
5937 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
5942 /* Return true if X is a MEM with the same size as MODE. */
5945 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
5952 size = MEM_SIZE (x);
5953 return size && INTVAL (size) == GET_MODE_SIZE (mode);
5956 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
5957 source of an "ext" instruction or the destination of an "ins"
5958 instruction. OP must be a register operand and the following
5959 conditions must hold:
5961 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
5962 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
5963 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
5965 Also reject lengths equal to a word as they are better handled
5966 by the move patterns. */
5969 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
5971 if (!ISA_HAS_EXT_INS
5972 || !register_operand (op, VOIDmode)
5973 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
5976 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
5979 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
5985 /* Return true if -msplit-addresses is selected and should be honored.
5987 -msplit-addresses is a half-way house between explicit relocations
5988 and the traditional assembler macros. It can split absolute 32-bit
5989 symbolic constants into a high/lo_sum pair but uses macros for other
5992 Like explicit relocation support for REL targets, it relies
5993 on GNU extensions in the assembler and the linker.
5995 Although this code should work for -O0, it has traditionally
5996 been treated as an optimization. */
5999 mips_split_addresses_p (void)
6001 return (TARGET_SPLIT_ADDRESSES
6005 && !ABI_HAS_64BIT_SYMBOLS);
6008 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6011 mips_init_relocs (void)
6013 memset (mips_split_p, '\0', sizeof (mips_split_p));
6014 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6015 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6017 if (ABI_HAS_64BIT_SYMBOLS)
6019 if (TARGET_EXPLICIT_RELOCS)
6021 mips_split_p[SYMBOL_64_HIGH] = true;
6022 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6023 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6025 mips_split_p[SYMBOL_64_MID] = true;
6026 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6027 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6029 mips_split_p[SYMBOL_64_LOW] = true;
6030 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6031 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6033 mips_split_p[SYMBOL_ABSOLUTE] = true;
6034 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6039 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6041 mips_split_p[SYMBOL_ABSOLUTE] = true;
6042 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6043 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6045 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6051 /* The high part is provided by a pseudo copy of $gp. */
6052 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6053 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6056 if (TARGET_EXPLICIT_RELOCS)
6058 /* Small data constants are kept whole until after reload,
6059 then lowered by mips_rewrite_small_data. */
6060 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6062 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6065 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6066 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6070 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6071 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6076 /* The HIGH and LO_SUM are matched by special .md patterns. */
6077 mips_split_p[SYMBOL_GOT_DISP] = true;
6079 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6080 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6081 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6083 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6084 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6085 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6090 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6092 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6093 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6099 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6100 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6101 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6104 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6105 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6107 mips_split_p[SYMBOL_DTPREL] = true;
6108 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6109 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6111 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6113 mips_split_p[SYMBOL_TPREL] = true;
6114 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6115 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6117 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6120 /* If OP is an UNSPEC address, return the address to which it refers,
6121 otherwise return OP itself. */
6124 mips_strip_unspec_address (rtx op)
6128 split_const (op, &base, &offset);
6129 if (UNSPEC_ADDRESS_P (base))
6130 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6134 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6135 in context CONTEXT. RELOCS is the array of relocations to use. */
6138 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6139 const char **relocs)
6141 enum mips_symbol_type symbol_type;
6144 symbol_type = mips_classify_symbolic_expression (op, context);
6145 gcc_assert (relocs[symbol_type]);
6147 fputs (relocs[symbol_type], file);
6148 output_addr_const (file, mips_strip_unspec_address (op));
6149 for (p = relocs[symbol_type]; *p != 0; p++)
6154 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6155 The punctuation characters are:
6157 '(' Start a nested ".set noreorder" block.
6158 ')' End a nested ".set noreorder" block.
6159 '[' Start a nested ".set noat" block.
6160 ']' End a nested ".set noat" block.
6161 '<' Start a nested ".set nomacro" block.
6162 '>' End a nested ".set nomacro" block.
6163 '*' Behave like %(%< if generating a delayed-branch sequence.
6164 '#' Print a nop if in a ".set noreorder" block.
6165 '/' Like '#', but do nothing within a delayed-branch sequence.
6166 '?' Print "l" if mips_branch_likely is true
6167 '.' Print the name of the register with a hard-wired zero (zero or $0).
6168 '@' Print the name of the assembler temporary register (at or $1).
6169 '^' Print the name of the pic call-through register (t9 or $25).
6170 '+' Print the name of the gp register (usually gp or $28).
6171 '$' Print the name of the stack pointer register (sp or $29).
6172 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6173 '-' Print ".set pop" under the same conditions for '|'.
6175 See also mips_init_print_operand_pucnt. */
6178 mips_print_operand_punctuation (FILE *file, int ch)
6183 if (set_noreorder++ == 0)
6184 fputs (".set\tnoreorder\n\t", file);
6188 gcc_assert (set_noreorder > 0);
6189 if (--set_noreorder == 0)
6190 fputs ("\n\t.set\treorder", file);
6194 if (set_noat++ == 0)
6195 fputs (".set\tnoat\n\t", file);
6199 gcc_assert (set_noat > 0);
6200 if (--set_noat == 0)
6201 fputs ("\n\t.set\tat", file);
6205 if (set_nomacro++ == 0)
6206 fputs (".set\tnomacro\n\t", file);
6210 gcc_assert (set_nomacro > 0);
6211 if (--set_nomacro == 0)
6212 fputs ("\n\t.set\tmacro", file);
6216 if (final_sequence != 0)
6218 mips_print_operand_punctuation (file, '(');
6219 mips_print_operand_punctuation (file, '<');
6224 if (set_noreorder != 0)
6225 fputs ("\n\tnop", file);
6229 /* Print an extra newline so that the delayed insn is separated
6230 from the following ones. This looks neater and is consistent
6231 with non-nop delayed sequences. */
6232 if (set_noreorder != 0 && final_sequence == 0)
6233 fputs ("\n\tnop\n", file);
6237 if (mips_branch_likely)
6242 fputs (reg_names[GP_REG_FIRST + 0], file);
6246 fputs (reg_names[GP_REG_FIRST + 1], file);
6250 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6254 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6258 fputs (reg_names[STACK_POINTER_REGNUM], file);
6263 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6268 fputs ("\n\t.set\tpop", file);
6277 /* Initialize mips_print_operand_punct. */
6280 mips_init_print_operand_punct (void)
6284 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
6285 mips_print_operand_punct[(unsigned char) *p] = true;
6288 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6289 associated with condition CODE. Print the condition part of the
6293 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
6307 /* Conveniently, the MIPS names for these conditions are the same
6308 as their RTL equivalents. */
6309 fputs (GET_RTX_NAME (code), file);
6313 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6318 /* Likewise floating-point branches. */
6321 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
6326 fputs ("c1f", file);
6330 fputs ("c1t", file);
6334 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6339 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6341 'X' Print CONST_INT OP in hexadecimal format.
6342 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6343 'd' Print CONST_INT OP in decimal.
6344 'h' Print the high-part relocation associated with OP, after stripping
6346 'R' Print the low-part relocation associated with OP.
6347 'C' Print the integer branch condition for comparison OP.
6348 'N' Print the inverse of the integer branch condition for comparison OP.
6349 'F' Print the FPU branch condition for comparison OP.
6350 'W' Print the inverse of the FPU branch condition for comparison OP.
6351 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6352 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6353 't' Like 'T', but with the EQ/NE cases reversed
6354 'Y' Print mips_fp_conditions[INTVAL (OP)]
6355 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6356 'q' Print a DSP accumulator register.
6357 'D' Print the second part of a double-word register or memory operand.
6358 'L' Print the low-order register in a double-word register operand.
6359 'M' Print high-order register in a double-word register operand.
6360 'z' Print $0 if OP is zero, otherwise print OP normally. */
6363 mips_print_operand (FILE *file, rtx op, int letter)
6367 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6369 mips_print_operand_punctuation (file, letter);
6374 code = GET_CODE (op);
6379 if (GET_CODE (op) == CONST_INT)
6380 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6382 output_operand_lossage ("invalid use of '%%%c'", letter);
6386 if (GET_CODE (op) == CONST_INT)
6387 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
6389 output_operand_lossage ("invalid use of '%%%c'", letter);
6393 if (GET_CODE (op) == CONST_INT)
6394 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
6396 output_operand_lossage ("invalid use of '%%%c'", letter);
6402 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
6406 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
6410 mips_print_int_branch_condition (file, code, letter);
6414 mips_print_int_branch_condition (file, reverse_condition (code), letter);
6418 mips_print_float_branch_condition (file, code, letter);
6422 mips_print_float_branch_condition (file, reverse_condition (code),
6429 int truth = (code == NE) == (letter == 'T');
6430 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6435 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
6436 fputs (mips_fp_conditions[UINTVAL (op)], file);
6438 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6445 mips_print_operand (file, op, 0);
6451 if (code == REG && MD_REG_P (REGNO (op)))
6452 fprintf (file, "$ac0");
6453 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
6454 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
6456 output_operand_lossage ("invalid use of '%%%c'", letter);
6464 unsigned int regno = REGNO (op);
6465 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
6466 || (letter == 'L' && TARGET_BIG_ENDIAN)
6469 fprintf (file, "%s", reg_names[regno]);
6475 output_address (plus_constant (XEXP (op, 0), 4));
6477 output_address (XEXP (op, 0));
6481 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6482 fputs (reg_names[GP_REG_FIRST], file);
6483 else if (CONST_GP_P (op))
6484 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6486 output_addr_const (file, mips_strip_unspec_address (op));
6492 /* Output address operand X to FILE. */
6495 mips_print_operand_address (FILE *file, rtx x)
6497 struct mips_address_info addr;
6499 if (mips_classify_address (&addr, x, word_mode, true))
6503 mips_print_operand (file, addr.offset, 0);
6504 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6507 case ADDRESS_LO_SUM:
6508 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
6510 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6513 case ADDRESS_CONST_INT:
6514 output_addr_const (file, x);
6515 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
6518 case ADDRESS_SYMBOLIC:
6519 output_addr_const (file, mips_strip_unspec_address (x));
6525 /* Implement TARGET_ENCODE_SECTION_INFO. */
6528 mips_encode_section_info (tree decl, rtx rtl, int first)
6530 default_encode_section_info (decl, rtl, first);
6532 if (TREE_CODE (decl) == FUNCTION_DECL)
6534 rtx symbol = XEXP (rtl, 0);
6535 tree type = TREE_TYPE (decl);
6537 /* Encode whether the symbol is short or long. */
6538 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
6539 || mips_far_type_p (type))
6540 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
6544 /* Implement TARGET_SELECT_RTX_SECTION. */
6547 mips_select_rtx_section (enum machine_mode mode, rtx x,
6548 unsigned HOST_WIDE_INT align)
6550 /* ??? Consider using mergeable small data sections. */
6551 if (mips_rtx_constant_in_small_data_p (mode))
6552 return get_named_section (NULL, ".sdata", 0);
6554 return default_elf_select_rtx_section (mode, x, align);
6557 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6559 The complication here is that, with the combination TARGET_ABICALLS
6560 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6561 therefore not be included in the read-only part of a DSO. Handle such
6562 cases by selecting a normal data section instead of a read-only one.
6563 The logic apes that in default_function_rodata_section. */
6566 mips_function_rodata_section (tree decl)
6568 if (!TARGET_ABICALLS || TARGET_GPWORD)
6569 return default_function_rodata_section (decl);
6571 if (decl && DECL_SECTION_NAME (decl))
6573 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6574 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6576 char *rname = ASTRDUP (name);
6578 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6580 else if (flag_function_sections
6581 && flag_data_sections
6582 && strncmp (name, ".text.", 6) == 0)
6584 char *rname = ASTRDUP (name);
6585 memcpy (rname + 1, "data", 4);
6586 return get_section (rname, SECTION_WRITE, decl);
6589 return data_section;
6592 /* Implement TARGET_IN_SMALL_DATA_P. */
6595 mips_in_small_data_p (const_tree decl)
6597 unsigned HOST_WIDE_INT size;
6599 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6602 /* We don't yet generate small-data references for -mabicalls
6603 or VxWorks RTP code. See the related -G handling in
6604 mips_override_options. */
6605 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
6608 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6612 /* Reject anything that isn't in a known small-data section. */
6613 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6614 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6617 /* If a symbol is defined externally, the assembler will use the
6618 usual -G rules when deciding how to implement macros. */
6619 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
6622 else if (TARGET_EMBEDDED_DATA)
6624 /* Don't put constants into the small data section: we want them
6625 to be in ROM rather than RAM. */
6626 if (TREE_CODE (decl) != VAR_DECL)
6629 if (TREE_READONLY (decl)
6630 && !TREE_SIDE_EFFECTS (decl)
6631 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6635 /* Enforce -mlocal-sdata. */
6636 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
6639 /* Enforce -mextern-sdata. */
6640 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
6642 if (DECL_EXTERNAL (decl))
6644 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
6648 size = int_size_in_bytes (TREE_TYPE (decl));
6649 return size <= mips_small_data_threshold;
6652 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6653 anchors for small data: the GP register acts as an anchor in that
6654 case. We also don't want to use them for PC-relative accesses,
6655 where the PC acts as an anchor. */
6658 mips_use_anchors_for_symbol_p (const_rtx symbol)
6660 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
6662 case SYMBOL_PC_RELATIVE:
6663 case SYMBOL_GP_RELATIVE:
6667 return default_use_anchors_for_symbol_p (symbol);
6671 /* The MIPS debug format wants all automatic variables and arguments
6672 to be in terms of the virtual frame pointer (stack pointer before
6673 any adjustment in the function), while the MIPS 3.0 linker wants
6674 the frame pointer to be the stack pointer after the initial
6675 adjustment. So, we do the adjustment here. The arg pointer (which
6676 is eliminated) points to the virtual frame pointer, while the frame
6677 pointer (which may be eliminated) points to the stack pointer after
6678 the initial adjustments. */
6681 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
6683 rtx offset2 = const0_rtx;
6684 rtx reg = eliminate_constant_term (addr, &offset2);
6687 offset = INTVAL (offset2);
6689 if (reg == stack_pointer_rtx
6690 || reg == frame_pointer_rtx
6691 || reg == hard_frame_pointer_rtx)
6693 offset -= cfun->machine->frame.total_size;
6694 if (reg == hard_frame_pointer_rtx)
6695 offset += cfun->machine->frame.hard_frame_pointer_offset;
6698 /* sdbout_parms does not want this to crash for unrecognized cases. */
6700 else if (reg != arg_pointer_rtx)
6701 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6708 /* Implement ASM_OUTPUT_EXTERNAL. */
6711 mips_output_external (FILE *file, tree decl, const char *name)
6713 default_elf_asm_output_external (file, decl, name);
6715 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6716 set in order to avoid putting out names that are never really
6718 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6720 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6722 /* When using assembler macros, emit .extern directives for
6723 all small-data externs so that the assembler knows how
6726 In most cases it would be safe (though pointless) to emit
6727 .externs for other symbols too. One exception is when an
6728 object is within the -G limit but declared by the user to
6729 be in a section other than .sbss or .sdata. */
6730 fputs ("\t.extern\t", file);
6731 assemble_name (file, name);
6732 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6733 int_size_in_bytes (TREE_TYPE (decl)));
6735 else if (TARGET_IRIX
6736 && mips_abi == ABI_32
6737 && TREE_CODE (decl) == FUNCTION_DECL)
6739 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6740 `.global name .text' directive for every used but
6741 undefined function. If we don't, the linker may perform
6742 an optimization (skipping over the insns that set $gp)
6743 when it is unsafe. */
6744 fputs ("\t.globl ", file);
6745 assemble_name (file, name);
6746 fputs (" .text\n", file);
6751 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
6754 mips_output_filename (FILE *stream, const char *name)
6756 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6758 if (write_symbols == DWARF2_DEBUG)
6760 else if (mips_output_filename_first_time)
6762 mips_output_filename_first_time = 0;
6763 num_source_filenames += 1;
6764 current_function_file = name;
6765 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6766 output_quoted_string (stream, name);
6767 putc ('\n', stream);
6769 /* If we are emitting stabs, let dbxout.c handle this (except for
6770 the mips_output_filename_first_time case). */
6771 else if (write_symbols == DBX_DEBUG)
6773 else if (name != current_function_file
6774 && strcmp (name, current_function_file) != 0)
6776 num_source_filenames += 1;
6777 current_function_file = name;
6778 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6779 output_quoted_string (stream, name);
6780 putc ('\n', stream);
6784 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
6787 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
6792 fputs ("\t.dtprelword\t", file);
6796 fputs ("\t.dtpreldword\t", file);
6802 output_addr_const (file, x);
6803 fputs ("+0x8000", file);
6806 /* Implement TARGET_DWARF_REGISTER_SPAN. */
6809 mips_dwarf_register_span (rtx reg)
6812 enum machine_mode mode;
6814 /* By default, GCC maps increasing register numbers to increasing
6815 memory locations, but paired FPRs are always little-endian,
6816 regardless of the prevailing endianness. */
6817 mode = GET_MODE (reg);
6818 if (FP_REG_P (REGNO (reg))
6819 && TARGET_BIG_ENDIAN
6820 && MAX_FPRS_PER_FMT > 1
6821 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
6823 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
6824 high = mips_subword (reg, true);
6825 low = mips_subword (reg, false);
6826 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
6832 /* Implement ASM_OUTPUT_ASCII. */
6835 mips_output_ascii (FILE *stream, const char *string, size_t len)
6841 fprintf (stream, "\t.ascii\t\"");
6842 for (i = 0; i < len; i++)
6846 c = (unsigned char) string[i];
6849 if (c == '\\' || c == '\"')
6851 putc ('\\', stream);
6859 fprintf (stream, "\\%03o", c);
6863 if (cur_pos > 72 && i+1 < len)
6866 fprintf (stream, "\"\n\t.ascii\t\"");
6869 fprintf (stream, "\"\n");
6872 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6873 macros, mark the symbol as written so that mips_asm_output_external
6874 won't emit an .extern for it. STREAM is the output file, NAME is the
6875 name of the symbol, INIT_STRING is the string that should be written
6876 before the symbol and FINAL_STRING is the string that should be
6877 written after it. FINAL_STRING is a printf format that consumes the
6878 remaining arguments. */
6881 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6882 const char *final_string, ...)
6886 fputs (init_string, stream);
6887 assemble_name (stream, name);
6888 va_start (ap, final_string);
6889 vfprintf (stream, final_string, ap);
6892 if (!TARGET_EXPLICIT_RELOCS)
6894 tree name_tree = get_identifier (name);
6895 TREE_ASM_WRITTEN (name_tree) = 1;
6899 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6900 NAME is the name of the object and ALIGN is the required alignment
6901 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6902 alignment argument. */
6905 mips_declare_common_object (FILE *stream, const char *name,
6906 const char *init_string,
6907 unsigned HOST_WIDE_INT size,
6908 unsigned int align, bool takes_alignment_p)
6910 if (!takes_alignment_p)
6912 size += (align / BITS_PER_UNIT) - 1;
6913 size -= size % (align / BITS_PER_UNIT);
6914 mips_declare_object (stream, name, init_string,
6915 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6918 mips_declare_object (stream, name, init_string,
6919 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6920 size, align / BITS_PER_UNIT);
6923 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6924 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6927 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6928 unsigned HOST_WIDE_INT size,
6931 /* If the target wants uninitialized const declarations in
6932 .rdata then don't put them in .comm. */
6933 if (TARGET_EMBEDDED_DATA
6934 && TARGET_UNINIT_CONST_IN_RODATA
6935 && TREE_CODE (decl) == VAR_DECL
6936 && TREE_READONLY (decl)
6937 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6939 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6940 targetm.asm_out.globalize_label (stream, name);
6942 switch_to_section (readonly_data_section);
6943 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6944 mips_declare_object (stream, name, "",
6945 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6949 mips_declare_common_object (stream, name, "\n\t.comm\t",
6953 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6954 extern int size_directive_output;
6956 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6957 definitions except that it uses mips_declare_object to emit the label. */
6960 mips_declare_object_name (FILE *stream, const char *name,
6961 tree decl ATTRIBUTE_UNUSED)
6963 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6964 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6967 size_directive_output = 0;
6968 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6972 size_directive_output = 1;
6973 size = int_size_in_bytes (TREE_TYPE (decl));
6974 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6977 mips_declare_object (stream, name, "", ":\n");
6980 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6983 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6987 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6988 if (!flag_inhibit_size_directive
6989 && DECL_SIZE (decl) != 0
6992 && DECL_INITIAL (decl) == error_mark_node
6993 && !size_directive_output)
6997 size_directive_output = 1;
6998 size = int_size_in_bytes (TREE_TYPE (decl));
6999 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7004 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7005 with the current ABI. */
7008 mips_mdebug_abi_name (void)
7021 return TARGET_64BIT ? "eabi64" : "eabi32";
7027 /* Implement TARGET_ASM_FILE_START. */
7030 mips_file_start (void)
7032 default_file_start ();
7034 /* Generate a special section to describe the ABI switches used to
7035 produce the resultant binary. This is unnecessary on IRIX and
7036 causes unwanted warnings from the native linker. */
7039 /* Record the ABI itself. Modern versions of binutils encode
7040 this information in the ELF header flags, but GDB needs the
7041 information in order to correctly debug binaries produced by
7042 older binutils. See the function mips_gdbarch_init in
7044 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7045 mips_mdebug_abi_name ());
7047 /* There is no ELF header flag to distinguish long32 forms of the
7048 EABI from long64 forms. Emit a special section to help tools
7049 such as GDB. Do the same for o64, which is sometimes used with
7051 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7052 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7053 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7055 #ifdef HAVE_AS_GNU_ATTRIBUTE
7056 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7057 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
7061 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7062 if (TARGET_ABICALLS)
7063 fprintf (asm_out_file, "\t.abicalls\n");
7065 if (flag_verbose_asm)
7066 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7068 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7071 /* Make the last instruction frame-related and note that it performs
7072 the operation described by FRAME_PATTERN. */
7075 mips_set_frame_expr (rtx frame_pattern)
7079 insn = get_last_insn ();
7080 RTX_FRAME_RELATED_P (insn) = 1;
7081 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7086 /* Return a frame-related rtx that stores REG at MEM.
7087 REG must be a single register. */
7090 mips_frame_set (rtx mem, rtx reg)
7094 /* If we're saving the return address register and the DWARF return
7095 address column differs from the hard register number, adjust the
7096 note reg to refer to the former. */
7097 if (REGNO (reg) == GP_REG_FIRST + 31
7098 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7099 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7101 set = gen_rtx_SET (VOIDmode, mem, reg);
7102 RTX_FRAME_RELATED_P (set) = 1;
7107 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7108 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7109 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7110 static const unsigned char mips16e_s2_s8_regs[] = {
7111 30, 23, 22, 21, 20, 19, 18
7113 static const unsigned char mips16e_a0_a3_regs[] = {
7117 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7118 ordered from the uppermost in memory to the lowest in memory. */
7119 static const unsigned char mips16e_save_restore_regs[] = {
7120 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7123 /* Return the index of the lowest X in the range [0, SIZE) for which
7124 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7127 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7132 for (i = 0; i < size; i++)
7133 if (BITSET_P (mask, regs[i]))
7139 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7140 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7141 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7142 is true for all indexes (X, SIZE). */
7145 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7146 unsigned int size, unsigned int *num_regs_ptr)
7150 i = mips16e_find_first_register (*mask_ptr, regs, size);
7151 for (i++; i < size; i++)
7152 if (!BITSET_P (*mask_ptr, regs[i]))
7155 *mask_ptr |= 1 << regs[i];
7159 /* Return a simplified form of X using the register values in REG_VALUES.
7160 REG_VALUES[R] is the last value assigned to hard register R, or null
7161 if R has not been modified.
7163 This function is rather limited, but is good enough for our purposes. */
7166 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7168 x = avoid_constant_pool_reference (x);
7172 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7173 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7174 x0, GET_MODE (XEXP (x, 0)));
7177 if (ARITHMETIC_P (x))
7179 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7180 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7181 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7185 && reg_values[REGNO (x)]
7186 && !rtx_unstable_p (reg_values[REGNO (x)]))
7187 return reg_values[REGNO (x)];
7192 /* Return true if (set DEST SRC) stores an argument register into its
7193 caller-allocated save slot, storing the number of that argument
7194 register in *REGNO_PTR if so. REG_VALUES is as for
7195 mips16e_collect_propagate_value. */
7198 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7199 unsigned int *regno_ptr)
7201 unsigned int argno, regno;
7202 HOST_WIDE_INT offset, required_offset;
7205 /* Check that this is a word-mode store. */
7206 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7209 /* Check that the register being saved is an unmodified argument
7211 regno = REGNO (src);
7212 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
7214 argno = regno - GP_ARG_FIRST;
7216 /* Check whether the address is an appropriate stack-pointer or
7217 frame-pointer access. */
7218 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7219 mips_split_plus (addr, &base, &offset);
7220 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7221 if (base == hard_frame_pointer_rtx)
7222 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7223 else if (base != stack_pointer_rtx)
7225 if (offset != required_offset)
7232 /* A subroutine of mips_expand_prologue, called only when generating
7233 MIPS16e SAVE instructions. Search the start of the function for any
7234 instructions that save argument registers into their caller-allocated
7235 save slots. Delete such instructions and return a value N such that
7236 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7237 instructions redundant. */
7240 mips16e_collect_argument_saves (void)
7242 rtx reg_values[FIRST_PSEUDO_REGISTER];
7243 rtx insn, next, set, dest, src;
7244 unsigned int nargs, regno;
7246 push_topmost_sequence ();
7248 memset (reg_values, 0, sizeof (reg_values));
7249 for (insn = get_insns (); insn; insn = next)
7251 next = NEXT_INSN (insn);
7258 set = PATTERN (insn);
7259 if (GET_CODE (set) != SET)
7262 dest = SET_DEST (set);
7263 src = SET_SRC (set);
7264 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
7266 if (!BITSET_P (cfun->machine->frame.mask, regno))
7269 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7272 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7273 reg_values[REGNO (dest)]
7274 = mips16e_collect_propagate_value (src, reg_values);
7278 pop_topmost_sequence ();
7283 /* Return a move between register REGNO and memory location SP + OFFSET.
7284 Make the move a load if RESTORE_P, otherwise make it a frame-related
7288 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7293 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7294 reg = gen_rtx_REG (SImode, regno);
7296 ? gen_rtx_SET (VOIDmode, reg, mem)
7297 : mips_frame_set (mem, reg));
7300 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7301 The instruction must:
7303 - Allocate or deallocate SIZE bytes in total; SIZE is known
7306 - Save or restore as many registers in *MASK_PTR as possible.
7307 The instruction saves the first registers at the top of the
7308 allocated area, with the other registers below it.
7310 - Save NARGS argument registers above the allocated area.
7312 (NARGS is always zero if RESTORE_P.)
7314 The SAVE and RESTORE instructions cannot save and restore all general
7315 registers, so there may be some registers left over for the caller to
7316 handle. Destructively modify *MASK_PTR so that it contains the registers
7317 that still need to be saved or restored. The caller can save these
7318 registers in the memory immediately below *OFFSET_PTR, which is a
7319 byte offset from the bottom of the allocated stack area. */
7322 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7323 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7327 HOST_WIDE_INT offset, top_offset;
7328 unsigned int i, regno;
7331 gcc_assert (cfun->machine->frame.num_fp == 0);
7333 /* Calculate the number of elements in the PARALLEL. We need one element
7334 for the stack adjustment, one for each argument register save, and one
7335 for each additional register move. */
7337 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7338 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7341 /* Create the final PARALLEL. */
7342 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7345 /* Add the stack pointer adjustment. */
7346 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7347 plus_constant (stack_pointer_rtx,
7348 restore_p ? size : -size));
7349 RTX_FRAME_RELATED_P (set) = 1;
7350 XVECEXP (pattern, 0, n++) = set;
7352 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7353 top_offset = restore_p ? size : 0;
7355 /* Save the arguments. */
7356 for (i = 0; i < nargs; i++)
7358 offset = top_offset + i * UNITS_PER_WORD;
7359 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7360 XVECEXP (pattern, 0, n++) = set;
7363 /* Then fill in the other register moves. */
7364 offset = top_offset;
7365 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7367 regno = mips16e_save_restore_regs[i];
7368 if (BITSET_P (*mask_ptr, regno))
7370 offset -= UNITS_PER_WORD;
7371 set = mips16e_save_restore_reg (restore_p, offset, regno);
7372 XVECEXP (pattern, 0, n++) = set;
7373 *mask_ptr &= ~(1 << regno);
7377 /* Tell the caller what offset it should use for the remaining registers. */
7378 *offset_ptr = size + (offset - top_offset);
7380 gcc_assert (n == XVECLEN (pattern, 0));
7385 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7386 pointer. Return true if PATTERN matches the kind of instruction
7387 generated by mips16e_build_save_restore. If INFO is nonnull,
7388 initialize it when returning true. */
7391 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7392 struct mips16e_save_restore_info *info)
7394 unsigned int i, nargs, mask, extra;
7395 HOST_WIDE_INT top_offset, save_offset, offset;
7396 rtx set, reg, mem, base;
7399 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7402 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7403 top_offset = adjust > 0 ? adjust : 0;
7405 /* Interpret all other members of the PARALLEL. */
7406 save_offset = top_offset - UNITS_PER_WORD;
7410 for (n = 1; n < XVECLEN (pattern, 0); n++)
7412 /* Check that we have a SET. */
7413 set = XVECEXP (pattern, 0, n);
7414 if (GET_CODE (set) != SET)
7417 /* Check that the SET is a load (if restoring) or a store
7419 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7423 /* Check that the address is the sum of the stack pointer and a
7424 possibly-zero constant offset. */
7425 mips_split_plus (XEXP (mem, 0), &base, &offset);
7426 if (base != stack_pointer_rtx)
7429 /* Check that SET's other operand is a register. */
7430 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7434 /* Check for argument saves. */
7435 if (offset == top_offset + nargs * UNITS_PER_WORD
7436 && REGNO (reg) == GP_ARG_FIRST + nargs)
7438 else if (offset == save_offset)
7440 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7441 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7444 mask |= 1 << REGNO (reg);
7445 save_offset -= UNITS_PER_WORD;
7451 /* Check that the restrictions on register ranges are met. */
7453 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7454 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7455 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7456 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7460 /* Make sure that the topmost argument register is not saved twice.
7461 The checks above ensure that the same is then true for the other
7462 argument registers. */
7463 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7466 /* Pass back information, if requested. */
7469 info->nargs = nargs;
7471 info->size = (adjust > 0 ? adjust : -adjust);
7477 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7478 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7479 the null terminator. */
7482 mips16e_add_register_range (char *s, unsigned int min_reg,
7483 unsigned int max_reg)
7485 if (min_reg != max_reg)
7486 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7488 s += sprintf (s, ",%s", reg_names[min_reg]);
7492 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7493 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7496 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7498 static char buffer[300];
7500 struct mips16e_save_restore_info info;
7501 unsigned int i, end;
7504 /* Parse the pattern. */
7505 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7508 /* Add the mnemonic. */
7509 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7512 /* Save the arguments. */
7514 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7515 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7516 else if (info.nargs == 1)
7517 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7519 /* Emit the amount of stack space to allocate or deallocate. */
7520 s += sprintf (s, "%d", (int) info.size);
7522 /* Save or restore $16. */
7523 if (BITSET_P (info.mask, 16))
7524 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7526 /* Save or restore $17. */
7527 if (BITSET_P (info.mask, 17))
7528 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7530 /* Save or restore registers in the range $s2...$s8, which
7531 mips16e_s2_s8_regs lists in decreasing order. Note that this
7532 is a software register range; the hardware registers are not
7533 numbered consecutively. */
7534 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7535 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7537 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7538 mips16e_s2_s8_regs[i]);
7540 /* Save or restore registers in the range $a0...$a3. */
7541 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7542 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7544 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7545 mips16e_a0_a3_regs[end - 1]);
7547 /* Save or restore $31. */
7548 if (BITSET_P (info.mask, 31))
7549 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7554 /* Return true if the current function has an insn that implicitly
7558 mips_function_has_gp_insn (void)
7560 /* Don't bother rechecking if we found one last time. */
7561 if (!cfun->machine->has_gp_insn_p)
7565 push_topmost_sequence ();
7566 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7567 if (USEFUL_INSN_P (insn)
7568 && (get_attr_got (insn) != GOT_UNSET
7569 || mips_small_data_pattern_p (PATTERN (insn))))
7571 cfun->machine->has_gp_insn_p = true;
7574 pop_topmost_sequence ();
7576 return cfun->machine->has_gp_insn_p;
7579 /* Return the register that should be used as the global pointer
7580 within this function. Return 0 if the function doesn't need
7581 a global pointer. */
7584 mips_global_pointer (void)
7588 /* $gp is always available unless we're using a GOT. */
7589 if (!TARGET_USE_GOT)
7590 return GLOBAL_POINTER_REGNUM;
7592 /* We must always provide $gp when it is used implicitly. */
7593 if (!TARGET_EXPLICIT_RELOCS)
7594 return GLOBAL_POINTER_REGNUM;
7596 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7598 if (current_function_profile)
7599 return GLOBAL_POINTER_REGNUM;
7601 /* If the function has a nonlocal goto, $gp must hold the correct
7602 global pointer for the target function. */
7603 if (current_function_has_nonlocal_goto)
7604 return GLOBAL_POINTER_REGNUM;
7606 /* If the gp is never referenced, there's no need to initialize it.
7607 Note that reload can sometimes introduce constant pool references
7608 into a function that otherwise didn't need them. For example,
7609 suppose we have an instruction like:
7611 (set (reg:DF R1) (float:DF (reg:SI R2)))
7613 If R2 turns out to be constant such as 1, the instruction may have a
7614 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7615 using this constant if R2 doesn't get allocated to a register.
7617 In cases like these, reload will have added the constant to the pool
7618 but no instruction will yet refer to it. */
7619 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
7620 && !current_function_uses_const_pool
7621 && !mips_function_has_gp_insn ())
7624 /* We need a global pointer, but perhaps we can use a call-clobbered
7625 register instead of $gp. */
7626 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
7627 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7628 if (!df_regs_ever_live_p (regno)
7629 && call_really_used_regs[regno]
7630 && !fixed_regs[regno]
7631 && regno != PIC_FUNCTION_ADDR_REGNUM)
7634 return GLOBAL_POINTER_REGNUM;
7637 /* Return true if the current function returns its value in a floating-point
7638 register in MIPS16 mode. */
7641 mips16_cfun_returns_in_fpr_p (void)
7643 tree return_type = DECL_RESULT (current_function_decl);
7644 return (TARGET_MIPS16
7645 && TARGET_HARD_FLOAT_ABI
7646 && !aggregate_value_p (return_type, current_function_decl)
7647 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
7650 /* Return true if the current function must save register REGNO. */
7653 mips_save_reg_p (unsigned int regno)
7655 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7656 if we have not chosen a call-clobbered substitute. */
7657 if (regno == GLOBAL_POINTER_REGNUM)
7658 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
7660 /* Check call-saved registers. */
7661 if ((current_function_saves_all_registers || df_regs_ever_live_p (regno))
7662 && !call_really_used_regs[regno])
7665 /* Save both registers in an FPR pair if either one is used. This is
7666 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7667 register to be used without the even register. */
7668 if (FP_REG_P (regno)
7669 && MAX_FPRS_PER_FMT == 2
7670 && df_regs_ever_live_p (regno + 1)
7671 && !call_really_used_regs[regno + 1])
7674 /* We need to save the old frame pointer before setting up a new one. */
7675 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7678 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7679 if (current_function_profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
7682 /* We need to save the incoming return address if it is ever clobbered
7683 within the function, if __builtin_eh_return is being used to set a
7684 different return address, or if a stub is being used to return a
7686 if (regno == GP_REG_FIRST + 31
7687 && (df_regs_ever_live_p (regno)
7688 || current_function_calls_eh_return
7689 || mips16_cfun_returns_in_fpr_p ()))
7695 /* Populate the current function's mips_frame_info structure.
7697 MIPS stack frames look like:
7699 +-------------------------------+
7701 | incoming stack arguments |
7703 +-------------------------------+
7705 | caller-allocated save area |
7706 A | for register arguments |
7708 +-------------------------------+ <-- incoming stack pointer
7710 | callee-allocated save area |
7711 B | for arguments that are |
7712 | split between registers and |
7715 +-------------------------------+ <-- arg_pointer_rtx
7717 C | callee-allocated save area |
7718 | for register varargs |
7720 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7721 | | + UNITS_PER_HWFPVALUE
7724 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7725 | | + UNITS_PER_WORD
7728 +-------------------------------+
7730 | local variables | | var_size
7732 +-------------------------------+
7734 | $gp save area | | cprestore_size
7736 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7738 | outgoing stack arguments |
7740 +-------------------------------+
7742 | caller-allocated save area |
7743 | for register arguments |
7745 +-------------------------------+ <-- stack_pointer_rtx
7747 hard_frame_pointer_rtx for
7750 At least two of A, B and C will be empty.
7752 Dynamic stack allocations such as alloca insert data at point P.
7753 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7754 hard_frame_pointer_rtx unchanged. */
7757 mips_compute_frame_info (void)
7759 struct mips_frame_info *frame;
7760 HOST_WIDE_INT offset, size;
7761 unsigned int regno, i;
7763 frame = &cfun->machine->frame;
7764 memset (frame, 0, sizeof (*frame));
7765 size = get_frame_size ();
7767 cfun->machine->global_pointer = mips_global_pointer ();
7769 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
7770 area and the $gp save slot. This area isn't needed in leaf functions,
7771 but if the target-independent frame size is nonzero, we're committed
7772 to allocating it anyway. */
7773 if (size == 0 && current_function_is_leaf)
7775 /* The MIPS 3.0 linker does not like functions that dynamically
7776 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7777 looks like we are trying to create a second frame pointer to the
7778 function, so allocate some stack space to make it happy. */
7779 if (current_function_calls_alloca)
7780 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
7782 frame->args_size = 0;
7783 frame->cprestore_size = 0;
7787 frame->args_size = current_function_outgoing_args_size;
7788 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
7790 offset = frame->args_size + frame->cprestore_size;
7792 /* Move above the local variables. */
7793 frame->var_size = MIPS_STACK_ALIGN (size);
7794 offset += frame->var_size;
7796 /* Find out which GPRs we need to save. */
7797 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7798 if (mips_save_reg_p (regno))
7801 frame->mask |= 1 << (regno - GP_REG_FIRST);
7804 /* If this function calls eh_return, we must also save and restore the
7805 EH data registers. */
7806 if (current_function_calls_eh_return)
7807 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
7810 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
7813 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7814 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7815 save all later registers too. */
7816 if (GENERATE_MIPS16E_SAVE_RESTORE)
7818 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
7819 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
7820 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
7821 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
7824 /* Move above the GPR save area. */
7825 if (frame->num_gp > 0)
7827 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
7828 frame->gp_sp_offset = offset - UNITS_PER_WORD;
7831 /* Find out which FPRs we need to save. This loop must iterate over
7832 the same space as its companion in mips_for_each_saved_reg. */
7833 if (TARGET_HARD_FLOAT)
7834 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
7835 if (mips_save_reg_p (regno))
7837 frame->num_fp += MAX_FPRS_PER_FMT;
7838 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
7841 /* Move above the FPR save area. */
7842 if (frame->num_fp > 0)
7844 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
7845 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
7848 /* Move above the callee-allocated varargs save area. */
7849 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
7850 frame->arg_pointer_offset = offset;
7852 /* Move above the callee-allocated area for pretend stack arguments. */
7853 offset += current_function_pretend_args_size;
7854 frame->total_size = offset;
7856 /* Work out the offsets of the save areas from the top of the frame. */
7857 if (frame->gp_sp_offset > 0)
7858 frame->gp_save_offset = frame->gp_sp_offset - offset;
7859 if (frame->fp_sp_offset > 0)
7860 frame->fp_save_offset = frame->fp_sp_offset - offset;
7862 /* MIPS16 code offsets the frame pointer by the size of the outgoing
7863 arguments. This tends to increase the chances of using unextended
7864 instructions for local variables and incoming arguments. */
7866 frame->hard_frame_pointer_offset = frame->args_size;
7869 /* Return the style of GP load sequence that is being used for the
7870 current function. */
7872 enum mips_loadgp_style
7873 mips_current_loadgp_style (void)
7875 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
7881 if (TARGET_ABSOLUTE_ABICALLS)
7882 return LOADGP_ABSOLUTE;
7884 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
7887 /* Implement FRAME_POINTER_REQUIRED. */
7890 mips_frame_pointer_required (void)
7892 /* If the function contains dynamic stack allocations, we need to
7893 use the frame pointer to access the static parts of the frame. */
7894 if (current_function_calls_alloca)
7897 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
7898 reload may be unable to compute the address of a local variable,
7899 since there is no way to add a large constant to the stack pointer
7900 without using a second temporary register. */
7903 mips_compute_frame_info ();
7904 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
7911 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
7912 or argument pointer. TO is either the stack pointer or hard frame
7916 mips_initial_elimination_offset (int from, int to)
7918 HOST_WIDE_INT offset;
7920 mips_compute_frame_info ();
7922 /* Set OFFSET to the offset from the soft frame pointer, which is also
7923 the offset from the end-of-prologue stack pointer. */
7926 case FRAME_POINTER_REGNUM:
7930 case ARG_POINTER_REGNUM:
7931 offset = cfun->machine->frame.arg_pointer_offset;
7938 if (to == HARD_FRAME_POINTER_REGNUM)
7939 offset -= cfun->machine->frame.hard_frame_pointer_offset;
7944 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
7945 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
7948 mips_extra_live_on_entry (bitmap regs)
7950 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
7951 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
7954 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7958 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
7963 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
7966 /* Emit code to change the current function's return address to
7967 ADDRESS. SCRATCH is available as a scratch register, if needed.
7968 ADDRESS and SCRATCH are both word-mode GPRs. */
7971 mips_set_return_address (rtx address, rtx scratch)
7975 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
7976 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
7977 cfun->machine->frame.gp_sp_offset);
7978 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
7981 /* Restore $gp from its save slot. Valid only when using o32 or
7985 mips_restore_gp (void)
7989 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
7991 base = frame_pointer_needed ? hard_frame_pointer_rtx : stack_pointer_rtx;
7992 address = mips_add_offset (pic_offset_table_rtx, base,
7993 current_function_outgoing_args_size);
7994 mips_emit_move (pic_offset_table_rtx, gen_frame_mem (Pmode, address));
7995 if (!TARGET_EXPLICIT_RELOCS)
7996 emit_insn (gen_blockage ());
7999 /* A function to save or store a register. The first argument is the
8000 register and the second is the stack slot. */
8001 typedef void (*mips_save_restore_fn) (rtx, rtx);
8003 /* Use FN to save or restore register REGNO. MODE is the register's
8004 mode and OFFSET is the offset of its save slot from the current
8008 mips_save_restore_reg (enum machine_mode mode, int regno,
8009 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8013 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8014 fn (gen_rtx_REG (mode, regno), mem);
8017 /* Call FN for each register that is saved by the current function.
8018 SP_OFFSET is the offset of the current stack pointer from the start
8022 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8024 enum machine_mode fpr_mode;
8025 HOST_WIDE_INT offset;
8028 /* Save registers starting from high to low. The debuggers prefer at least
8029 the return register be stored at func+4, and also it allows us not to
8030 need a nop in the epilogue if at least one register is reloaded in
8031 addition to return address. */
8032 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8033 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8034 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8036 mips_save_restore_reg (word_mode, regno, offset, fn);
8037 offset -= UNITS_PER_WORD;
8040 /* This loop must iterate over the same space as its companion in
8041 mips_compute_frame_info. */
8042 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8043 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8044 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
8045 regno >= FP_REG_FIRST;
8046 regno -= MAX_FPRS_PER_FMT)
8047 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8049 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8050 offset -= GET_MODE_SIZE (fpr_mode);
8054 /* If we're generating n32 or n64 abicalls, and the current function
8055 does not use $28 as its global pointer, emit a cplocal directive.
8056 Use pic_offset_table_rtx as the argument to the directive. */
8059 mips_output_cplocal (void)
8061 if (!TARGET_EXPLICIT_RELOCS
8062 && cfun->machine->global_pointer > 0
8063 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8064 output_asm_insn (".cplocal %+", 0);
8067 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
8070 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8074 #ifdef SDB_DEBUGGING_INFO
8075 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8076 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8079 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
8080 floating-point arguments. */
8082 && TARGET_HARD_FLOAT_ABI
8083 && current_function_args_info.fp_code != 0)
8084 mips16_build_function_stub ();
8086 /* Select the MIPS16 mode for this function. */
8088 fprintf (file, "\t.set\tmips16\n");
8090 fprintf (file, "\t.set\tnomips16\n");
8092 if (!FUNCTION_NAME_ALREADY_DECLARED)
8094 /* Get the function name the same way that toplev.c does before calling
8095 assemble_start_function. This is needed so that the name used here
8096 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8097 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8099 if (!flag_inhibit_size_directive)
8101 fputs ("\t.ent\t", file);
8102 assemble_name (file, fnname);
8106 assemble_name (file, fnname);
8107 fputs (":\n", file);
8110 /* Stop mips_file_end from treating this function as external. */
8111 if (TARGET_IRIX && mips_abi == ABI_32)
8112 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8114 /* Output MIPS-specific frame information. */
8115 if (!flag_inhibit_size_directive)
8117 const struct mips_frame_info *frame;
8119 frame = &cfun->machine->frame;
8121 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
8123 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8124 "# vars= " HOST_WIDE_INT_PRINT_DEC
8126 ", args= " HOST_WIDE_INT_PRINT_DEC
8127 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8128 reg_names[frame_pointer_needed
8129 ? HARD_FRAME_POINTER_REGNUM
8130 : STACK_POINTER_REGNUM],
8131 (frame_pointer_needed
8132 ? frame->total_size - frame->hard_frame_pointer_offset
8133 : frame->total_size),
8134 reg_names[GP_REG_FIRST + 31],
8136 frame->num_gp, frame->num_fp,
8138 frame->cprestore_size);
8140 /* .mask MASK, OFFSET. */
8141 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8142 frame->mask, frame->gp_save_offset);
8144 /* .fmask MASK, OFFSET. */
8145 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8146 frame->fmask, frame->fp_save_offset);
8149 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
8150 Also emit the ".set noreorder; .set nomacro" sequence for functions
8152 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8154 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
8155 if (!cfun->machine->all_noreorder_p)
8156 output_asm_insn ("%(.cpload\t%^%)", 0);
8158 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8160 else if (cfun->machine->all_noreorder_p)
8161 output_asm_insn ("%(%<", 0);
8163 /* Tell the assembler which register we're using as the global
8164 pointer. This is needed for thunks, since they can use either
8165 explicit relocs or assembler macros. */
8166 mips_output_cplocal ();
8169 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
8172 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8173 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8175 /* Reinstate the normal $gp. */
8176 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8177 mips_output_cplocal ();
8179 if (cfun->machine->all_noreorder_p)
8181 /* Avoid using %>%) since it adds excess whitespace. */
8182 output_asm_insn (".set\tmacro", 0);
8183 output_asm_insn (".set\treorder", 0);
8184 set_noreorder = set_nomacro = 0;
8187 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
8191 /* Get the function name the same way that toplev.c does before calling
8192 assemble_start_function. This is needed so that the name used here
8193 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8194 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8195 fputs ("\t.end\t", file);
8196 assemble_name (file, fnname);
8201 /* Save register REG to MEM. Make the instruction frame-related. */
8204 mips_save_reg (rtx reg, rtx mem)
8206 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
8210 if (mips_split_64bit_move_p (mem, reg))
8211 mips_split_doubleword_move (mem, reg);
8213 mips_emit_move (mem, reg);
8215 x1 = mips_frame_set (mips_subword (mem, false),
8216 mips_subword (reg, false));
8217 x2 = mips_frame_set (mips_subword (mem, true),
8218 mips_subword (reg, true));
8219 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
8224 && REGNO (reg) != GP_REG_FIRST + 31
8225 && !M16_REG_P (REGNO (reg)))
8227 /* Save a non-MIPS16 register by moving it through a temporary.
8228 We don't need to do this for $31 since there's a special
8229 instruction for it. */
8230 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
8231 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
8234 mips_emit_move (mem, reg);
8236 mips_set_frame_expr (mips_frame_set (mem, reg));
8240 /* The __gnu_local_gp symbol. */
8242 static GTY(()) rtx mips_gnu_local_gp;
8244 /* If we're generating n32 or n64 abicalls, emit instructions
8245 to set up the global pointer. */
8248 mips_emit_loadgp (void)
8250 rtx addr, offset, incoming_address, base, index;
8252 switch (mips_current_loadgp_style ())
8254 case LOADGP_ABSOLUTE:
8255 if (mips_gnu_local_gp == NULL)
8257 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
8258 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
8260 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
8264 addr = XEXP (DECL_RTL (current_function_decl), 0);
8265 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
8266 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8267 emit_insn (gen_loadgp_newabi (offset, incoming_address));
8268 if (!TARGET_EXPLICIT_RELOCS)
8269 emit_insn (gen_loadgp_blockage ());
8273 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
8274 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
8275 emit_insn (gen_loadgp_rtp (base, index));
8276 if (!TARGET_EXPLICIT_RELOCS)
8277 emit_insn (gen_loadgp_blockage ());
8285 /* Expand the "prologue" pattern. */
8288 mips_expand_prologue (void)
8290 const struct mips_frame_info *frame;
8295 if (cfun->machine->global_pointer > 0)
8296 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8298 frame = &cfun->machine->frame;
8299 size = frame->total_size;
8301 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8302 bytes beforehand; this is enough to cover the register save area
8303 without going out of range. */
8304 if ((frame->mask | frame->fmask) != 0)
8306 HOST_WIDE_INT step1;
8308 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
8309 if (GENERATE_MIPS16E_SAVE_RESTORE)
8311 HOST_WIDE_INT offset;
8312 unsigned int mask, regno;
8314 /* Try to merge argument stores into the save instruction. */
8315 nargs = mips16e_collect_argument_saves ();
8317 /* Build the save instruction. */
8319 insn = mips16e_build_save_restore (false, &mask, &offset,
8321 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8324 /* Check if we need to save other registers. */
8325 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8326 if (BITSET_P (mask, regno - GP_REG_FIRST))
8328 offset -= UNITS_PER_WORD;
8329 mips_save_restore_reg (word_mode, regno,
8330 offset, mips_save_reg);
8335 insn = gen_add3_insn (stack_pointer_rtx,
8338 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8340 mips_for_each_saved_reg (size, mips_save_reg);
8344 /* Allocate the rest of the frame. */
8347 if (SMALL_OPERAND (-size))
8348 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
8350 GEN_INT (-size)))) = 1;
8353 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
8356 /* There are no instructions to add or subtract registers
8357 from the stack pointer, so use the frame pointer as a
8358 temporary. We should always be using a frame pointer
8359 in this case anyway. */
8360 gcc_assert (frame_pointer_needed);
8361 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8362 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
8363 hard_frame_pointer_rtx,
8364 MIPS_PROLOGUE_TEMP (Pmode)));
8365 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
8368 emit_insn (gen_sub3_insn (stack_pointer_rtx,
8370 MIPS_PROLOGUE_TEMP (Pmode)));
8372 /* Describe the combined effect of the previous instructions. */
8374 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8375 plus_constant (stack_pointer_rtx, -size)));
8379 /* Set up the frame pointer, if we're using one. */
8380 if (frame_pointer_needed)
8382 HOST_WIDE_INT offset;
8384 offset = frame->hard_frame_pointer_offset;
8387 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8388 RTX_FRAME_RELATED_P (insn) = 1;
8390 else if (SMALL_OPERAND (offset))
8392 insn = gen_add3_insn (hard_frame_pointer_rtx,
8393 stack_pointer_rtx, GEN_INT (offset));
8394 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8398 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
8399 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8400 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
8401 hard_frame_pointer_rtx,
8402 MIPS_PROLOGUE_TEMP (Pmode)));
8404 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
8405 plus_constant (stack_pointer_rtx, offset)));
8409 mips_emit_loadgp ();
8411 /* Initialize the $gp save slot. */
8412 if (frame->cprestore_size > 0)
8413 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
8415 /* If we are profiling, make sure no instructions are scheduled before
8416 the call to mcount. */
8417 if (current_function_profile)
8418 emit_insn (gen_blockage ());
8421 /* Emit instructions to restore register REG from slot MEM. */
8424 mips_restore_reg (rtx reg, rtx mem)
8426 /* There's no MIPS16 instruction to load $31 directly. Load into
8427 $7 instead and adjust the return insn appropriately. */
8428 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
8429 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
8431 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
8433 /* Can't restore directly; move through a temporary. */
8434 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
8435 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
8438 mips_emit_move (reg, mem);
8441 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
8445 mips_expand_epilogue (bool sibcall_p)
8447 const struct mips_frame_info *frame;
8448 HOST_WIDE_INT step1, step2;
8451 if (!sibcall_p && mips_can_use_return_insn ())
8453 emit_jump_insn (gen_return ());
8457 /* In MIPS16 mode, if the return value should go into a floating-point
8458 register, we need to call a helper routine to copy it over. */
8459 if (mips16_cfun_returns_in_fpr_p ())
8460 mips16_copy_fpr_return_value ();
8462 /* Split the frame into two. STEP1 is the amount of stack we should
8463 deallocate before restoring the registers. STEP2 is the amount we
8464 should deallocate afterwards.
8466 Start off by assuming that no registers need to be restored. */
8467 frame = &cfun->machine->frame;
8468 step1 = frame->total_size;
8471 /* Work out which register holds the frame address. */
8472 if (!frame_pointer_needed)
8473 base = stack_pointer_rtx;
8476 base = hard_frame_pointer_rtx;
8477 step1 -= frame->hard_frame_pointer_offset;
8480 /* If we need to restore registers, deallocate as much stack as
8481 possible in the second step without going out of range. */
8482 if ((frame->mask | frame->fmask) != 0)
8484 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
8488 /* Set TARGET to BASE + STEP1. */
8494 /* Get an rtx for STEP1 that we can add to BASE. */
8495 adjust = GEN_INT (step1);
8496 if (!SMALL_OPERAND (step1))
8498 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
8499 adjust = MIPS_EPILOGUE_TEMP (Pmode);
8502 /* Normal mode code can copy the result straight into $sp. */
8504 target = stack_pointer_rtx;
8506 emit_insn (gen_add3_insn (target, base, adjust));
8509 /* Copy TARGET into the stack pointer. */
8510 if (target != stack_pointer_rtx)
8511 mips_emit_move (stack_pointer_rtx, target);
8513 /* If we're using addressing macros, $gp is implicitly used by all
8514 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8516 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
8517 emit_insn (gen_blockage ());
8519 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
8521 unsigned int regno, mask;
8522 HOST_WIDE_INT offset;
8525 /* Generate the restore instruction. */
8527 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
8529 /* Restore any other registers manually. */
8530 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8531 if (BITSET_P (mask, regno - GP_REG_FIRST))
8533 offset -= UNITS_PER_WORD;
8534 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
8537 /* Restore the remaining registers and deallocate the final bit
8539 emit_insn (restore);
8543 /* Restore the registers. */
8544 mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
8546 /* Deallocate the final bit of the frame. */
8548 emit_insn (gen_add3_insn (stack_pointer_rtx,
8553 /* Add in the __builtin_eh_return stack adjustment. We need to
8554 use a temporary in MIPS16 code. */
8555 if (current_function_calls_eh_return)
8559 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
8560 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
8561 MIPS_EPILOGUE_TEMP (Pmode),
8562 EH_RETURN_STACKADJ_RTX));
8563 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
8566 emit_insn (gen_add3_insn (stack_pointer_rtx,
8568 EH_RETURN_STACKADJ_RTX));
8575 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8576 path will restore the return address into $7 rather than $31. */
8578 && !GENERATE_MIPS16E_SAVE_RESTORE
8579 && BITSET_P (frame->mask, 31))
8580 regno = GP_REG_FIRST + 7;
8582 regno = GP_REG_FIRST + 31;
8583 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
8587 /* Return nonzero if this function is known to have a null epilogue.
8588 This allows the optimizer to omit jumps to jumps if no stack
8592 mips_can_use_return_insn (void)
8594 if (!reload_completed)
8597 if (current_function_profile)
8600 /* In MIPS16 mode, a function that returns a floating-point value
8601 needs to arrange to copy the return value into the floating-point
8603 if (mips16_cfun_returns_in_fpr_p ())
8606 return cfun->machine->frame.total_size == 0;
8609 /* Return true if register REGNO can store a value of mode MODE.
8610 The result of this function is cached in mips_hard_regno_mode_ok. */
8613 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
8616 enum mode_class class;
8618 if (mode == CCV2mode)
8621 && (regno - ST_REG_FIRST) % 2 == 0);
8623 if (mode == CCV4mode)
8626 && (regno - ST_REG_FIRST) % 4 == 0);
8631 return regno == FPSW_REGNUM;
8633 return (ST_REG_P (regno)
8635 || FP_REG_P (regno));
8638 size = GET_MODE_SIZE (mode);
8639 class = GET_MODE_CLASS (mode);
8641 if (GP_REG_P (regno))
8642 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
8644 if (FP_REG_P (regno)
8645 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
8646 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
8648 /* Allow TFmode for CCmode reloads. */
8649 if (mode == TFmode && ISA_HAS_8CC)
8652 if (class == MODE_FLOAT
8653 || class == MODE_COMPLEX_FLOAT
8654 || class == MODE_VECTOR_FLOAT)
8655 return size <= UNITS_PER_FPVALUE;
8657 /* Allow integer modes that fit into a single register. We need
8658 to put integers into FPRs when using instructions like CVT
8659 and TRUNC. There's no point allowing sizes smaller than a word,
8660 because the FPU has no appropriate load/store instructions. */
8661 if (class == MODE_INT)
8662 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
8665 if (ACC_REG_P (regno)
8666 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
8668 if (size <= UNITS_PER_WORD)
8671 if (size <= UNITS_PER_WORD * 2)
8672 return (DSP_ACC_REG_P (regno)
8673 ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0
8674 : regno == MD_REG_FIRST);
8677 if (ALL_COP_REG_P (regno))
8678 return class == MODE_INT && size <= UNITS_PER_WORD;
8683 /* Implement HARD_REGNO_NREGS. */
8686 mips_hard_regno_nregs (int regno, enum machine_mode mode)
8688 if (ST_REG_P (regno))
8689 /* The size of FP status registers is always 4, because they only hold
8690 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8691 return (GET_MODE_SIZE (mode) + 3) / 4;
8693 if (FP_REG_P (regno))
8694 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8696 /* All other registers are word-sized. */
8697 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8700 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8701 in mips_hard_regno_nregs. */
8704 mips_class_max_nregs (enum reg_class class, enum machine_mode mode)
8710 COPY_HARD_REG_SET (left, reg_class_contents[(int) class]);
8711 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
8713 size = MIN (size, 4);
8714 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
8716 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
8718 size = MIN (size, UNITS_PER_FPREG);
8719 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
8721 if (!hard_reg_set_empty_p (left))
8722 size = MIN (size, UNITS_PER_WORD);
8723 return (GET_MODE_SIZE (mode) + size - 1) / size;
8726 /* Implement CANNOT_CHANGE_MODE_CLASS. */
8729 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
8730 enum machine_mode to ATTRIBUTE_UNUSED,
8731 enum reg_class class)
8733 /* There are several problems with changing the modes of values
8734 in floating-point registers:
8736 - When a multi-word value is stored in paired floating-point
8737 registers, the first register always holds the low word.
8738 We therefore can't allow FPRs to change between single-word
8739 and multi-word modes on big-endian targets.
8741 - GCC assumes that each word of a multiword register can be accessed
8742 individually using SUBREGs. This is not true for floating-point
8743 registers if they are bigger than a word.
8745 - Loading a 32-bit value into a 64-bit floating-point register
8746 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8747 We can't allow FPRs to change from SImode to to a wider mode on
8750 - If the FPU has already interpreted a value in one format, we must
8751 not ask it to treat the value as having a different format.
8753 We therefore disallow all mode changes involving FPRs. */
8754 return reg_classes_intersect_p (FP_REGS, class);
8757 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
8760 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
8765 return TARGET_HARD_FLOAT;
8768 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
8771 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
8778 /* Implement MODES_TIEABLE_P. */
8781 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
8783 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
8784 prefer to put one of them in FPRs. */
8785 return (mode1 == mode2
8786 || (!mips_mode_ok_for_mov_fmt_p (mode1)
8787 && !mips_mode_ok_for_mov_fmt_p (mode2)));
8790 /* Implement PREFERRED_RELOAD_CLASS. */
8793 mips_preferred_reload_class (rtx x, enum reg_class class)
8795 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8798 if (reg_class_subset_p (FP_REGS, class)
8799 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
8802 if (reg_class_subset_p (GR_REGS, class))
8805 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8811 /* Implement REGISTER_MOVE_COST. */
8814 mips_register_move_cost (enum machine_mode mode,
8815 enum reg_class to, enum reg_class from)
8819 /* ??? We cannot move general registers into HI and LO because
8820 MIPS16 has no MTHI and MTLO instructions. Make the cost of
8821 moves in the opposite direction just as high, which stops the
8822 register allocators from using HI and LO for pseudos. */
8823 if (reg_class_subset_p (from, GENERAL_REGS)
8824 && reg_class_subset_p (to, GENERAL_REGS))
8826 if (reg_class_subset_p (from, M16_REGS)
8827 || reg_class_subset_p (to, M16_REGS))
8833 else if (reg_class_subset_p (from, GENERAL_REGS))
8835 if (reg_class_subset_p (to, GENERAL_REGS))
8837 if (reg_class_subset_p (to, FP_REGS))
8839 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
8841 if (reg_class_subset_p (to, ACC_REGS))
8844 else if (reg_class_subset_p (to, GENERAL_REGS))
8846 if (reg_class_subset_p (from, FP_REGS))
8848 if (reg_class_subset_p (from, ST_REGS))
8849 /* LUI followed by MOVF. */
8851 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
8853 if (reg_class_subset_p (from, ACC_REGS))
8856 else if (reg_class_subset_p (from, FP_REGS))
8858 if (reg_class_subset_p (to, FP_REGS)
8859 && mips_mode_ok_for_mov_fmt_p (mode))
8861 if (reg_class_subset_p (to, ST_REGS))
8862 /* An expensive sequence. */
8869 /* Return the register class required for a secondary register when
8870 copying between one of the registers in CLASS and value X, which
8871 has mode MODE. X is the source of the move if IN_P, otherwise it
8872 is the destination. Return NO_REGS if no secondary register is
8876 mips_secondary_reload_class (enum reg_class class,
8877 enum machine_mode mode, rtx x, bool in_p)
8881 /* If X is a constant that cannot be loaded into $25, it must be loaded
8882 into some other GPR. No other register class allows a direct move. */
8883 if (mips_dangerous_for_la25_p (x))
8884 return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
8886 regno = true_regnum (x);
8889 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
8890 if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
8893 /* We can't really copy to HI or LO at all in MIPS16 mode. */
8894 if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
8900 /* Copying from accumulator registers to anywhere other than a general
8901 register requires a temporary general register. */
8902 if (reg_class_subset_p (class, ACC_REGS))
8903 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8904 if (ACC_REG_P (regno))
8905 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
8907 /* We can only copy a value to a condition code register from a
8908 floating-point register, and even then we require a scratch
8909 floating-point register. We can only copy a value out of a
8910 condition-code register into a general register. */
8911 if (reg_class_subset_p (class, ST_REGS))
8915 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8917 if (ST_REG_P (regno))
8921 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
8924 if (reg_class_subset_p (class, FP_REGS))
8927 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
8928 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
8929 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
8932 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
8933 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8936 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
8937 /* We can force the constant to memory and use lwc1
8938 and ldc1. As above, we will use pairs of lwc1s if
8939 ldc1 is not supported. */
8942 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
8943 /* In this case we can use mov.fmt. */
8946 /* Otherwise, we need to reload through an integer register. */
8949 if (FP_REG_P (regno))
8950 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
8955 /* Implement TARGET_MODE_REP_EXTENDED. */
8958 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
8960 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
8961 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
8967 /* Implement TARGET_VALID_POINTER_MODE. */
8970 mips_valid_pointer_mode (enum machine_mode mode)
8972 return mode == SImode || (TARGET_64BIT && mode == DImode);
8975 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
8978 mips_vector_mode_supported_p (enum machine_mode mode)
8983 return TARGET_PAIRED_SINGLE_FLOAT;
9000 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9003 mips_scalar_mode_supported_p (enum machine_mode mode)
9005 if (ALL_FIXED_POINT_MODE_P (mode)
9006 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9009 return default_scalar_mode_supported_p (mode);
9012 /* Implement TARGET_INIT_LIBFUNCS. */
9014 #include "config/gofast.h"
9017 mips_init_libfuncs (void)
9019 if (TARGET_FIX_VR4120)
9021 /* Register the special divsi3 and modsi3 functions needed to work
9022 around VR4120 division errata. */
9023 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9024 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9027 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9029 /* Register the MIPS16 -mhard-float stubs. */
9030 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9031 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9032 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9033 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9035 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9036 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9037 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9038 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9039 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9040 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9041 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9043 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9044 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9045 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9047 if (TARGET_DOUBLE_FLOAT)
9049 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9050 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9051 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9052 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9054 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9055 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9056 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9057 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9058 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9059 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9060 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9062 set_conv_libfunc (sext_optab, DFmode, SFmode,
9063 "__mips16_extendsfdf2");
9064 set_conv_libfunc (trunc_optab, SFmode, DFmode,
9065 "__mips16_truncdfsf2");
9066 set_conv_libfunc (sfix_optab, SImode, DFmode,
9067 "__mips16_fix_truncdfsi");
9068 set_conv_libfunc (sfloat_optab, DFmode, SImode,
9069 "__mips16_floatsidf");
9070 set_conv_libfunc (ufloat_optab, DFmode, SImode,
9071 "__mips16_floatunsidf");
9075 /* Register the gofast functions if selected using --enable-gofast. */
9076 gofast_maybe_init_libfuncs ();
9079 /* Return the length of INSN. LENGTH is the initial length computed by
9080 attributes in the machine-description file. */
9083 mips_adjust_insn_length (rtx insn, int length)
9085 /* A unconditional jump has an unfilled delay slot if it is not part
9086 of a sequence. A conditional jump normally has a delay slot, but
9087 does not on MIPS16. */
9088 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9091 /* See how many nops might be needed to avoid hardware hazards. */
9092 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9093 switch (get_attr_hazard (insn))
9107 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
9108 the .md file length attributes are 4-based for both modes.
9109 Adjust the MIPS16 ones here. */
9116 /* Return an asm sequence to start a noat block and load the address
9117 of a label into $1. */
9120 mips_output_load_label (void)
9122 if (TARGET_EXPLICIT_RELOCS)
9126 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9129 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9132 if (ISA_HAS_LOAD_DELAY)
9133 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9134 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9138 if (Pmode == DImode)
9139 return "%[dla\t%@,%0";
9141 return "%[la\t%@,%0";
9145 /* Return the assembly code for INSN, which has the operands given by
9146 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9147 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9148 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9149 version of BRANCH_IF_TRUE. */
9152 mips_output_conditional_branch (rtx insn, rtx *operands,
9153 const char *branch_if_true,
9154 const char *branch_if_false)
9156 unsigned int length;
9157 rtx taken, not_taken;
9159 length = get_attr_length (insn);
9162 /* Just a simple conditional branch. */
9163 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9164 return branch_if_true;
9167 /* Generate a reversed branch around a direct jump. This fallback does
9168 not use branch-likely instructions. */
9169 mips_branch_likely = false;
9170 not_taken = gen_label_rtx ();
9171 taken = operands[1];
9173 /* Generate the reversed branch to NOT_TAKEN. */
9174 operands[1] = not_taken;
9175 output_asm_insn (branch_if_false, operands);
9177 /* If INSN has a delay slot, we must provide delay slots for both the
9178 branch to NOT_TAKEN and the conditional jump. We must also ensure
9179 that INSN's delay slot is executed in the appropriate cases. */
9182 /* This first delay slot will always be executed, so use INSN's
9183 delay slot if is not annulled. */
9184 if (!INSN_ANNULLED_BRANCH_P (insn))
9186 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9187 asm_out_file, optimize, 1, NULL);
9188 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9191 output_asm_insn ("nop", 0);
9192 fprintf (asm_out_file, "\n");
9195 /* Output the unconditional branch to TAKEN. */
9197 output_asm_insn ("j\t%0%/", &taken);
9200 output_asm_insn (mips_output_load_label (), &taken);
9201 output_asm_insn ("jr\t%@%]%/", 0);
9204 /* Now deal with its delay slot; see above. */
9207 /* This delay slot will only be executed if the branch is taken.
9208 Use INSN's delay slot if is annulled. */
9209 if (INSN_ANNULLED_BRANCH_P (insn))
9211 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9212 asm_out_file, optimize, 1, NULL);
9213 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9216 output_asm_insn ("nop", 0);
9217 fprintf (asm_out_file, "\n");
9220 /* Output NOT_TAKEN. */
9221 targetm.asm_out.internal_label (asm_out_file, "L",
9222 CODE_LABEL_NUMBER (not_taken));
9226 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9227 if some ordering condition is true. The condition is given by
9228 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9229 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9230 its second is always zero. */
9233 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9235 const char *branch[2];
9237 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9238 Make BRANCH[0] branch on the inverse condition. */
9239 switch (GET_CODE (operands[0]))
9241 /* These cases are equivalent to comparisons against zero. */
9243 inverted_p = !inverted_p;
9246 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9247 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9250 /* These cases are always true or always false. */
9252 inverted_p = !inverted_p;
9255 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9256 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9260 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9261 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9264 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9267 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
9268 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
9270 When working around R4000 and R4400 errata, we need to make sure that
9271 the division is not immediately followed by a shift[1][2]. We also
9272 need to stop the division from being put into a branch delay slot[3].
9273 The easiest way to avoid both problems is to add a nop after the
9274 division. When a divide-by-zero check is needed, this nop can be
9275 used to fill the branch delay slot.
9277 [1] If a double-word or a variable shift executes immediately
9278 after starting an integer division, the shift may give an
9279 incorrect result. See quotations of errata #16 and #28 from
9280 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9281 in mips.md for details.
9283 [2] A similar bug to [1] exists for all revisions of the
9284 R4000 and the R4400 when run in an MC configuration.
9285 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9287 "19. In this following sequence:
9289 ddiv (or ddivu or div or divu)
9290 dsll32 (or dsrl32, dsra32)
9292 if an MPT stall occurs, while the divide is slipping the cpu
9293 pipeline, then the following double shift would end up with an
9296 Workaround: The compiler needs to avoid generating any
9297 sequence with divide followed by extended double shift."
9299 This erratum is also present in "MIPS R4400MC Errata, Processor
9300 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9301 & 3.0" as errata #10 and #4, respectively.
9303 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9304 (also valid for MIPS R4000MC processors):
9306 "52. R4000SC: This bug does not apply for the R4000PC.
9308 There are two flavors of this bug:
9310 1) If the instruction just after divide takes an RF exception
9311 (tlb-refill, tlb-invalid) and gets an instruction cache
9312 miss (both primary and secondary) and the line which is
9313 currently in secondary cache at this index had the first
9314 data word, where the bits 5..2 are set, then R4000 would
9315 get a wrong result for the div.
9320 ------------------- # end-of page. -tlb-refill
9325 ------------------- # end-of page. -tlb-invalid
9328 2) If the divide is in the taken branch delay slot, where the
9329 target takes RF exception and gets an I-cache miss for the
9330 exception vector or where I-cache miss occurs for the
9331 target address, under the above mentioned scenarios, the
9332 div would get wrong results.
9335 j r2 # to next page mapped or unmapped
9336 div r8,r9 # this bug would be there as long
9337 # as there is an ICache miss and
9338 nop # the "data pattern" is present
9341 beq r0, r0, NextPage # to Next page
9345 This bug is present for div, divu, ddiv, and ddivu
9348 Workaround: For item 1), OS could make sure that the next page
9349 after the divide instruction is also mapped. For item 2), the
9350 compiler could make sure that the divide instruction is not in
9351 the branch delay slot."
9353 These processors have PRId values of 0x00004220 and 0x00004300 for
9354 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9357 mips_output_division (const char *division, rtx *operands)
9362 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9364 output_asm_insn (s, operands);
9367 if (TARGET_CHECK_ZERO_DIV)
9371 output_asm_insn (s, operands);
9372 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9374 else if (GENERATE_DIVIDE_TRAPS)
9376 output_asm_insn (s, operands);
9381 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9382 output_asm_insn (s, operands);
9383 s = "break\t7%)\n1:";
9389 /* Return true if IN_INSN is a multiply-add or multiply-subtract
9390 instruction and if OUT_INSN assigns to the accumulator operand. */
9393 mips_linked_madd_p (rtx out_insn, rtx in_insn)
9397 x = single_set (in_insn);
9403 if (GET_CODE (x) == PLUS
9404 && GET_CODE (XEXP (x, 0)) == MULT
9405 && reg_set_p (XEXP (x, 1), out_insn))
9408 if (GET_CODE (x) == MINUS
9409 && GET_CODE (XEXP (x, 1)) == MULT
9410 && reg_set_p (XEXP (x, 0), out_insn))
9416 /* True if the dependency between OUT_INSN and IN_INSN is on the store
9417 data rather than the address. We need this because the cprestore
9418 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
9419 which causes the default routine to abort. We just return false
9423 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9425 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9428 return !store_data_bypass_p (out_insn, in_insn);
9431 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9432 dependencies have no cost, except on the 20Kc where output-dependence
9433 is treated like input-dependence. */
9436 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9437 rtx dep ATTRIBUTE_UNUSED, int cost)
9439 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
9442 if (REG_NOTE_KIND (link) != 0)
9447 /* Return the number of instructions that can be issued per cycle. */
9450 mips_issue_rate (void)
9454 case PROCESSOR_74KC:
9455 case PROCESSOR_74KF2_1:
9456 case PROCESSOR_74KF1_1:
9457 case PROCESSOR_74KF3_2:
9458 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9459 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9460 but in reality only a maximum of 3 insns can be issued as
9461 floating-point loads and stores also require a slot in the
9465 case PROCESSOR_20KC:
9466 case PROCESSOR_R4130:
9467 case PROCESSOR_R5400:
9468 case PROCESSOR_R5500:
9469 case PROCESSOR_R7000:
9470 case PROCESSOR_R9000:
9474 case PROCESSOR_SB1A:
9475 /* This is actually 4, but we get better performance if we claim 3.
9476 This is partly because of unwanted speculative code motion with the
9477 larger number, and partly because in most common cases we can't
9478 reach the theoretical max of 4. */
9486 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9487 be as wide as the scheduling freedom in the DFA. */
9490 mips_multipass_dfa_lookahead (void)
9492 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9499 /* Remove the instruction at index LOWER from ready queue READY and
9500 reinsert it in front of the instruction at index HIGHER. LOWER must
9504 mips_promote_ready (rtx *ready, int lower, int higher)
9509 new_head = ready[lower];
9510 for (i = lower; i < higher; i++)
9511 ready[i] = ready[i + 1];
9512 ready[i] = new_head;
9515 /* If the priority of the instruction at POS2 in the ready queue READY
9516 is within LIMIT units of that of the instruction at POS1, swap the
9517 instructions if POS2 is not already less than POS1. */
9520 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
9523 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
9528 ready[pos1] = ready[pos2];
9533 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9534 that may clobber hi or lo. */
9535 static rtx mips_macc_chains_last_hilo;
9537 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9538 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9541 mips_macc_chains_record (rtx insn)
9543 if (get_attr_may_clobber_hilo (insn))
9544 mips_macc_chains_last_hilo = insn;
9547 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9548 has NREADY elements, looking for a multiply-add or multiply-subtract
9549 instruction that is cumulative with mips_macc_chains_last_hilo.
9550 If there is one, promote it ahead of anything else that might
9551 clobber hi or lo. */
9554 mips_macc_chains_reorder (rtx *ready, int nready)
9558 if (mips_macc_chains_last_hilo != 0)
9559 for (i = nready - 1; i >= 0; i--)
9560 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9562 for (j = nready - 1; j > i; j--)
9563 if (recog_memoized (ready[j]) >= 0
9564 && get_attr_may_clobber_hilo (ready[j]))
9566 mips_promote_ready (ready, i, j);
9573 /* The last instruction to be scheduled. */
9574 static rtx vr4130_last_insn;
9576 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9577 points to an rtx that is initially an instruction. Nullify the rtx
9578 if the instruction uses the value of register X. */
9581 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
9586 insn_ptr = (rtx *) data;
9589 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9593 /* Return true if there is true register dependence between vr4130_last_insn
9597 vr4130_true_reg_dependence_p (rtx insn)
9599 note_stores (PATTERN (vr4130_last_insn),
9600 vr4130_true_reg_dependence_p_1, &insn);
9604 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9605 the ready queue and that INSN2 is the instruction after it, return
9606 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9607 in which INSN1 and INSN2 can probably issue in parallel, but for
9608 which (INSN2, INSN1) should be less sensitive to instruction
9609 alignment than (INSN1, INSN2). See 4130.md for more details. */
9612 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9614 sd_iterator_def sd_it;
9617 /* Check for the following case:
9619 1) there is some other instruction X with an anti dependence on INSN1;
9620 2) X has a higher priority than INSN2; and
9621 3) X is an arithmetic instruction (and thus has no unit restrictions).
9623 If INSN1 is the last instruction blocking X, it would better to
9624 choose (INSN1, X) over (INSN2, INSN1). */
9625 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
9626 if (DEP_TYPE (dep) == REG_DEP_ANTI
9627 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
9628 && recog_memoized (DEP_CON (dep)) >= 0
9629 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
9632 if (vr4130_last_insn != 0
9633 && recog_memoized (insn1) >= 0
9634 && recog_memoized (insn2) >= 0)
9636 /* See whether INSN1 and INSN2 use different execution units,
9637 or if they are both ALU-type instructions. If so, they can
9638 probably execute in parallel. */
9639 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9640 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9641 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9643 /* If only one of the instructions has a dependence on
9644 vr4130_last_insn, prefer to schedule the other one first. */
9645 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
9646 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
9647 if (dep1_p != dep2_p)
9650 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9651 is not an ALU-type instruction and if INSN1 uses the same
9652 execution unit. (Note that if this condition holds, we already
9653 know that INSN2 uses a different execution unit.) */
9654 if (class1 != VR4130_CLASS_ALU
9655 && recog_memoized (vr4130_last_insn) >= 0
9656 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9663 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9664 queue with at least two instructions. Swap the first two if
9665 vr4130_swap_insns_p says that it could be worthwhile. */
9668 vr4130_reorder (rtx *ready, int nready)
9670 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9671 mips_promote_ready (ready, nready - 2, nready - 1);
9674 /* Record whether last 74k AGEN instruction was a load or store. */
9675 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
9677 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9678 resets to TYPE_UNKNOWN state. */
9681 mips_74k_agen_init (rtx insn)
9683 if (!insn || !NONJUMP_INSN_P (insn))
9684 mips_last_74k_agen_insn = TYPE_UNKNOWN;
9687 enum attr_type type = get_attr_type (insn);
9688 if (type == TYPE_LOAD || type == TYPE_STORE)
9689 mips_last_74k_agen_insn = type;
9693 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9694 loads to be grouped together, and multiple stores to be grouped
9695 together. Swap things around in the ready queue to make this happen. */
9698 mips_74k_agen_reorder (rtx *ready, int nready)
9701 int store_pos, load_pos;
9706 for (i = nready - 1; i >= 0; i--)
9708 rtx insn = ready[i];
9709 if (USEFUL_INSN_P (insn))
9710 switch (get_attr_type (insn))
9713 if (store_pos == -1)
9727 if (load_pos == -1 || store_pos == -1)
9730 switch (mips_last_74k_agen_insn)
9733 /* Prefer to schedule loads since they have a higher latency. */
9735 /* Swap loads to the front of the queue. */
9736 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
9739 /* Swap stores to the front of the queue. */
9740 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
9747 /* Implement TARGET_SCHED_INIT. */
9750 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9751 int max_ready ATTRIBUTE_UNUSED)
9753 mips_macc_chains_last_hilo = 0;
9754 vr4130_last_insn = 0;
9755 mips_74k_agen_init (NULL_RTX);
9758 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
9761 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9762 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
9764 if (!reload_completed
9767 mips_macc_chains_reorder (ready, *nreadyp);
9769 if (reload_completed
9771 && !TARGET_VR4130_ALIGN
9773 vr4130_reorder (ready, *nreadyp);
9776 mips_74k_agen_reorder (ready, *nreadyp);
9778 return mips_issue_rate ();
9781 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9784 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9787 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
9788 if (USEFUL_INSN_P (insn))
9791 if (!reload_completed && TUNE_MACC_CHAINS)
9792 mips_macc_chains_record (insn);
9793 vr4130_last_insn = insn;
9795 mips_74k_agen_init (insn);
9800 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9801 return the first operand of the associated PREF or PREFX insn. */
9804 mips_prefetch_cookie (rtx write, rtx locality)
9806 /* store_streamed / load_streamed. */
9807 if (INTVAL (locality) <= 0)
9808 return GEN_INT (INTVAL (write) + 4);
9811 if (INTVAL (locality) <= 2)
9814 /* store_retained / load_retained. */
9815 return GEN_INT (INTVAL (write) + 6);
9818 /* This structure describes a single built-in function. */
9819 struct mips_builtin_description {
9820 /* The code of the main .md file instruction. See mips_builtin_type
9821 for more information. */
9822 enum insn_code icode;
9824 /* The floating-point comparison code to use with ICODE, if any. */
9825 enum mips_fp_condition cond;
9827 /* The name of the built-in function. */
9830 /* Specifies how the function should be expanded. */
9831 enum mips_builtin_type builtin_type;
9833 /* The function's prototype. */
9834 enum mips_function_type function_type;
9836 /* The target flags required for this function. */
9840 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9841 FUNCTION_TYPE and TARGET_FLAGS are mips_builtin_description fields. */
9842 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9843 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9844 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9846 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
9847 require TARGET_FLAGS. */
9848 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9849 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9850 "__builtin_mips_" #INSN "_" #COND "_s", \
9851 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9852 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9853 "__builtin_mips_" #INSN "_" #COND "_d", \
9854 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9856 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9857 The lower and upper forms require TARGET_FLAGS while the any and all
9858 forms require MASK_MIPS3D. */
9859 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9860 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9861 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9862 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9863 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9864 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9865 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9866 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9867 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9868 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9869 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9870 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9871 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9873 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9874 require MASK_MIPS3D. */
9875 #define CMP_4S_BUILTINS(INSN, COND) \
9876 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9877 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9878 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9880 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9881 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9882 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9885 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9886 instruction requires TARGET_FLAGS. */
9887 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9888 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9889 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9890 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9892 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9893 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9894 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9897 /* Define all the built-in functions related to C.cond.fmt condition COND. */
9898 #define CMP_BUILTINS(COND) \
9899 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9900 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9901 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9902 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9903 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9904 CMP_4S_BUILTINS (c, COND), \
9905 CMP_4S_BUILTINS (cabs, COND)
9907 static const struct mips_builtin_description mips_ps_bdesc[] = {
9908 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9909 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9910 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9911 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9912 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
9913 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9914 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9915 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
9917 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
9918 MASK_PAIRED_SINGLE_FLOAT),
9919 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9920 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9921 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9922 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9924 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9925 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9926 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9927 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9928 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9929 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9931 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9932 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9933 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9934 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9935 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9936 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9938 MIPS_FP_CONDITIONS (CMP_BUILTINS)
9941 /* Built-in functions for the SB-1 processor. */
9943 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
9945 static const struct mips_builtin_description mips_sb1_bdesc[] = {
9946 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
9949 /* Built-in functions for the DSP ASE. */
9951 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
9952 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
9953 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
9954 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
9955 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
9957 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
9958 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
9959 mips_builtin_description fields. */
9960 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9961 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9962 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
9964 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
9965 branch instruction. TARGET_FLAGS is a mips_builtin_description field. */
9966 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
9967 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
9968 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
9970 static const struct mips_builtin_description mips_dsp_bdesc[] = {
9971 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9972 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9973 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9974 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9975 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9976 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9977 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
9978 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9979 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9980 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
9981 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9982 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9983 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
9984 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
9985 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
9986 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
9987 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
9988 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
9989 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
9990 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
9991 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
9992 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
9993 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9994 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9995 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9996 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9997 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9998 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
9999 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10000 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10001 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10002 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10003 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10004 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10005 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10006 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10007 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10008 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10009 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10010 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10011 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10012 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10013 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10014 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10015 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10016 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10017 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10018 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10019 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10020 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10021 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10022 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10023 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10024 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10025 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10026 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10027 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10028 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10029 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10030 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10031 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10032 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10033 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10034 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10035 BPOSGE_BUILTIN (32, MASK_DSP),
10037 /* The following are for the MIPS DSP ASE REV 2. */
10038 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
10039 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10040 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10041 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10042 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10043 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10044 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10045 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10046 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10047 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10048 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10049 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10050 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10051 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10052 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10053 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10054 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10055 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10056 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10057 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10058 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10059 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
10060 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10061 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10062 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10063 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10064 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10065 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10066 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10067 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10068 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10069 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10070 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10071 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
10074 static const struct mips_builtin_description mips_dsp_32only_bdesc[] = {
10075 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10076 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10077 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10078 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10079 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10080 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10081 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10082 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10083 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10084 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10085 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10086 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10087 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10088 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10089 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10090 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10091 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10092 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10093 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10094 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10095 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10097 /* The following are for the MIPS DSP ASE REV 2. */
10098 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10099 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10100 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10101 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10102 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10103 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10104 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10105 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
10106 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
10107 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10108 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10109 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10110 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10111 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10112 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
10115 /* This structure describes an array of mips_builtin_description entries. */
10116 struct mips_bdesc_map {
10117 /* The array that this entry describes. */
10118 const struct mips_builtin_description *bdesc;
10120 /* The number of entries in BDESC. */
10123 /* The target processor that supports the functions in BDESC.
10124 PROCESSOR_MAX means we enable them for all processors. */
10125 enum processor_type proc;
10127 /* The functions in BDESC are not supported if any of these
10128 target flags are set. */
10129 int unsupported_target_flags;
10132 /* All MIPS-specific built-in functions. */
10133 static const struct mips_bdesc_map mips_bdesc_arrays[] = {
10134 { mips_ps_bdesc, ARRAY_SIZE (mips_ps_bdesc), PROCESSOR_MAX, 0 },
10135 { mips_sb1_bdesc, ARRAY_SIZE (mips_sb1_bdesc), PROCESSOR_SB1, 0 },
10136 { mips_dsp_bdesc, ARRAY_SIZE (mips_dsp_bdesc), PROCESSOR_MAX, 0 },
10137 { mips_dsp_32only_bdesc, ARRAY_SIZE (mips_dsp_32only_bdesc),
10138 PROCESSOR_MAX, MASK_64BIT }
10141 /* MODE is a vector mode whose elements have type TYPE. Return the type
10142 of the vector itself. */
10145 mips_builtin_vector_type (tree type, enum machine_mode mode)
10147 static tree types[(int) MAX_MACHINE_MODE];
10149 if (types[(int) mode] == NULL_TREE)
10150 types[(int) mode] = build_vector_type_for_mode (type, mode);
10151 return types[(int) mode];
10154 /* Source-level argument types. */
10155 #define MIPS_ATYPE_VOID void_type_node
10156 #define MIPS_ATYPE_INT integer_type_node
10157 #define MIPS_ATYPE_POINTER ptr_type_node
10159 /* Standard mode-based argument types. */
10160 #define MIPS_ATYPE_SI intSI_type_node
10161 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10162 #define MIPS_ATYPE_DI intDI_type_node
10163 #define MIPS_ATYPE_SF float_type_node
10164 #define MIPS_ATYPE_DF double_type_node
10166 /* Vector argument types. */
10167 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10168 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10169 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10171 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10172 their associated MIPS_ATYPEs. */
10173 #define MIPS_FTYPE_ATYPES1(A, B) \
10174 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10176 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10177 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10179 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10180 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10182 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10183 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10186 /* Return the function type associated with function prototype TYPE. */
10189 mips_build_function_type (enum mips_function_type type)
10191 static tree types[(int) MIPS_MAX_FTYPE_MAX];
10193 if (types[(int) type] == NULL_TREE)
10196 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10197 case MIPS_FTYPE_NAME##NUM ARGS: \
10198 types[(int) type] \
10199 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10202 #include "config/mips/mips-ftypes.def"
10203 #undef DEF_MIPS_FTYPE
10205 gcc_unreachable ();
10208 return types[(int) type];
10211 /* Implement TARGET_INIT_BUILTINS. */
10214 mips_init_builtins (void)
10216 const struct mips_builtin_description *d;
10217 const struct mips_bdesc_map *m;
10218 unsigned int offset;
10220 /* Iterate through all of the bdesc arrays, initializing all of the
10221 builtin functions. */
10223 for (m = mips_bdesc_arrays;
10224 m < &mips_bdesc_arrays[ARRAY_SIZE (mips_bdesc_arrays)];
10227 if ((m->proc == PROCESSOR_MAX || m->proc == mips_arch)
10228 && (m->unsupported_target_flags & target_flags) == 0)
10229 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10230 if ((d->target_flags & target_flags) == d->target_flags)
10231 add_builtin_function (d->name,
10232 mips_build_function_type (d->function_type),
10233 d - m->bdesc + offset,
10234 BUILT_IN_MD, NULL, NULL);
10239 /* Take argument ARGNO from EXP's argument list and convert it into a
10240 form suitable for input operand OPNO of instruction ICODE. Return the
10244 mips_prepare_builtin_arg (enum insn_code icode,
10245 unsigned int opno, tree exp, unsigned int argno)
10248 enum machine_mode mode;
10250 value = expand_normal (CALL_EXPR_ARG (exp, argno));
10251 mode = insn_data[icode].operand[opno].mode;
10252 if (!insn_data[icode].operand[opno].predicate (value, mode))
10254 value = copy_to_mode_reg (mode, value);
10255 /* Check the predicate again. */
10256 if (!insn_data[icode].operand[opno].predicate (value, mode))
10258 error ("invalid argument to built-in function");
10266 /* Return an rtx suitable for output operand OP of instruction ICODE.
10267 If TARGET is non-null, try to use it where possible. */
10270 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10272 enum machine_mode mode;
10274 mode = insn_data[icode].operand[op].mode;
10275 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10276 target = gen_reg_rtx (mode);
10281 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
10282 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
10283 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
10284 suggests a good place to put the result. */
10287 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
10290 rtx ops[MAX_RECOG_OPERANDS];
10293 /* Map any target to operand 0. */
10297 ops[opno] = mips_prepare_builtin_target (icode, opno, target);
10301 /* Map the arguments to the other operands. The n_operands value
10302 for an expander includes match_dups and match_scratches as well as
10303 match_operands, so n_operands is only an upper bound on the number
10304 of arguments to the expander function. */
10305 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
10306 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
10307 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
10312 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10316 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10320 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10324 gcc_unreachable ();
10329 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
10330 function; TYPE says which. EXP is the CALL_EXPR that calls the
10331 function, ICODE is the instruction that should be used to compare
10332 the first two arguments, and COND is the condition it should test.
10333 TARGET, if nonnull, suggests a good place to put the result. */
10336 mips_expand_builtin_movtf (enum mips_builtin_type type,
10337 enum insn_code icode, enum mips_fp_condition cond,
10338 rtx target, tree exp)
10340 rtx cmp_result, op0, op1;
10342 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10343 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
10344 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
10345 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10347 icode = CODE_FOR_mips_cond_move_tf_ps;
10348 target = mips_prepare_builtin_target (icode, 0, target);
10349 if (type == MIPS_BUILTIN_MOVT)
10351 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
10352 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
10356 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
10357 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
10359 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10363 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10364 into TARGET otherwise. Return TARGET. */
10367 mips_builtin_branch_and_move (rtx condition, rtx target,
10368 rtx value_if_true, rtx value_if_false)
10370 rtx true_label, done_label;
10372 true_label = gen_label_rtx ();
10373 done_label = gen_label_rtx ();
10375 /* First assume that CONDITION is false. */
10376 mips_emit_move (target, value_if_false);
10378 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10379 emit_jump_insn (gen_condjump (condition, true_label));
10380 emit_jump_insn (gen_jump (done_label));
10383 /* Fix TARGET if CONDITION is true. */
10384 emit_label (true_label);
10385 mips_emit_move (target, value_if_true);
10387 emit_label (done_label);
10391 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
10392 the CALL_EXPR that calls the function, ICODE is the code of the
10393 comparison instruction, and COND is the condition it should test.
10394 TARGET, if nonnull, suggests a good place to put the boolean result. */
10397 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10398 enum insn_code icode, enum mips_fp_condition cond,
10399 rtx target, tree exp)
10401 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
10404 if (target == 0 || GET_MODE (target) != SImode)
10405 target = gen_reg_rtx (SImode);
10407 /* The instruction should have a target operand, an operand for each
10408 argument, and an operand for COND. */
10409 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
10411 /* Prepare the operands to the comparison. */
10412 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10413 for (argno = 0; argno < call_expr_nargs (exp); argno++)
10414 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
10416 switch (insn_data[icode].n_operands)
10419 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
10424 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
10425 args[2], args[3], GEN_INT (cond)));
10429 gcc_unreachable ();
10432 /* If the comparison sets more than one register, we define the result
10433 to be 0 if all registers are false and -1 if all registers are true.
10434 The value of the complete result is indeterminate otherwise. */
10435 switch (builtin_type)
10437 case MIPS_BUILTIN_CMP_ALL:
10438 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10439 return mips_builtin_branch_and_move (condition, target,
10440 const0_rtx, const1_rtx);
10442 case MIPS_BUILTIN_CMP_UPPER:
10443 case MIPS_BUILTIN_CMP_LOWER:
10444 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10445 condition = gen_single_cc (cmp_result, offset);
10446 return mips_builtin_branch_and_move (condition, target,
10447 const1_rtx, const0_rtx);
10450 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10451 return mips_builtin_branch_and_move (condition, target,
10452 const1_rtx, const0_rtx);
10456 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
10457 if nonnull, suggests a good place to put the boolean result. */
10460 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10462 rtx condition, cmp_result;
10465 if (target == 0 || GET_MODE (target) != SImode)
10466 target = gen_reg_rtx (SImode);
10468 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10470 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10475 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10476 return mips_builtin_branch_and_move (condition, target,
10477 const1_rtx, const0_rtx);
10480 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10481 Expand the call and return an rtx for its return value.
10482 TARGET, if nonnull, suggests a good place to put this value. */
10485 mips_expand_builtin_1 (const struct mips_builtin_description *bdesc,
10486 tree exp, rtx target)
10488 switch (bdesc->builtin_type)
10490 case MIPS_BUILTIN_DIRECT:
10491 return mips_expand_builtin_direct (bdesc->icode, target, exp, true);
10493 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10494 return mips_expand_builtin_direct (bdesc->icode, target, exp, false);
10496 case MIPS_BUILTIN_MOVT:
10497 case MIPS_BUILTIN_MOVF:
10498 return mips_expand_builtin_movtf (bdesc->builtin_type, bdesc->icode,
10499 bdesc->cond, target, exp);
10501 case MIPS_BUILTIN_CMP_ANY:
10502 case MIPS_BUILTIN_CMP_ALL:
10503 case MIPS_BUILTIN_CMP_UPPER:
10504 case MIPS_BUILTIN_CMP_LOWER:
10505 case MIPS_BUILTIN_CMP_SINGLE:
10506 return mips_expand_builtin_compare (bdesc->builtin_type, bdesc->icode,
10507 bdesc->cond, target, exp);
10509 case MIPS_BUILTIN_BPOSGE32:
10510 return mips_expand_builtin_bposge (bdesc->builtin_type, target);
10512 gcc_unreachable ();
10515 /* Implement TARGET_EXPAND_BUILTIN. */
10518 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10519 enum machine_mode mode ATTRIBUTE_UNUSED,
10520 int ignore ATTRIBUTE_UNUSED)
10523 unsigned int fcode;
10524 const struct mips_bdesc_map *m;
10526 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10527 fcode = DECL_FUNCTION_CODE (fndecl);
10530 error ("built-in function %qs not supported for MIPS16",
10531 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
10535 for (m = mips_bdesc_arrays;
10536 m < &mips_bdesc_arrays[ARRAY_SIZE (mips_bdesc_arrays)];
10539 if (fcode < m->size)
10540 return mips_expand_builtin_1 (m->bdesc + fcode, exp, target);
10543 gcc_unreachable ();
10546 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
10547 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10548 struct mips16_constant {
10549 struct mips16_constant *next;
10552 enum machine_mode mode;
10555 /* Information about an incomplete MIPS16 constant pool. FIRST is the
10556 first constant, HIGHEST_ADDRESS is the highest address that the first
10557 byte of the pool can have, and INSN_ADDRESS is the current instruction
10559 struct mips16_constant_pool {
10560 struct mips16_constant *first;
10561 int highest_address;
10565 /* Add constant VALUE to POOL and return its label. MODE is the
10566 value's mode (used for CONST_INTs, etc.). */
10569 mips16_add_constant (struct mips16_constant_pool *pool,
10570 rtx value, enum machine_mode mode)
10572 struct mips16_constant **p, *c;
10573 bool first_of_size_p;
10575 /* See whether the constant is already in the pool. If so, return the
10576 existing label, otherwise leave P pointing to the place where the
10577 constant should be added.
10579 Keep the pool sorted in increasing order of mode size so that we can
10580 reduce the number of alignments needed. */
10581 first_of_size_p = true;
10582 for (p = &pool->first; *p != 0; p = &(*p)->next)
10584 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
10585 return (*p)->label;
10586 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
10588 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
10589 first_of_size_p = false;
10592 /* In the worst case, the constant needed by the earliest instruction
10593 will end up at the end of the pool. The entire pool must then be
10594 accessible from that instruction.
10596 When adding the first constant, set the pool's highest address to
10597 the address of the first out-of-range byte. Adjust this address
10598 downwards each time a new constant is added. */
10599 if (pool->first == 0)
10600 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
10601 of the instruction with the lowest two bits clear. The base PC
10602 value for LDPC has the lowest three bits clear. Assume the worst
10603 case here; namely that the PC-relative instruction occupies the
10604 last 2 bytes in an aligned word. */
10605 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
10606 pool->highest_address -= GET_MODE_SIZE (mode);
10607 if (first_of_size_p)
10608 /* Take into account the worst possible padding due to alignment. */
10609 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
10611 /* Create a new entry. */
10612 c = XNEW (struct mips16_constant);
10615 c->label = gen_label_rtx ();
10622 /* Output constant VALUE after instruction INSN and return the last
10623 instruction emitted. MODE is the mode of the constant. */
10626 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
10628 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
10630 rtx size = GEN_INT (GET_MODE_SIZE (mode));
10631 return emit_insn_after (gen_consttable_int (value, size), insn);
10634 if (SCALAR_FLOAT_MODE_P (mode))
10635 return emit_insn_after (gen_consttable_float (value), insn);
10637 if (VECTOR_MODE_P (mode))
10641 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
10642 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
10643 CONST_VECTOR_ELT (value, i), insn);
10647 gcc_unreachable ();
10650 /* Dump out the constants in CONSTANTS after INSN. */
10653 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
10655 struct mips16_constant *c, *next;
10659 for (c = constants; c != NULL; c = next)
10661 /* If necessary, increase the alignment of PC. */
10662 if (align < GET_MODE_SIZE (c->mode))
10664 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
10665 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
10667 align = GET_MODE_SIZE (c->mode);
10669 insn = emit_label_after (c->label, insn);
10670 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
10676 emit_barrier_after (insn);
10679 /* Return the length of instruction INSN. */
10682 mips16_insn_length (rtx insn)
10686 rtx body = PATTERN (insn);
10687 if (GET_CODE (body) == ADDR_VEC)
10688 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
10689 if (GET_CODE (body) == ADDR_DIFF_VEC)
10690 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
10692 return get_attr_length (insn);
10695 /* If *X is a symbolic constant that refers to the constant pool, add
10696 the constant to POOL and rewrite *X to use the constant's label. */
10699 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
10701 rtx base, offset, label;
10703 split_const (*x, &base, &offset);
10704 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
10706 label = mips16_add_constant (pool, get_pool_constant (base),
10707 get_pool_mode (base));
10708 base = gen_rtx_LABEL_REF (Pmode, label);
10709 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
10713 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10714 INSN is the instruction we're rewriting and POOL points to the current
10716 struct mips16_rewrite_pool_refs_info {
10718 struct mips16_constant_pool *pool;
10721 /* Rewrite *X so that constant pool references refer to the constant's
10722 label instead. DATA points to a mips16_rewrite_pool_refs_info
10726 mips16_rewrite_pool_refs (rtx *x, void *data)
10728 struct mips16_rewrite_pool_refs_info *info = data;
10730 if (force_to_mem_operand (*x, Pmode))
10732 rtx mem = force_const_mem (GET_MODE (*x), *x);
10733 validate_change (info->insn, x, mem, false);
10738 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
10742 if (TARGET_MIPS16_TEXT_LOADS)
10743 mips16_rewrite_pool_constant (info->pool, x);
10745 return GET_CODE (*x) == CONST ? -1 : 0;
10748 /* Build MIPS16 constant pools. */
10751 mips16_lay_out_constants (void)
10753 struct mips16_constant_pool pool;
10754 struct mips16_rewrite_pool_refs_info info;
10757 if (!TARGET_MIPS16_PCREL_LOADS)
10761 memset (&pool, 0, sizeof (pool));
10762 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10764 /* Rewrite constant pool references in INSN. */
10769 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
10772 pool.insn_address += mips16_insn_length (insn);
10774 if (pool.first != NULL)
10776 /* If there are no natural barriers between the first user of
10777 the pool and the highest acceptable address, we'll need to
10778 create a new instruction to jump around the constant pool.
10779 In the worst case, this instruction will be 4 bytes long.
10781 If it's too late to do this transformation after INSN,
10782 do it immediately before INSN. */
10783 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
10787 label = gen_label_rtx ();
10789 jump = emit_jump_insn_before (gen_jump (label), insn);
10790 JUMP_LABEL (jump) = label;
10791 LABEL_NUSES (label) = 1;
10792 barrier = emit_barrier_after (jump);
10794 emit_label_after (label, barrier);
10795 pool.insn_address += 4;
10798 /* See whether the constant pool is now out of range of the first
10799 user. If so, output the constants after the previous barrier.
10800 Note that any instructions between BARRIER and INSN (inclusive)
10801 will use negative offsets to refer to the pool. */
10802 if (pool.insn_address > pool.highest_address)
10804 mips16_emit_constants (pool.first, barrier);
10808 else if (BARRIER_P (insn))
10812 mips16_emit_constants (pool.first, get_last_insn ());
10815 /* A temporary variable used by for_each_rtx callbacks, etc. */
10816 static rtx mips_sim_insn;
10818 /* A structure representing the state of the processor pipeline.
10819 Used by the mips_sim_* family of functions. */
10821 /* The maximum number of instructions that can be issued in a cycle.
10822 (Caches mips_issue_rate.) */
10823 unsigned int issue_rate;
10825 /* The current simulation time. */
10828 /* How many more instructions can be issued in the current cycle. */
10829 unsigned int insns_left;
10831 /* LAST_SET[X].INSN is the last instruction to set register X.
10832 LAST_SET[X].TIME is the time at which that instruction was issued.
10833 INSN is null if no instruction has yet set register X. */
10837 } last_set[FIRST_PSEUDO_REGISTER];
10839 /* The pipeline's current DFA state. */
10843 /* Reset STATE to the initial simulation state. */
10846 mips_sim_reset (struct mips_sim *state)
10849 state->insns_left = state->issue_rate;
10850 memset (&state->last_set, 0, sizeof (state->last_set));
10851 state_reset (state->dfa_state);
10854 /* Initialize STATE before its first use. DFA_STATE points to an
10855 allocated but uninitialized DFA state. */
10858 mips_sim_init (struct mips_sim *state, state_t dfa_state)
10860 state->issue_rate = mips_issue_rate ();
10861 state->dfa_state = dfa_state;
10862 mips_sim_reset (state);
10865 /* Advance STATE by one clock cycle. */
10868 mips_sim_next_cycle (struct mips_sim *state)
10871 state->insns_left = state->issue_rate;
10872 state_transition (state->dfa_state, 0);
10875 /* Advance simulation state STATE until instruction INSN can read
10879 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
10881 unsigned int regno, end_regno;
10883 end_regno = END_REGNO (reg);
10884 for (regno = REGNO (reg); regno < end_regno; regno++)
10885 if (state->last_set[regno].insn != 0)
10889 t = (state->last_set[regno].time
10890 + insn_latency (state->last_set[regno].insn, insn));
10891 while (state->time < t)
10892 mips_sim_next_cycle (state);
10896 /* A for_each_rtx callback. If *X is a register, advance simulation state
10897 DATA until mips_sim_insn can read the register's value. */
10900 mips_sim_wait_regs_2 (rtx *x, void *data)
10903 mips_sim_wait_reg (data, mips_sim_insn, *x);
10907 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
10910 mips_sim_wait_regs_1 (rtx *x, void *data)
10912 for_each_rtx (x, mips_sim_wait_regs_2, data);
10915 /* Advance simulation state STATE until all of INSN's register
10916 dependencies are satisfied. */
10919 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
10921 mips_sim_insn = insn;
10922 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
10925 /* Advance simulation state STATE until the units required by
10926 instruction INSN are available. */
10929 mips_sim_wait_units (struct mips_sim *state, rtx insn)
10933 tmp_state = alloca (state_size ());
10934 while (state->insns_left == 0
10935 || (memcpy (tmp_state, state->dfa_state, state_size ()),
10936 state_transition (tmp_state, insn) >= 0))
10937 mips_sim_next_cycle (state);
10940 /* Advance simulation state STATE until INSN is ready to issue. */
10943 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
10945 mips_sim_wait_regs (state, insn);
10946 mips_sim_wait_units (state, insn);
10949 /* mips_sim_insn has just set X. Update the LAST_SET array
10950 in simulation state DATA. */
10953 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
10955 struct mips_sim *state;
10960 unsigned int regno, end_regno;
10962 end_regno = END_REGNO (x);
10963 for (regno = REGNO (x); regno < end_regno; regno++)
10965 state->last_set[regno].insn = mips_sim_insn;
10966 state->last_set[regno].time = state->time;
10971 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
10972 can issue immediately (i.e., that mips_sim_wait_insn has already
10976 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
10978 state_transition (state->dfa_state, insn);
10979 state->insns_left--;
10981 mips_sim_insn = insn;
10982 note_stores (PATTERN (insn), mips_sim_record_set, state);
10985 /* Simulate issuing a NOP in state STATE. */
10988 mips_sim_issue_nop (struct mips_sim *state)
10990 if (state->insns_left == 0)
10991 mips_sim_next_cycle (state);
10992 state->insns_left--;
10995 /* Update simulation state STATE so that it's ready to accept the instruction
10996 after INSN. INSN should be part of the main rtl chain, not a member of a
11000 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
11002 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11004 mips_sim_issue_nop (state);
11006 switch (GET_CODE (SEQ_BEGIN (insn)))
11010 /* We can't predict the processor state after a call or label. */
11011 mips_sim_reset (state);
11015 /* The delay slots of branch likely instructions are only executed
11016 when the branch is taken. Therefore, if the caller has simulated
11017 the delay slot instruction, STATE does not really reflect the state
11018 of the pipeline for the instruction after the delay slot. Also,
11019 branch likely instructions tend to incur a penalty when not taken,
11020 so there will probably be an extra delay between the branch and
11021 the instruction after the delay slot. */
11022 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
11023 mips_sim_reset (state);
11031 /* The VR4130 pipeline issues aligned pairs of instructions together,
11032 but it stalls the second instruction if it depends on the first.
11033 In order to cut down the amount of logic required, this dependence
11034 check is not based on a full instruction decode. Instead, any non-SPECIAL
11035 instruction is assumed to modify the register specified by bits 20-16
11036 (which is usually the "rt" field).
11038 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
11039 input, so we can end up with a false dependence between the branch
11040 and its delay slot. If this situation occurs in instruction INSN,
11041 try to avoid it by swapping rs and rt. */
11044 vr4130_avoid_branch_rt_conflict (rtx insn)
11048 first = SEQ_BEGIN (insn);
11049 second = SEQ_END (insn);
11051 && NONJUMP_INSN_P (second)
11052 && GET_CODE (PATTERN (first)) == SET
11053 && GET_CODE (SET_DEST (PATTERN (first))) == PC
11054 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
11056 /* Check for the right kind of condition. */
11057 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
11058 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
11059 && REG_P (XEXP (cond, 0))
11060 && REG_P (XEXP (cond, 1))
11061 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
11062 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
11064 /* SECOND mentions the rt register but not the rs register. */
11065 rtx tmp = XEXP (cond, 0);
11066 XEXP (cond, 0) = XEXP (cond, 1);
11067 XEXP (cond, 1) = tmp;
11072 /* Implement -mvr4130-align. Go through each basic block and simulate the
11073 processor pipeline. If we find that a pair of instructions could execute
11074 in parallel, and the first of those instructions is not 8-byte aligned,
11075 insert a nop to make it aligned. */
11078 vr4130_align_insns (void)
11080 struct mips_sim state;
11081 rtx insn, subinsn, last, last2, next;
11086 /* LAST is the last instruction before INSN to have a nonzero length.
11087 LAST2 is the last such instruction before LAST. */
11091 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11094 mips_sim_init (&state, alloca (state_size ()));
11095 for (insn = get_insns (); insn != 0; insn = next)
11097 unsigned int length;
11099 next = NEXT_INSN (insn);
11101 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11102 This isn't really related to the alignment pass, but we do it on
11103 the fly to avoid a separate instruction walk. */
11104 vr4130_avoid_branch_rt_conflict (insn);
11106 if (USEFUL_INSN_P (insn))
11107 FOR_EACH_SUBINSN (subinsn, insn)
11109 mips_sim_wait_insn (&state, subinsn);
11111 /* If we want this instruction to issue in parallel with the
11112 previous one, make sure that the previous instruction is
11113 aligned. There are several reasons why this isn't worthwhile
11114 when the second instruction is a call:
11116 - Calls are less likely to be performance critical,
11117 - There's a good chance that the delay slot can execute
11118 in parallel with the call.
11119 - The return address would then be unaligned.
11121 In general, if we're going to insert a nop between instructions
11122 X and Y, it's better to insert it immediately after X. That
11123 way, if the nop makes Y aligned, it will also align any labels
11124 between X and Y. */
11125 if (state.insns_left != state.issue_rate
11126 && !CALL_P (subinsn))
11128 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
11130 /* SUBINSN is the first instruction in INSN and INSN is
11131 aligned. We want to align the previous instruction
11132 instead, so insert a nop between LAST2 and LAST.
11134 Note that LAST could be either a single instruction
11135 or a branch with a delay slot. In the latter case,
11136 LAST, like INSN, is already aligned, but the delay
11137 slot must have some extra delay that stops it from
11138 issuing at the same time as the branch. We therefore
11139 insert a nop before the branch in order to align its
11141 emit_insn_after (gen_nop (), last2);
11144 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
11146 /* SUBINSN is the delay slot of INSN, but INSN is
11147 currently unaligned. Insert a nop between
11148 LAST and INSN to align it. */
11149 emit_insn_after (gen_nop (), last);
11153 mips_sim_issue_insn (&state, subinsn);
11155 mips_sim_finish_insn (&state, insn);
11157 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11158 length = get_attr_length (insn);
11161 /* If the instruction is an asm statement or multi-instruction
11162 mips.md patern, the length is only an estimate. Insert an
11163 8 byte alignment after it so that the following instructions
11164 can be handled correctly. */
11165 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
11166 && (recog_memoized (insn) < 0 || length >= 8))
11168 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
11169 next = NEXT_INSN (next);
11170 mips_sim_next_cycle (&state);
11173 else if (length & 4)
11174 aligned_p = !aligned_p;
11179 /* See whether INSN is an aligned label. */
11180 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
11186 /* Subroutine of mips_reorg. If there is a hazard between INSN
11187 and a previous instruction, avoid it by inserting nops after
11190 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11191 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11192 before using the value of that register. *HILO_DELAY counts the
11193 number of instructions since the last hilo hazard (that is,
11194 the number of instructions since the last MFLO or MFHI).
11196 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11197 for the next instruction.
11199 LO_REG is an rtx for the LO register, used in dependence checking. */
11202 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
11203 rtx *delayed_reg, rtx lo_reg)
11206 int nops, ninsns, hazard_set;
11208 if (!INSN_P (insn))
11211 pattern = PATTERN (insn);
11213 /* Do not put the whole function in .set noreorder if it contains
11214 an asm statement. We don't know whether there will be hazards
11215 between the asm statement and the gcc-generated code. */
11216 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
11217 cfun->machine->all_noreorder_p = false;
11219 /* Ignore zero-length instructions (barriers and the like). */
11220 ninsns = get_attr_length (insn) / 4;
11224 /* Work out how many nops are needed. Note that we only care about
11225 registers that are explicitly mentioned in the instruction's pattern.
11226 It doesn't matter that calls use the argument registers or that they
11227 clobber hi and lo. */
11228 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
11229 nops = 2 - *hilo_delay;
11230 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
11235 /* Insert the nops between this instruction and the previous one.
11236 Each new nop takes us further from the last hilo hazard. */
11237 *hilo_delay += nops;
11239 emit_insn_after (gen_hazard_nop (), after);
11241 /* Set up the state for the next instruction. */
11242 *hilo_delay += ninsns;
11244 if (INSN_CODE (insn) >= 0)
11245 switch (get_attr_hazard (insn))
11255 hazard_set = (int) get_attr_hazard_set (insn);
11256 if (hazard_set == 0)
11257 set = single_set (insn);
11260 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
11261 set = XVECEXP (PATTERN (insn), 0, hazard_set - 1);
11263 gcc_assert (set && GET_CODE (set) == SET);
11264 *delayed_reg = SET_DEST (set);
11269 /* Go through the instruction stream and insert nops where necessary.
11270 See if the whole function can then be put into .set noreorder &
11274 mips_avoid_hazards (void)
11276 rtx insn, last_insn, lo_reg, delayed_reg;
11279 /* Force all instructions to be split into their final form. */
11280 split_all_insns_noflow ();
11282 /* Recalculate instruction lengths without taking nops into account. */
11283 cfun->machine->ignore_hazard_length_p = true;
11284 shorten_branches (get_insns ());
11286 cfun->machine->all_noreorder_p = true;
11288 /* Profiled functions can't be all noreorder because the profiler
11289 support uses assembler macros. */
11290 if (current_function_profile)
11291 cfun->machine->all_noreorder_p = false;
11293 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11294 we rely on the assembler to work around some errata. */
11295 if (TARGET_FIX_VR4120)
11296 cfun->machine->all_noreorder_p = false;
11298 /* The same is true for -mfix-vr4130 if we might generate MFLO or
11299 MFHI instructions. Note that we avoid using MFLO and MFHI if
11300 the VR4130 MACC and DMACC instructions are available instead;
11301 see the *mfhilo_{si,di}_macc patterns. */
11302 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
11303 cfun->machine->all_noreorder_p = false;
11308 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
11310 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11313 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11314 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
11315 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
11316 &hilo_delay, &delayed_reg, lo_reg);
11318 mips_avoid_hazard (last_insn, insn, &hilo_delay,
11319 &delayed_reg, lo_reg);
11325 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11330 mips16_lay_out_constants ();
11331 if (TARGET_EXPLICIT_RELOCS)
11333 if (mips_base_delayed_branch)
11334 dbr_schedule (get_insns ());
11335 mips_avoid_hazards ();
11336 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
11337 vr4130_align_insns ();
11341 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11342 in order to avoid duplicating too much logic from elsewhere. */
11345 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11346 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11349 rtx this, temp1, temp2, insn, fnaddr;
11350 bool use_sibcall_p;
11352 /* Pretend to be a post-reload pass while generating rtl. */
11353 reload_completed = 1;
11355 /* Mark the end of the (empty) prologue. */
11356 emit_note (NOTE_INSN_PROLOGUE_END);
11358 /* Determine if we can use a sibcall to call FUNCTION directly. */
11359 fnaddr = XEXP (DECL_RTL (function), 0);
11360 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
11361 && const_call_insn_operand (fnaddr, Pmode));
11363 /* Determine if we need to load FNADDR from the GOT. */
11364 if (!use_sibcall_p)
11365 switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
11367 case SYMBOL_GOT_PAGE_OFST:
11368 case SYMBOL_GOT_DISP:
11369 /* Pick a global pointer. Use a call-clobbered register if
11370 TARGET_CALL_SAVED_GP. */
11371 cfun->machine->global_pointer =
11372 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
11373 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11375 /* Set up the global pointer for n32 or n64 abicalls. */
11376 mips_emit_loadgp ();
11383 /* We need two temporary registers in some cases. */
11384 temp1 = gen_rtx_REG (Pmode, 2);
11385 temp2 = gen_rtx_REG (Pmode, 3);
11387 /* Find out which register contains the "this" pointer. */
11388 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11389 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
11391 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
11393 /* Add DELTA to THIS. */
11396 rtx offset = GEN_INT (delta);
11397 if (!SMALL_OPERAND (delta))
11399 mips_emit_move (temp1, offset);
11402 emit_insn (gen_add3_insn (this, this, offset));
11405 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11406 if (vcall_offset != 0)
11410 /* Set TEMP1 to *THIS. */
11411 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
11413 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11414 addr = mips_add_offset (temp2, temp1, vcall_offset);
11416 /* Load the offset and add it to THIS. */
11417 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
11418 emit_insn (gen_add3_insn (this, this, temp1));
11421 /* Jump to the target function. Use a sibcall if direct jumps are
11422 allowed, otherwise load the address into a register first. */
11425 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
11426 SIBLING_CALL_P (insn) = 1;
11430 /* This is messy. GAS treats "la $25,foo" as part of a call
11431 sequence and may allow a global "foo" to be lazily bound.
11432 The general move patterns therefore reject this combination.
11434 In this context, lazy binding would actually be OK
11435 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11436 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11437 We must therefore load the address via a temporary
11438 register if mips_dangerous_for_la25_p.
11440 If we jump to the temporary register rather than $25, the assembler
11441 can use the move insn to fill the jump's delay slot. */
11442 if (TARGET_USE_PIC_FN_ADDR_REG
11443 && !mips_dangerous_for_la25_p (fnaddr))
11444 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11445 mips_load_call_address (temp1, fnaddr, true);
11447 if (TARGET_USE_PIC_FN_ADDR_REG
11448 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
11449 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
11450 emit_jump_insn (gen_indirect_jump (temp1));
11453 /* Run just enough of rest_of_compilation. This sequence was
11454 "borrowed" from alpha.c. */
11455 insn = get_insns ();
11456 insn_locators_alloc ();
11457 split_all_insns_noflow ();
11458 mips16_lay_out_constants ();
11459 shorten_branches (insn);
11460 final_start_function (insn, file, 1);
11461 final (insn, file, 1);
11462 final_end_function ();
11464 /* Clean up the vars set above. Note that final_end_function resets
11465 the global pointer for us. */
11466 reload_completed = 0;
11469 /* The last argument passed to mips_set_mips16_mode, or negative if the
11470 function hasn't been called yet. */
11471 static GTY(()) int was_mips16_p = -1;
11473 /* Set up the target-dependent global state so that it matches the
11474 current function's ISA mode. */
11477 mips_set_mips16_mode (int mips16_p)
11479 if (mips16_p == was_mips16_p)
11482 /* Restore base settings of various flags. */
11483 target_flags = mips_base_target_flags;
11484 flag_delayed_branch = mips_base_delayed_branch;
11485 flag_schedule_insns = mips_base_schedule_insns;
11486 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
11487 flag_move_loop_invariants = mips_base_move_loop_invariants;
11488 align_loops = mips_base_align_loops;
11489 align_jumps = mips_base_align_jumps;
11490 align_functions = mips_base_align_functions;
11494 /* Switch to MIPS16 mode. */
11495 target_flags |= MASK_MIPS16;
11497 /* Don't run the scheduler before reload, since it tends to
11498 increase register pressure. */
11499 flag_schedule_insns = 0;
11501 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
11502 the whole function to be in a single section. */
11503 flag_reorder_blocks_and_partition = 0;
11505 /* Don't move loop invariants, because it tends to increase
11506 register pressure. It also introduces an extra move in cases
11507 where the constant is the first operand in a two-operand binary
11508 instruction, or when it forms a register argument to a functon
11510 flag_move_loop_invariants = 0;
11512 /* Silently disable -mexplicit-relocs since it doesn't apply
11513 to MIPS16 code. Even so, it would overly pedantic to warn
11514 about "-mips16 -mexplicit-relocs", especially given that
11515 we use a %gprel() operator. */
11516 target_flags &= ~MASK_EXPLICIT_RELOCS;
11518 /* Experiments suggest we get the best overall section-anchor
11519 results from using the range of an unextended LW or SW. Code
11520 that makes heavy use of byte or short accesses can do better
11521 with ranges of 0...31 and 0...63 respectively, but most code is
11522 sensitive to the range of LW and SW instead. */
11523 targetm.min_anchor_offset = 0;
11524 targetm.max_anchor_offset = 127;
11526 if (flag_pic || TARGET_ABICALLS)
11527 sorry ("MIPS16 PIC");
11529 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
11530 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
11534 /* Switch to normal (non-MIPS16) mode. */
11535 target_flags &= ~MASK_MIPS16;
11537 /* When using explicit relocs, we call dbr_schedule from within
11539 if (TARGET_EXPLICIT_RELOCS)
11540 flag_delayed_branch = 0;
11542 /* Provide default values for align_* for 64-bit targets. */
11545 if (align_loops == 0)
11547 if (align_jumps == 0)
11549 if (align_functions == 0)
11550 align_functions = 8;
11553 targetm.min_anchor_offset = -32768;
11554 targetm.max_anchor_offset = 32767;
11557 /* (Re)initialize MIPS target internals for new ISA. */
11558 mips_init_relocs ();
11560 if (was_mips16_p >= 0)
11561 /* Reinitialize target-dependent state. */
11564 was_mips16_p = mips16_p;
11567 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11568 function should use the MIPS16 ISA and switch modes accordingly. */
11571 mips_set_current_function (tree fndecl)
11573 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
11576 /* Allocate a chunk of memory for per-function machine-dependent data. */
11578 static struct machine_function *
11579 mips_init_machine_status (void)
11581 return ((struct machine_function *)
11582 ggc_alloc_cleared (sizeof (struct machine_function)));
11585 /* Return the processor associated with the given ISA level, or null
11586 if the ISA isn't valid. */
11588 static const struct mips_cpu_info *
11589 mips_cpu_info_from_isa (int isa)
11593 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11594 if (mips_cpu_info_table[i].isa == isa)
11595 return mips_cpu_info_table + i;
11600 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11601 with a final "000" replaced by "k". Ignore case.
11603 Note: this function is shared between GCC and GAS. */
11606 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
11608 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
11609 given++, canonical++;
11611 return ((*given == 0 && *canonical == 0)
11612 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
11615 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11616 CPU name. We've traditionally allowed a lot of variation here.
11618 Note: this function is shared between GCC and GAS. */
11621 mips_matching_cpu_name_p (const char *canonical, const char *given)
11623 /* First see if the name matches exactly, or with a final "000"
11624 turned into "k". */
11625 if (mips_strict_matching_cpu_name_p (canonical, given))
11628 /* If not, try comparing based on numerical designation alone.
11629 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11630 if (TOLOWER (*given) == 'r')
11632 if (!ISDIGIT (*given))
11635 /* Skip over some well-known prefixes in the canonical name,
11636 hoping to find a number there too. */
11637 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
11639 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
11641 else if (TOLOWER (canonical[0]) == 'r')
11644 return mips_strict_matching_cpu_name_p (canonical, given);
11647 /* Return the mips_cpu_info entry for the processor or ISA given
11648 by CPU_STRING. Return null if the string isn't recognized.
11650 A similar function exists in GAS. */
11652 static const struct mips_cpu_info *
11653 mips_parse_cpu (const char *cpu_string)
11658 /* In the past, we allowed upper-case CPU names, but it doesn't
11659 work well with the multilib machinery. */
11660 for (s = cpu_string; *s != 0; s++)
11663 warning (0, "CPU names must be lower case");
11667 /* 'from-abi' selects the most compatible architecture for the given
11668 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
11669 EABIs, we have to decide whether we're using the 32-bit or 64-bit
11671 if (strcasecmp (cpu_string, "from-abi") == 0)
11672 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
11673 : ABI_NEEDS_64BIT_REGS ? 3
11674 : (TARGET_64BIT ? 3 : 1));
11676 /* 'default' has traditionally been a no-op. Probably not very useful. */
11677 if (strcasecmp (cpu_string, "default") == 0)
11680 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11681 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
11682 return mips_cpu_info_table + i;
11687 /* Set up globals to generate code for the ISA or processor
11688 described by INFO. */
11691 mips_set_architecture (const struct mips_cpu_info *info)
11695 mips_arch_info = info;
11696 mips_arch = info->cpu;
11697 mips_isa = info->isa;
11701 /* Likewise for tuning. */
11704 mips_set_tune (const struct mips_cpu_info *info)
11708 mips_tune_info = info;
11709 mips_tune = info->cpu;
11713 /* Implement TARGET_HANDLE_OPTION. */
11716 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
11721 if (strcmp (arg, "32") == 0)
11723 else if (strcmp (arg, "o64") == 0)
11724 mips_abi = ABI_O64;
11725 else if (strcmp (arg, "n32") == 0)
11726 mips_abi = ABI_N32;
11727 else if (strcmp (arg, "64") == 0)
11729 else if (strcmp (arg, "eabi") == 0)
11730 mips_abi = ABI_EABI;
11737 return mips_parse_cpu (arg) != 0;
11740 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
11741 return mips_isa_option_info != 0;
11743 case OPT_mno_flush_func:
11744 mips_cache_flush_func = NULL;
11747 case OPT_mcode_readable_:
11748 if (strcmp (arg, "yes") == 0)
11749 mips_code_readable = CODE_READABLE_YES;
11750 else if (strcmp (arg, "pcrel") == 0)
11751 mips_code_readable = CODE_READABLE_PCREL;
11752 else if (strcmp (arg, "no") == 0)
11753 mips_code_readable = CODE_READABLE_NO;
11763 /* Implement OVERRIDE_OPTIONS. */
11766 mips_override_options (void)
11768 int i, start, regno, mode;
11770 #ifdef SUBTARGET_OVERRIDE_OPTIONS
11771 SUBTARGET_OVERRIDE_OPTIONS;
11774 /* Set the small data limit. */
11775 mips_small_data_threshold = (g_switch_set
11777 : MIPS_DEFAULT_GVALUE);
11779 /* The following code determines the architecture and register size.
11780 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
11781 The GAS and GCC code should be kept in sync as much as possible. */
11783 if (mips_arch_string != 0)
11784 mips_set_architecture (mips_parse_cpu (mips_arch_string));
11786 if (mips_isa_option_info != 0)
11788 if (mips_arch_info == 0)
11789 mips_set_architecture (mips_isa_option_info);
11790 else if (mips_arch_info->isa != mips_isa_option_info->isa)
11791 error ("%<-%s%> conflicts with the other architecture options, "
11792 "which specify a %s processor",
11793 mips_isa_option_info->name,
11794 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
11797 if (mips_arch_info == 0)
11799 #ifdef MIPS_CPU_STRING_DEFAULT
11800 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
11802 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
11806 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
11807 error ("%<-march=%s%> is not compatible with the selected ABI",
11808 mips_arch_info->name);
11810 /* Optimize for mips_arch, unless -mtune selects a different processor. */
11811 if (mips_tune_string != 0)
11812 mips_set_tune (mips_parse_cpu (mips_tune_string));
11814 if (mips_tune_info == 0)
11815 mips_set_tune (mips_arch_info);
11817 if ((target_flags_explicit & MASK_64BIT) != 0)
11819 /* The user specified the size of the integer registers. Make sure
11820 it agrees with the ABI and ISA. */
11821 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
11822 error ("%<-mgp64%> used with a 32-bit processor");
11823 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
11824 error ("%<-mgp32%> used with a 64-bit ABI");
11825 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
11826 error ("%<-mgp64%> used with a 32-bit ABI");
11830 /* Infer the integer register size from the ABI and processor.
11831 Restrict ourselves to 32-bit registers if that's all the
11832 processor has, or if the ABI cannot handle 64-bit registers. */
11833 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
11834 target_flags &= ~MASK_64BIT;
11836 target_flags |= MASK_64BIT;
11839 if ((target_flags_explicit & MASK_FLOAT64) != 0)
11841 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
11842 error ("unsupported combination: %s", "-mfp64 -msingle-float");
11843 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
11844 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
11845 else if (!TARGET_64BIT && TARGET_FLOAT64)
11847 if (!ISA_HAS_MXHC1)
11848 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
11849 " the target supports the mfhc1 and mthc1 instructions");
11850 else if (mips_abi != ABI_32)
11851 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
11857 /* -msingle-float selects 32-bit float registers. Otherwise the
11858 float registers should be the same size as the integer ones. */
11859 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
11860 target_flags |= MASK_FLOAT64;
11862 target_flags &= ~MASK_FLOAT64;
11865 /* End of code shared with GAS. */
11867 /* If no -mlong* option was given, infer it from the other options. */
11868 if ((target_flags_explicit & MASK_LONG64) == 0)
11870 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
11871 target_flags |= MASK_LONG64;
11873 target_flags &= ~MASK_LONG64;
11876 if (!TARGET_OLDABI)
11877 flag_pcc_struct_return = 0;
11879 /* Decide which rtx_costs structure to use. */
11881 mips_cost = &mips_rtx_cost_optimize_size;
11883 mips_cost = &mips_rtx_cost_data[mips_tune];
11885 /* If the user hasn't specified a branch cost, use the processor's
11887 if (mips_branch_cost == 0)
11888 mips_branch_cost = mips_cost->branch_cost;
11890 /* If neither -mbranch-likely nor -mno-branch-likely was given
11891 on the command line, set MASK_BRANCHLIKELY based on the target
11892 architecture and tuning flags. Annulled delay slots are a
11893 size win, so we only consider the processor-specific tuning
11894 for !optimize_size. */
11895 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
11897 if (ISA_HAS_BRANCHLIKELY
11899 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
11900 target_flags |= MASK_BRANCHLIKELY;
11902 target_flags &= ~MASK_BRANCHLIKELY;
11904 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
11905 warning (0, "the %qs architecture does not support branch-likely"
11906 " instructions", mips_arch_info->name);
11908 /* The effect of -mabicalls isn't defined for the EABI. */
11909 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
11911 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
11912 target_flags &= ~MASK_ABICALLS;
11915 /* MIPS16 cannot generate PIC yet. */
11916 if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
11918 sorry ("MIPS16 PIC");
11919 target_flags &= ~MASK_ABICALLS;
11920 flag_pic = flag_pie = flag_shlib = 0;
11923 if (TARGET_ABICALLS)
11924 /* We need to set flag_pic for executables as well as DSOs
11925 because we may reference symbols that are not defined in
11926 the final executable. (MIPS does not use things like
11927 copy relocs, for example.)
11929 Also, there is a body of code that uses __PIC__ to distinguish
11930 between -mabicalls and -mno-abicalls code. */
11933 /* -mvr4130-align is a "speed over size" optimization: it usually produces
11934 faster code, but at the expense of more nops. Enable it at -O3 and
11936 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
11937 target_flags |= MASK_VR4130_ALIGN;
11939 /* Prefer a call to memcpy over inline code when optimizing for size,
11940 though see MOVE_RATIO in mips.h. */
11941 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
11942 target_flags |= MASK_MEMCPY;
11944 /* If we have a nonzero small-data limit, check that the -mgpopt
11945 setting is consistent with the other target flags. */
11946 if (mips_small_data_threshold > 0)
11950 if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
11951 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
11953 TARGET_LOCAL_SDATA = false;
11954 TARGET_EXTERN_SDATA = false;
11958 if (TARGET_VXWORKS_RTP)
11959 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
11961 if (TARGET_ABICALLS)
11962 warning (0, "cannot use small-data accesses for %qs",
11967 #ifdef MIPS_TFMODE_FORMAT
11968 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
11971 /* Make sure that the user didn't turn off paired single support when
11972 MIPS-3D support is requested. */
11974 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
11975 && !TARGET_PAIRED_SINGLE_FLOAT)
11976 error ("%<-mips3d%> requires %<-mpaired-single%>");
11978 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
11980 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
11982 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
11983 and TARGET_HARD_FLOAT_ABI are both true. */
11984 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
11985 error ("%qs must be used with %qs",
11986 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
11987 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
11989 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
11991 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
11992 warning (0, "the %qs architecture does not support paired-single"
11993 " instructions", mips_arch_info->name);
11995 /* If TARGET_DSPR2, enable MASK_DSP. */
11997 target_flags |= MASK_DSP;
11999 mips_init_print_operand_punct ();
12001 /* Set up array to map GCC register number to debug register number.
12002 Ignore the special purpose register numbers. */
12004 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12006 mips_dbx_regno[i] = INVALID_REGNUM;
12007 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
12008 mips_dwarf_regno[i] = i;
12010 mips_dwarf_regno[i] = INVALID_REGNUM;
12013 start = GP_DBX_FIRST - GP_REG_FIRST;
12014 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
12015 mips_dbx_regno[i] = i + start;
12017 start = FP_DBX_FIRST - FP_REG_FIRST;
12018 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
12019 mips_dbx_regno[i] = i + start;
12021 /* Accumulator debug registers use big-endian ordering. */
12022 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
12023 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
12024 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
12025 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
12026 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
12028 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
12029 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
12032 /* Set up mips_hard_regno_mode_ok. */
12033 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
12034 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12035 mips_hard_regno_mode_ok[(int)mode][regno]
12036 = mips_hard_regno_mode_ok_p (regno, mode);
12038 /* Function to allocate machine-dependent function status. */
12039 init_machine_status = &mips_init_machine_status;
12041 /* Default to working around R4000 errata only if the processor
12042 was selected explicitly. */
12043 if ((target_flags_explicit & MASK_FIX_R4000) == 0
12044 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
12045 target_flags |= MASK_FIX_R4000;
12047 /* Default to working around R4400 errata only if the processor
12048 was selected explicitly. */
12049 if ((target_flags_explicit & MASK_FIX_R4400) == 0
12050 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
12051 target_flags |= MASK_FIX_R4400;
12053 /* Save base state of options. */
12054 mips_base_mips16 = TARGET_MIPS16;
12055 mips_base_target_flags = target_flags;
12056 mips_base_delayed_branch = flag_delayed_branch;
12057 mips_base_schedule_insns = flag_schedule_insns;
12058 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
12059 mips_base_move_loop_invariants = flag_move_loop_invariants;
12060 mips_base_align_loops = align_loops;
12061 mips_base_align_jumps = align_jumps;
12062 mips_base_align_functions = align_functions;
12064 /* Now select the ISA mode. */
12065 mips_set_mips16_mode (mips_base_mips16);
12068 /* Swap the register information for registers I and I + 1, which
12069 currently have the wrong endianness. Note that the registers'
12070 fixedness and call-clobberedness might have been set on the
12074 mips_swap_registers (unsigned int i)
12079 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12080 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12082 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
12083 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
12084 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
12085 SWAP_STRING (reg_names[i], reg_names[i + 1]);
12091 /* Implement CONDITIONAL_REGISTER_USAGE. */
12094 mips_conditional_register_usage (void)
12100 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
12101 fixed_regs[regno] = call_used_regs[regno] = 1;
12103 if (!TARGET_HARD_FLOAT)
12107 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
12108 fixed_regs[regno] = call_used_regs[regno] = 1;
12109 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12110 fixed_regs[regno] = call_used_regs[regno] = 1;
12112 else if (! ISA_HAS_8CC)
12116 /* We only have a single condition-code register. We implement
12117 this by fixing all the condition-code registers and generating
12118 RTL that refers directly to ST_REG_FIRST. */
12119 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12120 fixed_regs[regno] = call_used_regs[regno] = 1;
12122 /* In MIPS16 mode, we permit the $t temporary registers to be used
12123 for reload. We prohibit the unused $s registers, since they
12124 are call-saved, and saving them via a MIPS16 register would
12125 probably waste more time than just reloading the value. */
12128 fixed_regs[18] = call_used_regs[18] = 1;
12129 fixed_regs[19] = call_used_regs[19] = 1;
12130 fixed_regs[20] = call_used_regs[20] = 1;
12131 fixed_regs[21] = call_used_regs[21] = 1;
12132 fixed_regs[22] = call_used_regs[22] = 1;
12133 fixed_regs[23] = call_used_regs[23] = 1;
12134 fixed_regs[26] = call_used_regs[26] = 1;
12135 fixed_regs[27] = call_used_regs[27] = 1;
12136 fixed_regs[30] = call_used_regs[30] = 1;
12138 /* $f20-$f23 are call-clobbered for n64. */
12139 if (mips_abi == ABI_64)
12142 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
12143 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12145 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
12147 if (mips_abi == ABI_N32)
12150 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
12151 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12153 /* Make sure that double-register accumulator values are correctly
12154 ordered for the current endianness. */
12155 if (TARGET_LITTLE_ENDIAN)
12157 unsigned int regno;
12159 mips_swap_registers (MD_REG_FIRST);
12160 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
12161 mips_swap_registers (regno);
12165 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
12166 other registers for instructions for which it is possible. This
12167 encourages the compiler to use CMP in cases where an XOR would
12168 require some register shuffling. */
12171 mips_order_regs_for_local_alloc (void)
12175 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12176 reg_alloc_order[i] = i;
12180 /* It really doesn't matter where we put register 0, since it is
12181 a fixed register anyhow. */
12182 reg_alloc_order[0] = 24;
12183 reg_alloc_order[24] = 0;
12187 /* Initialize the GCC target structure. */
12188 #undef TARGET_ASM_ALIGNED_HI_OP
12189 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12190 #undef TARGET_ASM_ALIGNED_SI_OP
12191 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12192 #undef TARGET_ASM_ALIGNED_DI_OP
12193 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12195 #undef TARGET_ASM_FUNCTION_PROLOGUE
12196 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12197 #undef TARGET_ASM_FUNCTION_EPILOGUE
12198 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12199 #undef TARGET_ASM_SELECT_RTX_SECTION
12200 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12201 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12202 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12204 #undef TARGET_SCHED_INIT
12205 #define TARGET_SCHED_INIT mips_sched_init
12206 #undef TARGET_SCHED_REORDER
12207 #define TARGET_SCHED_REORDER mips_sched_reorder
12208 #undef TARGET_SCHED_REORDER2
12209 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12210 #undef TARGET_SCHED_VARIABLE_ISSUE
12211 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12212 #undef TARGET_SCHED_ADJUST_COST
12213 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12214 #undef TARGET_SCHED_ISSUE_RATE
12215 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12216 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12217 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12218 mips_multipass_dfa_lookahead
12220 #undef TARGET_DEFAULT_TARGET_FLAGS
12221 #define TARGET_DEFAULT_TARGET_FLAGS \
12223 | TARGET_CPU_DEFAULT \
12224 | TARGET_ENDIAN_DEFAULT \
12225 | TARGET_FP_EXCEPTIONS_DEFAULT \
12226 | MASK_CHECK_ZERO_DIV \
12228 #undef TARGET_HANDLE_OPTION
12229 #define TARGET_HANDLE_OPTION mips_handle_option
12231 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12232 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12234 #undef TARGET_INSERT_ATTRIBUTES
12235 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12236 #undef TARGET_MERGE_DECL_ATTRIBUTES
12237 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12238 #undef TARGET_SET_CURRENT_FUNCTION
12239 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12241 #undef TARGET_VALID_POINTER_MODE
12242 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12243 #undef TARGET_RTX_COSTS
12244 #define TARGET_RTX_COSTS mips_rtx_costs
12245 #undef TARGET_ADDRESS_COST
12246 #define TARGET_ADDRESS_COST mips_address_cost
12248 #undef TARGET_IN_SMALL_DATA_P
12249 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12251 #undef TARGET_MACHINE_DEPENDENT_REORG
12252 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12254 #undef TARGET_ASM_FILE_START
12255 #define TARGET_ASM_FILE_START mips_file_start
12256 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12257 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12259 #undef TARGET_INIT_LIBFUNCS
12260 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12262 #undef TARGET_BUILD_BUILTIN_VA_LIST
12263 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12264 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12265 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12267 #undef TARGET_PROMOTE_FUNCTION_ARGS
12268 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12269 #undef TARGET_PROMOTE_FUNCTION_RETURN
12270 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12271 #undef TARGET_PROMOTE_PROTOTYPES
12272 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12274 #undef TARGET_RETURN_IN_MEMORY
12275 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12276 #undef TARGET_RETURN_IN_MSB
12277 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12279 #undef TARGET_ASM_OUTPUT_MI_THUNK
12280 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12281 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12282 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12284 #undef TARGET_SETUP_INCOMING_VARARGS
12285 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12286 #undef TARGET_STRICT_ARGUMENT_NAMING
12287 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12288 #undef TARGET_MUST_PASS_IN_STACK
12289 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12290 #undef TARGET_PASS_BY_REFERENCE
12291 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12292 #undef TARGET_CALLEE_COPIES
12293 #define TARGET_CALLEE_COPIES mips_callee_copies
12294 #undef TARGET_ARG_PARTIAL_BYTES
12295 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12297 #undef TARGET_MODE_REP_EXTENDED
12298 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12300 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12301 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12303 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12304 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12306 #undef TARGET_INIT_BUILTINS
12307 #define TARGET_INIT_BUILTINS mips_init_builtins
12308 #undef TARGET_EXPAND_BUILTIN
12309 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12311 #undef TARGET_HAVE_TLS
12312 #define TARGET_HAVE_TLS HAVE_AS_TLS
12314 #undef TARGET_CANNOT_FORCE_CONST_MEM
12315 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12317 #undef TARGET_ENCODE_SECTION_INFO
12318 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12320 #undef TARGET_ATTRIBUTE_TABLE
12321 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12322 /* All our function attributes are related to how out-of-line copies should
12323 be compiled or called. They don't in themselves prevent inlining. */
12324 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12325 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12327 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12328 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12330 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12331 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12332 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12333 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12335 #undef TARGET_COMP_TYPE_ATTRIBUTES
12336 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12338 #ifdef HAVE_AS_DTPRELWORD
12339 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12340 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12342 #undef TARGET_DWARF_REGISTER_SPAN
12343 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12345 struct gcc_target targetm = TARGET_INITIALIZER;
12347 #include "gt-mips.h"