1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING. If not, write to
24 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
29 #include "coretypes.h"
34 #include "hard-reg-set.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
59 #include "tree-gimple.h"
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type {
150 /* Classifies the prototype of a builtin function. */
151 enum mips_function_type
153 MIPS_V2SF_FTYPE_V2SF,
154 MIPS_V2SF_FTYPE_V2SF_V2SF,
155 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
156 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
157 MIPS_V2SF_FTYPE_SF_SF,
158 MIPS_INT_FTYPE_V2SF_V2SF,
159 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
160 MIPS_INT_FTYPE_SF_SF,
161 MIPS_INT_FTYPE_DF_DF,
168 /* For MIPS DSP ASE */
170 MIPS_DI_FTYPE_DI_SI_SI,
171 MIPS_DI_FTYPE_DI_V2HI_V2HI,
172 MIPS_DI_FTYPE_DI_V4QI_V4QI,
174 MIPS_SI_FTYPE_PTR_SI,
178 MIPS_SI_FTYPE_V2HI_V2HI,
180 MIPS_SI_FTYPE_V4QI_V4QI,
183 MIPS_V2HI_FTYPE_SI_SI,
184 MIPS_V2HI_FTYPE_V2HI,
185 MIPS_V2HI_FTYPE_V2HI_SI,
186 MIPS_V2HI_FTYPE_V2HI_V2HI,
187 MIPS_V2HI_FTYPE_V4QI,
188 MIPS_V2HI_FTYPE_V4QI_V2HI,
190 MIPS_V4QI_FTYPE_V2HI_V2HI,
191 MIPS_V4QI_FTYPE_V4QI_SI,
192 MIPS_V4QI_FTYPE_V4QI_V4QI,
193 MIPS_VOID_FTYPE_SI_SI,
194 MIPS_VOID_FTYPE_V2HI_V2HI,
195 MIPS_VOID_FTYPE_V4QI_V4QI,
197 /* For MIPS DSP REV 2 ASE. */
198 MIPS_V4QI_FTYPE_V4QI,
199 MIPS_SI_FTYPE_SI_SI_SI,
200 MIPS_DI_FTYPE_DI_USI_USI,
202 MIPS_DI_FTYPE_USI_USI,
203 MIPS_V2HI_FTYPE_SI_SI_SI,
209 /* Specifies how a builtin function should be converted into rtl. */
210 enum mips_builtin_type
212 /* The builtin corresponds directly to an .md pattern. The return
213 value is mapped to operand 0 and the arguments are mapped to
214 operands 1 and above. */
217 /* The builtin corresponds directly to an .md pattern. There is no return
218 value and the arguments are mapped to operands 0 and above. */
219 MIPS_BUILTIN_DIRECT_NO_TARGET,
221 /* The builtin corresponds to a comparison instruction followed by
222 a mips_cond_move_tf_ps pattern. The first two arguments are the
223 values to compare and the second two arguments are the vector
224 operands for the movt.ps or movf.ps instruction (in assembly order). */
228 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
229 of this instruction is the result of the comparison, which has mode
230 CCV2 or CCV4. The function arguments are mapped to operands 1 and
231 above. The function's return value is an SImode boolean that is
232 true under the following conditions:
234 MIPS_BUILTIN_CMP_ANY: one of the registers is true
235 MIPS_BUILTIN_CMP_ALL: all of the registers are true
236 MIPS_BUILTIN_CMP_LOWER: the first register is true
237 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
238 MIPS_BUILTIN_CMP_ANY,
239 MIPS_BUILTIN_CMP_ALL,
240 MIPS_BUILTIN_CMP_UPPER,
241 MIPS_BUILTIN_CMP_LOWER,
243 /* As above, but the instruction only sets a single $fcc register. */
244 MIPS_BUILTIN_CMP_SINGLE,
246 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
247 MIPS_BUILTIN_BPOSGE32
250 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
251 #define MIPS_FP_CONDITIONS(MACRO) \
269 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
270 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
271 enum mips_fp_condition {
272 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
275 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
276 #define STRINGIFY(X) #X
277 static const char *const mips_fp_conditions[] = {
278 MIPS_FP_CONDITIONS (STRINGIFY)
281 /* A function to save or store a register. The first argument is the
282 register and the second is the stack slot. */
283 typedef void (*mips_save_restore_fn) (rtx, rtx);
285 struct mips16_constant;
286 struct mips_arg_info;
287 struct mips_address_info;
288 struct mips_integer_op;
291 static enum mips_symbol_type mips_classify_symbol (rtx);
292 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
293 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
294 static bool mips_classify_address (struct mips_address_info *, rtx,
295 enum machine_mode, int);
296 static bool mips_cannot_force_const_mem (rtx);
297 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
298 static int mips_symbol_insns (enum mips_symbol_type);
299 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
300 static rtx mips_force_temporary (rtx, rtx);
301 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
302 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
303 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
304 static unsigned int mips_build_lower (struct mips_integer_op *,
305 unsigned HOST_WIDE_INT);
306 static unsigned int mips_build_integer (struct mips_integer_op *,
307 unsigned HOST_WIDE_INT);
308 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
309 static int m16_check_op (rtx, int, int, int);
310 static bool mips_rtx_costs (rtx, int, int, int *);
311 static int mips_address_cost (rtx);
312 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
313 static void mips_load_call_address (rtx, rtx, int);
314 static bool mips_function_ok_for_sibcall (tree, tree);
315 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
316 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
317 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
318 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
319 tree, int, struct mips_arg_info *);
320 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
321 static void mips_set_architecture (const struct mips_cpu_info *);
322 static void mips_set_tune (const struct mips_cpu_info *);
323 static bool mips_handle_option (size_t, const char *, int);
324 static struct machine_function *mips_init_machine_status (void);
325 static void print_operand_reloc (FILE *, rtx, const char **);
326 static void mips_file_start (void);
327 static bool mips_rewrite_small_data_p (rtx);
328 static int mips_small_data_pattern_1 (rtx *, void *);
329 static int mips_rewrite_small_data_1 (rtx *, void *);
330 static bool mips_function_has_gp_insn (void);
331 static unsigned int mips_global_pointer (void);
332 static bool mips_save_reg_p (unsigned int);
333 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
334 mips_save_restore_fn);
335 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
336 static void mips_output_cplocal (void);
337 static void mips_emit_loadgp (void);
338 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
339 static void mips_set_frame_expr (rtx);
340 static rtx mips_frame_set (rtx, rtx);
341 static void mips_save_reg (rtx, rtx);
342 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
343 static void mips_restore_reg (rtx, rtx);
344 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
345 HOST_WIDE_INT, tree);
346 static int symbolic_expression_p (rtx);
347 static section *mips_select_rtx_section (enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT);
349 static section *mips_function_rodata_section (tree);
350 static bool mips_in_small_data_p (tree);
351 static bool mips_use_anchors_for_symbol_p (rtx);
352 static int mips_fpr_return_fields (tree, tree *);
353 static bool mips_return_in_msb (tree);
354 static rtx mips_return_fpr_pair (enum machine_mode mode,
355 enum machine_mode mode1, HOST_WIDE_INT,
356 enum machine_mode mode2, HOST_WIDE_INT);
357 static rtx mips16_gp_pseudo_reg (void);
358 static void mips16_fp_args (FILE *, int, int);
359 static void build_mips16_function_stub (FILE *);
360 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
361 static void dump_constants (struct mips16_constant *, rtx);
362 static int mips16_insn_length (rtx);
363 static int mips16_rewrite_pool_refs (rtx *, void *);
364 static void mips16_lay_out_constants (void);
365 static void mips_sim_reset (struct mips_sim *);
366 static void mips_sim_init (struct mips_sim *, state_t);
367 static void mips_sim_next_cycle (struct mips_sim *);
368 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
369 static int mips_sim_wait_regs_2 (rtx *, void *);
370 static void mips_sim_wait_regs_1 (rtx *, void *);
371 static void mips_sim_wait_regs (struct mips_sim *, rtx);
372 static void mips_sim_wait_units (struct mips_sim *, rtx);
373 static void mips_sim_wait_insn (struct mips_sim *, rtx);
374 static void mips_sim_record_set (rtx, rtx, void *);
375 static void mips_sim_issue_insn (struct mips_sim *, rtx);
376 static void mips_sim_issue_nop (struct mips_sim *);
377 static void mips_sim_finish_insn (struct mips_sim *, rtx);
378 static void vr4130_avoid_branch_rt_conflict (rtx);
379 static void vr4130_align_insns (void);
380 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
381 static void mips_avoid_hazards (void);
382 static void mips_reorg (void);
383 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
384 static bool mips_matching_cpu_name_p (const char *, const char *);
385 static const struct mips_cpu_info *mips_parse_cpu (const char *);
386 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
387 static bool mips_return_in_memory (tree, tree);
388 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
389 static void mips_macc_chains_record (rtx);
390 static void mips_macc_chains_reorder (rtx *, int);
391 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
392 static bool vr4130_true_reg_dependence_p (rtx);
393 static bool vr4130_swap_insns_p (rtx, rtx);
394 static void vr4130_reorder (rtx *, int);
395 static void mips_promote_ready (rtx *, int, int);
396 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
397 static int mips_variable_issue (FILE *, int, rtx, int);
398 static int mips_adjust_cost (rtx, rtx, rtx, int);
399 static int mips_issue_rate (void);
400 static int mips_multipass_dfa_lookahead (void);
401 static void mips_init_libfuncs (void);
402 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
404 static tree mips_build_builtin_va_list (void);
405 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
406 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
408 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
410 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
412 static bool mips_valid_pointer_mode (enum machine_mode);
413 static bool mips_vector_mode_supported_p (enum machine_mode);
414 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
415 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
416 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
417 static void mips_init_builtins (void);
418 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
419 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
420 enum insn_code, enum mips_fp_condition,
422 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
423 enum insn_code, enum mips_fp_condition,
425 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
426 static void mips_encode_section_info (tree, rtx, int);
427 static void mips_extra_live_on_entry (bitmap);
428 static int mips_comp_type_attributes (tree, tree);
429 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
430 static bool mips_offset_within_alignment_p (rtx, HOST_WIDE_INT);
431 static void mips_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
433 /* Structure to be filled in by compute_frame_size with register
434 save masks, and offsets for the current function. */
436 struct mips_frame_info GTY(())
438 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
439 HOST_WIDE_INT var_size; /* # bytes that variables take up */
440 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
441 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
442 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
443 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
444 unsigned int mask; /* mask of saved gp registers */
445 unsigned int fmask; /* mask of saved fp registers */
446 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
447 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
448 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
449 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
450 bool initialized; /* true if frame size already calculated */
451 int num_gp; /* number of gp registers saved */
452 int num_fp; /* number of fp registers saved */
455 struct machine_function GTY(()) {
456 /* Pseudo-reg holding the value of $28 in a mips16 function which
457 refers to GP relative global variables. */
458 rtx mips16_gp_pseudo_rtx;
460 /* The number of extra stack bytes taken up by register varargs.
461 This area is allocated by the callee at the very top of the frame. */
464 /* Current frame information, calculated by compute_frame_size. */
465 struct mips_frame_info frame;
467 /* The register to use as the global pointer within this function. */
468 unsigned int global_pointer;
470 /* True if mips_adjust_insn_length should ignore an instruction's
472 bool ignore_hazard_length_p;
474 /* True if the whole function is suitable for .set noreorder and
476 bool all_noreorder_p;
478 /* True if the function is known to have an instruction that needs $gp. */
482 /* Information about a single argument. */
485 /* True if the argument is passed in a floating-point register, or
486 would have been if we hadn't run out of registers. */
489 /* The number of words passed in registers, rounded up. */
490 unsigned int reg_words;
492 /* For EABI, the offset of the first register from GP_ARG_FIRST or
493 FP_ARG_FIRST. For other ABIs, the offset of the first register from
494 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
495 comment for details).
497 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
499 unsigned int reg_offset;
501 /* The number of words that must be passed on the stack, rounded up. */
502 unsigned int stack_words;
504 /* The offset from the start of the stack overflow area of the argument's
505 first stack word. Only meaningful when STACK_WORDS is nonzero. */
506 unsigned int stack_offset;
510 /* Information about an address described by mips_address_type.
516 REG is the base register and OFFSET is the constant offset.
519 REG is the register that contains the high part of the address,
520 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
521 is the type of OFFSET's symbol.
524 SYMBOL_TYPE is the type of symbol being referenced. */
526 struct mips_address_info
528 enum mips_address_type type;
531 enum mips_symbol_type symbol_type;
535 /* One stage in a constant building sequence. These sequences have
539 A = A CODE[1] VALUE[1]
540 A = A CODE[2] VALUE[2]
543 where A is an accumulator, each CODE[i] is a binary rtl operation
544 and each VALUE[i] is a constant integer. */
545 struct mips_integer_op {
547 unsigned HOST_WIDE_INT value;
551 /* The largest number of operations needed to load an integer constant.
552 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
553 When the lowest bit is clear, we can try, but reject a sequence with
554 an extra SLL at the end. */
555 #define MIPS_MAX_INTEGER_OPS 7
557 /* Information about a MIPS16e SAVE or RESTORE instruction. */
558 struct mips16e_save_restore_info {
559 /* The number of argument registers saved by a SAVE instruction.
560 0 for RESTORE instructions. */
563 /* Bit X is set if the instruction saves or restores GPR X. */
566 /* The total number of bytes to allocate. */
570 /* Global variables for machine-dependent things. */
572 /* Threshold for data being put into the small data/bss area, instead
573 of the normal data area. */
574 int mips_section_threshold = -1;
576 /* Count the number of .file directives, so that .loc is up to date. */
577 int num_source_filenames = 0;
579 /* Count the number of sdb related labels are generated (to find block
580 start and end boundaries). */
581 int sdb_label_count = 0;
583 /* Next label # for each statement for Silicon Graphics IRIS systems. */
586 /* Name of the file containing the current function. */
587 const char *current_function_file = "";
589 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
595 /* The next branch instruction is a branch likely, not branch normal. */
596 int mips_branch_likely;
598 /* The operands passed to the last cmpMM expander. */
601 /* The target cpu for code generation. */
602 enum processor_type mips_arch;
603 const struct mips_cpu_info *mips_arch_info;
605 /* The target cpu for optimization and scheduling. */
606 enum processor_type mips_tune;
607 const struct mips_cpu_info *mips_tune_info;
609 /* Which instruction set architecture to use. */
612 /* Which ABI to use. */
613 int mips_abi = MIPS_ABI_DEFAULT;
615 /* Cost information to use. */
616 const struct mips_rtx_cost_data *mips_cost;
618 /* Whether we are generating mips16 hard float code. In mips16 mode
619 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
620 -msoft-float was not specified by the user, which means that we
621 should arrange to call mips32 hard floating point code. */
622 int mips16_hard_float;
624 /* The architecture selected by -mipsN. */
625 static const struct mips_cpu_info *mips_isa_info;
627 /* If TRUE, we split addresses into their high and low parts in the RTL. */
628 int mips_split_addresses;
630 /* Mode used for saving/restoring general purpose registers. */
631 static enum machine_mode gpr_mode;
633 /* Array giving truth value on whether or not a given hard register
634 can support a given mode. */
635 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
637 /* List of all MIPS punctuation characters used by print_operand. */
638 char mips_print_operand_punct[256];
640 /* Map GCC register number to debugger register number. */
641 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
643 /* A copy of the original flag_delayed_branch: see override_options. */
644 static int mips_flag_delayed_branch;
646 static GTY (()) int mips_output_filename_first_time = 1;
648 /* mips_split_p[X] is true if symbols of type X can be split by
649 mips_split_symbol(). */
650 bool mips_split_p[NUM_SYMBOL_TYPES];
652 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
653 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
654 if they are matched by a special .md file pattern. */
655 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
657 /* Likewise for HIGHs. */
658 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
660 /* Map hard register number to register class */
661 const enum reg_class mips_regno_to_class[] =
663 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
664 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
665 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
666 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
667 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
668 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
669 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
670 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
676 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
677 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
678 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
679 HI_REG, LO_REG, NO_REGS, ST_REGS,
680 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
681 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
682 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
688 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
689 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
690 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
696 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
697 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
698 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
704 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
705 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
706 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
707 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
708 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
709 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
712 /* Table of machine dependent attributes. */
713 const struct attribute_spec mips_attribute_table[] =
715 { "long_call", 0, 0, false, true, true, NULL },
716 { "far", 0, 0, false, true, true, NULL },
717 { "near", 0, 0, false, true, true, NULL },
718 { NULL, 0, 0, false, false, false, NULL }
721 /* A table describing all the processors gcc knows about. Names are
722 matched in the order listed. The first mention of an ISA level is
723 taken as the canonical name for that ISA.
725 To ease comparison, please keep this table in the same order as
726 gas's mips_cpu_info_table[]. Please also make sure that
727 MIPS_ISA_LEVEL_SPEC handles all -march options correctly. */
728 const struct mips_cpu_info mips_cpu_info_table[] = {
729 /* Entries for generic ISAs */
730 { "mips1", PROCESSOR_R3000, 1 },
731 { "mips2", PROCESSOR_R6000, 2 },
732 { "mips3", PROCESSOR_R4000, 3 },
733 { "mips4", PROCESSOR_R8000, 4 },
734 { "mips32", PROCESSOR_4KC, 32 },
735 { "mips32r2", PROCESSOR_M4K, 33 },
736 { "mips64", PROCESSOR_5KC, 64 },
739 { "r3000", PROCESSOR_R3000, 1 },
740 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
741 { "r3900", PROCESSOR_R3900, 1 },
744 { "r6000", PROCESSOR_R6000, 2 },
747 { "r4000", PROCESSOR_R4000, 3 },
748 { "vr4100", PROCESSOR_R4100, 3 },
749 { "vr4111", PROCESSOR_R4111, 3 },
750 { "vr4120", PROCESSOR_R4120, 3 },
751 { "vr4130", PROCESSOR_R4130, 3 },
752 { "vr4300", PROCESSOR_R4300, 3 },
753 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
754 { "r4600", PROCESSOR_R4600, 3 },
755 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
756 { "r4650", PROCESSOR_R4650, 3 },
759 { "r8000", PROCESSOR_R8000, 4 },
760 { "vr5000", PROCESSOR_R5000, 4 },
761 { "vr5400", PROCESSOR_R5400, 4 },
762 { "vr5500", PROCESSOR_R5500, 4 },
763 { "rm7000", PROCESSOR_R7000, 4 },
764 { "rm9000", PROCESSOR_R9000, 4 },
767 { "4kc", PROCESSOR_4KC, 32 },
768 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
769 { "4kp", PROCESSOR_4KP, 32 },
770 { "4ksc", PROCESSOR_4KC, 32 },
772 /* MIPS32 Release 2 */
773 { "m4k", PROCESSOR_M4K, 33 },
774 { "4kec", PROCESSOR_4KC, 33 },
775 { "4kem", PROCESSOR_4KC, 33 },
776 { "4kep", PROCESSOR_4KP, 33 },
777 { "4ksd", PROCESSOR_4KC, 33 },
779 { "24kc", PROCESSOR_24KC, 33 },
780 { "24kf2_1", PROCESSOR_24KF2_1, 33 },
781 { "24kf", PROCESSOR_24KF2_1, 33 },
782 { "24kf1_1", PROCESSOR_24KF1_1, 33 },
783 { "24kfx", PROCESSOR_24KF1_1, 33 },
784 { "24kx", PROCESSOR_24KF1_1, 33 },
786 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
787 { "24kef2_1", PROCESSOR_24KF2_1, 33 },
788 { "24kef", PROCESSOR_24KF2_1, 33 },
789 { "24kef1_1", PROCESSOR_24KF1_1, 33 },
790 { "24kefx", PROCESSOR_24KF1_1, 33 },
791 { "24kex", PROCESSOR_24KF1_1, 33 },
793 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
794 { "34kf2_1", PROCESSOR_24KF2_1, 33 },
795 { "34kf", PROCESSOR_24KF2_1, 33 },
796 { "34kf1_1", PROCESSOR_24KF1_1, 33 },
797 { "34kfx", PROCESSOR_24KF1_1, 33 },
798 { "34kx", PROCESSOR_24KF1_1, 33 },
800 { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
801 { "74kf2_1", PROCESSOR_74KF2_1, 33 },
802 { "74kf", PROCESSOR_74KF2_1, 33 },
803 { "74kf1_1", PROCESSOR_74KF1_1, 33 },
804 { "74kfx", PROCESSOR_74KF1_1, 33 },
805 { "74kx", PROCESSOR_74KF1_1, 33 },
806 { "74kf3_2", PROCESSOR_74KF3_2, 33 },
809 { "5kc", PROCESSOR_5KC, 64 },
810 { "5kf", PROCESSOR_5KF, 64 },
811 { "20kc", PROCESSOR_20KC, 64 },
812 { "sb1", PROCESSOR_SB1, 64 },
813 { "sb1a", PROCESSOR_SB1A, 64 },
814 { "sr71000", PROCESSOR_SR71000, 64 },
820 /* Default costs. If these are used for a processor we should look
821 up the actual costs. */
822 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
823 COSTS_N_INSNS (7), /* fp_mult_sf */ \
824 COSTS_N_INSNS (8), /* fp_mult_df */ \
825 COSTS_N_INSNS (23), /* fp_div_sf */ \
826 COSTS_N_INSNS (36), /* fp_div_df */ \
827 COSTS_N_INSNS (10), /* int_mult_si */ \
828 COSTS_N_INSNS (10), /* int_mult_di */ \
829 COSTS_N_INSNS (69), /* int_div_si */ \
830 COSTS_N_INSNS (69), /* int_div_di */ \
831 2, /* branch_cost */ \
832 4 /* memory_latency */
834 /* Need to replace these with the costs of calling the appropriate
836 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
837 COSTS_N_INSNS (256), /* fp_mult_sf */ \
838 COSTS_N_INSNS (256), /* fp_mult_df */ \
839 COSTS_N_INSNS (256), /* fp_div_sf */ \
840 COSTS_N_INSNS (256) /* fp_div_df */
842 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
844 COSTS_N_INSNS (1), /* fp_add */
845 COSTS_N_INSNS (1), /* fp_mult_sf */
846 COSTS_N_INSNS (1), /* fp_mult_df */
847 COSTS_N_INSNS (1), /* fp_div_sf */
848 COSTS_N_INSNS (1), /* fp_div_df */
849 COSTS_N_INSNS (1), /* int_mult_si */
850 COSTS_N_INSNS (1), /* int_mult_di */
851 COSTS_N_INSNS (1), /* int_div_si */
852 COSTS_N_INSNS (1), /* int_div_di */
854 4 /* memory_latency */
857 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
860 COSTS_N_INSNS (2), /* fp_add */
861 COSTS_N_INSNS (4), /* fp_mult_sf */
862 COSTS_N_INSNS (5), /* fp_mult_df */
863 COSTS_N_INSNS (12), /* fp_div_sf */
864 COSTS_N_INSNS (19), /* fp_div_df */
865 COSTS_N_INSNS (12), /* int_mult_si */
866 COSTS_N_INSNS (12), /* int_mult_di */
867 COSTS_N_INSNS (35), /* int_div_si */
868 COSTS_N_INSNS (35), /* int_div_di */
870 4 /* memory_latency */
875 COSTS_N_INSNS (6), /* int_mult_si */
876 COSTS_N_INSNS (6), /* int_mult_di */
877 COSTS_N_INSNS (36), /* int_div_si */
878 COSTS_N_INSNS (36), /* int_div_di */
880 4 /* memory_latency */
884 COSTS_N_INSNS (36), /* int_mult_si */
885 COSTS_N_INSNS (36), /* int_mult_di */
886 COSTS_N_INSNS (37), /* int_div_si */
887 COSTS_N_INSNS (37), /* int_div_di */
889 4 /* memory_latency */
893 COSTS_N_INSNS (4), /* int_mult_si */
894 COSTS_N_INSNS (11), /* int_mult_di */
895 COSTS_N_INSNS (36), /* int_div_si */
896 COSTS_N_INSNS (68), /* int_div_di */
898 4 /* memory_latency */
901 COSTS_N_INSNS (4), /* fp_add */
902 COSTS_N_INSNS (4), /* fp_mult_sf */
903 COSTS_N_INSNS (5), /* fp_mult_df */
904 COSTS_N_INSNS (17), /* fp_div_sf */
905 COSTS_N_INSNS (32), /* fp_div_df */
906 COSTS_N_INSNS (4), /* int_mult_si */
907 COSTS_N_INSNS (11), /* int_mult_di */
908 COSTS_N_INSNS (36), /* int_div_si */
909 COSTS_N_INSNS (68), /* int_div_di */
911 4 /* memory_latency */
918 COSTS_N_INSNS (5), /* int_mult_si */
919 COSTS_N_INSNS (5), /* int_mult_di */
920 COSTS_N_INSNS (41), /* int_div_si */
921 COSTS_N_INSNS (41), /* int_div_di */
923 4 /* memory_latency */
926 COSTS_N_INSNS (8), /* fp_add */
927 COSTS_N_INSNS (8), /* fp_mult_sf */
928 COSTS_N_INSNS (10), /* fp_mult_df */
929 COSTS_N_INSNS (34), /* fp_div_sf */
930 COSTS_N_INSNS (64), /* fp_div_df */
931 COSTS_N_INSNS (5), /* int_mult_si */
932 COSTS_N_INSNS (5), /* int_mult_di */
933 COSTS_N_INSNS (41), /* int_div_si */
934 COSTS_N_INSNS (41), /* int_div_di */
936 4 /* memory_latency */
939 COSTS_N_INSNS (4), /* fp_add */
940 COSTS_N_INSNS (4), /* fp_mult_sf */
941 COSTS_N_INSNS (5), /* fp_mult_df */
942 COSTS_N_INSNS (17), /* fp_div_sf */
943 COSTS_N_INSNS (32), /* fp_div_df */
944 COSTS_N_INSNS (5), /* int_mult_si */
945 COSTS_N_INSNS (5), /* int_mult_di */
946 COSTS_N_INSNS (41), /* int_div_si */
947 COSTS_N_INSNS (41), /* int_div_di */
949 4 /* memory_latency */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (5), /* int_mult_di */
955 COSTS_N_INSNS (41), /* int_div_si */
956 COSTS_N_INSNS (41), /* int_div_di */
958 4 /* memory_latency */
961 COSTS_N_INSNS (8), /* fp_add */
962 COSTS_N_INSNS (8), /* fp_mult_sf */
963 COSTS_N_INSNS (10), /* fp_mult_df */
964 COSTS_N_INSNS (34), /* fp_div_sf */
965 COSTS_N_INSNS (64), /* fp_div_df */
966 COSTS_N_INSNS (5), /* int_mult_si */
967 COSTS_N_INSNS (5), /* int_mult_di */
968 COSTS_N_INSNS (41), /* int_div_si */
969 COSTS_N_INSNS (41), /* int_div_di */
971 4 /* memory_latency */
974 COSTS_N_INSNS (4), /* fp_add */
975 COSTS_N_INSNS (4), /* fp_mult_sf */
976 COSTS_N_INSNS (5), /* fp_mult_df */
977 COSTS_N_INSNS (17), /* fp_div_sf */
978 COSTS_N_INSNS (32), /* fp_div_df */
979 COSTS_N_INSNS (5), /* int_mult_si */
980 COSTS_N_INSNS (5), /* int_mult_di */
981 COSTS_N_INSNS (41), /* int_div_si */
982 COSTS_N_INSNS (41), /* int_div_di */
984 4 /* memory_latency */
987 COSTS_N_INSNS (6), /* fp_add */
988 COSTS_N_INSNS (6), /* fp_mult_sf */
989 COSTS_N_INSNS (7), /* fp_mult_df */
990 COSTS_N_INSNS (25), /* fp_div_sf */
991 COSTS_N_INSNS (48), /* fp_div_df */
992 COSTS_N_INSNS (5), /* int_mult_si */
993 COSTS_N_INSNS (5), /* int_mult_di */
994 COSTS_N_INSNS (41), /* int_div_si */
995 COSTS_N_INSNS (41), /* int_div_di */
997 4 /* memory_latency */
1003 COSTS_N_INSNS (2), /* fp_add */
1004 COSTS_N_INSNS (4), /* fp_mult_sf */
1005 COSTS_N_INSNS (5), /* fp_mult_df */
1006 COSTS_N_INSNS (12), /* fp_div_sf */
1007 COSTS_N_INSNS (19), /* fp_div_df */
1008 COSTS_N_INSNS (2), /* int_mult_si */
1009 COSTS_N_INSNS (2), /* int_mult_di */
1010 COSTS_N_INSNS (35), /* int_div_si */
1011 COSTS_N_INSNS (35), /* int_div_di */
1012 1, /* branch_cost */
1013 4 /* memory_latency */
1016 COSTS_N_INSNS (3), /* fp_add */
1017 COSTS_N_INSNS (5), /* fp_mult_sf */
1018 COSTS_N_INSNS (6), /* fp_mult_df */
1019 COSTS_N_INSNS (15), /* fp_div_sf */
1020 COSTS_N_INSNS (16), /* fp_div_df */
1021 COSTS_N_INSNS (17), /* int_mult_si */
1022 COSTS_N_INSNS (17), /* int_mult_di */
1023 COSTS_N_INSNS (38), /* int_div_si */
1024 COSTS_N_INSNS (38), /* int_div_di */
1025 2, /* branch_cost */
1026 6 /* memory_latency */
1029 COSTS_N_INSNS (6), /* fp_add */
1030 COSTS_N_INSNS (7), /* fp_mult_sf */
1031 COSTS_N_INSNS (8), /* fp_mult_df */
1032 COSTS_N_INSNS (23), /* fp_div_sf */
1033 COSTS_N_INSNS (36), /* fp_div_df */
1034 COSTS_N_INSNS (10), /* int_mult_si */
1035 COSTS_N_INSNS (10), /* int_mult_di */
1036 COSTS_N_INSNS (69), /* int_div_si */
1037 COSTS_N_INSNS (69), /* int_div_di */
1038 2, /* branch_cost */
1039 6 /* memory_latency */
1051 /* The only costs that appear to be updated here are
1052 integer multiplication. */
1054 COSTS_N_INSNS (4), /* int_mult_si */
1055 COSTS_N_INSNS (6), /* int_mult_di */
1056 COSTS_N_INSNS (69), /* int_div_si */
1057 COSTS_N_INSNS (69), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1071 COSTS_N_INSNS (6), /* fp_add */
1072 COSTS_N_INSNS (4), /* fp_mult_sf */
1073 COSTS_N_INSNS (5), /* fp_mult_df */
1074 COSTS_N_INSNS (23), /* fp_div_sf */
1075 COSTS_N_INSNS (36), /* fp_div_df */
1076 COSTS_N_INSNS (5), /* int_mult_si */
1077 COSTS_N_INSNS (5), /* int_mult_di */
1078 COSTS_N_INSNS (36), /* int_div_si */
1079 COSTS_N_INSNS (36), /* int_div_di */
1080 1, /* branch_cost */
1081 4 /* memory_latency */
1084 COSTS_N_INSNS (6), /* fp_add */
1085 COSTS_N_INSNS (5), /* fp_mult_sf */
1086 COSTS_N_INSNS (6), /* fp_mult_df */
1087 COSTS_N_INSNS (30), /* fp_div_sf */
1088 COSTS_N_INSNS (59), /* fp_div_df */
1089 COSTS_N_INSNS (3), /* int_mult_si */
1090 COSTS_N_INSNS (4), /* int_mult_di */
1091 COSTS_N_INSNS (42), /* int_div_si */
1092 COSTS_N_INSNS (74), /* int_div_di */
1093 1, /* branch_cost */
1094 4 /* memory_latency */
1097 COSTS_N_INSNS (6), /* fp_add */
1098 COSTS_N_INSNS (5), /* fp_mult_sf */
1099 COSTS_N_INSNS (6), /* fp_mult_df */
1100 COSTS_N_INSNS (30), /* fp_div_sf */
1101 COSTS_N_INSNS (59), /* fp_div_df */
1102 COSTS_N_INSNS (5), /* int_mult_si */
1103 COSTS_N_INSNS (9), /* int_mult_di */
1104 COSTS_N_INSNS (42), /* int_div_si */
1105 COSTS_N_INSNS (74), /* int_div_di */
1106 1, /* branch_cost */
1107 4 /* memory_latency */
1110 /* The only costs that are changed here are
1111 integer multiplication. */
1112 COSTS_N_INSNS (6), /* fp_add */
1113 COSTS_N_INSNS (7), /* fp_mult_sf */
1114 COSTS_N_INSNS (8), /* fp_mult_df */
1115 COSTS_N_INSNS (23), /* fp_div_sf */
1116 COSTS_N_INSNS (36), /* fp_div_df */
1117 COSTS_N_INSNS (5), /* int_mult_si */
1118 COSTS_N_INSNS (9), /* int_mult_di */
1119 COSTS_N_INSNS (69), /* int_div_si */
1120 COSTS_N_INSNS (69), /* int_div_di */
1121 1, /* branch_cost */
1122 4 /* memory_latency */
1128 /* The only costs that are changed here are
1129 integer multiplication. */
1130 COSTS_N_INSNS (6), /* fp_add */
1131 COSTS_N_INSNS (7), /* fp_mult_sf */
1132 COSTS_N_INSNS (8), /* fp_mult_df */
1133 COSTS_N_INSNS (23), /* fp_div_sf */
1134 COSTS_N_INSNS (36), /* fp_div_df */
1135 COSTS_N_INSNS (3), /* int_mult_si */
1136 COSTS_N_INSNS (8), /* int_mult_di */
1137 COSTS_N_INSNS (69), /* int_div_si */
1138 COSTS_N_INSNS (69), /* int_div_di */
1139 1, /* branch_cost */
1140 4 /* memory_latency */
1143 /* These costs are the same as the SB-1A below. */
1144 COSTS_N_INSNS (4), /* fp_add */
1145 COSTS_N_INSNS (4), /* fp_mult_sf */
1146 COSTS_N_INSNS (4), /* fp_mult_df */
1147 COSTS_N_INSNS (24), /* fp_div_sf */
1148 COSTS_N_INSNS (32), /* fp_div_df */
1149 COSTS_N_INSNS (3), /* int_mult_si */
1150 COSTS_N_INSNS (4), /* int_mult_di */
1151 COSTS_N_INSNS (36), /* int_div_si */
1152 COSTS_N_INSNS (68), /* int_div_di */
1153 1, /* branch_cost */
1154 4 /* memory_latency */
1157 /* These costs are the same as the SB-1 above. */
1158 COSTS_N_INSNS (4), /* fp_add */
1159 COSTS_N_INSNS (4), /* fp_mult_sf */
1160 COSTS_N_INSNS (4), /* fp_mult_df */
1161 COSTS_N_INSNS (24), /* fp_div_sf */
1162 COSTS_N_INSNS (32), /* fp_div_df */
1163 COSTS_N_INSNS (3), /* int_mult_si */
1164 COSTS_N_INSNS (4), /* int_mult_di */
1165 COSTS_N_INSNS (36), /* int_div_si */
1166 COSTS_N_INSNS (68), /* int_div_di */
1167 1, /* branch_cost */
1168 4 /* memory_latency */
1175 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
1176 mips16e_s2_s8_regs[X], it must also save the registers in indexes
1177 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
1178 static const unsigned char mips16e_s2_s8_regs[] = {
1179 30, 23, 22, 21, 20, 19, 18
1181 static const unsigned char mips16e_a0_a3_regs[] = {
1185 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
1186 ordered from the uppermost in memory to the lowest in memory. */
1187 static const unsigned char mips16e_save_restore_regs[] = {
1188 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
1191 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1192 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1193 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1196 /* Initialize the GCC target structure. */
1197 #undef TARGET_ASM_ALIGNED_HI_OP
1198 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1199 #undef TARGET_ASM_ALIGNED_SI_OP
1200 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1201 #undef TARGET_ASM_ALIGNED_DI_OP
1202 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1204 #undef TARGET_ASM_FUNCTION_PROLOGUE
1205 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1206 #undef TARGET_ASM_FUNCTION_EPILOGUE
1207 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1208 #undef TARGET_ASM_SELECT_RTX_SECTION
1209 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1210 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1211 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1213 #undef TARGET_SCHED_REORDER
1214 #define TARGET_SCHED_REORDER mips_sched_reorder
1215 #undef TARGET_SCHED_VARIABLE_ISSUE
1216 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1217 #undef TARGET_SCHED_ADJUST_COST
1218 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1219 #undef TARGET_SCHED_ISSUE_RATE
1220 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1221 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1222 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1223 mips_multipass_dfa_lookahead
1225 #undef TARGET_DEFAULT_TARGET_FLAGS
1226 #define TARGET_DEFAULT_TARGET_FLAGS \
1228 | TARGET_CPU_DEFAULT \
1229 | TARGET_ENDIAN_DEFAULT \
1230 | TARGET_FP_EXCEPTIONS_DEFAULT \
1231 | MASK_CHECK_ZERO_DIV \
1233 #undef TARGET_HANDLE_OPTION
1234 #define TARGET_HANDLE_OPTION mips_handle_option
1236 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1237 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1239 #undef TARGET_VALID_POINTER_MODE
1240 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1241 #undef TARGET_RTX_COSTS
1242 #define TARGET_RTX_COSTS mips_rtx_costs
1243 #undef TARGET_ADDRESS_COST
1244 #define TARGET_ADDRESS_COST mips_address_cost
1246 #undef TARGET_IN_SMALL_DATA_P
1247 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1249 #undef TARGET_MACHINE_DEPENDENT_REORG
1250 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1252 #undef TARGET_ASM_FILE_START
1253 #define TARGET_ASM_FILE_START mips_file_start
1254 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1255 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1257 #undef TARGET_INIT_LIBFUNCS
1258 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1260 #undef TARGET_BUILD_BUILTIN_VA_LIST
1261 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1262 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1263 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1265 #undef TARGET_PROMOTE_FUNCTION_ARGS
1266 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1267 #undef TARGET_PROMOTE_FUNCTION_RETURN
1268 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1269 #undef TARGET_PROMOTE_PROTOTYPES
1270 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1272 #undef TARGET_RETURN_IN_MEMORY
1273 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1274 #undef TARGET_RETURN_IN_MSB
1275 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1277 #undef TARGET_ASM_OUTPUT_MI_THUNK
1278 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1279 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1280 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1282 #undef TARGET_SETUP_INCOMING_VARARGS
1283 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1284 #undef TARGET_STRICT_ARGUMENT_NAMING
1285 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1286 #undef TARGET_MUST_PASS_IN_STACK
1287 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1288 #undef TARGET_PASS_BY_REFERENCE
1289 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1290 #undef TARGET_CALLEE_COPIES
1291 #define TARGET_CALLEE_COPIES mips_callee_copies
1292 #undef TARGET_ARG_PARTIAL_BYTES
1293 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1295 #undef TARGET_MODE_REP_EXTENDED
1296 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1298 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1299 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1301 #undef TARGET_INIT_BUILTINS
1302 #define TARGET_INIT_BUILTINS mips_init_builtins
1303 #undef TARGET_EXPAND_BUILTIN
1304 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1306 #undef TARGET_HAVE_TLS
1307 #define TARGET_HAVE_TLS HAVE_AS_TLS
1309 #undef TARGET_CANNOT_FORCE_CONST_MEM
1310 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1312 #undef TARGET_ENCODE_SECTION_INFO
1313 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1315 #undef TARGET_ATTRIBUTE_TABLE
1316 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1318 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1319 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1321 #undef TARGET_MIN_ANCHOR_OFFSET
1322 #define TARGET_MIN_ANCHOR_OFFSET -32768
1323 #undef TARGET_MAX_ANCHOR_OFFSET
1324 #define TARGET_MAX_ANCHOR_OFFSET 32767
1325 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1326 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1327 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1328 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1330 #undef TARGET_COMP_TYPE_ATTRIBUTES
1331 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
1333 #ifdef HAVE_AS_DTPRELWORD
1334 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1335 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
1338 struct gcc_target targetm = TARGET_INITIALIZER;
1341 /* Predicates to test for presence of "near" and "far"/"long_call"
1342 attributes on the given TYPE. */
1345 mips_near_type_p (tree type)
1347 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1351 mips_far_type_p (tree type)
1353 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1354 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1358 /* Return 0 if the attributes for two types are incompatible, 1 if they
1359 are compatible, and 2 if they are nearly compatible (which causes a
1360 warning to be generated). */
1363 mips_comp_type_attributes (tree type1, tree type2)
1365 /* Check for mismatch of non-default calling convention. */
1366 if (TREE_CODE (type1) != FUNCTION_TYPE)
1369 /* Disallow mixed near/far attributes. */
1370 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1372 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1378 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1379 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1382 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1384 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1386 *base_ptr = XEXP (x, 0);
1387 *offset_ptr = INTVAL (XEXP (x, 1));
1396 /* Return true if SYMBOL_REF X is associated with a global symbol
1397 (in the STB_GLOBAL sense). */
1400 mips_global_symbol_p (rtx x)
1404 decl = SYMBOL_REF_DECL (x);
1406 return !SYMBOL_REF_LOCAL_P (x);
1408 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1409 or weak symbols. Relocations in the object file will be against
1410 the target symbol, so it's that symbol's binding that matters here. */
1411 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1414 /* Return true if SYMBOL_REF X binds locally. */
1417 mips_symbol_binds_local_p (rtx x)
1419 return (SYMBOL_REF_DECL (x)
1420 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1421 : SYMBOL_REF_LOCAL_P (x));
1424 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1426 static enum mips_symbol_type
1427 mips_classify_symbol (rtx x)
1430 return SYMBOL_GOT_DISP;
1432 if (GET_CODE (x) == LABEL_REF)
1435 return SYMBOL_CONSTANT_POOL;
1436 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1437 return SYMBOL_GOT_PAGE_OFST;
1438 return SYMBOL_GENERAL;
1441 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1443 if (SYMBOL_REF_TLS_MODEL (x))
1446 if (CONSTANT_POOL_ADDRESS_P (x))
1449 return SYMBOL_CONSTANT_POOL;
1451 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1452 return SYMBOL_SMALL_DATA;
1455 /* Do not use small-data accesses for weak symbols; they may end up
1457 if (SYMBOL_REF_SMALL_P (x)
1458 && !SYMBOL_REF_WEAK (x))
1459 return SYMBOL_SMALL_DATA;
1461 if (TARGET_ABICALLS)
1463 /* Don't use GOT accesses for locally-binding symbols; we can use
1464 %hi and %lo instead. */
1465 if (TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))
1466 return SYMBOL_GENERAL;
1468 /* There are three cases to consider:
1470 - o32 PIC (either with or without explicit relocs)
1471 - n32/n64 PIC without explicit relocs
1472 - n32/n64 PIC with explicit relocs
1474 In the first case, both local and global accesses will use an
1475 R_MIPS_GOT16 relocation. We must correctly predict which of
1476 the two semantics (local or global) the assembler and linker
1477 will apply. The choice depends on the symbol's binding rather
1478 than its visibility.
1480 In the second case, the assembler will not use R_MIPS_GOT16
1481 relocations, but it chooses between local and global accesses
1482 in the same way as for o32 PIC.
1484 In the third case we have more freedom since both forms of
1485 access will work for any kind of symbol. However, there seems
1486 little point in doing things differently. */
1487 if (mips_global_symbol_p (x))
1488 return SYMBOL_GOT_DISP;
1490 return SYMBOL_GOT_PAGE_OFST;
1493 return SYMBOL_GENERAL;
1496 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1497 is the alignment (in bytes) of SYMBOL_REF X. */
1500 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1502 /* If for some reason we can't get the alignment for the
1503 symbol, initializing this to one means we will only accept
1505 HOST_WIDE_INT align = 1;
1508 /* Get the alignment of the symbol we're referring to. */
1509 t = SYMBOL_REF_DECL (x);
1511 align = DECL_ALIGN_UNIT (t);
1513 return offset >= 0 && offset < align;
1516 /* Return true if X is a symbolic constant that can be calculated in
1517 the same way as a bare symbol. If it is, store the type of the
1518 symbol in *SYMBOL_TYPE. */
1521 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1525 split_const (x, &x, &offset);
1526 if (UNSPEC_ADDRESS_P (x))
1528 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1529 x = UNSPEC_ADDRESS (x);
1531 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1533 *symbol_type = mips_classify_symbol (x);
1534 if (*symbol_type == SYMBOL_TLS)
1540 if (offset == const0_rtx)
1543 /* Check whether a nonzero offset is valid for the underlying
1545 switch (*symbol_type)
1547 case SYMBOL_GENERAL:
1548 case SYMBOL_64_HIGH:
1551 /* If the target has 64-bit pointers and the object file only
1552 supports 32-bit symbols, the values of those symbols will be
1553 sign-extended. In this case we can't allow an arbitrary offset
1554 in case the 32-bit value X + OFFSET has a different sign from X. */
1555 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1556 return offset_within_block_p (x, INTVAL (offset));
1558 /* In other cases the relocations can handle any offset. */
1561 case SYMBOL_CONSTANT_POOL:
1562 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1563 In this case, we no longer have access to the underlying constant,
1564 but the original symbol-based access was known to be valid. */
1565 if (GET_CODE (x) == LABEL_REF)
1570 case SYMBOL_SMALL_DATA:
1571 /* Make sure that the offset refers to something within the
1572 same object block. This should guarantee that the final
1573 PC- or GP-relative offset is within the 16-bit limit. */
1574 return offset_within_block_p (x, INTVAL (offset));
1576 case SYMBOL_GOT_PAGE_OFST:
1577 case SYMBOL_GOTOFF_PAGE:
1578 /* If the symbol is global, the GOT entry will contain the symbol's
1579 address, and we will apply a 16-bit offset after loading it.
1580 If the symbol is local, the linker should provide enough local
1581 GOT entries for a 16-bit offset, but larger offsets may lead
1583 return SMALL_INT (offset);
1587 /* There is no carry between the HI and LO REL relocations, so the
1588 offset is only valid if we know it won't lead to such a carry. */
1589 return mips_offset_within_alignment_p (x, INTVAL (offset));
1591 case SYMBOL_GOT_DISP:
1592 case SYMBOL_GOTOFF_DISP:
1593 case SYMBOL_GOTOFF_CALL:
1594 case SYMBOL_GOTOFF_LOADGP:
1597 case SYMBOL_GOTTPREL:
1606 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1609 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1611 if (!HARD_REGISTER_NUM_P (regno))
1615 regno = reg_renumber[regno];
1618 /* These fake registers will be eliminated to either the stack or
1619 hard frame pointer, both of which are usually valid base registers.
1620 Reload deals with the cases where the eliminated form isn't valid. */
1621 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1624 /* In mips16 mode, the stack pointer can only address word and doubleword
1625 values, nothing smaller. There are two problems here:
1627 (a) Instantiating virtual registers can introduce new uses of the
1628 stack pointer. If these virtual registers are valid addresses,
1629 the stack pointer should be too.
1631 (b) Most uses of the stack pointer are not made explicit until
1632 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1633 We don't know until that stage whether we'll be eliminating to the
1634 stack pointer (which needs the restriction) or the hard frame
1635 pointer (which doesn't).
1637 All in all, it seems more consistent to only enforce this restriction
1638 during and after reload. */
1639 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1640 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1642 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1646 /* Return true if X is a valid base register for the given mode.
1647 Allow only hard registers if STRICT. */
1650 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1652 if (!strict && GET_CODE (x) == SUBREG)
1656 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1660 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1661 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1664 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1665 enum machine_mode mode)
1667 switch (symbol_type)
1669 case SYMBOL_GENERAL:
1670 return !TARGET_MIPS16;
1672 case SYMBOL_SMALL_DATA:
1675 case SYMBOL_CONSTANT_POOL:
1676 /* PC-relative addressing is only available for lw and ld. */
1677 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1679 case SYMBOL_GOT_PAGE_OFST:
1682 case SYMBOL_GOT_DISP:
1683 /* The address will have to be loaded from the GOT first. */
1686 case SYMBOL_GOTOFF_PAGE:
1687 case SYMBOL_GOTOFF_DISP:
1688 case SYMBOL_GOTOFF_CALL:
1689 case SYMBOL_GOTOFF_LOADGP:
1694 case SYMBOL_GOTTPREL:
1696 case SYMBOL_64_HIGH:
1706 /* Return true if X is a valid address for machine mode MODE. If it is,
1707 fill in INFO appropriately. STRICT is true if we should only accept
1708 hard base registers. */
1711 mips_classify_address (struct mips_address_info *info, rtx x,
1712 enum machine_mode mode, int strict)
1714 switch (GET_CODE (x))
1718 info->type = ADDRESS_REG;
1720 info->offset = const0_rtx;
1721 return mips_valid_base_register_p (info->reg, mode, strict);
1724 info->type = ADDRESS_REG;
1725 info->reg = XEXP (x, 0);
1726 info->offset = XEXP (x, 1);
1727 return (mips_valid_base_register_p (info->reg, mode, strict)
1728 && const_arith_operand (info->offset, VOIDmode));
1731 info->type = ADDRESS_LO_SUM;
1732 info->reg = XEXP (x, 0);
1733 info->offset = XEXP (x, 1);
1734 return (mips_valid_base_register_p (info->reg, mode, strict)
1735 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1736 && mips_symbolic_address_p (info->symbol_type, mode)
1737 && mips_lo_relocs[info->symbol_type] != 0);
1740 /* Small-integer addresses don't occur very often, but they
1741 are legitimate if $0 is a valid base register. */
1742 info->type = ADDRESS_CONST_INT;
1743 return !TARGET_MIPS16 && SMALL_INT (x);
1748 info->type = ADDRESS_SYMBOLIC;
1749 return (mips_symbolic_constant_p (x, &info->symbol_type)
1750 && mips_symbolic_address_p (info->symbol_type, mode)
1751 && !mips_split_p[info->symbol_type]);
1758 /* Return true if X is a thread-local symbol. */
1761 mips_tls_operand_p (rtx x)
1763 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1766 /* Return true if X can not be forced into a constant pool. */
1769 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1771 return mips_tls_operand_p (*x);
1774 /* Return true if X can not be forced into a constant pool. */
1777 mips_cannot_force_const_mem (rtx x)
1783 /* As an optimization, reject constants that mips_legitimize_move
1786 Suppose we have a multi-instruction sequence that loads constant C
1787 into register R. If R does not get allocated a hard register, and
1788 R is used in an operand that allows both registers and memory
1789 references, reload will consider forcing C into memory and using
1790 one of the instruction's memory alternatives. Returning false
1791 here will force it to use an input reload instead. */
1792 if (GET_CODE (x) == CONST_INT)
1795 split_const (x, &base, &offset);
1796 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1800 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1806 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1807 constant pools, but normal-mode code doesn't need to. */
1810 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1811 rtx x ATTRIBUTE_UNUSED)
1813 return !TARGET_MIPS16;
1816 /* Return the number of instructions needed to load a symbol of the
1817 given type into a register. If valid in an address, the same number
1818 of instructions are needed for loads and stores. Treat extended
1819 mips16 instructions as two instructions. */
1822 mips_symbol_insns (enum mips_symbol_type type)
1826 case SYMBOL_GENERAL:
1827 /* In mips16 code, general symbols must be fetched from the
1832 /* When using 64-bit symbols, we need 5 preparatory instructions,
1835 lui $at,%highest(symbol)
1836 daddiu $at,$at,%higher(symbol)
1838 daddiu $at,$at,%hi(symbol)
1841 The final address is then $at + %lo(symbol). With 32-bit
1842 symbols we just need a preparatory lui. */
1843 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1845 case SYMBOL_SMALL_DATA:
1849 case SYMBOL_CONSTANT_POOL:
1850 /* This case is for mips16 only. Assume we'll need an
1851 extended instruction. */
1854 case SYMBOL_GOT_PAGE_OFST:
1855 case SYMBOL_GOT_DISP:
1856 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1857 the local/global classification is accurate. See override_options
1860 The worst cases are:
1862 (1) For local symbols when generating o32 or o64 code. The assembler
1868 ...and the final address will be $at + %lo(symbol).
1870 (2) For global symbols when -mxgot. The assembler will use:
1872 lui $at,%got_hi(symbol)
1875 ...and the final address will be $at + %got_lo(symbol). */
1878 case SYMBOL_GOTOFF_PAGE:
1879 case SYMBOL_GOTOFF_DISP:
1880 case SYMBOL_GOTOFF_CALL:
1881 case SYMBOL_GOTOFF_LOADGP:
1882 case SYMBOL_64_HIGH:
1888 case SYMBOL_GOTTPREL:
1890 /* Check whether the offset is a 16- or 32-bit value. */
1891 return mips_split_p[type] ? 2 : 1;
1894 /* We don't treat a bare TLS symbol as a constant. */
1900 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1903 mips_stack_address_p (rtx x, enum machine_mode mode)
1905 struct mips_address_info addr;
1907 return (mips_classify_address (&addr, x, mode, false)
1908 && addr.type == ADDRESS_REG
1909 && addr.reg == stack_pointer_rtx);
1912 /* Return true if a value at OFFSET bytes from BASE can be accessed
1913 using an unextended mips16 instruction. MODE is the mode of the
1916 Usually the offset in an unextended instruction is a 5-bit field.
1917 The offset is unsigned and shifted left once for HIs, twice
1918 for SIs, and so on. An exception is SImode accesses off the
1919 stack pointer, which have an 8-bit immediate field. */
1922 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1925 && GET_CODE (offset) == CONST_INT
1926 && INTVAL (offset) >= 0
1927 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1929 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1930 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1931 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1937 /* Return the number of instructions needed to load or store a value
1938 of mode MODE at X. Return 0 if X isn't valid for MODE.
1940 For mips16 code, count extended instructions as two instructions. */
1943 mips_address_insns (rtx x, enum machine_mode mode)
1945 struct mips_address_info addr;
1948 if (mode == BLKmode)
1949 /* BLKmode is used for single unaligned loads and stores. */
1952 /* Each word of a multi-word value will be accessed individually. */
1953 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1955 if (mips_classify_address (&addr, x, mode, false))
1960 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1964 case ADDRESS_LO_SUM:
1965 return (TARGET_MIPS16 ? factor * 2 : factor);
1967 case ADDRESS_CONST_INT:
1970 case ADDRESS_SYMBOLIC:
1971 return factor * mips_symbol_insns (addr.symbol_type);
1977 /* Likewise for constant X. */
1980 mips_const_insns (rtx x)
1982 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1983 enum mips_symbol_type symbol_type;
1986 switch (GET_CODE (x))
1990 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1991 || !mips_split_p[symbol_type])
1998 /* Unsigned 8-bit constants can be loaded using an unextended
1999 LI instruction. Unsigned 16-bit constants can be loaded
2000 using an extended LI. Negative constants must be loaded
2001 using LI and then negated. */
2002 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
2003 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2004 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
2005 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2008 return mips_build_integer (codes, INTVAL (x));
2012 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
2018 /* See if we can refer to X directly. */
2019 if (mips_symbolic_constant_p (x, &symbol_type))
2020 return mips_symbol_insns (symbol_type);
2022 /* Otherwise try splitting the constant into a base and offset.
2023 16-bit offsets can be added using an extra addiu. Larger offsets
2024 must be calculated separately and then added to the base. */
2025 split_const (x, &x, &offset);
2028 int n = mips_const_insns (x);
2031 if (SMALL_INT (offset))
2034 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2041 return mips_symbol_insns (mips_classify_symbol (x));
2049 /* Return the number of instructions needed for memory reference X.
2050 Count extended mips16 instructions as two instructions. */
2053 mips_fetch_insns (rtx x)
2055 gcc_assert (MEM_P (x));
2056 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
2060 /* Return the number of instructions needed for an integer division. */
2063 mips_idiv_insns (void)
2068 if (TARGET_CHECK_ZERO_DIV)
2070 if (GENERATE_DIVIDE_TRAPS)
2076 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2081 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
2082 returns a nonzero value if X is a legitimate address for a memory
2083 operand of the indicated MODE. STRICT is nonzero if this function
2084 is called during reload. */
2087 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
2089 struct mips_address_info addr;
2091 return mips_classify_address (&addr, x, mode, strict);
2095 /* Copy VALUE to a register and return that register. If new psuedos
2096 are allowed, copy it into a new register, otherwise use DEST. */
2099 mips_force_temporary (rtx dest, rtx value)
2101 if (can_create_pseudo_p ())
2102 return force_reg (Pmode, value);
2105 emit_move_insn (copy_rtx (dest), value);
2111 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
2112 and is used to load the high part into a register. */
2115 mips_split_symbol (rtx temp, rtx addr)
2120 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
2121 else if (!can_create_pseudo_p ())
2123 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2127 high = mips16_gp_pseudo_reg ();
2128 return gen_rtx_LO_SUM (Pmode, high, addr);
2132 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2133 type SYMBOL_TYPE. */
2136 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2140 split_const (address, &base, &offset);
2141 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2142 UNSPEC_ADDRESS_FIRST + symbol_type);
2143 if (offset != const0_rtx)
2144 base = gen_rtx_PLUS (Pmode, base, offset);
2145 return gen_rtx_CONST (Pmode, base);
2149 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2150 high part to BASE and return the result. Just return BASE otherwise.
2151 TEMP is available as a temporary register if needed.
2153 The returned expression can be used as the first operand to a LO_SUM. */
2156 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2157 enum mips_symbol_type symbol_type)
2159 if (mips_split_p[symbol_type])
2161 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2162 addr = mips_force_temporary (temp, addr);
2163 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2169 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2170 mips_force_temporary; it is only needed when OFFSET is not a
2174 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2176 if (!SMALL_OPERAND (offset))
2181 /* Load the full offset into a register so that we can use
2182 an unextended instruction for the address itself. */
2183 high = GEN_INT (offset);
2188 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2189 high = GEN_INT (CONST_HIGH_PART (offset));
2190 offset = CONST_LOW_PART (offset);
2192 high = mips_force_temporary (temp, high);
2193 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2195 return plus_constant (reg, offset);
2198 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2199 referencing, and TYPE is the symbol type to use (either global
2200 dynamic or local dynamic). V0 is an RTX for the return value
2201 location. The entire insn sequence is returned. */
2203 static GTY(()) rtx mips_tls_symbol;
2206 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2208 rtx insn, loc, tga, a0;
2210 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2212 if (!mips_tls_symbol)
2213 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2215 loc = mips_unspec_address (sym, type);
2219 emit_insn (gen_rtx_SET (Pmode, a0,
2220 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2221 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2222 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2223 CONST_OR_PURE_CALL_P (insn) = 1;
2224 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2225 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2226 insn = get_insns ();
2233 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2234 return value will be a valid address and move_operand (either a REG
2238 mips_legitimize_tls_address (rtx loc)
2240 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2241 enum tls_model model;
2243 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2244 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2246 model = SYMBOL_REF_TLS_MODEL (loc);
2247 /* Only TARGET_ABICALLS code can have more than one module; other
2248 code must be be static and should not use a GOT. All TLS models
2249 reduce to local exec in this situation. */
2250 if (!TARGET_ABICALLS)
2251 model = TLS_MODEL_LOCAL_EXEC;
2255 case TLS_MODEL_GLOBAL_DYNAMIC:
2256 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2257 dest = gen_reg_rtx (Pmode);
2258 emit_libcall_block (insn, dest, v0, loc);
2261 case TLS_MODEL_LOCAL_DYNAMIC:
2262 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2263 tmp1 = gen_reg_rtx (Pmode);
2265 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2266 share the LDM result with other LD model accesses. */
2267 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2269 emit_libcall_block (insn, tmp1, v0, eqv);
2271 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2272 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2273 mips_unspec_address (loc, SYMBOL_DTPREL));
2276 case TLS_MODEL_INITIAL_EXEC:
2277 tmp1 = gen_reg_rtx (Pmode);
2278 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2279 if (Pmode == DImode)
2281 emit_insn (gen_tls_get_tp_di (v1));
2282 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2286 emit_insn (gen_tls_get_tp_si (v1));
2287 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2289 dest = gen_reg_rtx (Pmode);
2290 emit_insn (gen_add3_insn (dest, tmp1, v1));
2293 case TLS_MODEL_LOCAL_EXEC:
2294 if (Pmode == DImode)
2295 emit_insn (gen_tls_get_tp_di (v1));
2297 emit_insn (gen_tls_get_tp_si (v1));
2299 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2300 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2301 mips_unspec_address (loc, SYMBOL_TPREL));
2311 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2312 be legitimized in a way that the generic machinery might not expect,
2313 put the new address in *XLOC and return true. MODE is the mode of
2314 the memory being accessed. */
2317 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2319 enum mips_symbol_type symbol_type;
2321 if (mips_tls_operand_p (*xloc))
2323 *xloc = mips_legitimize_tls_address (*xloc);
2327 /* See if the address can split into a high part and a LO_SUM. */
2328 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2329 && mips_symbolic_address_p (symbol_type, mode)
2330 && mips_split_p[symbol_type])
2332 *xloc = mips_split_symbol (0, *xloc);
2336 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2338 /* Handle REG + CONSTANT using mips_add_offset. */
2341 reg = XEXP (*xloc, 0);
2342 if (!mips_valid_base_register_p (reg, mode, 0))
2343 reg = copy_to_mode_reg (Pmode, reg);
2344 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2352 /* Subroutine of mips_build_integer (with the same interface).
2353 Assume that the final action in the sequence should be a left shift. */
2356 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2358 unsigned int i, shift;
2360 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2361 since signed numbers are easier to load than unsigned ones. */
2363 while ((value & 1) == 0)
2364 value /= 2, shift++;
2366 i = mips_build_integer (codes, value);
2367 codes[i].code = ASHIFT;
2368 codes[i].value = shift;
2373 /* As for mips_build_shift, but assume that the final action will be
2374 an IOR or PLUS operation. */
2377 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2379 unsigned HOST_WIDE_INT high;
2382 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2383 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2385 /* The constant is too complex to load with a simple lui/ori pair
2386 so our goal is to clear as many trailing zeros as possible.
2387 In this case, we know bit 16 is set and that the low 16 bits
2388 form a negative number. If we subtract that number from VALUE,
2389 we will clear at least the lowest 17 bits, maybe more. */
2390 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2391 codes[i].code = PLUS;
2392 codes[i].value = CONST_LOW_PART (value);
2396 i = mips_build_integer (codes, high);
2397 codes[i].code = IOR;
2398 codes[i].value = value & 0xffff;
2404 /* Fill CODES with a sequence of rtl operations to load VALUE.
2405 Return the number of operations needed. */
2408 mips_build_integer (struct mips_integer_op *codes,
2409 unsigned HOST_WIDE_INT value)
2411 if (SMALL_OPERAND (value)
2412 || SMALL_OPERAND_UNSIGNED (value)
2413 || LUI_OPERAND (value))
2415 /* The value can be loaded with a single instruction. */
2416 codes[0].code = UNKNOWN;
2417 codes[0].value = value;
2420 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2422 /* Either the constant is a simple LUI/ORI combination or its
2423 lowest bit is set. We don't want to shift in this case. */
2424 return mips_build_lower (codes, value);
2426 else if ((value & 0xffff) == 0)
2428 /* The constant will need at least three actions. The lowest
2429 16 bits are clear, so the final action will be a shift. */
2430 return mips_build_shift (codes, value);
2434 /* The final action could be a shift, add or inclusive OR.
2435 Rather than use a complex condition to select the best
2436 approach, try both mips_build_shift and mips_build_lower
2437 and pick the one that gives the shortest sequence.
2438 Note that this case is only used once per constant. */
2439 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2440 unsigned int cost, alt_cost;
2442 cost = mips_build_shift (codes, value);
2443 alt_cost = mips_build_lower (alt_codes, value);
2444 if (alt_cost < cost)
2446 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2454 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2457 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2459 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2460 enum machine_mode mode;
2461 unsigned int i, cost;
2464 mode = GET_MODE (dest);
2465 cost = mips_build_integer (codes, value);
2467 /* Apply each binary operation to X. Invariant: X is a legitimate
2468 source operand for a SET pattern. */
2469 x = GEN_INT (codes[0].value);
2470 for (i = 1; i < cost; i++)
2472 if (!can_create_pseudo_p ())
2474 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2478 x = force_reg (mode, x);
2479 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2482 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2486 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2487 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2491 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2495 /* Split moves of big integers into smaller pieces. */
2496 if (splittable_const_int_operand (src, mode))
2498 mips_move_integer (dest, dest, INTVAL (src));
2502 /* Split moves of symbolic constants into high/low pairs. */
2503 if (splittable_symbolic_operand (src, mode))
2505 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2509 if (mips_tls_operand_p (src))
2511 emit_move_insn (dest, mips_legitimize_tls_address (src));
2515 /* If we have (const (plus symbol offset)), load the symbol first
2516 and then add in the offset. This is usually better than forcing
2517 the constant into memory, at least in non-mips16 code. */
2518 split_const (src, &base, &offset);
2520 && offset != const0_rtx
2521 && (can_create_pseudo_p () || SMALL_INT (offset)))
2523 base = mips_force_temporary (dest, base);
2524 emit_move_insn (dest, mips_add_offset (0, base, INTVAL (offset)));
2528 src = force_const_mem (mode, src);
2530 /* When using explicit relocs, constant pool references are sometimes
2531 not legitimate addresses. */
2532 if (!memory_operand (src, VOIDmode))
2533 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2534 emit_move_insn (dest, src);
2538 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2539 sequence that is valid. */
2542 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2544 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2546 emit_move_insn (dest, force_reg (mode, src));
2550 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2551 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2552 && REG_P (src) && MD_REG_P (REGNO (src))
2553 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2555 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2556 if (GET_MODE_SIZE (mode) <= 4)
2557 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2558 gen_rtx_REG (SImode, REGNO (src)),
2559 gen_rtx_REG (SImode, other_regno)));
2561 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2562 gen_rtx_REG (DImode, REGNO (src)),
2563 gen_rtx_REG (DImode, other_regno)));
2567 /* We need to deal with constants that would be legitimate
2568 immediate_operands but not legitimate move_operands. */
2569 if (CONSTANT_P (src) && !move_operand (src, mode))
2571 mips_legitimize_const_move (mode, dest, src);
2572 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2578 /* We need a lot of little routines to check constant values on the
2579 mips16. These are used to figure out how long the instruction will
2580 be. It would be much better to do this using constraints, but
2581 there aren't nearly enough letters available. */
2584 m16_check_op (rtx op, int low, int high, int mask)
2586 return (GET_CODE (op) == CONST_INT
2587 && INTVAL (op) >= low
2588 && INTVAL (op) <= high
2589 && (INTVAL (op) & mask) == 0);
2593 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2595 return m16_check_op (op, 0x1, 0x8, 0);
2599 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2601 return m16_check_op (op, - 0x8, 0x7, 0);
2605 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2607 return m16_check_op (op, - 0x7, 0x8, 0);
2611 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2613 return m16_check_op (op, - 0x10, 0xf, 0);
2617 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2619 return m16_check_op (op, - 0xf, 0x10, 0);
2623 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2625 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2629 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2631 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2635 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2637 return m16_check_op (op, - 0x80, 0x7f, 0);
2641 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2643 return m16_check_op (op, - 0x7f, 0x80, 0);
2647 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2649 return m16_check_op (op, 0x0, 0xff, 0);
2653 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2655 return m16_check_op (op, - 0xff, 0x0, 0);
2659 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2661 return m16_check_op (op, - 0x1, 0xfe, 0);
2665 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2667 return m16_check_op (op, 0x0, 0xff << 2, 3);
2671 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2673 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2677 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2679 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2683 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2685 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2688 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
2689 address instruction. */
2692 mips_lwxs_address_p (rtx addr)
2695 && GET_CODE (addr) == PLUS
2696 && REG_P (XEXP (addr, 1)))
2698 rtx offset = XEXP (addr, 0);
2699 if (GET_CODE (offset) == MULT
2700 && REG_P (XEXP (offset, 0))
2701 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2702 && INTVAL (XEXP (offset, 1)) == 4)
2709 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2711 enum machine_mode mode = GET_MODE (x);
2712 bool float_mode_p = FLOAT_MODE_P (mode);
2719 /* A number between 1 and 8 inclusive is efficient for a shift.
2720 Otherwise, we will need an extended instruction. */
2721 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2722 || (outer_code) == LSHIFTRT)
2724 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2727 *total = COSTS_N_INSNS (1);
2731 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2732 if ((outer_code) == XOR
2733 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2739 /* We may be able to use slt or sltu for a comparison with a
2740 signed 16-bit value. (The boundary conditions aren't quite
2741 right, but this is just a heuristic anyhow.) */
2742 if (((outer_code) == LT || (outer_code) == LE
2743 || (outer_code) == GE || (outer_code) == GT
2744 || (outer_code) == LTU || (outer_code) == LEU
2745 || (outer_code) == GEU || (outer_code) == GTU)
2746 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2752 /* Equality comparisons with 0 are cheap. */
2753 if (((outer_code) == EQ || (outer_code) == NE)
2760 /* Constants in the range 0...255 can be loaded with an unextended
2761 instruction. They are therefore as cheap as a register move.
2763 Given the choice between "li R1,0...255" and "move R1,R2"
2764 (where R2 is a known constant), it is usually better to use "li",
2765 since we do not want to unnecessarily extend the lifetime
2767 if (outer_code == SET
2769 && INTVAL (x) < 256)
2777 /* These can be used anywhere. */
2782 /* Otherwise fall through to the handling below because
2783 we'll need to construct the constant. */
2789 if (LEGITIMATE_CONSTANT_P (x))
2791 *total = COSTS_N_INSNS (1);
2796 /* The value will need to be fetched from the constant pool. */
2797 *total = CONSTANT_POOL_COST;
2803 /* If the address is legitimate, return the number of
2804 instructions it needs. */
2805 rtx addr = XEXP (x, 0);
2806 int n = mips_address_insns (addr, GET_MODE (x));
2809 *total = COSTS_N_INSNS (n + 1);
2812 /* Check for scaled indexed address. */
2813 if (mips_lwxs_address_p (addr))
2815 *total = COSTS_N_INSNS (2);
2818 /* Otherwise use the default handling. */
2823 *total = COSTS_N_INSNS (6);
2827 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2833 if (mode == DImode && !TARGET_64BIT)
2835 *total = COSTS_N_INSNS (2);
2843 if (mode == DImode && !TARGET_64BIT)
2845 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2853 *total = COSTS_N_INSNS (1);
2855 *total = COSTS_N_INSNS (4);
2859 *total = COSTS_N_INSNS (1);
2866 *total = mips_cost->fp_add;
2870 else if (mode == DImode && !TARGET_64BIT)
2872 *total = COSTS_N_INSNS (4);
2878 if (mode == DImode && !TARGET_64BIT)
2880 *total = COSTS_N_INSNS (4);
2887 *total = mips_cost->fp_mult_sf;
2889 else if (mode == DFmode)
2890 *total = mips_cost->fp_mult_df;
2892 else if (mode == SImode)
2893 *total = mips_cost->int_mult_si;
2896 *total = mips_cost->int_mult_di;
2905 *total = mips_cost->fp_div_sf;
2907 *total = mips_cost->fp_div_df;
2916 *total = mips_cost->int_div_di;
2918 *total = mips_cost->int_div_si;
2923 /* A sign extend from SImode to DImode in 64-bit mode is often
2924 zero instructions, because the result can often be used
2925 directly by another instruction; we'll call it one. */
2926 if (TARGET_64BIT && mode == DImode
2927 && GET_MODE (XEXP (x, 0)) == SImode)
2928 *total = COSTS_N_INSNS (1);
2930 *total = COSTS_N_INSNS (2);
2934 if (TARGET_64BIT && mode == DImode
2935 && GET_MODE (XEXP (x, 0)) == SImode)
2936 *total = COSTS_N_INSNS (2);
2938 *total = COSTS_N_INSNS (1);
2942 case UNSIGNED_FLOAT:
2945 case FLOAT_TRUNCATE:
2947 *total = mips_cost->fp_add;
2955 /* Provide the costs of an addressing mode that contains ADDR.
2956 If ADDR is not a valid address, its cost is irrelevant. */
2959 mips_address_cost (rtx addr)
2961 return mips_address_insns (addr, SImode);
2964 /* Return one word of double-word value OP, taking into account the fixed
2965 endianness of certain registers. HIGH_P is true to select the high part,
2966 false to select the low part. */
2969 mips_subword (rtx op, int high_p)
2972 enum machine_mode mode;
2974 mode = GET_MODE (op);
2975 if (mode == VOIDmode)
2978 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2979 byte = UNITS_PER_WORD;
2985 if (FP_REG_P (REGNO (op)))
2986 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2987 if (ACC_HI_REG_P (REGNO (op)))
2988 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2992 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2994 return simplify_gen_subreg (word_mode, op, mode, byte);
2998 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3001 mips_split_64bit_move_p (rtx dest, rtx src)
3006 /* FP->FP moves can be done in a single instruction. */
3007 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3010 /* Check for floating-point loads and stores. They can be done using
3011 ldc1 and sdc1 on MIPS II and above. */
3014 if (FP_REG_RTX_P (dest) && MEM_P (src))
3016 if (FP_REG_RTX_P (src) && MEM_P (dest))
3023 /* Split a 64-bit move from SRC to DEST assuming that
3024 mips_split_64bit_move_p holds.
3026 Moves into and out of FPRs cause some difficulty here. Such moves
3027 will always be DFmode, since paired FPRs are not allowed to store
3028 DImode values. The most natural representation would be two separate
3029 32-bit moves, such as:
3031 (set (reg:SI $f0) (mem:SI ...))
3032 (set (reg:SI $f1) (mem:SI ...))
3034 However, the second insn is invalid because odd-numbered FPRs are
3035 not allowed to store independent values. Use the patterns load_df_low,
3036 load_df_high and store_df_high instead. */
3039 mips_split_64bit_move (rtx dest, rtx src)
3041 if (FP_REG_RTX_P (dest))
3043 /* Loading an FPR from memory or from GPRs. */
3046 dest = gen_lowpart (DFmode, dest);
3047 emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
3048 emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
3053 emit_insn (gen_load_df_low (copy_rtx (dest),
3054 mips_subword (src, 0)));
3055 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
3059 else if (FP_REG_RTX_P (src))
3061 /* Storing an FPR into memory or GPRs. */
3064 src = gen_lowpart (DFmode, src);
3065 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3066 emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
3070 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3071 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
3076 /* The operation can be split into two normal moves. Decide in
3077 which order to do them. */
3080 low_dest = mips_subword (dest, 0);
3081 if (REG_P (low_dest)
3082 && reg_overlap_mentioned_p (low_dest, src))
3084 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3085 emit_move_insn (low_dest, mips_subword (src, 0));
3089 emit_move_insn (low_dest, mips_subword (src, 0));
3090 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3095 /* Return the appropriate instructions to move SRC into DEST. Assume
3096 that SRC is operand 1 and DEST is operand 0. */
3099 mips_output_move (rtx dest, rtx src)
3101 enum rtx_code dest_code, src_code;
3104 dest_code = GET_CODE (dest);
3105 src_code = GET_CODE (src);
3106 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
3108 if (dbl_p && mips_split_64bit_move_p (dest, src))
3111 if ((src_code == REG && GP_REG_P (REGNO (src)))
3112 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3114 if (dest_code == REG)
3116 if (GP_REG_P (REGNO (dest)))
3117 return "move\t%0,%z1";
3119 if (MD_REG_P (REGNO (dest)))
3122 if (DSP_ACC_REG_P (REGNO (dest)))
3124 static char retval[] = "mt__\t%z1,%q0";
3125 retval[2] = reg_names[REGNO (dest)][4];
3126 retval[3] = reg_names[REGNO (dest)][5];
3130 if (FP_REG_P (REGNO (dest)))
3131 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3133 if (ALL_COP_REG_P (REGNO (dest)))
3135 static char retval[] = "dmtc_\t%z1,%0";
3137 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3138 return (dbl_p ? retval : retval + 1);
3141 if (dest_code == MEM)
3142 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3144 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3146 if (src_code == REG)
3148 if (DSP_ACC_REG_P (REGNO (src)))
3150 static char retval[] = "mf__\t%0,%q1";
3151 retval[2] = reg_names[REGNO (src)][4];
3152 retval[3] = reg_names[REGNO (src)][5];
3156 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3157 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3159 if (FP_REG_P (REGNO (src)))
3160 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3162 if (ALL_COP_REG_P (REGNO (src)))
3164 static char retval[] = "dmfc_\t%0,%1";
3166 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3167 return (dbl_p ? retval : retval + 1);
3171 if (src_code == MEM)
3172 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3174 if (src_code == CONST_INT)
3176 /* Don't use the X format, because that will give out of
3177 range numbers for 64-bit hosts and 32-bit targets. */
3179 return "li\t%0,%1\t\t\t# %X1";
3181 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3184 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3188 if (src_code == HIGH)
3189 return "lui\t%0,%h1";
3191 if (CONST_GP_P (src))
3192 return "move\t%0,%1";
3194 if (symbolic_operand (src, VOIDmode))
3195 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3197 if (src_code == REG && FP_REG_P (REGNO (src)))
3199 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3201 if (GET_MODE (dest) == V2SFmode)
3202 return "mov.ps\t%0,%1";
3204 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3207 if (dest_code == MEM)
3208 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3210 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3212 if (src_code == MEM)
3213 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3215 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3217 static char retval[] = "l_c_\t%0,%1";
3219 retval[1] = (dbl_p ? 'd' : 'w');
3220 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3223 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3225 static char retval[] = "s_c_\t%1,%0";
3227 retval[1] = (dbl_p ? 'd' : 'w');
3228 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3234 /* Restore $gp from its save slot. Valid only when using o32 or
3238 mips_restore_gp (void)
3242 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3244 address = mips_add_offset (pic_offset_table_rtx,
3245 frame_pointer_needed
3246 ? hard_frame_pointer_rtx
3247 : stack_pointer_rtx,
3248 current_function_outgoing_args_size);
3249 slot = gen_rtx_MEM (Pmode, address);
3251 emit_move_insn (pic_offset_table_rtx, slot);
3252 if (!TARGET_EXPLICIT_RELOCS)
3253 emit_insn (gen_blockage ());
3256 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3259 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3261 emit_insn (gen_rtx_SET (VOIDmode, target,
3262 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3265 /* Return true if CMP1 is a suitable second operand for relational
3266 operator CODE. See also the *sCC patterns in mips.md. */
3269 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3275 return reg_or_0_operand (cmp1, VOIDmode);
3279 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3283 return arith_operand (cmp1, VOIDmode);
3286 return sle_operand (cmp1, VOIDmode);
3289 return sleu_operand (cmp1, VOIDmode);
3296 /* Canonicalize LE or LEU comparisons into LT comparisons when
3297 possible to avoid extra instructions or inverting the
3301 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3302 enum machine_mode mode)
3304 HOST_WIDE_INT original, plus_one;
3306 if (GET_CODE (*cmp1) != CONST_INT)
3309 original = INTVAL (*cmp1);
3310 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3315 if (original < plus_one)
3318 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3327 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3340 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3341 result in TARGET. CMP0 and TARGET are register_operands that have
3342 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3343 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3346 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3347 rtx target, rtx cmp0, rtx cmp1)
3349 /* First see if there is a MIPS instruction that can do this operation
3350 with CMP1 in its current form. If not, try to canonicalize the
3351 comparison to LT. If that fails, try doing the same for the
3352 inverse operation. If that also fails, force CMP1 into a register
3354 if (mips_relational_operand_ok_p (code, cmp1))
3355 mips_emit_binary (code, target, cmp0, cmp1);
3356 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3357 mips_emit_binary (code, target, cmp0, cmp1);
3360 enum rtx_code inv_code = reverse_condition (code);
3361 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3363 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3364 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3366 else if (invert_ptr == 0)
3368 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3369 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3370 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3374 *invert_ptr = !*invert_ptr;
3375 mips_emit_binary (inv_code, target, cmp0, cmp1);
3380 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3381 The register will have the same mode as CMP0. */
3384 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3386 if (cmp1 == const0_rtx)
3389 if (uns_arith_operand (cmp1, VOIDmode))
3390 return expand_binop (GET_MODE (cmp0), xor_optab,
3391 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3393 return expand_binop (GET_MODE (cmp0), sub_optab,
3394 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3397 /* Convert *CODE into a code that can be used in a floating-point
3398 scc instruction (c.<cond>.<fmt>). Return true if the values of
3399 the condition code registers will be inverted, with 0 indicating
3400 that the condition holds. */
3403 mips_reverse_fp_cond_p (enum rtx_code *code)
3410 *code = reverse_condition_maybe_unordered (*code);
3418 /* Convert a comparison into something that can be used in a branch or
3419 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3420 being compared and *CODE is the code used to compare them.
3422 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3423 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3424 otherwise any standard branch condition can be used. The standard branch
3427 - EQ/NE between two registers.
3428 - any comparison between a register and zero. */
3431 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3433 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3435 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3437 *op0 = cmp_operands[0];
3438 *op1 = cmp_operands[1];
3440 else if (*code == EQ || *code == NE)
3444 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3449 *op0 = cmp_operands[0];
3450 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3455 /* The comparison needs a separate scc instruction. Store the
3456 result of the scc in *OP0 and compare it against zero. */
3457 bool invert = false;
3458 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3460 mips_emit_int_relational (*code, &invert, *op0,
3461 cmp_operands[0], cmp_operands[1]);
3462 *code = (invert ? EQ : NE);
3467 enum rtx_code cmp_code;
3469 /* Floating-point tests use a separate c.cond.fmt comparison to
3470 set a condition code register. The branch or conditional move
3471 will then compare that register against zero.
3473 Set CMP_CODE to the code of the comparison instruction and
3474 *CODE to the code that the branch or move should use. */
3476 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3478 ? gen_reg_rtx (CCmode)
3479 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3481 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3485 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3486 Store the result in TARGET and return true if successful.
3488 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3491 mips_emit_scc (enum rtx_code code, rtx target)
3493 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3496 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3497 if (code == EQ || code == NE)
3499 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3500 mips_emit_binary (code, target, zie, const0_rtx);
3503 mips_emit_int_relational (code, 0, target,
3504 cmp_operands[0], cmp_operands[1]);
3508 /* Emit the common code for doing conditional branches.
3509 operand[0] is the label to jump to.
3510 The comparison operands are saved away by cmp{si,di,sf,df}. */
3513 gen_conditional_branch (rtx *operands, enum rtx_code code)
3515 rtx op0, op1, condition;
3517 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3518 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3519 emit_jump_insn (gen_condjump (condition, operands[0]));
3524 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3525 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3528 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3529 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3534 reversed_p = mips_reverse_fp_cond_p (&cond);
3535 cmp_result = gen_reg_rtx (CCV2mode);
3536 emit_insn (gen_scc_ps (cmp_result,
3537 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3539 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3542 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3546 /* Emit the common code for conditional moves. OPERANDS is the array
3547 of operands passed to the conditional move define_expand. */
3550 gen_conditional_move (rtx *operands)
3555 code = GET_CODE (operands[1]);
3556 mips_emit_compare (&code, &op0, &op1, true);
3557 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3558 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3559 gen_rtx_fmt_ee (code,
3562 operands[2], operands[3])));
3565 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3566 the conditional_trap expander. */
3569 mips_gen_conditional_trap (rtx *operands)
3572 enum rtx_code cmp_code = GET_CODE (operands[0]);
3573 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3575 /* MIPS conditional trap machine instructions don't have GT or LE
3576 flavors, so we must invert the comparison and convert to LT and
3577 GE, respectively. */
3580 case GT: cmp_code = LT; break;
3581 case LE: cmp_code = GE; break;
3582 case GTU: cmp_code = LTU; break;
3583 case LEU: cmp_code = GEU; break;
3586 if (cmp_code == GET_CODE (operands[0]))
3588 op0 = cmp_operands[0];
3589 op1 = cmp_operands[1];
3593 op0 = cmp_operands[1];
3594 op1 = cmp_operands[0];
3596 op0 = force_reg (mode, op0);
3597 if (!arith_operand (op1, mode))
3598 op1 = force_reg (mode, op1);
3600 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3601 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3605 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
3608 mips_ok_for_lazy_binding_p (rtx x)
3610 return (TARGET_USE_GOT
3611 && GET_CODE (x) == SYMBOL_REF
3612 && !mips_symbol_binds_local_p (x));
3615 /* Load function address ADDR into register DEST. SIBCALL_P is true
3616 if the address is needed for a sibling call. */
3619 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3621 /* If we're generating PIC, and this call is to a global function,
3622 try to allow its address to be resolved lazily. This isn't
3623 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
3624 to the stub would be our caller's gp, not ours. */
3625 if (TARGET_EXPLICIT_RELOCS
3626 && !(sibcall_p && TARGET_CALL_SAVED_GP)
3627 && mips_ok_for_lazy_binding_p (addr))
3629 rtx high, lo_sum_symbol;
3631 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3632 addr, SYMBOL_GOTOFF_CALL);
3633 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3634 if (Pmode == SImode)
3635 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3637 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3640 emit_move_insn (dest, addr);
3644 /* Expand a call or call_value instruction. RESULT is where the
3645 result will go (null for calls), ADDR is the address of the
3646 function, ARGS_SIZE is the size of the arguments and AUX is
3647 the value passed to us by mips_function_arg. SIBCALL_P is true
3648 if we are expanding a sibling call, false if we're expanding
3652 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3654 rtx orig_addr, pattern, insn;
3657 if (!call_insn_operand (addr, VOIDmode))
3659 addr = gen_reg_rtx (Pmode);
3660 mips_load_call_address (addr, orig_addr, sibcall_p);
3663 if (mips16_hard_float
3664 && build_mips16_call_stub (result, addr, args_size,
3665 aux == 0 ? 0 : (int) GET_MODE (aux)))
3669 pattern = (sibcall_p
3670 ? gen_sibcall_internal (addr, args_size)
3671 : gen_call_internal (addr, args_size));
3672 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3676 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3677 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3680 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3681 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3684 pattern = (sibcall_p
3685 ? gen_sibcall_value_internal (result, addr, args_size)
3686 : gen_call_value_internal (result, addr, args_size));
3688 insn = emit_call_insn (pattern);
3690 /* Lazy-binding stubs require $gp to be valid on entry. */
3691 if (mips_ok_for_lazy_binding_p (orig_addr))
3692 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3696 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3699 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3700 tree exp ATTRIBUTE_UNUSED)
3702 return TARGET_SIBCALLS;
3705 /* Emit code to move general operand SRC into condition-code
3706 register DEST. SCRATCH is a scratch TFmode float register.
3713 where FP1 and FP2 are single-precision float registers
3714 taken from SCRATCH. */
3717 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3721 /* Change the source to SFmode. */
3723 src = adjust_address (src, SFmode, 0);
3724 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3725 src = gen_rtx_REG (SFmode, true_regnum (src));
3727 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3728 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
3730 emit_move_insn (copy_rtx (fp1), src);
3731 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3732 emit_insn (gen_slt_sf (dest, fp2, fp1));
3735 /* Emit code to change the current function's return address to
3736 ADDRESS. SCRATCH is available as a scratch register, if needed.
3737 ADDRESS and SCRATCH are both word-mode GPRs. */
3740 mips_set_return_address (rtx address, rtx scratch)
3744 compute_frame_size (get_frame_size ());
3745 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3746 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3747 cfun->machine->frame.gp_sp_offset);
3749 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3752 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3753 Assume that the areas do not overlap. */
3756 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3758 HOST_WIDE_INT offset, delta;
3759 unsigned HOST_WIDE_INT bits;
3761 enum machine_mode mode;
3764 /* Work out how many bits to move at a time. If both operands have
3765 half-word alignment, it is usually better to move in half words.
3766 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3767 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3768 Otherwise move word-sized chunks. */
3769 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3770 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3771 bits = BITS_PER_WORD / 2;
3773 bits = BITS_PER_WORD;
3775 mode = mode_for_size (bits, MODE_INT, 0);
3776 delta = bits / BITS_PER_UNIT;
3778 /* Allocate a buffer for the temporary registers. */
3779 regs = alloca (sizeof (rtx) * length / delta);
3781 /* Load as many BITS-sized chunks as possible. Use a normal load if
3782 the source has enough alignment, otherwise use left/right pairs. */
3783 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3785 regs[i] = gen_reg_rtx (mode);
3786 if (MEM_ALIGN (src) >= bits)
3787 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3790 rtx part = adjust_address (src, BLKmode, offset);
3791 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3796 /* Copy the chunks to the destination. */
3797 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3798 if (MEM_ALIGN (dest) >= bits)
3799 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3802 rtx part = adjust_address (dest, BLKmode, offset);
3803 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3807 /* Mop up any left-over bytes. */
3808 if (offset < length)
3810 src = adjust_address (src, BLKmode, offset);
3811 dest = adjust_address (dest, BLKmode, offset);
3812 move_by_pieces (dest, src, length - offset,
3813 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3817 #define MAX_MOVE_REGS 4
3818 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3821 /* Helper function for doing a loop-based block operation on memory
3822 reference MEM. Each iteration of the loop will operate on LENGTH
3825 Create a new base register for use within the loop and point it to
3826 the start of MEM. Create a new memory reference that uses this
3827 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3830 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3831 rtx *loop_reg, rtx *loop_mem)
3833 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3835 /* Although the new mem does not refer to a known location,
3836 it does keep up to LENGTH bytes of alignment. */
3837 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3838 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3842 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3843 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3844 memory regions do not overlap. */
3847 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3849 rtx label, src_reg, dest_reg, final_src;
3850 HOST_WIDE_INT leftover;
3852 leftover = length % MAX_MOVE_BYTES;
3855 /* Create registers and memory references for use within the loop. */
3856 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3857 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3859 /* Calculate the value that SRC_REG should have after the last iteration
3861 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3864 /* Emit the start of the loop. */
3865 label = gen_label_rtx ();
3868 /* Emit the loop body. */
3869 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3871 /* Move on to the next block. */
3872 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3873 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3875 /* Emit the loop condition. */
3876 if (Pmode == DImode)
3877 emit_insn (gen_cmpdi (src_reg, final_src));
3879 emit_insn (gen_cmpsi (src_reg, final_src));
3880 emit_jump_insn (gen_bne (label));
3882 /* Mop up any left-over bytes. */
3884 mips_block_move_straight (dest, src, leftover);
3888 /* Expand a loop of synci insns for the address range [BEGIN, END). */
3891 mips_expand_synci_loop (rtx begin, rtx end)
3893 rtx inc, label, cmp, cmp_result;
3895 /* Load INC with the cache line size (rdhwr INC,$1). */
3896 inc = gen_reg_rtx (SImode);
3897 emit_insn (gen_rdhwr (inc, const1_rtx));
3899 /* Loop back to here. */
3900 label = gen_label_rtx ();
3903 emit_insn (gen_synci (begin));
3905 cmp = gen_reg_rtx (Pmode);
3906 mips_emit_binary (GTU, cmp, begin, end);
3908 mips_emit_binary (PLUS, begin, begin, inc);
3910 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
3911 emit_jump_insn (gen_condjump (cmp_result, label));
3914 /* Expand a movmemsi instruction. */
3917 mips_expand_block_move (rtx dest, rtx src, rtx length)
3919 if (GET_CODE (length) == CONST_INT)
3921 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3923 mips_block_move_straight (dest, src, INTVAL (length));
3928 mips_block_move_loop (dest, src, INTVAL (length));
3935 /* Argument support functions. */
3937 /* Initialize CUMULATIVE_ARGS for a function. */
3940 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3941 rtx libname ATTRIBUTE_UNUSED)
3943 static CUMULATIVE_ARGS zero_cum;
3944 tree param, next_param;
3947 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3949 /* Determine if this function has variable arguments. This is
3950 indicated by the last argument being 'void_type_mode' if there
3951 are no variable arguments. The standard MIPS calling sequence
3952 passes all arguments in the general purpose registers in this case. */
3954 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3955 param != 0; param = next_param)
3957 next_param = TREE_CHAIN (param);
3958 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3959 cum->gp_reg_found = 1;
3964 /* Fill INFO with information about a single argument. CUM is the
3965 cumulative state for earlier arguments. MODE is the mode of this
3966 argument and TYPE is its type (if known). NAMED is true if this
3967 is a named (fixed) argument rather than a variable one. */
3970 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3971 tree type, int named, struct mips_arg_info *info)
3973 bool doubleword_aligned_p;
3974 unsigned int num_bytes, num_words, max_regs;
3976 /* Work out the size of the argument. */
3977 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3978 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3980 /* Decide whether it should go in a floating-point register, assuming
3981 one is free. Later code checks for availability.
3983 The checks against UNITS_PER_FPVALUE handle the soft-float and
3984 single-float cases. */
3988 /* The EABI conventions have traditionally been defined in terms
3989 of TYPE_MODE, regardless of the actual type. */
3990 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3991 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3992 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3997 /* Only leading floating-point scalars are passed in
3998 floating-point registers. We also handle vector floats the same
3999 say, which is OK because they are not covered by the standard ABI. */
4000 info->fpr_p = (!cum->gp_reg_found
4001 && cum->arg_number < 2
4002 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
4003 || VECTOR_FLOAT_TYPE_P (type))
4004 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4005 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4006 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4011 /* Scalar and complex floating-point types are passed in
4012 floating-point registers. */
4013 info->fpr_p = (named
4014 && (type == 0 || FLOAT_TYPE_P (type))
4015 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4016 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4017 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4018 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4020 /* ??? According to the ABI documentation, the real and imaginary
4021 parts of complex floats should be passed in individual registers.
4022 The real and imaginary parts of stack arguments are supposed
4023 to be contiguous and there should be an extra word of padding
4026 This has two problems. First, it makes it impossible to use a
4027 single "void *" va_list type, since register and stack arguments
4028 are passed differently. (At the time of writing, MIPSpro cannot
4029 handle complex float varargs correctly.) Second, it's unclear
4030 what should happen when there is only one register free.
4032 For now, we assume that named complex floats should go into FPRs
4033 if there are two FPRs free, otherwise they should be passed in the
4034 same way as a struct containing two floats. */
4036 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4037 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4039 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4040 info->fpr_p = false;
4050 /* See whether the argument has doubleword alignment. */
4051 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4053 /* Set REG_OFFSET to the register count we're interested in.
4054 The EABI allocates the floating-point registers separately,
4055 but the other ABIs allocate them like integer registers. */
4056 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4060 /* Advance to an even register if the argument is doubleword-aligned. */
4061 if (doubleword_aligned_p)
4062 info->reg_offset += info->reg_offset & 1;
4064 /* Work out the offset of a stack argument. */
4065 info->stack_offset = cum->stack_words;
4066 if (doubleword_aligned_p)
4067 info->stack_offset += info->stack_offset & 1;
4069 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4071 /* Partition the argument between registers and stack. */
4072 info->reg_words = MIN (num_words, max_regs);
4073 info->stack_words = num_words - info->reg_words;
4077 /* INFO describes an argument that is passed in a single-register value.
4078 Return the register it uses, assuming that FPRs are available if
4082 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4084 if (!info->fpr_p || !hard_float_p)
4085 return GP_ARG_FIRST + info->reg_offset;
4086 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4087 /* In o32, the second argument is always passed in $f14
4088 for TARGET_DOUBLE_FLOAT, regardless of whether the
4089 first argument was a word or doubleword. */
4090 return FP_ARG_FIRST + 2;
4092 return FP_ARG_FIRST + info->reg_offset;
4095 /* Implement FUNCTION_ARG_ADVANCE. */
4098 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4099 tree type, int named)
4101 struct mips_arg_info info;
4103 mips_arg_info (cum, mode, type, named, &info);
4106 cum->gp_reg_found = true;
4108 /* See the comment above the cumulative args structure in mips.h
4109 for an explanation of what this code does. It assumes the O32
4110 ABI, which passes at most 2 arguments in float registers. */
4111 if (cum->arg_number < 2 && info.fpr_p)
4112 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4114 if (mips_abi != ABI_EABI || !info.fpr_p)
4115 cum->num_gprs = info.reg_offset + info.reg_words;
4116 else if (info.reg_words > 0)
4117 cum->num_fprs += MAX_FPRS_PER_FMT;
4119 if (info.stack_words > 0)
4120 cum->stack_words = info.stack_offset + info.stack_words;
4125 /* Implement FUNCTION_ARG. */
4128 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4129 tree type, int named)
4131 struct mips_arg_info info;
4133 /* We will be called with a mode of VOIDmode after the last argument
4134 has been seen. Whatever we return will be passed to the call
4135 insn. If we need a mips16 fp_code, return a REG with the code
4136 stored as the mode. */
4137 if (mode == VOIDmode)
4139 if (TARGET_MIPS16 && cum->fp_code != 0)
4140 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4146 mips_arg_info (cum, mode, type, named, &info);
4148 /* Return straight away if the whole argument is passed on the stack. */
4149 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4153 && TREE_CODE (type) == RECORD_TYPE
4155 && TYPE_SIZE_UNIT (type)
4156 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4159 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4160 structure contains a double in its entirety, then that 64-bit
4161 chunk is passed in a floating point register. */
4164 /* First check to see if there is any such field. */
4165 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4166 if (TREE_CODE (field) == FIELD_DECL
4167 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4168 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4169 && host_integerp (bit_position (field), 0)
4170 && int_bit_position (field) % BITS_PER_WORD == 0)
4175 /* Now handle the special case by returning a PARALLEL
4176 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4177 chunks are passed in registers. */
4179 HOST_WIDE_INT bitpos;
4182 /* assign_parms checks the mode of ENTRY_PARM, so we must
4183 use the actual mode here. */
4184 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4187 field = TYPE_FIELDS (type);
4188 for (i = 0; i < info.reg_words; i++)
4192 for (; field; field = TREE_CHAIN (field))
4193 if (TREE_CODE (field) == FIELD_DECL
4194 && int_bit_position (field) >= bitpos)
4198 && int_bit_position (field) == bitpos
4199 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4200 && !TARGET_SOFT_FLOAT
4201 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4202 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4204 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4207 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4208 GEN_INT (bitpos / BITS_PER_UNIT));
4210 bitpos += BITS_PER_WORD;
4216 /* Handle the n32/n64 conventions for passing complex floating-point
4217 arguments in FPR pairs. The real part goes in the lower register
4218 and the imaginary part goes in the upper register. */
4221 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4224 enum machine_mode inner;
4227 inner = GET_MODE_INNER (mode);
4228 reg = FP_ARG_FIRST + info.reg_offset;
4229 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4231 /* Real part in registers, imaginary part on stack. */
4232 gcc_assert (info.stack_words == info.reg_words);
4233 return gen_rtx_REG (inner, reg);
4237 gcc_assert (info.stack_words == 0);
4238 real = gen_rtx_EXPR_LIST (VOIDmode,
4239 gen_rtx_REG (inner, reg),
4241 imag = gen_rtx_EXPR_LIST (VOIDmode,
4243 reg + info.reg_words / 2),
4244 GEN_INT (GET_MODE_SIZE (inner)));
4245 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4249 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4253 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4256 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4257 enum machine_mode mode, tree type, bool named)
4259 struct mips_arg_info info;
4261 mips_arg_info (cum, mode, type, named, &info);
4262 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4266 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4267 PARM_BOUNDARY bits of alignment, but will be given anything up
4268 to STACK_BOUNDARY bits if the type requires it. */
4271 function_arg_boundary (enum machine_mode mode, tree type)
4273 unsigned int alignment;
4275 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4276 if (alignment < PARM_BOUNDARY)
4277 alignment = PARM_BOUNDARY;
4278 if (alignment > STACK_BOUNDARY)
4279 alignment = STACK_BOUNDARY;
4283 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4284 upward rather than downward. In other words, return true if the
4285 first byte of the stack slot has useful data, false if the last
4289 mips_pad_arg_upward (enum machine_mode mode, tree type)
4291 /* On little-endian targets, the first byte of every stack argument
4292 is passed in the first byte of the stack slot. */
4293 if (!BYTES_BIG_ENDIAN)
4296 /* Otherwise, integral types are padded downward: the last byte of a
4297 stack argument is passed in the last byte of the stack slot. */
4299 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4300 : GET_MODE_CLASS (mode) == MODE_INT)
4303 /* Big-endian o64 pads floating-point arguments downward. */
4304 if (mips_abi == ABI_O64)
4305 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4308 /* Other types are padded upward for o32, o64, n32 and n64. */
4309 if (mips_abi != ABI_EABI)
4312 /* Arguments smaller than a stack slot are padded downward. */
4313 if (mode != BLKmode)
4314 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4316 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4320 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4321 if the least significant byte of the register has useful data. Return
4322 the opposite if the most significant byte does. */
4325 mips_pad_reg_upward (enum machine_mode mode, tree type)
4327 /* No shifting is required for floating-point arguments. */
4328 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4329 return !BYTES_BIG_ENDIAN;
4331 /* Otherwise, apply the same padding to register arguments as we do
4332 to stack arguments. */
4333 return mips_pad_arg_upward (mode, type);
4337 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4338 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4341 CUMULATIVE_ARGS local_cum;
4342 int gp_saved, fp_saved;
4344 /* The caller has advanced CUM up to, but not beyond, the last named
4345 argument. Advance a local copy of CUM past the last "real" named
4346 argument, to find out how many registers are left over. */
4349 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4351 /* Found out how many registers we need to save. */
4352 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4353 fp_saved = (EABI_FLOAT_VARARGS_P
4354 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4363 ptr = plus_constant (virtual_incoming_args_rtx,
4364 REG_PARM_STACK_SPACE (cfun->decl)
4365 - gp_saved * UNITS_PER_WORD);
4366 mem = gen_rtx_MEM (BLKmode, ptr);
4367 set_mem_alias_set (mem, get_varargs_alias_set ());
4369 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4374 /* We can't use move_block_from_reg, because it will use
4376 enum machine_mode mode;
4379 /* Set OFF to the offset from virtual_incoming_args_rtx of
4380 the first float register. The FP save area lies below
4381 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4382 off = -gp_saved * UNITS_PER_WORD;
4383 off &= ~(UNITS_PER_FPVALUE - 1);
4384 off -= fp_saved * UNITS_PER_FPREG;
4386 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4388 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4389 i += MAX_FPRS_PER_FMT)
4393 ptr = plus_constant (virtual_incoming_args_rtx, off);
4394 mem = gen_rtx_MEM (mode, ptr);
4395 set_mem_alias_set (mem, get_varargs_alias_set ());
4396 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4397 off += UNITS_PER_HWFPVALUE;
4401 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4402 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4403 + fp_saved * UNITS_PER_FPREG);
4406 /* Create the va_list data type.
4407 We keep 3 pointers, and two offsets.
4408 Two pointers are to the overflow area, which starts at the CFA.
4409 One of these is constant, for addressing into the GPR save area below it.
4410 The other is advanced up the stack through the overflow region.
4411 The third pointer is to the GPR save area. Since the FPR save area
4412 is just below it, we can address FPR slots off this pointer.
4413 We also keep two one-byte offsets, which are to be subtracted from the
4414 constant pointers to yield addresses in the GPR and FPR save areas.
4415 These are downcounted as float or non-float arguments are used,
4416 and when they get to zero, the argument must be obtained from the
4418 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4419 pointer is enough. It's started at the GPR save area, and is
4421 Note that the GPR save area is not constant size, due to optimization
4422 in the prologue. Hence, we can't use a design with two pointers
4423 and two offsets, although we could have designed this with two pointers
4424 and three offsets. */
4427 mips_build_builtin_va_list (void)
4429 if (EABI_FLOAT_VARARGS_P)
4431 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4434 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4436 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4438 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4440 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4442 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4443 unsigned_char_type_node);
4444 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4445 unsigned_char_type_node);
4446 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4447 warn on every user file. */
4448 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4449 array = build_array_type (unsigned_char_type_node,
4450 build_index_type (index));
4451 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4453 DECL_FIELD_CONTEXT (f_ovfl) = record;
4454 DECL_FIELD_CONTEXT (f_gtop) = record;
4455 DECL_FIELD_CONTEXT (f_ftop) = record;
4456 DECL_FIELD_CONTEXT (f_goff) = record;
4457 DECL_FIELD_CONTEXT (f_foff) = record;
4458 DECL_FIELD_CONTEXT (f_res) = record;
4460 TYPE_FIELDS (record) = f_ovfl;
4461 TREE_CHAIN (f_ovfl) = f_gtop;
4462 TREE_CHAIN (f_gtop) = f_ftop;
4463 TREE_CHAIN (f_ftop) = f_goff;
4464 TREE_CHAIN (f_goff) = f_foff;
4465 TREE_CHAIN (f_foff) = f_res;
4467 layout_type (record);
4470 else if (TARGET_IRIX && TARGET_IRIX6)
4471 /* On IRIX 6, this type is 'char *'. */
4472 return build_pointer_type (char_type_node);
4474 /* Otherwise, we use 'void *'. */
4475 return ptr_type_node;
4478 /* Implement va_start. */
4481 mips_va_start (tree valist, rtx nextarg)
4483 if (EABI_FLOAT_VARARGS_P)
4485 const CUMULATIVE_ARGS *cum;
4486 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4487 tree ovfl, gtop, ftop, goff, foff;
4489 int gpr_save_area_size;
4490 int fpr_save_area_size;
4493 cum = ¤t_function_args_info;
4495 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4497 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4499 f_ovfl = TYPE_FIELDS (va_list_type_node);
4500 f_gtop = TREE_CHAIN (f_ovfl);
4501 f_ftop = TREE_CHAIN (f_gtop);
4502 f_goff = TREE_CHAIN (f_ftop);
4503 f_foff = TREE_CHAIN (f_goff);
4505 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4507 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4509 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4511 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4513 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4516 /* Emit code to initialize OVFL, which points to the next varargs
4517 stack argument. CUM->STACK_WORDS gives the number of stack
4518 words used by named arguments. */
4519 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4520 if (cum->stack_words > 0)
4521 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4522 size_int (cum->stack_words * UNITS_PER_WORD));
4523 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4524 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4526 /* Emit code to initialize GTOP, the top of the GPR save area. */
4527 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4528 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4529 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4531 /* Emit code to initialize FTOP, the top of the FPR save area.
4532 This address is gpr_save_area_bytes below GTOP, rounded
4533 down to the next fp-aligned boundary. */
4534 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4535 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4536 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4538 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4539 size_int (-fpr_offset));
4540 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4541 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4543 /* Emit code to initialize GOFF, the offset from GTOP of the
4544 next GPR argument. */
4545 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4546 build_int_cst (NULL_TREE, gpr_save_area_size));
4547 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4549 /* Likewise emit code to initialize FOFF, the offset from FTOP
4550 of the next FPR argument. */
4551 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4552 build_int_cst (NULL_TREE, fpr_save_area_size));
4553 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4557 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4558 std_expand_builtin_va_start (valist, nextarg);
4562 /* Implement va_arg. */
4565 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4567 HOST_WIDE_INT size, rsize;
4571 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4574 type = build_pointer_type (type);
4576 size = int_size_in_bytes (type);
4577 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4579 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4580 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4583 /* Not a simple merged stack. */
4585 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4586 tree ovfl, top, off, align;
4587 HOST_WIDE_INT osize;
4590 f_ovfl = TYPE_FIELDS (va_list_type_node);
4591 f_gtop = TREE_CHAIN (f_ovfl);
4592 f_ftop = TREE_CHAIN (f_gtop);
4593 f_goff = TREE_CHAIN (f_ftop);
4594 f_foff = TREE_CHAIN (f_goff);
4596 /* We maintain separate pointers and offsets for floating-point
4597 and integer arguments, but we need similar code in both cases.
4600 TOP be the top of the register save area;
4601 OFF be the offset from TOP of the next register;
4602 ADDR_RTX be the address of the argument;
4603 RSIZE be the number of bytes used to store the argument
4604 when it's in the register save area;
4605 OSIZE be the number of bytes used to store it when it's
4606 in the stack overflow area; and
4607 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4609 The code we want is:
4611 1: off &= -rsize; // round down
4614 4: addr_rtx = top - off;
4619 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4620 10: addr_rtx = ovfl + PADDING;
4624 [1] and [9] can sometimes be optimized away. */
4626 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4629 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4630 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4632 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4634 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4637 /* When floating-point registers are saved to the stack,
4638 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4639 of the float's precision. */
4640 rsize = UNITS_PER_HWFPVALUE;
4642 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4643 (= PARM_BOUNDARY bits). This can be different from RSIZE
4646 (1) On 32-bit targets when TYPE is a structure such as:
4648 struct s { float f; };
4650 Such structures are passed in paired FPRs, so RSIZE
4651 will be 8 bytes. However, the structure only takes
4652 up 4 bytes of memory, so OSIZE will only be 4.
4654 (2) In combinations such as -mgp64 -msingle-float
4655 -fshort-double. Doubles passed in registers
4656 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4657 but those passed on the stack take up
4658 UNITS_PER_WORD bytes. */
4659 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4663 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4665 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4667 if (rsize > UNITS_PER_WORD)
4669 /* [1] Emit code for: off &= -rsize. */
4670 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4671 build_int_cst (NULL_TREE, -rsize));
4672 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4673 gimplify_and_add (t, pre_p);
4678 /* [2] Emit code to branch if off == 0. */
4679 t = build2 (NE_EXPR, boolean_type_node, off,
4680 build_int_cst (TREE_TYPE (off), 0));
4681 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4683 /* [5] Emit code for: off -= rsize. We do this as a form of
4684 post-increment not available to C. Also widen for the
4685 coming pointer arithmetic. */
4686 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4687 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4688 t = fold_convert (sizetype, t);
4689 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4691 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4692 the argument has RSIZE - SIZE bytes of leading padding. */
4693 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4694 if (BYTES_BIG_ENDIAN && rsize > size)
4696 u = size_int (rsize - size);
4697 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4699 COND_EXPR_THEN (addr) = t;
4701 if (osize > UNITS_PER_WORD)
4703 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4704 u = size_int (osize - 1);
4705 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4706 t = fold_convert (sizetype, t);
4707 u = size_int (-osize);
4708 t = build2 (BIT_AND_EXPR, sizetype, t, u);
4709 t = fold_convert (TREE_TYPE (ovfl), t);
4710 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4715 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4716 post-increment ovfl by osize. On big-endian machines,
4717 the argument has OSIZE - SIZE bytes of leading padding. */
4718 u = fold_convert (TREE_TYPE (ovfl),
4719 build_int_cst (NULL_TREE, osize));
4720 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4721 if (BYTES_BIG_ENDIAN && osize > size)
4723 u = size_int (osize - size);
4724 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4727 /* String [9] and [10,11] together. */
4729 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4730 COND_EXPR_ELSE (addr) = t;
4732 addr = fold_convert (build_pointer_type (type), addr);
4733 addr = build_va_arg_indirect_ref (addr);
4737 addr = build_va_arg_indirect_ref (addr);
4742 /* Return true if it is possible to use left/right accesses for a
4743 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4744 returning true, update *OP, *LEFT and *RIGHT as follows:
4746 *OP is a BLKmode reference to the whole field.
4748 *LEFT is a QImode reference to the first byte if big endian or
4749 the last byte if little endian. This address can be used in the
4750 left-side instructions (lwl, swl, ldl, sdl).
4752 *RIGHT is a QImode reference to the opposite end of the field and
4753 can be used in the patterning right-side instruction. */
4756 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4757 rtx *left, rtx *right)
4761 /* Check that the operand really is a MEM. Not all the extv and
4762 extzv predicates are checked. */
4766 /* Check that the size is valid. */
4767 if (width != 32 && (!TARGET_64BIT || width != 64))
4770 /* We can only access byte-aligned values. Since we are always passed
4771 a reference to the first byte of the field, it is not necessary to
4772 do anything with BITPOS after this check. */
4773 if (bitpos % BITS_PER_UNIT != 0)
4776 /* Reject aligned bitfields: we want to use a normal load or store
4777 instead of a left/right pair. */
4778 if (MEM_ALIGN (*op) >= width)
4781 /* Adjust *OP to refer to the whole field. This also has the effect
4782 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4783 *op = adjust_address (*op, BLKmode, 0);
4784 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4786 /* Get references to both ends of the field. We deliberately don't
4787 use the original QImode *OP for FIRST since the new BLKmode one
4788 might have a simpler address. */
4789 first = adjust_address (*op, QImode, 0);
4790 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4792 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4793 be the upper word and RIGHT the lower word. */
4794 if (TARGET_BIG_ENDIAN)
4795 *left = first, *right = last;
4797 *left = last, *right = first;
4803 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4804 Return true on success. We only handle cases where zero_extract is
4805 equivalent to sign_extract. */
4808 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4810 rtx left, right, temp;
4812 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4813 paradoxical word_mode subreg. This is the only case in which
4814 we allow the destination to be larger than the source. */
4815 if (GET_CODE (dest) == SUBREG
4816 && GET_MODE (dest) == DImode
4817 && SUBREG_BYTE (dest) == 0
4818 && GET_MODE (SUBREG_REG (dest)) == SImode)
4819 dest = SUBREG_REG (dest);
4821 /* After the above adjustment, the destination must be the same
4822 width as the source. */
4823 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4826 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4829 temp = gen_reg_rtx (GET_MODE (dest));
4830 if (GET_MODE (dest) == DImode)
4832 emit_insn (gen_mov_ldl (temp, src, left));
4833 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4837 emit_insn (gen_mov_lwl (temp, src, left));
4838 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4844 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4848 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4851 enum machine_mode mode;
4853 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4856 mode = mode_for_size (width, MODE_INT, 0);
4857 src = gen_lowpart (mode, src);
4861 emit_insn (gen_mov_sdl (dest, src, left));
4862 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4866 emit_insn (gen_mov_swl (dest, src, left));
4867 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4872 /* Return true if X is a MEM with the same size as MODE. */
4875 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4882 size = MEM_SIZE (x);
4883 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4886 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4887 source of an "ext" instruction or the destination of an "ins"
4888 instruction. OP must be a register operand and the following
4889 conditions must hold:
4891 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4892 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4893 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4895 Also reject lengths equal to a word as they are better handled
4896 by the move patterns. */
4899 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4901 HOST_WIDE_INT len, pos;
4903 if (!ISA_HAS_EXT_INS
4904 || !register_operand (op, VOIDmode)
4905 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4908 len = INTVAL (size);
4909 pos = INTVAL (position);
4911 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4912 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4918 /* Set up globals to generate code for the ISA or processor
4919 described by INFO. */
4922 mips_set_architecture (const struct mips_cpu_info *info)
4926 mips_arch_info = info;
4927 mips_arch = info->cpu;
4928 mips_isa = info->isa;
4933 /* Likewise for tuning. */
4936 mips_set_tune (const struct mips_cpu_info *info)
4940 mips_tune_info = info;
4941 mips_tune = info->cpu;
4945 /* Implement TARGET_HANDLE_OPTION. */
4948 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4953 if (strcmp (arg, "32") == 0)
4955 else if (strcmp (arg, "o64") == 0)
4957 else if (strcmp (arg, "n32") == 0)
4959 else if (strcmp (arg, "64") == 0)
4961 else if (strcmp (arg, "eabi") == 0)
4962 mips_abi = ABI_EABI;
4969 return mips_parse_cpu (arg) != 0;
4972 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4973 return mips_isa_info != 0;
4975 case OPT_mno_flush_func:
4976 mips_cache_flush_func = NULL;
4984 /* Set up the threshold for data to go into the small data area, instead
4985 of the normal data area, and detect any conflicts in the switches. */
4988 override_options (void)
4990 int i, start, regno;
4991 enum machine_mode mode;
4993 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4994 SUBTARGET_OVERRIDE_OPTIONS;
4997 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4999 /* The following code determines the architecture and register size.
5000 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5001 The GAS and GCC code should be kept in sync as much as possible. */
5003 if (mips_arch_string != 0)
5004 mips_set_architecture (mips_parse_cpu (mips_arch_string));
5006 if (mips_isa_info != 0)
5008 if (mips_arch_info == 0)
5009 mips_set_architecture (mips_isa_info);
5010 else if (mips_arch_info->isa != mips_isa_info->isa)
5011 error ("-%s conflicts with the other architecture options, "
5012 "which specify a %s processor",
5013 mips_isa_info->name,
5014 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
5017 if (mips_arch_info == 0)
5019 #ifdef MIPS_CPU_STRING_DEFAULT
5020 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
5022 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
5026 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
5027 error ("-march=%s is not compatible with the selected ABI",
5028 mips_arch_info->name);
5030 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5031 if (mips_tune_string != 0)
5032 mips_set_tune (mips_parse_cpu (mips_tune_string));
5034 if (mips_tune_info == 0)
5035 mips_set_tune (mips_arch_info);
5037 /* Set cost structure for the processor. */
5039 mips_cost = &mips_rtx_cost_optimize_size;
5041 mips_cost = &mips_rtx_cost_data[mips_tune];
5043 if ((target_flags_explicit & MASK_64BIT) != 0)
5045 /* The user specified the size of the integer registers. Make sure
5046 it agrees with the ABI and ISA. */
5047 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5048 error ("-mgp64 used with a 32-bit processor");
5049 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5050 error ("-mgp32 used with a 64-bit ABI");
5051 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5052 error ("-mgp64 used with a 32-bit ABI");
5056 /* Infer the integer register size from the ABI and processor.
5057 Restrict ourselves to 32-bit registers if that's all the
5058 processor has, or if the ABI cannot handle 64-bit registers. */
5059 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5060 target_flags &= ~MASK_64BIT;
5062 target_flags |= MASK_64BIT;
5065 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5067 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5068 only one right answer here. */
5069 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5070 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5071 else if (!TARGET_64BIT && TARGET_FLOAT64
5072 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
5073 error ("-mgp32 and -mfp64 can only be combined if the target"
5074 " supports the mfhc1 and mthc1 instructions");
5075 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5076 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5080 /* -msingle-float selects 32-bit float registers. Otherwise the
5081 float registers should be the same size as the integer ones. */
5082 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5083 target_flags |= MASK_FLOAT64;
5085 target_flags &= ~MASK_FLOAT64;
5088 /* End of code shared with GAS. */
5090 if ((target_flags_explicit & MASK_LONG64) == 0)
5092 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5093 target_flags |= MASK_LONG64;
5095 target_flags &= ~MASK_LONG64;
5098 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5099 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
5101 /* For some configurations, it is useful to have -march control
5102 the default setting of MASK_SOFT_FLOAT. */
5103 switch ((int) mips_arch)
5105 case PROCESSOR_R4100:
5106 case PROCESSOR_R4111:
5107 case PROCESSOR_R4120:
5108 case PROCESSOR_R4130:
5109 target_flags |= MASK_SOFT_FLOAT;
5113 target_flags &= ~MASK_SOFT_FLOAT;
5119 flag_pcc_struct_return = 0;
5121 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
5123 /* If neither -mbranch-likely nor -mno-branch-likely was given
5124 on the command line, set MASK_BRANCHLIKELY based on the target
5127 By default, we enable use of Branch Likely instructions on
5128 all architectures which support them with the following
5129 exceptions: when creating MIPS32 or MIPS64 code, and when
5130 tuning for architectures where their use tends to hurt
5133 The MIPS32 and MIPS64 architecture specifications say "Software
5134 is strongly encouraged to avoid use of Branch Likely
5135 instructions, as they will be removed from a future revision
5136 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5137 issue those instructions unless instructed to do so by
5139 if (ISA_HAS_BRANCHLIKELY
5140 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
5141 && !(TUNE_MIPS5500 || TUNE_SB1))
5142 target_flags |= MASK_BRANCHLIKELY;
5144 target_flags &= ~MASK_BRANCHLIKELY;
5146 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
5147 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
5149 /* The effect of -mabicalls isn't defined for the EABI. */
5150 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
5152 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
5153 target_flags &= ~MASK_ABICALLS;
5156 if (TARGET_ABICALLS)
5158 /* We need to set flag_pic for executables as well as DSOs
5159 because we may reference symbols that are not defined in
5160 the final executable. (MIPS does not use things like
5161 copy relocs, for example.)
5163 Also, there is a body of code that uses __PIC__ to distinguish
5164 between -mabicalls and -mno-abicalls code. */
5166 if (mips_section_threshold > 0)
5167 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
5170 if (TARGET_VXWORKS_RTP && mips_section_threshold > 0)
5171 warning (0, "-G and -mrtp are incompatible");
5173 /* mips_split_addresses is a half-way house between explicit
5174 relocations and the traditional assembler macros. It can
5175 split absolute 32-bit symbolic constants into a high/lo_sum
5176 pair but uses macros for other sorts of access.
5178 Like explicit relocation support for REL targets, it relies
5179 on GNU extensions in the assembler and the linker.
5181 Although this code should work for -O0, it has traditionally
5182 been treated as an optimization. */
5183 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
5184 && optimize && !flag_pic
5185 && !ABI_HAS_64BIT_SYMBOLS)
5186 mips_split_addresses = 1;
5188 mips_split_addresses = 0;
5190 /* -mvr4130-align is a "speed over size" optimization: it usually produces
5191 faster code, but at the expense of more nops. Enable it at -O3 and
5193 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
5194 target_flags |= MASK_VR4130_ALIGN;
5196 /* When compiling for the mips16, we cannot use floating point. We
5197 record the original hard float value in mips16_hard_float. */
5200 if (TARGET_SOFT_FLOAT)
5201 mips16_hard_float = 0;
5203 mips16_hard_float = 1;
5204 target_flags |= MASK_SOFT_FLOAT;
5206 /* Don't run the scheduler before reload, since it tends to
5207 increase register pressure. */
5208 flag_schedule_insns = 0;
5210 /* Don't do hot/cold partitioning. The constant layout code expects
5211 the whole function to be in a single section. */
5212 flag_reorder_blocks_and_partition = 0;
5214 /* Silently disable -mexplicit-relocs since it doesn't apply
5215 to mips16 code. Even so, it would overly pedantic to warn
5216 about "-mips16 -mexplicit-relocs", especially given that
5217 we use a %gprel() operator. */
5218 target_flags &= ~MASK_EXPLICIT_RELOCS;
5221 /* When using explicit relocs, we call dbr_schedule from within
5223 if (TARGET_EXPLICIT_RELOCS)
5225 mips_flag_delayed_branch = flag_delayed_branch;
5226 flag_delayed_branch = 0;
5229 #ifdef MIPS_TFMODE_FORMAT
5230 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
5233 /* Make sure that the user didn't turn off paired single support when
5234 MIPS-3D support is requested. */
5235 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
5236 && !TARGET_PAIRED_SINGLE_FLOAT)
5237 error ("-mips3d requires -mpaired-single");
5239 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
5241 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
5243 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
5244 and TARGET_HARD_FLOAT are both true. */
5245 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
5246 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
5248 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
5250 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
5251 error ("-mips3d/-mpaired-single must be used with -mips64");
5253 /* If TARGET_DSPR2, enable MASK_DSP. */
5255 target_flags |= MASK_DSP;
5257 if (TARGET_MIPS16 && TARGET_DSP)
5258 error ("-mips16 and -mdsp cannot be used together");
5260 mips_print_operand_punct['?'] = 1;
5261 mips_print_operand_punct['#'] = 1;
5262 mips_print_operand_punct['/'] = 1;
5263 mips_print_operand_punct['&'] = 1;
5264 mips_print_operand_punct['!'] = 1;
5265 mips_print_operand_punct['*'] = 1;
5266 mips_print_operand_punct['@'] = 1;
5267 mips_print_operand_punct['.'] = 1;
5268 mips_print_operand_punct['('] = 1;
5269 mips_print_operand_punct[')'] = 1;
5270 mips_print_operand_punct['['] = 1;
5271 mips_print_operand_punct[']'] = 1;
5272 mips_print_operand_punct['<'] = 1;
5273 mips_print_operand_punct['>'] = 1;
5274 mips_print_operand_punct['{'] = 1;
5275 mips_print_operand_punct['}'] = 1;
5276 mips_print_operand_punct['^'] = 1;
5277 mips_print_operand_punct['$'] = 1;
5278 mips_print_operand_punct['+'] = 1;
5279 mips_print_operand_punct['~'] = 1;
5281 /* Set up array to map GCC register number to debug register number.
5282 Ignore the special purpose register numbers. */
5284 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5285 mips_dbx_regno[i] = -1;
5287 start = GP_DBX_FIRST - GP_REG_FIRST;
5288 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5289 mips_dbx_regno[i] = i + start;
5291 start = FP_DBX_FIRST - FP_REG_FIRST;
5292 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5293 mips_dbx_regno[i] = i + start;
5295 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5296 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5298 /* Set up array giving whether a given register can hold a given mode. */
5300 for (mode = VOIDmode;
5301 mode != MAX_MACHINE_MODE;
5302 mode = (enum machine_mode) ((int)mode + 1))
5304 register int size = GET_MODE_SIZE (mode);
5305 register enum mode_class class = GET_MODE_CLASS (mode);
5307 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5311 if (mode == CCV2mode)
5314 && (regno - ST_REG_FIRST) % 2 == 0);
5316 else if (mode == CCV4mode)
5319 && (regno - ST_REG_FIRST) % 4 == 0);
5321 else if (mode == CCmode)
5324 temp = (regno == FPSW_REGNUM);
5326 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5327 || FP_REG_P (regno));
5330 else if (GP_REG_P (regno))
5331 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5333 else if (FP_REG_P (regno))
5334 temp = ((((regno % MAX_FPRS_PER_FMT) == 0)
5335 || (MIN_FPRS_PER_FMT == 1
5336 && size <= UNITS_PER_FPREG))
5337 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5338 || class == MODE_VECTOR_FLOAT)
5339 && size <= UNITS_PER_FPVALUE)
5340 /* Allow integer modes that fit into a single
5341 register. We need to put integers into FPRs
5342 when using instructions like cvt and trunc.
5343 We can't allow sizes smaller than a word,
5344 the FPU has no appropriate load/store
5345 instructions for those. */
5346 || (class == MODE_INT
5347 && size >= MIN_UNITS_PER_WORD
5348 && size <= UNITS_PER_FPREG)
5349 /* Allow TFmode for CCmode reloads. */
5350 || (ISA_HAS_8CC && mode == TFmode)));
5352 else if (ACC_REG_P (regno))
5353 temp = (INTEGRAL_MODE_P (mode)
5354 && (size <= UNITS_PER_WORD
5355 || (ACC_HI_REG_P (regno)
5356 && size == 2 * UNITS_PER_WORD)));
5358 else if (ALL_COP_REG_P (regno))
5359 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5363 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5367 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5368 initialized yet, so we can't use that here. */
5369 gpr_mode = TARGET_64BIT ? DImode : SImode;
5371 /* Provide default values for align_* for 64-bit targets. */
5372 if (TARGET_64BIT && !TARGET_MIPS16)
5374 if (align_loops == 0)
5376 if (align_jumps == 0)
5378 if (align_functions == 0)
5379 align_functions = 8;
5382 /* Function to allocate machine-dependent function status. */
5383 init_machine_status = &mips_init_machine_status;
5385 if (ABI_HAS_64BIT_SYMBOLS)
5387 if (TARGET_EXPLICIT_RELOCS)
5389 mips_split_p[SYMBOL_64_HIGH] = true;
5390 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5391 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5393 mips_split_p[SYMBOL_64_MID] = true;
5394 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5395 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5397 mips_split_p[SYMBOL_64_LOW] = true;
5398 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5399 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5401 mips_split_p[SYMBOL_GENERAL] = true;
5402 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5407 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5409 mips_split_p[SYMBOL_GENERAL] = true;
5410 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5411 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5417 /* The high part is provided by a pseudo copy of $gp. */
5418 mips_split_p[SYMBOL_SMALL_DATA] = true;
5419 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5422 if (TARGET_EXPLICIT_RELOCS)
5424 /* Small data constants are kept whole until after reload,
5425 then lowered by mips_rewrite_small_data. */
5426 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5428 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
5431 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5432 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
5436 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5437 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
5442 /* The HIGH and LO_SUM are matched by special .md patterns. */
5443 mips_split_p[SYMBOL_GOT_DISP] = true;
5445 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
5446 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
5447 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
5449 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5450 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5451 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5456 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
5458 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
5459 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5465 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5466 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5467 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5470 /* Thread-local relocation operators. */
5471 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5472 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5473 mips_split_p[SYMBOL_DTPREL] = 1;
5474 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5475 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5476 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5477 mips_split_p[SYMBOL_TPREL] = 1;
5478 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5479 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5481 mips_lo_relocs[SYMBOL_HALF] = "%half(";
5483 /* We don't have a thread pointer access instruction on MIPS16, or
5484 appropriate TLS relocations. */
5486 targetm.have_tls = false;
5488 /* Default to working around R4000 errata only if the processor
5489 was selected explicitly. */
5490 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5491 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5492 target_flags |= MASK_FIX_R4000;
5494 /* Default to working around R4400 errata only if the processor
5495 was selected explicitly. */
5496 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5497 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5498 target_flags |= MASK_FIX_R4400;
5501 /* Implement CONDITIONAL_REGISTER_USAGE. */
5504 mips_conditional_register_usage (void)
5510 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5511 fixed_regs[regno] = call_used_regs[regno] = 1;
5513 if (!TARGET_HARD_FLOAT)
5517 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5518 fixed_regs[regno] = call_used_regs[regno] = 1;
5519 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5520 fixed_regs[regno] = call_used_regs[regno] = 1;
5522 else if (! ISA_HAS_8CC)
5526 /* We only have a single condition code register. We
5527 implement this by hiding all the condition code registers,
5528 and generating RTL that refers directly to ST_REG_FIRST. */
5529 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5530 fixed_regs[regno] = call_used_regs[regno] = 1;
5532 /* In mips16 mode, we permit the $t temporary registers to be used
5533 for reload. We prohibit the unused $s registers, since they
5534 are caller saved, and saving them via a mips16 register would
5535 probably waste more time than just reloading the value. */
5538 fixed_regs[18] = call_used_regs[18] = 1;
5539 fixed_regs[19] = call_used_regs[19] = 1;
5540 fixed_regs[20] = call_used_regs[20] = 1;
5541 fixed_regs[21] = call_used_regs[21] = 1;
5542 fixed_regs[22] = call_used_regs[22] = 1;
5543 fixed_regs[23] = call_used_regs[23] = 1;
5544 fixed_regs[26] = call_used_regs[26] = 1;
5545 fixed_regs[27] = call_used_regs[27] = 1;
5546 fixed_regs[30] = call_used_regs[30] = 1;
5548 /* fp20-23 are now caller saved. */
5549 if (mips_abi == ABI_64)
5552 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5553 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5555 /* Odd registers from fp21 to fp31 are now caller saved. */
5556 if (mips_abi == ABI_N32)
5559 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5560 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5564 /* Allocate a chunk of memory for per-function machine-dependent data. */
5565 static struct machine_function *
5566 mips_init_machine_status (void)
5568 return ((struct machine_function *)
5569 ggc_alloc_cleared (sizeof (struct machine_function)));
5572 /* On the mips16, we want to allocate $24 (T_REG) before other
5573 registers for instructions for which it is possible. This helps
5574 avoid shuffling registers around in order to set up for an xor,
5575 encouraging the compiler to use a cmp instead. */
5578 mips_order_regs_for_local_alloc (void)
5582 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5583 reg_alloc_order[i] = i;
5587 /* It really doesn't matter where we put register 0, since it is
5588 a fixed register anyhow. */
5589 reg_alloc_order[0] = 24;
5590 reg_alloc_order[24] = 0;
5595 /* The MIPS debug format wants all automatic variables and arguments
5596 to be in terms of the virtual frame pointer (stack pointer before
5597 any adjustment in the function), while the MIPS 3.0 linker wants
5598 the frame pointer to be the stack pointer after the initial
5599 adjustment. So, we do the adjustment here. The arg pointer (which
5600 is eliminated) points to the virtual frame pointer, while the frame
5601 pointer (which may be eliminated) points to the stack pointer after
5602 the initial adjustments. */
5605 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5607 rtx offset2 = const0_rtx;
5608 rtx reg = eliminate_constant_term (addr, &offset2);
5611 offset = INTVAL (offset2);
5613 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5614 || reg == hard_frame_pointer_rtx)
5616 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5617 ? compute_frame_size (get_frame_size ())
5618 : cfun->machine->frame.total_size;
5620 /* MIPS16 frame is smaller */
5621 if (frame_pointer_needed && TARGET_MIPS16)
5622 frame_size -= cfun->machine->frame.args_size;
5624 offset = offset - frame_size;
5627 /* sdbout_parms does not want this to crash for unrecognized cases. */
5629 else if (reg != arg_pointer_rtx)
5630 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5637 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5639 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5640 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5641 'h' OP is HIGH, prints %hi(X),
5642 'd' output integer constant in decimal,
5643 'z' if the operand is 0, use $0 instead of normal operand.
5644 'D' print second part of double-word register or memory operand.
5645 'L' print low-order register of double-word register operand.
5646 'M' print high-order register of double-word register operand.
5647 'C' print part of opcode for a branch condition.
5648 'F' print part of opcode for a floating-point branch condition.
5649 'N' print part of opcode for a branch condition, inverted.
5650 'W' print part of opcode for a floating-point branch condition, inverted.
5651 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5652 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5653 't' like 'T', but with the EQ/NE cases reversed
5654 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5655 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5656 'R' print the reloc associated with LO_SUM
5657 'q' print DSP accumulator registers
5659 The punctuation characters are:
5661 '(' Turn on .set noreorder
5662 ')' Turn on .set reorder
5663 '[' Turn on .set noat
5665 '<' Turn on .set nomacro
5666 '>' Turn on .set macro
5667 '{' Turn on .set volatile (not GAS)
5668 '}' Turn on .set novolatile (not GAS)
5669 '&' Turn on .set noreorder if filling delay slots
5670 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5671 '!' Turn on .set nomacro if filling delay slots
5672 '#' Print nop if in a .set noreorder section.
5673 '/' Like '#', but does nothing within a delayed branch sequence
5674 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5675 '@' Print the name of the assembler temporary register (at or $1).
5676 '.' Print the name of the register with a hard-wired zero (zero or $0).
5677 '^' Print the name of the pic call-through register (t9 or $25).
5678 '$' Print the name of the stack pointer register (sp or $29).
5679 '+' Print the name of the gp register (usually gp or $28).
5680 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5683 print_operand (FILE *file, rtx op, int letter)
5685 register enum rtx_code code;
5687 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5692 if (mips_branch_likely)
5697 fputs (reg_names [GP_REG_FIRST + 1], file);
5701 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5705 fputs (reg_names [GP_REG_FIRST + 0], file);
5709 fputs (reg_names[STACK_POINTER_REGNUM], file);
5713 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5717 if (final_sequence != 0 && set_noreorder++ == 0)
5718 fputs (".set\tnoreorder\n\t", file);
5722 if (final_sequence != 0)
5724 if (set_noreorder++ == 0)
5725 fputs (".set\tnoreorder\n\t", file);
5727 if (set_nomacro++ == 0)
5728 fputs (".set\tnomacro\n\t", file);
5733 if (final_sequence != 0 && set_nomacro++ == 0)
5734 fputs ("\n\t.set\tnomacro", file);
5738 if (set_noreorder != 0)
5739 fputs ("\n\tnop", file);
5743 /* Print an extra newline so that the delayed insn is separated
5744 from the following ones. This looks neater and is consistent
5745 with non-nop delayed sequences. */
5746 if (set_noreorder != 0 && final_sequence == 0)
5747 fputs ("\n\tnop\n", file);
5751 if (set_noreorder++ == 0)
5752 fputs (".set\tnoreorder\n\t", file);
5756 if (set_noreorder == 0)
5757 error ("internal error: %%) found without a %%( in assembler pattern");
5759 else if (--set_noreorder == 0)
5760 fputs ("\n\t.set\treorder", file);
5765 if (set_noat++ == 0)
5766 fputs (".set\tnoat\n\t", file);
5771 error ("internal error: %%] found without a %%[ in assembler pattern");
5772 else if (--set_noat == 0)
5773 fputs ("\n\t.set\tat", file);
5778 if (set_nomacro++ == 0)
5779 fputs (".set\tnomacro\n\t", file);
5783 if (set_nomacro == 0)
5784 error ("internal error: %%> found without a %%< in assembler pattern");
5785 else if (--set_nomacro == 0)
5786 fputs ("\n\t.set\tmacro", file);
5791 if (set_volatile++ == 0)
5792 fputs ("#.set\tvolatile\n\t", file);
5796 if (set_volatile == 0)
5797 error ("internal error: %%} found without a %%{ in assembler pattern");
5798 else if (--set_volatile == 0)
5799 fputs ("\n\t#.set\tnovolatile", file);
5805 if (align_labels_log > 0)
5806 ASM_OUTPUT_ALIGN (file, align_labels_log);
5811 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5820 error ("PRINT_OPERAND null pointer");
5824 code = GET_CODE (op);
5829 case EQ: fputs ("eq", file); break;
5830 case NE: fputs ("ne", file); break;
5831 case GT: fputs ("gt", file); break;
5832 case GE: fputs ("ge", file); break;
5833 case LT: fputs ("lt", file); break;
5834 case LE: fputs ("le", file); break;
5835 case GTU: fputs ("gtu", file); break;
5836 case GEU: fputs ("geu", file); break;
5837 case LTU: fputs ("ltu", file); break;
5838 case LEU: fputs ("leu", file); break;
5840 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5843 else if (letter == 'N')
5846 case EQ: fputs ("ne", file); break;
5847 case NE: fputs ("eq", file); break;
5848 case GT: fputs ("le", file); break;
5849 case GE: fputs ("lt", file); break;
5850 case LT: fputs ("ge", file); break;
5851 case LE: fputs ("gt", file); break;
5852 case GTU: fputs ("leu", file); break;
5853 case GEU: fputs ("ltu", file); break;
5854 case LTU: fputs ("geu", file); break;
5855 case LEU: fputs ("gtu", file); break;
5857 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5860 else if (letter == 'F')
5863 case EQ: fputs ("c1f", file); break;
5864 case NE: fputs ("c1t", file); break;
5866 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5869 else if (letter == 'W')
5872 case EQ: fputs ("c1t", file); break;
5873 case NE: fputs ("c1f", file); break;
5875 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5878 else if (letter == 'h')
5880 if (GET_CODE (op) == HIGH)
5883 print_operand_reloc (file, op, mips_hi_relocs);
5886 else if (letter == 'R')
5887 print_operand_reloc (file, op, mips_lo_relocs);
5889 else if (letter == 'Y')
5891 if (GET_CODE (op) == CONST_INT
5892 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5893 < ARRAY_SIZE (mips_fp_conditions)))
5894 fputs (mips_fp_conditions[INTVAL (op)], file);
5896 output_operand_lossage ("invalid %%Y value");
5899 else if (letter == 'Z')
5903 print_operand (file, op, 0);
5908 else if (letter == 'q')
5913 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5915 regnum = REGNO (op);
5916 if (MD_REG_P (regnum))
5917 fprintf (file, "$ac0");
5918 else if (DSP_ACC_REG_P (regnum))
5919 fprintf (file, "$ac%c", reg_names[regnum][3]);
5921 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5924 else if (code == REG || code == SUBREG)
5926 register int regnum;
5929 regnum = REGNO (op);
5931 regnum = true_regnum (op);
5933 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5934 || (letter == 'L' && WORDS_BIG_ENDIAN)
5938 fprintf (file, "%s", reg_names[regnum]);
5941 else if (code == MEM)
5944 output_address (plus_constant (XEXP (op, 0), 4));
5946 output_address (XEXP (op, 0));
5949 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5950 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5952 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5953 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5955 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5956 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5958 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5959 fputs (reg_names[GP_REG_FIRST], file);
5961 else if (letter == 'd' || letter == 'x' || letter == 'X')
5962 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5964 else if (letter == 'T' || letter == 't')
5966 int truth = (code == NE) == (letter == 'T');
5967 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5970 else if (CONST_GP_P (op))
5971 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5974 output_addr_const (file, op);
5978 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5979 RELOCS is the array of relocations to use. */
5982 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5984 enum mips_symbol_type symbol_type;
5988 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5989 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5991 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5992 split_const (op, &base, &offset);
5993 if (UNSPEC_ADDRESS_P (base))
5994 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
5996 fputs (relocs[symbol_type], file);
5997 output_addr_const (file, op);
5998 for (p = relocs[symbol_type]; *p != 0; p++)
6003 /* Output address operand X to FILE. */
6006 print_operand_address (FILE *file, rtx x)
6008 struct mips_address_info addr;
6010 if (mips_classify_address (&addr, x, word_mode, true))
6014 print_operand (file, addr.offset, 0);
6015 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6018 case ADDRESS_LO_SUM:
6019 print_operand (file, addr.offset, 'R');
6020 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6023 case ADDRESS_CONST_INT:
6024 output_addr_const (file, x);
6025 fprintf (file, "(%s)", reg_names[0]);
6028 case ADDRESS_SYMBOLIC:
6029 output_addr_const (file, x);
6035 /* When using assembler macros, keep track of all of small-data externs
6036 so that mips_file_end can emit the appropriate declarations for them.
6038 In most cases it would be safe (though pointless) to emit .externs
6039 for other symbols too. One exception is when an object is within
6040 the -G limit but declared by the user to be in a section other
6041 than .sbss or .sdata. */
6044 mips_output_external (FILE *file, tree decl, const char *name)
6046 default_elf_asm_output_external (file, decl, name);
6048 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6049 set in order to avoid putting out names that are never really
6051 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6053 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6055 fputs ("\t.extern\t", file);
6056 assemble_name (file, name);
6057 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6058 int_size_in_bytes (TREE_TYPE (decl)));
6060 else if (TARGET_IRIX
6061 && mips_abi == ABI_32
6062 && TREE_CODE (decl) == FUNCTION_DECL)
6064 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6065 `.global name .text' directive for every used but
6066 undefined function. If we don't, the linker may perform
6067 an optimization (skipping over the insns that set $gp)
6068 when it is unsafe. */
6069 fputs ("\t.globl ", file);
6070 assemble_name (file, name);
6071 fputs (" .text\n", file);
6076 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6077 put out a MIPS ECOFF file and a stab. */
6080 mips_output_filename (FILE *stream, const char *name)
6083 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6085 if (write_symbols == DWARF2_DEBUG)
6087 else if (mips_output_filename_first_time)
6089 mips_output_filename_first_time = 0;
6090 num_source_filenames += 1;
6091 current_function_file = name;
6092 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6093 output_quoted_string (stream, name);
6094 putc ('\n', stream);
6097 /* If we are emitting stabs, let dbxout.c handle this (except for
6098 the mips_output_filename_first_time case). */
6099 else if (write_symbols == DBX_DEBUG)
6102 else if (name != current_function_file
6103 && strcmp (name, current_function_file) != 0)
6105 num_source_filenames += 1;
6106 current_function_file = name;
6107 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6108 output_quoted_string (stream, name);
6109 putc ('\n', stream);
6113 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6114 that should be written before the opening quote, such as "\t.ascii\t"
6115 for real string data or "\t# " for a comment. */
6118 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
6123 register const unsigned char *string =
6124 (const unsigned char *)string_param;
6126 fprintf (stream, "%s\"", prefix);
6127 for (i = 0; i < len; i++)
6129 register int c = string[i];
6133 if (c == '\\' || c == '\"')
6135 putc ('\\', stream);
6143 fprintf (stream, "\\%03o", c);
6147 if (cur_pos > 72 && i+1 < len)
6150 fprintf (stream, "\"\n%s\"", prefix);
6153 fprintf (stream, "\"\n");
6156 /* Implement TARGET_ASM_FILE_START. */
6159 mips_file_start (void)
6161 default_file_start ();
6165 /* Generate a special section to describe the ABI switches used to
6166 produce the resultant binary. This used to be done by the assembler
6167 setting bits in the ELF header's flags field, but we have run out of
6168 bits. GDB needs this information in order to be able to correctly
6169 debug these binaries. See the function mips_gdbarch_init() in
6170 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6171 causes unnecessary IRIX 6 ld warnings. */
6172 const char * abi_string = NULL;
6176 case ABI_32: abi_string = "abi32"; break;
6177 case ABI_N32: abi_string = "abiN32"; break;
6178 case ABI_64: abi_string = "abi64"; break;
6179 case ABI_O64: abi_string = "abiO64"; break;
6180 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6184 /* Note - we use fprintf directly rather than calling switch_to_section
6185 because in this way we can avoid creating an allocated section. We
6186 do not want this section to take up any space in the running
6188 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
6190 /* There is no ELF header flag to distinguish long32 forms of the
6191 EABI from long64 forms. Emit a special section to help tools
6192 such as GDB. Do the same for o64, which is sometimes used with
6194 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
6195 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
6196 TARGET_LONG64 ? 64 : 32);
6198 /* Restore the default section. */
6199 fprintf (asm_out_file, "\t.previous\n");
6201 #ifdef HAVE_AS_GNU_ATTRIBUTE
6202 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
6203 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
6207 /* Generate the pseudo ops that System V.4 wants. */
6208 if (TARGET_ABICALLS)
6209 fprintf (asm_out_file, "\t.abicalls\n");
6212 fprintf (asm_out_file, "\t.set\tmips16\n");
6214 if (flag_verbose_asm)
6215 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6217 mips_section_threshold, mips_arch_info->name, mips_isa);
6220 #ifdef BSS_SECTION_ASM_OP
6221 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6222 in the use of sbss. */
6225 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6226 unsigned HOST_WIDE_INT size, int align)
6228 extern tree last_assemble_variable_decl;
6230 if (mips_in_small_data_p (decl))
6231 switch_to_section (get_named_section (NULL, ".sbss", 0));
6233 switch_to_section (bss_section);
6234 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6235 last_assemble_variable_decl = decl;
6236 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6237 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6241 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6242 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6245 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6246 unsigned HOST_WIDE_INT size,
6249 /* If the target wants uninitialized const declarations in
6250 .rdata then don't put them in .comm. */
6251 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6252 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6253 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6255 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6256 targetm.asm_out.globalize_label (stream, name);
6258 switch_to_section (readonly_data_section);
6259 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6260 mips_declare_object (stream, name, "",
6261 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6265 mips_declare_common_object (stream, name, "\n\t.comm\t",
6269 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6270 NAME is the name of the object and ALIGN is the required alignment
6271 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6272 alignment argument. */
6275 mips_declare_common_object (FILE *stream, const char *name,
6276 const char *init_string,
6277 unsigned HOST_WIDE_INT size,
6278 unsigned int align, bool takes_alignment_p)
6280 if (!takes_alignment_p)
6282 size += (align / BITS_PER_UNIT) - 1;
6283 size -= size % (align / BITS_PER_UNIT);
6284 mips_declare_object (stream, name, init_string,
6285 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6288 mips_declare_object (stream, name, init_string,
6289 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6290 size, align / BITS_PER_UNIT);
6293 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6294 macros, mark the symbol as written so that mips_file_end won't emit an
6295 .extern for it. STREAM is the output file, NAME is the name of the
6296 symbol, INIT_STRING is the string that should be written before the
6297 symbol and FINAL_STRING is the string that should be written after it.
6298 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6301 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6302 const char *final_string, ...)
6306 fputs (init_string, stream);
6307 assemble_name (stream, name);
6308 va_start (ap, final_string);
6309 vfprintf (stream, final_string, ap);
6312 if (!TARGET_EXPLICIT_RELOCS)
6314 tree name_tree = get_identifier (name);
6315 TREE_ASM_WRITTEN (name_tree) = 1;
6319 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6320 extern int size_directive_output;
6322 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6323 definitions except that it uses mips_declare_object() to emit the label. */
6326 mips_declare_object_name (FILE *stream, const char *name,
6327 tree decl ATTRIBUTE_UNUSED)
6329 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6330 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6333 size_directive_output = 0;
6334 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6338 size_directive_output = 1;
6339 size = int_size_in_bytes (TREE_TYPE (decl));
6340 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6343 mips_declare_object (stream, name, "", ":\n");
6346 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6349 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6353 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6354 if (!flag_inhibit_size_directive
6355 && DECL_SIZE (decl) != 0
6356 && !at_end && top_level
6357 && DECL_INITIAL (decl) == error_mark_node
6358 && !size_directive_output)
6362 size_directive_output = 1;
6363 size = int_size_in_bytes (TREE_TYPE (decl));
6364 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6369 /* Return true if X is a small data address that can be rewritten
6373 mips_rewrite_small_data_p (rtx x)
6375 enum mips_symbol_type symbol_type;
6377 return (TARGET_EXPLICIT_RELOCS
6378 && mips_symbolic_constant_p (x, &symbol_type)
6379 && symbol_type == SYMBOL_SMALL_DATA);
6383 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6386 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6388 if (GET_CODE (*loc) == LO_SUM)
6391 return mips_rewrite_small_data_p (*loc);
6394 /* Return true if OP refers to small data symbols directly, not through
6398 mips_small_data_pattern_p (rtx op)
6400 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6403 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6406 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6408 if (mips_rewrite_small_data_p (*loc))
6409 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6411 if (GET_CODE (*loc) == LO_SUM)
6417 /* If possible, rewrite OP so that it refers to small data using
6418 explicit relocations. */
6421 mips_rewrite_small_data (rtx op)
6423 op = copy_insn (op);
6424 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6428 /* Return true if the current function has an insn that implicitly
6432 mips_function_has_gp_insn (void)
6434 /* Don't bother rechecking if we found one last time. */
6435 if (!cfun->machine->has_gp_insn_p)
6439 push_topmost_sequence ();
6440 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6442 && GET_CODE (PATTERN (insn)) != USE
6443 && GET_CODE (PATTERN (insn)) != CLOBBER
6444 && (get_attr_got (insn) != GOT_UNSET
6445 || small_data_pattern (PATTERN (insn), VOIDmode)))
6447 pop_topmost_sequence ();
6449 cfun->machine->has_gp_insn_p = (insn != 0);
6451 return cfun->machine->has_gp_insn_p;
6455 /* Return the register that should be used as the global pointer
6456 within this function. Return 0 if the function doesn't need
6457 a global pointer. */
6460 mips_global_pointer (void)
6464 /* $gp is always available unless we're using a GOT. */
6465 if (!TARGET_USE_GOT)
6466 return GLOBAL_POINTER_REGNUM;
6468 /* We must always provide $gp when it is used implicitly. */
6469 if (!TARGET_EXPLICIT_RELOCS)
6470 return GLOBAL_POINTER_REGNUM;
6472 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6474 if (current_function_profile)
6475 return GLOBAL_POINTER_REGNUM;
6477 /* If the function has a nonlocal goto, $gp must hold the correct
6478 global pointer for the target function. */
6479 if (current_function_has_nonlocal_goto)
6480 return GLOBAL_POINTER_REGNUM;
6482 /* If the gp is never referenced, there's no need to initialize it.
6483 Note that reload can sometimes introduce constant pool references
6484 into a function that otherwise didn't need them. For example,
6485 suppose we have an instruction like:
6487 (set (reg:DF R1) (float:DF (reg:SI R2)))
6489 If R2 turns out to be constant such as 1, the instruction may have a
6490 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6491 using this constant if R2 doesn't get allocated to a register.
6493 In cases like these, reload will have added the constant to the pool
6494 but no instruction will yet refer to it. */
6495 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
6496 && !current_function_uses_const_pool
6497 && !mips_function_has_gp_insn ())
6500 /* We need a global pointer, but perhaps we can use a call-clobbered
6501 register instead of $gp. */
6502 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
6503 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6504 if (!df_regs_ever_live_p (regno)
6505 && call_used_regs[regno]
6506 && !fixed_regs[regno]
6507 && regno != PIC_FUNCTION_ADDR_REGNUM)
6510 return GLOBAL_POINTER_REGNUM;
6514 /* Return true if the function return value MODE will get returned in a
6515 floating-point register. */
6518 mips_return_mode_in_fpr_p (enum machine_mode mode)
6520 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
6521 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
6522 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6523 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
6526 /* Return a two-character string representing a function floating-point
6527 return mode, used to name MIPS16 function stubs. */
6530 mips16_call_stub_mode_suffix (enum machine_mode mode)
6534 else if (mode == DFmode)
6536 else if (mode == SCmode)
6538 else if (mode == DCmode)
6540 else if (mode == V2SFmode)
6546 /* Return true if the current function returns its value in a floating-point
6547 register in MIPS16 mode. */
6550 mips16_cfun_returns_in_fpr_p (void)
6552 tree return_type = DECL_RESULT (current_function_decl);
6553 return (mips16_hard_float
6554 && !aggregate_value_p (return_type, current_function_decl)
6555 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
6559 /* Return true if the current function must save REGNO. */
6562 mips_save_reg_p (unsigned int regno)
6564 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
6565 if we have not chosen a call-clobbered substitute. */
6566 if (regno == GLOBAL_POINTER_REGNUM)
6567 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
6569 /* Check call-saved registers. */
6570 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
6573 /* Save both registers in an FPR pair if either one is used. This is
6574 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
6575 register to be used without the even register. */
6576 if (FP_REG_P (regno)
6577 && MAX_FPRS_PER_FMT == 2
6578 && df_regs_ever_live_p (regno + 1)
6579 && !call_used_regs[regno + 1])
6582 /* We need to save the old frame pointer before setting up a new one. */
6583 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6586 /* We need to save the incoming return address if it is ever clobbered
6587 within the function. */
6588 if (regno == GP_REG_FIRST + 31 && df_regs_ever_live_p (regno))
6593 /* $18 is a special case in mips16 code. It may be used to call
6594 a function which returns a floating point value, but it is
6595 marked in call_used_regs. */
6596 if (regno == GP_REG_FIRST + 18 && df_regs_ever_live_p (regno))
6599 /* $31 is also a special case. It will be used to copy a return
6600 value into the floating point registers if the return value is
6602 if (regno == GP_REG_FIRST + 31
6603 && mips16_cfun_returns_in_fpr_p ())
6610 /* Return the index of the lowest X in the range [0, SIZE) for which
6611 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
6614 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
6619 for (i = 0; i < size; i++)
6620 if (BITSET_P (mask, regs[i]))
6626 /* *MASK_PTR is a mask of general purpose registers and *GP_REG_SIZE_PTR
6627 is the number of bytes that they occupy. If *MASK_PTR contains REGS[X]
6628 for some X in [0, SIZE), adjust *MASK_PTR and *GP_REG_SIZE_PTR so that
6629 the same is true for all indexes (X, SIZE). */
6632 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
6633 unsigned int size, HOST_WIDE_INT *gp_reg_size_ptr)
6637 i = mips16e_find_first_register (*mask_ptr, regs, size);
6638 for (i++; i < size; i++)
6639 if (!BITSET_P (*mask_ptr, regs[i]))
6641 *gp_reg_size_ptr += GET_MODE_SIZE (gpr_mode);
6642 *mask_ptr |= 1 << regs[i];
6646 /* Return the bytes needed to compute the frame pointer from the current
6647 stack pointer. SIZE is the size (in bytes) of the local variables.
6649 MIPS stack frames look like:
6651 Before call After call
6652 high +-----------------------+ +-----------------------+
6654 | caller's temps. | | caller's temps. |
6656 +-----------------------+ +-----------------------+
6658 | arguments on stack. | | arguments on stack. |
6660 +-----------------------+ +-----------------------+
6661 | 4 words to save | | 4 words to save |
6662 | arguments passed | | arguments passed |
6663 | in registers, even | | in registers, even |
6664 | if not passed. | | if not passed. |
6665 SP->+-----------------------+ VFP->+-----------------------+
6666 (VFP = SP+fp_sp_offset) | |\
6667 | fp register save | | fp_reg_size
6669 SP+gp_sp_offset->+-----------------------+
6671 | | gp register save | | gp_reg_size
6672 gp_reg_rounded | | |/
6673 | +-----------------------+
6674 \| alignment padding |
6675 +-----------------------+
6677 | local variables | | var_size
6679 +-----------------------+
6681 | alloca allocations |
6683 +-----------------------+
6685 cprestore_size | | GP save for V.4 abi |
6687 +-----------------------+
6689 | arguments on stack | |
6691 +-----------------------+ |
6692 | 4 words to save | | args_size
6693 | arguments passed | |
6694 | in registers, even | |
6695 | if not passed. | |
6696 low | (TARGET_OLDABI only) |/
6697 memory SP->+-----------------------+
6702 compute_frame_size (HOST_WIDE_INT size)
6705 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6706 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6707 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6708 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6709 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6710 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6711 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6712 unsigned int mask; /* mask of saved gp registers */
6713 unsigned int fmask; /* mask of saved fp registers */
6715 cfun->machine->global_pointer = mips_global_pointer ();
6721 var_size = MIPS_STACK_ALIGN (size);
6722 args_size = current_function_outgoing_args_size;
6723 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6725 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6726 functions. If the function has local variables, we're committed
6727 to allocating it anyway. Otherwise reclaim it here. */
6728 if (var_size == 0 && current_function_is_leaf)
6729 cprestore_size = args_size = 0;
6731 /* The MIPS 3.0 linker does not like functions that dynamically
6732 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6733 looks like we are trying to create a second frame pointer to the
6734 function, so allocate some stack space to make it happy. */
6736 if (args_size == 0 && current_function_calls_alloca)
6737 args_size = 4 * UNITS_PER_WORD;
6739 total_size = var_size + args_size + cprestore_size;
6741 /* Calculate space needed for gp registers. */
6742 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6743 if (mips_save_reg_p (regno))
6745 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6746 mask |= 1 << (regno - GP_REG_FIRST);
6749 /* We need to restore these for the handler. */
6750 if (current_function_calls_eh_return)
6755 regno = EH_RETURN_DATA_REGNO (i);
6756 if (regno == INVALID_REGNUM)
6758 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6759 mask |= 1 << (regno - GP_REG_FIRST);
6763 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
6764 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
6765 save all later registers too. */
6766 if (GENERATE_MIPS16E_SAVE_RESTORE)
6768 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
6769 ARRAY_SIZE (mips16e_s2_s8_regs), &gp_reg_size);
6770 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
6771 ARRAY_SIZE (mips16e_a0_a3_regs), &gp_reg_size);
6774 /* This loop must iterate over the same space as its companion in
6775 mips_for_each_saved_reg. */
6776 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6777 regno >= FP_REG_FIRST;
6778 regno -= MAX_FPRS_PER_FMT)
6780 if (mips_save_reg_p (regno))
6782 fp_reg_size += MAX_FPRS_PER_FMT * UNITS_PER_FPREG;
6783 fmask |= ((1 << MAX_FPRS_PER_FMT) - 1) << (regno - FP_REG_FIRST);
6787 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6788 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6790 /* Add in the space required for saving incoming register arguments. */
6791 total_size += current_function_pretend_args_size;
6792 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6794 /* Save other computed information. */
6795 cfun->machine->frame.total_size = total_size;
6796 cfun->machine->frame.var_size = var_size;
6797 cfun->machine->frame.args_size = args_size;
6798 cfun->machine->frame.cprestore_size = cprestore_size;
6799 cfun->machine->frame.gp_reg_size = gp_reg_size;
6800 cfun->machine->frame.fp_reg_size = fp_reg_size;
6801 cfun->machine->frame.mask = mask;
6802 cfun->machine->frame.fmask = fmask;
6803 cfun->machine->frame.initialized = reload_completed;
6804 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6805 cfun->machine->frame.num_fp = (fp_reg_size
6806 / (MAX_FPRS_PER_FMT * UNITS_PER_FPREG));
6810 HOST_WIDE_INT offset;
6812 if (GENERATE_MIPS16E_SAVE_RESTORE)
6813 /* MIPS16e SAVE and RESTORE instructions require the GP save area
6814 to be aligned at the high end with any padding at the low end.
6815 It is only safe to use this calculation for o32, where we never
6816 have pretend arguments, and where any varargs will be saved in
6817 the caller-allocated area rather than at the top of the frame. */
6818 offset = (total_size - GET_MODE_SIZE (gpr_mode));
6820 offset = (args_size + cprestore_size + var_size
6821 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6822 cfun->machine->frame.gp_sp_offset = offset;
6823 cfun->machine->frame.gp_save_offset = offset - total_size;
6827 cfun->machine->frame.gp_sp_offset = 0;
6828 cfun->machine->frame.gp_save_offset = 0;
6833 HOST_WIDE_INT offset;
6835 offset = (args_size + cprestore_size + var_size
6836 + gp_reg_rounded + fp_reg_size
6837 - MAX_FPRS_PER_FMT * UNITS_PER_FPREG);
6838 cfun->machine->frame.fp_sp_offset = offset;
6839 cfun->machine->frame.fp_save_offset = offset - total_size;
6843 cfun->machine->frame.fp_sp_offset = 0;
6844 cfun->machine->frame.fp_save_offset = 0;
6847 /* Ok, we're done. */
6851 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6852 pointer or argument pointer. TO is either the stack pointer or
6853 hard frame pointer. */
6856 mips_initial_elimination_offset (int from, int to)
6858 HOST_WIDE_INT offset;
6860 compute_frame_size (get_frame_size ());
6862 /* Set OFFSET to the offset from the stack pointer. */
6865 case FRAME_POINTER_REGNUM:
6869 case ARG_POINTER_REGNUM:
6870 offset = (cfun->machine->frame.total_size
6871 - current_function_pretend_args_size);
6878 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6879 offset -= cfun->machine->frame.args_size;
6884 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6885 back to a previous frame. */
6887 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6892 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6895 /* Use FN to save or restore register REGNO. MODE is the register's
6896 mode and OFFSET is the offset of its save slot from the current
6900 mips_save_restore_reg (enum machine_mode mode, int regno,
6901 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6905 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6907 fn (gen_rtx_REG (mode, regno), mem);
6911 /* Call FN for each register that is saved by the current function.
6912 SP_OFFSET is the offset of the current stack pointer from the start
6916 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6918 enum machine_mode fpr_mode;
6919 HOST_WIDE_INT offset;
6922 /* Save registers starting from high to low. The debuggers prefer at least
6923 the return register be stored at func+4, and also it allows us not to
6924 need a nop in the epilogue if at least one register is reloaded in
6925 addition to return address. */
6926 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6927 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6928 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6930 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6931 offset -= GET_MODE_SIZE (gpr_mode);
6934 /* This loop must iterate over the same space as its companion in
6935 compute_frame_size. */
6936 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6937 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6938 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6939 regno >= FP_REG_FIRST;
6940 regno -= MAX_FPRS_PER_FMT)
6941 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6943 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6944 offset -= GET_MODE_SIZE (fpr_mode);
6948 /* If we're generating n32 or n64 abicalls, and the current function
6949 does not use $28 as its global pointer, emit a cplocal directive.
6950 Use pic_offset_table_rtx as the argument to the directive. */
6953 mips_output_cplocal (void)
6955 if (!TARGET_EXPLICIT_RELOCS
6956 && cfun->machine->global_pointer > 0
6957 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6958 output_asm_insn (".cplocal %+", 0);
6961 /* Return the style of GP load sequence that is being used for the
6962 current function. */
6964 enum mips_loadgp_style
6965 mips_current_loadgp_style (void)
6967 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
6973 if (TARGET_ABSOLUTE_ABICALLS)
6974 return LOADGP_ABSOLUTE;
6976 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6979 /* The __gnu_local_gp symbol. */
6981 static GTY(()) rtx mips_gnu_local_gp;
6983 /* If we're generating n32 or n64 abicalls, emit instructions
6984 to set up the global pointer. */
6987 mips_emit_loadgp (void)
6989 rtx addr, offset, incoming_address, base, index;
6991 switch (mips_current_loadgp_style ())
6993 case LOADGP_ABSOLUTE:
6994 if (mips_gnu_local_gp == NULL)
6996 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6997 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6999 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
7003 addr = XEXP (DECL_RTL (current_function_decl), 0);
7004 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
7005 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7006 emit_insn (gen_loadgp_newabi (offset, incoming_address));
7007 if (!TARGET_EXPLICIT_RELOCS)
7008 emit_insn (gen_loadgp_blockage ());
7012 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
7013 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
7014 emit_insn (gen_loadgp_rtp (base, index));
7015 if (!TARGET_EXPLICIT_RELOCS)
7016 emit_insn (gen_loadgp_blockage ());
7024 /* Set up the stack and frame (if desired) for the function. */
7027 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7030 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7032 #ifdef SDB_DEBUGGING_INFO
7033 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7034 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7037 /* In mips16 mode, we may need to generate a 32 bit to handle
7038 floating point arguments. The linker will arrange for any 32-bit
7039 functions to call this stub, which will then jump to the 16-bit
7041 if (mips16_hard_float
7042 && current_function_args_info.fp_code != 0)
7043 build_mips16_function_stub (file);
7045 if (!FUNCTION_NAME_ALREADY_DECLARED)
7047 /* Get the function name the same way that toplev.c does before calling
7048 assemble_start_function. This is needed so that the name used here
7049 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7050 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7052 if (!flag_inhibit_size_directive)
7054 fputs ("\t.ent\t", file);
7055 assemble_name (file, fnname);
7059 assemble_name (file, fnname);
7060 fputs (":\n", file);
7063 /* Stop mips_file_end from treating this function as external. */
7064 if (TARGET_IRIX && mips_abi == ABI_32)
7065 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
7067 if (!flag_inhibit_size_directive)
7069 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7071 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
7072 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
7073 ", args= " HOST_WIDE_INT_PRINT_DEC
7074 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
7075 (reg_names[(frame_pointer_needed)
7076 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7077 ((frame_pointer_needed && TARGET_MIPS16)
7078 ? tsize - cfun->machine->frame.args_size
7080 reg_names[GP_REG_FIRST + 31],
7081 cfun->machine->frame.var_size,
7082 cfun->machine->frame.num_gp,
7083 cfun->machine->frame.num_fp,
7084 cfun->machine->frame.args_size,
7085 cfun->machine->frame.cprestore_size);
7087 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7088 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7089 cfun->machine->frame.mask,
7090 cfun->machine->frame.gp_save_offset);
7091 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7092 cfun->machine->frame.fmask,
7093 cfun->machine->frame.fp_save_offset);
7096 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7097 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7100 if (mips_current_loadgp_style () == LOADGP_OLDABI)
7102 /* Handle the initialization of $gp for SVR4 PIC. */
7103 if (!cfun->machine->all_noreorder_p)
7104 output_asm_insn ("%(.cpload\t%^%)", 0);
7106 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
7108 else if (cfun->machine->all_noreorder_p)
7109 output_asm_insn ("%(%<", 0);
7111 /* Tell the assembler which register we're using as the global
7112 pointer. This is needed for thunks, since they can use either
7113 explicit relocs or assembler macros. */
7114 mips_output_cplocal ();
7117 /* Make the last instruction frame related and note that it performs
7118 the operation described by FRAME_PATTERN. */
7121 mips_set_frame_expr (rtx frame_pattern)
7125 insn = get_last_insn ();
7126 RTX_FRAME_RELATED_P (insn) = 1;
7127 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7133 /* Return a frame-related rtx that stores REG at MEM.
7134 REG must be a single register. */
7137 mips_frame_set (rtx mem, rtx reg)
7141 /* If we're saving the return address register and the dwarf return
7142 address column differs from the hard register number, adjust the
7143 note reg to refer to the former. */
7144 if (REGNO (reg) == GP_REG_FIRST + 31
7145 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7146 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7148 set = gen_rtx_SET (VOIDmode, mem, reg);
7149 RTX_FRAME_RELATED_P (set) = 1;
7155 /* Save register REG to MEM. Make the instruction frame-related. */
7158 mips_save_reg (rtx reg, rtx mem)
7160 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
7164 if (mips_split_64bit_move_p (mem, reg))
7165 mips_split_64bit_move (mem, reg);
7167 emit_move_insn (mem, reg);
7169 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
7170 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
7171 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
7176 && REGNO (reg) != GP_REG_FIRST + 31
7177 && !M16_REG_P (REGNO (reg)))
7179 /* Save a non-mips16 register by moving it through a temporary.
7180 We don't need to do this for $31 since there's a special
7181 instruction for it. */
7182 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
7183 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
7186 emit_move_insn (mem, reg);
7188 mips_set_frame_expr (mips_frame_set (mem, reg));
7192 /* Return a move between register REGNO and memory location SP + OFFSET.
7193 Make the move a load if RESTORE_P, otherwise make it a frame-related
7197 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7202 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7203 reg = gen_rtx_REG (SImode, regno);
7205 ? gen_rtx_SET (VOIDmode, reg, mem)
7206 : mips_frame_set (mem, reg));
7209 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7210 The instruction must:
7212 - Allocate or deallocate SIZE bytes in total; SIZE is known
7215 - Save or restore as many registers in *MASK_PTR as possible.
7216 The instruction saves the first registers at the top of the
7217 allocated area, with the other registers below it.
7219 - Save NARGS argument registers above the allocated area.
7221 (NARGS is always zero if RESTORE_P.)
7223 The SAVE and RESTORE instructions cannot save and restore all general
7224 registers, so there may be some registers left over for the caller to
7225 handle. Destructively modify *MASK_PTR so that it contains the registers
7226 that still need to be saved or restored. The caller can save these
7227 registers in the memory immediately below *OFFSET_PTR, which is a
7228 byte offset from the bottom of the allocated stack area. */
7231 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7232 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7236 HOST_WIDE_INT offset, top_offset;
7237 unsigned int i, regno;
7240 gcc_assert (cfun->machine->frame.fp_reg_size == 0);
7242 /* Calculate the number of elements in the PARALLEL. We need one element
7243 for the stack adjustment, one for each argument register save, and one
7244 for each additional register move. */
7246 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7247 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7250 /* Create the final PARALLEL. */
7251 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7254 /* Add the stack pointer adjustment. */
7255 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7256 plus_constant (stack_pointer_rtx,
7257 restore_p ? size : -size));
7258 RTX_FRAME_RELATED_P (set) = 1;
7259 XVECEXP (pattern, 0, n++) = set;
7261 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7262 top_offset = restore_p ? size : 0;
7264 /* Save the arguments. */
7265 for (i = 0; i < nargs; i++)
7267 offset = top_offset + i * GET_MODE_SIZE (gpr_mode);
7268 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7269 XVECEXP (pattern, 0, n++) = set;
7272 /* Then fill in the other register moves. */
7273 offset = top_offset;
7274 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7276 regno = mips16e_save_restore_regs[i];
7277 if (BITSET_P (*mask_ptr, regno))
7279 offset -= UNITS_PER_WORD;
7280 set = mips16e_save_restore_reg (restore_p, offset, regno);
7281 XVECEXP (pattern, 0, n++) = set;
7282 *mask_ptr &= ~(1 << regno);
7286 /* Tell the caller what offset it should use for the remaining registers. */
7287 *offset_ptr = size + (offset - top_offset) + size;
7289 gcc_assert (n == XVECLEN (pattern, 0));
7294 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7295 pointer. Return true if PATTERN matches the kind of instruction
7296 generated by mips16e_build_save_restore. If INFO is nonnull,
7297 initialize it when returning true. */
7300 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7301 struct mips16e_save_restore_info *info)
7303 unsigned int i, nargs, mask;
7304 HOST_WIDE_INT top_offset, save_offset, offset, extra;
7305 rtx set, reg, mem, base;
7308 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7311 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7312 top_offset = adjust > 0 ? adjust : 0;
7314 /* Interpret all other members of the PARALLEL. */
7315 save_offset = top_offset - GET_MODE_SIZE (gpr_mode);
7319 for (n = 1; n < XVECLEN (pattern, 0); n++)
7321 /* Check that we have a SET. */
7322 set = XVECEXP (pattern, 0, n);
7323 if (GET_CODE (set) != SET)
7326 /* Check that the SET is a load (if restoring) or a store
7328 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7332 /* Check that the address is the sum of the stack pointer and a
7333 possibly-zero constant offset. */
7334 mips_split_plus (XEXP (mem, 0), &base, &offset);
7335 if (base != stack_pointer_rtx)
7338 /* Check that SET's other operand is a register. */
7339 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7343 /* Check for argument saves. */
7344 if (offset == top_offset + nargs * GET_MODE_SIZE (gpr_mode)
7345 && REGNO (reg) == GP_ARG_FIRST + nargs)
7347 else if (offset == save_offset)
7349 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7350 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7353 mask |= 1 << REGNO (reg);
7354 save_offset -= GET_MODE_SIZE (gpr_mode);
7360 /* Check that the restrictions on register ranges are met. */
7362 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7363 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7364 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7365 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7369 /* Make sure that the topmost argument register is not saved twice.
7370 The checks above ensure that the same is then true for the other
7371 argument registers. */
7372 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7375 /* Pass back information, if requested. */
7378 info->nargs = nargs;
7380 info->size = (adjust > 0 ? adjust : -adjust);
7386 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7387 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7388 the null terminator. */
7391 mips16e_add_register_range (char *s, unsigned int min_reg,
7392 unsigned int max_reg)
7394 if (min_reg != max_reg)
7395 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7397 s += sprintf (s, ",%s", reg_names[min_reg]);
7401 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7402 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7405 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7407 static char buffer[300];
7409 struct mips16e_save_restore_info info;
7410 unsigned int i, end;
7413 /* Parse the pattern. */
7414 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7417 /* Add the mnemonic. */
7418 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7421 /* Save the arguments. */
7423 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7424 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7425 else if (info.nargs == 1)
7426 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7428 /* Emit the amount of stack space to allocate or deallocate. */
7429 s += sprintf (s, "%d", (int) info.size);
7431 /* Save or restore $16. */
7432 if (BITSET_P (info.mask, 16))
7433 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7435 /* Save or restore $17. */
7436 if (BITSET_P (info.mask, 17))
7437 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7439 /* Save or restore registers in the range $s2...$s8, which
7440 mips16e_s2_s8_regs lists in decreasing order. Note that this
7441 is a software register range; the hardware registers are not
7442 numbered consecutively. */
7443 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7444 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7446 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7447 mips16e_s2_s8_regs[i]);
7449 /* Save or restore registers in the range $a0...$a3. */
7450 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7451 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7453 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7454 mips16e_a0_a3_regs[end - 1]);
7456 /* Save or restore $31. */
7457 if (BITSET_P (info.mask, 31))
7458 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7463 /* Return a simplified form of X using the register values in REG_VALUES.
7464 REG_VALUES[R] is the last value assigned to hard register R, or null
7465 if R has not been modified.
7467 This function is rather limited, but is good enough for our purposes. */
7470 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7474 x = avoid_constant_pool_reference (x);
7478 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7479 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7480 x0, GET_MODE (XEXP (x, 0)));
7483 if (ARITHMETIC_P (x))
7485 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7486 x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7487 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7491 && reg_values[REGNO (x)]
7492 && !rtx_unstable_p (reg_values[REGNO (x)]))
7493 return reg_values[REGNO (x)];
7498 /* Return true if (set DEST SRC) stores an argument register into its
7499 caller-allocated save slot, storing the number of that argument
7500 register in *REGNO_PTR if so. REG_VALUES is as for
7501 mips16e_collect_propagate_value. */
7504 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7505 unsigned int *regno_ptr)
7507 unsigned int argno, regno;
7508 HOST_WIDE_INT offset, required_offset;
7511 /* Check that this is a word-mode store. */
7512 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7515 /* Check that the register being saved is an unmodified argument
7517 regno = REGNO (src);
7518 if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
7520 argno = regno - GP_ARG_FIRST;
7522 /* Check whether the address is an appropriate stack pointer or
7523 frame pointer access. The frame pointer is offset from the
7524 stack pointer by the size of the outgoing arguments. */
7525 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7526 mips_split_plus (addr, &base, &offset);
7527 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7528 if (base == hard_frame_pointer_rtx)
7529 required_offset -= cfun->machine->frame.args_size;
7530 else if (base != stack_pointer_rtx)
7532 if (offset != required_offset)
7539 /* A subroutine of mips_expand_prologue, called only when generating
7540 MIPS16e SAVE instructions. Search the start of the function for any
7541 instructions that save argument registers into their caller-allocated
7542 save slots. Delete such instructions and return a value N such that
7543 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7544 instructions redundant. */
7547 mips16e_collect_argument_saves (void)
7549 rtx reg_values[FIRST_PSEUDO_REGISTER];
7550 rtx insn, next, set, dest, src;
7551 unsigned int nargs, regno;
7553 push_topmost_sequence ();
7555 memset (reg_values, 0, sizeof (reg_values));
7556 for (insn = get_insns (); insn; insn = next)
7558 next = NEXT_INSN (insn);
7565 set = PATTERN (insn);
7566 if (GET_CODE (set) != SET)
7569 dest = SET_DEST (set);
7570 src = SET_SRC (set);
7571 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
7573 if (!BITSET_P (cfun->machine->frame.mask, regno))
7576 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7579 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7580 reg_values[REGNO (dest)]
7581 = mips16e_collect_propagate_value (src, reg_values);
7585 pop_topmost_sequence ();
7590 /* Expand the prologue into a bunch of separate insns. */
7593 mips_expand_prologue (void)
7599 if (cfun->machine->global_pointer > 0)
7600 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
7602 size = compute_frame_size (get_frame_size ());
7604 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
7605 bytes beforehand; this is enough to cover the register save area
7606 without going out of range. */
7607 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7609 HOST_WIDE_INT step1;
7611 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
7613 if (GENERATE_MIPS16E_SAVE_RESTORE)
7615 HOST_WIDE_INT offset;
7616 unsigned int mask, regno;
7618 /* Try to merge argument stores into the save instruction. */
7619 nargs = mips16e_collect_argument_saves ();
7621 /* Build the save instruction. */
7622 mask = cfun->machine->frame.mask;
7623 insn = mips16e_build_save_restore (false, &mask, &offset,
7625 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7628 /* Check if we need to save other registers. */
7629 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7630 if (BITSET_P (mask, regno - GP_REG_FIRST))
7632 offset -= GET_MODE_SIZE (gpr_mode);
7633 mips_save_restore_reg (gpr_mode, regno, offset, mips_save_reg);
7638 insn = gen_add3_insn (stack_pointer_rtx,
7641 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7643 mips_for_each_saved_reg (size, mips_save_reg);
7647 /* Allocate the rest of the frame. */
7650 if (SMALL_OPERAND (-size))
7651 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
7653 GEN_INT (-size)))) = 1;
7656 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
7659 /* There are no instructions to add or subtract registers
7660 from the stack pointer, so use the frame pointer as a
7661 temporary. We should always be using a frame pointer
7662 in this case anyway. */
7663 gcc_assert (frame_pointer_needed);
7664 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7665 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
7666 hard_frame_pointer_rtx,
7667 MIPS_PROLOGUE_TEMP (Pmode)));
7668 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7671 emit_insn (gen_sub3_insn (stack_pointer_rtx,
7673 MIPS_PROLOGUE_TEMP (Pmode)));
7675 /* Describe the combined effect of the previous instructions. */
7677 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7678 plus_constant (stack_pointer_rtx, -size)));
7682 /* Set up the frame pointer, if we're using one. In mips16 code,
7683 we point the frame pointer ahead of the outgoing argument area.
7684 This should allow more variables & incoming arguments to be
7685 accessed with unextended instructions. */
7686 if (frame_pointer_needed)
7688 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
7690 rtx offset = GEN_INT (cfun->machine->frame.args_size);
7691 if (SMALL_OPERAND (cfun->machine->frame.args_size))
7693 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7698 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
7699 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7700 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7701 hard_frame_pointer_rtx,
7702 MIPS_PROLOGUE_TEMP (Pmode)));
7704 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
7705 plus_constant (stack_pointer_rtx,
7706 cfun->machine->frame.args_size)));
7710 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
7711 stack_pointer_rtx)) = 1;
7714 mips_emit_loadgp ();
7716 /* If generating o32/o64 abicalls, save $gp on the stack. */
7717 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
7718 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
7720 /* If we are profiling, make sure no instructions are scheduled before
7721 the call to mcount. */
7723 if (current_function_profile)
7724 emit_insn (gen_blockage ());
7727 /* Do any necessary cleanup after a function to restore stack, frame,
7730 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7733 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7734 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7736 /* Reinstate the normal $gp. */
7737 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
7738 mips_output_cplocal ();
7740 if (cfun->machine->all_noreorder_p)
7742 /* Avoid using %>%) since it adds excess whitespace. */
7743 output_asm_insn (".set\tmacro", 0);
7744 output_asm_insn (".set\treorder", 0);
7745 set_noreorder = set_nomacro = 0;
7748 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
7752 /* Get the function name the same way that toplev.c does before calling
7753 assemble_start_function. This is needed so that the name used here
7754 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7755 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7756 fputs ("\t.end\t", file);
7757 assemble_name (file, fnname);
7762 /* Emit instructions to restore register REG from slot MEM. */
7765 mips_restore_reg (rtx reg, rtx mem)
7767 /* There's no mips16 instruction to load $31 directly. Load into
7768 $7 instead and adjust the return insn appropriately. */
7769 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
7770 reg = gen_rtx_REG (GET_MODE (reg), 7);
7772 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
7774 /* Can't restore directly; move through a temporary. */
7775 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
7776 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
7779 emit_move_insn (reg, mem);
7783 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
7784 if this epilogue precedes a sibling call, false if it is for a normal
7785 "epilogue" pattern. */
7788 mips_expand_epilogue (int sibcall_p)
7790 HOST_WIDE_INT step1, step2;
7793 if (!sibcall_p && mips_can_use_return_insn ())
7795 emit_jump_insn (gen_return ());
7799 /* In mips16 mode, if the return value should go into a floating-point
7800 register, we need to call a helper routine to copy it over. */
7801 if (mips16_cfun_returns_in_fpr_p ())
7810 enum machine_mode return_mode;
7812 return_type = DECL_RESULT (current_function_decl);
7813 return_mode = DECL_MODE (return_type);
7815 name = ACONCAT (("__mips16_ret_",
7816 mips16_call_stub_mode_suffix (return_mode),
7818 id = get_identifier (name);
7819 func = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7820 retval = gen_rtx_REG (return_mode, GP_RETURN);
7821 call = gen_call_value_internal (retval, func, const0_rtx);
7822 insn = emit_call_insn (call);
7823 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
7826 /* Split the frame into two. STEP1 is the amount of stack we should
7827 deallocate before restoring the registers. STEP2 is the amount we
7828 should deallocate afterwards.
7830 Start off by assuming that no registers need to be restored. */
7831 step1 = cfun->machine->frame.total_size;
7834 /* Work out which register holds the frame address. Account for the
7835 frame pointer offset used by mips16 code. */
7836 if (!frame_pointer_needed)
7837 base = stack_pointer_rtx;
7840 base = hard_frame_pointer_rtx;
7842 step1 -= cfun->machine->frame.args_size;
7845 /* If we need to restore registers, deallocate as much stack as
7846 possible in the second step without going out of range. */
7847 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7849 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7853 /* Set TARGET to BASE + STEP1. */
7859 /* Get an rtx for STEP1 that we can add to BASE. */
7860 adjust = GEN_INT (step1);
7861 if (!SMALL_OPERAND (step1))
7863 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7864 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7867 /* Normal mode code can copy the result straight into $sp. */
7869 target = stack_pointer_rtx;
7871 emit_insn (gen_add3_insn (target, base, adjust));
7874 /* Copy TARGET into the stack pointer. */
7875 if (target != stack_pointer_rtx)
7876 emit_move_insn (stack_pointer_rtx, target);
7878 /* If we're using addressing macros, $gp is implicitly used by all
7879 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
7881 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
7882 emit_insn (gen_blockage ());
7884 if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
7886 unsigned int regno, mask;
7887 HOST_WIDE_INT offset;
7890 /* Generate the restore instruction. */
7891 mask = cfun->machine->frame.mask;
7892 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
7894 /* Restore any other registers manually. */
7895 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7896 if (BITSET_P (mask, regno - GP_REG_FIRST))
7898 offset -= GET_MODE_SIZE (gpr_mode);
7899 mips_save_restore_reg (gpr_mode, regno, offset, mips_restore_reg);
7902 /* Restore the remaining registers and deallocate the final bit
7904 emit_insn (restore);
7908 /* Restore the registers. */
7909 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7912 /* Deallocate the final bit of the frame. */
7914 emit_insn (gen_add3_insn (stack_pointer_rtx,
7919 /* Add in the __builtin_eh_return stack adjustment. We need to
7920 use a temporary in mips16 code. */
7921 if (current_function_calls_eh_return)
7925 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7926 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7927 MIPS_EPILOGUE_TEMP (Pmode),
7928 EH_RETURN_STACKADJ_RTX));
7929 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7932 emit_insn (gen_add3_insn (stack_pointer_rtx,
7934 EH_RETURN_STACKADJ_RTX));
7939 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
7940 path will restore the return address into $7 rather than $31. */
7942 && !GENERATE_MIPS16E_SAVE_RESTORE
7943 && (cfun->machine->frame.mask & RA_MASK) != 0)
7944 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7945 GP_REG_FIRST + 7)));
7947 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7948 GP_REG_FIRST + 31)));
7952 /* Return nonzero if this function is known to have a null epilogue.
7953 This allows the optimizer to omit jumps to jumps if no stack
7957 mips_can_use_return_insn (void)
7959 if (! reload_completed)
7962 if (df_regs_ever_live_p (31) || current_function_profile)
7965 /* In mips16 mode, a function that returns a floating point value
7966 needs to arrange to copy the return value into the floating point
7968 if (mips16_cfun_returns_in_fpr_p ())
7971 if (cfun->machine->frame.initialized)
7972 return cfun->machine->frame.total_size == 0;
7974 return compute_frame_size (get_frame_size ()) == 0;
7977 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7978 in order to avoid duplicating too much logic from elsewhere. */
7981 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7982 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7985 rtx this, temp1, temp2, insn, fnaddr;
7987 /* Pretend to be a post-reload pass while generating rtl. */
7988 reload_completed = 1;
7990 /* Mark the end of the (empty) prologue. */
7991 emit_note (NOTE_INSN_PROLOGUE_END);
7993 /* Pick a global pointer. Use a call-clobbered register if
7994 TARGET_CALL_SAVED_GP, so that we can use a sibcall. */
7997 cfun->machine->global_pointer =
7998 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
8000 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8004 /* Set up the global pointer for n32 or n64 abicalls. If
8005 LOADGP_ABSOLUTE then the thunk does not use the gp and there is
8006 no need to load it.*/
8007 if (mips_current_loadgp_style () != LOADGP_ABSOLUTE
8008 || !targetm.binds_local_p (function))
8009 mips_emit_loadgp ();
8011 /* We need two temporary registers in some cases. */
8012 temp1 = gen_rtx_REG (Pmode, 2);
8013 temp2 = gen_rtx_REG (Pmode, 3);
8015 /* Find out which register contains the "this" pointer. */
8016 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8017 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
8019 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
8021 /* Add DELTA to THIS. */
8024 rtx offset = GEN_INT (delta);
8025 if (!SMALL_OPERAND (delta))
8027 emit_move_insn (temp1, offset);
8030 emit_insn (gen_add3_insn (this, this, offset));
8033 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
8034 if (vcall_offset != 0)
8038 /* Set TEMP1 to *THIS. */
8039 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
8041 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
8042 addr = mips_add_offset (temp2, temp1, vcall_offset);
8044 /* Load the offset and add it to THIS. */
8045 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
8046 emit_insn (gen_add3_insn (this, this, temp1));
8049 /* Jump to the target function. Use a sibcall if direct jumps are
8050 allowed, otherwise load the address into a register first. */
8051 fnaddr = XEXP (DECL_RTL (function), 0);
8052 if (TARGET_MIPS16 || TARGET_USE_GOT || SYMBOL_REF_LONG_CALL_P (fnaddr))
8054 /* This is messy. gas treats "la $25,foo" as part of a call
8055 sequence and may allow a global "foo" to be lazily bound.
8056 The general move patterns therefore reject this combination.
8058 In this context, lazy binding would actually be OK
8059 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
8060 TARGET_CALL_SAVED_GP; see mips_load_call_address.
8061 We must therefore load the address via a temporary
8062 register if mips_dangerous_for_la25_p.
8064 If we jump to the temporary register rather than $25, the assembler
8065 can use the move insn to fill the jump's delay slot. */
8066 if (TARGET_USE_PIC_FN_ADDR_REG
8067 && !mips_dangerous_for_la25_p (fnaddr))
8068 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8069 mips_load_call_address (temp1, fnaddr, true);
8071 if (TARGET_USE_PIC_FN_ADDR_REG
8072 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
8073 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
8074 emit_jump_insn (gen_indirect_jump (temp1));
8078 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
8079 SIBLING_CALL_P (insn) = 1;
8082 /* Run just enough of rest_of_compilation. This sequence was
8083 "borrowed" from alpha.c. */
8084 insn = get_insns ();
8085 insn_locators_alloc ();
8086 split_all_insns_noflow ();
8088 mips16_lay_out_constants ();
8089 shorten_branches (insn);
8090 final_start_function (insn, file, 1);
8091 final (insn, file, 1);
8092 final_end_function ();
8094 /* Clean up the vars set above. Note that final_end_function resets
8095 the global pointer for us. */
8096 reload_completed = 0;
8099 /* Returns nonzero if X contains a SYMBOL_REF. */
8102 symbolic_expression_p (rtx x)
8104 if (GET_CODE (x) == SYMBOL_REF)
8107 if (GET_CODE (x) == CONST)
8108 return symbolic_expression_p (XEXP (x, 0));
8111 return symbolic_expression_p (XEXP (x, 0));
8113 if (ARITHMETIC_P (x))
8114 return (symbolic_expression_p (XEXP (x, 0))
8115 || symbolic_expression_p (XEXP (x, 1)));
8120 /* Choose the section to use for the constant rtx expression X that has
8124 mips_select_rtx_section (enum machine_mode mode, rtx x,
8125 unsigned HOST_WIDE_INT align)
8129 /* In mips16 mode, the constant table always goes in the same section
8130 as the function, so that constants can be loaded using PC relative
8132 return function_section (current_function_decl);
8134 else if (TARGET_EMBEDDED_DATA)
8136 /* For embedded applications, always put constants in read-only data,
8137 in order to reduce RAM usage. */
8138 return mergeable_constant_section (mode, align, 0);
8142 /* For hosted applications, always put constants in small data if
8143 possible, as this gives the best performance. */
8144 /* ??? Consider using mergeable small data sections. */
8146 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
8147 && mips_section_threshold > 0)
8148 return get_named_section (NULL, ".sdata", 0);
8149 else if (flag_pic && symbolic_expression_p (x))
8150 return get_named_section (NULL, ".data.rel.ro", 3);
8152 return mergeable_constant_section (mode, align, 0);
8156 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8158 The complication here is that, with the combination TARGET_ABICALLS
8159 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
8160 therefore not be included in the read-only part of a DSO. Handle such
8161 cases by selecting a normal data section instead of a read-only one.
8162 The logic apes that in default_function_rodata_section. */
8165 mips_function_rodata_section (tree decl)
8167 if (!TARGET_ABICALLS || TARGET_GPWORD)
8168 return default_function_rodata_section (decl);
8170 if (decl && DECL_SECTION_NAME (decl))
8172 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8173 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8175 char *rname = ASTRDUP (name);
8177 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8179 else if (flag_function_sections && flag_data_sections
8180 && strncmp (name, ".text.", 6) == 0)
8182 char *rname = ASTRDUP (name);
8183 memcpy (rname + 1, "data", 4);
8184 return get_section (rname, SECTION_WRITE, decl);
8187 return data_section;
8190 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
8191 locally-defined objects go in a small data section. It also controls
8192 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
8193 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
8196 mips_in_small_data_p (tree decl)
8200 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8203 /* We don't yet generate small-data references for -mabicalls or
8204 VxWorks RTP code. See the related -G handling in override_options. */
8205 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8208 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8212 /* Reject anything that isn't in a known small-data section. */
8213 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8214 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8217 /* If a symbol is defined externally, the assembler will use the
8218 usual -G rules when deciding how to implement macros. */
8219 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
8222 else if (TARGET_EMBEDDED_DATA)
8224 /* Don't put constants into the small data section: we want them
8225 to be in ROM rather than RAM. */
8226 if (TREE_CODE (decl) != VAR_DECL)
8229 if (TREE_READONLY (decl)
8230 && !TREE_SIDE_EFFECTS (decl)
8231 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8235 size = int_size_in_bytes (TREE_TYPE (decl));
8236 return (size > 0 && size <= mips_section_threshold);
8239 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8240 anchors for small data: the GP register acts as an anchor in that
8241 case. We also don't want to use them for PC-relative accesses,
8242 where the PC acts as an anchor. */
8245 mips_use_anchors_for_symbol_p (rtx symbol)
8247 switch (mips_classify_symbol (symbol))
8249 case SYMBOL_CONSTANT_POOL:
8250 case SYMBOL_SMALL_DATA:
8258 /* See whether VALTYPE is a record whose fields should be returned in
8259 floating-point registers. If so, return the number of fields and
8260 list them in FIELDS (which should have two elements). Return 0
8263 For n32 & n64, a structure with one or two fields is returned in
8264 floating-point registers as long as every field has a floating-point
8268 mips_fpr_return_fields (tree valtype, tree *fields)
8276 if (TREE_CODE (valtype) != RECORD_TYPE)
8280 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
8282 if (TREE_CODE (field) != FIELD_DECL)
8285 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
8291 fields[i++] = field;
8297 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
8298 a value in the most significant part of $2/$3 if:
8300 - the target is big-endian;
8302 - the value has a structure or union type (we generalize this to
8303 cover aggregates from other languages too); and
8305 - the structure is not returned in floating-point registers. */
8308 mips_return_in_msb (tree valtype)
8312 return (TARGET_NEWABI
8313 && TARGET_BIG_ENDIAN
8314 && AGGREGATE_TYPE_P (valtype)
8315 && mips_fpr_return_fields (valtype, fields) == 0);
8319 /* Return a composite value in a pair of floating-point registers.
8320 MODE1 and OFFSET1 are the mode and byte offset for the first value,
8321 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
8324 For n32 & n64, $f0 always holds the first value and $f2 the second.
8325 Otherwise the values are packed together as closely as possible. */
8328 mips_return_fpr_pair (enum machine_mode mode,
8329 enum machine_mode mode1, HOST_WIDE_INT offset1,
8330 enum machine_mode mode2, HOST_WIDE_INT offset2)
8334 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
8335 return gen_rtx_PARALLEL
8338 gen_rtx_EXPR_LIST (VOIDmode,
8339 gen_rtx_REG (mode1, FP_RETURN),
8341 gen_rtx_EXPR_LIST (VOIDmode,
8342 gen_rtx_REG (mode2, FP_RETURN + inc),
8343 GEN_INT (offset2))));
8348 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
8349 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
8350 VALTYPE is null and MODE is the mode of the return value. */
8353 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
8354 enum machine_mode mode)
8361 mode = TYPE_MODE (valtype);
8362 unsignedp = TYPE_UNSIGNED (valtype);
8364 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
8365 true, we must promote the mode just as PROMOTE_MODE does. */
8366 mode = promote_mode (valtype, mode, &unsignedp, 1);
8368 /* Handle structures whose fields are returned in $f0/$f2. */
8369 switch (mips_fpr_return_fields (valtype, fields))
8372 return gen_rtx_REG (mode, FP_RETURN);
8375 return mips_return_fpr_pair (mode,
8376 TYPE_MODE (TREE_TYPE (fields[0])),
8377 int_byte_position (fields[0]),
8378 TYPE_MODE (TREE_TYPE (fields[1])),
8379 int_byte_position (fields[1]));
8382 /* If a value is passed in the most significant part of a register, see
8383 whether we have to round the mode up to a whole number of words. */
8384 if (mips_return_in_msb (valtype))
8386 HOST_WIDE_INT size = int_size_in_bytes (valtype);
8387 if (size % UNITS_PER_WORD != 0)
8389 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
8390 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
8394 /* For EABI, the class of return register depends entirely on MODE.
8395 For example, "struct { some_type x; }" and "union { some_type x; }"
8396 are returned in the same way as a bare "some_type" would be.
8397 Other ABIs only use FPRs for scalar, complex or vector types. */
8398 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
8399 return gen_rtx_REG (mode, GP_RETURN);
8404 /* Handle long doubles for n32 & n64. */
8406 return mips_return_fpr_pair (mode,
8408 DImode, GET_MODE_SIZE (mode) / 2);
8410 if (mips_return_mode_in_fpr_p (mode))
8412 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8413 return mips_return_fpr_pair (mode,
8414 GET_MODE_INNER (mode), 0,
8415 GET_MODE_INNER (mode),
8416 GET_MODE_SIZE (mode) / 2);
8418 return gen_rtx_REG (mode, FP_RETURN);
8422 return gen_rtx_REG (mode, GP_RETURN);
8425 /* Return nonzero when an argument must be passed by reference. */
8428 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8429 enum machine_mode mode, tree type,
8430 bool named ATTRIBUTE_UNUSED)
8432 if (mips_abi == ABI_EABI)
8436 /* ??? How should SCmode be handled? */
8437 if (mode == DImode || mode == DFmode)
8440 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
8441 return size == -1 || size > UNITS_PER_WORD;
8445 /* If we have a variable-sized parameter, we have no choice. */
8446 return targetm.calls.must_pass_in_stack (mode, type);
8451 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8452 enum machine_mode mode ATTRIBUTE_UNUSED,
8453 tree type ATTRIBUTE_UNUSED, bool named)
8455 return mips_abi == ABI_EABI && named;
8458 /* Return true if registers of class CLASS cannot change from mode FROM
8462 mips_cannot_change_mode_class (enum machine_mode from,
8463 enum machine_mode to, enum reg_class class)
8465 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
8466 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
8468 if (TARGET_BIG_ENDIAN)
8470 /* When a multi-word value is stored in paired floating-point
8471 registers, the first register always holds the low word.
8472 We therefore can't allow FPRs to change between single-word
8473 and multi-word modes. */
8474 if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
8479 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
8480 in LO and HI, the high word always comes first. We therefore
8481 can't allow values stored in HI to change between single-word
8482 and multi-word modes.
8483 This rule applies to both the original HI/LO pair and the new
8484 DSP accumulators. */
8485 if (reg_classes_intersect_p (ACC_REGS, class))
8490 /* gcc assumes that each word of a multiword register can be accessed
8491 individually using SUBREGs. This is not true for floating-point
8492 registers if they are bigger than a word. */
8493 if (UNITS_PER_FPREG > UNITS_PER_WORD
8494 && GET_MODE_SIZE (from) > UNITS_PER_WORD
8495 && GET_MODE_SIZE (to) < UNITS_PER_FPREG
8496 && reg_classes_intersect_p (FP_REGS, class))
8499 /* Loading a 32-bit value into a 64-bit floating-point register
8500 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8501 We can't allow 64-bit float registers to change from SImode to
8506 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
8507 && reg_classes_intersect_p (FP_REGS, class))
8513 /* Return true if X should not be moved directly into register $25.
8514 We need this because many versions of GAS will treat "la $25,foo" as
8515 part of a call sequence and so allow a global "foo" to be lazily bound. */
8518 mips_dangerous_for_la25_p (rtx x)
8520 return (!TARGET_EXPLICIT_RELOCS
8522 && GET_CODE (x) == SYMBOL_REF
8523 && mips_global_symbol_p (x));
8526 /* Implement PREFERRED_RELOAD_CLASS. */
8529 mips_preferred_reload_class (rtx x, enum reg_class class)
8531 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8534 if (TARGET_HARD_FLOAT
8535 && FLOAT_MODE_P (GET_MODE (x))
8536 && reg_class_subset_p (FP_REGS, class))
8539 if (reg_class_subset_p (GR_REGS, class))
8542 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8548 /* This function returns the register class required for a secondary
8549 register when copying between one of the registers in CLASS, and X,
8550 using MODE. If IN_P is nonzero, the copy is going from X to the
8551 register, otherwise the register is the source. A return value of
8552 NO_REGS means that no secondary register is required. */
8555 mips_secondary_reload_class (enum reg_class class,
8556 enum machine_mode mode, rtx x, int in_p)
8558 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8562 if (REG_P (x)|| GET_CODE (x) == SUBREG)
8563 regno = true_regnum (x);
8565 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8567 if (mips_dangerous_for_la25_p (x))
8570 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
8574 /* Copying from HI or LO to anywhere other than a general register
8575 requires a general register.
8576 This rule applies to both the original HI/LO pair and the new
8577 DSP accumulators. */
8578 if (reg_class_subset_p (class, ACC_REGS))
8580 if (TARGET_MIPS16 && in_p)
8582 /* We can't really copy to HI or LO at all in mips16 mode. */
8585 return gp_reg_p ? NO_REGS : gr_regs;
8587 if (ACC_REG_P (regno))
8589 if (TARGET_MIPS16 && ! in_p)
8591 /* We can't really copy to HI or LO at all in mips16 mode. */
8594 return class == gr_regs ? NO_REGS : gr_regs;
8597 /* We can only copy a value to a condition code register from a
8598 floating point register, and even then we require a scratch
8599 floating point register. We can only copy a value out of a
8600 condition code register into a general register. */
8601 if (class == ST_REGS)
8605 return gp_reg_p ? NO_REGS : gr_regs;
8607 if (ST_REG_P (regno))
8611 return class == gr_regs ? NO_REGS : gr_regs;
8614 if (class == FP_REGS)
8618 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8621 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8623 /* We can use the l.s and l.d macros to load floating-point
8624 constants. ??? For l.s, we could probably get better
8625 code by returning GR_REGS here. */
8628 else if (gp_reg_p || x == CONST0_RTX (mode))
8630 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8633 else if (FP_REG_P (regno))
8635 /* In this case we can use mov.s or mov.d. */
8640 /* Otherwise, we need to reload through an integer register. */
8645 /* In mips16 mode, going between memory and anything but M16_REGS
8646 requires an M16_REG. */
8649 if (class != M16_REGS && class != M16_NA_REGS)
8657 if (class == M16_REGS || class == M16_NA_REGS)
8666 /* Implement CLASS_MAX_NREGS.
8668 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
8670 - ST_REGS are always hold CCmode values, and CCmode values are
8671 considered to be 4 bytes wide.
8673 All other register classes are covered by UNITS_PER_WORD. Note that
8674 this is true even for unions of integer and float registers when the
8675 latter are smaller than the former. The only supported combination
8676 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
8677 words but 32-bit float registers. A word-based calculation is correct
8678 in that case since -msingle-float disallows multi-FPR values. */
8681 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
8682 enum machine_mode mode)
8684 if (class == ST_REGS)
8685 return (GET_MODE_SIZE (mode) + 3) / 4;
8686 else if (class == FP_REGS)
8687 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8689 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8693 mips_valid_pointer_mode (enum machine_mode mode)
8695 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8698 /* Target hook for vector_mode_supported_p. */
8701 mips_vector_mode_supported_p (enum machine_mode mode)
8706 return TARGET_PAIRED_SINGLE_FLOAT;
8717 /* If we can access small data directly (using gp-relative relocation
8718 operators) return the small data pointer, otherwise return null.
8720 For each mips16 function which refers to GP relative symbols, we
8721 use a pseudo register, initialized at the start of the function, to
8722 hold the $gp value. */
8725 mips16_gp_pseudo_reg (void)
8727 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8731 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8733 /* We want to initialize this to a value which gcc will believe
8735 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
8737 push_topmost_sequence ();
8738 /* We need to emit the initialization after the FUNCTION_BEG
8739 note, so that it will be integrated. */
8740 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8742 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
8744 if (scan == NULL_RTX)
8745 scan = get_insns ();
8746 insn = emit_insn_after (insn, scan);
8747 pop_topmost_sequence ();
8750 return cfun->machine->mips16_gp_pseudo_rtx;
8753 /* Write out code to move floating point arguments in or out of
8754 general registers. Output the instructions to FILE. FP_CODE is
8755 the code describing which arguments are present (see the comment at
8756 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
8757 we are copying from the floating point registers. */
8760 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
8765 CUMULATIVE_ARGS cum;
8767 /* This code only works for the original 32-bit ABI and the O64 ABI. */
8768 gcc_assert (TARGET_OLDABI);
8775 init_cumulative_args (&cum, NULL, NULL);
8777 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8779 enum machine_mode mode;
8780 struct mips_arg_info info;
8784 else if ((f & 3) == 2)
8789 mips_arg_info (&cum, mode, NULL, true, &info);
8790 gparg = mips_arg_regno (&info, false);
8791 fparg = mips_arg_regno (&info, true);
8794 fprintf (file, "\t%s\t%s,%s\n", s,
8795 reg_names[gparg], reg_names[fparg]);
8796 else if (TARGET_64BIT)
8797 fprintf (file, "\td%s\t%s,%s\n", s,
8798 reg_names[gparg], reg_names[fparg]);
8799 else if (ISA_HAS_MXHC1)
8800 /* -mips32r2 -mfp64 */
8801 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
8803 reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
8805 from_fp_p ? "mfhc1" : "mthc1",
8806 reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
8808 else if (TARGET_BIG_ENDIAN)
8809 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8810 reg_names[gparg], reg_names[fparg + 1], s,
8811 reg_names[gparg + 1], reg_names[fparg]);
8813 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8814 reg_names[gparg], reg_names[fparg], s,
8815 reg_names[gparg + 1], reg_names[fparg + 1]);
8817 function_arg_advance (&cum, mode, NULL, true);
8821 /* Build a mips16 function stub. This is used for functions which
8822 take arguments in the floating point registers. It is 32-bit code
8823 that moves the floating point args into the general registers, and
8824 then jumps to the 16-bit code. */
8827 build_mips16_function_stub (FILE *file)
8830 char *secname, *stubname;
8831 tree stubid, stubdecl;
8835 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8836 secname = (char *) alloca (strlen (fnname) + 20);
8837 sprintf (secname, ".mips16.fn.%s", fnname);
8838 stubname = (char *) alloca (strlen (fnname) + 20);
8839 sprintf (stubname, "__fn_stub_%s", fnname);
8840 stubid = get_identifier (stubname);
8841 stubdecl = build_decl (FUNCTION_DECL, stubid,
8842 build_function_type (void_type_node, NULL_TREE));
8843 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8844 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
8846 fprintf (file, "\t# Stub function for %s (", current_function_name ());
8848 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8850 fprintf (file, "%s%s",
8851 need_comma ? ", " : "",
8852 (f & 3) == 1 ? "float" : "double");
8855 fprintf (file, ")\n");
8857 fprintf (file, "\t.set\tnomips16\n");
8858 switch_to_section (function_section (stubdecl));
8859 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8861 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8862 within a .ent, and we cannot emit another .ent. */
8863 if (!FUNCTION_NAME_ALREADY_DECLARED)
8865 fputs ("\t.ent\t", file);
8866 assemble_name (file, stubname);
8870 assemble_name (file, stubname);
8871 fputs (":\n", file);
8873 /* We don't want the assembler to insert any nops here. */
8874 fprintf (file, "\t.set\tnoreorder\n");
8876 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8878 fprintf (asm_out_file, "\t.set\tnoat\n");
8879 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8880 assemble_name (file, fnname);
8881 fprintf (file, "\n");
8882 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8883 fprintf (asm_out_file, "\t.set\tat\n");
8885 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8886 with one of the mfc1 instructions, because the result is not
8887 available for one instruction, so if the very first instruction
8888 in the function refers to the register, it will see the wrong
8890 fprintf (file, "\tnop\n");
8892 fprintf (file, "\t.set\treorder\n");
8894 if (!FUNCTION_NAME_ALREADY_DECLARED)
8896 fputs ("\t.end\t", file);
8897 assemble_name (file, stubname);
8901 fprintf (file, "\t.set\tmips16\n");
8903 switch_to_section (function_section (current_function_decl));
8906 /* We keep a list of functions for which we have already built stubs
8907 in build_mips16_call_stub. */
8911 struct mips16_stub *next;
8916 static struct mips16_stub *mips16_stubs;
8918 /* Emit code to return a double value from a mips16 stub. GPREG is the
8919 first GP reg to use, FPREG is the first FP reg to use. */
8922 mips16_fpret_double (int gpreg, int fpreg)
8925 fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
8926 reg_names[gpreg], reg_names[fpreg]);
8927 else if (TARGET_FLOAT64)
8929 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8930 reg_names[gpreg + WORDS_BIG_ENDIAN],
8932 fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
8933 reg_names[gpreg + !WORDS_BIG_ENDIAN],
8938 if (TARGET_BIG_ENDIAN)
8940 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8941 reg_names[gpreg + 0],
8942 reg_names[fpreg + 1]);
8943 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8944 reg_names[gpreg + 1],
8945 reg_names[fpreg + 0]);
8949 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8950 reg_names[gpreg + 0],
8951 reg_names[fpreg + 0]);
8952 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8953 reg_names[gpreg + 1],
8954 reg_names[fpreg + 1]);
8959 /* Build a call stub for a mips16 call. A stub is needed if we are
8960 passing any floating point values which should go into the floating
8961 point registers. If we are, and the call turns out to be to a
8962 32-bit function, the stub will be used to move the values into the
8963 floating point registers before calling the 32-bit function. The
8964 linker will magically adjust the function call to either the 16-bit
8965 function or the 32-bit stub, depending upon where the function call
8966 is actually defined.
8968 Similarly, we need a stub if the return value might come back in a
8969 floating point register.
8971 RETVAL is the location of the return value, or null if this is
8972 a call rather than a call_value. FN is the address of the
8973 function and ARG_SIZE is the size of the arguments. FP_CODE
8974 is the code built by function_arg. This function returns a nonzero
8975 value if it builds the call instruction itself. */
8978 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8982 char *secname, *stubname;
8983 struct mips16_stub *l;
8984 tree stubid, stubdecl;
8988 /* We don't need to do anything if we aren't in mips16 mode, or if
8989 we were invoked with the -msoft-float option. */
8990 if (!mips16_hard_float)
8993 /* Figure out whether the value might come back in a floating point
8996 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
8998 /* We don't need to do anything if there were no floating point
8999 arguments and the value will not be returned in a floating point
9001 if (fp_code == 0 && ! fpret)
9004 /* We don't need to do anything if this is a call to a special
9005 mips16 support function. */
9006 if (GET_CODE (fn) == SYMBOL_REF
9007 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
9010 /* This code will only work for o32 and o64 abis. The other ABI's
9011 require more sophisticated support. */
9012 gcc_assert (TARGET_OLDABI);
9014 /* If we're calling via a function pointer, then we must always call
9015 via a stub. There are magic stubs provided in libgcc.a for each
9016 of the required cases. Each of them expects the function address
9017 to arrive in register $2. */
9019 if (GET_CODE (fn) != SYMBOL_REF)
9025 /* ??? If this code is modified to support other ABI's, we need
9026 to handle PARALLEL return values here. */
9029 sprintf (buf, "__mips16_call_stub_%s_%d",
9030 mips16_call_stub_mode_suffix (GET_MODE (retval)),
9033 sprintf (buf, "__mips16_call_stub_%d",
9036 id = get_identifier (buf);
9037 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
9039 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
9041 if (retval == NULL_RTX)
9042 insn = gen_call_internal (stub_fn, arg_size);
9044 insn = gen_call_value_internal (retval, stub_fn, arg_size);
9045 insn = emit_call_insn (insn);
9047 /* Put the register usage information on the CALL. */
9048 CALL_INSN_FUNCTION_USAGE (insn) =
9049 gen_rtx_EXPR_LIST (VOIDmode,
9050 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
9051 CALL_INSN_FUNCTION_USAGE (insn));
9053 /* If we are handling a floating point return value, we need to
9054 save $18 in the function prologue. Putting a note on the
9055 call will mean that df_regs_ever_live_p ($18) will be true if the
9056 call is not eliminated, and we can check that in the prologue
9059 CALL_INSN_FUNCTION_USAGE (insn) =
9060 gen_rtx_EXPR_LIST (VOIDmode,
9061 gen_rtx_USE (VOIDmode,
9062 gen_rtx_REG (word_mode, 18)),
9063 CALL_INSN_FUNCTION_USAGE (insn));
9065 /* Return 1 to tell the caller that we've generated the call
9070 /* We know the function we are going to call. If we have already
9071 built a stub, we don't need to do anything further. */
9073 fnname = XSTR (fn, 0);
9074 for (l = mips16_stubs; l != NULL; l = l->next)
9075 if (strcmp (l->name, fnname) == 0)
9080 /* Build a special purpose stub. When the linker sees a
9081 function call in mips16 code, it will check where the target
9082 is defined. If the target is a 32-bit call, the linker will
9083 search for the section defined here. It can tell which
9084 symbol this section is associated with by looking at the
9085 relocation information (the name is unreliable, since this
9086 might be a static function). If such a section is found, the
9087 linker will redirect the call to the start of the magic
9090 If the function does not return a floating point value, the
9091 special stub section is named
9094 If the function does return a floating point value, the stub
9096 .mips16.call.fp.FNNAME
9099 secname = (char *) alloca (strlen (fnname) + 40);
9100 sprintf (secname, ".mips16.call.%s%s",
9103 stubname = (char *) alloca (strlen (fnname) + 20);
9104 sprintf (stubname, "__call_stub_%s%s",
9107 stubid = get_identifier (stubname);
9108 stubdecl = build_decl (FUNCTION_DECL, stubid,
9109 build_function_type (void_type_node, NULL_TREE));
9110 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9111 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
9113 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9115 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9119 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9121 fprintf (asm_out_file, "%s%s",
9122 need_comma ? ", " : "",
9123 (f & 3) == 1 ? "float" : "double");
9126 fprintf (asm_out_file, ")\n");
9128 fprintf (asm_out_file, "\t.set\tnomips16\n");
9129 assemble_start_function (stubdecl, stubname);
9131 if (!FUNCTION_NAME_ALREADY_DECLARED)
9133 fputs ("\t.ent\t", asm_out_file);
9134 assemble_name (asm_out_file, stubname);
9135 fputs ("\n", asm_out_file);
9137 assemble_name (asm_out_file, stubname);
9138 fputs (":\n", asm_out_file);
9141 /* We build the stub code by hand. That's the only way we can
9142 do it, since we can't generate 32-bit code during a 16-bit
9145 /* We don't want the assembler to insert any nops here. */
9146 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9148 mips16_fp_args (asm_out_file, fp_code, 0);
9152 fprintf (asm_out_file, "\t.set\tnoat\n");
9153 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9155 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9156 fprintf (asm_out_file, "\t.set\tat\n");
9157 /* Unfortunately, we can't fill the jump delay slot. We
9158 can't fill with one of the mtc1 instructions, because the
9159 result is not available for one instruction, so if the
9160 very first instruction in the function refers to the
9161 register, it will see the wrong value. */
9162 fprintf (asm_out_file, "\tnop\n");
9166 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9167 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9168 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9169 /* As above, we can't fill the delay slot. */
9170 fprintf (asm_out_file, "\tnop\n");
9171 if (GET_MODE (retval) == SFmode)
9172 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9173 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9174 else if (GET_MODE (retval) == SCmode)
9176 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9177 reg_names[GP_REG_FIRST + 2],
9178 reg_names[FP_REG_FIRST + 0]);
9179 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9180 reg_names[GP_REG_FIRST + 3],
9181 reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
9183 else if (GET_MODE (retval) == DFmode
9184 || GET_MODE (retval) == V2SFmode)
9186 mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
9188 else if (GET_MODE (retval) == DCmode)
9190 mips16_fpret_double (GP_REG_FIRST + 2,
9192 mips16_fpret_double (GP_REG_FIRST + 4,
9193 FP_REG_FIRST + MAX_FPRS_PER_FMT);
9197 if (TARGET_BIG_ENDIAN)
9199 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9200 reg_names[GP_REG_FIRST + 2],
9201 reg_names[FP_REG_FIRST + 1]);
9202 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9203 reg_names[GP_REG_FIRST + 3],
9204 reg_names[FP_REG_FIRST + 0]);
9208 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9209 reg_names[GP_REG_FIRST + 2],
9210 reg_names[FP_REG_FIRST + 0]);
9211 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9212 reg_names[GP_REG_FIRST + 3],
9213 reg_names[FP_REG_FIRST + 1]);
9216 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9217 /* As above, we can't fill the delay slot. */
9218 fprintf (asm_out_file, "\tnop\n");
9221 fprintf (asm_out_file, "\t.set\treorder\n");
9223 #ifdef ASM_DECLARE_FUNCTION_SIZE
9224 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9227 if (!FUNCTION_NAME_ALREADY_DECLARED)
9229 fputs ("\t.end\t", asm_out_file);
9230 assemble_name (asm_out_file, stubname);
9231 fputs ("\n", asm_out_file);
9234 fprintf (asm_out_file, "\t.set\tmips16\n");
9236 /* Record this stub. */
9237 l = (struct mips16_stub *) xmalloc (sizeof *l);
9238 l->name = xstrdup (fnname);
9240 l->next = mips16_stubs;
9244 /* If we expect a floating point return value, but we've built a
9245 stub which does not expect one, then we're in trouble. We can't
9246 use the existing stub, because it won't handle the floating point
9247 value. We can't build a new stub, because the linker won't know
9248 which stub to use for the various calls in this object file.
9249 Fortunately, this case is illegal, since it means that a function
9250 was declared in two different ways in a single compilation. */
9251 if (fpret && ! l->fpret)
9252 error ("cannot handle inconsistent calls to %qs", fnname);
9254 /* If we are calling a stub which handles a floating point return
9255 value, we need to arrange to save $18 in the prologue. We do
9256 this by marking the function call as using the register. The
9257 prologue will later see that it is used, and emit code to save
9264 if (retval == NULL_RTX)
9265 insn = gen_call_internal (fn, arg_size);
9267 insn = gen_call_value_internal (retval, fn, arg_size);
9268 insn = emit_call_insn (insn);
9270 CALL_INSN_FUNCTION_USAGE (insn) =
9271 gen_rtx_EXPR_LIST (VOIDmode,
9272 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
9273 CALL_INSN_FUNCTION_USAGE (insn));
9275 /* Return 1 to tell the caller that we've generated the call
9280 /* Return 0 to let the caller generate the call insn. */
9284 /* An entry in the mips16 constant pool. VALUE is the pool constant,
9285 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
9287 struct mips16_constant {
9288 struct mips16_constant *next;
9291 enum machine_mode mode;
9294 /* Information about an incomplete mips16 constant pool. FIRST is the
9295 first constant, HIGHEST_ADDRESS is the highest address that the first
9296 byte of the pool can have, and INSN_ADDRESS is the current instruction
9299 struct mips16_constant_pool {
9300 struct mips16_constant *first;
9301 int highest_address;
9305 /* Add constant VALUE to POOL and return its label. MODE is the
9306 value's mode (used for CONST_INTs, etc.). */
9309 add_constant (struct mips16_constant_pool *pool,
9310 rtx value, enum machine_mode mode)
9312 struct mips16_constant **p, *c;
9313 bool first_of_size_p;
9315 /* See whether the constant is already in the pool. If so, return the
9316 existing label, otherwise leave P pointing to the place where the
9317 constant should be added.
9319 Keep the pool sorted in increasing order of mode size so that we can
9320 reduce the number of alignments needed. */
9321 first_of_size_p = true;
9322 for (p = &pool->first; *p != 0; p = &(*p)->next)
9324 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
9326 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
9328 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
9329 first_of_size_p = false;
9332 /* In the worst case, the constant needed by the earliest instruction
9333 will end up at the end of the pool. The entire pool must then be
9334 accessible from that instruction.
9336 When adding the first constant, set the pool's highest address to
9337 the address of the first out-of-range byte. Adjust this address
9338 downwards each time a new constant is added. */
9339 if (pool->first == 0)
9340 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
9341 is the address of the instruction with the lowest two bits clear.
9342 The base PC value for ld has the lowest three bits clear. Assume
9343 the worst case here. */
9344 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
9345 pool->highest_address -= GET_MODE_SIZE (mode);
9346 if (first_of_size_p)
9347 /* Take into account the worst possible padding due to alignment. */
9348 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
9350 /* Create a new entry. */
9351 c = (struct mips16_constant *) xmalloc (sizeof *c);
9354 c->label = gen_label_rtx ();
9361 /* Output constant VALUE after instruction INSN and return the last
9362 instruction emitted. MODE is the mode of the constant. */
9365 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
9367 switch (GET_MODE_CLASS (mode))
9371 rtx size = GEN_INT (GET_MODE_SIZE (mode));
9372 return emit_insn_after (gen_consttable_int (value, size), insn);
9376 return emit_insn_after (gen_consttable_float (value), insn);
9378 case MODE_VECTOR_FLOAT:
9379 case MODE_VECTOR_INT:
9382 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
9383 insn = dump_constants_1 (GET_MODE_INNER (mode),
9384 CONST_VECTOR_ELT (value, i), insn);
9394 /* Dump out the constants in CONSTANTS after INSN. */
9397 dump_constants (struct mips16_constant *constants, rtx insn)
9399 struct mips16_constant *c, *next;
9403 for (c = constants; c != NULL; c = next)
9405 /* If necessary, increase the alignment of PC. */
9406 if (align < GET_MODE_SIZE (c->mode))
9408 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
9409 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
9411 align = GET_MODE_SIZE (c->mode);
9413 insn = emit_label_after (c->label, insn);
9414 insn = dump_constants_1 (c->mode, c->value, insn);
9420 emit_barrier_after (insn);
9423 /* Return the length of instruction INSN. */
9426 mips16_insn_length (rtx insn)
9430 rtx body = PATTERN (insn);
9431 if (GET_CODE (body) == ADDR_VEC)
9432 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
9433 if (GET_CODE (body) == ADDR_DIFF_VEC)
9434 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
9436 return get_attr_length (insn);
9439 /* Rewrite *X so that constant pool references refer to the constant's
9440 label instead. DATA points to the constant pool structure. */
9443 mips16_rewrite_pool_refs (rtx *x, void *data)
9445 struct mips16_constant_pool *pool = data;
9446 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
9447 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
9448 get_pool_constant (*x),
9449 get_pool_mode (*x)));
9453 /* Build MIPS16 constant pools. */
9456 mips16_lay_out_constants (void)
9458 struct mips16_constant_pool pool;
9462 memset (&pool, 0, sizeof (pool));
9463 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9465 /* Rewrite constant pool references in INSN. */
9467 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
9469 pool.insn_address += mips16_insn_length (insn);
9471 if (pool.first != NULL)
9473 /* If there are no natural barriers between the first user of
9474 the pool and the highest acceptable address, we'll need to
9475 create a new instruction to jump around the constant pool.
9476 In the worst case, this instruction will be 4 bytes long.
9478 If it's too late to do this transformation after INSN,
9479 do it immediately before INSN. */
9480 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
9484 label = gen_label_rtx ();
9486 jump = emit_jump_insn_before (gen_jump (label), insn);
9487 JUMP_LABEL (jump) = label;
9488 LABEL_NUSES (label) = 1;
9489 barrier = emit_barrier_after (jump);
9491 emit_label_after (label, barrier);
9492 pool.insn_address += 4;
9495 /* See whether the constant pool is now out of range of the first
9496 user. If so, output the constants after the previous barrier.
9497 Note that any instructions between BARRIER and INSN (inclusive)
9498 will use negative offsets to refer to the pool. */
9499 if (pool.insn_address > pool.highest_address)
9501 dump_constants (pool.first, barrier);
9505 else if (BARRIER_P (insn))
9509 dump_constants (pool.first, get_last_insn ());
9512 /* A temporary variable used by for_each_rtx callbacks, etc. */
9513 static rtx mips_sim_insn;
9515 /* A structure representing the state of the processor pipeline.
9516 Used by the mips_sim_* family of functions. */
9518 /* The maximum number of instructions that can be issued in a cycle.
9519 (Caches mips_issue_rate.) */
9520 unsigned int issue_rate;
9522 /* The current simulation time. */
9525 /* How many more instructions can be issued in the current cycle. */
9526 unsigned int insns_left;
9528 /* LAST_SET[X].INSN is the last instruction to set register X.
9529 LAST_SET[X].TIME is the time at which that instruction was issued.
9530 INSN is null if no instruction has yet set register X. */
9534 } last_set[FIRST_PSEUDO_REGISTER];
9536 /* The pipeline's current DFA state. */
9540 /* Reset STATE to the initial simulation state. */
9543 mips_sim_reset (struct mips_sim *state)
9546 state->insns_left = state->issue_rate;
9547 memset (&state->last_set, 0, sizeof (state->last_set));
9548 state_reset (state->dfa_state);
9551 /* Initialize STATE before its first use. DFA_STATE points to an
9552 allocated but uninitialized DFA state. */
9555 mips_sim_init (struct mips_sim *state, state_t dfa_state)
9557 state->issue_rate = mips_issue_rate ();
9558 state->dfa_state = dfa_state;
9559 mips_sim_reset (state);
9562 /* Advance STATE by one clock cycle. */
9565 mips_sim_next_cycle (struct mips_sim *state)
9568 state->insns_left = state->issue_rate;
9569 state_transition (state->dfa_state, 0);
9572 /* Advance simulation state STATE until instruction INSN can read
9576 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
9580 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
9581 if (state->last_set[REGNO (reg) + i].insn != 0)
9585 t = state->last_set[REGNO (reg) + i].time;
9586 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
9587 while (state->time < t)
9588 mips_sim_next_cycle (state);
9592 /* A for_each_rtx callback. If *X is a register, advance simulation state
9593 DATA until mips_sim_insn can read the register's value. */
9596 mips_sim_wait_regs_2 (rtx *x, void *data)
9599 mips_sim_wait_reg (data, mips_sim_insn, *x);
9603 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
9606 mips_sim_wait_regs_1 (rtx *x, void *data)
9608 for_each_rtx (x, mips_sim_wait_regs_2, data);
9611 /* Advance simulation state STATE until all of INSN's register
9612 dependencies are satisfied. */
9615 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
9617 mips_sim_insn = insn;
9618 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
9621 /* Advance simulation state STATE until the units required by
9622 instruction INSN are available. */
9625 mips_sim_wait_units (struct mips_sim *state, rtx insn)
9629 tmp_state = alloca (state_size ());
9630 while (state->insns_left == 0
9631 || (memcpy (tmp_state, state->dfa_state, state_size ()),
9632 state_transition (tmp_state, insn) >= 0))
9633 mips_sim_next_cycle (state);
9636 /* Advance simulation state STATE until INSN is ready to issue. */
9639 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
9641 mips_sim_wait_regs (state, insn);
9642 mips_sim_wait_units (state, insn);
9645 /* mips_sim_insn has just set X. Update the LAST_SET array
9646 in simulation state DATA. */
9649 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9651 struct mips_sim *state;
9656 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
9658 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
9659 state->last_set[REGNO (x) + i].time = state->time;
9663 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
9664 can issue immediately (i.e., that mips_sim_wait_insn has already
9668 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
9670 state_transition (state->dfa_state, insn);
9671 state->insns_left--;
9673 mips_sim_insn = insn;
9674 note_stores (PATTERN (insn), mips_sim_record_set, state);
9677 /* Simulate issuing a NOP in state STATE. */
9680 mips_sim_issue_nop (struct mips_sim *state)
9682 if (state->insns_left == 0)
9683 mips_sim_next_cycle (state);
9684 state->insns_left--;
9687 /* Update simulation state STATE so that it's ready to accept the instruction
9688 after INSN. INSN should be part of the main rtl chain, not a member of a
9692 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
9694 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
9696 mips_sim_issue_nop (state);
9698 switch (GET_CODE (SEQ_BEGIN (insn)))
9702 /* We can't predict the processor state after a call or label. */
9703 mips_sim_reset (state);
9707 /* The delay slots of branch likely instructions are only executed
9708 when the branch is taken. Therefore, if the caller has simulated
9709 the delay slot instruction, STATE does not really reflect the state
9710 of the pipeline for the instruction after the delay slot. Also,
9711 branch likely instructions tend to incur a penalty when not taken,
9712 so there will probably be an extra delay between the branch and
9713 the instruction after the delay slot. */
9714 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
9715 mips_sim_reset (state);
9723 /* The VR4130 pipeline issues aligned pairs of instructions together,
9724 but it stalls the second instruction if it depends on the first.
9725 In order to cut down the amount of logic required, this dependence
9726 check is not based on a full instruction decode. Instead, any non-SPECIAL
9727 instruction is assumed to modify the register specified by bits 20-16
9728 (which is usually the "rt" field).
9730 In beq, beql, bne and bnel instructions, the rt field is actually an
9731 input, so we can end up with a false dependence between the branch
9732 and its delay slot. If this situation occurs in instruction INSN,
9733 try to avoid it by swapping rs and rt. */
9736 vr4130_avoid_branch_rt_conflict (rtx insn)
9740 first = SEQ_BEGIN (insn);
9741 second = SEQ_END (insn);
9743 && NONJUMP_INSN_P (second)
9744 && GET_CODE (PATTERN (first)) == SET
9745 && GET_CODE (SET_DEST (PATTERN (first))) == PC
9746 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
9748 /* Check for the right kind of condition. */
9749 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
9750 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
9751 && REG_P (XEXP (cond, 0))
9752 && REG_P (XEXP (cond, 1))
9753 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
9754 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
9756 /* SECOND mentions the rt register but not the rs register. */
9757 rtx tmp = XEXP (cond, 0);
9758 XEXP (cond, 0) = XEXP (cond, 1);
9759 XEXP (cond, 1) = tmp;
9764 /* Implement -mvr4130-align. Go through each basic block and simulate the
9765 processor pipeline. If we find that a pair of instructions could execute
9766 in parallel, and the first of those instruction is not 8-byte aligned,
9767 insert a nop to make it aligned. */
9770 vr4130_align_insns (void)
9772 struct mips_sim state;
9773 rtx insn, subinsn, last, last2, next;
9778 /* LAST is the last instruction before INSN to have a nonzero length.
9779 LAST2 is the last such instruction before LAST. */
9783 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
9786 mips_sim_init (&state, alloca (state_size ()));
9787 for (insn = get_insns (); insn != 0; insn = next)
9789 unsigned int length;
9791 next = NEXT_INSN (insn);
9793 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
9794 This isn't really related to the alignment pass, but we do it on
9795 the fly to avoid a separate instruction walk. */
9796 vr4130_avoid_branch_rt_conflict (insn);
9798 if (USEFUL_INSN_P (insn))
9799 FOR_EACH_SUBINSN (subinsn, insn)
9801 mips_sim_wait_insn (&state, subinsn);
9803 /* If we want this instruction to issue in parallel with the
9804 previous one, make sure that the previous instruction is
9805 aligned. There are several reasons why this isn't worthwhile
9806 when the second instruction is a call:
9808 - Calls are less likely to be performance critical,
9809 - There's a good chance that the delay slot can execute
9810 in parallel with the call.
9811 - The return address would then be unaligned.
9813 In general, if we're going to insert a nop between instructions
9814 X and Y, it's better to insert it immediately after X. That
9815 way, if the nop makes Y aligned, it will also align any labels
9817 if (state.insns_left != state.issue_rate
9818 && !CALL_P (subinsn))
9820 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
9822 /* SUBINSN is the first instruction in INSN and INSN is
9823 aligned. We want to align the previous instruction
9824 instead, so insert a nop between LAST2 and LAST.
9826 Note that LAST could be either a single instruction
9827 or a branch with a delay slot. In the latter case,
9828 LAST, like INSN, is already aligned, but the delay
9829 slot must have some extra delay that stops it from
9830 issuing at the same time as the branch. We therefore
9831 insert a nop before the branch in order to align its
9833 emit_insn_after (gen_nop (), last2);
9836 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
9838 /* SUBINSN is the delay slot of INSN, but INSN is
9839 currently unaligned. Insert a nop between
9840 LAST and INSN to align it. */
9841 emit_insn_after (gen_nop (), last);
9845 mips_sim_issue_insn (&state, subinsn);
9847 mips_sim_finish_insn (&state, insn);
9849 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
9850 length = get_attr_length (insn);
9853 /* If the instruction is an asm statement or multi-instruction
9854 mips.md patern, the length is only an estimate. Insert an
9855 8 byte alignment after it so that the following instructions
9856 can be handled correctly. */
9857 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
9858 && (recog_memoized (insn) < 0 || length >= 8))
9860 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
9861 next = NEXT_INSN (next);
9862 mips_sim_next_cycle (&state);
9865 else if (length & 4)
9866 aligned_p = !aligned_p;
9871 /* See whether INSN is an aligned label. */
9872 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
9878 /* Subroutine of mips_reorg. If there is a hazard between INSN
9879 and a previous instruction, avoid it by inserting nops after
9882 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
9883 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
9884 before using the value of that register. *HILO_DELAY counts the
9885 number of instructions since the last hilo hazard (that is,
9886 the number of instructions since the last mflo or mfhi).
9888 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
9889 for the next instruction.
9891 LO_REG is an rtx for the LO register, used in dependence checking. */
9894 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
9895 rtx *delayed_reg, rtx lo_reg)
9903 pattern = PATTERN (insn);
9905 /* Do not put the whole function in .set noreorder if it contains
9906 an asm statement. We don't know whether there will be hazards
9907 between the asm statement and the gcc-generated code. */
9908 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
9909 cfun->machine->all_noreorder_p = false;
9911 /* Ignore zero-length instructions (barriers and the like). */
9912 ninsns = get_attr_length (insn) / 4;
9916 /* Work out how many nops are needed. Note that we only care about
9917 registers that are explicitly mentioned in the instruction's pattern.
9918 It doesn't matter that calls use the argument registers or that they
9919 clobber hi and lo. */
9920 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
9921 nops = 2 - *hilo_delay;
9922 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9927 /* Insert the nops between this instruction and the previous one.
9928 Each new nop takes us further from the last hilo hazard. */
9929 *hilo_delay += nops;
9931 emit_insn_after (gen_hazard_nop (), after);
9933 /* Set up the state for the next instruction. */
9934 *hilo_delay += ninsns;
9936 if (INSN_CODE (insn) >= 0)
9937 switch (get_attr_hazard (insn))
9947 set = single_set (insn);
9948 gcc_assert (set != 0);
9949 *delayed_reg = SET_DEST (set);
9955 /* Go through the instruction stream and insert nops where necessary.
9956 See if the whole function can then be put into .set noreorder &
9960 mips_avoid_hazards (void)
9962 rtx insn, last_insn, lo_reg, delayed_reg;
9965 /* Force all instructions to be split into their final form. */
9966 split_all_insns_noflow ();
9968 /* Recalculate instruction lengths without taking nops into account. */
9969 cfun->machine->ignore_hazard_length_p = true;
9970 shorten_branches (get_insns ());
9972 cfun->machine->all_noreorder_p = true;
9974 /* Profiled functions can't be all noreorder because the profiler
9975 support uses assembler macros. */
9976 if (current_function_profile)
9977 cfun->machine->all_noreorder_p = false;
9979 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9980 we rely on the assembler to work around some errata. */
9981 if (TARGET_FIX_VR4120)
9982 cfun->machine->all_noreorder_p = false;
9984 /* The same is true for -mfix-vr4130 if we might generate mflo or
9985 mfhi instructions. Note that we avoid using mflo and mfhi if
9986 the VR4130 macc and dmacc instructions are available instead;
9987 see the *mfhilo_{si,di}_macc patterns. */
9988 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9989 cfun->machine->all_noreorder_p = false;
9994 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9996 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9999 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10000 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
10001 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
10002 &hilo_delay, &delayed_reg, lo_reg);
10004 mips_avoid_hazard (last_insn, insn, &hilo_delay,
10005 &delayed_reg, lo_reg);
10012 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
10018 mips16_lay_out_constants ();
10019 else if (TARGET_EXPLICIT_RELOCS)
10021 if (mips_flag_delayed_branch)
10022 dbr_schedule (get_insns ());
10023 mips_avoid_hazards ();
10024 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
10025 vr4130_align_insns ();
10029 /* This function does three things:
10031 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
10032 - Register the mips16 hardware floating point stubs.
10033 - Register the gofast functions if selected using --enable-gofast. */
10035 #include "config/gofast.h"
10038 mips_init_libfuncs (void)
10040 if (TARGET_FIX_VR4120)
10042 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10043 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10046 if (mips16_hard_float)
10048 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10049 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10050 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10051 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10053 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10054 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10055 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10056 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10057 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10058 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10060 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10061 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10063 if (TARGET_DOUBLE_FLOAT)
10065 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10066 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10067 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10068 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10070 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10071 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10072 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10073 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10074 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10075 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10077 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
10078 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
10080 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
10081 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
10085 gofast_maybe_init_libfuncs ();
10088 /* Return a number assessing the cost of moving a register in class
10089 FROM to class TO. The classes are expressed using the enumeration
10090 values such as `GENERAL_REGS'. A value of 2 is the default; other
10091 values are interpreted relative to that.
10093 It is not required that the cost always equal 2 when FROM is the
10094 same as TO; on some machines it is expensive to move between
10095 registers if they are not general registers.
10097 If reload sees an insn consisting of a single `set' between two
10098 hard registers, and if `REGISTER_MOVE_COST' applied to their
10099 classes returns a value of 2, reload does not check to ensure that
10100 the constraints of the insn are met. Setting a cost of other than
10101 2 will allow reload to verify that the constraints are met. You
10102 should do this if the `movM' pattern's constraints do not allow
10105 ??? We make the cost of moving from HI/LO into general
10106 registers the same as for one of moving general registers to
10107 HI/LO for TARGET_MIPS16 in order to prevent allocating a
10108 pseudo to HI/LO. This might hurt optimizations though, it
10109 isn't clear if it is wise. And it might not work in all cases. We
10110 could solve the DImode LO reg problem by using a multiply, just
10111 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10112 problem by using divide instructions. divu puts the remainder in
10113 the HI reg, so doing a divide by -1 will move the value in the HI
10114 reg for all values except -1. We could handle that case by using a
10115 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10116 a compare/branch to test the input value to see which instruction
10117 we need to use. This gets pretty messy, but it is feasible. */
10120 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10121 enum reg_class to, enum reg_class from)
10123 if (from == M16_REGS && GR_REG_CLASS_P (to))
10125 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
10127 else if (GR_REG_CLASS_P (from))
10129 if (to == M16_REGS)
10131 else if (to == M16_NA_REGS)
10133 else if (GR_REG_CLASS_P (to))
10140 else if (to == FP_REGS)
10142 else if (reg_class_subset_p (to, ACC_REGS))
10149 else if (COP_REG_CLASS_P (to))
10154 else if (from == FP_REGS)
10156 if (GR_REG_CLASS_P (to))
10158 else if (to == FP_REGS)
10160 else if (to == ST_REGS)
10163 else if (reg_class_subset_p (from, ACC_REGS))
10165 if (GR_REG_CLASS_P (to))
10173 else if (from == ST_REGS && GR_REG_CLASS_P (to))
10175 else if (COP_REG_CLASS_P (from))
10181 ??? What cases are these? Shouldn't we return 2 here? */
10186 /* Return the length of INSN. LENGTH is the initial length computed by
10187 attributes in the machine-description file. */
10190 mips_adjust_insn_length (rtx insn, int length)
10192 /* A unconditional jump has an unfilled delay slot if it is not part
10193 of a sequence. A conditional jump normally has a delay slot, but
10194 does not on MIPS16. */
10195 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10198 /* See how many nops might be needed to avoid hardware hazards. */
10199 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10200 switch (get_attr_hazard (insn))
10214 /* All MIPS16 instructions are a measly two bytes. */
10222 /* Return an asm sequence to start a noat block and load the address
10223 of a label into $1. */
10226 mips_output_load_label (void)
10228 if (TARGET_EXPLICIT_RELOCS)
10232 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10235 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10238 if (ISA_HAS_LOAD_DELAY)
10239 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10240 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10244 if (Pmode == DImode)
10245 return "%[dla\t%@,%0";
10247 return "%[la\t%@,%0";
10251 /* Return the assembly code for INSN, which has the operands given by
10252 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10253 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10254 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10255 version of BRANCH_IF_TRUE. */
10258 mips_output_conditional_branch (rtx insn, rtx *operands,
10259 const char *branch_if_true,
10260 const char *branch_if_false)
10262 unsigned int length;
10263 rtx taken, not_taken;
10265 length = get_attr_length (insn);
10268 /* Just a simple conditional branch. */
10269 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10270 return branch_if_true;
10273 /* Generate a reversed branch around a direct jump. This fallback does
10274 not use branch-likely instructions. */
10275 mips_branch_likely = false;
10276 not_taken = gen_label_rtx ();
10277 taken = operands[1];
10279 /* Generate the reversed branch to NOT_TAKEN. */
10280 operands[1] = not_taken;
10281 output_asm_insn (branch_if_false, operands);
10283 /* If INSN has a delay slot, we must provide delay slots for both the
10284 branch to NOT_TAKEN and the conditional jump. We must also ensure
10285 that INSN's delay slot is executed in the appropriate cases. */
10286 if (final_sequence)
10288 /* This first delay slot will always be executed, so use INSN's
10289 delay slot if is not annulled. */
10290 if (!INSN_ANNULLED_BRANCH_P (insn))
10292 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10293 asm_out_file, optimize, 1, NULL);
10294 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10297 output_asm_insn ("nop", 0);
10298 fprintf (asm_out_file, "\n");
10301 /* Output the unconditional branch to TAKEN. */
10303 output_asm_insn ("j\t%0%/", &taken);
10306 output_asm_insn (mips_output_load_label (), &taken);
10307 output_asm_insn ("jr\t%@%]%/", 0);
10310 /* Now deal with its delay slot; see above. */
10311 if (final_sequence)
10313 /* This delay slot will only be executed if the branch is taken.
10314 Use INSN's delay slot if is annulled. */
10315 if (INSN_ANNULLED_BRANCH_P (insn))
10317 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10318 asm_out_file, optimize, 1, NULL);
10319 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10322 output_asm_insn ("nop", 0);
10323 fprintf (asm_out_file, "\n");
10326 /* Output NOT_TAKEN. */
10327 (*targetm.asm_out.internal_label) (asm_out_file, "L",
10328 CODE_LABEL_NUMBER (not_taken));
10332 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10333 if some ordered condition is true. The condition is given by
10334 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10335 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10336 its second is always zero. */
10339 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10341 const char *branch[2];
10343 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10344 Make BRANCH[0] branch on the inverse condition. */
10345 switch (GET_CODE (operands[0]))
10347 /* These cases are equivalent to comparisons against zero. */
10349 inverted_p = !inverted_p;
10350 /* Fall through. */
10352 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10353 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10356 /* These cases are always true or always false. */
10358 inverted_p = !inverted_p;
10359 /* Fall through. */
10361 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10362 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10366 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10367 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10370 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10373 /* Used to output div or ddiv instruction DIVISION, which has the operands
10374 given by OPERANDS. Add in a divide-by-zero check if needed.
10376 When working around R4000 and R4400 errata, we need to make sure that
10377 the division is not immediately followed by a shift[1][2]. We also
10378 need to stop the division from being put into a branch delay slot[3].
10379 The easiest way to avoid both problems is to add a nop after the
10380 division. When a divide-by-zero check is needed, this nop can be
10381 used to fill the branch delay slot.
10383 [1] If a double-word or a variable shift executes immediately
10384 after starting an integer division, the shift may give an
10385 incorrect result. See quotations of errata #16 and #28 from
10386 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10387 in mips.md for details.
10389 [2] A similar bug to [1] exists for all revisions of the
10390 R4000 and the R4400 when run in an MC configuration.
10391 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10393 "19. In this following sequence:
10395 ddiv (or ddivu or div or divu)
10396 dsll32 (or dsrl32, dsra32)
10398 if an MPT stall occurs, while the divide is slipping the cpu
10399 pipeline, then the following double shift would end up with an
10402 Workaround: The compiler needs to avoid generating any
10403 sequence with divide followed by extended double shift."
10405 This erratum is also present in "MIPS R4400MC Errata, Processor
10406 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10407 & 3.0" as errata #10 and #4, respectively.
10409 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10410 (also valid for MIPS R4000MC processors):
10412 "52. R4000SC: This bug does not apply for the R4000PC.
10414 There are two flavors of this bug:
10416 1) If the instruction just after divide takes an RF exception
10417 (tlb-refill, tlb-invalid) and gets an instruction cache
10418 miss (both primary and secondary) and the line which is
10419 currently in secondary cache at this index had the first
10420 data word, where the bits 5..2 are set, then R4000 would
10421 get a wrong result for the div.
10426 ------------------- # end-of page. -tlb-refill
10431 ------------------- # end-of page. -tlb-invalid
10434 2) If the divide is in the taken branch delay slot, where the
10435 target takes RF exception and gets an I-cache miss for the
10436 exception vector or where I-cache miss occurs for the
10437 target address, under the above mentioned scenarios, the
10438 div would get wrong results.
10441 j r2 # to next page mapped or unmapped
10442 div r8,r9 # this bug would be there as long
10443 # as there is an ICache miss and
10444 nop # the "data pattern" is present
10447 beq r0, r0, NextPage # to Next page
10451 This bug is present for div, divu, ddiv, and ddivu
10454 Workaround: For item 1), OS could make sure that the next page
10455 after the divide instruction is also mapped. For item 2), the
10456 compiler could make sure that the divide instruction is not in
10457 the branch delay slot."
10459 These processors have PRId values of 0x00004220 and 0x00004300 for
10460 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10463 mips_output_division (const char *division, rtx *operands)
10468 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10470 output_asm_insn (s, operands);
10473 if (TARGET_CHECK_ZERO_DIV)
10477 output_asm_insn (s, operands);
10478 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10480 else if (GENERATE_DIVIDE_TRAPS)
10482 output_asm_insn (s, operands);
10483 s = "teq\t%2,%.,7";
10487 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10488 output_asm_insn (s, operands);
10489 s = "break\t7%)\n1:";
10495 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10496 with a final "000" replaced by "k". Ignore case.
10498 Note: this function is shared between GCC and GAS. */
10501 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
10503 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10504 given++, canonical++;
10506 return ((*given == 0 && *canonical == 0)
10507 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10511 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10512 CPU name. We've traditionally allowed a lot of variation here.
10514 Note: this function is shared between GCC and GAS. */
10517 mips_matching_cpu_name_p (const char *canonical, const char *given)
10519 /* First see if the name matches exactly, or with a final "000"
10520 turned into "k". */
10521 if (mips_strict_matching_cpu_name_p (canonical, given))
10524 /* If not, try comparing based on numerical designation alone.
10525 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10526 if (TOLOWER (*given) == 'r')
10528 if (!ISDIGIT (*given))
10531 /* Skip over some well-known prefixes in the canonical name,
10532 hoping to find a number there too. */
10533 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10535 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10537 else if (TOLOWER (canonical[0]) == 'r')
10540 return mips_strict_matching_cpu_name_p (canonical, given);
10544 /* Return the mips_cpu_info entry for the processor or ISA given
10545 by CPU_STRING. Return null if the string isn't recognized.
10547 A similar function exists in GAS. */
10549 static const struct mips_cpu_info *
10550 mips_parse_cpu (const char *cpu_string)
10552 const struct mips_cpu_info *p;
10555 /* In the past, we allowed upper-case CPU names, but it doesn't
10556 work well with the multilib machinery. */
10557 for (s = cpu_string; *s != 0; s++)
10560 warning (0, "the cpu name must be lower case");
10564 /* 'from-abi' selects the most compatible architecture for the given
10565 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10566 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10567 version. Look first at the -mgp options, if given, otherwise base
10568 the choice on MASK_64BIT in TARGET_DEFAULT. */
10569 if (strcasecmp (cpu_string, "from-abi") == 0)
10570 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10571 : ABI_NEEDS_64BIT_REGS ? 3
10572 : (TARGET_64BIT ? 3 : 1));
10574 /* 'default' has traditionally been a no-op. Probably not very useful. */
10575 if (strcasecmp (cpu_string, "default") == 0)
10578 for (p = mips_cpu_info_table; p->name != 0; p++)
10579 if (mips_matching_cpu_name_p (p->name, cpu_string))
10586 /* Return the processor associated with the given ISA level, or null
10587 if the ISA isn't valid. */
10589 static const struct mips_cpu_info *
10590 mips_cpu_info_from_isa (int isa)
10592 const struct mips_cpu_info *p;
10594 for (p = mips_cpu_info_table; p->name != 0; p++)
10601 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
10602 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
10603 they only hold condition code modes, and CCmode is always considered to
10604 be 4 bytes wide. All other registers are word sized. */
10607 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10609 if (ST_REG_P (regno))
10610 return ((GET_MODE_SIZE (mode) + 3) / 4);
10611 else if (! FP_REG_P (regno))
10612 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10614 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10617 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
10618 all BLKmode objects are returned in memory. Under the new (N32 and
10619 64-bit MIPS ABIs) small structures are returned in a register.
10620 Objects with varying size must still be returned in memory, of
10624 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
10627 return (TYPE_MODE (type) == BLKmode);
10629 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10630 || (int_size_in_bytes (type) == -1));
10634 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
10636 return !TARGET_OLDABI;
10639 /* Return true if INSN is a multiply-add or multiply-subtract
10640 instruction and PREV assigns to the accumulator operand. */
10643 mips_linked_madd_p (rtx prev, rtx insn)
10647 x = single_set (insn);
10653 if (GET_CODE (x) == PLUS
10654 && GET_CODE (XEXP (x, 0)) == MULT
10655 && reg_set_p (XEXP (x, 1), prev))
10658 if (GET_CODE (x) == MINUS
10659 && GET_CODE (XEXP (x, 1)) == MULT
10660 && reg_set_p (XEXP (x, 0), prev))
10666 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10667 that may clobber hi or lo. */
10669 static rtx mips_macc_chains_last_hilo;
10671 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10672 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10675 mips_macc_chains_record (rtx insn)
10677 if (get_attr_may_clobber_hilo (insn))
10678 mips_macc_chains_last_hilo = insn;
10681 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10682 has NREADY elements, looking for a multiply-add or multiply-subtract
10683 instruction that is cumulative with mips_macc_chains_last_hilo.
10684 If there is one, promote it ahead of anything else that might
10685 clobber hi or lo. */
10688 mips_macc_chains_reorder (rtx *ready, int nready)
10692 if (mips_macc_chains_last_hilo != 0)
10693 for (i = nready - 1; i >= 0; i--)
10694 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10696 for (j = nready - 1; j > i; j--)
10697 if (recog_memoized (ready[j]) >= 0
10698 && get_attr_may_clobber_hilo (ready[j]))
10700 mips_promote_ready (ready, i, j);
10707 /* The last instruction to be scheduled. */
10709 static rtx vr4130_last_insn;
10711 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10712 points to an rtx that is initially an instruction. Nullify the rtx
10713 if the instruction uses the value of register X. */
10716 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
10718 rtx *insn_ptr = data;
10721 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10725 /* Return true if there is true register dependence between vr4130_last_insn
10729 vr4130_true_reg_dependence_p (rtx insn)
10731 note_stores (PATTERN (vr4130_last_insn),
10732 vr4130_true_reg_dependence_p_1, &insn);
10736 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10737 the ready queue and that INSN2 is the instruction after it, return
10738 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10739 in which INSN1 and INSN2 can probably issue in parallel, but for
10740 which (INSN2, INSN1) should be less sensitive to instruction
10741 alignment than (INSN1, INSN2). See 4130.md for more details. */
10744 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10748 /* Check for the following case:
10750 1) there is some other instruction X with an anti dependence on INSN1;
10751 2) X has a higher priority than INSN2; and
10752 3) X is an arithmetic instruction (and thus has no unit restrictions).
10754 If INSN1 is the last instruction blocking X, it would better to
10755 choose (INSN1, X) over (INSN2, INSN1). */
10756 FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
10757 if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
10758 && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
10759 && recog_memoized (DEP_LINK_CON (dep)) >= 0
10760 && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
10763 if (vr4130_last_insn != 0
10764 && recog_memoized (insn1) >= 0
10765 && recog_memoized (insn2) >= 0)
10767 /* See whether INSN1 and INSN2 use different execution units,
10768 or if they are both ALU-type instructions. If so, they can
10769 probably execute in parallel. */
10770 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10771 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10772 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10774 /* If only one of the instructions has a dependence on
10775 vr4130_last_insn, prefer to schedule the other one first. */
10776 bool dep1 = vr4130_true_reg_dependence_p (insn1);
10777 bool dep2 = vr4130_true_reg_dependence_p (insn2);
10781 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10782 is not an ALU-type instruction and if INSN1 uses the same
10783 execution unit. (Note that if this condition holds, we already
10784 know that INSN2 uses a different execution unit.) */
10785 if (class1 != VR4130_CLASS_ALU
10786 && recog_memoized (vr4130_last_insn) >= 0
10787 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10794 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10795 queue with at least two instructions. Swap the first two if
10796 vr4130_swap_insns_p says that it could be worthwhile. */
10799 vr4130_reorder (rtx *ready, int nready)
10801 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10802 mips_promote_ready (ready, nready - 2, nready - 1);
10805 /* Remove the instruction at index LOWER from ready queue READY and
10806 reinsert it in front of the instruction at index HIGHER. LOWER must
10810 mips_promote_ready (rtx *ready, int lower, int higher)
10815 new_head = ready[lower];
10816 for (i = lower; i < higher; i++)
10817 ready[i] = ready[i + 1];
10818 ready[i] = new_head;
10821 /* Implement TARGET_SCHED_REORDER. */
10824 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10825 rtx *ready, int *nreadyp, int cycle)
10827 if (!reload_completed && TUNE_MACC_CHAINS)
10830 mips_macc_chains_last_hilo = 0;
10832 mips_macc_chains_reorder (ready, *nreadyp);
10834 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
10837 vr4130_last_insn = 0;
10839 vr4130_reorder (ready, *nreadyp);
10841 return mips_issue_rate ();
10844 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10847 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10848 rtx insn, int more)
10850 switch (GET_CODE (PATTERN (insn)))
10854 /* Don't count USEs and CLOBBERs against the issue rate. */
10859 if (!reload_completed && TUNE_MACC_CHAINS)
10860 mips_macc_chains_record (insn);
10861 vr4130_last_insn = insn;
10867 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10868 dependencies have no cost. */
10871 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10872 rtx dep ATTRIBUTE_UNUSED, int cost)
10874 if (REG_NOTE_KIND (link) != 0)
10879 /* Return the number of instructions that can be issued per cycle. */
10882 mips_issue_rate (void)
10886 case PROCESSOR_74KC:
10887 case PROCESSOR_74KF2_1:
10888 case PROCESSOR_74KF1_1:
10889 case PROCESSOR_74KF3_2:
10890 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10891 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10892 but in reality only a maximum of 3 insns can be issued as the
10893 floating point load/stores also require a slot in the AGEN pipe. */
10896 case PROCESSOR_R4130:
10897 case PROCESSOR_R5400:
10898 case PROCESSOR_R5500:
10899 case PROCESSOR_R7000:
10900 case PROCESSOR_R9000:
10903 case PROCESSOR_SB1:
10904 case PROCESSOR_SB1A:
10905 /* This is actually 4, but we get better performance if we claim 3.
10906 This is partly because of unwanted speculative code motion with the
10907 larger number, and partly because in most common cases we can't
10908 reach the theoretical max of 4. */
10916 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10917 be as wide as the scheduling freedom in the DFA. */
10920 mips_multipass_dfa_lookahead (void)
10922 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10929 /* Implements a store data bypass check. We need this because the cprestore
10930 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
10931 default routine to abort. We just return false for that case. */
10932 /* ??? Should try to give a better result here than assuming false. */
10935 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10937 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10940 return ! store_data_bypass_p (out_insn, in_insn);
10943 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10944 return the first operand of the associated "pref" or "prefx" insn. */
10947 mips_prefetch_cookie (rtx write, rtx locality)
10949 /* store_streamed / load_streamed. */
10950 if (INTVAL (locality) <= 0)
10951 return GEN_INT (INTVAL (write) + 4);
10953 /* store / load. */
10954 if (INTVAL (locality) <= 2)
10957 /* store_retained / load_retained. */
10958 return GEN_INT (INTVAL (write) + 6);
10961 /* MIPS builtin function support. */
10963 struct builtin_description
10965 /* The code of the main .md file instruction. See mips_builtin_type
10966 for more information. */
10967 enum insn_code icode;
10969 /* The floating-point comparison code to use with ICODE, if any. */
10970 enum mips_fp_condition cond;
10972 /* The name of the builtin function. */
10975 /* Specifies how the function should be expanded. */
10976 enum mips_builtin_type builtin_type;
10978 /* The function's prototype. */
10979 enum mips_function_type function_type;
10981 /* The target flags required for this function. */
10985 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10986 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10987 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10988 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10989 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10991 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10993 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10994 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10995 "__builtin_mips_" #INSN "_" #COND "_s", \
10996 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10997 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10998 "__builtin_mips_" #INSN "_" #COND "_d", \
10999 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
11001 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11002 The lower and upper forms require TARGET_FLAGS while the any and all
11003 forms require MASK_MIPS3D. */
11004 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
11005 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11006 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
11007 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
11008 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11009 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
11010 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
11011 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11012 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
11013 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
11014 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11015 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
11016 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
11018 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11019 require MASK_MIPS3D. */
11020 #define CMP_4S_BUILTINS(INSN, COND) \
11021 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11022 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
11023 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11025 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11026 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
11027 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11030 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11031 instruction requires TARGET_FLAGS. */
11032 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
11033 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11034 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
11035 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11037 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11038 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
11039 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11042 /* Define all the builtins related to c.cond.fmt condition COND. */
11043 #define CMP_BUILTINS(COND) \
11044 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11045 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
11046 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
11047 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11048 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
11049 CMP_4S_BUILTINS (c, COND), \
11050 CMP_4S_BUILTINS (cabs, COND)
11052 static const struct builtin_description mips_bdesc[] =
11054 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11055 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11056 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11057 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11058 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
11059 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11060 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11061 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11063 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
11064 MASK_PAIRED_SINGLE_FLOAT),
11065 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11066 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11067 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11068 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11070 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11071 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11072 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11073 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11074 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11075 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11077 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11078 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11079 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11080 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11081 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11082 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11084 MIPS_FP_CONDITIONS (CMP_BUILTINS)
11087 /* Builtin functions for the SB-1 processor. */
11089 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11091 static const struct builtin_description sb1_bdesc[] =
11093 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
11096 /* Builtin functions for DSP ASE. */
11098 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11099 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11100 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11101 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11102 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11104 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
11105 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
11106 builtin_description fields. */
11107 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
11108 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
11109 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
11111 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11112 branch instruction. TARGET_FLAGS is a builtin_description field. */
11113 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
11114 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
11115 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
11117 static const struct builtin_description dsp_bdesc[] =
11119 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11120 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11121 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11122 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11123 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11124 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11125 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11126 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11127 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11128 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11129 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11130 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11131 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11132 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
11133 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
11134 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
11135 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11136 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11137 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11138 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11139 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11140 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11141 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11142 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11143 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11144 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11145 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11146 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11147 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11148 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11149 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11150 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11151 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11152 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11153 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11154 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11155 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11156 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11157 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11158 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11159 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11160 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11161 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11162 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
11163 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11164 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
11165 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
11166 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11167 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11168 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11169 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11170 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11171 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11172 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11173 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11174 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11175 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11176 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11177 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11178 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
11179 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
11180 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11181 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11182 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11183 BPOSGE_BUILTIN (32, MASK_DSP),
11185 /* The following are for the MIPS DSP ASE REV 2. */
11186 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
11187 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11188 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11189 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11190 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11191 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11192 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11193 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11194 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11195 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11196 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11197 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11198 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11199 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11200 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11201 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11202 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11203 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11204 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11205 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11206 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11207 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
11208 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11209 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11210 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11211 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11212 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11213 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11214 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11215 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11216 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11217 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11218 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11219 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
11222 static const struct builtin_description dsp_32only_bdesc[] =
11224 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11225 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11226 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11227 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11228 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11229 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11230 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11231 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11232 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11233 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11234 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11235 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11236 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11237 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11238 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11239 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11240 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11241 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11242 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11243 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11244 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11246 /* The following are for the MIPS DSP ASE REV 2. */
11247 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11248 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11249 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11250 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11251 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11252 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11253 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11254 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
11255 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
11256 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11257 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11258 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11259 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11260 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11261 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
11264 /* This helps provide a mapping from builtin function codes to bdesc
11269 /* The builtin function table that this entry describes. */
11270 const struct builtin_description *bdesc;
11272 /* The number of entries in the builtin function table. */
11275 /* The target processor that supports these builtin functions.
11276 PROCESSOR_MAX means we enable them for all processors. */
11277 enum processor_type proc;
11279 /* If the target has these flags, this builtin function table
11280 will not be supported. */
11281 int unsupported_target_flags;
11284 static const struct bdesc_map bdesc_arrays[] =
11286 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
11287 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
11288 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
11289 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
11293 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
11294 suitable for input operand OP of instruction ICODE. Return the value. */
11297 mips_prepare_builtin_arg (enum insn_code icode,
11298 unsigned int op, tree exp, unsigned int argnum)
11301 enum machine_mode mode;
11303 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
11304 mode = insn_data[icode].operand[op].mode;
11305 if (!insn_data[icode].operand[op].predicate (value, mode))
11307 value = copy_to_mode_reg (mode, value);
11308 /* Check the predicate again. */
11309 if (!insn_data[icode].operand[op].predicate (value, mode))
11311 error ("invalid argument to builtin function");
11319 /* Return an rtx suitable for output operand OP of instruction ICODE.
11320 If TARGET is non-null, try to use it where possible. */
11323 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11325 enum machine_mode mode;
11327 mode = insn_data[icode].operand[op].mode;
11328 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11329 target = gen_reg_rtx (mode);
11334 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
11337 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11338 enum machine_mode mode ATTRIBUTE_UNUSED,
11339 int ignore ATTRIBUTE_UNUSED)
11341 enum insn_code icode;
11342 enum mips_builtin_type type;
11344 unsigned int fcode;
11345 const struct builtin_description *bdesc;
11346 const struct bdesc_map *m;
11348 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11349 fcode = DECL_FUNCTION_CODE (fndecl);
11352 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11354 if (fcode < m->size)
11357 icode = bdesc[fcode].icode;
11358 type = bdesc[fcode].builtin_type;
11368 case MIPS_BUILTIN_DIRECT:
11369 return mips_expand_builtin_direct (icode, target, exp, true);
11371 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11372 return mips_expand_builtin_direct (icode, target, exp, false);
11374 case MIPS_BUILTIN_MOVT:
11375 case MIPS_BUILTIN_MOVF:
11376 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
11379 case MIPS_BUILTIN_CMP_ANY:
11380 case MIPS_BUILTIN_CMP_ALL:
11381 case MIPS_BUILTIN_CMP_UPPER:
11382 case MIPS_BUILTIN_CMP_LOWER:
11383 case MIPS_BUILTIN_CMP_SINGLE:
11384 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
11387 case MIPS_BUILTIN_BPOSGE32:
11388 return mips_expand_builtin_bposge (type, target);
11395 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
11398 mips_init_builtins (void)
11400 const struct builtin_description *d;
11401 const struct bdesc_map *m;
11402 tree types[(int) MIPS_MAX_FTYPE_MAX];
11403 tree V2SF_type_node;
11404 tree V2HI_type_node;
11405 tree V4QI_type_node;
11406 unsigned int offset;
11408 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
11409 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
11412 if (TARGET_PAIRED_SINGLE_FLOAT)
11414 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
11416 types[MIPS_V2SF_FTYPE_V2SF]
11417 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
11419 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
11420 = build_function_type_list (V2SF_type_node,
11421 V2SF_type_node, V2SF_type_node, NULL_TREE);
11423 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
11424 = build_function_type_list (V2SF_type_node,
11425 V2SF_type_node, V2SF_type_node,
11426 integer_type_node, NULL_TREE);
11428 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
11429 = build_function_type_list (V2SF_type_node,
11430 V2SF_type_node, V2SF_type_node,
11431 V2SF_type_node, V2SF_type_node, NULL_TREE);
11433 types[MIPS_V2SF_FTYPE_SF_SF]
11434 = build_function_type_list (V2SF_type_node,
11435 float_type_node, float_type_node, NULL_TREE);
11437 types[MIPS_INT_FTYPE_V2SF_V2SF]
11438 = build_function_type_list (integer_type_node,
11439 V2SF_type_node, V2SF_type_node, NULL_TREE);
11441 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
11442 = build_function_type_list (integer_type_node,
11443 V2SF_type_node, V2SF_type_node,
11444 V2SF_type_node, V2SF_type_node, NULL_TREE);
11446 types[MIPS_INT_FTYPE_SF_SF]
11447 = build_function_type_list (integer_type_node,
11448 float_type_node, float_type_node, NULL_TREE);
11450 types[MIPS_INT_FTYPE_DF_DF]
11451 = build_function_type_list (integer_type_node,
11452 double_type_node, double_type_node, NULL_TREE);
11454 types[MIPS_SF_FTYPE_V2SF]
11455 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
11457 types[MIPS_SF_FTYPE_SF]
11458 = build_function_type_list (float_type_node,
11459 float_type_node, NULL_TREE);
11461 types[MIPS_SF_FTYPE_SF_SF]
11462 = build_function_type_list (float_type_node,
11463 float_type_node, float_type_node, NULL_TREE);
11465 types[MIPS_DF_FTYPE_DF]
11466 = build_function_type_list (double_type_node,
11467 double_type_node, NULL_TREE);
11469 types[MIPS_DF_FTYPE_DF_DF]
11470 = build_function_type_list (double_type_node,
11471 double_type_node, double_type_node, NULL_TREE);
11476 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
11477 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
11479 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
11480 = build_function_type_list (V2HI_type_node,
11481 V2HI_type_node, V2HI_type_node,
11484 types[MIPS_SI_FTYPE_SI_SI]
11485 = build_function_type_list (intSI_type_node,
11486 intSI_type_node, intSI_type_node,
11489 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
11490 = build_function_type_list (V4QI_type_node,
11491 V4QI_type_node, V4QI_type_node,
11494 types[MIPS_SI_FTYPE_V4QI]
11495 = build_function_type_list (intSI_type_node,
11499 types[MIPS_V2HI_FTYPE_V2HI]
11500 = build_function_type_list (V2HI_type_node,
11504 types[MIPS_SI_FTYPE_SI]
11505 = build_function_type_list (intSI_type_node,
11509 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
11510 = build_function_type_list (V4QI_type_node,
11511 V2HI_type_node, V2HI_type_node,
11514 types[MIPS_V2HI_FTYPE_SI_SI]
11515 = build_function_type_list (V2HI_type_node,
11516 intSI_type_node, intSI_type_node,
11519 types[MIPS_SI_FTYPE_V2HI]
11520 = build_function_type_list (intSI_type_node,
11524 types[MIPS_V2HI_FTYPE_V4QI]
11525 = build_function_type_list (V2HI_type_node,
11529 types[MIPS_V4QI_FTYPE_V4QI_SI]
11530 = build_function_type_list (V4QI_type_node,
11531 V4QI_type_node, intSI_type_node,
11534 types[MIPS_V2HI_FTYPE_V2HI_SI]
11535 = build_function_type_list (V2HI_type_node,
11536 V2HI_type_node, intSI_type_node,
11539 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
11540 = build_function_type_list (V2HI_type_node,
11541 V4QI_type_node, V2HI_type_node,
11544 types[MIPS_SI_FTYPE_V2HI_V2HI]
11545 = build_function_type_list (intSI_type_node,
11546 V2HI_type_node, V2HI_type_node,
11549 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
11550 = build_function_type_list (intDI_type_node,
11551 intDI_type_node, V4QI_type_node, V4QI_type_node,
11554 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
11555 = build_function_type_list (intDI_type_node,
11556 intDI_type_node, V2HI_type_node, V2HI_type_node,
11559 types[MIPS_DI_FTYPE_DI_SI_SI]
11560 = build_function_type_list (intDI_type_node,
11561 intDI_type_node, intSI_type_node, intSI_type_node,
11564 types[MIPS_V4QI_FTYPE_SI]
11565 = build_function_type_list (V4QI_type_node,
11569 types[MIPS_V2HI_FTYPE_SI]
11570 = build_function_type_list (V2HI_type_node,
11574 types[MIPS_VOID_FTYPE_V4QI_V4QI]
11575 = build_function_type_list (void_type_node,
11576 V4QI_type_node, V4QI_type_node,
11579 types[MIPS_SI_FTYPE_V4QI_V4QI]
11580 = build_function_type_list (intSI_type_node,
11581 V4QI_type_node, V4QI_type_node,
11584 types[MIPS_VOID_FTYPE_V2HI_V2HI]
11585 = build_function_type_list (void_type_node,
11586 V2HI_type_node, V2HI_type_node,
11589 types[MIPS_SI_FTYPE_DI_SI]
11590 = build_function_type_list (intSI_type_node,
11591 intDI_type_node, intSI_type_node,
11594 types[MIPS_DI_FTYPE_DI_SI]
11595 = build_function_type_list (intDI_type_node,
11596 intDI_type_node, intSI_type_node,
11599 types[MIPS_VOID_FTYPE_SI_SI]
11600 = build_function_type_list (void_type_node,
11601 intSI_type_node, intSI_type_node,
11604 types[MIPS_SI_FTYPE_PTR_SI]
11605 = build_function_type_list (intSI_type_node,
11606 ptr_type_node, intSI_type_node,
11609 types[MIPS_SI_FTYPE_VOID]
11610 = build_function_type (intSI_type_node, void_list_node);
11614 types[MIPS_V4QI_FTYPE_V4QI]
11615 = build_function_type_list (V4QI_type_node,
11619 types[MIPS_SI_FTYPE_SI_SI_SI]
11620 = build_function_type_list (intSI_type_node,
11621 intSI_type_node, intSI_type_node,
11622 intSI_type_node, NULL_TREE);
11624 types[MIPS_DI_FTYPE_DI_USI_USI]
11625 = build_function_type_list (intDI_type_node,
11627 unsigned_intSI_type_node,
11628 unsigned_intSI_type_node, NULL_TREE);
11630 types[MIPS_DI_FTYPE_SI_SI]
11631 = build_function_type_list (intDI_type_node,
11632 intSI_type_node, intSI_type_node,
11635 types[MIPS_DI_FTYPE_USI_USI]
11636 = build_function_type_list (intDI_type_node,
11637 unsigned_intSI_type_node,
11638 unsigned_intSI_type_node, NULL_TREE);
11640 types[MIPS_V2HI_FTYPE_SI_SI_SI]
11641 = build_function_type_list (V2HI_type_node,
11642 intSI_type_node, intSI_type_node,
11643 intSI_type_node, NULL_TREE);
11648 /* Iterate through all of the bdesc arrays, initializing all of the
11649 builtin functions. */
11652 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11654 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
11655 && (m->unsupported_target_flags & target_flags) == 0)
11656 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
11657 if ((d->target_flags & target_flags) == d->target_flags)
11658 add_builtin_function (d->name, types[d->function_type],
11659 d - m->bdesc + offset,
11660 BUILT_IN_MD, NULL, NULL);
11665 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
11666 .md pattern and CALL is the function expr with arguments. TARGET,
11667 if nonnull, suggests a good place to put the result.
11668 HAS_TARGET indicates the function must return something. */
11671 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11674 rtx ops[MAX_RECOG_OPERANDS];
11680 /* We save target to ops[0]. */
11681 ops[0] = mips_prepare_builtin_target (icode, 0, target);
11685 /* We need to test if the arglist is not zero. Some instructions have extra
11686 clobber registers. */
11687 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
11688 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11693 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11697 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11701 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11705 gcc_unreachable ();
11710 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
11711 function (TYPE says which). EXP is the tree for the function
11712 function, ICODE is the instruction that should be used to compare
11713 the first two arguments, and COND is the condition it should test.
11714 TARGET, if nonnull, suggests a good place to put the result. */
11717 mips_expand_builtin_movtf (enum mips_builtin_type type,
11718 enum insn_code icode, enum mips_fp_condition cond,
11719 rtx target, tree exp)
11721 rtx cmp_result, op0, op1;
11723 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11724 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11725 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11726 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11728 icode = CODE_FOR_mips_cond_move_tf_ps;
11729 target = mips_prepare_builtin_target (icode, 0, target);
11730 if (type == MIPS_BUILTIN_MOVT)
11732 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11733 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11737 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11738 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11740 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11744 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11745 into TARGET otherwise. Return TARGET. */
11748 mips_builtin_branch_and_move (rtx condition, rtx target,
11749 rtx value_if_true, rtx value_if_false)
11751 rtx true_label, done_label;
11753 true_label = gen_label_rtx ();
11754 done_label = gen_label_rtx ();
11756 /* First assume that CONDITION is false. */
11757 emit_move_insn (target, value_if_false);
11759 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11760 emit_jump_insn (gen_condjump (condition, true_label));
11761 emit_jump_insn (gen_jump (done_label));
11764 /* Fix TARGET if CONDITION is true. */
11765 emit_label (true_label);
11766 emit_move_insn (target, value_if_true);
11768 emit_label (done_label);
11772 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
11773 of the comparison instruction and COND is the condition it should test.
11774 EXP is the function call and arguments and TARGET, if nonnull,
11775 suggests a good place to put the boolean result. */
11778 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11779 enum insn_code icode, enum mips_fp_condition cond,
11780 rtx target, tree exp)
11782 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
11786 if (target == 0 || GET_MODE (target) != SImode)
11787 target = gen_reg_rtx (SImode);
11789 /* Prepare the operands to the comparison. */
11790 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11791 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
11792 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11794 switch (insn_data[icode].n_operands)
11797 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
11801 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
11802 ops[3], ops[4], GEN_INT (cond)));
11806 gcc_unreachable ();
11809 /* If the comparison sets more than one register, we define the result
11810 to be 0 if all registers are false and -1 if all registers are true.
11811 The value of the complete result is indeterminate otherwise. */
11812 switch (builtin_type)
11814 case MIPS_BUILTIN_CMP_ALL:
11815 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11816 return mips_builtin_branch_and_move (condition, target,
11817 const0_rtx, const1_rtx);
11819 case MIPS_BUILTIN_CMP_UPPER:
11820 case MIPS_BUILTIN_CMP_LOWER:
11821 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11822 condition = gen_single_cc (cmp_result, offset);
11823 return mips_builtin_branch_and_move (condition, target,
11824 const1_rtx, const0_rtx);
11827 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11828 return mips_builtin_branch_and_move (condition, target,
11829 const1_rtx, const0_rtx);
11833 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
11834 suggests a good place to put the boolean result. */
11837 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11839 rtx condition, cmp_result;
11842 if (target == 0 || GET_MODE (target) != SImode)
11843 target = gen_reg_rtx (SImode);
11845 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11847 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11852 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11853 return mips_builtin_branch_and_move (condition, target,
11854 const1_rtx, const0_rtx);
11857 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
11858 FIRST is true if this is the first time handling this decl. */
11861 mips_encode_section_info (tree decl, rtx rtl, int first)
11863 default_encode_section_info (decl, rtl, first);
11865 if (TREE_CODE (decl) == FUNCTION_DECL)
11867 rtx symbol = XEXP (rtl, 0);
11869 if ((TARGET_LONG_CALLS && !mips_near_type_p (TREE_TYPE (decl)))
11870 || mips_far_type_p (TREE_TYPE (decl)))
11871 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
11875 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
11876 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
11879 mips_extra_live_on_entry (bitmap regs)
11881 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
11882 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
11885 /* SImode values are represented as sign-extended to DImode. */
11888 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11890 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11891 return SIGN_EXTEND;
11896 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
11899 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
11904 fputs ("\t.dtprelword\t", file);
11908 fputs ("\t.dtpreldword\t", file);
11912 gcc_unreachable ();
11914 output_addr_const (file, x);
11915 fputs ("+0x8000", file);
11918 #include "gt-mips.h"