1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Enumerates the setting of the -mr10k-cache-barrier option. */
186 enum mips_r10k_cache_barrier_setting {
187 R10K_CACHE_BARRIER_NONE,
188 R10K_CACHE_BARRIER_STORE,
189 R10K_CACHE_BARRIER_LOAD_STORE
192 /* Macros to create an enumeration identifier for a function prototype. */
193 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
194 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
195 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
196 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
198 /* Classifies the prototype of a built-in function. */
199 enum mips_function_type {
200 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
201 #include "config/mips/mips-ftypes.def"
202 #undef DEF_MIPS_FTYPE
206 /* Specifies how a built-in function should be converted into rtl. */
207 enum mips_builtin_type {
208 /* The function corresponds directly to an .md pattern. The return
209 value is mapped to operand 0 and the arguments are mapped to
210 operands 1 and above. */
213 /* The function corresponds directly to an .md pattern. There is no return
214 value and the arguments are mapped to operands 0 and above. */
215 MIPS_BUILTIN_DIRECT_NO_TARGET,
217 /* The function corresponds to a comparison instruction followed by
218 a mips_cond_move_tf_ps pattern. The first two arguments are the
219 values to compare and the second two arguments are the vector
220 operands for the movt.ps or movf.ps instruction (in assembly order). */
224 /* The function corresponds to a V2SF comparison instruction. Operand 0
225 of this instruction is the result of the comparison, which has mode
226 CCV2 or CCV4. The function arguments are mapped to operands 1 and
227 above. The function's return value is an SImode boolean that is
228 true under the following conditions:
230 MIPS_BUILTIN_CMP_ANY: one of the registers is true
231 MIPS_BUILTIN_CMP_ALL: all of the registers are true
232 MIPS_BUILTIN_CMP_LOWER: the first register is true
233 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
234 MIPS_BUILTIN_CMP_ANY,
235 MIPS_BUILTIN_CMP_ALL,
236 MIPS_BUILTIN_CMP_UPPER,
237 MIPS_BUILTIN_CMP_LOWER,
239 /* As above, but the instruction only sets a single $fcc register. */
240 MIPS_BUILTIN_CMP_SINGLE,
242 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
243 MIPS_BUILTIN_BPOSGE32
246 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
247 #define MIPS_FP_CONDITIONS(MACRO) \
265 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
266 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
267 enum mips_fp_condition {
268 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
271 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
272 #define STRINGIFY(X) #X
273 static const char *const mips_fp_conditions[] = {
274 MIPS_FP_CONDITIONS (STRINGIFY)
277 /* Information about a function's frame layout. */
278 struct GTY(()) mips_frame_info {
279 /* The size of the frame in bytes. */
280 HOST_WIDE_INT total_size;
282 /* The number of bytes allocated to variables. */
283 HOST_WIDE_INT var_size;
285 /* The number of bytes allocated to outgoing function arguments. */
286 HOST_WIDE_INT args_size;
288 /* The number of bytes allocated to the .cprestore slot, or 0 if there
290 HOST_WIDE_INT cprestore_size;
292 /* Bit X is set if the function saves or restores GPR X. */
295 /* Likewise FPR X. */
298 /* Likewise doubleword accumulator X ($acX). */
299 unsigned int acc_mask;
301 /* The number of GPRs, FPRs, doubleword accumulators and COP0
305 unsigned int num_acc;
306 unsigned int num_cop0_regs;
308 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
309 save slots from the top of the frame, or zero if no such slots are
311 HOST_WIDE_INT gp_save_offset;
312 HOST_WIDE_INT fp_save_offset;
313 HOST_WIDE_INT acc_save_offset;
314 HOST_WIDE_INT cop0_save_offset;
316 /* Likewise, but giving offsets from the bottom of the frame. */
317 HOST_WIDE_INT gp_sp_offset;
318 HOST_WIDE_INT fp_sp_offset;
319 HOST_WIDE_INT acc_sp_offset;
320 HOST_WIDE_INT cop0_sp_offset;
322 /* The offset of arg_pointer_rtx from the bottom of the frame. */
323 HOST_WIDE_INT arg_pointer_offset;
325 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
326 HOST_WIDE_INT hard_frame_pointer_offset;
329 struct GTY(()) machine_function {
330 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
331 rtx mips16_gp_pseudo_rtx;
333 /* The number of extra stack bytes taken up by register varargs.
334 This area is allocated by the callee at the very top of the frame. */
337 /* The current frame information, calculated by mips_compute_frame_info. */
338 struct mips_frame_info frame;
340 /* The register to use as the function's global pointer, or INVALID_REGNUM
341 if the function doesn't need one. */
342 unsigned int global_pointer;
344 /* How many instructions it takes to load a label into $AT, or 0 if
345 this property hasn't yet been calculated. */
346 unsigned int load_label_length;
348 /* True if mips_adjust_insn_length should ignore an instruction's
350 bool ignore_hazard_length_p;
352 /* True if the whole function is suitable for .set noreorder and
354 bool all_noreorder_p;
356 /* True if the function has "inflexible" and "flexible" references
357 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
358 and mips_cfun_has_flexible_gp_ref_p for details. */
359 bool has_inflexible_gp_insn_p;
360 bool has_flexible_gp_insn_p;
362 /* True if the function's prologue must load the global pointer
363 value into pic_offset_table_rtx and store the same value in
364 the function's cprestore slot (if any). Even if this value
365 is currently false, we may decide to set it to true later;
366 see mips_must_initialize_gp_p () for details. */
367 bool must_initialize_gp_p;
369 /* True if the current function must restore $gp after any potential
370 clobber. This value is only meaningful during the first post-epilogue
371 split_insns pass; see mips_must_initialize_gp_p () for details. */
372 bool must_restore_gp_when_clobbered_p;
374 /* True if we have emitted an instruction to initialize
375 mips16_gp_pseudo_rtx. */
376 bool initialized_mips16_gp_pseudo_p;
378 /* True if this is an interrupt handler. */
379 bool interrupt_handler_p;
381 /* True if this is an interrupt handler that uses shadow registers. */
382 bool use_shadow_register_set_p;
384 /* True if this is an interrupt handler that should keep interrupts
386 bool keep_interrupts_masked_p;
388 /* True if this is an interrupt handler that should use DERET
390 bool use_debug_exception_return_p;
393 /* Information about a single argument. */
394 struct mips_arg_info {
395 /* True if the argument is passed in a floating-point register, or
396 would have been if we hadn't run out of registers. */
399 /* The number of words passed in registers, rounded up. */
400 unsigned int reg_words;
402 /* For EABI, the offset of the first register from GP_ARG_FIRST or
403 FP_ARG_FIRST. For other ABIs, the offset of the first register from
404 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
405 comment for details).
407 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
409 unsigned int reg_offset;
411 /* The number of words that must be passed on the stack, rounded up. */
412 unsigned int stack_words;
414 /* The offset from the start of the stack overflow area of the argument's
415 first stack word. Only meaningful when STACK_WORDS is nonzero. */
416 unsigned int stack_offset;
419 /* Information about an address described by mips_address_type.
425 REG is the base register and OFFSET is the constant offset.
428 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
429 is the type of symbol it references.
432 SYMBOL_TYPE is the type of symbol that the address references. */
433 struct mips_address_info {
434 enum mips_address_type type;
437 enum mips_symbol_type symbol_type;
440 /* One stage in a constant building sequence. These sequences have
444 A = A CODE[1] VALUE[1]
445 A = A CODE[2] VALUE[2]
448 where A is an accumulator, each CODE[i] is a binary rtl operation
449 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
450 struct mips_integer_op {
452 unsigned HOST_WIDE_INT value;
455 /* The largest number of operations needed to load an integer constant.
456 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
457 When the lowest bit is clear, we can try, but reject a sequence with
458 an extra SLL at the end. */
459 #define MIPS_MAX_INTEGER_OPS 7
461 /* Information about a MIPS16e SAVE or RESTORE instruction. */
462 struct mips16e_save_restore_info {
463 /* The number of argument registers saved by a SAVE instruction.
464 0 for RESTORE instructions. */
467 /* Bit X is set if the instruction saves or restores GPR X. */
470 /* The total number of bytes to allocate. */
474 /* Global variables for machine-dependent things. */
476 /* The -G setting, or the configuration's default small-data limit if
477 no -G option is given. */
478 static unsigned int mips_small_data_threshold;
480 /* The number of file directives written by mips_output_filename. */
481 int num_source_filenames;
483 /* The name that appeared in the last .file directive written by
484 mips_output_filename, or "" if mips_output_filename hasn't
485 written anything yet. */
486 const char *current_function_file = "";
488 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
491 /* Arrays that map GCC register numbers to debugger register numbers. */
492 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
493 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
495 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
496 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
497 struct mips_asm_switch mips_nomacro = { "macro", 0 };
498 struct mips_asm_switch mips_noat = { "at", 0 };
500 /* True if we're writing out a branch-likely instruction rather than a
502 static bool mips_branch_likely;
504 /* The current instruction-set architecture. */
505 enum processor_type mips_arch;
506 const struct mips_cpu_info *mips_arch_info;
508 /* The processor that we should tune the code for. */
509 enum processor_type mips_tune;
510 const struct mips_cpu_info *mips_tune_info;
512 /* The ISA level associated with mips_arch. */
515 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
516 static const struct mips_cpu_info *mips_isa_option_info;
518 /* Which ABI to use. */
519 int mips_abi = MIPS_ABI_DEFAULT;
521 /* Which cost information to use. */
522 const struct mips_rtx_cost_data *mips_cost;
524 /* The ambient target flags, excluding MASK_MIPS16. */
525 static int mips_base_target_flags;
527 /* True if MIPS16 is the default mode. */
528 bool mips_base_mips16;
530 /* The ambient values of other global variables. */
531 static int mips_base_schedule_insns; /* flag_schedule_insns */
532 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
533 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
534 static int mips_base_align_loops; /* align_loops */
535 static int mips_base_align_jumps; /* align_jumps */
536 static int mips_base_align_functions; /* align_functions */
538 /* The -mcode-readable setting. */
539 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
541 /* The -mr10k-cache-barrier setting. */
542 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
544 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
545 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
547 /* Index C is true if character C is a valid PRINT_OPERAND punctation
549 bool mips_print_operand_punct[256];
551 static GTY (()) int mips_output_filename_first_time = 1;
553 /* mips_split_p[X] is true if symbols of type X can be split by
554 mips_split_symbol. */
555 bool mips_split_p[NUM_SYMBOL_TYPES];
557 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
558 can be split by mips_split_symbol. */
559 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
561 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
562 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
563 if they are matched by a special .md file pattern. */
564 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
566 /* Likewise for HIGHs. */
567 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
569 /* Index R is the smallest register class that contains register R. */
570 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
571 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
572 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
573 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
574 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
575 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
576 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
577 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
578 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
579 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
580 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
581 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
582 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
583 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
584 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
585 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
586 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
587 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
588 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
589 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
590 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
591 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
592 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
593 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
594 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
595 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
596 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
597 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
598 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
599 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
600 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
601 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
602 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
603 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
604 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
605 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
606 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
607 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
608 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
609 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
610 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
611 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
612 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
613 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
614 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
615 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
616 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
617 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
620 /* The value of TARGET_ATTRIBUTE_TABLE. */
621 static const struct attribute_spec mips_attribute_table[] = {
622 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
623 { "long_call", 0, 0, false, true, true, NULL },
624 { "far", 0, 0, false, true, true, NULL },
625 { "near", 0, 0, false, true, true, NULL },
626 /* We would really like to treat "mips16" and "nomips16" as type
627 attributes, but GCC doesn't provide the hooks we need to support
628 the right conversion rules. As declaration attributes, they affect
629 code generation but don't carry other semantics. */
630 { "mips16", 0, 0, true, false, false, NULL },
631 { "nomips16", 0, 0, true, false, false, NULL },
632 /* Allow functions to be specified as interrupt handlers */
633 { "interrupt", 0, 0, false, true, true, NULL },
634 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
635 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
636 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
637 { NULL, 0, 0, false, false, false, NULL }
640 /* A table describing all the processors GCC knows about. Names are
641 matched in the order listed. The first mention of an ISA level is
642 taken as the canonical name for that ISA.
644 To ease comparison, please keep this table in the same order
645 as GAS's mips_cpu_info_table. Please also make sure that
646 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
647 options correctly. */
648 static const struct mips_cpu_info mips_cpu_info_table[] = {
649 /* Entries for generic ISAs. */
650 { "mips1", PROCESSOR_R3000, 1, 0 },
651 { "mips2", PROCESSOR_R6000, 2, 0 },
652 { "mips3", PROCESSOR_R4000, 3, 0 },
653 { "mips4", PROCESSOR_R8000, 4, 0 },
654 /* Prefer not to use branch-likely instructions for generic MIPS32rX
655 and MIPS64rX code. The instructions were officially deprecated
656 in revisions 2 and earlier, but revision 3 is likely to downgrade
657 that to a recommendation to avoid the instructions in code that
658 isn't tuned to a specific processor. */
659 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
660 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
661 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
662 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
663 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
665 /* MIPS I processors. */
666 { "r3000", PROCESSOR_R3000, 1, 0 },
667 { "r2000", PROCESSOR_R3000, 1, 0 },
668 { "r3900", PROCESSOR_R3900, 1, 0 },
670 /* MIPS II processors. */
671 { "r6000", PROCESSOR_R6000, 2, 0 },
673 /* MIPS III processors. */
674 { "r4000", PROCESSOR_R4000, 3, 0 },
675 { "vr4100", PROCESSOR_R4100, 3, 0 },
676 { "vr4111", PROCESSOR_R4111, 3, 0 },
677 { "vr4120", PROCESSOR_R4120, 3, 0 },
678 { "vr4130", PROCESSOR_R4130, 3, 0 },
679 { "vr4300", PROCESSOR_R4300, 3, 0 },
680 { "r4400", PROCESSOR_R4000, 3, 0 },
681 { "r4600", PROCESSOR_R4600, 3, 0 },
682 { "orion", PROCESSOR_R4600, 3, 0 },
683 { "r4650", PROCESSOR_R4650, 3, 0 },
684 /* ST Loongson 2E/2F processors. */
685 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
686 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
688 /* MIPS IV processors. */
689 { "r8000", PROCESSOR_R8000, 4, 0 },
690 { "r10000", PROCESSOR_R10000, 4, 0 },
691 { "r12000", PROCESSOR_R10000, 4, 0 },
692 { "r14000", PROCESSOR_R10000, 4, 0 },
693 { "r16000", PROCESSOR_R10000, 4, 0 },
694 { "vr5000", PROCESSOR_R5000, 4, 0 },
695 { "vr5400", PROCESSOR_R5400, 4, 0 },
696 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
697 { "rm7000", PROCESSOR_R7000, 4, 0 },
698 { "rm9000", PROCESSOR_R9000, 4, 0 },
700 /* MIPS32 processors. */
701 { "4kc", PROCESSOR_4KC, 32, 0 },
702 { "4km", PROCESSOR_4KC, 32, 0 },
703 { "4kp", PROCESSOR_4KP, 32, 0 },
704 { "4ksc", PROCESSOR_4KC, 32, 0 },
706 /* MIPS32 Release 2 processors. */
707 { "m4k", PROCESSOR_M4K, 33, 0 },
708 { "4kec", PROCESSOR_4KC, 33, 0 },
709 { "4kem", PROCESSOR_4KC, 33, 0 },
710 { "4kep", PROCESSOR_4KP, 33, 0 },
711 { "4ksd", PROCESSOR_4KC, 33, 0 },
713 { "24kc", PROCESSOR_24KC, 33, 0 },
714 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
715 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
716 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
717 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
718 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
720 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
721 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
722 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
723 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
724 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
725 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
727 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
728 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
729 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
730 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
731 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
732 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
734 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
735 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
736 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
737 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
738 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
739 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
740 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
742 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
743 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
744 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
745 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
747 /* MIPS64 processors. */
748 { "5kc", PROCESSOR_5KC, 64, 0 },
749 { "5kf", PROCESSOR_5KF, 64, 0 },
750 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
751 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
752 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
753 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
754 { "xlr", PROCESSOR_XLR, 64, 0 },
756 /* MIPS64 Release 2 processors. */
757 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
760 /* Default costs. If these are used for a processor we should look
761 up the actual costs. */
762 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
763 COSTS_N_INSNS (7), /* fp_mult_sf */ \
764 COSTS_N_INSNS (8), /* fp_mult_df */ \
765 COSTS_N_INSNS (23), /* fp_div_sf */ \
766 COSTS_N_INSNS (36), /* fp_div_df */ \
767 COSTS_N_INSNS (10), /* int_mult_si */ \
768 COSTS_N_INSNS (10), /* int_mult_di */ \
769 COSTS_N_INSNS (69), /* int_div_si */ \
770 COSTS_N_INSNS (69), /* int_div_di */ \
771 2, /* branch_cost */ \
772 4 /* memory_latency */
774 /* Floating-point costs for processors without an FPU. Just assume that
775 all floating-point libcalls are very expensive. */
776 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
777 COSTS_N_INSNS (256), /* fp_mult_sf */ \
778 COSTS_N_INSNS (256), /* fp_mult_df */ \
779 COSTS_N_INSNS (256), /* fp_div_sf */ \
780 COSTS_N_INSNS (256) /* fp_div_df */
782 /* Costs to use when optimizing for size. */
783 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
784 COSTS_N_INSNS (1), /* fp_add */
785 COSTS_N_INSNS (1), /* fp_mult_sf */
786 COSTS_N_INSNS (1), /* fp_mult_df */
787 COSTS_N_INSNS (1), /* fp_div_sf */
788 COSTS_N_INSNS (1), /* fp_div_df */
789 COSTS_N_INSNS (1), /* int_mult_si */
790 COSTS_N_INSNS (1), /* int_mult_di */
791 COSTS_N_INSNS (1), /* int_div_si */
792 COSTS_N_INSNS (1), /* int_div_di */
794 4 /* memory_latency */
797 /* Costs to use when optimizing for speed, indexed by processor. */
798 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
800 COSTS_N_INSNS (2), /* fp_add */
801 COSTS_N_INSNS (4), /* fp_mult_sf */
802 COSTS_N_INSNS (5), /* fp_mult_df */
803 COSTS_N_INSNS (12), /* fp_div_sf */
804 COSTS_N_INSNS (19), /* fp_div_df */
805 COSTS_N_INSNS (12), /* int_mult_si */
806 COSTS_N_INSNS (12), /* int_mult_di */
807 COSTS_N_INSNS (35), /* int_div_si */
808 COSTS_N_INSNS (35), /* int_div_di */
810 4 /* memory_latency */
814 COSTS_N_INSNS (6), /* int_mult_si */
815 COSTS_N_INSNS (6), /* int_mult_di */
816 COSTS_N_INSNS (36), /* int_div_si */
817 COSTS_N_INSNS (36), /* int_div_di */
819 4 /* memory_latency */
823 COSTS_N_INSNS (36), /* int_mult_si */
824 COSTS_N_INSNS (36), /* int_mult_di */
825 COSTS_N_INSNS (37), /* int_div_si */
826 COSTS_N_INSNS (37), /* int_div_di */
828 4 /* memory_latency */
832 COSTS_N_INSNS (4), /* int_mult_si */
833 COSTS_N_INSNS (11), /* int_mult_di */
834 COSTS_N_INSNS (36), /* int_div_si */
835 COSTS_N_INSNS (68), /* int_div_di */
837 4 /* memory_latency */
840 COSTS_N_INSNS (4), /* fp_add */
841 COSTS_N_INSNS (4), /* fp_mult_sf */
842 COSTS_N_INSNS (5), /* fp_mult_df */
843 COSTS_N_INSNS (17), /* fp_div_sf */
844 COSTS_N_INSNS (32), /* fp_div_df */
845 COSTS_N_INSNS (4), /* int_mult_si */
846 COSTS_N_INSNS (11), /* int_mult_di */
847 COSTS_N_INSNS (36), /* int_div_si */
848 COSTS_N_INSNS (68), /* int_div_di */
850 4 /* memory_latency */
853 COSTS_N_INSNS (4), /* fp_add */
854 COSTS_N_INSNS (4), /* fp_mult_sf */
855 COSTS_N_INSNS (5), /* fp_mult_df */
856 COSTS_N_INSNS (17), /* fp_div_sf */
857 COSTS_N_INSNS (32), /* fp_div_df */
858 COSTS_N_INSNS (4), /* int_mult_si */
859 COSTS_N_INSNS (7), /* int_mult_di */
860 COSTS_N_INSNS (42), /* int_div_si */
861 COSTS_N_INSNS (72), /* int_div_di */
863 4 /* memory_latency */
867 COSTS_N_INSNS (5), /* int_mult_si */
868 COSTS_N_INSNS (5), /* int_mult_di */
869 COSTS_N_INSNS (41), /* int_div_si */
870 COSTS_N_INSNS (41), /* int_div_di */
872 4 /* memory_latency */
875 COSTS_N_INSNS (8), /* fp_add */
876 COSTS_N_INSNS (8), /* fp_mult_sf */
877 COSTS_N_INSNS (10), /* fp_mult_df */
878 COSTS_N_INSNS (34), /* fp_div_sf */
879 COSTS_N_INSNS (64), /* fp_div_df */
880 COSTS_N_INSNS (5), /* int_mult_si */
881 COSTS_N_INSNS (5), /* int_mult_di */
882 COSTS_N_INSNS (41), /* int_div_si */
883 COSTS_N_INSNS (41), /* int_div_di */
885 4 /* memory_latency */
888 COSTS_N_INSNS (4), /* fp_add */
889 COSTS_N_INSNS (4), /* fp_mult_sf */
890 COSTS_N_INSNS (5), /* fp_mult_df */
891 COSTS_N_INSNS (17), /* fp_div_sf */
892 COSTS_N_INSNS (32), /* fp_div_df */
893 COSTS_N_INSNS (5), /* int_mult_si */
894 COSTS_N_INSNS (5), /* int_mult_di */
895 COSTS_N_INSNS (41), /* int_div_si */
896 COSTS_N_INSNS (41), /* int_div_di */
898 4 /* memory_latency */
902 COSTS_N_INSNS (5), /* int_mult_si */
903 COSTS_N_INSNS (5), /* int_mult_di */
904 COSTS_N_INSNS (41), /* int_div_si */
905 COSTS_N_INSNS (41), /* int_div_di */
907 4 /* memory_latency */
910 COSTS_N_INSNS (8), /* fp_add */
911 COSTS_N_INSNS (8), /* fp_mult_sf */
912 COSTS_N_INSNS (10), /* fp_mult_df */
913 COSTS_N_INSNS (34), /* fp_div_sf */
914 COSTS_N_INSNS (64), /* fp_div_df */
915 COSTS_N_INSNS (5), /* int_mult_si */
916 COSTS_N_INSNS (5), /* int_mult_di */
917 COSTS_N_INSNS (41), /* int_div_si */
918 COSTS_N_INSNS (41), /* int_div_di */
920 4 /* memory_latency */
923 COSTS_N_INSNS (4), /* fp_add */
924 COSTS_N_INSNS (4), /* fp_mult_sf */
925 COSTS_N_INSNS (5), /* fp_mult_df */
926 COSTS_N_INSNS (17), /* fp_div_sf */
927 COSTS_N_INSNS (32), /* fp_div_df */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (41), /* int_div_si */
931 COSTS_N_INSNS (41), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (6), /* fp_add */
937 COSTS_N_INSNS (6), /* fp_mult_sf */
938 COSTS_N_INSNS (7), /* fp_mult_df */
939 COSTS_N_INSNS (25), /* fp_div_sf */
940 COSTS_N_INSNS (48), /* fp_div_df */
941 COSTS_N_INSNS (5), /* int_mult_si */
942 COSTS_N_INSNS (5), /* int_mult_di */
943 COSTS_N_INSNS (41), /* int_div_si */
944 COSTS_N_INSNS (41), /* int_div_di */
946 4 /* memory_latency */
960 COSTS_N_INSNS (5), /* int_mult_si */
961 COSTS_N_INSNS (5), /* int_mult_di */
962 COSTS_N_INSNS (72), /* int_div_si */
963 COSTS_N_INSNS (72), /* int_div_di */
965 4 /* memory_latency */
968 COSTS_N_INSNS (2), /* fp_add */
969 COSTS_N_INSNS (4), /* fp_mult_sf */
970 COSTS_N_INSNS (5), /* fp_mult_df */
971 COSTS_N_INSNS (12), /* fp_div_sf */
972 COSTS_N_INSNS (19), /* fp_div_df */
973 COSTS_N_INSNS (2), /* int_mult_si */
974 COSTS_N_INSNS (2), /* int_mult_di */
975 COSTS_N_INSNS (35), /* int_div_si */
976 COSTS_N_INSNS (35), /* int_div_di */
978 4 /* memory_latency */
981 COSTS_N_INSNS (3), /* fp_add */
982 COSTS_N_INSNS (5), /* fp_mult_sf */
983 COSTS_N_INSNS (6), /* fp_mult_df */
984 COSTS_N_INSNS (15), /* fp_div_sf */
985 COSTS_N_INSNS (16), /* fp_div_df */
986 COSTS_N_INSNS (17), /* int_mult_si */
987 COSTS_N_INSNS (17), /* int_mult_di */
988 COSTS_N_INSNS (38), /* int_div_si */
989 COSTS_N_INSNS (38), /* int_div_di */
991 6 /* memory_latency */
994 COSTS_N_INSNS (6), /* fp_add */
995 COSTS_N_INSNS (7), /* fp_mult_sf */
996 COSTS_N_INSNS (8), /* fp_mult_df */
997 COSTS_N_INSNS (23), /* fp_div_sf */
998 COSTS_N_INSNS (36), /* fp_div_df */
999 COSTS_N_INSNS (10), /* int_mult_si */
1000 COSTS_N_INSNS (10), /* int_mult_di */
1001 COSTS_N_INSNS (69), /* int_div_si */
1002 COSTS_N_INSNS (69), /* int_div_di */
1003 2, /* branch_cost */
1004 6 /* memory_latency */
1016 /* The only costs that appear to be updated here are
1017 integer multiplication. */
1019 COSTS_N_INSNS (4), /* int_mult_si */
1020 COSTS_N_INSNS (6), /* int_mult_di */
1021 COSTS_N_INSNS (69), /* int_div_si */
1022 COSTS_N_INSNS (69), /* int_div_di */
1023 1, /* branch_cost */
1024 4 /* memory_latency */
1036 COSTS_N_INSNS (6), /* fp_add */
1037 COSTS_N_INSNS (4), /* fp_mult_sf */
1038 COSTS_N_INSNS (5), /* fp_mult_df */
1039 COSTS_N_INSNS (23), /* fp_div_sf */
1040 COSTS_N_INSNS (36), /* fp_div_df */
1041 COSTS_N_INSNS (5), /* int_mult_si */
1042 COSTS_N_INSNS (5), /* int_mult_di */
1043 COSTS_N_INSNS (36), /* int_div_si */
1044 COSTS_N_INSNS (36), /* int_div_di */
1045 1, /* branch_cost */
1046 4 /* memory_latency */
1049 COSTS_N_INSNS (6), /* fp_add */
1050 COSTS_N_INSNS (5), /* fp_mult_sf */
1051 COSTS_N_INSNS (6), /* fp_mult_df */
1052 COSTS_N_INSNS (30), /* fp_div_sf */
1053 COSTS_N_INSNS (59), /* fp_div_df */
1054 COSTS_N_INSNS (3), /* int_mult_si */
1055 COSTS_N_INSNS (4), /* int_mult_di */
1056 COSTS_N_INSNS (42), /* int_div_si */
1057 COSTS_N_INSNS (74), /* int_div_di */
1058 1, /* branch_cost */
1059 4 /* memory_latency */
1062 COSTS_N_INSNS (6), /* fp_add */
1063 COSTS_N_INSNS (5), /* fp_mult_sf */
1064 COSTS_N_INSNS (6), /* fp_mult_df */
1065 COSTS_N_INSNS (30), /* fp_div_sf */
1066 COSTS_N_INSNS (59), /* fp_div_df */
1067 COSTS_N_INSNS (5), /* int_mult_si */
1068 COSTS_N_INSNS (9), /* int_mult_di */
1069 COSTS_N_INSNS (42), /* int_div_si */
1070 COSTS_N_INSNS (74), /* int_div_di */
1071 1, /* branch_cost */
1072 4 /* memory_latency */
1075 /* The only costs that are changed here are
1076 integer multiplication. */
1077 COSTS_N_INSNS (6), /* fp_add */
1078 COSTS_N_INSNS (7), /* fp_mult_sf */
1079 COSTS_N_INSNS (8), /* fp_mult_df */
1080 COSTS_N_INSNS (23), /* fp_div_sf */
1081 COSTS_N_INSNS (36), /* fp_div_df */
1082 COSTS_N_INSNS (5), /* int_mult_si */
1083 COSTS_N_INSNS (9), /* int_mult_di */
1084 COSTS_N_INSNS (69), /* int_div_si */
1085 COSTS_N_INSNS (69), /* int_div_di */
1086 1, /* branch_cost */
1087 4 /* memory_latency */
1093 /* The only costs that are changed here are
1094 integer multiplication. */
1095 COSTS_N_INSNS (6), /* fp_add */
1096 COSTS_N_INSNS (7), /* fp_mult_sf */
1097 COSTS_N_INSNS (8), /* fp_mult_df */
1098 COSTS_N_INSNS (23), /* fp_div_sf */
1099 COSTS_N_INSNS (36), /* fp_div_df */
1100 COSTS_N_INSNS (3), /* int_mult_si */
1101 COSTS_N_INSNS (8), /* int_mult_di */
1102 COSTS_N_INSNS (69), /* int_div_si */
1103 COSTS_N_INSNS (69), /* int_div_di */
1104 1, /* branch_cost */
1105 4 /* memory_latency */
1108 COSTS_N_INSNS (2), /* fp_add */
1109 COSTS_N_INSNS (2), /* fp_mult_sf */
1110 COSTS_N_INSNS (2), /* fp_mult_df */
1111 COSTS_N_INSNS (12), /* fp_div_sf */
1112 COSTS_N_INSNS (19), /* fp_div_df */
1113 COSTS_N_INSNS (5), /* int_mult_si */
1114 COSTS_N_INSNS (9), /* int_mult_di */
1115 COSTS_N_INSNS (34), /* int_div_si */
1116 COSTS_N_INSNS (66), /* int_div_di */
1117 1, /* branch_cost */
1118 4 /* memory_latency */
1121 /* These costs are the same as the SB-1A below. */
1122 COSTS_N_INSNS (4), /* fp_add */
1123 COSTS_N_INSNS (4), /* fp_mult_sf */
1124 COSTS_N_INSNS (4), /* fp_mult_df */
1125 COSTS_N_INSNS (24), /* fp_div_sf */
1126 COSTS_N_INSNS (32), /* fp_div_df */
1127 COSTS_N_INSNS (3), /* int_mult_si */
1128 COSTS_N_INSNS (4), /* int_mult_di */
1129 COSTS_N_INSNS (36), /* int_div_si */
1130 COSTS_N_INSNS (68), /* int_div_di */
1131 1, /* branch_cost */
1132 4 /* memory_latency */
1135 /* These costs are the same as the SB-1 above. */
1136 COSTS_N_INSNS (4), /* fp_add */
1137 COSTS_N_INSNS (4), /* fp_mult_sf */
1138 COSTS_N_INSNS (4), /* fp_mult_df */
1139 COSTS_N_INSNS (24), /* fp_div_sf */
1140 COSTS_N_INSNS (32), /* fp_div_df */
1141 COSTS_N_INSNS (3), /* int_mult_si */
1142 COSTS_N_INSNS (4), /* int_mult_di */
1143 COSTS_N_INSNS (36), /* int_div_si */
1144 COSTS_N_INSNS (68), /* int_div_di */
1145 1, /* branch_cost */
1146 4 /* memory_latency */
1153 COSTS_N_INSNS (8), /* int_mult_si */
1154 COSTS_N_INSNS (8), /* int_mult_di */
1155 COSTS_N_INSNS (72), /* int_div_si */
1156 COSTS_N_INSNS (72), /* int_div_di */
1157 1, /* branch_cost */
1158 4 /* memory_latency */
1162 static rtx mips_find_pic_call_symbol (rtx, rtx);
1164 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1165 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1166 struct GTY (()) mflip_mips16_entry {
1170 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1172 /* Hash table callbacks for mflip_mips16_htab. */
1175 mflip_mips16_htab_hash (const void *entry)
1177 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1181 mflip_mips16_htab_eq (const void *entry, const void *name)
1183 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1184 (const char *) name) == 0;
1187 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1188 mode, false if it should next add an attribute for the opposite mode. */
1189 static GTY(()) bool mips16_flipper;
1191 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1192 for -mflip-mips16. Return true if it should use "mips16" and false if
1193 it should use "nomips16". */
1196 mflip_mips16_use_mips16_p (tree decl)
1198 struct mflip_mips16_entry *entry;
1203 /* Use the opposite of the command-line setting for anonymous decls. */
1204 if (!DECL_NAME (decl))
1205 return !mips_base_mips16;
1207 if (!mflip_mips16_htab)
1208 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1209 mflip_mips16_htab_eq, NULL);
1211 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1212 hash = htab_hash_string (name);
1213 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1214 entry = (struct mflip_mips16_entry *) *slot;
1217 mips16_flipper = !mips16_flipper;
1218 entry = GGC_NEW (struct mflip_mips16_entry);
1220 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1223 return entry->mips16_p;
1226 /* Predicates to test for presence of "near" and "far"/"long_call"
1227 attributes on the given TYPE. */
1230 mips_near_type_p (const_tree type)
1232 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1236 mips_far_type_p (const_tree type)
1238 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1239 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1242 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1245 mips_mips16_decl_p (const_tree decl)
1247 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1251 mips_nomips16_decl_p (const_tree decl)
1253 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1256 /* Check if the interrupt attribute is set for a function. */
1259 mips_interrupt_type_p (tree type)
1261 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1264 /* Check if the attribute to use shadow register set is set for a function. */
1267 mips_use_shadow_register_set_p (tree type)
1269 return lookup_attribute ("use_shadow_register_set",
1270 TYPE_ATTRIBUTES (type)) != NULL;
1273 /* Check if the attribute to keep interrupts masked is set for a function. */
1276 mips_keep_interrupts_masked_p (tree type)
1278 return lookup_attribute ("keep_interrupts_masked",
1279 TYPE_ATTRIBUTES (type)) != NULL;
1282 /* Check if the attribute to use debug exception return is set for
1286 mips_use_debug_exception_return_p (tree type)
1288 return lookup_attribute ("use_debug_exception_return",
1289 TYPE_ATTRIBUTES (type)) != NULL;
1292 /* Return true if function DECL is a MIPS16 function. Return the ambient
1293 setting if DECL is null. */
1296 mips_use_mips16_mode_p (tree decl)
1300 /* Nested functions must use the same frame pointer as their
1301 parent and must therefore use the same ISA mode. */
1302 tree parent = decl_function_context (decl);
1305 if (mips_mips16_decl_p (decl))
1307 if (mips_nomips16_decl_p (decl))
1310 return mips_base_mips16;
1313 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1316 mips_comp_type_attributes (const_tree type1, const_tree type2)
1318 /* Disallow mixed near/far attributes. */
1319 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1321 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1326 /* Implement TARGET_INSERT_ATTRIBUTES. */
1329 mips_insert_attributes (tree decl, tree *attributes)
1332 bool mips16_p, nomips16_p;
1334 /* Check for "mips16" and "nomips16" attributes. */
1335 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1336 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1337 if (TREE_CODE (decl) != FUNCTION_DECL)
1340 error ("%qs attribute only applies to functions", "mips16");
1342 error ("%qs attribute only applies to functions", "nomips16");
1346 mips16_p |= mips_mips16_decl_p (decl);
1347 nomips16_p |= mips_nomips16_decl_p (decl);
1348 if (mips16_p || nomips16_p)
1350 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1351 if (mips16_p && nomips16_p)
1352 error ("%qE cannot have both %<mips16%> and "
1353 "%<nomips16%> attributes",
1356 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1358 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1359 "mips16" attribute, arbitrarily pick one. We must pick the same
1360 setting for duplicate declarations of a function. */
1361 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1362 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1367 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1370 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1372 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1373 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1374 error ("%qE redeclared with conflicting %qs attributes",
1375 DECL_NAME (newdecl), "mips16");
1376 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1377 error ("%qE redeclared with conflicting %qs attributes",
1378 DECL_NAME (newdecl), "nomips16");
1380 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1381 DECL_ATTRIBUTES (newdecl));
1384 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1385 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1388 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1390 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1392 *base_ptr = XEXP (x, 0);
1393 *offset_ptr = INTVAL (XEXP (x, 1));
1402 static unsigned int mips_build_integer (struct mips_integer_op *,
1403 unsigned HOST_WIDE_INT);
1405 /* A subroutine of mips_build_integer, with the same interface.
1406 Assume that the final action in the sequence should be a left shift. */
1409 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1411 unsigned int i, shift;
1413 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1414 since signed numbers are easier to load than unsigned ones. */
1416 while ((value & 1) == 0)
1417 value /= 2, shift++;
1419 i = mips_build_integer (codes, value);
1420 codes[i].code = ASHIFT;
1421 codes[i].value = shift;
1425 /* As for mips_build_shift, but assume that the final action will be
1426 an IOR or PLUS operation. */
1429 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1431 unsigned HOST_WIDE_INT high;
1434 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1435 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1437 /* The constant is too complex to load with a simple LUI/ORI pair,
1438 so we want to give the recursive call as many trailing zeros as
1439 possible. In this case, we know bit 16 is set and that the
1440 low 16 bits form a negative number. If we subtract that number
1441 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1442 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1443 codes[i].code = PLUS;
1444 codes[i].value = CONST_LOW_PART (value);
1448 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1449 bits gives a value with at least 17 trailing zeros. */
1450 i = mips_build_integer (codes, high);
1451 codes[i].code = IOR;
1452 codes[i].value = value & 0xffff;
1457 /* Fill CODES with a sequence of rtl operations to load VALUE.
1458 Return the number of operations needed. */
1461 mips_build_integer (struct mips_integer_op *codes,
1462 unsigned HOST_WIDE_INT value)
1464 if (SMALL_OPERAND (value)
1465 || SMALL_OPERAND_UNSIGNED (value)
1466 || LUI_OPERAND (value))
1468 /* The value can be loaded with a single instruction. */
1469 codes[0].code = UNKNOWN;
1470 codes[0].value = value;
1473 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1475 /* Either the constant is a simple LUI/ORI combination or its
1476 lowest bit is set. We don't want to shift in this case. */
1477 return mips_build_lower (codes, value);
1479 else if ((value & 0xffff) == 0)
1481 /* The constant will need at least three actions. The lowest
1482 16 bits are clear, so the final action will be a shift. */
1483 return mips_build_shift (codes, value);
1487 /* The final action could be a shift, add or inclusive OR.
1488 Rather than use a complex condition to select the best
1489 approach, try both mips_build_shift and mips_build_lower
1490 and pick the one that gives the shortest sequence.
1491 Note that this case is only used once per constant. */
1492 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1493 unsigned int cost, alt_cost;
1495 cost = mips_build_shift (codes, value);
1496 alt_cost = mips_build_lower (alt_codes, value);
1497 if (alt_cost < cost)
1499 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1506 /* Return true if symbols of type TYPE require a GOT access. */
1509 mips_got_symbol_type_p (enum mips_symbol_type type)
1513 case SYMBOL_GOT_PAGE_OFST:
1514 case SYMBOL_GOT_DISP:
1522 /* Return true if X is a thread-local symbol. */
1525 mips_tls_symbol_p (rtx x)
1527 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1530 /* Return true if SYMBOL_REF X is associated with a global symbol
1531 (in the STB_GLOBAL sense). */
1534 mips_global_symbol_p (const_rtx x)
1536 const_tree decl = SYMBOL_REF_DECL (x);
1539 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1541 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1542 or weak symbols. Relocations in the object file will be against
1543 the target symbol, so it's that symbol's binding that matters here. */
1544 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1547 /* Return true if function X is a libgcc MIPS16 stub function. */
1550 mips16_stub_function_p (const_rtx x)
1552 return (GET_CODE (x) == SYMBOL_REF
1553 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1556 /* Return true if function X is a locally-defined and locally-binding
1560 mips16_local_function_p (const_rtx x)
1562 return (GET_CODE (x) == SYMBOL_REF
1563 && SYMBOL_REF_LOCAL_P (x)
1564 && !SYMBOL_REF_EXTERNAL_P (x)
1565 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1568 /* Return true if SYMBOL_REF X binds locally. */
1571 mips_symbol_binds_local_p (const_rtx x)
1573 return (SYMBOL_REF_DECL (x)
1574 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1575 : SYMBOL_REF_LOCAL_P (x));
1578 /* Return true if rtx constants of mode MODE should be put into a small
1582 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1584 return (!TARGET_EMBEDDED_DATA
1585 && TARGET_LOCAL_SDATA
1586 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1589 /* Return true if X should not be moved directly into register $25.
1590 We need this because many versions of GAS will treat "la $25,foo" as
1591 part of a call sequence and so allow a global "foo" to be lazily bound. */
1594 mips_dangerous_for_la25_p (rtx x)
1596 return (!TARGET_EXPLICIT_RELOCS
1598 && GET_CODE (x) == SYMBOL_REF
1599 && mips_global_symbol_p (x));
1602 /* Return true if calls to X might need $25 to be valid on entry. */
1605 mips_use_pic_fn_addr_reg_p (const_rtx x)
1607 if (!TARGET_USE_PIC_FN_ADDR_REG)
1610 /* MIPS16 stub functions are guaranteed not to use $25. */
1611 if (mips16_stub_function_p (x))
1614 if (GET_CODE (x) == SYMBOL_REF)
1616 /* If PLTs and copy relocations are available, the static linker
1617 will make sure that $25 is valid on entry to the target function. */
1618 if (TARGET_ABICALLS_PIC0)
1621 /* Locally-defined functions use absolute accesses to set up
1622 the global pointer. */
1623 if (TARGET_ABSOLUTE_ABICALLS
1624 && mips_symbol_binds_local_p (x)
1625 && !SYMBOL_REF_EXTERNAL_P (x))
1632 /* Return the method that should be used to access SYMBOL_REF or
1633 LABEL_REF X in context CONTEXT. */
1635 static enum mips_symbol_type
1636 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1639 return SYMBOL_GOT_DISP;
1641 if (GET_CODE (x) == LABEL_REF)
1643 /* LABEL_REFs are used for jump tables as well as text labels.
1644 Only return SYMBOL_PC_RELATIVE if we know the label is in
1645 the text section. */
1646 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1647 return SYMBOL_PC_RELATIVE;
1649 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1650 return SYMBOL_GOT_PAGE_OFST;
1652 return SYMBOL_ABSOLUTE;
1655 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1657 if (SYMBOL_REF_TLS_MODEL (x))
1660 if (CONSTANT_POOL_ADDRESS_P (x))
1662 if (TARGET_MIPS16_TEXT_LOADS)
1663 return SYMBOL_PC_RELATIVE;
1665 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1666 return SYMBOL_PC_RELATIVE;
1668 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1669 return SYMBOL_GP_RELATIVE;
1672 /* Do not use small-data accesses for weak symbols; they may end up
1674 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1675 return SYMBOL_GP_RELATIVE;
1677 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1679 if (TARGET_ABICALLS_PIC2
1680 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1682 /* There are three cases to consider:
1684 - o32 PIC (either with or without explicit relocs)
1685 - n32/n64 PIC without explicit relocs
1686 - n32/n64 PIC with explicit relocs
1688 In the first case, both local and global accesses will use an
1689 R_MIPS_GOT16 relocation. We must correctly predict which of
1690 the two semantics (local or global) the assembler and linker
1691 will apply. The choice depends on the symbol's binding rather
1692 than its visibility.
1694 In the second case, the assembler will not use R_MIPS_GOT16
1695 relocations, but it chooses between local and global accesses
1696 in the same way as for o32 PIC.
1698 In the third case we have more freedom since both forms of
1699 access will work for any kind of symbol. However, there seems
1700 little point in doing things differently. */
1701 if (mips_global_symbol_p (x))
1702 return SYMBOL_GOT_DISP;
1704 return SYMBOL_GOT_PAGE_OFST;
1707 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1708 return SYMBOL_FORCE_TO_MEM;
1710 return SYMBOL_ABSOLUTE;
1713 /* Classify the base of symbolic expression X, given that X appears in
1716 static enum mips_symbol_type
1717 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1721 split_const (x, &x, &offset);
1722 if (UNSPEC_ADDRESS_P (x))
1723 return UNSPEC_ADDRESS_TYPE (x);
1725 return mips_classify_symbol (x, context);
1728 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1729 is the alignment in bytes of SYMBOL_REF X. */
1732 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1734 HOST_WIDE_INT align;
1736 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1737 return IN_RANGE (offset, 0, align - 1);
1740 /* Return true if X is a symbolic constant that can be used in context
1741 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1744 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1745 enum mips_symbol_type *symbol_type)
1749 split_const (x, &x, &offset);
1750 if (UNSPEC_ADDRESS_P (x))
1752 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1753 x = UNSPEC_ADDRESS (x);
1755 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1757 *symbol_type = mips_classify_symbol (x, context);
1758 if (*symbol_type == SYMBOL_TLS)
1764 if (offset == const0_rtx)
1767 /* Check whether a nonzero offset is valid for the underlying
1769 switch (*symbol_type)
1771 case SYMBOL_ABSOLUTE:
1772 case SYMBOL_FORCE_TO_MEM:
1773 case SYMBOL_32_HIGH:
1774 case SYMBOL_64_HIGH:
1777 /* If the target has 64-bit pointers and the object file only
1778 supports 32-bit symbols, the values of those symbols will be
1779 sign-extended. In this case we can't allow an arbitrary offset
1780 in case the 32-bit value X + OFFSET has a different sign from X. */
1781 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1782 return offset_within_block_p (x, INTVAL (offset));
1784 /* In other cases the relocations can handle any offset. */
1787 case SYMBOL_PC_RELATIVE:
1788 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1789 In this case, we no longer have access to the underlying constant,
1790 but the original symbol-based access was known to be valid. */
1791 if (GET_CODE (x) == LABEL_REF)
1796 case SYMBOL_GP_RELATIVE:
1797 /* Make sure that the offset refers to something within the
1798 same object block. This should guarantee that the final
1799 PC- or GP-relative offset is within the 16-bit limit. */
1800 return offset_within_block_p (x, INTVAL (offset));
1802 case SYMBOL_GOT_PAGE_OFST:
1803 case SYMBOL_GOTOFF_PAGE:
1804 /* If the symbol is global, the GOT entry will contain the symbol's
1805 address, and we will apply a 16-bit offset after loading it.
1806 If the symbol is local, the linker should provide enough local
1807 GOT entries for a 16-bit offset, but larger offsets may lead
1809 return SMALL_INT (offset);
1813 /* There is no carry between the HI and LO REL relocations, so the
1814 offset is only valid if we know it won't lead to such a carry. */
1815 return mips_offset_within_alignment_p (x, INTVAL (offset));
1817 case SYMBOL_GOT_DISP:
1818 case SYMBOL_GOTOFF_DISP:
1819 case SYMBOL_GOTOFF_CALL:
1820 case SYMBOL_GOTOFF_LOADGP:
1823 case SYMBOL_GOTTPREL:
1831 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1832 single instruction. We rely on the fact that, in the worst case,
1833 all instructions involved in a MIPS16 address calculation are usually
1837 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1841 case SYMBOL_ABSOLUTE:
1842 /* When using 64-bit symbols, we need 5 preparatory instructions,
1845 lui $at,%highest(symbol)
1846 daddiu $at,$at,%higher(symbol)
1848 daddiu $at,$at,%hi(symbol)
1851 The final address is then $at + %lo(symbol). With 32-bit
1852 symbols we just need a preparatory LUI for normal mode and
1853 a preparatory LI and SLL for MIPS16. */
1854 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1856 case SYMBOL_GP_RELATIVE:
1857 /* Treat GP-relative accesses as taking a single instruction on
1858 MIPS16 too; the copy of $gp can often be shared. */
1861 case SYMBOL_PC_RELATIVE:
1862 /* PC-relative constants can be only be used with ADDIUPC,
1863 DADDIUPC, LWPC and LDPC. */
1864 if (mode == MAX_MACHINE_MODE
1865 || GET_MODE_SIZE (mode) == 4
1866 || GET_MODE_SIZE (mode) == 8)
1869 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1872 case SYMBOL_FORCE_TO_MEM:
1873 /* LEAs will be converted into constant-pool references by
1875 if (mode == MAX_MACHINE_MODE)
1878 /* The constant must be loaded and then dereferenced. */
1881 case SYMBOL_GOT_DISP:
1882 /* The constant will have to be loaded from the GOT before it
1883 is used in an address. */
1884 if (mode != MAX_MACHINE_MODE)
1889 case SYMBOL_GOT_PAGE_OFST:
1890 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1891 local/global classification is accurate. The worst cases are:
1893 (1) For local symbols when generating o32 or o64 code. The assembler
1899 ...and the final address will be $at + %lo(symbol).
1901 (2) For global symbols when -mxgot. The assembler will use:
1903 lui $at,%got_hi(symbol)
1906 ...and the final address will be $at + %got_lo(symbol). */
1909 case SYMBOL_GOTOFF_PAGE:
1910 case SYMBOL_GOTOFF_DISP:
1911 case SYMBOL_GOTOFF_CALL:
1912 case SYMBOL_GOTOFF_LOADGP:
1913 case SYMBOL_32_HIGH:
1914 case SYMBOL_64_HIGH:
1920 case SYMBOL_GOTTPREL:
1923 /* A 16-bit constant formed by a single relocation, or a 32-bit
1924 constant formed from a high 16-bit relocation and a low 16-bit
1925 relocation. Use mips_split_p to determine which. 32-bit
1926 constants need an "lui; addiu" sequence for normal mode and
1927 an "li; sll; addiu" sequence for MIPS16 mode. */
1928 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1931 /* We don't treat a bare TLS symbol as a constant. */
1937 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1938 to load symbols of type TYPE into a register. Return 0 if the given
1939 type of symbol cannot be used as an immediate operand.
1941 Otherwise, return the number of instructions needed to load or store
1942 values of mode MODE to or from addresses of type TYPE. Return 0 if
1943 the given type of symbol is not valid in addresses.
1945 In both cases, treat extended MIPS16 instructions as two instructions. */
1948 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1950 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1953 /* A for_each_rtx callback. Stop the search if *X references a
1954 thread-local symbol. */
1957 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1959 return mips_tls_symbol_p (*x);
1962 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1965 mips_cannot_force_const_mem (rtx x)
1967 enum mips_symbol_type type;
1970 /* There is no assembler syntax for expressing an address-sized
1972 if (GET_CODE (x) == HIGH)
1975 /* As an optimization, reject constants that mips_legitimize_move
1978 Suppose we have a multi-instruction sequence that loads constant C
1979 into register R. If R does not get allocated a hard register, and
1980 R is used in an operand that allows both registers and memory
1981 references, reload will consider forcing C into memory and using
1982 one of the instruction's memory alternatives. Returning false
1983 here will force it to use an input reload instead. */
1984 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1987 split_const (x, &base, &offset);
1988 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1989 && type != SYMBOL_FORCE_TO_MEM)
1991 /* The same optimization as for CONST_INT. */
1992 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1995 /* If MIPS16 constant pools live in the text section, they should
1996 not refer to anything that might need run-time relocation. */
1997 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2001 /* TLS symbols must be computed by mips_legitimize_move. */
2002 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2008 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2009 constants when we're using a per-function constant pool. */
2012 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2013 const_rtx x ATTRIBUTE_UNUSED)
2015 return !TARGET_MIPS16_PCREL_LOADS;
2018 /* Return true if register REGNO is a valid base register for mode MODE.
2019 STRICT_P is true if REG_OK_STRICT is in effect. */
2022 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2025 if (!HARD_REGISTER_NUM_P (regno))
2029 regno = reg_renumber[regno];
2032 /* These fake registers will be eliminated to either the stack or
2033 hard frame pointer, both of which are usually valid base registers.
2034 Reload deals with the cases where the eliminated form isn't valid. */
2035 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2038 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2039 values, nothing smaller. There are two problems here:
2041 (a) Instantiating virtual registers can introduce new uses of the
2042 stack pointer. If these virtual registers are valid addresses,
2043 the stack pointer should be too.
2045 (b) Most uses of the stack pointer are not made explicit until
2046 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2047 We don't know until that stage whether we'll be eliminating to the
2048 stack pointer (which needs the restriction) or the hard frame
2049 pointer (which doesn't).
2051 All in all, it seems more consistent to only enforce this restriction
2052 during and after reload. */
2053 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2054 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2056 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2059 /* Return true if X is a valid base register for mode MODE.
2060 STRICT_P is true if REG_OK_STRICT is in effect. */
2063 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2065 if (!strict_p && GET_CODE (x) == SUBREG)
2069 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2072 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2073 can address a value of mode MODE. */
2076 mips_valid_offset_p (rtx x, enum machine_mode mode)
2078 /* Check that X is a signed 16-bit number. */
2079 if (!const_arith_operand (x, Pmode))
2082 /* We may need to split multiword moves, so make sure that every word
2084 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2085 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2091 /* Return true if a LO_SUM can address a value of mode MODE when the
2092 LO_SUM symbol has type SYMBOL_TYPE. */
2095 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2097 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2099 if (mips_symbol_insns (symbol_type, mode) == 0)
2102 /* Check that there is a known low-part relocation. */
2103 if (mips_lo_relocs[symbol_type] == NULL)
2106 /* We may need to split multiword moves, so make sure that each word
2107 can be accessed without inducing a carry. This is mainly needed
2108 for o64, which has historically only guaranteed 64-bit alignment
2109 for 128-bit types. */
2110 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2111 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2117 /* Return true if X is a valid address for machine mode MODE. If it is,
2118 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2122 mips_classify_address (struct mips_address_info *info, rtx x,
2123 enum machine_mode mode, bool strict_p)
2125 switch (GET_CODE (x))
2129 info->type = ADDRESS_REG;
2131 info->offset = const0_rtx;
2132 return mips_valid_base_register_p (info->reg, mode, strict_p);
2135 info->type = ADDRESS_REG;
2136 info->reg = XEXP (x, 0);
2137 info->offset = XEXP (x, 1);
2138 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2139 && mips_valid_offset_p (info->offset, mode));
2142 info->type = ADDRESS_LO_SUM;
2143 info->reg = XEXP (x, 0);
2144 info->offset = XEXP (x, 1);
2145 /* We have to trust the creator of the LO_SUM to do something vaguely
2146 sane. Target-independent code that creates a LO_SUM should also
2147 create and verify the matching HIGH. Target-independent code that
2148 adds an offset to a LO_SUM must prove that the offset will not
2149 induce a carry. Failure to do either of these things would be
2150 a bug, and we are not required to check for it here. The MIPS
2151 backend itself should only create LO_SUMs for valid symbolic
2152 constants, with the high part being either a HIGH or a copy
2155 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2156 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2157 && mips_valid_lo_sum_p (info->symbol_type, mode));
2160 /* Small-integer addresses don't occur very often, but they
2161 are legitimate if $0 is a valid base register. */
2162 info->type = ADDRESS_CONST_INT;
2163 return !TARGET_MIPS16 && SMALL_INT (x);
2168 info->type = ADDRESS_SYMBOLIC;
2169 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2171 && mips_symbol_insns (info->symbol_type, mode) > 0
2172 && !mips_split_p[info->symbol_type]);
2179 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2182 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2184 struct mips_address_info addr;
2186 return mips_classify_address (&addr, x, mode, strict_p);
2189 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2192 mips_stack_address_p (rtx x, enum machine_mode mode)
2194 struct mips_address_info addr;
2196 return (mips_classify_address (&addr, x, mode, false)
2197 && addr.type == ADDRESS_REG
2198 && addr.reg == stack_pointer_rtx);
2201 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2202 address instruction. Note that such addresses are not considered
2203 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2204 is so restricted. */
2207 mips_lwxs_address_p (rtx addr)
2210 && GET_CODE (addr) == PLUS
2211 && REG_P (XEXP (addr, 1)))
2213 rtx offset = XEXP (addr, 0);
2214 if (GET_CODE (offset) == MULT
2215 && REG_P (XEXP (offset, 0))
2216 && CONST_INT_P (XEXP (offset, 1))
2217 && INTVAL (XEXP (offset, 1)) == 4)
2223 /* Return true if a value at OFFSET bytes from base register BASE can be
2224 accessed using an unextended MIPS16 instruction. MODE is the mode of
2227 Usually the offset in an unextended instruction is a 5-bit field.
2228 The offset is unsigned and shifted left once for LH and SH, twice
2229 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2230 an 8-bit immediate field that's shifted left twice. */
2233 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2234 unsigned HOST_WIDE_INT offset)
2236 if (offset % GET_MODE_SIZE (mode) == 0)
2238 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2239 return offset < 256U * GET_MODE_SIZE (mode);
2240 return offset < 32U * GET_MODE_SIZE (mode);
2245 /* Return the number of instructions needed to load or store a value
2246 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2247 Assume that multiword moves may need to be split into word moves
2248 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2251 For MIPS16 code, count extended instructions as two instructions. */
2254 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2256 struct mips_address_info addr;
2259 /* BLKmode is used for single unaligned loads and stores and should
2260 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2261 meaningless, so we have to single it out as a special case one way
2263 if (mode != BLKmode && might_split_p)
2264 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2268 if (mips_classify_address (&addr, x, mode, false))
2273 && !mips16_unextended_reference_p (mode, addr.reg,
2274 UINTVAL (addr.offset)))
2278 case ADDRESS_LO_SUM:
2279 return TARGET_MIPS16 ? factor * 2 : factor;
2281 case ADDRESS_CONST_INT:
2284 case ADDRESS_SYMBOLIC:
2285 return factor * mips_symbol_insns (addr.symbol_type, mode);
2290 /* Return the number of instructions needed to load constant X.
2291 Return 0 if X isn't a valid constant. */
2294 mips_const_insns (rtx x)
2296 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2297 enum mips_symbol_type symbol_type;
2300 switch (GET_CODE (x))
2303 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2305 || !mips_split_p[symbol_type])
2308 /* This is simply an LUI for normal mode. It is an extended
2309 LI followed by an extended SLL for MIPS16. */
2310 return TARGET_MIPS16 ? 4 : 1;
2314 /* Unsigned 8-bit constants can be loaded using an unextended
2315 LI instruction. Unsigned 16-bit constants can be loaded
2316 using an extended LI. Negative constants must be loaded
2317 using LI and then negated. */
2318 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2319 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2320 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2321 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2324 return mips_build_integer (codes, INTVAL (x));
2328 /* Allow zeros for normal mode, where we can use $0. */
2329 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2335 /* See if we can refer to X directly. */
2336 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2337 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2339 /* Otherwise try splitting the constant into a base and offset.
2340 If the offset is a 16-bit value, we can load the base address
2341 into a register and then use (D)ADDIU to add in the offset.
2342 If the offset is larger, we can load the base and offset
2343 into separate registers and add them together with (D)ADDU.
2344 However, the latter is only possible before reload; during
2345 and after reload, we must have the option of forcing the
2346 constant into the pool instead. */
2347 split_const (x, &x, &offset);
2350 int n = mips_const_insns (x);
2353 if (SMALL_INT (offset))
2355 else if (!targetm.cannot_force_const_mem (x))
2356 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2363 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2371 /* X is a doubleword constant that can be handled by splitting it into
2372 two words and loading each word separately. Return the number of
2373 instructions required to do this. */
2376 mips_split_const_insns (rtx x)
2378 unsigned int low, high;
2380 low = mips_const_insns (mips_subword (x, false));
2381 high = mips_const_insns (mips_subword (x, true));
2382 gcc_assert (low > 0 && high > 0);
2386 /* Return the number of instructions needed to implement INSN,
2387 given that it loads from or stores to MEM. Count extended
2388 MIPS16 instructions as two instructions. */
2391 mips_load_store_insns (rtx mem, rtx insn)
2393 enum machine_mode mode;
2397 gcc_assert (MEM_P (mem));
2398 mode = GET_MODE (mem);
2400 /* Try to prove that INSN does not need to be split. */
2401 might_split_p = true;
2402 if (GET_MODE_BITSIZE (mode) == 64)
2404 set = single_set (insn);
2405 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2406 might_split_p = false;
2409 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2412 /* Return the number of instructions needed for an integer division. */
2415 mips_idiv_insns (void)
2420 if (TARGET_CHECK_ZERO_DIV)
2422 if (GENERATE_DIVIDE_TRAPS)
2428 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2433 /* Emit a move from SRC to DEST. Assume that the move expanders can
2434 handle all moves if !can_create_pseudo_p (). The distinction is
2435 important because, unlike emit_move_insn, the move expanders know
2436 how to force Pmode objects into the constant pool even when the
2437 constant pool address is not itself legitimate. */
2440 mips_emit_move (rtx dest, rtx src)
2442 return (can_create_pseudo_p ()
2443 ? emit_move_insn (dest, src)
2444 : emit_move_insn_1 (dest, src));
2447 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2450 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2452 emit_insn (gen_rtx_SET (VOIDmode, target,
2453 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2456 /* Compute (CODE OP0 OP1) and store the result in a new register
2457 of mode MODE. Return that new register. */
2460 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2464 reg = gen_reg_rtx (mode);
2465 mips_emit_binary (code, reg, op0, op1);
2469 /* Copy VALUE to a register and return that register. If new pseudos
2470 are allowed, copy it into a new register, otherwise use DEST. */
2473 mips_force_temporary (rtx dest, rtx value)
2475 if (can_create_pseudo_p ())
2476 return force_reg (Pmode, value);
2479 mips_emit_move (dest, value);
2484 /* Emit a call sequence with call pattern PATTERN and return the call
2485 instruction itself (which is not necessarily the last instruction
2486 emitted). ORIG_ADDR is the original, unlegitimized address,
2487 ADDR is the legitimized form, and LAZY_P is true if the call
2488 address is lazily-bound. */
2491 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2495 insn = emit_call_insn (pattern);
2497 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2499 /* MIPS16 JALRs only take MIPS16 registers. If the target
2500 function requires $25 to be valid on entry, we must copy it
2501 there separately. The move instruction can be put in the
2502 call's delay slot. */
2503 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2504 emit_insn_before (gen_move_insn (reg, addr), insn);
2505 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2509 /* Lazy-binding stubs require $gp to be valid on entry. */
2510 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2514 /* See the comment above load_call<mode> for details. */
2515 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2516 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2517 emit_insn (gen_update_got_version ());
2522 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2523 then add CONST_INT OFFSET to the result. */
2526 mips_unspec_address_offset (rtx base, rtx offset,
2527 enum mips_symbol_type symbol_type)
2529 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2530 UNSPEC_ADDRESS_FIRST + symbol_type);
2531 if (offset != const0_rtx)
2532 base = gen_rtx_PLUS (Pmode, base, offset);
2533 return gen_rtx_CONST (Pmode, base);
2536 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2537 type SYMBOL_TYPE. */
2540 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2544 split_const (address, &base, &offset);
2545 return mips_unspec_address_offset (base, offset, symbol_type);
2548 /* If OP is an UNSPEC address, return the address to which it refers,
2549 otherwise return OP itself. */
2552 mips_strip_unspec_address (rtx op)
2556 split_const (op, &base, &offset);
2557 if (UNSPEC_ADDRESS_P (base))
2558 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2562 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2563 high part to BASE and return the result. Just return BASE otherwise.
2564 TEMP is as for mips_force_temporary.
2566 The returned expression can be used as the first operand to a LO_SUM. */
2569 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2570 enum mips_symbol_type symbol_type)
2572 if (mips_split_p[symbol_type])
2574 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2575 addr = mips_force_temporary (temp, addr);
2576 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2581 /* Return an instruction that copies $gp into register REG. We want
2582 GCC to treat the register's value as constant, so that its value
2583 can be rematerialized on demand. */
2586 gen_load_const_gp (rtx reg)
2588 return (Pmode == SImode
2589 ? gen_load_const_gp_si (reg)
2590 : gen_load_const_gp_di (reg));
2593 /* Return a pseudo register that contains the value of $gp throughout
2594 the current function. Such registers are needed by MIPS16 functions,
2595 for which $gp itself is not a valid base register or addition operand. */
2598 mips16_gp_pseudo_reg (void)
2600 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2601 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2603 /* Don't emit an instruction to initialize the pseudo register if
2604 we are being called from the tree optimizers' cost-calculation
2606 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2607 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2611 push_topmost_sequence ();
2613 scan = get_insns ();
2614 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2615 scan = NEXT_INSN (scan);
2617 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2618 emit_insn_after (insn, scan);
2620 pop_topmost_sequence ();
2622 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2625 return cfun->machine->mips16_gp_pseudo_rtx;
2628 /* Return a base register that holds pic_offset_table_rtx.
2629 TEMP, if nonnull, is a scratch Pmode base register. */
2632 mips_pic_base_register (rtx temp)
2635 return pic_offset_table_rtx;
2637 if (can_create_pseudo_p ())
2638 return mips16_gp_pseudo_reg ();
2641 /* The first post-reload split exposes all references to $gp
2642 (both uses and definitions). All references must remain
2643 explicit after that point.
2645 It is safe to introduce uses of $gp at any time, so for
2646 simplicity, we do that before the split too. */
2647 mips_emit_move (temp, pic_offset_table_rtx);
2649 emit_insn (gen_load_const_gp (temp));
2653 /* Return the RHS of a load_call<mode> insn. */
2656 mips_unspec_call (rtx reg, rtx symbol)
2660 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2661 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2664 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2665 reference. Return NULL_RTX otherwise. */
2668 mips_strip_unspec_call (rtx src)
2670 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2671 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2675 /* Create and return a GOT reference of type TYPE for address ADDR.
2676 TEMP, if nonnull, is a scratch Pmode base register. */
2679 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2681 rtx base, high, lo_sum_symbol;
2683 base = mips_pic_base_register (temp);
2685 /* If we used the temporary register to load $gp, we can't use
2686 it for the high part as well. */
2687 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2690 high = mips_unspec_offset_high (temp, base, addr, type);
2691 lo_sum_symbol = mips_unspec_address (addr, type);
2693 if (type == SYMBOL_GOTOFF_CALL)
2694 return mips_unspec_call (high, lo_sum_symbol);
2696 return (Pmode == SImode
2697 ? gen_unspec_gotsi (high, lo_sum_symbol)
2698 : gen_unspec_gotdi (high, lo_sum_symbol));
2701 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2702 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2703 constant in that context and can be split into high and low parts.
2704 If so, and if LOW_OUT is nonnull, emit the high part and store the
2705 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2707 TEMP is as for mips_force_temporary and is used to load the high
2708 part into a register.
2710 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2711 a legitimize SET_SRC for an .md pattern, otherwise the low part
2712 is guaranteed to be a legitimate address for mode MODE. */
2715 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2717 enum mips_symbol_context context;
2718 enum mips_symbol_type symbol_type;
2721 context = (mode == MAX_MACHINE_MODE
2722 ? SYMBOL_CONTEXT_LEA
2723 : SYMBOL_CONTEXT_MEM);
2724 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2726 addr = XEXP (addr, 0);
2727 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2728 && mips_symbol_insns (symbol_type, mode) > 0
2729 && mips_split_hi_p[symbol_type])
2732 switch (symbol_type)
2734 case SYMBOL_GOT_PAGE_OFST:
2735 /* The high part of a page/ofst pair is loaded from the GOT. */
2736 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2747 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2748 && mips_symbol_insns (symbol_type, mode) > 0
2749 && mips_split_p[symbol_type])
2752 switch (symbol_type)
2754 case SYMBOL_GOT_DISP:
2755 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2756 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2759 case SYMBOL_GP_RELATIVE:
2760 high = mips_pic_base_register (temp);
2761 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2765 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2766 high = mips_force_temporary (temp, high);
2767 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2776 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2777 mips_force_temporary; it is only needed when OFFSET is not a
2781 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2783 if (!SMALL_OPERAND (offset))
2789 /* Load the full offset into a register so that we can use
2790 an unextended instruction for the address itself. */
2791 high = GEN_INT (offset);
2796 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2797 The addition inside the macro CONST_HIGH_PART may cause an
2798 overflow, so we need to force a sign-extension check. */
2799 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2800 offset = CONST_LOW_PART (offset);
2802 high = mips_force_temporary (temp, high);
2803 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2805 return plus_constant (reg, offset);
2808 /* The __tls_get_attr symbol. */
2809 static GTY(()) rtx mips_tls_symbol;
2811 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2812 the TLS symbol we are referencing and TYPE is the symbol type to use
2813 (either global dynamic or local dynamic). V0 is an RTX for the
2814 return value location. */
2817 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2821 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2823 if (!mips_tls_symbol)
2824 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2826 loc = mips_unspec_address (sym, type);
2830 emit_insn (gen_rtx_SET (Pmode, a0,
2831 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2832 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2833 const0_rtx, NULL_RTX, false);
2834 RTL_CONST_CALL_P (insn) = 1;
2835 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2836 insn = get_insns ();
2843 /* Return a pseudo register that contains the current thread pointer. */
2850 tp = gen_reg_rtx (Pmode);
2851 if (Pmode == DImode)
2852 emit_insn (gen_tls_get_tp_di (tp));
2854 emit_insn (gen_tls_get_tp_si (tp));
2858 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2859 its address. The return value will be both a valid address and a valid
2860 SET_SRC (either a REG or a LO_SUM). */
2863 mips_legitimize_tls_address (rtx loc)
2865 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2866 enum tls_model model;
2870 sorry ("MIPS16 TLS");
2871 return gen_reg_rtx (Pmode);
2874 model = SYMBOL_REF_TLS_MODEL (loc);
2875 /* Only TARGET_ABICALLS code can have more than one module; other
2876 code must be be static and should not use a GOT. All TLS models
2877 reduce to local exec in this situation. */
2878 if (!TARGET_ABICALLS)
2879 model = TLS_MODEL_LOCAL_EXEC;
2883 case TLS_MODEL_GLOBAL_DYNAMIC:
2884 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2885 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2886 dest = gen_reg_rtx (Pmode);
2887 emit_libcall_block (insn, dest, v0, loc);
2890 case TLS_MODEL_LOCAL_DYNAMIC:
2891 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2892 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2893 tmp1 = gen_reg_rtx (Pmode);
2895 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2896 share the LDM result with other LD model accesses. */
2897 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2899 emit_libcall_block (insn, tmp1, v0, eqv);
2901 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2902 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2903 mips_unspec_address (loc, SYMBOL_DTPREL));
2906 case TLS_MODEL_INITIAL_EXEC:
2907 tp = mips_get_tp ();
2908 tmp1 = gen_reg_rtx (Pmode);
2909 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2910 if (Pmode == DImode)
2911 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2913 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2914 dest = gen_reg_rtx (Pmode);
2915 emit_insn (gen_add3_insn (dest, tmp1, tp));
2918 case TLS_MODEL_LOCAL_EXEC:
2919 tp = mips_get_tp ();
2920 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2921 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2922 mips_unspec_address (loc, SYMBOL_TPREL));
2931 /* If X is not a valid address for mode MODE, force it into a register. */
2934 mips_force_address (rtx x, enum machine_mode mode)
2936 if (!mips_legitimate_address_p (mode, x, false))
2937 x = force_reg (Pmode, x);
2941 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2942 be legitimized in a way that the generic machinery might not expect,
2943 return a new address, otherwise return NULL. MODE is the mode of
2944 the memory being accessed. */
2947 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2948 enum machine_mode mode)
2951 HOST_WIDE_INT offset;
2953 if (mips_tls_symbol_p (x))
2954 return mips_legitimize_tls_address (x);
2956 /* See if the address can split into a high part and a LO_SUM. */
2957 if (mips_split_symbol (NULL, x, mode, &addr))
2958 return mips_force_address (addr, mode);
2960 /* Handle BASE + OFFSET using mips_add_offset. */
2961 mips_split_plus (x, &base, &offset);
2964 if (!mips_valid_base_register_p (base, mode, false))
2965 base = copy_to_mode_reg (Pmode, base);
2966 addr = mips_add_offset (NULL, base, offset);
2967 return mips_force_address (addr, mode);
2973 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2976 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2978 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2979 enum machine_mode mode;
2980 unsigned int i, num_ops;
2983 mode = GET_MODE (dest);
2984 num_ops = mips_build_integer (codes, value);
2986 /* Apply each binary operation to X. Invariant: X is a legitimate
2987 source operand for a SET pattern. */
2988 x = GEN_INT (codes[0].value);
2989 for (i = 1; i < num_ops; i++)
2991 if (!can_create_pseudo_p ())
2993 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2997 x = force_reg (mode, x);
2998 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3001 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3004 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3005 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3009 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3013 /* Split moves of big integers into smaller pieces. */
3014 if (splittable_const_int_operand (src, mode))
3016 mips_move_integer (dest, dest, INTVAL (src));
3020 /* Split moves of symbolic constants into high/low pairs. */
3021 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3023 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3027 /* Generate the appropriate access sequences for TLS symbols. */
3028 if (mips_tls_symbol_p (src))
3030 mips_emit_move (dest, mips_legitimize_tls_address (src));
3034 /* If we have (const (plus symbol offset)), and that expression cannot
3035 be forced into memory, load the symbol first and add in the offset.
3036 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3037 forced into memory, as it usually produces better code. */
3038 split_const (src, &base, &offset);
3039 if (offset != const0_rtx
3040 && (targetm.cannot_force_const_mem (src)
3041 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3043 base = mips_force_temporary (dest, base);
3044 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3048 src = force_const_mem (mode, src);
3050 /* When using explicit relocs, constant pool references are sometimes
3051 not legitimate addresses. */
3052 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3053 mips_emit_move (dest, src);
3056 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3057 sequence that is valid. */
3060 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3062 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3064 mips_emit_move (dest, force_reg (mode, src));
3068 /* We need to deal with constants that would be legitimate
3069 immediate_operands but aren't legitimate move_operands. */
3070 if (CONSTANT_P (src) && !move_operand (src, mode))
3072 mips_legitimize_const_move (mode, dest, src);
3073 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3079 /* Return true if value X in context CONTEXT is a small-data address
3080 that can be rewritten as a LO_SUM. */
3083 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3085 enum mips_symbol_type symbol_type;
3087 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3088 && !mips_split_p[SYMBOL_GP_RELATIVE]
3089 && mips_symbolic_constant_p (x, context, &symbol_type)
3090 && symbol_type == SYMBOL_GP_RELATIVE);
3093 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3094 containing MEM, or null if none. */
3097 mips_small_data_pattern_1 (rtx *loc, void *data)
3099 enum mips_symbol_context context;
3101 if (GET_CODE (*loc) == LO_SUM)
3106 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3111 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3112 return mips_rewrite_small_data_p (*loc, context);
3115 /* Return true if OP refers to small data symbols directly, not through
3119 mips_small_data_pattern_p (rtx op)
3121 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3124 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3125 DATA is the containing MEM, or null if none. */
3128 mips_rewrite_small_data_1 (rtx *loc, void *data)
3130 enum mips_symbol_context context;
3134 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3138 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3139 if (mips_rewrite_small_data_p (*loc, context))
3140 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3142 if (GET_CODE (*loc) == LO_SUM)
3148 /* Rewrite instruction pattern PATTERN so that it refers to small data
3149 using explicit relocations. */
3152 mips_rewrite_small_data (rtx pattern)
3154 pattern = copy_insn (pattern);
3155 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3159 /* We need a lot of little routines to check the range of MIPS16 immediate
3163 m16_check_op (rtx op, int low, int high, int mask)
3165 return (CONST_INT_P (op)
3166 && IN_RANGE (INTVAL (op), low, high)
3167 && (INTVAL (op) & mask) == 0);
3171 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3173 return m16_check_op (op, 0x1, 0x8, 0);
3177 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3179 return m16_check_op (op, -0x8, 0x7, 0);
3183 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3185 return m16_check_op (op, -0x7, 0x8, 0);
3189 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3191 return m16_check_op (op, -0x10, 0xf, 0);
3195 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3197 return m16_check_op (op, -0xf, 0x10, 0);
3201 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3203 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3207 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3209 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3213 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3215 return m16_check_op (op, -0x80, 0x7f, 0);
3219 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3221 return m16_check_op (op, -0x7f, 0x80, 0);
3225 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3227 return m16_check_op (op, 0x0, 0xff, 0);
3231 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3233 return m16_check_op (op, -0xff, 0x0, 0);
3237 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3239 return m16_check_op (op, -0x1, 0xfe, 0);
3243 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3245 return m16_check_op (op, 0x0, 0xff << 2, 3);
3249 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3251 return m16_check_op (op, -0xff << 2, 0x0, 3);
3255 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3257 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3261 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3263 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3266 /* The cost of loading values from the constant pool. It should be
3267 larger than the cost of any constant we want to synthesize inline. */
3268 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3270 /* Return the cost of X when used as an operand to the MIPS16 instruction
3271 that implements CODE. Return -1 if there is no such instruction, or if
3272 X is not a valid immediate operand for it. */
3275 mips16_constant_cost (int code, HOST_WIDE_INT x)
3282 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3283 other shifts are extended. The shift patterns truncate the shift
3284 count to the right size, so there are no out-of-range values. */
3285 if (IN_RANGE (x, 1, 8))
3287 return COSTS_N_INSNS (1);
3290 if (IN_RANGE (x, -128, 127))
3292 if (SMALL_OPERAND (x))
3293 return COSTS_N_INSNS (1);
3297 /* Like LE, but reject the always-true case. */
3301 /* We add 1 to the immediate and use SLT. */
3304 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3307 if (IN_RANGE (x, 0, 255))
3309 if (SMALL_OPERAND_UNSIGNED (x))
3310 return COSTS_N_INSNS (1);
3315 /* Equality comparisons with 0 are cheap. */
3325 /* Return true if there is a non-MIPS16 instruction that implements CODE
3326 and if that instruction accepts X as an immediate operand. */
3329 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3336 /* All shift counts are truncated to a valid constant. */
3341 /* Likewise rotates, if the target supports rotates at all. */
3347 /* These instructions take 16-bit unsigned immediates. */
3348 return SMALL_OPERAND_UNSIGNED (x);
3353 /* These instructions take 16-bit signed immediates. */
3354 return SMALL_OPERAND (x);
3360 /* The "immediate" forms of these instructions are really
3361 implemented as comparisons with register 0. */
3366 /* Likewise, meaning that the only valid immediate operand is 1. */
3370 /* We add 1 to the immediate and use SLT. */
3371 return SMALL_OPERAND (x + 1);
3374 /* Likewise SLTU, but reject the always-true case. */
3375 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3379 /* The bit position and size are immediate operands. */
3380 return ISA_HAS_EXT_INS;
3383 /* By default assume that $0 can be used for 0. */
3388 /* Return the cost of binary operation X, given that the instruction
3389 sequence for a word-sized or smaller operation has cost SINGLE_COST
3390 and that the sequence of a double-word operation has cost DOUBLE_COST.
3391 If SPEED is true, optimize for speed otherwise optimize for size. */
3394 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3398 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3403 + rtx_cost (XEXP (x, 0), SET, speed)
3404 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3407 /* Return the cost of floating-point multiplications of mode MODE. */
3410 mips_fp_mult_cost (enum machine_mode mode)
3412 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3415 /* Return the cost of floating-point divisions of mode MODE. */
3418 mips_fp_div_cost (enum machine_mode mode)
3420 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3423 /* Return the cost of sign-extending OP to mode MODE, not including the
3424 cost of OP itself. */
3427 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3430 /* Extended loads are as cheap as unextended ones. */
3433 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3434 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3437 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3438 /* We can use SEB or SEH. */
3439 return COSTS_N_INSNS (1);
3441 /* We need to use a shift left and a shift right. */
3442 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3445 /* Return the cost of zero-extending OP to mode MODE, not including the
3446 cost of OP itself. */
3449 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3452 /* Extended loads are as cheap as unextended ones. */
3455 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3456 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3457 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3459 if (GENERATE_MIPS16E)
3460 /* We can use ZEB or ZEH. */
3461 return COSTS_N_INSNS (1);
3464 /* We need to load 0xff or 0xffff into a register and use AND. */
3465 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3467 /* We can use ANDI. */
3468 return COSTS_N_INSNS (1);
3471 /* Implement TARGET_RTX_COSTS. */
3474 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3476 enum machine_mode mode = GET_MODE (x);
3477 bool float_mode_p = FLOAT_MODE_P (mode);
3481 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3482 appear in the instruction stream, and the cost of a comparison is
3483 really the cost of the branch or scc condition. At the time of
3484 writing, GCC only uses an explicit outer COMPARE code when optabs
3485 is testing whether a constant is expensive enough to force into a
3486 register. We want optabs to pass such constants through the MIPS
3487 expanders instead, so make all constants very cheap here. */
3488 if (outer_code == COMPARE)
3490 gcc_assert (CONSTANT_P (x));
3498 /* Treat *clear_upper32-style ANDs as having zero cost in the
3499 second operand. The cost is entirely in the first operand.
3501 ??? This is needed because we would otherwise try to CSE
3502 the constant operand. Although that's the right thing for
3503 instructions that continue to be a register operation throughout
3504 compilation, it is disastrous for instructions that could
3505 later be converted into a memory operation. */
3507 && outer_code == AND
3508 && UINTVAL (x) == 0xffffffff)
3516 cost = mips16_constant_cost (outer_code, INTVAL (x));
3525 /* When not optimizing for size, we care more about the cost
3526 of hot code, and hot code is often in a loop. If a constant
3527 operand needs to be forced into a register, we will often be
3528 able to hoist the constant load out of the loop, so the load
3529 should not contribute to the cost. */
3530 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3542 if (force_to_mem_operand (x, VOIDmode))
3544 *total = COSTS_N_INSNS (1);
3547 cost = mips_const_insns (x);
3550 /* If the constant is likely to be stored in a GPR, SETs of
3551 single-insn constants are as cheap as register sets; we
3552 never want to CSE them.
3554 Don't reduce the cost of storing a floating-point zero in
3555 FPRs. If we have a zero in an FPR for other reasons, we
3556 can get better cfg-cleanup and delayed-branch results by
3557 using it consistently, rather than using $0 sometimes and
3558 an FPR at other times. Also, moves between floating-point
3559 registers are sometimes cheaper than (D)MTC1 $0. */
3561 && outer_code == SET
3562 && !(float_mode_p && TARGET_HARD_FLOAT))
3564 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3565 want to CSE the constant itself. It is usually better to
3566 have N copies of the last operation in the sequence and one
3567 shared copy of the other operations. (Note that this is
3568 not true for MIPS16 code, where the final operation in the
3569 sequence is often an extended instruction.)
3571 Also, if we have a CONST_INT, we don't know whether it is
3572 for a word or doubleword operation, so we cannot rely on
3573 the result of mips_build_integer. */
3574 else if (!TARGET_MIPS16
3575 && (outer_code == SET || mode == VOIDmode))
3577 *total = COSTS_N_INSNS (cost);
3580 /* The value will need to be fetched from the constant pool. */
3581 *total = CONSTANT_POOL_COST;
3585 /* If the address is legitimate, return the number of
3586 instructions it needs. */
3588 cost = mips_address_insns (addr, mode, true);
3591 *total = COSTS_N_INSNS (cost + 1);
3594 /* Check for a scaled indexed address. */
3595 if (mips_lwxs_address_p (addr))
3597 *total = COSTS_N_INSNS (2);
3600 /* Otherwise use the default handling. */
3604 *total = COSTS_N_INSNS (6);
3608 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3612 /* Check for a *clear_upper32 pattern and treat it like a zero
3613 extension. See the pattern's comment for details. */
3616 && CONST_INT_P (XEXP (x, 1))
3617 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3619 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3620 + rtx_cost (XEXP (x, 0), SET, speed));
3627 /* Double-word operations use two single-word operations. */
3628 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3637 if (CONSTANT_P (XEXP (x, 1)))
3638 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3641 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3647 *total = mips_cost->fp_add;
3649 *total = COSTS_N_INSNS (4);
3653 /* Low-part immediates need an extended MIPS16 instruction. */
3654 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3655 + rtx_cost (XEXP (x, 0), SET, speed));
3670 /* Branch comparisons have VOIDmode, so use the first operand's
3672 mode = GET_MODE (XEXP (x, 0));
3673 if (FLOAT_MODE_P (mode))
3675 *total = mips_cost->fp_add;
3678 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3684 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3685 && TARGET_FUSED_MADD
3686 && !HONOR_NANS (mode)
3687 && !HONOR_SIGNED_ZEROS (mode))
3689 /* See if we can use NMADD or NMSUB. See mips.md for the
3690 associated patterns. */
3691 rtx op0 = XEXP (x, 0);
3692 rtx op1 = XEXP (x, 1);
3693 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3695 *total = (mips_fp_mult_cost (mode)
3696 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3697 + rtx_cost (XEXP (op0, 1), SET, speed)
3698 + rtx_cost (op1, SET, speed));
3701 if (GET_CODE (op1) == MULT)
3703 *total = (mips_fp_mult_cost (mode)
3704 + rtx_cost (op0, SET, speed)
3705 + rtx_cost (XEXP (op1, 0), SET, speed)
3706 + rtx_cost (XEXP (op1, 1), SET, speed));
3715 /* If this is part of a MADD or MSUB, treat the PLUS as
3718 && TARGET_FUSED_MADD
3719 && GET_CODE (XEXP (x, 0)) == MULT)
3722 *total = mips_cost->fp_add;
3726 /* Double-word operations require three single-word operations and
3727 an SLTU. The MIPS16 version then needs to move the result of
3728 the SLTU from $24 to a MIPS16 register. */
3729 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3730 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3736 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3737 && TARGET_FUSED_MADD
3738 && !HONOR_NANS (mode)
3739 && HONOR_SIGNED_ZEROS (mode))
3741 /* See if we can use NMADD or NMSUB. See mips.md for the
3742 associated patterns. */
3743 rtx op = XEXP (x, 0);
3744 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3745 && GET_CODE (XEXP (op, 0)) == MULT)
3747 *total = (mips_fp_mult_cost (mode)
3748 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3749 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3750 + rtx_cost (XEXP (op, 1), SET, speed));
3756 *total = mips_cost->fp_add;
3758 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3763 *total = mips_fp_mult_cost (mode);
3764 else if (mode == DImode && !TARGET_64BIT)
3765 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3766 where the mulsidi3 always includes an MFHI and an MFLO. */
3768 ? mips_cost->int_mult_si * 3 + 6
3769 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3771 *total = (ISA_HAS_MUL3 ? 1 : 2);
3772 else if (mode == DImode)
3773 *total = mips_cost->int_mult_di;
3775 *total = mips_cost->int_mult_si;
3779 /* Check for a reciprocal. */
3782 && flag_unsafe_math_optimizations
3783 && XEXP (x, 0) == CONST1_RTX (mode))
3785 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3786 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3787 division as being free. */
3788 *total = rtx_cost (XEXP (x, 1), SET, speed);
3790 *total = (mips_fp_div_cost (mode)
3791 + rtx_cost (XEXP (x, 1), SET, speed));
3800 *total = mips_fp_div_cost (mode);
3809 /* It is our responsibility to make division by a power of 2
3810 as cheap as 2 register additions if we want the division
3811 expanders to be used for such operations; see the setting
3812 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3813 should always produce shorter code than using
3814 expand_sdiv2_pow2. */
3816 && CONST_INT_P (XEXP (x, 1))
3817 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3819 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3822 *total = COSTS_N_INSNS (mips_idiv_insns ());
3824 else if (mode == DImode)
3825 *total = mips_cost->int_div_di;
3827 *total = mips_cost->int_div_si;
3831 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3835 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3839 case UNSIGNED_FLOAT:
3842 case FLOAT_TRUNCATE:
3843 *total = mips_cost->fp_add;
3851 /* Implement TARGET_ADDRESS_COST. */
3854 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3856 return mips_address_insns (addr, SImode, false);
3859 /* Information about a single instruction in a multi-instruction
3861 struct mips_multi_member {
3862 /* True if this is a label, false if it is code. */
3865 /* The output_asm_insn format of the instruction. */
3868 /* The operands to the instruction. */
3869 rtx operands[MAX_RECOG_OPERANDS];
3871 typedef struct mips_multi_member mips_multi_member;
3873 /* Vector definitions for the above. */
3874 DEF_VEC_O(mips_multi_member);
3875 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3877 /* The instructions that make up the current multi-insn sequence. */
3878 static VEC (mips_multi_member, heap) *mips_multi_members;
3880 /* How many instructions (as opposed to labels) are in the current
3881 multi-insn sequence. */
3882 static unsigned int mips_multi_num_insns;
3884 /* Start a new multi-insn sequence. */
3887 mips_multi_start (void)
3889 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3890 mips_multi_num_insns = 0;
3893 /* Add a new, uninitialized member to the current multi-insn sequence. */
3895 static struct mips_multi_member *
3896 mips_multi_add (void)
3898 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3901 /* Add a normal insn with the given asm format to the current multi-insn
3902 sequence. The other arguments are a null-terminated list of operands. */
3905 mips_multi_add_insn (const char *format, ...)
3907 struct mips_multi_member *member;
3912 member = mips_multi_add ();
3913 member->is_label_p = false;
3914 member->format = format;
3915 va_start (ap, format);
3917 while ((op = va_arg (ap, rtx)))
3918 member->operands[i++] = op;
3920 mips_multi_num_insns++;
3923 /* Add the given label definition to the current multi-insn sequence.
3924 The definition should include the colon. */
3927 mips_multi_add_label (const char *label)
3929 struct mips_multi_member *member;
3931 member = mips_multi_add ();
3932 member->is_label_p = true;
3933 member->format = label;
3936 /* Return the index of the last member of the current multi-insn sequence. */
3939 mips_multi_last_index (void)
3941 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3944 /* Add a copy of an existing instruction to the current multi-insn
3945 sequence. I is the index of the instruction that should be copied. */
3948 mips_multi_copy_insn (unsigned int i)
3950 struct mips_multi_member *member;
3952 member = mips_multi_add ();
3953 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3955 gcc_assert (!member->is_label_p);
3958 /* Change the operand of an existing instruction in the current
3959 multi-insn sequence. I is the index of the instruction,
3960 OP is the index of the operand, and X is the new value. */
3963 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3965 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3968 /* Write out the asm code for the current multi-insn sequence. */
3971 mips_multi_write (void)
3973 struct mips_multi_member *member;
3977 VEC_iterate (mips_multi_member, mips_multi_members, i, member);
3979 if (member->is_label_p)
3980 fprintf (asm_out_file, "%s\n", member->format);
3982 output_asm_insn (member->format, member->operands);
3985 /* Return one word of double-word value OP, taking into account the fixed
3986 endianness of certain registers. HIGH_P is true to select the high part,
3987 false to select the low part. */
3990 mips_subword (rtx op, bool high_p)
3992 unsigned int byte, offset;
3993 enum machine_mode mode;
3995 mode = GET_MODE (op);
3996 if (mode == VOIDmode)
3997 mode = TARGET_64BIT ? TImode : DImode;
3999 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4000 byte = UNITS_PER_WORD;
4004 if (FP_REG_RTX_P (op))
4006 /* Paired FPRs are always ordered little-endian. */
4007 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4008 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4012 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4014 return simplify_gen_subreg (word_mode, op, mode, byte);
4017 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4020 mips_split_64bit_move_p (rtx dest, rtx src)
4025 /* FPR-to-FPR moves can be done in a single instruction, if they're
4027 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4030 /* Check for floating-point loads and stores. */
4031 if (ISA_HAS_LDC1_SDC1)
4033 if (FP_REG_RTX_P (dest) && MEM_P (src))
4035 if (FP_REG_RTX_P (src) && MEM_P (dest))
4041 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4042 this function handles 64-bit moves for which mips_split_64bit_move_p
4043 holds. For 64-bit targets, this function handles 128-bit moves. */
4046 mips_split_doubleword_move (rtx dest, rtx src)
4050 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4052 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4053 emit_insn (gen_move_doubleword_fprdi (dest, src));
4054 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4055 emit_insn (gen_move_doubleword_fprdf (dest, src));
4056 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4057 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4058 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4059 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4060 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4061 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4062 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4063 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4064 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4065 emit_insn (gen_move_doubleword_fprtf (dest, src));
4069 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4071 low_dest = mips_subword (dest, false);
4072 mips_emit_move (low_dest, mips_subword (src, false));
4074 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4076 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4078 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4080 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4082 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4084 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4088 /* The operation can be split into two normal moves. Decide in
4089 which order to do them. */
4090 low_dest = mips_subword (dest, false);
4091 if (REG_P (low_dest)
4092 && reg_overlap_mentioned_p (low_dest, src))
4094 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4095 mips_emit_move (low_dest, mips_subword (src, false));
4099 mips_emit_move (low_dest, mips_subword (src, false));
4100 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4105 /* Return the appropriate instructions to move SRC into DEST. Assume
4106 that SRC is operand 1 and DEST is operand 0. */
4109 mips_output_move (rtx dest, rtx src)
4111 enum rtx_code dest_code, src_code;
4112 enum machine_mode mode;
4113 enum mips_symbol_type symbol_type;
4116 dest_code = GET_CODE (dest);
4117 src_code = GET_CODE (src);
4118 mode = GET_MODE (dest);
4119 dbl_p = (GET_MODE_SIZE (mode) == 8);
4121 if (dbl_p && mips_split_64bit_move_p (dest, src))
4124 if ((src_code == REG && GP_REG_P (REGNO (src)))
4125 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4127 if (dest_code == REG)
4129 if (GP_REG_P (REGNO (dest)))
4130 return "move\t%0,%z1";
4132 /* Moves to HI are handled by special .md insns. */
4133 if (REGNO (dest) == LO_REGNUM)
4136 if (DSP_ACC_REG_P (REGNO (dest)))
4138 static char retval[] = "mt__\t%z1,%q0";
4140 retval[2] = reg_names[REGNO (dest)][4];
4141 retval[3] = reg_names[REGNO (dest)][5];
4145 if (FP_REG_P (REGNO (dest)))
4146 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4148 if (ALL_COP_REG_P (REGNO (dest)))
4150 static char retval[] = "dmtc_\t%z1,%0";
4152 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4153 return dbl_p ? retval : retval + 1;
4156 if (dest_code == MEM)
4157 switch (GET_MODE_SIZE (mode))
4159 case 1: return "sb\t%z1,%0";
4160 case 2: return "sh\t%z1,%0";
4161 case 4: return "sw\t%z1,%0";
4162 case 8: return "sd\t%z1,%0";
4165 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4167 if (src_code == REG)
4169 /* Moves from HI are handled by special .md insns. */
4170 if (REGNO (src) == LO_REGNUM)
4172 /* When generating VR4120 or VR4130 code, we use MACC and
4173 DMACC instead of MFLO. This avoids both the normal
4174 MIPS III HI/LO hazards and the errata related to
4177 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4181 if (DSP_ACC_REG_P (REGNO (src)))
4183 static char retval[] = "mf__\t%0,%q1";
4185 retval[2] = reg_names[REGNO (src)][4];
4186 retval[3] = reg_names[REGNO (src)][5];
4190 if (FP_REG_P (REGNO (src)))
4191 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4193 if (ALL_COP_REG_P (REGNO (src)))
4195 static char retval[] = "dmfc_\t%0,%1";
4197 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4198 return dbl_p ? retval : retval + 1;
4201 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4202 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4205 if (src_code == MEM)
4206 switch (GET_MODE_SIZE (mode))
4208 case 1: return "lbu\t%0,%1";
4209 case 2: return "lhu\t%0,%1";
4210 case 4: return "lw\t%0,%1";
4211 case 8: return "ld\t%0,%1";
4214 if (src_code == CONST_INT)
4216 /* Don't use the X format for the operand itself, because that
4217 will give out-of-range numbers for 64-bit hosts and 32-bit
4220 return "li\t%0,%1\t\t\t# %X1";
4222 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4225 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4229 if (src_code == HIGH)
4230 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4232 if (CONST_GP_P (src))
4233 return "move\t%0,%1";
4235 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4236 && mips_lo_relocs[symbol_type] != 0)
4238 /* A signed 16-bit constant formed by applying a relocation
4239 operator to a symbolic address. */
4240 gcc_assert (!mips_split_p[symbol_type]);
4241 return "li\t%0,%R1";
4244 if (symbolic_operand (src, VOIDmode))
4246 gcc_assert (TARGET_MIPS16
4247 ? TARGET_MIPS16_TEXT_LOADS
4248 : !TARGET_EXPLICIT_RELOCS);
4249 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4252 if (src_code == REG && FP_REG_P (REGNO (src)))
4254 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4256 if (GET_MODE (dest) == V2SFmode)
4257 return "mov.ps\t%0,%1";
4259 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4262 if (dest_code == MEM)
4263 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4265 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4267 if (src_code == MEM)
4268 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4270 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4272 static char retval[] = "l_c_\t%0,%1";
4274 retval[1] = (dbl_p ? 'd' : 'w');
4275 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4278 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4280 static char retval[] = "s_c_\t%1,%0";
4282 retval[1] = (dbl_p ? 'd' : 'w');
4283 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4289 /* Return true if CMP1 is a suitable second operand for integer ordering
4290 test CODE. See also the *sCC patterns in mips.md. */
4293 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4299 return reg_or_0_operand (cmp1, VOIDmode);
4303 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4307 return arith_operand (cmp1, VOIDmode);
4310 return sle_operand (cmp1, VOIDmode);
4313 return sleu_operand (cmp1, VOIDmode);
4320 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4321 integer ordering test *CODE, or if an equivalent combination can
4322 be formed by adjusting *CODE and *CMP1. When returning true, update
4323 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4327 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4328 enum machine_mode mode)
4330 HOST_WIDE_INT plus_one;
4332 if (mips_int_order_operand_ok_p (*code, *cmp1))
4335 if (CONST_INT_P (*cmp1))
4339 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4340 if (INTVAL (*cmp1) < plus_one)
4343 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4349 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4353 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4364 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4365 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4366 is nonnull, it's OK to set TARGET to the inverse of the result and
4367 flip *INVERT_PTR instead. */
4370 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4371 rtx target, rtx cmp0, rtx cmp1)
4373 enum machine_mode mode;
4375 /* First see if there is a MIPS instruction that can do this operation.
4376 If not, try doing the same for the inverse operation. If that also
4377 fails, force CMP1 into a register and try again. */
4378 mode = GET_MODE (cmp0);
4379 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4380 mips_emit_binary (code, target, cmp0, cmp1);
4383 enum rtx_code inv_code = reverse_condition (code);
4384 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4386 cmp1 = force_reg (mode, cmp1);
4387 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4389 else if (invert_ptr == 0)
4393 inv_target = mips_force_binary (GET_MODE (target),
4394 inv_code, cmp0, cmp1);
4395 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4399 *invert_ptr = !*invert_ptr;
4400 mips_emit_binary (inv_code, target, cmp0, cmp1);
4405 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4406 The register will have the same mode as CMP0. */
4409 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4411 if (cmp1 == const0_rtx)
4414 if (uns_arith_operand (cmp1, VOIDmode))
4415 return expand_binop (GET_MODE (cmp0), xor_optab,
4416 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4418 return expand_binop (GET_MODE (cmp0), sub_optab,
4419 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4422 /* Convert *CODE into a code that can be used in a floating-point
4423 scc instruction (C.cond.fmt). Return true if the values of
4424 the condition code registers will be inverted, with 0 indicating
4425 that the condition holds. */
4428 mips_reversed_fp_cond (enum rtx_code *code)
4435 *code = reverse_condition_maybe_unordered (*code);
4443 /* Convert a comparison into something that can be used in a branch or
4444 conditional move. On entry, *OP0 and *OP1 are the values being
4445 compared and *CODE is the code used to compare them.
4447 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4448 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4449 otherwise any standard branch condition can be used. The standard branch
4452 - EQ or NE between two registers.
4453 - any comparison between a register and zero. */
4456 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4461 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4463 if (!need_eq_ne_p && *op1 == const0_rtx)
4465 else if (*code == EQ || *code == NE)
4469 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4473 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4477 /* The comparison needs a separate scc instruction. Store the
4478 result of the scc in *OP0 and compare it against zero. */
4479 bool invert = false;
4480 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4481 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4482 *code = (invert ? EQ : NE);
4486 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4488 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4489 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4495 enum rtx_code cmp_code;
4497 /* Floating-point tests use a separate C.cond.fmt comparison to
4498 set a condition code register. The branch or conditional move
4499 will then compare that register against zero.
4501 Set CMP_CODE to the code of the comparison instruction and
4502 *CODE to the code that the branch or move should use. */
4504 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4506 ? gen_reg_rtx (CCmode)
4507 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4509 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4513 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4514 and OPERAND[3]. Store the result in OPERANDS[0].
4516 On 64-bit targets, the mode of the comparison and target will always be
4517 SImode, thus possibly narrower than that of the comparison's operands. */
4520 mips_expand_scc (rtx operands[])
4522 rtx target = operands[0];
4523 enum rtx_code code = GET_CODE (operands[1]);
4524 rtx op0 = operands[2];
4525 rtx op1 = operands[3];
4527 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4529 if (code == EQ || code == NE)
4532 && reg_imm10_operand (op1, GET_MODE (op1)))
4533 mips_emit_binary (code, target, op0, op1);
4536 rtx zie = mips_zero_if_equal (op0, op1);
4537 mips_emit_binary (code, target, zie, const0_rtx);
4541 mips_emit_int_order_test (code, 0, target, op0, op1);
4544 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4545 CODE and jump to OPERANDS[3] if the condition holds. */
4548 mips_expand_conditional_branch (rtx *operands)
4550 enum rtx_code code = GET_CODE (operands[0]);
4551 rtx op0 = operands[1];
4552 rtx op1 = operands[2];
4555 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4556 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4557 emit_jump_insn (gen_condjump (condition, operands[3]));
4562 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4563 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4566 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4567 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4572 reversed_p = mips_reversed_fp_cond (&cond);
4573 cmp_result = gen_reg_rtx (CCV2mode);
4574 emit_insn (gen_scc_ps (cmp_result,
4575 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4577 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4580 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4584 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4585 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4588 mips_expand_conditional_move (rtx *operands)
4591 enum rtx_code code = GET_CODE (operands[1]);
4592 rtx op0 = XEXP (operands[1], 0);
4593 rtx op1 = XEXP (operands[1], 1);
4595 mips_emit_compare (&code, &op0, &op1, true);
4596 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4597 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4598 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4599 operands[2], operands[3])));
4602 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4605 mips_expand_conditional_trap (rtx comparison)
4608 enum machine_mode mode;
4611 /* MIPS conditional trap instructions don't have GT or LE flavors,
4612 so we must swap the operands and convert to LT and GE respectively. */
4613 code = GET_CODE (comparison);
4620 code = swap_condition (code);
4621 op0 = XEXP (comparison, 1);
4622 op1 = XEXP (comparison, 0);
4626 op0 = XEXP (comparison, 0);
4627 op1 = XEXP (comparison, 1);
4631 mode = GET_MODE (XEXP (comparison, 0));
4632 op0 = force_reg (mode, op0);
4633 if (!arith_operand (op1, mode))
4634 op1 = force_reg (mode, op1);
4636 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4637 gen_rtx_fmt_ee (code, mode, op0, op1),
4641 /* Initialize *CUM for a call to a function of type FNTYPE. */
4644 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4646 memset (cum, 0, sizeof (*cum));
4647 cum->prototype = (fntype && prototype_p (fntype));
4648 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4651 /* Fill INFO with information about a single argument. CUM is the
4652 cumulative state for earlier arguments. MODE is the mode of this
4653 argument and TYPE is its type (if known). NAMED is true if this
4654 is a named (fixed) argument rather than a variable one. */
4657 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4658 enum machine_mode mode, tree type, int named)
4660 bool doubleword_aligned_p;
4661 unsigned int num_bytes, num_words, max_regs;
4663 /* Work out the size of the argument. */
4664 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4665 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4667 /* Decide whether it should go in a floating-point register, assuming
4668 one is free. Later code checks for availability.
4670 The checks against UNITS_PER_FPVALUE handle the soft-float and
4671 single-float cases. */
4675 /* The EABI conventions have traditionally been defined in terms
4676 of TYPE_MODE, regardless of the actual type. */
4677 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4678 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4679 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4684 /* Only leading floating-point scalars are passed in
4685 floating-point registers. We also handle vector floats the same
4686 say, which is OK because they are not covered by the standard ABI. */
4687 info->fpr_p = (!cum->gp_reg_found
4688 && cum->arg_number < 2
4690 || SCALAR_FLOAT_TYPE_P (type)
4691 || VECTOR_FLOAT_TYPE_P (type))
4692 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4693 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4694 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4699 /* Scalar, complex and vector floating-point types are passed in
4700 floating-point registers, as long as this is a named rather
4701 than a variable argument. */
4702 info->fpr_p = (named
4703 && (type == 0 || FLOAT_TYPE_P (type))
4704 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4705 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4706 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4707 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4709 /* ??? According to the ABI documentation, the real and imaginary
4710 parts of complex floats should be passed in individual registers.
4711 The real and imaginary parts of stack arguments are supposed
4712 to be contiguous and there should be an extra word of padding
4715 This has two problems. First, it makes it impossible to use a
4716 single "void *" va_list type, since register and stack arguments
4717 are passed differently. (At the time of writing, MIPSpro cannot
4718 handle complex float varargs correctly.) Second, it's unclear
4719 what should happen when there is only one register free.
4721 For now, we assume that named complex floats should go into FPRs
4722 if there are two FPRs free, otherwise they should be passed in the
4723 same way as a struct containing two floats. */
4725 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4726 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4728 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4729 info->fpr_p = false;
4739 /* See whether the argument has doubleword alignment. */
4740 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4742 /* Set REG_OFFSET to the register count we're interested in.
4743 The EABI allocates the floating-point registers separately,
4744 but the other ABIs allocate them like integer registers. */
4745 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4749 /* Advance to an even register if the argument is doubleword-aligned. */
4750 if (doubleword_aligned_p)
4751 info->reg_offset += info->reg_offset & 1;
4753 /* Work out the offset of a stack argument. */
4754 info->stack_offset = cum->stack_words;
4755 if (doubleword_aligned_p)
4756 info->stack_offset += info->stack_offset & 1;
4758 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4760 /* Partition the argument between registers and stack. */
4761 info->reg_words = MIN (num_words, max_regs);
4762 info->stack_words = num_words - info->reg_words;
4765 /* INFO describes a register argument that has the normal format for the
4766 argument's mode. Return the register it uses, assuming that FPRs are
4767 available if HARD_FLOAT_P. */
4770 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4772 if (!info->fpr_p || !hard_float_p)
4773 return GP_ARG_FIRST + info->reg_offset;
4774 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4775 /* In o32, the second argument is always passed in $f14
4776 for TARGET_DOUBLE_FLOAT, regardless of whether the
4777 first argument was a word or doubleword. */
4778 return FP_ARG_FIRST + 2;
4780 return FP_ARG_FIRST + info->reg_offset;
4783 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4786 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4788 return !TARGET_OLDABI;
4791 /* Implement FUNCTION_ARG. */
4794 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4795 tree type, int named)
4797 struct mips_arg_info info;
4799 /* We will be called with a mode of VOIDmode after the last argument
4800 has been seen. Whatever we return will be passed to the call expander.
4801 If we need a MIPS16 fp_code, return a REG with the code stored as
4803 if (mode == VOIDmode)
4805 if (TARGET_MIPS16 && cum->fp_code != 0)
4806 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4811 mips_get_arg_info (&info, cum, mode, type, named);
4813 /* Return straight away if the whole argument is passed on the stack. */
4814 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4817 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4818 contains a double in its entirety, then that 64-bit chunk is passed
4819 in a floating-point register. */
4821 && TARGET_HARD_FLOAT
4824 && TREE_CODE (type) == RECORD_TYPE
4825 && TYPE_SIZE_UNIT (type)
4826 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4830 /* First check to see if there is any such field. */
4831 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4832 if (TREE_CODE (field) == FIELD_DECL
4833 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4834 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4835 && host_integerp (bit_position (field), 0)
4836 && int_bit_position (field) % BITS_PER_WORD == 0)
4841 /* Now handle the special case by returning a PARALLEL
4842 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4843 chunks are passed in registers. */
4845 HOST_WIDE_INT bitpos;
4848 /* assign_parms checks the mode of ENTRY_PARM, so we must
4849 use the actual mode here. */
4850 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4853 field = TYPE_FIELDS (type);
4854 for (i = 0; i < info.reg_words; i++)
4858 for (; field; field = TREE_CHAIN (field))
4859 if (TREE_CODE (field) == FIELD_DECL
4860 && int_bit_position (field) >= bitpos)
4864 && int_bit_position (field) == bitpos
4865 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4866 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4867 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4869 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4872 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4873 GEN_INT (bitpos / BITS_PER_UNIT));
4875 bitpos += BITS_PER_WORD;
4881 /* Handle the n32/n64 conventions for passing complex floating-point
4882 arguments in FPR pairs. The real part goes in the lower register
4883 and the imaginary part goes in the upper register. */
4886 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4889 enum machine_mode inner;
4892 inner = GET_MODE_INNER (mode);
4893 regno = FP_ARG_FIRST + info.reg_offset;
4894 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4896 /* Real part in registers, imaginary part on stack. */
4897 gcc_assert (info.stack_words == info.reg_words);
4898 return gen_rtx_REG (inner, regno);
4902 gcc_assert (info.stack_words == 0);
4903 real = gen_rtx_EXPR_LIST (VOIDmode,
4904 gen_rtx_REG (inner, regno),
4906 imag = gen_rtx_EXPR_LIST (VOIDmode,
4908 regno + info.reg_words / 2),
4909 GEN_INT (GET_MODE_SIZE (inner)));
4910 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4914 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4917 /* Implement FUNCTION_ARG_ADVANCE. */
4920 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4921 tree type, int named)
4923 struct mips_arg_info info;
4925 mips_get_arg_info (&info, cum, mode, type, named);
4928 cum->gp_reg_found = true;
4930 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4931 an explanation of what this code does. It assumes that we're using
4932 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4934 if (cum->arg_number < 2 && info.fpr_p)
4935 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4937 /* Advance the register count. This has the effect of setting
4938 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4939 argument required us to skip the final GPR and pass the whole
4940 argument on the stack. */
4941 if (mips_abi != ABI_EABI || !info.fpr_p)
4942 cum->num_gprs = info.reg_offset + info.reg_words;
4943 else if (info.reg_words > 0)
4944 cum->num_fprs += MAX_FPRS_PER_FMT;
4946 /* Advance the stack word count. */
4947 if (info.stack_words > 0)
4948 cum->stack_words = info.stack_offset + info.stack_words;
4953 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4956 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4957 enum machine_mode mode, tree type, bool named)
4959 struct mips_arg_info info;
4961 mips_get_arg_info (&info, cum, mode, type, named);
4962 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4965 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4966 PARM_BOUNDARY bits of alignment, but will be given anything up
4967 to STACK_BOUNDARY bits if the type requires it. */
4970 mips_function_arg_boundary (enum machine_mode mode, tree type)
4972 unsigned int alignment;
4974 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4975 if (alignment < PARM_BOUNDARY)
4976 alignment = PARM_BOUNDARY;
4977 if (alignment > STACK_BOUNDARY)
4978 alignment = STACK_BOUNDARY;
4982 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4983 upward rather than downward. In other words, return true if the
4984 first byte of the stack slot has useful data, false if the last
4988 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4990 /* On little-endian targets, the first byte of every stack argument
4991 is passed in the first byte of the stack slot. */
4992 if (!BYTES_BIG_ENDIAN)
4995 /* Otherwise, integral types are padded downward: the last byte of a
4996 stack argument is passed in the last byte of the stack slot. */
4998 ? (INTEGRAL_TYPE_P (type)
4999 || POINTER_TYPE_P (type)
5000 || FIXED_POINT_TYPE_P (type))
5001 : (SCALAR_INT_MODE_P (mode)
5002 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5005 /* Big-endian o64 pads floating-point arguments downward. */
5006 if (mips_abi == ABI_O64)
5007 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5010 /* Other types are padded upward for o32, o64, n32 and n64. */
5011 if (mips_abi != ABI_EABI)
5014 /* Arguments smaller than a stack slot are padded downward. */
5015 if (mode != BLKmode)
5016 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5018 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5021 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5022 if the least significant byte of the register has useful data. Return
5023 the opposite if the most significant byte does. */
5026 mips_pad_reg_upward (enum machine_mode mode, tree type)
5028 /* No shifting is required for floating-point arguments. */
5029 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5030 return !BYTES_BIG_ENDIAN;
5032 /* Otherwise, apply the same padding to register arguments as we do
5033 to stack arguments. */
5034 return mips_pad_arg_upward (mode, type);
5037 /* Return nonzero when an argument must be passed by reference. */
5040 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5041 enum machine_mode mode, const_tree type,
5042 bool named ATTRIBUTE_UNUSED)
5044 if (mips_abi == ABI_EABI)
5048 /* ??? How should SCmode be handled? */
5049 if (mode == DImode || mode == DFmode
5050 || mode == DQmode || mode == UDQmode
5051 || mode == DAmode || mode == UDAmode)
5054 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5055 return size == -1 || size > UNITS_PER_WORD;
5059 /* If we have a variable-sized parameter, we have no choice. */
5060 return targetm.calls.must_pass_in_stack (mode, type);
5064 /* Implement TARGET_CALLEE_COPIES. */
5067 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5068 enum machine_mode mode ATTRIBUTE_UNUSED,
5069 const_tree type ATTRIBUTE_UNUSED, bool named)
5071 return mips_abi == ABI_EABI && named;
5074 /* See whether VALTYPE is a record whose fields should be returned in
5075 floating-point registers. If so, return the number of fields and
5076 list them in FIELDS (which should have two elements). Return 0
5079 For n32 & n64, a structure with one or two fields is returned in
5080 floating-point registers as long as every field has a floating-point
5084 mips_fpr_return_fields (const_tree valtype, tree *fields)
5092 if (TREE_CODE (valtype) != RECORD_TYPE)
5096 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
5098 if (TREE_CODE (field) != FIELD_DECL)
5101 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5107 fields[i++] = field;
5112 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5113 a value in the most significant part of $2/$3 if:
5115 - the target is big-endian;
5117 - the value has a structure or union type (we generalize this to
5118 cover aggregates from other languages too); and
5120 - the structure is not returned in floating-point registers. */
5123 mips_return_in_msb (const_tree valtype)
5127 return (TARGET_NEWABI
5128 && TARGET_BIG_ENDIAN
5129 && AGGREGATE_TYPE_P (valtype)
5130 && mips_fpr_return_fields (valtype, fields) == 0);
5133 /* Return true if the function return value MODE will get returned in a
5134 floating-point register. */
5137 mips_return_mode_in_fpr_p (enum machine_mode mode)
5139 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5140 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5141 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5142 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5145 /* Return the representation of an FPR return register when the
5146 value being returned in FP_RETURN has mode VALUE_MODE and the
5147 return type itself has mode TYPE_MODE. On NewABI targets,
5148 the two modes may be different for structures like:
5150 struct __attribute__((packed)) foo { float f; }
5152 where we return the SFmode value of "f" in FP_RETURN, but where
5153 the structure itself has mode BLKmode. */
5156 mips_return_fpr_single (enum machine_mode type_mode,
5157 enum machine_mode value_mode)
5161 x = gen_rtx_REG (value_mode, FP_RETURN);
5162 if (type_mode != value_mode)
5164 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5165 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5170 /* Return a composite value in a pair of floating-point registers.
5171 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5172 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5175 For n32 & n64, $f0 always holds the first value and $f2 the second.
5176 Otherwise the values are packed together as closely as possible. */
5179 mips_return_fpr_pair (enum machine_mode mode,
5180 enum machine_mode mode1, HOST_WIDE_INT offset1,
5181 enum machine_mode mode2, HOST_WIDE_INT offset2)
5185 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5186 return gen_rtx_PARALLEL
5189 gen_rtx_EXPR_LIST (VOIDmode,
5190 gen_rtx_REG (mode1, FP_RETURN),
5192 gen_rtx_EXPR_LIST (VOIDmode,
5193 gen_rtx_REG (mode2, FP_RETURN + inc),
5194 GEN_INT (offset2))));
5198 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5199 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5200 VALTYPE is null and MODE is the mode of the return value. */
5203 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5210 mode = TYPE_MODE (valtype);
5211 unsigned_p = TYPE_UNSIGNED (valtype);
5213 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5214 return values, promote the mode here too. */
5215 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5217 /* Handle structures whose fields are returned in $f0/$f2. */
5218 switch (mips_fpr_return_fields (valtype, fields))
5221 return mips_return_fpr_single (mode,
5222 TYPE_MODE (TREE_TYPE (fields[0])));
5225 return mips_return_fpr_pair (mode,
5226 TYPE_MODE (TREE_TYPE (fields[0])),
5227 int_byte_position (fields[0]),
5228 TYPE_MODE (TREE_TYPE (fields[1])),
5229 int_byte_position (fields[1]));
5232 /* If a value is passed in the most significant part of a register, see
5233 whether we have to round the mode up to a whole number of words. */
5234 if (mips_return_in_msb (valtype))
5236 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5237 if (size % UNITS_PER_WORD != 0)
5239 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5240 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5244 /* For EABI, the class of return register depends entirely on MODE.
5245 For example, "struct { some_type x; }" and "union { some_type x; }"
5246 are returned in the same way as a bare "some_type" would be.
5247 Other ABIs only use FPRs for scalar, complex or vector types. */
5248 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5249 return gen_rtx_REG (mode, GP_RETURN);
5254 /* Handle long doubles for n32 & n64. */
5256 return mips_return_fpr_pair (mode,
5258 DImode, GET_MODE_SIZE (mode) / 2);
5260 if (mips_return_mode_in_fpr_p (mode))
5262 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5263 return mips_return_fpr_pair (mode,
5264 GET_MODE_INNER (mode), 0,
5265 GET_MODE_INNER (mode),
5266 GET_MODE_SIZE (mode) / 2);
5268 return gen_rtx_REG (mode, FP_RETURN);
5272 return gen_rtx_REG (mode, GP_RETURN);
5275 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5276 all BLKmode objects are returned in memory. Under the n32, n64
5277 and embedded ABIs, small structures are returned in a register.
5278 Objects with varying size must still be returned in memory, of
5282 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5284 return (TARGET_OLDABI
5285 ? TYPE_MODE (type) == BLKmode
5286 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5289 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5292 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5293 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5296 CUMULATIVE_ARGS local_cum;
5297 int gp_saved, fp_saved;
5299 /* The caller has advanced CUM up to, but not beyond, the last named
5300 argument. Advance a local copy of CUM past the last "real" named
5301 argument, to find out how many registers are left over. */
5303 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5305 /* Found out how many registers we need to save. */
5306 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5307 fp_saved = (EABI_FLOAT_VARARGS_P
5308 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5317 ptr = plus_constant (virtual_incoming_args_rtx,
5318 REG_PARM_STACK_SPACE (cfun->decl)
5319 - gp_saved * UNITS_PER_WORD);
5320 mem = gen_frame_mem (BLKmode, ptr);
5321 set_mem_alias_set (mem, get_varargs_alias_set ());
5323 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5328 /* We can't use move_block_from_reg, because it will use
5330 enum machine_mode mode;
5333 /* Set OFF to the offset from virtual_incoming_args_rtx of
5334 the first float register. The FP save area lies below
5335 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5336 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5337 off -= fp_saved * UNITS_PER_FPREG;
5339 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5341 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5342 i += MAX_FPRS_PER_FMT)
5346 ptr = plus_constant (virtual_incoming_args_rtx, off);
5347 mem = gen_frame_mem (mode, ptr);
5348 set_mem_alias_set (mem, get_varargs_alias_set ());
5349 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5350 off += UNITS_PER_HWFPVALUE;
5354 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5355 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5356 + fp_saved * UNITS_PER_FPREG);
5359 /* Implement TARGET_BUILTIN_VA_LIST. */
5362 mips_build_builtin_va_list (void)
5364 if (EABI_FLOAT_VARARGS_P)
5366 /* We keep 3 pointers, and two offsets.
5368 Two pointers are to the overflow area, which starts at the CFA.
5369 One of these is constant, for addressing into the GPR save area
5370 below it. The other is advanced up the stack through the
5373 The third pointer is to the bottom of the GPR save area.
5374 Since the FPR save area is just below it, we can address
5375 FPR slots off this pointer.
5377 We also keep two one-byte offsets, which are to be subtracted
5378 from the constant pointers to yield addresses in the GPR and
5379 FPR save areas. These are downcounted as float or non-float
5380 arguments are used, and when they get to zero, the argument
5381 must be obtained from the overflow region. */
5382 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5385 record = lang_hooks.types.make_type (RECORD_TYPE);
5387 f_ovfl = build_decl (BUILTINS_LOCATION,
5388 FIELD_DECL, get_identifier ("__overflow_argptr"),
5390 f_gtop = build_decl (BUILTINS_LOCATION,
5391 FIELD_DECL, get_identifier ("__gpr_top"),
5393 f_ftop = build_decl (BUILTINS_LOCATION,
5394 FIELD_DECL, get_identifier ("__fpr_top"),
5396 f_goff = build_decl (BUILTINS_LOCATION,
5397 FIELD_DECL, get_identifier ("__gpr_offset"),
5398 unsigned_char_type_node);
5399 f_foff = build_decl (BUILTINS_LOCATION,
5400 FIELD_DECL, get_identifier ("__fpr_offset"),
5401 unsigned_char_type_node);
5402 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5403 warn on every user file. */
5404 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5405 array = build_array_type (unsigned_char_type_node,
5406 build_index_type (index));
5407 f_res = build_decl (BUILTINS_LOCATION,
5408 FIELD_DECL, get_identifier ("__reserved"), array);
5410 DECL_FIELD_CONTEXT (f_ovfl) = record;
5411 DECL_FIELD_CONTEXT (f_gtop) = record;
5412 DECL_FIELD_CONTEXT (f_ftop) = record;
5413 DECL_FIELD_CONTEXT (f_goff) = record;
5414 DECL_FIELD_CONTEXT (f_foff) = record;
5415 DECL_FIELD_CONTEXT (f_res) = record;
5417 TYPE_FIELDS (record) = f_ovfl;
5418 TREE_CHAIN (f_ovfl) = f_gtop;
5419 TREE_CHAIN (f_gtop) = f_ftop;
5420 TREE_CHAIN (f_ftop) = f_goff;
5421 TREE_CHAIN (f_goff) = f_foff;
5422 TREE_CHAIN (f_foff) = f_res;
5424 layout_type (record);
5427 else if (TARGET_IRIX && TARGET_IRIX6)
5428 /* On IRIX 6, this type is 'char *'. */
5429 return build_pointer_type (char_type_node);
5431 /* Otherwise, we use 'void *'. */
5432 return ptr_type_node;
5435 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5438 mips_va_start (tree valist, rtx nextarg)
5440 if (EABI_FLOAT_VARARGS_P)
5442 const CUMULATIVE_ARGS *cum;
5443 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5444 tree ovfl, gtop, ftop, goff, foff;
5446 int gpr_save_area_size;
5447 int fpr_save_area_size;
5450 cum = &crtl->args.info;
5452 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5454 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5456 f_ovfl = TYPE_FIELDS (va_list_type_node);
5457 f_gtop = TREE_CHAIN (f_ovfl);
5458 f_ftop = TREE_CHAIN (f_gtop);
5459 f_goff = TREE_CHAIN (f_ftop);
5460 f_foff = TREE_CHAIN (f_goff);
5462 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5464 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5466 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5468 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5470 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5473 /* Emit code to initialize OVFL, which points to the next varargs
5474 stack argument. CUM->STACK_WORDS gives the number of stack
5475 words used by named arguments. */
5476 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5477 if (cum->stack_words > 0)
5478 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5479 size_int (cum->stack_words * UNITS_PER_WORD));
5480 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5481 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5483 /* Emit code to initialize GTOP, the top of the GPR save area. */
5484 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5485 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5486 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5488 /* Emit code to initialize FTOP, the top of the FPR save area.
5489 This address is gpr_save_area_bytes below GTOP, rounded
5490 down to the next fp-aligned boundary. */
5491 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5492 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5493 fpr_offset &= -UNITS_PER_FPVALUE;
5495 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5496 size_int (-fpr_offset));
5497 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5498 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5500 /* Emit code to initialize GOFF, the offset from GTOP of the
5501 next GPR argument. */
5502 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5503 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5504 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5506 /* Likewise emit code to initialize FOFF, the offset from FTOP
5507 of the next FPR argument. */
5508 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5509 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5510 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5514 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5515 std_expand_builtin_va_start (valist, nextarg);
5519 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5522 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5528 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5530 type = build_pointer_type (type);
5532 if (!EABI_FLOAT_VARARGS_P)
5533 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5536 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5537 tree ovfl, top, off, align;
5538 HOST_WIDE_INT size, rsize, osize;
5541 f_ovfl = TYPE_FIELDS (va_list_type_node);
5542 f_gtop = TREE_CHAIN (f_ovfl);
5543 f_ftop = TREE_CHAIN (f_gtop);
5544 f_goff = TREE_CHAIN (f_ftop);
5545 f_foff = TREE_CHAIN (f_goff);
5549 TOP be the top of the GPR or FPR save area;
5550 OFF be the offset from TOP of the next register;
5551 ADDR_RTX be the address of the argument;
5552 SIZE be the number of bytes in the argument type;
5553 RSIZE be the number of bytes used to store the argument
5554 when it's in the register save area; and
5555 OSIZE be the number of bytes used to store it when it's
5556 in the stack overflow area.
5558 The code we want is:
5560 1: off &= -rsize; // round down
5563 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5568 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5569 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5573 [1] and [9] can sometimes be optimized away. */
5575 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5577 size = int_size_in_bytes (type);
5579 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5580 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5582 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5583 unshare_expr (valist), f_ftop, NULL_TREE);
5584 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5585 unshare_expr (valist), f_foff, NULL_TREE);
5587 /* When va_start saves FPR arguments to the stack, each slot
5588 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5589 argument's precision. */
5590 rsize = UNITS_PER_HWFPVALUE;
5592 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5593 (= PARM_BOUNDARY bits). This can be different from RSIZE
5596 (1) On 32-bit targets when TYPE is a structure such as:
5598 struct s { float f; };
5600 Such structures are passed in paired FPRs, so RSIZE
5601 will be 8 bytes. However, the structure only takes
5602 up 4 bytes of memory, so OSIZE will only be 4.
5604 (2) In combinations such as -mgp64 -msingle-float
5605 -fshort-double. Doubles passed in registers will then take
5606 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5607 stack take up UNITS_PER_WORD bytes. */
5608 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5612 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5613 unshare_expr (valist), f_gtop, NULL_TREE);
5614 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5615 unshare_expr (valist), f_goff, NULL_TREE);
5616 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5617 if (rsize > UNITS_PER_WORD)
5619 /* [1] Emit code for: off &= -rsize. */
5620 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5621 build_int_cst (TREE_TYPE (off), -rsize));
5622 gimplify_assign (unshare_expr (off), t, pre_p);
5627 /* [2] Emit code to branch if off == 0. */
5628 t = build2 (NE_EXPR, boolean_type_node, off,
5629 build_int_cst (TREE_TYPE (off), 0));
5630 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5632 /* [5] Emit code for: off -= rsize. We do this as a form of
5633 post-decrement not available to C. */
5634 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5635 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5637 /* [4] Emit code for:
5638 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5639 t = fold_convert (sizetype, t);
5640 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5641 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5642 if (BYTES_BIG_ENDIAN && rsize > size)
5644 u = size_int (rsize - size);
5645 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5647 COND_EXPR_THEN (addr) = t;
5649 if (osize > UNITS_PER_WORD)
5651 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5652 u = size_int (osize - 1);
5653 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5654 unshare_expr (ovfl), u);
5655 t = fold_convert (sizetype, t);
5656 u = size_int (-osize);
5657 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5658 t = fold_convert (TREE_TYPE (ovfl), t);
5659 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5660 unshare_expr (ovfl), t);
5665 /* [10, 11] Emit code for:
5666 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5668 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5669 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5670 if (BYTES_BIG_ENDIAN && osize > size)
5672 u = size_int (osize - size);
5673 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5676 /* String [9] and [10, 11] together. */
5678 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5679 COND_EXPR_ELSE (addr) = t;
5681 addr = fold_convert (build_pointer_type (type), addr);
5682 addr = build_va_arg_indirect_ref (addr);
5686 addr = build_va_arg_indirect_ref (addr);
5691 /* Start a definition of function NAME. MIPS16_P indicates whether the
5692 function contains MIPS16 code. */
5695 mips_start_function_definition (const char *name, bool mips16_p)
5698 fprintf (asm_out_file, "\t.set\tmips16\n");
5700 fprintf (asm_out_file, "\t.set\tnomips16\n");
5702 if (!flag_inhibit_size_directive)
5704 fputs ("\t.ent\t", asm_out_file);
5705 assemble_name (asm_out_file, name);
5706 fputs ("\n", asm_out_file);
5709 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5711 /* Start the definition proper. */
5712 assemble_name (asm_out_file, name);
5713 fputs (":\n", asm_out_file);
5716 /* End a function definition started by mips_start_function_definition. */
5719 mips_end_function_definition (const char *name)
5721 if (!flag_inhibit_size_directive)
5723 fputs ("\t.end\t", asm_out_file);
5724 assemble_name (asm_out_file, name);
5725 fputs ("\n", asm_out_file);
5729 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5732 mips_ok_for_lazy_binding_p (rtx x)
5734 return (TARGET_USE_GOT
5735 && GET_CODE (x) == SYMBOL_REF
5736 && !SYMBOL_REF_BIND_NOW_P (x)
5737 && !mips_symbol_binds_local_p (x));
5740 /* Load function address ADDR into register DEST. TYPE is as for
5741 mips_expand_call. Return true if we used an explicit lazy-binding
5745 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5747 /* If we're generating PIC, and this call is to a global function,
5748 try to allow its address to be resolved lazily. This isn't
5749 possible for sibcalls when $gp is call-saved because the value
5750 of $gp on entry to the stub would be our caller's gp, not ours. */
5751 if (TARGET_EXPLICIT_RELOCS
5752 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5753 && mips_ok_for_lazy_binding_p (addr))
5755 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5756 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5761 mips_emit_move (dest, addr);
5766 /* Each locally-defined hard-float MIPS16 function has a local symbol
5767 associated with it. This hash table maps the function symbol (FUNC)
5768 to the local symbol (LOCAL). */
5769 struct GTY(()) mips16_local_alias {
5773 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5775 /* Hash table callbacks for mips16_local_aliases. */
5778 mips16_local_aliases_hash (const void *entry)
5780 const struct mips16_local_alias *alias;
5782 alias = (const struct mips16_local_alias *) entry;
5783 return htab_hash_string (XSTR (alias->func, 0));
5787 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5789 const struct mips16_local_alias *alias1, *alias2;
5791 alias1 = (const struct mips16_local_alias *) entry1;
5792 alias2 = (const struct mips16_local_alias *) entry2;
5793 return rtx_equal_p (alias1->func, alias2->func);
5796 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5797 Return a local alias for it, creating a new one if necessary. */
5800 mips16_local_alias (rtx func)
5802 struct mips16_local_alias *alias, tmp_alias;
5805 /* Create the hash table if this is the first call. */
5806 if (mips16_local_aliases == NULL)
5807 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5808 mips16_local_aliases_eq, NULL);
5810 /* Look up the function symbol, creating a new entry if need be. */
5811 tmp_alias.func = func;
5812 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5813 gcc_assert (slot != NULL);
5815 alias = (struct mips16_local_alias *) *slot;
5818 const char *func_name, *local_name;
5821 /* Create a new SYMBOL_REF for the local symbol. The choice of
5822 __fn_local_* is based on the __fn_stub_* names that we've
5823 traditionally used for the non-MIPS16 stub. */
5824 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5825 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5826 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5827 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5829 /* Create a new structure to represent the mapping. */
5830 alias = GGC_NEW (struct mips16_local_alias);
5832 alias->local = local;
5835 return alias->local;
5838 /* A chained list of functions for which mips16_build_call_stub has already
5839 generated a stub. NAME is the name of the function and FP_RET_P is true
5840 if the function returns a value in floating-point registers. */
5841 struct mips16_stub {
5842 struct mips16_stub *next;
5846 static struct mips16_stub *mips16_stubs;
5848 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5851 mips16_stub_function (const char *name)
5855 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5856 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5860 /* Return the two-character string that identifies floating-point
5861 return mode MODE in the name of a MIPS16 function stub. */
5864 mips16_call_stub_mode_suffix (enum machine_mode mode)
5868 else if (mode == DFmode)
5870 else if (mode == SCmode)
5872 else if (mode == DCmode)
5874 else if (mode == V2SFmode)
5880 /* Write instructions to move a 32-bit value between general register
5881 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5882 from GPREG to FPREG and 'f' to move in the opposite direction. */
5885 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5887 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5888 reg_names[gpreg], reg_names[fpreg]);
5891 /* Likewise for 64-bit values. */
5894 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5897 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5898 reg_names[gpreg], reg_names[fpreg]);
5899 else if (TARGET_FLOAT64)
5901 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5902 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5903 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5904 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5908 /* Move the least-significant word. */
5909 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5910 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5911 /* ...then the most significant word. */
5912 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5913 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5917 /* Write out code to move floating-point arguments into or out of
5918 general registers. FP_CODE is the code describing which arguments
5919 are present (see the comment above the definition of CUMULATIVE_ARGS
5920 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5923 mips_output_args_xfer (int fp_code, char direction)
5925 unsigned int gparg, fparg, f;
5926 CUMULATIVE_ARGS cum;
5928 /* This code only works for o32 and o64. */
5929 gcc_assert (TARGET_OLDABI);
5931 mips_init_cumulative_args (&cum, NULL);
5933 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5935 enum machine_mode mode;
5936 struct mips_arg_info info;
5940 else if ((f & 3) == 2)
5945 mips_get_arg_info (&info, &cum, mode, NULL, true);
5946 gparg = mips_arg_regno (&info, false);
5947 fparg = mips_arg_regno (&info, true);
5950 mips_output_32bit_xfer (direction, gparg, fparg);
5952 mips_output_64bit_xfer (direction, gparg, fparg);
5954 mips_function_arg_advance (&cum, mode, NULL, true);
5958 /* Write a MIPS16 stub for the current function. This stub is used
5959 for functions which take arguments in the floating-point registers.
5960 It is normal-mode code that moves the floating-point arguments
5961 into the general registers and then jumps to the MIPS16 code. */
5964 mips16_build_function_stub (void)
5966 const char *fnname, *alias_name, *separator;
5967 char *secname, *stubname;
5972 /* Create the name of the stub, and its unique section. */
5973 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5974 alias = mips16_local_alias (symbol);
5976 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5977 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5978 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5979 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5981 /* Build a decl for the stub. */
5982 stubdecl = build_decl (BUILTINS_LOCATION,
5983 FUNCTION_DECL, get_identifier (stubname),
5984 build_function_type (void_type_node, NULL_TREE));
5985 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5986 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
5987 RESULT_DECL, NULL_TREE, void_type_node);
5989 /* Output a comment. */
5990 fprintf (asm_out_file, "\t# Stub function for %s (",
5991 current_function_name ());
5993 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5995 fprintf (asm_out_file, "%s%s", separator,
5996 (f & 3) == 1 ? "float" : "double");
5999 fprintf (asm_out_file, ")\n");
6001 /* Start the function definition. */
6002 assemble_start_function (stubdecl, stubname);
6003 mips_start_function_definition (stubname, false);
6005 /* If generating pic2 code, either set up the global pointer or
6007 if (TARGET_ABICALLS_PIC2)
6009 if (TARGET_ABSOLUTE_ABICALLS)
6010 fprintf (asm_out_file, "\t.option\tpic0\n");
6013 output_asm_insn ("%(.cpload\t%^%)", NULL);
6014 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6015 target function is. Use a local GOT access when loading the
6016 symbol, to cut down on the number of unnecessary GOT entries
6017 for stubs that aren't needed. */
6018 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6023 /* Load the address of the MIPS16 function into $25. Do this first so
6024 that targets with coprocessor interlocks can use an MFC1 to fill the
6026 output_asm_insn ("la\t%^,%0", &symbol);
6028 /* Move the arguments from floating-point registers to general registers. */
6029 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6031 /* Jump to the MIPS16 function. */
6032 output_asm_insn ("jr\t%^", NULL);
6034 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6035 fprintf (asm_out_file, "\t.option\tpic2\n");
6037 mips_end_function_definition (stubname);
6039 /* If the linker needs to create a dynamic symbol for the target
6040 function, it will associate the symbol with the stub (which,
6041 unlike the target function, follows the proper calling conventions).
6042 It is therefore useful to have a local alias for the target function,
6043 so that it can still be identified as MIPS16 code. As an optimization,
6044 this symbol can also be used for indirect MIPS16 references from
6045 within this file. */
6046 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6048 switch_to_section (function_section (current_function_decl));
6051 /* The current function is a MIPS16 function that returns a value in an FPR.
6052 Copy the return value from its soft-float to its hard-float location.
6053 libgcc2 has special non-MIPS16 helper functions for each case. */
6056 mips16_copy_fpr_return_value (void)
6058 rtx fn, insn, retval;
6060 enum machine_mode return_mode;
6063 return_type = DECL_RESULT (current_function_decl);
6064 return_mode = DECL_MODE (return_type);
6066 name = ACONCAT (("__mips16_ret_",
6067 mips16_call_stub_mode_suffix (return_mode),
6069 fn = mips16_stub_function (name);
6071 /* The function takes arguments in $2 (and possibly $3), so calls
6072 to it cannot be lazily bound. */
6073 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6075 /* Model the call as something that takes the GPR return value as
6076 argument and returns an "updated" value. */
6077 retval = gen_rtx_REG (return_mode, GP_RETURN);
6078 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6079 const0_rtx, NULL_RTX, false);
6080 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6083 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6084 RETVAL is the location of the return value, or null if this is
6085 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6086 arguments and FP_CODE is the code built by mips_function_arg;
6087 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6089 There are three alternatives:
6091 - If a stub was needed, emit the call and return the call insn itself.
6093 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6094 to the new target and return null.
6096 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6099 A stub is needed for calls to functions that, in normal mode,
6100 receive arguments in FPRs or return values in FPRs. The stub
6101 copies the arguments from their soft-float positions to their
6102 hard-float positions, calls the real function, then copies the
6103 return value from its hard-float position to its soft-float
6106 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6107 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6108 automatically redirects the JAL to the stub, otherwise the JAL
6109 continues to call FN directly. */
6112 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6116 struct mips16_stub *l;
6119 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6120 we were invoked with the -msoft-float option. */
6121 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6124 /* Figure out whether the value might come back in a floating-point
6126 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6128 /* We don't need to do anything if there were no floating-point
6129 arguments and the value will not be returned in a floating-point
6131 if (fp_code == 0 && !fp_ret_p)
6134 /* We don't need to do anything if this is a call to a special
6135 MIPS16 support function. */
6137 if (mips16_stub_function_p (fn))
6140 /* This code will only work for o32 and o64 abis. The other ABI's
6141 require more sophisticated support. */
6142 gcc_assert (TARGET_OLDABI);
6144 /* If we're calling via a function pointer, use one of the magic
6145 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6146 Each stub expects the function address to arrive in register $2. */
6147 if (GET_CODE (fn) != SYMBOL_REF
6148 || !call_insn_operand (fn, VOIDmode))
6151 rtx stub_fn, insn, addr;
6154 /* If this is a locally-defined and locally-binding function,
6155 avoid the stub by calling the local alias directly. */
6156 if (mips16_local_function_p (fn))
6158 *fn_ptr = mips16_local_alias (fn);
6162 /* Create a SYMBOL_REF for the libgcc.a function. */
6164 sprintf (buf, "__mips16_call_stub_%s_%d",
6165 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6168 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6169 stub_fn = mips16_stub_function (buf);
6171 /* The function uses $2 as an argument, so calls to it
6172 cannot be lazily bound. */
6173 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6175 /* Load the target function into $2. */
6176 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6177 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6179 /* Emit the call. */
6180 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6181 args_size, NULL_RTX, lazy_p);
6183 /* Tell GCC that this call does indeed use the value of $2. */
6184 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6186 /* If we are handling a floating-point return value, we need to
6187 save $18 in the function prologue. Putting a note on the
6188 call will mean that df_regs_ever_live_p ($18) will be true if the
6189 call is not eliminated, and we can check that in the prologue
6192 CALL_INSN_FUNCTION_USAGE (insn) =
6193 gen_rtx_EXPR_LIST (VOIDmode,
6194 gen_rtx_CLOBBER (VOIDmode,
6195 gen_rtx_REG (word_mode, 18)),
6196 CALL_INSN_FUNCTION_USAGE (insn));
6201 /* We know the function we are going to call. If we have already
6202 built a stub, we don't need to do anything further. */
6203 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6204 for (l = mips16_stubs; l != NULL; l = l->next)
6205 if (strcmp (l->name, fnname) == 0)
6210 const char *separator;
6211 char *secname, *stubname;
6212 tree stubid, stubdecl;
6215 /* If the function does not return in FPRs, the special stub
6219 If the function does return in FPRs, the stub section is named
6220 .mips16.call.fp.FNNAME
6222 Build a decl for the stub. */
6223 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6225 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6227 stubid = get_identifier (stubname);
6228 stubdecl = build_decl (BUILTINS_LOCATION,
6229 FUNCTION_DECL, stubid,
6230 build_function_type (void_type_node, NULL_TREE));
6231 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6232 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6233 RESULT_DECL, NULL_TREE,
6236 /* Output a comment. */
6237 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6239 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6243 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6245 fprintf (asm_out_file, "%s%s", separator,
6246 (f & 3) == 1 ? "float" : "double");
6249 fprintf (asm_out_file, ")\n");
6251 /* Start the function definition. */
6252 assemble_start_function (stubdecl, stubname);
6253 mips_start_function_definition (stubname, false);
6257 /* Load the address of the MIPS16 function into $25. Do this
6258 first so that targets with coprocessor interlocks can use
6259 an MFC1 to fill the delay slot. */
6260 if (TARGET_EXPLICIT_RELOCS)
6262 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6263 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6266 output_asm_insn ("la\t%^,%0", &fn);
6269 /* Move the arguments from general registers to floating-point
6271 mips_output_args_xfer (fp_code, 't');
6275 /* Jump to the previously-loaded address. */
6276 output_asm_insn ("jr\t%^", NULL);
6280 /* Save the return address in $18 and call the non-MIPS16 function.
6281 The stub's caller knows that $18 might be clobbered, even though
6282 $18 is usually a call-saved register. */
6283 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6284 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6285 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6287 /* Move the result from floating-point registers to
6288 general registers. */
6289 switch (GET_MODE (retval))
6292 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6293 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6296 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6297 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6299 /* On 64-bit targets, complex floats are returned in
6300 a single GPR, such that "sd" on a suitably-aligned
6301 target would store the value correctly. */
6302 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6303 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6304 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6305 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6306 reg_names[GP_RETURN],
6307 reg_names[GP_RETURN],
6308 reg_names[GP_RETURN + 1]);
6313 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6314 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6318 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6324 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6327 #ifdef ASM_DECLARE_FUNCTION_SIZE
6328 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6331 mips_end_function_definition (stubname);
6333 /* Record this stub. */
6334 l = XNEW (struct mips16_stub);
6335 l->name = xstrdup (fnname);
6336 l->fp_ret_p = fp_ret_p;
6337 l->next = mips16_stubs;
6341 /* If we expect a floating-point return value, but we've built a
6342 stub which does not expect one, then we're in trouble. We can't
6343 use the existing stub, because it won't handle the floating-point
6344 value. We can't build a new stub, because the linker won't know
6345 which stub to use for the various calls in this object file.
6346 Fortunately, this case is illegal, since it means that a function
6347 was declared in two different ways in a single compilation. */
6348 if (fp_ret_p && !l->fp_ret_p)
6349 error ("cannot handle inconsistent calls to %qs", fnname);
6351 if (retval == NULL_RTX)
6352 insn = gen_call_internal_direct (fn, args_size);
6354 insn = gen_call_value_internal_direct (retval, fn, args_size);
6355 insn = mips_emit_call_insn (insn, fn, fn, false);
6357 /* If we are calling a stub which handles a floating-point return
6358 value, we need to arrange to save $18 in the prologue. We do this
6359 by marking the function call as using the register. The prologue
6360 will later see that it is used, and emit code to save it. */
6362 CALL_INSN_FUNCTION_USAGE (insn) =
6363 gen_rtx_EXPR_LIST (VOIDmode,
6364 gen_rtx_CLOBBER (VOIDmode,
6365 gen_rtx_REG (word_mode, 18)),
6366 CALL_INSN_FUNCTION_USAGE (insn));
6371 /* Expand a call of type TYPE. RESULT is where the result will go (null
6372 for "call"s and "sibcall"s), ADDR is the address of the function,
6373 ARGS_SIZE is the size of the arguments and AUX is the value passed
6374 to us by mips_function_arg. LAZY_P is true if this call already
6375 involves a lazily-bound function address (such as when calling
6376 functions through a MIPS16 hard-float stub).
6378 Return the call itself. */
6381 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6382 rtx args_size, rtx aux, bool lazy_p)
6384 rtx orig_addr, pattern, insn;
6387 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6388 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6391 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6396 if (!call_insn_operand (addr, VOIDmode))
6398 if (type == MIPS_CALL_EPILOGUE)
6399 addr = MIPS_EPILOGUE_TEMP (Pmode);
6401 addr = gen_reg_rtx (Pmode);
6402 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6407 rtx (*fn) (rtx, rtx);
6409 if (type == MIPS_CALL_SIBCALL)
6410 fn = gen_sibcall_internal;
6412 fn = gen_call_internal;
6414 pattern = fn (addr, args_size);
6416 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6418 /* Handle return values created by mips_return_fpr_pair. */
6419 rtx (*fn) (rtx, rtx, rtx, rtx);
6422 if (type == MIPS_CALL_SIBCALL)
6423 fn = gen_sibcall_value_multiple_internal;
6425 fn = gen_call_value_multiple_internal;
6427 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6428 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6429 pattern = fn (reg1, addr, args_size, reg2);
6433 rtx (*fn) (rtx, rtx, rtx);
6435 if (type == MIPS_CALL_SIBCALL)
6436 fn = gen_sibcall_value_internal;
6438 fn = gen_call_value_internal;
6440 /* Handle return values created by mips_return_fpr_single. */
6441 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6442 result = XEXP (XVECEXP (result, 0, 0), 0);
6443 pattern = fn (result, addr, args_size);
6446 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6449 /* Split call instruction INSN into a $gp-clobbering call and
6450 (where necessary) an instruction to restore $gp from its save slot.
6451 CALL_PATTERN is the pattern of the new call. */
6454 mips_split_call (rtx insn, rtx call_pattern)
6458 new_insn = emit_call_insn (call_pattern);
6459 CALL_INSN_FUNCTION_USAGE (new_insn)
6460 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6461 if (!find_reg_note (insn, REG_NORETURN, 0))
6462 /* Pick a temporary register that is suitable for both MIPS16 and
6463 non-MIPS16 code. $4 and $5 are used for returning complex double
6464 values in soft-float code, so $6 is the first suitable candidate. */
6465 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6468 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6471 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6473 if (!TARGET_SIBCALLS)
6476 /* Interrupt handlers need special epilogue code and therefore can't
6478 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6481 /* We can't do a sibcall if the called function is a MIPS16 function
6482 because there is no direct "jx" instruction equivalent to "jalx" to
6483 switch the ISA mode. We only care about cases where the sibling
6484 and normal calls would both be direct. */
6486 && mips_use_mips16_mode_p (decl)
6487 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6490 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6491 functions could be MIPS16 ones unless an attribute explicitly tells
6493 if (TARGET_INTERLINK_MIPS16
6495 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6496 && !mips_nomips16_decl_p (decl)
6497 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6504 /* Emit code to move general operand SRC into condition-code
6505 register DEST given that SCRATCH is a scratch TFmode FPR.
6512 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6515 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6519 /* Change the source to SFmode. */
6521 src = adjust_address (src, SFmode, 0);
6522 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6523 src = gen_rtx_REG (SFmode, true_regnum (src));
6525 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6526 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6528 mips_emit_move (copy_rtx (fp1), src);
6529 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6530 emit_insn (gen_slt_sf (dest, fp2, fp1));
6533 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6534 Assume that the areas do not overlap. */
6537 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6539 HOST_WIDE_INT offset, delta;
6540 unsigned HOST_WIDE_INT bits;
6542 enum machine_mode mode;
6545 /* Work out how many bits to move at a time. If both operands have
6546 half-word alignment, it is usually better to move in half words.
6547 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6548 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6549 Otherwise move word-sized chunks. */
6550 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6551 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6552 bits = BITS_PER_WORD / 2;
6554 bits = BITS_PER_WORD;
6556 mode = mode_for_size (bits, MODE_INT, 0);
6557 delta = bits / BITS_PER_UNIT;
6559 /* Allocate a buffer for the temporary registers. */
6560 regs = XALLOCAVEC (rtx, length / delta);
6562 /* Load as many BITS-sized chunks as possible. Use a normal load if
6563 the source has enough alignment, otherwise use left/right pairs. */
6564 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6566 regs[i] = gen_reg_rtx (mode);
6567 if (MEM_ALIGN (src) >= bits)
6568 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6571 rtx part = adjust_address (src, BLKmode, offset);
6572 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6577 /* Copy the chunks to the destination. */
6578 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6579 if (MEM_ALIGN (dest) >= bits)
6580 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6583 rtx part = adjust_address (dest, BLKmode, offset);
6584 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6588 /* Mop up any left-over bytes. */
6589 if (offset < length)
6591 src = adjust_address (src, BLKmode, offset);
6592 dest = adjust_address (dest, BLKmode, offset);
6593 move_by_pieces (dest, src, length - offset,
6594 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6598 /* Helper function for doing a loop-based block operation on memory
6599 reference MEM. Each iteration of the loop will operate on LENGTH
6602 Create a new base register for use within the loop and point it to
6603 the start of MEM. Create a new memory reference that uses this
6604 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6607 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6608 rtx *loop_reg, rtx *loop_mem)
6610 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6612 /* Although the new mem does not refer to a known location,
6613 it does keep up to LENGTH bytes of alignment. */
6614 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6615 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6618 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6619 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6620 the memory regions do not overlap. */
6623 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6624 HOST_WIDE_INT bytes_per_iter)
6626 rtx label, src_reg, dest_reg, final_src, test;
6627 HOST_WIDE_INT leftover;
6629 leftover = length % bytes_per_iter;
6632 /* Create registers and memory references for use within the loop. */
6633 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6634 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6636 /* Calculate the value that SRC_REG should have after the last iteration
6638 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6641 /* Emit the start of the loop. */
6642 label = gen_label_rtx ();
6645 /* Emit the loop body. */
6646 mips_block_move_straight (dest, src, bytes_per_iter);
6648 /* Move on to the next block. */
6649 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6650 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6652 /* Emit the loop condition. */
6653 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6654 if (Pmode == DImode)
6655 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6657 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6659 /* Mop up any left-over bytes. */
6661 mips_block_move_straight (dest, src, leftover);
6664 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6665 memory reference SRC to memory reference DEST. */
6668 mips_expand_block_move (rtx dest, rtx src, rtx length)
6670 if (CONST_INT_P (length))
6672 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6674 mips_block_move_straight (dest, src, INTVAL (length));
6679 mips_block_move_loop (dest, src, INTVAL (length),
6680 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6687 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6690 mips_expand_synci_loop (rtx begin, rtx end)
6692 rtx inc, label, cmp, cmp_result;
6694 /* Load INC with the cache line size (rdhwr INC,$1). */
6695 inc = gen_reg_rtx (Pmode);
6696 emit_insn (Pmode == SImode
6697 ? gen_rdhwr_synci_step_si (inc)
6698 : gen_rdhwr_synci_step_di (inc));
6700 /* Loop back to here. */
6701 label = gen_label_rtx ();
6704 emit_insn (gen_synci (begin));
6706 cmp = mips_force_binary (Pmode, GTU, begin, end);
6708 mips_emit_binary (PLUS, begin, begin, inc);
6710 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6711 emit_jump_insn (gen_condjump (cmp_result, label));
6714 /* Expand a QI or HI mode atomic memory operation.
6716 GENERATOR contains a pointer to the gen_* function that generates
6717 the SI mode underlying atomic operation using masks that we
6720 RESULT is the return register for the operation. Its value is NULL
6723 MEM is the location of the atomic access.
6725 OLDVAL is the first operand for the operation.
6727 NEWVAL is the optional second operand for the operation. Its value
6728 is NULL if unused. */
6731 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6732 rtx result, rtx mem, rtx oldval, rtx newval)
6734 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6735 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6737 enum machine_mode mode;
6739 mode = GET_MODE (mem);
6741 /* Compute the address of the containing SImode value. */
6742 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6743 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6744 force_reg (Pmode, GEN_INT (-4)));
6746 /* Create a memory reference for it. */
6747 memsi = gen_rtx_MEM (SImode, memsi_addr);
6748 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6749 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6751 /* Work out the byte offset of the QImode or HImode value,
6752 counting from the least significant byte. */
6753 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6754 if (TARGET_BIG_ENDIAN)
6755 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6757 /* Multiply by eight to convert the shift value from bytes to bits. */
6758 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6760 /* Make the final shift an SImode value, so that it can be used in
6761 SImode operations. */
6762 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6764 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6765 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6766 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6767 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6769 /* Compute the equivalent exclusive mask. */
6770 inverted_mask = gen_reg_rtx (SImode);
6771 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6772 gen_rtx_NOT (SImode, mask)));
6774 /* Shift the old value into place. */
6775 if (oldval != const0_rtx)
6777 oldval = convert_modes (SImode, mode, oldval, true);
6778 oldval = force_reg (SImode, oldval);
6779 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6782 /* Do the same for the new value. */
6783 if (newval && newval != const0_rtx)
6785 newval = convert_modes (SImode, mode, newval, true);
6786 newval = force_reg (SImode, newval);
6787 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6790 /* Do the SImode atomic access. */
6792 res = gen_reg_rtx (SImode);
6794 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6796 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6798 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6804 /* Shift and convert the result. */
6805 mips_emit_binary (AND, res, res, mask);
6806 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6807 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6811 /* Return true if it is possible to use left/right accesses for a
6812 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6813 returning true, update *OP, *LEFT and *RIGHT as follows:
6815 *OP is a BLKmode reference to the whole field.
6817 *LEFT is a QImode reference to the first byte if big endian or
6818 the last byte if little endian. This address can be used in the
6819 left-side instructions (LWL, SWL, LDL, SDL).
6821 *RIGHT is a QImode reference to the opposite end of the field and
6822 can be used in the patterning right-side instruction. */
6825 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6826 rtx *left, rtx *right)
6830 /* Check that the operand really is a MEM. Not all the extv and
6831 extzv predicates are checked. */
6835 /* Check that the size is valid. */
6836 if (width != 32 && (!TARGET_64BIT || width != 64))
6839 /* We can only access byte-aligned values. Since we are always passed
6840 a reference to the first byte of the field, it is not necessary to
6841 do anything with BITPOS after this check. */
6842 if (bitpos % BITS_PER_UNIT != 0)
6845 /* Reject aligned bitfields: we want to use a normal load or store
6846 instead of a left/right pair. */
6847 if (MEM_ALIGN (*op) >= width)
6850 /* Adjust *OP to refer to the whole field. This also has the effect
6851 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6852 *op = adjust_address (*op, BLKmode, 0);
6853 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6855 /* Get references to both ends of the field. We deliberately don't
6856 use the original QImode *OP for FIRST since the new BLKmode one
6857 might have a simpler address. */
6858 first = adjust_address (*op, QImode, 0);
6859 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6861 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6862 correspond to the MSB and RIGHT to the LSB. */
6863 if (TARGET_BIG_ENDIAN)
6864 *left = first, *right = last;
6866 *left = last, *right = first;
6871 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6872 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6873 the operation is the equivalent of:
6875 (set DEST (*_extract SRC WIDTH BITPOS))
6877 Return true on success. */
6880 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6881 HOST_WIDE_INT bitpos)
6883 rtx left, right, temp;
6885 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6886 be a paradoxical word_mode subreg. This is the only case in which
6887 we allow the destination to be larger than the source. */
6888 if (GET_CODE (dest) == SUBREG
6889 && GET_MODE (dest) == DImode
6890 && GET_MODE (SUBREG_REG (dest)) == SImode)
6891 dest = SUBREG_REG (dest);
6893 /* After the above adjustment, the destination must be the same
6894 width as the source. */
6895 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6898 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6901 temp = gen_reg_rtx (GET_MODE (dest));
6902 if (GET_MODE (dest) == DImode)
6904 emit_insn (gen_mov_ldl (temp, src, left));
6905 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6909 emit_insn (gen_mov_lwl (temp, src, left));
6910 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6915 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6916 BITPOS and SRC are the operands passed to the expander; the operation
6917 is the equivalent of:
6919 (set (zero_extract DEST WIDTH BITPOS) SRC)
6921 Return true on success. */
6924 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6925 HOST_WIDE_INT bitpos)
6928 enum machine_mode mode;
6930 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6933 mode = mode_for_size (width, MODE_INT, 0);
6934 src = gen_lowpart (mode, src);
6937 emit_insn (gen_mov_sdl (dest, src, left));
6938 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6942 emit_insn (gen_mov_swl (dest, src, left));
6943 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6948 /* Return true if X is a MEM with the same size as MODE. */
6951 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6958 size = MEM_SIZE (x);
6959 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6962 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6963 source of an "ext" instruction or the destination of an "ins"
6964 instruction. OP must be a register operand and the following
6965 conditions must hold:
6967 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6968 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6969 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6971 Also reject lengths equal to a word as they are better handled
6972 by the move patterns. */
6975 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6977 if (!ISA_HAS_EXT_INS
6978 || !register_operand (op, VOIDmode)
6979 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6982 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6985 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6991 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6992 operation if MAXLEN is the maxium length of consecutive bits that
6993 can make up MASK. MODE is the mode of the operation. See
6994 mask_low_and_shift_len for the actual definition. */
6997 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6999 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7002 /* Return true iff OP1 and OP2 are valid operands together for the
7003 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7004 see the table in the comment before the pattern. */
7007 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7009 return (memory_operand (op1, mode)
7010 ? and_load_operand (op2, mode)
7011 : and_reg_operand (op2, mode));
7014 /* The canonical form of a mask-low-and-shift-left operation is
7015 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7016 cleared. Thus we need to shift MASK to the right before checking if it
7017 is a valid mask value. MODE is the mode of the operation. If true
7018 return the length of the mask, otherwise return -1. */
7021 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7023 HOST_WIDE_INT shval;
7025 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7026 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7029 /* Return true if -msplit-addresses is selected and should be honored.
7031 -msplit-addresses is a half-way house between explicit relocations
7032 and the traditional assembler macros. It can split absolute 32-bit
7033 symbolic constants into a high/lo_sum pair but uses macros for other
7036 Like explicit relocation support for REL targets, it relies
7037 on GNU extensions in the assembler and the linker.
7039 Although this code should work for -O0, it has traditionally
7040 been treated as an optimization. */
7043 mips_split_addresses_p (void)
7045 return (TARGET_SPLIT_ADDRESSES
7049 && !ABI_HAS_64BIT_SYMBOLS);
7052 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7055 mips_init_relocs (void)
7057 memset (mips_split_p, '\0', sizeof (mips_split_p));
7058 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7059 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7060 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7062 if (ABI_HAS_64BIT_SYMBOLS)
7064 if (TARGET_EXPLICIT_RELOCS)
7066 mips_split_p[SYMBOL_64_HIGH] = true;
7067 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7068 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7070 mips_split_p[SYMBOL_64_MID] = true;
7071 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7072 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7074 mips_split_p[SYMBOL_64_LOW] = true;
7075 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7076 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7078 mips_split_p[SYMBOL_ABSOLUTE] = true;
7079 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7084 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7086 mips_split_p[SYMBOL_ABSOLUTE] = true;
7087 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7088 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7090 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7096 /* The high part is provided by a pseudo copy of $gp. */
7097 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7098 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7100 else if (TARGET_EXPLICIT_RELOCS)
7101 /* Small data constants are kept whole until after reload,
7102 then lowered by mips_rewrite_small_data. */
7103 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7105 if (TARGET_EXPLICIT_RELOCS)
7107 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7110 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7111 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7115 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7116 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7119 /* Expose the use of $28 as soon as possible. */
7120 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7124 /* The HIGH and LO_SUM are matched by special .md patterns. */
7125 mips_split_p[SYMBOL_GOT_DISP] = true;
7127 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7128 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7129 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7131 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7132 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7133 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7138 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7140 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7141 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7143 /* Expose the use of $28 as soon as possible. */
7144 mips_split_p[SYMBOL_GOT_DISP] = true;
7150 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7151 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7152 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7155 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7156 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7158 mips_split_p[SYMBOL_DTPREL] = true;
7159 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7160 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7162 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7164 mips_split_p[SYMBOL_TPREL] = true;
7165 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7166 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7168 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7171 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7172 in context CONTEXT. RELOCS is the array of relocations to use. */
7175 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7176 const char **relocs)
7178 enum mips_symbol_type symbol_type;
7181 symbol_type = mips_classify_symbolic_expression (op, context);
7182 gcc_assert (relocs[symbol_type]);
7184 fputs (relocs[symbol_type], file);
7185 output_addr_const (file, mips_strip_unspec_address (op));
7186 for (p = relocs[symbol_type]; *p != 0; p++)
7191 /* Start a new block with the given asm switch enabled. If we need
7192 to print a directive, emit PREFIX before it and SUFFIX after it. */
7195 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7196 const char *prefix, const char *suffix)
7198 if (asm_switch->nesting_level == 0)
7199 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7200 asm_switch->nesting_level++;
7203 /* Likewise, but end a block. */
7206 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7207 const char *prefix, const char *suffix)
7209 gcc_assert (asm_switch->nesting_level);
7210 asm_switch->nesting_level--;
7211 if (asm_switch->nesting_level == 0)
7212 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7215 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7216 that either print a complete line or print nothing. */
7219 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7221 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7225 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7227 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7230 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7231 The punctuation characters are:
7233 '(' Start a nested ".set noreorder" block.
7234 ')' End a nested ".set noreorder" block.
7235 '[' Start a nested ".set noat" block.
7236 ']' End a nested ".set noat" block.
7237 '<' Start a nested ".set nomacro" block.
7238 '>' End a nested ".set nomacro" block.
7239 '*' Behave like %(%< if generating a delayed-branch sequence.
7240 '#' Print a nop if in a ".set noreorder" block.
7241 '/' Like '#', but do nothing within a delayed-branch sequence.
7242 '?' Print "l" if mips_branch_likely is true
7243 '~' Print a nop if mips_branch_likely is true
7244 '.' Print the name of the register with a hard-wired zero (zero or $0).
7245 '@' Print the name of the assembler temporary register (at or $1).
7246 '^' Print the name of the pic call-through register (t9 or $25).
7247 '+' Print the name of the gp register (usually gp or $28).
7248 '$' Print the name of the stack pointer register (sp or $29).
7250 See also mips_init_print_operand_pucnt. */
7253 mips_print_operand_punctuation (FILE *file, int ch)
7258 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7262 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7266 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7270 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7274 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7278 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7282 if (final_sequence != 0)
7284 mips_print_operand_punctuation (file, '(');
7285 mips_print_operand_punctuation (file, '<');
7290 if (mips_noreorder.nesting_level > 0)
7291 fputs ("\n\tnop", file);
7295 /* Print an extra newline so that the delayed insn is separated
7296 from the following ones. This looks neater and is consistent
7297 with non-nop delayed sequences. */
7298 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7299 fputs ("\n\tnop\n", file);
7303 if (mips_branch_likely)
7308 if (mips_branch_likely)
7309 fputs ("\n\tnop", file);
7313 fputs (reg_names[GP_REG_FIRST + 0], file);
7317 fputs (reg_names[AT_REGNUM], file);
7321 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7325 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7329 fputs (reg_names[STACK_POINTER_REGNUM], file);
7338 /* Initialize mips_print_operand_punct. */
7341 mips_init_print_operand_punct (void)
7345 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7346 mips_print_operand_punct[(unsigned char) *p] = true;
7349 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7350 associated with condition CODE. Print the condition part of the
7354 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7368 /* Conveniently, the MIPS names for these conditions are the same
7369 as their RTL equivalents. */
7370 fputs (GET_RTX_NAME (code), file);
7374 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7379 /* Likewise floating-point branches. */
7382 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7387 fputs ("c1f", file);
7391 fputs ("c1t", file);
7395 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7400 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7402 'X' Print CONST_INT OP in hexadecimal format.
7403 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7404 'd' Print CONST_INT OP in decimal.
7405 'm' Print one less than CONST_INT OP in decimal.
7406 'h' Print the high-part relocation associated with OP, after stripping
7408 'R' Print the low-part relocation associated with OP.
7409 'C' Print the integer branch condition for comparison OP.
7410 'N' Print the inverse of the integer branch condition for comparison OP.
7411 'F' Print the FPU branch condition for comparison OP.
7412 'W' Print the inverse of the FPU branch condition for comparison OP.
7413 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7414 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7415 't' Like 'T', but with the EQ/NE cases reversed
7416 'Y' Print mips_fp_conditions[INTVAL (OP)]
7417 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7418 'q' Print a DSP accumulator register.
7419 'D' Print the second part of a double-word register or memory operand.
7420 'L' Print the low-order register in a double-word register operand.
7421 'M' Print high-order register in a double-word register operand.
7422 'z' Print $0 if OP is zero, otherwise print OP normally. */
7425 mips_print_operand (FILE *file, rtx op, int letter)
7429 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7431 mips_print_operand_punctuation (file, letter);
7436 code = GET_CODE (op);
7441 if (CONST_INT_P (op))
7442 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7444 output_operand_lossage ("invalid use of '%%%c'", letter);
7448 if (CONST_INT_P (op))
7449 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7451 output_operand_lossage ("invalid use of '%%%c'", letter);
7455 if (CONST_INT_P (op))
7456 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7458 output_operand_lossage ("invalid use of '%%%c'", letter);
7462 if (CONST_INT_P (op))
7463 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7465 output_operand_lossage ("invalid use of '%%%c'", letter);
7471 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7475 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7479 mips_print_int_branch_condition (file, code, letter);
7483 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7487 mips_print_float_branch_condition (file, code, letter);
7491 mips_print_float_branch_condition (file, reverse_condition (code),
7498 int truth = (code == NE) == (letter == 'T');
7499 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7504 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7505 fputs (mips_fp_conditions[UINTVAL (op)], file);
7507 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7514 mips_print_operand (file, op, 0);
7520 if (code == REG && MD_REG_P (REGNO (op)))
7521 fprintf (file, "$ac0");
7522 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7523 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7525 output_operand_lossage ("invalid use of '%%%c'", letter);
7533 unsigned int regno = REGNO (op);
7534 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7535 || (letter == 'L' && TARGET_BIG_ENDIAN)
7538 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7539 output_operand_lossage ("invalid use of '%%%c'", letter);
7540 /* We need to print $0 .. $31 for COP0 registers. */
7541 if (COP0_REG_P (regno))
7542 fprintf (file, "$%s", ®_names[regno][4]);
7544 fprintf (file, "%s", reg_names[regno]);
7550 output_address (plus_constant (XEXP (op, 0), 4));
7551 else if (letter && letter != 'z')
7552 output_operand_lossage ("invalid use of '%%%c'", letter);
7554 output_address (XEXP (op, 0));
7558 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7559 fputs (reg_names[GP_REG_FIRST], file);
7560 else if (letter && letter != 'z')
7561 output_operand_lossage ("invalid use of '%%%c'", letter);
7562 else if (CONST_GP_P (op))
7563 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7565 output_addr_const (file, mips_strip_unspec_address (op));
7571 /* Output address operand X to FILE. */
7574 mips_print_operand_address (FILE *file, rtx x)
7576 struct mips_address_info addr;
7578 if (mips_classify_address (&addr, x, word_mode, true))
7582 mips_print_operand (file, addr.offset, 0);
7583 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7586 case ADDRESS_LO_SUM:
7587 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7589 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7592 case ADDRESS_CONST_INT:
7593 output_addr_const (file, x);
7594 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7597 case ADDRESS_SYMBOLIC:
7598 output_addr_const (file, mips_strip_unspec_address (x));
7604 /* Implement TARGET_ENCODE_SECTION_INFO. */
7607 mips_encode_section_info (tree decl, rtx rtl, int first)
7609 default_encode_section_info (decl, rtl, first);
7611 if (TREE_CODE (decl) == FUNCTION_DECL)
7613 rtx symbol = XEXP (rtl, 0);
7614 tree type = TREE_TYPE (decl);
7616 /* Encode whether the symbol is short or long. */
7617 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7618 || mips_far_type_p (type))
7619 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7623 /* Implement TARGET_SELECT_RTX_SECTION. */
7626 mips_select_rtx_section (enum machine_mode mode, rtx x,
7627 unsigned HOST_WIDE_INT align)
7629 /* ??? Consider using mergeable small data sections. */
7630 if (mips_rtx_constant_in_small_data_p (mode))
7631 return get_named_section (NULL, ".sdata", 0);
7633 return default_elf_select_rtx_section (mode, x, align);
7636 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7638 The complication here is that, with the combination TARGET_ABICALLS
7639 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7640 absolute addresses, and should therefore not be included in the
7641 read-only part of a DSO. Handle such cases by selecting a normal
7642 data section instead of a read-only one. The logic apes that in
7643 default_function_rodata_section. */
7646 mips_function_rodata_section (tree decl)
7648 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7649 return default_function_rodata_section (decl);
7651 if (decl && DECL_SECTION_NAME (decl))
7653 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7654 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7656 char *rname = ASTRDUP (name);
7658 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7660 else if (flag_function_sections
7661 && flag_data_sections
7662 && strncmp (name, ".text.", 6) == 0)
7664 char *rname = ASTRDUP (name);
7665 memcpy (rname + 1, "data", 4);
7666 return get_section (rname, SECTION_WRITE, decl);
7669 return data_section;
7672 /* Implement TARGET_IN_SMALL_DATA_P. */
7675 mips_in_small_data_p (const_tree decl)
7677 unsigned HOST_WIDE_INT size;
7679 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7682 /* We don't yet generate small-data references for -mabicalls
7683 or VxWorks RTP code. See the related -G handling in
7684 mips_override_options. */
7685 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7688 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7692 /* Reject anything that isn't in a known small-data section. */
7693 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7694 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7697 /* If a symbol is defined externally, the assembler will use the
7698 usual -G rules when deciding how to implement macros. */
7699 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7702 else if (TARGET_EMBEDDED_DATA)
7704 /* Don't put constants into the small data section: we want them
7705 to be in ROM rather than RAM. */
7706 if (TREE_CODE (decl) != VAR_DECL)
7709 if (TREE_READONLY (decl)
7710 && !TREE_SIDE_EFFECTS (decl)
7711 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7715 /* Enforce -mlocal-sdata. */
7716 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7719 /* Enforce -mextern-sdata. */
7720 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7722 if (DECL_EXTERNAL (decl))
7724 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7728 /* We have traditionally not treated zero-sized objects as small data,
7729 so this is now effectively part of the ABI. */
7730 size = int_size_in_bytes (TREE_TYPE (decl));
7731 return size > 0 && size <= mips_small_data_threshold;
7734 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7735 anchors for small data: the GP register acts as an anchor in that
7736 case. We also don't want to use them for PC-relative accesses,
7737 where the PC acts as an anchor. */
7740 mips_use_anchors_for_symbol_p (const_rtx symbol)
7742 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7744 case SYMBOL_PC_RELATIVE:
7745 case SYMBOL_GP_RELATIVE:
7749 return default_use_anchors_for_symbol_p (symbol);
7753 /* The MIPS debug format wants all automatic variables and arguments
7754 to be in terms of the virtual frame pointer (stack pointer before
7755 any adjustment in the function), while the MIPS 3.0 linker wants
7756 the frame pointer to be the stack pointer after the initial
7757 adjustment. So, we do the adjustment here. The arg pointer (which
7758 is eliminated) points to the virtual frame pointer, while the frame
7759 pointer (which may be eliminated) points to the stack pointer after
7760 the initial adjustments. */
7763 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7765 rtx offset2 = const0_rtx;
7766 rtx reg = eliminate_constant_term (addr, &offset2);
7769 offset = INTVAL (offset2);
7771 if (reg == stack_pointer_rtx
7772 || reg == frame_pointer_rtx
7773 || reg == hard_frame_pointer_rtx)
7775 offset -= cfun->machine->frame.total_size;
7776 if (reg == hard_frame_pointer_rtx)
7777 offset += cfun->machine->frame.hard_frame_pointer_offset;
7780 /* sdbout_parms does not want this to crash for unrecognized cases. */
7782 else if (reg != arg_pointer_rtx)
7783 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7790 /* Implement ASM_OUTPUT_EXTERNAL. */
7793 mips_output_external (FILE *file, tree decl, const char *name)
7795 default_elf_asm_output_external (file, decl, name);
7797 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7798 set in order to avoid putting out names that are never really
7800 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7802 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7804 /* When using assembler macros, emit .extern directives for
7805 all small-data externs so that the assembler knows how
7808 In most cases it would be safe (though pointless) to emit
7809 .externs for other symbols too. One exception is when an
7810 object is within the -G limit but declared by the user to
7811 be in a section other than .sbss or .sdata. */
7812 fputs ("\t.extern\t", file);
7813 assemble_name (file, name);
7814 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7815 int_size_in_bytes (TREE_TYPE (decl)));
7817 else if (TARGET_IRIX
7818 && mips_abi == ABI_32
7819 && TREE_CODE (decl) == FUNCTION_DECL)
7821 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7822 `.global name .text' directive for every used but
7823 undefined function. If we don't, the linker may perform
7824 an optimization (skipping over the insns that set $gp)
7825 when it is unsafe. */
7826 fputs ("\t.globl ", file);
7827 assemble_name (file, name);
7828 fputs (" .text\n", file);
7833 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7836 mips_output_filename (FILE *stream, const char *name)
7838 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7840 if (write_symbols == DWARF2_DEBUG)
7842 else if (mips_output_filename_first_time)
7844 mips_output_filename_first_time = 0;
7845 num_source_filenames += 1;
7846 current_function_file = name;
7847 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7848 output_quoted_string (stream, name);
7849 putc ('\n', stream);
7851 /* If we are emitting stabs, let dbxout.c handle this (except for
7852 the mips_output_filename_first_time case). */
7853 else if (write_symbols == DBX_DEBUG)
7855 else if (name != current_function_file
7856 && strcmp (name, current_function_file) != 0)
7858 num_source_filenames += 1;
7859 current_function_file = name;
7860 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7861 output_quoted_string (stream, name);
7862 putc ('\n', stream);
7866 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7868 static void ATTRIBUTE_UNUSED
7869 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7874 fputs ("\t.dtprelword\t", file);
7878 fputs ("\t.dtpreldword\t", file);
7884 output_addr_const (file, x);
7885 fputs ("+0x8000", file);
7888 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7891 mips_dwarf_register_span (rtx reg)
7894 enum machine_mode mode;
7896 /* By default, GCC maps increasing register numbers to increasing
7897 memory locations, but paired FPRs are always little-endian,
7898 regardless of the prevailing endianness. */
7899 mode = GET_MODE (reg);
7900 if (FP_REG_P (REGNO (reg))
7901 && TARGET_BIG_ENDIAN
7902 && MAX_FPRS_PER_FMT > 1
7903 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7905 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7906 high = mips_subword (reg, true);
7907 low = mips_subword (reg, false);
7908 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7914 /* Implement ASM_OUTPUT_ASCII. */
7917 mips_output_ascii (FILE *stream, const char *string, size_t len)
7923 fprintf (stream, "\t.ascii\t\"");
7924 for (i = 0; i < len; i++)
7928 c = (unsigned char) string[i];
7931 if (c == '\\' || c == '\"')
7933 putc ('\\', stream);
7941 fprintf (stream, "\\%03o", c);
7945 if (cur_pos > 72 && i+1 < len)
7948 fprintf (stream, "\"\n\t.ascii\t\"");
7951 fprintf (stream, "\"\n");
7954 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7955 macros, mark the symbol as written so that mips_asm_output_external
7956 won't emit an .extern for it. STREAM is the output file, NAME is the
7957 name of the symbol, INIT_STRING is the string that should be written
7958 before the symbol and FINAL_STRING is the string that should be
7959 written after it. FINAL_STRING is a printf format that consumes the
7960 remaining arguments. */
7963 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7964 const char *final_string, ...)
7968 fputs (init_string, stream);
7969 assemble_name (stream, name);
7970 va_start (ap, final_string);
7971 vfprintf (stream, final_string, ap);
7974 if (!TARGET_EXPLICIT_RELOCS)
7976 tree name_tree = get_identifier (name);
7977 TREE_ASM_WRITTEN (name_tree) = 1;
7981 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7982 NAME is the name of the object and ALIGN is the required alignment
7983 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7984 alignment argument. */
7987 mips_declare_common_object (FILE *stream, const char *name,
7988 const char *init_string,
7989 unsigned HOST_WIDE_INT size,
7990 unsigned int align, bool takes_alignment_p)
7992 if (!takes_alignment_p)
7994 size += (align / BITS_PER_UNIT) - 1;
7995 size -= size % (align / BITS_PER_UNIT);
7996 mips_declare_object (stream, name, init_string,
7997 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8000 mips_declare_object (stream, name, init_string,
8001 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8002 size, align / BITS_PER_UNIT);
8005 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8006 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8009 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8010 unsigned HOST_WIDE_INT size,
8013 /* If the target wants uninitialized const declarations in
8014 .rdata then don't put them in .comm. */
8015 if (TARGET_EMBEDDED_DATA
8016 && TARGET_UNINIT_CONST_IN_RODATA
8017 && TREE_CODE (decl) == VAR_DECL
8018 && TREE_READONLY (decl)
8019 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8021 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8022 targetm.asm_out.globalize_label (stream, name);
8024 switch_to_section (readonly_data_section);
8025 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8026 mips_declare_object (stream, name, "",
8027 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8031 mips_declare_common_object (stream, name, "\n\t.comm\t",
8035 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8036 extern int size_directive_output;
8038 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8039 definitions except that it uses mips_declare_object to emit the label. */
8042 mips_declare_object_name (FILE *stream, const char *name,
8043 tree decl ATTRIBUTE_UNUSED)
8045 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8046 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8049 size_directive_output = 0;
8050 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8054 size_directive_output = 1;
8055 size = int_size_in_bytes (TREE_TYPE (decl));
8056 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8059 mips_declare_object (stream, name, "", ":\n");
8062 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8065 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8069 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8070 if (!flag_inhibit_size_directive
8071 && DECL_SIZE (decl) != 0
8074 && DECL_INITIAL (decl) == error_mark_node
8075 && !size_directive_output)
8079 size_directive_output = 1;
8080 size = int_size_in_bytes (TREE_TYPE (decl));
8081 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8086 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8087 with the current ABI. */
8090 mips_mdebug_abi_name (void)
8103 return TARGET_64BIT ? "eabi64" : "eabi32";
8109 /* Implement TARGET_ASM_FILE_START. */
8112 mips_file_start (void)
8114 default_file_start ();
8116 /* Generate a special section to describe the ABI switches used to
8117 produce the resultant binary. This is unnecessary on IRIX and
8118 causes unwanted warnings from the native linker. */
8121 /* Record the ABI itself. Modern versions of binutils encode
8122 this information in the ELF header flags, but GDB needs the
8123 information in order to correctly debug binaries produced by
8124 older binutils. See the function mips_gdbarch_init in
8126 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8127 mips_mdebug_abi_name ());
8129 /* There is no ELF header flag to distinguish long32 forms of the
8130 EABI from long64 forms. Emit a special section to help tools
8131 such as GDB. Do the same for o64, which is sometimes used with
8133 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8134 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8135 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8137 #ifdef HAVE_AS_GNU_ATTRIBUTE
8138 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
8139 (TARGET_HARD_FLOAT_ABI
8140 ? (TARGET_DOUBLE_FLOAT
8141 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
8145 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8146 if (TARGET_ABICALLS)
8148 fprintf (asm_out_file, "\t.abicalls\n");
8149 if (TARGET_ABICALLS_PIC0)
8150 fprintf (asm_out_file, "\t.option\tpic0\n");
8153 if (flag_verbose_asm)
8154 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8156 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8159 /* Make the last instruction frame-related and note that it performs
8160 the operation described by FRAME_PATTERN. */
8163 mips_set_frame_expr (rtx frame_pattern)
8167 insn = get_last_insn ();
8168 RTX_FRAME_RELATED_P (insn) = 1;
8169 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8174 /* Return a frame-related rtx that stores REG at MEM.
8175 REG must be a single register. */
8178 mips_frame_set (rtx mem, rtx reg)
8182 /* If we're saving the return address register and the DWARF return
8183 address column differs from the hard register number, adjust the
8184 note reg to refer to the former. */
8185 if (REGNO (reg) == RETURN_ADDR_REGNUM
8186 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8187 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8189 set = gen_rtx_SET (VOIDmode, mem, reg);
8190 RTX_FRAME_RELATED_P (set) = 1;
8195 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8196 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8197 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8198 static const unsigned char mips16e_s2_s8_regs[] = {
8199 30, 23, 22, 21, 20, 19, 18
8201 static const unsigned char mips16e_a0_a3_regs[] = {
8205 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8206 ordered from the uppermost in memory to the lowest in memory. */
8207 static const unsigned char mips16e_save_restore_regs[] = {
8208 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8211 /* Return the index of the lowest X in the range [0, SIZE) for which
8212 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8215 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8220 for (i = 0; i < size; i++)
8221 if (BITSET_P (mask, regs[i]))
8227 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8228 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8229 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8230 is true for all indexes (X, SIZE). */
8233 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8234 unsigned int size, unsigned int *num_regs_ptr)
8238 i = mips16e_find_first_register (*mask_ptr, regs, size);
8239 for (i++; i < size; i++)
8240 if (!BITSET_P (*mask_ptr, regs[i]))
8243 *mask_ptr |= 1 << regs[i];
8247 /* Return a simplified form of X using the register values in REG_VALUES.
8248 REG_VALUES[R] is the last value assigned to hard register R, or null
8249 if R has not been modified.
8251 This function is rather limited, but is good enough for our purposes. */
8254 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8256 x = avoid_constant_pool_reference (x);
8260 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8261 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8262 x0, GET_MODE (XEXP (x, 0)));
8265 if (ARITHMETIC_P (x))
8267 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8268 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8269 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8273 && reg_values[REGNO (x)]
8274 && !rtx_unstable_p (reg_values[REGNO (x)]))
8275 return reg_values[REGNO (x)];
8280 /* Return true if (set DEST SRC) stores an argument register into its
8281 caller-allocated save slot, storing the number of that argument
8282 register in *REGNO_PTR if so. REG_VALUES is as for
8283 mips16e_collect_propagate_value. */
8286 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8287 unsigned int *regno_ptr)
8289 unsigned int argno, regno;
8290 HOST_WIDE_INT offset, required_offset;
8293 /* Check that this is a word-mode store. */
8294 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8297 /* Check that the register being saved is an unmodified argument
8299 regno = REGNO (src);
8300 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8302 argno = regno - GP_ARG_FIRST;
8304 /* Check whether the address is an appropriate stack-pointer or
8305 frame-pointer access. */
8306 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8307 mips_split_plus (addr, &base, &offset);
8308 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8309 if (base == hard_frame_pointer_rtx)
8310 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8311 else if (base != stack_pointer_rtx)
8313 if (offset != required_offset)
8320 /* A subroutine of mips_expand_prologue, called only when generating
8321 MIPS16e SAVE instructions. Search the start of the function for any
8322 instructions that save argument registers into their caller-allocated
8323 save slots. Delete such instructions and return a value N such that
8324 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8325 instructions redundant. */
8328 mips16e_collect_argument_saves (void)
8330 rtx reg_values[FIRST_PSEUDO_REGISTER];
8331 rtx insn, next, set, dest, src;
8332 unsigned int nargs, regno;
8334 push_topmost_sequence ();
8336 memset (reg_values, 0, sizeof (reg_values));
8337 for (insn = get_insns (); insn; insn = next)
8339 next = NEXT_INSN (insn);
8340 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8346 set = PATTERN (insn);
8347 if (GET_CODE (set) != SET)
8350 dest = SET_DEST (set);
8351 src = SET_SRC (set);
8352 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8354 if (!BITSET_P (cfun->machine->frame.mask, regno))
8357 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8360 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8361 reg_values[REGNO (dest)]
8362 = mips16e_collect_propagate_value (src, reg_values);
8366 pop_topmost_sequence ();
8371 /* Return a move between register REGNO and memory location SP + OFFSET.
8372 Make the move a load if RESTORE_P, otherwise make it a frame-related
8376 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8381 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8382 reg = gen_rtx_REG (SImode, regno);
8384 ? gen_rtx_SET (VOIDmode, reg, mem)
8385 : mips_frame_set (mem, reg));
8388 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8389 The instruction must:
8391 - Allocate or deallocate SIZE bytes in total; SIZE is known
8394 - Save or restore as many registers in *MASK_PTR as possible.
8395 The instruction saves the first registers at the top of the
8396 allocated area, with the other registers below it.
8398 - Save NARGS argument registers above the allocated area.
8400 (NARGS is always zero if RESTORE_P.)
8402 The SAVE and RESTORE instructions cannot save and restore all general
8403 registers, so there may be some registers left over for the caller to
8404 handle. Destructively modify *MASK_PTR so that it contains the registers
8405 that still need to be saved or restored. The caller can save these
8406 registers in the memory immediately below *OFFSET_PTR, which is a
8407 byte offset from the bottom of the allocated stack area. */
8410 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8411 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8415 HOST_WIDE_INT offset, top_offset;
8416 unsigned int i, regno;
8419 gcc_assert (cfun->machine->frame.num_fp == 0);
8421 /* Calculate the number of elements in the PARALLEL. We need one element
8422 for the stack adjustment, one for each argument register save, and one
8423 for each additional register move. */
8425 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8426 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8429 /* Create the final PARALLEL. */
8430 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8433 /* Add the stack pointer adjustment. */
8434 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8435 plus_constant (stack_pointer_rtx,
8436 restore_p ? size : -size));
8437 RTX_FRAME_RELATED_P (set) = 1;
8438 XVECEXP (pattern, 0, n++) = set;
8440 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8441 top_offset = restore_p ? size : 0;
8443 /* Save the arguments. */
8444 for (i = 0; i < nargs; i++)
8446 offset = top_offset + i * UNITS_PER_WORD;
8447 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8448 XVECEXP (pattern, 0, n++) = set;
8451 /* Then fill in the other register moves. */
8452 offset = top_offset;
8453 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8455 regno = mips16e_save_restore_regs[i];
8456 if (BITSET_P (*mask_ptr, regno))
8458 offset -= UNITS_PER_WORD;
8459 set = mips16e_save_restore_reg (restore_p, offset, regno);
8460 XVECEXP (pattern, 0, n++) = set;
8461 *mask_ptr &= ~(1 << regno);
8465 /* Tell the caller what offset it should use for the remaining registers. */
8466 *offset_ptr = size + (offset - top_offset);
8468 gcc_assert (n == XVECLEN (pattern, 0));
8473 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8474 pointer. Return true if PATTERN matches the kind of instruction
8475 generated by mips16e_build_save_restore. If INFO is nonnull,
8476 initialize it when returning true. */
8479 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8480 struct mips16e_save_restore_info *info)
8482 unsigned int i, nargs, mask, extra;
8483 HOST_WIDE_INT top_offset, save_offset, offset;
8484 rtx set, reg, mem, base;
8487 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8490 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8491 top_offset = adjust > 0 ? adjust : 0;
8493 /* Interpret all other members of the PARALLEL. */
8494 save_offset = top_offset - UNITS_PER_WORD;
8498 for (n = 1; n < XVECLEN (pattern, 0); n++)
8500 /* Check that we have a SET. */
8501 set = XVECEXP (pattern, 0, n);
8502 if (GET_CODE (set) != SET)
8505 /* Check that the SET is a load (if restoring) or a store
8507 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8511 /* Check that the address is the sum of the stack pointer and a
8512 possibly-zero constant offset. */
8513 mips_split_plus (XEXP (mem, 0), &base, &offset);
8514 if (base != stack_pointer_rtx)
8517 /* Check that SET's other operand is a register. */
8518 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8522 /* Check for argument saves. */
8523 if (offset == top_offset + nargs * UNITS_PER_WORD
8524 && REGNO (reg) == GP_ARG_FIRST + nargs)
8526 else if (offset == save_offset)
8528 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8529 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8532 mask |= 1 << REGNO (reg);
8533 save_offset -= UNITS_PER_WORD;
8539 /* Check that the restrictions on register ranges are met. */
8541 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8542 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8543 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8544 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8548 /* Make sure that the topmost argument register is not saved twice.
8549 The checks above ensure that the same is then true for the other
8550 argument registers. */
8551 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8554 /* Pass back information, if requested. */
8557 info->nargs = nargs;
8559 info->size = (adjust > 0 ? adjust : -adjust);
8565 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8566 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8567 the null terminator. */
8570 mips16e_add_register_range (char *s, unsigned int min_reg,
8571 unsigned int max_reg)
8573 if (min_reg != max_reg)
8574 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8576 s += sprintf (s, ",%s", reg_names[min_reg]);
8580 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8581 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8584 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8586 static char buffer[300];
8588 struct mips16e_save_restore_info info;
8589 unsigned int i, end;
8592 /* Parse the pattern. */
8593 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8596 /* Add the mnemonic. */
8597 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8600 /* Save the arguments. */
8602 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8603 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8604 else if (info.nargs == 1)
8605 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8607 /* Emit the amount of stack space to allocate or deallocate. */
8608 s += sprintf (s, "%d", (int) info.size);
8610 /* Save or restore $16. */
8611 if (BITSET_P (info.mask, 16))
8612 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8614 /* Save or restore $17. */
8615 if (BITSET_P (info.mask, 17))
8616 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8618 /* Save or restore registers in the range $s2...$s8, which
8619 mips16e_s2_s8_regs lists in decreasing order. Note that this
8620 is a software register range; the hardware registers are not
8621 numbered consecutively. */
8622 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8623 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8625 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8626 mips16e_s2_s8_regs[i]);
8628 /* Save or restore registers in the range $a0...$a3. */
8629 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8630 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8632 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8633 mips16e_a0_a3_regs[end - 1]);
8635 /* Save or restore $31. */
8636 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8637 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8642 /* Return true if the current function returns its value in a floating-point
8643 register in MIPS16 mode. */
8646 mips16_cfun_returns_in_fpr_p (void)
8648 tree return_type = DECL_RESULT (current_function_decl);
8649 return (TARGET_MIPS16
8650 && TARGET_HARD_FLOAT_ABI
8651 && !aggregate_value_p (return_type, current_function_decl)
8652 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8655 /* Return true if predicate PRED is true for at least one instruction.
8656 Cache the result in *CACHE, and assume that the result is true
8657 if *CACHE is already true. */
8660 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8666 push_topmost_sequence ();
8667 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8668 if (USEFUL_INSN_P (insn) && pred (insn))
8673 pop_topmost_sequence ();
8678 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8679 See mips_cfun_has_inflexible_gp_ref_p for details. */
8682 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8684 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8685 indicate that the target could be a traditional MIPS
8686 lazily-binding stub. */
8687 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8690 /* Return true if the current function refers to the global pointer
8691 in a way that forces $28 to be valid. This means that we can't
8692 change the choice of global pointer, even for NewABI code.
8694 One example of this (and one which needs several checks) is that
8695 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8696 (This restriction does not apply to PLTs.) */
8699 mips_cfun_has_inflexible_gp_ref_p (void)
8701 /* If the function has a nonlocal goto, $28 must hold the correct
8702 global pointer for the target function. That is, the target
8703 of the goto implicitly uses $28. */
8704 if (crtl->has_nonlocal_goto)
8707 if (TARGET_ABICALLS_PIC2)
8709 /* Symbolic accesses implicitly use the global pointer unless
8710 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8711 might go to traditional MIPS lazy-binding stubs. */
8712 if (!TARGET_EXPLICIT_RELOCS)
8715 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8716 can be lazily-bound. */
8720 /* MIPS16 functions that return in FPRs need to call an
8721 external libgcc routine. This call is only made explict
8722 during mips_expand_epilogue, and it too might be lazily bound. */
8723 if (mips16_cfun_returns_in_fpr_p ())
8727 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8728 mips_insn_has_inflexible_gp_ref_p);
8731 /* Return true if INSN refers to the global pointer in a "flexible" way.
8732 See mips_cfun_has_flexible_gp_ref_p for details. */
8735 mips_insn_has_flexible_gp_ref_p (rtx insn)
8737 return (get_attr_got (insn) != GOT_UNSET
8738 || mips_small_data_pattern_p (PATTERN (insn))
8739 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8742 /* Return true if the current function references the global pointer,
8743 but if those references do not inherently require the global pointer
8744 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8747 mips_cfun_has_flexible_gp_ref_p (void)
8749 /* Reload can sometimes introduce constant pool references
8750 into a function that otherwise didn't need them. For example,
8751 suppose we have an instruction like:
8753 (set (reg:DF R1) (float:DF (reg:SI R2)))
8755 If R2 turns out to be a constant such as 1, the instruction may
8756 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8757 the option of using this constant if R2 doesn't get allocated
8760 In cases like these, reload will have added the constant to the
8761 pool but no instruction will yet refer to it. */
8762 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8765 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8766 mips_insn_has_flexible_gp_ref_p);
8769 /* Return the register that should be used as the global pointer
8770 within this function. Return INVALID_REGNUM if the function
8771 doesn't need a global pointer. */
8774 mips_global_pointer (void)
8778 /* $gp is always available unless we're using a GOT. */
8779 if (!TARGET_USE_GOT)
8780 return GLOBAL_POINTER_REGNUM;
8782 /* If there are inflexible references to $gp, we must use the
8783 standard register. */
8784 if (mips_cfun_has_inflexible_gp_ref_p ())
8785 return GLOBAL_POINTER_REGNUM;
8787 /* If there are no current references to $gp, then the only uses
8788 we can introduce later are those involved in long branches. */
8789 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8790 return INVALID_REGNUM;
8792 /* If the global pointer is call-saved, try to use a call-clobbered
8794 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8795 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8796 if (!df_regs_ever_live_p (regno)
8797 && call_really_used_regs[regno]
8798 && !fixed_regs[regno]
8799 && regno != PIC_FUNCTION_ADDR_REGNUM)
8802 return GLOBAL_POINTER_REGNUM;
8805 /* Return true if the current function's prologue must load the global
8806 pointer value into pic_offset_table_rtx and store the same value in
8807 the function's cprestore slot (if any).
8809 One problem we have to deal with is that, when emitting GOT-based
8810 position independent code, long-branch sequences will need to load
8811 the address of the branch target from the GOT. We don't know until
8812 the very end of compilation whether (and where) the function needs
8813 long branches, so we must ensure that _any_ branch can access the
8814 global pointer in some form. However, we do not want to pessimize
8815 the usual case in which all branches are short.
8817 We handle this as follows:
8819 (1) During reload, we set cfun->machine->global_pointer to
8820 INVALID_REGNUM if we _know_ that the current function
8821 doesn't need a global pointer. This is only valid if
8822 long branches don't need the GOT.
8824 Otherwise, we assume that we might need a global pointer
8825 and pick an appropriate register.
8827 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8828 we ensure that the global pointer is available at every
8829 block boundary bar entry and exit. We do this in one of two ways:
8831 - If the function has a cprestore slot, we ensure that this
8832 slot is valid at every branch. However, as explained in
8833 point (6) below, there is no guarantee that pic_offset_table_rtx
8834 itself is valid if new uses of the global pointer are introduced
8835 after the first post-epilogue split.
8837 We guarantee that the cprestore slot is valid by loading it
8838 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8839 this register live at every block boundary bar function entry
8840 and exit. It is then invalid to move the load (and thus the
8841 preceding store) across a block boundary.
8843 - If the function has no cprestore slot, we guarantee that
8844 pic_offset_table_rtx itself is valid at every branch.
8846 See mips_eh_uses for the handling of the register liveness.
8848 (3) During prologue and epilogue generation, we emit "ghost"
8849 placeholder instructions to manipulate the global pointer.
8851 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8852 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8853 that the function needs a global pointer. (There is no need to set
8854 them earlier than this, and doing it as late as possible leads to
8855 fewer false positives.)
8857 (5) If cfun->machine->must_initialize_gp_p is true during a
8858 split_insns pass, we split the ghost instructions into real
8859 instructions. These split instructions can then be optimized in
8860 the usual way. Otherwise, we keep the ghost instructions intact,
8861 and optimize for the case where they aren't needed. We still
8862 have the option of splitting them later, if we need to introduce
8863 new uses of the global pointer.
8865 For example, the scheduler ignores a ghost instruction that
8866 stores $28 to the stack, but it handles the split form of
8867 the ghost instruction as an ordinary store.
8869 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8870 is true during the first post-epilogue split_insns pass, we split
8871 calls and restore_gp patterns into instructions that explicitly
8872 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8873 we split these patterns into instructions that _don't_ load from
8876 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8877 time of the split, then any instructions that exist at that time
8878 can make free use of pic_offset_table_rtx. However, if we want
8879 to introduce new uses of the global pointer after the split,
8880 we must explicitly load the value from the cprestore slot, since
8881 pic_offset_table_rtx itself might not be valid at a given point
8884 The idea is that we want to be able to delete redundant
8885 loads from the cprestore slot in the usual case where no
8886 long branches are needed.
8888 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8889 of md_reorg, we decide whether the global pointer is needed for
8890 long branches. If so, we set cfun->machine->must_initialize_gp_p
8891 to true and split the ghost instructions into real instructions
8894 Note that the ghost instructions must have a zero length for three reasons:
8896 - Giving the length of the underlying $gp sequence might cause
8897 us to use long branches in cases where they aren't really needed.
8899 - They would perturb things like alignment calculations.
8901 - More importantly, the hazard detection in md_reorg relies on
8902 empty instructions having a zero length.
8904 If we find a long branch and split the ghost instructions at the
8905 end of md_reorg, the split could introduce more long branches.
8906 That isn't a problem though, because we still do the split before
8907 the final shorten_branches pass.
8909 This is extremely ugly, but it seems like the best compromise between
8910 correctness and efficiency. */
8913 mips_must_initialize_gp_p (void)
8915 return cfun->machine->must_initialize_gp_p;
8918 /* Return true if REGNO is a register that is ordinarily call-clobbered
8919 but must nevertheless be preserved by an interrupt handler. */
8922 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8924 if (MD_REG_P (regno))
8927 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8930 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8932 /* $0 is hard-wired. */
8933 if (regno == GP_REG_FIRST)
8936 /* The interrupt handler can treat kernel registers as
8937 scratch registers. */
8938 if (KERNEL_REG_P (regno))
8941 /* The function will return the stack pointer to its original value
8943 if (regno == STACK_POINTER_REGNUM)
8946 /* Otherwise, return true for registers that aren't ordinarily
8948 return call_really_used_regs[regno];
8954 /* Return true if the current function should treat register REGNO
8958 mips_cfun_call_saved_reg_p (unsigned int regno)
8960 /* Interrupt handlers need to save extra registers. */
8961 if (cfun->machine->interrupt_handler_p
8962 && mips_interrupt_extra_call_saved_reg_p (regno))
8965 /* call_insns preserve $28 unless they explicitly say otherwise,
8966 so call_really_used_regs[] treats $28 as call-saved. However,
8967 we want the ABI property rather than the default call_insn
8969 return (regno == GLOBAL_POINTER_REGNUM
8970 ? TARGET_CALL_SAVED_GP
8971 : !call_really_used_regs[regno]);
8974 /* Return true if the function body might clobber register REGNO.
8975 We know that REGNO is call-saved. */
8978 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
8980 /* Some functions should be treated as clobbering all call-saved
8982 if (crtl->saves_all_registers)
8985 /* DF handles cases where a register is explicitly referenced in
8986 the rtl. Incoming values are passed in call-clobbered registers,
8987 so we can assume that any live call-saved register is set within
8989 if (df_regs_ever_live_p (regno))
8992 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8993 These clobbers are not explicit in the rtl. */
8994 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8997 /* If we're using a call-saved global pointer, the function's
8998 prologue will need to set it up. */
8999 if (cfun->machine->global_pointer == regno)
9002 /* The function's prologue will need to set the frame pointer if
9003 frame_pointer_needed. */
9004 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9007 /* If a MIPS16 function returns a value in FPRs, its epilogue
9008 will need to call an external libgcc routine. This yet-to-be
9009 generated call_insn will clobber $31. */
9010 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9013 /* If REGNO is ordinarily call-clobbered, we must assume that any
9014 called function could modify it. */
9015 if (cfun->machine->interrupt_handler_p
9016 && !current_function_is_leaf
9017 && mips_interrupt_extra_call_saved_reg_p (regno))
9023 /* Return true if the current function must save register REGNO. */
9026 mips_save_reg_p (unsigned int regno)
9028 if (mips_cfun_call_saved_reg_p (regno))
9030 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9033 /* Save both registers in an FPR pair if either one is used. This is
9034 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9035 register to be used without the even register. */
9036 if (FP_REG_P (regno)
9037 && MAX_FPRS_PER_FMT == 2
9038 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9042 /* We need to save the incoming return address if __builtin_eh_return
9043 is being used to set a different return address. */
9044 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9050 /* Populate the current function's mips_frame_info structure.
9052 MIPS stack frames look like:
9054 +-------------------------------+
9056 | incoming stack arguments |
9058 +-------------------------------+
9060 | caller-allocated save area |
9061 A | for register arguments |
9063 +-------------------------------+ <-- incoming stack pointer
9065 | callee-allocated save area |
9066 B | for arguments that are |
9067 | split between registers and |
9070 +-------------------------------+ <-- arg_pointer_rtx
9072 C | callee-allocated save area |
9073 | for register varargs |
9075 +-------------------------------+ <-- frame_pointer_rtx
9076 | | + cop0_sp_offset
9077 | COP0 reg save area | + UNITS_PER_WORD
9079 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9080 | | + UNITS_PER_WORD
9081 | accumulator save area |
9083 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9084 | | + UNITS_PER_HWFPVALUE
9087 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9088 | | + UNITS_PER_WORD
9091 +-------------------------------+ <-- frame_pointer_rtx with
9092 | | \ -fstack-protector
9093 | local variables | | var_size
9095 +-------------------------------+
9097 | $gp save area | | cprestore_size
9099 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9101 | outgoing stack arguments | |
9103 +-------------------------------+ | args_size
9105 | caller-allocated save area | |
9106 | for register arguments | |
9108 +-------------------------------+ <-- stack_pointer_rtx
9109 frame_pointer_rtx without
9111 hard_frame_pointer_rtx for
9114 At least two of A, B and C will be empty.
9116 Dynamic stack allocations such as alloca insert data at point P.
9117 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9118 hard_frame_pointer_rtx unchanged. */
9121 mips_compute_frame_info (void)
9123 struct mips_frame_info *frame;
9124 HOST_WIDE_INT offset, size;
9125 unsigned int regno, i;
9127 /* Set this function's interrupt properties. */
9128 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9131 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9132 else if (TARGET_HARD_FLOAT)
9133 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9134 else if (TARGET_MIPS16)
9135 error ("interrupt handlers cannot be MIPS16 functions");
9138 cfun->machine->interrupt_handler_p = true;
9139 cfun->machine->use_shadow_register_set_p =
9140 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9141 cfun->machine->keep_interrupts_masked_p =
9142 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9143 cfun->machine->use_debug_exception_return_p =
9144 mips_use_debug_exception_return_p (TREE_TYPE
9145 (current_function_decl));
9149 frame = &cfun->machine->frame;
9150 memset (frame, 0, sizeof (*frame));
9151 size = get_frame_size ();
9153 cfun->machine->global_pointer = mips_global_pointer ();
9155 /* The first two blocks contain the outgoing argument area and the $gp save
9156 slot. This area isn't needed in leaf functions, but if the
9157 target-independent frame size is nonzero, we have already committed to
9158 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9159 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9161 /* The MIPS 3.0 linker does not like functions that dynamically
9162 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9163 looks like we are trying to create a second frame pointer to the
9164 function, so allocate some stack space to make it happy. */
9165 if (cfun->calls_alloca)
9166 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9168 frame->args_size = 0;
9169 frame->cprestore_size = 0;
9173 frame->args_size = crtl->outgoing_args_size;
9174 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9176 offset = frame->args_size + frame->cprestore_size;
9178 /* Move above the local variables. */
9179 frame->var_size = MIPS_STACK_ALIGN (size);
9180 offset += frame->var_size;
9182 /* Find out which GPRs we need to save. */
9183 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9184 if (mips_save_reg_p (regno))
9187 frame->mask |= 1 << (regno - GP_REG_FIRST);
9190 /* If this function calls eh_return, we must also save and restore the
9191 EH data registers. */
9192 if (crtl->calls_eh_return)
9193 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9196 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9199 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9200 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9201 save all later registers too. */
9202 if (GENERATE_MIPS16E_SAVE_RESTORE)
9204 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9205 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9206 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9207 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9210 /* Move above the GPR save area. */
9211 if (frame->num_gp > 0)
9213 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9214 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9217 /* Find out which FPRs we need to save. This loop must iterate over
9218 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9219 if (TARGET_HARD_FLOAT)
9220 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9221 if (mips_save_reg_p (regno))
9223 frame->num_fp += MAX_FPRS_PER_FMT;
9224 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9227 /* Move above the FPR save area. */
9228 if (frame->num_fp > 0)
9230 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9231 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9234 /* Add in space for the interrupt context information. */
9235 if (cfun->machine->interrupt_handler_p)
9238 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9241 frame->acc_mask |= (1 << 0);
9244 /* Check accumulators 1, 2, 3. */
9245 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9246 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9249 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9252 /* All interrupt context functions need space to preserve STATUS. */
9253 frame->num_cop0_regs++;
9255 /* If we don't keep interrupts masked, we need to save EPC. */
9256 if (!cfun->machine->keep_interrupts_masked_p)
9257 frame->num_cop0_regs++;
9260 /* Move above the accumulator save area. */
9261 if (frame->num_acc > 0)
9263 /* Each accumulator needs 2 words. */
9264 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9265 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9268 /* Move above the COP0 register save area. */
9269 if (frame->num_cop0_regs > 0)
9271 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9272 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9275 /* Move above the callee-allocated varargs save area. */
9276 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9277 frame->arg_pointer_offset = offset;
9279 /* Move above the callee-allocated area for pretend stack arguments. */
9280 offset += crtl->args.pretend_args_size;
9281 frame->total_size = offset;
9283 /* Work out the offsets of the save areas from the top of the frame. */
9284 if (frame->gp_sp_offset > 0)
9285 frame->gp_save_offset = frame->gp_sp_offset - offset;
9286 if (frame->fp_sp_offset > 0)
9287 frame->fp_save_offset = frame->fp_sp_offset - offset;
9288 if (frame->acc_sp_offset > 0)
9289 frame->acc_save_offset = frame->acc_sp_offset - offset;
9290 if (frame->num_cop0_regs > 0)
9291 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9293 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9294 arguments. This tends to increase the chances of using unextended
9295 instructions for local variables and incoming arguments. */
9297 frame->hard_frame_pointer_offset = frame->args_size;
9300 /* Return the style of GP load sequence that is being used for the
9301 current function. */
9303 enum mips_loadgp_style
9304 mips_current_loadgp_style (void)
9306 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9312 if (TARGET_ABSOLUTE_ABICALLS)
9313 return LOADGP_ABSOLUTE;
9315 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9318 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9321 mips_frame_pointer_required (void)
9323 /* If the function contains dynamic stack allocations, we need to
9324 use the frame pointer to access the static parts of the frame. */
9325 if (cfun->calls_alloca)
9328 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9329 reload may be unable to compute the address of a local variable,
9330 since there is no way to add a large constant to the stack pointer
9331 without using a second temporary register. */
9334 mips_compute_frame_info ();
9335 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9342 /* Make sure that we're not trying to eliminate to the wrong hard frame
9346 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9348 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9351 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9352 or argument pointer. TO is either the stack pointer or hard frame
9356 mips_initial_elimination_offset (int from, int to)
9358 HOST_WIDE_INT offset;
9360 mips_compute_frame_info ();
9362 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9365 case FRAME_POINTER_REGNUM:
9366 if (FRAME_GROWS_DOWNWARD)
9367 offset = (cfun->machine->frame.args_size
9368 + cfun->machine->frame.cprestore_size
9369 + cfun->machine->frame.var_size);
9374 case ARG_POINTER_REGNUM:
9375 offset = cfun->machine->frame.arg_pointer_offset;
9382 if (to == HARD_FRAME_POINTER_REGNUM)
9383 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9388 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9391 mips_extra_live_on_entry (bitmap regs)
9395 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9396 the global pointer. */
9397 if (!TARGET_ABSOLUTE_ABICALLS)
9398 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9400 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9401 the global pointer. */
9403 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9405 /* See the comment above load_call<mode> for details. */
9406 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9410 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9414 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9419 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9422 /* Emit code to change the current function's return address to
9423 ADDRESS. SCRATCH is available as a scratch register, if needed.
9424 ADDRESS and SCRATCH are both word-mode GPRs. */
9427 mips_set_return_address (rtx address, rtx scratch)
9431 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9432 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9433 cfun->machine->frame.gp_sp_offset);
9434 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9437 /* Return true if the current function has a cprestore slot. */
9440 mips_cfun_has_cprestore_slot_p (void)
9442 return (cfun->machine->global_pointer != INVALID_REGNUM
9443 && cfun->machine->frame.cprestore_size > 0);
9446 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9447 cprestore slot. LOAD_P is true if the caller wants to load from
9448 the cprestore slot; it is false if the caller wants to store to
9452 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9455 const struct mips_frame_info *frame;
9457 frame = &cfun->machine->frame;
9458 /* .cprestore always uses the stack pointer instead of the frame pointer.
9459 We have a free choice for direct stores for non-MIPS16 functions,
9460 and for MIPS16 functions whose cprestore slot is in range of the
9461 stack pointer. Using the stack pointer would sometimes give more
9462 (early) scheduling freedom, but using the frame pointer would
9463 sometimes give more (late) scheduling freedom. It's hard to
9464 predict which applies to a given function, so let's keep things
9467 Loads must always use the frame pointer in functions that call
9468 alloca, and there's little benefit to using the stack pointer
9470 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9472 *base = hard_frame_pointer_rtx;
9473 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9477 *base = stack_pointer_rtx;
9478 *offset = frame->args_size;
9482 /* Return true if X is the load or store address of the cprestore slot;
9483 LOAD_P says which. */
9486 mips_cprestore_address_p (rtx x, bool load_p)
9488 rtx given_base, required_base;
9489 HOST_WIDE_INT given_offset, required_offset;
9491 mips_split_plus (x, &given_base, &given_offset);
9492 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9493 return given_base == required_base && given_offset == required_offset;
9496 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9497 going to load from it, false if we are going to store to it.
9498 Use TEMP as a temporary register if need be. */
9501 mips_cprestore_slot (rtx temp, bool load_p)
9504 HOST_WIDE_INT offset;
9506 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9507 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9510 /* Emit instructions to save global pointer value GP into cprestore
9511 slot MEM. OFFSET is the offset that MEM applies to the base register.
9513 MEM may not be a legitimate address. If it isn't, TEMP is a
9514 temporary register that can be used, otherwise it is a SCRATCH. */
9517 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9519 if (TARGET_CPRESTORE_DIRECTIVE)
9521 gcc_assert (gp == pic_offset_table_rtx);
9522 emit_insn (gen_cprestore (mem, offset));
9525 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9528 /* Restore $gp from its save slot, using TEMP as a temporary base register
9529 if need be. This function is for o32 and o64 abicalls only.
9531 See mips_must_initialize_gp_p for details about how we manage the
9535 mips_restore_gp_from_cprestore_slot (rtx temp)
9537 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9539 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9541 emit_note (NOTE_INSN_DELETED);
9547 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9548 mips_emit_move (pic_offset_table_rtx, temp);
9551 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9552 if (!TARGET_EXPLICIT_RELOCS)
9553 emit_insn (gen_blockage ());
9556 /* A function to save or store a register. The first argument is the
9557 register and the second is the stack slot. */
9558 typedef void (*mips_save_restore_fn) (rtx, rtx);
9560 /* Use FN to save or restore register REGNO. MODE is the register's
9561 mode and OFFSET is the offset of its save slot from the current
9565 mips_save_restore_reg (enum machine_mode mode, int regno,
9566 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9570 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9571 fn (gen_rtx_REG (mode, regno), mem);
9574 /* Call FN for each accumlator that is saved by the current function.
9575 SP_OFFSET is the offset of the current stack pointer from the start
9579 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9581 HOST_WIDE_INT offset;
9584 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9585 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9587 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9588 offset -= UNITS_PER_WORD;
9589 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9590 offset -= UNITS_PER_WORD;
9593 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9594 if (BITSET_P (cfun->machine->frame.acc_mask,
9595 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9597 mips_save_restore_reg (word_mode, regno, offset, fn);
9598 offset -= UNITS_PER_WORD;
9602 /* Call FN for each register that is saved by the current function.
9603 SP_OFFSET is the offset of the current stack pointer from the start
9607 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9608 mips_save_restore_fn fn)
9610 enum machine_mode fpr_mode;
9611 HOST_WIDE_INT offset;
9614 /* Save registers starting from high to low. The debuggers prefer at least
9615 the return register be stored at func+4, and also it allows us not to
9616 need a nop in the epilogue if at least one register is reloaded in
9617 addition to return address. */
9618 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9619 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9620 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9622 mips_save_restore_reg (word_mode, regno, offset, fn);
9623 offset -= UNITS_PER_WORD;
9626 /* This loop must iterate over the same space as its companion in
9627 mips_compute_frame_info. */
9628 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9629 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9630 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9631 regno >= FP_REG_FIRST;
9632 regno -= MAX_FPRS_PER_FMT)
9633 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9635 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9636 offset -= GET_MODE_SIZE (fpr_mode);
9640 /* Return true if a move between register REGNO and its save slot (MEM)
9641 can be done in a single move. LOAD_P is true if we are loading
9642 from the slot, false if we are storing to it. */
9645 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9647 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9648 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9651 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9652 GET_MODE (mem), mem, load_p) == NO_REGS;
9655 /* Emit a move from SRC to DEST, given that one of them is a register
9656 save slot and that the other is a register. TEMP is a temporary
9657 GPR of the same mode that is available if need be. */
9660 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9667 regno = REGNO (src);
9672 regno = REGNO (dest);
9676 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9678 /* We don't yet know whether we'll need this instruction or not.
9679 Postpone the decision by emitting a ghost move. This move
9680 is specifically not frame-related; only the split version is. */
9682 emit_insn (gen_move_gpdi (dest, src));
9684 emit_insn (gen_move_gpsi (dest, src));
9688 if (regno == HI_REGNUM)
9692 mips_emit_move (temp, src);
9694 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9695 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9697 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9698 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9703 emit_insn (gen_mfhidi_ti (temp,
9704 gen_rtx_REG (TImode, MD_REG_FIRST)));
9706 emit_insn (gen_mfhisi_di (temp,
9707 gen_rtx_REG (DImode, MD_REG_FIRST)));
9708 mips_emit_move (dest, temp);
9711 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9712 mips_emit_move (dest, src);
9715 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9716 mips_emit_move (temp, src);
9717 mips_emit_move (dest, temp);
9720 mips_set_frame_expr (mips_frame_set (dest, src));
9723 /* If we're generating n32 or n64 abicalls, and the current function
9724 does not use $28 as its global pointer, emit a cplocal directive.
9725 Use pic_offset_table_rtx as the argument to the directive. */
9728 mips_output_cplocal (void)
9730 if (!TARGET_EXPLICIT_RELOCS
9731 && mips_must_initialize_gp_p ()
9732 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9733 output_asm_insn (".cplocal %+", 0);
9736 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9739 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9743 #ifdef SDB_DEBUGGING_INFO
9744 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9745 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9748 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9749 floating-point arguments. */
9751 && TARGET_HARD_FLOAT_ABI
9752 && crtl->args.info.fp_code != 0)
9753 mips16_build_function_stub ();
9755 /* Get the function name the same way that toplev.c does before calling
9756 assemble_start_function. This is needed so that the name used here
9757 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9758 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9759 mips_start_function_definition (fnname, TARGET_MIPS16);
9761 /* Stop mips_file_end from treating this function as external. */
9762 if (TARGET_IRIX && mips_abi == ABI_32)
9763 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
9765 /* Output MIPS-specific frame information. */
9766 if (!flag_inhibit_size_directive)
9768 const struct mips_frame_info *frame;
9770 frame = &cfun->machine->frame;
9772 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9774 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9775 "# vars= " HOST_WIDE_INT_PRINT_DEC
9777 ", args= " HOST_WIDE_INT_PRINT_DEC
9778 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9779 reg_names[frame_pointer_needed
9780 ? HARD_FRAME_POINTER_REGNUM
9781 : STACK_POINTER_REGNUM],
9782 (frame_pointer_needed
9783 ? frame->total_size - frame->hard_frame_pointer_offset
9784 : frame->total_size),
9785 reg_names[RETURN_ADDR_REGNUM],
9787 frame->num_gp, frame->num_fp,
9789 frame->cprestore_size);
9791 /* .mask MASK, OFFSET. */
9792 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9793 frame->mask, frame->gp_save_offset);
9795 /* .fmask MASK, OFFSET. */
9796 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9797 frame->fmask, frame->fp_save_offset);
9800 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9801 Also emit the ".set noreorder; .set nomacro" sequence for functions
9803 if (mips_must_initialize_gp_p ()
9804 && mips_current_loadgp_style () == LOADGP_OLDABI)
9808 /* This is a fixed-form sequence. The position of the
9809 first two instructions is important because of the
9810 way _gp_disp is defined. */
9811 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9812 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9813 output_asm_insn ("sll\t$2,16", 0);
9814 output_asm_insn ("addu\t$2,$3", 0);
9818 /* .cpload must be in a .set noreorder but not a
9819 .set nomacro block. */
9820 mips_push_asm_switch (&mips_noreorder);
9821 output_asm_insn (".cpload\t%^", 0);
9822 if (!cfun->machine->all_noreorder_p)
9823 mips_pop_asm_switch (&mips_noreorder);
9825 mips_push_asm_switch (&mips_nomacro);
9828 else if (cfun->machine->all_noreorder_p)
9830 mips_push_asm_switch (&mips_noreorder);
9831 mips_push_asm_switch (&mips_nomacro);
9834 /* Tell the assembler which register we're using as the global
9835 pointer. This is needed for thunks, since they can use either
9836 explicit relocs or assembler macros. */
9837 mips_output_cplocal ();
9840 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9843 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9844 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9848 /* Reinstate the normal $gp. */
9849 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9850 mips_output_cplocal ();
9852 if (cfun->machine->all_noreorder_p)
9854 mips_pop_asm_switch (&mips_nomacro);
9855 mips_pop_asm_switch (&mips_noreorder);
9858 /* Get the function name the same way that toplev.c does before calling
9859 assemble_start_function. This is needed so that the name used here
9860 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9861 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9862 mips_end_function_definition (fnname);
9865 /* Save register REG to MEM. Make the instruction frame-related. */
9868 mips_save_reg (rtx reg, rtx mem)
9870 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9874 if (mips_split_64bit_move_p (mem, reg))
9875 mips_split_doubleword_move (mem, reg);
9877 mips_emit_move (mem, reg);
9879 x1 = mips_frame_set (mips_subword (mem, false),
9880 mips_subword (reg, false));
9881 x2 = mips_frame_set (mips_subword (mem, true),
9882 mips_subword (reg, true));
9883 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9886 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9889 /* The __gnu_local_gp symbol. */
9891 static GTY(()) rtx mips_gnu_local_gp;
9893 /* If we're generating n32 or n64 abicalls, emit instructions
9894 to set up the global pointer. */
9897 mips_emit_loadgp (void)
9899 rtx addr, offset, incoming_address, base, index, pic_reg;
9901 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9902 switch (mips_current_loadgp_style ())
9904 case LOADGP_ABSOLUTE:
9905 if (mips_gnu_local_gp == NULL)
9907 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9908 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9910 emit_insn (Pmode == SImode
9911 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9912 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9916 /* Added by mips_output_function_prologue. */
9920 addr = XEXP (DECL_RTL (current_function_decl), 0);
9921 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9922 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9923 emit_insn (Pmode == SImode
9924 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9925 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9929 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9930 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9931 emit_insn (Pmode == SImode
9932 ? gen_loadgp_rtp_si (pic_reg, base, index)
9933 : gen_loadgp_rtp_di (pic_reg, base, index));
9941 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9943 /* Emit a blockage if there are implicit uses of the GP register.
9944 This includes profiled functions, because FUNCTION_PROFILE uses
9946 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9947 emit_insn (gen_loadgp_blockage ());
9950 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9953 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9955 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9958 /* Expand the "prologue" pattern. */
9961 mips_expand_prologue (void)
9963 const struct mips_frame_info *frame;
9968 if (cfun->machine->global_pointer != INVALID_REGNUM)
9970 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
9971 or implicitly. If so, we can commit to using a global pointer
9972 straight away, otherwise we need to defer the decision. */
9973 if (mips_cfun_has_inflexible_gp_ref_p ()
9974 || mips_cfun_has_flexible_gp_ref_p ())
9976 cfun->machine->must_initialize_gp_p = true;
9977 cfun->machine->must_restore_gp_when_clobbered_p = true;
9980 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9983 frame = &cfun->machine->frame;
9984 size = frame->total_size;
9986 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9987 bytes beforehand; this is enough to cover the register save area
9988 without going out of range. */
9989 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
9990 || frame->num_cop0_regs > 0)
9992 HOST_WIDE_INT step1;
9994 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9995 if (GENERATE_MIPS16E_SAVE_RESTORE)
9997 HOST_WIDE_INT offset;
9998 unsigned int mask, regno;
10000 /* Try to merge argument stores into the save instruction. */
10001 nargs = mips16e_collect_argument_saves ();
10003 /* Build the save instruction. */
10004 mask = frame->mask;
10005 insn = mips16e_build_save_restore (false, &mask, &offset,
10007 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10010 /* Check if we need to save other registers. */
10011 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10012 if (BITSET_P (mask, regno - GP_REG_FIRST))
10014 offset -= UNITS_PER_WORD;
10015 mips_save_restore_reg (word_mode, regno,
10016 offset, mips_save_reg);
10021 if (cfun->machine->interrupt_handler_p)
10023 HOST_WIDE_INT offset;
10026 /* If this interrupt is using a shadow register set, we need to
10027 get the stack pointer from the previous register set. */
10028 if (cfun->machine->use_shadow_register_set_p)
10029 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10030 stack_pointer_rtx));
10032 if (!cfun->machine->keep_interrupts_masked_p)
10034 /* Move from COP0 Cause to K0. */
10035 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10036 gen_rtx_REG (SImode,
10037 COP0_CAUSE_REG_NUM)));
10038 /* Move from COP0 EPC to K1. */
10039 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10040 gen_rtx_REG (SImode,
10041 COP0_EPC_REG_NUM)));
10044 /* Allocate the first part of the frame. */
10045 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10047 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10050 /* Start at the uppermost location for saving. */
10051 offset = frame->cop0_sp_offset - size;
10052 if (!cfun->machine->keep_interrupts_masked_p)
10054 /* Push EPC into its stack slot. */
10055 mem = gen_frame_mem (word_mode,
10056 plus_constant (stack_pointer_rtx,
10058 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10059 offset -= UNITS_PER_WORD;
10062 /* Move from COP0 Status to K1. */
10063 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10064 gen_rtx_REG (SImode,
10065 COP0_STATUS_REG_NUM)));
10067 /* Right justify the RIPL in k0. */
10068 if (!cfun->machine->keep_interrupts_masked_p)
10069 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10070 gen_rtx_REG (SImode, K0_REG_NUM),
10071 GEN_INT (CAUSE_IPL)));
10073 /* Push Status into its stack slot. */
10074 mem = gen_frame_mem (word_mode,
10075 plus_constant (stack_pointer_rtx, offset));
10076 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10077 offset -= UNITS_PER_WORD;
10079 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10080 if (!cfun->machine->keep_interrupts_masked_p)
10081 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10084 gen_rtx_REG (SImode, K0_REG_NUM)));
10086 if (!cfun->machine->keep_interrupts_masked_p)
10087 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10088 IE is already the correct value, so we don't have to do
10089 anything explicit. */
10090 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10093 gen_rtx_REG (SImode, GP_REG_FIRST)));
10095 /* Disable interrupts by clearing the KSU, ERL, EXL,
10097 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10100 gen_rtx_REG (SImode, GP_REG_FIRST)));
10104 insn = gen_add3_insn (stack_pointer_rtx,
10107 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10110 mips_for_each_saved_acc (size, mips_save_reg);
10111 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10115 /* Allocate the rest of the frame. */
10118 if (SMALL_OPERAND (-size))
10119 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10121 GEN_INT (-size)))) = 1;
10124 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10127 /* There are no instructions to add or subtract registers
10128 from the stack pointer, so use the frame pointer as a
10129 temporary. We should always be using a frame pointer
10130 in this case anyway. */
10131 gcc_assert (frame_pointer_needed);
10132 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10133 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10134 hard_frame_pointer_rtx,
10135 MIPS_PROLOGUE_TEMP (Pmode)));
10136 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10139 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10141 MIPS_PROLOGUE_TEMP (Pmode)));
10143 /* Describe the combined effect of the previous instructions. */
10144 mips_set_frame_expr
10145 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10146 plus_constant (stack_pointer_rtx, -size)));
10150 /* Set up the frame pointer, if we're using one. */
10151 if (frame_pointer_needed)
10153 HOST_WIDE_INT offset;
10155 offset = frame->hard_frame_pointer_offset;
10158 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10159 RTX_FRAME_RELATED_P (insn) = 1;
10161 else if (SMALL_OPERAND (offset))
10163 insn = gen_add3_insn (hard_frame_pointer_rtx,
10164 stack_pointer_rtx, GEN_INT (offset));
10165 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10169 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10170 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10171 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10172 hard_frame_pointer_rtx,
10173 MIPS_PROLOGUE_TEMP (Pmode)));
10174 mips_set_frame_expr
10175 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10176 plus_constant (stack_pointer_rtx, offset)));
10180 mips_emit_loadgp ();
10182 /* Initialize the $gp save slot. */
10183 if (mips_cfun_has_cprestore_slot_p ())
10185 rtx base, mem, gp, temp;
10186 HOST_WIDE_INT offset;
10188 mips_get_cprestore_base_and_offset (&base, &offset, false);
10189 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10190 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10191 temp = (SMALL_OPERAND (offset)
10192 ? gen_rtx_SCRATCH (Pmode)
10193 : MIPS_PROLOGUE_TEMP (Pmode));
10194 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10196 mips_get_cprestore_base_and_offset (&base, &offset, true);
10197 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10198 emit_insn (gen_use_cprestore (mem));
10201 /* We need to search back to the last use of K0 or K1. */
10202 if (cfun->machine->interrupt_handler_p)
10204 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10206 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10208 /* Emit a move from K1 to COP0 Status after insn. */
10209 gcc_assert (insn != NULL_RTX);
10210 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10211 gen_rtx_REG (SImode, K1_REG_NUM)),
10215 /* If we are profiling, make sure no instructions are scheduled before
10216 the call to mcount. */
10218 emit_insn (gen_blockage ());
10221 /* Emit instructions to restore register REG from slot MEM. */
10224 mips_restore_reg (rtx reg, rtx mem)
10226 /* There's no MIPS16 instruction to load $31 directly. Load into
10227 $7 instead and adjust the return insn appropriately. */
10228 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10229 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10231 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10234 /* Emit any instructions needed before a return. */
10237 mips_expand_before_return (void)
10239 /* When using a call-clobbered gp, we start out with unified call
10240 insns that include instructions to restore the gp. We then split
10241 these unified calls after reload. These split calls explicitly
10242 clobber gp, so there is no need to define
10243 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10245 For consistency, we should also insert an explicit clobber of $28
10246 before return insns, so that the post-reload optimizers know that
10247 the register is not live on exit. */
10248 if (TARGET_CALL_CLOBBERED_GP)
10249 emit_clobber (pic_offset_table_rtx);
10252 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10256 mips_expand_epilogue (bool sibcall_p)
10258 const struct mips_frame_info *frame;
10259 HOST_WIDE_INT step1, step2;
10260 rtx base, target, insn;
10262 if (!sibcall_p && mips_can_use_return_insn ())
10264 emit_jump_insn (gen_return ());
10268 /* In MIPS16 mode, if the return value should go into a floating-point
10269 register, we need to call a helper routine to copy it over. */
10270 if (mips16_cfun_returns_in_fpr_p ())
10271 mips16_copy_fpr_return_value ();
10273 /* Split the frame into two. STEP1 is the amount of stack we should
10274 deallocate before restoring the registers. STEP2 is the amount we
10275 should deallocate afterwards.
10277 Start off by assuming that no registers need to be restored. */
10278 frame = &cfun->machine->frame;
10279 step1 = frame->total_size;
10282 /* Work out which register holds the frame address. */
10283 if (!frame_pointer_needed)
10284 base = stack_pointer_rtx;
10287 base = hard_frame_pointer_rtx;
10288 step1 -= frame->hard_frame_pointer_offset;
10291 /* If we need to restore registers, deallocate as much stack as
10292 possible in the second step without going out of range. */
10293 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10294 || frame->num_cop0_regs > 0)
10296 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10300 /* Set TARGET to BASE + STEP1. */
10306 /* Get an rtx for STEP1 that we can add to BASE. */
10307 adjust = GEN_INT (step1);
10308 if (!SMALL_OPERAND (step1))
10310 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10311 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10314 /* Normal mode code can copy the result straight into $sp. */
10315 if (!TARGET_MIPS16)
10316 target = stack_pointer_rtx;
10318 emit_insn (gen_add3_insn (target, base, adjust));
10321 /* Copy TARGET into the stack pointer. */
10322 if (target != stack_pointer_rtx)
10323 mips_emit_move (stack_pointer_rtx, target);
10325 /* If we're using addressing macros, $gp is implicitly used by all
10326 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10328 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10329 emit_insn (gen_blockage ());
10331 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10333 unsigned int regno, mask;
10334 HOST_WIDE_INT offset;
10337 /* Generate the restore instruction. */
10338 mask = frame->mask;
10339 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10341 /* Restore any other registers manually. */
10342 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10343 if (BITSET_P (mask, regno - GP_REG_FIRST))
10345 offset -= UNITS_PER_WORD;
10346 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10349 /* Restore the remaining registers and deallocate the final bit
10351 emit_insn (restore);
10355 /* Restore the registers. */
10356 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10357 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10360 if (cfun->machine->interrupt_handler_p)
10362 HOST_WIDE_INT offset;
10365 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10366 if (!cfun->machine->keep_interrupts_masked_p)
10368 /* Restore the original EPC. */
10369 mem = gen_frame_mem (word_mode,
10370 plus_constant (stack_pointer_rtx, offset));
10371 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10372 offset -= UNITS_PER_WORD;
10374 /* Move to COP0 EPC. */
10375 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10376 gen_rtx_REG (SImode, K0_REG_NUM)));
10379 /* Restore the original Status. */
10380 mem = gen_frame_mem (word_mode,
10381 plus_constant (stack_pointer_rtx, offset));
10382 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10383 offset -= UNITS_PER_WORD;
10385 /* If we don't use shoadow register set, we need to update SP. */
10386 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10387 emit_insn (gen_add3_insn (stack_pointer_rtx,
10391 /* Move to COP0 Status. */
10392 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10393 gen_rtx_REG (SImode, K0_REG_NUM)));
10397 /* Deallocate the final bit of the frame. */
10399 emit_insn (gen_add3_insn (stack_pointer_rtx,
10405 /* Add in the __builtin_eh_return stack adjustment. We need to
10406 use a temporary in MIPS16 code. */
10407 if (crtl->calls_eh_return)
10411 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10412 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10413 MIPS_EPILOGUE_TEMP (Pmode),
10414 EH_RETURN_STACKADJ_RTX));
10415 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10418 emit_insn (gen_add3_insn (stack_pointer_rtx,
10420 EH_RETURN_STACKADJ_RTX));
10425 mips_expand_before_return ();
10426 if (cfun->machine->interrupt_handler_p)
10428 /* Interrupt handlers generate eret or deret. */
10429 if (cfun->machine->use_debug_exception_return_p)
10430 emit_jump_insn (gen_mips_deret ());
10432 emit_jump_insn (gen_mips_eret ());
10436 unsigned int regno;
10438 /* When generating MIPS16 code, the normal
10439 mips_for_each_saved_gpr_and_fpr path will restore the return
10440 address into $7 rather than $31. */
10442 && !GENERATE_MIPS16E_SAVE_RESTORE
10443 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10444 regno = GP_REG_FIRST + 7;
10446 regno = RETURN_ADDR_REGNUM;
10447 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10451 /* Search from the beginning to the first use of K0 or K1. */
10452 if (cfun->machine->interrupt_handler_p
10453 && !cfun->machine->keep_interrupts_masked_p)
10455 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10457 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10459 gcc_assert (insn != NULL_RTX);
10460 /* Insert disable interrupts before the first use of K0 or K1. */
10461 emit_insn_before (gen_mips_di (), insn);
10462 emit_insn_before (gen_mips_ehb (), insn);
10466 /* Return nonzero if this function is known to have a null epilogue.
10467 This allows the optimizer to omit jumps to jumps if no stack
10471 mips_can_use_return_insn (void)
10473 /* Interrupt handlers need to go through the epilogue. */
10474 if (cfun->machine->interrupt_handler_p)
10477 if (!reload_completed)
10483 /* In MIPS16 mode, a function that returns a floating-point value
10484 needs to arrange to copy the return value into the floating-point
10486 if (mips16_cfun_returns_in_fpr_p ())
10489 return cfun->machine->frame.total_size == 0;
10492 /* Return true if register REGNO can store a value of mode MODE.
10493 The result of this function is cached in mips_hard_regno_mode_ok. */
10496 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10499 enum mode_class mclass;
10501 if (mode == CCV2mode)
10502 return (ISA_HAS_8CC
10503 && ST_REG_P (regno)
10504 && (regno - ST_REG_FIRST) % 2 == 0);
10506 if (mode == CCV4mode)
10507 return (ISA_HAS_8CC
10508 && ST_REG_P (regno)
10509 && (regno - ST_REG_FIRST) % 4 == 0);
10511 if (mode == CCmode)
10514 return regno == FPSW_REGNUM;
10516 return (ST_REG_P (regno)
10517 || GP_REG_P (regno)
10518 || FP_REG_P (regno));
10521 size = GET_MODE_SIZE (mode);
10522 mclass = GET_MODE_CLASS (mode);
10524 if (GP_REG_P (regno))
10525 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10527 if (FP_REG_P (regno)
10528 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10529 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10531 /* Allow TFmode for CCmode reloads. */
10532 if (mode == TFmode && ISA_HAS_8CC)
10535 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10536 if (TARGET_LOONGSON_VECTORS
10537 && (mode == V2SImode
10538 || mode == V4HImode
10539 || mode == V8QImode
10540 || mode == DImode))
10543 if (mclass == MODE_FLOAT
10544 || mclass == MODE_COMPLEX_FLOAT
10545 || mclass == MODE_VECTOR_FLOAT)
10546 return size <= UNITS_PER_FPVALUE;
10548 /* Allow integer modes that fit into a single register. We need
10549 to put integers into FPRs when using instructions like CVT
10550 and TRUNC. There's no point allowing sizes smaller than a word,
10551 because the FPU has no appropriate load/store instructions. */
10552 if (mclass == MODE_INT)
10553 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10556 if (ACC_REG_P (regno)
10557 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10559 if (MD_REG_P (regno))
10561 /* After a multiplication or division, clobbering HI makes
10562 the value of LO unpredictable, and vice versa. This means
10563 that, for all interesting cases, HI and LO are effectively
10566 We model this by requiring that any value that uses HI
10568 if (size <= UNITS_PER_WORD * 2)
10569 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10573 /* DSP accumulators do not have the same restrictions as
10574 HI and LO, so we can treat them as normal doubleword
10576 if (size <= UNITS_PER_WORD)
10579 if (size <= UNITS_PER_WORD * 2
10580 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10585 if (ALL_COP_REG_P (regno))
10586 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10588 if (regno == GOT_VERSION_REGNUM)
10589 return mode == SImode;
10594 /* Implement HARD_REGNO_NREGS. */
10597 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10599 if (ST_REG_P (regno))
10600 /* The size of FP status registers is always 4, because they only hold
10601 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10602 return (GET_MODE_SIZE (mode) + 3) / 4;
10604 if (FP_REG_P (regno))
10605 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10607 /* All other registers are word-sized. */
10608 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10611 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10612 in mips_hard_regno_nregs. */
10615 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10621 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10622 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10624 size = MIN (size, 4);
10625 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10627 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10629 size = MIN (size, UNITS_PER_FPREG);
10630 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10632 if (!hard_reg_set_empty_p (left))
10633 size = MIN (size, UNITS_PER_WORD);
10634 return (GET_MODE_SIZE (mode) + size - 1) / size;
10637 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10640 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10641 enum machine_mode to ATTRIBUTE_UNUSED,
10642 enum reg_class rclass)
10644 /* There are several problems with changing the modes of values
10645 in floating-point registers:
10647 - When a multi-word value is stored in paired floating-point
10648 registers, the first register always holds the low word.
10649 We therefore can't allow FPRs to change between single-word
10650 and multi-word modes on big-endian targets.
10652 - GCC assumes that each word of a multiword register can be accessed
10653 individually using SUBREGs. This is not true for floating-point
10654 registers if they are bigger than a word.
10656 - Loading a 32-bit value into a 64-bit floating-point register
10657 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10658 We can't allow FPRs to change from SImode to to a wider mode on
10661 - If the FPU has already interpreted a value in one format, we must
10662 not ask it to treat the value as having a different format.
10664 We therefore disallow all mode changes involving FPRs. */
10665 return reg_classes_intersect_p (FP_REGS, rclass);
10668 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10671 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10676 return TARGET_HARD_FLOAT;
10679 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10682 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10689 /* Implement MODES_TIEABLE_P. */
10692 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10694 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10695 prefer to put one of them in FPRs. */
10696 return (mode1 == mode2
10697 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10698 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10701 /* Implement PREFERRED_RELOAD_CLASS. */
10704 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10706 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10709 if (reg_class_subset_p (FP_REGS, rclass)
10710 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10713 if (reg_class_subset_p (GR_REGS, rclass))
10716 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10722 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10723 Return a "canonical" class to represent it in later calculations. */
10725 static enum reg_class
10726 mips_canonicalize_move_class (enum reg_class rclass)
10728 /* All moves involving accumulator registers have the same cost. */
10729 if (reg_class_subset_p (rclass, ACC_REGS))
10732 /* Likewise promote subclasses of general registers to the most
10733 interesting containing class. */
10734 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10736 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10737 rclass = GENERAL_REGS;
10742 /* Return the cost of moving a value of mode MODE from a register of
10743 class FROM to a GPR. Return 0 for classes that are unions of other
10744 classes handled by this function. */
10747 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10748 enum reg_class from)
10753 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10757 /* MFLO and MFHI. */
10765 /* LUI followed by MOVF. */
10771 /* This choice of value is historical. */
10779 /* Return the cost of moving a value of mode MODE from a GPR to a
10780 register of class TO. Return 0 for classes that are unions of
10781 other classes handled by this function. */
10784 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10789 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10793 /* MTLO and MTHI. */
10801 /* A secondary reload through an FPR scratch. */
10802 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10803 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10808 /* This choice of value is historical. */
10816 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10817 maximum of the move costs for subclasses; regclass will work out
10818 the maximum for us. */
10821 mips_register_move_cost (enum machine_mode mode,
10822 enum reg_class from, enum reg_class to)
10824 enum reg_class dregs;
10827 from = mips_canonicalize_move_class (from);
10828 to = mips_canonicalize_move_class (to);
10830 /* Handle moves that can be done without using general-purpose registers. */
10831 if (from == FP_REGS)
10833 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10837 /* The sequence generated by mips_expand_fcc_reload. */
10841 /* Handle cases in which only one class deviates from the ideal. */
10842 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10844 return mips_move_from_gpr_cost (mode, to);
10846 return mips_move_to_gpr_cost (mode, from);
10848 /* Handles cases that require a GPR temporary. */
10849 cost1 = mips_move_to_gpr_cost (mode, from);
10852 cost2 = mips_move_from_gpr_cost (mode, to);
10854 return cost1 + cost2;
10860 /* Implement TARGET_IRA_COVER_CLASSES. */
10862 static const enum reg_class *
10863 mips_ira_cover_classes (void)
10865 static const enum reg_class acc_classes[] = {
10866 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10867 ST_REGS, LIM_REG_CLASSES
10869 static const enum reg_class no_acc_classes[] = {
10870 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10871 ST_REGS, LIM_REG_CLASSES
10874 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10875 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10876 as a cover class only works well when we keep per-register costs.
10877 Using it when not optimizing can cause us to think accumulators
10878 have the same cost as GPRs in cases where GPRs are actually much
10880 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10883 /* Return the register class required for a secondary register when
10884 copying between one of the registers in RCLASS and value X, which
10885 has mode MODE. X is the source of the move if IN_P, otherwise it
10886 is the destination. Return NO_REGS if no secondary register is
10890 mips_secondary_reload_class (enum reg_class rclass,
10891 enum machine_mode mode, rtx x, bool in_p)
10895 /* If X is a constant that cannot be loaded into $25, it must be loaded
10896 into some other GPR. No other register class allows a direct move. */
10897 if (mips_dangerous_for_la25_p (x))
10898 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10900 regno = true_regnum (x);
10903 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10904 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10910 /* Copying from accumulator registers to anywhere other than a general
10911 register requires a temporary general register. */
10912 if (reg_class_subset_p (rclass, ACC_REGS))
10913 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10914 if (ACC_REG_P (regno))
10915 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10917 /* We can only copy a value to a condition code register from a
10918 floating-point register, and even then we require a scratch
10919 floating-point register. We can only copy a value out of a
10920 condition-code register into a general register. */
10921 if (reg_class_subset_p (rclass, ST_REGS))
10925 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10927 if (ST_REG_P (regno))
10931 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10934 if (reg_class_subset_p (rclass, FP_REGS))
10937 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10938 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10939 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10942 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10943 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10946 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
10947 /* We can force the constant to memory and use lwc1
10948 and ldc1. As above, we will use pairs of lwc1s if
10949 ldc1 is not supported. */
10952 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10953 /* In this case we can use mov.fmt. */
10956 /* Otherwise, we need to reload through an integer register. */
10959 if (FP_REG_P (regno))
10960 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10965 /* Implement TARGET_MODE_REP_EXTENDED. */
10968 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10970 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10971 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10972 return SIGN_EXTEND;
10977 /* Implement TARGET_VALID_POINTER_MODE. */
10980 mips_valid_pointer_mode (enum machine_mode mode)
10982 return mode == SImode || (TARGET_64BIT && mode == DImode);
10985 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10988 mips_vector_mode_supported_p (enum machine_mode mode)
10993 return TARGET_PAIRED_SINGLE_FLOAT;
11008 return TARGET_LOONGSON_VECTORS;
11015 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11018 mips_scalar_mode_supported_p (enum machine_mode mode)
11020 if (ALL_FIXED_POINT_MODE_P (mode)
11021 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11024 return default_scalar_mode_supported_p (mode);
11027 /* Implement TARGET_INIT_LIBFUNCS. */
11029 #include "config/gofast.h"
11032 mips_init_libfuncs (void)
11034 if (TARGET_FIX_VR4120)
11036 /* Register the special divsi3 and modsi3 functions needed to work
11037 around VR4120 division errata. */
11038 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11039 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11042 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11044 /* Register the MIPS16 -mhard-float stubs. */
11045 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11046 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11047 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11048 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11050 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11051 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11052 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11053 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11054 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11055 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11056 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11058 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11059 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11060 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11062 if (TARGET_DOUBLE_FLOAT)
11064 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11065 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11066 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11067 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11069 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11070 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11071 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11072 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11073 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11074 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11075 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11077 set_conv_libfunc (sext_optab, DFmode, SFmode,
11078 "__mips16_extendsfdf2");
11079 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11080 "__mips16_truncdfsf2");
11081 set_conv_libfunc (sfix_optab, SImode, DFmode,
11082 "__mips16_fix_truncdfsi");
11083 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11084 "__mips16_floatsidf");
11085 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11086 "__mips16_floatunsidf");
11090 /* Register the gofast functions if selected using --enable-gofast. */
11091 gofast_maybe_init_libfuncs ();
11093 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11094 on an external non-MIPS16 routine to implement __sync_synchronize. */
11096 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11099 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11102 mips_process_load_label (rtx target)
11104 rtx base, gp, intop;
11105 HOST_WIDE_INT offset;
11107 mips_multi_start ();
11111 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11112 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11116 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11117 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11121 gp = pic_offset_table_rtx;
11122 if (mips_cfun_has_cprestore_slot_p ())
11124 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11125 mips_get_cprestore_base_and_offset (&base, &offset, true);
11126 if (!SMALL_OPERAND (offset))
11128 intop = GEN_INT (CONST_HIGH_PART (offset));
11129 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11130 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11133 offset = CONST_LOW_PART (offset);
11135 intop = GEN_INT (offset);
11136 if (ISA_HAS_LOAD_DELAY)
11137 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11139 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11141 if (ISA_HAS_LOAD_DELAY)
11142 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11144 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11145 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11150 /* Return the number of instructions needed to load a label into $AT. */
11152 static unsigned int
11153 mips_load_label_length (void)
11155 if (cfun->machine->load_label_length == 0)
11157 mips_process_load_label (pc_rtx);
11158 cfun->machine->load_label_length = mips_multi_num_insns;
11160 return cfun->machine->load_label_length;
11163 /* Emit an asm sequence to start a noat block and load the address
11164 of a label into $1. */
11167 mips_output_load_label (rtx target)
11169 mips_push_asm_switch (&mips_noat);
11170 if (TARGET_EXPLICIT_RELOCS)
11172 mips_process_load_label (target);
11173 mips_multi_write ();
11177 if (Pmode == DImode)
11178 output_asm_insn ("dla\t%@,%0", &target);
11180 output_asm_insn ("la\t%@,%0", &target);
11184 /* Return the length of INSN. LENGTH is the initial length computed by
11185 attributes in the machine-description file. */
11188 mips_adjust_insn_length (rtx insn, int length)
11190 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11191 of a PIC long-branch sequence. Substitute the correct value. */
11192 if (length == MAX_PIC_BRANCH_LENGTH
11193 && INSN_CODE (insn) >= 0
11194 && get_attr_type (insn) == TYPE_BRANCH)
11196 /* Add the branch-over instruction and its delay slot, if this
11197 is a conditional branch. */
11198 length = simplejump_p (insn) ? 0 : 8;
11200 /* Load the label into $AT and jump to it. Ignore the delay
11201 slot of the jump. */
11202 length += mips_load_label_length () + 4;
11205 /* A unconditional jump has an unfilled delay slot if it is not part
11206 of a sequence. A conditional jump normally has a delay slot, but
11207 does not on MIPS16. */
11208 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11211 /* See how many nops might be needed to avoid hardware hazards. */
11212 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11213 switch (get_attr_hazard (insn))
11227 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11228 the .md file length attributes are 4-based for both modes.
11229 Adjust the MIPS16 ones here. */
11236 /* Return the assembly code for INSN, which has the operands given by
11237 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11238 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11239 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11240 version of BRANCH_IF_TRUE. */
11243 mips_output_conditional_branch (rtx insn, rtx *operands,
11244 const char *branch_if_true,
11245 const char *branch_if_false)
11247 unsigned int length;
11248 rtx taken, not_taken;
11250 gcc_assert (LABEL_P (operands[0]));
11252 length = get_attr_length (insn);
11255 /* Just a simple conditional branch. */
11256 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11257 return branch_if_true;
11260 /* Generate a reversed branch around a direct jump. This fallback does
11261 not use branch-likely instructions. */
11262 mips_branch_likely = false;
11263 not_taken = gen_label_rtx ();
11264 taken = operands[0];
11266 /* Generate the reversed branch to NOT_TAKEN. */
11267 operands[0] = not_taken;
11268 output_asm_insn (branch_if_false, operands);
11270 /* If INSN has a delay slot, we must provide delay slots for both the
11271 branch to NOT_TAKEN and the conditional jump. We must also ensure
11272 that INSN's delay slot is executed in the appropriate cases. */
11273 if (final_sequence)
11275 /* This first delay slot will always be executed, so use INSN's
11276 delay slot if is not annulled. */
11277 if (!INSN_ANNULLED_BRANCH_P (insn))
11279 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11280 asm_out_file, optimize, 1, NULL);
11281 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11284 output_asm_insn ("nop", 0);
11285 fprintf (asm_out_file, "\n");
11288 /* Output the unconditional branch to TAKEN. */
11289 if (TARGET_ABSOLUTE_JUMPS)
11290 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11293 mips_output_load_label (taken);
11294 output_asm_insn ("jr\t%@%]%/", 0);
11297 /* Now deal with its delay slot; see above. */
11298 if (final_sequence)
11300 /* This delay slot will only be executed if the branch is taken.
11301 Use INSN's delay slot if is annulled. */
11302 if (INSN_ANNULLED_BRANCH_P (insn))
11304 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11305 asm_out_file, optimize, 1, NULL);
11306 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11309 output_asm_insn ("nop", 0);
11310 fprintf (asm_out_file, "\n");
11313 /* Output NOT_TAKEN. */
11314 targetm.asm_out.internal_label (asm_out_file, "L",
11315 CODE_LABEL_NUMBER (not_taken));
11319 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11320 if some ordering condition is true. The condition is given by
11321 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11322 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11323 its second is always zero. */
11326 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11328 const char *branch[2];
11330 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11331 Make BRANCH[0] branch on the inverse condition. */
11332 switch (GET_CODE (operands[1]))
11334 /* These cases are equivalent to comparisons against zero. */
11336 inverted_p = !inverted_p;
11337 /* Fall through. */
11339 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11340 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11343 /* These cases are always true or always false. */
11345 inverted_p = !inverted_p;
11346 /* Fall through. */
11348 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11349 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11353 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11354 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11357 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11360 /* Start a block of code that needs access to the LL, SC and SYNC
11364 mips_start_ll_sc_sync_block (void)
11366 if (!ISA_HAS_LL_SC)
11368 output_asm_insn (".set\tpush", 0);
11369 output_asm_insn (".set\tmips2", 0);
11373 /* End a block started by mips_start_ll_sc_sync_block. */
11376 mips_end_ll_sc_sync_block (void)
11378 if (!ISA_HAS_LL_SC)
11379 output_asm_insn (".set\tpop", 0);
11382 /* Output and/or return the asm template for a sync instruction. */
11385 mips_output_sync (void)
11387 mips_start_ll_sc_sync_block ();
11388 output_asm_insn ("sync", 0);
11389 mips_end_ll_sc_sync_block ();
11393 /* Return the asm template associated with sync_insn1 value TYPE.
11394 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11396 static const char *
11397 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11401 case SYNC_INSN1_MOVE:
11402 return "move\t%0,%z2";
11403 case SYNC_INSN1_LI:
11404 return "li\t%0,%2";
11405 case SYNC_INSN1_ADDU:
11406 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11407 case SYNC_INSN1_ADDIU:
11408 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11409 case SYNC_INSN1_SUBU:
11410 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11411 case SYNC_INSN1_AND:
11412 return "and\t%0,%1,%z2";
11413 case SYNC_INSN1_ANDI:
11414 return "andi\t%0,%1,%2";
11415 case SYNC_INSN1_OR:
11416 return "or\t%0,%1,%z2";
11417 case SYNC_INSN1_ORI:
11418 return "ori\t%0,%1,%2";
11419 case SYNC_INSN1_XOR:
11420 return "xor\t%0,%1,%z2";
11421 case SYNC_INSN1_XORI:
11422 return "xori\t%0,%1,%2";
11424 gcc_unreachable ();
11427 /* Return the asm template associated with sync_insn2 value TYPE. */
11429 static const char *
11430 mips_sync_insn2_template (enum attr_sync_insn2 type)
11434 case SYNC_INSN2_NOP:
11435 gcc_unreachable ();
11436 case SYNC_INSN2_AND:
11437 return "and\t%0,%1,%z2";
11438 case SYNC_INSN2_XOR:
11439 return "xor\t%0,%1,%z2";
11440 case SYNC_INSN2_NOT:
11441 return "nor\t%0,%1,%.";
11443 gcc_unreachable ();
11446 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11447 the value of the one of the sync_* attributes. Return the operand
11448 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11449 have the associated attribute. */
11452 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11455 default_value = operands[index - 1];
11456 return default_value;
11459 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11460 sequence for it. */
11463 mips_process_sync_loop (rtx insn, rtx *operands)
11465 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11466 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11467 unsigned int tmp3_insn;
11468 enum attr_sync_insn1 insn1;
11469 enum attr_sync_insn2 insn2;
11472 /* Read an operand from the sync_WHAT attribute and store it in
11473 variable WHAT. DEFAULT is the default value if no attribute
11475 #define READ_OPERAND(WHAT, DEFAULT) \
11476 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11479 /* Read the memory. */
11480 READ_OPERAND (mem, 0);
11482 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11484 /* Read the other attributes. */
11485 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11486 READ_OPERAND (oldval, at);
11487 READ_OPERAND (newval, at);
11488 READ_OPERAND (inclusive_mask, 0);
11489 READ_OPERAND (exclusive_mask, 0);
11490 READ_OPERAND (required_oldval, 0);
11491 READ_OPERAND (insn1_op2, 0);
11492 insn1 = get_attr_sync_insn1 (insn);
11493 insn2 = get_attr_sync_insn2 (insn);
11495 mips_multi_start ();
11497 /* Output the release side of the memory barrier. */
11498 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11500 if (required_oldval == 0 && TARGET_OCTEON)
11502 /* Octeon doesn't reorder reads, so a full barrier can be
11503 created by using SYNCW to order writes combined with the
11504 write from the following SC. When the SC successfully
11505 completes, we know that all preceding writes are also
11506 committed to the coherent memory system. It is possible
11507 for a single SYNCW to fail, but a pair of them will never
11508 fail, so we use two. */
11509 mips_multi_add_insn ("syncw", NULL);
11510 mips_multi_add_insn ("syncw", NULL);
11513 mips_multi_add_insn ("sync", NULL);
11516 /* Output the branch-back label. */
11517 mips_multi_add_label ("1:");
11519 /* OLDVAL = *MEM. */
11520 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11521 oldval, mem, NULL);
11523 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11524 if (required_oldval)
11526 if (inclusive_mask == 0)
11530 gcc_assert (oldval != at);
11531 mips_multi_add_insn ("and\t%0,%1,%2",
11532 at, oldval, inclusive_mask, NULL);
11535 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11538 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11539 if (exclusive_mask == 0)
11543 gcc_assert (oldval != at);
11544 mips_multi_add_insn ("and\t%0,%1,%z2",
11545 at, oldval, exclusive_mask, NULL);
11549 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11551 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11552 at least one instruction in that case. */
11553 if (insn1 == SYNC_INSN1_MOVE
11554 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11558 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11559 newval, oldval, insn1_op2, NULL);
11563 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11564 if (insn2 == SYNC_INSN2_NOP)
11568 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11569 newval, tmp2, inclusive_mask, NULL);
11572 tmp3_insn = mips_multi_last_index ();
11574 /* $AT = $TMP1 | $TMP3. */
11575 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11577 mips_multi_set_operand (tmp3_insn, 0, at);
11582 gcc_assert (tmp1 != tmp3);
11583 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11586 /* if (!commit (*MEM = $AT)) goto 1.
11588 This will sometimes be a delayed branch; see the write code below
11590 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11591 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11593 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11594 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11596 mips_multi_copy_insn (tmp3_insn);
11597 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11600 mips_multi_add_insn ("nop", NULL);
11602 /* Output the acquire side of the memory barrier. */
11603 if (TARGET_SYNC_AFTER_SC)
11604 mips_multi_add_insn ("sync", NULL);
11606 /* Output the exit label, if needed. */
11607 if (required_oldval)
11608 mips_multi_add_label ("2:");
11610 #undef READ_OPERAND
11613 /* Output and/or return the asm template for sync loop INSN, which has
11614 the operands given by OPERANDS. */
11617 mips_output_sync_loop (rtx insn, rtx *operands)
11619 mips_process_sync_loop (insn, operands);
11621 /* Use branch-likely instructions to work around the LL/SC R10000
11623 mips_branch_likely = TARGET_FIX_R10000;
11625 mips_push_asm_switch (&mips_noreorder);
11626 mips_push_asm_switch (&mips_nomacro);
11627 mips_push_asm_switch (&mips_noat);
11628 mips_start_ll_sc_sync_block ();
11630 mips_multi_write ();
11632 mips_end_ll_sc_sync_block ();
11633 mips_pop_asm_switch (&mips_noat);
11634 mips_pop_asm_switch (&mips_nomacro);
11635 mips_pop_asm_switch (&mips_noreorder);
11640 /* Return the number of individual instructions in sync loop INSN,
11641 which has the operands given by OPERANDS. */
11644 mips_sync_loop_insns (rtx insn, rtx *operands)
11646 mips_process_sync_loop (insn, operands);
11647 return mips_multi_num_insns;
11650 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11651 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11653 When working around R4000 and R4400 errata, we need to make sure that
11654 the division is not immediately followed by a shift[1][2]. We also
11655 need to stop the division from being put into a branch delay slot[3].
11656 The easiest way to avoid both problems is to add a nop after the
11657 division. When a divide-by-zero check is needed, this nop can be
11658 used to fill the branch delay slot.
11660 [1] If a double-word or a variable shift executes immediately
11661 after starting an integer division, the shift may give an
11662 incorrect result. See quotations of errata #16 and #28 from
11663 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11664 in mips.md for details.
11666 [2] A similar bug to [1] exists for all revisions of the
11667 R4000 and the R4400 when run in an MC configuration.
11668 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11670 "19. In this following sequence:
11672 ddiv (or ddivu or div or divu)
11673 dsll32 (or dsrl32, dsra32)
11675 if an MPT stall occurs, while the divide is slipping the cpu
11676 pipeline, then the following double shift would end up with an
11679 Workaround: The compiler needs to avoid generating any
11680 sequence with divide followed by extended double shift."
11682 This erratum is also present in "MIPS R4400MC Errata, Processor
11683 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11684 & 3.0" as errata #10 and #4, respectively.
11686 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11687 (also valid for MIPS R4000MC processors):
11689 "52. R4000SC: This bug does not apply for the R4000PC.
11691 There are two flavors of this bug:
11693 1) If the instruction just after divide takes an RF exception
11694 (tlb-refill, tlb-invalid) and gets an instruction cache
11695 miss (both primary and secondary) and the line which is
11696 currently in secondary cache at this index had the first
11697 data word, where the bits 5..2 are set, then R4000 would
11698 get a wrong result for the div.
11703 ------------------- # end-of page. -tlb-refill
11708 ------------------- # end-of page. -tlb-invalid
11711 2) If the divide is in the taken branch delay slot, where the
11712 target takes RF exception and gets an I-cache miss for the
11713 exception vector or where I-cache miss occurs for the
11714 target address, under the above mentioned scenarios, the
11715 div would get wrong results.
11718 j r2 # to next page mapped or unmapped
11719 div r8,r9 # this bug would be there as long
11720 # as there is an ICache miss and
11721 nop # the "data pattern" is present
11724 beq r0, r0, NextPage # to Next page
11728 This bug is present for div, divu, ddiv, and ddivu
11731 Workaround: For item 1), OS could make sure that the next page
11732 after the divide instruction is also mapped. For item 2), the
11733 compiler could make sure that the divide instruction is not in
11734 the branch delay slot."
11736 These processors have PRId values of 0x00004220 and 0x00004300 for
11737 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11740 mips_output_division (const char *division, rtx *operands)
11745 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11747 output_asm_insn (s, operands);
11750 if (TARGET_CHECK_ZERO_DIV)
11754 output_asm_insn (s, operands);
11755 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11757 else if (GENERATE_DIVIDE_TRAPS)
11759 output_asm_insn (s, operands);
11760 s = "teq\t%2,%.,7";
11764 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11765 output_asm_insn (s, operands);
11766 s = "break\t7%)\n1:";
11772 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11773 instruction and if OUT_INSN assigns to the accumulator operand. */
11776 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11780 x = single_set (in_insn);
11786 if (GET_CODE (x) == PLUS
11787 && GET_CODE (XEXP (x, 0)) == MULT
11788 && reg_set_p (XEXP (x, 1), out_insn))
11791 if (GET_CODE (x) == MINUS
11792 && GET_CODE (XEXP (x, 1)) == MULT
11793 && reg_set_p (XEXP (x, 0), out_insn))
11799 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11800 data rather than the address. We need this because the cprestore
11801 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11802 which causes the default routine to abort. We just return false
11806 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11808 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11811 return !store_data_bypass_p (out_insn, in_insn);
11815 /* Variables and flags used in scheduler hooks when tuning for
11819 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11822 /* If true, then next ALU1/2 instruction will go to ALU1. */
11825 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11828 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11829 int alu1_core_unit_code;
11830 int alu2_core_unit_code;
11831 int falu1_core_unit_code;
11832 int falu2_core_unit_code;
11834 /* True if current cycle has a multi instruction.
11835 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11836 bool cycle_has_multi_p;
11838 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11839 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11841 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11842 instruction to go ALU1. */
11843 rtx alu1_turn_enabled_insn;
11844 rtx alu2_turn_enabled_insn;
11845 rtx falu1_turn_enabled_insn;
11846 rtx falu2_turn_enabled_insn;
11849 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11850 dependencies have no cost, except on the 20Kc where output-dependence
11851 is treated like input-dependence. */
11854 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11855 rtx dep ATTRIBUTE_UNUSED, int cost)
11857 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11860 if (REG_NOTE_KIND (link) != 0)
11865 /* Return the number of instructions that can be issued per cycle. */
11868 mips_issue_rate (void)
11872 case PROCESSOR_74KC:
11873 case PROCESSOR_74KF2_1:
11874 case PROCESSOR_74KF1_1:
11875 case PROCESSOR_74KF3_2:
11876 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11877 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11878 but in reality only a maximum of 3 insns can be issued as
11879 floating-point loads and stores also require a slot in the
11881 case PROCESSOR_R10000:
11882 /* All R10K Processors are quad-issue (being the first MIPS
11883 processors to support this feature). */
11886 case PROCESSOR_20KC:
11887 case PROCESSOR_R4130:
11888 case PROCESSOR_R5400:
11889 case PROCESSOR_R5500:
11890 case PROCESSOR_R7000:
11891 case PROCESSOR_R9000:
11892 case PROCESSOR_OCTEON:
11895 case PROCESSOR_SB1:
11896 case PROCESSOR_SB1A:
11897 /* This is actually 4, but we get better performance if we claim 3.
11898 This is partly because of unwanted speculative code motion with the
11899 larger number, and partly because in most common cases we can't
11900 reach the theoretical max of 4. */
11903 case PROCESSOR_LOONGSON_2E:
11904 case PROCESSOR_LOONGSON_2F:
11912 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11915 mips_ls2_init_dfa_post_cycle_insn (void)
11918 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11919 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11923 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11924 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11928 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11929 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11933 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11934 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11937 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11938 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11939 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11940 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11943 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11944 Init data used in mips_dfa_post_advance_cycle. */
11947 mips_init_dfa_post_cycle_insn (void)
11949 if (TUNE_LOONGSON_2EF)
11950 mips_ls2_init_dfa_post_cycle_insn ();
11953 /* Initialize STATE when scheduling for Loongson 2E/2F.
11954 Support round-robin dispatch scheme by enabling only one of
11955 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11959 mips_ls2_dfa_post_advance_cycle (state_t state)
11961 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
11963 /* Though there are no non-pipelined ALU1 insns,
11964 we can get an instruction of type 'multi' before reload. */
11965 gcc_assert (mips_ls2.cycle_has_multi_p);
11966 mips_ls2.alu1_turn_p = false;
11969 mips_ls2.cycle_has_multi_p = false;
11971 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
11972 /* We have a non-pipelined alu instruction in the core,
11973 adjust round-robin counter. */
11974 mips_ls2.alu1_turn_p = true;
11976 if (mips_ls2.alu1_turn_p)
11978 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
11979 gcc_unreachable ();
11983 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
11984 gcc_unreachable ();
11987 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
11989 /* There are no non-pipelined FALU1 insns. */
11990 gcc_unreachable ();
11991 mips_ls2.falu1_turn_p = false;
11994 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
11995 /* We have a non-pipelined falu instruction in the core,
11996 adjust round-robin counter. */
11997 mips_ls2.falu1_turn_p = true;
11999 if (mips_ls2.falu1_turn_p)
12001 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12002 gcc_unreachable ();
12006 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12007 gcc_unreachable ();
12011 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12012 This hook is being called at the start of each cycle. */
12015 mips_dfa_post_advance_cycle (void)
12017 if (TUNE_LOONGSON_2EF)
12018 mips_ls2_dfa_post_advance_cycle (curr_state);
12021 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12022 be as wide as the scheduling freedom in the DFA. */
12025 mips_multipass_dfa_lookahead (void)
12027 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12031 if (TUNE_LOONGSON_2EF)
12040 /* Remove the instruction at index LOWER from ready queue READY and
12041 reinsert it in front of the instruction at index HIGHER. LOWER must
12045 mips_promote_ready (rtx *ready, int lower, int higher)
12050 new_head = ready[lower];
12051 for (i = lower; i < higher; i++)
12052 ready[i] = ready[i + 1];
12053 ready[i] = new_head;
12056 /* If the priority of the instruction at POS2 in the ready queue READY
12057 is within LIMIT units of that of the instruction at POS1, swap the
12058 instructions if POS2 is not already less than POS1. */
12061 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12064 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12068 temp = ready[pos1];
12069 ready[pos1] = ready[pos2];
12070 ready[pos2] = temp;
12074 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12075 that may clobber hi or lo. */
12076 static rtx mips_macc_chains_last_hilo;
12078 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12079 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12082 mips_macc_chains_record (rtx insn)
12084 if (get_attr_may_clobber_hilo (insn))
12085 mips_macc_chains_last_hilo = insn;
12088 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12089 has NREADY elements, looking for a multiply-add or multiply-subtract
12090 instruction that is cumulative with mips_macc_chains_last_hilo.
12091 If there is one, promote it ahead of anything else that might
12092 clobber hi or lo. */
12095 mips_macc_chains_reorder (rtx *ready, int nready)
12099 if (mips_macc_chains_last_hilo != 0)
12100 for (i = nready - 1; i >= 0; i--)
12101 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12103 for (j = nready - 1; j > i; j--)
12104 if (recog_memoized (ready[j]) >= 0
12105 && get_attr_may_clobber_hilo (ready[j]))
12107 mips_promote_ready (ready, i, j);
12114 /* The last instruction to be scheduled. */
12115 static rtx vr4130_last_insn;
12117 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12118 points to an rtx that is initially an instruction. Nullify the rtx
12119 if the instruction uses the value of register X. */
12122 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12127 insn_ptr = (rtx *) data;
12130 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12134 /* Return true if there is true register dependence between vr4130_last_insn
12138 vr4130_true_reg_dependence_p (rtx insn)
12140 note_stores (PATTERN (vr4130_last_insn),
12141 vr4130_true_reg_dependence_p_1, &insn);
12145 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12146 the ready queue and that INSN2 is the instruction after it, return
12147 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12148 in which INSN1 and INSN2 can probably issue in parallel, but for
12149 which (INSN2, INSN1) should be less sensitive to instruction
12150 alignment than (INSN1, INSN2). See 4130.md for more details. */
12153 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12155 sd_iterator_def sd_it;
12158 /* Check for the following case:
12160 1) there is some other instruction X with an anti dependence on INSN1;
12161 2) X has a higher priority than INSN2; and
12162 3) X is an arithmetic instruction (and thus has no unit restrictions).
12164 If INSN1 is the last instruction blocking X, it would better to
12165 choose (INSN1, X) over (INSN2, INSN1). */
12166 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12167 if (DEP_TYPE (dep) == REG_DEP_ANTI
12168 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12169 && recog_memoized (DEP_CON (dep)) >= 0
12170 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12173 if (vr4130_last_insn != 0
12174 && recog_memoized (insn1) >= 0
12175 && recog_memoized (insn2) >= 0)
12177 /* See whether INSN1 and INSN2 use different execution units,
12178 or if they are both ALU-type instructions. If so, they can
12179 probably execute in parallel. */
12180 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12181 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12182 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12184 /* If only one of the instructions has a dependence on
12185 vr4130_last_insn, prefer to schedule the other one first. */
12186 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12187 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12188 if (dep1_p != dep2_p)
12191 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12192 is not an ALU-type instruction and if INSN1 uses the same
12193 execution unit. (Note that if this condition holds, we already
12194 know that INSN2 uses a different execution unit.) */
12195 if (class1 != VR4130_CLASS_ALU
12196 && recog_memoized (vr4130_last_insn) >= 0
12197 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12204 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12205 queue with at least two instructions. Swap the first two if
12206 vr4130_swap_insns_p says that it could be worthwhile. */
12209 vr4130_reorder (rtx *ready, int nready)
12211 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12212 mips_promote_ready (ready, nready - 2, nready - 1);
12215 /* Record whether last 74k AGEN instruction was a load or store. */
12216 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12218 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12219 resets to TYPE_UNKNOWN state. */
12222 mips_74k_agen_init (rtx insn)
12224 if (!insn || CALL_P (insn) || JUMP_P (insn))
12225 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12228 enum attr_type type = get_attr_type (insn);
12229 if (type == TYPE_LOAD || type == TYPE_STORE)
12230 mips_last_74k_agen_insn = type;
12234 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12235 loads to be grouped together, and multiple stores to be grouped
12236 together. Swap things around in the ready queue to make this happen. */
12239 mips_74k_agen_reorder (rtx *ready, int nready)
12242 int store_pos, load_pos;
12247 for (i = nready - 1; i >= 0; i--)
12249 rtx insn = ready[i];
12250 if (USEFUL_INSN_P (insn))
12251 switch (get_attr_type (insn))
12254 if (store_pos == -1)
12259 if (load_pos == -1)
12268 if (load_pos == -1 || store_pos == -1)
12271 switch (mips_last_74k_agen_insn)
12274 /* Prefer to schedule loads since they have a higher latency. */
12276 /* Swap loads to the front of the queue. */
12277 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12280 /* Swap stores to the front of the queue. */
12281 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12288 /* Implement TARGET_SCHED_INIT. */
12291 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12292 int max_ready ATTRIBUTE_UNUSED)
12294 mips_macc_chains_last_hilo = 0;
12295 vr4130_last_insn = 0;
12296 mips_74k_agen_init (NULL_RTX);
12298 /* When scheduling for Loongson2, branch instructions go to ALU1,
12299 therefore basic block is most likely to start with round-robin counter
12300 pointed to ALU2. */
12301 mips_ls2.alu1_turn_p = false;
12302 mips_ls2.falu1_turn_p = true;
12305 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12308 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12309 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12311 if (!reload_completed
12312 && TUNE_MACC_CHAINS
12314 mips_macc_chains_reorder (ready, *nreadyp);
12316 if (reload_completed
12318 && !TARGET_VR4130_ALIGN
12320 vr4130_reorder (ready, *nreadyp);
12323 mips_74k_agen_reorder (ready, *nreadyp);
12325 return mips_issue_rate ();
12328 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12331 mips_ls2_variable_issue (rtx insn)
12333 if (mips_ls2.alu1_turn_p)
12335 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12336 mips_ls2.alu1_turn_p = false;
12340 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12341 mips_ls2.alu1_turn_p = true;
12344 if (mips_ls2.falu1_turn_p)
12346 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12347 mips_ls2.falu1_turn_p = false;
12351 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12352 mips_ls2.falu1_turn_p = true;
12355 if (recog_memoized (insn) >= 0)
12356 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12359 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12362 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12363 rtx insn, int more)
12365 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12366 if (USEFUL_INSN_P (insn))
12368 if (get_attr_type (insn) != TYPE_GHOST)
12370 if (!reload_completed && TUNE_MACC_CHAINS)
12371 mips_macc_chains_record (insn);
12372 vr4130_last_insn = insn;
12374 mips_74k_agen_init (insn);
12375 else if (TUNE_LOONGSON_2EF)
12376 mips_ls2_variable_issue (insn);
12379 /* Instructions of type 'multi' should all be split before
12380 the second scheduling pass. */
12381 gcc_assert (!reload_completed
12382 || recog_memoized (insn) < 0
12383 || get_attr_type (insn) != TYPE_MULTI);
12388 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12389 return the first operand of the associated PREF or PREFX insn. */
12392 mips_prefetch_cookie (rtx write, rtx locality)
12394 /* store_streamed / load_streamed. */
12395 if (INTVAL (locality) <= 0)
12396 return GEN_INT (INTVAL (write) + 4);
12398 /* store / load. */
12399 if (INTVAL (locality) <= 2)
12402 /* store_retained / load_retained. */
12403 return GEN_INT (INTVAL (write) + 6);
12406 /* Flags that indicate when a built-in function is available.
12408 BUILTIN_AVAIL_NON_MIPS16
12409 The function is available on the current target, but only
12410 in non-MIPS16 mode. */
12411 #define BUILTIN_AVAIL_NON_MIPS16 1
12413 /* Declare an availability predicate for built-in functions that
12414 require non-MIPS16 mode and also require COND to be true.
12415 NAME is the main part of the predicate's name. */
12416 #define AVAIL_NON_MIPS16(NAME, COND) \
12417 static unsigned int \
12418 mips_builtin_avail_##NAME (void) \
12420 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12423 /* This structure describes a single built-in function. */
12424 struct mips_builtin_description {
12425 /* The code of the main .md file instruction. See mips_builtin_type
12426 for more information. */
12427 enum insn_code icode;
12429 /* The floating-point comparison code to use with ICODE, if any. */
12430 enum mips_fp_condition cond;
12432 /* The name of the built-in function. */
12435 /* Specifies how the function should be expanded. */
12436 enum mips_builtin_type builtin_type;
12438 /* The function's prototype. */
12439 enum mips_function_type function_type;
12441 /* Whether the function is available. */
12442 unsigned int (*avail) (void);
12445 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12446 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12447 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12448 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12449 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12450 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12451 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12452 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12453 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12455 /* Construct a mips_builtin_description from the given arguments.
12457 INSN is the name of the associated instruction pattern, without the
12458 leading CODE_FOR_mips_.
12460 CODE is the floating-point condition code associated with the
12461 function. It can be 'f' if the field is not applicable.
12463 NAME is the name of the function itself, without the leading
12466 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12468 AVAIL is the name of the availability predicate, without the leading
12469 mips_builtin_avail_. */
12470 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12471 FUNCTION_TYPE, AVAIL) \
12472 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12473 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12474 mips_builtin_avail_ ## AVAIL }
12476 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12477 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12478 are as for MIPS_BUILTIN. */
12479 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12480 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12482 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12483 are subject to mips_builtin_avail_<AVAIL>. */
12484 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12485 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12486 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12487 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12488 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12490 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12491 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12492 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12493 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12494 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12495 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12497 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12498 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12500 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12501 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12503 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12504 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12507 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12508 are subject to mips_builtin_avail_mips3d. */
12509 #define CMP_4S_BUILTINS(INSN, COND) \
12510 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12511 MIPS_BUILTIN_CMP_ANY, \
12512 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12513 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12514 MIPS_BUILTIN_CMP_ALL, \
12515 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12517 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12518 instruction requires mips_builtin_avail_<AVAIL>. */
12519 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12520 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12521 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12523 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12524 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12527 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12528 #define CMP_BUILTINS(COND) \
12529 MOVTF_BUILTINS (c, COND, paired_single), \
12530 MOVTF_BUILTINS (cabs, COND, mips3d), \
12531 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12532 CMP_PS_BUILTINS (c, COND, paired_single), \
12533 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12534 CMP_4S_BUILTINS (c, COND), \
12535 CMP_4S_BUILTINS (cabs, COND)
12537 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12538 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12539 and AVAIL are as for MIPS_BUILTIN. */
12540 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12541 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12542 FUNCTION_TYPE, AVAIL)
12544 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12545 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12546 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12547 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12548 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12550 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12551 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12552 builtin_description field. */
12553 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12554 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12555 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12556 FUNCTION_TYPE, mips_builtin_avail_loongson }
12558 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12559 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12560 builtin_description field. */
12561 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12562 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12564 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12565 We use functions of this form when the same insn can be usefully applied
12566 to more than one datatype. */
12567 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12568 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12570 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12571 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12572 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12573 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12574 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12575 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12577 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12578 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12579 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12580 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12581 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12582 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12583 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12584 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12585 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12586 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12587 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12588 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12589 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12590 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12591 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12592 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12593 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12594 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12595 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12596 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12597 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12598 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12599 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12600 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12601 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12602 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12603 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12604 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12605 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12607 static const struct mips_builtin_description mips_builtins[] = {
12608 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12609 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12610 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12611 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12612 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12613 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12614 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12615 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12617 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12618 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12619 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12620 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12621 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12623 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12624 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12625 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12626 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12627 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12628 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12630 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12631 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12632 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12633 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12634 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12635 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12637 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12639 /* Built-in functions for the SB-1 processor. */
12640 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12642 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12643 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12644 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12645 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12646 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12647 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12648 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12649 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12650 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12651 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12652 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12653 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12654 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12655 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12656 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12657 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12658 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12659 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12660 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12661 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12662 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12663 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12664 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12665 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12666 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12667 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12668 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12669 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12670 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12671 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12672 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12673 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12674 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12675 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12676 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12677 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12678 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12679 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12680 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12681 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12682 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12683 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12684 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12685 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12686 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12687 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12688 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12689 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12690 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12691 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12692 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12693 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12694 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12695 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12696 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12697 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12698 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12699 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12700 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12701 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12702 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12703 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12704 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12705 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12706 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12707 BPOSGE_BUILTIN (32, dsp),
12709 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12710 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12711 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12712 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12713 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12714 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12715 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12716 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12717 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12718 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12719 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12720 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12721 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12722 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12723 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12724 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12725 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12726 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12727 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12728 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12729 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12730 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12731 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12732 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12733 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12734 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12735 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12736 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12737 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12738 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12739 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12740 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12741 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12742 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12743 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12745 /* Built-in functions for the DSP ASE (32-bit only). */
12746 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12747 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12748 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12749 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12750 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12751 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12752 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12753 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12754 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12755 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12756 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12757 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12758 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12759 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12760 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12761 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12762 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12763 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12764 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12765 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12766 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12768 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12769 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12770 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12771 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12772 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12773 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12774 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12775 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12776 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
12777 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
12778 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12779 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12780 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12781 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12782 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12783 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12785 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12786 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12787 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12788 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12789 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12790 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12791 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12792 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12793 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12794 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12795 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12796 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12797 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12798 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12799 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12800 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12801 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12802 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12803 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12804 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12805 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12806 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12807 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12808 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12809 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12810 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12811 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12812 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12813 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12814 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12815 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12816 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12817 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12818 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12819 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12820 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12821 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12822 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12823 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12824 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12825 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12826 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12827 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12828 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12829 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12830 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12831 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12832 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12833 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12834 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12835 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12836 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12837 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12838 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12839 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12840 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12841 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12842 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12843 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
12844 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12845 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
12846 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
12847 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
12848 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
12849 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12850 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12851 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12852 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12853 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12854 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12855 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12856 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12857 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12858 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12859 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12860 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12861 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12862 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12863 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12864 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12865 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12866 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12867 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
12868 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
12869 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12870 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12871 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12872 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12873 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12874 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12875 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12876 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12877 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12878 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12879 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12880 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12881 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12882 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12883 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12884 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12886 /* Sundry other built-in functions. */
12887 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12890 /* MODE is a vector mode whose elements have type TYPE. Return the type
12891 of the vector itself. */
12894 mips_builtin_vector_type (tree type, enum machine_mode mode)
12896 static tree types[2 * (int) MAX_MACHINE_MODE];
12899 mode_index = (int) mode;
12901 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12902 mode_index += MAX_MACHINE_MODE;
12904 if (types[mode_index] == NULL_TREE)
12905 types[mode_index] = build_vector_type_for_mode (type, mode);
12906 return types[mode_index];
12909 /* Return a type for 'const volatile void *'. */
12912 mips_build_cvpointer_type (void)
12916 if (cache == NULL_TREE)
12917 cache = build_pointer_type (build_qualified_type
12919 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12923 /* Source-level argument types. */
12924 #define MIPS_ATYPE_VOID void_type_node
12925 #define MIPS_ATYPE_INT integer_type_node
12926 #define MIPS_ATYPE_POINTER ptr_type_node
12927 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12929 /* Standard mode-based argument types. */
12930 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12931 #define MIPS_ATYPE_SI intSI_type_node
12932 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12933 #define MIPS_ATYPE_DI intDI_type_node
12934 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12935 #define MIPS_ATYPE_SF float_type_node
12936 #define MIPS_ATYPE_DF double_type_node
12938 /* Vector argument types. */
12939 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12940 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12941 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12942 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12943 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12944 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12945 #define MIPS_ATYPE_UV2SI \
12946 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12947 #define MIPS_ATYPE_UV4HI \
12948 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
12949 #define MIPS_ATYPE_UV8QI \
12950 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
12952 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
12953 their associated MIPS_ATYPEs. */
12954 #define MIPS_FTYPE_ATYPES1(A, B) \
12955 MIPS_ATYPE_##A, MIPS_ATYPE_##B
12957 #define MIPS_FTYPE_ATYPES2(A, B, C) \
12958 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
12960 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
12961 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
12963 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
12964 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
12967 /* Return the function type associated with function prototype TYPE. */
12970 mips_build_function_type (enum mips_function_type type)
12972 static tree types[(int) MIPS_MAX_FTYPE_MAX];
12974 if (types[(int) type] == NULL_TREE)
12977 #define DEF_MIPS_FTYPE(NUM, ARGS) \
12978 case MIPS_FTYPE_NAME##NUM ARGS: \
12979 types[(int) type] \
12980 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
12983 #include "config/mips/mips-ftypes.def"
12984 #undef DEF_MIPS_FTYPE
12986 gcc_unreachable ();
12989 return types[(int) type];
12992 /* Implement TARGET_INIT_BUILTINS. */
12995 mips_init_builtins (void)
12997 const struct mips_builtin_description *d;
13000 /* Iterate through all of the bdesc arrays, initializing all of the
13001 builtin functions. */
13002 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13004 d = &mips_builtins[i];
13006 add_builtin_function (d->name,
13007 mips_build_function_type (d->function_type),
13008 i, BUILT_IN_MD, NULL, NULL);
13012 /* Take argument ARGNO from EXP's argument list and convert it into a
13013 form suitable for input operand OPNO of instruction ICODE. Return the
13017 mips_prepare_builtin_arg (enum insn_code icode,
13018 unsigned int opno, tree exp, unsigned int argno)
13022 enum machine_mode mode;
13024 arg = CALL_EXPR_ARG (exp, argno);
13025 value = expand_normal (arg);
13026 mode = insn_data[icode].operand[opno].mode;
13027 if (!insn_data[icode].operand[opno].predicate (value, mode))
13029 /* We need to get the mode from ARG for two reasons:
13031 - to cope with address operands, where MODE is the mode of the
13032 memory, rather than of VALUE itself.
13034 - to cope with special predicates like pmode_register_operand,
13035 where MODE is VOIDmode. */
13036 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
13038 /* Check the predicate again. */
13039 if (!insn_data[icode].operand[opno].predicate (value, mode))
13041 error ("invalid argument to built-in function");
13049 /* Return an rtx suitable for output operand OP of instruction ICODE.
13050 If TARGET is non-null, try to use it where possible. */
13053 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
13055 enum machine_mode mode;
13057 mode = insn_data[icode].operand[op].mode;
13058 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
13059 target = gen_reg_rtx (mode);
13064 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13065 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13066 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13067 suggests a good place to put the result. */
13070 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13073 rtx ops[MAX_RECOG_OPERANDS];
13076 /* Map any target to operand 0. */
13080 target = mips_prepare_builtin_target (icode, opno, target);
13081 ops[opno] = target;
13085 /* Map the arguments to the other operands. The n_operands value
13086 for an expander includes match_dups and match_scratches as well as
13087 match_operands, so n_operands is only an upper bound on the number
13088 of arguments to the expander function. */
13089 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
13090 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
13091 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
13096 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
13100 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
13104 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
13108 gcc_unreachable ();
13113 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13114 function; TYPE says which. EXP is the CALL_EXPR that calls the
13115 function, ICODE is the instruction that should be used to compare
13116 the first two arguments, and COND is the condition it should test.
13117 TARGET, if nonnull, suggests a good place to put the result. */
13120 mips_expand_builtin_movtf (enum mips_builtin_type type,
13121 enum insn_code icode, enum mips_fp_condition cond,
13122 rtx target, tree exp)
13124 rtx cmp_result, op0, op1;
13126 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13127 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
13128 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
13129 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
13131 icode = CODE_FOR_mips_cond_move_tf_ps;
13132 target = mips_prepare_builtin_target (icode, 0, target);
13133 if (type == MIPS_BUILTIN_MOVT)
13135 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
13136 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
13140 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
13141 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
13143 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
13147 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13148 into TARGET otherwise. Return TARGET. */
13151 mips_builtin_branch_and_move (rtx condition, rtx target,
13152 rtx value_if_true, rtx value_if_false)
13154 rtx true_label, done_label;
13156 true_label = gen_label_rtx ();
13157 done_label = gen_label_rtx ();
13159 /* First assume that CONDITION is false. */
13160 mips_emit_move (target, value_if_false);
13162 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13163 emit_jump_insn (gen_condjump (condition, true_label));
13164 emit_jump_insn (gen_jump (done_label));
13167 /* Fix TARGET if CONDITION is true. */
13168 emit_label (true_label);
13169 mips_emit_move (target, value_if_true);
13171 emit_label (done_label);
13175 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13176 the CALL_EXPR that calls the function, ICODE is the code of the
13177 comparison instruction, and COND is the condition it should test.
13178 TARGET, if nonnull, suggests a good place to put the boolean result. */
13181 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13182 enum insn_code icode, enum mips_fp_condition cond,
13183 rtx target, tree exp)
13185 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
13188 if (target == 0 || GET_MODE (target) != SImode)
13189 target = gen_reg_rtx (SImode);
13191 /* The instruction should have a target operand, an operand for each
13192 argument, and an operand for COND. */
13193 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
13195 /* Prepare the operands to the comparison. */
13196 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13197 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13198 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
13200 switch (insn_data[icode].n_operands)
13203 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13208 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13209 args[2], args[3], GEN_INT (cond)));
13213 gcc_unreachable ();
13216 /* If the comparison sets more than one register, we define the result
13217 to be 0 if all registers are false and -1 if all registers are true.
13218 The value of the complete result is indeterminate otherwise. */
13219 switch (builtin_type)
13221 case MIPS_BUILTIN_CMP_ALL:
13222 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13223 return mips_builtin_branch_and_move (condition, target,
13224 const0_rtx, const1_rtx);
13226 case MIPS_BUILTIN_CMP_UPPER:
13227 case MIPS_BUILTIN_CMP_LOWER:
13228 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13229 condition = gen_single_cc (cmp_result, offset);
13230 return mips_builtin_branch_and_move (condition, target,
13231 const1_rtx, const0_rtx);
13234 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13235 return mips_builtin_branch_and_move (condition, target,
13236 const1_rtx, const0_rtx);
13240 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13241 if nonnull, suggests a good place to put the boolean result. */
13244 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13246 rtx condition, cmp_result;
13249 if (target == 0 || GET_MODE (target) != SImode)
13250 target = gen_reg_rtx (SImode);
13252 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13254 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13259 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13260 return mips_builtin_branch_and_move (condition, target,
13261 const1_rtx, const0_rtx);
13264 /* Implement TARGET_EXPAND_BUILTIN. */
13267 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13268 enum machine_mode mode, int ignore)
13271 unsigned int fcode, avail;
13272 const struct mips_builtin_description *d;
13274 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13275 fcode = DECL_FUNCTION_CODE (fndecl);
13276 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13277 d = &mips_builtins[fcode];
13278 avail = d->avail ();
13279 gcc_assert (avail != 0);
13282 error ("built-in function %qE not supported for MIPS16",
13283 DECL_NAME (fndecl));
13284 return ignore ? const0_rtx : CONST0_RTX (mode);
13286 switch (d->builtin_type)
13288 case MIPS_BUILTIN_DIRECT:
13289 return mips_expand_builtin_direct (d->icode, target, exp, true);
13291 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13292 return mips_expand_builtin_direct (d->icode, target, exp, false);
13294 case MIPS_BUILTIN_MOVT:
13295 case MIPS_BUILTIN_MOVF:
13296 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13297 d->cond, target, exp);
13299 case MIPS_BUILTIN_CMP_ANY:
13300 case MIPS_BUILTIN_CMP_ALL:
13301 case MIPS_BUILTIN_CMP_UPPER:
13302 case MIPS_BUILTIN_CMP_LOWER:
13303 case MIPS_BUILTIN_CMP_SINGLE:
13304 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13305 d->cond, target, exp);
13307 case MIPS_BUILTIN_BPOSGE32:
13308 return mips_expand_builtin_bposge (d->builtin_type, target);
13310 gcc_unreachable ();
13313 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13314 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13315 struct mips16_constant {
13316 struct mips16_constant *next;
13319 enum machine_mode mode;
13322 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13323 first constant, HIGHEST_ADDRESS is the highest address that the first
13324 byte of the pool can have, and INSN_ADDRESS is the current instruction
13326 struct mips16_constant_pool {
13327 struct mips16_constant *first;
13328 int highest_address;
13332 /* Add constant VALUE to POOL and return its label. MODE is the
13333 value's mode (used for CONST_INTs, etc.). */
13336 mips16_add_constant (struct mips16_constant_pool *pool,
13337 rtx value, enum machine_mode mode)
13339 struct mips16_constant **p, *c;
13340 bool first_of_size_p;
13342 /* See whether the constant is already in the pool. If so, return the
13343 existing label, otherwise leave P pointing to the place where the
13344 constant should be added.
13346 Keep the pool sorted in increasing order of mode size so that we can
13347 reduce the number of alignments needed. */
13348 first_of_size_p = true;
13349 for (p = &pool->first; *p != 0; p = &(*p)->next)
13351 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13352 return (*p)->label;
13353 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13355 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13356 first_of_size_p = false;
13359 /* In the worst case, the constant needed by the earliest instruction
13360 will end up at the end of the pool. The entire pool must then be
13361 accessible from that instruction.
13363 When adding the first constant, set the pool's highest address to
13364 the address of the first out-of-range byte. Adjust this address
13365 downwards each time a new constant is added. */
13366 if (pool->first == 0)
13367 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13368 of the instruction with the lowest two bits clear. The base PC
13369 value for LDPC has the lowest three bits clear. Assume the worst
13370 case here; namely that the PC-relative instruction occupies the
13371 last 2 bytes in an aligned word. */
13372 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13373 pool->highest_address -= GET_MODE_SIZE (mode);
13374 if (first_of_size_p)
13375 /* Take into account the worst possible padding due to alignment. */
13376 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13378 /* Create a new entry. */
13379 c = XNEW (struct mips16_constant);
13382 c->label = gen_label_rtx ();
13389 /* Output constant VALUE after instruction INSN and return the last
13390 instruction emitted. MODE is the mode of the constant. */
13393 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13395 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13397 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13398 return emit_insn_after (gen_consttable_int (value, size), insn);
13401 if (SCALAR_FLOAT_MODE_P (mode))
13402 return emit_insn_after (gen_consttable_float (value), insn);
13404 if (VECTOR_MODE_P (mode))
13408 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13409 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13410 CONST_VECTOR_ELT (value, i), insn);
13414 gcc_unreachable ();
13417 /* Dump out the constants in CONSTANTS after INSN. */
13420 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13422 struct mips16_constant *c, *next;
13426 for (c = constants; c != NULL; c = next)
13428 /* If necessary, increase the alignment of PC. */
13429 if (align < GET_MODE_SIZE (c->mode))
13431 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13432 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13434 align = GET_MODE_SIZE (c->mode);
13436 insn = emit_label_after (c->label, insn);
13437 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13443 emit_barrier_after (insn);
13446 /* Return the length of instruction INSN. */
13449 mips16_insn_length (rtx insn)
13453 rtx body = PATTERN (insn);
13454 if (GET_CODE (body) == ADDR_VEC)
13455 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13456 if (GET_CODE (body) == ADDR_DIFF_VEC)
13457 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13459 return get_attr_length (insn);
13462 /* If *X is a symbolic constant that refers to the constant pool, add
13463 the constant to POOL and rewrite *X to use the constant's label. */
13466 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13468 rtx base, offset, label;
13470 split_const (*x, &base, &offset);
13471 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13473 label = mips16_add_constant (pool, get_pool_constant (base),
13474 get_pool_mode (base));
13475 base = gen_rtx_LABEL_REF (Pmode, label);
13476 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13480 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13481 INSN is the instruction we're rewriting and POOL points to the current
13483 struct mips16_rewrite_pool_refs_info {
13485 struct mips16_constant_pool *pool;
13488 /* Rewrite *X so that constant pool references refer to the constant's
13489 label instead. DATA points to a mips16_rewrite_pool_refs_info
13493 mips16_rewrite_pool_refs (rtx *x, void *data)
13495 struct mips16_rewrite_pool_refs_info *info =
13496 (struct mips16_rewrite_pool_refs_info *) data;
13498 if (force_to_mem_operand (*x, Pmode))
13500 rtx mem = force_const_mem (GET_MODE (*x), *x);
13501 validate_change (info->insn, x, mem, false);
13506 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13510 if (TARGET_MIPS16_TEXT_LOADS)
13511 mips16_rewrite_pool_constant (info->pool, x);
13513 return GET_CODE (*x) == CONST ? -1 : 0;
13516 /* Return whether CFG is used in mips_reorg. */
13519 mips_cfg_in_reorg (void)
13521 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13522 || TARGET_RELAX_PIC_CALLS);
13525 /* Build MIPS16 constant pools. */
13528 mips16_lay_out_constants (void)
13530 struct mips16_constant_pool pool;
13531 struct mips16_rewrite_pool_refs_info info;
13534 if (!TARGET_MIPS16_PCREL_LOADS)
13537 if (mips_cfg_in_reorg ())
13538 split_all_insns ();
13540 split_all_insns_noflow ();
13542 memset (&pool, 0, sizeof (pool));
13543 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13545 /* Rewrite constant pool references in INSN. */
13546 if (USEFUL_INSN_P (insn))
13550 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13553 pool.insn_address += mips16_insn_length (insn);
13555 if (pool.first != NULL)
13557 /* If there are no natural barriers between the first user of
13558 the pool and the highest acceptable address, we'll need to
13559 create a new instruction to jump around the constant pool.
13560 In the worst case, this instruction will be 4 bytes long.
13562 If it's too late to do this transformation after INSN,
13563 do it immediately before INSN. */
13564 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13568 label = gen_label_rtx ();
13570 jump = emit_jump_insn_before (gen_jump (label), insn);
13571 JUMP_LABEL (jump) = label;
13572 LABEL_NUSES (label) = 1;
13573 barrier = emit_barrier_after (jump);
13575 emit_label_after (label, barrier);
13576 pool.insn_address += 4;
13579 /* See whether the constant pool is now out of range of the first
13580 user. If so, output the constants after the previous barrier.
13581 Note that any instructions between BARRIER and INSN (inclusive)
13582 will use negative offsets to refer to the pool. */
13583 if (pool.insn_address > pool.highest_address)
13585 mips16_emit_constants (pool.first, barrier);
13589 else if (BARRIER_P (insn))
13593 mips16_emit_constants (pool.first, get_last_insn ());
13596 /* Return true if it is worth r10k_simplify_address's while replacing
13597 an address with X. We are looking for constants, and for addresses
13598 at a known offset from the incoming stack pointer. */
13601 r10k_simplified_address_p (rtx x)
13603 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13605 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13608 /* X is an expression that appears in INSN. Try to use the UD chains
13609 to simplify it, returning the simplified form on success and the
13610 original form otherwise. Replace the incoming value of $sp with
13611 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13614 r10k_simplify_address (rtx x, rtx insn)
13616 rtx newx, op0, op1, set, def_insn, note;
13618 struct df_link *defs;
13623 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13624 if (op0 != XEXP (x, 0))
13625 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13626 op0, GET_MODE (XEXP (x, 0)));
13628 else if (BINARY_P (x))
13630 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13631 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13632 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13633 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13635 else if (GET_CODE (x) == LO_SUM)
13637 /* LO_SUMs can be offset from HIGHs, if we know they won't
13638 overflow. See mips_classify_address for the rationale behind
13640 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13641 if (GET_CODE (op0) == HIGH)
13642 newx = XEXP (x, 1);
13644 else if (REG_P (x))
13646 /* Uses are recorded by regno_reg_rtx, not X itself. */
13647 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13649 defs = DF_REF_CHAIN (use);
13651 /* Require a single definition. */
13652 if (defs && defs->next == NULL)
13655 if (DF_REF_IS_ARTIFICIAL (def))
13657 /* Replace the incoming value of $sp with
13658 virtual_incoming_args_rtx. */
13659 if (x == stack_pointer_rtx
13660 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13661 newx = virtual_incoming_args_rtx;
13663 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13666 /* Make sure that DEF_INSN is a single set of REG. */
13667 def_insn = DF_REF_INSN (def);
13668 if (NONJUMP_INSN_P (def_insn))
13670 set = single_set (def_insn);
13671 if (set && rtx_equal_p (SET_DEST (set), x))
13673 /* Prefer to use notes, since the def-use chains
13674 are often shorter. */
13675 note = find_reg_equal_equiv_note (def_insn);
13677 newx = XEXP (note, 0);
13679 newx = SET_SRC (set);
13680 newx = r10k_simplify_address (newx, def_insn);
13686 if (newx && r10k_simplified_address_p (newx))
13691 /* Return true if ADDRESS is known to be an uncached address
13692 on R10K systems. */
13695 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13697 unsigned HOST_WIDE_INT upper;
13699 /* Check for KSEG1. */
13700 if (address + 0x60000000 < 0x20000000)
13703 /* Check for uncached XKPHYS addresses. */
13704 if (Pmode == DImode)
13706 upper = (address >> 40) & 0xf9ffff;
13707 if (upper == 0x900000 || upper == 0xb80000)
13713 /* Return true if we can prove that an access to address X in instruction
13714 INSN would be safe from R10K speculation. This X is a general
13715 expression; it might not be a legitimate address. */
13718 r10k_safe_address_p (rtx x, rtx insn)
13721 HOST_WIDE_INT offset_val;
13723 x = r10k_simplify_address (x, insn);
13725 /* Check for references to the stack frame. It doesn't really matter
13726 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13727 allows us to assume that accesses to any part of the eventual frame
13728 is safe from speculation at any point in the function. */
13729 mips_split_plus (x, &base, &offset_val);
13730 if (base == virtual_incoming_args_rtx
13731 && offset_val >= -cfun->machine->frame.total_size
13732 && offset_val < cfun->machine->frame.args_size)
13735 /* Check for uncached addresses. */
13736 if (CONST_INT_P (x))
13737 return r10k_uncached_address_p (INTVAL (x));
13739 /* Check for accesses to a static object. */
13740 split_const (x, &base, &offset);
13741 return offset_within_block_p (base, INTVAL (offset));
13744 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13745 an in-range access to an automatic variable, or to an object with
13746 a link-time-constant address. */
13749 r10k_safe_mem_expr_p (tree expr, rtx offset)
13751 if (expr == NULL_TREE
13752 || offset == NULL_RTX
13753 || !CONST_INT_P (offset)
13754 || INTVAL (offset) < 0
13755 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13758 while (TREE_CODE (expr) == COMPONENT_REF)
13760 expr = TREE_OPERAND (expr, 0);
13761 if (expr == NULL_TREE)
13765 return DECL_P (expr);
13768 /* A for_each_rtx callback for which DATA points to the instruction
13769 containing *X. Stop the search if we find a MEM that is not safe
13770 from R10K speculation. */
13773 r10k_needs_protection_p_1 (rtx *loc, void *data)
13781 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13784 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13790 /* A note_stores callback for which DATA points to an instruction pointer.
13791 If *DATA is nonnull, make it null if it X contains a MEM that is not
13792 safe from R10K speculation. */
13795 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13800 insn_ptr = (rtx *) data;
13801 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13802 *insn_ptr = NULL_RTX;
13805 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13806 Return nonzero if the call is not to a declared function. */
13809 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13818 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13824 /* Return true if instruction INSN needs to be protected by an R10K
13828 r10k_needs_protection_p (rtx insn)
13831 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13833 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13835 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13836 return insn == NULL_RTX;
13839 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13842 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13843 edge is unconditional. */
13846 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13851 FOR_EACH_EDGE (e, ei, bb->preds)
13852 if (!single_succ_p (e->src)
13853 || !TEST_BIT (protected_bbs, e->src->index)
13854 || (e->flags & EDGE_COMPLEX) != 0)
13859 /* Implement -mr10k-cache-barrier= for the current function. */
13862 r10k_insert_cache_barriers (void)
13864 int *rev_post_order;
13867 sbitmap protected_bbs;
13868 rtx insn, end, unprotected_region;
13872 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13876 /* Calculate dominators. */
13877 calculate_dominance_info (CDI_DOMINATORS);
13879 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13880 X is protected by a cache barrier. */
13881 protected_bbs = sbitmap_alloc (last_basic_block);
13882 sbitmap_zero (protected_bbs);
13884 /* Iterate over the basic blocks in reverse post-order. */
13885 rev_post_order = XNEWVEC (int, last_basic_block);
13886 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13887 for (i = 0; i < n; i++)
13889 bb = BASIC_BLOCK (rev_post_order[i]);
13891 /* If this block is only reached by unconditional edges, and if the
13892 source of every edge is protected, the beginning of the block is
13894 if (r10k_protected_bb_p (bb, protected_bbs))
13895 unprotected_region = NULL_RTX;
13897 unprotected_region = pc_rtx;
13898 end = NEXT_INSN (BB_END (bb));
13900 /* UNPROTECTED_REGION is:
13902 - null if we are processing a protected region,
13903 - pc_rtx if we are processing an unprotected region but have
13904 not yet found the first instruction in it
13905 - the first instruction in an unprotected region otherwise. */
13906 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13908 if (unprotected_region && USEFUL_INSN_P (insn))
13910 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13911 /* This CACHE instruction protects the following code. */
13912 unprotected_region = NULL_RTX;
13915 /* See if INSN is the first instruction in this
13916 unprotected region. */
13917 if (unprotected_region == pc_rtx)
13918 unprotected_region = insn;
13920 /* See if INSN needs to be protected. If so,
13921 we must insert a cache barrier somewhere between
13922 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13923 clear which position is better performance-wise,
13924 but as a tie-breaker, we assume that it is better
13925 to allow delay slots to be back-filled where
13926 possible, and that it is better not to insert
13927 barriers in the middle of already-scheduled code.
13928 We therefore insert the barrier at the beginning
13930 if (r10k_needs_protection_p (insn))
13932 emit_insn_before (gen_r10k_cache_barrier (),
13933 unprotected_region);
13934 unprotected_region = NULL_RTX;
13940 /* The called function is not required to protect the exit path.
13941 The code that follows a call is therefore unprotected. */
13942 unprotected_region = pc_rtx;
13945 /* Record whether the end of this block is protected. */
13946 if (unprotected_region == NULL_RTX)
13947 SET_BIT (protected_bbs, bb->index);
13949 XDELETEVEC (rev_post_order);
13951 sbitmap_free (protected_bbs);
13953 free_dominance_info (CDI_DOMINATORS);
13956 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
13960 mips_call_expr_from_insn (rtx insn)
13964 if (!CALL_P (insn))
13967 x = PATTERN (insn);
13968 if (GET_CODE (x) == PARALLEL)
13969 x = XVECEXP (x, 0, 0);
13970 if (GET_CODE (x) == SET)
13973 gcc_assert (GET_CODE (x) == CALL);
13977 /* REG is set in DEF. See if the definition is one of the ways we load a
13978 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
13979 it is return the symbol reference of the function, otherwise return
13983 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
13987 if (DF_REF_IS_ARTIFICIAL (def))
13990 def_insn = DF_REF_INSN (def);
13991 set = single_set (def_insn);
13992 if (set && rtx_equal_p (SET_DEST (set), reg))
13994 rtx note, src, symbol;
13996 /* First, look at REG_EQUAL/EQUIV notes. */
13997 note = find_reg_equal_equiv_note (def_insn);
13998 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
13999 return XEXP (note, 0);
14001 /* For %call16 references we don't have REG_EQUAL. */
14002 src = SET_SRC (set);
14003 symbol = mips_strip_unspec_call (src);
14006 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14010 /* Follow simple register copies. */
14012 return mips_find_pic_call_symbol (def_insn, src);
14018 /* Find the definition of the use of REG in INSN. See if the definition is
14019 one of the ways we load a register with a symbol address for a
14020 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14021 the function, otherwise return NULL_RTX. */
14024 mips_find_pic_call_symbol (rtx insn, rtx reg)
14027 struct df_link *defs;
14030 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14033 defs = DF_REF_CHAIN (use);
14036 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14040 /* If we have more than one definition, they need to be identical. */
14041 for (defs = defs->next; defs; defs = defs->next)
14045 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14046 if (!rtx_equal_p (symbol, other))
14053 /* Replace the args_size operand of the call expression CALL with the
14054 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14057 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14061 args_size = XEXP (call, 1);
14062 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14063 gen_rtvec (2, args_size, symbol),
14067 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14068 if instead of the arg_size argument it contains the call attributes. If
14069 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14070 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14074 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14076 rtx args_size, symbol;
14078 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14081 args_size = operands[args_size_opno];
14082 if (GET_CODE (args_size) != UNSPEC)
14084 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14086 symbol = XVECEXP (args_size, 0, 1);
14087 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14089 operands[args_size_opno] = symbol;
14093 /* Use DF to annotate PIC indirect calls with the function symbol they
14097 mips_annotate_pic_calls (void)
14103 FOR_BB_INSNS (bb, insn)
14105 rtx call, reg, symbol;
14107 call = mips_call_expr_from_insn (insn);
14110 gcc_assert (MEM_P (XEXP (call, 0)));
14111 reg = XEXP (XEXP (call, 0), 0);
14115 symbol = mips_find_pic_call_symbol (insn, reg);
14117 mips_annotate_pic_call_expr (call, symbol);
14121 /* A temporary variable used by for_each_rtx callbacks, etc. */
14122 static rtx mips_sim_insn;
14124 /* A structure representing the state of the processor pipeline.
14125 Used by the mips_sim_* family of functions. */
14127 /* The maximum number of instructions that can be issued in a cycle.
14128 (Caches mips_issue_rate.) */
14129 unsigned int issue_rate;
14131 /* The current simulation time. */
14134 /* How many more instructions can be issued in the current cycle. */
14135 unsigned int insns_left;
14137 /* LAST_SET[X].INSN is the last instruction to set register X.
14138 LAST_SET[X].TIME is the time at which that instruction was issued.
14139 INSN is null if no instruction has yet set register X. */
14143 } last_set[FIRST_PSEUDO_REGISTER];
14145 /* The pipeline's current DFA state. */
14149 /* Reset STATE to the initial simulation state. */
14152 mips_sim_reset (struct mips_sim *state)
14155 state->insns_left = state->issue_rate;
14156 memset (&state->last_set, 0, sizeof (state->last_set));
14157 state_reset (state->dfa_state);
14160 /* Initialize STATE before its first use. DFA_STATE points to an
14161 allocated but uninitialized DFA state. */
14164 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14166 state->issue_rate = mips_issue_rate ();
14167 state->dfa_state = dfa_state;
14168 mips_sim_reset (state);
14171 /* Advance STATE by one clock cycle. */
14174 mips_sim_next_cycle (struct mips_sim *state)
14177 state->insns_left = state->issue_rate;
14178 state_transition (state->dfa_state, 0);
14181 /* Advance simulation state STATE until instruction INSN can read
14185 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14187 unsigned int regno, end_regno;
14189 end_regno = END_REGNO (reg);
14190 for (regno = REGNO (reg); regno < end_regno; regno++)
14191 if (state->last_set[regno].insn != 0)
14195 t = (state->last_set[regno].time
14196 + insn_latency (state->last_set[regno].insn, insn));
14197 while (state->time < t)
14198 mips_sim_next_cycle (state);
14202 /* A for_each_rtx callback. If *X is a register, advance simulation state
14203 DATA until mips_sim_insn can read the register's value. */
14206 mips_sim_wait_regs_2 (rtx *x, void *data)
14209 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14213 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14216 mips_sim_wait_regs_1 (rtx *x, void *data)
14218 for_each_rtx (x, mips_sim_wait_regs_2, data);
14221 /* Advance simulation state STATE until all of INSN's register
14222 dependencies are satisfied. */
14225 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14227 mips_sim_insn = insn;
14228 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14231 /* Advance simulation state STATE until the units required by
14232 instruction INSN are available. */
14235 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14239 tmp_state = alloca (state_size ());
14240 while (state->insns_left == 0
14241 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14242 state_transition (tmp_state, insn) >= 0))
14243 mips_sim_next_cycle (state);
14246 /* Advance simulation state STATE until INSN is ready to issue. */
14249 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14251 mips_sim_wait_regs (state, insn);
14252 mips_sim_wait_units (state, insn);
14255 /* mips_sim_insn has just set X. Update the LAST_SET array
14256 in simulation state DATA. */
14259 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14261 struct mips_sim *state;
14263 state = (struct mips_sim *) data;
14266 unsigned int regno, end_regno;
14268 end_regno = END_REGNO (x);
14269 for (regno = REGNO (x); regno < end_regno; regno++)
14271 state->last_set[regno].insn = mips_sim_insn;
14272 state->last_set[regno].time = state->time;
14277 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14278 can issue immediately (i.e., that mips_sim_wait_insn has already
14282 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14284 state_transition (state->dfa_state, insn);
14285 state->insns_left--;
14287 mips_sim_insn = insn;
14288 note_stores (PATTERN (insn), mips_sim_record_set, state);
14291 /* Simulate issuing a NOP in state STATE. */
14294 mips_sim_issue_nop (struct mips_sim *state)
14296 if (state->insns_left == 0)
14297 mips_sim_next_cycle (state);
14298 state->insns_left--;
14301 /* Update simulation state STATE so that it's ready to accept the instruction
14302 after INSN. INSN should be part of the main rtl chain, not a member of a
14306 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14308 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14310 mips_sim_issue_nop (state);
14312 switch (GET_CODE (SEQ_BEGIN (insn)))
14316 /* We can't predict the processor state after a call or label. */
14317 mips_sim_reset (state);
14321 /* The delay slots of branch likely instructions are only executed
14322 when the branch is taken. Therefore, if the caller has simulated
14323 the delay slot instruction, STATE does not really reflect the state
14324 of the pipeline for the instruction after the delay slot. Also,
14325 branch likely instructions tend to incur a penalty when not taken,
14326 so there will probably be an extra delay between the branch and
14327 the instruction after the delay slot. */
14328 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14329 mips_sim_reset (state);
14337 /* The VR4130 pipeline issues aligned pairs of instructions together,
14338 but it stalls the second instruction if it depends on the first.
14339 In order to cut down the amount of logic required, this dependence
14340 check is not based on a full instruction decode. Instead, any non-SPECIAL
14341 instruction is assumed to modify the register specified by bits 20-16
14342 (which is usually the "rt" field).
14344 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14345 input, so we can end up with a false dependence between the branch
14346 and its delay slot. If this situation occurs in instruction INSN,
14347 try to avoid it by swapping rs and rt. */
14350 vr4130_avoid_branch_rt_conflict (rtx insn)
14354 first = SEQ_BEGIN (insn);
14355 second = SEQ_END (insn);
14357 && NONJUMP_INSN_P (second)
14358 && GET_CODE (PATTERN (first)) == SET
14359 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14360 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14362 /* Check for the right kind of condition. */
14363 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14364 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14365 && REG_P (XEXP (cond, 0))
14366 && REG_P (XEXP (cond, 1))
14367 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14368 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14370 /* SECOND mentions the rt register but not the rs register. */
14371 rtx tmp = XEXP (cond, 0);
14372 XEXP (cond, 0) = XEXP (cond, 1);
14373 XEXP (cond, 1) = tmp;
14378 /* Implement -mvr4130-align. Go through each basic block and simulate the
14379 processor pipeline. If we find that a pair of instructions could execute
14380 in parallel, and the first of those instructions is not 8-byte aligned,
14381 insert a nop to make it aligned. */
14384 vr4130_align_insns (void)
14386 struct mips_sim state;
14387 rtx insn, subinsn, last, last2, next;
14392 /* LAST is the last instruction before INSN to have a nonzero length.
14393 LAST2 is the last such instruction before LAST. */
14397 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14400 mips_sim_init (&state, alloca (state_size ()));
14401 for (insn = get_insns (); insn != 0; insn = next)
14403 unsigned int length;
14405 next = NEXT_INSN (insn);
14407 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14408 This isn't really related to the alignment pass, but we do it on
14409 the fly to avoid a separate instruction walk. */
14410 vr4130_avoid_branch_rt_conflict (insn);
14412 if (USEFUL_INSN_P (insn))
14413 FOR_EACH_SUBINSN (subinsn, insn)
14415 mips_sim_wait_insn (&state, subinsn);
14417 /* If we want this instruction to issue in parallel with the
14418 previous one, make sure that the previous instruction is
14419 aligned. There are several reasons why this isn't worthwhile
14420 when the second instruction is a call:
14422 - Calls are less likely to be performance critical,
14423 - There's a good chance that the delay slot can execute
14424 in parallel with the call.
14425 - The return address would then be unaligned.
14427 In general, if we're going to insert a nop between instructions
14428 X and Y, it's better to insert it immediately after X. That
14429 way, if the nop makes Y aligned, it will also align any labels
14430 between X and Y. */
14431 if (state.insns_left != state.issue_rate
14432 && !CALL_P (subinsn))
14434 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14436 /* SUBINSN is the first instruction in INSN and INSN is
14437 aligned. We want to align the previous instruction
14438 instead, so insert a nop between LAST2 and LAST.
14440 Note that LAST could be either a single instruction
14441 or a branch with a delay slot. In the latter case,
14442 LAST, like INSN, is already aligned, but the delay
14443 slot must have some extra delay that stops it from
14444 issuing at the same time as the branch. We therefore
14445 insert a nop before the branch in order to align its
14447 emit_insn_after (gen_nop (), last2);
14450 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14452 /* SUBINSN is the delay slot of INSN, but INSN is
14453 currently unaligned. Insert a nop between
14454 LAST and INSN to align it. */
14455 emit_insn_after (gen_nop (), last);
14459 mips_sim_issue_insn (&state, subinsn);
14461 mips_sim_finish_insn (&state, insn);
14463 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14464 length = get_attr_length (insn);
14467 /* If the instruction is an asm statement or multi-instruction
14468 mips.md patern, the length is only an estimate. Insert an
14469 8 byte alignment after it so that the following instructions
14470 can be handled correctly. */
14471 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14472 && (recog_memoized (insn) < 0 || length >= 8))
14474 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14475 next = NEXT_INSN (next);
14476 mips_sim_next_cycle (&state);
14479 else if (length & 4)
14480 aligned_p = !aligned_p;
14485 /* See whether INSN is an aligned label. */
14486 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14492 /* This structure records that the current function has a LO_SUM
14493 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14494 the largest offset applied to BASE by all such LO_SUMs. */
14495 struct mips_lo_sum_offset {
14497 HOST_WIDE_INT offset;
14500 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14503 mips_hash_base (rtx base)
14505 int do_not_record_p;
14507 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14510 /* Hash-table callbacks for mips_lo_sum_offsets. */
14513 mips_lo_sum_offset_hash (const void *entry)
14515 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14519 mips_lo_sum_offset_eq (const void *entry, const void *value)
14521 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14522 (const_rtx) value);
14525 /* Look up symbolic constant X in HTAB, which is a hash table of
14526 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14527 paired with a recorded LO_SUM, otherwise record X in the table. */
14530 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14534 struct mips_lo_sum_offset *entry;
14536 /* Split X into a base and offset. */
14537 split_const (x, &base, &offset);
14538 if (UNSPEC_ADDRESS_P (base))
14539 base = UNSPEC_ADDRESS (base);
14541 /* Look up the base in the hash table. */
14542 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14546 entry = (struct mips_lo_sum_offset *) *slot;
14547 if (option == INSERT)
14551 entry = XNEW (struct mips_lo_sum_offset);
14552 entry->base = base;
14553 entry->offset = INTVAL (offset);
14558 if (INTVAL (offset) > entry->offset)
14559 entry->offset = INTVAL (offset);
14562 return INTVAL (offset) <= entry->offset;
14565 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14566 Record every LO_SUM in *LOC. */
14569 mips_record_lo_sum (rtx *loc, void *data)
14571 if (GET_CODE (*loc) == LO_SUM)
14572 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14576 /* Return true if INSN is a SET of an orphaned high-part relocation.
14577 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14578 LO_SUMs in the current function. */
14581 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14583 enum mips_symbol_type type;
14586 set = single_set (insn);
14589 /* Check for %his. */
14591 if (GET_CODE (x) == HIGH
14592 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14593 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14595 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14596 if (GET_CODE (x) == UNSPEC
14597 && XINT (x, 1) == UNSPEC_LOAD_GOT
14598 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14599 SYMBOL_CONTEXT_LEA, &type)
14600 && type == SYMBOL_GOTOFF_PAGE)
14601 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14606 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14607 INSN and a previous instruction, avoid it by inserting nops after
14610 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14611 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14612 before using the value of that register. *HILO_DELAY counts the
14613 number of instructions since the last hilo hazard (that is,
14614 the number of instructions since the last MFLO or MFHI).
14616 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14617 for the next instruction.
14619 LO_REG is an rtx for the LO register, used in dependence checking. */
14622 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14623 rtx *delayed_reg, rtx lo_reg)
14628 pattern = PATTERN (insn);
14630 /* Do not put the whole function in .set noreorder if it contains
14631 an asm statement. We don't know whether there will be hazards
14632 between the asm statement and the gcc-generated code. */
14633 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14634 cfun->machine->all_noreorder_p = false;
14636 /* Ignore zero-length instructions (barriers and the like). */
14637 ninsns = get_attr_length (insn) / 4;
14641 /* Work out how many nops are needed. Note that we only care about
14642 registers that are explicitly mentioned in the instruction's pattern.
14643 It doesn't matter that calls use the argument registers or that they
14644 clobber hi and lo. */
14645 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14646 nops = 2 - *hilo_delay;
14647 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14652 /* Insert the nops between this instruction and the previous one.
14653 Each new nop takes us further from the last hilo hazard. */
14654 *hilo_delay += nops;
14656 emit_insn_after (gen_hazard_nop (), after);
14658 /* Set up the state for the next instruction. */
14659 *hilo_delay += ninsns;
14661 if (INSN_CODE (insn) >= 0)
14662 switch (get_attr_hazard (insn))
14672 set = single_set (insn);
14674 *delayed_reg = SET_DEST (set);
14679 /* Go through the instruction stream and insert nops where necessary.
14680 Also delete any high-part relocations whose partnering low parts
14681 are now all dead. See if the whole function can then be put into
14682 .set noreorder and .set nomacro. */
14685 mips_reorg_process_insns (void)
14687 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14691 /* Force all instructions to be split into their final form. */
14692 split_all_insns_noflow ();
14694 /* Recalculate instruction lengths without taking nops into account. */
14695 cfun->machine->ignore_hazard_length_p = true;
14696 shorten_branches (get_insns ());
14698 cfun->machine->all_noreorder_p = true;
14700 /* We don't track MIPS16 PC-relative offsets closely enough to make
14701 a good job of "set .noreorder" code in MIPS16 mode. */
14703 cfun->machine->all_noreorder_p = false;
14705 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14706 if (!TARGET_EXPLICIT_RELOCS)
14707 cfun->machine->all_noreorder_p = false;
14709 /* Profiled functions can't be all noreorder because the profiler
14710 support uses assembler macros. */
14712 cfun->machine->all_noreorder_p = false;
14714 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14715 we rely on the assembler to work around some errata. */
14716 if (TARGET_FIX_VR4120)
14717 cfun->machine->all_noreorder_p = false;
14719 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14720 MFHI instructions. Note that we avoid using MFLO and MFHI if
14721 the VR4130 MACC and DMACC instructions are available instead;
14722 see the *mfhilo_{si,di}_macc patterns. */
14723 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14724 cfun->machine->all_noreorder_p = false;
14726 htab = htab_create (37, mips_lo_sum_offset_hash,
14727 mips_lo_sum_offset_eq, free);
14729 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14730 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14731 FOR_EACH_SUBINSN (subinsn, insn)
14732 if (USEFUL_INSN_P (subinsn))
14733 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14738 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14740 /* Make a second pass over the instructions. Delete orphaned
14741 high-part relocations or turn them into NOPs. Avoid hazards
14742 by inserting NOPs. */
14743 for (insn = get_insns (); insn != 0; insn = next_insn)
14745 next_insn = NEXT_INSN (insn);
14746 if (USEFUL_INSN_P (insn))
14748 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14750 /* If we find an orphaned high-part relocation in a delay
14751 slot, it's easier to turn that instruction into a NOP than
14752 to delete it. The delay slot will be a NOP either way. */
14753 FOR_EACH_SUBINSN (subinsn, insn)
14754 if (INSN_P (subinsn))
14756 if (mips_orphaned_high_part_p (htab, subinsn))
14758 PATTERN (subinsn) = gen_nop ();
14759 INSN_CODE (subinsn) = CODE_FOR_nop;
14761 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14762 &delayed_reg, lo_reg);
14768 /* INSN is a single instruction. Delete it if it's an
14769 orphaned high-part relocation. */
14770 if (mips_orphaned_high_part_p (htab, insn))
14771 delete_insn (insn);
14772 /* Also delete cache barriers if the last instruction
14773 was an annulled branch. INSN will not be speculatively
14775 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14777 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14778 delete_insn (insn);
14781 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14782 &delayed_reg, lo_reg);
14789 htab_delete (htab);
14792 /* If we are using a GOT, but have not decided to use a global pointer yet,
14793 see whether we need one to implement long branches. Convert the ghost
14794 global-pointer instructions into real ones if so. */
14797 mips_expand_ghost_gp_insns (void)
14802 /* Quick exit if we already know that we will or won't need a
14804 if (!TARGET_USE_GOT
14805 || cfun->machine->global_pointer == INVALID_REGNUM
14806 || mips_must_initialize_gp_p ())
14809 shorten_branches (get_insns ());
14811 /* Look for a branch that is longer than normal. The normal length for
14812 non-MIPS16 branches is 8, because the length includes the delay slot.
14813 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14814 but they have no delay slot. */
14815 normal_length = (TARGET_MIPS16 ? 4 : 8);
14816 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14818 && USEFUL_INSN_P (insn)
14819 && get_attr_length (insn) > normal_length)
14822 if (insn == NULL_RTX)
14825 /* We've now established that we need $gp. */
14826 cfun->machine->must_initialize_gp_p = true;
14827 split_all_insns_noflow ();
14832 /* Subroutine of mips_reorg to manage passes that require DF. */
14835 mips_df_reorg (void)
14837 /* Create def-use chains. */
14838 df_set_flags (DF_EQ_NOTES);
14839 df_chain_add_problem (DF_UD_CHAIN);
14842 if (TARGET_RELAX_PIC_CALLS)
14843 mips_annotate_pic_calls ();
14845 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
14846 r10k_insert_cache_barriers ();
14848 df_finish_pass (false);
14851 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14856 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14857 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14858 to date if the CFG is available. */
14859 if (mips_cfg_in_reorg ())
14860 compute_bb_for_insn ();
14861 mips16_lay_out_constants ();
14862 if (mips_cfg_in_reorg ())
14865 free_bb_for_insn ();
14868 if (optimize > 0 && flag_delayed_branch)
14869 dbr_schedule (get_insns ());
14870 mips_reorg_process_insns ();
14872 && TARGET_EXPLICIT_RELOCS
14874 && TARGET_VR4130_ALIGN)
14875 vr4130_align_insns ();
14876 if (mips_expand_ghost_gp_insns ())
14877 /* The expansion could invalidate some of the VR4130 alignment
14878 optimizations, but this should be an extremely rare case anyhow. */
14879 mips_reorg_process_insns ();
14882 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14883 in order to avoid duplicating too much logic from elsewhere. */
14886 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14887 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14890 rtx this_rtx, temp1, temp2, insn, fnaddr;
14891 bool use_sibcall_p;
14893 /* Pretend to be a post-reload pass while generating rtl. */
14894 reload_completed = 1;
14896 /* Mark the end of the (empty) prologue. */
14897 emit_note (NOTE_INSN_PROLOGUE_END);
14899 /* Determine if we can use a sibcall to call FUNCTION directly. */
14900 fnaddr = XEXP (DECL_RTL (function), 0);
14901 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
14902 && const_call_insn_operand (fnaddr, Pmode));
14904 /* Determine if we need to load FNADDR from the GOT. */
14906 && (mips_got_symbol_type_p
14907 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
14909 /* Pick a global pointer. Use a call-clobbered register if
14910 TARGET_CALL_SAVED_GP. */
14911 cfun->machine->global_pointer
14912 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
14913 cfun->machine->must_initialize_gp_p = true;
14914 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
14916 /* Set up the global pointer for n32 or n64 abicalls. */
14917 mips_emit_loadgp ();
14920 /* We need two temporary registers in some cases. */
14921 temp1 = gen_rtx_REG (Pmode, 2);
14922 temp2 = gen_rtx_REG (Pmode, 3);
14924 /* Find out which register contains the "this" pointer. */
14925 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14926 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
14928 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
14930 /* Add DELTA to THIS_RTX. */
14933 rtx offset = GEN_INT (delta);
14934 if (!SMALL_OPERAND (delta))
14936 mips_emit_move (temp1, offset);
14939 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
14942 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
14943 if (vcall_offset != 0)
14947 /* Set TEMP1 to *THIS_RTX. */
14948 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
14950 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
14951 addr = mips_add_offset (temp2, temp1, vcall_offset);
14953 /* Load the offset and add it to THIS_RTX. */
14954 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
14955 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
14958 /* Jump to the target function. Use a sibcall if direct jumps are
14959 allowed, otherwise load the address into a register first. */
14962 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
14963 SIBLING_CALL_P (insn) = 1;
14967 /* This is messy. GAS treats "la $25,foo" as part of a call
14968 sequence and may allow a global "foo" to be lazily bound.
14969 The general move patterns therefore reject this combination.
14971 In this context, lazy binding would actually be OK
14972 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
14973 TARGET_CALL_SAVED_GP; see mips_load_call_address.
14974 We must therefore load the address via a temporary
14975 register if mips_dangerous_for_la25_p.
14977 If we jump to the temporary register rather than $25,
14978 the assembler can use the move insn to fill the jump's
14981 We can use the same technique for MIPS16 code, where $25
14982 is not a valid JR register. */
14983 if (TARGET_USE_PIC_FN_ADDR_REG
14985 && !mips_dangerous_for_la25_p (fnaddr))
14986 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
14987 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
14989 if (TARGET_USE_PIC_FN_ADDR_REG
14990 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
14991 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
14992 emit_jump_insn (gen_indirect_jump (temp1));
14995 /* Run just enough of rest_of_compilation. This sequence was
14996 "borrowed" from alpha.c. */
14997 insn = get_insns ();
14998 insn_locators_alloc ();
14999 split_all_insns_noflow ();
15000 mips16_lay_out_constants ();
15001 shorten_branches (insn);
15002 final_start_function (insn, file, 1);
15003 final (insn, file, 1);
15004 final_end_function ();
15006 /* Clean up the vars set above. Note that final_end_function resets
15007 the global pointer for us. */
15008 reload_completed = 0;
15011 /* The last argument passed to mips_set_mips16_mode, or negative if the
15012 function hasn't been called yet.
15014 There are two copies of this information. One is saved and restored
15015 by the PCH process while the other is specific to this compiler
15016 invocation. The information calculated by mips_set_mips16_mode
15017 is invalid unless the two variables are the same. */
15018 static int was_mips16_p = -1;
15019 static GTY(()) int was_mips16_pch_p = -1;
15021 /* Set up the target-dependent global state so that it matches the
15022 current function's ISA mode. */
15025 mips_set_mips16_mode (int mips16_p)
15027 if (mips16_p == was_mips16_p
15028 && mips16_p == was_mips16_pch_p)
15031 /* Restore base settings of various flags. */
15032 target_flags = mips_base_target_flags;
15033 flag_schedule_insns = mips_base_schedule_insns;
15034 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15035 flag_move_loop_invariants = mips_base_move_loop_invariants;
15036 align_loops = mips_base_align_loops;
15037 align_jumps = mips_base_align_jumps;
15038 align_functions = mips_base_align_functions;
15042 /* Switch to MIPS16 mode. */
15043 target_flags |= MASK_MIPS16;
15045 /* Don't run the scheduler before reload, since it tends to
15046 increase register pressure. */
15047 flag_schedule_insns = 0;
15049 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15050 the whole function to be in a single section. */
15051 flag_reorder_blocks_and_partition = 0;
15053 /* Don't move loop invariants, because it tends to increase
15054 register pressure. It also introduces an extra move in cases
15055 where the constant is the first operand in a two-operand binary
15056 instruction, or when it forms a register argument to a functon
15058 flag_move_loop_invariants = 0;
15060 target_flags |= MASK_EXPLICIT_RELOCS;
15062 /* Experiments suggest we get the best overall section-anchor
15063 results from using the range of an unextended LW or SW. Code
15064 that makes heavy use of byte or short accesses can do better
15065 with ranges of 0...31 and 0...63 respectively, but most code is
15066 sensitive to the range of LW and SW instead. */
15067 targetm.min_anchor_offset = 0;
15068 targetm.max_anchor_offset = 127;
15070 targetm.const_anchor = 0;
15072 /* MIPS16 has no BAL instruction. */
15073 target_flags &= ~MASK_RELAX_PIC_CALLS;
15075 if (flag_pic && !TARGET_OLDABI)
15076 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15079 sorry ("MIPS16 -mxgot code");
15081 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15082 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15086 /* Switch to normal (non-MIPS16) mode. */
15087 target_flags &= ~MASK_MIPS16;
15089 /* Provide default values for align_* for 64-bit targets. */
15092 if (align_loops == 0)
15094 if (align_jumps == 0)
15096 if (align_functions == 0)
15097 align_functions = 8;
15100 targetm.min_anchor_offset = -32768;
15101 targetm.max_anchor_offset = 32767;
15103 targetm.const_anchor = 0x8000;
15106 /* (Re)initialize MIPS target internals for new ISA. */
15107 mips_init_relocs ();
15109 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
15110 /* Reinitialize target-dependent state. */
15113 was_mips16_p = mips16_p;
15114 was_mips16_pch_p = mips16_p;
15117 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15118 function should use the MIPS16 ISA and switch modes accordingly. */
15121 mips_set_current_function (tree fndecl)
15123 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15126 /* Allocate a chunk of memory for per-function machine-dependent data. */
15128 static struct machine_function *
15129 mips_init_machine_status (void)
15131 return ((struct machine_function *)
15132 ggc_alloc_cleared (sizeof (struct machine_function)));
15135 /* Return the processor associated with the given ISA level, or null
15136 if the ISA isn't valid. */
15138 static const struct mips_cpu_info *
15139 mips_cpu_info_from_isa (int isa)
15143 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15144 if (mips_cpu_info_table[i].isa == isa)
15145 return mips_cpu_info_table + i;
15150 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15151 with a final "000" replaced by "k". Ignore case.
15153 Note: this function is shared between GCC and GAS. */
15156 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15158 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15159 given++, canonical++;
15161 return ((*given == 0 && *canonical == 0)
15162 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15165 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15166 CPU name. We've traditionally allowed a lot of variation here.
15168 Note: this function is shared between GCC and GAS. */
15171 mips_matching_cpu_name_p (const char *canonical, const char *given)
15173 /* First see if the name matches exactly, or with a final "000"
15174 turned into "k". */
15175 if (mips_strict_matching_cpu_name_p (canonical, given))
15178 /* If not, try comparing based on numerical designation alone.
15179 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15180 if (TOLOWER (*given) == 'r')
15182 if (!ISDIGIT (*given))
15185 /* Skip over some well-known prefixes in the canonical name,
15186 hoping to find a number there too. */
15187 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15189 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15191 else if (TOLOWER (canonical[0]) == 'r')
15194 return mips_strict_matching_cpu_name_p (canonical, given);
15197 /* Return the mips_cpu_info entry for the processor or ISA given
15198 by CPU_STRING. Return null if the string isn't recognized.
15200 A similar function exists in GAS. */
15202 static const struct mips_cpu_info *
15203 mips_parse_cpu (const char *cpu_string)
15208 /* In the past, we allowed upper-case CPU names, but it doesn't
15209 work well with the multilib machinery. */
15210 for (s = cpu_string; *s != 0; s++)
15213 warning (0, "CPU names must be lower case");
15217 /* 'from-abi' selects the most compatible architecture for the given
15218 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15219 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15221 if (strcasecmp (cpu_string, "from-abi") == 0)
15222 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15223 : ABI_NEEDS_64BIT_REGS ? 3
15224 : (TARGET_64BIT ? 3 : 1));
15226 /* 'default' has traditionally been a no-op. Probably not very useful. */
15227 if (strcasecmp (cpu_string, "default") == 0)
15230 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15231 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15232 return mips_cpu_info_table + i;
15237 /* Set up globals to generate code for the ISA or processor
15238 described by INFO. */
15241 mips_set_architecture (const struct mips_cpu_info *info)
15245 mips_arch_info = info;
15246 mips_arch = info->cpu;
15247 mips_isa = info->isa;
15251 /* Likewise for tuning. */
15254 mips_set_tune (const struct mips_cpu_info *info)
15258 mips_tune_info = info;
15259 mips_tune = info->cpu;
15263 /* Implement TARGET_HANDLE_OPTION. */
15266 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
15271 if (strcmp (arg, "32") == 0)
15273 else if (strcmp (arg, "o64") == 0)
15274 mips_abi = ABI_O64;
15275 else if (strcmp (arg, "n32") == 0)
15276 mips_abi = ABI_N32;
15277 else if (strcmp (arg, "64") == 0)
15279 else if (strcmp (arg, "eabi") == 0)
15280 mips_abi = ABI_EABI;
15287 return mips_parse_cpu (arg) != 0;
15290 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15291 return mips_isa_option_info != 0;
15293 case OPT_mno_flush_func:
15294 mips_cache_flush_func = NULL;
15297 case OPT_mcode_readable_:
15298 if (strcmp (arg, "yes") == 0)
15299 mips_code_readable = CODE_READABLE_YES;
15300 else if (strcmp (arg, "pcrel") == 0)
15301 mips_code_readable = CODE_READABLE_PCREL;
15302 else if (strcmp (arg, "no") == 0)
15303 mips_code_readable = CODE_READABLE_NO;
15308 case OPT_mr10k_cache_barrier_:
15309 if (strcmp (arg, "load-store") == 0)
15310 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15311 else if (strcmp (arg, "store") == 0)
15312 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15313 else if (strcmp (arg, "none") == 0)
15314 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15324 /* Implement OVERRIDE_OPTIONS. */
15327 mips_override_options (void)
15329 int i, start, regno, mode;
15331 /* Process flags as though we were generating non-MIPS16 code. */
15332 mips_base_mips16 = TARGET_MIPS16;
15333 target_flags &= ~MASK_MIPS16;
15335 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15336 SUBTARGET_OVERRIDE_OPTIONS;
15339 /* Set the small data limit. */
15340 mips_small_data_threshold = (g_switch_set
15342 : MIPS_DEFAULT_GVALUE);
15344 /* The following code determines the architecture and register size.
15345 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15346 The GAS and GCC code should be kept in sync as much as possible. */
15348 if (mips_arch_string != 0)
15349 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15351 if (mips_isa_option_info != 0)
15353 if (mips_arch_info == 0)
15354 mips_set_architecture (mips_isa_option_info);
15355 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15356 error ("%<-%s%> conflicts with the other architecture options, "
15357 "which specify a %s processor",
15358 mips_isa_option_info->name,
15359 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15362 if (mips_arch_info == 0)
15364 #ifdef MIPS_CPU_STRING_DEFAULT
15365 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15367 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15371 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15372 error ("%<-march=%s%> is not compatible with the selected ABI",
15373 mips_arch_info->name);
15375 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15376 if (mips_tune_string != 0)
15377 mips_set_tune (mips_parse_cpu (mips_tune_string));
15379 if (mips_tune_info == 0)
15380 mips_set_tune (mips_arch_info);
15382 if ((target_flags_explicit & MASK_64BIT) != 0)
15384 /* The user specified the size of the integer registers. Make sure
15385 it agrees with the ABI and ISA. */
15386 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15387 error ("%<-mgp64%> used with a 32-bit processor");
15388 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15389 error ("%<-mgp32%> used with a 64-bit ABI");
15390 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15391 error ("%<-mgp64%> used with a 32-bit ABI");
15395 /* Infer the integer register size from the ABI and processor.
15396 Restrict ourselves to 32-bit registers if that's all the
15397 processor has, or if the ABI cannot handle 64-bit registers. */
15398 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15399 target_flags &= ~MASK_64BIT;
15401 target_flags |= MASK_64BIT;
15404 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15406 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15407 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15408 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15409 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15410 else if (!TARGET_64BIT && TARGET_FLOAT64)
15412 if (!ISA_HAS_MXHC1)
15413 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15414 " the target supports the mfhc1 and mthc1 instructions");
15415 else if (mips_abi != ABI_32)
15416 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15422 /* -msingle-float selects 32-bit float registers. Otherwise the
15423 float registers should be the same size as the integer ones. */
15424 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15425 target_flags |= MASK_FLOAT64;
15427 target_flags &= ~MASK_FLOAT64;
15430 /* End of code shared with GAS. */
15432 /* If no -mlong* option was given, infer it from the other options. */
15433 if ((target_flags_explicit & MASK_LONG64) == 0)
15435 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15436 target_flags |= MASK_LONG64;
15438 target_flags &= ~MASK_LONG64;
15441 if (!TARGET_OLDABI)
15442 flag_pcc_struct_return = 0;
15444 /* Decide which rtx_costs structure to use. */
15446 mips_cost = &mips_rtx_cost_optimize_size;
15448 mips_cost = &mips_rtx_cost_data[mips_tune];
15450 /* If the user hasn't specified a branch cost, use the processor's
15452 if (mips_branch_cost == 0)
15453 mips_branch_cost = mips_cost->branch_cost;
15455 /* If neither -mbranch-likely nor -mno-branch-likely was given
15456 on the command line, set MASK_BRANCHLIKELY based on the target
15457 architecture and tuning flags. Annulled delay slots are a
15458 size win, so we only consider the processor-specific tuning
15459 for !optimize_size. */
15460 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15462 if (ISA_HAS_BRANCHLIKELY
15464 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15465 target_flags |= MASK_BRANCHLIKELY;
15467 target_flags &= ~MASK_BRANCHLIKELY;
15469 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15470 warning (0, "the %qs architecture does not support branch-likely"
15471 " instructions", mips_arch_info->name);
15473 /* The effect of -mabicalls isn't defined for the EABI. */
15474 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15476 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15477 target_flags &= ~MASK_ABICALLS;
15480 if (TARGET_ABICALLS_PIC2)
15481 /* We need to set flag_pic for executables as well as DSOs
15482 because we may reference symbols that are not defined in
15483 the final executable. (MIPS does not use things like
15484 copy relocs, for example.)
15486 There is a body of code that uses __PIC__ to distinguish
15487 between -mabicalls and -mno-abicalls code. The non-__PIC__
15488 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15489 long as any indirect jumps use $25. */
15492 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15493 faster code, but at the expense of more nops. Enable it at -O3 and
15495 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15496 target_flags |= MASK_VR4130_ALIGN;
15498 /* Prefer a call to memcpy over inline code when optimizing for size,
15499 though see MOVE_RATIO in mips.h. */
15500 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15501 target_flags |= MASK_MEMCPY;
15503 /* If we have a nonzero small-data limit, check that the -mgpopt
15504 setting is consistent with the other target flags. */
15505 if (mips_small_data_threshold > 0)
15509 if (!TARGET_EXPLICIT_RELOCS)
15510 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15512 TARGET_LOCAL_SDATA = false;
15513 TARGET_EXTERN_SDATA = false;
15517 if (TARGET_VXWORKS_RTP)
15518 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15520 if (TARGET_ABICALLS)
15521 warning (0, "cannot use small-data accesses for %qs",
15526 #ifdef MIPS_TFMODE_FORMAT
15527 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15530 /* Make sure that the user didn't turn off paired single support when
15531 MIPS-3D support is requested. */
15533 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15534 && !TARGET_PAIRED_SINGLE_FLOAT)
15535 error ("%<-mips3d%> requires %<-mpaired-single%>");
15537 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15539 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15541 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15542 and TARGET_HARD_FLOAT_ABI are both true. */
15543 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15544 error ("%qs must be used with %qs",
15545 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15546 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15548 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15550 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15551 warning (0, "the %qs architecture does not support paired-single"
15552 " instructions", mips_arch_info->name);
15554 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15555 && !TARGET_CACHE_BUILTIN)
15557 error ("%qs requires a target that provides the %qs instruction",
15558 "-mr10k-cache-barrier", "cache");
15559 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15562 /* If TARGET_DSPR2, enable MASK_DSP. */
15564 target_flags |= MASK_DSP;
15566 /* .eh_frame addresses should be the same width as a C pointer.
15567 Most MIPS ABIs support only one pointer size, so the assembler
15568 will usually know exactly how big an .eh_frame address is.
15570 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15571 originally defined to use 64-bit pointers (i.e. it is LP64), and
15572 this is still the default mode. However, we also support an n32-like
15573 ILP32 mode, which is selected by -mlong32. The problem is that the
15574 assembler has traditionally not had an -mlong option, so it has
15575 traditionally not known whether we're using the ILP32 or LP64 form.
15577 As it happens, gas versions up to and including 2.19 use _32-bit_
15578 addresses for EABI64 .cfi_* directives. This is wrong for the
15579 default LP64 mode, so we can't use the directives by default.
15580 Moreover, since gas's current behavior is at odds with gcc's
15581 default behavior, it seems unwise to rely on future versions
15582 of gas behaving the same way. We therefore avoid using .cfi
15583 directives for -mlong32 as well. */
15584 if (mips_abi == ABI_EABI && TARGET_64BIT)
15585 flag_dwarf2_cfi_asm = 0;
15587 /* .cfi_* directives generate a read-only section, so fall back on
15588 manual .eh_frame creation if we need the section to be writable. */
15589 if (TARGET_WRITABLE_EH_FRAME)
15590 flag_dwarf2_cfi_asm = 0;
15592 mips_init_print_operand_punct ();
15594 /* Set up array to map GCC register number to debug register number.
15595 Ignore the special purpose register numbers. */
15597 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15599 mips_dbx_regno[i] = INVALID_REGNUM;
15600 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15601 mips_dwarf_regno[i] = i;
15603 mips_dwarf_regno[i] = INVALID_REGNUM;
15606 start = GP_DBX_FIRST - GP_REG_FIRST;
15607 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15608 mips_dbx_regno[i] = i + start;
15610 start = FP_DBX_FIRST - FP_REG_FIRST;
15611 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15612 mips_dbx_regno[i] = i + start;
15614 /* Accumulator debug registers use big-endian ordering. */
15615 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15616 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15617 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15618 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15619 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15621 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15622 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15625 /* Set up mips_hard_regno_mode_ok. */
15626 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15627 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15628 mips_hard_regno_mode_ok[mode][regno]
15629 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15631 /* Function to allocate machine-dependent function status. */
15632 init_machine_status = &mips_init_machine_status;
15634 /* Default to working around R4000 errata only if the processor
15635 was selected explicitly. */
15636 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15637 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15638 target_flags |= MASK_FIX_R4000;
15640 /* Default to working around R4400 errata only if the processor
15641 was selected explicitly. */
15642 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15643 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15644 target_flags |= MASK_FIX_R4400;
15646 /* Default to working around R10000 errata only if the processor
15647 was selected explicitly. */
15648 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15649 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15650 target_flags |= MASK_FIX_R10000;
15652 /* Make sure that branch-likely instructions available when using
15653 -mfix-r10000. The instructions are not available if either:
15655 1. -mno-branch-likely was passed.
15656 2. The selected ISA does not support branch-likely and
15657 the command line does not include -mbranch-likely. */
15658 if (TARGET_FIX_R10000
15659 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15660 ? !ISA_HAS_BRANCHLIKELY
15661 : !TARGET_BRANCHLIKELY))
15662 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15664 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15666 warning (0, "the %qs architecture does not support the synci "
15667 "instruction", mips_arch_info->name);
15668 target_flags &= ~MASK_SYNCI;
15671 /* Only optimize PIC indirect calls if they are actually required. */
15672 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15673 target_flags &= ~MASK_RELAX_PIC_CALLS;
15675 /* Save base state of options. */
15676 mips_base_target_flags = target_flags;
15677 mips_base_schedule_insns = flag_schedule_insns;
15678 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15679 mips_base_move_loop_invariants = flag_move_loop_invariants;
15680 mips_base_align_loops = align_loops;
15681 mips_base_align_jumps = align_jumps;
15682 mips_base_align_functions = align_functions;
15684 /* Now select the ISA mode.
15686 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15687 MIPS16 mode afterwards if need be. */
15688 mips_set_mips16_mode (false);
15691 /* Swap the register information for registers I and I + 1, which
15692 currently have the wrong endianness. Note that the registers'
15693 fixedness and call-clobberedness might have been set on the
15697 mips_swap_registers (unsigned int i)
15702 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15703 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15705 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15706 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15707 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15708 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15714 /* Implement CONDITIONAL_REGISTER_USAGE. */
15717 mips_conditional_register_usage (void)
15722 /* These DSP control register fields are global. */
15723 global_regs[CCDSP_PO_REGNUM] = 1;
15724 global_regs[CCDSP_SC_REGNUM] = 1;
15730 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15731 fixed_regs[regno] = call_used_regs[regno] = 1;
15733 if (!TARGET_HARD_FLOAT)
15737 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15738 fixed_regs[regno] = call_used_regs[regno] = 1;
15739 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15740 fixed_regs[regno] = call_used_regs[regno] = 1;
15742 else if (! ISA_HAS_8CC)
15746 /* We only have a single condition-code register. We implement
15747 this by fixing all the condition-code registers and generating
15748 RTL that refers directly to ST_REG_FIRST. */
15749 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15750 fixed_regs[regno] = call_used_regs[regno] = 1;
15752 /* In MIPS16 mode, we permit the $t temporary registers to be used
15753 for reload. We prohibit the unused $s registers, since they
15754 are call-saved, and saving them via a MIPS16 register would
15755 probably waste more time than just reloading the value. */
15758 fixed_regs[18] = call_used_regs[18] = 1;
15759 fixed_regs[19] = call_used_regs[19] = 1;
15760 fixed_regs[20] = call_used_regs[20] = 1;
15761 fixed_regs[21] = call_used_regs[21] = 1;
15762 fixed_regs[22] = call_used_regs[22] = 1;
15763 fixed_regs[23] = call_used_regs[23] = 1;
15764 fixed_regs[26] = call_used_regs[26] = 1;
15765 fixed_regs[27] = call_used_regs[27] = 1;
15766 fixed_regs[30] = call_used_regs[30] = 1;
15768 /* $f20-$f23 are call-clobbered for n64. */
15769 if (mips_abi == ABI_64)
15772 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15773 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15775 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15777 if (mips_abi == ABI_N32)
15780 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15781 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15783 /* Make sure that double-register accumulator values are correctly
15784 ordered for the current endianness. */
15785 if (TARGET_LITTLE_ENDIAN)
15787 unsigned int regno;
15789 mips_swap_registers (MD_REG_FIRST);
15790 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15791 mips_swap_registers (regno);
15795 /* Initialize vector TARGET to VALS. */
15798 mips_expand_vector_init (rtx target, rtx vals)
15800 enum machine_mode mode;
15801 enum machine_mode inner;
15802 unsigned int i, n_elts;
15805 mode = GET_MODE (target);
15806 inner = GET_MODE_INNER (mode);
15807 n_elts = GET_MODE_NUNITS (mode);
15809 gcc_assert (VECTOR_MODE_P (mode));
15811 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15812 for (i = 0; i < n_elts; i++)
15813 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15814 XVECEXP (vals, 0, i));
15816 emit_move_insn (target, mem);
15819 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15820 other registers for instructions for which it is possible. This
15821 encourages the compiler to use CMP in cases where an XOR would
15822 require some register shuffling. */
15825 mips_order_regs_for_local_alloc (void)
15829 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15830 reg_alloc_order[i] = i;
15834 /* It really doesn't matter where we put register 0, since it is
15835 a fixed register anyhow. */
15836 reg_alloc_order[0] = 24;
15837 reg_alloc_order[24] = 0;
15841 /* Implement EH_USES. */
15844 mips_eh_uses (unsigned int regno)
15846 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
15848 /* We need to force certain registers to be live in order to handle
15849 PIC long branches correctly. See mips_must_initialize_gp_p for
15851 if (mips_cfun_has_cprestore_slot_p ())
15853 if (regno == CPRESTORE_SLOT_REGNUM)
15858 if (cfun->machine->global_pointer == regno)
15866 /* Implement EPILOGUE_USES. */
15869 mips_epilogue_uses (unsigned int regno)
15871 /* Say that the epilogue uses the return address register. Note that
15872 in the case of sibcalls, the values "used by the epilogue" are
15873 considered live at the start of the called function. */
15874 if (regno == RETURN_ADDR_REGNUM)
15877 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15878 See the comment above load_call<mode> for details. */
15879 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
15882 /* An interrupt handler must preserve some registers that are
15883 ordinarily call-clobbered. */
15884 if (cfun->machine->interrupt_handler_p
15885 && mips_interrupt_extra_call_saved_reg_p (regno))
15891 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15894 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
15896 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
15899 /* Return true if INSN needs to be wrapped in ".set noat".
15900 INSN has NOPERANDS operands, stored in OPVEC. */
15903 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
15907 if (recog_memoized (insn) >= 0)
15908 for (i = 0; i < noperands; i++)
15909 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
15914 /* Implement FINAL_PRESCAN_INSN. */
15917 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
15919 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15920 mips_push_asm_switch (&mips_noat);
15923 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
15926 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
15927 rtx *opvec, int noperands)
15929 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15930 mips_pop_asm_switch (&mips_noat);
15933 /* Return the size in bytes of the trampoline code, padded to
15934 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
15935 function address immediately follow. */
15938 mips_trampoline_code_size (void)
15940 if (TARGET_USE_PIC_FN_ADDR_REG)
15942 else if (ptr_mode == DImode)
15944 else if (ISA_HAS_LOAD_DELAY)
15950 /* Implement TARGET_TRAMPOLINE_INIT. */
15953 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
15955 rtx addr, end_addr, high, low, opcode, mem;
15958 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
15960 /* Work out the offsets of the pointers from the start of the
15961 trampoline code. */
15962 end_addr_offset = mips_trampoline_code_size ();
15963 static_chain_offset = end_addr_offset;
15964 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
15966 /* Get pointers to the beginning and end of the code block. */
15967 addr = force_reg (Pmode, XEXP (m_tramp, 0));
15968 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
15970 #define OP(X) gen_int_mode (X, SImode)
15972 /* Build up the code in TRAMPOLINE. */
15974 if (TARGET_USE_PIC_FN_ADDR_REG)
15976 /* $25 contains the address of the trampoline. Emit code of the form:
15978 l[wd] $1, target_function_offset($25)
15979 l[wd] $static_chain, static_chain_offset($25)
15982 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
15983 target_function_offset,
15984 PIC_FUNCTION_ADDR_REGNUM));
15985 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
15986 static_chain_offset,
15987 PIC_FUNCTION_ADDR_REGNUM));
15988 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
15989 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
15991 else if (ptr_mode == DImode)
15993 /* It's too cumbersome to create the full 64-bit address, so let's
15999 1: l[wd] $25, target_function_offset - 12($31)
16000 l[wd] $static_chain, static_chain_offset - 12($31)
16004 where 12 is the offset of "1:" from the start of the code block. */
16005 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16006 trampoline[i++] = OP (MIPS_BAL (1));
16007 trampoline[i++] = OP (MIPS_NOP);
16008 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16009 target_function_offset - 12,
16010 RETURN_ADDR_REGNUM));
16011 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16012 static_chain_offset - 12,
16013 RETURN_ADDR_REGNUM));
16014 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16015 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16019 /* If the target has load delays, emit:
16021 lui $1, %hi(end_addr)
16022 lw $25, %lo(end_addr + ...)($1)
16023 lw $static_chain, %lo(end_addr + ...)($1)
16029 lui $1, %hi(end_addr)
16030 lw $25, %lo(end_addr + ...)($1)
16032 lw $static_chain, %lo(end_addr + ...)($1). */
16034 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16035 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16036 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16037 NULL, false, OPTAB_WIDEN);
16038 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16039 NULL, false, OPTAB_WIDEN);
16040 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16042 /* Emit the LUI. */
16043 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16044 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16045 NULL, false, OPTAB_WIDEN);
16047 /* Emit the load of the target function. */
16048 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16049 target_function_offset - end_addr_offset,
16051 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16052 NULL, false, OPTAB_WIDEN);
16054 /* Emit the JR here, if we can. */
16055 if (!ISA_HAS_LOAD_DELAY)
16056 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16058 /* Emit the load of the static chain register. */
16059 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16060 static_chain_offset - end_addr_offset,
16062 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16063 NULL, false, OPTAB_WIDEN);
16065 /* Emit the JR, if we couldn't above. */
16066 if (ISA_HAS_LOAD_DELAY)
16068 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16069 trampoline[i++] = OP (MIPS_NOP);
16075 /* Copy the trampoline code. Leave any padding uninitialized. */
16076 for (j = 0; j < i; j++)
16078 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16079 mips_emit_move (mem, trampoline[j]);
16082 /* Set up the static chain pointer field. */
16083 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16084 mips_emit_move (mem, chain_value);
16086 /* Set up the target function field. */
16087 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16088 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16090 /* Flush the code part of the trampoline. */
16091 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16092 emit_insn (gen_clear_cache (addr, end_addr));
16095 /* Initialize the GCC target structure. */
16096 #undef TARGET_ASM_ALIGNED_HI_OP
16097 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16098 #undef TARGET_ASM_ALIGNED_SI_OP
16099 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16100 #undef TARGET_ASM_ALIGNED_DI_OP
16101 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16103 #undef TARGET_LEGITIMIZE_ADDRESS
16104 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16106 #undef TARGET_ASM_FUNCTION_PROLOGUE
16107 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16108 #undef TARGET_ASM_FUNCTION_EPILOGUE
16109 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16110 #undef TARGET_ASM_SELECT_RTX_SECTION
16111 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16112 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16113 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16115 #undef TARGET_SCHED_INIT
16116 #define TARGET_SCHED_INIT mips_sched_init
16117 #undef TARGET_SCHED_REORDER
16118 #define TARGET_SCHED_REORDER mips_sched_reorder
16119 #undef TARGET_SCHED_REORDER2
16120 #define TARGET_SCHED_REORDER2 mips_sched_reorder
16121 #undef TARGET_SCHED_VARIABLE_ISSUE
16122 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16123 #undef TARGET_SCHED_ADJUST_COST
16124 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16125 #undef TARGET_SCHED_ISSUE_RATE
16126 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16127 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16128 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16129 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16130 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16131 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16132 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16133 mips_multipass_dfa_lookahead
16135 #undef TARGET_DEFAULT_TARGET_FLAGS
16136 #define TARGET_DEFAULT_TARGET_FLAGS \
16138 | TARGET_CPU_DEFAULT \
16139 | TARGET_ENDIAN_DEFAULT \
16140 | TARGET_FP_EXCEPTIONS_DEFAULT \
16141 | MASK_CHECK_ZERO_DIV \
16143 #undef TARGET_HANDLE_OPTION
16144 #define TARGET_HANDLE_OPTION mips_handle_option
16146 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16147 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16149 #undef TARGET_INSERT_ATTRIBUTES
16150 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16151 #undef TARGET_MERGE_DECL_ATTRIBUTES
16152 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16153 #undef TARGET_SET_CURRENT_FUNCTION
16154 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16156 #undef TARGET_VALID_POINTER_MODE
16157 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16158 #undef TARGET_RTX_COSTS
16159 #define TARGET_RTX_COSTS mips_rtx_costs
16160 #undef TARGET_ADDRESS_COST
16161 #define TARGET_ADDRESS_COST mips_address_cost
16163 #undef TARGET_IN_SMALL_DATA_P
16164 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16166 #undef TARGET_MACHINE_DEPENDENT_REORG
16167 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16169 #undef TARGET_ASM_FILE_START
16170 #define TARGET_ASM_FILE_START mips_file_start
16171 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16172 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16174 #undef TARGET_INIT_LIBFUNCS
16175 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16177 #undef TARGET_BUILD_BUILTIN_VA_LIST
16178 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16179 #undef TARGET_EXPAND_BUILTIN_VA_START
16180 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16181 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16182 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16184 #undef TARGET_PROMOTE_FUNCTION_MODE
16185 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16186 #undef TARGET_PROMOTE_PROTOTYPES
16187 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16189 #undef TARGET_RETURN_IN_MEMORY
16190 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16191 #undef TARGET_RETURN_IN_MSB
16192 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16194 #undef TARGET_ASM_OUTPUT_MI_THUNK
16195 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16196 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16197 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16199 #undef TARGET_SETUP_INCOMING_VARARGS
16200 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16201 #undef TARGET_STRICT_ARGUMENT_NAMING
16202 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16203 #undef TARGET_MUST_PASS_IN_STACK
16204 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16205 #undef TARGET_PASS_BY_REFERENCE
16206 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16207 #undef TARGET_CALLEE_COPIES
16208 #define TARGET_CALLEE_COPIES mips_callee_copies
16209 #undef TARGET_ARG_PARTIAL_BYTES
16210 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16212 #undef TARGET_MODE_REP_EXTENDED
16213 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16215 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16216 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16218 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16219 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16221 #undef TARGET_INIT_BUILTINS
16222 #define TARGET_INIT_BUILTINS mips_init_builtins
16223 #undef TARGET_EXPAND_BUILTIN
16224 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16226 #undef TARGET_HAVE_TLS
16227 #define TARGET_HAVE_TLS HAVE_AS_TLS
16229 #undef TARGET_CANNOT_FORCE_CONST_MEM
16230 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16232 #undef TARGET_ENCODE_SECTION_INFO
16233 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16235 #undef TARGET_ATTRIBUTE_TABLE
16236 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16237 /* All our function attributes are related to how out-of-line copies should
16238 be compiled or called. They don't in themselves prevent inlining. */
16239 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16240 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16242 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16243 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16245 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16246 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16247 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16248 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16250 #undef TARGET_COMP_TYPE_ATTRIBUTES
16251 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16253 #ifdef HAVE_AS_DTPRELWORD
16254 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16255 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16257 #undef TARGET_DWARF_REGISTER_SPAN
16258 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16260 #undef TARGET_IRA_COVER_CLASSES
16261 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16263 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16264 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16266 #undef TARGET_LEGITIMATE_ADDRESS_P
16267 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16269 #undef TARGET_FRAME_POINTER_REQUIRED
16270 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16272 #undef TARGET_CAN_ELIMINATE
16273 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16275 #undef TARGET_TRAMPOLINE_INIT
16276 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16278 struct gcc_target targetm = TARGET_INITIALIZER;
16280 #include "gt-mips.h"