1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 #include "diagnostic.h"
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type {
150 /* Macros to create an enumeration identifier for a function prototype. */
151 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
152 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
153 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
154 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
156 /* Classifies the prototype of a builtin function. */
157 enum mips_function_type
159 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
160 #include "config/mips/mips-ftypes.def"
161 #undef DEF_MIPS_FTYPE
165 /* Specifies how a builtin function should be converted into rtl. */
166 enum mips_builtin_type
168 /* The builtin corresponds directly to an .md pattern. The return
169 value is mapped to operand 0 and the arguments are mapped to
170 operands 1 and above. */
173 /* The builtin corresponds directly to an .md pattern. There is no return
174 value and the arguments are mapped to operands 0 and above. */
175 MIPS_BUILTIN_DIRECT_NO_TARGET,
177 /* The builtin corresponds to a comparison instruction followed by
178 a mips_cond_move_tf_ps pattern. The first two arguments are the
179 values to compare and the second two arguments are the vector
180 operands for the movt.ps or movf.ps instruction (in assembly order). */
184 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
185 of this instruction is the result of the comparison, which has mode
186 CCV2 or CCV4. The function arguments are mapped to operands 1 and
187 above. The function's return value is an SImode boolean that is
188 true under the following conditions:
190 MIPS_BUILTIN_CMP_ANY: one of the registers is true
191 MIPS_BUILTIN_CMP_ALL: all of the registers are true
192 MIPS_BUILTIN_CMP_LOWER: the first register is true
193 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
194 MIPS_BUILTIN_CMP_ANY,
195 MIPS_BUILTIN_CMP_ALL,
196 MIPS_BUILTIN_CMP_UPPER,
197 MIPS_BUILTIN_CMP_LOWER,
199 /* As above, but the instruction only sets a single $fcc register. */
200 MIPS_BUILTIN_CMP_SINGLE,
202 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
203 MIPS_BUILTIN_BPOSGE32
206 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
207 #define MIPS_FP_CONDITIONS(MACRO) \
225 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
226 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
227 enum mips_fp_condition {
228 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
231 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
232 #define STRINGIFY(X) #X
233 static const char *const mips_fp_conditions[] = {
234 MIPS_FP_CONDITIONS (STRINGIFY)
237 /* Information about a function's frame layout. */
238 struct mips_frame_info GTY(())
240 /* The size of the frame in bytes. */
241 HOST_WIDE_INT total_size;
243 /* The number of bytes allocated to variables. */
244 HOST_WIDE_INT var_size;
246 /* The number of bytes allocated to outgoing function arguments. */
247 HOST_WIDE_INT args_size;
249 /* The number of bytes allocated to the .cprestore slot, or 0 if there
251 HOST_WIDE_INT cprestore_size;
253 /* Bit X is set if the function saves or restores GPR X. */
256 /* Likewise FPR X. */
259 /* The number of GPRs and FPRs saved. */
263 /* The offset of the topmost GPR and FPR save slots from the top of
264 the frame, or zero if no such slots are needed. */
265 HOST_WIDE_INT gp_save_offset;
266 HOST_WIDE_INT fp_save_offset;
268 /* Likewise, but giving offsets from the bottom of the frame. */
269 HOST_WIDE_INT gp_sp_offset;
270 HOST_WIDE_INT fp_sp_offset;
272 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
273 HOST_WIDE_INT arg_pointer_offset;
275 /* The offset of hard_frame_pointer_rtx from frame_pointer_rtx. */
276 HOST_WIDE_INT hard_frame_pointer_offset;
279 struct machine_function GTY(()) {
280 /* Pseudo-reg holding the value of $28 in a mips16 function which
281 refers to GP relative global variables. */
282 rtx mips16_gp_pseudo_rtx;
284 /* The number of extra stack bytes taken up by register varargs.
285 This area is allocated by the callee at the very top of the frame. */
288 /* Current frame information, calculated by mips_compute_frame_info. */
289 struct mips_frame_info frame;
291 /* The register to use as the global pointer within this function. */
292 unsigned int global_pointer;
294 /* True if mips_adjust_insn_length should ignore an instruction's
296 bool ignore_hazard_length_p;
298 /* True if the whole function is suitable for .set noreorder and
300 bool all_noreorder_p;
302 /* True if the function is known to have an instruction that needs $gp. */
305 /* True if we have emitted an instruction to initialize
306 mips16_gp_pseudo_rtx. */
307 bool initialized_mips16_gp_pseudo_p;
310 /* Information about a single argument. */
313 /* True if the argument is passed in a floating-point register, or
314 would have been if we hadn't run out of registers. */
317 /* The number of words passed in registers, rounded up. */
318 unsigned int reg_words;
320 /* For EABI, the offset of the first register from GP_ARG_FIRST or
321 FP_ARG_FIRST. For other ABIs, the offset of the first register from
322 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
323 comment for details).
325 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
327 unsigned int reg_offset;
329 /* The number of words that must be passed on the stack, rounded up. */
330 unsigned int stack_words;
332 /* The offset from the start of the stack overflow area of the argument's
333 first stack word. Only meaningful when STACK_WORDS is nonzero. */
334 unsigned int stack_offset;
338 /* Information about an address described by mips_address_type.
344 REG is the base register and OFFSET is the constant offset.
347 REG is the register that contains the high part of the address,
348 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
349 is the type of OFFSET's symbol.
352 SYMBOL_TYPE is the type of symbol being referenced. */
354 struct mips_address_info
356 enum mips_address_type type;
359 enum mips_symbol_type symbol_type;
363 /* One stage in a constant building sequence. These sequences have
367 A = A CODE[1] VALUE[1]
368 A = A CODE[2] VALUE[2]
371 where A is an accumulator, each CODE[i] is a binary rtl operation
372 and each VALUE[i] is a constant integer. */
373 struct mips_integer_op {
375 unsigned HOST_WIDE_INT value;
379 /* The largest number of operations needed to load an integer constant.
380 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
381 When the lowest bit is clear, we can try, but reject a sequence with
382 an extra SLL at the end. */
383 #define MIPS_MAX_INTEGER_OPS 7
385 /* Information about a MIPS16e SAVE or RESTORE instruction. */
386 struct mips16e_save_restore_info {
387 /* The number of argument registers saved by a SAVE instruction.
388 0 for RESTORE instructions. */
391 /* Bit X is set if the instruction saves or restores GPR X. */
394 /* The total number of bytes to allocate. */
398 /* Global variables for machine-dependent things. */
400 /* Threshold for data being put into the small data/bss area, instead
401 of the normal data area. */
402 int mips_section_threshold = -1;
404 /* Count the number of .file directives, so that .loc is up to date. */
405 int num_source_filenames = 0;
407 /* Name of the file containing the current function. */
408 const char *current_function_file = "";
410 /* Count the number of sdb related labels are generated (to find block
411 start and end boundaries). */
412 int sdb_label_count = 0;
414 /* Next label # for each statement for Silicon Graphics IRIS systems. */
417 /* Map GCC register number to debugger register number. */
418 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
419 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
421 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
426 /* The next branch instruction is a branch likely, not branch normal. */
427 int mips_branch_likely;
429 /* The operands passed to the last cmpMM expander. */
432 /* The target cpu for code generation. */
433 enum processor_type mips_arch;
434 const struct mips_cpu_info *mips_arch_info;
436 /* The target cpu for optimization and scheduling. */
437 enum processor_type mips_tune;
438 const struct mips_cpu_info *mips_tune_info;
440 /* Which instruction set architecture to use. */
443 /* The architecture selected by -mipsN. */
444 static const struct mips_cpu_info *mips_isa_info;
446 /* Which ABI to use. */
447 int mips_abi = MIPS_ABI_DEFAULT;
449 /* Cost information to use. */
450 const struct mips_rtx_cost_data *mips_cost;
452 /* Remember the ambient target flags, excluding mips16. */
453 static int mips_base_target_flags;
454 /* The mips16 command-line target flags only. */
455 static bool mips_base_mips16;
456 /* Similar copies of option settings. */
457 static int mips_flag_delayed_branch; /* flag_delayed_branch */
458 static int mips_base_schedule_insns; /* flag_schedule_insns */
459 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
460 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
461 static int mips_base_align_loops; /* align_loops */
462 static int mips_base_align_jumps; /* align_jumps */
463 static int mips_base_align_functions; /* align_functions */
465 /* The -mtext-loads setting. */
466 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
468 /* If TRUE, we split addresses into their high and low parts in the RTL. */
469 int mips_split_addresses;
471 /* Array giving truth value on whether or not a given hard register
472 can support a given mode. */
473 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
475 /* List of all MIPS punctuation characters used by print_operand. */
476 char mips_print_operand_punct[256];
478 static GTY (()) int mips_output_filename_first_time = 1;
480 /* mips_split_p[X] is true if symbols of type X can be split by
481 mips_split_symbol(). */
482 bool mips_split_p[NUM_SYMBOL_TYPES];
484 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
485 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
486 if they are matched by a special .md file pattern. */
487 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
489 /* Likewise for HIGHs. */
490 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
492 /* Map hard register number to register class */
493 const enum reg_class mips_regno_to_class[] =
495 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
496 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
497 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
498 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
499 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
500 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
501 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
502 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
503 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
504 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
505 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
506 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
507 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
508 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
509 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
510 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
511 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
512 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
513 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
514 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
515 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
516 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
517 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
518 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
519 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
520 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
521 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
522 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
523 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
524 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
525 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
526 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
527 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
528 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
529 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
530 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
531 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
532 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
533 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
534 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
535 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
536 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
537 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
538 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
539 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
540 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
541 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
544 /* Table of machine dependent attributes. */
545 const struct attribute_spec mips_attribute_table[] =
547 { "long_call", 0, 0, false, true, true, NULL },
548 { "far", 0, 0, false, true, true, NULL },
549 { "near", 0, 0, false, true, true, NULL },
550 /* Switch MIPS16 ASE on and off per-function. We would really like
551 to make these type attributes, but GCC doesn't provide the hooks
552 we need to support the right conversion rules. As declaration
553 attributes, they affect code generation but don't carry other
555 { "mips16", 0, 0, true, false, false, NULL },
556 { "nomips16", 0, 0, true, false, false, NULL },
557 { NULL, 0, 0, false, false, false, NULL }
560 /* A table describing all the processors gcc knows about. Names are
561 matched in the order listed. The first mention of an ISA level is
562 taken as the canonical name for that ISA.
564 To ease comparison, please keep this table in the same order
565 as gas's mips_cpu_info_table[]. Please also make sure that
566 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
567 options correctly. */
568 const struct mips_cpu_info mips_cpu_info_table[] = {
569 /* Entries for generic ISAs */
570 { "mips1", PROCESSOR_R3000, 1, 0 },
571 { "mips2", PROCESSOR_R6000, 2, 0 },
572 { "mips3", PROCESSOR_R4000, 3, 0 },
573 { "mips4", PROCESSOR_R8000, 4, 0 },
574 /* Prefer not to use branch-likely instructions for generic MIPS32rX
575 and MIPS64rX code. The instructions were officially deprecated
576 in revisions 2 and earlier, but revision 3 is likely to downgrade
577 that to a recommendation to avoid the instructions in code that
578 isn't tuned to a specific processor. */
579 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
580 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
581 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
584 { "r3000", PROCESSOR_R3000, 1, 0 },
585 { "r2000", PROCESSOR_R3000, 1, 0 }, /* = r3000 */
586 { "r3900", PROCESSOR_R3900, 1, 0 },
589 { "r6000", PROCESSOR_R6000, 2, 0 },
592 { "r4000", PROCESSOR_R4000, 3, 0 },
593 { "vr4100", PROCESSOR_R4100, 3, 0 },
594 { "vr4111", PROCESSOR_R4111, 3, 0 },
595 { "vr4120", PROCESSOR_R4120, 3, 0 },
596 { "vr4130", PROCESSOR_R4130, 3, 0 },
597 { "vr4300", PROCESSOR_R4300, 3, 0 },
598 { "r4400", PROCESSOR_R4000, 3, 0 }, /* = r4000 */
599 { "r4600", PROCESSOR_R4600, 3, 0 },
600 { "orion", PROCESSOR_R4600, 3, 0 }, /* = r4600 */
601 { "r4650", PROCESSOR_R4650, 3, 0 },
604 { "r8000", PROCESSOR_R8000, 4, 0 },
605 { "vr5000", PROCESSOR_R5000, 4, 0 },
606 { "vr5400", PROCESSOR_R5400, 4, 0 },
607 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
608 { "rm7000", PROCESSOR_R7000, 4, 0 },
609 { "rm9000", PROCESSOR_R9000, 4, 0 },
612 { "4kc", PROCESSOR_4KC, 32, 0 },
613 { "4km", PROCESSOR_4KC, 32, 0 }, /* = 4kc */
614 { "4kp", PROCESSOR_4KP, 32, 0 },
615 { "4ksc", PROCESSOR_4KC, 32, 0 },
617 /* MIPS32 Release 2 */
618 { "m4k", PROCESSOR_M4K, 33, 0 },
619 { "4kec", PROCESSOR_4KC, 33, 0 },
620 { "4kem", PROCESSOR_4KC, 33, 0 },
621 { "4kep", PROCESSOR_4KP, 33, 0 },
622 { "4ksd", PROCESSOR_4KC, 33, 0 },
624 { "24kc", PROCESSOR_24KC, 33, 0 },
625 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
626 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
627 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
628 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
629 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
631 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP */
632 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
633 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
634 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
635 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
636 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
638 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP */
639 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
640 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
641 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
642 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
643 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
645 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2 */
646 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
647 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
648 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
649 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
650 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
651 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
654 { "5kc", PROCESSOR_5KC, 64, 0 },
655 { "5kf", PROCESSOR_5KF, 64, 0 },
656 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
657 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
658 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
659 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
662 /* Default costs. If these are used for a processor we should look
663 up the actual costs. */
664 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
665 COSTS_N_INSNS (7), /* fp_mult_sf */ \
666 COSTS_N_INSNS (8), /* fp_mult_df */ \
667 COSTS_N_INSNS (23), /* fp_div_sf */ \
668 COSTS_N_INSNS (36), /* fp_div_df */ \
669 COSTS_N_INSNS (10), /* int_mult_si */ \
670 COSTS_N_INSNS (10), /* int_mult_di */ \
671 COSTS_N_INSNS (69), /* int_div_si */ \
672 COSTS_N_INSNS (69), /* int_div_di */ \
673 2, /* branch_cost */ \
674 4 /* memory_latency */
676 /* Need to replace these with the costs of calling the appropriate
678 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
679 COSTS_N_INSNS (256), /* fp_mult_sf */ \
680 COSTS_N_INSNS (256), /* fp_mult_df */ \
681 COSTS_N_INSNS (256), /* fp_div_sf */ \
682 COSTS_N_INSNS (256) /* fp_div_df */
684 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
686 COSTS_N_INSNS (1), /* fp_add */
687 COSTS_N_INSNS (1), /* fp_mult_sf */
688 COSTS_N_INSNS (1), /* fp_mult_df */
689 COSTS_N_INSNS (1), /* fp_div_sf */
690 COSTS_N_INSNS (1), /* fp_div_df */
691 COSTS_N_INSNS (1), /* int_mult_si */
692 COSTS_N_INSNS (1), /* int_mult_di */
693 COSTS_N_INSNS (1), /* int_div_si */
694 COSTS_N_INSNS (1), /* int_div_di */
696 4 /* memory_latency */
699 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
702 COSTS_N_INSNS (2), /* fp_add */
703 COSTS_N_INSNS (4), /* fp_mult_sf */
704 COSTS_N_INSNS (5), /* fp_mult_df */
705 COSTS_N_INSNS (12), /* fp_div_sf */
706 COSTS_N_INSNS (19), /* fp_div_df */
707 COSTS_N_INSNS (12), /* int_mult_si */
708 COSTS_N_INSNS (12), /* int_mult_di */
709 COSTS_N_INSNS (35), /* int_div_si */
710 COSTS_N_INSNS (35), /* int_div_di */
712 4 /* memory_latency */
717 COSTS_N_INSNS (6), /* int_mult_si */
718 COSTS_N_INSNS (6), /* int_mult_di */
719 COSTS_N_INSNS (36), /* int_div_si */
720 COSTS_N_INSNS (36), /* int_div_di */
722 4 /* memory_latency */
726 COSTS_N_INSNS (36), /* int_mult_si */
727 COSTS_N_INSNS (36), /* int_mult_di */
728 COSTS_N_INSNS (37), /* int_div_si */
729 COSTS_N_INSNS (37), /* int_div_di */
731 4 /* memory_latency */
735 COSTS_N_INSNS (4), /* int_mult_si */
736 COSTS_N_INSNS (11), /* int_mult_di */
737 COSTS_N_INSNS (36), /* int_div_si */
738 COSTS_N_INSNS (68), /* int_div_di */
740 4 /* memory_latency */
743 COSTS_N_INSNS (4), /* fp_add */
744 COSTS_N_INSNS (4), /* fp_mult_sf */
745 COSTS_N_INSNS (5), /* fp_mult_df */
746 COSTS_N_INSNS (17), /* fp_div_sf */
747 COSTS_N_INSNS (32), /* fp_div_df */
748 COSTS_N_INSNS (4), /* int_mult_si */
749 COSTS_N_INSNS (11), /* int_mult_di */
750 COSTS_N_INSNS (36), /* int_div_si */
751 COSTS_N_INSNS (68), /* int_div_di */
753 4 /* memory_latency */
756 COSTS_N_INSNS (4), /* fp_add */
757 COSTS_N_INSNS (4), /* fp_mult_sf */
758 COSTS_N_INSNS (5), /* fp_mult_df */
759 COSTS_N_INSNS (17), /* fp_div_sf */
760 COSTS_N_INSNS (32), /* fp_div_df */
761 COSTS_N_INSNS (4), /* int_mult_si */
762 COSTS_N_INSNS (7), /* int_mult_di */
763 COSTS_N_INSNS (42), /* int_div_si */
764 COSTS_N_INSNS (72), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (5), /* int_mult_si */
771 COSTS_N_INSNS (5), /* int_mult_di */
772 COSTS_N_INSNS (41), /* int_div_si */
773 COSTS_N_INSNS (41), /* int_div_di */
775 4 /* memory_latency */
778 COSTS_N_INSNS (8), /* fp_add */
779 COSTS_N_INSNS (8), /* fp_mult_sf */
780 COSTS_N_INSNS (10), /* fp_mult_df */
781 COSTS_N_INSNS (34), /* fp_div_sf */
782 COSTS_N_INSNS (64), /* fp_div_df */
783 COSTS_N_INSNS (5), /* int_mult_si */
784 COSTS_N_INSNS (5), /* int_mult_di */
785 COSTS_N_INSNS (41), /* int_div_si */
786 COSTS_N_INSNS (41), /* int_div_di */
788 4 /* memory_latency */
791 COSTS_N_INSNS (4), /* fp_add */
792 COSTS_N_INSNS (4), /* fp_mult_sf */
793 COSTS_N_INSNS (5), /* fp_mult_df */
794 COSTS_N_INSNS (17), /* fp_div_sf */
795 COSTS_N_INSNS (32), /* fp_div_df */
796 COSTS_N_INSNS (5), /* int_mult_si */
797 COSTS_N_INSNS (5), /* int_mult_di */
798 COSTS_N_INSNS (41), /* int_div_si */
799 COSTS_N_INSNS (41), /* int_div_di */
801 4 /* memory_latency */
805 COSTS_N_INSNS (5), /* int_mult_si */
806 COSTS_N_INSNS (5), /* int_mult_di */
807 COSTS_N_INSNS (41), /* int_div_si */
808 COSTS_N_INSNS (41), /* int_div_di */
810 4 /* memory_latency */
813 COSTS_N_INSNS (8), /* fp_add */
814 COSTS_N_INSNS (8), /* fp_mult_sf */
815 COSTS_N_INSNS (10), /* fp_mult_df */
816 COSTS_N_INSNS (34), /* fp_div_sf */
817 COSTS_N_INSNS (64), /* fp_div_df */
818 COSTS_N_INSNS (5), /* int_mult_si */
819 COSTS_N_INSNS (5), /* int_mult_di */
820 COSTS_N_INSNS (41), /* int_div_si */
821 COSTS_N_INSNS (41), /* int_div_di */
823 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (17), /* fp_div_sf */
830 COSTS_N_INSNS (32), /* fp_div_df */
831 COSTS_N_INSNS (5), /* int_mult_si */
832 COSTS_N_INSNS (5), /* int_mult_di */
833 COSTS_N_INSNS (41), /* int_div_si */
834 COSTS_N_INSNS (41), /* int_div_di */
836 4 /* memory_latency */
839 COSTS_N_INSNS (6), /* fp_add */
840 COSTS_N_INSNS (6), /* fp_mult_sf */
841 COSTS_N_INSNS (7), /* fp_mult_df */
842 COSTS_N_INSNS (25), /* fp_div_sf */
843 COSTS_N_INSNS (48), /* fp_div_df */
844 COSTS_N_INSNS (5), /* int_mult_si */
845 COSTS_N_INSNS (5), /* int_mult_di */
846 COSTS_N_INSNS (41), /* int_div_si */
847 COSTS_N_INSNS (41), /* int_div_di */
849 4 /* memory_latency */
855 COSTS_N_INSNS (2), /* fp_add */
856 COSTS_N_INSNS (4), /* fp_mult_sf */
857 COSTS_N_INSNS (5), /* fp_mult_df */
858 COSTS_N_INSNS (12), /* fp_div_sf */
859 COSTS_N_INSNS (19), /* fp_div_df */
860 COSTS_N_INSNS (2), /* int_mult_si */
861 COSTS_N_INSNS (2), /* int_mult_di */
862 COSTS_N_INSNS (35), /* int_div_si */
863 COSTS_N_INSNS (35), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (3), /* fp_add */
869 COSTS_N_INSNS (5), /* fp_mult_sf */
870 COSTS_N_INSNS (6), /* fp_mult_df */
871 COSTS_N_INSNS (15), /* fp_div_sf */
872 COSTS_N_INSNS (16), /* fp_div_df */
873 COSTS_N_INSNS (17), /* int_mult_si */
874 COSTS_N_INSNS (17), /* int_mult_di */
875 COSTS_N_INSNS (38), /* int_div_si */
876 COSTS_N_INSNS (38), /* int_div_di */
878 6 /* memory_latency */
881 COSTS_N_INSNS (6), /* fp_add */
882 COSTS_N_INSNS (7), /* fp_mult_sf */
883 COSTS_N_INSNS (8), /* fp_mult_df */
884 COSTS_N_INSNS (23), /* fp_div_sf */
885 COSTS_N_INSNS (36), /* fp_div_df */
886 COSTS_N_INSNS (10), /* int_mult_si */
887 COSTS_N_INSNS (10), /* int_mult_di */
888 COSTS_N_INSNS (69), /* int_div_si */
889 COSTS_N_INSNS (69), /* int_div_di */
891 6 /* memory_latency */
903 /* The only costs that appear to be updated here are
904 integer multiplication. */
906 COSTS_N_INSNS (4), /* int_mult_si */
907 COSTS_N_INSNS (6), /* int_mult_di */
908 COSTS_N_INSNS (69), /* int_div_si */
909 COSTS_N_INSNS (69), /* int_div_di */
911 4 /* memory_latency */
923 COSTS_N_INSNS (6), /* fp_add */
924 COSTS_N_INSNS (4), /* fp_mult_sf */
925 COSTS_N_INSNS (5), /* fp_mult_df */
926 COSTS_N_INSNS (23), /* fp_div_sf */
927 COSTS_N_INSNS (36), /* fp_div_df */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (36), /* int_div_si */
931 COSTS_N_INSNS (36), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (6), /* fp_add */
937 COSTS_N_INSNS (5), /* fp_mult_sf */
938 COSTS_N_INSNS (6), /* fp_mult_df */
939 COSTS_N_INSNS (30), /* fp_div_sf */
940 COSTS_N_INSNS (59), /* fp_div_df */
941 COSTS_N_INSNS (3), /* int_mult_si */
942 COSTS_N_INSNS (4), /* int_mult_di */
943 COSTS_N_INSNS (42), /* int_div_si */
944 COSTS_N_INSNS (74), /* int_div_di */
946 4 /* memory_latency */
949 COSTS_N_INSNS (6), /* fp_add */
950 COSTS_N_INSNS (5), /* fp_mult_sf */
951 COSTS_N_INSNS (6), /* fp_mult_df */
952 COSTS_N_INSNS (30), /* fp_div_sf */
953 COSTS_N_INSNS (59), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (9), /* int_mult_di */
956 COSTS_N_INSNS (42), /* int_div_si */
957 COSTS_N_INSNS (74), /* int_div_di */
959 4 /* memory_latency */
962 /* The only costs that are changed here are
963 integer multiplication. */
964 COSTS_N_INSNS (6), /* fp_add */
965 COSTS_N_INSNS (7), /* fp_mult_sf */
966 COSTS_N_INSNS (8), /* fp_mult_df */
967 COSTS_N_INSNS (23), /* fp_div_sf */
968 COSTS_N_INSNS (36), /* fp_div_df */
969 COSTS_N_INSNS (5), /* int_mult_si */
970 COSTS_N_INSNS (9), /* int_mult_di */
971 COSTS_N_INSNS (69), /* int_div_si */
972 COSTS_N_INSNS (69), /* int_div_di */
974 4 /* memory_latency */
980 /* The only costs that are changed here are
981 integer multiplication. */
982 COSTS_N_INSNS (6), /* fp_add */
983 COSTS_N_INSNS (7), /* fp_mult_sf */
984 COSTS_N_INSNS (8), /* fp_mult_df */
985 COSTS_N_INSNS (23), /* fp_div_sf */
986 COSTS_N_INSNS (36), /* fp_div_df */
987 COSTS_N_INSNS (3), /* int_mult_si */
988 COSTS_N_INSNS (8), /* int_mult_di */
989 COSTS_N_INSNS (69), /* int_div_si */
990 COSTS_N_INSNS (69), /* int_div_di */
992 4 /* memory_latency */
995 /* These costs are the same as the SB-1A below. */
996 COSTS_N_INSNS (4), /* fp_add */
997 COSTS_N_INSNS (4), /* fp_mult_sf */
998 COSTS_N_INSNS (4), /* fp_mult_df */
999 COSTS_N_INSNS (24), /* fp_div_sf */
1000 COSTS_N_INSNS (32), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (4), /* int_mult_di */
1003 COSTS_N_INSNS (36), /* int_div_si */
1004 COSTS_N_INSNS (68), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 /* These costs are the same as the SB-1 above. */
1010 COSTS_N_INSNS (4), /* fp_add */
1011 COSTS_N_INSNS (4), /* fp_mult_sf */
1012 COSTS_N_INSNS (4), /* fp_mult_df */
1013 COSTS_N_INSNS (24), /* fp_div_sf */
1014 COSTS_N_INSNS (32), /* fp_div_df */
1015 COSTS_N_INSNS (3), /* int_mult_si */
1016 COSTS_N_INSNS (4), /* int_mult_di */
1017 COSTS_N_INSNS (36), /* int_div_si */
1018 COSTS_N_INSNS (68), /* int_div_di */
1019 1, /* branch_cost */
1020 4 /* memory_latency */
1027 /* Use a hash table to keep track of implicit mips16/nomips16 attributes
1028 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1030 struct mflip_mips16_entry GTY (()) {
1034 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1036 /* Hash table callbacks for mflip_mips16_htab. */
1039 mflip_mips16_htab_hash (const void *entry)
1041 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1045 mflip_mips16_htab_eq (const void *entry, const void *name)
1047 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1048 (const char *) name) == 0;
1051 static GTY(()) int mips16_flipper;
1053 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1054 for -mflip-mips16. Return true if it should use "mips16" and false if
1055 it should use "nomips16". */
1058 mflip_mips16_use_mips16_p (tree decl)
1060 struct mflip_mips16_entry *entry;
1065 /* Use the opposite of the command-line setting for anonymous decls. */
1066 if (!DECL_NAME (decl))
1067 return !mips_base_mips16;
1069 if (!mflip_mips16_htab)
1070 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1071 mflip_mips16_htab_eq, NULL);
1073 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1074 hash = htab_hash_string (name);
1075 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1076 entry = (struct mflip_mips16_entry *) *slot;
1079 mips16_flipper = !mips16_flipper;
1080 entry = GGC_NEW (struct mflip_mips16_entry);
1082 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1085 return entry->mips16_p;
1088 /* Predicates to test for presence of "near" and "far"/"long_call"
1089 attributes on the given TYPE. */
1092 mips_near_type_p (const_tree type)
1094 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1098 mips_far_type_p (const_tree type)
1100 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1101 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1104 /* Similar predicates for "mips16"/"nomips16" attributes. */
1107 mips_mips16_decl_p (const_tree decl)
1109 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1113 mips_nomips16_decl_p (const_tree decl)
1115 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1118 /* Return true if function DECL is a MIPS16 function. Return the ambient
1119 setting if DECL is null. */
1122 mips_use_mips16_mode_p (tree decl)
1126 /* Nested functions must use the same frame pointer as their
1127 parent and must therefore use the same ISA mode. */
1128 tree parent = decl_function_context (decl);
1131 if (mips_mips16_decl_p (decl))
1133 if (mips_nomips16_decl_p (decl))
1136 return mips_base_mips16;
1139 /* Return 0 if the attributes for two types are incompatible, 1 if they
1140 are compatible, and 2 if they are nearly compatible (which causes a
1141 warning to be generated). */
1144 mips_comp_type_attributes (const_tree type1, const_tree type2)
1146 /* Check for mismatch of non-default calling convention. */
1147 if (TREE_CODE (type1) != FUNCTION_TYPE)
1150 /* Disallow mixed near/far attributes. */
1151 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1153 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1159 /* Implement TARGET_INSERT_ATTRIBUTES. */
1162 mips_insert_attributes (tree decl, tree *attributes)
1165 bool mips16_p, nomips16_p;
1167 /* Check for "mips16" and "nomips16" attributes. */
1168 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1169 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1170 if (TREE_CODE (decl) != FUNCTION_DECL)
1173 error ("%qs attribute only applies to functions", "mips16");
1175 error ("%qs attribute only applies to functions", "nomips16");
1179 mips16_p |= mips_mips16_decl_p (decl);
1180 nomips16_p |= mips_nomips16_decl_p (decl);
1181 if (mips16_p || nomips16_p)
1183 /* DECL cannot be simultaneously mips16 and nomips16. */
1184 if (mips16_p && nomips16_p)
1185 error ("%qs cannot have both %<mips16%> and "
1186 "%<nomips16%> attributes",
1187 IDENTIFIER_POINTER (DECL_NAME (decl)));
1189 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1191 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1192 "mips16" attribute, arbitrarily pick one. We must pick the same
1193 setting for duplicate declarations of a function. */
1194 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1195 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1200 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1203 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1205 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1206 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1207 error ("%qs redeclared with conflicting %qs attributes",
1208 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "mips16");
1209 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1210 error ("%qs redeclared with conflicting %qs attributes",
1211 IDENTIFIER_POINTER (DECL_NAME (newdecl)), "nomips16");
1213 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1214 DECL_ATTRIBUTES (newdecl));
1217 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1218 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1221 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1223 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1225 *base_ptr = XEXP (x, 0);
1226 *offset_ptr = INTVAL (XEXP (x, 1));
1235 static unsigned int mips_build_integer (struct mips_integer_op *,
1236 unsigned HOST_WIDE_INT);
1238 /* Subroutine of mips_build_integer (with the same interface).
1239 Assume that the final action in the sequence should be a left shift. */
1242 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1244 unsigned int i, shift;
1246 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1247 since signed numbers are easier to load than unsigned ones. */
1249 while ((value & 1) == 0)
1250 value /= 2, shift++;
1252 i = mips_build_integer (codes, value);
1253 codes[i].code = ASHIFT;
1254 codes[i].value = shift;
1259 /* As for mips_build_shift, but assume that the final action will be
1260 an IOR or PLUS operation. */
1263 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1265 unsigned HOST_WIDE_INT high;
1268 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1269 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1271 /* The constant is too complex to load with a simple lui/ori pair
1272 so our goal is to clear as many trailing zeros as possible.
1273 In this case, we know bit 16 is set and that the low 16 bits
1274 form a negative number. If we subtract that number from VALUE,
1275 we will clear at least the lowest 17 bits, maybe more. */
1276 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1277 codes[i].code = PLUS;
1278 codes[i].value = CONST_LOW_PART (value);
1282 i = mips_build_integer (codes, high);
1283 codes[i].code = IOR;
1284 codes[i].value = value & 0xffff;
1290 /* Fill CODES with a sequence of rtl operations to load VALUE.
1291 Return the number of operations needed. */
1294 mips_build_integer (struct mips_integer_op *codes,
1295 unsigned HOST_WIDE_INT value)
1297 if (SMALL_OPERAND (value)
1298 || SMALL_OPERAND_UNSIGNED (value)
1299 || LUI_OPERAND (value))
1301 /* The value can be loaded with a single instruction. */
1302 codes[0].code = UNKNOWN;
1303 codes[0].value = value;
1306 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1308 /* Either the constant is a simple LUI/ORI combination or its
1309 lowest bit is set. We don't want to shift in this case. */
1310 return mips_build_lower (codes, value);
1312 else if ((value & 0xffff) == 0)
1314 /* The constant will need at least three actions. The lowest
1315 16 bits are clear, so the final action will be a shift. */
1316 return mips_build_shift (codes, value);
1320 /* The final action could be a shift, add or inclusive OR.
1321 Rather than use a complex condition to select the best
1322 approach, try both mips_build_shift and mips_build_lower
1323 and pick the one that gives the shortest sequence.
1324 Note that this case is only used once per constant. */
1325 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1326 unsigned int cost, alt_cost;
1328 cost = mips_build_shift (codes, value);
1329 alt_cost = mips_build_lower (alt_codes, value);
1330 if (alt_cost < cost)
1332 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1339 /* Return true if X is a thread-local symbol. */
1342 mips_tls_operand_p (rtx x)
1344 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1347 /* Return true if SYMBOL_REF X is associated with a global symbol
1348 (in the STB_GLOBAL sense). */
1351 mips_global_symbol_p (const_rtx x)
1353 const_tree const decl = SYMBOL_REF_DECL (x);
1356 return !SYMBOL_REF_LOCAL_P (x);
1358 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1359 or weak symbols. Relocations in the object file will be against
1360 the target symbol, so it's that symbol's binding that matters here. */
1361 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1364 /* Return true if SYMBOL_REF X binds locally. */
1367 mips_symbol_binds_local_p (const_rtx x)
1369 return (SYMBOL_REF_DECL (x)
1370 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1371 : SYMBOL_REF_LOCAL_P (x));
1374 /* Return true if rtx constants of mode MODE should be put into a small
1378 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1380 return (!TARGET_EMBEDDED_DATA
1381 && TARGET_LOCAL_SDATA
1382 && GET_MODE_SIZE (mode) <= mips_section_threshold);
1385 /* Return true if X should not be moved directly into register $25.
1386 We need this because many versions of GAS will treat "la $25,foo" as
1387 part of a call sequence and so allow a global "foo" to be lazily bound. */
1390 mips_dangerous_for_la25_p (rtx x)
1392 return (!TARGET_EXPLICIT_RELOCS
1394 && GET_CODE (x) == SYMBOL_REF
1395 && mips_global_symbol_p (x));
1398 /* Return the method that should be used to access SYMBOL_REF or
1399 LABEL_REF X in context CONTEXT. */
1401 static enum mips_symbol_type
1402 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1405 return SYMBOL_GOT_DISP;
1407 if (GET_CODE (x) == LABEL_REF)
1409 /* LABEL_REFs are used for jump tables as well as text labels.
1410 Only return SYMBOL_PC_RELATIVE if we know the label is in
1411 the text section. */
1412 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1413 return SYMBOL_PC_RELATIVE;
1414 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1415 return SYMBOL_GOT_PAGE_OFST;
1416 return SYMBOL_ABSOLUTE;
1419 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1421 if (SYMBOL_REF_TLS_MODEL (x))
1424 if (CONSTANT_POOL_ADDRESS_P (x))
1426 if (TARGET_MIPS16_TEXT_LOADS)
1427 return SYMBOL_PC_RELATIVE;
1429 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1430 return SYMBOL_PC_RELATIVE;
1432 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1433 return SYMBOL_GP_RELATIVE;
1436 /* Do not use small-data accesses for weak symbols; they may end up
1439 && SYMBOL_REF_SMALL_P (x)
1440 && !SYMBOL_REF_WEAK (x))
1441 return SYMBOL_GP_RELATIVE;
1443 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1446 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1448 /* There are three cases to consider:
1450 - o32 PIC (either with or without explicit relocs)
1451 - n32/n64 PIC without explicit relocs
1452 - n32/n64 PIC with explicit relocs
1454 In the first case, both local and global accesses will use an
1455 R_MIPS_GOT16 relocation. We must correctly predict which of
1456 the two semantics (local or global) the assembler and linker
1457 will apply. The choice depends on the symbol's binding rather
1458 than its visibility.
1460 In the second case, the assembler will not use R_MIPS_GOT16
1461 relocations, but it chooses between local and global accesses
1462 in the same way as for o32 PIC.
1464 In the third case we have more freedom since both forms of
1465 access will work for any kind of symbol. However, there seems
1466 little point in doing things differently. */
1467 if (mips_global_symbol_p (x))
1468 return SYMBOL_GOT_DISP;
1470 return SYMBOL_GOT_PAGE_OFST;
1473 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1474 return SYMBOL_FORCE_TO_MEM;
1475 return SYMBOL_ABSOLUTE;
1478 /* Classify symbolic expression X, given that it appears in context
1481 static enum mips_symbol_type
1482 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1486 split_const (x, &x, &offset);
1487 if (UNSPEC_ADDRESS_P (x))
1488 return UNSPEC_ADDRESS_TYPE (x);
1490 return mips_classify_symbol (x, context);
1493 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1494 is the alignment (in bytes) of SYMBOL_REF X. */
1497 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1499 /* If for some reason we can't get the alignment for the
1500 symbol, initializing this to one means we will only accept
1502 HOST_WIDE_INT align = 1;
1505 /* Get the alignment of the symbol we're referring to. */
1506 t = SYMBOL_REF_DECL (x);
1508 align = DECL_ALIGN_UNIT (t);
1510 return offset >= 0 && offset < align;
1513 /* Return true if X is a symbolic constant that can be used in context
1514 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1517 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1518 enum mips_symbol_type *symbol_type)
1522 split_const (x, &x, &offset);
1523 if (UNSPEC_ADDRESS_P (x))
1525 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1526 x = UNSPEC_ADDRESS (x);
1528 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1530 *symbol_type = mips_classify_symbol (x, context);
1531 if (*symbol_type == SYMBOL_TLS)
1537 if (offset == const0_rtx)
1540 /* Check whether a nonzero offset is valid for the underlying
1542 switch (*symbol_type)
1544 case SYMBOL_ABSOLUTE:
1545 case SYMBOL_FORCE_TO_MEM:
1546 case SYMBOL_32_HIGH:
1547 case SYMBOL_64_HIGH:
1550 /* If the target has 64-bit pointers and the object file only
1551 supports 32-bit symbols, the values of those symbols will be
1552 sign-extended. In this case we can't allow an arbitrary offset
1553 in case the 32-bit value X + OFFSET has a different sign from X. */
1554 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1555 return offset_within_block_p (x, INTVAL (offset));
1557 /* In other cases the relocations can handle any offset. */
1560 case SYMBOL_PC_RELATIVE:
1561 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1562 In this case, we no longer have access to the underlying constant,
1563 but the original symbol-based access was known to be valid. */
1564 if (GET_CODE (x) == LABEL_REF)
1569 case SYMBOL_GP_RELATIVE:
1570 /* Make sure that the offset refers to something within the
1571 same object block. This should guarantee that the final
1572 PC- or GP-relative offset is within the 16-bit limit. */
1573 return offset_within_block_p (x, INTVAL (offset));
1575 case SYMBOL_GOT_PAGE_OFST:
1576 case SYMBOL_GOTOFF_PAGE:
1577 /* If the symbol is global, the GOT entry will contain the symbol's
1578 address, and we will apply a 16-bit offset after loading it.
1579 If the symbol is local, the linker should provide enough local
1580 GOT entries for a 16-bit offset, but larger offsets may lead
1582 return SMALL_INT (offset);
1586 /* There is no carry between the HI and LO REL relocations, so the
1587 offset is only valid if we know it won't lead to such a carry. */
1588 return mips_offset_within_alignment_p (x, INTVAL (offset));
1590 case SYMBOL_GOT_DISP:
1591 case SYMBOL_GOTOFF_DISP:
1592 case SYMBOL_GOTOFF_CALL:
1593 case SYMBOL_GOTOFF_LOADGP:
1596 case SYMBOL_GOTTPREL:
1604 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1605 single instruction. We rely on the fact that, in the worst case,
1606 all instructions involved in a MIPS16 address calculation are usually
1610 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1614 case SYMBOL_ABSOLUTE:
1615 /* When using 64-bit symbols, we need 5 preparatory instructions,
1618 lui $at,%highest(symbol)
1619 daddiu $at,$at,%higher(symbol)
1621 daddiu $at,$at,%hi(symbol)
1624 The final address is then $at + %lo(symbol). With 32-bit
1625 symbols we just need a preparatory lui for normal mode and
1626 a preparatory "li; sll" for MIPS16. */
1627 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1629 case SYMBOL_GP_RELATIVE:
1630 /* Treat GP-relative accesses as taking a single instruction on
1631 MIPS16 too; the copy of $gp can often be shared. */
1634 case SYMBOL_PC_RELATIVE:
1635 /* PC-relative constants can be only be used with addiupc,
1637 if (mode == MAX_MACHINE_MODE
1638 || GET_MODE_SIZE (mode) == 4
1639 || GET_MODE_SIZE (mode) == 8)
1642 /* The constant must be loaded using addiupc first. */
1645 case SYMBOL_FORCE_TO_MEM:
1646 /* LEAs will be converted into constant-pool references by
1648 if (mode == MAX_MACHINE_MODE)
1651 /* The constant must be loaded from the constant pool. */
1654 case SYMBOL_GOT_DISP:
1655 /* The constant will have to be loaded from the GOT before it
1656 is used in an address. */
1657 if (mode != MAX_MACHINE_MODE)
1662 case SYMBOL_GOT_PAGE_OFST:
1663 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1664 the local/global classification is accurate. See override_options
1667 The worst cases are:
1669 (1) For local symbols when generating o32 or o64 code. The assembler
1675 ...and the final address will be $at + %lo(symbol).
1677 (2) For global symbols when -mxgot. The assembler will use:
1679 lui $at,%got_hi(symbol)
1682 ...and the final address will be $at + %got_lo(symbol). */
1685 case SYMBOL_GOTOFF_PAGE:
1686 case SYMBOL_GOTOFF_DISP:
1687 case SYMBOL_GOTOFF_CALL:
1688 case SYMBOL_GOTOFF_LOADGP:
1689 case SYMBOL_32_HIGH:
1690 case SYMBOL_64_HIGH:
1696 case SYMBOL_GOTTPREL:
1699 /* A 16-bit constant formed by a single relocation, or a 32-bit
1700 constant formed from a high 16-bit relocation and a low 16-bit
1701 relocation. Use mips_split_p to determine which. */
1702 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1705 /* We don't treat a bare TLS symbol as a constant. */
1711 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1712 to load symbols of type TYPE into a register. Return 0 if the given
1713 type of symbol cannot be used as an immediate operand.
1715 Otherwise, return the number of instructions needed to load or store
1716 values of mode MODE to or from addresses of type TYPE. Return 0 if
1717 the given type of symbol is not valid in addresses.
1719 In both cases, treat extended MIPS16 instructions as two instructions. */
1722 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1724 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1727 /* Return true if X can not be forced into a constant pool. */
1730 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1732 return mips_tls_operand_p (*x);
1735 /* Return true if X can not be forced into a constant pool. */
1738 mips_cannot_force_const_mem (rtx x)
1744 /* As an optimization, reject constants that mips_legitimize_move
1747 Suppose we have a multi-instruction sequence that loads constant C
1748 into register R. If R does not get allocated a hard register, and
1749 R is used in an operand that allows both registers and memory
1750 references, reload will consider forcing C into memory and using
1751 one of the instruction's memory alternatives. Returning false
1752 here will force it to use an input reload instead. */
1753 if (GET_CODE (x) == CONST_INT)
1756 split_const (x, &base, &offset);
1757 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1761 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1767 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1768 constants when we're using a per-function constant pool. */
1771 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1772 const_rtx x ATTRIBUTE_UNUSED)
1774 return !TARGET_MIPS16_PCREL_LOADS;
1777 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1780 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1782 if (!HARD_REGISTER_NUM_P (regno))
1786 regno = reg_renumber[regno];
1789 /* These fake registers will be eliminated to either the stack or
1790 hard frame pointer, both of which are usually valid base registers.
1791 Reload deals with the cases where the eliminated form isn't valid. */
1792 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1795 /* In mips16 mode, the stack pointer can only address word and doubleword
1796 values, nothing smaller. There are two problems here:
1798 (a) Instantiating virtual registers can introduce new uses of the
1799 stack pointer. If these virtual registers are valid addresses,
1800 the stack pointer should be too.
1802 (b) Most uses of the stack pointer are not made explicit until
1803 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1804 We don't know until that stage whether we'll be eliminating to the
1805 stack pointer (which needs the restriction) or the hard frame
1806 pointer (which doesn't).
1808 All in all, it seems more consistent to only enforce this restriction
1809 during and after reload. */
1810 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1811 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1813 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1817 /* Return true if X is a valid base register for the given mode.
1818 Allow only hard registers if STRICT. */
1821 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1823 if (!strict && GET_CODE (x) == SUBREG)
1827 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1831 /* Return true if X is a valid address for machine mode MODE. If it is,
1832 fill in INFO appropriately. STRICT is true if we should only accept
1833 hard base registers. */
1836 mips_classify_address (struct mips_address_info *info, rtx x,
1837 enum machine_mode mode, int strict)
1839 switch (GET_CODE (x))
1843 info->type = ADDRESS_REG;
1845 info->offset = const0_rtx;
1846 return mips_valid_base_register_p (info->reg, mode, strict);
1849 info->type = ADDRESS_REG;
1850 info->reg = XEXP (x, 0);
1851 info->offset = XEXP (x, 1);
1852 return (mips_valid_base_register_p (info->reg, mode, strict)
1853 && const_arith_operand (info->offset, VOIDmode));
1856 info->type = ADDRESS_LO_SUM;
1857 info->reg = XEXP (x, 0);
1858 info->offset = XEXP (x, 1);
1859 /* We have to trust the creator of the LO_SUM to do something vaguely
1860 sane. Target-independent code that creates a LO_SUM should also
1861 create and verify the matching HIGH. Target-independent code that
1862 adds an offset to a LO_SUM must prove that the offset will not
1863 induce a carry. Failure to do either of these things would be
1864 a bug, and we are not required to check for it here. The MIPS
1865 backend itself should only create LO_SUMs for valid symbolic
1866 constants, with the high part being either a HIGH or a copy
1869 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
1870 return (mips_valid_base_register_p (info->reg, mode, strict)
1871 && mips_symbol_insns (info->symbol_type, mode) > 0
1872 && mips_lo_relocs[info->symbol_type] != 0);
1875 /* Small-integer addresses don't occur very often, but they
1876 are legitimate if $0 is a valid base register. */
1877 info->type = ADDRESS_CONST_INT;
1878 return !TARGET_MIPS16 && SMALL_INT (x);
1883 info->type = ADDRESS_SYMBOLIC;
1884 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
1886 && mips_symbol_insns (info->symbol_type, mode) > 0
1887 && !mips_split_p[info->symbol_type]);
1894 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1895 returns a nonzero value if X is a legitimate address for a memory
1896 operand of the indicated MODE. STRICT is nonzero if this function
1897 is called during reload. */
1900 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1902 struct mips_address_info addr;
1904 return mips_classify_address (&addr, x, mode, strict);
1907 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1910 mips_stack_address_p (rtx x, enum machine_mode mode)
1912 struct mips_address_info addr;
1914 return (mips_classify_address (&addr, x, mode, false)
1915 && addr.type == ADDRESS_REG
1916 && addr.reg == stack_pointer_rtx);
1919 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
1920 address instruction. */
1923 mips_lwxs_address_p (rtx addr)
1926 && GET_CODE (addr) == PLUS
1927 && REG_P (XEXP (addr, 1)))
1929 rtx offset = XEXP (addr, 0);
1930 if (GET_CODE (offset) == MULT
1931 && REG_P (XEXP (offset, 0))
1932 && GET_CODE (XEXP (offset, 1)) == CONST_INT
1933 && INTVAL (XEXP (offset, 1)) == 4)
1939 /* Return true if a value at OFFSET bytes from BASE can be accessed
1940 using an unextended mips16 instruction. MODE is the mode of the
1943 Usually the offset in an unextended instruction is a 5-bit field.
1944 The offset is unsigned and shifted left once for HIs, twice
1945 for SIs, and so on. An exception is SImode accesses off the
1946 stack pointer, which have an 8-bit immediate field. */
1949 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1952 && GET_CODE (offset) == CONST_INT
1953 && INTVAL (offset) >= 0
1954 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1956 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1957 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1958 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1964 /* Return the number of instructions needed to load or store a value
1965 of mode MODE at X. Return 0 if X isn't valid for MODE. Assume that
1966 multiword moves may need to be split into word moves if MIGHT_SPLIT_P,
1967 otherwise assume that a single load or store is enough.
1969 For mips16 code, count extended instructions as two instructions. */
1972 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
1974 struct mips_address_info addr;
1977 /* BLKmode is used for single unaligned loads and stores and should
1978 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
1979 meaningless, so we have to single it out as a special case one way
1981 if (mode != BLKmode && might_split_p)
1982 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1986 if (mips_classify_address (&addr, x, mode, false))
1991 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1995 case ADDRESS_LO_SUM:
1996 return (TARGET_MIPS16 ? factor * 2 : factor);
1998 case ADDRESS_CONST_INT:
2001 case ADDRESS_SYMBOLIC:
2002 return factor * mips_symbol_insns (addr.symbol_type, mode);
2008 /* Likewise for constant X. */
2011 mips_const_insns (rtx x)
2013 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2014 enum mips_symbol_type symbol_type;
2017 switch (GET_CODE (x))
2020 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2022 || !mips_split_p[symbol_type])
2025 /* This is simply an lui for normal mode. It is an extended
2026 "li" followed by an extended "sll" for MIPS16. */
2027 return TARGET_MIPS16 ? 4 : 1;
2031 /* Unsigned 8-bit constants can be loaded using an unextended
2032 LI instruction. Unsigned 16-bit constants can be loaded
2033 using an extended LI. Negative constants must be loaded
2034 using LI and then negated. */
2035 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
2036 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2037 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
2038 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2041 return mips_build_integer (codes, INTVAL (x));
2045 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
2051 /* See if we can refer to X directly. */
2052 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2053 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2055 /* Otherwise try splitting the constant into a base and offset.
2056 16-bit offsets can be added using an extra addiu. Larger offsets
2057 must be calculated separately and then added to the base. */
2058 split_const (x, &x, &offset);
2061 int n = mips_const_insns (x);
2064 if (SMALL_INT (offset))
2067 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2074 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2083 /* Return the number of instructions needed to implement INSN,
2084 given that it loads from or stores to MEM. Count extended
2085 mips16 instructions as two instructions. */
2088 mips_load_store_insns (rtx mem, rtx insn)
2090 enum machine_mode mode;
2094 gcc_assert (MEM_P (mem));
2095 mode = GET_MODE (mem);
2097 /* Try to prove that INSN does not need to be split. */
2098 might_split_p = true;
2099 if (GET_MODE_BITSIZE (mode) == 64)
2101 set = single_set (insn);
2102 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2103 might_split_p = false;
2106 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2110 /* Return the number of instructions needed for an integer division. */
2113 mips_idiv_insns (void)
2118 if (TARGET_CHECK_ZERO_DIV)
2120 if (GENERATE_DIVIDE_TRAPS)
2126 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2131 /* Emit a move from SRC to DEST. Assume that the move expanders can
2132 handle all moves if !can_create_pseudo_p (). The distinction is
2133 important because, unlike emit_move_insn, the move expanders know
2134 how to force Pmode objects into the constant pool even when the
2135 constant pool address is not itself legitimate. */
2138 mips_emit_move (rtx dest, rtx src)
2140 return (can_create_pseudo_p ()
2141 ? emit_move_insn (dest, src)
2142 : emit_move_insn_1 (dest, src));
2145 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2148 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2150 emit_insn (gen_rtx_SET (VOIDmode, target,
2151 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2154 /* Copy VALUE to a register and return that register. If new psuedos
2155 are allowed, copy it into a new register, otherwise use DEST. */
2158 mips_force_temporary (rtx dest, rtx value)
2160 if (can_create_pseudo_p ())
2161 return force_reg (Pmode, value);
2164 mips_emit_move (copy_rtx (dest), value);
2169 /* If we can access small data directly (using gp-relative relocation
2170 operators) return the small data pointer, otherwise return null.
2172 For each mips16 function which refers to GP relative symbols, we
2173 use a pseudo register, initialized at the start of the function, to
2174 hold the $gp value. */
2177 mips16_gp_pseudo_reg (void)
2179 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2180 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2182 /* Don't initialize the pseudo register if we are being called from
2183 the tree optimizers' cost-calculation routines. */
2184 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2185 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2189 /* We want to initialize this to a value which gcc will believe
2191 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2193 push_topmost_sequence ();
2194 /* We need to emit the initialization after the FUNCTION_BEG
2195 note, so that it will be integrated. */
2196 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
2198 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
2200 if (scan == NULL_RTX)
2201 scan = get_insns ();
2202 insn = emit_insn_after (insn, scan);
2203 pop_topmost_sequence ();
2205 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2208 return cfun->machine->mips16_gp_pseudo_rtx;
2211 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2212 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2213 constant in that context and can be split into a high part and a LO_SUM.
2214 If so, and if LO_SUM_OUT is nonnull, emit the high part and return
2215 the LO_SUM in *LO_SUM_OUT. Leave *LO_SUM_OUT unchanged otherwise.
2217 TEMP is as for mips_force_temporary and is used to load the high
2218 part into a register. */
2221 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *lo_sum_out)
2223 enum mips_symbol_context context;
2224 enum mips_symbol_type symbol_type;
2227 context = (mode == MAX_MACHINE_MODE
2228 ? SYMBOL_CONTEXT_LEA
2229 : SYMBOL_CONTEXT_MEM);
2230 if (!mips_symbolic_constant_p (addr, context, &symbol_type)
2231 || mips_symbol_insns (symbol_type, mode) == 0
2232 || !mips_split_p[symbol_type])
2237 if (symbol_type == SYMBOL_GP_RELATIVE)
2239 if (!can_create_pseudo_p ())
2241 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2245 high = mips16_gp_pseudo_reg ();
2249 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2250 high = mips_force_temporary (temp, high);
2252 *lo_sum_out = gen_rtx_LO_SUM (Pmode, high, addr);
2258 /* Wrap symbol or label BASE in an unspec address of type SYMBOL_TYPE
2259 and add CONST_INT OFFSET to the result. */
2262 mips_unspec_address_offset (rtx base, rtx offset,
2263 enum mips_symbol_type symbol_type)
2265 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2266 UNSPEC_ADDRESS_FIRST + symbol_type);
2267 if (offset != const0_rtx)
2268 base = gen_rtx_PLUS (Pmode, base, offset);
2269 return gen_rtx_CONST (Pmode, base);
2272 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2273 type SYMBOL_TYPE. */
2276 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2280 split_const (address, &base, &offset);
2281 return mips_unspec_address_offset (base, offset, symbol_type);
2285 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2286 high part to BASE and return the result. Just return BASE otherwise.
2287 TEMP is available as a temporary register if needed.
2289 The returned expression can be used as the first operand to a LO_SUM. */
2292 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2293 enum mips_symbol_type symbol_type)
2295 if (mips_split_p[symbol_type])
2297 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2298 addr = mips_force_temporary (temp, addr);
2299 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2305 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2306 mips_force_temporary; it is only needed when OFFSET is not a
2310 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2312 if (!SMALL_OPERAND (offset))
2317 /* Load the full offset into a register so that we can use
2318 an unextended instruction for the address itself. */
2319 high = GEN_INT (offset);
2324 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2325 high = GEN_INT (CONST_HIGH_PART (offset));
2326 offset = CONST_LOW_PART (offset);
2328 high = mips_force_temporary (temp, high);
2329 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2331 return plus_constant (reg, offset);
2334 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2335 referencing, and TYPE is the symbol type to use (either global
2336 dynamic or local dynamic). V0 is an RTX for the return value
2337 location. The entire insn sequence is returned. */
2339 static GTY(()) rtx mips_tls_symbol;
2342 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2344 rtx insn, loc, tga, a0;
2346 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2348 if (!mips_tls_symbol)
2349 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2351 loc = mips_unspec_address (sym, type);
2355 emit_insn (gen_rtx_SET (Pmode, a0,
2356 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2357 tga = gen_const_mem (Pmode, mips_tls_symbol);
2358 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2359 CONST_OR_PURE_CALL_P (insn) = 1;
2360 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2361 insn = get_insns ();
2368 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2369 return value will be a valid address and move_operand (either a REG
2373 mips_legitimize_tls_address (rtx loc)
2375 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2376 enum tls_model model;
2380 sorry ("MIPS16 TLS");
2381 return gen_reg_rtx (Pmode);
2384 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2385 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2387 model = SYMBOL_REF_TLS_MODEL (loc);
2388 /* Only TARGET_ABICALLS code can have more than one module; other
2389 code must be be static and should not use a GOT. All TLS models
2390 reduce to local exec in this situation. */
2391 if (!TARGET_ABICALLS)
2392 model = TLS_MODEL_LOCAL_EXEC;
2396 case TLS_MODEL_GLOBAL_DYNAMIC:
2397 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2398 dest = gen_reg_rtx (Pmode);
2399 emit_libcall_block (insn, dest, v0, loc);
2402 case TLS_MODEL_LOCAL_DYNAMIC:
2403 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2404 tmp1 = gen_reg_rtx (Pmode);
2406 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2407 share the LDM result with other LD model accesses. */
2408 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2410 emit_libcall_block (insn, tmp1, v0, eqv);
2412 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2413 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2414 mips_unspec_address (loc, SYMBOL_DTPREL));
2417 case TLS_MODEL_INITIAL_EXEC:
2418 tmp1 = gen_reg_rtx (Pmode);
2419 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2420 if (Pmode == DImode)
2422 emit_insn (gen_tls_get_tp_di (v1));
2423 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2427 emit_insn (gen_tls_get_tp_si (v1));
2428 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2430 dest = gen_reg_rtx (Pmode);
2431 emit_insn (gen_add3_insn (dest, tmp1, v1));
2434 case TLS_MODEL_LOCAL_EXEC:
2435 if (Pmode == DImode)
2436 emit_insn (gen_tls_get_tp_di (v1));
2438 emit_insn (gen_tls_get_tp_si (v1));
2440 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2441 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2442 mips_unspec_address (loc, SYMBOL_TPREL));
2452 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2453 be legitimized in a way that the generic machinery might not expect,
2454 put the new address in *XLOC and return true. MODE is the mode of
2455 the memory being accessed. */
2458 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2460 if (mips_tls_operand_p (*xloc))
2462 *xloc = mips_legitimize_tls_address (*xloc);
2466 /* See if the address can split into a high part and a LO_SUM. */
2467 if (mips_split_symbol (NULL, *xloc, mode, xloc))
2470 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2472 /* Handle REG + CONSTANT using mips_add_offset. */
2475 reg = XEXP (*xloc, 0);
2476 if (!mips_valid_base_register_p (reg, mode, 0))
2477 reg = copy_to_mode_reg (Pmode, reg);
2478 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2486 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2489 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2491 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2492 enum machine_mode mode;
2493 unsigned int i, cost;
2496 mode = GET_MODE (dest);
2497 cost = mips_build_integer (codes, value);
2499 /* Apply each binary operation to X. Invariant: X is a legitimate
2500 source operand for a SET pattern. */
2501 x = GEN_INT (codes[0].value);
2502 for (i = 1; i < cost; i++)
2504 if (!can_create_pseudo_p ())
2506 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2510 x = force_reg (mode, x);
2511 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2514 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2518 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2519 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2523 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2527 /* Split moves of big integers into smaller pieces. */
2528 if (splittable_const_int_operand (src, mode))
2530 mips_move_integer (dest, dest, INTVAL (src));
2534 /* Split moves of symbolic constants into high/low pairs. */
2535 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2537 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2541 if (mips_tls_operand_p (src))
2543 mips_emit_move (dest, mips_legitimize_tls_address (src));
2547 /* If we have (const (plus symbol offset)), and that expression cannot
2548 be forced into memory, load the symbol first and add in the offset.
2549 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2550 forced into memory, as it usually produces better code. */
2551 split_const (src, &base, &offset);
2552 if (offset != const0_rtx
2553 && (targetm.cannot_force_const_mem (src)
2554 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2556 base = mips_force_temporary (dest, base);
2557 mips_emit_move (dest, mips_add_offset (0, base, INTVAL (offset)));
2561 src = force_const_mem (mode, src);
2563 /* When using explicit relocs, constant pool references are sometimes
2564 not legitimate addresses. */
2565 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2566 mips_emit_move (dest, src);
2570 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2571 sequence that is valid. */
2574 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2576 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2578 mips_emit_move (dest, force_reg (mode, src));
2582 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2583 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2584 && REG_P (src) && MD_REG_P (REGNO (src))
2585 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2587 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2588 if (GET_MODE_SIZE (mode) <= 4)
2589 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2590 gen_rtx_REG (SImode, REGNO (src)),
2591 gen_rtx_REG (SImode, other_regno)));
2593 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2594 gen_rtx_REG (DImode, REGNO (src)),
2595 gen_rtx_REG (DImode, other_regno)));
2599 /* We need to deal with constants that would be legitimate
2600 immediate_operands but not legitimate move_operands. */
2601 if (CONSTANT_P (src) && !move_operand (src, mode))
2603 mips_legitimize_const_move (mode, dest, src);
2604 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2610 /* Return true if X in context CONTEXT is a small data address that can
2611 be rewritten as a LO_SUM. */
2614 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2616 enum mips_symbol_type symbol_type;
2618 return (TARGET_EXPLICIT_RELOCS
2619 && mips_symbolic_constant_p (x, context, &symbol_type)
2620 && symbol_type == SYMBOL_GP_RELATIVE);
2624 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
2625 containing MEM, or null if none. */
2628 mips_small_data_pattern_1 (rtx *loc, void *data)
2630 enum mips_symbol_context context;
2632 if (GET_CODE (*loc) == LO_SUM)
2637 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
2642 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2643 return mips_rewrite_small_data_p (*loc, context);
2646 /* Return true if OP refers to small data symbols directly, not through
2650 mips_small_data_pattern_p (rtx op)
2652 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
2655 /* A for_each_rtx callback, used by mips_rewrite_small_data.
2656 DATA is the containing MEM, or null if none. */
2659 mips_rewrite_small_data_1 (rtx *loc, void *data)
2661 enum mips_symbol_context context;
2665 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
2669 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
2670 if (mips_rewrite_small_data_p (*loc, context))
2671 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
2673 if (GET_CODE (*loc) == LO_SUM)
2679 /* If possible, rewrite OP so that it refers to small data using
2680 explicit relocations. */
2683 mips_rewrite_small_data (rtx op)
2685 op = copy_insn (op);
2686 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
2690 /* We need a lot of little routines to check constant values on the
2691 mips16. These are used to figure out how long the instruction will
2692 be. It would be much better to do this using constraints, but
2693 there aren't nearly enough letters available. */
2696 m16_check_op (rtx op, int low, int high, int mask)
2698 return (GET_CODE (op) == CONST_INT
2699 && INTVAL (op) >= low
2700 && INTVAL (op) <= high
2701 && (INTVAL (op) & mask) == 0);
2705 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2707 return m16_check_op (op, 0x1, 0x8, 0);
2711 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2713 return m16_check_op (op, - 0x8, 0x7, 0);
2717 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2719 return m16_check_op (op, - 0x7, 0x8, 0);
2723 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2725 return m16_check_op (op, - 0x10, 0xf, 0);
2729 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2731 return m16_check_op (op, - 0xf, 0x10, 0);
2735 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2737 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2741 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2743 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2747 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2749 return m16_check_op (op, - 0x80, 0x7f, 0);
2753 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2755 return m16_check_op (op, - 0x7f, 0x80, 0);
2759 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2761 return m16_check_op (op, 0x0, 0xff, 0);
2765 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2767 return m16_check_op (op, - 0xff, 0x0, 0);
2771 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2773 return m16_check_op (op, - 0x1, 0xfe, 0);
2777 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2779 return m16_check_op (op, 0x0, 0xff << 2, 3);
2783 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2785 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2789 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2791 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2795 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2797 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2800 /* The cost of loading values from the constant pool. It should be
2801 larger than the cost of any constant we want to synthesize inline. */
2803 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
2805 /* Return the cost of X when used as an operand to the MIPS16 instruction
2806 that implements CODE. Return -1 if there is no such instruction, or if
2807 X is not a valid immediate operand for it. */
2810 mips16_constant_cost (int code, HOST_WIDE_INT x)
2817 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
2818 other shifts are extended. The shift patterns truncate the shift
2819 count to the right size, so there are no out-of-range values. */
2820 if (IN_RANGE (x, 1, 8))
2822 return COSTS_N_INSNS (1);
2825 if (IN_RANGE (x, -128, 127))
2827 if (SMALL_OPERAND (x))
2828 return COSTS_N_INSNS (1);
2832 /* Like LE, but reject the always-true case. */
2836 /* We add 1 to the immediate and use SLT. */
2839 /* We can use CMPI for an xor with an unsigned 16-bit X. */
2842 if (IN_RANGE (x, 0, 255))
2844 if (SMALL_OPERAND_UNSIGNED (x))
2845 return COSTS_N_INSNS (1);
2850 /* Equality comparisons with 0 are cheap. */
2860 /* Return true if there is a non-MIPS16 instruction that implements CODE
2861 and if that instruction accepts X as an immediate operand. */
2864 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
2871 /* All shift counts are truncated to a valid constant. */
2876 /* Likewise rotates, if the target supports rotates at all. */
2882 /* These instructions take 16-bit unsigned immediates. */
2883 return SMALL_OPERAND_UNSIGNED (x);
2888 /* These instructions take 16-bit signed immediates. */
2889 return SMALL_OPERAND (x);
2895 /* The "immediate" forms of these instructions are really
2896 implemented as comparisons with register 0. */
2901 /* Likewise, meaning that the only valid immediate operand is 1. */
2905 /* We add 1 to the immediate and use SLT. */
2906 return SMALL_OPERAND (x + 1);
2909 /* Likewise SLTU, but reject the always-true case. */
2910 return SMALL_OPERAND (x + 1) && x + 1 != 0;
2914 /* The bit position and size are immediate operands. */
2915 return ISA_HAS_EXT_INS;
2918 /* By default assume that $0 can be used for 0. */
2923 /* Return the cost of binary operation X, given that the instruction
2924 sequence for a word-sized or smaller operation has cost SINGLE_COST
2925 and that the sequence of a double-word operation has cost DOUBLE_COST. */
2928 mips_binary_cost (rtx x, int single_cost, int double_cost)
2932 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
2937 + rtx_cost (XEXP (x, 0), 0)
2938 + rtx_cost (XEXP (x, 1), GET_CODE (x)));
2941 /* Return the cost of floating-point multiplications of mode MODE. */
2944 mips_fp_mult_cost (enum machine_mode mode)
2946 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
2949 /* Return the cost of floating-point divisions of mode MODE. */
2952 mips_fp_div_cost (enum machine_mode mode)
2954 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
2957 /* Return the cost of sign-extending OP to mode MODE, not including the
2958 cost of OP itself. */
2961 mips_sign_extend_cost (enum machine_mode mode, rtx op)
2964 /* Extended loads are as cheap as unextended ones. */
2967 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2968 /* A sign extension from SImode to DImode in 64-bit mode is free. */
2971 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
2972 /* We can use SEB or SEH. */
2973 return COSTS_N_INSNS (1);
2975 /* We need to use a shift left and a shift right. */
2976 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2979 /* Return the cost of zero-extending OP to mode MODE, not including the
2980 cost of OP itself. */
2983 mips_zero_extend_cost (enum machine_mode mode, rtx op)
2986 /* Extended loads are as cheap as unextended ones. */
2989 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
2990 /* We need a shift left by 32 bits and a shift right by 32 bits. */
2991 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
2993 if (GENERATE_MIPS16E)
2994 /* We can use ZEB or ZEH. */
2995 return COSTS_N_INSNS (1);
2998 /* We need to load 0xff or 0xffff into a register and use AND. */
2999 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3001 /* We can use ANDI. */
3002 return COSTS_N_INSNS (1);
3005 /* Implement TARGET_RTX_COSTS. */
3008 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
3010 enum machine_mode mode = GET_MODE (x);
3011 bool float_mode_p = FLOAT_MODE_P (mode);
3015 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3016 appear in the instruction stream, and the cost of a comparison is
3017 really the cost of the branch or scc condition. At the time of
3018 writing, gcc only uses an explicit outer COMPARE code when optabs
3019 is testing whether a constant is expensive enough to force into a
3020 register. We want optabs to pass such constants through the MIPS
3021 expanders instead, so make all constants very cheap here. */
3022 if (outer_code == COMPARE)
3024 gcc_assert (CONSTANT_P (x));
3032 /* Treat *clear_upper32-style ANDs as having zero cost in the
3033 second operand. The cost is entirely in the first operand.
3035 ??? This is needed because we would otherwise try to CSE
3036 the constant operand. Although that's the right thing for
3037 instructions that continue to be a register operation throughout
3038 compilation, it is disastrous for instructions that could
3039 later be converted into a memory operation. */
3041 && outer_code == AND
3042 && UINTVAL (x) == 0xffffffff)
3050 cost = mips16_constant_cost (outer_code, INTVAL (x));
3059 /* When not optimizing for size, we care more about the cost
3060 of hot code, and hot code is often in a loop. If a constant
3061 operand needs to be forced into a register, we will often be
3062 able to hoist the constant load out of the loop, so the load
3063 should not contribute to the cost. */
3065 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3077 if (force_to_mem_operand (x, VOIDmode))
3079 *total = COSTS_N_INSNS (1);
3082 cost = mips_const_insns (x);
3085 /* If the constant is likely to be stored in a GPR, SETs of
3086 single-insn constants are as cheap as register sets; we
3087 never want to CSE them.
3089 Don't reduce the cost of storing a floating-point zero in
3090 FPRs. If we have a zero in an FPR for other reasons, we
3091 can get better cfg-cleanup and delayed-branch results by
3092 using it consistently, rather than using $0 sometimes and
3093 an FPR at other times. Also, moves between floating-point
3094 registers are sometimes cheaper than (D)MTC1 $0. */
3096 && outer_code == SET
3097 && !(float_mode_p && TARGET_HARD_FLOAT))
3099 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3100 want to CSE the constant itself. It is usually better to
3101 have N copies of the last operation in the sequence and one
3102 shared copy of the other operations. (Note that this is
3103 not true for MIPS16 code, where the final operation in the
3104 sequence is often an extended instruction.)
3106 Also, if we have a CONST_INT, we don't know whether it is
3107 for a word or doubleword operation, so we cannot rely on
3108 the result of mips_build_integer. */
3109 else if (!TARGET_MIPS16
3110 && (outer_code == SET || mode == VOIDmode))
3112 *total = COSTS_N_INSNS (cost);
3115 /* The value will need to be fetched from the constant pool. */
3116 *total = CONSTANT_POOL_COST;
3120 /* If the address is legitimate, return the number of
3121 instructions it needs. */
3123 cost = mips_address_insns (addr, mode, true);
3126 *total = COSTS_N_INSNS (cost + 1);
3129 /* Check for a scaled indexed address. */
3130 if (mips_lwxs_address_p (addr))
3132 *total = COSTS_N_INSNS (2);
3135 /* Otherwise use the default handling. */
3139 *total = COSTS_N_INSNS (6);
3143 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3147 /* Check for a *clear_upper32 pattern and treat it like a zero
3148 extension. See the pattern's comment for details. */
3151 && CONST_INT_P (XEXP (x, 1))
3152 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3154 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3155 + rtx_cost (XEXP (x, 0), 0));
3162 /* Double-word operations use two single-word operations. */
3163 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3171 if (CONSTANT_P (XEXP (x, 1)))
3172 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3174 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3179 *total = mips_cost->fp_add;
3181 *total = COSTS_N_INSNS (4);
3185 /* Low-part immediates need an extended MIPS16 instruction. */
3186 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3187 + rtx_cost (XEXP (x, 0), 0));
3202 /* Branch comparisons have VOIDmode, so use the first operand's
3204 mode = GET_MODE (XEXP (x, 0));
3205 if (FLOAT_MODE_P (mode))
3207 *total = mips_cost->fp_add;
3210 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3215 && ISA_HAS_NMADD_NMSUB (mode)
3216 && TARGET_FUSED_MADD
3217 && !HONOR_NANS (mode)
3218 && !HONOR_SIGNED_ZEROS (mode))
3220 /* See if we can use NMADD or NMSUB. See mips.md for the
3221 associated patterns. */
3222 rtx op0 = XEXP (x, 0);
3223 rtx op1 = XEXP (x, 1);
3224 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3226 *total = (mips_fp_mult_cost (mode)
3227 + rtx_cost (XEXP (XEXP (op0, 0), 0), 0)
3228 + rtx_cost (XEXP (op0, 1), 0)
3229 + rtx_cost (op1, 0));
3232 if (GET_CODE (op1) == MULT)
3234 *total = (mips_fp_mult_cost (mode)
3236 + rtx_cost (XEXP (op1, 0), 0)
3237 + rtx_cost (XEXP (op1, 1), 0));
3247 && TARGET_FUSED_MADD
3248 && GET_CODE (XEXP (x, 0)) == MULT)
3251 *total = mips_cost->fp_add;
3255 /* Double-word operations require three single-word operations and
3256 an SLTU. The MIPS16 version then needs to move the result of
3257 the SLTU from $24 to a MIPS16 register. */
3258 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3259 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3264 && ISA_HAS_NMADD_NMSUB (mode)
3265 && TARGET_FUSED_MADD
3266 && !HONOR_NANS (mode)
3267 && HONOR_SIGNED_ZEROS (mode))
3269 /* See if we can use NMADD or NMSUB. See mips.md for the
3270 associated patterns. */
3271 rtx op = XEXP (x, 0);
3272 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3273 && GET_CODE (XEXP (op, 0)) == MULT)
3275 *total = (mips_fp_mult_cost (mode)
3276 + rtx_cost (XEXP (XEXP (op, 0), 0), 0)
3277 + rtx_cost (XEXP (XEXP (op, 0), 1), 0)
3278 + rtx_cost (XEXP (op, 1), 0));
3284 *total = mips_cost->fp_add;
3286 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3291 *total = mips_fp_mult_cost (mode);
3292 else if (mode == DImode && !TARGET_64BIT)
3293 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3294 where the mulsidi3 always includes an MFHI and an MFLO. */
3295 *total = (optimize_size
3296 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3297 : mips_cost->int_mult_si * 3 + 6);
3298 else if (optimize_size)
3299 *total = (ISA_HAS_MUL3 ? 1 : 2);
3300 else if (mode == DImode)
3301 *total = mips_cost->int_mult_di;
3303 *total = mips_cost->int_mult_si;
3307 /* Check for a reciprocal. */
3310 && flag_unsafe_math_optimizations
3311 && XEXP (x, 0) == CONST1_RTX (mode))
3313 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3314 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3315 division as being free. */
3316 *total = rtx_cost (XEXP (x, 1), 0);
3318 *total = mips_fp_div_cost (mode) + rtx_cost (XEXP (x, 1), 0);
3327 *total = mips_fp_div_cost (mode);
3336 /* It is our responsibility to make division by a power of 2
3337 as cheap as 2 register additions if we want the division
3338 expanders to be used for such operations; see the setting
3339 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3340 should always produce shorter code than using
3341 expand_sdiv2_pow2. */
3343 && CONST_INT_P (XEXP (x, 1))
3344 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3346 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), 0);
3349 *total = COSTS_N_INSNS (mips_idiv_insns ());
3351 else if (mode == DImode)
3352 *total = mips_cost->int_div_di;
3354 *total = mips_cost->int_div_si;
3358 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3362 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3366 case UNSIGNED_FLOAT:
3369 case FLOAT_TRUNCATE:
3370 *total = mips_cost->fp_add;
3378 /* Provide the costs of an addressing mode that contains ADDR.
3379 If ADDR is not a valid address, its cost is irrelevant. */
3382 mips_address_cost (rtx addr)
3384 return mips_address_insns (addr, SImode, false);
3387 /* Return one word of double-word value OP, taking into account the fixed
3388 endianness of certain registers. HIGH_P is true to select the high part,
3389 false to select the low part. */
3392 mips_subword (rtx op, int high_p)
3394 unsigned int byte, offset;
3395 enum machine_mode mode;
3397 mode = GET_MODE (op);
3398 if (mode == VOIDmode)
3401 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3402 byte = UNITS_PER_WORD;
3406 if (FP_REG_RTX_P (op))
3408 /* Paired FPRs are always ordered little-endian. */
3409 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3410 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3414 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3416 return simplify_gen_subreg (word_mode, op, mode, byte);
3420 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3423 mips_split_64bit_move_p (rtx dest, rtx src)
3428 /* FP->FP moves can be done in a single instruction. */
3429 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3432 /* Check for floating-point loads and stores. */
3433 if (ISA_HAS_LDC1_SDC1)
3435 if (FP_REG_RTX_P (dest) && MEM_P (src))
3437 if (FP_REG_RTX_P (src) && MEM_P (dest))
3444 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3445 this function handles 64-bit moves for which mips_split_64bit_move_p
3446 holds. For 64-bit targets, this function handles 128-bit moves. */
3449 mips_split_doubleword_move (rtx dest, rtx src)
3451 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3453 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3454 emit_insn (gen_move_doubleword_fprdi (dest, src));
3455 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3456 emit_insn (gen_move_doubleword_fprdf (dest, src));
3457 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3458 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3459 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3460 emit_insn (gen_move_doubleword_fprtf (dest, src));
3466 /* The operation can be split into two normal moves. Decide in
3467 which order to do them. */
3470 low_dest = mips_subword (dest, 0);
3471 if (REG_P (low_dest)
3472 && reg_overlap_mentioned_p (low_dest, src))
3474 mips_emit_move (mips_subword (dest, 1), mips_subword (src, 1));
3475 mips_emit_move (low_dest, mips_subword (src, 0));
3479 mips_emit_move (low_dest, mips_subword (src, 0));
3480 mips_emit_move (mips_subword (dest, 1), mips_subword (src, 1));
3485 /* Return the appropriate instructions to move SRC into DEST. Assume
3486 that SRC is operand 1 and DEST is operand 0. */
3489 mips_output_move (rtx dest, rtx src)
3491 enum rtx_code dest_code, src_code;
3492 enum mips_symbol_type symbol_type;
3495 dest_code = GET_CODE (dest);
3496 src_code = GET_CODE (src);
3497 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
3499 if (dbl_p && mips_split_64bit_move_p (dest, src))
3502 if ((src_code == REG && GP_REG_P (REGNO (src)))
3503 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3505 if (dest_code == REG)
3507 if (GP_REG_P (REGNO (dest)))
3508 return "move\t%0,%z1";
3510 if (MD_REG_P (REGNO (dest)))
3513 if (DSP_ACC_REG_P (REGNO (dest)))
3515 static char retval[] = "mt__\t%z1,%q0";
3516 retval[2] = reg_names[REGNO (dest)][4];
3517 retval[3] = reg_names[REGNO (dest)][5];
3521 if (FP_REG_P (REGNO (dest)))
3522 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3524 if (ALL_COP_REG_P (REGNO (dest)))
3526 static char retval[] = "dmtc_\t%z1,%0";
3528 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3529 return (dbl_p ? retval : retval + 1);
3532 if (dest_code == MEM)
3533 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3535 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3537 if (src_code == REG)
3539 if (DSP_ACC_REG_P (REGNO (src)))
3541 static char retval[] = "mf__\t%0,%q1";
3542 retval[2] = reg_names[REGNO (src)][4];
3543 retval[3] = reg_names[REGNO (src)][5];
3547 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3548 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3550 if (FP_REG_P (REGNO (src)))
3551 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3553 if (ALL_COP_REG_P (REGNO (src)))
3555 static char retval[] = "dmfc_\t%0,%1";
3557 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3558 return (dbl_p ? retval : retval + 1);
3562 if (src_code == MEM)
3563 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3565 if (src_code == CONST_INT)
3567 /* Don't use the X format, because that will give out of
3568 range numbers for 64-bit hosts and 32-bit targets. */
3570 return "li\t%0,%1\t\t\t# %X1";
3572 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3575 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3579 if (src_code == HIGH)
3580 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
3582 if (CONST_GP_P (src))
3583 return "move\t%0,%1";
3585 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
3586 && mips_lo_relocs[symbol_type] != 0)
3588 /* A signed 16-bit constant formed by applying a relocation
3589 operator to a symbolic address. */
3590 gcc_assert (!mips_split_p[symbol_type]);
3591 return "li\t%0,%R1";
3594 if (symbolic_operand (src, VOIDmode))
3596 gcc_assert (TARGET_MIPS16
3597 ? TARGET_MIPS16_TEXT_LOADS
3598 : !TARGET_EXPLICIT_RELOCS);
3599 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3602 if (src_code == REG && FP_REG_P (REGNO (src)))
3604 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3606 if (GET_MODE (dest) == V2SFmode)
3607 return "mov.ps\t%0,%1";
3609 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3612 if (dest_code == MEM)
3613 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3615 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3617 if (src_code == MEM)
3618 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3620 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3622 static char retval[] = "l_c_\t%0,%1";
3624 retval[1] = (dbl_p ? 'd' : 'w');
3625 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3628 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3630 static char retval[] = "s_c_\t%1,%0";
3632 retval[1] = (dbl_p ? 'd' : 'w');
3633 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3639 /* Return true if CMP1 is a suitable second operand for relational
3640 operator CODE. See also the *sCC patterns in mips.md. */
3643 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3649 return reg_or_0_operand (cmp1, VOIDmode);
3653 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3657 return arith_operand (cmp1, VOIDmode);
3660 return sle_operand (cmp1, VOIDmode);
3663 return sleu_operand (cmp1, VOIDmode);
3670 /* Canonicalize LE or LEU comparisons into LT comparisons when
3671 possible to avoid extra instructions or inverting the
3675 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3676 enum machine_mode mode)
3678 HOST_WIDE_INT plus_one;
3680 if (mips_relational_operand_ok_p (*code, *cmp1))
3683 if (GET_CODE (*cmp1) == CONST_INT)
3687 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3688 if (INTVAL (*cmp1) < plus_one)
3691 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3697 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
3701 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3712 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3713 result in TARGET. CMP0 and TARGET are register_operands that have
3714 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3715 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3718 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3719 rtx target, rtx cmp0, rtx cmp1)
3721 /* First see if there is a MIPS instruction that can do this operation.
3722 If not, try doing the same for the inverse operation. If that also
3723 fails, force CMP1 into a register and try again. */
3724 if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3725 mips_emit_binary (code, target, cmp0, cmp1);
3728 enum rtx_code inv_code = reverse_condition (code);
3729 if (!mips_canonicalize_comparison (&inv_code, &cmp1, GET_MODE (target)))
3731 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3732 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3734 else if (invert_ptr == 0)
3736 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3737 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3738 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3742 *invert_ptr = !*invert_ptr;
3743 mips_emit_binary (inv_code, target, cmp0, cmp1);
3748 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3749 The register will have the same mode as CMP0. */
3752 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3754 if (cmp1 == const0_rtx)
3757 if (uns_arith_operand (cmp1, VOIDmode))
3758 return expand_binop (GET_MODE (cmp0), xor_optab,
3759 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3761 return expand_binop (GET_MODE (cmp0), sub_optab,
3762 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3765 /* Convert *CODE into a code that can be used in a floating-point
3766 scc instruction (c.<cond>.<fmt>). Return true if the values of
3767 the condition code registers will be inverted, with 0 indicating
3768 that the condition holds. */
3771 mips_reverse_fp_cond_p (enum rtx_code *code)
3778 *code = reverse_condition_maybe_unordered (*code);
3786 /* Convert a comparison into something that can be used in a branch or
3787 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3788 being compared and *CODE is the code used to compare them.
3790 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3791 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3792 otherwise any standard branch condition can be used. The standard branch
3795 - EQ/NE between two registers.
3796 - any comparison between a register and zero. */
3799 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3801 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3803 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3805 *op0 = cmp_operands[0];
3806 *op1 = cmp_operands[1];
3808 else if (*code == EQ || *code == NE)
3812 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3817 *op0 = cmp_operands[0];
3818 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3823 /* The comparison needs a separate scc instruction. Store the
3824 result of the scc in *OP0 and compare it against zero. */
3825 bool invert = false;
3826 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3828 mips_emit_int_relational (*code, &invert, *op0,
3829 cmp_operands[0], cmp_operands[1]);
3830 *code = (invert ? EQ : NE);
3833 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_operands[0])))
3835 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
3836 mips_emit_binary (*code, *op0, cmp_operands[0], cmp_operands[1]);
3842 enum rtx_code cmp_code;
3844 /* Floating-point tests use a separate c.cond.fmt comparison to
3845 set a condition code register. The branch or conditional move
3846 will then compare that register against zero.
3848 Set CMP_CODE to the code of the comparison instruction and
3849 *CODE to the code that the branch or move should use. */
3851 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3853 ? gen_reg_rtx (CCmode)
3854 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3856 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3860 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3861 Store the result in TARGET and return true if successful.
3863 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3866 mips_emit_scc (enum rtx_code code, rtx target)
3868 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3871 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3872 if (code == EQ || code == NE)
3874 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3875 mips_emit_binary (code, target, zie, const0_rtx);
3878 mips_emit_int_relational (code, 0, target,
3879 cmp_operands[0], cmp_operands[1]);
3883 /* Emit the common code for doing conditional branches.
3884 operand[0] is the label to jump to.
3885 The comparison operands are saved away by cmp{si,di,sf,df}. */
3888 gen_conditional_branch (rtx *operands, enum rtx_code code)
3890 rtx op0, op1, condition;
3892 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3893 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3894 emit_jump_insn (gen_condjump (condition, operands[0]));
3899 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3900 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3903 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3904 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3909 reversed_p = mips_reverse_fp_cond_p (&cond);
3910 cmp_result = gen_reg_rtx (CCV2mode);
3911 emit_insn (gen_scc_ps (cmp_result,
3912 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3914 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3917 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3921 /* Emit the common code for conditional moves. OPERANDS is the array
3922 of operands passed to the conditional move define_expand. */
3925 gen_conditional_move (rtx *operands)
3930 code = GET_CODE (operands[1]);
3931 mips_emit_compare (&code, &op0, &op1, true);
3932 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3933 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3934 gen_rtx_fmt_ee (code,
3937 operands[2], operands[3])));
3940 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3941 the conditional_trap expander. */
3944 mips_gen_conditional_trap (rtx *operands)
3947 enum rtx_code cmp_code = GET_CODE (operands[0]);
3948 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3950 /* MIPS conditional trap machine instructions don't have GT or LE
3951 flavors, so we must invert the comparison and convert to LT and
3952 GE, respectively. */
3955 case GT: cmp_code = LT; break;
3956 case LE: cmp_code = GE; break;
3957 case GTU: cmp_code = LTU; break;
3958 case LEU: cmp_code = GEU; break;
3961 if (cmp_code == GET_CODE (operands[0]))
3963 op0 = cmp_operands[0];
3964 op1 = cmp_operands[1];
3968 op0 = cmp_operands[1];
3969 op1 = cmp_operands[0];
3971 op0 = force_reg (mode, op0);
3972 if (!arith_operand (op1, mode))
3973 op1 = force_reg (mode, op1);
3975 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3976 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3980 /* Argument support functions. */
3982 /* Initialize CUMULATIVE_ARGS for a function. */
3985 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3986 rtx libname ATTRIBUTE_UNUSED)
3988 static CUMULATIVE_ARGS zero_cum;
3989 tree param, next_param;
3992 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3994 /* Determine if this function has variable arguments. This is
3995 indicated by the last argument being 'void_type_mode' if there
3996 are no variable arguments. The standard MIPS calling sequence
3997 passes all arguments in the general purpose registers in this case. */
3999 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
4000 param != 0; param = next_param)
4002 next_param = TREE_CHAIN (param);
4003 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
4004 cum->gp_reg_found = 1;
4009 /* Fill INFO with information about a single argument. CUM is the
4010 cumulative state for earlier arguments. MODE is the mode of this
4011 argument and TYPE is its type (if known). NAMED is true if this
4012 is a named (fixed) argument rather than a variable one. */
4015 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4016 tree type, int named, struct mips_arg_info *info)
4018 bool doubleword_aligned_p;
4019 unsigned int num_bytes, num_words, max_regs;
4021 /* Work out the size of the argument. */
4022 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4023 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4025 /* Decide whether it should go in a floating-point register, assuming
4026 one is free. Later code checks for availability.
4028 The checks against UNITS_PER_FPVALUE handle the soft-float and
4029 single-float cases. */
4033 /* The EABI conventions have traditionally been defined in terms
4034 of TYPE_MODE, regardless of the actual type. */
4035 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4036 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4037 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4042 /* Only leading floating-point scalars are passed in
4043 floating-point registers. We also handle vector floats the same
4044 say, which is OK because they are not covered by the standard ABI. */
4045 info->fpr_p = (!cum->gp_reg_found
4046 && cum->arg_number < 2
4047 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
4048 || VECTOR_FLOAT_TYPE_P (type))
4049 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4050 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4051 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4056 /* Scalar and complex floating-point types are passed in
4057 floating-point registers. */
4058 info->fpr_p = (named
4059 && (type == 0 || FLOAT_TYPE_P (type))
4060 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4061 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4062 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4063 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4065 /* ??? According to the ABI documentation, the real and imaginary
4066 parts of complex floats should be passed in individual registers.
4067 The real and imaginary parts of stack arguments are supposed
4068 to be contiguous and there should be an extra word of padding
4071 This has two problems. First, it makes it impossible to use a
4072 single "void *" va_list type, since register and stack arguments
4073 are passed differently. (At the time of writing, MIPSpro cannot
4074 handle complex float varargs correctly.) Second, it's unclear
4075 what should happen when there is only one register free.
4077 For now, we assume that named complex floats should go into FPRs
4078 if there are two FPRs free, otherwise they should be passed in the
4079 same way as a struct containing two floats. */
4081 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4082 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4084 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4085 info->fpr_p = false;
4095 /* See whether the argument has doubleword alignment. */
4096 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4098 /* Set REG_OFFSET to the register count we're interested in.
4099 The EABI allocates the floating-point registers separately,
4100 but the other ABIs allocate them like integer registers. */
4101 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4105 /* Advance to an even register if the argument is doubleword-aligned. */
4106 if (doubleword_aligned_p)
4107 info->reg_offset += info->reg_offset & 1;
4109 /* Work out the offset of a stack argument. */
4110 info->stack_offset = cum->stack_words;
4111 if (doubleword_aligned_p)
4112 info->stack_offset += info->stack_offset & 1;
4114 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4116 /* Partition the argument between registers and stack. */
4117 info->reg_words = MIN (num_words, max_regs);
4118 info->stack_words = num_words - info->reg_words;
4121 /* INFO describes an argument that is passed in a single-register value.
4122 Return the register it uses, assuming that FPRs are available if
4126 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4128 if (!info->fpr_p || !hard_float_p)
4129 return GP_ARG_FIRST + info->reg_offset;
4130 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4131 /* In o32, the second argument is always passed in $f14
4132 for TARGET_DOUBLE_FLOAT, regardless of whether the
4133 first argument was a word or doubleword. */
4134 return FP_ARG_FIRST + 2;
4136 return FP_ARG_FIRST + info->reg_offset;
4140 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4142 return !TARGET_OLDABI;
4145 /* Implement FUNCTION_ARG. */
4148 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4149 tree type, int named)
4151 struct mips_arg_info info;
4153 /* We will be called with a mode of VOIDmode after the last argument
4154 has been seen. Whatever we return will be passed to the call
4155 insn. If we need a mips16 fp_code, return a REG with the code
4156 stored as the mode. */
4157 if (mode == VOIDmode)
4159 if (TARGET_MIPS16 && cum->fp_code != 0)
4160 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4166 mips_arg_info (cum, mode, type, named, &info);
4168 /* Return straight away if the whole argument is passed on the stack. */
4169 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4173 && TREE_CODE (type) == RECORD_TYPE
4175 && TYPE_SIZE_UNIT (type)
4176 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4179 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4180 structure contains a double in its entirety, then that 64-bit
4181 chunk is passed in a floating point register. */
4184 /* First check to see if there is any such field. */
4185 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4186 if (TREE_CODE (field) == FIELD_DECL
4187 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4188 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4189 && host_integerp (bit_position (field), 0)
4190 && int_bit_position (field) % BITS_PER_WORD == 0)
4195 /* Now handle the special case by returning a PARALLEL
4196 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4197 chunks are passed in registers. */
4199 HOST_WIDE_INT bitpos;
4202 /* assign_parms checks the mode of ENTRY_PARM, so we must
4203 use the actual mode here. */
4204 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4207 field = TYPE_FIELDS (type);
4208 for (i = 0; i < info.reg_words; i++)
4212 for (; field; field = TREE_CHAIN (field))
4213 if (TREE_CODE (field) == FIELD_DECL
4214 && int_bit_position (field) >= bitpos)
4218 && int_bit_position (field) == bitpos
4219 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4220 && !TARGET_SOFT_FLOAT
4221 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4222 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4224 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4227 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4228 GEN_INT (bitpos / BITS_PER_UNIT));
4230 bitpos += BITS_PER_WORD;
4236 /* Handle the n32/n64 conventions for passing complex floating-point
4237 arguments in FPR pairs. The real part goes in the lower register
4238 and the imaginary part goes in the upper register. */
4241 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4244 enum machine_mode inner;
4247 inner = GET_MODE_INNER (mode);
4248 reg = FP_ARG_FIRST + info.reg_offset;
4249 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4251 /* Real part in registers, imaginary part on stack. */
4252 gcc_assert (info.stack_words == info.reg_words);
4253 return gen_rtx_REG (inner, reg);
4257 gcc_assert (info.stack_words == 0);
4258 real = gen_rtx_EXPR_LIST (VOIDmode,
4259 gen_rtx_REG (inner, reg),
4261 imag = gen_rtx_EXPR_LIST (VOIDmode,
4263 reg + info.reg_words / 2),
4264 GEN_INT (GET_MODE_SIZE (inner)));
4265 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4269 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4272 /* Implement FUNCTION_ARG_ADVANCE. */
4275 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4276 tree type, int named)
4278 struct mips_arg_info info;
4280 mips_arg_info (cum, mode, type, named, &info);
4283 cum->gp_reg_found = true;
4285 /* See the comment above the cumulative args structure in mips.h
4286 for an explanation of what this code does. It assumes the O32
4287 ABI, which passes at most 2 arguments in float registers. */
4288 if (cum->arg_number < 2 && info.fpr_p)
4289 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4291 if (mips_abi != ABI_EABI || !info.fpr_p)
4292 cum->num_gprs = info.reg_offset + info.reg_words;
4293 else if (info.reg_words > 0)
4294 cum->num_fprs += MAX_FPRS_PER_FMT;
4296 if (info.stack_words > 0)
4297 cum->stack_words = info.stack_offset + info.stack_words;
4302 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4305 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4306 enum machine_mode mode, tree type, bool named)
4308 struct mips_arg_info info;
4310 mips_arg_info (cum, mode, type, named, &info);
4311 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4315 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4316 PARM_BOUNDARY bits of alignment, but will be given anything up
4317 to STACK_BOUNDARY bits if the type requires it. */
4320 function_arg_boundary (enum machine_mode mode, tree type)
4322 unsigned int alignment;
4324 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4325 if (alignment < PARM_BOUNDARY)
4326 alignment = PARM_BOUNDARY;
4327 if (alignment > STACK_BOUNDARY)
4328 alignment = STACK_BOUNDARY;
4332 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4333 upward rather than downward. In other words, return true if the
4334 first byte of the stack slot has useful data, false if the last
4338 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4340 /* On little-endian targets, the first byte of every stack argument
4341 is passed in the first byte of the stack slot. */
4342 if (!BYTES_BIG_ENDIAN)
4345 /* Otherwise, integral types are padded downward: the last byte of a
4346 stack argument is passed in the last byte of the stack slot. */
4348 ? (INTEGRAL_TYPE_P (type)
4349 || POINTER_TYPE_P (type)
4350 || FIXED_POINT_TYPE_P (type))
4351 : (GET_MODE_CLASS (mode) == MODE_INT
4352 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4355 /* Big-endian o64 pads floating-point arguments downward. */
4356 if (mips_abi == ABI_O64)
4357 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4360 /* Other types are padded upward for o32, o64, n32 and n64. */
4361 if (mips_abi != ABI_EABI)
4364 /* Arguments smaller than a stack slot are padded downward. */
4365 if (mode != BLKmode)
4366 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4368 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4372 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4373 if the least significant byte of the register has useful data. Return
4374 the opposite if the most significant byte does. */
4377 mips_pad_reg_upward (enum machine_mode mode, tree type)
4379 /* No shifting is required for floating-point arguments. */
4380 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4381 return !BYTES_BIG_ENDIAN;
4383 /* Otherwise, apply the same padding to register arguments as we do
4384 to stack arguments. */
4385 return mips_pad_arg_upward (mode, type);
4389 /* Return nonzero when an argument must be passed by reference. */
4392 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4393 enum machine_mode mode, const_tree type,
4394 bool named ATTRIBUTE_UNUSED)
4396 if (mips_abi == ABI_EABI)
4400 /* ??? How should SCmode be handled? */
4401 if (mode == DImode || mode == DFmode
4402 || mode == DQmode || mode == UDQmode
4403 || mode == DAmode || mode == UDAmode)
4406 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4407 return size == -1 || size > UNITS_PER_WORD;
4411 /* If we have a variable-sized parameter, we have no choice. */
4412 return targetm.calls.must_pass_in_stack (mode, type);
4417 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4418 enum machine_mode mode ATTRIBUTE_UNUSED,
4419 const_tree type ATTRIBUTE_UNUSED, bool named)
4421 return mips_abi == ABI_EABI && named;
4424 /* See whether VALTYPE is a record whose fields should be returned in
4425 floating-point registers. If so, return the number of fields and
4426 list them in FIELDS (which should have two elements). Return 0
4429 For n32 & n64, a structure with one or two fields is returned in
4430 floating-point registers as long as every field has a floating-point
4434 mips_fpr_return_fields (const_tree valtype, tree *fields)
4442 if (TREE_CODE (valtype) != RECORD_TYPE)
4446 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4448 if (TREE_CODE (field) != FIELD_DECL)
4451 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
4457 fields[i++] = field;
4463 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4464 a value in the most significant part of $2/$3 if:
4466 - the target is big-endian;
4468 - the value has a structure or union type (we generalize this to
4469 cover aggregates from other languages too); and
4471 - the structure is not returned in floating-point registers. */
4474 mips_return_in_msb (const_tree valtype)
4478 return (TARGET_NEWABI
4479 && TARGET_BIG_ENDIAN
4480 && AGGREGATE_TYPE_P (valtype)
4481 && mips_fpr_return_fields (valtype, fields) == 0);
4485 /* Return true if the function return value MODE will get returned in a
4486 floating-point register. */
4489 mips_return_mode_in_fpr_p (enum machine_mode mode)
4491 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4492 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4493 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4494 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4497 /* Return a composite value in a pair of floating-point registers.
4498 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4499 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4502 For n32 & n64, $f0 always holds the first value and $f2 the second.
4503 Otherwise the values are packed together as closely as possible. */
4506 mips_return_fpr_pair (enum machine_mode mode,
4507 enum machine_mode mode1, HOST_WIDE_INT offset1,
4508 enum machine_mode mode2, HOST_WIDE_INT offset2)
4512 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4513 return gen_rtx_PARALLEL
4516 gen_rtx_EXPR_LIST (VOIDmode,
4517 gen_rtx_REG (mode1, FP_RETURN),
4519 gen_rtx_EXPR_LIST (VOIDmode,
4520 gen_rtx_REG (mode2, FP_RETURN + inc),
4521 GEN_INT (offset2))));
4526 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4527 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4528 VALTYPE is null and MODE is the mode of the return value. */
4531 mips_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
4532 enum machine_mode mode)
4539 mode = TYPE_MODE (valtype);
4540 unsignedp = TYPE_UNSIGNED (valtype);
4542 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
4543 true, we must promote the mode just as PROMOTE_MODE does. */
4544 mode = promote_mode (valtype, mode, &unsignedp, 1);
4546 /* Handle structures whose fields are returned in $f0/$f2. */
4547 switch (mips_fpr_return_fields (valtype, fields))
4550 return gen_rtx_REG (mode, FP_RETURN);
4553 return mips_return_fpr_pair (mode,
4554 TYPE_MODE (TREE_TYPE (fields[0])),
4555 int_byte_position (fields[0]),
4556 TYPE_MODE (TREE_TYPE (fields[1])),
4557 int_byte_position (fields[1]));
4560 /* If a value is passed in the most significant part of a register, see
4561 whether we have to round the mode up to a whole number of words. */
4562 if (mips_return_in_msb (valtype))
4564 HOST_WIDE_INT size = int_size_in_bytes (valtype);
4565 if (size % UNITS_PER_WORD != 0)
4567 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
4568 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
4572 /* For EABI, the class of return register depends entirely on MODE.
4573 For example, "struct { some_type x; }" and "union { some_type x; }"
4574 are returned in the same way as a bare "some_type" would be.
4575 Other ABIs only use FPRs for scalar, complex or vector types. */
4576 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
4577 return gen_rtx_REG (mode, GP_RETURN);
4582 /* Handle long doubles for n32 & n64. */
4584 return mips_return_fpr_pair (mode,
4586 DImode, GET_MODE_SIZE (mode) / 2);
4588 if (mips_return_mode_in_fpr_p (mode))
4590 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4591 return mips_return_fpr_pair (mode,
4592 GET_MODE_INNER (mode), 0,
4593 GET_MODE_INNER (mode),
4594 GET_MODE_SIZE (mode) / 2);
4596 return gen_rtx_REG (mode, FP_RETURN);
4600 return gen_rtx_REG (mode, GP_RETURN);
4603 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
4604 all BLKmode objects are returned in memory. Under the new (N32 and
4605 64-bit MIPS ABIs) small structures are returned in a register.
4606 Objects with varying size must still be returned in memory, of
4610 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
4613 return (TYPE_MODE (type) == BLKmode);
4615 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
4616 || (int_size_in_bytes (type) == -1));
4620 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4621 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4624 CUMULATIVE_ARGS local_cum;
4625 int gp_saved, fp_saved;
4627 /* The caller has advanced CUM up to, but not beyond, the last named
4628 argument. Advance a local copy of CUM past the last "real" named
4629 argument, to find out how many registers are left over. */
4632 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4634 /* Found out how many registers we need to save. */
4635 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4636 fp_saved = (EABI_FLOAT_VARARGS_P
4637 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4646 ptr = plus_constant (virtual_incoming_args_rtx,
4647 REG_PARM_STACK_SPACE (cfun->decl)
4648 - gp_saved * UNITS_PER_WORD);
4649 mem = gen_frame_mem (BLKmode, ptr);
4650 set_mem_alias_set (mem, get_varargs_alias_set ());
4652 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4657 /* We can't use move_block_from_reg, because it will use
4659 enum machine_mode mode;
4662 /* Set OFF to the offset from virtual_incoming_args_rtx of
4663 the first float register. The FP save area lies below
4664 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4665 off = -gp_saved * UNITS_PER_WORD;
4666 off &= ~(UNITS_PER_FPVALUE - 1);
4667 off -= fp_saved * UNITS_PER_FPREG;
4669 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4671 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4672 i += MAX_FPRS_PER_FMT)
4676 ptr = plus_constant (virtual_incoming_args_rtx, off);
4677 mem = gen_frame_mem (mode, ptr);
4678 set_mem_alias_set (mem, get_varargs_alias_set ());
4679 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4680 off += UNITS_PER_HWFPVALUE;
4684 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4685 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4686 + fp_saved * UNITS_PER_FPREG);
4689 /* Create the va_list data type.
4690 We keep 3 pointers, and two offsets.
4691 Two pointers are to the overflow area, which starts at the CFA.
4692 One of these is constant, for addressing into the GPR save area below it.
4693 The other is advanced up the stack through the overflow region.
4694 The third pointer is to the GPR save area. Since the FPR save area
4695 is just below it, we can address FPR slots off this pointer.
4696 We also keep two one-byte offsets, which are to be subtracted from the
4697 constant pointers to yield addresses in the GPR and FPR save areas.
4698 These are downcounted as float or non-float arguments are used,
4699 and when they get to zero, the argument must be obtained from the
4701 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4702 pointer is enough. It's started at the GPR save area, and is
4704 Note that the GPR save area is not constant size, due to optimization
4705 in the prologue. Hence, we can't use a design with two pointers
4706 and two offsets, although we could have designed this with two pointers
4707 and three offsets. */
4710 mips_build_builtin_va_list (void)
4712 if (EABI_FLOAT_VARARGS_P)
4714 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4717 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4719 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4721 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4723 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4725 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4726 unsigned_char_type_node);
4727 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4728 unsigned_char_type_node);
4729 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4730 warn on every user file. */
4731 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4732 array = build_array_type (unsigned_char_type_node,
4733 build_index_type (index));
4734 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4736 DECL_FIELD_CONTEXT (f_ovfl) = record;
4737 DECL_FIELD_CONTEXT (f_gtop) = record;
4738 DECL_FIELD_CONTEXT (f_ftop) = record;
4739 DECL_FIELD_CONTEXT (f_goff) = record;
4740 DECL_FIELD_CONTEXT (f_foff) = record;
4741 DECL_FIELD_CONTEXT (f_res) = record;
4743 TYPE_FIELDS (record) = f_ovfl;
4744 TREE_CHAIN (f_ovfl) = f_gtop;
4745 TREE_CHAIN (f_gtop) = f_ftop;
4746 TREE_CHAIN (f_ftop) = f_goff;
4747 TREE_CHAIN (f_goff) = f_foff;
4748 TREE_CHAIN (f_foff) = f_res;
4750 layout_type (record);
4753 else if (TARGET_IRIX && TARGET_IRIX6)
4754 /* On IRIX 6, this type is 'char *'. */
4755 return build_pointer_type (char_type_node);
4757 /* Otherwise, we use 'void *'. */
4758 return ptr_type_node;
4761 /* Implement va_start. */
4764 mips_va_start (tree valist, rtx nextarg)
4766 if (EABI_FLOAT_VARARGS_P)
4768 const CUMULATIVE_ARGS *cum;
4769 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4770 tree ovfl, gtop, ftop, goff, foff;
4772 int gpr_save_area_size;
4773 int fpr_save_area_size;
4776 cum = ¤t_function_args_info;
4778 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4780 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4782 f_ovfl = TYPE_FIELDS (va_list_type_node);
4783 f_gtop = TREE_CHAIN (f_ovfl);
4784 f_ftop = TREE_CHAIN (f_gtop);
4785 f_goff = TREE_CHAIN (f_ftop);
4786 f_foff = TREE_CHAIN (f_goff);
4788 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4790 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4792 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4794 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4796 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4799 /* Emit code to initialize OVFL, which points to the next varargs
4800 stack argument. CUM->STACK_WORDS gives the number of stack
4801 words used by named arguments. */
4802 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4803 if (cum->stack_words > 0)
4804 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4805 size_int (cum->stack_words * UNITS_PER_WORD));
4806 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4807 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4809 /* Emit code to initialize GTOP, the top of the GPR save area. */
4810 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4811 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4812 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4814 /* Emit code to initialize FTOP, the top of the FPR save area.
4815 This address is gpr_save_area_bytes below GTOP, rounded
4816 down to the next fp-aligned boundary. */
4817 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4818 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4819 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4821 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4822 size_int (-fpr_offset));
4823 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4824 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4826 /* Emit code to initialize GOFF, the offset from GTOP of the
4827 next GPR argument. */
4828 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4829 build_int_cst (NULL_TREE, gpr_save_area_size));
4830 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4832 /* Likewise emit code to initialize FOFF, the offset from FTOP
4833 of the next FPR argument. */
4834 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4835 build_int_cst (NULL_TREE, fpr_save_area_size));
4836 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4840 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4841 std_expand_builtin_va_start (valist, nextarg);
4845 /* Implement va_arg. */
4848 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4850 HOST_WIDE_INT size, rsize;
4854 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4857 type = build_pointer_type (type);
4859 size = int_size_in_bytes (type);
4860 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4862 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4863 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4866 /* Not a simple merged stack. */
4868 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4869 tree ovfl, top, off, align;
4870 HOST_WIDE_INT osize;
4873 f_ovfl = TYPE_FIELDS (va_list_type_node);
4874 f_gtop = TREE_CHAIN (f_ovfl);
4875 f_ftop = TREE_CHAIN (f_gtop);
4876 f_goff = TREE_CHAIN (f_ftop);
4877 f_foff = TREE_CHAIN (f_goff);
4879 /* We maintain separate pointers and offsets for floating-point
4880 and integer arguments, but we need similar code in both cases.
4883 TOP be the top of the register save area;
4884 OFF be the offset from TOP of the next register;
4885 ADDR_RTX be the address of the argument;
4886 RSIZE be the number of bytes used to store the argument
4887 when it's in the register save area;
4888 OSIZE be the number of bytes used to store it when it's
4889 in the stack overflow area; and
4890 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4892 The code we want is:
4894 1: off &= -rsize; // round down
4897 4: addr_rtx = top - off;
4902 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4903 10: addr_rtx = ovfl + PADDING;
4907 [1] and [9] can sometimes be optimized away. */
4909 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4912 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4913 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4915 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4917 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4920 /* When floating-point registers are saved to the stack,
4921 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4922 of the float's precision. */
4923 rsize = UNITS_PER_HWFPVALUE;
4925 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4926 (= PARM_BOUNDARY bits). This can be different from RSIZE
4929 (1) On 32-bit targets when TYPE is a structure such as:
4931 struct s { float f; };
4933 Such structures are passed in paired FPRs, so RSIZE
4934 will be 8 bytes. However, the structure only takes
4935 up 4 bytes of memory, so OSIZE will only be 4.
4937 (2) In combinations such as -mgp64 -msingle-float
4938 -fshort-double. Doubles passed in registers
4939 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4940 but those passed on the stack take up
4941 UNITS_PER_WORD bytes. */
4942 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4946 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4948 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4950 if (rsize > UNITS_PER_WORD)
4952 /* [1] Emit code for: off &= -rsize. */
4953 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4954 build_int_cst (NULL_TREE, -rsize));
4955 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4956 gimplify_and_add (t, pre_p);
4961 /* [2] Emit code to branch if off == 0. */
4962 t = build2 (NE_EXPR, boolean_type_node, off,
4963 build_int_cst (TREE_TYPE (off), 0));
4964 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4966 /* [5] Emit code for: off -= rsize. We do this as a form of
4967 post-increment not available to C. Also widen for the
4968 coming pointer arithmetic. */
4969 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4970 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4971 t = fold_convert (sizetype, t);
4972 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4974 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4975 the argument has RSIZE - SIZE bytes of leading padding. */
4976 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4977 if (BYTES_BIG_ENDIAN && rsize > size)
4979 u = size_int (rsize - size);
4980 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4982 COND_EXPR_THEN (addr) = t;
4984 if (osize > UNITS_PER_WORD)
4986 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4987 u = size_int (osize - 1);
4988 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4989 t = fold_convert (sizetype, t);
4990 u = size_int (-osize);
4991 t = build2 (BIT_AND_EXPR, sizetype, t, u);
4992 t = fold_convert (TREE_TYPE (ovfl), t);
4993 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4998 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4999 post-increment ovfl by osize. On big-endian machines,
5000 the argument has OSIZE - SIZE bytes of leading padding. */
5001 u = fold_convert (TREE_TYPE (ovfl),
5002 build_int_cst (NULL_TREE, osize));
5003 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5004 if (BYTES_BIG_ENDIAN && osize > size)
5006 u = size_int (osize - size);
5007 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5010 /* String [9] and [10,11] together. */
5012 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5013 COND_EXPR_ELSE (addr) = t;
5015 addr = fold_convert (build_pointer_type (type), addr);
5016 addr = build_va_arg_indirect_ref (addr);
5020 addr = build_va_arg_indirect_ref (addr);
5025 /* We keep a list of functions for which we have already built stubs
5026 in build_mips16_call_stub. */
5030 struct mips16_stub *next;
5035 static struct mips16_stub *mips16_stubs;
5037 /* Return a two-character string representing a function floating-point
5038 return mode, used to name MIPS16 function stubs. */
5041 mips16_call_stub_mode_suffix (enum machine_mode mode)
5045 else if (mode == DFmode)
5047 else if (mode == SCmode)
5049 else if (mode == DCmode)
5051 else if (mode == V2SFmode)
5057 /* Write instructions to move a 32-bit value between general register
5058 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5059 from GPREG to FPREG and 'f' to move in the opposite direction. */
5062 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5064 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5065 reg_names[gpreg], reg_names[fpreg]);
5068 /* Likewise for 64-bit values. */
5071 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5074 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5075 reg_names[gpreg], reg_names[fpreg]);
5076 else if (TARGET_FLOAT64)
5078 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5079 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5080 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5081 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5085 /* Move the least-significant word. */
5086 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5087 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5088 /* ...then the most significant word. */
5089 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5090 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5094 /* Write out code to move floating-point arguments into or out of
5095 general registers. FP_CODE is the code describing which arguments
5096 are present (see the comment above the definition of CUMULATIVE_ARGS
5097 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5100 mips_output_args_xfer (int fp_code, char direction)
5102 unsigned int gparg, fparg, f;
5103 CUMULATIVE_ARGS cum;
5105 /* This code only works for the original 32-bit ABI and the O64 ABI. */
5106 gcc_assert (TARGET_OLDABI);
5108 init_cumulative_args (&cum, NULL, NULL);
5110 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5112 enum machine_mode mode;
5113 struct mips_arg_info info;
5117 else if ((f & 3) == 2)
5122 mips_arg_info (&cum, mode, NULL, true, &info);
5123 gparg = mips_arg_regno (&info, false);
5124 fparg = mips_arg_regno (&info, true);
5127 mips_output_32bit_xfer (direction, gparg, fparg);
5129 mips_output_64bit_xfer (direction, gparg, fparg);
5131 function_arg_advance (&cum, mode, NULL, true);
5135 /* Build a mips16 function stub. This is used for functions which
5136 take arguments in the floating point registers. It is 32-bit code
5137 that moves the floating point args into the general registers, and
5138 then jumps to the 16-bit code. */
5141 build_mips16_function_stub (void)
5144 char *secname, *stubname;
5145 tree stubid, stubdecl;
5149 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5150 fnname = targetm.strip_name_encoding (fnname);
5151 secname = (char *) alloca (strlen (fnname) + 20);
5152 sprintf (secname, ".mips16.fn.%s", fnname);
5153 stubname = (char *) alloca (strlen (fnname) + 20);
5154 sprintf (stubname, "__fn_stub_%s", fnname);
5155 stubid = get_identifier (stubname);
5156 stubdecl = build_decl (FUNCTION_DECL, stubid,
5157 build_function_type (void_type_node, NULL_TREE));
5158 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5159 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5161 fprintf (asm_out_file, "\t# Stub function for %s (",
5162 current_function_name ());
5164 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
5166 fprintf (asm_out_file, "%s%s",
5167 need_comma ? ", " : "",
5168 (f & 3) == 1 ? "float" : "double");
5171 fprintf (asm_out_file, ")\n");
5173 fprintf (asm_out_file, "\t.set\tnomips16\n");
5174 switch_to_section (function_section (stubdecl));
5175 ASM_OUTPUT_ALIGN (asm_out_file,
5176 floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
5178 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
5179 within a .ent, and we cannot emit another .ent. */
5180 if (!FUNCTION_NAME_ALREADY_DECLARED)
5182 fputs ("\t.ent\t", asm_out_file);
5183 assemble_name (asm_out_file, stubname);
5184 fputs ("\n", asm_out_file);
5187 assemble_name (asm_out_file, stubname);
5188 fputs (":\n", asm_out_file);
5190 /* Load the address of the MIPS16 function into $at. Do this first so
5191 that targets with coprocessor interlocks can use an MFC1 to fill the
5193 fprintf (asm_out_file, "\t.set\tnoat\n");
5194 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
5195 assemble_name (asm_out_file, fnname);
5196 fprintf (asm_out_file, "\n");
5198 mips_output_args_xfer (current_function_args_info.fp_code, 'f');
5200 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5201 fprintf (asm_out_file, "\t.set\tat\n");
5203 if (!FUNCTION_NAME_ALREADY_DECLARED)
5205 fputs ("\t.end\t", asm_out_file);
5206 assemble_name (asm_out_file, stubname);
5207 fputs ("\n", asm_out_file);
5210 switch_to_section (function_section (current_function_decl));
5213 /* The current function is a MIPS16 function that returns a value in an FPR.
5214 Copy the return value from its soft-float to its hard-float location.
5215 libgcc2 has special non-MIPS16 helper functions for each case. */
5218 mips16_copy_fpr_return_value (void)
5220 rtx fn, insn, arg, call;
5221 tree id, return_type;
5222 enum machine_mode return_mode;
5224 return_type = DECL_RESULT (current_function_decl);
5225 return_mode = DECL_MODE (return_type);
5227 id = get_identifier (ACONCAT (("__mips16_ret_",
5228 mips16_call_stub_mode_suffix (return_mode),
5230 fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5231 arg = gen_rtx_REG (return_mode, GP_RETURN);
5232 call = gen_call_value_internal (arg, fn, const0_rtx);
5233 insn = emit_call_insn (call);
5234 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), arg);
5237 /* Build a call stub for a mips16 call. A stub is needed if we are
5238 passing any floating point values which should go into the floating
5239 point registers. If we are, and the call turns out to be to a
5240 32-bit function, the stub will be used to move the values into the
5241 floating point registers before calling the 32-bit function. The
5242 linker will magically adjust the function call to either the 16-bit
5243 function or the 32-bit stub, depending upon where the function call
5244 is actually defined.
5246 Similarly, we need a stub if the return value might come back in a
5247 floating point register.
5249 RETVAL is the location of the return value, or null if this is
5250 a call rather than a call_value. FN is the address of the
5251 function and ARG_SIZE is the size of the arguments. FP_CODE
5252 is the code built by function_arg. This function returns a nonzero
5253 value if it builds the call instruction itself. */
5256 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
5260 char *secname, *stubname;
5261 struct mips16_stub *l;
5262 tree stubid, stubdecl;
5267 /* We don't need to do anything if we aren't in mips16 mode, or if
5268 we were invoked with the -msoft-float option. */
5269 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5272 /* Figure out whether the value might come back in a floating point
5275 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
5277 /* We don't need to do anything if there were no floating point
5278 arguments and the value will not be returned in a floating point
5280 if (fp_code == 0 && ! fpret)
5283 /* We don't need to do anything if this is a call to a special
5284 mips16 support function. */
5285 if (GET_CODE (fn) == SYMBOL_REF
5286 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
5289 /* This code will only work for o32 and o64 abis. The other ABI's
5290 require more sophisticated support. */
5291 gcc_assert (TARGET_OLDABI);
5293 /* If we're calling via a function pointer, then we must always call
5294 via a stub. There are magic stubs provided in libgcc.a for each
5295 of the required cases. Each of them expects the function address
5296 to arrive in register $2. */
5298 if (GET_CODE (fn) != SYMBOL_REF)
5304 /* ??? If this code is modified to support other ABI's, we need
5305 to handle PARALLEL return values here. */
5308 sprintf (buf, "__mips16_call_stub_%s_%d",
5309 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5312 sprintf (buf, "__mips16_call_stub_%d",
5315 id = get_identifier (buf);
5316 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
5318 mips_emit_move (gen_rtx_REG (Pmode, 2), fn);
5320 if (retval == NULL_RTX)
5321 insn = gen_call_internal (stub_fn, arg_size);
5323 insn = gen_call_value_internal (retval, stub_fn, arg_size);
5324 insn = emit_call_insn (insn);
5326 /* Put the register usage information on the CALL. */
5327 CALL_INSN_FUNCTION_USAGE (insn) =
5328 gen_rtx_EXPR_LIST (VOIDmode,
5329 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
5330 CALL_INSN_FUNCTION_USAGE (insn));
5332 /* If we are handling a floating point return value, we need to
5333 save $18 in the function prologue. Putting a note on the
5334 call will mean that df_regs_ever_live_p ($18) will be true if the
5335 call is not eliminated, and we can check that in the prologue
5338 CALL_INSN_FUNCTION_USAGE (insn) =
5339 gen_rtx_EXPR_LIST (VOIDmode,
5340 gen_rtx_USE (VOIDmode,
5341 gen_rtx_REG (word_mode, 18)),
5342 CALL_INSN_FUNCTION_USAGE (insn));
5344 /* Return 1 to tell the caller that we've generated the call
5349 /* We know the function we are going to call. If we have already
5350 built a stub, we don't need to do anything further. */
5352 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5353 for (l = mips16_stubs; l != NULL; l = l->next)
5354 if (strcmp (l->name, fnname) == 0)
5359 /* Build a special purpose stub. When the linker sees a
5360 function call in mips16 code, it will check where the target
5361 is defined. If the target is a 32-bit call, the linker will
5362 search for the section defined here. It can tell which
5363 symbol this section is associated with by looking at the
5364 relocation information (the name is unreliable, since this
5365 might be a static function). If such a section is found, the
5366 linker will redirect the call to the start of the magic
5369 If the function does not return a floating point value, the
5370 special stub section is named
5373 If the function does return a floating point value, the stub
5375 .mips16.call.fp.FNNAME
5378 secname = (char *) alloca (strlen (fnname) + 40);
5379 sprintf (secname, ".mips16.call.%s%s",
5382 stubname = (char *) alloca (strlen (fnname) + 20);
5383 sprintf (stubname, "__call_stub_%s%s",
5386 stubid = get_identifier (stubname);
5387 stubdecl = build_decl (FUNCTION_DECL, stubid,
5388 build_function_type (void_type_node, NULL_TREE));
5389 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5390 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
5392 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
5394 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
5398 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5400 fprintf (asm_out_file, "%s%s",
5401 need_comma ? ", " : "",
5402 (f & 3) == 1 ? "float" : "double");
5405 fprintf (asm_out_file, ")\n");
5407 fprintf (asm_out_file, "\t.set\tnomips16\n");
5408 assemble_start_function (stubdecl, stubname);
5410 if (!FUNCTION_NAME_ALREADY_DECLARED)
5412 fputs ("\t.ent\t", asm_out_file);
5413 assemble_name (asm_out_file, stubname);
5414 fputs ("\n", asm_out_file);
5416 assemble_name (asm_out_file, stubname);
5417 fputs (":\n", asm_out_file);
5420 /* We build the stub code by hand. That's the only way we can
5421 do it, since we can't generate 32-bit code during a 16-bit
5426 /* Load the address of the MIPS16 function into $at. Do this
5427 first so that targets with coprocessor interlocks can use
5428 an MFC1 to fill the delay slot. */
5429 fprintf (asm_out_file, "\t.set\tnoat\n");
5430 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
5434 mips_output_args_xfer (fp_code, 't');
5438 /* Jump to the previously-loaded address. */
5439 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
5440 fprintf (asm_out_file, "\t.set\tat\n");
5444 fprintf (asm_out_file, "\tmove\t%s,%s\n",
5445 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
5446 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
5447 switch (GET_MODE (retval))
5450 mips_output_32bit_xfer ('f', GP_RETURN + 1,
5451 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5454 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5455 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
5457 /* On 64-bit targets, complex floats are returned in
5458 a single GPR, such that "sd" on a suitably-aligned
5459 target would store the value correctly. */
5460 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
5461 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
5462 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
5463 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
5464 reg_names[GP_RETURN],
5465 reg_names[GP_RETURN],
5466 reg_names[GP_RETURN + 1]);
5471 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
5472 FP_REG_FIRST + MAX_FPRS_PER_FMT);
5476 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
5482 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
5485 #ifdef ASM_DECLARE_FUNCTION_SIZE
5486 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
5489 if (!FUNCTION_NAME_ALREADY_DECLARED)
5491 fputs ("\t.end\t", asm_out_file);
5492 assemble_name (asm_out_file, stubname);
5493 fputs ("\n", asm_out_file);
5496 /* Record this stub. */
5497 l = (struct mips16_stub *) xmalloc (sizeof *l);
5498 l->name = xstrdup (fnname);
5500 l->next = mips16_stubs;
5504 /* If we expect a floating point return value, but we've built a
5505 stub which does not expect one, then we're in trouble. We can't
5506 use the existing stub, because it won't handle the floating point
5507 value. We can't build a new stub, because the linker won't know
5508 which stub to use for the various calls in this object file.
5509 Fortunately, this case is illegal, since it means that a function
5510 was declared in two different ways in a single compilation. */
5511 if (fpret && ! l->fpret)
5512 error ("cannot handle inconsistent calls to %qs", fnname);
5514 if (retval == NULL_RTX)
5515 insn = gen_call_internal_direct (fn, arg_size);
5517 insn = gen_call_value_internal_direct (retval, fn, arg_size);
5518 insn = emit_call_insn (insn);
5520 /* If we are calling a stub which handles a floating point return
5521 value, we need to arrange to save $18 in the prologue. We do
5522 this by marking the function call as using the register. The
5523 prologue will later see that it is used, and emit code to save
5526 CALL_INSN_FUNCTION_USAGE (insn) =
5527 gen_rtx_EXPR_LIST (VOIDmode,
5528 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
5529 CALL_INSN_FUNCTION_USAGE (insn));
5531 /* Return 1 to tell the caller that we've generated the call
5536 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5539 mips_ok_for_lazy_binding_p (rtx x)
5541 return (TARGET_USE_GOT
5542 && GET_CODE (x) == SYMBOL_REF
5543 && !mips_symbol_binds_local_p (x));
5546 /* Load function address ADDR into register DEST. SIBCALL_P is true
5547 if the address is needed for a sibling call. Return true if we
5548 used an explicit lazy-binding sequence. */
5551 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
5553 /* If we're generating PIC, and this call is to a global function,
5554 try to allow its address to be resolved lazily. This isn't
5555 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
5556 to the stub would be our caller's gp, not ours. */
5557 if (TARGET_EXPLICIT_RELOCS
5558 && !(sibcall_p && TARGET_CALL_SAVED_GP)
5559 && mips_ok_for_lazy_binding_p (addr))
5561 rtx high, lo_sum_symbol;
5563 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
5564 addr, SYMBOL_GOTOFF_CALL);
5565 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
5566 if (Pmode == SImode)
5567 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
5569 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
5574 mips_emit_move (dest, addr);
5580 /* Expand a call or call_value instruction. RESULT is where the
5581 result will go (null for calls), ADDR is the address of the
5582 function, ARGS_SIZE is the size of the arguments and AUX is
5583 the value passed to us by mips_function_arg. SIBCALL_P is true
5584 if we are expanding a sibling call, false if we're expanding
5588 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
5590 rtx orig_addr, pattern, insn;
5595 if (!call_insn_operand (addr, VOIDmode))
5597 addr = gen_reg_rtx (Pmode);
5598 lazy_p = mips_load_call_address (addr, orig_addr, sibcall_p);
5602 && TARGET_HARD_FLOAT_ABI
5603 && build_mips16_call_stub (result, addr, args_size,
5604 aux == 0 ? 0 : (int) GET_MODE (aux)))
5608 pattern = (sibcall_p
5609 ? gen_sibcall_internal (addr, args_size)
5610 : gen_call_internal (addr, args_size));
5611 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
5615 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
5616 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
5619 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
5620 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
5623 pattern = (sibcall_p
5624 ? gen_sibcall_value_internal (result, addr, args_size)
5625 : gen_call_value_internal (result, addr, args_size));
5627 insn = emit_call_insn (pattern);
5629 /* Lazy-binding stubs require $gp to be valid on entry. We also pretend
5630 that they use FAKE_CALL_REGNO; see the load_call<mode> patterns for
5634 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
5635 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
5636 gen_rtx_REG (Pmode, FAKE_CALL_REGNO));
5641 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
5644 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
5646 if (!TARGET_SIBCALLS)
5649 /* We can't do a sibcall if the called function is a MIPS16 function
5650 because there is no direct "jx" instruction equivalent to "jalx" to
5651 switch the ISA mode. */
5652 if (mips_use_mips16_mode_p (decl))
5655 /* ...and when -minterlink-mips16 is in effect, assume that external
5656 functions could be MIPS16 ones unless an attribute explicitly
5657 tells us otherwise. We only care about cases where the sibling
5658 and normal calls would both be direct. */
5659 if (TARGET_INTERLINK_MIPS16
5661 && DECL_EXTERNAL (decl)
5662 && !mips_nomips16_decl_p (decl)
5663 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
5670 /* Emit code to move general operand SRC into condition-code
5671 register DEST. SCRATCH is a scratch TFmode float register.
5678 where FP1 and FP2 are single-precision float registers
5679 taken from SCRATCH. */
5682 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
5686 /* Change the source to SFmode. */
5688 src = adjust_address (src, SFmode, 0);
5689 else if (REG_P (src) || GET_CODE (src) == SUBREG)
5690 src = gen_rtx_REG (SFmode, true_regnum (src));
5692 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
5693 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
5695 mips_emit_move (copy_rtx (fp1), src);
5696 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
5697 emit_insn (gen_slt_sf (dest, fp2, fp1));
5700 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
5701 Assume that the areas do not overlap. */
5704 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
5706 HOST_WIDE_INT offset, delta;
5707 unsigned HOST_WIDE_INT bits;
5709 enum machine_mode mode;
5712 /* Work out how many bits to move at a time. If both operands have
5713 half-word alignment, it is usually better to move in half words.
5714 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
5715 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
5716 Otherwise move word-sized chunks. */
5717 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
5718 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
5719 bits = BITS_PER_WORD / 2;
5721 bits = BITS_PER_WORD;
5723 mode = mode_for_size (bits, MODE_INT, 0);
5724 delta = bits / BITS_PER_UNIT;
5726 /* Allocate a buffer for the temporary registers. */
5727 regs = alloca (sizeof (rtx) * length / delta);
5729 /* Load as many BITS-sized chunks as possible. Use a normal load if
5730 the source has enough alignment, otherwise use left/right pairs. */
5731 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5733 regs[i] = gen_reg_rtx (mode);
5734 if (MEM_ALIGN (src) >= bits)
5735 mips_emit_move (regs[i], adjust_address (src, mode, offset));
5738 rtx part = adjust_address (src, BLKmode, offset);
5739 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
5744 /* Copy the chunks to the destination. */
5745 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
5746 if (MEM_ALIGN (dest) >= bits)
5747 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
5750 rtx part = adjust_address (dest, BLKmode, offset);
5751 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
5755 /* Mop up any left-over bytes. */
5756 if (offset < length)
5758 src = adjust_address (src, BLKmode, offset);
5759 dest = adjust_address (dest, BLKmode, offset);
5760 move_by_pieces (dest, src, length - offset,
5761 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
5765 #define MAX_MOVE_REGS 4
5766 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
5769 /* Helper function for doing a loop-based block operation on memory
5770 reference MEM. Each iteration of the loop will operate on LENGTH
5773 Create a new base register for use within the loop and point it to
5774 the start of MEM. Create a new memory reference that uses this
5775 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
5778 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
5779 rtx *loop_reg, rtx *loop_mem)
5781 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
5783 /* Although the new mem does not refer to a known location,
5784 it does keep up to LENGTH bytes of alignment. */
5785 *loop_mem = change_address (mem, BLKmode, *loop_reg);
5786 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
5790 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
5791 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
5792 memory regions do not overlap. */
5795 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
5797 rtx label, src_reg, dest_reg, final_src;
5798 HOST_WIDE_INT leftover;
5800 leftover = length % MAX_MOVE_BYTES;
5803 /* Create registers and memory references for use within the loop. */
5804 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
5805 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
5807 /* Calculate the value that SRC_REG should have after the last iteration
5809 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
5812 /* Emit the start of the loop. */
5813 label = gen_label_rtx ();
5816 /* Emit the loop body. */
5817 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
5819 /* Move on to the next block. */
5820 mips_emit_move (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
5821 mips_emit_move (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
5823 /* Emit the loop condition. */
5824 if (Pmode == DImode)
5825 emit_insn (gen_cmpdi (src_reg, final_src));
5827 emit_insn (gen_cmpsi (src_reg, final_src));
5828 emit_jump_insn (gen_bne (label));
5830 /* Mop up any left-over bytes. */
5832 mips_block_move_straight (dest, src, leftover);
5835 /* Expand a movmemsi instruction. */
5838 mips_expand_block_move (rtx dest, rtx src, rtx length)
5840 if (GET_CODE (length) == CONST_INT)
5842 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
5844 mips_block_move_straight (dest, src, INTVAL (length));
5849 mips_block_move_loop (dest, src, INTVAL (length));
5857 /* Expand a loop of synci insns for the address range [BEGIN, END). */
5860 mips_expand_synci_loop (rtx begin, rtx end)
5862 rtx inc, label, cmp, cmp_result;
5864 /* Load INC with the cache line size (rdhwr INC,$1). */
5865 inc = gen_reg_rtx (SImode);
5866 emit_insn (gen_rdhwr (inc, const1_rtx));
5868 /* Loop back to here. */
5869 label = gen_label_rtx ();
5872 emit_insn (gen_synci (begin));
5874 cmp = gen_reg_rtx (Pmode);
5875 mips_emit_binary (GTU, cmp, begin, end);
5877 mips_emit_binary (PLUS, begin, begin, inc);
5879 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
5880 emit_jump_insn (gen_condjump (cmp_result, label));
5883 /* Return true if it is possible to use left/right accesses for a
5884 bitfield of WIDTH bits starting BITPOS bits into *OP. When
5885 returning true, update *OP, *LEFT and *RIGHT as follows:
5887 *OP is a BLKmode reference to the whole field.
5889 *LEFT is a QImode reference to the first byte if big endian or
5890 the last byte if little endian. This address can be used in the
5891 left-side instructions (lwl, swl, ldl, sdl).
5893 *RIGHT is a QImode reference to the opposite end of the field and
5894 can be used in the patterning right-side instruction. */
5897 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
5898 rtx *left, rtx *right)
5902 /* Check that the operand really is a MEM. Not all the extv and
5903 extzv predicates are checked. */
5907 /* Check that the size is valid. */
5908 if (width != 32 && (!TARGET_64BIT || width != 64))
5911 /* We can only access byte-aligned values. Since we are always passed
5912 a reference to the first byte of the field, it is not necessary to
5913 do anything with BITPOS after this check. */
5914 if (bitpos % BITS_PER_UNIT != 0)
5917 /* Reject aligned bitfields: we want to use a normal load or store
5918 instead of a left/right pair. */
5919 if (MEM_ALIGN (*op) >= width)
5922 /* Adjust *OP to refer to the whole field. This also has the effect
5923 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
5924 *op = adjust_address (*op, BLKmode, 0);
5925 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
5927 /* Get references to both ends of the field. We deliberately don't
5928 use the original QImode *OP for FIRST since the new BLKmode one
5929 might have a simpler address. */
5930 first = adjust_address (*op, QImode, 0);
5931 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
5933 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
5934 be the upper word and RIGHT the lower word. */
5935 if (TARGET_BIG_ENDIAN)
5936 *left = first, *right = last;
5938 *left = last, *right = first;
5944 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
5945 Return true on success. We only handle cases where zero_extract is
5946 equivalent to sign_extract. */
5949 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
5951 rtx left, right, temp;
5953 /* If TARGET_64BIT, the destination of a 32-bit load will be a
5954 paradoxical word_mode subreg. This is the only case in which
5955 we allow the destination to be larger than the source. */
5956 if (GET_CODE (dest) == SUBREG
5957 && GET_MODE (dest) == DImode
5958 && SUBREG_BYTE (dest) == 0
5959 && GET_MODE (SUBREG_REG (dest)) == SImode)
5960 dest = SUBREG_REG (dest);
5962 /* After the above adjustment, the destination must be the same
5963 width as the source. */
5964 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
5967 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
5970 temp = gen_reg_rtx (GET_MODE (dest));
5971 if (GET_MODE (dest) == DImode)
5973 emit_insn (gen_mov_ldl (temp, src, left));
5974 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
5978 emit_insn (gen_mov_lwl (temp, src, left));
5979 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
5985 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
5989 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
5992 enum machine_mode mode;
5994 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
5997 mode = mode_for_size (width, MODE_INT, 0);
5998 src = gen_lowpart (mode, src);
6002 emit_insn (gen_mov_sdl (dest, src, left));
6003 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6007 emit_insn (gen_mov_swl (dest, src, left));
6008 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6013 /* Return true if X is a MEM with the same size as MODE. */
6016 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6023 size = MEM_SIZE (x);
6024 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6027 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
6028 source of an "ext" instruction or the destination of an "ins"
6029 instruction. OP must be a register operand and the following
6030 conditions must hold:
6032 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
6033 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
6034 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
6036 Also reject lengths equal to a word as they are better handled
6037 by the move patterns. */
6040 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
6042 HOST_WIDE_INT len, pos;
6044 if (!ISA_HAS_EXT_INS
6045 || !register_operand (op, VOIDmode)
6046 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6049 len = INTVAL (size);
6050 pos = INTVAL (position);
6052 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
6053 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
6059 /* Initialize mips_split_addresses from the associated command-line
6062 mips_split_addresses is a half-way house between explicit
6063 relocations and the traditional assembler macros. It can
6064 split absolute 32-bit symbolic constants into a high/lo_sum
6065 pair but uses macros for other sorts of access.
6067 Like explicit relocation support for REL targets, it relies
6068 on GNU extensions in the assembler and the linker.
6070 Although this code should work for -O0, it has traditionally
6071 been treated as an optimization. */
6074 mips_init_split_addresses (void)
6076 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
6077 && optimize && !flag_pic
6078 && !ABI_HAS_64BIT_SYMBOLS)
6079 mips_split_addresses = 1;
6081 mips_split_addresses = 0;
6084 /* (Re-)Initialize information about relocs. */
6087 mips_init_relocs (void)
6089 memset (mips_split_p, '\0', sizeof (mips_split_p));
6090 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6091 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6093 if (ABI_HAS_64BIT_SYMBOLS)
6095 if (TARGET_EXPLICIT_RELOCS)
6097 mips_split_p[SYMBOL_64_HIGH] = true;
6098 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6099 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6101 mips_split_p[SYMBOL_64_MID] = true;
6102 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6103 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6105 mips_split_p[SYMBOL_64_LOW] = true;
6106 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6107 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6109 mips_split_p[SYMBOL_ABSOLUTE] = true;
6110 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6115 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses || TARGET_MIPS16)
6117 mips_split_p[SYMBOL_ABSOLUTE] = true;
6118 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6119 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6121 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6127 /* The high part is provided by a pseudo copy of $gp. */
6128 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6129 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6132 if (TARGET_EXPLICIT_RELOCS)
6134 /* Small data constants are kept whole until after reload,
6135 then lowered by mips_rewrite_small_data. */
6136 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6138 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6141 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6142 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6146 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6147 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6152 /* The HIGH and LO_SUM are matched by special .md patterns. */
6153 mips_split_p[SYMBOL_GOT_DISP] = true;
6155 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6156 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6157 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6159 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6160 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6161 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6166 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6168 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6169 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6175 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6176 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6177 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6180 /* Thread-local relocation operators. */
6181 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6182 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6183 mips_split_p[SYMBOL_DTPREL] = 1;
6184 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6185 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6186 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6187 mips_split_p[SYMBOL_TPREL] = 1;
6188 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6189 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6191 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6194 /* If OP is an UNSPEC address, return the address to which it refers,
6195 otherwise return OP itself. */
6198 mips_strip_unspec_address (rtx op)
6202 split_const (op, &base, &offset);
6203 if (UNSPEC_ADDRESS_P (base))
6204 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6208 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6209 in context CONTEXT. RELOCS is the array of relocations to use. */
6212 print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6213 const char **relocs)
6215 enum mips_symbol_type symbol_type;
6218 symbol_type = mips_classify_symbolic_expression (op, context);
6219 if (relocs[symbol_type] == 0)
6220 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
6222 fputs (relocs[symbol_type], file);
6223 output_addr_const (file, mips_strip_unspec_address (op));
6224 for (p = relocs[symbol_type]; *p != 0; p++)
6229 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6230 The punctuation characters are:
6232 '(' Start a nested ".set noreorder" block.
6233 ')' End a nested ".set noreorder" block.
6234 '[' Start a nested ".set noat" block.
6235 ']' End a nested ".set noat" block.
6236 '<' Start a nested ".set nomacro" block.
6237 '>' End a nested ".set nomacro" block.
6238 '*' Behave like %(%< if generating a delayed-branch sequence.
6239 '#' Print a nop if in a ".set noreorder" block.
6240 '/' Like '#', but do nothing within a delayed-branch sequence.
6241 '?' Print "l" if mips_branch_likely is true
6242 '.' Print the name of the register with a hard-wired zero (zero or $0).
6243 '@' Print the name of the assembler temporary register (at or $1).
6244 '^' Print the name of the pic call-through register (t9 or $25).
6245 '+' Print the name of the gp register (usually gp or $28).
6246 '$' Print the name of the stack pointer register (sp or $29).
6247 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
6248 '-' Print ".set pop" under the same conditions for '|'.
6250 See also mips_init_print_operand_pucnt. */
6253 mips_print_operand_punctuation (FILE *file, int ch)
6258 if (set_noreorder++ == 0)
6259 fputs (".set\tnoreorder\n\t", file);
6263 gcc_assert (set_noreorder > 0);
6264 if (--set_noreorder == 0)
6265 fputs ("\n\t.set\treorder", file);
6269 if (set_noat++ == 0)
6270 fputs (".set\tnoat\n\t", file);
6274 gcc_assert (set_noat > 0);
6275 if (--set_noat == 0)
6276 fputs ("\n\t.set\tat", file);
6280 if (set_nomacro++ == 0)
6281 fputs (".set\tnomacro\n\t", file);
6285 gcc_assert (set_nomacro > 0);
6286 if (--set_nomacro == 0)
6287 fputs ("\n\t.set\tmacro", file);
6291 if (final_sequence != 0)
6293 mips_print_operand_punctuation (file, '(');
6294 mips_print_operand_punctuation (file, '<');
6299 if (set_noreorder != 0)
6300 fputs ("\n\tnop", file);
6304 /* Print an extra newline so that the delayed insn is separated
6305 from the following ones. This looks neater and is consistent
6306 with non-nop delayed sequences. */
6307 if (set_noreorder != 0 && final_sequence == 0)
6308 fputs ("\n\tnop\n", file);
6312 if (mips_branch_likely)
6317 fputs (reg_names[GP_REG_FIRST + 0], file);
6321 fputs (reg_names[GP_REG_FIRST + 1], file);
6325 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
6329 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
6333 fputs (reg_names[STACK_POINTER_REGNUM], file);
6338 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
6343 fputs ("\n\t.set\tpop", file);
6352 /* Initialize mips_print_operand_punct. */
6355 mips_init_print_operand_punct (void)
6359 for (p = "()[]<>*#/?.@^+$|-"; *p; p++)
6360 mips_print_operand_punct[(unsigned char) *p] = true;
6363 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
6364 associated with condition CODE. Print the condition part of the
6368 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
6382 /* Conveniently, the MIPS names for these conditions are the same
6383 as their RTL equivalents. */
6384 fputs (GET_RTX_NAME (code), file);
6388 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6393 /* Likewise floating-point branches. */
6396 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
6401 fputs ("c1f", file);
6405 fputs ("c1t", file);
6409 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
6414 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
6416 'X' Print CONST_INT OP in hexadecimal format.
6417 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
6418 'd' Print CONST_INT OP in decimal.
6419 'h' Print the high-part relocation associated with OP, after stripping
6421 'R' Print the low-part relocation associated with OP.
6422 'C' Print the integer branch condition for comparison OP.
6423 'N' Print the inverse of the integer branch condition for comparison OP.
6424 'F' Print the FPU branch condition for comparison OP.
6425 'W' Print the inverse of the FPU branch condition for comparison OP.
6426 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
6427 'z' for (eq:?I ...), 'n' for (ne:?I ...).
6428 't' Like 'T', but with the EQ/NE cases reversed
6429 'Y' Print mips_fp_conditions[INTVAL (OP)]
6430 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
6431 'q' Print a DSP accumulator register.
6432 'D' Print the second part of a double-word register or memory operand.
6433 'L' Print the low-order register in a double-word register operand.
6434 'M' Print high-order register in a double-word register operand.
6435 'z' Print $0 if OP is zero, otherwise print OP normally. */
6438 print_operand (FILE *file, rtx op, int letter)
6442 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
6444 mips_print_operand_punctuation (file, letter);
6449 code = GET_CODE (op);
6454 if (GET_CODE (op) == CONST_INT)
6455 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
6457 output_operand_lossage ("invalid use of '%%%c'", letter);
6461 if (GET_CODE (op) == CONST_INT)
6462 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
6464 output_operand_lossage ("invalid use of '%%%c'", letter);
6468 if (GET_CODE (op) == CONST_INT)
6469 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
6471 output_operand_lossage ("invalid use of '%%%c'", letter);
6477 print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
6481 print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
6485 mips_print_int_branch_condition (file, code, letter);
6489 mips_print_int_branch_condition (file, reverse_condition (code), letter);
6493 mips_print_float_branch_condition (file, code, letter);
6497 mips_print_float_branch_condition (file, reverse_condition (code),
6504 int truth = (code == NE) == (letter == 'T');
6505 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
6510 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
6511 fputs (mips_fp_conditions[UINTVAL (op)], file);
6513 output_operand_lossage ("'%%%c' is not a valid operand prefix",
6520 print_operand (file, op, 0);
6526 if (code == REG && MD_REG_P (REGNO (op)))
6527 fprintf (file, "$ac0");
6528 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
6529 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
6531 output_operand_lossage ("invalid use of '%%%c'", letter);
6539 unsigned int regno = REGNO (op);
6540 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
6541 || (letter == 'L' && TARGET_BIG_ENDIAN)
6544 fprintf (file, "%s", reg_names[regno]);
6550 output_address (plus_constant (XEXP (op, 0), 4));
6552 output_address (XEXP (op, 0));
6556 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
6557 fputs (reg_names[GP_REG_FIRST], file);
6558 else if (CONST_GP_P (op))
6559 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
6561 output_addr_const (file, mips_strip_unspec_address (op));
6567 /* Output address operand X to FILE. */
6570 print_operand_address (FILE *file, rtx x)
6572 struct mips_address_info addr;
6574 if (mips_classify_address (&addr, x, word_mode, true))
6578 print_operand (file, addr.offset, 0);
6579 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6582 case ADDRESS_LO_SUM:
6583 print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
6585 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6588 case ADDRESS_CONST_INT:
6589 output_addr_const (file, x);
6590 fprintf (file, "(%s)", reg_names[0]);
6593 case ADDRESS_SYMBOLIC:
6594 output_addr_const (file, mips_strip_unspec_address (x));
6600 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
6601 FIRST is true if this is the first time handling this decl. */
6604 mips_encode_section_info (tree decl, rtx rtl, int first)
6606 default_encode_section_info (decl, rtl, first);
6608 if (TREE_CODE (decl) == FUNCTION_DECL)
6610 rtx symbol = XEXP (rtl, 0);
6611 tree type = TREE_TYPE (decl);
6613 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
6614 || mips_far_type_p (type))
6615 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
6619 /* Implement TARGET_SELECT_RTX_SECTION. */
6622 mips_select_rtx_section (enum machine_mode mode, rtx x,
6623 unsigned HOST_WIDE_INT align)
6625 /* ??? Consider using mergeable small data sections. */
6626 if (mips_rtx_constant_in_small_data_p (mode))
6627 return get_named_section (NULL, ".sdata", 0);
6629 return default_elf_select_rtx_section (mode, x, align);
6632 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6634 The complication here is that, with the combination TARGET_ABICALLS
6635 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6636 therefore not be included in the read-only part of a DSO. Handle such
6637 cases by selecting a normal data section instead of a read-only one.
6638 The logic apes that in default_function_rodata_section. */
6641 mips_function_rodata_section (tree decl)
6643 if (!TARGET_ABICALLS || TARGET_GPWORD)
6644 return default_function_rodata_section (decl);
6646 if (decl && DECL_SECTION_NAME (decl))
6648 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6649 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6651 char *rname = ASTRDUP (name);
6653 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6655 else if (flag_function_sections && flag_data_sections
6656 && strncmp (name, ".text.", 6) == 0)
6658 char *rname = ASTRDUP (name);
6659 memcpy (rname + 1, "data", 4);
6660 return get_section (rname, SECTION_WRITE, decl);
6663 return data_section;
6666 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
6667 locally-defined objects go in a small data section. It also controls
6668 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
6669 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
6672 mips_in_small_data_p (const_tree decl)
6676 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6679 /* We don't yet generate small-data references for -mabicalls or
6680 VxWorks RTP code. See the related -G handling in override_options. */
6681 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
6684 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6688 /* Reject anything that isn't in a known small-data section. */
6689 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6690 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6693 /* If a symbol is defined externally, the assembler will use the
6694 usual -G rules when deciding how to implement macros. */
6695 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
6698 else if (TARGET_EMBEDDED_DATA)
6700 /* Don't put constants into the small data section: we want them
6701 to be in ROM rather than RAM. */
6702 if (TREE_CODE (decl) != VAR_DECL)
6705 if (TREE_READONLY (decl)
6706 && !TREE_SIDE_EFFECTS (decl)
6707 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6711 /* Enforce -mlocal-sdata. */
6712 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
6715 /* Enforce -mextern-sdata. */
6716 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
6718 if (DECL_EXTERNAL (decl))
6720 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
6724 size = int_size_in_bytes (TREE_TYPE (decl));
6725 return (size > 0 && size <= mips_section_threshold);
6728 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
6729 anchors for small data: the GP register acts as an anchor in that
6730 case. We also don't want to use them for PC-relative accesses,
6731 where the PC acts as an anchor. */
6734 mips_use_anchors_for_symbol_p (const_rtx symbol)
6736 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
6738 case SYMBOL_PC_RELATIVE:
6739 case SYMBOL_GP_RELATIVE:
6743 return default_use_anchors_for_symbol_p (symbol);
6747 /* The MIPS debug format wants all automatic variables and arguments
6748 to be in terms of the virtual frame pointer (stack pointer before
6749 any adjustment in the function), while the MIPS 3.0 linker wants
6750 the frame pointer to be the stack pointer after the initial
6751 adjustment. So, we do the adjustment here. The arg pointer (which
6752 is eliminated) points to the virtual frame pointer, while the frame
6753 pointer (which may be eliminated) points to the stack pointer after
6754 the initial adjustments. */
6757 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
6759 rtx offset2 = const0_rtx;
6760 rtx reg = eliminate_constant_term (addr, &offset2);
6763 offset = INTVAL (offset2);
6765 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
6766 || reg == hard_frame_pointer_rtx)
6768 offset -= cfun->machine->frame.total_size;
6769 if (reg == hard_frame_pointer_rtx)
6770 offset += cfun->machine->frame.hard_frame_pointer_offset;
6773 /* sdbout_parms does not want this to crash for unrecognized cases. */
6775 else if (reg != arg_pointer_rtx)
6776 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
6783 /* When using assembler macros, keep track of all of small-data externs
6784 so that mips_file_end can emit the appropriate declarations for them.
6786 In most cases it would be safe (though pointless) to emit .externs
6787 for other symbols too. One exception is when an object is within
6788 the -G limit but declared by the user to be in a section other
6789 than .sbss or .sdata. */
6792 mips_output_external (FILE *file, tree decl, const char *name)
6794 default_elf_asm_output_external (file, decl, name);
6796 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6797 set in order to avoid putting out names that are never really
6799 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6801 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6803 fputs ("\t.extern\t", file);
6804 assemble_name (file, name);
6805 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6806 int_size_in_bytes (TREE_TYPE (decl)));
6808 else if (TARGET_IRIX
6809 && mips_abi == ABI_32
6810 && TREE_CODE (decl) == FUNCTION_DECL)
6812 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6813 `.global name .text' directive for every used but
6814 undefined function. If we don't, the linker may perform
6815 an optimization (skipping over the insns that set $gp)
6816 when it is unsafe. */
6817 fputs ("\t.globl ", file);
6818 assemble_name (file, name);
6819 fputs (" .text\n", file);
6824 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6825 put out a MIPS ECOFF file and a stab. */
6828 mips_output_filename (FILE *stream, const char *name)
6831 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6833 if (write_symbols == DWARF2_DEBUG)
6835 else if (mips_output_filename_first_time)
6837 mips_output_filename_first_time = 0;
6838 num_source_filenames += 1;
6839 current_function_file = name;
6840 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6841 output_quoted_string (stream, name);
6842 putc ('\n', stream);
6845 /* If we are emitting stabs, let dbxout.c handle this (except for
6846 the mips_output_filename_first_time case). */
6847 else if (write_symbols == DBX_DEBUG)
6850 else if (name != current_function_file
6851 && strcmp (name, current_function_file) != 0)
6853 num_source_filenames += 1;
6854 current_function_file = name;
6855 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6856 output_quoted_string (stream, name);
6857 putc ('\n', stream);
6861 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
6864 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
6869 fputs ("\t.dtprelword\t", file);
6873 fputs ("\t.dtpreldword\t", file);
6879 output_addr_const (file, x);
6880 fputs ("+0x8000", file);
6883 /* Implement TARGET_DWARF_REGISTER_SPAN. */
6886 mips_dwarf_register_span (rtx reg)
6889 enum machine_mode mode;
6891 /* By default, GCC maps increasing register numbers to increasing
6892 memory locations, but paired FPRs are always little-endian,
6893 regardless of the prevailing endianness. */
6894 mode = GET_MODE (reg);
6895 if (FP_REG_P (REGNO (reg))
6896 && TARGET_BIG_ENDIAN
6897 && MAX_FPRS_PER_FMT > 1
6898 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
6900 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
6901 high = mips_subword (reg, true);
6902 low = mips_subword (reg, false);
6903 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
6909 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6910 that should be written before the opening quote, such as "\t.ascii\t"
6911 for real string data or "\t# " for a comment. */
6914 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
6919 register const unsigned char *string =
6920 (const unsigned char *)string_param;
6922 fprintf (stream, "%s\"", prefix);
6923 for (i = 0; i < len; i++)
6925 register int c = string[i];
6929 if (c == '\\' || c == '\"')
6931 putc ('\\', stream);
6939 fprintf (stream, "\\%03o", c);
6943 if (cur_pos > 72 && i+1 < len)
6946 fprintf (stream, "\"\n%s\"", prefix);
6949 fprintf (stream, "\"\n");
6952 #ifdef BSS_SECTION_ASM_OP
6953 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6954 in the use of sbss. */
6957 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6958 unsigned HOST_WIDE_INT size, int align)
6960 extern tree last_assemble_variable_decl;
6962 if (mips_in_small_data_p (decl))
6963 switch_to_section (get_named_section (NULL, ".sbss", 0));
6965 switch_to_section (bss_section);
6966 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6967 last_assemble_variable_decl = decl;
6968 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6969 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6973 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6974 macros, mark the symbol as written so that mips_file_end won't emit an
6975 .extern for it. STREAM is the output file, NAME is the name of the
6976 symbol, INIT_STRING is the string that should be written before the
6977 symbol and FINAL_STRING is the string that should be written after it.
6978 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6981 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6982 const char *final_string, ...)
6986 fputs (init_string, stream);
6987 assemble_name (stream, name);
6988 va_start (ap, final_string);
6989 vfprintf (stream, final_string, ap);
6992 if (!TARGET_EXPLICIT_RELOCS)
6994 tree name_tree = get_identifier (name);
6995 TREE_ASM_WRITTEN (name_tree) = 1;
6999 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7000 NAME is the name of the object and ALIGN is the required alignment
7001 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7002 alignment argument. */
7005 mips_declare_common_object (FILE *stream, const char *name,
7006 const char *init_string,
7007 unsigned HOST_WIDE_INT size,
7008 unsigned int align, bool takes_alignment_p)
7010 if (!takes_alignment_p)
7012 size += (align / BITS_PER_UNIT) - 1;
7013 size -= size % (align / BITS_PER_UNIT);
7014 mips_declare_object (stream, name, init_string,
7015 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7018 mips_declare_object (stream, name, init_string,
7019 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7020 size, align / BITS_PER_UNIT);
7023 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7024 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7027 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7028 unsigned HOST_WIDE_INT size,
7031 /* If the target wants uninitialized const declarations in
7032 .rdata then don't put them in .comm. */
7033 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
7034 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
7035 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7037 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7038 targetm.asm_out.globalize_label (stream, name);
7040 switch_to_section (readonly_data_section);
7041 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7042 mips_declare_object (stream, name, "",
7043 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7047 mips_declare_common_object (stream, name, "\n\t.comm\t",
7051 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7052 extern int size_directive_output;
7054 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7055 definitions except that it uses mips_declare_object() to emit the label. */
7058 mips_declare_object_name (FILE *stream, const char *name,
7059 tree decl ATTRIBUTE_UNUSED)
7061 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7062 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7065 size_directive_output = 0;
7066 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7070 size_directive_output = 1;
7071 size = int_size_in_bytes (TREE_TYPE (decl));
7072 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7075 mips_declare_object (stream, name, "", ":\n");
7078 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7081 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7085 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7086 if (!flag_inhibit_size_directive
7087 && DECL_SIZE (decl) != 0
7088 && !at_end && top_level
7089 && DECL_INITIAL (decl) == error_mark_node
7090 && !size_directive_output)
7094 size_directive_output = 1;
7095 size = int_size_in_bytes (TREE_TYPE (decl));
7096 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7101 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7102 with the current ABI. */
7105 mips_mdebug_abi_name (void)
7118 return TARGET_64BIT ? "eabi64" : "eabi32";
7124 /* Implement TARGET_ASM_FILE_START. */
7127 mips_file_start (void)
7129 default_file_start ();
7133 /* Generate a special section to describe the ABI switches used to
7134 produce the resultant binary. This used to be done by the assembler
7135 setting bits in the ELF header's flags field, but we have run out of
7136 bits. GDB needs this information in order to be able to correctly
7137 debug these binaries. See the function mips_gdbarch_init() in
7138 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
7139 causes unnecessary IRIX 6 ld warnings. */
7140 /* Note - we use fprintf directly rather than calling switch_to_section
7141 because in this way we can avoid creating an allocated section. We
7142 do not want this section to take up any space in the running
7144 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7145 mips_mdebug_abi_name ());
7147 /* There is no ELF header flag to distinguish long32 forms of the
7148 EABI from long64 forms. Emit a special section to help tools
7149 such as GDB. Do the same for o64, which is sometimes used with
7151 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7152 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7153 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7155 #ifdef HAVE_AS_GNU_ATTRIBUTE
7156 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7157 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
7161 /* Generate the pseudo ops that System V.4 wants. */
7162 if (TARGET_ABICALLS)
7163 fprintf (asm_out_file, "\t.abicalls\n");
7165 if (flag_verbose_asm)
7166 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7168 mips_section_threshold, mips_arch_info->name, mips_isa);
7172 /* Make the last instruction frame related and note that it performs
7173 the operation described by FRAME_PATTERN. */
7176 mips_set_frame_expr (rtx frame_pattern)
7180 insn = get_last_insn ();
7181 RTX_FRAME_RELATED_P (insn) = 1;
7182 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7188 /* Return a frame-related rtx that stores REG at MEM.
7189 REG must be a single register. */
7192 mips_frame_set (rtx mem, rtx reg)
7196 /* If we're saving the return address register and the dwarf return
7197 address column differs from the hard register number, adjust the
7198 note reg to refer to the former. */
7199 if (REGNO (reg) == GP_REG_FIRST + 31
7200 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7201 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7203 set = gen_rtx_SET (VOIDmode, mem, reg);
7204 RTX_FRAME_RELATED_P (set) = 1;
7209 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7210 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7211 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7212 static const unsigned char mips16e_s2_s8_regs[] = {
7213 30, 23, 22, 21, 20, 19, 18
7215 static const unsigned char mips16e_a0_a3_regs[] = {
7219 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7220 ordered from the uppermost in memory to the lowest in memory. */
7221 static const unsigned char mips16e_save_restore_regs[] = {
7222 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7225 /* Return the index of the lowest X in the range [0, SIZE) for which
7226 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7229 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7234 for (i = 0; i < size; i++)
7235 if (BITSET_P (mask, regs[i]))
7241 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7242 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
7243 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
7244 is true for all indexes (X, SIZE). */
7247 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
7248 unsigned int size, unsigned int *num_regs_ptr)
7252 i = mips16e_find_first_register (*mask_ptr, regs, size);
7253 for (i++; i < size; i++)
7254 if (!BITSET_P (*mask_ptr, regs[i]))
7257 *mask_ptr |= 1 << regs[i];
7261 /* Return a simplified form of X using the register values in REG_VALUES.
7262 REG_VALUES[R] is the last value assigned to hard register R, or null
7263 if R has not been modified.
7265 This function is rather limited, but is good enough for our purposes. */
7268 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7272 x = avoid_constant_pool_reference (x);
7276 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7277 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7278 x0, GET_MODE (XEXP (x, 0)));
7281 if (ARITHMETIC_P (x))
7283 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7284 x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7285 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7289 && reg_values[REGNO (x)]
7290 && !rtx_unstable_p (reg_values[REGNO (x)]))
7291 return reg_values[REGNO (x)];
7296 /* Return true if (set DEST SRC) stores an argument register into its
7297 caller-allocated save slot, storing the number of that argument
7298 register in *REGNO_PTR if so. REG_VALUES is as for
7299 mips16e_collect_propagate_value. */
7302 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7303 unsigned int *regno_ptr)
7305 unsigned int argno, regno;
7306 HOST_WIDE_INT offset, required_offset;
7309 /* Check that this is a word-mode store. */
7310 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7313 /* Check that the register being saved is an unmodified argument
7315 regno = REGNO (src);
7316 if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
7318 argno = regno - GP_ARG_FIRST;
7320 /* Check whether the address is an appropriate stack pointer or
7321 frame pointer access. */
7322 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7323 mips_split_plus (addr, &base, &offset);
7324 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7325 if (base == hard_frame_pointer_rtx)
7326 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
7327 else if (base != stack_pointer_rtx)
7329 if (offset != required_offset)
7336 /* A subroutine of mips_expand_prologue, called only when generating
7337 MIPS16e SAVE instructions. Search the start of the function for any
7338 instructions that save argument registers into their caller-allocated
7339 save slots. Delete such instructions and return a value N such that
7340 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7341 instructions redundant. */
7344 mips16e_collect_argument_saves (void)
7346 rtx reg_values[FIRST_PSEUDO_REGISTER];
7347 rtx insn, next, set, dest, src;
7348 unsigned int nargs, regno;
7350 push_topmost_sequence ();
7352 memset (reg_values, 0, sizeof (reg_values));
7353 for (insn = get_insns (); insn; insn = next)
7355 next = NEXT_INSN (insn);
7362 set = PATTERN (insn);
7363 if (GET_CODE (set) != SET)
7366 dest = SET_DEST (set);
7367 src = SET_SRC (set);
7368 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
7370 if (!BITSET_P (cfun->machine->frame.mask, regno))
7373 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7376 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7377 reg_values[REGNO (dest)]
7378 = mips16e_collect_propagate_value (src, reg_values);
7382 pop_topmost_sequence ();
7387 /* Return a move between register REGNO and memory location SP + OFFSET.
7388 Make the move a load if RESTORE_P, otherwise make it a frame-related
7392 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7397 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7398 reg = gen_rtx_REG (SImode, regno);
7400 ? gen_rtx_SET (VOIDmode, reg, mem)
7401 : mips_frame_set (mem, reg));
7404 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7405 The instruction must:
7407 - Allocate or deallocate SIZE bytes in total; SIZE is known
7410 - Save or restore as many registers in *MASK_PTR as possible.
7411 The instruction saves the first registers at the top of the
7412 allocated area, with the other registers below it.
7414 - Save NARGS argument registers above the allocated area.
7416 (NARGS is always zero if RESTORE_P.)
7418 The SAVE and RESTORE instructions cannot save and restore all general
7419 registers, so there may be some registers left over for the caller to
7420 handle. Destructively modify *MASK_PTR so that it contains the registers
7421 that still need to be saved or restored. The caller can save these
7422 registers in the memory immediately below *OFFSET_PTR, which is a
7423 byte offset from the bottom of the allocated stack area. */
7426 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7427 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7431 HOST_WIDE_INT offset, top_offset;
7432 unsigned int i, regno;
7435 gcc_assert (cfun->machine->frame.num_fp == 0);
7437 /* Calculate the number of elements in the PARALLEL. We need one element
7438 for the stack adjustment, one for each argument register save, and one
7439 for each additional register move. */
7441 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7442 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7445 /* Create the final PARALLEL. */
7446 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7449 /* Add the stack pointer adjustment. */
7450 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7451 plus_constant (stack_pointer_rtx,
7452 restore_p ? size : -size));
7453 RTX_FRAME_RELATED_P (set) = 1;
7454 XVECEXP (pattern, 0, n++) = set;
7456 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7457 top_offset = restore_p ? size : 0;
7459 /* Save the arguments. */
7460 for (i = 0; i < nargs; i++)
7462 offset = top_offset + i * UNITS_PER_WORD;
7463 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7464 XVECEXP (pattern, 0, n++) = set;
7467 /* Then fill in the other register moves. */
7468 offset = top_offset;
7469 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7471 regno = mips16e_save_restore_regs[i];
7472 if (BITSET_P (*mask_ptr, regno))
7474 offset -= UNITS_PER_WORD;
7475 set = mips16e_save_restore_reg (restore_p, offset, regno);
7476 XVECEXP (pattern, 0, n++) = set;
7477 *mask_ptr &= ~(1 << regno);
7481 /* Tell the caller what offset it should use for the remaining registers. */
7482 *offset_ptr = size + (offset - top_offset);
7484 gcc_assert (n == XVECLEN (pattern, 0));
7489 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7490 pointer. Return true if PATTERN matches the kind of instruction
7491 generated by mips16e_build_save_restore. If INFO is nonnull,
7492 initialize it when returning true. */
7495 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7496 struct mips16e_save_restore_info *info)
7498 unsigned int i, nargs, mask, extra;
7499 HOST_WIDE_INT top_offset, save_offset, offset;
7500 rtx set, reg, mem, base;
7503 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7506 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7507 top_offset = adjust > 0 ? adjust : 0;
7509 /* Interpret all other members of the PARALLEL. */
7510 save_offset = top_offset - UNITS_PER_WORD;
7514 for (n = 1; n < XVECLEN (pattern, 0); n++)
7516 /* Check that we have a SET. */
7517 set = XVECEXP (pattern, 0, n);
7518 if (GET_CODE (set) != SET)
7521 /* Check that the SET is a load (if restoring) or a store
7523 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7527 /* Check that the address is the sum of the stack pointer and a
7528 possibly-zero constant offset. */
7529 mips_split_plus (XEXP (mem, 0), &base, &offset);
7530 if (base != stack_pointer_rtx)
7533 /* Check that SET's other operand is a register. */
7534 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7538 /* Check for argument saves. */
7539 if (offset == top_offset + nargs * UNITS_PER_WORD
7540 && REGNO (reg) == GP_ARG_FIRST + nargs)
7542 else if (offset == save_offset)
7544 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7545 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7548 mask |= 1 << REGNO (reg);
7549 save_offset -= UNITS_PER_WORD;
7555 /* Check that the restrictions on register ranges are met. */
7557 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7558 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7559 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7560 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7564 /* Make sure that the topmost argument register is not saved twice.
7565 The checks above ensure that the same is then true for the other
7566 argument registers. */
7567 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7570 /* Pass back information, if requested. */
7573 info->nargs = nargs;
7575 info->size = (adjust > 0 ? adjust : -adjust);
7581 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7582 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7583 the null terminator. */
7586 mips16e_add_register_range (char *s, unsigned int min_reg,
7587 unsigned int max_reg)
7589 if (min_reg != max_reg)
7590 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7592 s += sprintf (s, ",%s", reg_names[min_reg]);
7596 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7597 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7600 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7602 static char buffer[300];
7604 struct mips16e_save_restore_info info;
7605 unsigned int i, end;
7608 /* Parse the pattern. */
7609 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7612 /* Add the mnemonic. */
7613 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7616 /* Save the arguments. */
7618 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7619 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7620 else if (info.nargs == 1)
7621 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7623 /* Emit the amount of stack space to allocate or deallocate. */
7624 s += sprintf (s, "%d", (int) info.size);
7626 /* Save or restore $16. */
7627 if (BITSET_P (info.mask, 16))
7628 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7630 /* Save or restore $17. */
7631 if (BITSET_P (info.mask, 17))
7632 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7634 /* Save or restore registers in the range $s2...$s8, which
7635 mips16e_s2_s8_regs lists in decreasing order. Note that this
7636 is a software register range; the hardware registers are not
7637 numbered consecutively. */
7638 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7639 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7641 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7642 mips16e_s2_s8_regs[i]);
7644 /* Save or restore registers in the range $a0...$a3. */
7645 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7646 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7648 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7649 mips16e_a0_a3_regs[end - 1]);
7651 /* Save or restore $31. */
7652 if (BITSET_P (info.mask, 31))
7653 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7658 /* Return true if the current function has an insn that implicitly
7662 mips_function_has_gp_insn (void)
7664 /* Don't bother rechecking if we found one last time. */
7665 if (!cfun->machine->has_gp_insn_p)
7669 push_topmost_sequence ();
7670 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7672 && GET_CODE (PATTERN (insn)) != USE
7673 && GET_CODE (PATTERN (insn)) != CLOBBER
7674 && (get_attr_got (insn) != GOT_UNSET
7675 || small_data_pattern (PATTERN (insn), VOIDmode)))
7677 pop_topmost_sequence ();
7679 cfun->machine->has_gp_insn_p = (insn != 0);
7681 return cfun->machine->has_gp_insn_p;
7685 /* Return the register that should be used as the global pointer
7686 within this function. Return 0 if the function doesn't need
7687 a global pointer. */
7690 mips_global_pointer (void)
7694 /* $gp is always available unless we're using a GOT. */
7695 if (!TARGET_USE_GOT)
7696 return GLOBAL_POINTER_REGNUM;
7698 /* We must always provide $gp when it is used implicitly. */
7699 if (!TARGET_EXPLICIT_RELOCS)
7700 return GLOBAL_POINTER_REGNUM;
7702 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
7704 if (current_function_profile)
7705 return GLOBAL_POINTER_REGNUM;
7707 /* If the function has a nonlocal goto, $gp must hold the correct
7708 global pointer for the target function. */
7709 if (current_function_has_nonlocal_goto)
7710 return GLOBAL_POINTER_REGNUM;
7712 /* If the gp is never referenced, there's no need to initialize it.
7713 Note that reload can sometimes introduce constant pool references
7714 into a function that otherwise didn't need them. For example,
7715 suppose we have an instruction like:
7717 (set (reg:DF R1) (float:DF (reg:SI R2)))
7719 If R2 turns out to be constant such as 1, the instruction may have a
7720 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
7721 using this constant if R2 doesn't get allocated to a register.
7723 In cases like these, reload will have added the constant to the pool
7724 but no instruction will yet refer to it. */
7725 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
7726 && !current_function_uses_const_pool
7727 && !mips_function_has_gp_insn ())
7730 /* We need a global pointer, but perhaps we can use a call-clobbered
7731 register instead of $gp. */
7732 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
7733 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7734 if (!df_regs_ever_live_p (regno)
7735 && call_really_used_regs[regno]
7736 && !fixed_regs[regno]
7737 && regno != PIC_FUNCTION_ADDR_REGNUM)
7740 return GLOBAL_POINTER_REGNUM;
7743 /* Return true if the current function returns its value in a floating-point
7744 register in MIPS16 mode. */
7747 mips16_cfun_returns_in_fpr_p (void)
7749 tree return_type = DECL_RESULT (current_function_decl);
7750 return (TARGET_MIPS16
7751 && TARGET_HARD_FLOAT_ABI
7752 && !aggregate_value_p (return_type, current_function_decl)
7753 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
7757 /* Return true if the current function must save REGNO. */
7760 mips_save_reg_p (unsigned int regno)
7762 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
7763 if we have not chosen a call-clobbered substitute. */
7764 if (regno == GLOBAL_POINTER_REGNUM)
7765 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
7767 /* Check call-saved registers. */
7768 if ((current_function_saves_all_registers || df_regs_ever_live_p (regno))
7769 && !call_really_used_regs[regno])
7772 /* Save both registers in an FPR pair if either one is used. This is
7773 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
7774 register to be used without the even register. */
7775 if (FP_REG_P (regno)
7776 && MAX_FPRS_PER_FMT == 2
7777 && df_regs_ever_live_p (regno + 1)
7778 && !call_really_used_regs[regno + 1])
7781 /* We need to save the old frame pointer before setting up a new one. */
7782 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7785 /* Check for registers that must be saved for FUNCTION_PROFILER. */
7786 if (current_function_profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
7789 /* We need to save the incoming return address if it is ever clobbered
7790 within the function, if __builtin_eh_return is being used to set a
7791 different return address, or if a stub is being used to return a
7793 if (regno == GP_REG_FIRST + 31
7794 && (df_regs_ever_live_p (regno)
7795 || current_function_calls_eh_return
7796 || mips16_cfun_returns_in_fpr_p ()))
7802 /* Populate the current function's mips_frame_info structure.
7804 MIPS stack frames look like:
7806 +-------------------------------+
7808 | incoming stack arguments |
7810 +-------------------------------+
7812 | caller-allocated save area |
7813 A | for register arguments |
7815 +-------------------------------+ <-- incoming stack pointer
7817 | callee-allocated save area |
7818 B | for arguments that are |
7819 | split between registers and |
7822 +-------------------------------+ <-- arg_pointer_rtx
7824 C | callee-allocated save area |
7825 | for register varargs |
7827 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
7828 | | + UNITS_PER_HWFPVALUE
7831 +-------------------------------+ <-- frame_pointer_rtx + gp_sp_offset
7832 | | + UNITS_PER_WORD
7835 +-------------------------------+
7837 | local variables | | var_size
7839 +-------------------------------+
7841 | $gp save area | | cprestore_size
7843 P +-------------------------------+ <-- hard_frame_pointer_rtx for
7845 | outgoing stack arguments |
7847 +-------------------------------+
7849 | caller-allocated save area |
7850 | for register arguments |
7852 +-------------------------------+ <-- stack_pointer_rtx
7854 hard_frame_pointer_rtx for
7857 At least two of A, B and C will be empty.
7859 Dynamic stack allocations such as alloca insert data at point P.
7860 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7861 hard_frame_pointer_rtx unchanged. */
7864 mips_compute_frame_info (void)
7866 struct mips_frame_info *frame;
7867 HOST_WIDE_INT offset, size;
7868 unsigned int regno, i;
7870 frame = &cfun->machine->frame;
7871 memset (frame, 0, sizeof (*frame));
7872 size = get_frame_size ();
7874 cfun->machine->global_pointer = mips_global_pointer ();
7876 /* The first STARTING_FRAME_OFFSET bytes contain the outgoing argument
7877 area and the $gp save slot. This area isn't needed in leaf functions,
7878 but if the target-independent frame size is nonzero, we're committed
7879 to allocating it anyway. */
7880 if (size == 0 && current_function_is_leaf)
7882 /* The MIPS 3.0 linker does not like functions that dynamically
7883 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
7884 looks like we are trying to create a second frame pointer to the
7885 function, so allocate some stack space to make it happy. */
7886 if (current_function_calls_alloca)
7887 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
7889 frame->args_size = 0;
7890 frame->cprestore_size = 0;
7894 frame->args_size = current_function_outgoing_args_size;
7895 frame->cprestore_size = STARTING_FRAME_OFFSET - frame->args_size;
7897 offset = frame->args_size + frame->cprestore_size;
7899 /* Move above the local variables. */
7900 frame->var_size = MIPS_STACK_ALIGN (size);
7901 offset += frame->var_size;
7903 /* Find out which GPRs we need to save. */
7904 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
7905 if (mips_save_reg_p (regno))
7908 frame->mask |= 1 << (regno - GP_REG_FIRST);
7911 /* If this function calls eh_return, we must also save and restore the
7912 EH data registers. */
7913 if (current_function_calls_eh_return)
7914 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
7917 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
7920 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
7921 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
7922 save all later registers too. */
7923 if (GENERATE_MIPS16E_SAVE_RESTORE)
7925 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
7926 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
7927 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
7928 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
7931 /* Move above the GPR save area. */
7932 if (frame->num_gp > 0)
7934 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
7935 frame->gp_sp_offset = offset - UNITS_PER_WORD;
7938 /* Find out which FPRs we need to save. This loop must iterate over
7939 the same space as its companion in mips_for_each_saved_reg. */
7940 if (TARGET_HARD_FLOAT)
7941 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
7942 if (mips_save_reg_p (regno))
7944 frame->num_fp += MAX_FPRS_PER_FMT;
7945 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
7948 /* Move above the FPR save area. */
7949 if (frame->num_fp > 0)
7951 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
7952 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
7955 /* Move above the callee-allocated varargs save area. */
7956 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
7957 frame->arg_pointer_offset = offset;
7959 /* Move above the callee-allocated area for pretend stack arguments. */
7960 offset += current_function_pretend_args_size;
7961 frame->total_size = offset;
7963 /* Work out the offsets of the save areas from the top of the frame. */
7964 if (frame->gp_sp_offset > 0)
7965 frame->gp_save_offset = frame->gp_sp_offset - offset;
7966 if (frame->fp_sp_offset > 0)
7967 frame->fp_save_offset = frame->fp_sp_offset - offset;
7969 /* MIPS16 code offsets the frame pointer by the size of the outgoing
7970 arguments. This tends to increase the chances of using unextended
7971 instructions for local variables and incoming arguments. */
7973 frame->hard_frame_pointer_offset = frame->args_size;
7976 /* Return the style of GP load sequence that is being used for the
7977 current function. */
7979 enum mips_loadgp_style
7980 mips_current_loadgp_style (void)
7982 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
7988 if (TARGET_ABSOLUTE_ABICALLS)
7989 return LOADGP_ABSOLUTE;
7991 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
7994 /* Implement FRAME_POINTER_REQUIRED. */
7997 mips_frame_pointer_required (void)
7999 /* If the function contains dynamic stack allocations, we need to
8000 use the frame pointer to access the static parts of the frame. */
8001 if (current_function_calls_alloca)
8004 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8005 reload may be unable to compute the address of a local variable,
8006 since there is no way to add a large constant to the stack pointer
8007 without using a second temporary register. */
8010 mips_compute_frame_info ();
8011 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8018 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
8019 pointer or argument pointer. TO is either the stack pointer or
8020 hard frame pointer. */
8023 mips_initial_elimination_offset (int from, int to)
8025 HOST_WIDE_INT offset;
8027 mips_compute_frame_info ();
8029 /* Set OFFSET to the offset from the soft frame pointer, which is also
8030 the offset from the end-of-prologue stack pointer. */
8033 case FRAME_POINTER_REGNUM:
8037 case ARG_POINTER_REGNUM:
8038 offset = cfun->machine->frame.arg_pointer_offset;
8045 if (to == HARD_FRAME_POINTER_REGNUM)
8046 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8051 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
8052 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
8055 mips_extra_live_on_entry (bitmap regs)
8057 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
8058 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8061 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
8062 back to a previous frame. */
8065 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
8070 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
8073 /* Emit code to change the current function's return address to
8074 ADDRESS. SCRATCH is available as a scratch register, if needed.
8075 ADDRESS and SCRATCH are both word-mode GPRs. */
8078 mips_set_return_address (rtx address, rtx scratch)
8082 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
8083 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
8084 cfun->machine->frame.gp_sp_offset);
8086 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
8089 /* Restore $gp from its save slot. Valid only when using o32 or
8093 mips_restore_gp (void)
8097 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
8099 address = mips_add_offset (pic_offset_table_rtx,
8100 frame_pointer_needed
8101 ? hard_frame_pointer_rtx
8102 : stack_pointer_rtx,
8103 current_function_outgoing_args_size);
8105 mips_emit_move (pic_offset_table_rtx, gen_frame_mem (Pmode, address));
8106 if (!TARGET_EXPLICIT_RELOCS)
8107 emit_insn (gen_blockage ());
8110 /* A function to save or store a register. The first argument is the
8111 register and the second is the stack slot. */
8112 typedef void (*mips_save_restore_fn) (rtx, rtx);
8114 /* Use FN to save or restore register REGNO. MODE is the register's
8115 mode and OFFSET is the offset of its save slot from the current
8119 mips_save_restore_reg (enum machine_mode mode, int regno,
8120 HOST_WIDE_INT offset, mips_save_restore_fn fn)
8124 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
8126 fn (gen_rtx_REG (mode, regno), mem);
8130 /* Call FN for each register that is saved by the current function.
8131 SP_OFFSET is the offset of the current stack pointer from the start
8135 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
8137 enum machine_mode fpr_mode;
8138 HOST_WIDE_INT offset;
8141 /* Save registers starting from high to low. The debuggers prefer at least
8142 the return register be stored at func+4, and also it allows us not to
8143 need a nop in the epilogue if at least one register is reloaded in
8144 addition to return address. */
8145 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
8146 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
8147 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
8149 mips_save_restore_reg (word_mode, regno, offset, fn);
8150 offset -= UNITS_PER_WORD;
8153 /* This loop must iterate over the same space as its companion in
8154 mips_compute_frame_info. */
8155 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
8156 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
8157 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
8158 regno >= FP_REG_FIRST;
8159 regno -= MAX_FPRS_PER_FMT)
8160 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
8162 mips_save_restore_reg (fpr_mode, regno, offset, fn);
8163 offset -= GET_MODE_SIZE (fpr_mode);
8167 /* If we're generating n32 or n64 abicalls, and the current function
8168 does not use $28 as its global pointer, emit a cplocal directive.
8169 Use pic_offset_table_rtx as the argument to the directive. */
8172 mips_output_cplocal (void)
8174 if (!TARGET_EXPLICIT_RELOCS
8175 && cfun->machine->global_pointer > 0
8176 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
8177 output_asm_insn (".cplocal %+", 0);
8180 /* Set up the stack and frame (if desired) for the function. */
8183 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8186 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
8188 #ifdef SDB_DEBUGGING_INFO
8189 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
8190 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
8193 /* In mips16 mode, we may need to generate a 32 bit to handle
8194 floating point arguments. The linker will arrange for any 32-bit
8195 functions to call this stub, which will then jump to the 16-bit
8198 && TARGET_HARD_FLOAT_ABI
8199 && current_function_args_info.fp_code != 0)
8200 build_mips16_function_stub ();
8202 /* Select the mips16 mode for this function. */
8204 fprintf (file, "\t.set\tmips16\n");
8206 fprintf (file, "\t.set\tnomips16\n");
8208 if (!FUNCTION_NAME_ALREADY_DECLARED)
8210 /* Get the function name the same way that toplev.c does before calling
8211 assemble_start_function. This is needed so that the name used here
8212 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8213 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8215 if (!flag_inhibit_size_directive)
8217 fputs ("\t.ent\t", file);
8218 assemble_name (file, fnname);
8222 assemble_name (file, fnname);
8223 fputs (":\n", file);
8226 /* Stop mips_file_end from treating this function as external. */
8227 if (TARGET_IRIX && mips_abi == ABI_32)
8228 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
8230 if (!flag_inhibit_size_directive)
8232 /* .frame FRAMEREG, FRAMESIZE, RETREG */
8234 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
8235 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
8236 ", args= " HOST_WIDE_INT_PRINT_DEC
8237 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
8238 (reg_names[(frame_pointer_needed)
8239 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
8240 (frame_pointer_needed
8241 ? tsize - cfun->machine->frame.hard_frame_pointer_offset
8243 reg_names[GP_REG_FIRST + 31],
8244 cfun->machine->frame.var_size,
8245 cfun->machine->frame.num_gp,
8246 cfun->machine->frame.num_fp,
8247 cfun->machine->frame.args_size,
8248 cfun->machine->frame.cprestore_size);
8250 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
8251 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8252 cfun->machine->frame.mask,
8253 cfun->machine->frame.gp_save_offset);
8254 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
8255 cfun->machine->frame.fmask,
8256 cfun->machine->frame.fp_save_offset);
8259 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
8260 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
8263 if (mips_current_loadgp_style () == LOADGP_OLDABI)
8265 /* Handle the initialization of $gp for SVR4 PIC. */
8266 if (!cfun->machine->all_noreorder_p)
8267 output_asm_insn ("%(.cpload\t%^%)", 0);
8269 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
8271 else if (cfun->machine->all_noreorder_p)
8272 output_asm_insn ("%(%<", 0);
8274 /* Tell the assembler which register we're using as the global
8275 pointer. This is needed for thunks, since they can use either
8276 explicit relocs or assembler macros. */
8277 mips_output_cplocal ();
8280 /* Do any necessary cleanup after a function to restore stack, frame,
8283 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
8286 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8287 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
8289 /* Reinstate the normal $gp. */
8290 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
8291 mips_output_cplocal ();
8293 if (cfun->machine->all_noreorder_p)
8295 /* Avoid using %>%) since it adds excess whitespace. */
8296 output_asm_insn (".set\tmacro", 0);
8297 output_asm_insn (".set\treorder", 0);
8298 set_noreorder = set_nomacro = 0;
8301 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
8305 /* Get the function name the same way that toplev.c does before calling
8306 assemble_start_function. This is needed so that the name used here
8307 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
8308 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8309 fputs ("\t.end\t", file);
8310 assemble_name (file, fnname);
8315 /* Save register REG to MEM. Make the instruction frame-related. */
8318 mips_save_reg (rtx reg, rtx mem)
8320 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
8324 if (mips_split_64bit_move_p (mem, reg))
8325 mips_split_doubleword_move (mem, reg);
8327 mips_emit_move (mem, reg);
8329 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
8330 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
8331 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
8336 && REGNO (reg) != GP_REG_FIRST + 31
8337 && !M16_REG_P (REGNO (reg)))
8339 /* Save a non-mips16 register by moving it through a temporary.
8340 We don't need to do this for $31 since there's a special
8341 instruction for it. */
8342 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
8343 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
8346 mips_emit_move (mem, reg);
8348 mips_set_frame_expr (mips_frame_set (mem, reg));
8352 /* The __gnu_local_gp symbol. */
8354 static GTY(()) rtx mips_gnu_local_gp;
8356 /* If we're generating n32 or n64 abicalls, emit instructions
8357 to set up the global pointer. */
8360 mips_emit_loadgp (void)
8362 rtx addr, offset, incoming_address, base, index;
8364 switch (mips_current_loadgp_style ())
8366 case LOADGP_ABSOLUTE:
8367 if (mips_gnu_local_gp == NULL)
8369 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
8370 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
8372 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
8376 addr = XEXP (DECL_RTL (current_function_decl), 0);
8377 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
8378 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8379 emit_insn (gen_loadgp_newabi (offset, incoming_address));
8380 if (!TARGET_EXPLICIT_RELOCS)
8381 emit_insn (gen_loadgp_blockage ());
8385 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
8386 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
8387 emit_insn (gen_loadgp_rtp (base, index));
8388 if (!TARGET_EXPLICIT_RELOCS)
8389 emit_insn (gen_loadgp_blockage ());
8397 /* Expand the prologue into a bunch of separate insns. */
8400 mips_expand_prologue (void)
8406 if (cfun->machine->global_pointer > 0)
8407 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8409 size = cfun->machine->frame.total_size;
8411 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
8412 bytes beforehand; this is enough to cover the register save area
8413 without going out of range. */
8414 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
8416 HOST_WIDE_INT step1;
8418 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
8420 if (GENERATE_MIPS16E_SAVE_RESTORE)
8422 HOST_WIDE_INT offset;
8423 unsigned int mask, regno;
8425 /* Try to merge argument stores into the save instruction. */
8426 nargs = mips16e_collect_argument_saves ();
8428 /* Build the save instruction. */
8429 mask = cfun->machine->frame.mask;
8430 insn = mips16e_build_save_restore (false, &mask, &offset,
8432 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8435 /* Check if we need to save other registers. */
8436 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8437 if (BITSET_P (mask, regno - GP_REG_FIRST))
8439 offset -= UNITS_PER_WORD;
8440 mips_save_restore_reg (word_mode, regno,
8441 offset, mips_save_reg);
8446 insn = gen_add3_insn (stack_pointer_rtx,
8449 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8451 mips_for_each_saved_reg (size, mips_save_reg);
8455 /* Allocate the rest of the frame. */
8458 if (SMALL_OPERAND (-size))
8459 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
8461 GEN_INT (-size)))) = 1;
8464 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
8467 /* There are no instructions to add or subtract registers
8468 from the stack pointer, so use the frame pointer as a
8469 temporary. We should always be using a frame pointer
8470 in this case anyway. */
8471 gcc_assert (frame_pointer_needed);
8472 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8473 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
8474 hard_frame_pointer_rtx,
8475 MIPS_PROLOGUE_TEMP (Pmode)));
8476 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
8479 emit_insn (gen_sub3_insn (stack_pointer_rtx,
8481 MIPS_PROLOGUE_TEMP (Pmode)));
8483 /* Describe the combined effect of the previous instructions. */
8485 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8486 plus_constant (stack_pointer_rtx, -size)));
8490 /* Set up the frame pointer, if we're using one. */
8491 if (frame_pointer_needed)
8493 HOST_WIDE_INT offset;
8495 offset = cfun->machine->frame.hard_frame_pointer_offset;
8498 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8499 RTX_FRAME_RELATED_P (insn) = 1;
8501 else if (SMALL_OPERAND (offset))
8503 insn = gen_add3_insn (hard_frame_pointer_rtx,
8504 stack_pointer_rtx, GEN_INT (offset));
8505 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
8509 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
8510 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
8511 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
8512 hard_frame_pointer_rtx,
8513 MIPS_PROLOGUE_TEMP (Pmode)));
8515 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
8516 plus_constant (stack_pointer_rtx, offset)));
8520 mips_emit_loadgp ();
8522 /* If generating o32/o64 abicalls, save $gp on the stack. */
8523 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
8524 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
8526 /* If we are profiling, make sure no instructions are scheduled before
8527 the call to mcount. */
8529 if (current_function_profile)
8530 emit_insn (gen_blockage ());
8533 /* Emit instructions to restore register REG from slot MEM. */
8536 mips_restore_reg (rtx reg, rtx mem)
8538 /* There's no mips16 instruction to load $31 directly. Load into
8539 $7 instead and adjust the return insn appropriately. */
8540 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
8541 reg = gen_rtx_REG (GET_MODE (reg), 7);
8543 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
8545 /* Can't restore directly; move through a temporary. */
8546 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
8547 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
8550 mips_emit_move (reg, mem);
8554 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
8555 if this epilogue precedes a sibling call, false if it is for a normal
8556 "epilogue" pattern. */
8559 mips_expand_epilogue (int sibcall_p)
8561 HOST_WIDE_INT step1, step2;
8564 if (!sibcall_p && mips_can_use_return_insn ())
8566 emit_jump_insn (gen_return ());
8570 /* In mips16 mode, if the return value should go into a floating-point
8571 register, we need to call a helper routine to copy it over. */
8572 if (mips16_cfun_returns_in_fpr_p ())
8573 mips16_copy_fpr_return_value ();
8575 /* Split the frame into two. STEP1 is the amount of stack we should
8576 deallocate before restoring the registers. STEP2 is the amount we
8577 should deallocate afterwards.
8579 Start off by assuming that no registers need to be restored. */
8580 step1 = cfun->machine->frame.total_size;
8583 /* Work out which register holds the frame address. */
8584 if (!frame_pointer_needed)
8585 base = stack_pointer_rtx;
8588 base = hard_frame_pointer_rtx;
8589 step1 -= cfun->machine->frame.hard_frame_pointer_offset;
8592 /* If we need to restore registers, deallocate as much stack as
8593 possible in the second step without going out of range. */
8594 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
8596 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
8600 /* Set TARGET to BASE + STEP1. */
8606 /* Get an rtx for STEP1 that we can add to BASE. */
8607 adjust = GEN_INT (step1);
8608 if (!SMALL_OPERAND (step1))
8610 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
8611 adjust = MIPS_EPILOGUE_TEMP (Pmode);
8614 /* Normal mode code can copy the result straight into $sp. */
8616 target = stack_pointer_rtx;
8618 emit_insn (gen_add3_insn (target, base, adjust));
8621 /* Copy TARGET into the stack pointer. */
8622 if (target != stack_pointer_rtx)
8623 mips_emit_move (stack_pointer_rtx, target);
8625 /* If we're using addressing macros, $gp is implicitly used by all
8626 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
8628 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
8629 emit_insn (gen_blockage ());
8631 if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
8633 unsigned int regno, mask;
8634 HOST_WIDE_INT offset;
8637 /* Generate the restore instruction. */
8638 mask = cfun->machine->frame.mask;
8639 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
8641 /* Restore any other registers manually. */
8642 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
8643 if (BITSET_P (mask, regno - GP_REG_FIRST))
8645 offset -= UNITS_PER_WORD;
8646 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
8649 /* Restore the remaining registers and deallocate the final bit
8651 emit_insn (restore);
8655 /* Restore the registers. */
8656 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
8659 /* Deallocate the final bit of the frame. */
8661 emit_insn (gen_add3_insn (stack_pointer_rtx,
8666 /* Add in the __builtin_eh_return stack adjustment. We need to
8667 use a temporary in mips16 code. */
8668 if (current_function_calls_eh_return)
8672 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
8673 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
8674 MIPS_EPILOGUE_TEMP (Pmode),
8675 EH_RETURN_STACKADJ_RTX));
8676 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
8679 emit_insn (gen_add3_insn (stack_pointer_rtx,
8681 EH_RETURN_STACKADJ_RTX));
8686 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
8687 path will restore the return address into $7 rather than $31. */
8689 && !GENERATE_MIPS16E_SAVE_RESTORE
8690 && (cfun->machine->frame.mask & RA_MASK) != 0)
8691 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
8692 GP_REG_FIRST + 7)));
8694 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
8695 GP_REG_FIRST + 31)));
8699 /* Return nonzero if this function is known to have a null epilogue.
8700 This allows the optimizer to omit jumps to jumps if no stack
8704 mips_can_use_return_insn (void)
8706 if (! reload_completed)
8709 if (current_function_profile)
8712 /* In mips16 mode, a function that returns a floating point value
8713 needs to arrange to copy the return value into the floating point
8715 if (mips16_cfun_returns_in_fpr_p ())
8718 return cfun->machine->frame.total_size == 0;
8721 /* Return true if register REGNO can store a value of mode MODE.
8722 The result of this function is cached in mips_hard_regno_mode_ok. */
8725 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
8728 enum mode_class class;
8730 if (mode == CCV2mode)
8733 && (regno - ST_REG_FIRST) % 2 == 0);
8735 if (mode == CCV4mode)
8738 && (regno - ST_REG_FIRST) % 4 == 0);
8743 return regno == FPSW_REGNUM;
8745 return (ST_REG_P (regno)
8747 || FP_REG_P (regno));
8750 size = GET_MODE_SIZE (mode);
8751 class = GET_MODE_CLASS (mode);
8753 if (GP_REG_P (regno))
8754 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
8756 if (FP_REG_P (regno)
8757 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
8758 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
8760 /* Allow TFmode for CCmode reloads. */
8761 if (mode == TFmode && ISA_HAS_8CC)
8764 if (class == MODE_FLOAT
8765 || class == MODE_COMPLEX_FLOAT
8766 || class == MODE_VECTOR_FLOAT)
8767 return size <= UNITS_PER_FPVALUE;
8769 /* Allow integer modes that fit into a single register. We need
8770 to put integers into FPRs when using instructions like CVT
8771 and TRUNC. There's no point allowing sizes smaller than a word,
8772 because the FPU has no appropriate load/store instructions. */
8773 if (class == MODE_INT)
8774 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
8777 if (ACC_REG_P (regno)
8778 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
8780 if (size <= UNITS_PER_WORD)
8783 if (size <= UNITS_PER_WORD * 2)
8784 return (DSP_ACC_REG_P (regno)
8785 ? ((regno - DSP_ACC_REG_FIRST) & 1) == 0
8786 : regno == MD_REG_FIRST);
8789 if (ALL_COP_REG_P (regno))
8790 return class == MODE_INT && size <= UNITS_PER_WORD;
8795 /* Implement HARD_REGNO_NREGS. */
8798 mips_hard_regno_nregs (int regno, enum machine_mode mode)
8800 if (ST_REG_P (regno))
8801 /* The size of FP status registers is always 4, because they only hold
8802 CCmode values, and CCmode is always considered to be 4 bytes wide. */
8803 return (GET_MODE_SIZE (mode) + 3) / 4;
8805 if (FP_REG_P (regno))
8806 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8808 /* All other registers are word-sized. */
8809 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8812 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
8813 in mips_hard_regno_nregs. */
8816 mips_class_max_nregs (enum reg_class class, enum machine_mode mode)
8822 COPY_HARD_REG_SET (left, reg_class_contents[(int) class]);
8823 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
8825 size = MIN (size, 4);
8826 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
8828 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
8830 size = MIN (size, UNITS_PER_FPREG);
8831 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
8833 if (!hard_reg_set_empty_p (left))
8834 size = MIN (size, UNITS_PER_WORD);
8835 return (GET_MODE_SIZE (mode) + size - 1) / size;
8838 /* Return true if registers of class CLASS cannot change from mode FROM
8842 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
8843 enum machine_mode to ATTRIBUTE_UNUSED,
8844 enum reg_class class)
8846 /* There are several problems with changing the modes of values
8847 in floating-point registers:
8849 - When a multi-word value is stored in paired floating-point
8850 registers, the first register always holds the low word.
8851 We therefore can't allow FPRs to change between single-word
8852 and multi-word modes on big-endian targets.
8854 - GCC assumes that each word of a multiword register can be accessed
8855 individually using SUBREGs. This is not true for floating-point
8856 registers if they are bigger than a word.
8858 - Loading a 32-bit value into a 64-bit floating-point register
8859 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8860 We can't allow FPRs to change from SImode to to a wider mode on
8863 - If the FPU has already interpreted a value in one format, we must
8864 not ask it to treat the value as having a different format.
8866 We therefore only allow changes between 4-byte and smaller integer
8867 values, all of which have the "W" format as far as the FPU is
8869 return (reg_classes_intersect_p (FP_REGS, class)
8870 && (GET_MODE_CLASS (from) != MODE_INT
8871 || GET_MODE_CLASS (to) != MODE_INT
8872 || GET_MODE_SIZE (from) > 4
8873 || GET_MODE_SIZE (to) > 4));
8876 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
8879 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
8884 return TARGET_HARD_FLOAT;
8887 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
8890 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
8897 /* Implement MODES_TIEABLE_P. */
8900 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
8902 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
8903 prefer to put one of them in FPRs. */
8904 return (mode1 == mode2
8905 || (!mips_mode_ok_for_mov_fmt_p (mode1)
8906 && !mips_mode_ok_for_mov_fmt_p (mode2)));
8909 /* Implement PREFERRED_RELOAD_CLASS. */
8912 mips_preferred_reload_class (rtx x, enum reg_class class)
8914 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8917 if (reg_class_subset_p (FP_REGS, class)
8918 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
8921 if (reg_class_subset_p (GR_REGS, class))
8924 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8930 /* Return a number assessing the cost of moving a register in class
8931 FROM to class TO. The classes are expressed using the enumeration
8932 values such as `GENERAL_REGS'. A value of 2 is the default; other
8933 values are interpreted relative to that.
8935 It is not required that the cost always equal 2 when FROM is the
8936 same as TO; on some machines it is expensive to move between
8937 registers if they are not general registers.
8939 If reload sees an insn consisting of a single `set' between two
8940 hard registers, and if `REGISTER_MOVE_COST' applied to their
8941 classes returns a value of 2, reload does not check to ensure that
8942 the constraints of the insn are met. Setting a cost of other than
8943 2 will allow reload to verify that the constraints are met. You
8944 should do this if the `movM' pattern's constraints do not allow
8947 ??? We make the cost of moving from HI/LO into general
8948 registers the same as for one of moving general registers to
8949 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8950 pseudo to HI/LO. This might hurt optimizations though, it
8951 isn't clear if it is wise. And it might not work in all cases. We
8952 could solve the DImode LO reg problem by using a multiply, just
8953 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8954 problem by using divide instructions. divu puts the remainder in
8955 the HI reg, so doing a divide by -1 will move the value in the HI
8956 reg for all values except -1. We could handle that case by using a
8957 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8958 a compare/branch to test the input value to see which instruction
8959 we need to use. This gets pretty messy, but it is feasible. */
8962 mips_register_move_cost (enum machine_mode mode,
8963 enum reg_class to, enum reg_class from)
8967 if (reg_class_subset_p (from, GENERAL_REGS)
8968 && reg_class_subset_p (to, GENERAL_REGS))
8970 if (reg_class_subset_p (from, M16_REGS)
8971 || reg_class_subset_p (to, M16_REGS))
8977 else if (reg_class_subset_p (from, GENERAL_REGS))
8979 if (reg_class_subset_p (to, GENERAL_REGS))
8981 if (reg_class_subset_p (to, FP_REGS))
8983 if (reg_class_subset_p (to, ALL_COP_AND_GR_REGS))
8985 if (reg_class_subset_p (to, ACC_REGS))
8988 else if (reg_class_subset_p (to, GENERAL_REGS))
8990 if (reg_class_subset_p (from, FP_REGS))
8992 if (reg_class_subset_p (from, ST_REGS))
8993 /* LUI followed by MOVF. */
8995 if (reg_class_subset_p (from, ALL_COP_AND_GR_REGS))
8997 if (reg_class_subset_p (from, ACC_REGS))
9000 else if (reg_class_subset_p (from, FP_REGS))
9002 if (reg_class_subset_p (to, FP_REGS)
9003 && mips_mode_ok_for_mov_fmt_p (mode))
9005 if (reg_class_subset_p (to, ST_REGS))
9006 /* An expensive sequence. */
9013 /* This function returns the register class required for a secondary
9014 register when copying between one of the registers in CLASS, and X,
9015 using MODE. If IN_P is nonzero, the copy is going from X to the
9016 register, otherwise the register is the source. A return value of
9017 NO_REGS means that no secondary register is required. */
9020 mips_secondary_reload_class (enum reg_class class,
9021 enum machine_mode mode, rtx x, int in_p)
9025 /* If X is a constant that cannot be loaded into $25, it must be loaded
9026 into some other GPR. No other register class allows a direct move. */
9027 if (mips_dangerous_for_la25_p (x))
9028 return reg_class_subset_p (class, LEA_REGS) ? NO_REGS : LEA_REGS;
9030 regno = true_regnum (x);
9033 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
9034 if (!reg_class_subset_p (class, M16_REGS) && !M16_REG_P (regno))
9037 /* We can't really copy to HI or LO at all in MIPS16 mode. */
9038 if (in_p ? reg_classes_intersect_p (class, ACC_REGS) : ACC_REG_P (regno))
9044 /* Copying from accumulator registers to anywhere other than a general
9045 register requires a temporary general register. */
9046 if (reg_class_subset_p (class, ACC_REGS))
9047 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9048 if (ACC_REG_P (regno))
9049 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9051 /* We can only copy a value to a condition code register from a
9052 floating point register, and even then we require a scratch
9053 floating point register. We can only copy a value out of a
9054 condition code register into a general register. */
9055 if (reg_class_subset_p (class, ST_REGS))
9059 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
9061 if (ST_REG_P (regno))
9065 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9068 if (reg_class_subset_p (class, FP_REGS))
9071 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
9072 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
9073 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
9076 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
9077 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
9080 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
9081 /* We can force the constant to memory and use lwc1
9082 and ldc1. As above, we will use pairs of lwc1s if
9083 ldc1 is not supported. */
9086 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
9087 /* In this case we can use mov.fmt. */
9090 /* Otherwise, we need to reload through an integer register. */
9093 if (FP_REG_P (regno))
9094 return reg_class_subset_p (class, GR_REGS) ? NO_REGS : GR_REGS;
9099 /* SImode values are represented as sign-extended to DImode. */
9102 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
9104 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
9111 mips_valid_pointer_mode (enum machine_mode mode)
9113 return (mode == SImode || (TARGET_64BIT && mode == DImode));
9116 /* Target hook for vector_mode_supported_p. */
9119 mips_vector_mode_supported_p (enum machine_mode mode)
9124 return TARGET_PAIRED_SINGLE_FLOAT;
9141 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
9144 mips_scalar_mode_supported_p (enum machine_mode mode)
9146 if (ALL_FIXED_POINT_MODE_P (mode)
9147 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
9150 return default_scalar_mode_supported_p (mode);
9152 /* This function does three things:
9154 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9155 - Register the mips16 hardware floating point stubs.
9156 - Register the gofast functions if selected using --enable-gofast. */
9158 #include "config/gofast.h"
9161 mips_init_libfuncs (void)
9163 if (TARGET_FIX_VR4120)
9165 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9166 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9169 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
9171 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9172 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9173 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9174 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9176 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9177 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9178 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9179 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9180 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9181 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9182 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
9184 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9185 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9186 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
9188 if (TARGET_DOUBLE_FLOAT)
9190 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9191 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9192 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9193 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9195 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9196 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9197 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9198 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9199 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9200 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9201 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
9203 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9204 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9206 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9207 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9208 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__mips16_floatunsidf");
9212 gofast_maybe_init_libfuncs ();
9215 /* Return the length of INSN. LENGTH is the initial length computed by
9216 attributes in the machine-description file. */
9219 mips_adjust_insn_length (rtx insn, int length)
9221 /* A unconditional jump has an unfilled delay slot if it is not part
9222 of a sequence. A conditional jump normally has a delay slot, but
9223 does not on MIPS16. */
9224 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9227 /* See how many nops might be needed to avoid hardware hazards. */
9228 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9229 switch (get_attr_hazard (insn))
9243 /* All MIPS16 instructions are a measly two bytes. */
9251 /* Return an asm sequence to start a noat block and load the address
9252 of a label into $1. */
9255 mips_output_load_label (void)
9257 if (TARGET_EXPLICIT_RELOCS)
9261 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9264 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9267 if (ISA_HAS_LOAD_DELAY)
9268 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9269 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9273 if (Pmode == DImode)
9274 return "%[dla\t%@,%0";
9276 return "%[la\t%@,%0";
9280 /* Return the assembly code for INSN, which has the operands given by
9281 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9282 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9283 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9284 version of BRANCH_IF_TRUE. */
9287 mips_output_conditional_branch (rtx insn, rtx *operands,
9288 const char *branch_if_true,
9289 const char *branch_if_false)
9291 unsigned int length;
9292 rtx taken, not_taken;
9294 length = get_attr_length (insn);
9297 /* Just a simple conditional branch. */
9298 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9299 return branch_if_true;
9302 /* Generate a reversed branch around a direct jump. This fallback does
9303 not use branch-likely instructions. */
9304 mips_branch_likely = false;
9305 not_taken = gen_label_rtx ();
9306 taken = operands[1];
9308 /* Generate the reversed branch to NOT_TAKEN. */
9309 operands[1] = not_taken;
9310 output_asm_insn (branch_if_false, operands);
9312 /* If INSN has a delay slot, we must provide delay slots for both the
9313 branch to NOT_TAKEN and the conditional jump. We must also ensure
9314 that INSN's delay slot is executed in the appropriate cases. */
9317 /* This first delay slot will always be executed, so use INSN's
9318 delay slot if is not annulled. */
9319 if (!INSN_ANNULLED_BRANCH_P (insn))
9321 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9322 asm_out_file, optimize, 1, NULL);
9323 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9326 output_asm_insn ("nop", 0);
9327 fprintf (asm_out_file, "\n");
9330 /* Output the unconditional branch to TAKEN. */
9332 output_asm_insn ("j\t%0%/", &taken);
9335 output_asm_insn (mips_output_load_label (), &taken);
9336 output_asm_insn ("jr\t%@%]%/", 0);
9339 /* Now deal with its delay slot; see above. */
9342 /* This delay slot will only be executed if the branch is taken.
9343 Use INSN's delay slot if is annulled. */
9344 if (INSN_ANNULLED_BRANCH_P (insn))
9346 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9347 asm_out_file, optimize, 1, NULL);
9348 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9351 output_asm_insn ("nop", 0);
9352 fprintf (asm_out_file, "\n");
9355 /* Output NOT_TAKEN. */
9356 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9357 CODE_LABEL_NUMBER (not_taken));
9361 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9362 if some ordered condition is true. The condition is given by
9363 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9364 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9365 its second is always zero. */
9368 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9370 const char *branch[2];
9372 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9373 Make BRANCH[0] branch on the inverse condition. */
9374 switch (GET_CODE (operands[0]))
9376 /* These cases are equivalent to comparisons against zero. */
9378 inverted_p = !inverted_p;
9381 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9382 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9385 /* These cases are always true or always false. */
9387 inverted_p = !inverted_p;
9390 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9391 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9395 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9396 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9399 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9402 /* Used to output div or ddiv instruction DIVISION, which has the operands
9403 given by OPERANDS. Add in a divide-by-zero check if needed.
9405 When working around R4000 and R4400 errata, we need to make sure that
9406 the division is not immediately followed by a shift[1][2]. We also
9407 need to stop the division from being put into a branch delay slot[3].
9408 The easiest way to avoid both problems is to add a nop after the
9409 division. When a divide-by-zero check is needed, this nop can be
9410 used to fill the branch delay slot.
9412 [1] If a double-word or a variable shift executes immediately
9413 after starting an integer division, the shift may give an
9414 incorrect result. See quotations of errata #16 and #28 from
9415 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9416 in mips.md for details.
9418 [2] A similar bug to [1] exists for all revisions of the
9419 R4000 and the R4400 when run in an MC configuration.
9420 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9422 "19. In this following sequence:
9424 ddiv (or ddivu or div or divu)
9425 dsll32 (or dsrl32, dsra32)
9427 if an MPT stall occurs, while the divide is slipping the cpu
9428 pipeline, then the following double shift would end up with an
9431 Workaround: The compiler needs to avoid generating any
9432 sequence with divide followed by extended double shift."
9434 This erratum is also present in "MIPS R4400MC Errata, Processor
9435 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9436 & 3.0" as errata #10 and #4, respectively.
9438 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9439 (also valid for MIPS R4000MC processors):
9441 "52. R4000SC: This bug does not apply for the R4000PC.
9443 There are two flavors of this bug:
9445 1) If the instruction just after divide takes an RF exception
9446 (tlb-refill, tlb-invalid) and gets an instruction cache
9447 miss (both primary and secondary) and the line which is
9448 currently in secondary cache at this index had the first
9449 data word, where the bits 5..2 are set, then R4000 would
9450 get a wrong result for the div.
9455 ------------------- # end-of page. -tlb-refill
9460 ------------------- # end-of page. -tlb-invalid
9463 2) If the divide is in the taken branch delay slot, where the
9464 target takes RF exception and gets an I-cache miss for the
9465 exception vector or where I-cache miss occurs for the
9466 target address, under the above mentioned scenarios, the
9467 div would get wrong results.
9470 j r2 # to next page mapped or unmapped
9471 div r8,r9 # this bug would be there as long
9472 # as there is an ICache miss and
9473 nop # the "data pattern" is present
9476 beq r0, r0, NextPage # to Next page
9480 This bug is present for div, divu, ddiv, and ddivu
9483 Workaround: For item 1), OS could make sure that the next page
9484 after the divide instruction is also mapped. For item 2), the
9485 compiler could make sure that the divide instruction is not in
9486 the branch delay slot."
9488 These processors have PRId values of 0x00004220 and 0x00004300 for
9489 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9492 mips_output_division (const char *division, rtx *operands)
9497 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9499 output_asm_insn (s, operands);
9502 if (TARGET_CHECK_ZERO_DIV)
9506 output_asm_insn (s, operands);
9507 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9509 else if (GENERATE_DIVIDE_TRAPS)
9511 output_asm_insn (s, operands);
9516 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9517 output_asm_insn (s, operands);
9518 s = "break\t7%)\n1:";
9524 /* Return true if INSN is a multiply-add or multiply-subtract
9525 instruction and PREV assigns to the accumulator operand. */
9528 mips_linked_madd_p (rtx prev, rtx insn)
9532 x = single_set (insn);
9538 if (GET_CODE (x) == PLUS
9539 && GET_CODE (XEXP (x, 0)) == MULT
9540 && reg_set_p (XEXP (x, 1), prev))
9543 if (GET_CODE (x) == MINUS
9544 && GET_CODE (XEXP (x, 1)) == MULT
9545 && reg_set_p (XEXP (x, 0), prev))
9551 /* Implements a store data bypass check. We need this because the cprestore
9552 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9553 default routine to abort. We just return false for that case. */
9554 /* ??? Should try to give a better result here than assuming false. */
9557 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9559 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9562 return ! store_data_bypass_p (out_insn, in_insn);
9565 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9566 dependencies have no cost, except on the 20Kc where output-dependence
9567 is treated like input-dependence. */
9570 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9571 rtx dep ATTRIBUTE_UNUSED, int cost)
9573 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
9576 if (REG_NOTE_KIND (link) != 0)
9581 /* Return the number of instructions that can be issued per cycle. */
9584 mips_issue_rate (void)
9588 case PROCESSOR_74KC:
9589 case PROCESSOR_74KF2_1:
9590 case PROCESSOR_74KF1_1:
9591 case PROCESSOR_74KF3_2:
9592 /* The 74k is not strictly quad-issue cpu, but can be seen as one
9593 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
9594 but in reality only a maximum of 3 insns can be issued as the
9595 floating point load/stores also require a slot in the AGEN pipe. */
9598 case PROCESSOR_20KC:
9599 case PROCESSOR_R4130:
9600 case PROCESSOR_R5400:
9601 case PROCESSOR_R5500:
9602 case PROCESSOR_R7000:
9603 case PROCESSOR_R9000:
9607 case PROCESSOR_SB1A:
9608 /* This is actually 4, but we get better performance if we claim 3.
9609 This is partly because of unwanted speculative code motion with the
9610 larger number, and partly because in most common cases we can't
9611 reach the theoretical max of 4. */
9619 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9620 be as wide as the scheduling freedom in the DFA. */
9623 mips_multipass_dfa_lookahead (void)
9625 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9632 /* Remove the instruction at index LOWER from ready queue READY and
9633 reinsert it in front of the instruction at index HIGHER. LOWER must
9637 mips_promote_ready (rtx *ready, int lower, int higher)
9642 new_head = ready[lower];
9643 for (i = lower; i < higher; i++)
9644 ready[i] = ready[i + 1];
9645 ready[i] = new_head;
9648 /* If the priority of the instruction at POS2 in the ready queue READY
9649 is within LIMIT units of that of the instruction at POS1, swap the
9650 instructions if POS2 is not already less than POS1. */
9653 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
9656 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
9660 ready[pos1] = ready[pos2];
9665 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9666 that may clobber hi or lo. */
9668 static rtx mips_macc_chains_last_hilo;
9670 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9671 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9674 mips_macc_chains_record (rtx insn)
9676 if (get_attr_may_clobber_hilo (insn))
9677 mips_macc_chains_last_hilo = insn;
9680 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9681 has NREADY elements, looking for a multiply-add or multiply-subtract
9682 instruction that is cumulative with mips_macc_chains_last_hilo.
9683 If there is one, promote it ahead of anything else that might
9684 clobber hi or lo. */
9687 mips_macc_chains_reorder (rtx *ready, int nready)
9691 if (mips_macc_chains_last_hilo != 0)
9692 for (i = nready - 1; i >= 0; i--)
9693 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9695 for (j = nready - 1; j > i; j--)
9696 if (recog_memoized (ready[j]) >= 0
9697 && get_attr_may_clobber_hilo (ready[j]))
9699 mips_promote_ready (ready, i, j);
9706 /* The last instruction to be scheduled. */
9708 static rtx vr4130_last_insn;
9710 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9711 points to an rtx that is initially an instruction. Nullify the rtx
9712 if the instruction uses the value of register X. */
9715 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9717 rtx *insn_ptr = data;
9720 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9724 /* Return true if there is true register dependence between vr4130_last_insn
9728 vr4130_true_reg_dependence_p (rtx insn)
9730 note_stores (PATTERN (vr4130_last_insn),
9731 vr4130_true_reg_dependence_p_1, &insn);
9735 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9736 the ready queue and that INSN2 is the instruction after it, return
9737 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9738 in which INSN1 and INSN2 can probably issue in parallel, but for
9739 which (INSN2, INSN1) should be less sensitive to instruction
9740 alignment than (INSN1, INSN2). See 4130.md for more details. */
9743 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9745 sd_iterator_def sd_it;
9748 /* Check for the following case:
9750 1) there is some other instruction X with an anti dependence on INSN1;
9751 2) X has a higher priority than INSN2; and
9752 3) X is an arithmetic instruction (and thus has no unit restrictions).
9754 If INSN1 is the last instruction blocking X, it would better to
9755 choose (INSN1, X) over (INSN2, INSN1). */
9756 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
9757 if (DEP_TYPE (dep) == REG_DEP_ANTI
9758 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
9759 && recog_memoized (DEP_CON (dep)) >= 0
9760 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
9763 if (vr4130_last_insn != 0
9764 && recog_memoized (insn1) >= 0
9765 && recog_memoized (insn2) >= 0)
9767 /* See whether INSN1 and INSN2 use different execution units,
9768 or if they are both ALU-type instructions. If so, they can
9769 probably execute in parallel. */
9770 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9771 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9772 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9774 /* If only one of the instructions has a dependence on
9775 vr4130_last_insn, prefer to schedule the other one first. */
9776 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9777 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9781 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9782 is not an ALU-type instruction and if INSN1 uses the same
9783 execution unit. (Note that if this condition holds, we already
9784 know that INSN2 uses a different execution unit.) */
9785 if (class1 != VR4130_CLASS_ALU
9786 && recog_memoized (vr4130_last_insn) >= 0
9787 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9794 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9795 queue with at least two instructions. Swap the first two if
9796 vr4130_swap_insns_p says that it could be worthwhile. */
9799 vr4130_reorder (rtx *ready, int nready)
9801 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9802 mips_promote_ready (ready, nready - 2, nready - 1);
9805 /* Record whether last 74k AGEN instruction was a load or store. */
9807 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
9809 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
9810 resets to TYPE_UNKNOWN state. */
9813 mips_74k_agen_init (rtx insn)
9815 if (!insn || !NONJUMP_INSN_P (insn))
9816 mips_last_74k_agen_insn = TYPE_UNKNOWN;
9817 else if (USEFUL_INSN_P (insn))
9819 enum attr_type type = get_attr_type (insn);
9820 if (type == TYPE_LOAD || type == TYPE_STORE)
9821 mips_last_74k_agen_insn = type;
9825 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
9826 loads to be grouped together, and multiple stores to be grouped
9827 together. Swap things around in the ready queue to make this happen. */
9830 mips_74k_agen_reorder (rtx *ready, int nready)
9833 int store_pos, load_pos;
9838 for (i = nready - 1; i >= 0; i--)
9840 rtx insn = ready[i];
9841 if (USEFUL_INSN_P (insn))
9842 switch (get_attr_type (insn))
9845 if (store_pos == -1)
9859 if (load_pos == -1 || store_pos == -1)
9862 switch (mips_last_74k_agen_insn)
9865 /* Prefer to schedule loads since they have a higher latency. */
9867 /* Swap loads to the front of the queue. */
9868 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
9871 /* Swap stores to the front of the queue. */
9872 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
9879 /* Implement TARGET_SCHED_INIT. */
9882 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9883 int max_ready ATTRIBUTE_UNUSED)
9885 mips_macc_chains_last_hilo = 0;
9886 vr4130_last_insn = 0;
9887 mips_74k_agen_init (NULL_RTX);
9890 /* Implement TARGET_SCHED_REORDER and TARG_SCHED_REORDER2. */
9893 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9894 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
9896 if (!reload_completed
9899 mips_macc_chains_reorder (ready, *nreadyp);
9900 if (reload_completed
9902 && !TARGET_VR4130_ALIGN
9904 vr4130_reorder (ready, *nreadyp);
9906 mips_74k_agen_reorder (ready, *nreadyp);
9907 return mips_issue_rate ();
9910 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9913 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9917 mips_74k_agen_init (insn);
9918 switch (GET_CODE (PATTERN (insn)))
9922 /* Don't count USEs and CLOBBERs against the issue rate. */
9927 if (!reload_completed && TUNE_MACC_CHAINS)
9928 mips_macc_chains_record (insn);
9929 vr4130_last_insn = insn;
9935 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9936 return the first operand of the associated "pref" or "prefx" insn. */
9939 mips_prefetch_cookie (rtx write, rtx locality)
9941 /* store_streamed / load_streamed. */
9942 if (INTVAL (locality) <= 0)
9943 return GEN_INT (INTVAL (write) + 4);
9946 if (INTVAL (locality) <= 2)
9949 /* store_retained / load_retained. */
9950 return GEN_INT (INTVAL (write) + 6);
9953 /* MIPS builtin function support. */
9955 struct builtin_description
9957 /* The code of the main .md file instruction. See mips_builtin_type
9958 for more information. */
9959 enum insn_code icode;
9961 /* The floating-point comparison code to use with ICODE, if any. */
9962 enum mips_fp_condition cond;
9964 /* The name of the builtin function. */
9967 /* Specifies how the function should be expanded. */
9968 enum mips_builtin_type builtin_type;
9970 /* The function's prototype. */
9971 enum mips_function_type function_type;
9973 /* The target flags required for this function. */
9977 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9978 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9979 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9980 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9981 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9983 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9985 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9986 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9987 "__builtin_mips_" #INSN "_" #COND "_s", \
9988 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9989 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9990 "__builtin_mips_" #INSN "_" #COND "_d", \
9991 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9993 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9994 The lower and upper forms require TARGET_FLAGS while the any and all
9995 forms require MASK_MIPS3D. */
9996 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9997 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9998 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9999 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10000 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10001 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10002 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10003 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10004 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10005 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10006 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10007 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10008 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10010 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10011 require MASK_MIPS3D. */
10012 #define CMP_4S_BUILTINS(INSN, COND) \
10013 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10014 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10015 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10017 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10018 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10019 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10022 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10023 instruction requires TARGET_FLAGS. */
10024 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10025 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10026 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10027 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10029 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10030 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10031 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10034 /* Define all the builtins related to c.cond.fmt condition COND. */
10035 #define CMP_BUILTINS(COND) \
10036 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10037 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10038 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10039 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10040 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10041 CMP_4S_BUILTINS (c, COND), \
10042 CMP_4S_BUILTINS (cabs, COND)
10044 static const struct builtin_description mips_bdesc[] =
10046 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10047 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10048 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10049 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10050 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10051 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10052 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10053 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10055 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10056 MASK_PAIRED_SINGLE_FLOAT),
10057 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10058 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10059 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10060 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10062 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10063 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10064 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10065 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10066 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10067 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10069 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10070 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10071 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10072 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10073 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10074 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10076 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10079 /* Builtin functions for the SB-1 processor. */
10081 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10083 static const struct builtin_description sb1_bdesc[] =
10085 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10088 /* Builtin functions for DSP ASE. */
10090 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10091 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10092 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10093 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10094 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
10096 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10097 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10098 builtin_description fields. */
10099 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10100 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10101 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10103 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10104 branch instruction. TARGET_FLAGS is a builtin_description field. */
10105 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10106 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10107 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10109 static const struct builtin_description dsp_bdesc[] =
10111 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10112 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10113 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10114 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10115 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10116 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10117 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10118 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10119 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10120 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10121 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10122 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10123 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10124 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10125 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10126 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10127 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10128 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10129 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10130 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10131 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10132 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10133 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10134 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10135 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10136 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10137 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10138 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10139 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10140 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10141 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10142 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10143 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10144 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10145 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10146 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10147 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10148 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10149 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10150 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10151 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10152 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10153 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10154 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10155 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10156 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10157 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10158 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10159 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10160 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10161 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10162 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10163 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10164 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10165 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10166 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10167 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10168 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10169 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10170 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10171 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10172 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10173 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10174 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, MASK_DSP),
10175 BPOSGE_BUILTIN (32, MASK_DSP),
10177 /* The following are for the MIPS DSP ASE REV 2. */
10178 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
10179 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10180 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10181 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10182 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10183 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10184 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10185 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10186 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10187 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10188 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10189 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10190 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10191 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10192 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10193 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10194 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10195 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
10196 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
10197 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10198 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
10199 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
10200 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10201 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10202 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10203 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
10204 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10205 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10206 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10207 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10208 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10209 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
10210 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
10211 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
10214 static const struct builtin_description dsp_32only_bdesc[] =
10216 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10217 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10218 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10219 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10220 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10221 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10222 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10223 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10224 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10225 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10226 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10227 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10228 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10229 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10230 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10231 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10232 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10233 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10234 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10235 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10236 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10238 /* The following are for the MIPS DSP ASE REV 2. */
10239 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10240 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10241 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10242 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10243 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
10244 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
10245 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10246 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
10247 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
10248 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10249 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10250 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10251 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10252 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
10253 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
10256 /* This helps provide a mapping from builtin function codes to bdesc
10261 /* The builtin function table that this entry describes. */
10262 const struct builtin_description *bdesc;
10264 /* The number of entries in the builtin function table. */
10267 /* The target processor that supports these builtin functions.
10268 PROCESSOR_MAX means we enable them for all processors. */
10269 enum processor_type proc;
10271 /* If the target has these flags, this builtin function table
10272 will not be supported. */
10273 int unsupported_target_flags;
10276 static const struct bdesc_map bdesc_arrays[] =
10278 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
10279 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
10280 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
10281 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
10285 /* MODE is a vector mode whose elements have type TYPE. Return the type
10286 of the vector itself. */
10289 mips_builtin_vector_type (tree type, enum machine_mode mode)
10291 static tree types[(int) MAX_MACHINE_MODE];
10293 if (types[(int) mode] == NULL_TREE)
10294 types[(int) mode] = build_vector_type_for_mode (type, mode);
10295 return types[(int) mode];
10298 /* Source-level argument types. */
10299 #define MIPS_ATYPE_VOID void_type_node
10300 #define MIPS_ATYPE_INT integer_type_node
10301 #define MIPS_ATYPE_POINTER ptr_type_node
10303 /* Standard mode-based argument types. */
10304 #define MIPS_ATYPE_SI intSI_type_node
10305 #define MIPS_ATYPE_USI unsigned_intSI_type_node
10306 #define MIPS_ATYPE_DI intDI_type_node
10307 #define MIPS_ATYPE_SF float_type_node
10308 #define MIPS_ATYPE_DF double_type_node
10310 /* Vector argument types. */
10311 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
10312 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
10313 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
10315 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
10316 their associated MIPS_ATYPEs. */
10317 #define MIPS_FTYPE_ATYPES1(A, B) \
10318 MIPS_ATYPE_##A, MIPS_ATYPE_##B
10320 #define MIPS_FTYPE_ATYPES2(A, B, C) \
10321 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
10323 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
10324 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
10326 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
10327 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
10330 /* Return the function type associated with function prototype TYPE. */
10333 mips_build_function_type (enum mips_function_type type)
10335 static tree types[(int) MIPS_MAX_FTYPE_MAX];
10337 if (types[(int) type] == NULL_TREE)
10340 #define DEF_MIPS_FTYPE(NUM, ARGS) \
10341 case MIPS_FTYPE_NAME##NUM ARGS: \
10342 types[(int) type] \
10343 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
10346 #include "config/mips/mips-ftypes.def"
10347 #undef DEF_MIPS_FTYPE
10349 gcc_unreachable ();
10352 return types[(int) type];
10355 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10358 mips_init_builtins (void)
10360 const struct builtin_description *d;
10361 const struct bdesc_map *m;
10362 unsigned int offset;
10364 /* Iterate through all of the bdesc arrays, initializing all of the
10365 builtin functions. */
10368 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10370 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10371 && (m->unsupported_target_flags & target_flags) == 0)
10372 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10373 if ((d->target_flags & target_flags) == d->target_flags)
10374 add_builtin_function (d->name,
10375 mips_build_function_type (d->function_type),
10376 d - m->bdesc + offset,
10377 BUILT_IN_MD, NULL, NULL);
10382 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
10383 suitable for input operand OP of instruction ICODE. Return the value. */
10386 mips_prepare_builtin_arg (enum insn_code icode,
10387 unsigned int op, tree exp, unsigned int argnum)
10390 enum machine_mode mode;
10392 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
10393 mode = insn_data[icode].operand[op].mode;
10394 if (!insn_data[icode].operand[op].predicate (value, mode))
10396 value = copy_to_mode_reg (mode, value);
10397 /* Check the predicate again. */
10398 if (!insn_data[icode].operand[op].predicate (value, mode))
10400 error ("invalid argument to builtin function");
10408 /* Return an rtx suitable for output operand OP of instruction ICODE.
10409 If TARGET is non-null, try to use it where possible. */
10412 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10414 enum machine_mode mode;
10416 mode = insn_data[icode].operand[op].mode;
10417 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10418 target = gen_reg_rtx (mode);
10423 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10424 .md pattern and CALL is the function expr with arguments. TARGET,
10425 if nonnull, suggests a good place to put the result.
10426 HAS_TARGET indicates the function must return something. */
10429 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
10432 rtx ops[MAX_RECOG_OPERANDS];
10438 /* We save target to ops[0]. */
10439 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10443 /* We need to test if the arglist is not zero. Some instructions have extra
10444 clobber registers. */
10445 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
10446 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
10451 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10455 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10459 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10463 gcc_unreachable ();
10468 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10469 function (TYPE says which). EXP is the tree for the function
10470 function, ICODE is the instruction that should be used to compare
10471 the first two arguments, and COND is the condition it should test.
10472 TARGET, if nonnull, suggests a good place to put the result. */
10475 mips_expand_builtin_movtf (enum mips_builtin_type type,
10476 enum insn_code icode, enum mips_fp_condition cond,
10477 rtx target, tree exp)
10479 rtx cmp_result, op0, op1;
10481 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10482 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
10483 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
10484 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10486 icode = CODE_FOR_mips_cond_move_tf_ps;
10487 target = mips_prepare_builtin_target (icode, 0, target);
10488 if (type == MIPS_BUILTIN_MOVT)
10490 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
10491 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
10495 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
10496 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
10498 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10502 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10503 into TARGET otherwise. Return TARGET. */
10506 mips_builtin_branch_and_move (rtx condition, rtx target,
10507 rtx value_if_true, rtx value_if_false)
10509 rtx true_label, done_label;
10511 true_label = gen_label_rtx ();
10512 done_label = gen_label_rtx ();
10514 /* First assume that CONDITION is false. */
10515 mips_emit_move (target, value_if_false);
10517 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10518 emit_jump_insn (gen_condjump (condition, true_label));
10519 emit_jump_insn (gen_jump (done_label));
10522 /* Fix TARGET if CONDITION is true. */
10523 emit_label (true_label);
10524 mips_emit_move (target, value_if_true);
10526 emit_label (done_label);
10530 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10531 of the comparison instruction and COND is the condition it should test.
10532 EXP is the function call and arguments and TARGET, if nonnull,
10533 suggests a good place to put the boolean result. */
10536 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10537 enum insn_code icode, enum mips_fp_condition cond,
10538 rtx target, tree exp)
10540 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10544 if (target == 0 || GET_MODE (target) != SImode)
10545 target = gen_reg_rtx (SImode);
10547 /* Prepare the operands to the comparison. */
10548 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10549 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
10550 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
10552 switch (insn_data[icode].n_operands)
10555 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10559 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10560 ops[3], ops[4], GEN_INT (cond)));
10564 gcc_unreachable ();
10567 /* If the comparison sets more than one register, we define the result
10568 to be 0 if all registers are false and -1 if all registers are true.
10569 The value of the complete result is indeterminate otherwise. */
10570 switch (builtin_type)
10572 case MIPS_BUILTIN_CMP_ALL:
10573 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10574 return mips_builtin_branch_and_move (condition, target,
10575 const0_rtx, const1_rtx);
10577 case MIPS_BUILTIN_CMP_UPPER:
10578 case MIPS_BUILTIN_CMP_LOWER:
10579 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10580 condition = gen_single_cc (cmp_result, offset);
10581 return mips_builtin_branch_and_move (condition, target,
10582 const1_rtx, const0_rtx);
10585 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10586 return mips_builtin_branch_and_move (condition, target,
10587 const1_rtx, const0_rtx);
10591 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10592 suggests a good place to put the boolean result. */
10595 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10597 rtx condition, cmp_result;
10600 if (target == 0 || GET_MODE (target) != SImode)
10601 target = gen_reg_rtx (SImode);
10603 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10605 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10610 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10611 return mips_builtin_branch_and_move (condition, target,
10612 const1_rtx, const0_rtx);
10615 /* EXP is a CALL_EXPR that calls the function described by BDESC.
10616 Expand the call and return an rtx for its return value.
10617 TARGET, if nonnull, suggests a good place to put this value. */
10620 mips_expand_builtin_1 (const struct builtin_description *bdesc,
10621 tree exp, rtx target)
10623 switch (bdesc->builtin_type)
10625 case MIPS_BUILTIN_DIRECT:
10626 return mips_expand_builtin_direct (bdesc->icode, target, exp, true);
10628 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10629 return mips_expand_builtin_direct (bdesc->icode, target, exp, false);
10631 case MIPS_BUILTIN_MOVT:
10632 case MIPS_BUILTIN_MOVF:
10633 return mips_expand_builtin_movtf (bdesc->builtin_type, bdesc->icode,
10634 bdesc->cond, target, exp);
10636 case MIPS_BUILTIN_CMP_ANY:
10637 case MIPS_BUILTIN_CMP_ALL:
10638 case MIPS_BUILTIN_CMP_UPPER:
10639 case MIPS_BUILTIN_CMP_LOWER:
10640 case MIPS_BUILTIN_CMP_SINGLE:
10641 return mips_expand_builtin_compare (bdesc->builtin_type, bdesc->icode,
10642 bdesc->cond, target, exp);
10644 case MIPS_BUILTIN_BPOSGE32:
10645 return mips_expand_builtin_bposge (bdesc->builtin_type, target);
10647 gcc_unreachable ();
10650 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10653 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10654 enum machine_mode mode ATTRIBUTE_UNUSED,
10655 int ignore ATTRIBUTE_UNUSED)
10658 unsigned int fcode;
10659 const struct bdesc_map *m;
10661 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10662 fcode = DECL_FUNCTION_CODE (fndecl);
10666 error ("built-in function %qs not supported for MIPS16",
10667 IDENTIFIER_POINTER (DECL_NAME (fndecl)));
10671 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10673 if (fcode < m->size)
10674 return mips_expand_builtin_1 (m->bdesc + fcode, exp, target);
10677 gcc_unreachable ();
10680 /* An entry in the mips16 constant pool. VALUE is the pool constant,
10681 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
10683 struct mips16_constant {
10684 struct mips16_constant *next;
10687 enum machine_mode mode;
10690 /* Information about an incomplete mips16 constant pool. FIRST is the
10691 first constant, HIGHEST_ADDRESS is the highest address that the first
10692 byte of the pool can have, and INSN_ADDRESS is the current instruction
10695 struct mips16_constant_pool {
10696 struct mips16_constant *first;
10697 int highest_address;
10701 /* Add constant VALUE to POOL and return its label. MODE is the
10702 value's mode (used for CONST_INTs, etc.). */
10705 add_constant (struct mips16_constant_pool *pool,
10706 rtx value, enum machine_mode mode)
10708 struct mips16_constant **p, *c;
10709 bool first_of_size_p;
10711 /* See whether the constant is already in the pool. If so, return the
10712 existing label, otherwise leave P pointing to the place where the
10713 constant should be added.
10715 Keep the pool sorted in increasing order of mode size so that we can
10716 reduce the number of alignments needed. */
10717 first_of_size_p = true;
10718 for (p = &pool->first; *p != 0; p = &(*p)->next)
10720 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
10721 return (*p)->label;
10722 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
10724 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
10725 first_of_size_p = false;
10728 /* In the worst case, the constant needed by the earliest instruction
10729 will end up at the end of the pool. The entire pool must then be
10730 accessible from that instruction.
10732 When adding the first constant, set the pool's highest address to
10733 the address of the first out-of-range byte. Adjust this address
10734 downwards each time a new constant is added. */
10735 if (pool->first == 0)
10736 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
10737 is the address of the instruction with the lowest two bits clear.
10738 The base PC value for ld has the lowest three bits clear. Assume
10739 the worst case here. */
10740 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
10741 pool->highest_address -= GET_MODE_SIZE (mode);
10742 if (first_of_size_p)
10743 /* Take into account the worst possible padding due to alignment. */
10744 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
10746 /* Create a new entry. */
10747 c = (struct mips16_constant *) xmalloc (sizeof *c);
10750 c->label = gen_label_rtx ();
10757 /* Output constant VALUE after instruction INSN and return the last
10758 instruction emitted. MODE is the mode of the constant. */
10761 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
10763 if (SCALAR_INT_MODE_P (mode)
10764 || ALL_SCALAR_FRACT_MODE_P (mode)
10765 || ALL_SCALAR_ACCUM_MODE_P (mode))
10767 rtx size = GEN_INT (GET_MODE_SIZE (mode));
10768 return emit_insn_after (gen_consttable_int (value, size), insn);
10771 if (SCALAR_FLOAT_MODE_P (mode))
10772 return emit_insn_after (gen_consttable_float (value), insn);
10774 if (VECTOR_MODE_P (mode))
10778 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
10779 insn = dump_constants_1 (GET_MODE_INNER (mode),
10780 CONST_VECTOR_ELT (value, i), insn);
10784 gcc_unreachable ();
10788 /* Dump out the constants in CONSTANTS after INSN. */
10791 dump_constants (struct mips16_constant *constants, rtx insn)
10793 struct mips16_constant *c, *next;
10797 for (c = constants; c != NULL; c = next)
10799 /* If necessary, increase the alignment of PC. */
10800 if (align < GET_MODE_SIZE (c->mode))
10802 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
10803 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
10805 align = GET_MODE_SIZE (c->mode);
10807 insn = emit_label_after (c->label, insn);
10808 insn = dump_constants_1 (c->mode, c->value, insn);
10814 emit_barrier_after (insn);
10817 /* Return the length of instruction INSN. */
10820 mips16_insn_length (rtx insn)
10824 rtx body = PATTERN (insn);
10825 if (GET_CODE (body) == ADDR_VEC)
10826 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
10827 if (GET_CODE (body) == ADDR_DIFF_VEC)
10828 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
10830 return get_attr_length (insn);
10833 /* If *X is a symbolic constant that refers to the constant pool, add
10834 the constant to POOL and rewrite *X to use the constant's label. */
10837 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
10839 rtx base, offset, label;
10841 split_const (*x, &base, &offset);
10842 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
10844 label = add_constant (pool, get_pool_constant (base),
10845 get_pool_mode (base));
10846 base = gen_rtx_LABEL_REF (Pmode, label);
10847 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
10851 /* This structure is used to communicate with mips16_rewrite_pool_refs.
10852 INSN is the instruction we're rewriting and POOL points to the current
10854 struct mips16_rewrite_pool_refs_info {
10856 struct mips16_constant_pool *pool;
10859 /* Rewrite *X so that constant pool references refer to the constant's
10860 label instead. DATA points to a mips16_rewrite_pool_refs_info
10864 mips16_rewrite_pool_refs (rtx *x, void *data)
10866 struct mips16_rewrite_pool_refs_info *info = data;
10868 if (force_to_mem_operand (*x, Pmode))
10870 rtx mem = force_const_mem (GET_MODE (*x), *x);
10871 validate_change (info->insn, x, mem, false);
10876 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
10880 if (TARGET_MIPS16_TEXT_LOADS)
10881 mips16_rewrite_pool_constant (info->pool, x);
10883 return GET_CODE (*x) == CONST ? -1 : 0;
10886 /* Build MIPS16 constant pools. */
10889 mips16_lay_out_constants (void)
10891 struct mips16_constant_pool pool;
10892 struct mips16_rewrite_pool_refs_info info;
10895 if (!TARGET_MIPS16_PCREL_LOADS)
10899 memset (&pool, 0, sizeof (pool));
10900 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10902 /* Rewrite constant pool references in INSN. */
10907 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
10910 pool.insn_address += mips16_insn_length (insn);
10912 if (pool.first != NULL)
10914 /* If there are no natural barriers between the first user of
10915 the pool and the highest acceptable address, we'll need to
10916 create a new instruction to jump around the constant pool.
10917 In the worst case, this instruction will be 4 bytes long.
10919 If it's too late to do this transformation after INSN,
10920 do it immediately before INSN. */
10921 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
10925 label = gen_label_rtx ();
10927 jump = emit_jump_insn_before (gen_jump (label), insn);
10928 JUMP_LABEL (jump) = label;
10929 LABEL_NUSES (label) = 1;
10930 barrier = emit_barrier_after (jump);
10932 emit_label_after (label, barrier);
10933 pool.insn_address += 4;
10936 /* See whether the constant pool is now out of range of the first
10937 user. If so, output the constants after the previous barrier.
10938 Note that any instructions between BARRIER and INSN (inclusive)
10939 will use negative offsets to refer to the pool. */
10940 if (pool.insn_address > pool.highest_address)
10942 dump_constants (pool.first, barrier);
10946 else if (BARRIER_P (insn))
10950 dump_constants (pool.first, get_last_insn ());
10953 /* A temporary variable used by for_each_rtx callbacks, etc. */
10954 static rtx mips_sim_insn;
10956 /* A structure representing the state of the processor pipeline.
10957 Used by the mips_sim_* family of functions. */
10959 /* The maximum number of instructions that can be issued in a cycle.
10960 (Caches mips_issue_rate.) */
10961 unsigned int issue_rate;
10963 /* The current simulation time. */
10966 /* How many more instructions can be issued in the current cycle. */
10967 unsigned int insns_left;
10969 /* LAST_SET[X].INSN is the last instruction to set register X.
10970 LAST_SET[X].TIME is the time at which that instruction was issued.
10971 INSN is null if no instruction has yet set register X. */
10975 } last_set[FIRST_PSEUDO_REGISTER];
10977 /* The pipeline's current DFA state. */
10981 /* Reset STATE to the initial simulation state. */
10984 mips_sim_reset (struct mips_sim *state)
10987 state->insns_left = state->issue_rate;
10988 memset (&state->last_set, 0, sizeof (state->last_set));
10989 state_reset (state->dfa_state);
10992 /* Initialize STATE before its first use. DFA_STATE points to an
10993 allocated but uninitialized DFA state. */
10996 mips_sim_init (struct mips_sim *state, state_t dfa_state)
10998 state->issue_rate = mips_issue_rate ();
10999 state->dfa_state = dfa_state;
11000 mips_sim_reset (state);
11003 /* Advance STATE by one clock cycle. */
11006 mips_sim_next_cycle (struct mips_sim *state)
11009 state->insns_left = state->issue_rate;
11010 state_transition (state->dfa_state, 0);
11013 /* Advance simulation state STATE until instruction INSN can read
11017 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
11021 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
11022 if (state->last_set[REGNO (reg) + i].insn != 0)
11026 t = state->last_set[REGNO (reg) + i].time;
11027 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
11028 while (state->time < t)
11029 mips_sim_next_cycle (state);
11033 /* A for_each_rtx callback. If *X is a register, advance simulation state
11034 DATA until mips_sim_insn can read the register's value. */
11037 mips_sim_wait_regs_2 (rtx *x, void *data)
11040 mips_sim_wait_reg (data, mips_sim_insn, *x);
11044 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
11047 mips_sim_wait_regs_1 (rtx *x, void *data)
11049 for_each_rtx (x, mips_sim_wait_regs_2, data);
11052 /* Advance simulation state STATE until all of INSN's register
11053 dependencies are satisfied. */
11056 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
11058 mips_sim_insn = insn;
11059 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
11062 /* Advance simulation state STATE until the units required by
11063 instruction INSN are available. */
11066 mips_sim_wait_units (struct mips_sim *state, rtx insn)
11070 tmp_state = alloca (state_size ());
11071 while (state->insns_left == 0
11072 || (memcpy (tmp_state, state->dfa_state, state_size ()),
11073 state_transition (tmp_state, insn) >= 0))
11074 mips_sim_next_cycle (state);
11077 /* Advance simulation state STATE until INSN is ready to issue. */
11080 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
11082 mips_sim_wait_regs (state, insn);
11083 mips_sim_wait_units (state, insn);
11086 /* mips_sim_insn has just set X. Update the LAST_SET array
11087 in simulation state DATA. */
11090 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
11092 struct mips_sim *state;
11097 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
11099 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
11100 state->last_set[REGNO (x) + i].time = state->time;
11104 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
11105 can issue immediately (i.e., that mips_sim_wait_insn has already
11109 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
11111 state_transition (state->dfa_state, insn);
11112 state->insns_left--;
11114 mips_sim_insn = insn;
11115 note_stores (PATTERN (insn), mips_sim_record_set, state);
11118 /* Simulate issuing a NOP in state STATE. */
11121 mips_sim_issue_nop (struct mips_sim *state)
11123 if (state->insns_left == 0)
11124 mips_sim_next_cycle (state);
11125 state->insns_left--;
11128 /* Update simulation state STATE so that it's ready to accept the instruction
11129 after INSN. INSN should be part of the main rtl chain, not a member of a
11133 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
11135 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
11137 mips_sim_issue_nop (state);
11139 switch (GET_CODE (SEQ_BEGIN (insn)))
11143 /* We can't predict the processor state after a call or label. */
11144 mips_sim_reset (state);
11148 /* The delay slots of branch likely instructions are only executed
11149 when the branch is taken. Therefore, if the caller has simulated
11150 the delay slot instruction, STATE does not really reflect the state
11151 of the pipeline for the instruction after the delay slot. Also,
11152 branch likely instructions tend to incur a penalty when not taken,
11153 so there will probably be an extra delay between the branch and
11154 the instruction after the delay slot. */
11155 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
11156 mips_sim_reset (state);
11164 /* The VR4130 pipeline issues aligned pairs of instructions together,
11165 but it stalls the second instruction if it depends on the first.
11166 In order to cut down the amount of logic required, this dependence
11167 check is not based on a full instruction decode. Instead, any non-SPECIAL
11168 instruction is assumed to modify the register specified by bits 20-16
11169 (which is usually the "rt" field).
11171 In beq, beql, bne and bnel instructions, the rt field is actually an
11172 input, so we can end up with a false dependence between the branch
11173 and its delay slot. If this situation occurs in instruction INSN,
11174 try to avoid it by swapping rs and rt. */
11177 vr4130_avoid_branch_rt_conflict (rtx insn)
11181 first = SEQ_BEGIN (insn);
11182 second = SEQ_END (insn);
11184 && NONJUMP_INSN_P (second)
11185 && GET_CODE (PATTERN (first)) == SET
11186 && GET_CODE (SET_DEST (PATTERN (first))) == PC
11187 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
11189 /* Check for the right kind of condition. */
11190 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
11191 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
11192 && REG_P (XEXP (cond, 0))
11193 && REG_P (XEXP (cond, 1))
11194 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
11195 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
11197 /* SECOND mentions the rt register but not the rs register. */
11198 rtx tmp = XEXP (cond, 0);
11199 XEXP (cond, 0) = XEXP (cond, 1);
11200 XEXP (cond, 1) = tmp;
11205 /* Implement -mvr4130-align. Go through each basic block and simulate the
11206 processor pipeline. If we find that a pair of instructions could execute
11207 in parallel, and the first of those instruction is not 8-byte aligned,
11208 insert a nop to make it aligned. */
11211 vr4130_align_insns (void)
11213 struct mips_sim state;
11214 rtx insn, subinsn, last, last2, next;
11219 /* LAST is the last instruction before INSN to have a nonzero length.
11220 LAST2 is the last such instruction before LAST. */
11224 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
11227 mips_sim_init (&state, alloca (state_size ()));
11228 for (insn = get_insns (); insn != 0; insn = next)
11230 unsigned int length;
11232 next = NEXT_INSN (insn);
11234 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
11235 This isn't really related to the alignment pass, but we do it on
11236 the fly to avoid a separate instruction walk. */
11237 vr4130_avoid_branch_rt_conflict (insn);
11239 if (USEFUL_INSN_P (insn))
11240 FOR_EACH_SUBINSN (subinsn, insn)
11242 mips_sim_wait_insn (&state, subinsn);
11244 /* If we want this instruction to issue in parallel with the
11245 previous one, make sure that the previous instruction is
11246 aligned. There are several reasons why this isn't worthwhile
11247 when the second instruction is a call:
11249 - Calls are less likely to be performance critical,
11250 - There's a good chance that the delay slot can execute
11251 in parallel with the call.
11252 - The return address would then be unaligned.
11254 In general, if we're going to insert a nop between instructions
11255 X and Y, it's better to insert it immediately after X. That
11256 way, if the nop makes Y aligned, it will also align any labels
11257 between X and Y. */
11258 if (state.insns_left != state.issue_rate
11259 && !CALL_P (subinsn))
11261 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
11263 /* SUBINSN is the first instruction in INSN and INSN is
11264 aligned. We want to align the previous instruction
11265 instead, so insert a nop between LAST2 and LAST.
11267 Note that LAST could be either a single instruction
11268 or a branch with a delay slot. In the latter case,
11269 LAST, like INSN, is already aligned, but the delay
11270 slot must have some extra delay that stops it from
11271 issuing at the same time as the branch. We therefore
11272 insert a nop before the branch in order to align its
11274 emit_insn_after (gen_nop (), last2);
11277 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
11279 /* SUBINSN is the delay slot of INSN, but INSN is
11280 currently unaligned. Insert a nop between
11281 LAST and INSN to align it. */
11282 emit_insn_after (gen_nop (), last);
11286 mips_sim_issue_insn (&state, subinsn);
11288 mips_sim_finish_insn (&state, insn);
11290 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
11291 length = get_attr_length (insn);
11294 /* If the instruction is an asm statement or multi-instruction
11295 mips.md patern, the length is only an estimate. Insert an
11296 8 byte alignment after it so that the following instructions
11297 can be handled correctly. */
11298 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
11299 && (recog_memoized (insn) < 0 || length >= 8))
11301 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
11302 next = NEXT_INSN (next);
11303 mips_sim_next_cycle (&state);
11306 else if (length & 4)
11307 aligned_p = !aligned_p;
11312 /* See whether INSN is an aligned label. */
11313 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
11319 /* Subroutine of mips_reorg. If there is a hazard between INSN
11320 and a previous instruction, avoid it by inserting nops after
11323 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
11324 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
11325 before using the value of that register. *HILO_DELAY counts the
11326 number of instructions since the last hilo hazard (that is,
11327 the number of instructions since the last mflo or mfhi).
11329 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
11330 for the next instruction.
11332 LO_REG is an rtx for the LO register, used in dependence checking. */
11335 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
11336 rtx *delayed_reg, rtx lo_reg)
11339 int nops, ninsns, hazard_set;
11341 if (!INSN_P (insn))
11344 pattern = PATTERN (insn);
11346 /* Do not put the whole function in .set noreorder if it contains
11347 an asm statement. We don't know whether there will be hazards
11348 between the asm statement and the gcc-generated code. */
11349 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
11350 cfun->machine->all_noreorder_p = false;
11352 /* Ignore zero-length instructions (barriers and the like). */
11353 ninsns = get_attr_length (insn) / 4;
11357 /* Work out how many nops are needed. Note that we only care about
11358 registers that are explicitly mentioned in the instruction's pattern.
11359 It doesn't matter that calls use the argument registers or that they
11360 clobber hi and lo. */
11361 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
11362 nops = 2 - *hilo_delay;
11363 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
11368 /* Insert the nops between this instruction and the previous one.
11369 Each new nop takes us further from the last hilo hazard. */
11370 *hilo_delay += nops;
11372 emit_insn_after (gen_hazard_nop (), after);
11374 /* Set up the state for the next instruction. */
11375 *hilo_delay += ninsns;
11377 if (INSN_CODE (insn) >= 0)
11378 switch (get_attr_hazard (insn))
11388 hazard_set = (int) get_attr_hazard_set (insn);
11389 if (hazard_set == 0)
11390 set = single_set (insn);
11393 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL);
11394 set = XVECEXP (PATTERN (insn), 0, hazard_set - 1);
11396 gcc_assert (set && GET_CODE (set) == SET);
11397 *delayed_reg = SET_DEST (set);
11403 /* Go through the instruction stream and insert nops where necessary.
11404 See if the whole function can then be put into .set noreorder &
11408 mips_avoid_hazards (void)
11410 rtx insn, last_insn, lo_reg, delayed_reg;
11413 /* Force all instructions to be split into their final form. */
11414 split_all_insns_noflow ();
11416 /* Recalculate instruction lengths without taking nops into account. */
11417 cfun->machine->ignore_hazard_length_p = true;
11418 shorten_branches (get_insns ());
11420 cfun->machine->all_noreorder_p = true;
11422 /* Profiled functions can't be all noreorder because the profiler
11423 support uses assembler macros. */
11424 if (current_function_profile)
11425 cfun->machine->all_noreorder_p = false;
11427 /* Code compiled with -mfix-vr4120 can't be all noreorder because
11428 we rely on the assembler to work around some errata. */
11429 if (TARGET_FIX_VR4120)
11430 cfun->machine->all_noreorder_p = false;
11432 /* The same is true for -mfix-vr4130 if we might generate mflo or
11433 mfhi instructions. Note that we avoid using mflo and mfhi if
11434 the VR4130 macc and dmacc instructions are available instead;
11435 see the *mfhilo_{si,di}_macc patterns. */
11436 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
11437 cfun->machine->all_noreorder_p = false;
11442 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
11444 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11447 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
11448 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
11449 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
11450 &hilo_delay, &delayed_reg, lo_reg);
11452 mips_avoid_hazard (last_insn, insn, &hilo_delay,
11453 &delayed_reg, lo_reg);
11460 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
11465 mips16_lay_out_constants ();
11466 if (TARGET_EXPLICIT_RELOCS)
11468 if (mips_flag_delayed_branch)
11469 dbr_schedule (get_insns ());
11470 mips_avoid_hazards ();
11471 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
11472 vr4130_align_insns ();
11476 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
11477 in order to avoid duplicating too much logic from elsewhere. */
11480 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
11481 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
11484 rtx this, temp1, temp2, insn, fnaddr;
11485 bool use_sibcall_p;
11487 /* Pretend to be a post-reload pass while generating rtl. */
11488 reload_completed = 1;
11490 /* Mark the end of the (empty) prologue. */
11491 emit_note (NOTE_INSN_PROLOGUE_END);
11493 /* Determine if we can use a sibcall to call FUNCTION directly. */
11494 fnaddr = XEXP (DECL_RTL (function), 0);
11495 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
11496 && const_call_insn_operand (fnaddr, Pmode));
11498 /* Determine if we need to load FNADDR from the GOT. */
11499 if (!use_sibcall_p)
11500 switch (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))
11502 case SYMBOL_GOT_PAGE_OFST:
11503 case SYMBOL_GOT_DISP:
11504 /* Pick a global pointer. Use a call-clobbered register if
11505 TARGET_CALL_SAVED_GP. */
11506 cfun->machine->global_pointer =
11507 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
11508 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11510 /* Set up the global pointer for n32 or n64 abicalls. */
11511 mips_emit_loadgp ();
11518 /* We need two temporary registers in some cases. */
11519 temp1 = gen_rtx_REG (Pmode, 2);
11520 temp2 = gen_rtx_REG (Pmode, 3);
11522 /* Find out which register contains the "this" pointer. */
11523 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
11524 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
11526 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
11528 /* Add DELTA to THIS. */
11531 rtx offset = GEN_INT (delta);
11532 if (!SMALL_OPERAND (delta))
11534 mips_emit_move (temp1, offset);
11537 emit_insn (gen_add3_insn (this, this, offset));
11540 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
11541 if (vcall_offset != 0)
11545 /* Set TEMP1 to *THIS. */
11546 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this));
11548 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
11549 addr = mips_add_offset (temp2, temp1, vcall_offset);
11551 /* Load the offset and add it to THIS. */
11552 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
11553 emit_insn (gen_add3_insn (this, this, temp1));
11556 /* Jump to the target function. Use a sibcall if direct jumps are
11557 allowed, otherwise load the address into a register first. */
11560 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
11561 SIBLING_CALL_P (insn) = 1;
11565 /* This is messy. gas treats "la $25,foo" as part of a call
11566 sequence and may allow a global "foo" to be lazily bound.
11567 The general move patterns therefore reject this combination.
11569 In this context, lazy binding would actually be OK
11570 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
11571 TARGET_CALL_SAVED_GP; see mips_load_call_address.
11572 We must therefore load the address via a temporary
11573 register if mips_dangerous_for_la25_p.
11575 If we jump to the temporary register rather than $25, the assembler
11576 can use the move insn to fill the jump's delay slot. */
11577 if (TARGET_USE_PIC_FN_ADDR_REG
11578 && !mips_dangerous_for_la25_p (fnaddr))
11579 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
11580 mips_load_call_address (temp1, fnaddr, true);
11582 if (TARGET_USE_PIC_FN_ADDR_REG
11583 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
11584 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
11585 emit_jump_insn (gen_indirect_jump (temp1));
11588 /* Run just enough of rest_of_compilation. This sequence was
11589 "borrowed" from alpha.c. */
11590 insn = get_insns ();
11591 insn_locators_alloc ();
11592 split_all_insns_noflow ();
11593 mips16_lay_out_constants ();
11594 shorten_branches (insn);
11595 final_start_function (insn, file, 1);
11596 final (insn, file, 1);
11597 final_end_function ();
11599 /* Clean up the vars set above. Note that final_end_function resets
11600 the global pointer for us. */
11601 reload_completed = 0;
11604 static GTY(()) int was_mips16_p = -1;
11606 /* Set up the target-dependent global state so that it matches the
11607 current function's ISA mode. */
11610 mips_set_mips16_mode (int mips16_p)
11612 if (mips16_p == was_mips16_p)
11615 /* Restore base settings of various flags. */
11616 target_flags = mips_base_target_flags;
11617 flag_delayed_branch = mips_flag_delayed_branch;
11618 flag_schedule_insns = mips_base_schedule_insns;
11619 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
11620 flag_move_loop_invariants = mips_base_move_loop_invariants;
11621 align_loops = mips_base_align_loops;
11622 align_jumps = mips_base_align_jumps;
11623 align_functions = mips_base_align_functions;
11627 /* Select mips16 instruction set. */
11628 target_flags |= MASK_MIPS16;
11630 /* Don't run the scheduler before reload, since it tends to
11631 increase register pressure. */
11632 flag_schedule_insns = 0;
11634 /* Don't do hot/cold partitioning. The constant layout code expects
11635 the whole function to be in a single section. */
11636 flag_reorder_blocks_and_partition = 0;
11638 /* Don't move loop invariants, because it tends to increase
11639 register pressure. It also introduces an extra move in cases
11640 where the constant is the first operand in a two-operand binary
11641 instruction, or when it forms a register argument to a functon
11643 flag_move_loop_invariants = 0;
11645 /* Silently disable -mexplicit-relocs since it doesn't apply
11646 to mips16 code. Even so, it would overly pedantic to warn
11647 about "-mips16 -mexplicit-relocs", especially given that
11648 we use a %gprel() operator. */
11649 target_flags &= ~MASK_EXPLICIT_RELOCS;
11651 /* Experiments suggest we get the best overall results from using
11652 the range of an unextended lw or sw. Code that makes heavy use
11653 of byte or short accesses can do better with ranges of 0...31
11654 and 0...63 respectively, but most code is sensitive to the range
11655 of lw and sw instead. */
11656 targetm.min_anchor_offset = 0;
11657 targetm.max_anchor_offset = 127;
11659 if (flag_pic || TARGET_ABICALLS)
11660 sorry ("MIPS16 PIC");
11664 /* Reset to select base non-mips16 ISA. */
11665 target_flags &= ~MASK_MIPS16;
11667 /* When using explicit relocs, we call dbr_schedule from within
11669 if (TARGET_EXPLICIT_RELOCS)
11670 flag_delayed_branch = 0;
11672 /* Provide default values for align_* for 64-bit targets. */
11675 if (align_loops == 0)
11677 if (align_jumps == 0)
11679 if (align_functions == 0)
11680 align_functions = 8;
11683 targetm.min_anchor_offset = -32768;
11684 targetm.max_anchor_offset = 32767;
11687 /* (Re)initialize mips target internals for new ISA. */
11688 mips_init_split_addresses ();
11689 mips_init_relocs ();
11691 if (was_mips16_p >= 0)
11692 /* Reinitialize target-dependent state. */
11695 was_mips16_p = TARGET_MIPS16;
11698 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
11699 function should use the MIPS16 ISA and switch modes accordingly. */
11702 mips_set_current_function (tree fndecl)
11704 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
11707 /* Allocate a chunk of memory for per-function machine-dependent data. */
11708 static struct machine_function *
11709 mips_init_machine_status (void)
11711 return ((struct machine_function *)
11712 ggc_alloc_cleared (sizeof (struct machine_function)));
11715 /* Return the processor associated with the given ISA level, or null
11716 if the ISA isn't valid. */
11718 static const struct mips_cpu_info *
11719 mips_cpu_info_from_isa (int isa)
11723 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11724 if (mips_cpu_info_table[i].isa == isa)
11725 return mips_cpu_info_table + i;
11730 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
11731 with a final "000" replaced by "k". Ignore case.
11733 Note: this function is shared between GCC and GAS. */
11736 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
11738 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
11739 given++, canonical++;
11741 return ((*given == 0 && *canonical == 0)
11742 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
11746 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
11747 CPU name. We've traditionally allowed a lot of variation here.
11749 Note: this function is shared between GCC and GAS. */
11752 mips_matching_cpu_name_p (const char *canonical, const char *given)
11754 /* First see if the name matches exactly, or with a final "000"
11755 turned into "k". */
11756 if (mips_strict_matching_cpu_name_p (canonical, given))
11759 /* If not, try comparing based on numerical designation alone.
11760 See if GIVEN is an unadorned number, or 'r' followed by a number. */
11761 if (TOLOWER (*given) == 'r')
11763 if (!ISDIGIT (*given))
11766 /* Skip over some well-known prefixes in the canonical name,
11767 hoping to find a number there too. */
11768 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
11770 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
11772 else if (TOLOWER (canonical[0]) == 'r')
11775 return mips_strict_matching_cpu_name_p (canonical, given);
11779 /* Return the mips_cpu_info entry for the processor or ISA given
11780 by CPU_STRING. Return null if the string isn't recognized.
11782 A similar function exists in GAS. */
11784 static const struct mips_cpu_info *
11785 mips_parse_cpu (const char *cpu_string)
11790 /* In the past, we allowed upper-case CPU names, but it doesn't
11791 work well with the multilib machinery. */
11792 for (s = cpu_string; *s != 0; s++)
11795 warning (0, "the cpu name must be lower case");
11799 /* 'from-abi' selects the most compatible architecture for the given
11800 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
11801 EABIs, we have to decide whether we're using the 32-bit or 64-bit
11802 version. Look first at the -mgp options, if given, otherwise base
11803 the choice on MASK_64BIT in TARGET_DEFAULT. */
11804 if (strcasecmp (cpu_string, "from-abi") == 0)
11805 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
11806 : ABI_NEEDS_64BIT_REGS ? 3
11807 : (TARGET_64BIT ? 3 : 1));
11809 /* 'default' has traditionally been a no-op. Probably not very useful. */
11810 if (strcasecmp (cpu_string, "default") == 0)
11813 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
11814 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
11815 return mips_cpu_info_table + i;
11821 /* Set up globals to generate code for the ISA or processor
11822 described by INFO. */
11825 mips_set_architecture (const struct mips_cpu_info *info)
11829 mips_arch_info = info;
11830 mips_arch = info->cpu;
11831 mips_isa = info->isa;
11836 /* Likewise for tuning. */
11839 mips_set_tune (const struct mips_cpu_info *info)
11843 mips_tune_info = info;
11844 mips_tune = info->cpu;
11848 /* Implement TARGET_HANDLE_OPTION. */
11851 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
11856 if (strcmp (arg, "32") == 0)
11858 else if (strcmp (arg, "o64") == 0)
11859 mips_abi = ABI_O64;
11860 else if (strcmp (arg, "n32") == 0)
11861 mips_abi = ABI_N32;
11862 else if (strcmp (arg, "64") == 0)
11864 else if (strcmp (arg, "eabi") == 0)
11865 mips_abi = ABI_EABI;
11872 return mips_parse_cpu (arg) != 0;
11875 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
11876 return mips_isa_info != 0;
11878 case OPT_mno_flush_func:
11879 mips_cache_flush_func = NULL;
11882 case OPT_mcode_readable_:
11883 if (strcmp (arg, "yes") == 0)
11884 mips_code_readable = CODE_READABLE_YES;
11885 else if (strcmp (arg, "pcrel") == 0)
11886 mips_code_readable = CODE_READABLE_PCREL;
11887 else if (strcmp (arg, "no") == 0)
11888 mips_code_readable = CODE_READABLE_NO;
11898 /* Set up the threshold for data to go into the small data area, instead
11899 of the normal data area, and detect any conflicts in the switches. */
11902 override_options (void)
11904 int i, start, regno;
11905 enum machine_mode mode;
11907 #ifdef SUBTARGET_OVERRIDE_OPTIONS
11908 SUBTARGET_OVERRIDE_OPTIONS;
11911 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
11913 /* The following code determines the architecture and register size.
11914 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
11915 The GAS and GCC code should be kept in sync as much as possible. */
11917 if (mips_arch_string != 0)
11918 mips_set_architecture (mips_parse_cpu (mips_arch_string));
11920 if (mips_isa_info != 0)
11922 if (mips_arch_info == 0)
11923 mips_set_architecture (mips_isa_info);
11924 else if (mips_arch_info->isa != mips_isa_info->isa)
11925 error ("-%s conflicts with the other architecture options, "
11926 "which specify a %s processor",
11927 mips_isa_info->name,
11928 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
11931 if (mips_arch_info == 0)
11933 #ifdef MIPS_CPU_STRING_DEFAULT
11934 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
11936 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
11940 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
11941 error ("-march=%s is not compatible with the selected ABI",
11942 mips_arch_info->name);
11944 /* Optimize for mips_arch, unless -mtune selects a different processor. */
11945 if (mips_tune_string != 0)
11946 mips_set_tune (mips_parse_cpu (mips_tune_string));
11948 if (mips_tune_info == 0)
11949 mips_set_tune (mips_arch_info);
11951 /* Set cost structure for the processor. */
11953 mips_cost = &mips_rtx_cost_optimize_size;
11955 mips_cost = &mips_rtx_cost_data[mips_tune];
11957 /* If the user hasn't specified a branch cost, use the processor's
11959 if (mips_branch_cost == 0)
11960 mips_branch_cost = mips_cost->branch_cost;
11962 if ((target_flags_explicit & MASK_64BIT) != 0)
11964 /* The user specified the size of the integer registers. Make sure
11965 it agrees with the ABI and ISA. */
11966 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
11967 error ("-mgp64 used with a 32-bit processor");
11968 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
11969 error ("-mgp32 used with a 64-bit ABI");
11970 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
11971 error ("-mgp64 used with a 32-bit ABI");
11975 /* Infer the integer register size from the ABI and processor.
11976 Restrict ourselves to 32-bit registers if that's all the
11977 processor has, or if the ABI cannot handle 64-bit registers. */
11978 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
11979 target_flags &= ~MASK_64BIT;
11981 target_flags |= MASK_64BIT;
11984 if ((target_flags_explicit & MASK_FLOAT64) != 0)
11986 /* Really, -mfp32 and -mfp64 are ornamental options. There's
11987 only one right answer here. */
11988 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
11989 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
11990 else if (!TARGET_64BIT && TARGET_FLOAT64
11991 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
11992 error ("-mgp32 and -mfp64 can only be combined if the target"
11993 " supports the mfhc1 and mthc1 instructions");
11994 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
11995 error ("unsupported combination: %s", "-mfp64 -msingle-float");
11999 /* -msingle-float selects 32-bit float registers. Otherwise the
12000 float registers should be the same size as the integer ones. */
12001 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
12002 target_flags |= MASK_FLOAT64;
12004 target_flags &= ~MASK_FLOAT64;
12007 /* End of code shared with GAS. */
12009 if ((target_flags_explicit & MASK_LONG64) == 0)
12011 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
12012 target_flags |= MASK_LONG64;
12014 target_flags &= ~MASK_LONG64;
12017 if (!TARGET_OLDABI)
12018 flag_pcc_struct_return = 0;
12020 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
12022 /* If neither -mbranch-likely nor -mno-branch-likely was given
12023 on the command line, set MASK_BRANCHLIKELY based on the target
12024 architecture and tuning flags. Annulled delay slots are a
12025 size win, so we only consider the processor-specific tuning
12026 for !optimize_size. */
12027 if (ISA_HAS_BRANCHLIKELY
12029 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
12030 target_flags |= MASK_BRANCHLIKELY;
12032 target_flags &= ~MASK_BRANCHLIKELY;
12034 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
12035 warning (0, "the %qs architecture does not support branch-likely"
12036 " instructions", mips_arch_info->name);
12038 /* The effect of -mabicalls isn't defined for the EABI. */
12039 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
12041 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
12042 target_flags &= ~MASK_ABICALLS;
12045 /* MIPS16 cannot generate PIC yet. */
12046 if (TARGET_MIPS16 && (flag_pic || TARGET_ABICALLS))
12048 sorry ("MIPS16 PIC");
12049 target_flags &= ~MASK_ABICALLS;
12050 flag_pic = flag_pie = flag_shlib = 0;
12053 if (TARGET_ABICALLS)
12054 /* We need to set flag_pic for executables as well as DSOs
12055 because we may reference symbols that are not defined in
12056 the final executable. (MIPS does not use things like
12057 copy relocs, for example.)
12059 Also, there is a body of code that uses __PIC__ to distinguish
12060 between -mabicalls and -mno-abicalls code. */
12063 /* -mvr4130-align is a "speed over size" optimization: it usually produces
12064 faster code, but at the expense of more nops. Enable it at -O3 and
12066 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
12067 target_flags |= MASK_VR4130_ALIGN;
12069 /* Prefer a call to memcpy over inline code when optimizing for size,
12070 though see MOVE_RATIO in mips.h. */
12071 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
12072 target_flags |= MASK_MEMCPY;
12074 /* If we have a nonzero small-data limit, check that the -mgpopt
12075 setting is consistent with the other target flags. */
12076 if (mips_section_threshold > 0)
12080 if (!TARGET_MIPS16 && !TARGET_EXPLICIT_RELOCS)
12081 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
12083 TARGET_LOCAL_SDATA = false;
12084 TARGET_EXTERN_SDATA = false;
12088 if (TARGET_VXWORKS_RTP)
12089 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
12091 if (TARGET_ABICALLS)
12092 warning (0, "cannot use small-data accesses for %qs",
12097 #ifdef MIPS_TFMODE_FORMAT
12098 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
12101 /* Make sure that the user didn't turn off paired single support when
12102 MIPS-3D support is requested. */
12103 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
12104 && !TARGET_PAIRED_SINGLE_FLOAT)
12105 error ("-mips3d requires -mpaired-single");
12107 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
12109 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
12111 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
12112 and TARGET_HARD_FLOAT_ABI are both true. */
12113 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
12114 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
12116 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
12118 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
12119 warning (0, "the %qs architecture does not support paired-single"
12120 " instructions", mips_arch_info->name);
12122 /* If TARGET_DSPR2, enable MASK_DSP. */
12124 target_flags |= MASK_DSP;
12126 mips_init_print_operand_punct ();
12128 /* Set up array to map GCC register number to debug register number.
12129 Ignore the special purpose register numbers. */
12131 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12133 mips_dbx_regno[i] = INVALID_REGNUM;
12134 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
12135 mips_dwarf_regno[i] = i;
12137 mips_dwarf_regno[i] = INVALID_REGNUM;
12140 start = GP_DBX_FIRST - GP_REG_FIRST;
12141 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
12142 mips_dbx_regno[i] = i + start;
12144 start = FP_DBX_FIRST - FP_REG_FIRST;
12145 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
12146 mips_dbx_regno[i] = i + start;
12148 /* HI and LO debug registers use big-endian ordering. */
12149 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
12150 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
12151 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
12152 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
12153 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
12155 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
12156 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
12159 /* Set up mips_hard_regno_mode_ok. */
12160 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
12161 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
12162 mips_hard_regno_mode_ok[(int)mode][regno]
12163 = mips_hard_regno_mode_ok_p (regno, mode);
12165 /* Function to allocate machine-dependent function status. */
12166 init_machine_status = &mips_init_machine_status;
12168 /* Default to working around R4000 errata only if the processor
12169 was selected explicitly. */
12170 if ((target_flags_explicit & MASK_FIX_R4000) == 0
12171 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
12172 target_flags |= MASK_FIX_R4000;
12174 /* Default to working around R4400 errata only if the processor
12175 was selected explicitly. */
12176 if ((target_flags_explicit & MASK_FIX_R4400) == 0
12177 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
12178 target_flags |= MASK_FIX_R4400;
12180 /* Save base state of options. */
12181 mips_base_mips16 = TARGET_MIPS16;
12182 mips_base_target_flags = target_flags;
12183 mips_flag_delayed_branch = flag_delayed_branch;
12184 mips_base_schedule_insns = flag_schedule_insns;
12185 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
12186 mips_base_move_loop_invariants = flag_move_loop_invariants;
12187 mips_base_align_loops = align_loops;
12188 mips_base_align_jumps = align_jumps;
12189 mips_base_align_functions = align_functions;
12191 /* Now select the mips16 or 32-bit instruction set, as requested. */
12192 mips_set_mips16_mode (mips_base_mips16);
12195 /* Swap the register information for registers I and I + 1, which
12196 currently have the wrong endianness. Note that the registers'
12197 fixedness and call-clobberedness might have been set on the
12201 mips_swap_registers (unsigned int i)
12206 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
12207 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
12209 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
12210 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
12211 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
12212 SWAP_STRING (reg_names[i], reg_names[i + 1]);
12218 /* Implement CONDITIONAL_REGISTER_USAGE. */
12221 mips_conditional_register_usage (void)
12227 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
12228 fixed_regs[regno] = call_used_regs[regno] = 1;
12230 if (!TARGET_HARD_FLOAT)
12234 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
12235 fixed_regs[regno] = call_used_regs[regno] = 1;
12236 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12237 fixed_regs[regno] = call_used_regs[regno] = 1;
12239 else if (! ISA_HAS_8CC)
12243 /* We only have a single condition code register. We
12244 implement this by hiding all the condition code registers,
12245 and generating RTL that refers directly to ST_REG_FIRST. */
12246 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
12247 fixed_regs[regno] = call_used_regs[regno] = 1;
12249 /* In mips16 mode, we permit the $t temporary registers to be used
12250 for reload. We prohibit the unused $s registers, since they
12251 are caller saved, and saving them via a mips16 register would
12252 probably waste more time than just reloading the value. */
12255 fixed_regs[18] = call_used_regs[18] = 1;
12256 fixed_regs[19] = call_used_regs[19] = 1;
12257 fixed_regs[20] = call_used_regs[20] = 1;
12258 fixed_regs[21] = call_used_regs[21] = 1;
12259 fixed_regs[22] = call_used_regs[22] = 1;
12260 fixed_regs[23] = call_used_regs[23] = 1;
12261 fixed_regs[26] = call_used_regs[26] = 1;
12262 fixed_regs[27] = call_used_regs[27] = 1;
12263 fixed_regs[30] = call_used_regs[30] = 1;
12265 /* fp20-23 are now caller saved. */
12266 if (mips_abi == ABI_64)
12269 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
12270 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12272 /* Odd registers from fp21 to fp31 are now caller saved. */
12273 if (mips_abi == ABI_N32)
12276 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
12277 call_really_used_regs[regno] = call_used_regs[regno] = 1;
12279 /* Make sure that double-register accumulator values are correctly
12280 ordered for the current endianness. */
12281 if (TARGET_LITTLE_ENDIAN)
12284 mips_swap_registers (MD_REG_FIRST);
12285 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
12286 mips_swap_registers (regno);
12290 /* On the mips16, we want to allocate $24 (T_REG) before other
12291 registers for instructions for which it is possible. This helps
12292 avoid shuffling registers around in order to set up for an xor,
12293 encouraging the compiler to use a cmp instead. */
12296 mips_order_regs_for_local_alloc (void)
12300 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12301 reg_alloc_order[i] = i;
12305 /* It really doesn't matter where we put register 0, since it is
12306 a fixed register anyhow. */
12307 reg_alloc_order[0] = 24;
12308 reg_alloc_order[24] = 0;
12312 /* Initialize the GCC target structure. */
12313 #undef TARGET_ASM_ALIGNED_HI_OP
12314 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
12315 #undef TARGET_ASM_ALIGNED_SI_OP
12316 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
12317 #undef TARGET_ASM_ALIGNED_DI_OP
12318 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
12320 #undef TARGET_ASM_FUNCTION_PROLOGUE
12321 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
12322 #undef TARGET_ASM_FUNCTION_EPILOGUE
12323 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
12324 #undef TARGET_ASM_SELECT_RTX_SECTION
12325 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
12326 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
12327 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
12329 #undef TARGET_SCHED_INIT
12330 #define TARGET_SCHED_INIT mips_sched_init
12331 #undef TARGET_SCHED_REORDER
12332 #define TARGET_SCHED_REORDER mips_sched_reorder
12333 #undef TARGET_SCHED_REORDER2
12334 #define TARGET_SCHED_REORDER2 mips_sched_reorder
12335 #undef TARGET_SCHED_VARIABLE_ISSUE
12336 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
12337 #undef TARGET_SCHED_ADJUST_COST
12338 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
12339 #undef TARGET_SCHED_ISSUE_RATE
12340 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
12341 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12342 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
12343 mips_multipass_dfa_lookahead
12345 #undef TARGET_DEFAULT_TARGET_FLAGS
12346 #define TARGET_DEFAULT_TARGET_FLAGS \
12348 | TARGET_CPU_DEFAULT \
12349 | TARGET_ENDIAN_DEFAULT \
12350 | TARGET_FP_EXCEPTIONS_DEFAULT \
12351 | MASK_CHECK_ZERO_DIV \
12353 #undef TARGET_HANDLE_OPTION
12354 #define TARGET_HANDLE_OPTION mips_handle_option
12356 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12357 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
12359 #undef TARGET_INSERT_ATTRIBUTES
12360 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
12361 #undef TARGET_MERGE_DECL_ATTRIBUTES
12362 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
12363 #undef TARGET_SET_CURRENT_FUNCTION
12364 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
12366 #undef TARGET_VALID_POINTER_MODE
12367 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
12368 #undef TARGET_RTX_COSTS
12369 #define TARGET_RTX_COSTS mips_rtx_costs
12370 #undef TARGET_ADDRESS_COST
12371 #define TARGET_ADDRESS_COST mips_address_cost
12373 #undef TARGET_IN_SMALL_DATA_P
12374 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
12376 #undef TARGET_MACHINE_DEPENDENT_REORG
12377 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
12379 #undef TARGET_ASM_FILE_START
12380 #define TARGET_ASM_FILE_START mips_file_start
12381 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
12382 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
12384 #undef TARGET_INIT_LIBFUNCS
12385 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
12387 #undef TARGET_BUILD_BUILTIN_VA_LIST
12388 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
12389 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12390 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
12392 #undef TARGET_PROMOTE_FUNCTION_ARGS
12393 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
12394 #undef TARGET_PROMOTE_FUNCTION_RETURN
12395 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
12396 #undef TARGET_PROMOTE_PROTOTYPES
12397 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
12399 #undef TARGET_RETURN_IN_MEMORY
12400 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
12401 #undef TARGET_RETURN_IN_MSB
12402 #define TARGET_RETURN_IN_MSB mips_return_in_msb
12404 #undef TARGET_ASM_OUTPUT_MI_THUNK
12405 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
12406 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12407 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12409 #undef TARGET_SETUP_INCOMING_VARARGS
12410 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
12411 #undef TARGET_STRICT_ARGUMENT_NAMING
12412 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
12413 #undef TARGET_MUST_PASS_IN_STACK
12414 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
12415 #undef TARGET_PASS_BY_REFERENCE
12416 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
12417 #undef TARGET_CALLEE_COPIES
12418 #define TARGET_CALLEE_COPIES mips_callee_copies
12419 #undef TARGET_ARG_PARTIAL_BYTES
12420 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
12422 #undef TARGET_MODE_REP_EXTENDED
12423 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
12425 #undef TARGET_VECTOR_MODE_SUPPORTED_P
12426 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
12428 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12429 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
12431 #undef TARGET_INIT_BUILTINS
12432 #define TARGET_INIT_BUILTINS mips_init_builtins
12433 #undef TARGET_EXPAND_BUILTIN
12434 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
12436 #undef TARGET_HAVE_TLS
12437 #define TARGET_HAVE_TLS HAVE_AS_TLS
12439 #undef TARGET_CANNOT_FORCE_CONST_MEM
12440 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
12442 #undef TARGET_ENCODE_SECTION_INFO
12443 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
12445 #undef TARGET_ATTRIBUTE_TABLE
12446 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
12447 /* All our function attributes are related to how out-of-line copies should
12448 be compiled or called. They don't in themselves prevent inlining. */
12449 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
12450 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
12452 #undef TARGET_EXTRA_LIVE_ON_ENTRY
12453 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
12455 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
12456 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
12457 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
12458 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
12460 #undef TARGET_COMP_TYPE_ATTRIBUTES
12461 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
12463 #ifdef HAVE_AS_DTPRELWORD
12464 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12465 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
12467 #undef TARGET_DWARF_REGISTER_SPAN
12468 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
12470 struct gcc_target targetm = TARGET_INITIALIZER;
12472 #include "gt-mips.h"