1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING. If not, write to
24 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
29 #include "coretypes.h"
34 #include "hard-reg-set.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
59 #include "tree-gimple.h"
62 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Classifies an address.
131 A natural register + offset address. The register satisfies
132 mips_valid_base_register_p and the offset is a const_arith_operand.
135 A LO_SUM rtx. The first operand is a valid base register and
136 the second operand is a symbolic address.
139 A signed 16-bit constant address.
142 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
143 enum mips_address_type {
150 /* Classifies the prototype of a builtin function. */
151 enum mips_function_type
153 MIPS_V2SF_FTYPE_V2SF,
154 MIPS_V2SF_FTYPE_V2SF_V2SF,
155 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
156 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
157 MIPS_V2SF_FTYPE_SF_SF,
158 MIPS_INT_FTYPE_V2SF_V2SF,
159 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
160 MIPS_INT_FTYPE_SF_SF,
161 MIPS_INT_FTYPE_DF_DF,
168 /* For MIPS DSP ASE */
170 MIPS_DI_FTYPE_DI_SI_SI,
171 MIPS_DI_FTYPE_DI_V2HI_V2HI,
172 MIPS_DI_FTYPE_DI_V4QI_V4QI,
174 MIPS_SI_FTYPE_PTR_SI,
178 MIPS_SI_FTYPE_V2HI_V2HI,
180 MIPS_SI_FTYPE_V4QI_V4QI,
183 MIPS_V2HI_FTYPE_SI_SI,
184 MIPS_V2HI_FTYPE_V2HI,
185 MIPS_V2HI_FTYPE_V2HI_SI,
186 MIPS_V2HI_FTYPE_V2HI_V2HI,
187 MIPS_V2HI_FTYPE_V4QI,
188 MIPS_V2HI_FTYPE_V4QI_V2HI,
190 MIPS_V4QI_FTYPE_V2HI_V2HI,
191 MIPS_V4QI_FTYPE_V4QI_SI,
192 MIPS_V4QI_FTYPE_V4QI_V4QI,
193 MIPS_VOID_FTYPE_SI_SI,
194 MIPS_VOID_FTYPE_V2HI_V2HI,
195 MIPS_VOID_FTYPE_V4QI_V4QI,
197 /* For MIPS DSP REV 2 ASE. */
198 MIPS_V4QI_FTYPE_V4QI,
199 MIPS_SI_FTYPE_SI_SI_SI,
200 MIPS_DI_FTYPE_DI_USI_USI,
202 MIPS_DI_FTYPE_USI_USI,
203 MIPS_V2HI_FTYPE_SI_SI_SI,
209 /* Specifies how a builtin function should be converted into rtl. */
210 enum mips_builtin_type
212 /* The builtin corresponds directly to an .md pattern. The return
213 value is mapped to operand 0 and the arguments are mapped to
214 operands 1 and above. */
217 /* The builtin corresponds directly to an .md pattern. There is no return
218 value and the arguments are mapped to operands 0 and above. */
219 MIPS_BUILTIN_DIRECT_NO_TARGET,
221 /* The builtin corresponds to a comparison instruction followed by
222 a mips_cond_move_tf_ps pattern. The first two arguments are the
223 values to compare and the second two arguments are the vector
224 operands for the movt.ps or movf.ps instruction (in assembly order). */
228 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
229 of this instruction is the result of the comparison, which has mode
230 CCV2 or CCV4. The function arguments are mapped to operands 1 and
231 above. The function's return value is an SImode boolean that is
232 true under the following conditions:
234 MIPS_BUILTIN_CMP_ANY: one of the registers is true
235 MIPS_BUILTIN_CMP_ALL: all of the registers are true
236 MIPS_BUILTIN_CMP_LOWER: the first register is true
237 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
238 MIPS_BUILTIN_CMP_ANY,
239 MIPS_BUILTIN_CMP_ALL,
240 MIPS_BUILTIN_CMP_UPPER,
241 MIPS_BUILTIN_CMP_LOWER,
243 /* As above, but the instruction only sets a single $fcc register. */
244 MIPS_BUILTIN_CMP_SINGLE,
246 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
247 MIPS_BUILTIN_BPOSGE32
250 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
251 #define MIPS_FP_CONDITIONS(MACRO) \
269 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
270 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
271 enum mips_fp_condition {
272 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
275 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
276 #define STRINGIFY(X) #X
277 static const char *const mips_fp_conditions[] = {
278 MIPS_FP_CONDITIONS (STRINGIFY)
281 /* A function to save or store a register. The first argument is the
282 register and the second is the stack slot. */
283 typedef void (*mips_save_restore_fn) (rtx, rtx);
285 struct mips16_constant;
286 struct mips_arg_info;
287 struct mips_address_info;
288 struct mips_integer_op;
291 static enum mips_symbol_type mips_classify_symbol (rtx);
292 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
293 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
294 static bool mips_classify_address (struct mips_address_info *, rtx,
295 enum machine_mode, int);
296 static bool mips_cannot_force_const_mem (rtx);
297 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
298 static int mips_symbol_insns (enum mips_symbol_type);
299 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
300 static rtx mips_force_temporary (rtx, rtx);
301 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
302 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
303 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
304 static unsigned int mips_build_lower (struct mips_integer_op *,
305 unsigned HOST_WIDE_INT);
306 static unsigned int mips_build_integer (struct mips_integer_op *,
307 unsigned HOST_WIDE_INT);
308 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
309 static int m16_check_op (rtx, int, int, int);
310 static bool mips_rtx_costs (rtx, int, int, int *);
311 static int mips_address_cost (rtx);
312 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
313 static void mips_load_call_address (rtx, rtx, int);
314 static bool mips_function_ok_for_sibcall (tree, tree);
315 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
316 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
317 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
318 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
319 tree, int, struct mips_arg_info *);
320 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
321 static void mips_set_architecture (const struct mips_cpu_info *);
322 static void mips_set_tune (const struct mips_cpu_info *);
323 static bool mips_handle_option (size_t, const char *, int);
324 static struct machine_function *mips_init_machine_status (void);
325 static void print_operand_reloc (FILE *, rtx, const char **);
326 static void mips_file_start (void);
327 static bool mips_rewrite_small_data_p (rtx);
328 static int mips_small_data_pattern_1 (rtx *, void *);
329 static int mips_rewrite_small_data_1 (rtx *, void *);
330 static bool mips_function_has_gp_insn (void);
331 static unsigned int mips_global_pointer (void);
332 static bool mips_save_reg_p (unsigned int);
333 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
334 mips_save_restore_fn);
335 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
336 static void mips_output_cplocal (void);
337 static void mips_emit_loadgp (void);
338 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
339 static void mips_set_frame_expr (rtx);
340 static rtx mips_frame_set (rtx, rtx);
341 static void mips_save_reg (rtx, rtx);
342 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
343 static void mips_restore_reg (rtx, rtx);
344 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
345 HOST_WIDE_INT, tree);
346 static int symbolic_expression_p (rtx);
347 static section *mips_select_rtx_section (enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT);
349 static section *mips_function_rodata_section (tree);
350 static bool mips_in_small_data_p (tree);
351 static bool mips_use_anchors_for_symbol_p (rtx);
352 static int mips_fpr_return_fields (tree, tree *);
353 static bool mips_return_in_msb (tree);
354 static rtx mips_return_fpr_pair (enum machine_mode mode,
355 enum machine_mode mode1, HOST_WIDE_INT,
356 enum machine_mode mode2, HOST_WIDE_INT);
357 static rtx mips16_gp_pseudo_reg (void);
358 static void mips16_fp_args (FILE *, int, int);
359 static void build_mips16_function_stub (FILE *);
360 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
361 static void dump_constants (struct mips16_constant *, rtx);
362 static int mips16_insn_length (rtx);
363 static int mips16_rewrite_pool_refs (rtx *, void *);
364 static void mips16_lay_out_constants (void);
365 static void mips_sim_reset (struct mips_sim *);
366 static void mips_sim_init (struct mips_sim *, state_t);
367 static void mips_sim_next_cycle (struct mips_sim *);
368 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
369 static int mips_sim_wait_regs_2 (rtx *, void *);
370 static void mips_sim_wait_regs_1 (rtx *, void *);
371 static void mips_sim_wait_regs (struct mips_sim *, rtx);
372 static void mips_sim_wait_units (struct mips_sim *, rtx);
373 static void mips_sim_wait_insn (struct mips_sim *, rtx);
374 static void mips_sim_record_set (rtx, rtx, void *);
375 static void mips_sim_issue_insn (struct mips_sim *, rtx);
376 static void mips_sim_issue_nop (struct mips_sim *);
377 static void mips_sim_finish_insn (struct mips_sim *, rtx);
378 static void vr4130_avoid_branch_rt_conflict (rtx);
379 static void vr4130_align_insns (void);
380 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
381 static void mips_avoid_hazards (void);
382 static void mips_reorg (void);
383 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
384 static bool mips_matching_cpu_name_p (const char *, const char *);
385 static const struct mips_cpu_info *mips_parse_cpu (const char *);
386 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
387 static bool mips_return_in_memory (tree, tree);
388 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
389 static void mips_macc_chains_record (rtx);
390 static void mips_macc_chains_reorder (rtx *, int);
391 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
392 static bool vr4130_true_reg_dependence_p (rtx);
393 static bool vr4130_swap_insns_p (rtx, rtx);
394 static void vr4130_reorder (rtx *, int);
395 static void mips_promote_ready (rtx *, int, int);
396 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
397 static int mips_variable_issue (FILE *, int, rtx, int);
398 static int mips_adjust_cost (rtx, rtx, rtx, int);
399 static int mips_issue_rate (void);
400 static int mips_multipass_dfa_lookahead (void);
401 static void mips_init_libfuncs (void);
402 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
404 static tree mips_build_builtin_va_list (void);
405 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
406 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
408 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
410 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
412 static bool mips_valid_pointer_mode (enum machine_mode);
413 static bool mips_vector_mode_supported_p (enum machine_mode);
414 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree, unsigned int);
415 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
416 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
417 static void mips_init_builtins (void);
418 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
419 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
420 enum insn_code, enum mips_fp_condition,
422 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
423 enum insn_code, enum mips_fp_condition,
425 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
426 static void mips_encode_section_info (tree, rtx, int);
427 static void mips_extra_live_on_entry (bitmap);
428 static int mips_comp_type_attributes (tree, tree);
429 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
430 static bool mips_offset_within_alignment_p (rtx, HOST_WIDE_INT);
431 static void mips_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
433 /* Structure to be filled in by compute_frame_size with register
434 save masks, and offsets for the current function. */
436 struct mips_frame_info GTY(())
438 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
439 HOST_WIDE_INT var_size; /* # bytes that variables take up */
440 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
441 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
442 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
443 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
444 unsigned int mask; /* mask of saved gp registers */
445 unsigned int fmask; /* mask of saved fp registers */
446 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
447 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
448 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
449 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
450 bool initialized; /* true if frame size already calculated */
451 int num_gp; /* number of gp registers saved */
452 int num_fp; /* number of fp registers saved */
455 struct machine_function GTY(()) {
456 /* Pseudo-reg holding the value of $28 in a mips16 function which
457 refers to GP relative global variables. */
458 rtx mips16_gp_pseudo_rtx;
460 /* The number of extra stack bytes taken up by register varargs.
461 This area is allocated by the callee at the very top of the frame. */
464 /* Current frame information, calculated by compute_frame_size. */
465 struct mips_frame_info frame;
467 /* The register to use as the global pointer within this function. */
468 unsigned int global_pointer;
470 /* True if mips_adjust_insn_length should ignore an instruction's
472 bool ignore_hazard_length_p;
474 /* True if the whole function is suitable for .set noreorder and
476 bool all_noreorder_p;
478 /* True if the function is known to have an instruction that needs $gp. */
482 /* Information about a single argument. */
485 /* True if the argument is passed in a floating-point register, or
486 would have been if we hadn't run out of registers. */
489 /* The number of words passed in registers, rounded up. */
490 unsigned int reg_words;
492 /* For EABI, the offset of the first register from GP_ARG_FIRST or
493 FP_ARG_FIRST. For other ABIs, the offset of the first register from
494 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
495 comment for details).
497 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
499 unsigned int reg_offset;
501 /* The number of words that must be passed on the stack, rounded up. */
502 unsigned int stack_words;
504 /* The offset from the start of the stack overflow area of the argument's
505 first stack word. Only meaningful when STACK_WORDS is nonzero. */
506 unsigned int stack_offset;
510 /* Information about an address described by mips_address_type.
516 REG is the base register and OFFSET is the constant offset.
519 REG is the register that contains the high part of the address,
520 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
521 is the type of OFFSET's symbol.
524 SYMBOL_TYPE is the type of symbol being referenced. */
526 struct mips_address_info
528 enum mips_address_type type;
531 enum mips_symbol_type symbol_type;
535 /* One stage in a constant building sequence. These sequences have
539 A = A CODE[1] VALUE[1]
540 A = A CODE[2] VALUE[2]
543 where A is an accumulator, each CODE[i] is a binary rtl operation
544 and each VALUE[i] is a constant integer. */
545 struct mips_integer_op {
547 unsigned HOST_WIDE_INT value;
551 /* The largest number of operations needed to load an integer constant.
552 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
553 When the lowest bit is clear, we can try, but reject a sequence with
554 an extra SLL at the end. */
555 #define MIPS_MAX_INTEGER_OPS 7
557 /* Information about a MIPS16e SAVE or RESTORE instruction. */
558 struct mips16e_save_restore_info {
559 /* The number of argument registers saved by a SAVE instruction.
560 0 for RESTORE instructions. */
563 /* Bit X is set if the instruction saves or restores GPR X. */
566 /* The total number of bytes to allocate. */
570 /* Global variables for machine-dependent things. */
572 /* Threshold for data being put into the small data/bss area, instead
573 of the normal data area. */
574 int mips_section_threshold = -1;
576 /* Count the number of .file directives, so that .loc is up to date. */
577 int num_source_filenames = 0;
579 /* Count the number of sdb related labels are generated (to find block
580 start and end boundaries). */
581 int sdb_label_count = 0;
583 /* Next label # for each statement for Silicon Graphics IRIS systems. */
586 /* Name of the file containing the current function. */
587 const char *current_function_file = "";
589 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
595 /* The next branch instruction is a branch likely, not branch normal. */
596 int mips_branch_likely;
598 /* The operands passed to the last cmpMM expander. */
601 /* The target cpu for code generation. */
602 enum processor_type mips_arch;
603 const struct mips_cpu_info *mips_arch_info;
605 /* The target cpu for optimization and scheduling. */
606 enum processor_type mips_tune;
607 const struct mips_cpu_info *mips_tune_info;
609 /* Which instruction set architecture to use. */
612 /* Which ABI to use. */
613 int mips_abi = MIPS_ABI_DEFAULT;
615 /* Cost information to use. */
616 const struct mips_rtx_cost_data *mips_cost;
618 /* Whether we are generating mips16 hard float code. In mips16 mode
619 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
620 -msoft-float was not specified by the user, which means that we
621 should arrange to call mips32 hard floating point code. */
622 int mips16_hard_float;
624 /* The architecture selected by -mipsN. */
625 static const struct mips_cpu_info *mips_isa_info;
627 /* If TRUE, we split addresses into their high and low parts in the RTL. */
628 int mips_split_addresses;
630 /* Mode used for saving/restoring general purpose registers. */
631 static enum machine_mode gpr_mode;
633 /* Array giving truth value on whether or not a given hard register
634 can support a given mode. */
635 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
637 /* List of all MIPS punctuation characters used by print_operand. */
638 char mips_print_operand_punct[256];
640 /* Map GCC register number to debugger register number. */
641 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
643 /* A copy of the original flag_delayed_branch: see override_options. */
644 static int mips_flag_delayed_branch;
646 static GTY (()) int mips_output_filename_first_time = 1;
648 /* mips_split_p[X] is true if symbols of type X can be split by
649 mips_split_symbol(). */
650 bool mips_split_p[NUM_SYMBOL_TYPES];
652 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
653 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
654 if they are matched by a special .md file pattern. */
655 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
657 /* Likewise for HIGHs. */
658 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
660 /* Map hard register number to register class */
661 const enum reg_class mips_regno_to_class[] =
663 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
664 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
665 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
666 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
667 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
668 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
669 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
670 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
675 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
676 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
677 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
678 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
679 HI_REG, LO_REG, NO_REGS, ST_REGS,
680 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
681 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
682 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
687 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
688 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
689 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
690 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
695 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
696 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
697 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
698 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
703 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
704 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
705 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
706 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
707 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
708 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
709 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
712 /* Table of machine dependent attributes. */
713 const struct attribute_spec mips_attribute_table[] =
715 { "long_call", 0, 0, false, true, true, NULL },
716 { "far", 0, 0, false, true, true, NULL },
717 { "near", 0, 0, false, true, true, NULL },
718 { NULL, 0, 0, false, false, false, NULL }
721 /* A table describing all the processors gcc knows about. Names are
722 matched in the order listed. The first mention of an ISA level is
723 taken as the canonical name for that ISA.
725 To ease comparison, please keep this table in the same order as
726 gas's mips_cpu_info_table[]. Please also make sure that
727 MIPS_ISA_LEVEL_SPEC handles all -march options correctly. */
728 const struct mips_cpu_info mips_cpu_info_table[] = {
729 /* Entries for generic ISAs */
730 { "mips1", PROCESSOR_R3000, 1 },
731 { "mips2", PROCESSOR_R6000, 2 },
732 { "mips3", PROCESSOR_R4000, 3 },
733 { "mips4", PROCESSOR_R8000, 4 },
734 { "mips32", PROCESSOR_4KC, 32 },
735 { "mips32r2", PROCESSOR_M4K, 33 },
736 { "mips64", PROCESSOR_5KC, 64 },
739 { "r3000", PROCESSOR_R3000, 1 },
740 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
741 { "r3900", PROCESSOR_R3900, 1 },
744 { "r6000", PROCESSOR_R6000, 2 },
747 { "r4000", PROCESSOR_R4000, 3 },
748 { "vr4100", PROCESSOR_R4100, 3 },
749 { "vr4111", PROCESSOR_R4111, 3 },
750 { "vr4120", PROCESSOR_R4120, 3 },
751 { "vr4130", PROCESSOR_R4130, 3 },
752 { "vr4300", PROCESSOR_R4300, 3 },
753 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
754 { "r4600", PROCESSOR_R4600, 3 },
755 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
756 { "r4650", PROCESSOR_R4650, 3 },
759 { "r8000", PROCESSOR_R8000, 4 },
760 { "vr5000", PROCESSOR_R5000, 4 },
761 { "vr5400", PROCESSOR_R5400, 4 },
762 { "vr5500", PROCESSOR_R5500, 4 },
763 { "rm7000", PROCESSOR_R7000, 4 },
764 { "rm9000", PROCESSOR_R9000, 4 },
767 { "4kc", PROCESSOR_4KC, 32 },
768 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
769 { "4kp", PROCESSOR_4KP, 32 },
770 { "4ksc", PROCESSOR_4KC, 32 },
772 /* MIPS32 Release 2 */
773 { "m4k", PROCESSOR_M4K, 33 },
774 { "4kec", PROCESSOR_4KC, 33 },
775 { "4kem", PROCESSOR_4KC, 33 },
776 { "4kep", PROCESSOR_4KP, 33 },
777 { "4ksd", PROCESSOR_4KC, 33 },
779 { "24kc", PROCESSOR_24KC, 33 },
780 { "24kf2_1", PROCESSOR_24KF2_1, 33 },
781 { "24kf", PROCESSOR_24KF2_1, 33 },
782 { "24kf1_1", PROCESSOR_24KF1_1, 33 },
783 { "24kfx", PROCESSOR_24KF1_1, 33 },
784 { "24kx", PROCESSOR_24KF1_1, 33 },
786 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
787 { "24kef2_1", PROCESSOR_24KF2_1, 33 },
788 { "24kef", PROCESSOR_24KF2_1, 33 },
789 { "24kef1_1", PROCESSOR_24KF1_1, 33 },
790 { "24kefx", PROCESSOR_24KF1_1, 33 },
791 { "24kex", PROCESSOR_24KF1_1, 33 },
793 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
794 { "34kf2_1", PROCESSOR_24KF2_1, 33 },
795 { "34kf", PROCESSOR_24KF2_1, 33 },
796 { "34kf1_1", PROCESSOR_24KF1_1, 33 },
797 { "34kfx", PROCESSOR_24KF1_1, 33 },
798 { "34kx", PROCESSOR_24KF1_1, 33 },
800 { "74kc", PROCESSOR_74KC, 33 }, /* 74K with DSPr2 */
801 { "74kf2_1", PROCESSOR_74KF2_1, 33 },
802 { "74kf", PROCESSOR_74KF2_1, 33 },
803 { "74kf1_1", PROCESSOR_74KF1_1, 33 },
804 { "74kfx", PROCESSOR_74KF1_1, 33 },
805 { "74kx", PROCESSOR_74KF1_1, 33 },
806 { "74kf3_2", PROCESSOR_74KF3_2, 33 },
809 { "5kc", PROCESSOR_5KC, 64 },
810 { "5kf", PROCESSOR_5KF, 64 },
811 { "20kc", PROCESSOR_20KC, 64 },
812 { "sb1", PROCESSOR_SB1, 64 },
813 { "sb1a", PROCESSOR_SB1A, 64 },
814 { "sr71000", PROCESSOR_SR71000, 64 },
820 /* Default costs. If these are used for a processor we should look
821 up the actual costs. */
822 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
823 COSTS_N_INSNS (7), /* fp_mult_sf */ \
824 COSTS_N_INSNS (8), /* fp_mult_df */ \
825 COSTS_N_INSNS (23), /* fp_div_sf */ \
826 COSTS_N_INSNS (36), /* fp_div_df */ \
827 COSTS_N_INSNS (10), /* int_mult_si */ \
828 COSTS_N_INSNS (10), /* int_mult_di */ \
829 COSTS_N_INSNS (69), /* int_div_si */ \
830 COSTS_N_INSNS (69), /* int_div_di */ \
831 2, /* branch_cost */ \
832 4 /* memory_latency */
834 /* Need to replace these with the costs of calling the appropriate
836 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
837 COSTS_N_INSNS (256), /* fp_mult_sf */ \
838 COSTS_N_INSNS (256), /* fp_mult_df */ \
839 COSTS_N_INSNS (256), /* fp_div_sf */ \
840 COSTS_N_INSNS (256) /* fp_div_df */
842 static struct mips_rtx_cost_data const mips_rtx_cost_optimize_size =
844 COSTS_N_INSNS (1), /* fp_add */
845 COSTS_N_INSNS (1), /* fp_mult_sf */
846 COSTS_N_INSNS (1), /* fp_mult_df */
847 COSTS_N_INSNS (1), /* fp_div_sf */
848 COSTS_N_INSNS (1), /* fp_div_df */
849 COSTS_N_INSNS (1), /* int_mult_si */
850 COSTS_N_INSNS (1), /* int_mult_di */
851 COSTS_N_INSNS (1), /* int_div_si */
852 COSTS_N_INSNS (1), /* int_div_di */
854 4 /* memory_latency */
857 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
860 COSTS_N_INSNS (2), /* fp_add */
861 COSTS_N_INSNS (4), /* fp_mult_sf */
862 COSTS_N_INSNS (5), /* fp_mult_df */
863 COSTS_N_INSNS (12), /* fp_div_sf */
864 COSTS_N_INSNS (19), /* fp_div_df */
865 COSTS_N_INSNS (12), /* int_mult_si */
866 COSTS_N_INSNS (12), /* int_mult_di */
867 COSTS_N_INSNS (35), /* int_div_si */
868 COSTS_N_INSNS (35), /* int_div_di */
870 4 /* memory_latency */
875 COSTS_N_INSNS (6), /* int_mult_si */
876 COSTS_N_INSNS (6), /* int_mult_di */
877 COSTS_N_INSNS (36), /* int_div_si */
878 COSTS_N_INSNS (36), /* int_div_di */
880 4 /* memory_latency */
884 COSTS_N_INSNS (36), /* int_mult_si */
885 COSTS_N_INSNS (36), /* int_mult_di */
886 COSTS_N_INSNS (37), /* int_div_si */
887 COSTS_N_INSNS (37), /* int_div_di */
889 4 /* memory_latency */
893 COSTS_N_INSNS (4), /* int_mult_si */
894 COSTS_N_INSNS (11), /* int_mult_di */
895 COSTS_N_INSNS (36), /* int_div_si */
896 COSTS_N_INSNS (68), /* int_div_di */
898 4 /* memory_latency */
901 COSTS_N_INSNS (4), /* fp_add */
902 COSTS_N_INSNS (4), /* fp_mult_sf */
903 COSTS_N_INSNS (5), /* fp_mult_df */
904 COSTS_N_INSNS (17), /* fp_div_sf */
905 COSTS_N_INSNS (32), /* fp_div_df */
906 COSTS_N_INSNS (4), /* int_mult_si */
907 COSTS_N_INSNS (11), /* int_mult_di */
908 COSTS_N_INSNS (36), /* int_div_si */
909 COSTS_N_INSNS (68), /* int_div_di */
911 4 /* memory_latency */
914 COSTS_N_INSNS (4), /* fp_add */
915 COSTS_N_INSNS (4), /* fp_mult_sf */
916 COSTS_N_INSNS (5), /* fp_mult_df */
917 COSTS_N_INSNS (17), /* fp_div_sf */
918 COSTS_N_INSNS (32), /* fp_div_df */
919 COSTS_N_INSNS (4), /* int_mult_si */
920 COSTS_N_INSNS (7), /* int_mult_di */
921 COSTS_N_INSNS (42), /* int_div_si */
922 COSTS_N_INSNS (72), /* int_div_di */
924 4 /* memory_latency */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (41), /* int_div_si */
931 COSTS_N_INSNS (41), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (8), /* fp_add */
937 COSTS_N_INSNS (8), /* fp_mult_sf */
938 COSTS_N_INSNS (10), /* fp_mult_df */
939 COSTS_N_INSNS (34), /* fp_div_sf */
940 COSTS_N_INSNS (64), /* fp_div_df */
941 COSTS_N_INSNS (5), /* int_mult_si */
942 COSTS_N_INSNS (5), /* int_mult_di */
943 COSTS_N_INSNS (41), /* int_div_si */
944 COSTS_N_INSNS (41), /* int_div_di */
946 4 /* memory_latency */
949 COSTS_N_INSNS (4), /* fp_add */
950 COSTS_N_INSNS (4), /* fp_mult_sf */
951 COSTS_N_INSNS (5), /* fp_mult_df */
952 COSTS_N_INSNS (17), /* fp_div_sf */
953 COSTS_N_INSNS (32), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (5), /* int_mult_di */
956 COSTS_N_INSNS (41), /* int_div_si */
957 COSTS_N_INSNS (41), /* int_div_di */
959 4 /* memory_latency */
963 COSTS_N_INSNS (5), /* int_mult_si */
964 COSTS_N_INSNS (5), /* int_mult_di */
965 COSTS_N_INSNS (41), /* int_div_si */
966 COSTS_N_INSNS (41), /* int_div_di */
968 4 /* memory_latency */
971 COSTS_N_INSNS (8), /* fp_add */
972 COSTS_N_INSNS (8), /* fp_mult_sf */
973 COSTS_N_INSNS (10), /* fp_mult_df */
974 COSTS_N_INSNS (34), /* fp_div_sf */
975 COSTS_N_INSNS (64), /* fp_div_df */
976 COSTS_N_INSNS (5), /* int_mult_si */
977 COSTS_N_INSNS (5), /* int_mult_di */
978 COSTS_N_INSNS (41), /* int_div_si */
979 COSTS_N_INSNS (41), /* int_div_di */
981 4 /* memory_latency */
984 COSTS_N_INSNS (4), /* fp_add */
985 COSTS_N_INSNS (4), /* fp_mult_sf */
986 COSTS_N_INSNS (5), /* fp_mult_df */
987 COSTS_N_INSNS (17), /* fp_div_sf */
988 COSTS_N_INSNS (32), /* fp_div_df */
989 COSTS_N_INSNS (5), /* int_mult_si */
990 COSTS_N_INSNS (5), /* int_mult_di */
991 COSTS_N_INSNS (41), /* int_div_si */
992 COSTS_N_INSNS (41), /* int_div_di */
994 4 /* memory_latency */
997 COSTS_N_INSNS (6), /* fp_add */
998 COSTS_N_INSNS (6), /* fp_mult_sf */
999 COSTS_N_INSNS (7), /* fp_mult_df */
1000 COSTS_N_INSNS (25), /* fp_div_sf */
1001 COSTS_N_INSNS (48), /* fp_div_df */
1002 COSTS_N_INSNS (5), /* int_mult_si */
1003 COSTS_N_INSNS (5), /* int_mult_di */
1004 COSTS_N_INSNS (41), /* int_div_si */
1005 COSTS_N_INSNS (41), /* int_div_di */
1006 1, /* branch_cost */
1007 4 /* memory_latency */
1013 COSTS_N_INSNS (2), /* fp_add */
1014 COSTS_N_INSNS (4), /* fp_mult_sf */
1015 COSTS_N_INSNS (5), /* fp_mult_df */
1016 COSTS_N_INSNS (12), /* fp_div_sf */
1017 COSTS_N_INSNS (19), /* fp_div_df */
1018 COSTS_N_INSNS (2), /* int_mult_si */
1019 COSTS_N_INSNS (2), /* int_mult_di */
1020 COSTS_N_INSNS (35), /* int_div_si */
1021 COSTS_N_INSNS (35), /* int_div_di */
1022 1, /* branch_cost */
1023 4 /* memory_latency */
1026 COSTS_N_INSNS (3), /* fp_add */
1027 COSTS_N_INSNS (5), /* fp_mult_sf */
1028 COSTS_N_INSNS (6), /* fp_mult_df */
1029 COSTS_N_INSNS (15), /* fp_div_sf */
1030 COSTS_N_INSNS (16), /* fp_div_df */
1031 COSTS_N_INSNS (17), /* int_mult_si */
1032 COSTS_N_INSNS (17), /* int_mult_di */
1033 COSTS_N_INSNS (38), /* int_div_si */
1034 COSTS_N_INSNS (38), /* int_div_di */
1035 2, /* branch_cost */
1036 6 /* memory_latency */
1039 COSTS_N_INSNS (6), /* fp_add */
1040 COSTS_N_INSNS (7), /* fp_mult_sf */
1041 COSTS_N_INSNS (8), /* fp_mult_df */
1042 COSTS_N_INSNS (23), /* fp_div_sf */
1043 COSTS_N_INSNS (36), /* fp_div_df */
1044 COSTS_N_INSNS (10), /* int_mult_si */
1045 COSTS_N_INSNS (10), /* int_mult_di */
1046 COSTS_N_INSNS (69), /* int_div_si */
1047 COSTS_N_INSNS (69), /* int_div_di */
1048 2, /* branch_cost */
1049 6 /* memory_latency */
1061 /* The only costs that appear to be updated here are
1062 integer multiplication. */
1064 COSTS_N_INSNS (4), /* int_mult_si */
1065 COSTS_N_INSNS (6), /* int_mult_di */
1066 COSTS_N_INSNS (69), /* int_div_si */
1067 COSTS_N_INSNS (69), /* int_div_di */
1068 1, /* branch_cost */
1069 4 /* memory_latency */
1081 COSTS_N_INSNS (6), /* fp_add */
1082 COSTS_N_INSNS (4), /* fp_mult_sf */
1083 COSTS_N_INSNS (5), /* fp_mult_df */
1084 COSTS_N_INSNS (23), /* fp_div_sf */
1085 COSTS_N_INSNS (36), /* fp_div_df */
1086 COSTS_N_INSNS (5), /* int_mult_si */
1087 COSTS_N_INSNS (5), /* int_mult_di */
1088 COSTS_N_INSNS (36), /* int_div_si */
1089 COSTS_N_INSNS (36), /* int_div_di */
1090 1, /* branch_cost */
1091 4 /* memory_latency */
1094 COSTS_N_INSNS (6), /* fp_add */
1095 COSTS_N_INSNS (5), /* fp_mult_sf */
1096 COSTS_N_INSNS (6), /* fp_mult_df */
1097 COSTS_N_INSNS (30), /* fp_div_sf */
1098 COSTS_N_INSNS (59), /* fp_div_df */
1099 COSTS_N_INSNS (3), /* int_mult_si */
1100 COSTS_N_INSNS (4), /* int_mult_di */
1101 COSTS_N_INSNS (42), /* int_div_si */
1102 COSTS_N_INSNS (74), /* int_div_di */
1103 1, /* branch_cost */
1104 4 /* memory_latency */
1107 COSTS_N_INSNS (6), /* fp_add */
1108 COSTS_N_INSNS (5), /* fp_mult_sf */
1109 COSTS_N_INSNS (6), /* fp_mult_df */
1110 COSTS_N_INSNS (30), /* fp_div_sf */
1111 COSTS_N_INSNS (59), /* fp_div_df */
1112 COSTS_N_INSNS (5), /* int_mult_si */
1113 COSTS_N_INSNS (9), /* int_mult_di */
1114 COSTS_N_INSNS (42), /* int_div_si */
1115 COSTS_N_INSNS (74), /* int_div_di */
1116 1, /* branch_cost */
1117 4 /* memory_latency */
1120 /* The only costs that are changed here are
1121 integer multiplication. */
1122 COSTS_N_INSNS (6), /* fp_add */
1123 COSTS_N_INSNS (7), /* fp_mult_sf */
1124 COSTS_N_INSNS (8), /* fp_mult_df */
1125 COSTS_N_INSNS (23), /* fp_div_sf */
1126 COSTS_N_INSNS (36), /* fp_div_df */
1127 COSTS_N_INSNS (5), /* int_mult_si */
1128 COSTS_N_INSNS (9), /* int_mult_di */
1129 COSTS_N_INSNS (69), /* int_div_si */
1130 COSTS_N_INSNS (69), /* int_div_di */
1131 1, /* branch_cost */
1132 4 /* memory_latency */
1138 /* The only costs that are changed here are
1139 integer multiplication. */
1140 COSTS_N_INSNS (6), /* fp_add */
1141 COSTS_N_INSNS (7), /* fp_mult_sf */
1142 COSTS_N_INSNS (8), /* fp_mult_df */
1143 COSTS_N_INSNS (23), /* fp_div_sf */
1144 COSTS_N_INSNS (36), /* fp_div_df */
1145 COSTS_N_INSNS (3), /* int_mult_si */
1146 COSTS_N_INSNS (8), /* int_mult_di */
1147 COSTS_N_INSNS (69), /* int_div_si */
1148 COSTS_N_INSNS (69), /* int_div_di */
1149 1, /* branch_cost */
1150 4 /* memory_latency */
1153 /* These costs are the same as the SB-1A below. */
1154 COSTS_N_INSNS (4), /* fp_add */
1155 COSTS_N_INSNS (4), /* fp_mult_sf */
1156 COSTS_N_INSNS (4), /* fp_mult_df */
1157 COSTS_N_INSNS (24), /* fp_div_sf */
1158 COSTS_N_INSNS (32), /* fp_div_df */
1159 COSTS_N_INSNS (3), /* int_mult_si */
1160 COSTS_N_INSNS (4), /* int_mult_di */
1161 COSTS_N_INSNS (36), /* int_div_si */
1162 COSTS_N_INSNS (68), /* int_div_di */
1163 1, /* branch_cost */
1164 4 /* memory_latency */
1167 /* These costs are the same as the SB-1 above. */
1168 COSTS_N_INSNS (4), /* fp_add */
1169 COSTS_N_INSNS (4), /* fp_mult_sf */
1170 COSTS_N_INSNS (4), /* fp_mult_df */
1171 COSTS_N_INSNS (24), /* fp_div_sf */
1172 COSTS_N_INSNS (32), /* fp_div_df */
1173 COSTS_N_INSNS (3), /* int_mult_si */
1174 COSTS_N_INSNS (4), /* int_mult_di */
1175 COSTS_N_INSNS (36), /* int_div_si */
1176 COSTS_N_INSNS (68), /* int_div_di */
1177 1, /* branch_cost */
1178 4 /* memory_latency */
1185 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
1186 mips16e_s2_s8_regs[X], it must also save the registers in indexes
1187 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
1188 static const unsigned char mips16e_s2_s8_regs[] = {
1189 30, 23, 22, 21, 20, 19, 18
1191 static const unsigned char mips16e_a0_a3_regs[] = {
1195 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
1196 ordered from the uppermost in memory to the lowest in memory. */
1197 static const unsigned char mips16e_save_restore_regs[] = {
1198 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
1201 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1202 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1203 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1206 /* Initialize the GCC target structure. */
1207 #undef TARGET_ASM_ALIGNED_HI_OP
1208 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1209 #undef TARGET_ASM_ALIGNED_SI_OP
1210 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1211 #undef TARGET_ASM_ALIGNED_DI_OP
1212 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1214 #undef TARGET_ASM_FUNCTION_PROLOGUE
1215 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1216 #undef TARGET_ASM_FUNCTION_EPILOGUE
1217 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1218 #undef TARGET_ASM_SELECT_RTX_SECTION
1219 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1220 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1221 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1223 #undef TARGET_SCHED_REORDER
1224 #define TARGET_SCHED_REORDER mips_sched_reorder
1225 #undef TARGET_SCHED_VARIABLE_ISSUE
1226 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1227 #undef TARGET_SCHED_ADJUST_COST
1228 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1229 #undef TARGET_SCHED_ISSUE_RATE
1230 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1231 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1232 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1233 mips_multipass_dfa_lookahead
1235 #undef TARGET_DEFAULT_TARGET_FLAGS
1236 #define TARGET_DEFAULT_TARGET_FLAGS \
1238 | TARGET_CPU_DEFAULT \
1239 | TARGET_ENDIAN_DEFAULT \
1240 | TARGET_FP_EXCEPTIONS_DEFAULT \
1241 | MASK_CHECK_ZERO_DIV \
1243 #undef TARGET_HANDLE_OPTION
1244 #define TARGET_HANDLE_OPTION mips_handle_option
1246 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1247 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1249 #undef TARGET_VALID_POINTER_MODE
1250 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1251 #undef TARGET_RTX_COSTS
1252 #define TARGET_RTX_COSTS mips_rtx_costs
1253 #undef TARGET_ADDRESS_COST
1254 #define TARGET_ADDRESS_COST mips_address_cost
1256 #undef TARGET_IN_SMALL_DATA_P
1257 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1259 #undef TARGET_MACHINE_DEPENDENT_REORG
1260 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1262 #undef TARGET_ASM_FILE_START
1263 #define TARGET_ASM_FILE_START mips_file_start
1264 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1265 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1267 #undef TARGET_INIT_LIBFUNCS
1268 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1270 #undef TARGET_BUILD_BUILTIN_VA_LIST
1271 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1272 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1273 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1275 #undef TARGET_PROMOTE_FUNCTION_ARGS
1276 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1277 #undef TARGET_PROMOTE_FUNCTION_RETURN
1278 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1279 #undef TARGET_PROMOTE_PROTOTYPES
1280 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1282 #undef TARGET_RETURN_IN_MEMORY
1283 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1284 #undef TARGET_RETURN_IN_MSB
1285 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1287 #undef TARGET_ASM_OUTPUT_MI_THUNK
1288 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1289 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1290 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1292 #undef TARGET_SETUP_INCOMING_VARARGS
1293 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1294 #undef TARGET_STRICT_ARGUMENT_NAMING
1295 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1296 #undef TARGET_MUST_PASS_IN_STACK
1297 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1298 #undef TARGET_PASS_BY_REFERENCE
1299 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1300 #undef TARGET_CALLEE_COPIES
1301 #define TARGET_CALLEE_COPIES mips_callee_copies
1302 #undef TARGET_ARG_PARTIAL_BYTES
1303 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1305 #undef TARGET_MODE_REP_EXTENDED
1306 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1308 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1309 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1311 #undef TARGET_INIT_BUILTINS
1312 #define TARGET_INIT_BUILTINS mips_init_builtins
1313 #undef TARGET_EXPAND_BUILTIN
1314 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1316 #undef TARGET_HAVE_TLS
1317 #define TARGET_HAVE_TLS HAVE_AS_TLS
1319 #undef TARGET_CANNOT_FORCE_CONST_MEM
1320 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1322 #undef TARGET_ENCODE_SECTION_INFO
1323 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1325 #undef TARGET_ATTRIBUTE_TABLE
1326 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1328 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1329 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1331 #undef TARGET_MIN_ANCHOR_OFFSET
1332 #define TARGET_MIN_ANCHOR_OFFSET -32768
1333 #undef TARGET_MAX_ANCHOR_OFFSET
1334 #define TARGET_MAX_ANCHOR_OFFSET 32767
1335 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1336 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1337 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1338 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1340 #undef TARGET_COMP_TYPE_ATTRIBUTES
1341 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
1343 #ifdef HAVE_AS_DTPRELWORD
1344 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1345 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
1348 struct gcc_target targetm = TARGET_INITIALIZER;
1351 /* Predicates to test for presence of "near" and "far"/"long_call"
1352 attributes on the given TYPE. */
1355 mips_near_type_p (tree type)
1357 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1361 mips_far_type_p (tree type)
1363 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1364 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1368 /* Return 0 if the attributes for two types are incompatible, 1 if they
1369 are compatible, and 2 if they are nearly compatible (which causes a
1370 warning to be generated). */
1373 mips_comp_type_attributes (tree type1, tree type2)
1375 /* Check for mismatch of non-default calling convention. */
1376 if (TREE_CODE (type1) != FUNCTION_TYPE)
1379 /* Disallow mixed near/far attributes. */
1380 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1382 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1388 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1389 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1392 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1394 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1396 *base_ptr = XEXP (x, 0);
1397 *offset_ptr = INTVAL (XEXP (x, 1));
1406 /* Return true if SYMBOL_REF X is associated with a global symbol
1407 (in the STB_GLOBAL sense). */
1410 mips_global_symbol_p (rtx x)
1414 decl = SYMBOL_REF_DECL (x);
1416 return !SYMBOL_REF_LOCAL_P (x);
1418 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1419 or weak symbols. Relocations in the object file will be against
1420 the target symbol, so it's that symbol's binding that matters here. */
1421 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1424 /* Return true if SYMBOL_REF X binds locally. */
1427 mips_symbol_binds_local_p (rtx x)
1429 return (SYMBOL_REF_DECL (x)
1430 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1431 : SYMBOL_REF_LOCAL_P (x));
1434 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1436 static enum mips_symbol_type
1437 mips_classify_symbol (rtx x)
1440 return SYMBOL_GOT_DISP;
1442 if (GET_CODE (x) == LABEL_REF)
1445 return SYMBOL_CONSTANT_POOL;
1446 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1447 return SYMBOL_GOT_PAGE_OFST;
1448 return SYMBOL_GENERAL;
1451 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1453 if (SYMBOL_REF_TLS_MODEL (x))
1456 if (CONSTANT_POOL_ADDRESS_P (x))
1459 return SYMBOL_CONSTANT_POOL;
1461 if (!TARGET_EMBEDDED_DATA
1462 && GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1463 return SYMBOL_SMALL_DATA;
1466 /* Do not use small-data accesses for weak symbols; they may end up
1468 if (SYMBOL_REF_SMALL_P (x)
1469 && !SYMBOL_REF_WEAK (x))
1470 return SYMBOL_SMALL_DATA;
1472 if (TARGET_ABICALLS)
1474 /* Don't use GOT accesses for locally-binding symbols; we can use
1475 %hi and %lo instead. */
1476 if (TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))
1477 return SYMBOL_GENERAL;
1479 /* There are three cases to consider:
1481 - o32 PIC (either with or without explicit relocs)
1482 - n32/n64 PIC without explicit relocs
1483 - n32/n64 PIC with explicit relocs
1485 In the first case, both local and global accesses will use an
1486 R_MIPS_GOT16 relocation. We must correctly predict which of
1487 the two semantics (local or global) the assembler and linker
1488 will apply. The choice depends on the symbol's binding rather
1489 than its visibility.
1491 In the second case, the assembler will not use R_MIPS_GOT16
1492 relocations, but it chooses between local and global accesses
1493 in the same way as for o32 PIC.
1495 In the third case we have more freedom since both forms of
1496 access will work for any kind of symbol. However, there seems
1497 little point in doing things differently. */
1498 if (mips_global_symbol_p (x))
1499 return SYMBOL_GOT_DISP;
1501 return SYMBOL_GOT_PAGE_OFST;
1504 return SYMBOL_GENERAL;
1507 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1508 is the alignment (in bytes) of SYMBOL_REF X. */
1511 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1513 /* If for some reason we can't get the alignment for the
1514 symbol, initializing this to one means we will only accept
1516 HOST_WIDE_INT align = 1;
1519 /* Get the alignment of the symbol we're referring to. */
1520 t = SYMBOL_REF_DECL (x);
1522 align = DECL_ALIGN_UNIT (t);
1524 return offset >= 0 && offset < align;
1527 /* Return true if X is a symbolic constant that can be calculated in
1528 the same way as a bare symbol. If it is, store the type of the
1529 symbol in *SYMBOL_TYPE. */
1532 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1536 split_const (x, &x, &offset);
1537 if (UNSPEC_ADDRESS_P (x))
1539 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1540 x = UNSPEC_ADDRESS (x);
1542 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1544 *symbol_type = mips_classify_symbol (x);
1545 if (*symbol_type == SYMBOL_TLS)
1551 if (offset == const0_rtx)
1554 /* Check whether a nonzero offset is valid for the underlying
1556 switch (*symbol_type)
1558 case SYMBOL_GENERAL:
1559 case SYMBOL_64_HIGH:
1562 /* If the target has 64-bit pointers and the object file only
1563 supports 32-bit symbols, the values of those symbols will be
1564 sign-extended. In this case we can't allow an arbitrary offset
1565 in case the 32-bit value X + OFFSET has a different sign from X. */
1566 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1567 return offset_within_block_p (x, INTVAL (offset));
1569 /* In other cases the relocations can handle any offset. */
1572 case SYMBOL_CONSTANT_POOL:
1573 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1574 In this case, we no longer have access to the underlying constant,
1575 but the original symbol-based access was known to be valid. */
1576 if (GET_CODE (x) == LABEL_REF)
1581 case SYMBOL_SMALL_DATA:
1582 /* Make sure that the offset refers to something within the
1583 same object block. This should guarantee that the final
1584 PC- or GP-relative offset is within the 16-bit limit. */
1585 return offset_within_block_p (x, INTVAL (offset));
1587 case SYMBOL_GOT_PAGE_OFST:
1588 case SYMBOL_GOTOFF_PAGE:
1589 /* If the symbol is global, the GOT entry will contain the symbol's
1590 address, and we will apply a 16-bit offset after loading it.
1591 If the symbol is local, the linker should provide enough local
1592 GOT entries for a 16-bit offset, but larger offsets may lead
1594 return SMALL_INT (offset);
1598 /* There is no carry between the HI and LO REL relocations, so the
1599 offset is only valid if we know it won't lead to such a carry. */
1600 return mips_offset_within_alignment_p (x, INTVAL (offset));
1602 case SYMBOL_GOT_DISP:
1603 case SYMBOL_GOTOFF_DISP:
1604 case SYMBOL_GOTOFF_CALL:
1605 case SYMBOL_GOTOFF_LOADGP:
1608 case SYMBOL_GOTTPREL:
1617 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1620 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1622 if (!HARD_REGISTER_NUM_P (regno))
1626 regno = reg_renumber[regno];
1629 /* These fake registers will be eliminated to either the stack or
1630 hard frame pointer, both of which are usually valid base registers.
1631 Reload deals with the cases where the eliminated form isn't valid. */
1632 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1635 /* In mips16 mode, the stack pointer can only address word and doubleword
1636 values, nothing smaller. There are two problems here:
1638 (a) Instantiating virtual registers can introduce new uses of the
1639 stack pointer. If these virtual registers are valid addresses,
1640 the stack pointer should be too.
1642 (b) Most uses of the stack pointer are not made explicit until
1643 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1644 We don't know until that stage whether we'll be eliminating to the
1645 stack pointer (which needs the restriction) or the hard frame
1646 pointer (which doesn't).
1648 All in all, it seems more consistent to only enforce this restriction
1649 during and after reload. */
1650 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1651 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1653 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1657 /* Return true if X is a valid base register for the given mode.
1658 Allow only hard registers if STRICT. */
1661 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1663 if (!strict && GET_CODE (x) == SUBREG)
1667 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1671 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1672 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1675 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1676 enum machine_mode mode)
1678 switch (symbol_type)
1680 case SYMBOL_GENERAL:
1681 return !TARGET_MIPS16;
1683 case SYMBOL_SMALL_DATA:
1686 case SYMBOL_CONSTANT_POOL:
1687 /* PC-relative addressing is only available for lw and ld. */
1688 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1690 case SYMBOL_GOT_PAGE_OFST:
1693 case SYMBOL_GOT_DISP:
1694 /* The address will have to be loaded from the GOT first. */
1697 case SYMBOL_GOTOFF_PAGE:
1698 case SYMBOL_GOTOFF_DISP:
1699 case SYMBOL_GOTOFF_CALL:
1700 case SYMBOL_GOTOFF_LOADGP:
1705 case SYMBOL_GOTTPREL:
1707 case SYMBOL_64_HIGH:
1717 /* Return true if X is a valid address for machine mode MODE. If it is,
1718 fill in INFO appropriately. STRICT is true if we should only accept
1719 hard base registers. */
1722 mips_classify_address (struct mips_address_info *info, rtx x,
1723 enum machine_mode mode, int strict)
1725 switch (GET_CODE (x))
1729 info->type = ADDRESS_REG;
1731 info->offset = const0_rtx;
1732 return mips_valid_base_register_p (info->reg, mode, strict);
1735 info->type = ADDRESS_REG;
1736 info->reg = XEXP (x, 0);
1737 info->offset = XEXP (x, 1);
1738 return (mips_valid_base_register_p (info->reg, mode, strict)
1739 && const_arith_operand (info->offset, VOIDmode));
1742 info->type = ADDRESS_LO_SUM;
1743 info->reg = XEXP (x, 0);
1744 info->offset = XEXP (x, 1);
1745 return (mips_valid_base_register_p (info->reg, mode, strict)
1746 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1747 && mips_symbolic_address_p (info->symbol_type, mode)
1748 && mips_lo_relocs[info->symbol_type] != 0);
1751 /* Small-integer addresses don't occur very often, but they
1752 are legitimate if $0 is a valid base register. */
1753 info->type = ADDRESS_CONST_INT;
1754 return !TARGET_MIPS16 && SMALL_INT (x);
1759 info->type = ADDRESS_SYMBOLIC;
1760 return (mips_symbolic_constant_p (x, &info->symbol_type)
1761 && mips_symbolic_address_p (info->symbol_type, mode)
1762 && !mips_split_p[info->symbol_type]);
1769 /* Return true if X is a thread-local symbol. */
1772 mips_tls_operand_p (rtx x)
1774 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1777 /* Return true if X can not be forced into a constant pool. */
1780 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1782 return mips_tls_operand_p (*x);
1785 /* Return true if X can not be forced into a constant pool. */
1788 mips_cannot_force_const_mem (rtx x)
1794 /* As an optimization, reject constants that mips_legitimize_move
1797 Suppose we have a multi-instruction sequence that loads constant C
1798 into register R. If R does not get allocated a hard register, and
1799 R is used in an operand that allows both registers and memory
1800 references, reload will consider forcing C into memory and using
1801 one of the instruction's memory alternatives. Returning false
1802 here will force it to use an input reload instead. */
1803 if (GET_CODE (x) == CONST_INT)
1806 split_const (x, &base, &offset);
1807 if (symbolic_operand (base, VOIDmode) && SMALL_INT (offset))
1811 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1817 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1818 constant pools, but normal-mode code doesn't need to. */
1821 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1822 rtx x ATTRIBUTE_UNUSED)
1824 return !TARGET_MIPS16;
1827 /* Return the number of instructions needed to load a symbol of the
1828 given type into a register. If valid in an address, the same number
1829 of instructions are needed for loads and stores. Treat extended
1830 mips16 instructions as two instructions. */
1833 mips_symbol_insns (enum mips_symbol_type type)
1837 case SYMBOL_GENERAL:
1838 /* In mips16 code, general symbols must be fetched from the
1843 /* When using 64-bit symbols, we need 5 preparatory instructions,
1846 lui $at,%highest(symbol)
1847 daddiu $at,$at,%higher(symbol)
1849 daddiu $at,$at,%hi(symbol)
1852 The final address is then $at + %lo(symbol). With 32-bit
1853 symbols we just need a preparatory lui. */
1854 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1856 case SYMBOL_SMALL_DATA:
1860 case SYMBOL_CONSTANT_POOL:
1861 /* This case is for mips16 only. Assume we'll need an
1862 extended instruction. */
1865 case SYMBOL_GOT_PAGE_OFST:
1866 case SYMBOL_GOT_DISP:
1867 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1868 the local/global classification is accurate. See override_options
1871 The worst cases are:
1873 (1) For local symbols when generating o32 or o64 code. The assembler
1879 ...and the final address will be $at + %lo(symbol).
1881 (2) For global symbols when -mxgot. The assembler will use:
1883 lui $at,%got_hi(symbol)
1886 ...and the final address will be $at + %got_lo(symbol). */
1889 case SYMBOL_GOTOFF_PAGE:
1890 case SYMBOL_GOTOFF_DISP:
1891 case SYMBOL_GOTOFF_CALL:
1892 case SYMBOL_GOTOFF_LOADGP:
1893 case SYMBOL_64_HIGH:
1899 case SYMBOL_GOTTPREL:
1901 /* Check whether the offset is a 16- or 32-bit value. */
1902 return mips_split_p[type] ? 2 : 1;
1905 /* We don't treat a bare TLS symbol as a constant. */
1911 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1914 mips_stack_address_p (rtx x, enum machine_mode mode)
1916 struct mips_address_info addr;
1918 return (mips_classify_address (&addr, x, mode, false)
1919 && addr.type == ADDRESS_REG
1920 && addr.reg == stack_pointer_rtx);
1923 /* Return true if a value at OFFSET bytes from BASE can be accessed
1924 using an unextended mips16 instruction. MODE is the mode of the
1927 Usually the offset in an unextended instruction is a 5-bit field.
1928 The offset is unsigned and shifted left once for HIs, twice
1929 for SIs, and so on. An exception is SImode accesses off the
1930 stack pointer, which have an 8-bit immediate field. */
1933 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1936 && GET_CODE (offset) == CONST_INT
1937 && INTVAL (offset) >= 0
1938 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1940 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1941 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1942 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1948 /* Return the number of instructions needed to load or store a value
1949 of mode MODE at X. Return 0 if X isn't valid for MODE.
1951 For mips16 code, count extended instructions as two instructions. */
1954 mips_address_insns (rtx x, enum machine_mode mode)
1956 struct mips_address_info addr;
1959 if (mode == BLKmode)
1960 /* BLKmode is used for single unaligned loads and stores. */
1963 /* Each word of a multi-word value will be accessed individually. */
1964 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1966 if (mips_classify_address (&addr, x, mode, false))
1971 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1975 case ADDRESS_LO_SUM:
1976 return (TARGET_MIPS16 ? factor * 2 : factor);
1978 case ADDRESS_CONST_INT:
1981 case ADDRESS_SYMBOLIC:
1982 return factor * mips_symbol_insns (addr.symbol_type);
1988 /* Likewise for constant X. */
1991 mips_const_insns (rtx x)
1993 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1994 enum mips_symbol_type symbol_type;
1997 switch (GET_CODE (x))
2001 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
2002 || !mips_split_p[symbol_type])
2009 /* Unsigned 8-bit constants can be loaded using an unextended
2010 LI instruction. Unsigned 16-bit constants can be loaded
2011 using an extended LI. Negative constants must be loaded
2012 using LI and then negated. */
2013 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
2014 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2015 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
2016 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2019 return mips_build_integer (codes, INTVAL (x));
2023 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
2029 /* See if we can refer to X directly. */
2030 if (mips_symbolic_constant_p (x, &symbol_type))
2031 return mips_symbol_insns (symbol_type);
2033 /* Otherwise try splitting the constant into a base and offset.
2034 16-bit offsets can be added using an extra addiu. Larger offsets
2035 must be calculated separately and then added to the base. */
2036 split_const (x, &x, &offset);
2039 int n = mips_const_insns (x);
2042 if (SMALL_INT (offset))
2045 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2052 return mips_symbol_insns (mips_classify_symbol (x));
2060 /* Return the number of instructions needed for memory reference X.
2061 Count extended mips16 instructions as two instructions. */
2064 mips_fetch_insns (rtx x)
2066 gcc_assert (MEM_P (x));
2067 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
2071 /* Return the number of instructions needed for an integer division. */
2074 mips_idiv_insns (void)
2079 if (TARGET_CHECK_ZERO_DIV)
2081 if (GENERATE_DIVIDE_TRAPS)
2087 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2092 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
2093 returns a nonzero value if X is a legitimate address for a memory
2094 operand of the indicated MODE. STRICT is nonzero if this function
2095 is called during reload. */
2098 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
2100 struct mips_address_info addr;
2102 return mips_classify_address (&addr, x, mode, strict);
2106 /* Copy VALUE to a register and return that register. If new psuedos
2107 are allowed, copy it into a new register, otherwise use DEST. */
2110 mips_force_temporary (rtx dest, rtx value)
2112 if (can_create_pseudo_p ())
2113 return force_reg (Pmode, value);
2116 emit_move_insn (copy_rtx (dest), value);
2122 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
2123 and is used to load the high part into a register. */
2126 mips_split_symbol (rtx temp, rtx addr)
2131 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
2132 else if (!can_create_pseudo_p ())
2134 emit_insn (gen_load_const_gp (copy_rtx (temp)));
2138 high = mips16_gp_pseudo_reg ();
2139 return gen_rtx_LO_SUM (Pmode, high, addr);
2143 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2144 type SYMBOL_TYPE. */
2147 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2151 split_const (address, &base, &offset);
2152 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2153 UNSPEC_ADDRESS_FIRST + symbol_type);
2154 if (offset != const0_rtx)
2155 base = gen_rtx_PLUS (Pmode, base, offset);
2156 return gen_rtx_CONST (Pmode, base);
2160 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2161 high part to BASE and return the result. Just return BASE otherwise.
2162 TEMP is available as a temporary register if needed.
2164 The returned expression can be used as the first operand to a LO_SUM. */
2167 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2168 enum mips_symbol_type symbol_type)
2170 if (mips_split_p[symbol_type])
2172 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2173 addr = mips_force_temporary (temp, addr);
2174 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2180 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2181 mips_force_temporary; it is only needed when OFFSET is not a
2185 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2187 if (!SMALL_OPERAND (offset))
2192 /* Load the full offset into a register so that we can use
2193 an unextended instruction for the address itself. */
2194 high = GEN_INT (offset);
2199 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2200 high = GEN_INT (CONST_HIGH_PART (offset));
2201 offset = CONST_LOW_PART (offset);
2203 high = mips_force_temporary (temp, high);
2204 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2206 return plus_constant (reg, offset);
2209 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2210 referencing, and TYPE is the symbol type to use (either global
2211 dynamic or local dynamic). V0 is an RTX for the return value
2212 location. The entire insn sequence is returned. */
2214 static GTY(()) rtx mips_tls_symbol;
2217 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2219 rtx insn, loc, tga, a0;
2221 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2223 if (!mips_tls_symbol)
2224 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2226 loc = mips_unspec_address (sym, type);
2230 emit_insn (gen_rtx_SET (Pmode, a0,
2231 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2232 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2233 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2234 CONST_OR_PURE_CALL_P (insn) = 1;
2235 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2236 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2237 insn = get_insns ();
2244 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2245 return value will be a valid address and move_operand (either a REG
2249 mips_legitimize_tls_address (rtx loc)
2251 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2252 enum tls_model model;
2254 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2255 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2257 model = SYMBOL_REF_TLS_MODEL (loc);
2258 /* Only TARGET_ABICALLS code can have more than one module; other
2259 code must be be static and should not use a GOT. All TLS models
2260 reduce to local exec in this situation. */
2261 if (!TARGET_ABICALLS)
2262 model = TLS_MODEL_LOCAL_EXEC;
2266 case TLS_MODEL_GLOBAL_DYNAMIC:
2267 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2268 dest = gen_reg_rtx (Pmode);
2269 emit_libcall_block (insn, dest, v0, loc);
2272 case TLS_MODEL_LOCAL_DYNAMIC:
2273 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2274 tmp1 = gen_reg_rtx (Pmode);
2276 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2277 share the LDM result with other LD model accesses. */
2278 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2280 emit_libcall_block (insn, tmp1, v0, eqv);
2282 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2283 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2284 mips_unspec_address (loc, SYMBOL_DTPREL));
2287 case TLS_MODEL_INITIAL_EXEC:
2288 tmp1 = gen_reg_rtx (Pmode);
2289 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2290 if (Pmode == DImode)
2292 emit_insn (gen_tls_get_tp_di (v1));
2293 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2297 emit_insn (gen_tls_get_tp_si (v1));
2298 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2300 dest = gen_reg_rtx (Pmode);
2301 emit_insn (gen_add3_insn (dest, tmp1, v1));
2304 case TLS_MODEL_LOCAL_EXEC:
2305 if (Pmode == DImode)
2306 emit_insn (gen_tls_get_tp_di (v1));
2308 emit_insn (gen_tls_get_tp_si (v1));
2310 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2311 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2312 mips_unspec_address (loc, SYMBOL_TPREL));
2322 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2323 be legitimized in a way that the generic machinery might not expect,
2324 put the new address in *XLOC and return true. MODE is the mode of
2325 the memory being accessed. */
2328 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2330 enum mips_symbol_type symbol_type;
2332 if (mips_tls_operand_p (*xloc))
2334 *xloc = mips_legitimize_tls_address (*xloc);
2338 /* See if the address can split into a high part and a LO_SUM. */
2339 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2340 && mips_symbolic_address_p (symbol_type, mode)
2341 && mips_split_p[symbol_type])
2343 *xloc = mips_split_symbol (0, *xloc);
2347 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2349 /* Handle REG + CONSTANT using mips_add_offset. */
2352 reg = XEXP (*xloc, 0);
2353 if (!mips_valid_base_register_p (reg, mode, 0))
2354 reg = copy_to_mode_reg (Pmode, reg);
2355 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2363 /* Subroutine of mips_build_integer (with the same interface).
2364 Assume that the final action in the sequence should be a left shift. */
2367 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2369 unsigned int i, shift;
2371 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2372 since signed numbers are easier to load than unsigned ones. */
2374 while ((value & 1) == 0)
2375 value /= 2, shift++;
2377 i = mips_build_integer (codes, value);
2378 codes[i].code = ASHIFT;
2379 codes[i].value = shift;
2384 /* As for mips_build_shift, but assume that the final action will be
2385 an IOR or PLUS operation. */
2388 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2390 unsigned HOST_WIDE_INT high;
2393 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2394 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2396 /* The constant is too complex to load with a simple lui/ori pair
2397 so our goal is to clear as many trailing zeros as possible.
2398 In this case, we know bit 16 is set and that the low 16 bits
2399 form a negative number. If we subtract that number from VALUE,
2400 we will clear at least the lowest 17 bits, maybe more. */
2401 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2402 codes[i].code = PLUS;
2403 codes[i].value = CONST_LOW_PART (value);
2407 i = mips_build_integer (codes, high);
2408 codes[i].code = IOR;
2409 codes[i].value = value & 0xffff;
2415 /* Fill CODES with a sequence of rtl operations to load VALUE.
2416 Return the number of operations needed. */
2419 mips_build_integer (struct mips_integer_op *codes,
2420 unsigned HOST_WIDE_INT value)
2422 if (SMALL_OPERAND (value)
2423 || SMALL_OPERAND_UNSIGNED (value)
2424 || LUI_OPERAND (value))
2426 /* The value can be loaded with a single instruction. */
2427 codes[0].code = UNKNOWN;
2428 codes[0].value = value;
2431 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2433 /* Either the constant is a simple LUI/ORI combination or its
2434 lowest bit is set. We don't want to shift in this case. */
2435 return mips_build_lower (codes, value);
2437 else if ((value & 0xffff) == 0)
2439 /* The constant will need at least three actions. The lowest
2440 16 bits are clear, so the final action will be a shift. */
2441 return mips_build_shift (codes, value);
2445 /* The final action could be a shift, add or inclusive OR.
2446 Rather than use a complex condition to select the best
2447 approach, try both mips_build_shift and mips_build_lower
2448 and pick the one that gives the shortest sequence.
2449 Note that this case is only used once per constant. */
2450 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2451 unsigned int cost, alt_cost;
2453 cost = mips_build_shift (codes, value);
2454 alt_cost = mips_build_lower (alt_codes, value);
2455 if (alt_cost < cost)
2457 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2465 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2468 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2470 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2471 enum machine_mode mode;
2472 unsigned int i, cost;
2475 mode = GET_MODE (dest);
2476 cost = mips_build_integer (codes, value);
2478 /* Apply each binary operation to X. Invariant: X is a legitimate
2479 source operand for a SET pattern. */
2480 x = GEN_INT (codes[0].value);
2481 for (i = 1; i < cost; i++)
2483 if (!can_create_pseudo_p ())
2485 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2489 x = force_reg (mode, x);
2490 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2493 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2497 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2498 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2502 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2506 /* Split moves of big integers into smaller pieces. */
2507 if (splittable_const_int_operand (src, mode))
2509 mips_move_integer (dest, dest, INTVAL (src));
2513 /* Split moves of symbolic constants into high/low pairs. */
2514 if (splittable_symbolic_operand (src, mode))
2516 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2520 if (mips_tls_operand_p (src))
2522 emit_move_insn (dest, mips_legitimize_tls_address (src));
2526 /* If we have (const (plus symbol offset)), load the symbol first
2527 and then add in the offset. This is usually better than forcing
2528 the constant into memory, at least in non-mips16 code. */
2529 split_const (src, &base, &offset);
2531 && offset != const0_rtx
2532 && (can_create_pseudo_p () || SMALL_INT (offset)))
2534 base = mips_force_temporary (dest, base);
2535 emit_move_insn (dest, mips_add_offset (0, base, INTVAL (offset)));
2539 src = force_const_mem (mode, src);
2541 /* When using explicit relocs, constant pool references are sometimes
2542 not legitimate addresses. */
2543 if (!memory_operand (src, VOIDmode))
2544 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2545 emit_move_insn (dest, src);
2549 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2550 sequence that is valid. */
2553 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2555 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2557 emit_move_insn (dest, force_reg (mode, src));
2561 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2562 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2563 && REG_P (src) && MD_REG_P (REGNO (src))
2564 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2566 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2567 if (GET_MODE_SIZE (mode) <= 4)
2568 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2569 gen_rtx_REG (SImode, REGNO (src)),
2570 gen_rtx_REG (SImode, other_regno)));
2572 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2573 gen_rtx_REG (DImode, REGNO (src)),
2574 gen_rtx_REG (DImode, other_regno)));
2578 /* We need to deal with constants that would be legitimate
2579 immediate_operands but not legitimate move_operands. */
2580 if (CONSTANT_P (src) && !move_operand (src, mode))
2582 mips_legitimize_const_move (mode, dest, src);
2583 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2589 /* We need a lot of little routines to check constant values on the
2590 mips16. These are used to figure out how long the instruction will
2591 be. It would be much better to do this using constraints, but
2592 there aren't nearly enough letters available. */
2595 m16_check_op (rtx op, int low, int high, int mask)
2597 return (GET_CODE (op) == CONST_INT
2598 && INTVAL (op) >= low
2599 && INTVAL (op) <= high
2600 && (INTVAL (op) & mask) == 0);
2604 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2606 return m16_check_op (op, 0x1, 0x8, 0);
2610 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2612 return m16_check_op (op, - 0x8, 0x7, 0);
2616 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2618 return m16_check_op (op, - 0x7, 0x8, 0);
2622 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2624 return m16_check_op (op, - 0x10, 0xf, 0);
2628 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2630 return m16_check_op (op, - 0xf, 0x10, 0);
2634 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2636 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2640 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2642 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2646 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2648 return m16_check_op (op, - 0x80, 0x7f, 0);
2652 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2654 return m16_check_op (op, - 0x7f, 0x80, 0);
2658 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2660 return m16_check_op (op, 0x0, 0xff, 0);
2664 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2666 return m16_check_op (op, - 0xff, 0x0, 0);
2670 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2672 return m16_check_op (op, - 0x1, 0xfe, 0);
2676 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2678 return m16_check_op (op, 0x0, 0xff << 2, 3);
2682 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2684 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2688 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2690 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2694 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2696 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2699 /* Return true if ADDR matches the pattern for the lwxs load scaled indexed
2700 address instruction. */
2703 mips_lwxs_address_p (rtx addr)
2706 && GET_CODE (addr) == PLUS
2707 && REG_P (XEXP (addr, 1)))
2709 rtx offset = XEXP (addr, 0);
2710 if (GET_CODE (offset) == MULT
2711 && REG_P (XEXP (offset, 0))
2712 && GET_CODE (XEXP (offset, 1)) == CONST_INT
2713 && INTVAL (XEXP (offset, 1)) == 4)
2720 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2722 enum machine_mode mode = GET_MODE (x);
2723 bool float_mode_p = FLOAT_MODE_P (mode);
2730 /* A number between 1 and 8 inclusive is efficient for a shift.
2731 Otherwise, we will need an extended instruction. */
2732 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2733 || (outer_code) == LSHIFTRT)
2735 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2738 *total = COSTS_N_INSNS (1);
2742 /* We can use cmpi for an xor with an unsigned 16-bit value. */
2743 if ((outer_code) == XOR
2744 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2750 /* We may be able to use slt or sltu for a comparison with a
2751 signed 16-bit value. (The boundary conditions aren't quite
2752 right, but this is just a heuristic anyhow.) */
2753 if (((outer_code) == LT || (outer_code) == LE
2754 || (outer_code) == GE || (outer_code) == GT
2755 || (outer_code) == LTU || (outer_code) == LEU
2756 || (outer_code) == GEU || (outer_code) == GTU)
2757 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2763 /* Equality comparisons with 0 are cheap. */
2764 if (((outer_code) == EQ || (outer_code) == NE)
2771 /* Constants in the range 0...255 can be loaded with an unextended
2772 instruction. They are therefore as cheap as a register move.
2774 Given the choice between "li R1,0...255" and "move R1,R2"
2775 (where R2 is a known constant), it is usually better to use "li",
2776 since we do not want to unnecessarily extend the lifetime
2778 if (outer_code == SET
2780 && INTVAL (x) < 256)
2788 /* These can be used anywhere. */
2793 /* Otherwise fall through to the handling below because
2794 we'll need to construct the constant. */
2800 if (LEGITIMATE_CONSTANT_P (x))
2802 *total = COSTS_N_INSNS (1);
2807 /* The value will need to be fetched from the constant pool. */
2808 *total = CONSTANT_POOL_COST;
2814 /* If the address is legitimate, return the number of
2815 instructions it needs. */
2816 rtx addr = XEXP (x, 0);
2817 int n = mips_address_insns (addr, GET_MODE (x));
2820 *total = COSTS_N_INSNS (n + 1);
2823 /* Check for scaled indexed address. */
2824 if (mips_lwxs_address_p (addr))
2826 *total = COSTS_N_INSNS (2);
2829 /* Otherwise use the default handling. */
2834 *total = COSTS_N_INSNS (6);
2838 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2844 if (mode == DImode && !TARGET_64BIT)
2846 *total = COSTS_N_INSNS (2);
2854 if (mode == DImode && !TARGET_64BIT)
2856 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2864 *total = COSTS_N_INSNS (1);
2866 *total = COSTS_N_INSNS (4);
2870 *total = COSTS_N_INSNS (1);
2877 *total = mips_cost->fp_add;
2881 else if (mode == DImode && !TARGET_64BIT)
2883 *total = COSTS_N_INSNS (4);
2889 if (mode == DImode && !TARGET_64BIT)
2891 *total = COSTS_N_INSNS (4);
2898 *total = mips_cost->fp_mult_sf;
2900 else if (mode == DFmode)
2901 *total = mips_cost->fp_mult_df;
2903 else if (mode == SImode)
2904 *total = mips_cost->int_mult_si;
2907 *total = mips_cost->int_mult_di;
2916 *total = mips_cost->fp_div_sf;
2918 *total = mips_cost->fp_div_df;
2927 *total = mips_cost->int_div_di;
2929 *total = mips_cost->int_div_si;
2934 /* A sign extend from SImode to DImode in 64-bit mode is often
2935 zero instructions, because the result can often be used
2936 directly by another instruction; we'll call it one. */
2937 if (TARGET_64BIT && mode == DImode
2938 && GET_MODE (XEXP (x, 0)) == SImode)
2939 *total = COSTS_N_INSNS (1);
2941 *total = COSTS_N_INSNS (2);
2945 if (TARGET_64BIT && mode == DImode
2946 && GET_MODE (XEXP (x, 0)) == SImode)
2947 *total = COSTS_N_INSNS (2);
2949 *total = COSTS_N_INSNS (1);
2953 case UNSIGNED_FLOAT:
2956 case FLOAT_TRUNCATE:
2958 *total = mips_cost->fp_add;
2966 /* Provide the costs of an addressing mode that contains ADDR.
2967 If ADDR is not a valid address, its cost is irrelevant. */
2970 mips_address_cost (rtx addr)
2972 return mips_address_insns (addr, SImode);
2975 /* Return one word of double-word value OP, taking into account the fixed
2976 endianness of certain registers. HIGH_P is true to select the high part,
2977 false to select the low part. */
2980 mips_subword (rtx op, int high_p)
2983 enum machine_mode mode;
2985 mode = GET_MODE (op);
2986 if (mode == VOIDmode)
2989 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2990 byte = UNITS_PER_WORD;
2996 if (FP_REG_P (REGNO (op)))
2997 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2998 if (ACC_HI_REG_P (REGNO (op)))
2999 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
3003 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3005 return simplify_gen_subreg (word_mode, op, mode, byte);
3009 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3012 mips_split_64bit_move_p (rtx dest, rtx src)
3017 /* FP->FP moves can be done in a single instruction. */
3018 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3021 /* Check for floating-point loads and stores. They can be done using
3022 ldc1 and sdc1 on MIPS II and above. */
3025 if (FP_REG_RTX_P (dest) && MEM_P (src))
3027 if (FP_REG_RTX_P (src) && MEM_P (dest))
3034 /* Split a 64-bit move from SRC to DEST assuming that
3035 mips_split_64bit_move_p holds.
3037 Moves into and out of FPRs cause some difficulty here. Such moves
3038 will always be DFmode, since paired FPRs are not allowed to store
3039 DImode values. The most natural representation would be two separate
3040 32-bit moves, such as:
3042 (set (reg:SI $f0) (mem:SI ...))
3043 (set (reg:SI $f1) (mem:SI ...))
3045 However, the second insn is invalid because odd-numbered FPRs are
3046 not allowed to store independent values. Use the patterns load_df_low,
3047 load_df_high and store_df_high instead. */
3050 mips_split_64bit_move (rtx dest, rtx src)
3052 if (FP_REG_RTX_P (dest))
3054 /* Loading an FPR from memory or from GPRs. */
3057 dest = gen_lowpart (DFmode, dest);
3058 emit_insn (gen_load_df_low (dest, mips_subword (src, 0)));
3059 emit_insn (gen_mthc1 (dest, mips_subword (src, 1),
3064 emit_insn (gen_load_df_low (copy_rtx (dest),
3065 mips_subword (src, 0)));
3066 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
3070 else if (FP_REG_RTX_P (src))
3072 /* Storing an FPR into memory or GPRs. */
3075 src = gen_lowpart (DFmode, src);
3076 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3077 emit_insn (gen_mfhc1 (mips_subword (dest, 1), src));
3081 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
3082 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
3087 /* The operation can be split into two normal moves. Decide in
3088 which order to do them. */
3091 low_dest = mips_subword (dest, 0);
3092 if (REG_P (low_dest)
3093 && reg_overlap_mentioned_p (low_dest, src))
3095 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3096 emit_move_insn (low_dest, mips_subword (src, 0));
3100 emit_move_insn (low_dest, mips_subword (src, 0));
3101 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
3106 /* Return the appropriate instructions to move SRC into DEST. Assume
3107 that SRC is operand 1 and DEST is operand 0. */
3110 mips_output_move (rtx dest, rtx src)
3112 enum rtx_code dest_code, src_code;
3115 dest_code = GET_CODE (dest);
3116 src_code = GET_CODE (src);
3117 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
3119 if (dbl_p && mips_split_64bit_move_p (dest, src))
3122 if ((src_code == REG && GP_REG_P (REGNO (src)))
3123 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
3125 if (dest_code == REG)
3127 if (GP_REG_P (REGNO (dest)))
3128 return "move\t%0,%z1";
3130 if (MD_REG_P (REGNO (dest)))
3133 if (DSP_ACC_REG_P (REGNO (dest)))
3135 static char retval[] = "mt__\t%z1,%q0";
3136 retval[2] = reg_names[REGNO (dest)][4];
3137 retval[3] = reg_names[REGNO (dest)][5];
3141 if (FP_REG_P (REGNO (dest)))
3142 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
3144 if (ALL_COP_REG_P (REGNO (dest)))
3146 static char retval[] = "dmtc_\t%z1,%0";
3148 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3149 return (dbl_p ? retval : retval + 1);
3152 if (dest_code == MEM)
3153 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
3155 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3157 if (src_code == REG)
3159 if (DSP_ACC_REG_P (REGNO (src)))
3161 static char retval[] = "mf__\t%0,%q1";
3162 retval[2] = reg_names[REGNO (src)][4];
3163 retval[3] = reg_names[REGNO (src)][5];
3167 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3168 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3170 if (FP_REG_P (REGNO (src)))
3171 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
3173 if (ALL_COP_REG_P (REGNO (src)))
3175 static char retval[] = "dmfc_\t%0,%1";
3177 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3178 return (dbl_p ? retval : retval + 1);
3182 if (src_code == MEM)
3183 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
3185 if (src_code == CONST_INT)
3187 /* Don't use the X format, because that will give out of
3188 range numbers for 64-bit hosts and 32-bit targets. */
3190 return "li\t%0,%1\t\t\t# %X1";
3192 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
3195 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
3199 if (src_code == HIGH)
3200 return "lui\t%0,%h1";
3202 if (CONST_GP_P (src))
3203 return "move\t%0,%1";
3205 if (symbolic_operand (src, VOIDmode))
3206 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
3208 if (src_code == REG && FP_REG_P (REGNO (src)))
3210 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3212 if (GET_MODE (dest) == V2SFmode)
3213 return "mov.ps\t%0,%1";
3215 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
3218 if (dest_code == MEM)
3219 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
3221 if (dest_code == REG && FP_REG_P (REGNO (dest)))
3223 if (src_code == MEM)
3224 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
3226 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
3228 static char retval[] = "l_c_\t%0,%1";
3230 retval[1] = (dbl_p ? 'd' : 'w');
3231 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3234 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
3236 static char retval[] = "s_c_\t%1,%0";
3238 retval[1] = (dbl_p ? 'd' : 'w');
3239 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3245 /* Restore $gp from its save slot. Valid only when using o32 or
3249 mips_restore_gp (void)
3253 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3255 address = mips_add_offset (pic_offset_table_rtx,
3256 frame_pointer_needed
3257 ? hard_frame_pointer_rtx
3258 : stack_pointer_rtx,
3259 current_function_outgoing_args_size);
3260 slot = gen_rtx_MEM (Pmode, address);
3262 emit_move_insn (pic_offset_table_rtx, slot);
3263 if (!TARGET_EXPLICIT_RELOCS)
3264 emit_insn (gen_blockage ());
3267 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3270 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3272 emit_insn (gen_rtx_SET (VOIDmode, target,
3273 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3276 /* Return true if CMP1 is a suitable second operand for relational
3277 operator CODE. See also the *sCC patterns in mips.md. */
3280 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3286 return reg_or_0_operand (cmp1, VOIDmode);
3290 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3294 return arith_operand (cmp1, VOIDmode);
3297 return sle_operand (cmp1, VOIDmode);
3300 return sleu_operand (cmp1, VOIDmode);
3307 /* Canonicalize LE or LEU comparisons into LT comparisons when
3308 possible to avoid extra instructions or inverting the
3312 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3313 enum machine_mode mode)
3315 HOST_WIDE_INT original, plus_one;
3317 if (GET_CODE (*cmp1) != CONST_INT)
3320 original = INTVAL (*cmp1);
3321 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3326 if (original < plus_one)
3329 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3338 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3351 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3352 result in TARGET. CMP0 and TARGET are register_operands that have
3353 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3354 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3357 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3358 rtx target, rtx cmp0, rtx cmp1)
3360 /* First see if there is a MIPS instruction that can do this operation
3361 with CMP1 in its current form. If not, try to canonicalize the
3362 comparison to LT. If that fails, try doing the same for the
3363 inverse operation. If that also fails, force CMP1 into a register
3365 if (mips_relational_operand_ok_p (code, cmp1))
3366 mips_emit_binary (code, target, cmp0, cmp1);
3367 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3368 mips_emit_binary (code, target, cmp0, cmp1);
3371 enum rtx_code inv_code = reverse_condition (code);
3372 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3374 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3375 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3377 else if (invert_ptr == 0)
3379 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3380 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3381 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3385 *invert_ptr = !*invert_ptr;
3386 mips_emit_binary (inv_code, target, cmp0, cmp1);
3391 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3392 The register will have the same mode as CMP0. */
3395 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3397 if (cmp1 == const0_rtx)
3400 if (uns_arith_operand (cmp1, VOIDmode))
3401 return expand_binop (GET_MODE (cmp0), xor_optab,
3402 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3404 return expand_binop (GET_MODE (cmp0), sub_optab,
3405 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3408 /* Convert *CODE into a code that can be used in a floating-point
3409 scc instruction (c.<cond>.<fmt>). Return true if the values of
3410 the condition code registers will be inverted, with 0 indicating
3411 that the condition holds. */
3414 mips_reverse_fp_cond_p (enum rtx_code *code)
3421 *code = reverse_condition_maybe_unordered (*code);
3429 /* Convert a comparison into something that can be used in a branch or
3430 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3431 being compared and *CODE is the code used to compare them.
3433 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3434 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3435 otherwise any standard branch condition can be used. The standard branch
3438 - EQ/NE between two registers.
3439 - any comparison between a register and zero. */
3442 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3444 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3446 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3448 *op0 = cmp_operands[0];
3449 *op1 = cmp_operands[1];
3451 else if (*code == EQ || *code == NE)
3455 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3460 *op0 = cmp_operands[0];
3461 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3466 /* The comparison needs a separate scc instruction. Store the
3467 result of the scc in *OP0 and compare it against zero. */
3468 bool invert = false;
3469 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3471 mips_emit_int_relational (*code, &invert, *op0,
3472 cmp_operands[0], cmp_operands[1]);
3473 *code = (invert ? EQ : NE);
3478 enum rtx_code cmp_code;
3480 /* Floating-point tests use a separate c.cond.fmt comparison to
3481 set a condition code register. The branch or conditional move
3482 will then compare that register against zero.
3484 Set CMP_CODE to the code of the comparison instruction and
3485 *CODE to the code that the branch or move should use. */
3487 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3489 ? gen_reg_rtx (CCmode)
3490 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3492 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3496 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3497 Store the result in TARGET and return true if successful.
3499 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3502 mips_emit_scc (enum rtx_code code, rtx target)
3504 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3507 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3508 if (code == EQ || code == NE)
3510 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3511 mips_emit_binary (code, target, zie, const0_rtx);
3514 mips_emit_int_relational (code, 0, target,
3515 cmp_operands[0], cmp_operands[1]);
3519 /* Emit the common code for doing conditional branches.
3520 operand[0] is the label to jump to.
3521 The comparison operands are saved away by cmp{si,di,sf,df}. */
3524 gen_conditional_branch (rtx *operands, enum rtx_code code)
3526 rtx op0, op1, condition;
3528 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3529 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3530 emit_jump_insn (gen_condjump (condition, operands[0]));
3535 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3536 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3539 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3540 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3545 reversed_p = mips_reverse_fp_cond_p (&cond);
3546 cmp_result = gen_reg_rtx (CCV2mode);
3547 emit_insn (gen_scc_ps (cmp_result,
3548 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3550 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3553 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3557 /* Emit the common code for conditional moves. OPERANDS is the array
3558 of operands passed to the conditional move define_expand. */
3561 gen_conditional_move (rtx *operands)
3566 code = GET_CODE (operands[1]);
3567 mips_emit_compare (&code, &op0, &op1, true);
3568 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3569 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3570 gen_rtx_fmt_ee (code,
3573 operands[2], operands[3])));
3576 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3577 the conditional_trap expander. */
3580 mips_gen_conditional_trap (rtx *operands)
3583 enum rtx_code cmp_code = GET_CODE (operands[0]);
3584 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3586 /* MIPS conditional trap machine instructions don't have GT or LE
3587 flavors, so we must invert the comparison and convert to LT and
3588 GE, respectively. */
3591 case GT: cmp_code = LT; break;
3592 case LE: cmp_code = GE; break;
3593 case GTU: cmp_code = LTU; break;
3594 case LEU: cmp_code = GEU; break;
3597 if (cmp_code == GET_CODE (operands[0]))
3599 op0 = cmp_operands[0];
3600 op1 = cmp_operands[1];
3604 op0 = cmp_operands[1];
3605 op1 = cmp_operands[0];
3607 op0 = force_reg (mode, op0);
3608 if (!arith_operand (op1, mode))
3609 op1 = force_reg (mode, op1);
3611 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3612 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3616 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
3619 mips_ok_for_lazy_binding_p (rtx x)
3621 return (TARGET_USE_GOT
3622 && GET_CODE (x) == SYMBOL_REF
3623 && !mips_symbol_binds_local_p (x));
3626 /* Load function address ADDR into register DEST. SIBCALL_P is true
3627 if the address is needed for a sibling call. */
3630 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3632 /* If we're generating PIC, and this call is to a global function,
3633 try to allow its address to be resolved lazily. This isn't
3634 possible if TARGET_CALL_SAVED_GP since the value of $gp on entry
3635 to the stub would be our caller's gp, not ours. */
3636 if (TARGET_EXPLICIT_RELOCS
3637 && !(sibcall_p && TARGET_CALL_SAVED_GP)
3638 && mips_ok_for_lazy_binding_p (addr))
3640 rtx high, lo_sum_symbol;
3642 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3643 addr, SYMBOL_GOTOFF_CALL);
3644 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3645 if (Pmode == SImode)
3646 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3648 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3651 emit_move_insn (dest, addr);
3655 /* Expand a call or call_value instruction. RESULT is where the
3656 result will go (null for calls), ADDR is the address of the
3657 function, ARGS_SIZE is the size of the arguments and AUX is
3658 the value passed to us by mips_function_arg. SIBCALL_P is true
3659 if we are expanding a sibling call, false if we're expanding
3663 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3665 rtx orig_addr, pattern, insn;
3668 if (!call_insn_operand (addr, VOIDmode))
3670 addr = gen_reg_rtx (Pmode);
3671 mips_load_call_address (addr, orig_addr, sibcall_p);
3674 if (mips16_hard_float
3675 && build_mips16_call_stub (result, addr, args_size,
3676 aux == 0 ? 0 : (int) GET_MODE (aux)))
3680 pattern = (sibcall_p
3681 ? gen_sibcall_internal (addr, args_size)
3682 : gen_call_internal (addr, args_size));
3683 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3687 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3688 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3691 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3692 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3695 pattern = (sibcall_p
3696 ? gen_sibcall_value_internal (result, addr, args_size)
3697 : gen_call_value_internal (result, addr, args_size));
3699 insn = emit_call_insn (pattern);
3701 /* Lazy-binding stubs require $gp to be valid on entry. */
3702 if (mips_ok_for_lazy_binding_p (orig_addr))
3703 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3707 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3710 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3711 tree exp ATTRIBUTE_UNUSED)
3713 return TARGET_SIBCALLS;
3716 /* Emit code to move general operand SRC into condition-code
3717 register DEST. SCRATCH is a scratch TFmode float register.
3724 where FP1 and FP2 are single-precision float registers
3725 taken from SCRATCH. */
3728 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3732 /* Change the source to SFmode. */
3734 src = adjust_address (src, SFmode, 0);
3735 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3736 src = gen_rtx_REG (SFmode, true_regnum (src));
3738 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3739 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
3741 emit_move_insn (copy_rtx (fp1), src);
3742 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3743 emit_insn (gen_slt_sf (dest, fp2, fp1));
3746 /* Emit code to change the current function's return address to
3747 ADDRESS. SCRATCH is available as a scratch register, if needed.
3748 ADDRESS and SCRATCH are both word-mode GPRs. */
3751 mips_set_return_address (rtx address, rtx scratch)
3755 compute_frame_size (get_frame_size ());
3756 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3757 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3758 cfun->machine->frame.gp_sp_offset);
3760 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3763 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3764 Assume that the areas do not overlap. */
3767 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3769 HOST_WIDE_INT offset, delta;
3770 unsigned HOST_WIDE_INT bits;
3772 enum machine_mode mode;
3775 /* Work out how many bits to move at a time. If both operands have
3776 half-word alignment, it is usually better to move in half words.
3777 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3778 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3779 Otherwise move word-sized chunks. */
3780 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3781 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3782 bits = BITS_PER_WORD / 2;
3784 bits = BITS_PER_WORD;
3786 mode = mode_for_size (bits, MODE_INT, 0);
3787 delta = bits / BITS_PER_UNIT;
3789 /* Allocate a buffer for the temporary registers. */
3790 regs = alloca (sizeof (rtx) * length / delta);
3792 /* Load as many BITS-sized chunks as possible. Use a normal load if
3793 the source has enough alignment, otherwise use left/right pairs. */
3794 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3796 regs[i] = gen_reg_rtx (mode);
3797 if (MEM_ALIGN (src) >= bits)
3798 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3801 rtx part = adjust_address (src, BLKmode, offset);
3802 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3807 /* Copy the chunks to the destination. */
3808 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3809 if (MEM_ALIGN (dest) >= bits)
3810 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3813 rtx part = adjust_address (dest, BLKmode, offset);
3814 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3818 /* Mop up any left-over bytes. */
3819 if (offset < length)
3821 src = adjust_address (src, BLKmode, offset);
3822 dest = adjust_address (dest, BLKmode, offset);
3823 move_by_pieces (dest, src, length - offset,
3824 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3828 #define MAX_MOVE_REGS 4
3829 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3832 /* Helper function for doing a loop-based block operation on memory
3833 reference MEM. Each iteration of the loop will operate on LENGTH
3836 Create a new base register for use within the loop and point it to
3837 the start of MEM. Create a new memory reference that uses this
3838 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3841 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3842 rtx *loop_reg, rtx *loop_mem)
3844 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3846 /* Although the new mem does not refer to a known location,
3847 it does keep up to LENGTH bytes of alignment. */
3848 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3849 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3853 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3854 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3855 memory regions do not overlap. */
3858 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3860 rtx label, src_reg, dest_reg, final_src;
3861 HOST_WIDE_INT leftover;
3863 leftover = length % MAX_MOVE_BYTES;
3866 /* Create registers and memory references for use within the loop. */
3867 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3868 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3870 /* Calculate the value that SRC_REG should have after the last iteration
3872 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3875 /* Emit the start of the loop. */
3876 label = gen_label_rtx ();
3879 /* Emit the loop body. */
3880 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3882 /* Move on to the next block. */
3883 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3884 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3886 /* Emit the loop condition. */
3887 if (Pmode == DImode)
3888 emit_insn (gen_cmpdi (src_reg, final_src));
3890 emit_insn (gen_cmpsi (src_reg, final_src));
3891 emit_jump_insn (gen_bne (label));
3893 /* Mop up any left-over bytes. */
3895 mips_block_move_straight (dest, src, leftover);
3899 /* Expand a loop of synci insns for the address range [BEGIN, END). */
3902 mips_expand_synci_loop (rtx begin, rtx end)
3904 rtx inc, label, cmp, cmp_result;
3906 /* Load INC with the cache line size (rdhwr INC,$1). */
3907 inc = gen_reg_rtx (SImode);
3908 emit_insn (gen_rdhwr (inc, const1_rtx));
3910 /* Loop back to here. */
3911 label = gen_label_rtx ();
3914 emit_insn (gen_synci (begin));
3916 cmp = gen_reg_rtx (Pmode);
3917 mips_emit_binary (GTU, cmp, begin, end);
3919 mips_emit_binary (PLUS, begin, begin, inc);
3921 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
3922 emit_jump_insn (gen_condjump (cmp_result, label));
3925 /* Expand a movmemsi instruction. */
3928 mips_expand_block_move (rtx dest, rtx src, rtx length)
3930 if (GET_CODE (length) == CONST_INT)
3932 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3934 mips_block_move_straight (dest, src, INTVAL (length));
3939 mips_block_move_loop (dest, src, INTVAL (length));
3946 /* Argument support functions. */
3948 /* Initialize CUMULATIVE_ARGS for a function. */
3951 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3952 rtx libname ATTRIBUTE_UNUSED)
3954 static CUMULATIVE_ARGS zero_cum;
3955 tree param, next_param;
3958 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3960 /* Determine if this function has variable arguments. This is
3961 indicated by the last argument being 'void_type_mode' if there
3962 are no variable arguments. The standard MIPS calling sequence
3963 passes all arguments in the general purpose registers in this case. */
3965 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3966 param != 0; param = next_param)
3968 next_param = TREE_CHAIN (param);
3969 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3970 cum->gp_reg_found = 1;
3975 /* Fill INFO with information about a single argument. CUM is the
3976 cumulative state for earlier arguments. MODE is the mode of this
3977 argument and TYPE is its type (if known). NAMED is true if this
3978 is a named (fixed) argument rather than a variable one. */
3981 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3982 tree type, int named, struct mips_arg_info *info)
3984 bool doubleword_aligned_p;
3985 unsigned int num_bytes, num_words, max_regs;
3987 /* Work out the size of the argument. */
3988 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3989 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3991 /* Decide whether it should go in a floating-point register, assuming
3992 one is free. Later code checks for availability.
3994 The checks against UNITS_PER_FPVALUE handle the soft-float and
3995 single-float cases. */
3999 /* The EABI conventions have traditionally been defined in terms
4000 of TYPE_MODE, regardless of the actual type. */
4001 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4002 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4003 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4008 /* Only leading floating-point scalars are passed in
4009 floating-point registers. We also handle vector floats the same
4010 say, which is OK because they are not covered by the standard ABI. */
4011 info->fpr_p = (!cum->gp_reg_found
4012 && cum->arg_number < 2
4013 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
4014 || VECTOR_FLOAT_TYPE_P (type))
4015 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4016 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4017 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4022 /* Scalar and complex floating-point types are passed in
4023 floating-point registers. */
4024 info->fpr_p = (named
4025 && (type == 0 || FLOAT_TYPE_P (type))
4026 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4027 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4028 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4029 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4031 /* ??? According to the ABI documentation, the real and imaginary
4032 parts of complex floats should be passed in individual registers.
4033 The real and imaginary parts of stack arguments are supposed
4034 to be contiguous and there should be an extra word of padding
4037 This has two problems. First, it makes it impossible to use a
4038 single "void *" va_list type, since register and stack arguments
4039 are passed differently. (At the time of writing, MIPSpro cannot
4040 handle complex float varargs correctly.) Second, it's unclear
4041 what should happen when there is only one register free.
4043 For now, we assume that named complex floats should go into FPRs
4044 if there are two FPRs free, otherwise they should be passed in the
4045 same way as a struct containing two floats. */
4047 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4048 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4050 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4051 info->fpr_p = false;
4061 /* See whether the argument has doubleword alignment. */
4062 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4064 /* Set REG_OFFSET to the register count we're interested in.
4065 The EABI allocates the floating-point registers separately,
4066 but the other ABIs allocate them like integer registers. */
4067 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4071 /* Advance to an even register if the argument is doubleword-aligned. */
4072 if (doubleword_aligned_p)
4073 info->reg_offset += info->reg_offset & 1;
4075 /* Work out the offset of a stack argument. */
4076 info->stack_offset = cum->stack_words;
4077 if (doubleword_aligned_p)
4078 info->stack_offset += info->stack_offset & 1;
4080 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4082 /* Partition the argument between registers and stack. */
4083 info->reg_words = MIN (num_words, max_regs);
4084 info->stack_words = num_words - info->reg_words;
4088 /* INFO describes an argument that is passed in a single-register value.
4089 Return the register it uses, assuming that FPRs are available if
4093 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4095 if (!info->fpr_p || !hard_float_p)
4096 return GP_ARG_FIRST + info->reg_offset;
4097 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4098 /* In o32, the second argument is always passed in $f14
4099 for TARGET_DOUBLE_FLOAT, regardless of whether the
4100 first argument was a word or doubleword. */
4101 return FP_ARG_FIRST + 2;
4103 return FP_ARG_FIRST + info->reg_offset;
4106 /* Implement FUNCTION_ARG_ADVANCE. */
4109 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4110 tree type, int named)
4112 struct mips_arg_info info;
4114 mips_arg_info (cum, mode, type, named, &info);
4117 cum->gp_reg_found = true;
4119 /* See the comment above the cumulative args structure in mips.h
4120 for an explanation of what this code does. It assumes the O32
4121 ABI, which passes at most 2 arguments in float registers. */
4122 if (cum->arg_number < 2 && info.fpr_p)
4123 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4125 if (mips_abi != ABI_EABI || !info.fpr_p)
4126 cum->num_gprs = info.reg_offset + info.reg_words;
4127 else if (info.reg_words > 0)
4128 cum->num_fprs += MAX_FPRS_PER_FMT;
4130 if (info.stack_words > 0)
4131 cum->stack_words = info.stack_offset + info.stack_words;
4136 /* Implement FUNCTION_ARG. */
4139 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4140 tree type, int named)
4142 struct mips_arg_info info;
4144 /* We will be called with a mode of VOIDmode after the last argument
4145 has been seen. Whatever we return will be passed to the call
4146 insn. If we need a mips16 fp_code, return a REG with the code
4147 stored as the mode. */
4148 if (mode == VOIDmode)
4150 if (TARGET_MIPS16 && cum->fp_code != 0)
4151 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4157 mips_arg_info (cum, mode, type, named, &info);
4159 /* Return straight away if the whole argument is passed on the stack. */
4160 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4164 && TREE_CODE (type) == RECORD_TYPE
4166 && TYPE_SIZE_UNIT (type)
4167 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4170 /* The Irix 6 n32/n64 ABIs say that if any 64-bit chunk of the
4171 structure contains a double in its entirety, then that 64-bit
4172 chunk is passed in a floating point register. */
4175 /* First check to see if there is any such field. */
4176 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4177 if (TREE_CODE (field) == FIELD_DECL
4178 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4179 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4180 && host_integerp (bit_position (field), 0)
4181 && int_bit_position (field) % BITS_PER_WORD == 0)
4186 /* Now handle the special case by returning a PARALLEL
4187 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4188 chunks are passed in registers. */
4190 HOST_WIDE_INT bitpos;
4193 /* assign_parms checks the mode of ENTRY_PARM, so we must
4194 use the actual mode here. */
4195 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4198 field = TYPE_FIELDS (type);
4199 for (i = 0; i < info.reg_words; i++)
4203 for (; field; field = TREE_CHAIN (field))
4204 if (TREE_CODE (field) == FIELD_DECL
4205 && int_bit_position (field) >= bitpos)
4209 && int_bit_position (field) == bitpos
4210 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4211 && !TARGET_SOFT_FLOAT
4212 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4213 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4215 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4218 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4219 GEN_INT (bitpos / BITS_PER_UNIT));
4221 bitpos += BITS_PER_WORD;
4227 /* Handle the n32/n64 conventions for passing complex floating-point
4228 arguments in FPR pairs. The real part goes in the lower register
4229 and the imaginary part goes in the upper register. */
4232 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4235 enum machine_mode inner;
4238 inner = GET_MODE_INNER (mode);
4239 reg = FP_ARG_FIRST + info.reg_offset;
4240 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4242 /* Real part in registers, imaginary part on stack. */
4243 gcc_assert (info.stack_words == info.reg_words);
4244 return gen_rtx_REG (inner, reg);
4248 gcc_assert (info.stack_words == 0);
4249 real = gen_rtx_EXPR_LIST (VOIDmode,
4250 gen_rtx_REG (inner, reg),
4252 imag = gen_rtx_EXPR_LIST (VOIDmode,
4254 reg + info.reg_words / 2),
4255 GEN_INT (GET_MODE_SIZE (inner)));
4256 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4260 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4264 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4267 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4268 enum machine_mode mode, tree type, bool named)
4270 struct mips_arg_info info;
4272 mips_arg_info (cum, mode, type, named, &info);
4273 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4277 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4278 PARM_BOUNDARY bits of alignment, but will be given anything up
4279 to STACK_BOUNDARY bits if the type requires it. */
4282 function_arg_boundary (enum machine_mode mode, tree type)
4284 unsigned int alignment;
4286 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4287 if (alignment < PARM_BOUNDARY)
4288 alignment = PARM_BOUNDARY;
4289 if (alignment > STACK_BOUNDARY)
4290 alignment = STACK_BOUNDARY;
4294 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4295 upward rather than downward. In other words, return true if the
4296 first byte of the stack slot has useful data, false if the last
4300 mips_pad_arg_upward (enum machine_mode mode, tree type)
4302 /* On little-endian targets, the first byte of every stack argument
4303 is passed in the first byte of the stack slot. */
4304 if (!BYTES_BIG_ENDIAN)
4307 /* Otherwise, integral types are padded downward: the last byte of a
4308 stack argument is passed in the last byte of the stack slot. */
4310 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4311 : GET_MODE_CLASS (mode) == MODE_INT)
4314 /* Big-endian o64 pads floating-point arguments downward. */
4315 if (mips_abi == ABI_O64)
4316 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4319 /* Other types are padded upward for o32, o64, n32 and n64. */
4320 if (mips_abi != ABI_EABI)
4323 /* Arguments smaller than a stack slot are padded downward. */
4324 if (mode != BLKmode)
4325 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4327 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4331 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4332 if the least significant byte of the register has useful data. Return
4333 the opposite if the most significant byte does. */
4336 mips_pad_reg_upward (enum machine_mode mode, tree type)
4338 /* No shifting is required for floating-point arguments. */
4339 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4340 return !BYTES_BIG_ENDIAN;
4342 /* Otherwise, apply the same padding to register arguments as we do
4343 to stack arguments. */
4344 return mips_pad_arg_upward (mode, type);
4348 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4349 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4352 CUMULATIVE_ARGS local_cum;
4353 int gp_saved, fp_saved;
4355 /* The caller has advanced CUM up to, but not beyond, the last named
4356 argument. Advance a local copy of CUM past the last "real" named
4357 argument, to find out how many registers are left over. */
4360 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4362 /* Found out how many registers we need to save. */
4363 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4364 fp_saved = (EABI_FLOAT_VARARGS_P
4365 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4374 ptr = plus_constant (virtual_incoming_args_rtx,
4375 REG_PARM_STACK_SPACE (cfun->decl)
4376 - gp_saved * UNITS_PER_WORD);
4377 mem = gen_rtx_MEM (BLKmode, ptr);
4378 set_mem_alias_set (mem, get_varargs_alias_set ());
4380 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4385 /* We can't use move_block_from_reg, because it will use
4387 enum machine_mode mode;
4390 /* Set OFF to the offset from virtual_incoming_args_rtx of
4391 the first float register. The FP save area lies below
4392 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4393 off = -gp_saved * UNITS_PER_WORD;
4394 off &= ~(UNITS_PER_FPVALUE - 1);
4395 off -= fp_saved * UNITS_PER_FPREG;
4397 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4399 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
4400 i += MAX_FPRS_PER_FMT)
4404 ptr = plus_constant (virtual_incoming_args_rtx, off);
4405 mem = gen_rtx_MEM (mode, ptr);
4406 set_mem_alias_set (mem, get_varargs_alias_set ());
4407 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4408 off += UNITS_PER_HWFPVALUE;
4412 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4413 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4414 + fp_saved * UNITS_PER_FPREG);
4417 /* Create the va_list data type.
4418 We keep 3 pointers, and two offsets.
4419 Two pointers are to the overflow area, which starts at the CFA.
4420 One of these is constant, for addressing into the GPR save area below it.
4421 The other is advanced up the stack through the overflow region.
4422 The third pointer is to the GPR save area. Since the FPR save area
4423 is just below it, we can address FPR slots off this pointer.
4424 We also keep two one-byte offsets, which are to be subtracted from the
4425 constant pointers to yield addresses in the GPR and FPR save areas.
4426 These are downcounted as float or non-float arguments are used,
4427 and when they get to zero, the argument must be obtained from the
4429 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4430 pointer is enough. It's started at the GPR save area, and is
4432 Note that the GPR save area is not constant size, due to optimization
4433 in the prologue. Hence, we can't use a design with two pointers
4434 and two offsets, although we could have designed this with two pointers
4435 and three offsets. */
4438 mips_build_builtin_va_list (void)
4440 if (EABI_FLOAT_VARARGS_P)
4442 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4445 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4447 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4449 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4451 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4453 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4454 unsigned_char_type_node);
4455 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4456 unsigned_char_type_node);
4457 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4458 warn on every user file. */
4459 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4460 array = build_array_type (unsigned_char_type_node,
4461 build_index_type (index));
4462 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4464 DECL_FIELD_CONTEXT (f_ovfl) = record;
4465 DECL_FIELD_CONTEXT (f_gtop) = record;
4466 DECL_FIELD_CONTEXT (f_ftop) = record;
4467 DECL_FIELD_CONTEXT (f_goff) = record;
4468 DECL_FIELD_CONTEXT (f_foff) = record;
4469 DECL_FIELD_CONTEXT (f_res) = record;
4471 TYPE_FIELDS (record) = f_ovfl;
4472 TREE_CHAIN (f_ovfl) = f_gtop;
4473 TREE_CHAIN (f_gtop) = f_ftop;
4474 TREE_CHAIN (f_ftop) = f_goff;
4475 TREE_CHAIN (f_goff) = f_foff;
4476 TREE_CHAIN (f_foff) = f_res;
4478 layout_type (record);
4481 else if (TARGET_IRIX && TARGET_IRIX6)
4482 /* On IRIX 6, this type is 'char *'. */
4483 return build_pointer_type (char_type_node);
4485 /* Otherwise, we use 'void *'. */
4486 return ptr_type_node;
4489 /* Implement va_start. */
4492 mips_va_start (tree valist, rtx nextarg)
4494 if (EABI_FLOAT_VARARGS_P)
4496 const CUMULATIVE_ARGS *cum;
4497 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4498 tree ovfl, gtop, ftop, goff, foff;
4500 int gpr_save_area_size;
4501 int fpr_save_area_size;
4504 cum = ¤t_function_args_info;
4506 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4508 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4510 f_ovfl = TYPE_FIELDS (va_list_type_node);
4511 f_gtop = TREE_CHAIN (f_ovfl);
4512 f_ftop = TREE_CHAIN (f_gtop);
4513 f_goff = TREE_CHAIN (f_ftop);
4514 f_foff = TREE_CHAIN (f_goff);
4516 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4518 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4520 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4522 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4524 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4527 /* Emit code to initialize OVFL, which points to the next varargs
4528 stack argument. CUM->STACK_WORDS gives the number of stack
4529 words used by named arguments. */
4530 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4531 if (cum->stack_words > 0)
4532 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
4533 size_int (cum->stack_words * UNITS_PER_WORD));
4534 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4535 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4537 /* Emit code to initialize GTOP, the top of the GPR save area. */
4538 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4539 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gtop), gtop, t);
4540 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4542 /* Emit code to initialize FTOP, the top of the FPR save area.
4543 This address is gpr_save_area_bytes below GTOP, rounded
4544 down to the next fp-aligned boundary. */
4545 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4546 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4547 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4549 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
4550 size_int (-fpr_offset));
4551 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ftop), ftop, t);
4552 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4554 /* Emit code to initialize GOFF, the offset from GTOP of the
4555 next GPR argument. */
4556 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (goff), goff,
4557 build_int_cst (NULL_TREE, gpr_save_area_size));
4558 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4560 /* Likewise emit code to initialize FOFF, the offset from FTOP
4561 of the next FPR argument. */
4562 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (foff), foff,
4563 build_int_cst (NULL_TREE, fpr_save_area_size));
4564 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4568 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4569 std_expand_builtin_va_start (valist, nextarg);
4573 /* Implement va_arg. */
4576 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4578 HOST_WIDE_INT size, rsize;
4582 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4585 type = build_pointer_type (type);
4587 size = int_size_in_bytes (type);
4588 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4590 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4591 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4594 /* Not a simple merged stack. */
4596 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4597 tree ovfl, top, off, align;
4598 HOST_WIDE_INT osize;
4601 f_ovfl = TYPE_FIELDS (va_list_type_node);
4602 f_gtop = TREE_CHAIN (f_ovfl);
4603 f_ftop = TREE_CHAIN (f_gtop);
4604 f_goff = TREE_CHAIN (f_ftop);
4605 f_foff = TREE_CHAIN (f_goff);
4607 /* We maintain separate pointers and offsets for floating-point
4608 and integer arguments, but we need similar code in both cases.
4611 TOP be the top of the register save area;
4612 OFF be the offset from TOP of the next register;
4613 ADDR_RTX be the address of the argument;
4614 RSIZE be the number of bytes used to store the argument
4615 when it's in the register save area;
4616 OSIZE be the number of bytes used to store it when it's
4617 in the stack overflow area; and
4618 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4620 The code we want is:
4622 1: off &= -rsize; // round down
4625 4: addr_rtx = top - off;
4630 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4631 10: addr_rtx = ovfl + PADDING;
4635 [1] and [9] can sometimes be optimized away. */
4637 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4640 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4641 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4643 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4645 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4648 /* When floating-point registers are saved to the stack,
4649 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4650 of the float's precision. */
4651 rsize = UNITS_PER_HWFPVALUE;
4653 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4654 (= PARM_BOUNDARY bits). This can be different from RSIZE
4657 (1) On 32-bit targets when TYPE is a structure such as:
4659 struct s { float f; };
4661 Such structures are passed in paired FPRs, so RSIZE
4662 will be 8 bytes. However, the structure only takes
4663 up 4 bytes of memory, so OSIZE will only be 4.
4665 (2) In combinations such as -mgp64 -msingle-float
4666 -fshort-double. Doubles passed in registers
4667 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4668 but those passed on the stack take up
4669 UNITS_PER_WORD bytes. */
4670 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4674 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4676 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4678 if (rsize > UNITS_PER_WORD)
4680 /* [1] Emit code for: off &= -rsize. */
4681 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4682 build_int_cst (NULL_TREE, -rsize));
4683 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (off), off, t);
4684 gimplify_and_add (t, pre_p);
4689 /* [2] Emit code to branch if off == 0. */
4690 t = build2 (NE_EXPR, boolean_type_node, off,
4691 build_int_cst (TREE_TYPE (off), 0));
4692 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4694 /* [5] Emit code for: off -= rsize. We do this as a form of
4695 post-increment not available to C. Also widen for the
4696 coming pointer arithmetic. */
4697 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4698 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4699 t = fold_convert (sizetype, t);
4700 t = fold_build1 (NEGATE_EXPR, sizetype, t);
4702 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4703 the argument has RSIZE - SIZE bytes of leading padding. */
4704 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
4705 if (BYTES_BIG_ENDIAN && rsize > size)
4707 u = size_int (rsize - size);
4708 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4710 COND_EXPR_THEN (addr) = t;
4712 if (osize > UNITS_PER_WORD)
4714 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4715 u = size_int (osize - 1);
4716 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4717 t = fold_convert (sizetype, t);
4718 u = size_int (-osize);
4719 t = build2 (BIT_AND_EXPR, sizetype, t, u);
4720 t = fold_convert (TREE_TYPE (ovfl), t);
4721 align = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovfl), ovfl, t);
4726 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4727 post-increment ovfl by osize. On big-endian machines,
4728 the argument has OSIZE - SIZE bytes of leading padding. */
4729 u = fold_convert (TREE_TYPE (ovfl),
4730 build_int_cst (NULL_TREE, osize));
4731 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4732 if (BYTES_BIG_ENDIAN && osize > size)
4734 u = size_int (osize - size);
4735 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
4738 /* String [9] and [10,11] together. */
4740 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4741 COND_EXPR_ELSE (addr) = t;
4743 addr = fold_convert (build_pointer_type (type), addr);
4744 addr = build_va_arg_indirect_ref (addr);
4748 addr = build_va_arg_indirect_ref (addr);
4753 /* Return true if it is possible to use left/right accesses for a
4754 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4755 returning true, update *OP, *LEFT and *RIGHT as follows:
4757 *OP is a BLKmode reference to the whole field.
4759 *LEFT is a QImode reference to the first byte if big endian or
4760 the last byte if little endian. This address can be used in the
4761 left-side instructions (lwl, swl, ldl, sdl).
4763 *RIGHT is a QImode reference to the opposite end of the field and
4764 can be used in the patterning right-side instruction. */
4767 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4768 rtx *left, rtx *right)
4772 /* Check that the operand really is a MEM. Not all the extv and
4773 extzv predicates are checked. */
4777 /* Check that the size is valid. */
4778 if (width != 32 && (!TARGET_64BIT || width != 64))
4781 /* We can only access byte-aligned values. Since we are always passed
4782 a reference to the first byte of the field, it is not necessary to
4783 do anything with BITPOS after this check. */
4784 if (bitpos % BITS_PER_UNIT != 0)
4787 /* Reject aligned bitfields: we want to use a normal load or store
4788 instead of a left/right pair. */
4789 if (MEM_ALIGN (*op) >= width)
4792 /* Adjust *OP to refer to the whole field. This also has the effect
4793 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4794 *op = adjust_address (*op, BLKmode, 0);
4795 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4797 /* Get references to both ends of the field. We deliberately don't
4798 use the original QImode *OP for FIRST since the new BLKmode one
4799 might have a simpler address. */
4800 first = adjust_address (*op, QImode, 0);
4801 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4803 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4804 be the upper word and RIGHT the lower word. */
4805 if (TARGET_BIG_ENDIAN)
4806 *left = first, *right = last;
4808 *left = last, *right = first;
4814 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4815 Return true on success. We only handle cases where zero_extract is
4816 equivalent to sign_extract. */
4819 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4821 rtx left, right, temp;
4823 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4824 paradoxical word_mode subreg. This is the only case in which
4825 we allow the destination to be larger than the source. */
4826 if (GET_CODE (dest) == SUBREG
4827 && GET_MODE (dest) == DImode
4828 && SUBREG_BYTE (dest) == 0
4829 && GET_MODE (SUBREG_REG (dest)) == SImode)
4830 dest = SUBREG_REG (dest);
4832 /* After the above adjustment, the destination must be the same
4833 width as the source. */
4834 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4837 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4840 temp = gen_reg_rtx (GET_MODE (dest));
4841 if (GET_MODE (dest) == DImode)
4843 emit_insn (gen_mov_ldl (temp, src, left));
4844 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4848 emit_insn (gen_mov_lwl (temp, src, left));
4849 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4855 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4859 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4862 enum machine_mode mode;
4864 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4867 mode = mode_for_size (width, MODE_INT, 0);
4868 src = gen_lowpart (mode, src);
4872 emit_insn (gen_mov_sdl (dest, src, left));
4873 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4877 emit_insn (gen_mov_swl (dest, src, left));
4878 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4883 /* Return true if X is a MEM with the same size as MODE. */
4886 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4893 size = MEM_SIZE (x);
4894 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4897 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4898 source of an "ext" instruction or the destination of an "ins"
4899 instruction. OP must be a register operand and the following
4900 conditions must hold:
4902 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4903 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4904 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4906 Also reject lengths equal to a word as they are better handled
4907 by the move patterns. */
4910 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4912 HOST_WIDE_INT len, pos;
4914 if (!ISA_HAS_EXT_INS
4915 || !register_operand (op, VOIDmode)
4916 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4919 len = INTVAL (size);
4920 pos = INTVAL (position);
4922 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4923 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4929 /* Set up globals to generate code for the ISA or processor
4930 described by INFO. */
4933 mips_set_architecture (const struct mips_cpu_info *info)
4937 mips_arch_info = info;
4938 mips_arch = info->cpu;
4939 mips_isa = info->isa;
4944 /* Likewise for tuning. */
4947 mips_set_tune (const struct mips_cpu_info *info)
4951 mips_tune_info = info;
4952 mips_tune = info->cpu;
4956 /* Implement TARGET_HANDLE_OPTION. */
4959 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4964 if (strcmp (arg, "32") == 0)
4966 else if (strcmp (arg, "o64") == 0)
4968 else if (strcmp (arg, "n32") == 0)
4970 else if (strcmp (arg, "64") == 0)
4972 else if (strcmp (arg, "eabi") == 0)
4973 mips_abi = ABI_EABI;
4980 return mips_parse_cpu (arg) != 0;
4983 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4984 return mips_isa_info != 0;
4986 case OPT_mno_flush_func:
4987 mips_cache_flush_func = NULL;
4995 /* Set up the threshold for data to go into the small data area, instead
4996 of the normal data area, and detect any conflicts in the switches. */
4999 override_options (void)
5001 int i, start, regno;
5002 enum machine_mode mode;
5004 #ifdef SUBTARGET_OVERRIDE_OPTIONS
5005 SUBTARGET_OVERRIDE_OPTIONS;
5008 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
5010 /* The following code determines the architecture and register size.
5011 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5012 The GAS and GCC code should be kept in sync as much as possible. */
5014 if (mips_arch_string != 0)
5015 mips_set_architecture (mips_parse_cpu (mips_arch_string));
5017 if (mips_isa_info != 0)
5019 if (mips_arch_info == 0)
5020 mips_set_architecture (mips_isa_info);
5021 else if (mips_arch_info->isa != mips_isa_info->isa)
5022 error ("-%s conflicts with the other architecture options, "
5023 "which specify a %s processor",
5024 mips_isa_info->name,
5025 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
5028 if (mips_arch_info == 0)
5030 #ifdef MIPS_CPU_STRING_DEFAULT
5031 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
5033 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
5037 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
5038 error ("-march=%s is not compatible with the selected ABI",
5039 mips_arch_info->name);
5041 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5042 if (mips_tune_string != 0)
5043 mips_set_tune (mips_parse_cpu (mips_tune_string));
5045 if (mips_tune_info == 0)
5046 mips_set_tune (mips_arch_info);
5048 /* Set cost structure for the processor. */
5050 mips_cost = &mips_rtx_cost_optimize_size;
5052 mips_cost = &mips_rtx_cost_data[mips_tune];
5054 if ((target_flags_explicit & MASK_64BIT) != 0)
5056 /* The user specified the size of the integer registers. Make sure
5057 it agrees with the ABI and ISA. */
5058 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5059 error ("-mgp64 used with a 32-bit processor");
5060 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5061 error ("-mgp32 used with a 64-bit ABI");
5062 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5063 error ("-mgp64 used with a 32-bit ABI");
5067 /* Infer the integer register size from the ABI and processor.
5068 Restrict ourselves to 32-bit registers if that's all the
5069 processor has, or if the ABI cannot handle 64-bit registers. */
5070 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5071 target_flags &= ~MASK_64BIT;
5073 target_flags |= MASK_64BIT;
5076 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5078 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5079 only one right answer here. */
5080 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5081 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5082 else if (!TARGET_64BIT && TARGET_FLOAT64
5083 && !(ISA_HAS_MXHC1 && mips_abi == ABI_32))
5084 error ("-mgp32 and -mfp64 can only be combined if the target"
5085 " supports the mfhc1 and mthc1 instructions");
5086 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5087 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5091 /* -msingle-float selects 32-bit float registers. Otherwise the
5092 float registers should be the same size as the integer ones. */
5093 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5094 target_flags |= MASK_FLOAT64;
5096 target_flags &= ~MASK_FLOAT64;
5099 /* End of code shared with GAS. */
5101 if ((target_flags_explicit & MASK_LONG64) == 0)
5103 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5104 target_flags |= MASK_LONG64;
5106 target_flags &= ~MASK_LONG64;
5109 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
5110 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
5112 /* For some configurations, it is useful to have -march control
5113 the default setting of MASK_SOFT_FLOAT. */
5114 switch ((int) mips_arch)
5116 case PROCESSOR_R4100:
5117 case PROCESSOR_R4111:
5118 case PROCESSOR_R4120:
5119 case PROCESSOR_R4130:
5120 target_flags |= MASK_SOFT_FLOAT;
5124 target_flags &= ~MASK_SOFT_FLOAT;
5130 flag_pcc_struct_return = 0;
5132 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
5134 /* If neither -mbranch-likely nor -mno-branch-likely was given
5135 on the command line, set MASK_BRANCHLIKELY based on the target
5138 By default, we enable use of Branch Likely instructions on
5139 all architectures which support them with the following
5140 exceptions: when creating MIPS32 or MIPS64 code, and when
5141 tuning for architectures where their use tends to hurt
5144 The MIPS32 and MIPS64 architecture specifications say "Software
5145 is strongly encouraged to avoid use of Branch Likely
5146 instructions, as they will be removed from a future revision
5147 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
5148 issue those instructions unless instructed to do so by
5150 if (ISA_HAS_BRANCHLIKELY
5151 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
5152 && !(TUNE_MIPS5500 || TUNE_SB1))
5153 target_flags |= MASK_BRANCHLIKELY;
5155 target_flags &= ~MASK_BRANCHLIKELY;
5157 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
5158 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
5160 /* The effect of -mabicalls isn't defined for the EABI. */
5161 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
5163 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
5164 target_flags &= ~MASK_ABICALLS;
5167 if (TARGET_ABICALLS)
5169 /* We need to set flag_pic for executables as well as DSOs
5170 because we may reference symbols that are not defined in
5171 the final executable. (MIPS does not use things like
5172 copy relocs, for example.)
5174 Also, there is a body of code that uses __PIC__ to distinguish
5175 between -mabicalls and -mno-abicalls code. */
5177 if (mips_section_threshold > 0)
5178 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
5181 if (TARGET_VXWORKS_RTP && mips_section_threshold > 0)
5182 warning (0, "-G and -mrtp are incompatible");
5184 /* mips_split_addresses is a half-way house between explicit
5185 relocations and the traditional assembler macros. It can
5186 split absolute 32-bit symbolic constants into a high/lo_sum
5187 pair but uses macros for other sorts of access.
5189 Like explicit relocation support for REL targets, it relies
5190 on GNU extensions in the assembler and the linker.
5192 Although this code should work for -O0, it has traditionally
5193 been treated as an optimization. */
5194 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
5195 && optimize && !flag_pic
5196 && !ABI_HAS_64BIT_SYMBOLS)
5197 mips_split_addresses = 1;
5199 mips_split_addresses = 0;
5201 /* -mvr4130-align is a "speed over size" optimization: it usually produces
5202 faster code, but at the expense of more nops. Enable it at -O3 and
5204 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
5205 target_flags |= MASK_VR4130_ALIGN;
5207 /* When compiling for the mips16, we cannot use floating point. We
5208 record the original hard float value in mips16_hard_float. */
5211 if (TARGET_SOFT_FLOAT)
5212 mips16_hard_float = 0;
5214 mips16_hard_float = 1;
5215 target_flags |= MASK_SOFT_FLOAT;
5217 /* Don't run the scheduler before reload, since it tends to
5218 increase register pressure. */
5219 flag_schedule_insns = 0;
5221 /* Don't do hot/cold partitioning. The constant layout code expects
5222 the whole function to be in a single section. */
5223 flag_reorder_blocks_and_partition = 0;
5225 /* Silently disable -mexplicit-relocs since it doesn't apply
5226 to mips16 code. Even so, it would overly pedantic to warn
5227 about "-mips16 -mexplicit-relocs", especially given that
5228 we use a %gprel() operator. */
5229 target_flags &= ~MASK_EXPLICIT_RELOCS;
5232 /* When using explicit relocs, we call dbr_schedule from within
5234 if (TARGET_EXPLICIT_RELOCS)
5236 mips_flag_delayed_branch = flag_delayed_branch;
5237 flag_delayed_branch = 0;
5240 #ifdef MIPS_TFMODE_FORMAT
5241 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
5244 /* Make sure that the user didn't turn off paired single support when
5245 MIPS-3D support is requested. */
5246 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
5247 && !TARGET_PAIRED_SINGLE_FLOAT)
5248 error ("-mips3d requires -mpaired-single");
5250 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
5252 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
5254 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
5255 and TARGET_HARD_FLOAT are both true. */
5256 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
5257 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
5259 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
5261 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
5262 error ("-mips3d/-mpaired-single must be used with -mips64");
5264 /* If TARGET_DSPR2, enable MASK_DSP. */
5266 target_flags |= MASK_DSP;
5268 if (TARGET_MIPS16 && TARGET_DSP)
5269 error ("-mips16 and -mdsp cannot be used together");
5271 mips_print_operand_punct['?'] = 1;
5272 mips_print_operand_punct['#'] = 1;
5273 mips_print_operand_punct['/'] = 1;
5274 mips_print_operand_punct['&'] = 1;
5275 mips_print_operand_punct['!'] = 1;
5276 mips_print_operand_punct['*'] = 1;
5277 mips_print_operand_punct['@'] = 1;
5278 mips_print_operand_punct['.'] = 1;
5279 mips_print_operand_punct['('] = 1;
5280 mips_print_operand_punct[')'] = 1;
5281 mips_print_operand_punct['['] = 1;
5282 mips_print_operand_punct[']'] = 1;
5283 mips_print_operand_punct['<'] = 1;
5284 mips_print_operand_punct['>'] = 1;
5285 mips_print_operand_punct['{'] = 1;
5286 mips_print_operand_punct['}'] = 1;
5287 mips_print_operand_punct['^'] = 1;
5288 mips_print_operand_punct['$'] = 1;
5289 mips_print_operand_punct['+'] = 1;
5290 mips_print_operand_punct['~'] = 1;
5292 /* Set up array to map GCC register number to debug register number.
5293 Ignore the special purpose register numbers. */
5295 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5296 mips_dbx_regno[i] = -1;
5298 start = GP_DBX_FIRST - GP_REG_FIRST;
5299 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5300 mips_dbx_regno[i] = i + start;
5302 start = FP_DBX_FIRST - FP_REG_FIRST;
5303 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5304 mips_dbx_regno[i] = i + start;
5306 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5307 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5309 /* Set up array giving whether a given register can hold a given mode. */
5311 for (mode = VOIDmode;
5312 mode != MAX_MACHINE_MODE;
5313 mode = (enum machine_mode) ((int)mode + 1))
5315 register int size = GET_MODE_SIZE (mode);
5316 register enum mode_class class = GET_MODE_CLASS (mode);
5318 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5322 if (mode == CCV2mode)
5325 && (regno - ST_REG_FIRST) % 2 == 0);
5327 else if (mode == CCV4mode)
5330 && (regno - ST_REG_FIRST) % 4 == 0);
5332 else if (mode == CCmode)
5335 temp = (regno == FPSW_REGNUM);
5337 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5338 || FP_REG_P (regno));
5341 else if (GP_REG_P (regno))
5342 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5344 else if (FP_REG_P (regno))
5345 temp = ((((regno % MAX_FPRS_PER_FMT) == 0)
5346 || (MIN_FPRS_PER_FMT == 1
5347 && size <= UNITS_PER_FPREG))
5348 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5349 || class == MODE_VECTOR_FLOAT)
5350 && size <= UNITS_PER_FPVALUE)
5351 /* Allow integer modes that fit into a single
5352 register. We need to put integers into FPRs
5353 when using instructions like cvt and trunc.
5354 We can't allow sizes smaller than a word,
5355 the FPU has no appropriate load/store
5356 instructions for those. */
5357 || (class == MODE_INT
5358 && size >= MIN_UNITS_PER_WORD
5359 && size <= UNITS_PER_FPREG)
5360 /* Allow TFmode for CCmode reloads. */
5361 || (ISA_HAS_8CC && mode == TFmode)));
5363 else if (ACC_REG_P (regno))
5364 temp = (INTEGRAL_MODE_P (mode)
5365 && (size <= UNITS_PER_WORD
5366 || (ACC_HI_REG_P (regno)
5367 && size == 2 * UNITS_PER_WORD)));
5369 else if (ALL_COP_REG_P (regno))
5370 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5374 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5378 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5379 initialized yet, so we can't use that here. */
5380 gpr_mode = TARGET_64BIT ? DImode : SImode;
5382 /* Provide default values for align_* for 64-bit targets. */
5383 if (TARGET_64BIT && !TARGET_MIPS16)
5385 if (align_loops == 0)
5387 if (align_jumps == 0)
5389 if (align_functions == 0)
5390 align_functions = 8;
5393 /* Function to allocate machine-dependent function status. */
5394 init_machine_status = &mips_init_machine_status;
5396 if (ABI_HAS_64BIT_SYMBOLS)
5398 if (TARGET_EXPLICIT_RELOCS)
5400 mips_split_p[SYMBOL_64_HIGH] = true;
5401 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5402 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5404 mips_split_p[SYMBOL_64_MID] = true;
5405 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5406 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5408 mips_split_p[SYMBOL_64_LOW] = true;
5409 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5410 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5412 mips_split_p[SYMBOL_GENERAL] = true;
5413 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5418 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5420 mips_split_p[SYMBOL_GENERAL] = true;
5421 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5422 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5428 /* The high part is provided by a pseudo copy of $gp. */
5429 mips_split_p[SYMBOL_SMALL_DATA] = true;
5430 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5433 if (TARGET_EXPLICIT_RELOCS)
5435 /* Small data constants are kept whole until after reload,
5436 then lowered by mips_rewrite_small_data. */
5437 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5439 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
5442 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5443 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
5447 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5448 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
5453 /* The HIGH and LO_SUM are matched by special .md patterns. */
5454 mips_split_p[SYMBOL_GOT_DISP] = true;
5456 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
5457 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
5458 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
5460 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5461 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5462 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5467 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
5469 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
5470 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5476 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5477 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5478 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5481 /* Thread-local relocation operators. */
5482 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5483 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5484 mips_split_p[SYMBOL_DTPREL] = 1;
5485 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5486 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5487 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5488 mips_split_p[SYMBOL_TPREL] = 1;
5489 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5490 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5492 mips_lo_relocs[SYMBOL_HALF] = "%half(";
5494 /* We don't have a thread pointer access instruction on MIPS16, or
5495 appropriate TLS relocations. */
5497 targetm.have_tls = false;
5499 /* Default to working around R4000 errata only if the processor
5500 was selected explicitly. */
5501 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5502 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5503 target_flags |= MASK_FIX_R4000;
5505 /* Default to working around R4400 errata only if the processor
5506 was selected explicitly. */
5507 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5508 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5509 target_flags |= MASK_FIX_R4400;
5512 /* Implement CONDITIONAL_REGISTER_USAGE. */
5515 mips_conditional_register_usage (void)
5521 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5522 fixed_regs[regno] = call_used_regs[regno] = 1;
5524 if (!TARGET_HARD_FLOAT)
5528 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5529 fixed_regs[regno] = call_used_regs[regno] = 1;
5530 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5531 fixed_regs[regno] = call_used_regs[regno] = 1;
5533 else if (! ISA_HAS_8CC)
5537 /* We only have a single condition code register. We
5538 implement this by hiding all the condition code registers,
5539 and generating RTL that refers directly to ST_REG_FIRST. */
5540 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5541 fixed_regs[regno] = call_used_regs[regno] = 1;
5543 /* In mips16 mode, we permit the $t temporary registers to be used
5544 for reload. We prohibit the unused $s registers, since they
5545 are caller saved, and saving them via a mips16 register would
5546 probably waste more time than just reloading the value. */
5549 fixed_regs[18] = call_used_regs[18] = 1;
5550 fixed_regs[19] = call_used_regs[19] = 1;
5551 fixed_regs[20] = call_used_regs[20] = 1;
5552 fixed_regs[21] = call_used_regs[21] = 1;
5553 fixed_regs[22] = call_used_regs[22] = 1;
5554 fixed_regs[23] = call_used_regs[23] = 1;
5555 fixed_regs[26] = call_used_regs[26] = 1;
5556 fixed_regs[27] = call_used_regs[27] = 1;
5557 fixed_regs[30] = call_used_regs[30] = 1;
5559 /* fp20-23 are now caller saved. */
5560 if (mips_abi == ABI_64)
5563 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5564 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5566 /* Odd registers from fp21 to fp31 are now caller saved. */
5567 if (mips_abi == ABI_N32)
5570 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5571 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5575 /* Allocate a chunk of memory for per-function machine-dependent data. */
5576 static struct machine_function *
5577 mips_init_machine_status (void)
5579 return ((struct machine_function *)
5580 ggc_alloc_cleared (sizeof (struct machine_function)));
5583 /* On the mips16, we want to allocate $24 (T_REG) before other
5584 registers for instructions for which it is possible. This helps
5585 avoid shuffling registers around in order to set up for an xor,
5586 encouraging the compiler to use a cmp instead. */
5589 mips_order_regs_for_local_alloc (void)
5593 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5594 reg_alloc_order[i] = i;
5598 /* It really doesn't matter where we put register 0, since it is
5599 a fixed register anyhow. */
5600 reg_alloc_order[0] = 24;
5601 reg_alloc_order[24] = 0;
5606 /* The MIPS debug format wants all automatic variables and arguments
5607 to be in terms of the virtual frame pointer (stack pointer before
5608 any adjustment in the function), while the MIPS 3.0 linker wants
5609 the frame pointer to be the stack pointer after the initial
5610 adjustment. So, we do the adjustment here. The arg pointer (which
5611 is eliminated) points to the virtual frame pointer, while the frame
5612 pointer (which may be eliminated) points to the stack pointer after
5613 the initial adjustments. */
5616 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5618 rtx offset2 = const0_rtx;
5619 rtx reg = eliminate_constant_term (addr, &offset2);
5622 offset = INTVAL (offset2);
5624 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5625 || reg == hard_frame_pointer_rtx)
5627 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5628 ? compute_frame_size (get_frame_size ())
5629 : cfun->machine->frame.total_size;
5631 /* MIPS16 frame is smaller */
5632 if (frame_pointer_needed && TARGET_MIPS16)
5633 frame_size -= cfun->machine->frame.args_size;
5635 offset = offset - frame_size;
5638 /* sdbout_parms does not want this to crash for unrecognized cases. */
5640 else if (reg != arg_pointer_rtx)
5641 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5648 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5650 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5651 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5652 'h' OP is HIGH, prints %hi(X),
5653 'd' output integer constant in decimal,
5654 'z' if the operand is 0, use $0 instead of normal operand.
5655 'D' print second part of double-word register or memory operand.
5656 'L' print low-order register of double-word register operand.
5657 'M' print high-order register of double-word register operand.
5658 'C' print part of opcode for a branch condition.
5659 'F' print part of opcode for a floating-point branch condition.
5660 'N' print part of opcode for a branch condition, inverted.
5661 'W' print part of opcode for a floating-point branch condition, inverted.
5662 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5663 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5664 't' like 'T', but with the EQ/NE cases reversed
5665 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5666 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5667 'R' print the reloc associated with LO_SUM
5668 'q' print DSP accumulator registers
5670 The punctuation characters are:
5672 '(' Turn on .set noreorder
5673 ')' Turn on .set reorder
5674 '[' Turn on .set noat
5676 '<' Turn on .set nomacro
5677 '>' Turn on .set macro
5678 '{' Turn on .set volatile (not GAS)
5679 '}' Turn on .set novolatile (not GAS)
5680 '&' Turn on .set noreorder if filling delay slots
5681 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5682 '!' Turn on .set nomacro if filling delay slots
5683 '#' Print nop if in a .set noreorder section.
5684 '/' Like '#', but does nothing within a delayed branch sequence
5685 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5686 '@' Print the name of the assembler temporary register (at or $1).
5687 '.' Print the name of the register with a hard-wired zero (zero or $0).
5688 '^' Print the name of the pic call-through register (t9 or $25).
5689 '$' Print the name of the stack pointer register (sp or $29).
5690 '+' Print the name of the gp register (usually gp or $28).
5691 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5694 print_operand (FILE *file, rtx op, int letter)
5696 register enum rtx_code code;
5698 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5703 if (mips_branch_likely)
5708 fputs (reg_names [GP_REG_FIRST + 1], file);
5712 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5716 fputs (reg_names [GP_REG_FIRST + 0], file);
5720 fputs (reg_names[STACK_POINTER_REGNUM], file);
5724 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5728 if (final_sequence != 0 && set_noreorder++ == 0)
5729 fputs (".set\tnoreorder\n\t", file);
5733 if (final_sequence != 0)
5735 if (set_noreorder++ == 0)
5736 fputs (".set\tnoreorder\n\t", file);
5738 if (set_nomacro++ == 0)
5739 fputs (".set\tnomacro\n\t", file);
5744 if (final_sequence != 0 && set_nomacro++ == 0)
5745 fputs ("\n\t.set\tnomacro", file);
5749 if (set_noreorder != 0)
5750 fputs ("\n\tnop", file);
5754 /* Print an extra newline so that the delayed insn is separated
5755 from the following ones. This looks neater and is consistent
5756 with non-nop delayed sequences. */
5757 if (set_noreorder != 0 && final_sequence == 0)
5758 fputs ("\n\tnop\n", file);
5762 if (set_noreorder++ == 0)
5763 fputs (".set\tnoreorder\n\t", file);
5767 if (set_noreorder == 0)
5768 error ("internal error: %%) found without a %%( in assembler pattern");
5770 else if (--set_noreorder == 0)
5771 fputs ("\n\t.set\treorder", file);
5776 if (set_noat++ == 0)
5777 fputs (".set\tnoat\n\t", file);
5782 error ("internal error: %%] found without a %%[ in assembler pattern");
5783 else if (--set_noat == 0)
5784 fputs ("\n\t.set\tat", file);
5789 if (set_nomacro++ == 0)
5790 fputs (".set\tnomacro\n\t", file);
5794 if (set_nomacro == 0)
5795 error ("internal error: %%> found without a %%< in assembler pattern");
5796 else if (--set_nomacro == 0)
5797 fputs ("\n\t.set\tmacro", file);
5802 if (set_volatile++ == 0)
5803 fputs ("#.set\tvolatile\n\t", file);
5807 if (set_volatile == 0)
5808 error ("internal error: %%} found without a %%{ in assembler pattern");
5809 else if (--set_volatile == 0)
5810 fputs ("\n\t#.set\tnovolatile", file);
5816 if (align_labels_log > 0)
5817 ASM_OUTPUT_ALIGN (file, align_labels_log);
5822 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5831 error ("PRINT_OPERAND null pointer");
5835 code = GET_CODE (op);
5840 case EQ: fputs ("eq", file); break;
5841 case NE: fputs ("ne", file); break;
5842 case GT: fputs ("gt", file); break;
5843 case GE: fputs ("ge", file); break;
5844 case LT: fputs ("lt", file); break;
5845 case LE: fputs ("le", file); break;
5846 case GTU: fputs ("gtu", file); break;
5847 case GEU: fputs ("geu", file); break;
5848 case LTU: fputs ("ltu", file); break;
5849 case LEU: fputs ("leu", file); break;
5851 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5854 else if (letter == 'N')
5857 case EQ: fputs ("ne", file); break;
5858 case NE: fputs ("eq", file); break;
5859 case GT: fputs ("le", file); break;
5860 case GE: fputs ("lt", file); break;
5861 case LT: fputs ("ge", file); break;
5862 case LE: fputs ("gt", file); break;
5863 case GTU: fputs ("leu", file); break;
5864 case GEU: fputs ("ltu", file); break;
5865 case LTU: fputs ("geu", file); break;
5866 case LEU: fputs ("gtu", file); break;
5868 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5871 else if (letter == 'F')
5874 case EQ: fputs ("c1f", file); break;
5875 case NE: fputs ("c1t", file); break;
5877 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5880 else if (letter == 'W')
5883 case EQ: fputs ("c1t", file); break;
5884 case NE: fputs ("c1f", file); break;
5886 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5889 else if (letter == 'h')
5891 if (GET_CODE (op) == HIGH)
5894 print_operand_reloc (file, op, mips_hi_relocs);
5897 else if (letter == 'R')
5898 print_operand_reloc (file, op, mips_lo_relocs);
5900 else if (letter == 'Y')
5902 if (GET_CODE (op) == CONST_INT
5903 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5904 < ARRAY_SIZE (mips_fp_conditions)))
5905 fputs (mips_fp_conditions[INTVAL (op)], file);
5907 output_operand_lossage ("invalid %%Y value");
5910 else if (letter == 'Z')
5914 print_operand (file, op, 0);
5919 else if (letter == 'q')
5924 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5926 regnum = REGNO (op);
5927 if (MD_REG_P (regnum))
5928 fprintf (file, "$ac0");
5929 else if (DSP_ACC_REG_P (regnum))
5930 fprintf (file, "$ac%c", reg_names[regnum][3]);
5932 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5935 else if (code == REG || code == SUBREG)
5937 register int regnum;
5940 regnum = REGNO (op);
5942 regnum = true_regnum (op);
5944 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5945 || (letter == 'L' && WORDS_BIG_ENDIAN)
5949 fprintf (file, "%s", reg_names[regnum]);
5952 else if (code == MEM)
5955 output_address (plus_constant (XEXP (op, 0), 4));
5957 output_address (XEXP (op, 0));
5960 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5961 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5963 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5964 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5966 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5967 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5969 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5970 fputs (reg_names[GP_REG_FIRST], file);
5972 else if (letter == 'd' || letter == 'x' || letter == 'X')
5973 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5975 else if (letter == 'T' || letter == 't')
5977 int truth = (code == NE) == (letter == 'T');
5978 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5981 else if (CONST_GP_P (op))
5982 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5985 output_addr_const (file, op);
5989 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5990 RELOCS is the array of relocations to use. */
5993 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5995 enum mips_symbol_type symbol_type;
5999 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
6000 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
6002 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
6003 split_const (op, &base, &offset);
6004 if (UNSPEC_ADDRESS_P (base))
6005 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6007 fputs (relocs[symbol_type], file);
6008 output_addr_const (file, op);
6009 for (p = relocs[symbol_type]; *p != 0; p++)
6014 /* Output address operand X to FILE. */
6017 print_operand_address (FILE *file, rtx x)
6019 struct mips_address_info addr;
6021 if (mips_classify_address (&addr, x, word_mode, true))
6025 print_operand (file, addr.offset, 0);
6026 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6029 case ADDRESS_LO_SUM:
6030 print_operand (file, addr.offset, 'R');
6031 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
6034 case ADDRESS_CONST_INT:
6035 output_addr_const (file, x);
6036 fprintf (file, "(%s)", reg_names[0]);
6039 case ADDRESS_SYMBOLIC:
6040 output_addr_const (file, x);
6046 /* When using assembler macros, keep track of all of small-data externs
6047 so that mips_file_end can emit the appropriate declarations for them.
6049 In most cases it would be safe (though pointless) to emit .externs
6050 for other symbols too. One exception is when an object is within
6051 the -G limit but declared by the user to be in a section other
6052 than .sbss or .sdata. */
6055 mips_output_external (FILE *file, tree decl, const char *name)
6057 default_elf_asm_output_external (file, decl, name);
6059 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
6060 set in order to avoid putting out names that are never really
6062 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
6064 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
6066 fputs ("\t.extern\t", file);
6067 assemble_name (file, name);
6068 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
6069 int_size_in_bytes (TREE_TYPE (decl)));
6071 else if (TARGET_IRIX
6072 && mips_abi == ABI_32
6073 && TREE_CODE (decl) == FUNCTION_DECL)
6075 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
6076 `.global name .text' directive for every used but
6077 undefined function. If we don't, the linker may perform
6078 an optimization (skipping over the insns that set $gp)
6079 when it is unsafe. */
6080 fputs ("\t.globl ", file);
6081 assemble_name (file, name);
6082 fputs (" .text\n", file);
6087 /* Emit a new filename to a stream. If we are smuggling stabs, try to
6088 put out a MIPS ECOFF file and a stab. */
6091 mips_output_filename (FILE *stream, const char *name)
6094 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6096 if (write_symbols == DWARF2_DEBUG)
6098 else if (mips_output_filename_first_time)
6100 mips_output_filename_first_time = 0;
6101 num_source_filenames += 1;
6102 current_function_file = name;
6103 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6104 output_quoted_string (stream, name);
6105 putc ('\n', stream);
6108 /* If we are emitting stabs, let dbxout.c handle this (except for
6109 the mips_output_filename_first_time case). */
6110 else if (write_symbols == DBX_DEBUG)
6113 else if (name != current_function_file
6114 && strcmp (name, current_function_file) != 0)
6116 num_source_filenames += 1;
6117 current_function_file = name;
6118 fprintf (stream, "\t.file\t%d ", num_source_filenames);
6119 output_quoted_string (stream, name);
6120 putc ('\n', stream);
6124 /* Output an ASCII string, in a space-saving way. PREFIX is the string
6125 that should be written before the opening quote, such as "\t.ascii\t"
6126 for real string data or "\t# " for a comment. */
6129 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
6134 register const unsigned char *string =
6135 (const unsigned char *)string_param;
6137 fprintf (stream, "%s\"", prefix);
6138 for (i = 0; i < len; i++)
6140 register int c = string[i];
6144 if (c == '\\' || c == '\"')
6146 putc ('\\', stream);
6154 fprintf (stream, "\\%03o", c);
6158 if (cur_pos > 72 && i+1 < len)
6161 fprintf (stream, "\"\n%s\"", prefix);
6164 fprintf (stream, "\"\n");
6167 /* Implement TARGET_ASM_FILE_START. */
6170 mips_file_start (void)
6172 default_file_start ();
6176 /* Generate a special section to describe the ABI switches used to
6177 produce the resultant binary. This used to be done by the assembler
6178 setting bits in the ELF header's flags field, but we have run out of
6179 bits. GDB needs this information in order to be able to correctly
6180 debug these binaries. See the function mips_gdbarch_init() in
6181 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6182 causes unnecessary IRIX 6 ld warnings. */
6183 const char * abi_string = NULL;
6187 case ABI_32: abi_string = "abi32"; break;
6188 case ABI_N32: abi_string = "abiN32"; break;
6189 case ABI_64: abi_string = "abi64"; break;
6190 case ABI_O64: abi_string = "abiO64"; break;
6191 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6195 /* Note - we use fprintf directly rather than calling switch_to_section
6196 because in this way we can avoid creating an allocated section. We
6197 do not want this section to take up any space in the running
6199 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
6201 /* There is no ELF header flag to distinguish long32 forms of the
6202 EABI from long64 forms. Emit a special section to help tools
6203 such as GDB. Do the same for o64, which is sometimes used with
6205 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
6206 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
6207 TARGET_LONG64 ? 64 : 32);
6209 /* Restore the default section. */
6210 fprintf (asm_out_file, "\t.previous\n");
6212 #ifdef HAVE_AS_GNU_ATTRIBUTE
6213 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
6214 TARGET_HARD_FLOAT_ABI ? (TARGET_DOUBLE_FLOAT ? 1 : 2) : 3);
6218 /* Generate the pseudo ops that System V.4 wants. */
6219 if (TARGET_ABICALLS)
6220 fprintf (asm_out_file, "\t.abicalls\n");
6223 fprintf (asm_out_file, "\t.set\tmips16\n");
6225 if (flag_verbose_asm)
6226 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6228 mips_section_threshold, mips_arch_info->name, mips_isa);
6231 #ifdef BSS_SECTION_ASM_OP
6232 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
6233 in the use of sbss. */
6236 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
6237 unsigned HOST_WIDE_INT size, int align)
6239 extern tree last_assemble_variable_decl;
6241 if (mips_in_small_data_p (decl))
6242 switch_to_section (get_named_section (NULL, ".sbss", 0));
6244 switch_to_section (bss_section);
6245 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6246 last_assemble_variable_decl = decl;
6247 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
6248 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
6252 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
6253 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6256 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6257 unsigned HOST_WIDE_INT size,
6260 /* If the target wants uninitialized const declarations in
6261 .rdata then don't put them in .comm. */
6262 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6263 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6264 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6266 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6267 targetm.asm_out.globalize_label (stream, name);
6269 switch_to_section (readonly_data_section);
6270 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6271 mips_declare_object (stream, name, "",
6272 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6276 mips_declare_common_object (stream, name, "\n\t.comm\t",
6280 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6281 NAME is the name of the object and ALIGN is the required alignment
6282 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6283 alignment argument. */
6286 mips_declare_common_object (FILE *stream, const char *name,
6287 const char *init_string,
6288 unsigned HOST_WIDE_INT size,
6289 unsigned int align, bool takes_alignment_p)
6291 if (!takes_alignment_p)
6293 size += (align / BITS_PER_UNIT) - 1;
6294 size -= size % (align / BITS_PER_UNIT);
6295 mips_declare_object (stream, name, init_string,
6296 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6299 mips_declare_object (stream, name, init_string,
6300 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6301 size, align / BITS_PER_UNIT);
6304 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6305 macros, mark the symbol as written so that mips_file_end won't emit an
6306 .extern for it. STREAM is the output file, NAME is the name of the
6307 symbol, INIT_STRING is the string that should be written before the
6308 symbol and FINAL_STRING is the string that should be written after it.
6309 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6312 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6313 const char *final_string, ...)
6317 fputs (init_string, stream);
6318 assemble_name (stream, name);
6319 va_start (ap, final_string);
6320 vfprintf (stream, final_string, ap);
6323 if (!TARGET_EXPLICIT_RELOCS)
6325 tree name_tree = get_identifier (name);
6326 TREE_ASM_WRITTEN (name_tree) = 1;
6330 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6331 extern int size_directive_output;
6333 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6334 definitions except that it uses mips_declare_object() to emit the label. */
6337 mips_declare_object_name (FILE *stream, const char *name,
6338 tree decl ATTRIBUTE_UNUSED)
6340 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6341 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6344 size_directive_output = 0;
6345 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6349 size_directive_output = 1;
6350 size = int_size_in_bytes (TREE_TYPE (decl));
6351 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6354 mips_declare_object (stream, name, "", ":\n");
6357 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6360 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6364 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6365 if (!flag_inhibit_size_directive
6366 && DECL_SIZE (decl) != 0
6367 && !at_end && top_level
6368 && DECL_INITIAL (decl) == error_mark_node
6369 && !size_directive_output)
6373 size_directive_output = 1;
6374 size = int_size_in_bytes (TREE_TYPE (decl));
6375 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6380 /* Return true if X is a small data address that can be rewritten
6384 mips_rewrite_small_data_p (rtx x)
6386 enum mips_symbol_type symbol_type;
6388 return (TARGET_EXPLICIT_RELOCS
6389 && mips_symbolic_constant_p (x, &symbol_type)
6390 && symbol_type == SYMBOL_SMALL_DATA);
6394 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6397 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6399 if (GET_CODE (*loc) == LO_SUM)
6402 return mips_rewrite_small_data_p (*loc);
6405 /* Return true if OP refers to small data symbols directly, not through
6409 mips_small_data_pattern_p (rtx op)
6411 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6414 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6417 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6419 if (mips_rewrite_small_data_p (*loc))
6420 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6422 if (GET_CODE (*loc) == LO_SUM)
6428 /* If possible, rewrite OP so that it refers to small data using
6429 explicit relocations. */
6432 mips_rewrite_small_data (rtx op)
6434 op = copy_insn (op);
6435 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6439 /* Return true if the current function has an insn that implicitly
6443 mips_function_has_gp_insn (void)
6445 /* Don't bother rechecking if we found one last time. */
6446 if (!cfun->machine->has_gp_insn_p)
6450 push_topmost_sequence ();
6451 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6453 && GET_CODE (PATTERN (insn)) != USE
6454 && GET_CODE (PATTERN (insn)) != CLOBBER
6455 && (get_attr_got (insn) != GOT_UNSET
6456 || small_data_pattern (PATTERN (insn), VOIDmode)))
6458 pop_topmost_sequence ();
6460 cfun->machine->has_gp_insn_p = (insn != 0);
6462 return cfun->machine->has_gp_insn_p;
6466 /* Return the register that should be used as the global pointer
6467 within this function. Return 0 if the function doesn't need
6468 a global pointer. */
6471 mips_global_pointer (void)
6475 /* $gp is always available unless we're using a GOT. */
6476 if (!TARGET_USE_GOT)
6477 return GLOBAL_POINTER_REGNUM;
6479 /* We must always provide $gp when it is used implicitly. */
6480 if (!TARGET_EXPLICIT_RELOCS)
6481 return GLOBAL_POINTER_REGNUM;
6483 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6485 if (current_function_profile)
6486 return GLOBAL_POINTER_REGNUM;
6488 /* If the function has a nonlocal goto, $gp must hold the correct
6489 global pointer for the target function. */
6490 if (current_function_has_nonlocal_goto)
6491 return GLOBAL_POINTER_REGNUM;
6493 /* If the gp is never referenced, there's no need to initialize it.
6494 Note that reload can sometimes introduce constant pool references
6495 into a function that otherwise didn't need them. For example,
6496 suppose we have an instruction like:
6498 (set (reg:DF R1) (float:DF (reg:SI R2)))
6500 If R2 turns out to be constant such as 1, the instruction may have a
6501 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6502 using this constant if R2 doesn't get allocated to a register.
6504 In cases like these, reload will have added the constant to the pool
6505 but no instruction will yet refer to it. */
6506 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
6507 && !current_function_uses_const_pool
6508 && !mips_function_has_gp_insn ())
6511 /* We need a global pointer, but perhaps we can use a call-clobbered
6512 register instead of $gp. */
6513 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
6514 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6515 if (!df_regs_ever_live_p (regno)
6516 && call_used_regs[regno]
6517 && !fixed_regs[regno]
6518 && regno != PIC_FUNCTION_ADDR_REGNUM)
6521 return GLOBAL_POINTER_REGNUM;
6525 /* Return true if the function return value MODE will get returned in a
6526 floating-point register. */
6529 mips_return_mode_in_fpr_p (enum machine_mode mode)
6531 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
6532 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
6533 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
6534 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
6537 /* Return a two-character string representing a function floating-point
6538 return mode, used to name MIPS16 function stubs. */
6541 mips16_call_stub_mode_suffix (enum machine_mode mode)
6545 else if (mode == DFmode)
6547 else if (mode == SCmode)
6549 else if (mode == DCmode)
6551 else if (mode == V2SFmode)
6557 /* Return true if the current function returns its value in a floating-point
6558 register in MIPS16 mode. */
6561 mips16_cfun_returns_in_fpr_p (void)
6563 tree return_type = DECL_RESULT (current_function_decl);
6564 return (mips16_hard_float
6565 && !aggregate_value_p (return_type, current_function_decl)
6566 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
6570 /* Return true if the current function must save REGNO. */
6573 mips_save_reg_p (unsigned int regno)
6575 /* We only need to save $gp if TARGET_CALL_SAVED_GP and only then
6576 if we have not chosen a call-clobbered substitute. */
6577 if (regno == GLOBAL_POINTER_REGNUM)
6578 return TARGET_CALL_SAVED_GP && cfun->machine->global_pointer == regno;
6580 /* Check call-saved registers. */
6581 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
6584 /* Save both registers in an FPR pair if either one is used. This is
6585 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
6586 register to be used without the even register. */
6587 if (FP_REG_P (regno)
6588 && MAX_FPRS_PER_FMT == 2
6589 && df_regs_ever_live_p (regno + 1)
6590 && !call_used_regs[regno + 1])
6593 /* We need to save the old frame pointer before setting up a new one. */
6594 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6597 /* We need to save the incoming return address if it is ever clobbered
6598 within the function. */
6599 if (regno == GP_REG_FIRST + 31 && df_regs_ever_live_p (regno))
6604 /* $18 is a special case in mips16 code. It may be used to call
6605 a function which returns a floating point value, but it is
6606 marked in call_used_regs. */
6607 if (regno == GP_REG_FIRST + 18 && df_regs_ever_live_p (regno))
6610 /* $31 is also a special case. It will be used to copy a return
6611 value into the floating point registers if the return value is
6613 if (regno == GP_REG_FIRST + 31
6614 && mips16_cfun_returns_in_fpr_p ())
6621 /* Return the index of the lowest X in the range [0, SIZE) for which
6622 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
6625 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
6630 for (i = 0; i < size; i++)
6631 if (BITSET_P (mask, regs[i]))
6637 /* *MASK_PTR is a mask of general purpose registers and *GP_REG_SIZE_PTR
6638 is the number of bytes that they occupy. If *MASK_PTR contains REGS[X]
6639 for some X in [0, SIZE), adjust *MASK_PTR and *GP_REG_SIZE_PTR so that
6640 the same is true for all indexes (X, SIZE). */
6643 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
6644 unsigned int size, HOST_WIDE_INT *gp_reg_size_ptr)
6648 i = mips16e_find_first_register (*mask_ptr, regs, size);
6649 for (i++; i < size; i++)
6650 if (!BITSET_P (*mask_ptr, regs[i]))
6652 *gp_reg_size_ptr += GET_MODE_SIZE (gpr_mode);
6653 *mask_ptr |= 1 << regs[i];
6657 /* Return the bytes needed to compute the frame pointer from the current
6658 stack pointer. SIZE is the size (in bytes) of the local variables.
6660 MIPS stack frames look like:
6662 Before call After call
6663 high +-----------------------+ +-----------------------+
6665 | caller's temps. | | caller's temps. |
6667 +-----------------------+ +-----------------------+
6669 | arguments on stack. | | arguments on stack. |
6671 +-----------------------+ +-----------------------+
6672 | 4 words to save | | 4 words to save |
6673 | arguments passed | | arguments passed |
6674 | in registers, even | | in registers, even |
6675 | if not passed. | | if not passed. |
6676 SP->+-----------------------+ VFP->+-----------------------+
6677 (VFP = SP+fp_sp_offset) | |\
6678 | fp register save | | fp_reg_size
6680 SP+gp_sp_offset->+-----------------------+
6682 | | gp register save | | gp_reg_size
6683 gp_reg_rounded | | |/
6684 | +-----------------------+
6685 \| alignment padding |
6686 +-----------------------+
6688 | local variables | | var_size
6690 +-----------------------+
6692 | alloca allocations |
6694 +-----------------------+
6696 cprestore_size | | GP save for V.4 abi |
6698 +-----------------------+
6700 | arguments on stack | |
6702 +-----------------------+ |
6703 | 4 words to save | | args_size
6704 | arguments passed | |
6705 | in registers, even | |
6706 | if not passed. | |
6707 low | (TARGET_OLDABI only) |/
6708 memory SP->+-----------------------+
6713 compute_frame_size (HOST_WIDE_INT size)
6716 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6717 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6718 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6719 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6720 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6721 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6722 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6723 unsigned int mask; /* mask of saved gp registers */
6724 unsigned int fmask; /* mask of saved fp registers */
6726 cfun->machine->global_pointer = mips_global_pointer ();
6732 var_size = MIPS_STACK_ALIGN (size);
6733 args_size = current_function_outgoing_args_size;
6734 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6736 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6737 functions. If the function has local variables, we're committed
6738 to allocating it anyway. Otherwise reclaim it here. */
6739 if (var_size == 0 && current_function_is_leaf)
6740 cprestore_size = args_size = 0;
6742 /* The MIPS 3.0 linker does not like functions that dynamically
6743 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6744 looks like we are trying to create a second frame pointer to the
6745 function, so allocate some stack space to make it happy. */
6747 if (args_size == 0 && current_function_calls_alloca)
6748 args_size = 4 * UNITS_PER_WORD;
6750 total_size = var_size + args_size + cprestore_size;
6752 /* Calculate space needed for gp registers. */
6753 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6754 if (mips_save_reg_p (regno))
6756 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6757 mask |= 1 << (regno - GP_REG_FIRST);
6760 /* We need to restore these for the handler. */
6761 if (current_function_calls_eh_return)
6766 regno = EH_RETURN_DATA_REGNO (i);
6767 if (regno == INVALID_REGNUM)
6769 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6770 mask |= 1 << (regno - GP_REG_FIRST);
6774 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
6775 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
6776 save all later registers too. */
6777 if (GENERATE_MIPS16E_SAVE_RESTORE)
6779 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
6780 ARRAY_SIZE (mips16e_s2_s8_regs), &gp_reg_size);
6781 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
6782 ARRAY_SIZE (mips16e_a0_a3_regs), &gp_reg_size);
6785 /* This loop must iterate over the same space as its companion in
6786 mips_for_each_saved_reg. */
6787 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6788 regno >= FP_REG_FIRST;
6789 regno -= MAX_FPRS_PER_FMT)
6791 if (mips_save_reg_p (regno))
6793 fp_reg_size += MAX_FPRS_PER_FMT * UNITS_PER_FPREG;
6794 fmask |= ((1 << MAX_FPRS_PER_FMT) - 1) << (regno - FP_REG_FIRST);
6798 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6799 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6801 /* Add in the space required for saving incoming register arguments. */
6802 total_size += current_function_pretend_args_size;
6803 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6805 /* Save other computed information. */
6806 cfun->machine->frame.total_size = total_size;
6807 cfun->machine->frame.var_size = var_size;
6808 cfun->machine->frame.args_size = args_size;
6809 cfun->machine->frame.cprestore_size = cprestore_size;
6810 cfun->machine->frame.gp_reg_size = gp_reg_size;
6811 cfun->machine->frame.fp_reg_size = fp_reg_size;
6812 cfun->machine->frame.mask = mask;
6813 cfun->machine->frame.fmask = fmask;
6814 cfun->machine->frame.initialized = reload_completed;
6815 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6816 cfun->machine->frame.num_fp = (fp_reg_size
6817 / (MAX_FPRS_PER_FMT * UNITS_PER_FPREG));
6821 HOST_WIDE_INT offset;
6823 if (GENERATE_MIPS16E_SAVE_RESTORE)
6824 /* MIPS16e SAVE and RESTORE instructions require the GP save area
6825 to be aligned at the high end with any padding at the low end.
6826 It is only safe to use this calculation for o32, where we never
6827 have pretend arguments, and where any varargs will be saved in
6828 the caller-allocated area rather than at the top of the frame. */
6829 offset = (total_size - GET_MODE_SIZE (gpr_mode));
6831 offset = (args_size + cprestore_size + var_size
6832 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6833 cfun->machine->frame.gp_sp_offset = offset;
6834 cfun->machine->frame.gp_save_offset = offset - total_size;
6838 cfun->machine->frame.gp_sp_offset = 0;
6839 cfun->machine->frame.gp_save_offset = 0;
6844 HOST_WIDE_INT offset;
6846 offset = (args_size + cprestore_size + var_size
6847 + gp_reg_rounded + fp_reg_size
6848 - MAX_FPRS_PER_FMT * UNITS_PER_FPREG);
6849 cfun->machine->frame.fp_sp_offset = offset;
6850 cfun->machine->frame.fp_save_offset = offset - total_size;
6854 cfun->machine->frame.fp_sp_offset = 0;
6855 cfun->machine->frame.fp_save_offset = 0;
6858 /* Ok, we're done. */
6862 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6863 pointer or argument pointer. TO is either the stack pointer or
6864 hard frame pointer. */
6867 mips_initial_elimination_offset (int from, int to)
6869 HOST_WIDE_INT offset;
6871 compute_frame_size (get_frame_size ());
6873 /* Set OFFSET to the offset from the stack pointer. */
6876 case FRAME_POINTER_REGNUM:
6880 case ARG_POINTER_REGNUM:
6881 offset = (cfun->machine->frame.total_size
6882 - current_function_pretend_args_size);
6889 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6890 offset -= cfun->machine->frame.args_size;
6895 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6896 back to a previous frame. */
6898 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6903 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6906 /* Use FN to save or restore register REGNO. MODE is the register's
6907 mode and OFFSET is the offset of its save slot from the current
6911 mips_save_restore_reg (enum machine_mode mode, int regno,
6912 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6916 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6918 fn (gen_rtx_REG (mode, regno), mem);
6922 /* Call FN for each register that is saved by the current function.
6923 SP_OFFSET is the offset of the current stack pointer from the start
6927 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6929 enum machine_mode fpr_mode;
6930 HOST_WIDE_INT offset;
6933 /* Save registers starting from high to low. The debuggers prefer at least
6934 the return register be stored at func+4, and also it allows us not to
6935 need a nop in the epilogue if at least one register is reloaded in
6936 addition to return address. */
6937 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6938 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6939 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6941 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6942 offset -= GET_MODE_SIZE (gpr_mode);
6945 /* This loop must iterate over the same space as its companion in
6946 compute_frame_size. */
6947 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6948 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6949 for (regno = (FP_REG_LAST - MAX_FPRS_PER_FMT + 1);
6950 regno >= FP_REG_FIRST;
6951 regno -= MAX_FPRS_PER_FMT)
6952 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6954 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6955 offset -= GET_MODE_SIZE (fpr_mode);
6959 /* If we're generating n32 or n64 abicalls, and the current function
6960 does not use $28 as its global pointer, emit a cplocal directive.
6961 Use pic_offset_table_rtx as the argument to the directive. */
6964 mips_output_cplocal (void)
6966 if (!TARGET_EXPLICIT_RELOCS
6967 && cfun->machine->global_pointer > 0
6968 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6969 output_asm_insn (".cplocal %+", 0);
6972 /* Return the style of GP load sequence that is being used for the
6973 current function. */
6975 enum mips_loadgp_style
6976 mips_current_loadgp_style (void)
6978 if (!TARGET_USE_GOT || cfun->machine->global_pointer == 0)
6984 if (TARGET_ABSOLUTE_ABICALLS)
6985 return LOADGP_ABSOLUTE;
6987 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6990 /* The __gnu_local_gp symbol. */
6992 static GTY(()) rtx mips_gnu_local_gp;
6994 /* If we're generating n32 or n64 abicalls, emit instructions
6995 to set up the global pointer. */
6998 mips_emit_loadgp (void)
7000 rtx addr, offset, incoming_address, base, index;
7002 switch (mips_current_loadgp_style ())
7004 case LOADGP_ABSOLUTE:
7005 if (mips_gnu_local_gp == NULL)
7007 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
7008 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
7010 emit_insn (gen_loadgp_absolute (mips_gnu_local_gp));
7014 addr = XEXP (DECL_RTL (current_function_decl), 0);
7015 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
7016 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7017 emit_insn (gen_loadgp_newabi (offset, incoming_address));
7018 if (!TARGET_EXPLICIT_RELOCS)
7019 emit_insn (gen_loadgp_blockage ());
7023 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
7024 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
7025 emit_insn (gen_loadgp_rtp (base, index));
7026 if (!TARGET_EXPLICIT_RELOCS)
7027 emit_insn (gen_loadgp_blockage ());
7035 /* Set up the stack and frame (if desired) for the function. */
7038 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7041 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7043 #ifdef SDB_DEBUGGING_INFO
7044 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7045 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7048 /* In mips16 mode, we may need to generate a 32 bit to handle
7049 floating point arguments. The linker will arrange for any 32-bit
7050 functions to call this stub, which will then jump to the 16-bit
7052 if (mips16_hard_float
7053 && current_function_args_info.fp_code != 0)
7054 build_mips16_function_stub (file);
7056 if (!FUNCTION_NAME_ALREADY_DECLARED)
7058 /* Get the function name the same way that toplev.c does before calling
7059 assemble_start_function. This is needed so that the name used here
7060 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7061 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7063 if (!flag_inhibit_size_directive)
7065 fputs ("\t.ent\t", file);
7066 assemble_name (file, fnname);
7070 assemble_name (file, fnname);
7071 fputs (":\n", file);
7074 /* Stop mips_file_end from treating this function as external. */
7075 if (TARGET_IRIX && mips_abi == ABI_32)
7076 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
7078 if (!flag_inhibit_size_directive)
7080 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7082 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
7083 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
7084 ", args= " HOST_WIDE_INT_PRINT_DEC
7085 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
7086 (reg_names[(frame_pointer_needed)
7087 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7088 ((frame_pointer_needed && TARGET_MIPS16)
7089 ? tsize - cfun->machine->frame.args_size
7091 reg_names[GP_REG_FIRST + 31],
7092 cfun->machine->frame.var_size,
7093 cfun->machine->frame.num_gp,
7094 cfun->machine->frame.num_fp,
7095 cfun->machine->frame.args_size,
7096 cfun->machine->frame.cprestore_size);
7098 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7099 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7100 cfun->machine->frame.mask,
7101 cfun->machine->frame.gp_save_offset);
7102 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
7103 cfun->machine->frame.fmask,
7104 cfun->machine->frame.fp_save_offset);
7107 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7108 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7111 if (mips_current_loadgp_style () == LOADGP_OLDABI)
7113 /* Handle the initialization of $gp for SVR4 PIC. */
7114 if (!cfun->machine->all_noreorder_p)
7115 output_asm_insn ("%(.cpload\t%^%)", 0);
7117 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
7119 else if (cfun->machine->all_noreorder_p)
7120 output_asm_insn ("%(%<", 0);
7122 /* Tell the assembler which register we're using as the global
7123 pointer. This is needed for thunks, since they can use either
7124 explicit relocs or assembler macros. */
7125 mips_output_cplocal ();
7128 /* Make the last instruction frame related and note that it performs
7129 the operation described by FRAME_PATTERN. */
7132 mips_set_frame_expr (rtx frame_pattern)
7136 insn = get_last_insn ();
7137 RTX_FRAME_RELATED_P (insn) = 1;
7138 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7144 /* Return a frame-related rtx that stores REG at MEM.
7145 REG must be a single register. */
7148 mips_frame_set (rtx mem, rtx reg)
7152 /* If we're saving the return address register and the dwarf return
7153 address column differs from the hard register number, adjust the
7154 note reg to refer to the former. */
7155 if (REGNO (reg) == GP_REG_FIRST + 31
7156 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7157 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7159 set = gen_rtx_SET (VOIDmode, mem, reg);
7160 RTX_FRAME_RELATED_P (set) = 1;
7166 /* Save register REG to MEM. Make the instruction frame-related. */
7169 mips_save_reg (rtx reg, rtx mem)
7171 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
7175 if (mips_split_64bit_move_p (mem, reg))
7176 mips_split_64bit_move (mem, reg);
7178 emit_move_insn (mem, reg);
7180 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
7181 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
7182 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
7187 && REGNO (reg) != GP_REG_FIRST + 31
7188 && !M16_REG_P (REGNO (reg)))
7190 /* Save a non-mips16 register by moving it through a temporary.
7191 We don't need to do this for $31 since there's a special
7192 instruction for it. */
7193 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
7194 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
7197 emit_move_insn (mem, reg);
7199 mips_set_frame_expr (mips_frame_set (mem, reg));
7203 /* Return a move between register REGNO and memory location SP + OFFSET.
7204 Make the move a load if RESTORE_P, otherwise make it a frame-related
7208 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
7213 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
7214 reg = gen_rtx_REG (SImode, regno);
7216 ? gen_rtx_SET (VOIDmode, reg, mem)
7217 : mips_frame_set (mem, reg));
7220 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
7221 The instruction must:
7223 - Allocate or deallocate SIZE bytes in total; SIZE is known
7226 - Save or restore as many registers in *MASK_PTR as possible.
7227 The instruction saves the first registers at the top of the
7228 allocated area, with the other registers below it.
7230 - Save NARGS argument registers above the allocated area.
7232 (NARGS is always zero if RESTORE_P.)
7234 The SAVE and RESTORE instructions cannot save and restore all general
7235 registers, so there may be some registers left over for the caller to
7236 handle. Destructively modify *MASK_PTR so that it contains the registers
7237 that still need to be saved or restored. The caller can save these
7238 registers in the memory immediately below *OFFSET_PTR, which is a
7239 byte offset from the bottom of the allocated stack area. */
7242 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
7243 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
7247 HOST_WIDE_INT offset, top_offset;
7248 unsigned int i, regno;
7251 gcc_assert (cfun->machine->frame.fp_reg_size == 0);
7253 /* Calculate the number of elements in the PARALLEL. We need one element
7254 for the stack adjustment, one for each argument register save, and one
7255 for each additional register move. */
7257 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7258 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
7261 /* Create the final PARALLEL. */
7262 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
7265 /* Add the stack pointer adjustment. */
7266 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7267 plus_constant (stack_pointer_rtx,
7268 restore_p ? size : -size));
7269 RTX_FRAME_RELATED_P (set) = 1;
7270 XVECEXP (pattern, 0, n++) = set;
7272 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7273 top_offset = restore_p ? size : 0;
7275 /* Save the arguments. */
7276 for (i = 0; i < nargs; i++)
7278 offset = top_offset + i * GET_MODE_SIZE (gpr_mode);
7279 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
7280 XVECEXP (pattern, 0, n++) = set;
7283 /* Then fill in the other register moves. */
7284 offset = top_offset;
7285 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
7287 regno = mips16e_save_restore_regs[i];
7288 if (BITSET_P (*mask_ptr, regno))
7290 offset -= UNITS_PER_WORD;
7291 set = mips16e_save_restore_reg (restore_p, offset, regno);
7292 XVECEXP (pattern, 0, n++) = set;
7293 *mask_ptr &= ~(1 << regno);
7297 /* Tell the caller what offset it should use for the remaining registers. */
7298 *offset_ptr = size + (offset - top_offset) + size;
7300 gcc_assert (n == XVECLEN (pattern, 0));
7305 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
7306 pointer. Return true if PATTERN matches the kind of instruction
7307 generated by mips16e_build_save_restore. If INFO is nonnull,
7308 initialize it when returning true. */
7311 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
7312 struct mips16e_save_restore_info *info)
7314 unsigned int i, nargs, mask;
7315 HOST_WIDE_INT top_offset, save_offset, offset, extra;
7316 rtx set, reg, mem, base;
7319 if (!GENERATE_MIPS16E_SAVE_RESTORE)
7322 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
7323 top_offset = adjust > 0 ? adjust : 0;
7325 /* Interpret all other members of the PARALLEL. */
7326 save_offset = top_offset - GET_MODE_SIZE (gpr_mode);
7330 for (n = 1; n < XVECLEN (pattern, 0); n++)
7332 /* Check that we have a SET. */
7333 set = XVECEXP (pattern, 0, n);
7334 if (GET_CODE (set) != SET)
7337 /* Check that the SET is a load (if restoring) or a store
7339 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
7343 /* Check that the address is the sum of the stack pointer and a
7344 possibly-zero constant offset. */
7345 mips_split_plus (XEXP (mem, 0), &base, &offset);
7346 if (base != stack_pointer_rtx)
7349 /* Check that SET's other operand is a register. */
7350 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
7354 /* Check for argument saves. */
7355 if (offset == top_offset + nargs * GET_MODE_SIZE (gpr_mode)
7356 && REGNO (reg) == GP_ARG_FIRST + nargs)
7358 else if (offset == save_offset)
7360 while (mips16e_save_restore_regs[i++] != REGNO (reg))
7361 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
7364 mask |= 1 << REGNO (reg);
7365 save_offset -= GET_MODE_SIZE (gpr_mode);
7371 /* Check that the restrictions on register ranges are met. */
7373 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
7374 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
7375 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
7376 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
7380 /* Make sure that the topmost argument register is not saved twice.
7381 The checks above ensure that the same is then true for the other
7382 argument registers. */
7383 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
7386 /* Pass back information, if requested. */
7389 info->nargs = nargs;
7391 info->size = (adjust > 0 ? adjust : -adjust);
7397 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
7398 for the register range [MIN_REG, MAX_REG]. Return a pointer to
7399 the null terminator. */
7402 mips16e_add_register_range (char *s, unsigned int min_reg,
7403 unsigned int max_reg)
7405 if (min_reg != max_reg)
7406 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
7408 s += sprintf (s, ",%s", reg_names[min_reg]);
7412 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
7413 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
7416 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
7418 static char buffer[300];
7420 struct mips16e_save_restore_info info;
7421 unsigned int i, end;
7424 /* Parse the pattern. */
7425 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
7428 /* Add the mnemonic. */
7429 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
7432 /* Save the arguments. */
7434 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
7435 reg_names[GP_ARG_FIRST + info.nargs - 1]);
7436 else if (info.nargs == 1)
7437 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
7439 /* Emit the amount of stack space to allocate or deallocate. */
7440 s += sprintf (s, "%d", (int) info.size);
7442 /* Save or restore $16. */
7443 if (BITSET_P (info.mask, 16))
7444 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
7446 /* Save or restore $17. */
7447 if (BITSET_P (info.mask, 17))
7448 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
7450 /* Save or restore registers in the range $s2...$s8, which
7451 mips16e_s2_s8_regs lists in decreasing order. Note that this
7452 is a software register range; the hardware registers are not
7453 numbered consecutively. */
7454 end = ARRAY_SIZE (mips16e_s2_s8_regs);
7455 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
7457 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
7458 mips16e_s2_s8_regs[i]);
7460 /* Save or restore registers in the range $a0...$a3. */
7461 end = ARRAY_SIZE (mips16e_a0_a3_regs);
7462 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
7464 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
7465 mips16e_a0_a3_regs[end - 1]);
7467 /* Save or restore $31. */
7468 if (BITSET_P (info.mask, 31))
7469 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
7474 /* Return a simplified form of X using the register values in REG_VALUES.
7475 REG_VALUES[R] is the last value assigned to hard register R, or null
7476 if R has not been modified.
7478 This function is rather limited, but is good enough for our purposes. */
7481 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
7485 x = avoid_constant_pool_reference (x);
7489 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7490 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
7491 x0, GET_MODE (XEXP (x, 0)));
7494 if (ARITHMETIC_P (x))
7496 x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
7497 x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
7498 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
7502 && reg_values[REGNO (x)]
7503 && !rtx_unstable_p (reg_values[REGNO (x)]))
7504 return reg_values[REGNO (x)];
7509 /* Return true if (set DEST SRC) stores an argument register into its
7510 caller-allocated save slot, storing the number of that argument
7511 register in *REGNO_PTR if so. REG_VALUES is as for
7512 mips16e_collect_propagate_value. */
7515 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
7516 unsigned int *regno_ptr)
7518 unsigned int argno, regno;
7519 HOST_WIDE_INT offset, required_offset;
7522 /* Check that this is a word-mode store. */
7523 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
7526 /* Check that the register being saved is an unmodified argument
7528 regno = REGNO (src);
7529 if (regno < GP_ARG_FIRST || regno > GP_ARG_LAST || reg_values[regno])
7531 argno = regno - GP_ARG_FIRST;
7533 /* Check whether the address is an appropriate stack pointer or
7534 frame pointer access. The frame pointer is offset from the
7535 stack pointer by the size of the outgoing arguments. */
7536 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
7537 mips_split_plus (addr, &base, &offset);
7538 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
7539 if (base == hard_frame_pointer_rtx)
7540 required_offset -= cfun->machine->frame.args_size;
7541 else if (base != stack_pointer_rtx)
7543 if (offset != required_offset)
7550 /* A subroutine of mips_expand_prologue, called only when generating
7551 MIPS16e SAVE instructions. Search the start of the function for any
7552 instructions that save argument registers into their caller-allocated
7553 save slots. Delete such instructions and return a value N such that
7554 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
7555 instructions redundant. */
7558 mips16e_collect_argument_saves (void)
7560 rtx reg_values[FIRST_PSEUDO_REGISTER];
7561 rtx insn, next, set, dest, src;
7562 unsigned int nargs, regno;
7564 push_topmost_sequence ();
7566 memset (reg_values, 0, sizeof (reg_values));
7567 for (insn = get_insns (); insn; insn = next)
7569 next = NEXT_INSN (insn);
7576 set = PATTERN (insn);
7577 if (GET_CODE (set) != SET)
7580 dest = SET_DEST (set);
7581 src = SET_SRC (set);
7582 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
7584 if (!BITSET_P (cfun->machine->frame.mask, regno))
7587 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
7590 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
7591 reg_values[REGNO (dest)]
7592 = mips16e_collect_propagate_value (src, reg_values);
7596 pop_topmost_sequence ();
7601 /* Expand the prologue into a bunch of separate insns. */
7604 mips_expand_prologue (void)
7610 if (cfun->machine->global_pointer > 0)
7611 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
7613 size = compute_frame_size (get_frame_size ());
7615 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
7616 bytes beforehand; this is enough to cover the register save area
7617 without going out of range. */
7618 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7620 HOST_WIDE_INT step1;
7622 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
7624 if (GENERATE_MIPS16E_SAVE_RESTORE)
7626 HOST_WIDE_INT offset;
7627 unsigned int mask, regno;
7629 /* Try to merge argument stores into the save instruction. */
7630 nargs = mips16e_collect_argument_saves ();
7632 /* Build the save instruction. */
7633 mask = cfun->machine->frame.mask;
7634 insn = mips16e_build_save_restore (false, &mask, &offset,
7636 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7639 /* Check if we need to save other registers. */
7640 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7641 if (BITSET_P (mask, regno - GP_REG_FIRST))
7643 offset -= GET_MODE_SIZE (gpr_mode);
7644 mips_save_restore_reg (gpr_mode, regno, offset, mips_save_reg);
7649 insn = gen_add3_insn (stack_pointer_rtx,
7652 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
7654 mips_for_each_saved_reg (size, mips_save_reg);
7658 /* Allocate the rest of the frame. */
7661 if (SMALL_OPERAND (-size))
7662 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
7664 GEN_INT (-size)))) = 1;
7667 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
7670 /* There are no instructions to add or subtract registers
7671 from the stack pointer, so use the frame pointer as a
7672 temporary. We should always be using a frame pointer
7673 in this case anyway. */
7674 gcc_assert (frame_pointer_needed);
7675 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7676 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
7677 hard_frame_pointer_rtx,
7678 MIPS_PROLOGUE_TEMP (Pmode)));
7679 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7682 emit_insn (gen_sub3_insn (stack_pointer_rtx,
7684 MIPS_PROLOGUE_TEMP (Pmode)));
7686 /* Describe the combined effect of the previous instructions. */
7688 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7689 plus_constant (stack_pointer_rtx, -size)));
7693 /* Set up the frame pointer, if we're using one. In mips16 code,
7694 we point the frame pointer ahead of the outgoing argument area.
7695 This should allow more variables & incoming arguments to be
7696 accessed with unextended instructions. */
7697 if (frame_pointer_needed)
7699 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
7701 rtx offset = GEN_INT (cfun->machine->frame.args_size);
7702 if (SMALL_OPERAND (cfun->machine->frame.args_size))
7704 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7709 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
7710 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7711 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
7712 hard_frame_pointer_rtx,
7713 MIPS_PROLOGUE_TEMP (Pmode)));
7715 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
7716 plus_constant (stack_pointer_rtx,
7717 cfun->machine->frame.args_size)));
7721 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
7722 stack_pointer_rtx)) = 1;
7725 mips_emit_loadgp ();
7727 /* If generating o32/o64 abicalls, save $gp on the stack. */
7728 if (TARGET_ABICALLS && TARGET_OLDABI && !current_function_is_leaf)
7729 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
7731 /* If we are profiling, make sure no instructions are scheduled before
7732 the call to mcount. */
7734 if (current_function_profile)
7735 emit_insn (gen_blockage ());
7738 /* Do any necessary cleanup after a function to restore stack, frame,
7741 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7744 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
7745 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
7747 /* Reinstate the normal $gp. */
7748 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
7749 mips_output_cplocal ();
7751 if (cfun->machine->all_noreorder_p)
7753 /* Avoid using %>%) since it adds excess whitespace. */
7754 output_asm_insn (".set\tmacro", 0);
7755 output_asm_insn (".set\treorder", 0);
7756 set_noreorder = set_nomacro = 0;
7759 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
7763 /* Get the function name the same way that toplev.c does before calling
7764 assemble_start_function. This is needed so that the name used here
7765 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7766 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7767 fputs ("\t.end\t", file);
7768 assemble_name (file, fnname);
7773 /* Emit instructions to restore register REG from slot MEM. */
7776 mips_restore_reg (rtx reg, rtx mem)
7778 /* There's no mips16 instruction to load $31 directly. Load into
7779 $7 instead and adjust the return insn appropriately. */
7780 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
7781 reg = gen_rtx_REG (GET_MODE (reg), 7);
7783 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
7785 /* Can't restore directly; move through a temporary. */
7786 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
7787 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
7790 emit_move_insn (reg, mem);
7794 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
7795 if this epilogue precedes a sibling call, false if it is for a normal
7796 "epilogue" pattern. */
7799 mips_expand_epilogue (int sibcall_p)
7801 HOST_WIDE_INT step1, step2;
7804 if (!sibcall_p && mips_can_use_return_insn ())
7806 emit_jump_insn (gen_return ());
7810 /* In mips16 mode, if the return value should go into a floating-point
7811 register, we need to call a helper routine to copy it over. */
7812 if (mips16_cfun_returns_in_fpr_p ())
7821 enum machine_mode return_mode;
7823 return_type = DECL_RESULT (current_function_decl);
7824 return_mode = DECL_MODE (return_type);
7826 name = ACONCAT (("__mips16_ret_",
7827 mips16_call_stub_mode_suffix (return_mode),
7829 id = get_identifier (name);
7830 func = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7831 retval = gen_rtx_REG (return_mode, GP_RETURN);
7832 call = gen_call_value_internal (retval, func, const0_rtx);
7833 insn = emit_call_insn (call);
7834 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
7837 /* Split the frame into two. STEP1 is the amount of stack we should
7838 deallocate before restoring the registers. STEP2 is the amount we
7839 should deallocate afterwards.
7841 Start off by assuming that no registers need to be restored. */
7842 step1 = cfun->machine->frame.total_size;
7845 /* Work out which register holds the frame address. Account for the
7846 frame pointer offset used by mips16 code. */
7847 if (!frame_pointer_needed)
7848 base = stack_pointer_rtx;
7851 base = hard_frame_pointer_rtx;
7853 step1 -= cfun->machine->frame.args_size;
7856 /* If we need to restore registers, deallocate as much stack as
7857 possible in the second step without going out of range. */
7858 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7860 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7864 /* Set TARGET to BASE + STEP1. */
7870 /* Get an rtx for STEP1 that we can add to BASE. */
7871 adjust = GEN_INT (step1);
7872 if (!SMALL_OPERAND (step1))
7874 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7875 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7878 /* Normal mode code can copy the result straight into $sp. */
7880 target = stack_pointer_rtx;
7882 emit_insn (gen_add3_insn (target, base, adjust));
7885 /* Copy TARGET into the stack pointer. */
7886 if (target != stack_pointer_rtx)
7887 emit_move_insn (stack_pointer_rtx, target);
7889 /* If we're using addressing macros, $gp is implicitly used by all
7890 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
7892 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
7893 emit_insn (gen_blockage ());
7895 if (GENERATE_MIPS16E_SAVE_RESTORE && cfun->machine->frame.mask != 0)
7897 unsigned int regno, mask;
7898 HOST_WIDE_INT offset;
7901 /* Generate the restore instruction. */
7902 mask = cfun->machine->frame.mask;
7903 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
7905 /* Restore any other registers manually. */
7906 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
7907 if (BITSET_P (mask, regno - GP_REG_FIRST))
7909 offset -= GET_MODE_SIZE (gpr_mode);
7910 mips_save_restore_reg (gpr_mode, regno, offset, mips_restore_reg);
7913 /* Restore the remaining registers and deallocate the final bit
7915 emit_insn (restore);
7919 /* Restore the registers. */
7920 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7923 /* Deallocate the final bit of the frame. */
7925 emit_insn (gen_add3_insn (stack_pointer_rtx,
7930 /* Add in the __builtin_eh_return stack adjustment. We need to
7931 use a temporary in mips16 code. */
7932 if (current_function_calls_eh_return)
7936 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7937 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7938 MIPS_EPILOGUE_TEMP (Pmode),
7939 EH_RETURN_STACKADJ_RTX));
7940 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7943 emit_insn (gen_add3_insn (stack_pointer_rtx,
7945 EH_RETURN_STACKADJ_RTX));
7950 /* When generating MIPS16 code, the normal mips_for_each_saved_reg
7951 path will restore the return address into $7 rather than $31. */
7953 && !GENERATE_MIPS16E_SAVE_RESTORE
7954 && (cfun->machine->frame.mask & RA_MASK) != 0)
7955 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7956 GP_REG_FIRST + 7)));
7958 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7959 GP_REG_FIRST + 31)));
7963 /* Return nonzero if this function is known to have a null epilogue.
7964 This allows the optimizer to omit jumps to jumps if no stack
7968 mips_can_use_return_insn (void)
7970 if (! reload_completed)
7973 if (df_regs_ever_live_p (31) || current_function_profile)
7976 /* In mips16 mode, a function that returns a floating point value
7977 needs to arrange to copy the return value into the floating point
7979 if (mips16_cfun_returns_in_fpr_p ())
7982 if (cfun->machine->frame.initialized)
7983 return cfun->machine->frame.total_size == 0;
7985 return compute_frame_size (get_frame_size ()) == 0;
7988 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7989 in order to avoid duplicating too much logic from elsewhere. */
7992 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7993 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7996 rtx this, temp1, temp2, insn, fnaddr;
7998 /* Pretend to be a post-reload pass while generating rtl. */
7999 reload_completed = 1;
8001 /* Mark the end of the (empty) prologue. */
8002 emit_note (NOTE_INSN_PROLOGUE_END);
8004 /* Pick a global pointer. Use a call-clobbered register if
8005 TARGET_CALL_SAVED_GP, so that we can use a sibcall. */
8008 cfun->machine->global_pointer =
8009 TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
8011 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
8015 /* Set up the global pointer for n32 or n64 abicalls. If
8016 LOADGP_ABSOLUTE then the thunk does not use the gp and there is
8017 no need to load it.*/
8018 if (mips_current_loadgp_style () != LOADGP_ABSOLUTE
8019 || !targetm.binds_local_p (function))
8020 mips_emit_loadgp ();
8022 /* We need two temporary registers in some cases. */
8023 temp1 = gen_rtx_REG (Pmode, 2);
8024 temp2 = gen_rtx_REG (Pmode, 3);
8026 /* Find out which register contains the "this" pointer. */
8027 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8028 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
8030 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
8032 /* Add DELTA to THIS. */
8035 rtx offset = GEN_INT (delta);
8036 if (!SMALL_OPERAND (delta))
8038 emit_move_insn (temp1, offset);
8041 emit_insn (gen_add3_insn (this, this, offset));
8044 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
8045 if (vcall_offset != 0)
8049 /* Set TEMP1 to *THIS. */
8050 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
8052 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
8053 addr = mips_add_offset (temp2, temp1, vcall_offset);
8055 /* Load the offset and add it to THIS. */
8056 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
8057 emit_insn (gen_add3_insn (this, this, temp1));
8060 /* Jump to the target function. Use a sibcall if direct jumps are
8061 allowed, otherwise load the address into a register first. */
8062 fnaddr = XEXP (DECL_RTL (function), 0);
8063 if (TARGET_MIPS16 || TARGET_USE_GOT || SYMBOL_REF_LONG_CALL_P (fnaddr))
8065 /* This is messy. gas treats "la $25,foo" as part of a call
8066 sequence and may allow a global "foo" to be lazily bound.
8067 The general move patterns therefore reject this combination.
8069 In this context, lazy binding would actually be OK
8070 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
8071 TARGET_CALL_SAVED_GP; see mips_load_call_address.
8072 We must therefore load the address via a temporary
8073 register if mips_dangerous_for_la25_p.
8075 If we jump to the temporary register rather than $25, the assembler
8076 can use the move insn to fill the jump's delay slot. */
8077 if (TARGET_USE_PIC_FN_ADDR_REG
8078 && !mips_dangerous_for_la25_p (fnaddr))
8079 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
8080 mips_load_call_address (temp1, fnaddr, true);
8082 if (TARGET_USE_PIC_FN_ADDR_REG
8083 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
8084 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
8085 emit_jump_insn (gen_indirect_jump (temp1));
8089 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
8090 SIBLING_CALL_P (insn) = 1;
8093 /* Run just enough of rest_of_compilation. This sequence was
8094 "borrowed" from alpha.c. */
8095 insn = get_insns ();
8096 insn_locators_alloc ();
8097 split_all_insns_noflow ();
8099 mips16_lay_out_constants ();
8100 shorten_branches (insn);
8101 final_start_function (insn, file, 1);
8102 final (insn, file, 1);
8103 final_end_function ();
8105 /* Clean up the vars set above. Note that final_end_function resets
8106 the global pointer for us. */
8107 reload_completed = 0;
8110 /* Returns nonzero if X contains a SYMBOL_REF. */
8113 symbolic_expression_p (rtx x)
8115 if (GET_CODE (x) == SYMBOL_REF)
8118 if (GET_CODE (x) == CONST)
8119 return symbolic_expression_p (XEXP (x, 0));
8122 return symbolic_expression_p (XEXP (x, 0));
8124 if (ARITHMETIC_P (x))
8125 return (symbolic_expression_p (XEXP (x, 0))
8126 || symbolic_expression_p (XEXP (x, 1)));
8131 /* Choose the section to use for the constant rtx expression X that has
8135 mips_select_rtx_section (enum machine_mode mode, rtx x,
8136 unsigned HOST_WIDE_INT align)
8140 /* In mips16 mode, the constant table always goes in the same section
8141 as the function, so that constants can be loaded using PC relative
8143 return function_section (current_function_decl);
8145 else if (TARGET_EMBEDDED_DATA)
8147 /* For embedded applications, always put constants in read-only data,
8148 in order to reduce RAM usage. */
8149 return mergeable_constant_section (mode, align, 0);
8153 /* For hosted applications, always put constants in small data if
8154 possible, as this gives the best performance. */
8155 /* ??? Consider using mergeable small data sections. */
8157 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
8158 && mips_section_threshold > 0)
8159 return get_named_section (NULL, ".sdata", 0);
8160 else if (flag_pic && symbolic_expression_p (x))
8161 return get_named_section (NULL, ".data.rel.ro", 3);
8163 return mergeable_constant_section (mode, align, 0);
8167 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8169 The complication here is that, with the combination TARGET_ABICALLS
8170 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
8171 therefore not be included in the read-only part of a DSO. Handle such
8172 cases by selecting a normal data section instead of a read-only one.
8173 The logic apes that in default_function_rodata_section. */
8176 mips_function_rodata_section (tree decl)
8178 if (!TARGET_ABICALLS || TARGET_GPWORD)
8179 return default_function_rodata_section (decl);
8181 if (decl && DECL_SECTION_NAME (decl))
8183 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8184 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8186 char *rname = ASTRDUP (name);
8188 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8190 else if (flag_function_sections && flag_data_sections
8191 && strncmp (name, ".text.", 6) == 0)
8193 char *rname = ASTRDUP (name);
8194 memcpy (rname + 1, "data", 4);
8195 return get_section (rname, SECTION_WRITE, decl);
8198 return data_section;
8201 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
8202 locally-defined objects go in a small data section. It also controls
8203 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
8204 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
8207 mips_in_small_data_p (tree decl)
8211 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8214 /* We don't yet generate small-data references for -mabicalls or
8215 VxWorks RTP code. See the related -G handling in override_options. */
8216 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8219 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8223 /* Reject anything that isn't in a known small-data section. */
8224 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8225 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8228 /* If a symbol is defined externally, the assembler will use the
8229 usual -G rules when deciding how to implement macros. */
8230 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
8233 else if (TARGET_EMBEDDED_DATA)
8235 /* Don't put constants into the small data section: we want them
8236 to be in ROM rather than RAM. */
8237 if (TREE_CODE (decl) != VAR_DECL)
8240 if (TREE_READONLY (decl)
8241 && !TREE_SIDE_EFFECTS (decl)
8242 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8246 size = int_size_in_bytes (TREE_TYPE (decl));
8247 return (size > 0 && size <= mips_section_threshold);
8250 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8251 anchors for small data: the GP register acts as an anchor in that
8252 case. We also don't want to use them for PC-relative accesses,
8253 where the PC acts as an anchor. */
8256 mips_use_anchors_for_symbol_p (rtx symbol)
8258 switch (mips_classify_symbol (symbol))
8260 case SYMBOL_CONSTANT_POOL:
8261 case SYMBOL_SMALL_DATA:
8269 /* See whether VALTYPE is a record whose fields should be returned in
8270 floating-point registers. If so, return the number of fields and
8271 list them in FIELDS (which should have two elements). Return 0
8274 For n32 & n64, a structure with one or two fields is returned in
8275 floating-point registers as long as every field has a floating-point
8279 mips_fpr_return_fields (tree valtype, tree *fields)
8287 if (TREE_CODE (valtype) != RECORD_TYPE)
8291 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
8293 if (TREE_CODE (field) != FIELD_DECL)
8296 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
8302 fields[i++] = field;
8308 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
8309 a value in the most significant part of $2/$3 if:
8311 - the target is big-endian;
8313 - the value has a structure or union type (we generalize this to
8314 cover aggregates from other languages too); and
8316 - the structure is not returned in floating-point registers. */
8319 mips_return_in_msb (tree valtype)
8323 return (TARGET_NEWABI
8324 && TARGET_BIG_ENDIAN
8325 && AGGREGATE_TYPE_P (valtype)
8326 && mips_fpr_return_fields (valtype, fields) == 0);
8330 /* Return a composite value in a pair of floating-point registers.
8331 MODE1 and OFFSET1 are the mode and byte offset for the first value,
8332 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
8335 For n32 & n64, $f0 always holds the first value and $f2 the second.
8336 Otherwise the values are packed together as closely as possible. */
8339 mips_return_fpr_pair (enum machine_mode mode,
8340 enum machine_mode mode1, HOST_WIDE_INT offset1,
8341 enum machine_mode mode2, HOST_WIDE_INT offset2)
8345 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
8346 return gen_rtx_PARALLEL
8349 gen_rtx_EXPR_LIST (VOIDmode,
8350 gen_rtx_REG (mode1, FP_RETURN),
8352 gen_rtx_EXPR_LIST (VOIDmode,
8353 gen_rtx_REG (mode2, FP_RETURN + inc),
8354 GEN_INT (offset2))));
8359 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
8360 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
8361 VALTYPE is null and MODE is the mode of the return value. */
8364 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
8365 enum machine_mode mode)
8372 mode = TYPE_MODE (valtype);
8373 unsignedp = TYPE_UNSIGNED (valtype);
8375 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
8376 true, we must promote the mode just as PROMOTE_MODE does. */
8377 mode = promote_mode (valtype, mode, &unsignedp, 1);
8379 /* Handle structures whose fields are returned in $f0/$f2. */
8380 switch (mips_fpr_return_fields (valtype, fields))
8383 return gen_rtx_REG (mode, FP_RETURN);
8386 return mips_return_fpr_pair (mode,
8387 TYPE_MODE (TREE_TYPE (fields[0])),
8388 int_byte_position (fields[0]),
8389 TYPE_MODE (TREE_TYPE (fields[1])),
8390 int_byte_position (fields[1]));
8393 /* If a value is passed in the most significant part of a register, see
8394 whether we have to round the mode up to a whole number of words. */
8395 if (mips_return_in_msb (valtype))
8397 HOST_WIDE_INT size = int_size_in_bytes (valtype);
8398 if (size % UNITS_PER_WORD != 0)
8400 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
8401 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
8405 /* For EABI, the class of return register depends entirely on MODE.
8406 For example, "struct { some_type x; }" and "union { some_type x; }"
8407 are returned in the same way as a bare "some_type" would be.
8408 Other ABIs only use FPRs for scalar, complex or vector types. */
8409 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
8410 return gen_rtx_REG (mode, GP_RETURN);
8415 /* Handle long doubles for n32 & n64. */
8417 return mips_return_fpr_pair (mode,
8419 DImode, GET_MODE_SIZE (mode) / 2);
8421 if (mips_return_mode_in_fpr_p (mode))
8423 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8424 return mips_return_fpr_pair (mode,
8425 GET_MODE_INNER (mode), 0,
8426 GET_MODE_INNER (mode),
8427 GET_MODE_SIZE (mode) / 2);
8429 return gen_rtx_REG (mode, FP_RETURN);
8433 return gen_rtx_REG (mode, GP_RETURN);
8436 /* Return nonzero when an argument must be passed by reference. */
8439 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8440 enum machine_mode mode, tree type,
8441 bool named ATTRIBUTE_UNUSED)
8443 if (mips_abi == ABI_EABI)
8447 /* ??? How should SCmode be handled? */
8448 if (mode == DImode || mode == DFmode)
8451 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
8452 return size == -1 || size > UNITS_PER_WORD;
8456 /* If we have a variable-sized parameter, we have no choice. */
8457 return targetm.calls.must_pass_in_stack (mode, type);
8462 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
8463 enum machine_mode mode ATTRIBUTE_UNUSED,
8464 tree type ATTRIBUTE_UNUSED, bool named)
8466 return mips_abi == ABI_EABI && named;
8469 /* Return true if registers of class CLASS cannot change from mode FROM
8473 mips_cannot_change_mode_class (enum machine_mode from,
8474 enum machine_mode to, enum reg_class class)
8476 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
8477 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
8479 if (TARGET_BIG_ENDIAN)
8481 /* When a multi-word value is stored in paired floating-point
8482 registers, the first register always holds the low word.
8483 We therefore can't allow FPRs to change between single-word
8484 and multi-word modes. */
8485 if (MAX_FPRS_PER_FMT > 1 && reg_classes_intersect_p (FP_REGS, class))
8490 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
8491 in LO and HI, the high word always comes first. We therefore
8492 can't allow values stored in HI to change between single-word
8493 and multi-word modes.
8494 This rule applies to both the original HI/LO pair and the new
8495 DSP accumulators. */
8496 if (reg_classes_intersect_p (ACC_REGS, class))
8501 /* gcc assumes that each word of a multiword register can be accessed
8502 individually using SUBREGs. This is not true for floating-point
8503 registers if they are bigger than a word. */
8504 if (UNITS_PER_FPREG > UNITS_PER_WORD
8505 && GET_MODE_SIZE (from) > UNITS_PER_WORD
8506 && GET_MODE_SIZE (to) < UNITS_PER_FPREG
8507 && reg_classes_intersect_p (FP_REGS, class))
8510 /* Loading a 32-bit value into a 64-bit floating-point register
8511 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
8512 We can't allow 64-bit float registers to change from SImode to
8517 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
8518 && reg_classes_intersect_p (FP_REGS, class))
8524 /* Return true if X should not be moved directly into register $25.
8525 We need this because many versions of GAS will treat "la $25,foo" as
8526 part of a call sequence and so allow a global "foo" to be lazily bound. */
8529 mips_dangerous_for_la25_p (rtx x)
8531 return (!TARGET_EXPLICIT_RELOCS
8533 && GET_CODE (x) == SYMBOL_REF
8534 && mips_global_symbol_p (x));
8537 /* Implement PREFERRED_RELOAD_CLASS. */
8540 mips_preferred_reload_class (rtx x, enum reg_class class)
8542 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
8545 if (TARGET_HARD_FLOAT
8546 && FLOAT_MODE_P (GET_MODE (x))
8547 && reg_class_subset_p (FP_REGS, class))
8550 if (reg_class_subset_p (GR_REGS, class))
8553 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
8559 /* This function returns the register class required for a secondary
8560 register when copying between one of the registers in CLASS, and X,
8561 using MODE. If IN_P is nonzero, the copy is going from X to the
8562 register, otherwise the register is the source. A return value of
8563 NO_REGS means that no secondary register is required. */
8566 mips_secondary_reload_class (enum reg_class class,
8567 enum machine_mode mode, rtx x, int in_p)
8569 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8573 if (REG_P (x)|| GET_CODE (x) == SUBREG)
8574 regno = true_regnum (x);
8576 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8578 if (mips_dangerous_for_la25_p (x))
8581 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
8585 /* Copying from HI or LO to anywhere other than a general register
8586 requires a general register.
8587 This rule applies to both the original HI/LO pair and the new
8588 DSP accumulators. */
8589 if (reg_class_subset_p (class, ACC_REGS))
8591 if (TARGET_MIPS16 && in_p)
8593 /* We can't really copy to HI or LO at all in mips16 mode. */
8596 return gp_reg_p ? NO_REGS : gr_regs;
8598 if (ACC_REG_P (regno))
8600 if (TARGET_MIPS16 && ! in_p)
8602 /* We can't really copy to HI or LO at all in mips16 mode. */
8605 return class == gr_regs ? NO_REGS : gr_regs;
8608 /* We can only copy a value to a condition code register from a
8609 floating point register, and even then we require a scratch
8610 floating point register. We can only copy a value out of a
8611 condition code register into a general register. */
8612 if (class == ST_REGS)
8616 return gp_reg_p ? NO_REGS : gr_regs;
8618 if (ST_REG_P (regno))
8622 return class == gr_regs ? NO_REGS : gr_regs;
8625 if (class == FP_REGS)
8629 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8632 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8634 /* We can use the l.s and l.d macros to load floating-point
8635 constants. ??? For l.s, we could probably get better
8636 code by returning GR_REGS here. */
8639 else if (gp_reg_p || x == CONST0_RTX (mode))
8641 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8644 else if (FP_REG_P (regno))
8646 /* In this case we can use mov.s or mov.d. */
8651 /* Otherwise, we need to reload through an integer register. */
8656 /* In mips16 mode, going between memory and anything but M16_REGS
8657 requires an M16_REG. */
8660 if (class != M16_REGS && class != M16_NA_REGS)
8668 if (class == M16_REGS || class == M16_NA_REGS)
8677 /* Implement CLASS_MAX_NREGS.
8679 - UNITS_PER_FPREG controls the number of registers needed by FP_REGS.
8681 - ST_REGS are always hold CCmode values, and CCmode values are
8682 considered to be 4 bytes wide.
8684 All other register classes are covered by UNITS_PER_WORD. Note that
8685 this is true even for unions of integer and float registers when the
8686 latter are smaller than the former. The only supported combination
8687 in which case this occurs is -mgp64 -msingle-float, which has 64-bit
8688 words but 32-bit float registers. A word-based calculation is correct
8689 in that case since -msingle-float disallows multi-FPR values. */
8692 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
8693 enum machine_mode mode)
8695 if (class == ST_REGS)
8696 return (GET_MODE_SIZE (mode) + 3) / 4;
8697 else if (class == FP_REGS)
8698 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
8700 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8704 mips_valid_pointer_mode (enum machine_mode mode)
8706 return (mode == SImode || (TARGET_64BIT && mode == DImode));
8709 /* Target hook for vector_mode_supported_p. */
8712 mips_vector_mode_supported_p (enum machine_mode mode)
8717 return TARGET_PAIRED_SINGLE_FLOAT;
8728 /* If we can access small data directly (using gp-relative relocation
8729 operators) return the small data pointer, otherwise return null.
8731 For each mips16 function which refers to GP relative symbols, we
8732 use a pseudo register, initialized at the start of the function, to
8733 hold the $gp value. */
8736 mips16_gp_pseudo_reg (void)
8738 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8742 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8744 /* We want to initialize this to a value which gcc will believe
8746 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
8748 push_topmost_sequence ();
8749 /* We need to emit the initialization after the FUNCTION_BEG
8750 note, so that it will be integrated. */
8751 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8753 && NOTE_KIND (scan) == NOTE_INSN_FUNCTION_BEG)
8755 if (scan == NULL_RTX)
8756 scan = get_insns ();
8757 insn = emit_insn_after (insn, scan);
8758 pop_topmost_sequence ();
8761 return cfun->machine->mips16_gp_pseudo_rtx;
8764 /* Write out code to move floating point arguments in or out of
8765 general registers. Output the instructions to FILE. FP_CODE is
8766 the code describing which arguments are present (see the comment at
8767 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
8768 we are copying from the floating point registers. */
8771 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
8776 CUMULATIVE_ARGS cum;
8778 /* This code only works for the original 32-bit ABI and the O64 ABI. */
8779 gcc_assert (TARGET_OLDABI);
8786 init_cumulative_args (&cum, NULL, NULL);
8788 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8790 enum machine_mode mode;
8791 struct mips_arg_info info;
8795 else if ((f & 3) == 2)
8800 mips_arg_info (&cum, mode, NULL, true, &info);
8801 gparg = mips_arg_regno (&info, false);
8802 fparg = mips_arg_regno (&info, true);
8805 fprintf (file, "\t%s\t%s,%s\n", s,
8806 reg_names[gparg], reg_names[fparg]);
8807 else if (TARGET_64BIT)
8808 fprintf (file, "\td%s\t%s,%s\n", s,
8809 reg_names[gparg], reg_names[fparg]);
8810 else if (ISA_HAS_MXHC1)
8811 /* -mips32r2 -mfp64 */
8812 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n",
8814 reg_names[gparg + (WORDS_BIG_ENDIAN ? 1 : 0)],
8816 from_fp_p ? "mfhc1" : "mthc1",
8817 reg_names[gparg + (WORDS_BIG_ENDIAN ? 0 : 1)],
8819 else if (TARGET_BIG_ENDIAN)
8820 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8821 reg_names[gparg], reg_names[fparg + 1], s,
8822 reg_names[gparg + 1], reg_names[fparg]);
8824 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8825 reg_names[gparg], reg_names[fparg], s,
8826 reg_names[gparg + 1], reg_names[fparg + 1]);
8828 function_arg_advance (&cum, mode, NULL, true);
8832 /* Build a mips16 function stub. This is used for functions which
8833 take arguments in the floating point registers. It is 32-bit code
8834 that moves the floating point args into the general registers, and
8835 then jumps to the 16-bit code. */
8838 build_mips16_function_stub (FILE *file)
8841 char *secname, *stubname;
8842 tree stubid, stubdecl;
8846 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8847 secname = (char *) alloca (strlen (fnname) + 20);
8848 sprintf (secname, ".mips16.fn.%s", fnname);
8849 stubname = (char *) alloca (strlen (fnname) + 20);
8850 sprintf (stubname, "__fn_stub_%s", fnname);
8851 stubid = get_identifier (stubname);
8852 stubdecl = build_decl (FUNCTION_DECL, stubid,
8853 build_function_type (void_type_node, NULL_TREE));
8854 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8855 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
8857 fprintf (file, "\t# Stub function for %s (", current_function_name ());
8859 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8861 fprintf (file, "%s%s",
8862 need_comma ? ", " : "",
8863 (f & 3) == 1 ? "float" : "double");
8866 fprintf (file, ")\n");
8868 fprintf (file, "\t.set\tnomips16\n");
8869 switch_to_section (function_section (stubdecl));
8870 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8872 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8873 within a .ent, and we cannot emit another .ent. */
8874 if (!FUNCTION_NAME_ALREADY_DECLARED)
8876 fputs ("\t.ent\t", file);
8877 assemble_name (file, stubname);
8881 assemble_name (file, stubname);
8882 fputs (":\n", file);
8884 /* We don't want the assembler to insert any nops here. */
8885 fprintf (file, "\t.set\tnoreorder\n");
8887 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8889 fprintf (asm_out_file, "\t.set\tnoat\n");
8890 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8891 assemble_name (file, fnname);
8892 fprintf (file, "\n");
8893 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8894 fprintf (asm_out_file, "\t.set\tat\n");
8896 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8897 with one of the mfc1 instructions, because the result is not
8898 available for one instruction, so if the very first instruction
8899 in the function refers to the register, it will see the wrong
8901 fprintf (file, "\tnop\n");
8903 fprintf (file, "\t.set\treorder\n");
8905 if (!FUNCTION_NAME_ALREADY_DECLARED)
8907 fputs ("\t.end\t", file);
8908 assemble_name (file, stubname);
8912 fprintf (file, "\t.set\tmips16\n");
8914 switch_to_section (function_section (current_function_decl));
8917 /* We keep a list of functions for which we have already built stubs
8918 in build_mips16_call_stub. */
8922 struct mips16_stub *next;
8927 static struct mips16_stub *mips16_stubs;
8929 /* Emit code to return a double value from a mips16 stub. GPREG is the
8930 first GP reg to use, FPREG is the first FP reg to use. */
8933 mips16_fpret_double (int gpreg, int fpreg)
8936 fprintf (asm_out_file, "\tdmfc1\t%s,%s\n",
8937 reg_names[gpreg], reg_names[fpreg]);
8938 else if (TARGET_FLOAT64)
8940 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8941 reg_names[gpreg + WORDS_BIG_ENDIAN],
8943 fprintf (asm_out_file, "\tmfhc1\t%s,%s\n",
8944 reg_names[gpreg + !WORDS_BIG_ENDIAN],
8949 if (TARGET_BIG_ENDIAN)
8951 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8952 reg_names[gpreg + 0],
8953 reg_names[fpreg + 1]);
8954 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8955 reg_names[gpreg + 1],
8956 reg_names[fpreg + 0]);
8960 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8961 reg_names[gpreg + 0],
8962 reg_names[fpreg + 0]);
8963 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8964 reg_names[gpreg + 1],
8965 reg_names[fpreg + 1]);
8970 /* Build a call stub for a mips16 call. A stub is needed if we are
8971 passing any floating point values which should go into the floating
8972 point registers. If we are, and the call turns out to be to a
8973 32-bit function, the stub will be used to move the values into the
8974 floating point registers before calling the 32-bit function. The
8975 linker will magically adjust the function call to either the 16-bit
8976 function or the 32-bit stub, depending upon where the function call
8977 is actually defined.
8979 Similarly, we need a stub if the return value might come back in a
8980 floating point register.
8982 RETVAL is the location of the return value, or null if this is
8983 a call rather than a call_value. FN is the address of the
8984 function and ARG_SIZE is the size of the arguments. FP_CODE
8985 is the code built by function_arg. This function returns a nonzero
8986 value if it builds the call instruction itself. */
8989 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8993 char *secname, *stubname;
8994 struct mips16_stub *l;
8995 tree stubid, stubdecl;
8999 /* We don't need to do anything if we aren't in mips16 mode, or if
9000 we were invoked with the -msoft-float option. */
9001 if (!mips16_hard_float)
9004 /* Figure out whether the value might come back in a floating point
9007 fpret = mips_return_mode_in_fpr_p (GET_MODE (retval));
9009 /* We don't need to do anything if there were no floating point
9010 arguments and the value will not be returned in a floating point
9012 if (fp_code == 0 && ! fpret)
9015 /* We don't need to do anything if this is a call to a special
9016 mips16 support function. */
9017 if (GET_CODE (fn) == SYMBOL_REF
9018 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
9021 /* This code will only work for o32 and o64 abis. The other ABI's
9022 require more sophisticated support. */
9023 gcc_assert (TARGET_OLDABI);
9025 /* If we're calling via a function pointer, then we must always call
9026 via a stub. There are magic stubs provided in libgcc.a for each
9027 of the required cases. Each of them expects the function address
9028 to arrive in register $2. */
9030 if (GET_CODE (fn) != SYMBOL_REF)
9036 /* ??? If this code is modified to support other ABI's, we need
9037 to handle PARALLEL return values here. */
9040 sprintf (buf, "__mips16_call_stub_%s_%d",
9041 mips16_call_stub_mode_suffix (GET_MODE (retval)),
9044 sprintf (buf, "__mips16_call_stub_%d",
9047 id = get_identifier (buf);
9048 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
9050 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
9052 if (retval == NULL_RTX)
9053 insn = gen_call_internal (stub_fn, arg_size);
9055 insn = gen_call_value_internal (retval, stub_fn, arg_size);
9056 insn = emit_call_insn (insn);
9058 /* Put the register usage information on the CALL. */
9059 CALL_INSN_FUNCTION_USAGE (insn) =
9060 gen_rtx_EXPR_LIST (VOIDmode,
9061 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
9062 CALL_INSN_FUNCTION_USAGE (insn));
9064 /* If we are handling a floating point return value, we need to
9065 save $18 in the function prologue. Putting a note on the
9066 call will mean that df_regs_ever_live_p ($18) will be true if the
9067 call is not eliminated, and we can check that in the prologue
9070 CALL_INSN_FUNCTION_USAGE (insn) =
9071 gen_rtx_EXPR_LIST (VOIDmode,
9072 gen_rtx_USE (VOIDmode,
9073 gen_rtx_REG (word_mode, 18)),
9074 CALL_INSN_FUNCTION_USAGE (insn));
9076 /* Return 1 to tell the caller that we've generated the call
9081 /* We know the function we are going to call. If we have already
9082 built a stub, we don't need to do anything further. */
9084 fnname = XSTR (fn, 0);
9085 for (l = mips16_stubs; l != NULL; l = l->next)
9086 if (strcmp (l->name, fnname) == 0)
9091 /* Build a special purpose stub. When the linker sees a
9092 function call in mips16 code, it will check where the target
9093 is defined. If the target is a 32-bit call, the linker will
9094 search for the section defined here. It can tell which
9095 symbol this section is associated with by looking at the
9096 relocation information (the name is unreliable, since this
9097 might be a static function). If such a section is found, the
9098 linker will redirect the call to the start of the magic
9101 If the function does not return a floating point value, the
9102 special stub section is named
9105 If the function does return a floating point value, the stub
9107 .mips16.call.fp.FNNAME
9110 secname = (char *) alloca (strlen (fnname) + 40);
9111 sprintf (secname, ".mips16.call.%s%s",
9114 stubname = (char *) alloca (strlen (fnname) + 20);
9115 sprintf (stubname, "__call_stub_%s%s",
9118 stubid = get_identifier (stubname);
9119 stubdecl = build_decl (FUNCTION_DECL, stubid,
9120 build_function_type (void_type_node, NULL_TREE));
9121 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9122 DECL_RESULT (stubdecl) = build_decl (RESULT_DECL, NULL_TREE, void_type_node);
9124 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9126 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9130 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9132 fprintf (asm_out_file, "%s%s",
9133 need_comma ? ", " : "",
9134 (f & 3) == 1 ? "float" : "double");
9137 fprintf (asm_out_file, ")\n");
9139 fprintf (asm_out_file, "\t.set\tnomips16\n");
9140 assemble_start_function (stubdecl, stubname);
9142 if (!FUNCTION_NAME_ALREADY_DECLARED)
9144 fputs ("\t.ent\t", asm_out_file);
9145 assemble_name (asm_out_file, stubname);
9146 fputs ("\n", asm_out_file);
9148 assemble_name (asm_out_file, stubname);
9149 fputs (":\n", asm_out_file);
9152 /* We build the stub code by hand. That's the only way we can
9153 do it, since we can't generate 32-bit code during a 16-bit
9156 /* We don't want the assembler to insert any nops here. */
9157 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9159 mips16_fp_args (asm_out_file, fp_code, 0);
9163 fprintf (asm_out_file, "\t.set\tnoat\n");
9164 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9166 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9167 fprintf (asm_out_file, "\t.set\tat\n");
9168 /* Unfortunately, we can't fill the jump delay slot. We
9169 can't fill with one of the mtc1 instructions, because the
9170 result is not available for one instruction, so if the
9171 very first instruction in the function refers to the
9172 register, it will see the wrong value. */
9173 fprintf (asm_out_file, "\tnop\n");
9177 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9178 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9179 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9180 /* As above, we can't fill the delay slot. */
9181 fprintf (asm_out_file, "\tnop\n");
9182 if (GET_MODE (retval) == SFmode)
9183 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9184 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9185 else if (GET_MODE (retval) == SCmode)
9187 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9188 reg_names[GP_REG_FIRST + 2],
9189 reg_names[FP_REG_FIRST + 0]);
9190 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9191 reg_names[GP_REG_FIRST + 3],
9192 reg_names[FP_REG_FIRST + MAX_FPRS_PER_FMT]);
9194 else if (GET_MODE (retval) == DFmode
9195 || GET_MODE (retval) == V2SFmode)
9197 mips16_fpret_double (GP_REG_FIRST + 2, FP_REG_FIRST + 0);
9199 else if (GET_MODE (retval) == DCmode)
9201 mips16_fpret_double (GP_REG_FIRST + 2,
9203 mips16_fpret_double (GP_REG_FIRST + 4,
9204 FP_REG_FIRST + MAX_FPRS_PER_FMT);
9208 if (TARGET_BIG_ENDIAN)
9210 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9211 reg_names[GP_REG_FIRST + 2],
9212 reg_names[FP_REG_FIRST + 1]);
9213 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9214 reg_names[GP_REG_FIRST + 3],
9215 reg_names[FP_REG_FIRST + 0]);
9219 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9220 reg_names[GP_REG_FIRST + 2],
9221 reg_names[FP_REG_FIRST + 0]);
9222 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9223 reg_names[GP_REG_FIRST + 3],
9224 reg_names[FP_REG_FIRST + 1]);
9227 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9228 /* As above, we can't fill the delay slot. */
9229 fprintf (asm_out_file, "\tnop\n");
9232 fprintf (asm_out_file, "\t.set\treorder\n");
9234 #ifdef ASM_DECLARE_FUNCTION_SIZE
9235 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9238 if (!FUNCTION_NAME_ALREADY_DECLARED)
9240 fputs ("\t.end\t", asm_out_file);
9241 assemble_name (asm_out_file, stubname);
9242 fputs ("\n", asm_out_file);
9245 fprintf (asm_out_file, "\t.set\tmips16\n");
9247 /* Record this stub. */
9248 l = (struct mips16_stub *) xmalloc (sizeof *l);
9249 l->name = xstrdup (fnname);
9251 l->next = mips16_stubs;
9255 /* If we expect a floating point return value, but we've built a
9256 stub which does not expect one, then we're in trouble. We can't
9257 use the existing stub, because it won't handle the floating point
9258 value. We can't build a new stub, because the linker won't know
9259 which stub to use for the various calls in this object file.
9260 Fortunately, this case is illegal, since it means that a function
9261 was declared in two different ways in a single compilation. */
9262 if (fpret && ! l->fpret)
9263 error ("cannot handle inconsistent calls to %qs", fnname);
9265 /* If we are calling a stub which handles a floating point return
9266 value, we need to arrange to save $18 in the prologue. We do
9267 this by marking the function call as using the register. The
9268 prologue will later see that it is used, and emit code to save
9275 if (retval == NULL_RTX)
9276 insn = gen_call_internal (fn, arg_size);
9278 insn = gen_call_value_internal (retval, fn, arg_size);
9279 insn = emit_call_insn (insn);
9281 CALL_INSN_FUNCTION_USAGE (insn) =
9282 gen_rtx_EXPR_LIST (VOIDmode,
9283 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
9284 CALL_INSN_FUNCTION_USAGE (insn));
9286 /* Return 1 to tell the caller that we've generated the call
9291 /* Return 0 to let the caller generate the call insn. */
9295 /* An entry in the mips16 constant pool. VALUE is the pool constant,
9296 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
9298 struct mips16_constant {
9299 struct mips16_constant *next;
9302 enum machine_mode mode;
9305 /* Information about an incomplete mips16 constant pool. FIRST is the
9306 first constant, HIGHEST_ADDRESS is the highest address that the first
9307 byte of the pool can have, and INSN_ADDRESS is the current instruction
9310 struct mips16_constant_pool {
9311 struct mips16_constant *first;
9312 int highest_address;
9316 /* Add constant VALUE to POOL and return its label. MODE is the
9317 value's mode (used for CONST_INTs, etc.). */
9320 add_constant (struct mips16_constant_pool *pool,
9321 rtx value, enum machine_mode mode)
9323 struct mips16_constant **p, *c;
9324 bool first_of_size_p;
9326 /* See whether the constant is already in the pool. If so, return the
9327 existing label, otherwise leave P pointing to the place where the
9328 constant should be added.
9330 Keep the pool sorted in increasing order of mode size so that we can
9331 reduce the number of alignments needed. */
9332 first_of_size_p = true;
9333 for (p = &pool->first; *p != 0; p = &(*p)->next)
9335 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
9337 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
9339 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
9340 first_of_size_p = false;
9343 /* In the worst case, the constant needed by the earliest instruction
9344 will end up at the end of the pool. The entire pool must then be
9345 accessible from that instruction.
9347 When adding the first constant, set the pool's highest address to
9348 the address of the first out-of-range byte. Adjust this address
9349 downwards each time a new constant is added. */
9350 if (pool->first == 0)
9351 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
9352 is the address of the instruction with the lowest two bits clear.
9353 The base PC value for ld has the lowest three bits clear. Assume
9354 the worst case here. */
9355 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
9356 pool->highest_address -= GET_MODE_SIZE (mode);
9357 if (first_of_size_p)
9358 /* Take into account the worst possible padding due to alignment. */
9359 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
9361 /* Create a new entry. */
9362 c = (struct mips16_constant *) xmalloc (sizeof *c);
9365 c->label = gen_label_rtx ();
9372 /* Output constant VALUE after instruction INSN and return the last
9373 instruction emitted. MODE is the mode of the constant. */
9376 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
9378 switch (GET_MODE_CLASS (mode))
9382 rtx size = GEN_INT (GET_MODE_SIZE (mode));
9383 return emit_insn_after (gen_consttable_int (value, size), insn);
9387 return emit_insn_after (gen_consttable_float (value), insn);
9389 case MODE_VECTOR_FLOAT:
9390 case MODE_VECTOR_INT:
9393 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
9394 insn = dump_constants_1 (GET_MODE_INNER (mode),
9395 CONST_VECTOR_ELT (value, i), insn);
9405 /* Dump out the constants in CONSTANTS after INSN. */
9408 dump_constants (struct mips16_constant *constants, rtx insn)
9410 struct mips16_constant *c, *next;
9414 for (c = constants; c != NULL; c = next)
9416 /* If necessary, increase the alignment of PC. */
9417 if (align < GET_MODE_SIZE (c->mode))
9419 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
9420 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
9422 align = GET_MODE_SIZE (c->mode);
9424 insn = emit_label_after (c->label, insn);
9425 insn = dump_constants_1 (c->mode, c->value, insn);
9431 emit_barrier_after (insn);
9434 /* Return the length of instruction INSN. */
9437 mips16_insn_length (rtx insn)
9441 rtx body = PATTERN (insn);
9442 if (GET_CODE (body) == ADDR_VEC)
9443 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
9444 if (GET_CODE (body) == ADDR_DIFF_VEC)
9445 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
9447 return get_attr_length (insn);
9450 /* Rewrite *X so that constant pool references refer to the constant's
9451 label instead. DATA points to the constant pool structure. */
9454 mips16_rewrite_pool_refs (rtx *x, void *data)
9456 struct mips16_constant_pool *pool = data;
9457 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
9458 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
9459 get_pool_constant (*x),
9460 get_pool_mode (*x)));
9464 /* Build MIPS16 constant pools. */
9467 mips16_lay_out_constants (void)
9469 struct mips16_constant_pool pool;
9473 memset (&pool, 0, sizeof (pool));
9474 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9476 /* Rewrite constant pool references in INSN. */
9478 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
9480 pool.insn_address += mips16_insn_length (insn);
9482 if (pool.first != NULL)
9484 /* If there are no natural barriers between the first user of
9485 the pool and the highest acceptable address, we'll need to
9486 create a new instruction to jump around the constant pool.
9487 In the worst case, this instruction will be 4 bytes long.
9489 If it's too late to do this transformation after INSN,
9490 do it immediately before INSN. */
9491 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
9495 label = gen_label_rtx ();
9497 jump = emit_jump_insn_before (gen_jump (label), insn);
9498 JUMP_LABEL (jump) = label;
9499 LABEL_NUSES (label) = 1;
9500 barrier = emit_barrier_after (jump);
9502 emit_label_after (label, barrier);
9503 pool.insn_address += 4;
9506 /* See whether the constant pool is now out of range of the first
9507 user. If so, output the constants after the previous barrier.
9508 Note that any instructions between BARRIER and INSN (inclusive)
9509 will use negative offsets to refer to the pool. */
9510 if (pool.insn_address > pool.highest_address)
9512 dump_constants (pool.first, barrier);
9516 else if (BARRIER_P (insn))
9520 dump_constants (pool.first, get_last_insn ());
9523 /* A temporary variable used by for_each_rtx callbacks, etc. */
9524 static rtx mips_sim_insn;
9526 /* A structure representing the state of the processor pipeline.
9527 Used by the mips_sim_* family of functions. */
9529 /* The maximum number of instructions that can be issued in a cycle.
9530 (Caches mips_issue_rate.) */
9531 unsigned int issue_rate;
9533 /* The current simulation time. */
9536 /* How many more instructions can be issued in the current cycle. */
9537 unsigned int insns_left;
9539 /* LAST_SET[X].INSN is the last instruction to set register X.
9540 LAST_SET[X].TIME is the time at which that instruction was issued.
9541 INSN is null if no instruction has yet set register X. */
9545 } last_set[FIRST_PSEUDO_REGISTER];
9547 /* The pipeline's current DFA state. */
9551 /* Reset STATE to the initial simulation state. */
9554 mips_sim_reset (struct mips_sim *state)
9557 state->insns_left = state->issue_rate;
9558 memset (&state->last_set, 0, sizeof (state->last_set));
9559 state_reset (state->dfa_state);
9562 /* Initialize STATE before its first use. DFA_STATE points to an
9563 allocated but uninitialized DFA state. */
9566 mips_sim_init (struct mips_sim *state, state_t dfa_state)
9568 state->issue_rate = mips_issue_rate ();
9569 state->dfa_state = dfa_state;
9570 mips_sim_reset (state);
9573 /* Advance STATE by one clock cycle. */
9576 mips_sim_next_cycle (struct mips_sim *state)
9579 state->insns_left = state->issue_rate;
9580 state_transition (state->dfa_state, 0);
9583 /* Advance simulation state STATE until instruction INSN can read
9587 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
9591 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
9592 if (state->last_set[REGNO (reg) + i].insn != 0)
9596 t = state->last_set[REGNO (reg) + i].time;
9597 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
9598 while (state->time < t)
9599 mips_sim_next_cycle (state);
9603 /* A for_each_rtx callback. If *X is a register, advance simulation state
9604 DATA until mips_sim_insn can read the register's value. */
9607 mips_sim_wait_regs_2 (rtx *x, void *data)
9610 mips_sim_wait_reg (data, mips_sim_insn, *x);
9614 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
9617 mips_sim_wait_regs_1 (rtx *x, void *data)
9619 for_each_rtx (x, mips_sim_wait_regs_2, data);
9622 /* Advance simulation state STATE until all of INSN's register
9623 dependencies are satisfied. */
9626 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
9628 mips_sim_insn = insn;
9629 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
9632 /* Advance simulation state STATE until the units required by
9633 instruction INSN are available. */
9636 mips_sim_wait_units (struct mips_sim *state, rtx insn)
9640 tmp_state = alloca (state_size ());
9641 while (state->insns_left == 0
9642 || (memcpy (tmp_state, state->dfa_state, state_size ()),
9643 state_transition (tmp_state, insn) >= 0))
9644 mips_sim_next_cycle (state);
9647 /* Advance simulation state STATE until INSN is ready to issue. */
9650 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
9652 mips_sim_wait_regs (state, insn);
9653 mips_sim_wait_units (state, insn);
9656 /* mips_sim_insn has just set X. Update the LAST_SET array
9657 in simulation state DATA. */
9660 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9662 struct mips_sim *state;
9667 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
9669 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
9670 state->last_set[REGNO (x) + i].time = state->time;
9674 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
9675 can issue immediately (i.e., that mips_sim_wait_insn has already
9679 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
9681 state_transition (state->dfa_state, insn);
9682 state->insns_left--;
9684 mips_sim_insn = insn;
9685 note_stores (PATTERN (insn), mips_sim_record_set, state);
9688 /* Simulate issuing a NOP in state STATE. */
9691 mips_sim_issue_nop (struct mips_sim *state)
9693 if (state->insns_left == 0)
9694 mips_sim_next_cycle (state);
9695 state->insns_left--;
9698 /* Update simulation state STATE so that it's ready to accept the instruction
9699 after INSN. INSN should be part of the main rtl chain, not a member of a
9703 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
9705 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
9707 mips_sim_issue_nop (state);
9709 switch (GET_CODE (SEQ_BEGIN (insn)))
9713 /* We can't predict the processor state after a call or label. */
9714 mips_sim_reset (state);
9718 /* The delay slots of branch likely instructions are only executed
9719 when the branch is taken. Therefore, if the caller has simulated
9720 the delay slot instruction, STATE does not really reflect the state
9721 of the pipeline for the instruction after the delay slot. Also,
9722 branch likely instructions tend to incur a penalty when not taken,
9723 so there will probably be an extra delay between the branch and
9724 the instruction after the delay slot. */
9725 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
9726 mips_sim_reset (state);
9734 /* The VR4130 pipeline issues aligned pairs of instructions together,
9735 but it stalls the second instruction if it depends on the first.
9736 In order to cut down the amount of logic required, this dependence
9737 check is not based on a full instruction decode. Instead, any non-SPECIAL
9738 instruction is assumed to modify the register specified by bits 20-16
9739 (which is usually the "rt" field).
9741 In beq, beql, bne and bnel instructions, the rt field is actually an
9742 input, so we can end up with a false dependence between the branch
9743 and its delay slot. If this situation occurs in instruction INSN,
9744 try to avoid it by swapping rs and rt. */
9747 vr4130_avoid_branch_rt_conflict (rtx insn)
9751 first = SEQ_BEGIN (insn);
9752 second = SEQ_END (insn);
9754 && NONJUMP_INSN_P (second)
9755 && GET_CODE (PATTERN (first)) == SET
9756 && GET_CODE (SET_DEST (PATTERN (first))) == PC
9757 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
9759 /* Check for the right kind of condition. */
9760 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
9761 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
9762 && REG_P (XEXP (cond, 0))
9763 && REG_P (XEXP (cond, 1))
9764 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
9765 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
9767 /* SECOND mentions the rt register but not the rs register. */
9768 rtx tmp = XEXP (cond, 0);
9769 XEXP (cond, 0) = XEXP (cond, 1);
9770 XEXP (cond, 1) = tmp;
9775 /* Implement -mvr4130-align. Go through each basic block and simulate the
9776 processor pipeline. If we find that a pair of instructions could execute
9777 in parallel, and the first of those instruction is not 8-byte aligned,
9778 insert a nop to make it aligned. */
9781 vr4130_align_insns (void)
9783 struct mips_sim state;
9784 rtx insn, subinsn, last, last2, next;
9789 /* LAST is the last instruction before INSN to have a nonzero length.
9790 LAST2 is the last such instruction before LAST. */
9794 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
9797 mips_sim_init (&state, alloca (state_size ()));
9798 for (insn = get_insns (); insn != 0; insn = next)
9800 unsigned int length;
9802 next = NEXT_INSN (insn);
9804 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
9805 This isn't really related to the alignment pass, but we do it on
9806 the fly to avoid a separate instruction walk. */
9807 vr4130_avoid_branch_rt_conflict (insn);
9809 if (USEFUL_INSN_P (insn))
9810 FOR_EACH_SUBINSN (subinsn, insn)
9812 mips_sim_wait_insn (&state, subinsn);
9814 /* If we want this instruction to issue in parallel with the
9815 previous one, make sure that the previous instruction is
9816 aligned. There are several reasons why this isn't worthwhile
9817 when the second instruction is a call:
9819 - Calls are less likely to be performance critical,
9820 - There's a good chance that the delay slot can execute
9821 in parallel with the call.
9822 - The return address would then be unaligned.
9824 In general, if we're going to insert a nop between instructions
9825 X and Y, it's better to insert it immediately after X. That
9826 way, if the nop makes Y aligned, it will also align any labels
9828 if (state.insns_left != state.issue_rate
9829 && !CALL_P (subinsn))
9831 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
9833 /* SUBINSN is the first instruction in INSN and INSN is
9834 aligned. We want to align the previous instruction
9835 instead, so insert a nop between LAST2 and LAST.
9837 Note that LAST could be either a single instruction
9838 or a branch with a delay slot. In the latter case,
9839 LAST, like INSN, is already aligned, but the delay
9840 slot must have some extra delay that stops it from
9841 issuing at the same time as the branch. We therefore
9842 insert a nop before the branch in order to align its
9844 emit_insn_after (gen_nop (), last2);
9847 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
9849 /* SUBINSN is the delay slot of INSN, but INSN is
9850 currently unaligned. Insert a nop between
9851 LAST and INSN to align it. */
9852 emit_insn_after (gen_nop (), last);
9856 mips_sim_issue_insn (&state, subinsn);
9858 mips_sim_finish_insn (&state, insn);
9860 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
9861 length = get_attr_length (insn);
9864 /* If the instruction is an asm statement or multi-instruction
9865 mips.md patern, the length is only an estimate. Insert an
9866 8 byte alignment after it so that the following instructions
9867 can be handled correctly. */
9868 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
9869 && (recog_memoized (insn) < 0 || length >= 8))
9871 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
9872 next = NEXT_INSN (next);
9873 mips_sim_next_cycle (&state);
9876 else if (length & 4)
9877 aligned_p = !aligned_p;
9882 /* See whether INSN is an aligned label. */
9883 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
9889 /* Subroutine of mips_reorg. If there is a hazard between INSN
9890 and a previous instruction, avoid it by inserting nops after
9893 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
9894 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
9895 before using the value of that register. *HILO_DELAY counts the
9896 number of instructions since the last hilo hazard (that is,
9897 the number of instructions since the last mflo or mfhi).
9899 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
9900 for the next instruction.
9902 LO_REG is an rtx for the LO register, used in dependence checking. */
9905 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
9906 rtx *delayed_reg, rtx lo_reg)
9914 pattern = PATTERN (insn);
9916 /* Do not put the whole function in .set noreorder if it contains
9917 an asm statement. We don't know whether there will be hazards
9918 between the asm statement and the gcc-generated code. */
9919 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
9920 cfun->machine->all_noreorder_p = false;
9922 /* Ignore zero-length instructions (barriers and the like). */
9923 ninsns = get_attr_length (insn) / 4;
9927 /* Work out how many nops are needed. Note that we only care about
9928 registers that are explicitly mentioned in the instruction's pattern.
9929 It doesn't matter that calls use the argument registers or that they
9930 clobber hi and lo. */
9931 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
9932 nops = 2 - *hilo_delay;
9933 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9938 /* Insert the nops between this instruction and the previous one.
9939 Each new nop takes us further from the last hilo hazard. */
9940 *hilo_delay += nops;
9942 emit_insn_after (gen_hazard_nop (), after);
9944 /* Set up the state for the next instruction. */
9945 *hilo_delay += ninsns;
9947 if (INSN_CODE (insn) >= 0)
9948 switch (get_attr_hazard (insn))
9958 set = single_set (insn);
9959 gcc_assert (set != 0);
9960 *delayed_reg = SET_DEST (set);
9966 /* Go through the instruction stream and insert nops where necessary.
9967 See if the whole function can then be put into .set noreorder &
9971 mips_avoid_hazards (void)
9973 rtx insn, last_insn, lo_reg, delayed_reg;
9976 /* Force all instructions to be split into their final form. */
9977 split_all_insns_noflow ();
9979 /* Recalculate instruction lengths without taking nops into account. */
9980 cfun->machine->ignore_hazard_length_p = true;
9981 shorten_branches (get_insns ());
9983 cfun->machine->all_noreorder_p = true;
9985 /* Profiled functions can't be all noreorder because the profiler
9986 support uses assembler macros. */
9987 if (current_function_profile)
9988 cfun->machine->all_noreorder_p = false;
9990 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9991 we rely on the assembler to work around some errata. */
9992 if (TARGET_FIX_VR4120)
9993 cfun->machine->all_noreorder_p = false;
9995 /* The same is true for -mfix-vr4130 if we might generate mflo or
9996 mfhi instructions. Note that we avoid using mflo and mfhi if
9997 the VR4130 macc and dmacc instructions are available instead;
9998 see the *mfhilo_{si,di}_macc patterns. */
9999 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
10000 cfun->machine->all_noreorder_p = false;
10005 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
10007 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
10010 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
10011 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
10012 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
10013 &hilo_delay, &delayed_reg, lo_reg);
10015 mips_avoid_hazard (last_insn, insn, &hilo_delay,
10016 &delayed_reg, lo_reg);
10023 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
10029 mips16_lay_out_constants ();
10030 else if (TARGET_EXPLICIT_RELOCS)
10032 if (mips_flag_delayed_branch)
10033 dbr_schedule (get_insns ());
10034 mips_avoid_hazards ();
10035 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
10036 vr4130_align_insns ();
10040 /* This function does three things:
10042 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
10043 - Register the mips16 hardware floating point stubs.
10044 - Register the gofast functions if selected using --enable-gofast. */
10046 #include "config/gofast.h"
10049 mips_init_libfuncs (void)
10051 if (TARGET_FIX_VR4120)
10053 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10054 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10057 if (mips16_hard_float)
10059 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10060 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10061 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10062 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10064 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10065 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10066 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10067 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10068 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10069 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10071 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10072 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10074 if (TARGET_DOUBLE_FLOAT)
10076 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10077 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10078 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10079 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10081 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10082 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10083 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10084 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10085 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10086 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10088 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
10089 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
10091 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
10092 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
10096 gofast_maybe_init_libfuncs ();
10099 /* Return a number assessing the cost of moving a register in class
10100 FROM to class TO. The classes are expressed using the enumeration
10101 values such as `GENERAL_REGS'. A value of 2 is the default; other
10102 values are interpreted relative to that.
10104 It is not required that the cost always equal 2 when FROM is the
10105 same as TO; on some machines it is expensive to move between
10106 registers if they are not general registers.
10108 If reload sees an insn consisting of a single `set' between two
10109 hard registers, and if `REGISTER_MOVE_COST' applied to their
10110 classes returns a value of 2, reload does not check to ensure that
10111 the constraints of the insn are met. Setting a cost of other than
10112 2 will allow reload to verify that the constraints are met. You
10113 should do this if the `movM' pattern's constraints do not allow
10116 ??? We make the cost of moving from HI/LO into general
10117 registers the same as for one of moving general registers to
10118 HI/LO for TARGET_MIPS16 in order to prevent allocating a
10119 pseudo to HI/LO. This might hurt optimizations though, it
10120 isn't clear if it is wise. And it might not work in all cases. We
10121 could solve the DImode LO reg problem by using a multiply, just
10122 like reload_{in,out}si. We could solve the SImode/HImode HI reg
10123 problem by using divide instructions. divu puts the remainder in
10124 the HI reg, so doing a divide by -1 will move the value in the HI
10125 reg for all values except -1. We could handle that case by using a
10126 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
10127 a compare/branch to test the input value to see which instruction
10128 we need to use. This gets pretty messy, but it is feasible. */
10131 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10132 enum reg_class to, enum reg_class from)
10134 if (from == M16_REGS && GR_REG_CLASS_P (to))
10136 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
10138 else if (GR_REG_CLASS_P (from))
10140 if (to == M16_REGS)
10142 else if (to == M16_NA_REGS)
10144 else if (GR_REG_CLASS_P (to))
10151 else if (to == FP_REGS)
10153 else if (reg_class_subset_p (to, ACC_REGS))
10160 else if (COP_REG_CLASS_P (to))
10165 else if (from == FP_REGS)
10167 if (GR_REG_CLASS_P (to))
10169 else if (to == FP_REGS)
10171 else if (to == ST_REGS)
10174 else if (reg_class_subset_p (from, ACC_REGS))
10176 if (GR_REG_CLASS_P (to))
10184 else if (from == ST_REGS && GR_REG_CLASS_P (to))
10186 else if (COP_REG_CLASS_P (from))
10192 ??? What cases are these? Shouldn't we return 2 here? */
10197 /* Return the length of INSN. LENGTH is the initial length computed by
10198 attributes in the machine-description file. */
10201 mips_adjust_insn_length (rtx insn, int length)
10203 /* A unconditional jump has an unfilled delay slot if it is not part
10204 of a sequence. A conditional jump normally has a delay slot, but
10205 does not on MIPS16. */
10206 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10209 /* See how many nops might be needed to avoid hardware hazards. */
10210 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10211 switch (get_attr_hazard (insn))
10225 /* All MIPS16 instructions are a measly two bytes. */
10233 /* Return an asm sequence to start a noat block and load the address
10234 of a label into $1. */
10237 mips_output_load_label (void)
10239 if (TARGET_EXPLICIT_RELOCS)
10243 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10246 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10249 if (ISA_HAS_LOAD_DELAY)
10250 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10251 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10255 if (Pmode == DImode)
10256 return "%[dla\t%@,%0";
10258 return "%[la\t%@,%0";
10262 /* Return the assembly code for INSN, which has the operands given by
10263 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10264 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10265 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10266 version of BRANCH_IF_TRUE. */
10269 mips_output_conditional_branch (rtx insn, rtx *operands,
10270 const char *branch_if_true,
10271 const char *branch_if_false)
10273 unsigned int length;
10274 rtx taken, not_taken;
10276 length = get_attr_length (insn);
10279 /* Just a simple conditional branch. */
10280 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10281 return branch_if_true;
10284 /* Generate a reversed branch around a direct jump. This fallback does
10285 not use branch-likely instructions. */
10286 mips_branch_likely = false;
10287 not_taken = gen_label_rtx ();
10288 taken = operands[1];
10290 /* Generate the reversed branch to NOT_TAKEN. */
10291 operands[1] = not_taken;
10292 output_asm_insn (branch_if_false, operands);
10294 /* If INSN has a delay slot, we must provide delay slots for both the
10295 branch to NOT_TAKEN and the conditional jump. We must also ensure
10296 that INSN's delay slot is executed in the appropriate cases. */
10297 if (final_sequence)
10299 /* This first delay slot will always be executed, so use INSN's
10300 delay slot if is not annulled. */
10301 if (!INSN_ANNULLED_BRANCH_P (insn))
10303 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10304 asm_out_file, optimize, 1, NULL);
10305 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10308 output_asm_insn ("nop", 0);
10309 fprintf (asm_out_file, "\n");
10312 /* Output the unconditional branch to TAKEN. */
10314 output_asm_insn ("j\t%0%/", &taken);
10317 output_asm_insn (mips_output_load_label (), &taken);
10318 output_asm_insn ("jr\t%@%]%/", 0);
10321 /* Now deal with its delay slot; see above. */
10322 if (final_sequence)
10324 /* This delay slot will only be executed if the branch is taken.
10325 Use INSN's delay slot if is annulled. */
10326 if (INSN_ANNULLED_BRANCH_P (insn))
10328 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10329 asm_out_file, optimize, 1, NULL);
10330 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10333 output_asm_insn ("nop", 0);
10334 fprintf (asm_out_file, "\n");
10337 /* Output NOT_TAKEN. */
10338 (*targetm.asm_out.internal_label) (asm_out_file, "L",
10339 CODE_LABEL_NUMBER (not_taken));
10343 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10344 if some ordered condition is true. The condition is given by
10345 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10346 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10347 its second is always zero. */
10350 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10352 const char *branch[2];
10354 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10355 Make BRANCH[0] branch on the inverse condition. */
10356 switch (GET_CODE (operands[0]))
10358 /* These cases are equivalent to comparisons against zero. */
10360 inverted_p = !inverted_p;
10361 /* Fall through. */
10363 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10364 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10367 /* These cases are always true or always false. */
10369 inverted_p = !inverted_p;
10370 /* Fall through. */
10372 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10373 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10377 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10378 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10381 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10384 /* Used to output div or ddiv instruction DIVISION, which has the operands
10385 given by OPERANDS. Add in a divide-by-zero check if needed.
10387 When working around R4000 and R4400 errata, we need to make sure that
10388 the division is not immediately followed by a shift[1][2]. We also
10389 need to stop the division from being put into a branch delay slot[3].
10390 The easiest way to avoid both problems is to add a nop after the
10391 division. When a divide-by-zero check is needed, this nop can be
10392 used to fill the branch delay slot.
10394 [1] If a double-word or a variable shift executes immediately
10395 after starting an integer division, the shift may give an
10396 incorrect result. See quotations of errata #16 and #28 from
10397 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10398 in mips.md for details.
10400 [2] A similar bug to [1] exists for all revisions of the
10401 R4000 and the R4400 when run in an MC configuration.
10402 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10404 "19. In this following sequence:
10406 ddiv (or ddivu or div or divu)
10407 dsll32 (or dsrl32, dsra32)
10409 if an MPT stall occurs, while the divide is slipping the cpu
10410 pipeline, then the following double shift would end up with an
10413 Workaround: The compiler needs to avoid generating any
10414 sequence with divide followed by extended double shift."
10416 This erratum is also present in "MIPS R4400MC Errata, Processor
10417 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10418 & 3.0" as errata #10 and #4, respectively.
10420 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10421 (also valid for MIPS R4000MC processors):
10423 "52. R4000SC: This bug does not apply for the R4000PC.
10425 There are two flavors of this bug:
10427 1) If the instruction just after divide takes an RF exception
10428 (tlb-refill, tlb-invalid) and gets an instruction cache
10429 miss (both primary and secondary) and the line which is
10430 currently in secondary cache at this index had the first
10431 data word, where the bits 5..2 are set, then R4000 would
10432 get a wrong result for the div.
10437 ------------------- # end-of page. -tlb-refill
10442 ------------------- # end-of page. -tlb-invalid
10445 2) If the divide is in the taken branch delay slot, where the
10446 target takes RF exception and gets an I-cache miss for the
10447 exception vector or where I-cache miss occurs for the
10448 target address, under the above mentioned scenarios, the
10449 div would get wrong results.
10452 j r2 # to next page mapped or unmapped
10453 div r8,r9 # this bug would be there as long
10454 # as there is an ICache miss and
10455 nop # the "data pattern" is present
10458 beq r0, r0, NextPage # to Next page
10462 This bug is present for div, divu, ddiv, and ddivu
10465 Workaround: For item 1), OS could make sure that the next page
10466 after the divide instruction is also mapped. For item 2), the
10467 compiler could make sure that the divide instruction is not in
10468 the branch delay slot."
10470 These processors have PRId values of 0x00004220 and 0x00004300 for
10471 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10474 mips_output_division (const char *division, rtx *operands)
10479 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10481 output_asm_insn (s, operands);
10484 if (TARGET_CHECK_ZERO_DIV)
10488 output_asm_insn (s, operands);
10489 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10491 else if (GENERATE_DIVIDE_TRAPS)
10493 output_asm_insn (s, operands);
10494 s = "teq\t%2,%.,7";
10498 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10499 output_asm_insn (s, operands);
10500 s = "break\t7%)\n1:";
10506 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10507 with a final "000" replaced by "k". Ignore case.
10509 Note: this function is shared between GCC and GAS. */
10512 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
10514 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10515 given++, canonical++;
10517 return ((*given == 0 && *canonical == 0)
10518 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10522 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10523 CPU name. We've traditionally allowed a lot of variation here.
10525 Note: this function is shared between GCC and GAS. */
10528 mips_matching_cpu_name_p (const char *canonical, const char *given)
10530 /* First see if the name matches exactly, or with a final "000"
10531 turned into "k". */
10532 if (mips_strict_matching_cpu_name_p (canonical, given))
10535 /* If not, try comparing based on numerical designation alone.
10536 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10537 if (TOLOWER (*given) == 'r')
10539 if (!ISDIGIT (*given))
10542 /* Skip over some well-known prefixes in the canonical name,
10543 hoping to find a number there too. */
10544 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10546 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10548 else if (TOLOWER (canonical[0]) == 'r')
10551 return mips_strict_matching_cpu_name_p (canonical, given);
10555 /* Return the mips_cpu_info entry for the processor or ISA given
10556 by CPU_STRING. Return null if the string isn't recognized.
10558 A similar function exists in GAS. */
10560 static const struct mips_cpu_info *
10561 mips_parse_cpu (const char *cpu_string)
10563 const struct mips_cpu_info *p;
10566 /* In the past, we allowed upper-case CPU names, but it doesn't
10567 work well with the multilib machinery. */
10568 for (s = cpu_string; *s != 0; s++)
10571 warning (0, "the cpu name must be lower case");
10575 /* 'from-abi' selects the most compatible architecture for the given
10576 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10577 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10578 version. Look first at the -mgp options, if given, otherwise base
10579 the choice on MASK_64BIT in TARGET_DEFAULT. */
10580 if (strcasecmp (cpu_string, "from-abi") == 0)
10581 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10582 : ABI_NEEDS_64BIT_REGS ? 3
10583 : (TARGET_64BIT ? 3 : 1));
10585 /* 'default' has traditionally been a no-op. Probably not very useful. */
10586 if (strcasecmp (cpu_string, "default") == 0)
10589 for (p = mips_cpu_info_table; p->name != 0; p++)
10590 if (mips_matching_cpu_name_p (p->name, cpu_string))
10597 /* Return the processor associated with the given ISA level, or null
10598 if the ISA isn't valid. */
10600 static const struct mips_cpu_info *
10601 mips_cpu_info_from_isa (int isa)
10603 const struct mips_cpu_info *p;
10605 for (p = mips_cpu_info_table; p->name != 0; p++)
10612 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
10613 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
10614 they only hold condition code modes, and CCmode is always considered to
10615 be 4 bytes wide. All other registers are word sized. */
10618 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10620 if (ST_REG_P (regno))
10621 return ((GET_MODE_SIZE (mode) + 3) / 4);
10622 else if (! FP_REG_P (regno))
10623 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10625 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10628 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
10629 all BLKmode objects are returned in memory. Under the new (N32 and
10630 64-bit MIPS ABIs) small structures are returned in a register.
10631 Objects with varying size must still be returned in memory, of
10635 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
10638 return (TYPE_MODE (type) == BLKmode);
10640 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10641 || (int_size_in_bytes (type) == -1));
10645 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
10647 return !TARGET_OLDABI;
10650 /* Return true if INSN is a multiply-add or multiply-subtract
10651 instruction and PREV assigns to the accumulator operand. */
10654 mips_linked_madd_p (rtx prev, rtx insn)
10658 x = single_set (insn);
10664 if (GET_CODE (x) == PLUS
10665 && GET_CODE (XEXP (x, 0)) == MULT
10666 && reg_set_p (XEXP (x, 1), prev))
10669 if (GET_CODE (x) == MINUS
10670 && GET_CODE (XEXP (x, 1)) == MULT
10671 && reg_set_p (XEXP (x, 0), prev))
10677 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
10678 that may clobber hi or lo. */
10680 static rtx mips_macc_chains_last_hilo;
10682 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
10683 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
10686 mips_macc_chains_record (rtx insn)
10688 if (get_attr_may_clobber_hilo (insn))
10689 mips_macc_chains_last_hilo = insn;
10692 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
10693 has NREADY elements, looking for a multiply-add or multiply-subtract
10694 instruction that is cumulative with mips_macc_chains_last_hilo.
10695 If there is one, promote it ahead of anything else that might
10696 clobber hi or lo. */
10699 mips_macc_chains_reorder (rtx *ready, int nready)
10703 if (mips_macc_chains_last_hilo != 0)
10704 for (i = nready - 1; i >= 0; i--)
10705 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
10707 for (j = nready - 1; j > i; j--)
10708 if (recog_memoized (ready[j]) >= 0
10709 && get_attr_may_clobber_hilo (ready[j]))
10711 mips_promote_ready (ready, i, j);
10718 /* The last instruction to be scheduled. */
10720 static rtx vr4130_last_insn;
10722 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
10723 points to an rtx that is initially an instruction. Nullify the rtx
10724 if the instruction uses the value of register X. */
10727 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
10729 rtx *insn_ptr = data;
10732 && reg_referenced_p (x, PATTERN (*insn_ptr)))
10736 /* Return true if there is true register dependence between vr4130_last_insn
10740 vr4130_true_reg_dependence_p (rtx insn)
10742 note_stores (PATTERN (vr4130_last_insn),
10743 vr4130_true_reg_dependence_p_1, &insn);
10747 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
10748 the ready queue and that INSN2 is the instruction after it, return
10749 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
10750 in which INSN1 and INSN2 can probably issue in parallel, but for
10751 which (INSN2, INSN1) should be less sensitive to instruction
10752 alignment than (INSN1, INSN2). See 4130.md for more details. */
10755 vr4130_swap_insns_p (rtx insn1, rtx insn2)
10759 /* Check for the following case:
10761 1) there is some other instruction X with an anti dependence on INSN1;
10762 2) X has a higher priority than INSN2; and
10763 3) X is an arithmetic instruction (and thus has no unit restrictions).
10765 If INSN1 is the last instruction blocking X, it would better to
10766 choose (INSN1, X) over (INSN2, INSN1). */
10767 FOR_EACH_DEP_LINK (dep, INSN_FORW_DEPS (insn1))
10768 if (DEP_LINK_KIND (dep) == REG_DEP_ANTI
10769 && INSN_PRIORITY (DEP_LINK_CON (dep)) > INSN_PRIORITY (insn2)
10770 && recog_memoized (DEP_LINK_CON (dep)) >= 0
10771 && get_attr_vr4130_class (DEP_LINK_CON (dep)) == VR4130_CLASS_ALU)
10774 if (vr4130_last_insn != 0
10775 && recog_memoized (insn1) >= 0
10776 && recog_memoized (insn2) >= 0)
10778 /* See whether INSN1 and INSN2 use different execution units,
10779 or if they are both ALU-type instructions. If so, they can
10780 probably execute in parallel. */
10781 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
10782 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
10783 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
10785 /* If only one of the instructions has a dependence on
10786 vr4130_last_insn, prefer to schedule the other one first. */
10787 bool dep1 = vr4130_true_reg_dependence_p (insn1);
10788 bool dep2 = vr4130_true_reg_dependence_p (insn2);
10792 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
10793 is not an ALU-type instruction and if INSN1 uses the same
10794 execution unit. (Note that if this condition holds, we already
10795 know that INSN2 uses a different execution unit.) */
10796 if (class1 != VR4130_CLASS_ALU
10797 && recog_memoized (vr4130_last_insn) >= 0
10798 && class1 == get_attr_vr4130_class (vr4130_last_insn))
10805 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
10806 queue with at least two instructions. Swap the first two if
10807 vr4130_swap_insns_p says that it could be worthwhile. */
10810 vr4130_reorder (rtx *ready, int nready)
10812 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
10813 mips_promote_ready (ready, nready - 2, nready - 1);
10816 /* Remove the instruction at index LOWER from ready queue READY and
10817 reinsert it in front of the instruction at index HIGHER. LOWER must
10821 mips_promote_ready (rtx *ready, int lower, int higher)
10826 new_head = ready[lower];
10827 for (i = lower; i < higher; i++)
10828 ready[i] = ready[i + 1];
10829 ready[i] = new_head;
10832 /* Implement TARGET_SCHED_REORDER. */
10835 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10836 rtx *ready, int *nreadyp, int cycle)
10838 if (!reload_completed && TUNE_MACC_CHAINS)
10841 mips_macc_chains_last_hilo = 0;
10843 mips_macc_chains_reorder (ready, *nreadyp);
10845 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
10848 vr4130_last_insn = 0;
10850 vr4130_reorder (ready, *nreadyp);
10852 return mips_issue_rate ();
10855 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
10858 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
10859 rtx insn, int more)
10861 switch (GET_CODE (PATTERN (insn)))
10865 /* Don't count USEs and CLOBBERs against the issue rate. */
10870 if (!reload_completed && TUNE_MACC_CHAINS)
10871 mips_macc_chains_record (insn);
10872 vr4130_last_insn = insn;
10878 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10879 dependencies have no cost, except on the 20Kc where output-dependence
10880 is treated like input-dependence. */
10883 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10884 rtx dep ATTRIBUTE_UNUSED, int cost)
10886 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
10889 if (REG_NOTE_KIND (link) != 0)
10894 /* Return the number of instructions that can be issued per cycle. */
10897 mips_issue_rate (void)
10901 case PROCESSOR_74KC:
10902 case PROCESSOR_74KF2_1:
10903 case PROCESSOR_74KF1_1:
10904 case PROCESSOR_74KF3_2:
10905 /* The 74k is not strictly quad-issue cpu, but can be seen as one
10906 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
10907 but in reality only a maximum of 3 insns can be issued as the
10908 floating point load/stores also require a slot in the AGEN pipe. */
10911 case PROCESSOR_20KC:
10912 case PROCESSOR_R4130:
10913 case PROCESSOR_R5400:
10914 case PROCESSOR_R5500:
10915 case PROCESSOR_R7000:
10916 case PROCESSOR_R9000:
10919 case PROCESSOR_SB1:
10920 case PROCESSOR_SB1A:
10921 /* This is actually 4, but we get better performance if we claim 3.
10922 This is partly because of unwanted speculative code motion with the
10923 larger number, and partly because in most common cases we can't
10924 reach the theoretical max of 4. */
10932 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
10933 be as wide as the scheduling freedom in the DFA. */
10936 mips_multipass_dfa_lookahead (void)
10938 /* Can schedule up to 4 of the 6 function units in any one cycle. */
10945 /* Implements a store data bypass check. We need this because the cprestore
10946 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
10947 default routine to abort. We just return false for that case. */
10948 /* ??? Should try to give a better result here than assuming false. */
10951 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10953 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10956 return ! store_data_bypass_p (out_insn, in_insn);
10959 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10960 return the first operand of the associated "pref" or "prefx" insn. */
10963 mips_prefetch_cookie (rtx write, rtx locality)
10965 /* store_streamed / load_streamed. */
10966 if (INTVAL (locality) <= 0)
10967 return GEN_INT (INTVAL (write) + 4);
10969 /* store / load. */
10970 if (INTVAL (locality) <= 2)
10973 /* store_retained / load_retained. */
10974 return GEN_INT (INTVAL (write) + 6);
10977 /* MIPS builtin function support. */
10979 struct builtin_description
10981 /* The code of the main .md file instruction. See mips_builtin_type
10982 for more information. */
10983 enum insn_code icode;
10985 /* The floating-point comparison code to use with ICODE, if any. */
10986 enum mips_fp_condition cond;
10988 /* The name of the builtin function. */
10991 /* Specifies how the function should be expanded. */
10992 enum mips_builtin_type builtin_type;
10994 /* The function's prototype. */
10995 enum mips_function_type function_type;
10997 /* The target flags required for this function. */
11001 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
11002 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
11003 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
11004 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
11005 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
11007 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
11009 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
11010 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
11011 "__builtin_mips_" #INSN "_" #COND "_s", \
11012 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
11013 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
11014 "__builtin_mips_" #INSN "_" #COND "_d", \
11015 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
11017 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11018 The lower and upper forms require TARGET_FLAGS while the any and all
11019 forms require MASK_MIPS3D. */
11020 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
11021 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11022 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
11023 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
11024 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11025 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
11026 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
11027 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11028 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
11029 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
11030 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11031 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
11032 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
11034 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11035 require MASK_MIPS3D. */
11036 #define CMP_4S_BUILTINS(INSN, COND) \
11037 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11038 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
11039 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11041 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
11042 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
11043 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11046 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11047 instruction requires TARGET_FLAGS. */
11048 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
11049 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11050 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
11051 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11053 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
11054 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
11055 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11058 /* Define all the builtins related to c.cond.fmt condition COND. */
11059 #define CMP_BUILTINS(COND) \
11060 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11061 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
11062 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
11063 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
11064 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
11065 CMP_4S_BUILTINS (c, COND), \
11066 CMP_4S_BUILTINS (cabs, COND)
11068 static const struct builtin_description mips_bdesc[] =
11070 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11071 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11072 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11073 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11074 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
11075 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11076 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11077 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
11079 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
11080 MASK_PAIRED_SINGLE_FLOAT),
11081 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11082 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11083 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11084 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11086 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11087 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11088 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11089 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11090 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11091 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11093 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
11094 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
11095 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
11096 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
11097 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
11098 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
11100 MIPS_FP_CONDITIONS (CMP_BUILTINS)
11103 /* Builtin functions for the SB-1 processor. */
11105 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11107 static const struct builtin_description sb1_bdesc[] =
11109 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
11112 /* Builtin functions for DSP ASE. */
11114 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11115 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11116 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11117 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11118 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11120 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
11121 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
11122 builtin_description fields. */
11123 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
11124 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
11125 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
11127 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11128 branch instruction. TARGET_FLAGS is a builtin_description field. */
11129 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
11130 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
11131 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
11133 static const struct builtin_description dsp_bdesc[] =
11135 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11136 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11137 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11138 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11139 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11140 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11141 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11142 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11143 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11144 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11145 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11146 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11147 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11148 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
11149 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
11150 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
11151 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11152 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11153 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
11154 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
11155 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11156 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
11157 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11158 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11159 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11160 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11161 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11162 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11163 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11164 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
11165 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11166 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11167 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11168 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11169 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
11170 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11171 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
11172 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11173 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11174 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
11175 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11176 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11177 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
11178 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
11179 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
11180 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
11181 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
11182 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11183 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11184 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
11185 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11186 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11187 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
11188 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11189 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11190 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
11191 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
11192 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11193 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
11194 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
11195 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
11196 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11197 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11198 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
11199 BPOSGE_BUILTIN (32, MASK_DSP),
11201 /* The following are for the MIPS DSP ASE REV 2. */
11202 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, MASK_DSPR2),
11203 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11204 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11205 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11206 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11207 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11208 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11209 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11210 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11211 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11212 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11213 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11214 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11215 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11216 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11217 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11218 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11219 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, MASK_DSPR2),
11220 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, MASK_DSPR2),
11221 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11222 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSPR2),
11223 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSPR2),
11224 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11225 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11226 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11227 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSPR2),
11228 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11229 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11230 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11231 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11232 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11233 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSPR2),
11234 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2),
11235 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSPR2)
11238 static const struct builtin_description dsp_32only_bdesc[] =
11240 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11241 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11242 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11243 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
11244 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11245 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11246 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11247 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11248 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
11249 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11250 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11251 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11252 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
11253 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11254 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11255 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11256 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11257 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11258 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
11259 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11260 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
11262 /* The following are for the MIPS DSP ASE REV 2. */
11263 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11264 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11265 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11266 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11267 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSPR2),
11268 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, MASK_DSPR2),
11269 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11270 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, MASK_DSPR2),
11271 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, MASK_DSPR2),
11272 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11273 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11274 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11275 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11276 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2),
11277 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSPR2)
11280 /* This helps provide a mapping from builtin function codes to bdesc
11285 /* The builtin function table that this entry describes. */
11286 const struct builtin_description *bdesc;
11288 /* The number of entries in the builtin function table. */
11291 /* The target processor that supports these builtin functions.
11292 PROCESSOR_MAX means we enable them for all processors. */
11293 enum processor_type proc;
11295 /* If the target has these flags, this builtin function table
11296 will not be supported. */
11297 int unsupported_target_flags;
11300 static const struct bdesc_map bdesc_arrays[] =
11302 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX, 0 },
11303 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1, 0 },
11304 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX, 0 },
11305 { dsp_32only_bdesc, ARRAY_SIZE (dsp_32only_bdesc), PROCESSOR_MAX,
11309 /* Take the argument ARGNUM of the arglist of EXP and convert it into a form
11310 suitable for input operand OP of instruction ICODE. Return the value. */
11313 mips_prepare_builtin_arg (enum insn_code icode,
11314 unsigned int op, tree exp, unsigned int argnum)
11317 enum machine_mode mode;
11319 value = expand_normal (CALL_EXPR_ARG (exp, argnum));
11320 mode = insn_data[icode].operand[op].mode;
11321 if (!insn_data[icode].operand[op].predicate (value, mode))
11323 value = copy_to_mode_reg (mode, value);
11324 /* Check the predicate again. */
11325 if (!insn_data[icode].operand[op].predicate (value, mode))
11327 error ("invalid argument to builtin function");
11335 /* Return an rtx suitable for output operand OP of instruction ICODE.
11336 If TARGET is non-null, try to use it where possible. */
11339 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
11341 enum machine_mode mode;
11343 mode = insn_data[icode].operand[op].mode;
11344 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
11345 target = gen_reg_rtx (mode);
11350 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
11353 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11354 enum machine_mode mode ATTRIBUTE_UNUSED,
11355 int ignore ATTRIBUTE_UNUSED)
11357 enum insn_code icode;
11358 enum mips_builtin_type type;
11360 unsigned int fcode;
11361 const struct builtin_description *bdesc;
11362 const struct bdesc_map *m;
11364 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11365 fcode = DECL_FUNCTION_CODE (fndecl);
11368 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11370 if (fcode < m->size)
11373 icode = bdesc[fcode].icode;
11374 type = bdesc[fcode].builtin_type;
11384 case MIPS_BUILTIN_DIRECT:
11385 return mips_expand_builtin_direct (icode, target, exp, true);
11387 case MIPS_BUILTIN_DIRECT_NO_TARGET:
11388 return mips_expand_builtin_direct (icode, target, exp, false);
11390 case MIPS_BUILTIN_MOVT:
11391 case MIPS_BUILTIN_MOVF:
11392 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
11395 case MIPS_BUILTIN_CMP_ANY:
11396 case MIPS_BUILTIN_CMP_ALL:
11397 case MIPS_BUILTIN_CMP_UPPER:
11398 case MIPS_BUILTIN_CMP_LOWER:
11399 case MIPS_BUILTIN_CMP_SINGLE:
11400 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
11403 case MIPS_BUILTIN_BPOSGE32:
11404 return mips_expand_builtin_bposge (type, target);
11411 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
11414 mips_init_builtins (void)
11416 const struct builtin_description *d;
11417 const struct bdesc_map *m;
11418 tree types[(int) MIPS_MAX_FTYPE_MAX];
11419 tree V2SF_type_node;
11420 tree V2HI_type_node;
11421 tree V4QI_type_node;
11422 unsigned int offset;
11424 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
11425 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
11428 if (TARGET_PAIRED_SINGLE_FLOAT)
11430 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
11432 types[MIPS_V2SF_FTYPE_V2SF]
11433 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
11435 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
11436 = build_function_type_list (V2SF_type_node,
11437 V2SF_type_node, V2SF_type_node, NULL_TREE);
11439 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
11440 = build_function_type_list (V2SF_type_node,
11441 V2SF_type_node, V2SF_type_node,
11442 integer_type_node, NULL_TREE);
11444 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
11445 = build_function_type_list (V2SF_type_node,
11446 V2SF_type_node, V2SF_type_node,
11447 V2SF_type_node, V2SF_type_node, NULL_TREE);
11449 types[MIPS_V2SF_FTYPE_SF_SF]
11450 = build_function_type_list (V2SF_type_node,
11451 float_type_node, float_type_node, NULL_TREE);
11453 types[MIPS_INT_FTYPE_V2SF_V2SF]
11454 = build_function_type_list (integer_type_node,
11455 V2SF_type_node, V2SF_type_node, NULL_TREE);
11457 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
11458 = build_function_type_list (integer_type_node,
11459 V2SF_type_node, V2SF_type_node,
11460 V2SF_type_node, V2SF_type_node, NULL_TREE);
11462 types[MIPS_INT_FTYPE_SF_SF]
11463 = build_function_type_list (integer_type_node,
11464 float_type_node, float_type_node, NULL_TREE);
11466 types[MIPS_INT_FTYPE_DF_DF]
11467 = build_function_type_list (integer_type_node,
11468 double_type_node, double_type_node, NULL_TREE);
11470 types[MIPS_SF_FTYPE_V2SF]
11471 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
11473 types[MIPS_SF_FTYPE_SF]
11474 = build_function_type_list (float_type_node,
11475 float_type_node, NULL_TREE);
11477 types[MIPS_SF_FTYPE_SF_SF]
11478 = build_function_type_list (float_type_node,
11479 float_type_node, float_type_node, NULL_TREE);
11481 types[MIPS_DF_FTYPE_DF]
11482 = build_function_type_list (double_type_node,
11483 double_type_node, NULL_TREE);
11485 types[MIPS_DF_FTYPE_DF_DF]
11486 = build_function_type_list (double_type_node,
11487 double_type_node, double_type_node, NULL_TREE);
11492 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
11493 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
11495 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
11496 = build_function_type_list (V2HI_type_node,
11497 V2HI_type_node, V2HI_type_node,
11500 types[MIPS_SI_FTYPE_SI_SI]
11501 = build_function_type_list (intSI_type_node,
11502 intSI_type_node, intSI_type_node,
11505 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
11506 = build_function_type_list (V4QI_type_node,
11507 V4QI_type_node, V4QI_type_node,
11510 types[MIPS_SI_FTYPE_V4QI]
11511 = build_function_type_list (intSI_type_node,
11515 types[MIPS_V2HI_FTYPE_V2HI]
11516 = build_function_type_list (V2HI_type_node,
11520 types[MIPS_SI_FTYPE_SI]
11521 = build_function_type_list (intSI_type_node,
11525 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
11526 = build_function_type_list (V4QI_type_node,
11527 V2HI_type_node, V2HI_type_node,
11530 types[MIPS_V2HI_FTYPE_SI_SI]
11531 = build_function_type_list (V2HI_type_node,
11532 intSI_type_node, intSI_type_node,
11535 types[MIPS_SI_FTYPE_V2HI]
11536 = build_function_type_list (intSI_type_node,
11540 types[MIPS_V2HI_FTYPE_V4QI]
11541 = build_function_type_list (V2HI_type_node,
11545 types[MIPS_V4QI_FTYPE_V4QI_SI]
11546 = build_function_type_list (V4QI_type_node,
11547 V4QI_type_node, intSI_type_node,
11550 types[MIPS_V2HI_FTYPE_V2HI_SI]
11551 = build_function_type_list (V2HI_type_node,
11552 V2HI_type_node, intSI_type_node,
11555 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
11556 = build_function_type_list (V2HI_type_node,
11557 V4QI_type_node, V2HI_type_node,
11560 types[MIPS_SI_FTYPE_V2HI_V2HI]
11561 = build_function_type_list (intSI_type_node,
11562 V2HI_type_node, V2HI_type_node,
11565 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
11566 = build_function_type_list (intDI_type_node,
11567 intDI_type_node, V4QI_type_node, V4QI_type_node,
11570 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
11571 = build_function_type_list (intDI_type_node,
11572 intDI_type_node, V2HI_type_node, V2HI_type_node,
11575 types[MIPS_DI_FTYPE_DI_SI_SI]
11576 = build_function_type_list (intDI_type_node,
11577 intDI_type_node, intSI_type_node, intSI_type_node,
11580 types[MIPS_V4QI_FTYPE_SI]
11581 = build_function_type_list (V4QI_type_node,
11585 types[MIPS_V2HI_FTYPE_SI]
11586 = build_function_type_list (V2HI_type_node,
11590 types[MIPS_VOID_FTYPE_V4QI_V4QI]
11591 = build_function_type_list (void_type_node,
11592 V4QI_type_node, V4QI_type_node,
11595 types[MIPS_SI_FTYPE_V4QI_V4QI]
11596 = build_function_type_list (intSI_type_node,
11597 V4QI_type_node, V4QI_type_node,
11600 types[MIPS_VOID_FTYPE_V2HI_V2HI]
11601 = build_function_type_list (void_type_node,
11602 V2HI_type_node, V2HI_type_node,
11605 types[MIPS_SI_FTYPE_DI_SI]
11606 = build_function_type_list (intSI_type_node,
11607 intDI_type_node, intSI_type_node,
11610 types[MIPS_DI_FTYPE_DI_SI]
11611 = build_function_type_list (intDI_type_node,
11612 intDI_type_node, intSI_type_node,
11615 types[MIPS_VOID_FTYPE_SI_SI]
11616 = build_function_type_list (void_type_node,
11617 intSI_type_node, intSI_type_node,
11620 types[MIPS_SI_FTYPE_PTR_SI]
11621 = build_function_type_list (intSI_type_node,
11622 ptr_type_node, intSI_type_node,
11625 types[MIPS_SI_FTYPE_VOID]
11626 = build_function_type (intSI_type_node, void_list_node);
11630 types[MIPS_V4QI_FTYPE_V4QI]
11631 = build_function_type_list (V4QI_type_node,
11635 types[MIPS_SI_FTYPE_SI_SI_SI]
11636 = build_function_type_list (intSI_type_node,
11637 intSI_type_node, intSI_type_node,
11638 intSI_type_node, NULL_TREE);
11640 types[MIPS_DI_FTYPE_DI_USI_USI]
11641 = build_function_type_list (intDI_type_node,
11643 unsigned_intSI_type_node,
11644 unsigned_intSI_type_node, NULL_TREE);
11646 types[MIPS_DI_FTYPE_SI_SI]
11647 = build_function_type_list (intDI_type_node,
11648 intSI_type_node, intSI_type_node,
11651 types[MIPS_DI_FTYPE_USI_USI]
11652 = build_function_type_list (intDI_type_node,
11653 unsigned_intSI_type_node,
11654 unsigned_intSI_type_node, NULL_TREE);
11656 types[MIPS_V2HI_FTYPE_SI_SI_SI]
11657 = build_function_type_list (V2HI_type_node,
11658 intSI_type_node, intSI_type_node,
11659 intSI_type_node, NULL_TREE);
11664 /* Iterate through all of the bdesc arrays, initializing all of the
11665 builtin functions. */
11668 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
11670 if ((m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
11671 && (m->unsupported_target_flags & target_flags) == 0)
11672 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
11673 if ((d->target_flags & target_flags) == d->target_flags)
11674 add_builtin_function (d->name, types[d->function_type],
11675 d - m->bdesc + offset,
11676 BUILT_IN_MD, NULL, NULL);
11681 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
11682 .md pattern and CALL is the function expr with arguments. TARGET,
11683 if nonnull, suggests a good place to put the result.
11684 HAS_TARGET indicates the function must return something. */
11687 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
11690 rtx ops[MAX_RECOG_OPERANDS];
11696 /* We save target to ops[0]. */
11697 ops[0] = mips_prepare_builtin_target (icode, 0, target);
11701 /* We need to test if the arglist is not zero. Some instructions have extra
11702 clobber registers. */
11703 for (; i < insn_data[icode].n_operands && i <= call_expr_nargs (exp); i++, j++)
11704 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11709 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
11713 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
11717 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
11721 gcc_unreachable ();
11726 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
11727 function (TYPE says which). EXP is the tree for the function
11728 function, ICODE is the instruction that should be used to compare
11729 the first two arguments, and COND is the condition it should test.
11730 TARGET, if nonnull, suggests a good place to put the result. */
11733 mips_expand_builtin_movtf (enum mips_builtin_type type,
11734 enum insn_code icode, enum mips_fp_condition cond,
11735 rtx target, tree exp)
11737 rtx cmp_result, op0, op1;
11739 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11740 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
11741 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
11742 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
11744 icode = CODE_FOR_mips_cond_move_tf_ps;
11745 target = mips_prepare_builtin_target (icode, 0, target);
11746 if (type == MIPS_BUILTIN_MOVT)
11748 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
11749 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
11753 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
11754 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
11756 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
11760 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
11761 into TARGET otherwise. Return TARGET. */
11764 mips_builtin_branch_and_move (rtx condition, rtx target,
11765 rtx value_if_true, rtx value_if_false)
11767 rtx true_label, done_label;
11769 true_label = gen_label_rtx ();
11770 done_label = gen_label_rtx ();
11772 /* First assume that CONDITION is false. */
11773 emit_move_insn (target, value_if_false);
11775 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
11776 emit_jump_insn (gen_condjump (condition, true_label));
11777 emit_jump_insn (gen_jump (done_label));
11780 /* Fix TARGET if CONDITION is true. */
11781 emit_label (true_label);
11782 emit_move_insn (target, value_if_true);
11784 emit_label (done_label);
11788 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
11789 of the comparison instruction and COND is the condition it should test.
11790 EXP is the function call and arguments and TARGET, if nonnull,
11791 suggests a good place to put the boolean result. */
11794 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
11795 enum insn_code icode, enum mips_fp_condition cond,
11796 rtx target, tree exp)
11798 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
11802 if (target == 0 || GET_MODE (target) != SImode)
11803 target = gen_reg_rtx (SImode);
11805 /* Prepare the operands to the comparison. */
11806 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
11807 for (i = 1; i < insn_data[icode].n_operands - 1; i++, j++)
11808 ops[i] = mips_prepare_builtin_arg (icode, i, exp, j);
11810 switch (insn_data[icode].n_operands)
11813 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
11817 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
11818 ops[3], ops[4], GEN_INT (cond)));
11822 gcc_unreachable ();
11825 /* If the comparison sets more than one register, we define the result
11826 to be 0 if all registers are false and -1 if all registers are true.
11827 The value of the complete result is indeterminate otherwise. */
11828 switch (builtin_type)
11830 case MIPS_BUILTIN_CMP_ALL:
11831 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
11832 return mips_builtin_branch_and_move (condition, target,
11833 const0_rtx, const1_rtx);
11835 case MIPS_BUILTIN_CMP_UPPER:
11836 case MIPS_BUILTIN_CMP_LOWER:
11837 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
11838 condition = gen_single_cc (cmp_result, offset);
11839 return mips_builtin_branch_and_move (condition, target,
11840 const1_rtx, const0_rtx);
11843 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
11844 return mips_builtin_branch_and_move (condition, target,
11845 const1_rtx, const0_rtx);
11849 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
11850 suggests a good place to put the boolean result. */
11853 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
11855 rtx condition, cmp_result;
11858 if (target == 0 || GET_MODE (target) != SImode)
11859 target = gen_reg_rtx (SImode);
11861 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
11863 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
11868 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
11869 return mips_builtin_branch_and_move (condition, target,
11870 const1_rtx, const0_rtx);
11873 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
11874 FIRST is true if this is the first time handling this decl. */
11877 mips_encode_section_info (tree decl, rtx rtl, int first)
11879 default_encode_section_info (decl, rtl, first);
11881 if (TREE_CODE (decl) == FUNCTION_DECL)
11883 rtx symbol = XEXP (rtl, 0);
11885 if ((TARGET_LONG_CALLS && !mips_near_type_p (TREE_TYPE (decl)))
11886 || mips_far_type_p (TREE_TYPE (decl)))
11887 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
11891 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. Some code models use the incoming
11892 value of PIC_FUNCTION_ADDR_REGNUM to set up the global pointer. */
11895 mips_extra_live_on_entry (bitmap regs)
11897 if (TARGET_USE_GOT && !TARGET_ABSOLUTE_ABICALLS)
11898 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
11901 /* SImode values are represented as sign-extended to DImode. */
11904 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11906 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11907 return SIGN_EXTEND;
11912 /* MIPS implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
11915 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
11920 fputs ("\t.dtprelword\t", file);
11924 fputs ("\t.dtpreldword\t", file);
11928 gcc_unreachable ();
11930 output_addr_const (file, x);
11931 fputs ("+0x8000", file);
11934 #include "gt-mips.h"