1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save & restore registers.
77 Use a maximum gap of 0x100 in the mips16 case. We can then use
78 unextended instructions to save and restore registers, and to
79 allocate and deallocate the top part of the frame.
81 The value in the !mips16 case must be a SMALL_OPERAND and must
82 preserve the maximum stack alignment. */
83 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
85 /* True if INSN is a mips.md pattern or asm statement. */
86 #define USEFUL_INSN_P(INSN) \
88 && GET_CODE (PATTERN (INSN)) != USE \
89 && GET_CODE (PATTERN (INSN)) != CLOBBER \
90 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
91 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
93 /* If INSN is a delayed branch sequence, return the first instruction
94 in the sequence, otherwise return INSN itself. */
95 #define SEQ_BEGIN(INSN) \
96 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
97 ? XVECEXP (PATTERN (INSN), 0, 0) \
100 /* Likewise for the last instruction in a delayed branch sequence. */
101 #define SEQ_END(INSN) \
102 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
103 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
106 /* Execute the following loop body with SUBINSN set to each instruction
107 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
108 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
109 for ((SUBINSN) = SEQ_BEGIN (INSN); \
110 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
111 (SUBINSN) = NEXT_INSN (SUBINSN))
113 /* Classifies an address.
116 A natural register + offset address. The register satisfies
117 mips_valid_base_register_p and the offset is a const_arith_operand.
120 A LO_SUM rtx. The first operand is a valid base register and
121 the second operand is a symbolic address.
124 A signed 16-bit constant address.
127 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
128 enum mips_address_type {
135 /* Classifies the prototype of a builtin function. */
136 enum mips_function_type
138 MIPS_V2SF_FTYPE_V2SF,
139 MIPS_V2SF_FTYPE_V2SF_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
142 MIPS_V2SF_FTYPE_SF_SF,
143 MIPS_INT_FTYPE_V2SF_V2SF,
144 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
145 MIPS_INT_FTYPE_SF_SF,
146 MIPS_INT_FTYPE_DF_DF,
153 /* For MIPS DSP ASE */
155 MIPS_DI_FTYPE_DI_SI_SI,
156 MIPS_DI_FTYPE_DI_V2HI_V2HI,
157 MIPS_DI_FTYPE_DI_V4QI_V4QI,
159 MIPS_SI_FTYPE_PTR_SI,
163 MIPS_SI_FTYPE_V2HI_V2HI,
165 MIPS_SI_FTYPE_V4QI_V4QI,
168 MIPS_V2HI_FTYPE_SI_SI,
169 MIPS_V2HI_FTYPE_V2HI,
170 MIPS_V2HI_FTYPE_V2HI_SI,
171 MIPS_V2HI_FTYPE_V2HI_V2HI,
172 MIPS_V2HI_FTYPE_V4QI,
173 MIPS_V2HI_FTYPE_V4QI_V2HI,
175 MIPS_V4QI_FTYPE_V2HI_V2HI,
176 MIPS_V4QI_FTYPE_V4QI_SI,
177 MIPS_V4QI_FTYPE_V4QI_V4QI,
178 MIPS_VOID_FTYPE_SI_SI,
179 MIPS_VOID_FTYPE_V2HI_V2HI,
180 MIPS_VOID_FTYPE_V4QI_V4QI,
186 /* Specifies how a builtin function should be converted into rtl. */
187 enum mips_builtin_type
189 /* The builtin corresponds directly to an .md pattern. The return
190 value is mapped to operand 0 and the arguments are mapped to
191 operands 1 and above. */
194 /* The builtin corresponds directly to an .md pattern. There is no return
195 value and the arguments are mapped to operands 0 and above. */
196 MIPS_BUILTIN_DIRECT_NO_TARGET,
198 /* The builtin corresponds to a comparison instruction followed by
199 a mips_cond_move_tf_ps pattern. The first two arguments are the
200 values to compare and the second two arguments are the vector
201 operands for the movt.ps or movf.ps instruction (in assembly order). */
205 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
206 of this instruction is the result of the comparison, which has mode
207 CCV2 or CCV4. The function arguments are mapped to operands 1 and
208 above. The function's return value is an SImode boolean that is
209 true under the following conditions:
211 MIPS_BUILTIN_CMP_ANY: one of the registers is true
212 MIPS_BUILTIN_CMP_ALL: all of the registers are true
213 MIPS_BUILTIN_CMP_LOWER: the first register is true
214 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
215 MIPS_BUILTIN_CMP_ANY,
216 MIPS_BUILTIN_CMP_ALL,
217 MIPS_BUILTIN_CMP_UPPER,
218 MIPS_BUILTIN_CMP_LOWER,
220 /* As above, but the instruction only sets a single $fcc register. */
221 MIPS_BUILTIN_CMP_SINGLE,
223 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
224 MIPS_BUILTIN_BPOSGE32
227 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
228 #define MIPS_FP_CONDITIONS(MACRO) \
246 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
247 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
248 enum mips_fp_condition {
249 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
252 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
253 #define STRINGIFY(X) #X
254 static const char *const mips_fp_conditions[] = {
255 MIPS_FP_CONDITIONS (STRINGIFY)
258 /* A function to save or store a register. The first argument is the
259 register and the second is the stack slot. */
260 typedef void (*mips_save_restore_fn) (rtx, rtx);
262 struct mips16_constant;
263 struct mips_arg_info;
264 struct mips_address_info;
265 struct mips_integer_op;
268 static enum mips_symbol_type mips_classify_symbol (rtx);
269 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
270 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
271 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
272 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
273 static bool mips_classify_address (struct mips_address_info *, rtx,
274 enum machine_mode, int);
275 static bool mips_cannot_force_const_mem (rtx);
276 static int mips_symbol_insns (enum mips_symbol_type);
277 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
278 static rtx mips_force_temporary (rtx, rtx);
279 static rtx mips_split_symbol (rtx, rtx);
280 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
281 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
282 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
283 static unsigned int mips_build_lower (struct mips_integer_op *,
284 unsigned HOST_WIDE_INT);
285 static unsigned int mips_build_integer (struct mips_integer_op *,
286 unsigned HOST_WIDE_INT);
287 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static void mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static void mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static int mips_fpr_return_fields (tree, tree *);
336 static bool mips_return_in_msb (tree);
337 static rtx mips_return_fpr_pair (enum machine_mode mode,
338 enum machine_mode mode1, HOST_WIDE_INT,
339 enum machine_mode mode2, HOST_WIDE_INT);
340 static rtx mips16_gp_pseudo_reg (void);
341 static void mips16_fp_args (FILE *, int, int);
342 static void build_mips16_function_stub (FILE *);
343 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
344 static void dump_constants (struct mips16_constant *, rtx);
345 static int mips16_insn_length (rtx);
346 static int mips16_rewrite_pool_refs (rtx *, void *);
347 static void mips16_lay_out_constants (void);
348 static void mips_sim_reset (struct mips_sim *);
349 static void mips_sim_init (struct mips_sim *, state_t);
350 static void mips_sim_next_cycle (struct mips_sim *);
351 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
352 static int mips_sim_wait_regs_2 (rtx *, void *);
353 static void mips_sim_wait_regs_1 (rtx *, void *);
354 static void mips_sim_wait_regs (struct mips_sim *, rtx);
355 static void mips_sim_wait_units (struct mips_sim *, rtx);
356 static void mips_sim_wait_insn (struct mips_sim *, rtx);
357 static void mips_sim_record_set (rtx, rtx, void *);
358 static void mips_sim_issue_insn (struct mips_sim *, rtx);
359 static void mips_sim_issue_nop (struct mips_sim *);
360 static void mips_sim_finish_insn (struct mips_sim *, rtx);
361 static void vr4130_avoid_branch_rt_conflict (rtx);
362 static void vr4130_align_insns (void);
363 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
364 static void mips_avoid_hazards (void);
365 static void mips_reorg (void);
366 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
367 static bool mips_matching_cpu_name_p (const char *, const char *);
368 static const struct mips_cpu_info *mips_parse_cpu (const char *);
369 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
370 static bool mips_return_in_memory (tree, tree);
371 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
372 static void mips_macc_chains_record (rtx);
373 static void mips_macc_chains_reorder (rtx *, int);
374 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
375 static bool vr4130_true_reg_dependence_p (rtx);
376 static bool vr4130_swap_insns_p (rtx, rtx);
377 static void vr4130_reorder (rtx *, int);
378 static void mips_promote_ready (rtx *, int, int);
379 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
380 static int mips_variable_issue (FILE *, int, rtx, int);
381 static int mips_adjust_cost (rtx, rtx, rtx, int);
382 static int mips_issue_rate (void);
383 static int mips_multipass_dfa_lookahead (void);
384 static void mips_init_libfuncs (void);
385 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
387 static tree mips_build_builtin_va_list (void);
388 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
389 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
391 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
393 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
395 static bool mips_valid_pointer_mode (enum machine_mode);
396 static bool mips_vector_mode_supported_p (enum machine_mode);
397 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
398 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
399 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
400 static void mips_init_builtins (void);
401 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
402 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
403 enum insn_code, enum mips_fp_condition,
405 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
406 enum insn_code, enum mips_fp_condition,
408 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
409 static void mips_encode_section_info (tree, rtx, int);
411 /* Structure to be filled in by compute_frame_size with register
412 save masks, and offsets for the current function. */
414 struct mips_frame_info GTY(())
416 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
417 HOST_WIDE_INT var_size; /* # bytes that variables take up */
418 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
419 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
420 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
421 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
422 unsigned int mask; /* mask of saved gp registers */
423 unsigned int fmask; /* mask of saved fp registers */
424 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
425 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
426 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
427 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
428 bool initialized; /* true if frame size already calculated */
429 int num_gp; /* number of gp registers saved */
430 int num_fp; /* number of fp registers saved */
433 struct machine_function GTY(()) {
434 /* Pseudo-reg holding the value of $28 in a mips16 function which
435 refers to GP relative global variables. */
436 rtx mips16_gp_pseudo_rtx;
438 /* The number of extra stack bytes taken up by register varargs.
439 This area is allocated by the callee at the very top of the frame. */
442 /* Current frame information, calculated by compute_frame_size. */
443 struct mips_frame_info frame;
445 /* The register to use as the global pointer within this function. */
446 unsigned int global_pointer;
448 /* True if mips_adjust_insn_length should ignore an instruction's
450 bool ignore_hazard_length_p;
452 /* True if the whole function is suitable for .set noreorder and
454 bool all_noreorder_p;
456 /* True if the function is known to have an instruction that needs $gp. */
460 /* Information about a single argument. */
463 /* True if the argument is passed in a floating-point register, or
464 would have been if we hadn't run out of registers. */
467 /* The number of words passed in registers, rounded up. */
468 unsigned int reg_words;
470 /* For EABI, the offset of the first register from GP_ARG_FIRST or
471 FP_ARG_FIRST. For other ABIs, the offset of the first register from
472 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
473 comment for details).
475 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
477 unsigned int reg_offset;
479 /* The number of words that must be passed on the stack, rounded up. */
480 unsigned int stack_words;
482 /* The offset from the start of the stack overflow area of the argument's
483 first stack word. Only meaningful when STACK_WORDS is nonzero. */
484 unsigned int stack_offset;
488 /* Information about an address described by mips_address_type.
494 REG is the base register and OFFSET is the constant offset.
497 REG is the register that contains the high part of the address,
498 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
499 is the type of OFFSET's symbol.
502 SYMBOL_TYPE is the type of symbol being referenced. */
504 struct mips_address_info
506 enum mips_address_type type;
509 enum mips_symbol_type symbol_type;
513 /* One stage in a constant building sequence. These sequences have
517 A = A CODE[1] VALUE[1]
518 A = A CODE[2] VALUE[2]
521 where A is an accumulator, each CODE[i] is a binary rtl operation
522 and each VALUE[i] is a constant integer. */
523 struct mips_integer_op {
525 unsigned HOST_WIDE_INT value;
529 /* The largest number of operations needed to load an integer constant.
530 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
531 When the lowest bit is clear, we can try, but reject a sequence with
532 an extra SLL at the end. */
533 #define MIPS_MAX_INTEGER_OPS 7
536 /* Global variables for machine-dependent things. */
538 /* Threshold for data being put into the small data/bss area, instead
539 of the normal data area. */
540 int mips_section_threshold = -1;
542 /* Count the number of .file directives, so that .loc is up to date. */
543 int num_source_filenames = 0;
545 /* Count the number of sdb related labels are generated (to find block
546 start and end boundaries). */
547 int sdb_label_count = 0;
549 /* Next label # for each statement for Silicon Graphics IRIS systems. */
552 /* Linked list of all externals that are to be emitted when optimizing
553 for the global pointer if they haven't been declared by the end of
554 the program with an appropriate .comm or initialization. */
556 struct extern_list GTY (())
558 struct extern_list *next; /* next external */
559 const char *name; /* name of the external */
560 int size; /* size in bytes */
563 static GTY (()) struct extern_list *extern_head = 0;
565 /* Name of the file containing the current function. */
566 const char *current_function_file = "";
568 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
574 /* The next branch instruction is a branch likely, not branch normal. */
575 int mips_branch_likely;
577 /* The operands passed to the last cmpMM expander. */
580 /* The target cpu for code generation. */
581 enum processor_type mips_arch;
582 const struct mips_cpu_info *mips_arch_info;
584 /* The target cpu for optimization and scheduling. */
585 enum processor_type mips_tune;
586 const struct mips_cpu_info *mips_tune_info;
588 /* Which instruction set architecture to use. */
591 /* Which ABI to use. */
592 int mips_abi = MIPS_ABI_DEFAULT;
594 /* Cost information to use. */
595 const struct mips_rtx_cost_data *mips_cost;
597 /* Whether we are generating mips16 hard float code. In mips16 mode
598 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
599 -msoft-float was not specified by the user, which means that we
600 should arrange to call mips32 hard floating point code. */
601 int mips16_hard_float;
603 /* The architecture selected by -mipsN. */
604 static const struct mips_cpu_info *mips_isa_info;
606 /* If TRUE, we split addresses into their high and low parts in the RTL. */
607 int mips_split_addresses;
609 /* Mode used for saving/restoring general purpose registers. */
610 static enum machine_mode gpr_mode;
612 /* Array giving truth value on whether or not a given hard register
613 can support a given mode. */
614 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
616 /* List of all MIPS punctuation characters used by print_operand. */
617 char mips_print_operand_punct[256];
619 /* Map GCC register number to debugger register number. */
620 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
622 /* A copy of the original flag_delayed_branch: see override_options. */
623 static int mips_flag_delayed_branch;
625 static GTY (()) int mips_output_filename_first_time = 1;
627 /* mips_split_p[X] is true if symbols of type X can be split by
628 mips_split_symbol(). */
629 static bool mips_split_p[NUM_SYMBOL_TYPES];
631 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
632 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
633 if they are matched by a special .md file pattern. */
634 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
636 /* Likewise for HIGHs. */
637 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
639 /* Map hard register number to register class */
640 const enum reg_class mips_regno_to_class[] =
642 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
643 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
644 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
645 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
646 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
649 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
650 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
651 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
652 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 HI_REG, LO_REG, NO_REGS, ST_REGS,
659 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
660 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
661 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
662 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
663 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
664 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
671 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
672 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
679 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
680 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
687 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
688 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
691 /* Map register constraint character to register class. */
692 enum reg_class mips_char_to_class[256];
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sr71000", PROCESSOR_SR71000, 64 },
768 /* Default costs. If these are used for a processor we should look
769 up the actual costs. */
770 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
771 COSTS_N_INSNS (7), /* fp_mult_sf */ \
772 COSTS_N_INSNS (8), /* fp_mult_df */ \
773 COSTS_N_INSNS (23), /* fp_div_sf */ \
774 COSTS_N_INSNS (36), /* fp_div_df */ \
775 COSTS_N_INSNS (10), /* int_mult_si */ \
776 COSTS_N_INSNS (10), /* int_mult_di */ \
777 COSTS_N_INSNS (69), /* int_div_si */ \
778 COSTS_N_INSNS (69), /* int_div_di */ \
779 2, /* branch_cost */ \
780 4 /* memory_latency */
782 /* Need to replace these with the costs of calling the appropriate
784 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
785 COSTS_N_INSNS (256), /* fp_mult_sf */ \
786 COSTS_N_INSNS (256), /* fp_mult_df */ \
787 COSTS_N_INSNS (256), /* fp_div_sf */ \
788 COSTS_N_INSNS (256) /* fp_div_df */
790 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
793 COSTS_N_INSNS (2), /* fp_add */
794 COSTS_N_INSNS (4), /* fp_mult_sf */
795 COSTS_N_INSNS (5), /* fp_mult_df */
796 COSTS_N_INSNS (12), /* fp_div_sf */
797 COSTS_N_INSNS (19), /* fp_div_df */
798 COSTS_N_INSNS (12), /* int_mult_si */
799 COSTS_N_INSNS (12), /* int_mult_di */
800 COSTS_N_INSNS (35), /* int_div_si */
801 COSTS_N_INSNS (35), /* int_div_di */
803 4 /* memory_latency */
808 COSTS_N_INSNS (6), /* int_mult_si */
809 COSTS_N_INSNS (6), /* int_mult_di */
810 COSTS_N_INSNS (36), /* int_div_si */
811 COSTS_N_INSNS (36), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (36), /* int_mult_si */
818 COSTS_N_INSNS (36), /* int_mult_di */
819 COSTS_N_INSNS (37), /* int_div_si */
820 COSTS_N_INSNS (37), /* int_div_di */
822 4 /* memory_latency */
826 COSTS_N_INSNS (4), /* int_mult_si */
827 COSTS_N_INSNS (11), /* int_mult_di */
828 COSTS_N_INSNS (36), /* int_div_si */
829 COSTS_N_INSNS (68), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (11), /* int_mult_di */
841 COSTS_N_INSNS (36), /* int_div_si */
842 COSTS_N_INSNS (68), /* int_div_di */
844 4 /* memory_latency */
850 COSTS_N_INSNS (8), /* fp_add */
851 COSTS_N_INSNS (8), /* fp_mult_sf */
852 COSTS_N_INSNS (10), /* fp_mult_df */
853 COSTS_N_INSNS (34), /* fp_div_sf */
854 COSTS_N_INSNS (64), /* fp_div_df */
855 COSTS_N_INSNS (5), /* int_mult_si */
856 COSTS_N_INSNS (5), /* int_mult_di */
857 COSTS_N_INSNS (41), /* int_div_si */
858 COSTS_N_INSNS (41), /* int_div_di */
860 4 /* memory_latency */
863 COSTS_N_INSNS (4), /* fp_add */
864 COSTS_N_INSNS (4), /* fp_mult_sf */
865 COSTS_N_INSNS (5), /* fp_mult_df */
866 COSTS_N_INSNS (17), /* fp_div_sf */
867 COSTS_N_INSNS (32), /* fp_div_df */
868 COSTS_N_INSNS (5), /* int_mult_si */
869 COSTS_N_INSNS (5), /* int_mult_di */
870 COSTS_N_INSNS (41), /* int_div_si */
871 COSTS_N_INSNS (41), /* int_div_di */
873 4 /* memory_latency */
879 COSTS_N_INSNS (2), /* fp_add */
880 COSTS_N_INSNS (4), /* fp_mult_sf */
881 COSTS_N_INSNS (5), /* fp_mult_df */
882 COSTS_N_INSNS (12), /* fp_div_sf */
883 COSTS_N_INSNS (19), /* fp_div_df */
884 COSTS_N_INSNS (2), /* int_mult_si */
885 COSTS_N_INSNS (2), /* int_mult_di */
886 COSTS_N_INSNS (35), /* int_div_si */
887 COSTS_N_INSNS (35), /* int_div_di */
889 4 /* memory_latency */
892 COSTS_N_INSNS (3), /* fp_add */
893 COSTS_N_INSNS (5), /* fp_mult_sf */
894 COSTS_N_INSNS (6), /* fp_mult_df */
895 COSTS_N_INSNS (15), /* fp_div_sf */
896 COSTS_N_INSNS (16), /* fp_div_df */
897 COSTS_N_INSNS (17), /* int_mult_si */
898 COSTS_N_INSNS (17), /* int_mult_di */
899 COSTS_N_INSNS (38), /* int_div_si */
900 COSTS_N_INSNS (38), /* int_div_di */
902 6 /* memory_latency */
905 COSTS_N_INSNS (6), /* fp_add */
906 COSTS_N_INSNS (7), /* fp_mult_sf */
907 COSTS_N_INSNS (8), /* fp_mult_df */
908 COSTS_N_INSNS (23), /* fp_div_sf */
909 COSTS_N_INSNS (36), /* fp_div_df */
910 COSTS_N_INSNS (10), /* int_mult_si */
911 COSTS_N_INSNS (10), /* int_mult_di */
912 COSTS_N_INSNS (69), /* int_div_si */
913 COSTS_N_INSNS (69), /* int_div_di */
915 6 /* memory_latency */
927 /* The only costs that appear to be updated here are
928 integer multiplication. */
930 COSTS_N_INSNS (4), /* int_mult_si */
931 COSTS_N_INSNS (6), /* int_mult_di */
932 COSTS_N_INSNS (69), /* int_div_si */
933 COSTS_N_INSNS (69), /* int_div_di */
935 4 /* memory_latency */
947 COSTS_N_INSNS (6), /* fp_add */
948 COSTS_N_INSNS (4), /* fp_mult_sf */
949 COSTS_N_INSNS (5), /* fp_mult_df */
950 COSTS_N_INSNS (23), /* fp_div_sf */
951 COSTS_N_INSNS (36), /* fp_div_df */
952 COSTS_N_INSNS (5), /* int_mult_si */
953 COSTS_N_INSNS (5), /* int_mult_di */
954 COSTS_N_INSNS (36), /* int_div_si */
955 COSTS_N_INSNS (36), /* int_div_di */
957 4 /* memory_latency */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (5), /* fp_mult_sf */
962 COSTS_N_INSNS (6), /* fp_mult_df */
963 COSTS_N_INSNS (30), /* fp_div_sf */
964 COSTS_N_INSNS (59), /* fp_div_df */
965 COSTS_N_INSNS (3), /* int_mult_si */
966 COSTS_N_INSNS (4), /* int_mult_di */
967 COSTS_N_INSNS (42), /* int_div_si */
968 COSTS_N_INSNS (74), /* int_div_di */
970 4 /* memory_latency */
973 COSTS_N_INSNS (6), /* fp_add */
974 COSTS_N_INSNS (5), /* fp_mult_sf */
975 COSTS_N_INSNS (6), /* fp_mult_df */
976 COSTS_N_INSNS (30), /* fp_div_sf */
977 COSTS_N_INSNS (59), /* fp_div_df */
978 COSTS_N_INSNS (5), /* int_mult_si */
979 COSTS_N_INSNS (9), /* int_mult_di */
980 COSTS_N_INSNS (42), /* int_div_si */
981 COSTS_N_INSNS (74), /* int_div_di */
983 4 /* memory_latency */
986 /* The only costs that are changed here are
987 integer multiplication. */
988 COSTS_N_INSNS (6), /* fp_add */
989 COSTS_N_INSNS (7), /* fp_mult_sf */
990 COSTS_N_INSNS (8), /* fp_mult_df */
991 COSTS_N_INSNS (23), /* fp_div_sf */
992 COSTS_N_INSNS (36), /* fp_div_df */
993 COSTS_N_INSNS (5), /* int_mult_si */
994 COSTS_N_INSNS (9), /* int_mult_di */
995 COSTS_N_INSNS (69), /* int_div_si */
996 COSTS_N_INSNS (69), /* int_div_di */
998 4 /* memory_latency */
1004 /* The only costs that are changed here are
1005 integer multiplication. */
1006 COSTS_N_INSNS (6), /* fp_add */
1007 COSTS_N_INSNS (7), /* fp_mult_sf */
1008 COSTS_N_INSNS (8), /* fp_mult_df */
1009 COSTS_N_INSNS (23), /* fp_div_sf */
1010 COSTS_N_INSNS (36), /* fp_div_df */
1011 COSTS_N_INSNS (3), /* int_mult_si */
1012 COSTS_N_INSNS (8), /* int_mult_di */
1013 COSTS_N_INSNS (69), /* int_div_si */
1014 COSTS_N_INSNS (69), /* int_div_di */
1015 1, /* branch_cost */
1016 4 /* memory_latency */
1019 COSTS_N_INSNS (4), /* fp_add */
1020 COSTS_N_INSNS (4), /* fp_mult_sf */
1021 COSTS_N_INSNS (4), /* fp_mult_df */
1022 COSTS_N_INSNS (24), /* fp_div_sf */
1023 COSTS_N_INSNS (32), /* fp_div_df */
1024 COSTS_N_INSNS (3), /* int_mult_si */
1025 COSTS_N_INSNS (4), /* int_mult_di */
1026 COSTS_N_INSNS (36), /* int_div_si */
1027 COSTS_N_INSNS (68), /* int_div_di */
1028 1, /* branch_cost */
1029 4 /* memory_latency */
1037 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1038 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1039 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1042 /* Initialize the GCC target structure. */
1043 #undef TARGET_ASM_ALIGNED_HI_OP
1044 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1045 #undef TARGET_ASM_ALIGNED_SI_OP
1046 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1047 #undef TARGET_ASM_ALIGNED_DI_OP
1048 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1050 #undef TARGET_ASM_FUNCTION_PROLOGUE
1051 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1052 #undef TARGET_ASM_FUNCTION_EPILOGUE
1053 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1054 #undef TARGET_ASM_SELECT_RTX_SECTION
1055 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1056 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1057 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1059 #undef TARGET_SCHED_REORDER
1060 #define TARGET_SCHED_REORDER mips_sched_reorder
1061 #undef TARGET_SCHED_VARIABLE_ISSUE
1062 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1063 #undef TARGET_SCHED_ADJUST_COST
1064 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1065 #undef TARGET_SCHED_ISSUE_RATE
1066 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1067 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1068 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1069 mips_multipass_dfa_lookahead
1071 #undef TARGET_DEFAULT_TARGET_FLAGS
1072 #define TARGET_DEFAULT_TARGET_FLAGS \
1074 | TARGET_CPU_DEFAULT \
1075 | TARGET_ENDIAN_DEFAULT \
1076 | TARGET_FP_EXCEPTIONS_DEFAULT \
1077 | MASK_CHECK_ZERO_DIV \
1079 #undef TARGET_HANDLE_OPTION
1080 #define TARGET_HANDLE_OPTION mips_handle_option
1082 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1083 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1085 #undef TARGET_VALID_POINTER_MODE
1086 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1087 #undef TARGET_RTX_COSTS
1088 #define TARGET_RTX_COSTS mips_rtx_costs
1089 #undef TARGET_ADDRESS_COST
1090 #define TARGET_ADDRESS_COST mips_address_cost
1092 #undef TARGET_IN_SMALL_DATA_P
1093 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1095 #undef TARGET_MACHINE_DEPENDENT_REORG
1096 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1098 #undef TARGET_ASM_FILE_START
1099 #undef TARGET_ASM_FILE_END
1100 #define TARGET_ASM_FILE_START mips_file_start
1101 #define TARGET_ASM_FILE_END mips_file_end
1102 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1103 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1105 #undef TARGET_INIT_LIBFUNCS
1106 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1108 #undef TARGET_BUILD_BUILTIN_VA_LIST
1109 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1110 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1111 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1113 #undef TARGET_PROMOTE_FUNCTION_ARGS
1114 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1115 #undef TARGET_PROMOTE_FUNCTION_RETURN
1116 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1117 #undef TARGET_PROMOTE_PROTOTYPES
1118 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1120 #undef TARGET_RETURN_IN_MEMORY
1121 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1122 #undef TARGET_RETURN_IN_MSB
1123 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1125 #undef TARGET_ASM_OUTPUT_MI_THUNK
1126 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1127 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1128 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1130 #undef TARGET_SETUP_INCOMING_VARARGS
1131 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1132 #undef TARGET_STRICT_ARGUMENT_NAMING
1133 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1134 #undef TARGET_MUST_PASS_IN_STACK
1135 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1136 #undef TARGET_PASS_BY_REFERENCE
1137 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1138 #undef TARGET_CALLEE_COPIES
1139 #define TARGET_CALLEE_COPIES mips_callee_copies
1140 #undef TARGET_ARG_PARTIAL_BYTES
1141 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1143 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1144 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1146 #undef TARGET_INIT_BUILTINS
1147 #define TARGET_INIT_BUILTINS mips_init_builtins
1148 #undef TARGET_EXPAND_BUILTIN
1149 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1151 #undef TARGET_HAVE_TLS
1152 #define TARGET_HAVE_TLS HAVE_AS_TLS
1154 #undef TARGET_CANNOT_FORCE_CONST_MEM
1155 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1157 #undef TARGET_ENCODE_SECTION_INFO
1158 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1160 #undef TARGET_ATTRIBUTE_TABLE
1161 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1163 struct gcc_target targetm = TARGET_INITIALIZER;
1165 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1167 static enum mips_symbol_type
1168 mips_classify_symbol (rtx x)
1170 if (GET_CODE (x) == LABEL_REF)
1173 return SYMBOL_CONSTANT_POOL;
1174 if (TARGET_ABICALLS)
1175 return SYMBOL_GOT_LOCAL;
1176 return SYMBOL_GENERAL;
1179 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1181 if (SYMBOL_REF_TLS_MODEL (x))
1184 if (CONSTANT_POOL_ADDRESS_P (x))
1187 return SYMBOL_CONSTANT_POOL;
1189 if (TARGET_ABICALLS)
1190 return SYMBOL_GOT_LOCAL;
1192 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1193 return SYMBOL_SMALL_DATA;
1195 return SYMBOL_GENERAL;
1198 if (SYMBOL_REF_SMALL_P (x))
1199 return SYMBOL_SMALL_DATA;
1201 if (TARGET_ABICALLS)
1203 if (SYMBOL_REF_DECL (x) == 0)
1204 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
1206 /* There are three cases to consider:
1208 - o32 PIC (either with or without explicit relocs)
1209 - n32/n64 PIC without explicit relocs
1210 - n32/n64 PIC with explicit relocs
1212 In the first case, both local and global accesses will use an
1213 R_MIPS_GOT16 relocation. We must correctly predict which of
1214 the two semantics (local or global) the assembler and linker
1215 will apply. The choice doesn't depend on the symbol's
1216 visibility, so we deliberately ignore decl_visibility and
1219 In the second case, the assembler will not use R_MIPS_GOT16
1220 relocations, but it chooses between local and global accesses
1221 in the same way as for o32 PIC.
1223 In the third case we have more freedom since both forms of
1224 access will work for any kind of symbol. However, there seems
1225 little point in doing things differently. */
1226 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
1227 return SYMBOL_GOT_GLOBAL;
1229 return SYMBOL_GOT_LOCAL;
1232 return SYMBOL_GENERAL;
1236 /* Split X into a base and a constant offset, storing them in *BASE
1237 and *OFFSET respectively. */
1240 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1244 if (GET_CODE (x) == CONST)
1247 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1249 *offset += INTVAL (XEXP (x, 1));
1256 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1257 to the same object as SYMBOL. */
1260 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1262 if (GET_CODE (symbol) != SYMBOL_REF)
1265 if (CONSTANT_POOL_ADDRESS_P (symbol)
1267 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1270 if (SYMBOL_REF_DECL (symbol) != 0
1272 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1279 /* Return true if X is a symbolic constant that can be calculated in
1280 the same way as a bare symbol. If it is, store the type of the
1281 symbol in *SYMBOL_TYPE. */
1284 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1286 HOST_WIDE_INT offset;
1288 mips_split_const (x, &x, &offset);
1289 if (UNSPEC_ADDRESS_P (x))
1290 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1291 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1293 *symbol_type = mips_classify_symbol (x);
1294 if (*symbol_type == SYMBOL_TLS)
1303 /* Check whether a nonzero offset is valid for the underlying
1305 switch (*symbol_type)
1307 case SYMBOL_GENERAL:
1308 case SYMBOL_64_HIGH:
1311 /* If the target has 64-bit pointers and the object file only
1312 supports 32-bit symbols, the values of those symbols will be
1313 sign-extended. In this case we can't allow an arbitrary offset
1314 in case the 32-bit value X + OFFSET has a different sign from X. */
1315 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1316 return mips_offset_within_object_p (x, offset);
1318 /* In other cases the relocations can handle any offset. */
1321 case SYMBOL_CONSTANT_POOL:
1322 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1323 In this case, we no longer have access to the underlying constant,
1324 but the original symbol-based access was known to be valid. */
1325 if (GET_CODE (x) == LABEL_REF)
1330 case SYMBOL_SMALL_DATA:
1331 /* Make sure that the offset refers to something within the
1332 underlying object. This should guarantee that the final
1333 PC- or GP-relative offset is within the 16-bit limit. */
1334 return mips_offset_within_object_p (x, offset);
1336 case SYMBOL_GOT_LOCAL:
1337 case SYMBOL_GOTOFF_PAGE:
1338 /* The linker should provide enough local GOT entries for a
1339 16-bit offset. Larger offsets may lead to GOT overflow. */
1340 return SMALL_OPERAND (offset);
1342 case SYMBOL_GOT_GLOBAL:
1343 case SYMBOL_GOTOFF_GLOBAL:
1344 case SYMBOL_GOTOFF_CALL:
1345 case SYMBOL_GOTOFF_LOADGP:
1350 case SYMBOL_GOTTPREL:
1358 /* Return true if X is a symbolic constant whose value is not split
1359 into separate relocations. */
1362 mips_atomic_symbolic_constant_p (rtx x)
1364 enum mips_symbol_type type;
1365 return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
1369 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1372 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1374 if (regno >= FIRST_PSEUDO_REGISTER)
1378 regno = reg_renumber[regno];
1381 /* These fake registers will be eliminated to either the stack or
1382 hard frame pointer, both of which are usually valid base registers.
1383 Reload deals with the cases where the eliminated form isn't valid. */
1384 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1387 /* In mips16 mode, the stack pointer can only address word and doubleword
1388 values, nothing smaller. There are two problems here:
1390 (a) Instantiating virtual registers can introduce new uses of the
1391 stack pointer. If these virtual registers are valid addresses,
1392 the stack pointer should be too.
1394 (b) Most uses of the stack pointer are not made explicit until
1395 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1396 We don't know until that stage whether we'll be eliminating to the
1397 stack pointer (which needs the restriction) or the hard frame
1398 pointer (which doesn't).
1400 All in all, it seems more consistent to only enforce this restriction
1401 during and after reload. */
1402 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1403 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1405 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1409 /* Return true if X is a valid base register for the given mode.
1410 Allow only hard registers if STRICT. */
1413 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1415 if (!strict && GET_CODE (x) == SUBREG)
1419 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1423 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1424 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1427 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1428 enum machine_mode mode)
1430 switch (symbol_type)
1432 case SYMBOL_GENERAL:
1433 return !TARGET_MIPS16;
1435 case SYMBOL_SMALL_DATA:
1438 case SYMBOL_CONSTANT_POOL:
1439 /* PC-relative addressing is only available for lw and ld. */
1440 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1442 case SYMBOL_GOT_LOCAL:
1445 case SYMBOL_GOT_GLOBAL:
1446 /* The address will have to be loaded from the GOT first. */
1453 case SYMBOL_GOTTPREL:
1457 case SYMBOL_GOTOFF_PAGE:
1458 case SYMBOL_GOTOFF_GLOBAL:
1459 case SYMBOL_GOTOFF_CALL:
1460 case SYMBOL_GOTOFF_LOADGP:
1461 case SYMBOL_64_HIGH:
1470 /* Return true if X is a valid address for machine mode MODE. If it is,
1471 fill in INFO appropriately. STRICT is true if we should only accept
1472 hard base registers. */
1475 mips_classify_address (struct mips_address_info *info, rtx x,
1476 enum machine_mode mode, int strict)
1478 switch (GET_CODE (x))
1482 info->type = ADDRESS_REG;
1484 info->offset = const0_rtx;
1485 return mips_valid_base_register_p (info->reg, mode, strict);
1488 info->type = ADDRESS_REG;
1489 info->reg = XEXP (x, 0);
1490 info->offset = XEXP (x, 1);
1491 return (mips_valid_base_register_p (info->reg, mode, strict)
1492 && const_arith_operand (info->offset, VOIDmode));
1495 info->type = ADDRESS_LO_SUM;
1496 info->reg = XEXP (x, 0);
1497 info->offset = XEXP (x, 1);
1498 return (mips_valid_base_register_p (info->reg, mode, strict)
1499 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1500 && mips_symbolic_address_p (info->symbol_type, mode)
1501 && mips_lo_relocs[info->symbol_type] != 0);
1504 /* Small-integer addresses don't occur very often, but they
1505 are legitimate if $0 is a valid base register. */
1506 info->type = ADDRESS_CONST_INT;
1507 return !TARGET_MIPS16 && SMALL_INT (x);
1512 info->type = ADDRESS_SYMBOLIC;
1513 return (mips_symbolic_constant_p (x, &info->symbol_type)
1514 && mips_symbolic_address_p (info->symbol_type, mode)
1515 && !mips_split_p[info->symbol_type]);
1522 /* Return true if X is a thread-local symbol. */
1525 mips_tls_operand_p (rtx x)
1527 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1530 /* Return true if X can not be forced into a constant pool. */
1533 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1535 return mips_tls_operand_p (*x);
1538 /* Return true if X can not be forced into a constant pool. */
1541 mips_cannot_force_const_mem (rtx x)
1543 if (! TARGET_HAVE_TLS)
1546 return for_each_rtx (&x, &mips_tls_symbol_ref_1, 0);
1549 /* Return the number of instructions needed to load a symbol of the
1550 given type into a register. If valid in an address, the same number
1551 of instructions are needed for loads and stores. Treat extended
1552 mips16 instructions as two instructions. */
1555 mips_symbol_insns (enum mips_symbol_type type)
1559 case SYMBOL_GENERAL:
1560 /* In mips16 code, general symbols must be fetched from the
1565 /* When using 64-bit symbols, we need 5 preparatory instructions,
1568 lui $at,%highest(symbol)
1569 daddiu $at,$at,%higher(symbol)
1571 daddiu $at,$at,%hi(symbol)
1574 The final address is then $at + %lo(symbol). With 32-bit
1575 symbols we just need a preparatory lui. */
1576 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1578 case SYMBOL_SMALL_DATA:
1581 case SYMBOL_CONSTANT_POOL:
1582 /* This case is for mips16 only. Assume we'll need an
1583 extended instruction. */
1586 case SYMBOL_GOT_LOCAL:
1587 case SYMBOL_GOT_GLOBAL:
1588 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1589 the local/global classification is accurate. See override_options
1592 The worst cases are:
1594 (1) For local symbols when generating o32 or o64 code. The assembler
1600 ...and the final address will be $at + %lo(symbol).
1602 (2) For global symbols when -mxgot. The assembler will use:
1604 lui $at,%got_hi(symbol)
1607 ...and the final address will be $at + %got_lo(symbol). */
1610 case SYMBOL_GOTOFF_PAGE:
1611 case SYMBOL_GOTOFF_GLOBAL:
1612 case SYMBOL_GOTOFF_CALL:
1613 case SYMBOL_GOTOFF_LOADGP:
1614 case SYMBOL_64_HIGH:
1620 case SYMBOL_GOTTPREL:
1622 /* Check whether the offset is a 16- or 32-bit value. */
1623 return mips_split_p[type] ? 2 : 1;
1626 /* We don't treat a bare TLS symbol as a constant. */
1632 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1635 mips_stack_address_p (rtx x, enum machine_mode mode)
1637 struct mips_address_info addr;
1639 return (mips_classify_address (&addr, x, mode, false)
1640 && addr.type == ADDRESS_REG
1641 && addr.reg == stack_pointer_rtx);
1644 /* Return true if a value at OFFSET bytes from BASE can be accessed
1645 using an unextended mips16 instruction. MODE is the mode of the
1648 Usually the offset in an unextended instruction is a 5-bit field.
1649 The offset is unsigned and shifted left once for HIs, twice
1650 for SIs, and so on. An exception is SImode accesses off the
1651 stack pointer, which have an 8-bit immediate field. */
1654 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1657 && GET_CODE (offset) == CONST_INT
1658 && INTVAL (offset) >= 0
1659 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1661 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1662 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1663 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1669 /* Return the number of instructions needed to load or store a value
1670 of mode MODE at X. Return 0 if X isn't valid for MODE.
1672 For mips16 code, count extended instructions as two instructions. */
1675 mips_address_insns (rtx x, enum machine_mode mode)
1677 struct mips_address_info addr;
1680 if (mode == BLKmode)
1681 /* BLKmode is used for single unaligned loads and stores. */
1684 /* Each word of a multi-word value will be accessed individually. */
1685 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1687 if (mips_classify_address (&addr, x, mode, false))
1692 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1696 case ADDRESS_LO_SUM:
1697 return (TARGET_MIPS16 ? factor * 2 : factor);
1699 case ADDRESS_CONST_INT:
1702 case ADDRESS_SYMBOLIC:
1703 return factor * mips_symbol_insns (addr.symbol_type);
1709 /* Likewise for constant X. */
1712 mips_const_insns (rtx x)
1714 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1715 enum mips_symbol_type symbol_type;
1716 HOST_WIDE_INT offset;
1718 switch (GET_CODE (x))
1722 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1723 || !mips_split_p[symbol_type])
1730 /* Unsigned 8-bit constants can be loaded using an unextended
1731 LI instruction. Unsigned 16-bit constants can be loaded
1732 using an extended LI. Negative constants must be loaded
1733 using LI and then negated. */
1734 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1735 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1736 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1737 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1740 return mips_build_integer (codes, INTVAL (x));
1744 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1750 /* See if we can refer to X directly. */
1751 if (mips_symbolic_constant_p (x, &symbol_type))
1752 return mips_symbol_insns (symbol_type);
1754 /* Otherwise try splitting the constant into a base and offset.
1755 16-bit offsets can be added using an extra addiu. Larger offsets
1756 must be calculated separately and then added to the base. */
1757 mips_split_const (x, &x, &offset);
1760 int n = mips_const_insns (x);
1763 if (SMALL_OPERAND (offset))
1766 return n + 1 + mips_build_integer (codes, offset);
1773 return mips_symbol_insns (mips_classify_symbol (x));
1781 /* Return the number of instructions needed for memory reference X.
1782 Count extended mips16 instructions as two instructions. */
1785 mips_fetch_insns (rtx x)
1787 gcc_assert (MEM_P (x));
1788 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1792 /* Return the number of instructions needed for an integer division. */
1795 mips_idiv_insns (void)
1800 if (TARGET_CHECK_ZERO_DIV)
1802 if (GENERATE_DIVIDE_TRAPS)
1808 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1813 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1814 returns a nonzero value if X is a legitimate address for a memory
1815 operand of the indicated MODE. STRICT is nonzero if this function
1816 is called during reload. */
1819 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1821 struct mips_address_info addr;
1823 return mips_classify_address (&addr, x, mode, strict);
1827 /* Copy VALUE to a register and return that register. If new psuedos
1828 are allowed, copy it into a new register, otherwise use DEST. */
1831 mips_force_temporary (rtx dest, rtx value)
1833 if (!no_new_pseudos)
1834 return force_reg (Pmode, value);
1837 emit_move_insn (copy_rtx (dest), value);
1843 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1844 and is used to load the high part into a register. */
1847 mips_split_symbol (rtx temp, rtx addr)
1852 high = mips16_gp_pseudo_reg ();
1854 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1855 return gen_rtx_LO_SUM (Pmode, high, addr);
1859 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1860 type SYMBOL_TYPE. */
1863 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1866 HOST_WIDE_INT offset;
1868 mips_split_const (address, &base, &offset);
1869 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1870 UNSPEC_ADDRESS_FIRST + symbol_type);
1871 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1875 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1876 high part to BASE and return the result. Just return BASE otherwise.
1877 TEMP is available as a temporary register if needed.
1879 The returned expression can be used as the first operand to a LO_SUM. */
1882 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1883 enum mips_symbol_type symbol_type)
1885 if (mips_split_p[symbol_type])
1887 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1888 addr = mips_force_temporary (temp, addr);
1889 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1895 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1896 mips_force_temporary; it is only needed when OFFSET is not a
1900 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1902 if (!SMALL_OPERAND (offset))
1907 /* Load the full offset into a register so that we can use
1908 an unextended instruction for the address itself. */
1909 high = GEN_INT (offset);
1914 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1915 high = GEN_INT (CONST_HIGH_PART (offset));
1916 offset = CONST_LOW_PART (offset);
1918 high = mips_force_temporary (temp, high);
1919 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1921 return plus_constant (reg, offset);
1924 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1925 referencing, and TYPE is the symbol type to use (either global
1926 dynamic or local dynamic). V0 is an RTX for the return value
1927 location. The entire insn sequence is returned. */
1929 static GTY(()) rtx mips_tls_symbol;
1932 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1934 rtx insn, loc, tga, a0;
1936 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
1938 if (!mips_tls_symbol)
1939 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
1941 loc = mips_unspec_address (sym, type);
1945 emit_insn (gen_rtx_SET (Pmode, a0,
1946 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
1947 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
1948 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
1949 CONST_OR_PURE_CALL_P (insn) = 1;
1950 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
1951 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
1952 insn = get_insns ();
1959 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
1960 return value will be a valid address and move_operand (either a REG
1964 mips_legitimize_tls_address (rtx loc)
1966 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
1967 enum tls_model model;
1969 v0 = gen_rtx_REG (Pmode, GP_RETURN);
1970 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
1972 model = SYMBOL_REF_TLS_MODEL (loc);
1976 case TLS_MODEL_GLOBAL_DYNAMIC:
1977 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
1978 dest = gen_reg_rtx (Pmode);
1979 emit_libcall_block (insn, dest, v0, loc);
1982 case TLS_MODEL_LOCAL_DYNAMIC:
1983 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
1984 tmp1 = gen_reg_rtx (Pmode);
1986 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
1987 share the LDM result with other LD model accesses. */
1988 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1990 emit_libcall_block (insn, tmp1, v0, eqv);
1992 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
1993 dest = gen_rtx_LO_SUM (Pmode, tmp2,
1994 mips_unspec_address (loc, SYMBOL_DTPREL));
1997 case TLS_MODEL_INITIAL_EXEC:
1998 tmp1 = gen_reg_rtx (Pmode);
1999 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2000 if (Pmode == DImode)
2002 emit_insn (gen_tls_get_tp_di (v1));
2003 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2007 emit_insn (gen_tls_get_tp_si (v1));
2008 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2010 dest = gen_reg_rtx (Pmode);
2011 emit_insn (gen_add3_insn (dest, tmp1, v1));
2014 case TLS_MODEL_LOCAL_EXEC:
2016 if (Pmode == DImode)
2017 emit_insn (gen_tls_get_tp_di (v1));
2019 emit_insn (gen_tls_get_tp_si (v1));
2021 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2022 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2023 mips_unspec_address (loc, SYMBOL_TPREL));
2033 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2034 be legitimized in a way that the generic machinery might not expect,
2035 put the new address in *XLOC and return true. MODE is the mode of
2036 the memory being accessed. */
2039 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2041 enum mips_symbol_type symbol_type;
2043 if (mips_tls_operand_p (*xloc))
2045 *xloc = mips_legitimize_tls_address (*xloc);
2049 /* See if the address can split into a high part and a LO_SUM. */
2050 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2051 && mips_symbolic_address_p (symbol_type, mode)
2052 && mips_split_p[symbol_type])
2054 *xloc = mips_split_symbol (0, *xloc);
2058 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2060 /* Handle REG + CONSTANT using mips_add_offset. */
2063 reg = XEXP (*xloc, 0);
2064 if (!mips_valid_base_register_p (reg, mode, 0))
2065 reg = copy_to_mode_reg (Pmode, reg);
2066 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2074 /* Subroutine of mips_build_integer (with the same interface).
2075 Assume that the final action in the sequence should be a left shift. */
2078 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2080 unsigned int i, shift;
2082 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2083 since signed numbers are easier to load than unsigned ones. */
2085 while ((value & 1) == 0)
2086 value /= 2, shift++;
2088 i = mips_build_integer (codes, value);
2089 codes[i].code = ASHIFT;
2090 codes[i].value = shift;
2095 /* As for mips_build_shift, but assume that the final action will be
2096 an IOR or PLUS operation. */
2099 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2101 unsigned HOST_WIDE_INT high;
2104 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2105 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2107 /* The constant is too complex to load with a simple lui/ori pair
2108 so our goal is to clear as many trailing zeros as possible.
2109 In this case, we know bit 16 is set and that the low 16 bits
2110 form a negative number. If we subtract that number from VALUE,
2111 we will clear at least the lowest 17 bits, maybe more. */
2112 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2113 codes[i].code = PLUS;
2114 codes[i].value = CONST_LOW_PART (value);
2118 i = mips_build_integer (codes, high);
2119 codes[i].code = IOR;
2120 codes[i].value = value & 0xffff;
2126 /* Fill CODES with a sequence of rtl operations to load VALUE.
2127 Return the number of operations needed. */
2130 mips_build_integer (struct mips_integer_op *codes,
2131 unsigned HOST_WIDE_INT value)
2133 if (SMALL_OPERAND (value)
2134 || SMALL_OPERAND_UNSIGNED (value)
2135 || LUI_OPERAND (value))
2137 /* The value can be loaded with a single instruction. */
2138 codes[0].code = UNKNOWN;
2139 codes[0].value = value;
2142 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2144 /* Either the constant is a simple LUI/ORI combination or its
2145 lowest bit is set. We don't want to shift in this case. */
2146 return mips_build_lower (codes, value);
2148 else if ((value & 0xffff) == 0)
2150 /* The constant will need at least three actions. The lowest
2151 16 bits are clear, so the final action will be a shift. */
2152 return mips_build_shift (codes, value);
2156 /* The final action could be a shift, add or inclusive OR.
2157 Rather than use a complex condition to select the best
2158 approach, try both mips_build_shift and mips_build_lower
2159 and pick the one that gives the shortest sequence.
2160 Note that this case is only used once per constant. */
2161 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2162 unsigned int cost, alt_cost;
2164 cost = mips_build_shift (codes, value);
2165 alt_cost = mips_build_lower (alt_codes, value);
2166 if (alt_cost < cost)
2168 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2176 /* Move VALUE into register DEST. */
2179 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
2181 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2182 enum machine_mode mode;
2183 unsigned int i, cost;
2186 mode = GET_MODE (dest);
2187 cost = mips_build_integer (codes, value);
2189 /* Apply each binary operation to X. Invariant: X is a legitimate
2190 source operand for a SET pattern. */
2191 x = GEN_INT (codes[0].value);
2192 for (i = 1; i < cost; i++)
2195 emit_move_insn (dest, x), x = dest;
2197 x = force_reg (mode, x);
2198 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2201 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2205 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2206 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2210 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2213 HOST_WIDE_INT offset;
2214 enum mips_symbol_type symbol_type;
2216 /* Split moves of big integers into smaller pieces. In mips16 code,
2217 it's better to force the constant into memory instead. */
2218 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
2220 mips_move_integer (dest, INTVAL (src));
2224 if (mips_tls_operand_p (src))
2226 emit_move_insn (dest, mips_legitimize_tls_address (src));
2230 /* See if the symbol can be split. For mips16, this is often worse than
2231 forcing it in the constant pool since it needs the single-register form
2232 of addiu or daddiu. */
2234 && mips_symbolic_constant_p (src, &symbol_type)
2235 && mips_split_p[symbol_type])
2237 emit_move_insn (dest, mips_split_symbol (dest, src));
2241 /* If we have (const (plus symbol offset)), load the symbol first
2242 and then add in the offset. This is usually better than forcing
2243 the constant into memory, at least in non-mips16 code. */
2244 mips_split_const (src, &base, &offset);
2247 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2249 base = mips_force_temporary (dest, base);
2250 emit_move_insn (dest, mips_add_offset (0, base, offset));
2254 src = force_const_mem (mode, src);
2256 /* When using explicit relocs, constant pool references are sometimes
2257 not legitimate addresses. */
2258 if (!memory_operand (src, VOIDmode))
2259 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2260 emit_move_insn (dest, src);
2264 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2265 sequence that is valid. */
2268 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2270 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2272 emit_move_insn (dest, force_reg (mode, src));
2276 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2277 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2278 && REG_P (src) && MD_REG_P (REGNO (src))
2279 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2281 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2282 if (GET_MODE_SIZE (mode) <= 4)
2283 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2284 gen_rtx_REG (SImode, REGNO (src)),
2285 gen_rtx_REG (SImode, other_regno)));
2287 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2288 gen_rtx_REG (DImode, REGNO (src)),
2289 gen_rtx_REG (DImode, other_regno)));
2293 /* We need to deal with constants that would be legitimate
2294 immediate_operands but not legitimate move_operands. */
2295 if (CONSTANT_P (src) && !move_operand (src, mode))
2297 mips_legitimize_const_move (mode, dest, src);
2298 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2304 /* We need a lot of little routines to check constant values on the
2305 mips16. These are used to figure out how long the instruction will
2306 be. It would be much better to do this using constraints, but
2307 there aren't nearly enough letters available. */
2310 m16_check_op (rtx op, int low, int high, int mask)
2312 return (GET_CODE (op) == CONST_INT
2313 && INTVAL (op) >= low
2314 && INTVAL (op) <= high
2315 && (INTVAL (op) & mask) == 0);
2319 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2321 return m16_check_op (op, 0x1, 0x8, 0);
2325 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2327 return m16_check_op (op, - 0x8, 0x7, 0);
2331 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2333 return m16_check_op (op, - 0x7, 0x8, 0);
2337 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2339 return m16_check_op (op, - 0x10, 0xf, 0);
2343 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2345 return m16_check_op (op, - 0xf, 0x10, 0);
2349 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2351 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2355 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2357 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2361 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2363 return m16_check_op (op, - 0x80, 0x7f, 0);
2367 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2369 return m16_check_op (op, - 0x7f, 0x80, 0);
2373 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2375 return m16_check_op (op, 0x0, 0xff, 0);
2379 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2381 return m16_check_op (op, - 0xff, 0x0, 0);
2385 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2387 return m16_check_op (op, - 0x1, 0xfe, 0);
2391 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2393 return m16_check_op (op, 0x0, 0xff << 2, 3);
2397 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2399 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2403 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2405 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2409 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2411 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2415 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2417 enum machine_mode mode = GET_MODE (x);
2418 bool float_mode_p = FLOAT_MODE_P (mode);
2425 /* A number between 1 and 8 inclusive is efficient for a shift.
2426 Otherwise, we will need an extended instruction. */
2427 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2428 || (outer_code) == LSHIFTRT)
2430 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2433 *total = COSTS_N_INSNS (1);
2437 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2438 if ((outer_code) == XOR
2439 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2445 /* We may be able to use slt or sltu for a comparison with a
2446 signed 16 bit value. (The boundary conditions aren't quite
2447 right, but this is just a heuristic anyhow.) */
2448 if (((outer_code) == LT || (outer_code) == LE
2449 || (outer_code) == GE || (outer_code) == GT
2450 || (outer_code) == LTU || (outer_code) == LEU
2451 || (outer_code) == GEU || (outer_code) == GTU)
2452 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2458 /* Equality comparisons with 0 are cheap. */
2459 if (((outer_code) == EQ || (outer_code) == NE)
2466 /* Constants in the range 0...255 can be loaded with an unextended
2467 instruction. They are therefore as cheap as a register move.
2469 Given the choice between "li R1,0...255" and "move R1,R2"
2470 (where R2 is a known constant), it is usually better to use "li",
2471 since we do not want to unnecessarily extend the lifetime
2473 if (outer_code == SET
2475 && INTVAL (x) < 256)
2483 /* These can be used anywhere. */
2488 /* Otherwise fall through to the handling below because
2489 we'll need to construct the constant. */
2495 if (LEGITIMATE_CONSTANT_P (x))
2497 *total = COSTS_N_INSNS (1);
2502 /* The value will need to be fetched from the constant pool. */
2503 *total = CONSTANT_POOL_COST;
2509 /* If the address is legitimate, return the number of
2510 instructions it needs, otherwise use the default handling. */
2511 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2514 *total = COSTS_N_INSNS (n + 1);
2521 *total = COSTS_N_INSNS (6);
2525 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2531 if (mode == DImode && !TARGET_64BIT)
2533 *total = COSTS_N_INSNS (2);
2541 if (mode == DImode && !TARGET_64BIT)
2543 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2551 *total = COSTS_N_INSNS (1);
2553 *total = COSTS_N_INSNS (4);
2557 *total = COSTS_N_INSNS (1);
2564 *total = mips_cost->fp_add;
2568 else if (mode == DImode && !TARGET_64BIT)
2570 *total = COSTS_N_INSNS (4);
2576 if (mode == DImode && !TARGET_64BIT)
2578 *total = COSTS_N_INSNS (4);
2585 *total = mips_cost->fp_mult_sf;
2587 else if (mode == DFmode)
2588 *total = mips_cost->fp_mult_df;
2590 else if (mode == SImode)
2591 *total = mips_cost->int_mult_si;
2594 *total = mips_cost->int_mult_di;
2603 *total = mips_cost->fp_div_sf;
2605 *total = mips_cost->fp_div_df;
2614 *total = mips_cost->int_div_di;
2616 *total = mips_cost->int_div_si;
2621 /* A sign extend from SImode to DImode in 64 bit mode is often
2622 zero instructions, because the result can often be used
2623 directly by another instruction; we'll call it one. */
2624 if (TARGET_64BIT && mode == DImode
2625 && GET_MODE (XEXP (x, 0)) == SImode)
2626 *total = COSTS_N_INSNS (1);
2628 *total = COSTS_N_INSNS (2);
2632 if (TARGET_64BIT && mode == DImode
2633 && GET_MODE (XEXP (x, 0)) == SImode)
2634 *total = COSTS_N_INSNS (2);
2636 *total = COSTS_N_INSNS (1);
2640 case UNSIGNED_FLOAT:
2643 case FLOAT_TRUNCATE:
2645 *total = mips_cost->fp_add;
2653 /* Provide the costs of an addressing mode that contains ADDR.
2654 If ADDR is not a valid address, its cost is irrelevant. */
2657 mips_address_cost (rtx addr)
2659 return mips_address_insns (addr, SImode);
2662 /* Return one word of double-word value OP, taking into account the fixed
2663 endianness of certain registers. HIGH_P is true to select the high part,
2664 false to select the low part. */
2667 mips_subword (rtx op, int high_p)
2670 enum machine_mode mode;
2672 mode = GET_MODE (op);
2673 if (mode == VOIDmode)
2676 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2677 byte = UNITS_PER_WORD;
2683 if (FP_REG_P (REGNO (op)))
2684 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2685 if (ACC_HI_REG_P (REGNO (op)))
2686 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2690 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2692 return simplify_gen_subreg (word_mode, op, mode, byte);
2696 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2699 mips_split_64bit_move_p (rtx dest, rtx src)
2704 /* FP->FP moves can be done in a single instruction. */
2705 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2708 /* Check for floating-point loads and stores. They can be done using
2709 ldc1 and sdc1 on MIPS II and above. */
2712 if (FP_REG_RTX_P (dest) && MEM_P (src))
2714 if (FP_REG_RTX_P (src) && MEM_P (dest))
2721 /* Split a 64-bit move from SRC to DEST assuming that
2722 mips_split_64bit_move_p holds.
2724 Moves into and out of FPRs cause some difficulty here. Such moves
2725 will always be DFmode, since paired FPRs are not allowed to store
2726 DImode values. The most natural representation would be two separate
2727 32-bit moves, such as:
2729 (set (reg:SI $f0) (mem:SI ...))
2730 (set (reg:SI $f1) (mem:SI ...))
2732 However, the second insn is invalid because odd-numbered FPRs are
2733 not allowed to store independent values. Use the patterns load_df_low,
2734 load_df_high and store_df_high instead. */
2737 mips_split_64bit_move (rtx dest, rtx src)
2739 if (FP_REG_RTX_P (dest))
2741 /* Loading an FPR from memory or from GPRs. */
2742 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2743 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2746 else if (FP_REG_RTX_P (src))
2748 /* Storing an FPR into memory or GPRs. */
2749 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2750 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2754 /* The operation can be split into two normal moves. Decide in
2755 which order to do them. */
2758 low_dest = mips_subword (dest, 0);
2759 if (REG_P (low_dest)
2760 && reg_overlap_mentioned_p (low_dest, src))
2762 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2763 emit_move_insn (low_dest, mips_subword (src, 0));
2767 emit_move_insn (low_dest, mips_subword (src, 0));
2768 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2773 /* Return the appropriate instructions to move SRC into DEST. Assume
2774 that SRC is operand 1 and DEST is operand 0. */
2777 mips_output_move (rtx dest, rtx src)
2779 enum rtx_code dest_code, src_code;
2782 dest_code = GET_CODE (dest);
2783 src_code = GET_CODE (src);
2784 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2786 if (dbl_p && mips_split_64bit_move_p (dest, src))
2789 if ((src_code == REG && GP_REG_P (REGNO (src)))
2790 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2792 if (dest_code == REG)
2794 if (GP_REG_P (REGNO (dest)))
2795 return "move\t%0,%z1";
2797 if (MD_REG_P (REGNO (dest)))
2800 if (DSP_ACC_REG_P (REGNO (dest)))
2802 static char retval[] = "mt__\t%z1,%q0";
2803 retval[2] = reg_names[REGNO (dest)][4];
2804 retval[3] = reg_names[REGNO (dest)][5];
2808 if (FP_REG_P (REGNO (dest)))
2809 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2811 if (ALL_COP_REG_P (REGNO (dest)))
2813 static char retval[] = "dmtc_\t%z1,%0";
2815 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2816 return (dbl_p ? retval : retval + 1);
2819 if (dest_code == MEM)
2820 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2822 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2824 if (src_code == REG)
2826 if (DSP_ACC_REG_P (REGNO (src)))
2828 static char retval[] = "mf__\t%0,%q1";
2829 retval[2] = reg_names[REGNO (src)][4];
2830 retval[3] = reg_names[REGNO (src)][5];
2834 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2835 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2837 if (FP_REG_P (REGNO (src)))
2838 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2840 if (ALL_COP_REG_P (REGNO (src)))
2842 static char retval[] = "dmfc_\t%0,%1";
2844 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2845 return (dbl_p ? retval : retval + 1);
2849 if (src_code == MEM)
2850 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2852 if (src_code == CONST_INT)
2854 /* Don't use the X format, because that will give out of
2855 range numbers for 64 bit hosts and 32 bit targets. */
2857 return "li\t%0,%1\t\t\t# %X1";
2859 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2862 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2866 if (src_code == HIGH)
2867 return "lui\t%0,%h1";
2869 if (CONST_GP_P (src))
2870 return "move\t%0,%1";
2872 if (symbolic_operand (src, VOIDmode))
2873 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2875 if (src_code == REG && FP_REG_P (REGNO (src)))
2877 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2879 if (GET_MODE (dest) == V2SFmode)
2880 return "mov.ps\t%0,%1";
2882 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2885 if (dest_code == MEM)
2886 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2888 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2890 if (src_code == MEM)
2891 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2893 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2895 static char retval[] = "l_c_\t%0,%1";
2897 retval[1] = (dbl_p ? 'd' : 'w');
2898 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2901 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2903 static char retval[] = "s_c_\t%1,%0";
2905 retval[1] = (dbl_p ? 'd' : 'w');
2906 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2912 /* Restore $gp from its save slot. Valid only when using o32 or
2916 mips_restore_gp (void)
2920 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2922 address = mips_add_offset (pic_offset_table_rtx,
2923 frame_pointer_needed
2924 ? hard_frame_pointer_rtx
2925 : stack_pointer_rtx,
2926 current_function_outgoing_args_size);
2927 slot = gen_rtx_MEM (Pmode, address);
2929 emit_move_insn (pic_offset_table_rtx, slot);
2930 if (!TARGET_EXPLICIT_RELOCS)
2931 emit_insn (gen_blockage ());
2934 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2937 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2939 emit_insn (gen_rtx_SET (VOIDmode, target,
2940 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2943 /* Return true if CMP1 is a suitable second operand for relational
2944 operator CODE. See also the *sCC patterns in mips.md. */
2947 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2953 return reg_or_0_operand (cmp1, VOIDmode);
2957 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2961 return arith_operand (cmp1, VOIDmode);
2964 return sle_operand (cmp1, VOIDmode);
2967 return sleu_operand (cmp1, VOIDmode);
2974 /* Canonicalize LE or LEU comparisons into LT comparisons when
2975 possible to avoid extra instructions or inverting the
2979 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
2980 enum machine_mode mode)
2982 HOST_WIDE_INT original, plus_one;
2984 if (GET_CODE (*cmp1) != CONST_INT)
2987 original = INTVAL (*cmp1);
2988 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
2993 if (original < plus_one)
2996 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3005 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3018 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3019 result in TARGET. CMP0 and TARGET are register_operands that have
3020 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3021 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3024 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3025 rtx target, rtx cmp0, rtx cmp1)
3027 /* First see if there is a MIPS instruction that can do this operation
3028 with CMP1 in its current form. If not, try to canonicalize the
3029 comparison to LT. If that fails, try doing the same for the
3030 inverse operation. If that also fails, force CMP1 into a register
3032 if (mips_relational_operand_ok_p (code, cmp1))
3033 mips_emit_binary (code, target, cmp0, cmp1);
3034 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3035 mips_emit_binary (code, target, cmp0, cmp1);
3038 enum rtx_code inv_code = reverse_condition (code);
3039 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3041 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3042 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3044 else if (invert_ptr == 0)
3046 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3047 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3048 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3052 *invert_ptr = !*invert_ptr;
3053 mips_emit_binary (inv_code, target, cmp0, cmp1);
3058 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3059 The register will have the same mode as CMP0. */
3062 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3064 if (cmp1 == const0_rtx)
3067 if (uns_arith_operand (cmp1, VOIDmode))
3068 return expand_binop (GET_MODE (cmp0), xor_optab,
3069 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3071 return expand_binop (GET_MODE (cmp0), sub_optab,
3072 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3075 /* Convert a comparison into something that can be used in a branch or
3076 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3077 being compared and *CODE is the code used to compare them.
3079 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3080 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3081 otherwise any standard branch condition can be used. The standard branch
3084 - EQ/NE between two registers.
3085 - any comparison between a register and zero. */
3088 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3090 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3092 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3094 *op0 = cmp_operands[0];
3095 *op1 = cmp_operands[1];
3097 else if (*code == EQ || *code == NE)
3101 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3106 *op0 = cmp_operands[0];
3107 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3112 /* The comparison needs a separate scc instruction. Store the
3113 result of the scc in *OP0 and compare it against zero. */
3114 bool invert = false;
3115 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3117 mips_emit_int_relational (*code, &invert, *op0,
3118 cmp_operands[0], cmp_operands[1]);
3119 *code = (invert ? EQ : NE);
3124 enum rtx_code cmp_code;
3126 /* Floating-point tests use a separate c.cond.fmt comparison to
3127 set a condition code register. The branch or conditional move
3128 will then compare that register against zero.
3130 Set CMP_CODE to the code of the comparison instruction and
3131 *CODE to the code that the branch or move should use. */
3137 cmp_code = reverse_condition_maybe_unordered (*code);
3147 ? gen_reg_rtx (CCmode)
3148 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3150 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3154 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3155 Store the result in TARGET and return true if successful.
3157 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3160 mips_emit_scc (enum rtx_code code, rtx target)
3162 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3165 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3166 if (code == EQ || code == NE)
3168 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3169 mips_emit_binary (code, target, zie, const0_rtx);
3172 mips_emit_int_relational (code, 0, target,
3173 cmp_operands[0], cmp_operands[1]);
3177 /* Emit the common code for doing conditional branches.
3178 operand[0] is the label to jump to.
3179 The comparison operands are saved away by cmp{si,di,sf,df}. */
3182 gen_conditional_branch (rtx *operands, enum rtx_code code)
3184 rtx op0, op1, target;
3186 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3187 target = gen_rtx_IF_THEN_ELSE (VOIDmode,
3188 gen_rtx_fmt_ee (code, GET_MODE (op0),
3190 gen_rtx_LABEL_REF (VOIDmode, operands[0]),
3192 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
3195 /* Emit the common code for conditional moves. OPERANDS is the array
3196 of operands passed to the conditional move define_expand. */
3199 gen_conditional_move (rtx *operands)
3204 code = GET_CODE (operands[1]);
3205 mips_emit_compare (&code, &op0, &op1, true);
3206 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3207 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3208 gen_rtx_fmt_ee (code,
3211 operands[2], operands[3])));
3214 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3215 the conditional_trap expander. */
3218 mips_gen_conditional_trap (rtx *operands)
3221 enum rtx_code cmp_code = GET_CODE (operands[0]);
3222 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3224 /* MIPS conditional trap machine instructions don't have GT or LE
3225 flavors, so we must invert the comparison and convert to LT and
3226 GE, respectively. */
3229 case GT: cmp_code = LT; break;
3230 case LE: cmp_code = GE; break;
3231 case GTU: cmp_code = LTU; break;
3232 case LEU: cmp_code = GEU; break;
3235 if (cmp_code == GET_CODE (operands[0]))
3237 op0 = cmp_operands[0];
3238 op1 = cmp_operands[1];
3242 op0 = cmp_operands[1];
3243 op1 = cmp_operands[0];
3245 op0 = force_reg (mode, op0);
3246 if (!arith_operand (op1, mode))
3247 op1 = force_reg (mode, op1);
3249 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3250 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3254 /* Load function address ADDR into register DEST. SIBCALL_P is true
3255 if the address is needed for a sibling call. */
3258 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3260 /* If we're generating PIC, and this call is to a global function,
3261 try to allow its address to be resolved lazily. This isn't
3262 possible for NewABI sibcalls since the value of $gp on entry
3263 to the stub would be our caller's gp, not ours. */
3264 if (TARGET_EXPLICIT_RELOCS
3265 && !(sibcall_p && TARGET_NEWABI)
3266 && global_got_operand (addr, VOIDmode))
3268 rtx high, lo_sum_symbol;
3270 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3271 addr, SYMBOL_GOTOFF_CALL);
3272 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3273 if (Pmode == SImode)
3274 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3276 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3279 emit_move_insn (dest, addr);
3283 /* Expand a call or call_value instruction. RESULT is where the
3284 result will go (null for calls), ADDR is the address of the
3285 function, ARGS_SIZE is the size of the arguments and AUX is
3286 the value passed to us by mips_function_arg. SIBCALL_P is true
3287 if we are expanding a sibling call, false if we're expanding
3291 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3293 rtx orig_addr, pattern, insn;
3296 if (!call_insn_operand (addr, VOIDmode))
3298 addr = gen_reg_rtx (Pmode);
3299 mips_load_call_address (addr, orig_addr, sibcall_p);
3303 && mips16_hard_float
3304 && build_mips16_call_stub (result, addr, args_size,
3305 aux == 0 ? 0 : (int) GET_MODE (aux)))
3309 pattern = (sibcall_p
3310 ? gen_sibcall_internal (addr, args_size)
3311 : gen_call_internal (addr, args_size));
3312 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3316 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3317 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3320 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3321 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3324 pattern = (sibcall_p
3325 ? gen_sibcall_value_internal (result, addr, args_size)
3326 : gen_call_value_internal (result, addr, args_size));
3328 insn = emit_call_insn (pattern);
3330 /* Lazy-binding stubs require $gp to be valid on entry. */
3331 if (global_got_operand (orig_addr, VOIDmode))
3332 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3336 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3339 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3340 tree exp ATTRIBUTE_UNUSED)
3342 return TARGET_SIBCALLS;
3345 /* Emit code to move general operand SRC into condition-code
3346 register DEST. SCRATCH is a scratch TFmode float register.
3353 where FP1 and FP2 are single-precision float registers
3354 taken from SCRATCH. */
3357 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3361 /* Change the source to SFmode. */
3363 src = adjust_address (src, SFmode, 0);
3364 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3365 src = gen_rtx_REG (SFmode, true_regnum (src));
3367 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3368 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3370 emit_move_insn (copy_rtx (fp1), src);
3371 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3372 emit_insn (gen_slt_sf (dest, fp2, fp1));
3375 /* Emit code to change the current function's return address to
3376 ADDRESS. SCRATCH is available as a scratch register, if needed.
3377 ADDRESS and SCRATCH are both word-mode GPRs. */
3380 mips_set_return_address (rtx address, rtx scratch)
3384 compute_frame_size (get_frame_size ());
3385 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3386 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3387 cfun->machine->frame.gp_sp_offset);
3389 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3392 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3393 Assume that the areas do not overlap. */
3396 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3398 HOST_WIDE_INT offset, delta;
3399 unsigned HOST_WIDE_INT bits;
3401 enum machine_mode mode;
3404 /* Work out how many bits to move at a time. If both operands have
3405 half-word alignment, it is usually better to move in half words.
3406 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3407 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3408 Otherwise move word-sized chunks. */
3409 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3410 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3411 bits = BITS_PER_WORD / 2;
3413 bits = BITS_PER_WORD;
3415 mode = mode_for_size (bits, MODE_INT, 0);
3416 delta = bits / BITS_PER_UNIT;
3418 /* Allocate a buffer for the temporary registers. */
3419 regs = alloca (sizeof (rtx) * length / delta);
3421 /* Load as many BITS-sized chunks as possible. Use a normal load if
3422 the source has enough alignment, otherwise use left/right pairs. */
3423 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3425 regs[i] = gen_reg_rtx (mode);
3426 if (MEM_ALIGN (src) >= bits)
3427 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3430 rtx part = adjust_address (src, BLKmode, offset);
3431 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3436 /* Copy the chunks to the destination. */
3437 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3438 if (MEM_ALIGN (dest) >= bits)
3439 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3442 rtx part = adjust_address (dest, BLKmode, offset);
3443 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3447 /* Mop up any left-over bytes. */
3448 if (offset < length)
3450 src = adjust_address (src, BLKmode, offset);
3451 dest = adjust_address (dest, BLKmode, offset);
3452 move_by_pieces (dest, src, length - offset,
3453 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3457 #define MAX_MOVE_REGS 4
3458 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3461 /* Helper function for doing a loop-based block operation on memory
3462 reference MEM. Each iteration of the loop will operate on LENGTH
3465 Create a new base register for use within the loop and point it to
3466 the start of MEM. Create a new memory reference that uses this
3467 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3470 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3471 rtx *loop_reg, rtx *loop_mem)
3473 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3475 /* Although the new mem does not refer to a known location,
3476 it does keep up to LENGTH bytes of alignment. */
3477 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3478 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3482 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3483 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3484 memory regions do not overlap. */
3487 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3489 rtx label, src_reg, dest_reg, final_src;
3490 HOST_WIDE_INT leftover;
3492 leftover = length % MAX_MOVE_BYTES;
3495 /* Create registers and memory references for use within the loop. */
3496 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3497 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3499 /* Calculate the value that SRC_REG should have after the last iteration
3501 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3504 /* Emit the start of the loop. */
3505 label = gen_label_rtx ();
3508 /* Emit the loop body. */
3509 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3511 /* Move on to the next block. */
3512 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3513 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3515 /* Emit the loop condition. */
3516 if (Pmode == DImode)
3517 emit_insn (gen_cmpdi (src_reg, final_src));
3519 emit_insn (gen_cmpsi (src_reg, final_src));
3520 emit_jump_insn (gen_bne (label));
3522 /* Mop up any left-over bytes. */
3524 mips_block_move_straight (dest, src, leftover);
3527 /* Expand a movmemsi instruction. */
3530 mips_expand_block_move (rtx dest, rtx src, rtx length)
3532 if (GET_CODE (length) == CONST_INT)
3534 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3536 mips_block_move_straight (dest, src, INTVAL (length));
3541 mips_block_move_loop (dest, src, INTVAL (length));
3548 /* Argument support functions. */
3550 /* Initialize CUMULATIVE_ARGS for a function. */
3553 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3554 rtx libname ATTRIBUTE_UNUSED)
3556 static CUMULATIVE_ARGS zero_cum;
3557 tree param, next_param;
3560 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3562 /* Determine if this function has variable arguments. This is
3563 indicated by the last argument being 'void_type_mode' if there
3564 are no variable arguments. The standard MIPS calling sequence
3565 passes all arguments in the general purpose registers in this case. */
3567 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3568 param != 0; param = next_param)
3570 next_param = TREE_CHAIN (param);
3571 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3572 cum->gp_reg_found = 1;
3577 /* Fill INFO with information about a single argument. CUM is the
3578 cumulative state for earlier arguments. MODE is the mode of this
3579 argument and TYPE is its type (if known). NAMED is true if this
3580 is a named (fixed) argument rather than a variable one. */
3583 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3584 tree type, int named, struct mips_arg_info *info)
3586 bool doubleword_aligned_p;
3587 unsigned int num_bytes, num_words, max_regs;
3589 /* Work out the size of the argument. */
3590 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3591 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3593 /* Decide whether it should go in a floating-point register, assuming
3594 one is free. Later code checks for availability.
3596 The checks against UNITS_PER_FPVALUE handle the soft-float and
3597 single-float cases. */
3601 /* The EABI conventions have traditionally been defined in terms
3602 of TYPE_MODE, regardless of the actual type. */
3603 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3604 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3605 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3610 /* Only leading floating-point scalars are passed in
3611 floating-point registers. We also handle vector floats the same
3612 say, which is OK because they are not covered by the standard ABI. */
3613 info->fpr_p = (!cum->gp_reg_found
3614 && cum->arg_number < 2
3615 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3616 || VECTOR_FLOAT_TYPE_P (type))
3617 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3618 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3619 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3624 /* Scalar and complex floating-point types are passed in
3625 floating-point registers. */
3626 info->fpr_p = (named
3627 && (type == 0 || FLOAT_TYPE_P (type))
3628 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3629 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3630 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3631 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3633 /* ??? According to the ABI documentation, the real and imaginary
3634 parts of complex floats should be passed in individual registers.
3635 The real and imaginary parts of stack arguments are supposed
3636 to be contiguous and there should be an extra word of padding
3639 This has two problems. First, it makes it impossible to use a
3640 single "void *" va_list type, since register and stack arguments
3641 are passed differently. (At the time of writing, MIPSpro cannot
3642 handle complex float varargs correctly.) Second, it's unclear
3643 what should happen when there is only one register free.
3645 For now, we assume that named complex floats should go into FPRs
3646 if there are two FPRs free, otherwise they should be passed in the
3647 same way as a struct containing two floats. */
3649 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3650 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3652 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3653 info->fpr_p = false;
3663 /* See whether the argument has doubleword alignment. */
3664 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3666 /* Set REG_OFFSET to the register count we're interested in.
3667 The EABI allocates the floating-point registers separately,
3668 but the other ABIs allocate them like integer registers. */
3669 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3673 /* Advance to an even register if the argument is doubleword-aligned. */
3674 if (doubleword_aligned_p)
3675 info->reg_offset += info->reg_offset & 1;
3677 /* Work out the offset of a stack argument. */
3678 info->stack_offset = cum->stack_words;
3679 if (doubleword_aligned_p)
3680 info->stack_offset += info->stack_offset & 1;
3682 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3684 /* Partition the argument between registers and stack. */
3685 info->reg_words = MIN (num_words, max_regs);
3686 info->stack_words = num_words - info->reg_words;
3690 /* Implement FUNCTION_ARG_ADVANCE. */
3693 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3694 tree type, int named)
3696 struct mips_arg_info info;
3698 mips_arg_info (cum, mode, type, named, &info);
3701 cum->gp_reg_found = true;
3703 /* See the comment above the cumulative args structure in mips.h
3704 for an explanation of what this code does. It assumes the O32
3705 ABI, which passes at most 2 arguments in float registers. */
3706 if (cum->arg_number < 2 && info.fpr_p)
3707 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3709 if (mips_abi != ABI_EABI || !info.fpr_p)
3710 cum->num_gprs = info.reg_offset + info.reg_words;
3711 else if (info.reg_words > 0)
3712 cum->num_fprs += FP_INC;
3714 if (info.stack_words > 0)
3715 cum->stack_words = info.stack_offset + info.stack_words;
3720 /* Implement FUNCTION_ARG. */
3723 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3724 tree type, int named)
3726 struct mips_arg_info info;
3728 /* We will be called with a mode of VOIDmode after the last argument
3729 has been seen. Whatever we return will be passed to the call
3730 insn. If we need a mips16 fp_code, return a REG with the code
3731 stored as the mode. */
3732 if (mode == VOIDmode)
3734 if (TARGET_MIPS16 && cum->fp_code != 0)
3735 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3741 mips_arg_info (cum, mode, type, named, &info);
3743 /* Return straight away if the whole argument is passed on the stack. */
3744 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3748 && TREE_CODE (type) == RECORD_TYPE
3750 && TYPE_SIZE_UNIT (type)
3751 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3754 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3755 structure contains a double in its entirety, then that 64 bit
3756 chunk is passed in a floating point register. */
3759 /* First check to see if there is any such field. */
3760 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3761 if (TREE_CODE (field) == FIELD_DECL
3762 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3763 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3764 && host_integerp (bit_position (field), 0)
3765 && int_bit_position (field) % BITS_PER_WORD == 0)
3770 /* Now handle the special case by returning a PARALLEL
3771 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3772 chunks are passed in registers. */
3774 HOST_WIDE_INT bitpos;
3777 /* assign_parms checks the mode of ENTRY_PARM, so we must
3778 use the actual mode here. */
3779 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3782 field = TYPE_FIELDS (type);
3783 for (i = 0; i < info.reg_words; i++)
3787 for (; field; field = TREE_CHAIN (field))
3788 if (TREE_CODE (field) == FIELD_DECL
3789 && int_bit_position (field) >= bitpos)
3793 && int_bit_position (field) == bitpos
3794 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3795 && !TARGET_SOFT_FLOAT
3796 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3797 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3799 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3802 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3803 GEN_INT (bitpos / BITS_PER_UNIT));
3805 bitpos += BITS_PER_WORD;
3811 /* Handle the n32/n64 conventions for passing complex floating-point
3812 arguments in FPR pairs. The real part goes in the lower register
3813 and the imaginary part goes in the upper register. */
3816 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3819 enum machine_mode inner;
3822 inner = GET_MODE_INNER (mode);
3823 reg = FP_ARG_FIRST + info.reg_offset;
3824 real = gen_rtx_EXPR_LIST (VOIDmode,
3825 gen_rtx_REG (inner, reg),
3827 imag = gen_rtx_EXPR_LIST (VOIDmode,
3828 gen_rtx_REG (inner, reg + info.reg_words / 2),
3829 GEN_INT (GET_MODE_SIZE (inner)));
3830 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3834 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3835 else if (info.reg_offset == 1)
3836 /* This code handles the special o32 case in which the second word
3837 of the argument structure is passed in floating-point registers. */
3838 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3840 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3844 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3847 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3848 enum machine_mode mode, tree type, bool named)
3850 struct mips_arg_info info;
3852 mips_arg_info (cum, mode, type, named, &info);
3853 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3857 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3858 PARM_BOUNDARY bits of alignment, but will be given anything up
3859 to STACK_BOUNDARY bits if the type requires it. */
3862 function_arg_boundary (enum machine_mode mode, tree type)
3864 unsigned int alignment;
3866 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3867 if (alignment < PARM_BOUNDARY)
3868 alignment = PARM_BOUNDARY;
3869 if (alignment > STACK_BOUNDARY)
3870 alignment = STACK_BOUNDARY;
3874 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3875 upward rather than downward. In other words, return true if the
3876 first byte of the stack slot has useful data, false if the last
3880 mips_pad_arg_upward (enum machine_mode mode, tree type)
3882 /* On little-endian targets, the first byte of every stack argument
3883 is passed in the first byte of the stack slot. */
3884 if (!BYTES_BIG_ENDIAN)
3887 /* Otherwise, integral types are padded downward: the last byte of a
3888 stack argument is passed in the last byte of the stack slot. */
3890 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3891 : GET_MODE_CLASS (mode) == MODE_INT)
3894 /* Big-endian o64 pads floating-point arguments downward. */
3895 if (mips_abi == ABI_O64)
3896 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3899 /* Other types are padded upward for o32, o64, n32 and n64. */
3900 if (mips_abi != ABI_EABI)
3903 /* Arguments smaller than a stack slot are padded downward. */
3904 if (mode != BLKmode)
3905 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3907 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3911 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3912 if the least significant byte of the register has useful data. Return
3913 the opposite if the most significant byte does. */
3916 mips_pad_reg_upward (enum machine_mode mode, tree type)
3918 /* No shifting is required for floating-point arguments. */
3919 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3920 return !BYTES_BIG_ENDIAN;
3922 /* Otherwise, apply the same padding to register arguments as we do
3923 to stack arguments. */
3924 return mips_pad_arg_upward (mode, type);
3928 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3929 tree type, int *pretend_size ATTRIBUTE_UNUSED,
3932 CUMULATIVE_ARGS local_cum;
3933 int gp_saved, fp_saved;
3935 /* The caller has advanced CUM up to, but not beyond, the last named
3936 argument. Advance a local copy of CUM past the last "real" named
3937 argument, to find out how many registers are left over. */
3940 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3942 /* Found out how many registers we need to save. */
3943 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3944 fp_saved = (EABI_FLOAT_VARARGS_P
3945 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3954 ptr = plus_constant (virtual_incoming_args_rtx,
3955 REG_PARM_STACK_SPACE (cfun->decl)
3956 - gp_saved * UNITS_PER_WORD);
3957 mem = gen_rtx_MEM (BLKmode, ptr);
3958 set_mem_alias_set (mem, get_varargs_alias_set ());
3960 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3965 /* We can't use move_block_from_reg, because it will use
3967 enum machine_mode mode;
3970 /* Set OFF to the offset from virtual_incoming_args_rtx of
3971 the first float register. The FP save area lies below
3972 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3973 off = -gp_saved * UNITS_PER_WORD;
3974 off &= ~(UNITS_PER_FPVALUE - 1);
3975 off -= fp_saved * UNITS_PER_FPREG;
3977 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3979 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3983 ptr = plus_constant (virtual_incoming_args_rtx, off);
3984 mem = gen_rtx_MEM (mode, ptr);
3985 set_mem_alias_set (mem, get_varargs_alias_set ());
3986 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3987 off += UNITS_PER_HWFPVALUE;
3991 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
3992 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
3993 + fp_saved * UNITS_PER_FPREG);
3996 /* Create the va_list data type.
3997 We keep 3 pointers, and two offsets.
3998 Two pointers are to the overflow area, which starts at the CFA.
3999 One of these is constant, for addressing into the GPR save area below it.
4000 The other is advanced up the stack through the overflow region.
4001 The third pointer is to the GPR save area. Since the FPR save area
4002 is just below it, we can address FPR slots off this pointer.
4003 We also keep two one-byte offsets, which are to be subtracted from the
4004 constant pointers to yield addresses in the GPR and FPR save areas.
4005 These are downcounted as float or non-float arguments are used,
4006 and when they get to zero, the argument must be obtained from the
4008 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4009 pointer is enough. It's started at the GPR save area, and is
4011 Note that the GPR save area is not constant size, due to optimization
4012 in the prologue. Hence, we can't use a design with two pointers
4013 and two offsets, although we could have designed this with two pointers
4014 and three offsets. */
4017 mips_build_builtin_va_list (void)
4019 if (EABI_FLOAT_VARARGS_P)
4021 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4024 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4026 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4028 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4030 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4032 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4033 unsigned_char_type_node);
4034 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4035 unsigned_char_type_node);
4036 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4037 warn on every user file. */
4038 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4039 array = build_array_type (unsigned_char_type_node,
4040 build_index_type (index));
4041 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4043 DECL_FIELD_CONTEXT (f_ovfl) = record;
4044 DECL_FIELD_CONTEXT (f_gtop) = record;
4045 DECL_FIELD_CONTEXT (f_ftop) = record;
4046 DECL_FIELD_CONTEXT (f_goff) = record;
4047 DECL_FIELD_CONTEXT (f_foff) = record;
4048 DECL_FIELD_CONTEXT (f_res) = record;
4050 TYPE_FIELDS (record) = f_ovfl;
4051 TREE_CHAIN (f_ovfl) = f_gtop;
4052 TREE_CHAIN (f_gtop) = f_ftop;
4053 TREE_CHAIN (f_ftop) = f_goff;
4054 TREE_CHAIN (f_goff) = f_foff;
4055 TREE_CHAIN (f_foff) = f_res;
4057 layout_type (record);
4060 else if (TARGET_IRIX && TARGET_IRIX6)
4061 /* On IRIX 6, this type is 'char *'. */
4062 return build_pointer_type (char_type_node);
4064 /* Otherwise, we use 'void *'. */
4065 return ptr_type_node;
4068 /* Implement va_start. */
4071 mips_va_start (tree valist, rtx nextarg)
4073 if (EABI_FLOAT_VARARGS_P)
4075 const CUMULATIVE_ARGS *cum;
4076 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4077 tree ovfl, gtop, ftop, goff, foff;
4079 int gpr_save_area_size;
4080 int fpr_save_area_size;
4083 cum = ¤t_function_args_info;
4085 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4087 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4089 f_ovfl = TYPE_FIELDS (va_list_type_node);
4090 f_gtop = TREE_CHAIN (f_ovfl);
4091 f_ftop = TREE_CHAIN (f_gtop);
4092 f_goff = TREE_CHAIN (f_ftop);
4093 f_foff = TREE_CHAIN (f_goff);
4095 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4097 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4099 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4101 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4103 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4106 /* Emit code to initialize OVFL, which points to the next varargs
4107 stack argument. CUM->STACK_WORDS gives the number of stack
4108 words used by named arguments. */
4109 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4110 if (cum->stack_words > 0)
4111 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4112 build_int_cst (NULL_TREE,
4113 cum->stack_words * UNITS_PER_WORD));
4114 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4115 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4117 /* Emit code to initialize GTOP, the top of the GPR save area. */
4118 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4119 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4120 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4122 /* Emit code to initialize FTOP, the top of the FPR save area.
4123 This address is gpr_save_area_bytes below GTOP, rounded
4124 down to the next fp-aligned boundary. */
4125 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4126 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4127 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4129 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4130 build_int_cst (NULL_TREE, -fpr_offset));
4131 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4132 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4134 /* Emit code to initialize GOFF, the offset from GTOP of the
4135 next GPR argument. */
4136 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4137 build_int_cst (NULL_TREE, gpr_save_area_size));
4138 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4140 /* Likewise emit code to initialize FOFF, the offset from FTOP
4141 of the next FPR argument. */
4142 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4143 build_int_cst (NULL_TREE, fpr_save_area_size));
4144 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4148 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4149 std_expand_builtin_va_start (valist, nextarg);
4153 /* Implement va_arg. */
4156 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4158 HOST_WIDE_INT size, rsize;
4162 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4165 type = build_pointer_type (type);
4167 size = int_size_in_bytes (type);
4168 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4170 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4171 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4174 /* Not a simple merged stack. */
4176 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4177 tree ovfl, top, off, align;
4178 HOST_WIDE_INT osize;
4181 f_ovfl = TYPE_FIELDS (va_list_type_node);
4182 f_gtop = TREE_CHAIN (f_ovfl);
4183 f_ftop = TREE_CHAIN (f_gtop);
4184 f_goff = TREE_CHAIN (f_ftop);
4185 f_foff = TREE_CHAIN (f_goff);
4187 /* We maintain separate pointers and offsets for floating-point
4188 and integer arguments, but we need similar code in both cases.
4191 TOP be the top of the register save area;
4192 OFF be the offset from TOP of the next register;
4193 ADDR_RTX be the address of the argument;
4194 RSIZE be the number of bytes used to store the argument
4195 when it's in the register save area;
4196 OSIZE be the number of bytes used to store it when it's
4197 in the stack overflow area; and
4198 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4200 The code we want is:
4202 1: off &= -rsize; // round down
4205 4: addr_rtx = top - off;
4210 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4211 10: addr_rtx = ovfl + PADDING;
4215 [1] and [9] can sometimes be optimized away. */
4217 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4220 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4221 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4223 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4225 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4228 /* When floating-point registers are saved to the stack,
4229 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4230 of the float's precision. */
4231 rsize = UNITS_PER_HWFPVALUE;
4233 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4234 (= PARM_BOUNDARY bits). This can be different from RSIZE
4237 (1) On 32-bit targets when TYPE is a structure such as:
4239 struct s { float f; };
4241 Such structures are passed in paired FPRs, so RSIZE
4242 will be 8 bytes. However, the structure only takes
4243 up 4 bytes of memory, so OSIZE will only be 4.
4245 (2) In combinations such as -mgp64 -msingle-float
4246 -fshort-double. Doubles passed in registers
4247 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4248 but those passed on the stack take up
4249 UNITS_PER_WORD bytes. */
4250 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4254 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4256 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4258 if (rsize > UNITS_PER_WORD)
4260 /* [1] Emit code for: off &= -rsize. */
4261 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4262 build_int_cst (NULL_TREE, -rsize));
4263 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4264 gimplify_and_add (t, pre_p);
4269 /* [2] Emit code to branch if off == 0. */
4270 t = build (NE_EXPR, boolean_type_node, off,
4271 build_int_cst (TREE_TYPE (off), 0));
4272 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
4274 /* [5] Emit code for: off -= rsize. We do this as a form of
4275 post-increment not available to C. Also widen for the
4276 coming pointer arithmetic. */
4277 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4278 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4279 t = fold_convert (sizetype, t);
4280 t = fold_convert (TREE_TYPE (top), t);
4282 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4283 the argument has RSIZE - SIZE bytes of leading padding. */
4284 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
4285 if (BYTES_BIG_ENDIAN && rsize > size)
4287 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4289 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4291 COND_EXPR_THEN (addr) = t;
4293 if (osize > UNITS_PER_WORD)
4295 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4296 u = fold_convert (TREE_TYPE (ovfl),
4297 build_int_cst (NULL_TREE, osize - 1));
4298 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4299 u = fold_convert (TREE_TYPE (ovfl),
4300 build_int_cst (NULL_TREE, -osize));
4301 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4302 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4307 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4308 post-increment ovfl by osize. On big-endian machines,
4309 the argument has OSIZE - SIZE bytes of leading padding. */
4310 u = fold_convert (TREE_TYPE (ovfl),
4311 build_int_cst (NULL_TREE, osize));
4312 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4313 if (BYTES_BIG_ENDIAN && osize > size)
4315 u = fold_convert (TREE_TYPE (t),
4316 build_int_cst (NULL_TREE, osize - size));
4317 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4320 /* String [9] and [10,11] together. */
4322 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4323 COND_EXPR_ELSE (addr) = t;
4325 addr = fold_convert (build_pointer_type (type), addr);
4326 addr = build_va_arg_indirect_ref (addr);
4330 addr = build_va_arg_indirect_ref (addr);
4335 /* Return true if it is possible to use left/right accesses for a
4336 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4337 returning true, update *OP, *LEFT and *RIGHT as follows:
4339 *OP is a BLKmode reference to the whole field.
4341 *LEFT is a QImode reference to the first byte if big endian or
4342 the last byte if little endian. This address can be used in the
4343 left-side instructions (lwl, swl, ldl, sdl).
4345 *RIGHT is a QImode reference to the opposite end of the field and
4346 can be used in the patterning right-side instruction. */
4349 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4350 rtx *left, rtx *right)
4354 /* Check that the operand really is a MEM. Not all the extv and
4355 extzv predicates are checked. */
4359 /* Check that the size is valid. */
4360 if (width != 32 && (!TARGET_64BIT || width != 64))
4363 /* We can only access byte-aligned values. Since we are always passed
4364 a reference to the first byte of the field, it is not necessary to
4365 do anything with BITPOS after this check. */
4366 if (bitpos % BITS_PER_UNIT != 0)
4369 /* Reject aligned bitfields: we want to use a normal load or store
4370 instead of a left/right pair. */
4371 if (MEM_ALIGN (*op) >= width)
4374 /* Adjust *OP to refer to the whole field. This also has the effect
4375 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4376 *op = adjust_address (*op, BLKmode, 0);
4377 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4379 /* Get references to both ends of the field. We deliberately don't
4380 use the original QImode *OP for FIRST since the new BLKmode one
4381 might have a simpler address. */
4382 first = adjust_address (*op, QImode, 0);
4383 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4385 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4386 be the upper word and RIGHT the lower word. */
4387 if (TARGET_BIG_ENDIAN)
4388 *left = first, *right = last;
4390 *left = last, *right = first;
4396 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4397 Return true on success. We only handle cases where zero_extract is
4398 equivalent to sign_extract. */
4401 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4403 rtx left, right, temp;
4405 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4406 paradoxical word_mode subreg. This is the only case in which
4407 we allow the destination to be larger than the source. */
4408 if (GET_CODE (dest) == SUBREG
4409 && GET_MODE (dest) == DImode
4410 && SUBREG_BYTE (dest) == 0
4411 && GET_MODE (SUBREG_REG (dest)) == SImode)
4412 dest = SUBREG_REG (dest);
4414 /* After the above adjustment, the destination must be the same
4415 width as the source. */
4416 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4419 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4422 temp = gen_reg_rtx (GET_MODE (dest));
4423 if (GET_MODE (dest) == DImode)
4425 emit_insn (gen_mov_ldl (temp, src, left));
4426 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4430 emit_insn (gen_mov_lwl (temp, src, left));
4431 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4437 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4441 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4445 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4448 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4450 if (GET_MODE (src) == DImode)
4452 emit_insn (gen_mov_sdl (dest, src, left));
4453 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4457 emit_insn (gen_mov_swl (dest, src, left));
4458 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4463 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4464 source of an "ext" instruction or the destination of an "ins"
4465 instruction. OP must be a register operand and the following
4466 conditions must hold:
4468 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4469 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4470 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4472 Also reject lengths equal to a word as they are better handled
4473 by the move patterns. */
4476 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4478 HOST_WIDE_INT len, pos;
4480 if (!ISA_HAS_EXT_INS
4481 || !register_operand (op, VOIDmode)
4482 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4485 len = INTVAL (size);
4486 pos = INTVAL (position);
4488 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4489 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4495 /* Set up globals to generate code for the ISA or processor
4496 described by INFO. */
4499 mips_set_architecture (const struct mips_cpu_info *info)
4503 mips_arch_info = info;
4504 mips_arch = info->cpu;
4505 mips_isa = info->isa;
4510 /* Likewise for tuning. */
4513 mips_set_tune (const struct mips_cpu_info *info)
4517 mips_tune_info = info;
4518 mips_tune = info->cpu;
4522 /* Implement TARGET_HANDLE_OPTION. */
4525 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4530 if (strcmp (arg, "32") == 0)
4532 else if (strcmp (arg, "o64") == 0)
4534 else if (strcmp (arg, "n32") == 0)
4536 else if (strcmp (arg, "64") == 0)
4538 else if (strcmp (arg, "eabi") == 0)
4539 mips_abi = ABI_EABI;
4546 return mips_parse_cpu (arg) != 0;
4549 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4550 return mips_isa_info != 0;
4552 case OPT_mno_flush_func:
4553 mips_cache_flush_func = NULL;
4561 /* Set up the threshold for data to go into the small data area, instead
4562 of the normal data area, and detect any conflicts in the switches. */
4565 override_options (void)
4567 int i, start, regno;
4568 enum machine_mode mode;
4570 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4572 /* The following code determines the architecture and register size.
4573 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4574 The GAS and GCC code should be kept in sync as much as possible. */
4576 if (mips_arch_string != 0)
4577 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4579 if (mips_isa_info != 0)
4581 if (mips_arch_info == 0)
4582 mips_set_architecture (mips_isa_info);
4583 else if (mips_arch_info->isa != mips_isa_info->isa)
4584 error ("-%s conflicts with the other architecture options, "
4585 "which specify a %s processor",
4586 mips_isa_info->name,
4587 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4590 if (mips_arch_info == 0)
4592 #ifdef MIPS_CPU_STRING_DEFAULT
4593 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4595 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4599 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4600 error ("-march=%s is not compatible with the selected ABI",
4601 mips_arch_info->name);
4603 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4604 if (mips_tune_string != 0)
4605 mips_set_tune (mips_parse_cpu (mips_tune_string));
4607 if (mips_tune_info == 0)
4608 mips_set_tune (mips_arch_info);
4610 /* Set cost structure for the processor. */
4611 mips_cost = &mips_rtx_cost_data[mips_tune];
4613 if ((target_flags_explicit & MASK_64BIT) != 0)
4615 /* The user specified the size of the integer registers. Make sure
4616 it agrees with the ABI and ISA. */
4617 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4618 error ("-mgp64 used with a 32-bit processor");
4619 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4620 error ("-mgp32 used with a 64-bit ABI");
4621 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4622 error ("-mgp64 used with a 32-bit ABI");
4626 /* Infer the integer register size from the ABI and processor.
4627 Restrict ourselves to 32-bit registers if that's all the
4628 processor has, or if the ABI cannot handle 64-bit registers. */
4629 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4630 target_flags &= ~MASK_64BIT;
4632 target_flags |= MASK_64BIT;
4635 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4637 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4638 only one right answer here. */
4639 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4640 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4641 else if (!TARGET_64BIT && TARGET_FLOAT64)
4642 error ("unsupported combination: %s", "-mgp32 -mfp64");
4643 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4644 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4648 /* -msingle-float selects 32-bit float registers. Otherwise the
4649 float registers should be the same size as the integer ones. */
4650 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4651 target_flags |= MASK_FLOAT64;
4653 target_flags &= ~MASK_FLOAT64;
4656 /* End of code shared with GAS. */
4658 if ((target_flags_explicit & MASK_LONG64) == 0)
4660 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4661 target_flags |= MASK_LONG64;
4663 target_flags &= ~MASK_LONG64;
4666 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4667 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4669 /* For some configurations, it is useful to have -march control
4670 the default setting of MASK_SOFT_FLOAT. */
4671 switch ((int) mips_arch)
4673 case PROCESSOR_R4100:
4674 case PROCESSOR_R4111:
4675 case PROCESSOR_R4120:
4676 case PROCESSOR_R4130:
4677 target_flags |= MASK_SOFT_FLOAT;
4681 target_flags &= ~MASK_SOFT_FLOAT;
4687 flag_pcc_struct_return = 0;
4689 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4691 /* If neither -mbranch-likely nor -mno-branch-likely was given
4692 on the command line, set MASK_BRANCHLIKELY based on the target
4695 By default, we enable use of Branch Likely instructions on
4696 all architectures which support them with the following
4697 exceptions: when creating MIPS32 or MIPS64 code, and when
4698 tuning for architectures where their use tends to hurt
4701 The MIPS32 and MIPS64 architecture specifications say "Software
4702 is strongly encouraged to avoid use of Branch Likely
4703 instructions, as they will be removed from a future revision
4704 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4705 issue those instructions unless instructed to do so by
4707 if (ISA_HAS_BRANCHLIKELY
4708 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4709 && !(TUNE_MIPS5500 || TUNE_SB1))
4710 target_flags |= MASK_BRANCHLIKELY;
4712 target_flags &= ~MASK_BRANCHLIKELY;
4714 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4715 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4717 /* The effect of -mabicalls isn't defined for the EABI. */
4718 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4720 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4721 target_flags &= ~MASK_ABICALLS;
4724 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4725 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4726 /* ??? -non_shared turns off pic code generation, but this is not
4728 if (TARGET_ABICALLS)
4731 if (mips_section_threshold > 0)
4732 warning (0, "-G is incompatible with PIC code which is the default");
4735 /* mips_split_addresses is a half-way house between explicit
4736 relocations and the traditional assembler macros. It can
4737 split absolute 32-bit symbolic constants into a high/lo_sum
4738 pair but uses macros for other sorts of access.
4740 Like explicit relocation support for REL targets, it relies
4741 on GNU extensions in the assembler and the linker.
4743 Although this code should work for -O0, it has traditionally
4744 been treated as an optimization. */
4745 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4746 && optimize && !flag_pic
4747 && !ABI_HAS_64BIT_SYMBOLS)
4748 mips_split_addresses = 1;
4750 mips_split_addresses = 0;
4752 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4753 faster code, but at the expense of more nops. Enable it at -O3 and
4755 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4756 target_flags |= MASK_VR4130_ALIGN;
4758 /* When compiling for the mips16, we cannot use floating point. We
4759 record the original hard float value in mips16_hard_float. */
4762 if (TARGET_SOFT_FLOAT)
4763 mips16_hard_float = 0;
4765 mips16_hard_float = 1;
4766 target_flags |= MASK_SOFT_FLOAT;
4768 /* Don't run the scheduler before reload, since it tends to
4769 increase register pressure. */
4770 flag_schedule_insns = 0;
4772 /* Don't do hot/cold partitioning. The constant layout code expects
4773 the whole function to be in a single section. */
4774 flag_reorder_blocks_and_partition = 0;
4776 /* Silently disable -mexplicit-relocs since it doesn't apply
4777 to mips16 code. Even so, it would overly pedantic to warn
4778 about "-mips16 -mexplicit-relocs", especially given that
4779 we use a %gprel() operator. */
4780 target_flags &= ~MASK_EXPLICIT_RELOCS;
4783 /* When using explicit relocs, we call dbr_schedule from within
4785 if (TARGET_EXPLICIT_RELOCS)
4787 mips_flag_delayed_branch = flag_delayed_branch;
4788 flag_delayed_branch = 0;
4791 #ifdef MIPS_TFMODE_FORMAT
4792 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4795 /* Make sure that the user didn't turn off paired single support when
4796 MIPS-3D support is requested. */
4797 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4798 && !TARGET_PAIRED_SINGLE_FLOAT)
4799 error ("-mips3d requires -mpaired-single");
4801 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4803 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4805 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4806 and TARGET_HARD_FLOAT are both true. */
4807 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4808 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4810 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4812 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4813 error ("-mips3d/-mpaired-single must be used with -mips64");
4815 if (TARGET_MIPS16 && TARGET_DSP)
4816 error ("-mips16 and -mdsp cannot be used together");
4818 mips_print_operand_punct['?'] = 1;
4819 mips_print_operand_punct['#'] = 1;
4820 mips_print_operand_punct['/'] = 1;
4821 mips_print_operand_punct['&'] = 1;
4822 mips_print_operand_punct['!'] = 1;
4823 mips_print_operand_punct['*'] = 1;
4824 mips_print_operand_punct['@'] = 1;
4825 mips_print_operand_punct['.'] = 1;
4826 mips_print_operand_punct['('] = 1;
4827 mips_print_operand_punct[')'] = 1;
4828 mips_print_operand_punct['['] = 1;
4829 mips_print_operand_punct[']'] = 1;
4830 mips_print_operand_punct['<'] = 1;
4831 mips_print_operand_punct['>'] = 1;
4832 mips_print_operand_punct['{'] = 1;
4833 mips_print_operand_punct['}'] = 1;
4834 mips_print_operand_punct['^'] = 1;
4835 mips_print_operand_punct['$'] = 1;
4836 mips_print_operand_punct['+'] = 1;
4837 mips_print_operand_punct['~'] = 1;
4839 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4840 mips_char_to_class['t'] = T_REG;
4841 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4842 mips_char_to_class['h'] = HI_REG;
4843 mips_char_to_class['l'] = LO_REG;
4844 mips_char_to_class['x'] = MD_REGS;
4845 mips_char_to_class['b'] = ALL_REGS;
4846 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4847 TARGET_MIPS16 ? M16_NA_REGS :
4849 mips_char_to_class['e'] = LEA_REGS;
4850 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4851 mips_char_to_class['v'] = V1_REG;
4852 mips_char_to_class['y'] = GR_REGS;
4853 mips_char_to_class['z'] = ST_REGS;
4854 mips_char_to_class['B'] = COP0_REGS;
4855 mips_char_to_class['C'] = COP2_REGS;
4856 mips_char_to_class['D'] = COP3_REGS;
4857 mips_char_to_class['A'] = DSP_ACC_REGS;
4858 mips_char_to_class['a'] = ACC_REGS;
4860 /* Set up array to map GCC register number to debug register number.
4861 Ignore the special purpose register numbers. */
4863 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4864 mips_dbx_regno[i] = -1;
4866 start = GP_DBX_FIRST - GP_REG_FIRST;
4867 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4868 mips_dbx_regno[i] = i + start;
4870 start = FP_DBX_FIRST - FP_REG_FIRST;
4871 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4872 mips_dbx_regno[i] = i + start;
4874 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4875 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4877 /* Set up array giving whether a given register can hold a given mode. */
4879 for (mode = VOIDmode;
4880 mode != MAX_MACHINE_MODE;
4881 mode = (enum machine_mode) ((int)mode + 1))
4883 register int size = GET_MODE_SIZE (mode);
4884 register enum mode_class class = GET_MODE_CLASS (mode);
4886 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4890 if (mode == CCV2mode)
4893 && (regno - ST_REG_FIRST) % 2 == 0);
4895 else if (mode == CCV4mode)
4898 && (regno - ST_REG_FIRST) % 4 == 0);
4900 else if (mode == CCmode)
4903 temp = (regno == FPSW_REGNUM);
4905 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4906 || FP_REG_P (regno));
4909 else if (GP_REG_P (regno))
4910 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4912 else if (FP_REG_P (regno))
4913 temp = ((regno % FP_INC) == 0)
4914 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4915 || class == MODE_VECTOR_FLOAT)
4916 && size <= UNITS_PER_FPVALUE)
4917 /* Allow integer modes that fit into a single
4918 register. We need to put integers into FPRs
4919 when using instructions like cvt and trunc. */
4920 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4921 /* Allow TFmode for CCmode reloads. */
4922 || (ISA_HAS_8CC && mode == TFmode));
4924 else if (ACC_REG_P (regno))
4925 temp = (INTEGRAL_MODE_P (mode)
4926 && (size <= UNITS_PER_WORD
4927 || (ACC_HI_REG_P (regno)
4928 && size == 2 * UNITS_PER_WORD)));
4930 else if (ALL_COP_REG_P (regno))
4931 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4935 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4939 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4940 initialized yet, so we can't use that here. */
4941 gpr_mode = TARGET_64BIT ? DImode : SImode;
4943 /* Provide default values for align_* for 64-bit targets. */
4944 if (TARGET_64BIT && !TARGET_MIPS16)
4946 if (align_loops == 0)
4948 if (align_jumps == 0)
4950 if (align_functions == 0)
4951 align_functions = 8;
4954 /* Function to allocate machine-dependent function status. */
4955 init_machine_status = &mips_init_machine_status;
4957 if (ABI_HAS_64BIT_SYMBOLS)
4959 if (TARGET_EXPLICIT_RELOCS)
4961 mips_split_p[SYMBOL_64_HIGH] = true;
4962 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4963 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4965 mips_split_p[SYMBOL_64_MID] = true;
4966 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4967 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4969 mips_split_p[SYMBOL_64_LOW] = true;
4970 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4971 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4973 mips_split_p[SYMBOL_GENERAL] = true;
4974 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4979 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4981 mips_split_p[SYMBOL_GENERAL] = true;
4982 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4983 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4989 /* The high part is provided by a pseudo copy of $gp. */
4990 mips_split_p[SYMBOL_SMALL_DATA] = true;
4991 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4994 if (TARGET_EXPLICIT_RELOCS)
4996 /* Small data constants are kept whole until after reload,
4997 then lowered by mips_rewrite_small_data. */
4998 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5000 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5003 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5004 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5008 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5009 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5014 /* The HIGH and LO_SUM are matched by special .md patterns. */
5015 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5017 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5018 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5019 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5021 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5022 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5023 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5028 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5030 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5031 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5037 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5038 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5039 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5042 /* Thread-local relocation operators. */
5043 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5044 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5045 mips_split_p[SYMBOL_DTPREL] = 1;
5046 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5047 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5048 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5049 mips_split_p[SYMBOL_TPREL] = 1;
5050 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5051 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5053 /* We don't have a thread pointer access instruction on MIPS16, or
5054 appropriate TLS relocations. */
5056 targetm.have_tls = false;
5058 /* Default to working around R4000 errata only if the processor
5059 was selected explicitly. */
5060 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5061 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5062 target_flags |= MASK_FIX_R4000;
5064 /* Default to working around R4400 errata only if the processor
5065 was selected explicitly. */
5066 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5067 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5068 target_flags |= MASK_FIX_R4400;
5071 /* Implement CONDITIONAL_REGISTER_USAGE. */
5074 mips_conditional_register_usage (void)
5080 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5081 fixed_regs[regno] = call_used_regs[regno] = 1;
5083 if (!TARGET_HARD_FLOAT)
5087 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5088 fixed_regs[regno] = call_used_regs[regno] = 1;
5089 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5090 fixed_regs[regno] = call_used_regs[regno] = 1;
5092 else if (! ISA_HAS_8CC)
5096 /* We only have a single condition code register. We
5097 implement this by hiding all the condition code registers,
5098 and generating RTL that refers directly to ST_REG_FIRST. */
5099 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5100 fixed_regs[regno] = call_used_regs[regno] = 1;
5102 /* In mips16 mode, we permit the $t temporary registers to be used
5103 for reload. We prohibit the unused $s registers, since they
5104 are caller saved, and saving them via a mips16 register would
5105 probably waste more time than just reloading the value. */
5108 fixed_regs[18] = call_used_regs[18] = 1;
5109 fixed_regs[19] = call_used_regs[19] = 1;
5110 fixed_regs[20] = call_used_regs[20] = 1;
5111 fixed_regs[21] = call_used_regs[21] = 1;
5112 fixed_regs[22] = call_used_regs[22] = 1;
5113 fixed_regs[23] = call_used_regs[23] = 1;
5114 fixed_regs[26] = call_used_regs[26] = 1;
5115 fixed_regs[27] = call_used_regs[27] = 1;
5116 fixed_regs[30] = call_used_regs[30] = 1;
5118 /* fp20-23 are now caller saved. */
5119 if (mips_abi == ABI_64)
5122 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5123 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5125 /* Odd registers from fp21 to fp31 are now caller saved. */
5126 if (mips_abi == ABI_N32)
5129 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5130 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5134 /* Allocate a chunk of memory for per-function machine-dependent data. */
5135 static struct machine_function *
5136 mips_init_machine_status (void)
5138 return ((struct machine_function *)
5139 ggc_alloc_cleared (sizeof (struct machine_function)));
5142 /* On the mips16, we want to allocate $24 (T_REG) before other
5143 registers for instructions for which it is possible. This helps
5144 avoid shuffling registers around in order to set up for an xor,
5145 encouraging the compiler to use a cmp instead. */
5148 mips_order_regs_for_local_alloc (void)
5152 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5153 reg_alloc_order[i] = i;
5157 /* It really doesn't matter where we put register 0, since it is
5158 a fixed register anyhow. */
5159 reg_alloc_order[0] = 24;
5160 reg_alloc_order[24] = 0;
5165 /* The MIPS debug format wants all automatic variables and arguments
5166 to be in terms of the virtual frame pointer (stack pointer before
5167 any adjustment in the function), while the MIPS 3.0 linker wants
5168 the frame pointer to be the stack pointer after the initial
5169 adjustment. So, we do the adjustment here. The arg pointer (which
5170 is eliminated) points to the virtual frame pointer, while the frame
5171 pointer (which may be eliminated) points to the stack pointer after
5172 the initial adjustments. */
5175 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5177 rtx offset2 = const0_rtx;
5178 rtx reg = eliminate_constant_term (addr, &offset2);
5181 offset = INTVAL (offset2);
5183 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5184 || reg == hard_frame_pointer_rtx)
5186 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5187 ? compute_frame_size (get_frame_size ())
5188 : cfun->machine->frame.total_size;
5190 /* MIPS16 frame is smaller */
5191 if (frame_pointer_needed && TARGET_MIPS16)
5192 frame_size -= cfun->machine->frame.args_size;
5194 offset = offset - frame_size;
5197 /* sdbout_parms does not want this to crash for unrecognized cases. */
5199 else if (reg != arg_pointer_rtx)
5200 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5207 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5209 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5210 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5211 'h' OP is HIGH, prints %hi(X),
5212 'd' output integer constant in decimal,
5213 'z' if the operand is 0, use $0 instead of normal operand.
5214 'D' print second part of double-word register or memory operand.
5215 'L' print low-order register of double-word register operand.
5216 'M' print high-order register of double-word register operand.
5217 'C' print part of opcode for a branch condition.
5218 'F' print part of opcode for a floating-point branch condition.
5219 'N' print part of opcode for a branch condition, inverted.
5220 'W' print part of opcode for a floating-point branch condition, inverted.
5221 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5222 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5223 't' like 'T', but with the EQ/NE cases reversed
5224 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5225 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5226 'R' print the reloc associated with LO_SUM
5227 'q' print DSP accumulator registers
5229 The punctuation characters are:
5231 '(' Turn on .set noreorder
5232 ')' Turn on .set reorder
5233 '[' Turn on .set noat
5235 '<' Turn on .set nomacro
5236 '>' Turn on .set macro
5237 '{' Turn on .set volatile (not GAS)
5238 '}' Turn on .set novolatile (not GAS)
5239 '&' Turn on .set noreorder if filling delay slots
5240 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5241 '!' Turn on .set nomacro if filling delay slots
5242 '#' Print nop if in a .set noreorder section.
5243 '/' Like '#', but does nothing within a delayed branch sequence
5244 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5245 '@' Print the name of the assembler temporary register (at or $1).
5246 '.' Print the name of the register with a hard-wired zero (zero or $0).
5247 '^' Print the name of the pic call-through register (t9 or $25).
5248 '$' Print the name of the stack pointer register (sp or $29).
5249 '+' Print the name of the gp register (usually gp or $28).
5250 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5253 print_operand (FILE *file, rtx op, int letter)
5255 register enum rtx_code code;
5257 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5262 if (mips_branch_likely)
5267 fputs (reg_names [GP_REG_FIRST + 1], file);
5271 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5275 fputs (reg_names [GP_REG_FIRST + 0], file);
5279 fputs (reg_names[STACK_POINTER_REGNUM], file);
5283 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5287 if (final_sequence != 0 && set_noreorder++ == 0)
5288 fputs (".set\tnoreorder\n\t", file);
5292 if (final_sequence != 0)
5294 if (set_noreorder++ == 0)
5295 fputs (".set\tnoreorder\n\t", file);
5297 if (set_nomacro++ == 0)
5298 fputs (".set\tnomacro\n\t", file);
5303 if (final_sequence != 0 && set_nomacro++ == 0)
5304 fputs ("\n\t.set\tnomacro", file);
5308 if (set_noreorder != 0)
5309 fputs ("\n\tnop", file);
5313 /* Print an extra newline so that the delayed insn is separated
5314 from the following ones. This looks neater and is consistent
5315 with non-nop delayed sequences. */
5316 if (set_noreorder != 0 && final_sequence == 0)
5317 fputs ("\n\tnop\n", file);
5321 if (set_noreorder++ == 0)
5322 fputs (".set\tnoreorder\n\t", file);
5326 if (set_noreorder == 0)
5327 error ("internal error: %%) found without a %%( in assembler pattern");
5329 else if (--set_noreorder == 0)
5330 fputs ("\n\t.set\treorder", file);
5335 if (set_noat++ == 0)
5336 fputs (".set\tnoat\n\t", file);
5341 error ("internal error: %%] found without a %%[ in assembler pattern");
5342 else if (--set_noat == 0)
5343 fputs ("\n\t.set\tat", file);
5348 if (set_nomacro++ == 0)
5349 fputs (".set\tnomacro\n\t", file);
5353 if (set_nomacro == 0)
5354 error ("internal error: %%> found without a %%< in assembler pattern");
5355 else if (--set_nomacro == 0)
5356 fputs ("\n\t.set\tmacro", file);
5361 if (set_volatile++ == 0)
5362 fputs ("#.set\tvolatile\n\t", file);
5366 if (set_volatile == 0)
5367 error ("internal error: %%} found without a %%{ in assembler pattern");
5368 else if (--set_volatile == 0)
5369 fputs ("\n\t#.set\tnovolatile", file);
5375 if (align_labels_log > 0)
5376 ASM_OUTPUT_ALIGN (file, align_labels_log);
5381 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5390 error ("PRINT_OPERAND null pointer");
5394 code = GET_CODE (op);
5399 case EQ: fputs ("eq", file); break;
5400 case NE: fputs ("ne", file); break;
5401 case GT: fputs ("gt", file); break;
5402 case GE: fputs ("ge", file); break;
5403 case LT: fputs ("lt", file); break;
5404 case LE: fputs ("le", file); break;
5405 case GTU: fputs ("gtu", file); break;
5406 case GEU: fputs ("geu", file); break;
5407 case LTU: fputs ("ltu", file); break;
5408 case LEU: fputs ("leu", file); break;
5410 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5413 else if (letter == 'N')
5416 case EQ: fputs ("ne", file); break;
5417 case NE: fputs ("eq", file); break;
5418 case GT: fputs ("le", file); break;
5419 case GE: fputs ("lt", file); break;
5420 case LT: fputs ("ge", file); break;
5421 case LE: fputs ("gt", file); break;
5422 case GTU: fputs ("leu", file); break;
5423 case GEU: fputs ("ltu", file); break;
5424 case LTU: fputs ("geu", file); break;
5425 case LEU: fputs ("gtu", file); break;
5427 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5430 else if (letter == 'F')
5433 case EQ: fputs ("c1f", file); break;
5434 case NE: fputs ("c1t", file); break;
5436 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5439 else if (letter == 'W')
5442 case EQ: fputs ("c1t", file); break;
5443 case NE: fputs ("c1f", file); break;
5445 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5448 else if (letter == 'h')
5450 if (GET_CODE (op) == HIGH)
5453 print_operand_reloc (file, op, mips_hi_relocs);
5456 else if (letter == 'R')
5457 print_operand_reloc (file, op, mips_lo_relocs);
5459 else if (letter == 'Y')
5461 if (GET_CODE (op) == CONST_INT
5462 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5463 < ARRAY_SIZE (mips_fp_conditions)))
5464 fputs (mips_fp_conditions[INTVAL (op)], file);
5466 output_operand_lossage ("invalid %%Y value");
5469 else if (letter == 'Z')
5473 print_operand (file, op, 0);
5478 else if (letter == 'q')
5483 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5485 regnum = REGNO (op);
5486 if (MD_REG_P (regnum))
5487 fprintf (file, "$ac0");
5488 else if (DSP_ACC_REG_P (regnum))
5489 fprintf (file, "$ac%c", reg_names[regnum][3]);
5491 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5494 else if (code == REG || code == SUBREG)
5496 register int regnum;
5499 regnum = REGNO (op);
5501 regnum = true_regnum (op);
5503 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5504 || (letter == 'L' && WORDS_BIG_ENDIAN)
5508 fprintf (file, "%s", reg_names[regnum]);
5511 else if (code == MEM)
5514 output_address (plus_constant (XEXP (op, 0), 4));
5516 output_address (XEXP (op, 0));
5519 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5520 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5522 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5523 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5525 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5526 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5528 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5529 fputs (reg_names[GP_REG_FIRST], file);
5531 else if (letter == 'd' || letter == 'x' || letter == 'X')
5532 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5534 else if (letter == 'T' || letter == 't')
5536 int truth = (code == NE) == (letter == 'T');
5537 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5540 else if (CONST_GP_P (op))
5541 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5544 output_addr_const (file, op);
5548 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5549 RELOCS is the array of relocations to use. */
5552 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5554 enum mips_symbol_type symbol_type;
5557 HOST_WIDE_INT offset;
5559 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5560 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5562 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5563 mips_split_const (op, &base, &offset);
5564 if (UNSPEC_ADDRESS_P (base))
5565 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5567 fputs (relocs[symbol_type], file);
5568 output_addr_const (file, op);
5569 for (p = relocs[symbol_type]; *p != 0; p++)
5574 /* Output address operand X to FILE. */
5577 print_operand_address (FILE *file, rtx x)
5579 struct mips_address_info addr;
5581 if (mips_classify_address (&addr, x, word_mode, true))
5585 print_operand (file, addr.offset, 0);
5586 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5589 case ADDRESS_LO_SUM:
5590 print_operand (file, addr.offset, 'R');
5591 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5594 case ADDRESS_CONST_INT:
5595 output_addr_const (file, x);
5596 fprintf (file, "(%s)", reg_names[0]);
5599 case ADDRESS_SYMBOLIC:
5600 output_addr_const (file, x);
5606 /* When using assembler macros, keep track of all of small-data externs
5607 so that mips_file_end can emit the appropriate declarations for them.
5609 In most cases it would be safe (though pointless) to emit .externs
5610 for other symbols too. One exception is when an object is within
5611 the -G limit but declared by the user to be in a section other
5612 than .sbss or .sdata. */
5615 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5617 register struct extern_list *p;
5619 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5621 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5622 p->next = extern_head;
5624 p->size = int_size_in_bytes (TREE_TYPE (decl));
5628 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5630 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5631 p->next = extern_head;
5642 irix_output_external_libcall (rtx fun)
5644 register struct extern_list *p;
5646 if (mips_abi == ABI_32)
5648 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5649 p->next = extern_head;
5650 p->name = XSTR (fun, 0);
5657 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5658 put out a MIPS ECOFF file and a stab. */
5661 mips_output_filename (FILE *stream, const char *name)
5664 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5666 if (write_symbols == DWARF2_DEBUG)
5668 else if (mips_output_filename_first_time)
5670 mips_output_filename_first_time = 0;
5671 num_source_filenames += 1;
5672 current_function_file = name;
5673 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5674 output_quoted_string (stream, name);
5675 putc ('\n', stream);
5678 /* If we are emitting stabs, let dbxout.c handle this (except for
5679 the mips_output_filename_first_time case). */
5680 else if (write_symbols == DBX_DEBUG)
5683 else if (name != current_function_file
5684 && strcmp (name, current_function_file) != 0)
5686 num_source_filenames += 1;
5687 current_function_file = name;
5688 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5689 output_quoted_string (stream, name);
5690 putc ('\n', stream);
5694 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5695 that should be written before the opening quote, such as "\t.ascii\t"
5696 for real string data or "\t# " for a comment. */
5699 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5704 register const unsigned char *string =
5705 (const unsigned char *)string_param;
5707 fprintf (stream, "%s\"", prefix);
5708 for (i = 0; i < len; i++)
5710 register int c = string[i];
5714 if (c == '\\' || c == '\"')
5716 putc ('\\', stream);
5724 fprintf (stream, "\\%03o", c);
5728 if (cur_pos > 72 && i+1 < len)
5731 fprintf (stream, "\"\n%s\"", prefix);
5734 fprintf (stream, "\"\n");
5737 /* Implement TARGET_ASM_FILE_START. */
5740 mips_file_start (void)
5742 default_file_start ();
5746 /* Generate a special section to describe the ABI switches used to
5747 produce the resultant binary. This used to be done by the assembler
5748 setting bits in the ELF header's flags field, but we have run out of
5749 bits. GDB needs this information in order to be able to correctly
5750 debug these binaries. See the function mips_gdbarch_init() in
5751 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5752 causes unnecessary IRIX 6 ld warnings. */
5753 const char * abi_string = NULL;
5757 case ABI_32: abi_string = "abi32"; break;
5758 case ABI_N32: abi_string = "abiN32"; break;
5759 case ABI_64: abi_string = "abi64"; break;
5760 case ABI_O64: abi_string = "abiO64"; break;
5761 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5765 /* Note - we use fprintf directly rather than called named_section()
5766 because in this way we can avoid creating an allocated section. We
5767 do not want this section to take up any space in the running
5769 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5771 /* There is no ELF header flag to distinguish long32 forms of the
5772 EABI from long64 forms. Emit a special section to help tools
5774 if (mips_abi == ABI_EABI)
5775 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5776 TARGET_LONG64 ? 64 : 32);
5778 /* Restore the default section. */
5779 fprintf (asm_out_file, "\t.previous\n");
5782 /* Generate the pseudo ops that System V.4 wants. */
5783 if (TARGET_ABICALLS)
5784 /* ??? but do not want this (or want pic0) if -non-shared? */
5785 fprintf (asm_out_file, "\t.abicalls\n");
5788 fprintf (asm_out_file, "\t.set\tmips16\n");
5790 if (flag_verbose_asm)
5791 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5793 mips_section_threshold, mips_arch_info->name, mips_isa);
5796 #ifdef BSS_SECTION_ASM_OP
5797 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5798 in the use of sbss. */
5801 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5802 unsigned HOST_WIDE_INT size, int align)
5804 extern tree last_assemble_variable_decl;
5806 if (mips_in_small_data_p (decl))
5807 named_section (0, ".sbss", 0);
5810 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5811 last_assemble_variable_decl = decl;
5812 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5813 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5817 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5818 .externs for any small-data variables that turned out to be external. */
5821 mips_file_end (void)
5824 struct extern_list *p;
5828 fputs ("\n", asm_out_file);
5830 for (p = extern_head; p != 0; p = p->next)
5832 name_tree = get_identifier (p->name);
5834 /* Positively ensure only one .extern for any given symbol. */
5835 if (!TREE_ASM_WRITTEN (name_tree)
5836 && TREE_SYMBOL_REFERENCED (name_tree))
5838 TREE_ASM_WRITTEN (name_tree) = 1;
5839 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5840 `.global name .text' directive for every used but
5841 undefined function. If we don't, the linker may perform
5842 an optimization (skipping over the insns that set $gp)
5843 when it is unsafe. */
5844 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5846 fputs ("\t.globl ", asm_out_file);
5847 assemble_name (asm_out_file, p->name);
5848 fputs (" .text\n", asm_out_file);
5852 fputs ("\t.extern\t", asm_out_file);
5853 assemble_name (asm_out_file, p->name);
5854 fprintf (asm_out_file, ", %d\n", p->size);
5861 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5862 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5865 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5866 unsigned HOST_WIDE_INT size,
5869 /* If the target wants uninitialized const declarations in
5870 .rdata then don't put them in .comm. */
5871 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5872 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5873 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5875 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5876 targetm.asm_out.globalize_label (stream, name);
5878 readonly_data_section ();
5879 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5880 mips_declare_object (stream, name, "",
5881 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5885 mips_declare_common_object (stream, name, "\n\t.comm\t",
5889 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5890 NAME is the name of the object and ALIGN is the required alignment
5891 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5892 alignment argument. */
5895 mips_declare_common_object (FILE *stream, const char *name,
5896 const char *init_string,
5897 unsigned HOST_WIDE_INT size,
5898 unsigned int align, bool takes_alignment_p)
5900 if (!takes_alignment_p)
5902 size += (align / BITS_PER_UNIT) - 1;
5903 size -= size % (align / BITS_PER_UNIT);
5904 mips_declare_object (stream, name, init_string,
5905 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5908 mips_declare_object (stream, name, init_string,
5909 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5910 size, align / BITS_PER_UNIT);
5913 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5914 macros, mark the symbol as written so that mips_file_end won't emit an
5915 .extern for it. STREAM is the output file, NAME is the name of the
5916 symbol, INIT_STRING is the string that should be written before the
5917 symbol and FINAL_STRING is the string that should be written after it.
5918 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5921 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5922 const char *final_string, ...)
5926 fputs (init_string, stream);
5927 assemble_name (stream, name);
5928 va_start (ap, final_string);
5929 vfprintf (stream, final_string, ap);
5932 if (!TARGET_EXPLICIT_RELOCS)
5934 tree name_tree = get_identifier (name);
5935 TREE_ASM_WRITTEN (name_tree) = 1;
5939 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5940 extern int size_directive_output;
5942 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5943 definitions except that it uses mips_declare_object() to emit the label. */
5946 mips_declare_object_name (FILE *stream, const char *name,
5947 tree decl ATTRIBUTE_UNUSED)
5949 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5950 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5953 size_directive_output = 0;
5954 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5958 size_directive_output = 1;
5959 size = int_size_in_bytes (TREE_TYPE (decl));
5960 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5963 mips_declare_object (stream, name, "", ":\n");
5966 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5969 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5973 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5974 if (!flag_inhibit_size_directive
5975 && DECL_SIZE (decl) != 0
5976 && !at_end && top_level
5977 && DECL_INITIAL (decl) == error_mark_node
5978 && !size_directive_output)
5982 size_directive_output = 1;
5983 size = int_size_in_bytes (TREE_TYPE (decl));
5984 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5989 /* Return true if X is a small data address that can be rewritten
5993 mips_rewrite_small_data_p (rtx x)
5995 enum mips_symbol_type symbol_type;
5997 return (TARGET_EXPLICIT_RELOCS
5998 && mips_symbolic_constant_p (x, &symbol_type)
5999 && symbol_type == SYMBOL_SMALL_DATA);
6003 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6006 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6008 if (GET_CODE (*loc) == LO_SUM)
6011 return mips_rewrite_small_data_p (*loc);
6014 /* Return true if OP refers to small data symbols directly, not through
6018 mips_small_data_pattern_p (rtx op)
6020 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6023 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6026 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6028 if (mips_rewrite_small_data_p (*loc))
6029 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6031 if (GET_CODE (*loc) == LO_SUM)
6037 /* If possible, rewrite OP so that it refers to small data using
6038 explicit relocations. */
6041 mips_rewrite_small_data (rtx op)
6043 op = copy_insn (op);
6044 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6048 /* Return true if the current function has an insn that implicitly
6052 mips_function_has_gp_insn (void)
6054 /* Don't bother rechecking if we found one last time. */
6055 if (!cfun->machine->has_gp_insn_p)
6059 push_topmost_sequence ();
6060 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6062 && GET_CODE (PATTERN (insn)) != USE
6063 && GET_CODE (PATTERN (insn)) != CLOBBER
6064 && (get_attr_got (insn) != GOT_UNSET
6065 || small_data_pattern (PATTERN (insn), VOIDmode)))
6067 pop_topmost_sequence ();
6069 cfun->machine->has_gp_insn_p = (insn != 0);
6071 return cfun->machine->has_gp_insn_p;
6075 /* Return the register that should be used as the global pointer
6076 within this function. Return 0 if the function doesn't need
6077 a global pointer. */
6080 mips_global_pointer (void)
6084 /* $gp is always available in non-abicalls code. */
6085 if (!TARGET_ABICALLS)
6086 return GLOBAL_POINTER_REGNUM;
6088 /* We must always provide $gp when it is used implicitly. */
6089 if (!TARGET_EXPLICIT_RELOCS)
6090 return GLOBAL_POINTER_REGNUM;
6092 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6094 if (current_function_profile)
6095 return GLOBAL_POINTER_REGNUM;
6097 /* If the function has a nonlocal goto, $gp must hold the correct
6098 global pointer for the target function. */
6099 if (current_function_has_nonlocal_goto)
6100 return GLOBAL_POINTER_REGNUM;
6102 /* If the gp is never referenced, there's no need to initialize it.
6103 Note that reload can sometimes introduce constant pool references
6104 into a function that otherwise didn't need them. For example,
6105 suppose we have an instruction like:
6107 (set (reg:DF R1) (float:DF (reg:SI R2)))
6109 If R2 turns out to be constant such as 1, the instruction may have a
6110 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6111 using this constant if R2 doesn't get allocated to a register.
6113 In cases like these, reload will have added the constant to the pool
6114 but no instruction will yet refer to it. */
6115 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6116 && !current_function_uses_const_pool
6117 && !mips_function_has_gp_insn ())
6120 /* We need a global pointer, but perhaps we can use a call-clobbered
6121 register instead of $gp. */
6122 if (TARGET_NEWABI && current_function_is_leaf)
6123 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6124 if (!regs_ever_live[regno]
6125 && call_used_regs[regno]
6126 && !fixed_regs[regno]
6127 && regno != PIC_FUNCTION_ADDR_REGNUM)
6130 return GLOBAL_POINTER_REGNUM;
6134 /* Return true if the current function must save REGNO. */
6137 mips_save_reg_p (unsigned int regno)
6139 /* We only need to save $gp for NewABI PIC. */
6140 if (regno == GLOBAL_POINTER_REGNUM)
6141 return (TARGET_ABICALLS && TARGET_NEWABI
6142 && cfun->machine->global_pointer == regno);
6144 /* Check call-saved registers. */
6145 if (regs_ever_live[regno] && !call_used_regs[regno])
6148 /* We need to save the old frame pointer before setting up a new one. */
6149 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6152 /* We need to save the incoming return address if it is ever clobbered
6153 within the function. */
6154 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6161 return_type = DECL_RESULT (current_function_decl);
6163 /* $18 is a special case in mips16 code. It may be used to call
6164 a function which returns a floating point value, but it is
6165 marked in call_used_regs. */
6166 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6169 /* $31 is also a special case. It will be used to copy a return
6170 value into the floating point registers if the return value is
6172 if (regno == GP_REG_FIRST + 31
6173 && mips16_hard_float
6174 && !aggregate_value_p (return_type, current_function_decl)
6175 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6176 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6184 /* Return the bytes needed to compute the frame pointer from the current
6185 stack pointer. SIZE is the size (in bytes) of the local variables.
6187 MIPS stack frames look like:
6189 Before call After call
6190 +-----------------------+ +-----------------------+
6193 | caller's temps. | | caller's temps. |
6195 +-----------------------+ +-----------------------+
6197 | arguments on stack. | | arguments on stack. |
6199 +-----------------------+ +-----------------------+
6200 | 4 words to save | | 4 words to save |
6201 | arguments passed | | arguments passed |
6202 | in registers, even | | in registers, even |
6203 SP->| if not passed. | VFP->| if not passed. |
6204 +-----------------------+ +-----------------------+
6206 | fp register save |
6208 +-----------------------+
6210 | gp register save |
6212 +-----------------------+
6216 +-----------------------+
6218 | alloca allocations |
6220 +-----------------------+
6222 | GP save for V.4 abi |
6224 +-----------------------+
6226 | arguments on stack |
6228 +-----------------------+
6230 | arguments passed |
6231 | in registers, even |
6232 low SP->| if not passed. |
6233 memory +-----------------------+
6238 compute_frame_size (HOST_WIDE_INT size)
6241 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6242 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6243 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6244 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6245 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6246 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6247 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6248 unsigned int mask; /* mask of saved gp registers */
6249 unsigned int fmask; /* mask of saved fp registers */
6251 cfun->machine->global_pointer = mips_global_pointer ();
6257 var_size = MIPS_STACK_ALIGN (size);
6258 args_size = current_function_outgoing_args_size;
6259 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6261 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6262 functions. If the function has local variables, we're committed
6263 to allocating it anyway. Otherwise reclaim it here. */
6264 if (var_size == 0 && current_function_is_leaf)
6265 cprestore_size = args_size = 0;
6267 /* The MIPS 3.0 linker does not like functions that dynamically
6268 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6269 looks like we are trying to create a second frame pointer to the
6270 function, so allocate some stack space to make it happy. */
6272 if (args_size == 0 && current_function_calls_alloca)
6273 args_size = 4 * UNITS_PER_WORD;
6275 total_size = var_size + args_size + cprestore_size;
6277 /* Calculate space needed for gp registers. */
6278 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6279 if (mips_save_reg_p (regno))
6281 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6282 mask |= 1 << (regno - GP_REG_FIRST);
6285 /* We need to restore these for the handler. */
6286 if (current_function_calls_eh_return)
6291 regno = EH_RETURN_DATA_REGNO (i);
6292 if (regno == INVALID_REGNUM)
6294 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6295 mask |= 1 << (regno - GP_REG_FIRST);
6299 /* This loop must iterate over the same space as its companion in
6300 save_restore_insns. */
6301 for (regno = (FP_REG_LAST - FP_INC + 1);
6302 regno >= FP_REG_FIRST;
6305 if (mips_save_reg_p (regno))
6307 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6308 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6312 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6313 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6315 /* Add in the space required for saving incoming register arguments. */
6316 total_size += current_function_pretend_args_size;
6317 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6319 /* Save other computed information. */
6320 cfun->machine->frame.total_size = total_size;
6321 cfun->machine->frame.var_size = var_size;
6322 cfun->machine->frame.args_size = args_size;
6323 cfun->machine->frame.cprestore_size = cprestore_size;
6324 cfun->machine->frame.gp_reg_size = gp_reg_size;
6325 cfun->machine->frame.fp_reg_size = fp_reg_size;
6326 cfun->machine->frame.mask = mask;
6327 cfun->machine->frame.fmask = fmask;
6328 cfun->machine->frame.initialized = reload_completed;
6329 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6330 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6334 HOST_WIDE_INT offset;
6336 offset = (args_size + cprestore_size + var_size
6337 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6338 cfun->machine->frame.gp_sp_offset = offset;
6339 cfun->machine->frame.gp_save_offset = offset - total_size;
6343 cfun->machine->frame.gp_sp_offset = 0;
6344 cfun->machine->frame.gp_save_offset = 0;
6349 HOST_WIDE_INT offset;
6351 offset = (args_size + cprestore_size + var_size
6352 + gp_reg_rounded + fp_reg_size
6353 - FP_INC * UNITS_PER_FPREG);
6354 cfun->machine->frame.fp_sp_offset = offset;
6355 cfun->machine->frame.fp_save_offset = offset - total_size;
6359 cfun->machine->frame.fp_sp_offset = 0;
6360 cfun->machine->frame.fp_save_offset = 0;
6363 /* Ok, we're done. */
6367 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6368 pointer or argument pointer. TO is either the stack pointer or
6369 hard frame pointer. */
6372 mips_initial_elimination_offset (int from, int to)
6374 HOST_WIDE_INT offset;
6376 compute_frame_size (get_frame_size ());
6378 /* Set OFFSET to the offset from the stack pointer. */
6381 case FRAME_POINTER_REGNUM:
6385 case ARG_POINTER_REGNUM:
6386 offset = (cfun->machine->frame.total_size
6387 - current_function_pretend_args_size);
6394 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6395 offset -= cfun->machine->frame.args_size;
6400 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6401 back to a previous frame. */
6403 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6408 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6411 /* Use FN to save or restore register REGNO. MODE is the register's
6412 mode and OFFSET is the offset of its save slot from the current
6416 mips_save_restore_reg (enum machine_mode mode, int regno,
6417 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6421 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6423 fn (gen_rtx_REG (mode, regno), mem);
6427 /* Call FN for each register that is saved by the current function.
6428 SP_OFFSET is the offset of the current stack pointer from the start
6432 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6434 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6436 enum machine_mode fpr_mode;
6437 HOST_WIDE_INT offset;
6440 /* Save registers starting from high to low. The debuggers prefer at least
6441 the return register be stored at func+4, and also it allows us not to
6442 need a nop in the epilog if at least one register is reloaded in
6443 addition to return address. */
6444 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6445 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6446 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6448 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6449 offset -= GET_MODE_SIZE (gpr_mode);
6452 /* This loop must iterate over the same space as its companion in
6453 compute_frame_size. */
6454 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6455 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6456 for (regno = (FP_REG_LAST - FP_INC + 1);
6457 regno >= FP_REG_FIRST;
6459 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6461 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6462 offset -= GET_MODE_SIZE (fpr_mode);
6467 /* If we're generating n32 or n64 abicalls, and the current function
6468 does not use $28 as its global pointer, emit a cplocal directive.
6469 Use pic_offset_table_rtx as the argument to the directive. */
6472 mips_output_cplocal (void)
6474 if (!TARGET_EXPLICIT_RELOCS
6475 && cfun->machine->global_pointer > 0
6476 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6477 output_asm_insn (".cplocal %+", 0);
6480 /* If we're generating n32 or n64 abicalls, emit instructions
6481 to set up the global pointer. */
6484 mips_emit_loadgp (void)
6486 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6488 rtx addr, offset, incoming_address;
6490 addr = XEXP (DECL_RTL (current_function_decl), 0);
6491 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6492 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6493 emit_insn (gen_loadgp (offset, incoming_address));
6494 if (!TARGET_EXPLICIT_RELOCS)
6495 emit_insn (gen_loadgp_blockage ());
6499 /* Set up the stack and frame (if desired) for the function. */
6502 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6505 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6507 #ifdef SDB_DEBUGGING_INFO
6508 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6509 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6512 /* In mips16 mode, we may need to generate a 32 bit to handle
6513 floating point arguments. The linker will arrange for any 32 bit
6514 functions to call this stub, which will then jump to the 16 bit
6516 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6517 && current_function_args_info.fp_code != 0)
6518 build_mips16_function_stub (file);
6520 if (!FUNCTION_NAME_ALREADY_DECLARED)
6522 /* Get the function name the same way that toplev.c does before calling
6523 assemble_start_function. This is needed so that the name used here
6524 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6525 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6527 if (!flag_inhibit_size_directive)
6529 fputs ("\t.ent\t", file);
6530 assemble_name (file, fnname);
6534 assemble_name (file, fnname);
6535 fputs (":\n", file);
6538 /* Stop mips_file_end from treating this function as external. */
6539 if (TARGET_IRIX && mips_abi == ABI_32)
6540 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6542 if (!flag_inhibit_size_directive)
6544 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6546 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6547 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6548 ", args= " HOST_WIDE_INT_PRINT_DEC
6549 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6550 (reg_names[(frame_pointer_needed)
6551 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6552 ((frame_pointer_needed && TARGET_MIPS16)
6553 ? tsize - cfun->machine->frame.args_size
6555 reg_names[GP_REG_FIRST + 31],
6556 cfun->machine->frame.var_size,
6557 cfun->machine->frame.num_gp,
6558 cfun->machine->frame.num_fp,
6559 cfun->machine->frame.args_size,
6560 cfun->machine->frame.cprestore_size);
6562 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6563 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6564 cfun->machine->frame.mask,
6565 cfun->machine->frame.gp_save_offset);
6566 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6567 cfun->machine->frame.fmask,
6568 cfun->machine->frame.fp_save_offset);
6571 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6572 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6575 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6577 /* Handle the initialization of $gp for SVR4 PIC. */
6578 if (!cfun->machine->all_noreorder_p)
6579 output_asm_insn ("%(.cpload\t%^%)", 0);
6581 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6583 else if (cfun->machine->all_noreorder_p)
6584 output_asm_insn ("%(%<", 0);
6586 /* Tell the assembler which register we're using as the global
6587 pointer. This is needed for thunks, since they can use either
6588 explicit relocs or assembler macros. */
6589 mips_output_cplocal ();
6592 /* Make the last instruction frame related and note that it performs
6593 the operation described by FRAME_PATTERN. */
6596 mips_set_frame_expr (rtx frame_pattern)
6600 insn = get_last_insn ();
6601 RTX_FRAME_RELATED_P (insn) = 1;
6602 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6608 /* Return a frame-related rtx that stores REG at MEM.
6609 REG must be a single register. */
6612 mips_frame_set (rtx mem, rtx reg)
6616 /* If we're saving the return address register and the dwarf return
6617 address column differs from the hard register number, adjust the
6618 note reg to refer to the former. */
6619 if (REGNO (reg) == GP_REG_FIRST + 31
6620 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6621 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6623 set = gen_rtx_SET (VOIDmode, mem, reg);
6624 RTX_FRAME_RELATED_P (set) = 1;
6630 /* Save register REG to MEM. Make the instruction frame-related. */
6633 mips_save_reg (rtx reg, rtx mem)
6635 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6639 if (mips_split_64bit_move_p (mem, reg))
6640 mips_split_64bit_move (mem, reg);
6642 emit_move_insn (mem, reg);
6644 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6645 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6646 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6651 && REGNO (reg) != GP_REG_FIRST + 31
6652 && !M16_REG_P (REGNO (reg)))
6654 /* Save a non-mips16 register by moving it through a temporary.
6655 We don't need to do this for $31 since there's a special
6656 instruction for it. */
6657 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6658 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6661 emit_move_insn (mem, reg);
6663 mips_set_frame_expr (mips_frame_set (mem, reg));
6668 /* Expand the prologue into a bunch of separate insns. */
6671 mips_expand_prologue (void)
6675 if (cfun->machine->global_pointer > 0)
6676 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6678 size = compute_frame_size (get_frame_size ());
6680 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6681 bytes beforehand; this is enough to cover the register save area
6682 without going out of range. */
6683 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6685 HOST_WIDE_INT step1;
6687 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6688 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6690 GEN_INT (-step1)))) = 1;
6692 mips_for_each_saved_reg (size, mips_save_reg);
6695 /* Allocate the rest of the frame. */
6698 if (SMALL_OPERAND (-size))
6699 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6701 GEN_INT (-size)))) = 1;
6704 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6707 /* There are no instructions to add or subtract registers
6708 from the stack pointer, so use the frame pointer as a
6709 temporary. We should always be using a frame pointer
6710 in this case anyway. */
6711 gcc_assert (frame_pointer_needed);
6712 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6713 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6714 hard_frame_pointer_rtx,
6715 MIPS_PROLOGUE_TEMP (Pmode)));
6716 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6719 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6721 MIPS_PROLOGUE_TEMP (Pmode)));
6723 /* Describe the combined effect of the previous instructions. */
6725 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6726 plus_constant (stack_pointer_rtx, -size)));
6730 /* Set up the frame pointer, if we're using one. In mips16 code,
6731 we point the frame pointer ahead of the outgoing argument area.
6732 This should allow more variables & incoming arguments to be
6733 accessed with unextended instructions. */
6734 if (frame_pointer_needed)
6736 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6738 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6740 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6745 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6746 stack_pointer_rtx)) = 1;
6749 /* If generating o32/o64 abicalls, save $gp on the stack. */
6750 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6751 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6753 mips_emit_loadgp ();
6755 /* If we are profiling, make sure no instructions are scheduled before
6756 the call to mcount. */
6758 if (current_function_profile)
6759 emit_insn (gen_blockage ());
6762 /* Do any necessary cleanup after a function to restore stack, frame,
6765 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6768 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6769 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6771 /* Reinstate the normal $gp. */
6772 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6773 mips_output_cplocal ();
6775 if (cfun->machine->all_noreorder_p)
6777 /* Avoid using %>%) since it adds excess whitespace. */
6778 output_asm_insn (".set\tmacro", 0);
6779 output_asm_insn (".set\treorder", 0);
6780 set_noreorder = set_nomacro = 0;
6783 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6787 /* Get the function name the same way that toplev.c does before calling
6788 assemble_start_function. This is needed so that the name used here
6789 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6790 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6791 fputs ("\t.end\t", file);
6792 assemble_name (file, fnname);
6797 /* Emit instructions to restore register REG from slot MEM. */
6800 mips_restore_reg (rtx reg, rtx mem)
6802 /* There's no mips16 instruction to load $31 directly. Load into
6803 $7 instead and adjust the return insn appropriately. */
6804 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6805 reg = gen_rtx_REG (GET_MODE (reg), 7);
6807 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6809 /* Can't restore directly; move through a temporary. */
6810 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6811 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6814 emit_move_insn (reg, mem);
6818 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6819 if this epilogue precedes a sibling call, false if it is for a normal
6820 "epilogue" pattern. */
6823 mips_expand_epilogue (int sibcall_p)
6825 HOST_WIDE_INT step1, step2;
6828 if (!sibcall_p && mips_can_use_return_insn ())
6830 emit_jump_insn (gen_return ());
6834 /* Split the frame into two. STEP1 is the amount of stack we should
6835 deallocate before restoring the registers. STEP2 is the amount we
6836 should deallocate afterwards.
6838 Start off by assuming that no registers need to be restored. */
6839 step1 = cfun->machine->frame.total_size;
6842 /* Work out which register holds the frame address. Account for the
6843 frame pointer offset used by mips16 code. */
6844 if (!frame_pointer_needed)
6845 base = stack_pointer_rtx;
6848 base = hard_frame_pointer_rtx;
6850 step1 -= cfun->machine->frame.args_size;
6853 /* If we need to restore registers, deallocate as much stack as
6854 possible in the second step without going out of range. */
6855 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6857 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6861 /* Set TARGET to BASE + STEP1. */
6867 /* Get an rtx for STEP1 that we can add to BASE. */
6868 adjust = GEN_INT (step1);
6869 if (!SMALL_OPERAND (step1))
6871 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6872 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6875 /* Normal mode code can copy the result straight into $sp. */
6877 target = stack_pointer_rtx;
6879 emit_insn (gen_add3_insn (target, base, adjust));
6882 /* Copy TARGET into the stack pointer. */
6883 if (target != stack_pointer_rtx)
6884 emit_move_insn (stack_pointer_rtx, target);
6886 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6887 implicitly used by all SYMBOL_REFs. We must emit a blockage
6888 insn before restoring it. */
6889 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6890 emit_insn (gen_blockage ());
6892 /* Restore the registers. */
6893 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6896 /* Deallocate the final bit of the frame. */
6898 emit_insn (gen_add3_insn (stack_pointer_rtx,
6902 /* Add in the __builtin_eh_return stack adjustment. We need to
6903 use a temporary in mips16 code. */
6904 if (current_function_calls_eh_return)
6908 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6909 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6910 MIPS_EPILOGUE_TEMP (Pmode),
6911 EH_RETURN_STACKADJ_RTX));
6912 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6915 emit_insn (gen_add3_insn (stack_pointer_rtx,
6917 EH_RETURN_STACKADJ_RTX));
6922 /* The mips16 loads the return address into $7, not $31. */
6923 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6924 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6925 GP_REG_FIRST + 7)));
6927 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6928 GP_REG_FIRST + 31)));
6932 /* Return nonzero if this function is known to have a null epilogue.
6933 This allows the optimizer to omit jumps to jumps if no stack
6937 mips_can_use_return_insn (void)
6941 if (! reload_completed)
6944 if (regs_ever_live[31] || current_function_profile)
6947 return_type = DECL_RESULT (current_function_decl);
6949 /* In mips16 mode, a function which returns a floating point value
6950 needs to arrange to copy the return value into the floating point
6953 && mips16_hard_float
6954 && ! aggregate_value_p (return_type, current_function_decl)
6955 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6956 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6959 if (cfun->machine->frame.initialized)
6960 return cfun->machine->frame.total_size == 0;
6962 return compute_frame_size (get_frame_size ()) == 0;
6965 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6966 in order to avoid duplicating too much logic from elsewhere. */
6969 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6970 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6973 rtx this, temp1, temp2, insn, fnaddr;
6975 /* Pretend to be a post-reload pass while generating rtl. */
6977 reload_completed = 1;
6978 reset_block_changes ();
6980 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6981 for TARGET_NEWABI since the latter is a call-saved register. */
6982 if (TARGET_ABICALLS)
6983 cfun->machine->global_pointer
6984 = REGNO (pic_offset_table_rtx)
6985 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6987 /* Set up the global pointer for n32 or n64 abicalls. */
6988 mips_emit_loadgp ();
6990 /* We need two temporary registers in some cases. */
6991 temp1 = gen_rtx_REG (Pmode, 2);
6992 temp2 = gen_rtx_REG (Pmode, 3);
6994 /* Find out which register contains the "this" pointer. */
6995 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6996 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6998 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7000 /* Add DELTA to THIS. */
7003 rtx offset = GEN_INT (delta);
7004 if (!SMALL_OPERAND (delta))
7006 emit_move_insn (temp1, offset);
7009 emit_insn (gen_add3_insn (this, this, offset));
7012 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7013 if (vcall_offset != 0)
7017 /* Set TEMP1 to *THIS. */
7018 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7020 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7021 addr = mips_add_offset (temp2, temp1, vcall_offset);
7023 /* Load the offset and add it to THIS. */
7024 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7025 emit_insn (gen_add3_insn (this, this, temp1));
7028 /* Jump to the target function. Use a sibcall if direct jumps are
7029 allowed, otherwise load the address into a register first. */
7030 fnaddr = XEXP (DECL_RTL (function), 0);
7031 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7033 /* This is messy. gas treats "la $25,foo" as part of a call
7034 sequence and may allow a global "foo" to be lazily bound.
7035 The general move patterns therefore reject this combination.
7037 In this context, lazy binding would actually be OK for o32 and o64,
7038 but it's still wrong for n32 and n64; see mips_load_call_address.
7039 We must therefore load the address via a temporary register if
7040 mips_dangerous_for_la25_p.
7042 If we jump to the temporary register rather than $25, the assembler
7043 can use the move insn to fill the jump's delay slot. */
7044 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7045 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7046 mips_load_call_address (temp1, fnaddr, true);
7048 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7049 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7050 emit_jump_insn (gen_indirect_jump (temp1));
7054 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7055 SIBLING_CALL_P (insn) = 1;
7058 /* Run just enough of rest_of_compilation. This sequence was
7059 "borrowed" from alpha.c. */
7060 insn = get_insns ();
7061 insn_locators_initialize ();
7062 split_all_insns_noflow ();
7064 mips16_lay_out_constants ();
7065 shorten_branches (insn);
7066 final_start_function (insn, file, 1);
7067 final (insn, file, 1);
7068 final_end_function ();
7070 /* Clean up the vars set above. Note that final_end_function resets
7071 the global pointer for us. */
7072 reload_completed = 0;
7076 /* Returns nonzero if X contains a SYMBOL_REF. */
7079 symbolic_expression_p (rtx x)
7081 if (GET_CODE (x) == SYMBOL_REF)
7084 if (GET_CODE (x) == CONST)
7085 return symbolic_expression_p (XEXP (x, 0));
7088 return symbolic_expression_p (XEXP (x, 0));
7090 if (ARITHMETIC_P (x))
7091 return (symbolic_expression_p (XEXP (x, 0))
7092 || symbolic_expression_p (XEXP (x, 1)));
7097 /* Choose the section to use for the constant rtx expression X that has
7101 mips_select_rtx_section (enum machine_mode mode, rtx x,
7102 unsigned HOST_WIDE_INT align)
7106 /* In mips16 mode, the constant table always goes in the same section
7107 as the function, so that constants can be loaded using PC relative
7109 function_section (current_function_decl);
7111 else if (TARGET_EMBEDDED_DATA)
7113 /* For embedded applications, always put constants in read-only data,
7114 in order to reduce RAM usage. */
7115 mergeable_constant_section (mode, align, 0);
7119 /* For hosted applications, always put constants in small data if
7120 possible, as this gives the best performance. */
7121 /* ??? Consider using mergeable small data sections. */
7123 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7124 && mips_section_threshold > 0)
7125 named_section (0, ".sdata", 0);
7126 else if (flag_pic && symbolic_expression_p (x))
7127 named_section (0, ".data.rel.ro", 3);
7129 mergeable_constant_section (mode, align, 0);
7133 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7135 The complication here is that, with the combination TARGET_ABICALLS
7136 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7137 therefore not be included in the read-only part of a DSO. Handle such
7138 cases by selecting a normal data section instead of a read-only one.
7139 The logic apes that in default_function_rodata_section. */
7142 mips_function_rodata_section (tree decl)
7144 if (!TARGET_ABICALLS || TARGET_GPWORD)
7145 default_function_rodata_section (decl);
7146 else if (decl && DECL_SECTION_NAME (decl))
7148 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7149 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7151 char *rname = ASTRDUP (name);
7153 named_section_real (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7155 else if (flag_function_sections && flag_data_sections
7156 && strncmp (name, ".text.", 6) == 0)
7158 char *rname = ASTRDUP (name);
7159 memcpy (rname + 1, "data", 4);
7160 named_section_flags (rname, SECTION_WRITE);
7169 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7170 access DECL using %gp_rel(...)($gp). */
7173 mips_in_small_data_p (tree decl)
7177 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7180 /* We don't yet generate small-data references for -mabicalls. See related
7181 -G handling in override_options. */
7182 if (TARGET_ABICALLS)
7185 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7189 /* Reject anything that isn't in a known small-data section. */
7190 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7191 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7194 /* If a symbol is defined externally, the assembler will use the
7195 usual -G rules when deciding how to implement macros. */
7196 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7199 else if (TARGET_EMBEDDED_DATA)
7201 /* Don't put constants into the small data section: we want them
7202 to be in ROM rather than RAM. */
7203 if (TREE_CODE (decl) != VAR_DECL)
7206 if (TREE_READONLY (decl)
7207 && !TREE_SIDE_EFFECTS (decl)
7208 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7212 size = int_size_in_bytes (TREE_TYPE (decl));
7213 return (size > 0 && size <= mips_section_threshold);
7216 /* See whether VALTYPE is a record whose fields should be returned in
7217 floating-point registers. If so, return the number of fields and
7218 list them in FIELDS (which should have two elements). Return 0
7221 For n32 & n64, a structure with one or two fields is returned in
7222 floating-point registers as long as every field has a floating-point
7226 mips_fpr_return_fields (tree valtype, tree *fields)
7234 if (TREE_CODE (valtype) != RECORD_TYPE)
7238 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7240 if (TREE_CODE (field) != FIELD_DECL)
7243 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7249 fields[i++] = field;
7255 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7256 a value in the most significant part of $2/$3 if:
7258 - the target is big-endian;
7260 - the value has a structure or union type (we generalize this to
7261 cover aggregates from other languages too); and
7263 - the structure is not returned in floating-point registers. */
7266 mips_return_in_msb (tree valtype)
7270 return (TARGET_NEWABI
7271 && TARGET_BIG_ENDIAN
7272 && AGGREGATE_TYPE_P (valtype)
7273 && mips_fpr_return_fields (valtype, fields) == 0);
7277 /* Return a composite value in a pair of floating-point registers.
7278 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7279 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7282 For n32 & n64, $f0 always holds the first value and $f2 the second.
7283 Otherwise the values are packed together as closely as possible. */
7286 mips_return_fpr_pair (enum machine_mode mode,
7287 enum machine_mode mode1, HOST_WIDE_INT offset1,
7288 enum machine_mode mode2, HOST_WIDE_INT offset2)
7292 inc = (TARGET_NEWABI ? 2 : FP_INC);
7293 return gen_rtx_PARALLEL
7296 gen_rtx_EXPR_LIST (VOIDmode,
7297 gen_rtx_REG (mode1, FP_RETURN),
7299 gen_rtx_EXPR_LIST (VOIDmode,
7300 gen_rtx_REG (mode2, FP_RETURN + inc),
7301 GEN_INT (offset2))));
7306 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7307 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7308 VALTYPE is null and MODE is the mode of the return value. */
7311 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7312 enum machine_mode mode)
7319 mode = TYPE_MODE (valtype);
7320 unsignedp = TYPE_UNSIGNED (valtype);
7322 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7323 true, we must promote the mode just as PROMOTE_MODE does. */
7324 mode = promote_mode (valtype, mode, &unsignedp, 1);
7326 /* Handle structures whose fields are returned in $f0/$f2. */
7327 switch (mips_fpr_return_fields (valtype, fields))
7330 return gen_rtx_REG (mode, FP_RETURN);
7333 return mips_return_fpr_pair (mode,
7334 TYPE_MODE (TREE_TYPE (fields[0])),
7335 int_byte_position (fields[0]),
7336 TYPE_MODE (TREE_TYPE (fields[1])),
7337 int_byte_position (fields[1]));
7340 /* If a value is passed in the most significant part of a register, see
7341 whether we have to round the mode up to a whole number of words. */
7342 if (mips_return_in_msb (valtype))
7344 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7345 if (size % UNITS_PER_WORD != 0)
7347 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7348 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7352 /* For EABI, the class of return register depends entirely on MODE.
7353 For example, "struct { some_type x; }" and "union { some_type x; }"
7354 are returned in the same way as a bare "some_type" would be.
7355 Other ABIs only use FPRs for scalar, complex or vector types. */
7356 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7357 return gen_rtx_REG (mode, GP_RETURN);
7360 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7361 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7362 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7363 return gen_rtx_REG (mode, FP_RETURN);
7365 /* Handle long doubles for n32 & n64. */
7367 return mips_return_fpr_pair (mode,
7369 DImode, GET_MODE_SIZE (mode) / 2);
7371 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7372 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7373 return mips_return_fpr_pair (mode,
7374 GET_MODE_INNER (mode), 0,
7375 GET_MODE_INNER (mode),
7376 GET_MODE_SIZE (mode) / 2);
7378 return gen_rtx_REG (mode, GP_RETURN);
7381 /* Return nonzero when an argument must be passed by reference. */
7384 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7385 enum machine_mode mode, tree type,
7386 bool named ATTRIBUTE_UNUSED)
7388 if (mips_abi == ABI_EABI)
7392 /* ??? How should SCmode be handled? */
7393 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7396 size = int_size_in_bytes (type);
7397 return size == -1 || size > UNITS_PER_WORD;
7401 /* If we have a variable-sized parameter, we have no choice. */
7402 return targetm.calls.must_pass_in_stack (mode, type);
7407 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7408 enum machine_mode mode ATTRIBUTE_UNUSED,
7409 tree type ATTRIBUTE_UNUSED, bool named)
7411 return mips_abi == ABI_EABI && named;
7414 /* Return true if registers of class CLASS cannot change from mode FROM
7418 mips_cannot_change_mode_class (enum machine_mode from,
7419 enum machine_mode to, enum reg_class class)
7421 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7422 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7424 if (TARGET_BIG_ENDIAN)
7426 /* When a multi-word value is stored in paired floating-point
7427 registers, the first register always holds the low word.
7428 We therefore can't allow FPRs to change between single-word
7429 and multi-word modes. */
7430 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7435 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7436 in LO and HI, the high word always comes first. We therefore
7437 can't allow values stored in HI to change between single-word
7438 and multi-word modes.
7439 This rule applies to both the original HI/LO pair and the new
7440 DSP accumulators. */
7441 if (reg_classes_intersect_p (ACC_REGS, class))
7445 /* Loading a 32-bit value into a 64-bit floating-point register
7446 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7447 We can't allow 64-bit float registers to change from SImode to
7451 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7452 && reg_classes_intersect_p (FP_REGS, class))
7457 /* Return true if X should not be moved directly into register $25.
7458 We need this because many versions of GAS will treat "la $25,foo" as
7459 part of a call sequence and so allow a global "foo" to be lazily bound. */
7462 mips_dangerous_for_la25_p (rtx x)
7464 HOST_WIDE_INT offset;
7466 if (TARGET_EXPLICIT_RELOCS)
7469 mips_split_const (x, &x, &offset);
7470 return global_got_operand (x, VOIDmode);
7473 /* Implement PREFERRED_RELOAD_CLASS. */
7476 mips_preferred_reload_class (rtx x, enum reg_class class)
7478 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7481 if (TARGET_HARD_FLOAT
7482 && FLOAT_MODE_P (GET_MODE (x))
7483 && reg_class_subset_p (FP_REGS, class))
7486 if (reg_class_subset_p (GR_REGS, class))
7489 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7495 /* This function returns the register class required for a secondary
7496 register when copying between one of the registers in CLASS, and X,
7497 using MODE. If IN_P is nonzero, the copy is going from X to the
7498 register, otherwise the register is the source. A return value of
7499 NO_REGS means that no secondary register is required. */
7502 mips_secondary_reload_class (enum reg_class class,
7503 enum machine_mode mode, rtx x, int in_p)
7505 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7509 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7510 regno = true_regnum (x);
7512 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7514 if (mips_dangerous_for_la25_p (x))
7517 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7521 /* Copying from HI or LO to anywhere other than a general register
7522 requires a general register.
7523 This rule applies to both the original HI/LO pair and the new
7524 DSP accumulators. */
7525 if (reg_class_subset_p (class, ACC_REGS))
7527 if (TARGET_MIPS16 && in_p)
7529 /* We can't really copy to HI or LO at all in mips16 mode. */
7532 return gp_reg_p ? NO_REGS : gr_regs;
7534 if (ACC_REG_P (regno))
7536 if (TARGET_MIPS16 && ! in_p)
7538 /* We can't really copy to HI or LO at all in mips16 mode. */
7541 return class == gr_regs ? NO_REGS : gr_regs;
7544 /* We can only copy a value to a condition code register from a
7545 floating point register, and even then we require a scratch
7546 floating point register. We can only copy a value out of a
7547 condition code register into a general register. */
7548 if (class == ST_REGS)
7552 return gp_reg_p ? NO_REGS : gr_regs;
7554 if (ST_REG_P (regno))
7558 return class == gr_regs ? NO_REGS : gr_regs;
7561 if (class == FP_REGS)
7565 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7568 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7570 /* We can use the l.s and l.d macros to load floating-point
7571 constants. ??? For l.s, we could probably get better
7572 code by returning GR_REGS here. */
7575 else if (gp_reg_p || x == CONST0_RTX (mode))
7577 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7580 else if (FP_REG_P (regno))
7582 /* In this case we can use mov.s or mov.d. */
7587 /* Otherwise, we need to reload through an integer register. */
7592 /* In mips16 mode, going between memory and anything but M16_REGS
7593 requires an M16_REG. */
7596 if (class != M16_REGS && class != M16_NA_REGS)
7604 if (class == M16_REGS || class == M16_NA_REGS)
7613 /* Implement CLASS_MAX_NREGS.
7615 Usually all registers are word-sized. The only supported exception
7616 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7617 registers. A word-based calculation is correct even in that case,
7618 since -msingle-float disallows multi-FPR values.
7620 The FP status registers are an exception to this rule. They are always
7621 4 bytes wide as they only hold condition code modes, and CCmode is always
7622 considered to be 4 bytes wide. */
7625 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7626 enum machine_mode mode)
7628 if (class == ST_REGS)
7629 return (GET_MODE_SIZE (mode) + 3) / 4;
7631 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7635 mips_valid_pointer_mode (enum machine_mode mode)
7637 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7640 /* Target hook for vector_mode_supported_p. */
7643 mips_vector_mode_supported_p (enum machine_mode mode)
7648 return TARGET_PAIRED_SINGLE_FLOAT;
7659 /* If we can access small data directly (using gp-relative relocation
7660 operators) return the small data pointer, otherwise return null.
7662 For each mips16 function which refers to GP relative symbols, we
7663 use a pseudo register, initialized at the start of the function, to
7664 hold the $gp value. */
7667 mips16_gp_pseudo_reg (void)
7669 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7674 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7676 /* We want to initialize this to a value which gcc will believe
7679 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7680 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7681 gen_rtx_CONST (Pmode, unspec));
7682 insn = get_insns ();
7685 push_topmost_sequence ();
7686 /* We need to emit the initialization after the FUNCTION_BEG
7687 note, so that it will be integrated. */
7688 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7690 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7692 if (scan == NULL_RTX)
7693 scan = get_insns ();
7694 insn = emit_insn_after (insn, scan);
7695 pop_topmost_sequence ();
7698 return cfun->machine->mips16_gp_pseudo_rtx;
7701 /* Write out code to move floating point arguments in or out of
7702 general registers. Output the instructions to FILE. FP_CODE is
7703 the code describing which arguments are present (see the comment at
7704 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7705 we are copying from the floating point registers. */
7708 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7714 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7715 gcc_assert (TARGET_OLDABI);
7721 gparg = GP_ARG_FIRST;
7722 fparg = FP_ARG_FIRST;
7723 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7727 if ((fparg & 1) != 0)
7729 fprintf (file, "\t%s\t%s,%s\n", s,
7730 reg_names[gparg], reg_names[fparg]);
7732 else if ((f & 3) == 2)
7735 fprintf (file, "\td%s\t%s,%s\n", s,
7736 reg_names[gparg], reg_names[fparg]);
7739 if ((fparg & 1) != 0)
7741 if (TARGET_BIG_ENDIAN)
7742 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7743 reg_names[gparg], reg_names[fparg + 1], s,
7744 reg_names[gparg + 1], reg_names[fparg]);
7746 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7747 reg_names[gparg], reg_names[fparg], s,
7748 reg_names[gparg + 1], reg_names[fparg + 1]);
7761 /* Build a mips16 function stub. This is used for functions which
7762 take arguments in the floating point registers. It is 32 bit code
7763 that moves the floating point args into the general registers, and
7764 then jumps to the 16 bit code. */
7767 build_mips16_function_stub (FILE *file)
7770 char *secname, *stubname;
7771 tree stubid, stubdecl;
7775 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7776 secname = (char *) alloca (strlen (fnname) + 20);
7777 sprintf (secname, ".mips16.fn.%s", fnname);
7778 stubname = (char *) alloca (strlen (fnname) + 20);
7779 sprintf (stubname, "__fn_stub_%s", fnname);
7780 stubid = get_identifier (stubname);
7781 stubdecl = build_decl (FUNCTION_DECL, stubid,
7782 build_function_type (void_type_node, NULL_TREE));
7783 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7785 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7787 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7789 fprintf (file, "%s%s",
7790 need_comma ? ", " : "",
7791 (f & 3) == 1 ? "float" : "double");
7794 fprintf (file, ")\n");
7796 fprintf (file, "\t.set\tnomips16\n");
7797 function_section (stubdecl);
7798 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7800 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7801 within a .ent, and we cannot emit another .ent. */
7802 if (!FUNCTION_NAME_ALREADY_DECLARED)
7804 fputs ("\t.ent\t", file);
7805 assemble_name (file, stubname);
7809 assemble_name (file, stubname);
7810 fputs (":\n", file);
7812 /* We don't want the assembler to insert any nops here. */
7813 fprintf (file, "\t.set\tnoreorder\n");
7815 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7817 fprintf (asm_out_file, "\t.set\tnoat\n");
7818 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7819 assemble_name (file, fnname);
7820 fprintf (file, "\n");
7821 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7822 fprintf (asm_out_file, "\t.set\tat\n");
7824 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7825 with one of the mfc1 instructions, because the result is not
7826 available for one instruction, so if the very first instruction
7827 in the function refers to the register, it will see the wrong
7829 fprintf (file, "\tnop\n");
7831 fprintf (file, "\t.set\treorder\n");
7833 if (!FUNCTION_NAME_ALREADY_DECLARED)
7835 fputs ("\t.end\t", file);
7836 assemble_name (file, stubname);
7840 fprintf (file, "\t.set\tmips16\n");
7842 function_section (current_function_decl);
7845 /* We keep a list of functions for which we have already built stubs
7846 in build_mips16_call_stub. */
7850 struct mips16_stub *next;
7855 static struct mips16_stub *mips16_stubs;
7857 /* Build a call stub for a mips16 call. A stub is needed if we are
7858 passing any floating point values which should go into the floating
7859 point registers. If we are, and the call turns out to be to a 32
7860 bit function, the stub will be used to move the values into the
7861 floating point registers before calling the 32 bit function. The
7862 linker will magically adjust the function call to either the 16 bit
7863 function or the 32 bit stub, depending upon where the function call
7864 is actually defined.
7866 Similarly, we need a stub if the return value might come back in a
7867 floating point register.
7869 RETVAL is the location of the return value, or null if this is
7870 a call rather than a call_value. FN is the address of the
7871 function and ARG_SIZE is the size of the arguments. FP_CODE
7872 is the code built by function_arg. This function returns a nonzero
7873 value if it builds the call instruction itself. */
7876 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7880 char *secname, *stubname;
7881 struct mips16_stub *l;
7882 tree stubid, stubdecl;
7886 /* We don't need to do anything if we aren't in mips16 mode, or if
7887 we were invoked with the -msoft-float option. */
7888 if (! TARGET_MIPS16 || ! mips16_hard_float)
7891 /* Figure out whether the value might come back in a floating point
7893 fpret = (retval != 0
7894 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7895 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7897 /* We don't need to do anything if there were no floating point
7898 arguments and the value will not be returned in a floating point
7900 if (fp_code == 0 && ! fpret)
7903 /* We don't need to do anything if this is a call to a special
7904 mips16 support function. */
7905 if (GET_CODE (fn) == SYMBOL_REF
7906 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7909 /* This code will only work for o32 and o64 abis. The other ABI's
7910 require more sophisticated support. */
7911 gcc_assert (TARGET_OLDABI);
7913 /* We can only handle SFmode and DFmode floating point return
7916 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
7918 /* If we're calling via a function pointer, then we must always call
7919 via a stub. There are magic stubs provided in libgcc.a for each
7920 of the required cases. Each of them expects the function address
7921 to arrive in register $2. */
7923 if (GET_CODE (fn) != SYMBOL_REF)
7929 /* ??? If this code is modified to support other ABI's, we need
7930 to handle PARALLEL return values here. */
7932 sprintf (buf, "__mips16_call_stub_%s%d",
7934 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7937 id = get_identifier (buf);
7938 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7940 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7942 if (retval == NULL_RTX)
7943 insn = gen_call_internal (stub_fn, arg_size);
7945 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7946 insn = emit_call_insn (insn);
7948 /* Put the register usage information on the CALL. */
7949 CALL_INSN_FUNCTION_USAGE (insn) =
7950 gen_rtx_EXPR_LIST (VOIDmode,
7951 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7952 CALL_INSN_FUNCTION_USAGE (insn));
7954 /* If we are handling a floating point return value, we need to
7955 save $18 in the function prologue. Putting a note on the
7956 call will mean that regs_ever_live[$18] will be true if the
7957 call is not eliminated, and we can check that in the prologue
7960 CALL_INSN_FUNCTION_USAGE (insn) =
7961 gen_rtx_EXPR_LIST (VOIDmode,
7962 gen_rtx_USE (VOIDmode,
7963 gen_rtx_REG (word_mode, 18)),
7964 CALL_INSN_FUNCTION_USAGE (insn));
7966 /* Return 1 to tell the caller that we've generated the call
7971 /* We know the function we are going to call. If we have already
7972 built a stub, we don't need to do anything further. */
7974 fnname = XSTR (fn, 0);
7975 for (l = mips16_stubs; l != NULL; l = l->next)
7976 if (strcmp (l->name, fnname) == 0)
7981 /* Build a special purpose stub. When the linker sees a
7982 function call in mips16 code, it will check where the target
7983 is defined. If the target is a 32 bit call, the linker will
7984 search for the section defined here. It can tell which
7985 symbol this section is associated with by looking at the
7986 relocation information (the name is unreliable, since this
7987 might be a static function). If such a section is found, the
7988 linker will redirect the call to the start of the magic
7991 If the function does not return a floating point value, the
7992 special stub section is named
7995 If the function does return a floating point value, the stub
7997 .mips16.call.fp.FNNAME
8000 secname = (char *) alloca (strlen (fnname) + 40);
8001 sprintf (secname, ".mips16.call.%s%s",
8004 stubname = (char *) alloca (strlen (fnname) + 20);
8005 sprintf (stubname, "__call_stub_%s%s",
8008 stubid = get_identifier (stubname);
8009 stubdecl = build_decl (FUNCTION_DECL, stubid,
8010 build_function_type (void_type_node, NULL_TREE));
8011 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8013 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8015 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8019 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8021 fprintf (asm_out_file, "%s%s",
8022 need_comma ? ", " : "",
8023 (f & 3) == 1 ? "float" : "double");
8026 fprintf (asm_out_file, ")\n");
8028 fprintf (asm_out_file, "\t.set\tnomips16\n");
8029 assemble_start_function (stubdecl, stubname);
8031 if (!FUNCTION_NAME_ALREADY_DECLARED)
8033 fputs ("\t.ent\t", asm_out_file);
8034 assemble_name (asm_out_file, stubname);
8035 fputs ("\n", asm_out_file);
8037 assemble_name (asm_out_file, stubname);
8038 fputs (":\n", asm_out_file);
8041 /* We build the stub code by hand. That's the only way we can
8042 do it, since we can't generate 32 bit code during a 16 bit
8045 /* We don't want the assembler to insert any nops here. */
8046 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8048 mips16_fp_args (asm_out_file, fp_code, 0);
8052 fprintf (asm_out_file, "\t.set\tnoat\n");
8053 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8055 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8056 fprintf (asm_out_file, "\t.set\tat\n");
8057 /* Unfortunately, we can't fill the jump delay slot. We
8058 can't fill with one of the mtc1 instructions, because the
8059 result is not available for one instruction, so if the
8060 very first instruction in the function refers to the
8061 register, it will see the wrong value. */
8062 fprintf (asm_out_file, "\tnop\n");
8066 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8067 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8068 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8069 /* As above, we can't fill the delay slot. */
8070 fprintf (asm_out_file, "\tnop\n");
8071 if (GET_MODE (retval) == SFmode)
8072 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8073 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8076 if (TARGET_BIG_ENDIAN)
8078 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8079 reg_names[GP_REG_FIRST + 2],
8080 reg_names[FP_REG_FIRST + 1]);
8081 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8082 reg_names[GP_REG_FIRST + 3],
8083 reg_names[FP_REG_FIRST + 0]);
8087 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8088 reg_names[GP_REG_FIRST + 2],
8089 reg_names[FP_REG_FIRST + 0]);
8090 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8091 reg_names[GP_REG_FIRST + 3],
8092 reg_names[FP_REG_FIRST + 1]);
8095 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8096 /* As above, we can't fill the delay slot. */
8097 fprintf (asm_out_file, "\tnop\n");
8100 fprintf (asm_out_file, "\t.set\treorder\n");
8102 #ifdef ASM_DECLARE_FUNCTION_SIZE
8103 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8106 if (!FUNCTION_NAME_ALREADY_DECLARED)
8108 fputs ("\t.end\t", asm_out_file);
8109 assemble_name (asm_out_file, stubname);
8110 fputs ("\n", asm_out_file);
8113 fprintf (asm_out_file, "\t.set\tmips16\n");
8115 /* Record this stub. */
8116 l = (struct mips16_stub *) xmalloc (sizeof *l);
8117 l->name = xstrdup (fnname);
8119 l->next = mips16_stubs;
8123 /* If we expect a floating point return value, but we've built a
8124 stub which does not expect one, then we're in trouble. We can't
8125 use the existing stub, because it won't handle the floating point
8126 value. We can't build a new stub, because the linker won't know
8127 which stub to use for the various calls in this object file.
8128 Fortunately, this case is illegal, since it means that a function
8129 was declared in two different ways in a single compilation. */
8130 if (fpret && ! l->fpret)
8131 error ("cannot handle inconsistent calls to %qs", fnname);
8133 /* If we are calling a stub which handles a floating point return
8134 value, we need to arrange to save $18 in the prologue. We do
8135 this by marking the function call as using the register. The
8136 prologue will later see that it is used, and emit code to save
8143 if (retval == NULL_RTX)
8144 insn = gen_call_internal (fn, arg_size);
8146 insn = gen_call_value_internal (retval, fn, arg_size);
8147 insn = emit_call_insn (insn);
8149 CALL_INSN_FUNCTION_USAGE (insn) =
8150 gen_rtx_EXPR_LIST (VOIDmode,
8151 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8152 CALL_INSN_FUNCTION_USAGE (insn));
8154 /* Return 1 to tell the caller that we've generated the call
8159 /* Return 0 to let the caller generate the call insn. */
8163 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8164 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8166 struct mips16_constant {
8167 struct mips16_constant *next;
8170 enum machine_mode mode;
8173 /* Information about an incomplete mips16 constant pool. FIRST is the
8174 first constant, HIGHEST_ADDRESS is the highest address that the first
8175 byte of the pool can have, and INSN_ADDRESS is the current instruction
8178 struct mips16_constant_pool {
8179 struct mips16_constant *first;
8180 int highest_address;
8184 /* Add constant VALUE to POOL and return its label. MODE is the
8185 value's mode (used for CONST_INTs, etc.). */
8188 add_constant (struct mips16_constant_pool *pool,
8189 rtx value, enum machine_mode mode)
8191 struct mips16_constant **p, *c;
8192 bool first_of_size_p;
8194 /* See whether the constant is already in the pool. If so, return the
8195 existing label, otherwise leave P pointing to the place where the
8196 constant should be added.
8198 Keep the pool sorted in increasing order of mode size so that we can
8199 reduce the number of alignments needed. */
8200 first_of_size_p = true;
8201 for (p = &pool->first; *p != 0; p = &(*p)->next)
8203 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8205 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8207 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8208 first_of_size_p = false;
8211 /* In the worst case, the constant needed by the earliest instruction
8212 will end up at the end of the pool. The entire pool must then be
8213 accessible from that instruction.
8215 When adding the first constant, set the pool's highest address to
8216 the address of the first out-of-range byte. Adjust this address
8217 downwards each time a new constant is added. */
8218 if (pool->first == 0)
8219 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8220 is the address of the instruction with the lowest two bits clear.
8221 The base PC value for ld has the lowest three bits clear. Assume
8222 the worst case here. */
8223 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8224 pool->highest_address -= GET_MODE_SIZE (mode);
8225 if (first_of_size_p)
8226 /* Take into account the worst possible padding due to alignment. */
8227 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8229 /* Create a new entry. */
8230 c = (struct mips16_constant *) xmalloc (sizeof *c);
8233 c->label = gen_label_rtx ();
8240 /* Output constant VALUE after instruction INSN and return the last
8241 instruction emitted. MODE is the mode of the constant. */
8244 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8246 switch (GET_MODE_CLASS (mode))
8250 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8251 return emit_insn_after (gen_consttable_int (value, size), insn);
8255 return emit_insn_after (gen_consttable_float (value), insn);
8257 case MODE_VECTOR_FLOAT:
8258 case MODE_VECTOR_INT:
8261 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8262 insn = dump_constants_1 (GET_MODE_INNER (mode),
8263 CONST_VECTOR_ELT (value, i), insn);
8273 /* Dump out the constants in CONSTANTS after INSN. */
8276 dump_constants (struct mips16_constant *constants, rtx insn)
8278 struct mips16_constant *c, *next;
8282 for (c = constants; c != NULL; c = next)
8284 /* If necessary, increase the alignment of PC. */
8285 if (align < GET_MODE_SIZE (c->mode))
8287 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8288 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8290 align = GET_MODE_SIZE (c->mode);
8292 insn = emit_label_after (c->label, insn);
8293 insn = dump_constants_1 (c->mode, c->value, insn);
8299 emit_barrier_after (insn);
8302 /* Return the length of instruction INSN. */
8305 mips16_insn_length (rtx insn)
8309 rtx body = PATTERN (insn);
8310 if (GET_CODE (body) == ADDR_VEC)
8311 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8312 if (GET_CODE (body) == ADDR_DIFF_VEC)
8313 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8315 return get_attr_length (insn);
8318 /* Rewrite *X so that constant pool references refer to the constant's
8319 label instead. DATA points to the constant pool structure. */
8322 mips16_rewrite_pool_refs (rtx *x, void *data)
8324 struct mips16_constant_pool *pool = data;
8325 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8326 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8327 get_pool_constant (*x),
8328 get_pool_mode (*x)));
8332 /* Build MIPS16 constant pools. */
8335 mips16_lay_out_constants (void)
8337 struct mips16_constant_pool pool;
8341 memset (&pool, 0, sizeof (pool));
8342 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8344 /* Rewrite constant pool references in INSN. */
8346 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8348 pool.insn_address += mips16_insn_length (insn);
8350 if (pool.first != NULL)
8352 /* If there are no natural barriers between the first user of
8353 the pool and the highest acceptable address, we'll need to
8354 create a new instruction to jump around the constant pool.
8355 In the worst case, this instruction will be 4 bytes long.
8357 If it's too late to do this transformation after INSN,
8358 do it immediately before INSN. */
8359 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8363 label = gen_label_rtx ();
8365 jump = emit_jump_insn_before (gen_jump (label), insn);
8366 JUMP_LABEL (jump) = label;
8367 LABEL_NUSES (label) = 1;
8368 barrier = emit_barrier_after (jump);
8370 emit_label_after (label, barrier);
8371 pool.insn_address += 4;
8374 /* See whether the constant pool is now out of range of the first
8375 user. If so, output the constants after the previous barrier.
8376 Note that any instructions between BARRIER and INSN (inclusive)
8377 will use negative offsets to refer to the pool. */
8378 if (pool.insn_address > pool.highest_address)
8380 dump_constants (pool.first, barrier);
8384 else if (BARRIER_P (insn))
8388 dump_constants (pool.first, get_last_insn ());
8391 /* A temporary variable used by for_each_rtx callbacks, etc. */
8392 static rtx mips_sim_insn;
8394 /* A structure representing the state of the processor pipeline.
8395 Used by the mips_sim_* family of functions. */
8397 /* The maximum number of instructions that can be issued in a cycle.
8398 (Caches mips_issue_rate.) */
8399 unsigned int issue_rate;
8401 /* The current simulation time. */
8404 /* How many more instructions can be issued in the current cycle. */
8405 unsigned int insns_left;
8407 /* LAST_SET[X].INSN is the last instruction to set register X.
8408 LAST_SET[X].TIME is the time at which that instruction was issued.
8409 INSN is null if no instruction has yet set register X. */
8413 } last_set[FIRST_PSEUDO_REGISTER];
8415 /* The pipeline's current DFA state. */
8419 /* Reset STATE to the initial simulation state. */
8422 mips_sim_reset (struct mips_sim *state)
8425 state->insns_left = state->issue_rate;
8426 memset (&state->last_set, 0, sizeof (state->last_set));
8427 state_reset (state->dfa_state);
8430 /* Initialize STATE before its first use. DFA_STATE points to an
8431 allocated but uninitialized DFA state. */
8434 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8436 state->issue_rate = mips_issue_rate ();
8437 state->dfa_state = dfa_state;
8438 mips_sim_reset (state);
8441 /* Advance STATE by one clock cycle. */
8444 mips_sim_next_cycle (struct mips_sim *state)
8447 state->insns_left = state->issue_rate;
8448 state_transition (state->dfa_state, 0);
8451 /* Advance simulation state STATE until instruction INSN can read
8455 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8459 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8460 if (state->last_set[REGNO (reg) + i].insn != 0)
8464 t = state->last_set[REGNO (reg) + i].time;
8465 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8466 while (state->time < t)
8467 mips_sim_next_cycle (state);
8471 /* A for_each_rtx callback. If *X is a register, advance simulation state
8472 DATA until mips_sim_insn can read the register's value. */
8475 mips_sim_wait_regs_2 (rtx *x, void *data)
8478 mips_sim_wait_reg (data, mips_sim_insn, *x);
8482 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8485 mips_sim_wait_regs_1 (rtx *x, void *data)
8487 for_each_rtx (x, mips_sim_wait_regs_2, data);
8490 /* Advance simulation state STATE until all of INSN's register
8491 dependencies are satisfied. */
8494 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8496 mips_sim_insn = insn;
8497 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8500 /* Advance simulation state STATE until the units required by
8501 instruction INSN are available. */
8504 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8508 tmp_state = alloca (state_size ());
8509 while (state->insns_left == 0
8510 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8511 state_transition (tmp_state, insn) >= 0))
8512 mips_sim_next_cycle (state);
8515 /* Advance simulation state STATE until INSN is ready to issue. */
8518 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8520 mips_sim_wait_regs (state, insn);
8521 mips_sim_wait_units (state, insn);
8524 /* mips_sim_insn has just set X. Update the LAST_SET array
8525 in simulation state DATA. */
8528 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8530 struct mips_sim *state;
8535 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8537 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8538 state->last_set[REGNO (x) + i].time = state->time;
8542 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8543 can issue immediately (i.e., that mips_sim_wait_insn has already
8547 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8549 state_transition (state->dfa_state, insn);
8550 state->insns_left--;
8552 mips_sim_insn = insn;
8553 note_stores (PATTERN (insn), mips_sim_record_set, state);
8556 /* Simulate issuing a NOP in state STATE. */
8559 mips_sim_issue_nop (struct mips_sim *state)
8561 if (state->insns_left == 0)
8562 mips_sim_next_cycle (state);
8563 state->insns_left--;
8566 /* Update simulation state STATE so that it's ready to accept the instruction
8567 after INSN. INSN should be part of the main rtl chain, not a member of a
8571 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8573 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8575 mips_sim_issue_nop (state);
8577 switch (GET_CODE (SEQ_BEGIN (insn)))
8581 /* We can't predict the processor state after a call or label. */
8582 mips_sim_reset (state);
8586 /* The delay slots of branch likely instructions are only executed
8587 when the branch is taken. Therefore, if the caller has simulated
8588 the delay slot instruction, STATE does not really reflect the state
8589 of the pipeline for the instruction after the delay slot. Also,
8590 branch likely instructions tend to incur a penalty when not taken,
8591 so there will probably be an extra delay between the branch and
8592 the instruction after the delay slot. */
8593 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8594 mips_sim_reset (state);
8602 /* The VR4130 pipeline issues aligned pairs of instructions together,
8603 but it stalls the second instruction if it depends on the first.
8604 In order to cut down the amount of logic required, this dependence
8605 check is not based on a full instruction decode. Instead, any non-SPECIAL
8606 instruction is assumed to modify the register specified by bits 20-16
8607 (which is usually the "rt" field).
8609 In beq, beql, bne and bnel instructions, the rt field is actually an
8610 input, so we can end up with a false dependence between the branch
8611 and its delay slot. If this situation occurs in instruction INSN,
8612 try to avoid it by swapping rs and rt. */
8615 vr4130_avoid_branch_rt_conflict (rtx insn)
8619 first = SEQ_BEGIN (insn);
8620 second = SEQ_END (insn);
8622 && NONJUMP_INSN_P (second)
8623 && GET_CODE (PATTERN (first)) == SET
8624 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8625 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8627 /* Check for the right kind of condition. */
8628 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8629 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8630 && REG_P (XEXP (cond, 0))
8631 && REG_P (XEXP (cond, 1))
8632 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8633 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8635 /* SECOND mentions the rt register but not the rs register. */
8636 rtx tmp = XEXP (cond, 0);
8637 XEXP (cond, 0) = XEXP (cond, 1);
8638 XEXP (cond, 1) = tmp;
8643 /* Implement -mvr4130-align. Go through each basic block and simulate the
8644 processor pipeline. If we find that a pair of instructions could execute
8645 in parallel, and the first of those instruction is not 8-byte aligned,
8646 insert a nop to make it aligned. */
8649 vr4130_align_insns (void)
8651 struct mips_sim state;
8652 rtx insn, subinsn, last, last2, next;
8657 /* LAST is the last instruction before INSN to have a nonzero length.
8658 LAST2 is the last such instruction before LAST. */
8662 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8665 mips_sim_init (&state, alloca (state_size ()));
8666 for (insn = get_insns (); insn != 0; insn = next)
8668 unsigned int length;
8670 next = NEXT_INSN (insn);
8672 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8673 This isn't really related to the alignment pass, but we do it on
8674 the fly to avoid a separate instruction walk. */
8675 vr4130_avoid_branch_rt_conflict (insn);
8677 if (USEFUL_INSN_P (insn))
8678 FOR_EACH_SUBINSN (subinsn, insn)
8680 mips_sim_wait_insn (&state, subinsn);
8682 /* If we want this instruction to issue in parallel with the
8683 previous one, make sure that the previous instruction is
8684 aligned. There are several reasons why this isn't worthwhile
8685 when the second instruction is a call:
8687 - Calls are less likely to be performance critical,
8688 - There's a good chance that the delay slot can execute
8689 in parallel with the call.
8690 - The return address would then be unaligned.
8692 In general, if we're going to insert a nop between instructions
8693 X and Y, it's better to insert it immediately after X. That
8694 way, if the nop makes Y aligned, it will also align any labels
8696 if (state.insns_left != state.issue_rate
8697 && !CALL_P (subinsn))
8699 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8701 /* SUBINSN is the first instruction in INSN and INSN is
8702 aligned. We want to align the previous instruction
8703 instead, so insert a nop between LAST2 and LAST.
8705 Note that LAST could be either a single instruction
8706 or a branch with a delay slot. In the latter case,
8707 LAST, like INSN, is already aligned, but the delay
8708 slot must have some extra delay that stops it from
8709 issuing at the same time as the branch. We therefore
8710 insert a nop before the branch in order to align its
8712 emit_insn_after (gen_nop (), last2);
8715 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8717 /* SUBINSN is the delay slot of INSN, but INSN is
8718 currently unaligned. Insert a nop between
8719 LAST and INSN to align it. */
8720 emit_insn_after (gen_nop (), last);
8724 mips_sim_issue_insn (&state, subinsn);
8726 mips_sim_finish_insn (&state, insn);
8728 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8729 length = get_attr_length (insn);
8732 /* If the instruction is an asm statement or multi-instruction
8733 mips.md patern, the length is only an estimate. Insert an
8734 8 byte alignment after it so that the following instructions
8735 can be handled correctly. */
8736 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8737 && (recog_memoized (insn) < 0 || length >= 8))
8739 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8740 next = NEXT_INSN (next);
8741 mips_sim_next_cycle (&state);
8744 else if (length & 4)
8745 aligned_p = !aligned_p;
8750 /* See whether INSN is an aligned label. */
8751 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8757 /* Subroutine of mips_reorg. If there is a hazard between INSN
8758 and a previous instruction, avoid it by inserting nops after
8761 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8762 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8763 before using the value of that register. *HILO_DELAY counts the
8764 number of instructions since the last hilo hazard (that is,
8765 the number of instructions since the last mflo or mfhi).
8767 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8768 for the next instruction.
8770 LO_REG is an rtx for the LO register, used in dependence checking. */
8773 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8774 rtx *delayed_reg, rtx lo_reg)
8782 pattern = PATTERN (insn);
8784 /* Do not put the whole function in .set noreorder if it contains
8785 an asm statement. We don't know whether there will be hazards
8786 between the asm statement and the gcc-generated code. */
8787 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8788 cfun->machine->all_noreorder_p = false;
8790 /* Ignore zero-length instructions (barriers and the like). */
8791 ninsns = get_attr_length (insn) / 4;
8795 /* Work out how many nops are needed. Note that we only care about
8796 registers that are explicitly mentioned in the instruction's pattern.
8797 It doesn't matter that calls use the argument registers or that they
8798 clobber hi and lo. */
8799 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8800 nops = 2 - *hilo_delay;
8801 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8806 /* Insert the nops between this instruction and the previous one.
8807 Each new nop takes us further from the last hilo hazard. */
8808 *hilo_delay += nops;
8810 emit_insn_after (gen_hazard_nop (), after);
8812 /* Set up the state for the next instruction. */
8813 *hilo_delay += ninsns;
8815 if (INSN_CODE (insn) >= 0)
8816 switch (get_attr_hazard (insn))
8826 set = single_set (insn);
8827 gcc_assert (set != 0);
8828 *delayed_reg = SET_DEST (set);
8834 /* Go through the instruction stream and insert nops where necessary.
8835 See if the whole function can then be put into .set noreorder &
8839 mips_avoid_hazards (void)
8841 rtx insn, last_insn, lo_reg, delayed_reg;
8844 /* Force all instructions to be split into their final form. */
8845 split_all_insns_noflow ();
8847 /* Recalculate instruction lengths without taking nops into account. */
8848 cfun->machine->ignore_hazard_length_p = true;
8849 shorten_branches (get_insns ());
8851 cfun->machine->all_noreorder_p = true;
8853 /* Profiled functions can't be all noreorder because the profiler
8854 support uses assembler macros. */
8855 if (current_function_profile)
8856 cfun->machine->all_noreorder_p = false;
8858 /* Code compiled with -mfix-vr4120 can't be all noreorder because
8859 we rely on the assembler to work around some errata. */
8860 if (TARGET_FIX_VR4120)
8861 cfun->machine->all_noreorder_p = false;
8863 /* The same is true for -mfix-vr4130 if we might generate mflo or
8864 mfhi instructions. Note that we avoid using mflo and mfhi if
8865 the VR4130 macc and dmacc instructions are available instead;
8866 see the *mfhilo_{si,di}_macc patterns. */
8867 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
8868 cfun->machine->all_noreorder_p = false;
8873 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8875 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8878 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8879 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8880 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8881 &hilo_delay, &delayed_reg, lo_reg);
8883 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8884 &delayed_reg, lo_reg);
8891 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8897 mips16_lay_out_constants ();
8898 else if (TARGET_EXPLICIT_RELOCS)
8900 if (mips_flag_delayed_branch)
8901 dbr_schedule (get_insns (), dump_file);
8902 mips_avoid_hazards ();
8903 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8904 vr4130_align_insns ();
8908 /* This function does three things:
8910 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8911 - Register the mips16 hardware floating point stubs.
8912 - Register the gofast functions if selected using --enable-gofast. */
8914 #include "config/gofast.h"
8917 mips_init_libfuncs (void)
8919 if (TARGET_FIX_VR4120)
8921 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8922 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8925 if (TARGET_MIPS16 && mips16_hard_float)
8927 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8928 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8929 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8930 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8932 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8933 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8934 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8935 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8936 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8937 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8939 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8940 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8942 if (TARGET_DOUBLE_FLOAT)
8944 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8945 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8946 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8947 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8949 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8950 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8951 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8952 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8953 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8954 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8956 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8957 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8959 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8960 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8964 gofast_maybe_init_libfuncs ();
8967 /* Return a number assessing the cost of moving a register in class
8968 FROM to class TO. The classes are expressed using the enumeration
8969 values such as `GENERAL_REGS'. A value of 2 is the default; other
8970 values are interpreted relative to that.
8972 It is not required that the cost always equal 2 when FROM is the
8973 same as TO; on some machines it is expensive to move between
8974 registers if they are not general registers.
8976 If reload sees an insn consisting of a single `set' between two
8977 hard registers, and if `REGISTER_MOVE_COST' applied to their
8978 classes returns a value of 2, reload does not check to ensure that
8979 the constraints of the insn are met. Setting a cost of other than
8980 2 will allow reload to verify that the constraints are met. You
8981 should do this if the `movM' pattern's constraints do not allow
8984 ??? We make the cost of moving from HI/LO into general
8985 registers the same as for one of moving general registers to
8986 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8987 pseudo to HI/LO. This might hurt optimizations though, it
8988 isn't clear if it is wise. And it might not work in all cases. We
8989 could solve the DImode LO reg problem by using a multiply, just
8990 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8991 problem by using divide instructions. divu puts the remainder in
8992 the HI reg, so doing a divide by -1 will move the value in the HI
8993 reg for all values except -1. We could handle that case by using a
8994 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8995 a compare/branch to test the input value to see which instruction
8996 we need to use. This gets pretty messy, but it is feasible. */
8999 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9000 enum reg_class to, enum reg_class from)
9002 if (from == M16_REGS && GR_REG_CLASS_P (to))
9004 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9006 else if (GR_REG_CLASS_P (from))
9010 else if (to == M16_NA_REGS)
9012 else if (GR_REG_CLASS_P (to))
9019 else if (to == FP_REGS)
9021 else if (reg_class_subset_p (to, ACC_REGS))
9028 else if (COP_REG_CLASS_P (to))
9033 else if (from == FP_REGS)
9035 if (GR_REG_CLASS_P (to))
9037 else if (to == FP_REGS)
9039 else if (to == ST_REGS)
9042 else if (reg_class_subset_p (from, ACC_REGS))
9044 if (GR_REG_CLASS_P (to))
9052 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9054 else if (COP_REG_CLASS_P (from))
9060 ??? What cases are these? Shouldn't we return 2 here? */
9065 /* Return the length of INSN. LENGTH is the initial length computed by
9066 attributes in the machine-description file. */
9069 mips_adjust_insn_length (rtx insn, int length)
9071 /* A unconditional jump has an unfilled delay slot if it is not part
9072 of a sequence. A conditional jump normally has a delay slot, but
9073 does not on MIPS16. */
9074 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9077 /* See how many nops might be needed to avoid hardware hazards. */
9078 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9079 switch (get_attr_hazard (insn))
9093 /* All MIPS16 instructions are a measly two bytes. */
9101 /* Return an asm sequence to start a noat block and load the address
9102 of a label into $1. */
9105 mips_output_load_label (void)
9107 if (TARGET_EXPLICIT_RELOCS)
9111 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9114 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9117 if (ISA_HAS_LOAD_DELAY)
9118 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9119 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9123 if (Pmode == DImode)
9124 return "%[dla\t%@,%0";
9126 return "%[la\t%@,%0";
9131 /* Output assembly instructions to peform a conditional branch.
9133 INSN is the branch instruction. OPERANDS[0] is the condition.
9134 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9135 of the first operand to the condition. If TWO_OPERANDS_P is
9136 nonzero the comparison takes two operands; OPERANDS[3] will be the
9139 If INVERTED_P is nonzero we are to branch if the condition does
9140 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9142 LENGTH is the length (in bytes) of the sequence we are to generate.
9143 That tells us whether to generate a simple conditional branch, or a
9144 reversed conditional branch around a `jr' instruction. */
9146 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
9147 int float_p, int inverted_p, int length)
9149 static char buffer[200];
9150 /* The kind of comparison we are doing. */
9151 enum rtx_code code = GET_CODE (operands[0]);
9152 /* Nonzero if the opcode for the comparison needs a `z' indicating
9153 that it is a comparison against zero. */
9155 /* A string to use in the assembly output to represent the first
9157 const char *op1 = "%z2";
9158 /* A string to use in the assembly output to represent the second
9159 operand. Use the hard-wired zero register if there's no second
9161 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9162 /* The operand-printing string for the comparison. */
9163 const char *const comp = (float_p ? "%F0" : "%C0");
9164 /* The operand-printing string for the inverted comparison. */
9165 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9167 /* The MIPS processors (for levels of the ISA at least two), have
9168 "likely" variants of each branch instruction. These instructions
9169 annul the instruction in the delay slot if the branch is not
9171 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9173 if (!two_operands_p)
9175 /* To compute whether than A > B, for example, we normally
9176 subtract B from A and then look at the sign bit. But, if we
9177 are doing an unsigned comparison, and B is zero, we don't
9178 have to do the subtraction. Instead, we can just check to
9179 see if A is nonzero. Thus, we change the CODE here to
9180 reflect the simpler comparison operation. */
9192 /* A condition which will always be true. */
9198 /* A condition which will always be false. */
9204 /* Not a special case. */
9209 /* Relative comparisons are always done against zero. But
9210 equality comparisons are done between two operands, and therefore
9211 do not require a `z' in the assembly language output. */
9212 need_z_p = (!float_p && code != EQ && code != NE);
9213 /* For comparisons against zero, the zero is not provided
9218 /* Begin by terminating the buffer. That way we can always use
9219 strcat to add to it. */
9226 /* Just a simple conditional branch. */
9228 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9229 inverted_p ? inverted_comp : comp);
9231 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9232 inverted_p ? inverted_comp : comp,
9233 need_z_p ? "z" : "",
9243 /* Generate a reversed conditional branch around ` j'
9256 If the original branch was a likely branch, the delay slot
9257 must be executed only if the branch is taken, so generate:
9269 When generating PIC, instead of:
9282 rtx target = gen_label_rtx ();
9284 orig_target = operands[1];
9285 operands[1] = target;
9286 /* Generate the reversed comparison. This takes four
9289 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9290 inverted_p ? comp : inverted_comp);
9292 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9293 inverted_p ? comp : inverted_comp,
9294 need_z_p ? "z" : "",
9297 output_asm_insn (buffer, operands);
9299 if (length != 16 && length != 28 && ! mips_branch_likely)
9301 /* Output delay slot instruction. */
9302 rtx insn = final_sequence;
9303 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9305 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9308 output_asm_insn ("%#", 0);
9311 output_asm_insn ("j\t%0", &orig_target);
9314 output_asm_insn (mips_output_load_label (), &orig_target);
9315 output_asm_insn ("jr\t%@%]", 0);
9318 if (length != 16 && length != 28 && mips_branch_likely)
9320 /* Output delay slot instruction. */
9321 rtx insn = final_sequence;
9322 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9324 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9327 output_asm_insn ("%#", 0);
9329 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9330 CODE_LABEL_NUMBER (target));
9343 /* Used to output div or ddiv instruction DIVISION, which has the operands
9344 given by OPERANDS. Add in a divide-by-zero check if needed.
9346 When working around R4000 and R4400 errata, we need to make sure that
9347 the division is not immediately followed by a shift[1][2]. We also
9348 need to stop the division from being put into a branch delay slot[3].
9349 The easiest way to avoid both problems is to add a nop after the
9350 division. When a divide-by-zero check is needed, this nop can be
9351 used to fill the branch delay slot.
9353 [1] If a double-word or a variable shift executes immediately
9354 after starting an integer division, the shift may give an
9355 incorrect result. See quotations of errata #16 and #28 from
9356 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9357 in mips.md for details.
9359 [2] A similar bug to [1] exists for all revisions of the
9360 R4000 and the R4400 when run in an MC configuration.
9361 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9363 "19. In this following sequence:
9365 ddiv (or ddivu or div or divu)
9366 dsll32 (or dsrl32, dsra32)
9368 if an MPT stall occurs, while the divide is slipping the cpu
9369 pipeline, then the following double shift would end up with an
9372 Workaround: The compiler needs to avoid generating any
9373 sequence with divide followed by extended double shift."
9375 This erratum is also present in "MIPS R4400MC Errata, Processor
9376 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9377 & 3.0" as errata #10 and #4, respectively.
9379 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9380 (also valid for MIPS R4000MC processors):
9382 "52. R4000SC: This bug does not apply for the R4000PC.
9384 There are two flavors of this bug:
9386 1) If the instruction just after divide takes an RF exception
9387 (tlb-refill, tlb-invalid) and gets an instruction cache
9388 miss (both primary and secondary) and the line which is
9389 currently in secondary cache at this index had the first
9390 data word, where the bits 5..2 are set, then R4000 would
9391 get a wrong result for the div.
9396 ------------------- # end-of page. -tlb-refill
9401 ------------------- # end-of page. -tlb-invalid
9404 2) If the divide is in the taken branch delay slot, where the
9405 target takes RF exception and gets an I-cache miss for the
9406 exception vector or where I-cache miss occurs for the
9407 target address, under the above mentioned scenarios, the
9408 div would get wrong results.
9411 j r2 # to next page mapped or unmapped
9412 div r8,r9 # this bug would be there as long
9413 # as there is an ICache miss and
9414 nop # the "data pattern" is present
9417 beq r0, r0, NextPage # to Next page
9421 This bug is present for div, divu, ddiv, and ddivu
9424 Workaround: For item 1), OS could make sure that the next page
9425 after the divide instruction is also mapped. For item 2), the
9426 compiler could make sure that the divide instruction is not in
9427 the branch delay slot."
9429 These processors have PRId values of 0x00004220 and 0x00004300 for
9430 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9433 mips_output_division (const char *division, rtx *operands)
9438 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9440 output_asm_insn (s, operands);
9443 if (TARGET_CHECK_ZERO_DIV)
9447 output_asm_insn (s, operands);
9448 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9450 else if (GENERATE_DIVIDE_TRAPS)
9452 output_asm_insn (s, operands);
9457 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9458 output_asm_insn (s, operands);
9459 s = "break\t7%)\n1:";
9465 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9466 with a final "000" replaced by "k". Ignore case.
9468 Note: this function is shared between GCC and GAS. */
9471 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9473 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9474 given++, canonical++;
9476 return ((*given == 0 && *canonical == 0)
9477 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9481 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9482 CPU name. We've traditionally allowed a lot of variation here.
9484 Note: this function is shared between GCC and GAS. */
9487 mips_matching_cpu_name_p (const char *canonical, const char *given)
9489 /* First see if the name matches exactly, or with a final "000"
9491 if (mips_strict_matching_cpu_name_p (canonical, given))
9494 /* If not, try comparing based on numerical designation alone.
9495 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9496 if (TOLOWER (*given) == 'r')
9498 if (!ISDIGIT (*given))
9501 /* Skip over some well-known prefixes in the canonical name,
9502 hoping to find a number there too. */
9503 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9505 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9507 else if (TOLOWER (canonical[0]) == 'r')
9510 return mips_strict_matching_cpu_name_p (canonical, given);
9514 /* Return the mips_cpu_info entry for the processor or ISA given
9515 by CPU_STRING. Return null if the string isn't recognized.
9517 A similar function exists in GAS. */
9519 static const struct mips_cpu_info *
9520 mips_parse_cpu (const char *cpu_string)
9522 const struct mips_cpu_info *p;
9525 /* In the past, we allowed upper-case CPU names, but it doesn't
9526 work well with the multilib machinery. */
9527 for (s = cpu_string; *s != 0; s++)
9530 warning (0, "the cpu name must be lower case");
9534 /* 'from-abi' selects the most compatible architecture for the given
9535 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9536 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9537 version. Look first at the -mgp options, if given, otherwise base
9538 the choice on MASK_64BIT in TARGET_DEFAULT. */
9539 if (strcasecmp (cpu_string, "from-abi") == 0)
9540 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9541 : ABI_NEEDS_64BIT_REGS ? 3
9542 : (TARGET_64BIT ? 3 : 1));
9544 /* 'default' has traditionally been a no-op. Probably not very useful. */
9545 if (strcasecmp (cpu_string, "default") == 0)
9548 for (p = mips_cpu_info_table; p->name != 0; p++)
9549 if (mips_matching_cpu_name_p (p->name, cpu_string))
9556 /* Return the processor associated with the given ISA level, or null
9557 if the ISA isn't valid. */
9559 static const struct mips_cpu_info *
9560 mips_cpu_info_from_isa (int isa)
9562 const struct mips_cpu_info *p;
9564 for (p = mips_cpu_info_table; p->name != 0; p++)
9571 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9572 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9573 they only hold condition code modes, and CCmode is always considered to
9574 be 4 bytes wide. All other registers are word sized. */
9577 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9579 if (ST_REG_P (regno))
9580 return ((GET_MODE_SIZE (mode) + 3) / 4);
9581 else if (! FP_REG_P (regno))
9582 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9584 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9587 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9588 all BLKmode objects are returned in memory. Under the new (N32 and
9589 64-bit MIPS ABIs) small structures are returned in a register.
9590 Objects with varying size must still be returned in memory, of
9594 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9597 return (TYPE_MODE (type) == BLKmode);
9599 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9600 || (int_size_in_bytes (type) == -1));
9604 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9606 return !TARGET_OLDABI;
9609 /* Return true if INSN is a multiply-add or multiply-subtract
9610 instruction and PREV assigns to the accumulator operand. */
9613 mips_linked_madd_p (rtx prev, rtx insn)
9617 x = single_set (insn);
9623 if (GET_CODE (x) == PLUS
9624 && GET_CODE (XEXP (x, 0)) == MULT
9625 && reg_set_p (XEXP (x, 1), prev))
9628 if (GET_CODE (x) == MINUS
9629 && GET_CODE (XEXP (x, 1)) == MULT
9630 && reg_set_p (XEXP (x, 0), prev))
9636 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9637 that may clobber hi or lo. */
9639 static rtx mips_macc_chains_last_hilo;
9641 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9642 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9645 mips_macc_chains_record (rtx insn)
9647 if (get_attr_may_clobber_hilo (insn))
9648 mips_macc_chains_last_hilo = insn;
9651 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9652 has NREADY elements, looking for a multiply-add or multiply-subtract
9653 instruction that is cumulative with mips_macc_chains_last_hilo.
9654 If there is one, promote it ahead of anything else that might
9655 clobber hi or lo. */
9658 mips_macc_chains_reorder (rtx *ready, int nready)
9662 if (mips_macc_chains_last_hilo != 0)
9663 for (i = nready - 1; i >= 0; i--)
9664 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9666 for (j = nready - 1; j > i; j--)
9667 if (recog_memoized (ready[j]) >= 0
9668 && get_attr_may_clobber_hilo (ready[j]))
9670 mips_promote_ready (ready, i, j);
9677 /* The last instruction to be scheduled. */
9679 static rtx vr4130_last_insn;
9681 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9682 points to an rtx that is initially an instruction. Nullify the rtx
9683 if the instruction uses the value of register X. */
9686 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9688 rtx *insn_ptr = data;
9691 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9695 /* Return true if there is true register dependence between vr4130_last_insn
9699 vr4130_true_reg_dependence_p (rtx insn)
9701 note_stores (PATTERN (vr4130_last_insn),
9702 vr4130_true_reg_dependence_p_1, &insn);
9706 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9707 the ready queue and that INSN2 is the instruction after it, return
9708 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9709 in which INSN1 and INSN2 can probably issue in parallel, but for
9710 which (INSN2, INSN1) should be less sensitive to instruction
9711 alignment than (INSN1, INSN2). See 4130.md for more details. */
9714 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9718 /* Check for the following case:
9720 1) there is some other instruction X with an anti dependence on INSN1;
9721 2) X has a higher priority than INSN2; and
9722 3) X is an arithmetic instruction (and thus has no unit restrictions).
9724 If INSN1 is the last instruction blocking X, it would better to
9725 choose (INSN1, X) over (INSN2, INSN1). */
9726 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9727 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9728 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9729 && recog_memoized (XEXP (dep, 0)) >= 0
9730 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9733 if (vr4130_last_insn != 0
9734 && recog_memoized (insn1) >= 0
9735 && recog_memoized (insn2) >= 0)
9737 /* See whether INSN1 and INSN2 use different execution units,
9738 or if they are both ALU-type instructions. If so, they can
9739 probably execute in parallel. */
9740 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9741 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9742 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9744 /* If only one of the instructions has a dependence on
9745 vr4130_last_insn, prefer to schedule the other one first. */
9746 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9747 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9751 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9752 is not an ALU-type instruction and if INSN1 uses the same
9753 execution unit. (Note that if this condition holds, we already
9754 know that INSN2 uses a different execution unit.) */
9755 if (class1 != VR4130_CLASS_ALU
9756 && recog_memoized (vr4130_last_insn) >= 0
9757 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9764 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9765 queue with at least two instructions. Swap the first two if
9766 vr4130_swap_insns_p says that it could be worthwhile. */
9769 vr4130_reorder (rtx *ready, int nready)
9771 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9772 mips_promote_ready (ready, nready - 2, nready - 1);
9775 /* Remove the instruction at index LOWER from ready queue READY and
9776 reinsert it in front of the instruction at index HIGHER. LOWER must
9780 mips_promote_ready (rtx *ready, int lower, int higher)
9785 new_head = ready[lower];
9786 for (i = lower; i < higher; i++)
9787 ready[i] = ready[i + 1];
9788 ready[i] = new_head;
9791 /* Implement TARGET_SCHED_REORDER. */
9794 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9795 rtx *ready, int *nreadyp, int cycle)
9797 if (!reload_completed && TUNE_MACC_CHAINS)
9800 mips_macc_chains_last_hilo = 0;
9802 mips_macc_chains_reorder (ready, *nreadyp);
9804 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9807 vr4130_last_insn = 0;
9809 vr4130_reorder (ready, *nreadyp);
9811 return mips_issue_rate ();
9814 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9817 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9820 switch (GET_CODE (PATTERN (insn)))
9824 /* Don't count USEs and CLOBBERs against the issue rate. */
9829 if (!reload_completed && TUNE_MACC_CHAINS)
9830 mips_macc_chains_record (insn);
9831 vr4130_last_insn = insn;
9837 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9838 dependencies have no cost. */
9841 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9842 rtx dep ATTRIBUTE_UNUSED, int cost)
9844 if (REG_NOTE_KIND (link) != 0)
9849 /* Return the number of instructions that can be issued per cycle. */
9852 mips_issue_rate (void)
9856 case PROCESSOR_R4130:
9857 case PROCESSOR_R5400:
9858 case PROCESSOR_R5500:
9859 case PROCESSOR_R7000:
9860 case PROCESSOR_R9000:
9864 /* This is actually 4, but we get better performance if we claim 3.
9865 This is partly because of unwanted speculative code motion with the
9866 larger number, and partly because in most common cases we can't
9867 reach the theoretical max of 4. */
9875 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9876 be as wide as the scheduling freedom in the DFA. */
9879 mips_multipass_dfa_lookahead (void)
9881 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9882 if (mips_tune == PROCESSOR_SB1)
9888 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9889 return the first operand of the associated "pref" or "prefx" insn. */
9892 mips_prefetch_cookie (rtx write, rtx locality)
9894 /* store_streamed / load_streamed. */
9895 if (INTVAL (locality) <= 0)
9896 return GEN_INT (INTVAL (write) + 4);
9899 if (INTVAL (locality) <= 2)
9902 /* store_retained / load_retained. */
9903 return GEN_INT (INTVAL (write) + 6);
9906 /* MIPS builtin function support. */
9908 struct builtin_description
9910 /* The code of the main .md file instruction. See mips_builtin_type
9911 for more information. */
9912 enum insn_code icode;
9914 /* The floating-point comparison code to use with ICODE, if any. */
9915 enum mips_fp_condition cond;
9917 /* The name of the builtin function. */
9920 /* Specifies how the function should be expanded. */
9921 enum mips_builtin_type builtin_type;
9923 /* The function's prototype. */
9924 enum mips_function_type function_type;
9926 /* The target flags required for this function. */
9930 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9931 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9932 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9933 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9934 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9936 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9938 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9939 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9940 "__builtin_mips_" #INSN "_" #COND "_s", \
9941 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9942 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9943 "__builtin_mips_" #INSN "_" #COND "_d", \
9944 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9946 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9947 The lower and upper forms require TARGET_FLAGS while the any and all
9948 forms require MASK_MIPS3D. */
9949 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9950 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9951 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9952 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9953 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9954 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9955 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9956 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9957 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9958 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9959 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9960 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9961 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9963 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9964 require MASK_MIPS3D. */
9965 #define CMP_4S_BUILTINS(INSN, COND) \
9966 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9967 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9968 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9970 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9971 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9972 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9975 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9976 instruction requires TARGET_FLAGS. */
9977 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9978 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9979 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9980 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9982 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9983 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9984 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9987 /* Define all the builtins related to c.cond.fmt condition COND. */
9988 #define CMP_BUILTINS(COND) \
9989 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9990 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9991 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9992 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
9993 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9994 CMP_4S_BUILTINS (c, COND), \
9995 CMP_4S_BUILTINS (cabs, COND)
9997 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
9998 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
10000 static const struct builtin_description mips_bdesc[] =
10002 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10003 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10004 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10005 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10006 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10007 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10008 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10009 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10011 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10012 MASK_PAIRED_SINGLE_FLOAT),
10013 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10014 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10015 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10016 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10018 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10019 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10020 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10021 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10022 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10023 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10025 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10026 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10027 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10028 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10029 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10030 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10032 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10035 /* Builtin functions for the SB-1 processor. */
10037 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10039 static const struct builtin_description sb1_bdesc[] =
10041 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10044 /* Builtin functions for DSP ASE. */
10046 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10047 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10048 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10049 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10051 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10052 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10053 builtin_description fields. */
10054 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10055 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10056 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10058 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10059 branch instruction. TARGET_FLAGS is a builtin_description field. */
10060 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10061 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10062 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10064 static const struct builtin_description dsp_bdesc[] =
10066 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10067 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10068 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10069 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10070 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10071 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10072 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10073 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10074 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10075 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10076 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10077 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10078 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10079 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10080 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10081 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10082 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10083 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10084 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10085 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10086 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10087 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10088 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10089 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10090 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10091 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10092 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10093 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10094 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10095 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10096 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10097 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10098 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10099 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10100 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10101 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10102 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10103 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10104 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10105 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10106 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10107 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10108 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10109 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10110 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10111 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10112 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10113 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10114 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10115 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10116 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10117 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10118 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10119 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10120 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10121 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10122 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10123 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10124 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10125 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10126 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10127 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10128 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10129 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10130 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10131 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10132 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10133 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10134 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10135 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10136 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10137 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10138 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10139 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10140 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10141 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10142 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10143 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10144 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10145 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10146 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10147 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10148 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10149 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10150 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10151 BPOSGE_BUILTIN (32, MASK_DSP)
10154 /* This helps provide a mapping from builtin function codes to bdesc
10159 /* The builtin function table that this entry describes. */
10160 const struct builtin_description *bdesc;
10162 /* The number of entries in the builtin function table. */
10165 /* The target processor that supports these builtin functions.
10166 PROCESSOR_MAX means we enable them for all processors. */
10167 enum processor_type proc;
10170 static const struct bdesc_map bdesc_arrays[] =
10172 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10173 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10174 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10177 /* Take the head of argument list *ARGLIST and convert it into a form
10178 suitable for input operand OP of instruction ICODE. Return the value
10179 and point *ARGLIST at the next element of the list. */
10182 mips_prepare_builtin_arg (enum insn_code icode,
10183 unsigned int op, tree *arglist)
10186 enum machine_mode mode;
10188 value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0);
10189 mode = insn_data[icode].operand[op].mode;
10190 if (!insn_data[icode].operand[op].predicate (value, mode))
10192 value = copy_to_mode_reg (mode, value);
10193 /* Check the predicate again. */
10194 if (!insn_data[icode].operand[op].predicate (value, mode))
10196 error ("invalid argument to builtin function");
10201 *arglist = TREE_CHAIN (*arglist);
10205 /* Return an rtx suitable for output operand OP of instruction ICODE.
10206 If TARGET is non-null, try to use it where possible. */
10209 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10211 enum machine_mode mode;
10213 mode = insn_data[icode].operand[op].mode;
10214 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10215 target = gen_reg_rtx (mode);
10220 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10223 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10224 enum machine_mode mode ATTRIBUTE_UNUSED,
10225 int ignore ATTRIBUTE_UNUSED)
10227 enum insn_code icode;
10228 enum mips_builtin_type type;
10229 tree fndecl, arglist;
10230 unsigned int fcode;
10231 const struct builtin_description *bdesc;
10232 const struct bdesc_map *m;
10234 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10235 arglist = TREE_OPERAND (exp, 1);
10236 fcode = DECL_FUNCTION_CODE (fndecl);
10239 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10241 if (fcode < m->size)
10244 icode = bdesc[fcode].icode;
10245 type = bdesc[fcode].builtin_type;
10255 case MIPS_BUILTIN_DIRECT:
10256 return mips_expand_builtin_direct (icode, target, arglist, true);
10258 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10259 return mips_expand_builtin_direct (icode, target, arglist, false);
10261 case MIPS_BUILTIN_MOVT:
10262 case MIPS_BUILTIN_MOVF:
10263 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10266 case MIPS_BUILTIN_CMP_ANY:
10267 case MIPS_BUILTIN_CMP_ALL:
10268 case MIPS_BUILTIN_CMP_UPPER:
10269 case MIPS_BUILTIN_CMP_LOWER:
10270 case MIPS_BUILTIN_CMP_SINGLE:
10271 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10274 case MIPS_BUILTIN_BPOSGE32:
10275 return mips_expand_builtin_bposge (type, target);
10282 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10285 mips_init_builtins (void)
10287 const struct builtin_description *d;
10288 const struct bdesc_map *m;
10289 tree types[(int) MIPS_MAX_FTYPE_MAX];
10290 tree V2SF_type_node;
10291 tree V2HI_type_node;
10292 tree V4QI_type_node;
10293 unsigned int offset;
10295 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10296 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10299 if (TARGET_PAIRED_SINGLE_FLOAT)
10301 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10303 types[MIPS_V2SF_FTYPE_V2SF]
10304 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10306 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10307 = build_function_type_list (V2SF_type_node,
10308 V2SF_type_node, V2SF_type_node, NULL_TREE);
10310 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10311 = build_function_type_list (V2SF_type_node,
10312 V2SF_type_node, V2SF_type_node,
10313 integer_type_node, NULL_TREE);
10315 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10316 = build_function_type_list (V2SF_type_node,
10317 V2SF_type_node, V2SF_type_node,
10318 V2SF_type_node, V2SF_type_node, NULL_TREE);
10320 types[MIPS_V2SF_FTYPE_SF_SF]
10321 = build_function_type_list (V2SF_type_node,
10322 float_type_node, float_type_node, NULL_TREE);
10324 types[MIPS_INT_FTYPE_V2SF_V2SF]
10325 = build_function_type_list (integer_type_node,
10326 V2SF_type_node, V2SF_type_node, NULL_TREE);
10328 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10329 = build_function_type_list (integer_type_node,
10330 V2SF_type_node, V2SF_type_node,
10331 V2SF_type_node, V2SF_type_node, NULL_TREE);
10333 types[MIPS_INT_FTYPE_SF_SF]
10334 = build_function_type_list (integer_type_node,
10335 float_type_node, float_type_node, NULL_TREE);
10337 types[MIPS_INT_FTYPE_DF_DF]
10338 = build_function_type_list (integer_type_node,
10339 double_type_node, double_type_node, NULL_TREE);
10341 types[MIPS_SF_FTYPE_V2SF]
10342 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10344 types[MIPS_SF_FTYPE_SF]
10345 = build_function_type_list (float_type_node,
10346 float_type_node, NULL_TREE);
10348 types[MIPS_SF_FTYPE_SF_SF]
10349 = build_function_type_list (float_type_node,
10350 float_type_node, float_type_node, NULL_TREE);
10352 types[MIPS_DF_FTYPE_DF]
10353 = build_function_type_list (double_type_node,
10354 double_type_node, NULL_TREE);
10356 types[MIPS_DF_FTYPE_DF_DF]
10357 = build_function_type_list (double_type_node,
10358 double_type_node, double_type_node, NULL_TREE);
10363 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10364 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10366 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10367 = build_function_type_list (V2HI_type_node,
10368 V2HI_type_node, V2HI_type_node,
10371 types[MIPS_SI_FTYPE_SI_SI]
10372 = build_function_type_list (intSI_type_node,
10373 intSI_type_node, intSI_type_node,
10376 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10377 = build_function_type_list (V4QI_type_node,
10378 V4QI_type_node, V4QI_type_node,
10381 types[MIPS_SI_FTYPE_V4QI]
10382 = build_function_type_list (intSI_type_node,
10386 types[MIPS_V2HI_FTYPE_V2HI]
10387 = build_function_type_list (V2HI_type_node,
10391 types[MIPS_SI_FTYPE_SI]
10392 = build_function_type_list (intSI_type_node,
10396 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10397 = build_function_type_list (V4QI_type_node,
10398 V2HI_type_node, V2HI_type_node,
10401 types[MIPS_V2HI_FTYPE_SI_SI]
10402 = build_function_type_list (V2HI_type_node,
10403 intSI_type_node, intSI_type_node,
10406 types[MIPS_SI_FTYPE_V2HI]
10407 = build_function_type_list (intSI_type_node,
10411 types[MIPS_V2HI_FTYPE_V4QI]
10412 = build_function_type_list (V2HI_type_node,
10416 types[MIPS_V4QI_FTYPE_V4QI_SI]
10417 = build_function_type_list (V4QI_type_node,
10418 V4QI_type_node, intSI_type_node,
10421 types[MIPS_V2HI_FTYPE_V2HI_SI]
10422 = build_function_type_list (V2HI_type_node,
10423 V2HI_type_node, intSI_type_node,
10426 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10427 = build_function_type_list (V2HI_type_node,
10428 V4QI_type_node, V2HI_type_node,
10431 types[MIPS_SI_FTYPE_V2HI_V2HI]
10432 = build_function_type_list (intSI_type_node,
10433 V2HI_type_node, V2HI_type_node,
10436 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10437 = build_function_type_list (intDI_type_node,
10438 intDI_type_node, V4QI_type_node, V4QI_type_node,
10441 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10442 = build_function_type_list (intDI_type_node,
10443 intDI_type_node, V2HI_type_node, V2HI_type_node,
10446 types[MIPS_DI_FTYPE_DI_SI_SI]
10447 = build_function_type_list (intDI_type_node,
10448 intDI_type_node, intSI_type_node, intSI_type_node,
10451 types[MIPS_V4QI_FTYPE_SI]
10452 = build_function_type_list (V4QI_type_node,
10456 types[MIPS_V2HI_FTYPE_SI]
10457 = build_function_type_list (V2HI_type_node,
10461 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10462 = build_function_type_list (void_type_node,
10463 V4QI_type_node, V4QI_type_node,
10466 types[MIPS_SI_FTYPE_V4QI_V4QI]
10467 = build_function_type_list (intSI_type_node,
10468 V4QI_type_node, V4QI_type_node,
10471 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10472 = build_function_type_list (void_type_node,
10473 V2HI_type_node, V2HI_type_node,
10476 types[MIPS_SI_FTYPE_DI_SI]
10477 = build_function_type_list (intSI_type_node,
10478 intDI_type_node, intSI_type_node,
10481 types[MIPS_DI_FTYPE_DI_SI]
10482 = build_function_type_list (intDI_type_node,
10483 intDI_type_node, intSI_type_node,
10486 types[MIPS_VOID_FTYPE_SI_SI]
10487 = build_function_type_list (void_type_node,
10488 intSI_type_node, intSI_type_node,
10491 types[MIPS_SI_FTYPE_PTR_SI]
10492 = build_function_type_list (intSI_type_node,
10493 ptr_type_node, intSI_type_node,
10496 types[MIPS_SI_FTYPE_VOID]
10497 = build_function_type (intSI_type_node, void_list_node);
10500 /* Iterate through all of the bdesc arrays, initializing all of the
10501 builtin functions. */
10504 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10506 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10507 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10508 if ((d->target_flags & target_flags) == d->target_flags)
10509 lang_hooks.builtin_function (d->name, types[d->function_type],
10510 d - m->bdesc + offset,
10511 BUILT_IN_MD, NULL, NULL);
10516 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10517 .md pattern and ARGLIST is the list of function arguments. TARGET,
10518 if nonnull, suggests a good place to put the result.
10519 HAS_TARGET indicates the function must return something. */
10522 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10525 rtx ops[MAX_RECOG_OPERANDS];
10530 /* We save target to ops[0]. */
10531 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10535 /* We need to test if arglist is not zero. Some instructions have extra
10536 clobber registers. */
10537 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10538 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10543 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10547 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10551 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10555 gcc_unreachable ();
10560 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10561 function (TYPE says which). ARGLIST is the list of arguments to the
10562 function, ICODE is the instruction that should be used to compare
10563 the first two arguments, and COND is the condition it should test.
10564 TARGET, if nonnull, suggests a good place to put the result. */
10567 mips_expand_builtin_movtf (enum mips_builtin_type type,
10568 enum insn_code icode, enum mips_fp_condition cond,
10569 rtx target, tree arglist)
10571 rtx cmp_result, op0, op1;
10573 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10574 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10575 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10576 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10578 icode = CODE_FOR_mips_cond_move_tf_ps;
10579 target = mips_prepare_builtin_target (icode, 0, target);
10580 if (type == MIPS_BUILTIN_MOVT)
10582 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10583 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10587 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10588 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10590 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10594 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10595 of the comparison instruction and COND is the condition it should test.
10596 ARGLIST is the list of function arguments and TARGET, if nonnull,
10597 suggests a good place to put the boolean result. */
10600 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10601 enum insn_code icode, enum mips_fp_condition cond,
10602 rtx target, tree arglist)
10604 rtx label1, label2, if_then_else;
10605 rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
10606 rtx target_if_equal, target_if_unequal;
10609 if (target == 0 || GET_MODE (target) != SImode)
10610 target = gen_reg_rtx (SImode);
10612 /* Prepare the operands to the comparison. */
10613 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10614 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10615 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10617 switch (insn_data[icode].n_operands)
10620 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
10624 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10625 ops[3], ops[4], GEN_INT (cond));
10629 gcc_unreachable ();
10632 /* If the comparison sets more than one register, we define the result
10633 to be 0 if all registers are false and -1 if all registers are true.
10634 The value of the complete result is indeterminate otherwise. It is
10635 possible to test individual registers using SUBREGs.
10637 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
10638 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
10639 and TARGET_IF_UNEQUAL otherwise. */
10640 if (builtin_type == MIPS_BUILTIN_CMP_ALL)
10643 target_if_equal = const1_rtx;
10644 target_if_unequal = const0_rtx;
10649 target_if_equal = const0_rtx;
10650 target_if_unequal = const1_rtx;
10651 if (builtin_type == MIPS_BUILTIN_CMP_UPPER)
10652 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 4);
10653 else if (builtin_type == MIPS_BUILTIN_CMP_LOWER)
10654 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 0);
10657 /* First assume that CMP_RESULT == CMP_VALUE. */
10658 emit_move_insn (target, target_if_equal);
10660 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
10662 label1 = gen_label_rtx ();
10663 label2 = gen_label_rtx ();
10665 = gen_rtx_IF_THEN_ELSE (VOIDmode,
10666 gen_rtx_fmt_ee (NE, GET_MODE (cmp_result),
10667 cmp_result, GEN_INT (cmp_value)),
10668 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
10669 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
10670 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10671 gen_rtx_LABEL_REF (VOIDmode, label2)));
10673 emit_label (label1);
10675 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
10676 emit_move_insn (target, target_if_unequal);
10677 emit_label (label2);
10682 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10683 suggests a good place to put the boolean result.
10685 The sequence we want is
10695 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10697 rtx label1, label2, if_then_else;
10701 if (target == 0 || GET_MODE (target) != SImode)
10702 target = gen_reg_rtx (SImode);
10704 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10706 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10711 /* Move 0 to target */
10712 emit_move_insn (target, const0_rtx);
10714 /* Generate two labels */
10715 label1 = gen_label_rtx ();
10716 label2 = gen_label_rtx ();
10718 /* Generate if_then_else */
10720 = gen_rtx_IF_THEN_ELSE (VOIDmode,
10721 gen_rtx_fmt_ee (GE, CCDSPmode,
10722 cmp_result, GEN_INT (cmp_value)),
10723 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
10725 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
10726 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10727 gen_rtx_LABEL_REF (VOIDmode, label2)));
10729 emit_label (label1);
10730 emit_move_insn (target, const1_rtx);
10731 emit_label (label2);
10736 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10737 FIRST is true if this is the first time handling this decl. */
10740 mips_encode_section_info (tree decl, rtx rtl, int first)
10742 default_encode_section_info (decl, rtl, first);
10744 if (TREE_CODE (decl) == FUNCTION_DECL
10745 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10747 rtx symbol = XEXP (rtl, 0);
10748 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10752 #include "gt-mips.h"