1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting {
153 R10K_CACHE_BARRIER_NONE,
154 R10K_CACHE_BARRIER_STORE,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type {
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type {
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY,
201 MIPS_BUILTIN_CMP_ALL,
202 MIPS_BUILTIN_CMP_UPPER,
203 MIPS_BUILTIN_CMP_LOWER,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition {
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY)
243 /* Information about a function's frame layout. */
244 struct GTY(()) mips_frame_info {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* Likewise doubleword accumulator X ($acX). */
265 unsigned int acc_mask;
267 /* The number of GPRs, FPRs, doubleword accumulators and COP0
271 unsigned int num_acc;
272 unsigned int num_cop0_regs;
274 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
275 save slots from the top of the frame, or zero if no such slots are
277 HOST_WIDE_INT gp_save_offset;
278 HOST_WIDE_INT fp_save_offset;
279 HOST_WIDE_INT acc_save_offset;
280 HOST_WIDE_INT cop0_save_offset;
282 /* Likewise, but giving offsets from the bottom of the frame. */
283 HOST_WIDE_INT gp_sp_offset;
284 HOST_WIDE_INT fp_sp_offset;
285 HOST_WIDE_INT acc_sp_offset;
286 HOST_WIDE_INT cop0_sp_offset;
288 /* The offset of arg_pointer_rtx from the bottom of the frame. */
289 HOST_WIDE_INT arg_pointer_offset;
291 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
292 HOST_WIDE_INT hard_frame_pointer_offset;
295 struct GTY(()) machine_function {
296 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
297 rtx mips16_gp_pseudo_rtx;
299 /* The number of extra stack bytes taken up by register varargs.
300 This area is allocated by the callee at the very top of the frame. */
303 /* The current frame information, calculated by mips_compute_frame_info. */
304 struct mips_frame_info frame;
306 /* The register to use as the function's global pointer, or INVALID_REGNUM
307 if the function doesn't need one. */
308 unsigned int global_pointer;
310 /* True if mips_adjust_insn_length should ignore an instruction's
312 bool ignore_hazard_length_p;
314 /* True if the whole function is suitable for .set noreorder and
316 bool all_noreorder_p;
318 /* True if the function is known to have an instruction that needs $gp. */
321 /* True if we have emitted an instruction to initialize
322 mips16_gp_pseudo_rtx. */
323 bool initialized_mips16_gp_pseudo_p;
325 /* True if this is an interrupt handler. */
326 bool interrupt_handler_p;
328 /* True if this is an interrupt handler that uses shadow registers. */
329 bool use_shadow_register_set_p;
331 /* True if this is an interrupt handler that should keep interrupts
333 bool keep_interrupts_masked_p;
335 /* True if this is an interrupt handler that should use DERET
337 bool use_debug_exception_return_p;
340 /* Information about a single argument. */
341 struct mips_arg_info {
342 /* True if the argument is passed in a floating-point register, or
343 would have been if we hadn't run out of registers. */
346 /* The number of words passed in registers, rounded up. */
347 unsigned int reg_words;
349 /* For EABI, the offset of the first register from GP_ARG_FIRST or
350 FP_ARG_FIRST. For other ABIs, the offset of the first register from
351 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
352 comment for details).
354 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
356 unsigned int reg_offset;
358 /* The number of words that must be passed on the stack, rounded up. */
359 unsigned int stack_words;
361 /* The offset from the start of the stack overflow area of the argument's
362 first stack word. Only meaningful when STACK_WORDS is nonzero. */
363 unsigned int stack_offset;
366 /* Information about an address described by mips_address_type.
372 REG is the base register and OFFSET is the constant offset.
375 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
376 is the type of symbol it references.
379 SYMBOL_TYPE is the type of symbol that the address references. */
380 struct mips_address_info {
381 enum mips_address_type type;
384 enum mips_symbol_type symbol_type;
387 /* One stage in a constant building sequence. These sequences have
391 A = A CODE[1] VALUE[1]
392 A = A CODE[2] VALUE[2]
395 where A is an accumulator, each CODE[i] is a binary rtl operation
396 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
397 struct mips_integer_op {
399 unsigned HOST_WIDE_INT value;
402 /* The largest number of operations needed to load an integer constant.
403 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
404 When the lowest bit is clear, we can try, but reject a sequence with
405 an extra SLL at the end. */
406 #define MIPS_MAX_INTEGER_OPS 7
408 /* Information about a MIPS16e SAVE or RESTORE instruction. */
409 struct mips16e_save_restore_info {
410 /* The number of argument registers saved by a SAVE instruction.
411 0 for RESTORE instructions. */
414 /* Bit X is set if the instruction saves or restores GPR X. */
417 /* The total number of bytes to allocate. */
421 /* Global variables for machine-dependent things. */
423 /* The -G setting, or the configuration's default small-data limit if
424 no -G option is given. */
425 static unsigned int mips_small_data_threshold;
427 /* The number of file directives written by mips_output_filename. */
428 int num_source_filenames;
430 /* The name that appeared in the last .file directive written by
431 mips_output_filename, or "" if mips_output_filename hasn't
432 written anything yet. */
433 const char *current_function_file = "";
435 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
438 /* Arrays that map GCC register numbers to debugger register numbers. */
439 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
440 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
442 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
447 /* True if we're writing out a branch-likely instruction rather than a
449 static bool mips_branch_likely;
451 /* The current instruction-set architecture. */
452 enum processor_type mips_arch;
453 const struct mips_cpu_info *mips_arch_info;
455 /* The processor that we should tune the code for. */
456 enum processor_type mips_tune;
457 const struct mips_cpu_info *mips_tune_info;
459 /* The ISA level associated with mips_arch. */
462 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
463 static const struct mips_cpu_info *mips_isa_option_info;
465 /* Which ABI to use. */
466 int mips_abi = MIPS_ABI_DEFAULT;
468 /* Which cost information to use. */
469 const struct mips_rtx_cost_data *mips_cost;
471 /* The ambient target flags, excluding MASK_MIPS16. */
472 static int mips_base_target_flags;
474 /* True if MIPS16 is the default mode. */
475 bool mips_base_mips16;
477 /* The ambient values of other global variables. */
478 static int mips_base_schedule_insns; /* flag_schedule_insns */
479 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
480 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
481 static int mips_base_align_loops; /* align_loops */
482 static int mips_base_align_jumps; /* align_jumps */
483 static int mips_base_align_functions; /* align_functions */
485 /* The -mcode-readable setting. */
486 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
488 /* The -mr10k-cache-barrier setting. */
489 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
491 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
492 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
494 /* Index C is true if character C is a valid PRINT_OPERAND punctation
496 bool mips_print_operand_punct[256];
498 static GTY (()) int mips_output_filename_first_time = 1;
500 /* mips_split_p[X] is true if symbols of type X can be split by
501 mips_split_symbol. */
502 bool mips_split_p[NUM_SYMBOL_TYPES];
504 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
505 can be split by mips_split_symbol. */
506 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
508 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
509 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
510 if they are matched by a special .md file pattern. */
511 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
513 /* Likewise for HIGHs. */
514 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
516 /* Index R is the smallest register class that contains register R. */
517 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
518 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
519 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
520 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
521 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
522 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
523 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
524 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
525 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
526 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
527 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
528 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
529 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
530 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
531 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
532 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
533 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
534 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
535 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
536 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
537 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
538 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
539 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
540 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
541 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
542 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
543 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
544 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
545 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
546 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
547 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
548 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
549 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
550 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
551 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
552 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
553 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
554 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
555 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
556 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
557 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
558 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
559 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
560 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
561 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
562 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
563 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
564 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
567 /* The value of TARGET_ATTRIBUTE_TABLE. */
568 static const struct attribute_spec mips_attribute_table[] = {
569 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
570 { "long_call", 0, 0, false, true, true, NULL },
571 { "far", 0, 0, false, true, true, NULL },
572 { "near", 0, 0, false, true, true, NULL },
573 /* We would really like to treat "mips16" and "nomips16" as type
574 attributes, but GCC doesn't provide the hooks we need to support
575 the right conversion rules. As declaration attributes, they affect
576 code generation but don't carry other semantics. */
577 { "mips16", 0, 0, true, false, false, NULL },
578 { "nomips16", 0, 0, true, false, false, NULL },
579 /* Allow functions to be specified as interrupt handlers */
580 { "interrupt", 0, 0, false, true, true, NULL },
581 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
582 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
583 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
584 { NULL, 0, 0, false, false, false, NULL }
587 /* A table describing all the processors GCC knows about. Names are
588 matched in the order listed. The first mention of an ISA level is
589 taken as the canonical name for that ISA.
591 To ease comparison, please keep this table in the same order
592 as GAS's mips_cpu_info_table. Please also make sure that
593 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
594 options correctly. */
595 static const struct mips_cpu_info mips_cpu_info_table[] = {
596 /* Entries for generic ISAs. */
597 { "mips1", PROCESSOR_R3000, 1, 0 },
598 { "mips2", PROCESSOR_R6000, 2, 0 },
599 { "mips3", PROCESSOR_R4000, 3, 0 },
600 { "mips4", PROCESSOR_R8000, 4, 0 },
601 /* Prefer not to use branch-likely instructions for generic MIPS32rX
602 and MIPS64rX code. The instructions were officially deprecated
603 in revisions 2 and earlier, but revision 3 is likely to downgrade
604 that to a recommendation to avoid the instructions in code that
605 isn't tuned to a specific processor. */
606 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
607 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
608 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
609 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
610 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
612 /* MIPS I processors. */
613 { "r3000", PROCESSOR_R3000, 1, 0 },
614 { "r2000", PROCESSOR_R3000, 1, 0 },
615 { "r3900", PROCESSOR_R3900, 1, 0 },
617 /* MIPS II processors. */
618 { "r6000", PROCESSOR_R6000, 2, 0 },
620 /* MIPS III processors. */
621 { "r4000", PROCESSOR_R4000, 3, 0 },
622 { "vr4100", PROCESSOR_R4100, 3, 0 },
623 { "vr4111", PROCESSOR_R4111, 3, 0 },
624 { "vr4120", PROCESSOR_R4120, 3, 0 },
625 { "vr4130", PROCESSOR_R4130, 3, 0 },
626 { "vr4300", PROCESSOR_R4300, 3, 0 },
627 { "r4400", PROCESSOR_R4000, 3, 0 },
628 { "r4600", PROCESSOR_R4600, 3, 0 },
629 { "orion", PROCESSOR_R4600, 3, 0 },
630 { "r4650", PROCESSOR_R4650, 3, 0 },
631 /* ST Loongson 2E/2F processors. */
632 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
633 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
635 /* MIPS IV processors. */
636 { "r8000", PROCESSOR_R8000, 4, 0 },
637 { "r10000", PROCESSOR_R10000, 4, 0 },
638 { "r12000", PROCESSOR_R10000, 4, 0 },
639 { "r14000", PROCESSOR_R10000, 4, 0 },
640 { "r16000", PROCESSOR_R10000, 4, 0 },
641 { "vr5000", PROCESSOR_R5000, 4, 0 },
642 { "vr5400", PROCESSOR_R5400, 4, 0 },
643 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
644 { "rm7000", PROCESSOR_R7000, 4, 0 },
645 { "rm9000", PROCESSOR_R9000, 4, 0 },
647 /* MIPS32 processors. */
648 { "4kc", PROCESSOR_4KC, 32, 0 },
649 { "4km", PROCESSOR_4KC, 32, 0 },
650 { "4kp", PROCESSOR_4KP, 32, 0 },
651 { "4ksc", PROCESSOR_4KC, 32, 0 },
653 /* MIPS32 Release 2 processors. */
654 { "m4k", PROCESSOR_M4K, 33, 0 },
655 { "4kec", PROCESSOR_4KC, 33, 0 },
656 { "4kem", PROCESSOR_4KC, 33, 0 },
657 { "4kep", PROCESSOR_4KP, 33, 0 },
658 { "4ksd", PROCESSOR_4KC, 33, 0 },
660 { "24kc", PROCESSOR_24KC, 33, 0 },
661 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
662 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
663 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
664 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
665 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
667 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
668 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
669 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
670 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
671 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
672 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
674 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
675 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
676 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
677 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
678 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
679 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
681 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
682 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
683 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
684 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
685 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
686 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
687 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
689 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
690 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
691 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
692 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
694 /* MIPS64 processors. */
695 { "5kc", PROCESSOR_5KC, 64, 0 },
696 { "5kf", PROCESSOR_5KF, 64, 0 },
697 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
698 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
699 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
700 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
701 { "xlr", PROCESSOR_XLR, 64, 0 },
703 /* MIPS64 Release 2 processors. */
704 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
707 /* Default costs. If these are used for a processor we should look
708 up the actual costs. */
709 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
710 COSTS_N_INSNS (7), /* fp_mult_sf */ \
711 COSTS_N_INSNS (8), /* fp_mult_df */ \
712 COSTS_N_INSNS (23), /* fp_div_sf */ \
713 COSTS_N_INSNS (36), /* fp_div_df */ \
714 COSTS_N_INSNS (10), /* int_mult_si */ \
715 COSTS_N_INSNS (10), /* int_mult_di */ \
716 COSTS_N_INSNS (69), /* int_div_si */ \
717 COSTS_N_INSNS (69), /* int_div_di */ \
718 2, /* branch_cost */ \
719 4 /* memory_latency */
721 /* Floating-point costs for processors without an FPU. Just assume that
722 all floating-point libcalls are very expensive. */
723 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
724 COSTS_N_INSNS (256), /* fp_mult_sf */ \
725 COSTS_N_INSNS (256), /* fp_mult_df */ \
726 COSTS_N_INSNS (256), /* fp_div_sf */ \
727 COSTS_N_INSNS (256) /* fp_div_df */
729 /* Costs to use when optimizing for size. */
730 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
731 COSTS_N_INSNS (1), /* fp_add */
732 COSTS_N_INSNS (1), /* fp_mult_sf */
733 COSTS_N_INSNS (1), /* fp_mult_df */
734 COSTS_N_INSNS (1), /* fp_div_sf */
735 COSTS_N_INSNS (1), /* fp_div_df */
736 COSTS_N_INSNS (1), /* int_mult_si */
737 COSTS_N_INSNS (1), /* int_mult_di */
738 COSTS_N_INSNS (1), /* int_div_si */
739 COSTS_N_INSNS (1), /* int_div_di */
741 4 /* memory_latency */
744 /* Costs to use when optimizing for speed, indexed by processor. */
745 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
747 COSTS_N_INSNS (2), /* fp_add */
748 COSTS_N_INSNS (4), /* fp_mult_sf */
749 COSTS_N_INSNS (5), /* fp_mult_df */
750 COSTS_N_INSNS (12), /* fp_div_sf */
751 COSTS_N_INSNS (19), /* fp_div_df */
752 COSTS_N_INSNS (12), /* int_mult_si */
753 COSTS_N_INSNS (12), /* int_mult_di */
754 COSTS_N_INSNS (35), /* int_div_si */
755 COSTS_N_INSNS (35), /* int_div_di */
757 4 /* memory_latency */
761 COSTS_N_INSNS (6), /* int_mult_si */
762 COSTS_N_INSNS (6), /* int_mult_di */
763 COSTS_N_INSNS (36), /* int_div_si */
764 COSTS_N_INSNS (36), /* int_div_di */
766 4 /* memory_latency */
770 COSTS_N_INSNS (36), /* int_mult_si */
771 COSTS_N_INSNS (36), /* int_mult_di */
772 COSTS_N_INSNS (37), /* int_div_si */
773 COSTS_N_INSNS (37), /* int_div_di */
775 4 /* memory_latency */
779 COSTS_N_INSNS (4), /* int_mult_si */
780 COSTS_N_INSNS (11), /* int_mult_di */
781 COSTS_N_INSNS (36), /* int_div_si */
782 COSTS_N_INSNS (68), /* int_div_di */
784 4 /* memory_latency */
787 COSTS_N_INSNS (4), /* fp_add */
788 COSTS_N_INSNS (4), /* fp_mult_sf */
789 COSTS_N_INSNS (5), /* fp_mult_df */
790 COSTS_N_INSNS (17), /* fp_div_sf */
791 COSTS_N_INSNS (32), /* fp_div_df */
792 COSTS_N_INSNS (4), /* int_mult_si */
793 COSTS_N_INSNS (11), /* int_mult_di */
794 COSTS_N_INSNS (36), /* int_div_si */
795 COSTS_N_INSNS (68), /* int_div_di */
797 4 /* memory_latency */
800 COSTS_N_INSNS (4), /* fp_add */
801 COSTS_N_INSNS (4), /* fp_mult_sf */
802 COSTS_N_INSNS (5), /* fp_mult_df */
803 COSTS_N_INSNS (17), /* fp_div_sf */
804 COSTS_N_INSNS (32), /* fp_div_df */
805 COSTS_N_INSNS (4), /* int_mult_si */
806 COSTS_N_INSNS (7), /* int_mult_di */
807 COSTS_N_INSNS (42), /* int_div_si */
808 COSTS_N_INSNS (72), /* int_div_di */
810 4 /* memory_latency */
814 COSTS_N_INSNS (5), /* int_mult_si */
815 COSTS_N_INSNS (5), /* int_mult_di */
816 COSTS_N_INSNS (41), /* int_div_si */
817 COSTS_N_INSNS (41), /* int_div_di */
819 4 /* memory_latency */
822 COSTS_N_INSNS (8), /* fp_add */
823 COSTS_N_INSNS (8), /* fp_mult_sf */
824 COSTS_N_INSNS (10), /* fp_mult_df */
825 COSTS_N_INSNS (34), /* fp_div_sf */
826 COSTS_N_INSNS (64), /* fp_div_df */
827 COSTS_N_INSNS (5), /* int_mult_si */
828 COSTS_N_INSNS (5), /* int_mult_di */
829 COSTS_N_INSNS (41), /* int_div_si */
830 COSTS_N_INSNS (41), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (5), /* int_mult_si */
841 COSTS_N_INSNS (5), /* int_mult_di */
842 COSTS_N_INSNS (41), /* int_div_si */
843 COSTS_N_INSNS (41), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (5), /* int_mult_si */
850 COSTS_N_INSNS (5), /* int_mult_di */
851 COSTS_N_INSNS (41), /* int_div_si */
852 COSTS_N_INSNS (41), /* int_div_di */
854 4 /* memory_latency */
857 COSTS_N_INSNS (8), /* fp_add */
858 COSTS_N_INSNS (8), /* fp_mult_sf */
859 COSTS_N_INSNS (10), /* fp_mult_df */
860 COSTS_N_INSNS (34), /* fp_div_sf */
861 COSTS_N_INSNS (64), /* fp_div_df */
862 COSTS_N_INSNS (5), /* int_mult_si */
863 COSTS_N_INSNS (5), /* int_mult_di */
864 COSTS_N_INSNS (41), /* int_div_si */
865 COSTS_N_INSNS (41), /* int_div_di */
867 4 /* memory_latency */
870 COSTS_N_INSNS (4), /* fp_add */
871 COSTS_N_INSNS (4), /* fp_mult_sf */
872 COSTS_N_INSNS (5), /* fp_mult_df */
873 COSTS_N_INSNS (17), /* fp_div_sf */
874 COSTS_N_INSNS (32), /* fp_div_df */
875 COSTS_N_INSNS (5), /* int_mult_si */
876 COSTS_N_INSNS (5), /* int_mult_di */
877 COSTS_N_INSNS (41), /* int_div_si */
878 COSTS_N_INSNS (41), /* int_div_di */
880 4 /* memory_latency */
883 COSTS_N_INSNS (6), /* fp_add */
884 COSTS_N_INSNS (6), /* fp_mult_sf */
885 COSTS_N_INSNS (7), /* fp_mult_df */
886 COSTS_N_INSNS (25), /* fp_div_sf */
887 COSTS_N_INSNS (48), /* fp_div_df */
888 COSTS_N_INSNS (5), /* int_mult_si */
889 COSTS_N_INSNS (5), /* int_mult_di */
890 COSTS_N_INSNS (41), /* int_div_si */
891 COSTS_N_INSNS (41), /* int_div_di */
893 4 /* memory_latency */
907 COSTS_N_INSNS (5), /* int_mult_si */
908 COSTS_N_INSNS (5), /* int_mult_di */
909 COSTS_N_INSNS (72), /* int_div_si */
910 COSTS_N_INSNS (72), /* int_div_di */
912 4 /* memory_latency */
915 COSTS_N_INSNS (2), /* fp_add */
916 COSTS_N_INSNS (4), /* fp_mult_sf */
917 COSTS_N_INSNS (5), /* fp_mult_df */
918 COSTS_N_INSNS (12), /* fp_div_sf */
919 COSTS_N_INSNS (19), /* fp_div_df */
920 COSTS_N_INSNS (2), /* int_mult_si */
921 COSTS_N_INSNS (2), /* int_mult_di */
922 COSTS_N_INSNS (35), /* int_div_si */
923 COSTS_N_INSNS (35), /* int_div_di */
925 4 /* memory_latency */
928 COSTS_N_INSNS (3), /* fp_add */
929 COSTS_N_INSNS (5), /* fp_mult_sf */
930 COSTS_N_INSNS (6), /* fp_mult_df */
931 COSTS_N_INSNS (15), /* fp_div_sf */
932 COSTS_N_INSNS (16), /* fp_div_df */
933 COSTS_N_INSNS (17), /* int_mult_si */
934 COSTS_N_INSNS (17), /* int_mult_di */
935 COSTS_N_INSNS (38), /* int_div_si */
936 COSTS_N_INSNS (38), /* int_div_di */
938 6 /* memory_latency */
941 COSTS_N_INSNS (6), /* fp_add */
942 COSTS_N_INSNS (7), /* fp_mult_sf */
943 COSTS_N_INSNS (8), /* fp_mult_df */
944 COSTS_N_INSNS (23), /* fp_div_sf */
945 COSTS_N_INSNS (36), /* fp_div_df */
946 COSTS_N_INSNS (10), /* int_mult_si */
947 COSTS_N_INSNS (10), /* int_mult_di */
948 COSTS_N_INSNS (69), /* int_div_si */
949 COSTS_N_INSNS (69), /* int_div_di */
951 6 /* memory_latency */
963 /* The only costs that appear to be updated here are
964 integer multiplication. */
966 COSTS_N_INSNS (4), /* int_mult_si */
967 COSTS_N_INSNS (6), /* int_mult_di */
968 COSTS_N_INSNS (69), /* int_div_si */
969 COSTS_N_INSNS (69), /* int_div_di */
971 4 /* memory_latency */
983 COSTS_N_INSNS (6), /* fp_add */
984 COSTS_N_INSNS (4), /* fp_mult_sf */
985 COSTS_N_INSNS (5), /* fp_mult_df */
986 COSTS_N_INSNS (23), /* fp_div_sf */
987 COSTS_N_INSNS (36), /* fp_div_df */
988 COSTS_N_INSNS (5), /* int_mult_si */
989 COSTS_N_INSNS (5), /* int_mult_di */
990 COSTS_N_INSNS (36), /* int_div_si */
991 COSTS_N_INSNS (36), /* int_div_di */
993 4 /* memory_latency */
996 COSTS_N_INSNS (6), /* fp_add */
997 COSTS_N_INSNS (5), /* fp_mult_sf */
998 COSTS_N_INSNS (6), /* fp_mult_df */
999 COSTS_N_INSNS (30), /* fp_div_sf */
1000 COSTS_N_INSNS (59), /* fp_div_df */
1001 COSTS_N_INSNS (3), /* int_mult_si */
1002 COSTS_N_INSNS (4), /* int_mult_di */
1003 COSTS_N_INSNS (42), /* int_div_si */
1004 COSTS_N_INSNS (74), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 COSTS_N_INSNS (6), /* fp_add */
1010 COSTS_N_INSNS (5), /* fp_mult_sf */
1011 COSTS_N_INSNS (6), /* fp_mult_df */
1012 COSTS_N_INSNS (30), /* fp_div_sf */
1013 COSTS_N_INSNS (59), /* fp_div_df */
1014 COSTS_N_INSNS (5), /* int_mult_si */
1015 COSTS_N_INSNS (9), /* int_mult_di */
1016 COSTS_N_INSNS (42), /* int_div_si */
1017 COSTS_N_INSNS (74), /* int_div_di */
1018 1, /* branch_cost */
1019 4 /* memory_latency */
1022 /* The only costs that are changed here are
1023 integer multiplication. */
1024 COSTS_N_INSNS (6), /* fp_add */
1025 COSTS_N_INSNS (7), /* fp_mult_sf */
1026 COSTS_N_INSNS (8), /* fp_mult_df */
1027 COSTS_N_INSNS (23), /* fp_div_sf */
1028 COSTS_N_INSNS (36), /* fp_div_df */
1029 COSTS_N_INSNS (5), /* int_mult_si */
1030 COSTS_N_INSNS (9), /* int_mult_di */
1031 COSTS_N_INSNS (69), /* int_div_si */
1032 COSTS_N_INSNS (69), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1040 /* The only costs that are changed here are
1041 integer multiplication. */
1042 COSTS_N_INSNS (6), /* fp_add */
1043 COSTS_N_INSNS (7), /* fp_mult_sf */
1044 COSTS_N_INSNS (8), /* fp_mult_df */
1045 COSTS_N_INSNS (23), /* fp_div_sf */
1046 COSTS_N_INSNS (36), /* fp_div_df */
1047 COSTS_N_INSNS (3), /* int_mult_si */
1048 COSTS_N_INSNS (8), /* int_mult_di */
1049 COSTS_N_INSNS (69), /* int_div_si */
1050 COSTS_N_INSNS (69), /* int_div_di */
1051 1, /* branch_cost */
1052 4 /* memory_latency */
1055 COSTS_N_INSNS (2), /* fp_add */
1056 COSTS_N_INSNS (2), /* fp_mult_sf */
1057 COSTS_N_INSNS (2), /* fp_mult_df */
1058 COSTS_N_INSNS (12), /* fp_div_sf */
1059 COSTS_N_INSNS (19), /* fp_div_df */
1060 COSTS_N_INSNS (5), /* int_mult_si */
1061 COSTS_N_INSNS (9), /* int_mult_di */
1062 COSTS_N_INSNS (34), /* int_div_si */
1063 COSTS_N_INSNS (66), /* int_div_di */
1064 1, /* branch_cost */
1065 4 /* memory_latency */
1068 /* These costs are the same as the SB-1A below. */
1069 COSTS_N_INSNS (4), /* fp_add */
1070 COSTS_N_INSNS (4), /* fp_mult_sf */
1071 COSTS_N_INSNS (4), /* fp_mult_df */
1072 COSTS_N_INSNS (24), /* fp_div_sf */
1073 COSTS_N_INSNS (32), /* fp_div_df */
1074 COSTS_N_INSNS (3), /* int_mult_si */
1075 COSTS_N_INSNS (4), /* int_mult_di */
1076 COSTS_N_INSNS (36), /* int_div_si */
1077 COSTS_N_INSNS (68), /* int_div_di */
1078 1, /* branch_cost */
1079 4 /* memory_latency */
1082 /* These costs are the same as the SB-1 above. */
1083 COSTS_N_INSNS (4), /* fp_add */
1084 COSTS_N_INSNS (4), /* fp_mult_sf */
1085 COSTS_N_INSNS (4), /* fp_mult_df */
1086 COSTS_N_INSNS (24), /* fp_div_sf */
1087 COSTS_N_INSNS (32), /* fp_div_df */
1088 COSTS_N_INSNS (3), /* int_mult_si */
1089 COSTS_N_INSNS (4), /* int_mult_di */
1090 COSTS_N_INSNS (36), /* int_div_si */
1091 COSTS_N_INSNS (68), /* int_div_di */
1092 1, /* branch_cost */
1093 4 /* memory_latency */
1100 COSTS_N_INSNS (8), /* int_mult_si */
1101 COSTS_N_INSNS (8), /* int_mult_di */
1102 COSTS_N_INSNS (72), /* int_div_si */
1103 COSTS_N_INSNS (72), /* int_div_di */
1104 1, /* branch_cost */
1105 4 /* memory_latency */
1109 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1110 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1111 struct GTY (()) mflip_mips16_entry {
1115 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1117 /* Hash table callbacks for mflip_mips16_htab. */
1120 mflip_mips16_htab_hash (const void *entry)
1122 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1126 mflip_mips16_htab_eq (const void *entry, const void *name)
1128 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1129 (const char *) name) == 0;
1132 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1133 mode, false if it should next add an attribute for the opposite mode. */
1134 static GTY(()) bool mips16_flipper;
1136 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1137 for -mflip-mips16. Return true if it should use "mips16" and false if
1138 it should use "nomips16". */
1141 mflip_mips16_use_mips16_p (tree decl)
1143 struct mflip_mips16_entry *entry;
1148 /* Use the opposite of the command-line setting for anonymous decls. */
1149 if (!DECL_NAME (decl))
1150 return !mips_base_mips16;
1152 if (!mflip_mips16_htab)
1153 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1154 mflip_mips16_htab_eq, NULL);
1156 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1157 hash = htab_hash_string (name);
1158 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1159 entry = (struct mflip_mips16_entry *) *slot;
1162 mips16_flipper = !mips16_flipper;
1163 entry = GGC_NEW (struct mflip_mips16_entry);
1165 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1168 return entry->mips16_p;
1171 /* Predicates to test for presence of "near" and "far"/"long_call"
1172 attributes on the given TYPE. */
1175 mips_near_type_p (const_tree type)
1177 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1181 mips_far_type_p (const_tree type)
1183 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1184 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1187 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1190 mips_mips16_decl_p (const_tree decl)
1192 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1196 mips_nomips16_decl_p (const_tree decl)
1198 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1201 /* Check if the interrupt attribute is set for a function. */
1204 mips_interrupt_type_p (tree type)
1206 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1209 /* Check if the attribute to use shadow register set is set for a function. */
1212 mips_use_shadow_register_set_p (tree type)
1214 return lookup_attribute ("use_shadow_register_set",
1215 TYPE_ATTRIBUTES (type)) != NULL;
1218 /* Check if the attribute to keep interrupts masked is set for a function. */
1221 mips_keep_interrupts_masked_p (tree type)
1223 return lookup_attribute ("keep_interrupts_masked",
1224 TYPE_ATTRIBUTES (type)) != NULL;
1227 /* Check if the attribute to use debug exception return is set for
1231 mips_use_debug_exception_return_p (tree type)
1233 return lookup_attribute ("use_debug_exception_return",
1234 TYPE_ATTRIBUTES (type)) != NULL;
1237 /* Return true if function DECL is a MIPS16 function. Return the ambient
1238 setting if DECL is null. */
1241 mips_use_mips16_mode_p (tree decl)
1245 /* Nested functions must use the same frame pointer as their
1246 parent and must therefore use the same ISA mode. */
1247 tree parent = decl_function_context (decl);
1250 if (mips_mips16_decl_p (decl))
1252 if (mips_nomips16_decl_p (decl))
1255 return mips_base_mips16;
1258 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1261 mips_comp_type_attributes (const_tree type1, const_tree type2)
1263 /* Disallow mixed near/far attributes. */
1264 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1266 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1271 /* Implement TARGET_INSERT_ATTRIBUTES. */
1274 mips_insert_attributes (tree decl, tree *attributes)
1277 bool mips16_p, nomips16_p;
1279 /* Check for "mips16" and "nomips16" attributes. */
1280 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1281 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1282 if (TREE_CODE (decl) != FUNCTION_DECL)
1285 error ("%qs attribute only applies to functions", "mips16");
1287 error ("%qs attribute only applies to functions", "nomips16");
1291 mips16_p |= mips_mips16_decl_p (decl);
1292 nomips16_p |= mips_nomips16_decl_p (decl);
1293 if (mips16_p || nomips16_p)
1295 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1296 if (mips16_p && nomips16_p)
1297 error ("%qE cannot have both %<mips16%> and "
1298 "%<nomips16%> attributes",
1301 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1303 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1304 "mips16" attribute, arbitrarily pick one. We must pick the same
1305 setting for duplicate declarations of a function. */
1306 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1307 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1312 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1315 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1317 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1318 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1319 error ("%qE redeclared with conflicting %qs attributes",
1320 DECL_NAME (newdecl), "mips16");
1321 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1322 error ("%qE redeclared with conflicting %qs attributes",
1323 DECL_NAME (newdecl), "nomips16");
1325 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1326 DECL_ATTRIBUTES (newdecl));
1329 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1330 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1333 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1335 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1337 *base_ptr = XEXP (x, 0);
1338 *offset_ptr = INTVAL (XEXP (x, 1));
1347 static unsigned int mips_build_integer (struct mips_integer_op *,
1348 unsigned HOST_WIDE_INT);
1350 /* A subroutine of mips_build_integer, with the same interface.
1351 Assume that the final action in the sequence should be a left shift. */
1354 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1356 unsigned int i, shift;
1358 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1359 since signed numbers are easier to load than unsigned ones. */
1361 while ((value & 1) == 0)
1362 value /= 2, shift++;
1364 i = mips_build_integer (codes, value);
1365 codes[i].code = ASHIFT;
1366 codes[i].value = shift;
1370 /* As for mips_build_shift, but assume that the final action will be
1371 an IOR or PLUS operation. */
1374 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1376 unsigned HOST_WIDE_INT high;
1379 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1380 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1382 /* The constant is too complex to load with a simple LUI/ORI pair,
1383 so we want to give the recursive call as many trailing zeros as
1384 possible. In this case, we know bit 16 is set and that the
1385 low 16 bits form a negative number. If we subtract that number
1386 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1387 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1388 codes[i].code = PLUS;
1389 codes[i].value = CONST_LOW_PART (value);
1393 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1394 bits gives a value with at least 17 trailing zeros. */
1395 i = mips_build_integer (codes, high);
1396 codes[i].code = IOR;
1397 codes[i].value = value & 0xffff;
1402 /* Fill CODES with a sequence of rtl operations to load VALUE.
1403 Return the number of operations needed. */
1406 mips_build_integer (struct mips_integer_op *codes,
1407 unsigned HOST_WIDE_INT value)
1409 if (SMALL_OPERAND (value)
1410 || SMALL_OPERAND_UNSIGNED (value)
1411 || LUI_OPERAND (value))
1413 /* The value can be loaded with a single instruction. */
1414 codes[0].code = UNKNOWN;
1415 codes[0].value = value;
1418 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1420 /* Either the constant is a simple LUI/ORI combination or its
1421 lowest bit is set. We don't want to shift in this case. */
1422 return mips_build_lower (codes, value);
1424 else if ((value & 0xffff) == 0)
1426 /* The constant will need at least three actions. The lowest
1427 16 bits are clear, so the final action will be a shift. */
1428 return mips_build_shift (codes, value);
1432 /* The final action could be a shift, add or inclusive OR.
1433 Rather than use a complex condition to select the best
1434 approach, try both mips_build_shift and mips_build_lower
1435 and pick the one that gives the shortest sequence.
1436 Note that this case is only used once per constant. */
1437 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1438 unsigned int cost, alt_cost;
1440 cost = mips_build_shift (codes, value);
1441 alt_cost = mips_build_lower (alt_codes, value);
1442 if (alt_cost < cost)
1444 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1451 /* Return true if symbols of type TYPE require a GOT access. */
1454 mips_got_symbol_type_p (enum mips_symbol_type type)
1458 case SYMBOL_GOT_PAGE_OFST:
1459 case SYMBOL_GOT_DISP:
1467 /* Return true if X is a thread-local symbol. */
1470 mips_tls_symbol_p (rtx x)
1472 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1475 /* Return true if SYMBOL_REF X is associated with a global symbol
1476 (in the STB_GLOBAL sense). */
1479 mips_global_symbol_p (const_rtx x)
1481 const_tree decl = SYMBOL_REF_DECL (x);
1484 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1486 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1487 or weak symbols. Relocations in the object file will be against
1488 the target symbol, so it's that symbol's binding that matters here. */
1489 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1492 /* Return true if function X is a libgcc MIPS16 stub function. */
1495 mips16_stub_function_p (const_rtx x)
1497 return (GET_CODE (x) == SYMBOL_REF
1498 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1501 /* Return true if function X is a locally-defined and locally-binding
1505 mips16_local_function_p (const_rtx x)
1507 return (GET_CODE (x) == SYMBOL_REF
1508 && SYMBOL_REF_LOCAL_P (x)
1509 && !SYMBOL_REF_EXTERNAL_P (x)
1510 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1513 /* Return true if SYMBOL_REF X binds locally. */
1516 mips_symbol_binds_local_p (const_rtx x)
1518 return (SYMBOL_REF_DECL (x)
1519 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1520 : SYMBOL_REF_LOCAL_P (x));
1523 /* Return true if rtx constants of mode MODE should be put into a small
1527 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1529 return (!TARGET_EMBEDDED_DATA
1530 && TARGET_LOCAL_SDATA
1531 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1534 /* Return true if X should not be moved directly into register $25.
1535 We need this because many versions of GAS will treat "la $25,foo" as
1536 part of a call sequence and so allow a global "foo" to be lazily bound. */
1539 mips_dangerous_for_la25_p (rtx x)
1541 return (!TARGET_EXPLICIT_RELOCS
1543 && GET_CODE (x) == SYMBOL_REF
1544 && mips_global_symbol_p (x));
1547 /* Return true if calls to X might need $25 to be valid on entry. */
1550 mips_use_pic_fn_addr_reg_p (const_rtx x)
1552 if (!TARGET_USE_PIC_FN_ADDR_REG)
1555 /* MIPS16 stub functions are guaranteed not to use $25. */
1556 if (mips16_stub_function_p (x))
1559 if (GET_CODE (x) == SYMBOL_REF)
1561 /* If PLTs and copy relocations are available, the static linker
1562 will make sure that $25 is valid on entry to the target function. */
1563 if (TARGET_ABICALLS_PIC0)
1566 /* Locally-defined functions use absolute accesses to set up
1567 the global pointer. */
1568 if (TARGET_ABSOLUTE_ABICALLS
1569 && mips_symbol_binds_local_p (x)
1570 && !SYMBOL_REF_EXTERNAL_P (x))
1577 /* Return the method that should be used to access SYMBOL_REF or
1578 LABEL_REF X in context CONTEXT. */
1580 static enum mips_symbol_type
1581 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1584 return SYMBOL_GOT_DISP;
1586 if (GET_CODE (x) == LABEL_REF)
1588 /* LABEL_REFs are used for jump tables as well as text labels.
1589 Only return SYMBOL_PC_RELATIVE if we know the label is in
1590 the text section. */
1591 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1592 return SYMBOL_PC_RELATIVE;
1594 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1595 return SYMBOL_GOT_PAGE_OFST;
1597 return SYMBOL_ABSOLUTE;
1600 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1602 if (SYMBOL_REF_TLS_MODEL (x))
1605 if (CONSTANT_POOL_ADDRESS_P (x))
1607 if (TARGET_MIPS16_TEXT_LOADS)
1608 return SYMBOL_PC_RELATIVE;
1610 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1611 return SYMBOL_PC_RELATIVE;
1613 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1614 return SYMBOL_GP_RELATIVE;
1617 /* Do not use small-data accesses for weak symbols; they may end up
1619 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1620 return SYMBOL_GP_RELATIVE;
1622 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1624 if (TARGET_ABICALLS_PIC2
1625 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1627 /* There are three cases to consider:
1629 - o32 PIC (either with or without explicit relocs)
1630 - n32/n64 PIC without explicit relocs
1631 - n32/n64 PIC with explicit relocs
1633 In the first case, both local and global accesses will use an
1634 R_MIPS_GOT16 relocation. We must correctly predict which of
1635 the two semantics (local or global) the assembler and linker
1636 will apply. The choice depends on the symbol's binding rather
1637 than its visibility.
1639 In the second case, the assembler will not use R_MIPS_GOT16
1640 relocations, but it chooses between local and global accesses
1641 in the same way as for o32 PIC.
1643 In the third case we have more freedom since both forms of
1644 access will work for any kind of symbol. However, there seems
1645 little point in doing things differently. */
1646 if (mips_global_symbol_p (x))
1647 return SYMBOL_GOT_DISP;
1649 return SYMBOL_GOT_PAGE_OFST;
1652 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1653 return SYMBOL_FORCE_TO_MEM;
1655 return SYMBOL_ABSOLUTE;
1658 /* Classify the base of symbolic expression X, given that X appears in
1661 static enum mips_symbol_type
1662 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1666 split_const (x, &x, &offset);
1667 if (UNSPEC_ADDRESS_P (x))
1668 return UNSPEC_ADDRESS_TYPE (x);
1670 return mips_classify_symbol (x, context);
1673 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1674 is the alignment in bytes of SYMBOL_REF X. */
1677 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1679 HOST_WIDE_INT align;
1681 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1682 return IN_RANGE (offset, 0, align - 1);
1685 /* Return true if X is a symbolic constant that can be used in context
1686 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1689 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1690 enum mips_symbol_type *symbol_type)
1694 split_const (x, &x, &offset);
1695 if (UNSPEC_ADDRESS_P (x))
1697 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1698 x = UNSPEC_ADDRESS (x);
1700 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1702 *symbol_type = mips_classify_symbol (x, context);
1703 if (*symbol_type == SYMBOL_TLS)
1709 if (offset == const0_rtx)
1712 /* Check whether a nonzero offset is valid for the underlying
1714 switch (*symbol_type)
1716 case SYMBOL_ABSOLUTE:
1717 case SYMBOL_FORCE_TO_MEM:
1718 case SYMBOL_32_HIGH:
1719 case SYMBOL_64_HIGH:
1722 /* If the target has 64-bit pointers and the object file only
1723 supports 32-bit symbols, the values of those symbols will be
1724 sign-extended. In this case we can't allow an arbitrary offset
1725 in case the 32-bit value X + OFFSET has a different sign from X. */
1726 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1727 return offset_within_block_p (x, INTVAL (offset));
1729 /* In other cases the relocations can handle any offset. */
1732 case SYMBOL_PC_RELATIVE:
1733 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1734 In this case, we no longer have access to the underlying constant,
1735 but the original symbol-based access was known to be valid. */
1736 if (GET_CODE (x) == LABEL_REF)
1741 case SYMBOL_GP_RELATIVE:
1742 /* Make sure that the offset refers to something within the
1743 same object block. This should guarantee that the final
1744 PC- or GP-relative offset is within the 16-bit limit. */
1745 return offset_within_block_p (x, INTVAL (offset));
1747 case SYMBOL_GOT_PAGE_OFST:
1748 case SYMBOL_GOTOFF_PAGE:
1749 /* If the symbol is global, the GOT entry will contain the symbol's
1750 address, and we will apply a 16-bit offset after loading it.
1751 If the symbol is local, the linker should provide enough local
1752 GOT entries for a 16-bit offset, but larger offsets may lead
1754 return SMALL_INT (offset);
1758 /* There is no carry between the HI and LO REL relocations, so the
1759 offset is only valid if we know it won't lead to such a carry. */
1760 return mips_offset_within_alignment_p (x, INTVAL (offset));
1762 case SYMBOL_GOT_DISP:
1763 case SYMBOL_GOTOFF_DISP:
1764 case SYMBOL_GOTOFF_CALL:
1765 case SYMBOL_GOTOFF_LOADGP:
1768 case SYMBOL_GOTTPREL:
1776 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1777 single instruction. We rely on the fact that, in the worst case,
1778 all instructions involved in a MIPS16 address calculation are usually
1782 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1786 case SYMBOL_ABSOLUTE:
1787 /* When using 64-bit symbols, we need 5 preparatory instructions,
1790 lui $at,%highest(symbol)
1791 daddiu $at,$at,%higher(symbol)
1793 daddiu $at,$at,%hi(symbol)
1796 The final address is then $at + %lo(symbol). With 32-bit
1797 symbols we just need a preparatory LUI for normal mode and
1798 a preparatory LI and SLL for MIPS16. */
1799 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1801 case SYMBOL_GP_RELATIVE:
1802 /* Treat GP-relative accesses as taking a single instruction on
1803 MIPS16 too; the copy of $gp can often be shared. */
1806 case SYMBOL_PC_RELATIVE:
1807 /* PC-relative constants can be only be used with ADDIUPC,
1808 DADDIUPC, LWPC and LDPC. */
1809 if (mode == MAX_MACHINE_MODE
1810 || GET_MODE_SIZE (mode) == 4
1811 || GET_MODE_SIZE (mode) == 8)
1814 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1817 case SYMBOL_FORCE_TO_MEM:
1818 /* LEAs will be converted into constant-pool references by
1820 if (mode == MAX_MACHINE_MODE)
1823 /* The constant must be loaded and then dereferenced. */
1826 case SYMBOL_GOT_DISP:
1827 /* The constant will have to be loaded from the GOT before it
1828 is used in an address. */
1829 if (mode != MAX_MACHINE_MODE)
1834 case SYMBOL_GOT_PAGE_OFST:
1835 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1836 local/global classification is accurate. The worst cases are:
1838 (1) For local symbols when generating o32 or o64 code. The assembler
1844 ...and the final address will be $at + %lo(symbol).
1846 (2) For global symbols when -mxgot. The assembler will use:
1848 lui $at,%got_hi(symbol)
1851 ...and the final address will be $at + %got_lo(symbol). */
1854 case SYMBOL_GOTOFF_PAGE:
1855 case SYMBOL_GOTOFF_DISP:
1856 case SYMBOL_GOTOFF_CALL:
1857 case SYMBOL_GOTOFF_LOADGP:
1858 case SYMBOL_32_HIGH:
1859 case SYMBOL_64_HIGH:
1865 case SYMBOL_GOTTPREL:
1868 /* A 16-bit constant formed by a single relocation, or a 32-bit
1869 constant formed from a high 16-bit relocation and a low 16-bit
1870 relocation. Use mips_split_p to determine which. 32-bit
1871 constants need an "lui; addiu" sequence for normal mode and
1872 an "li; sll; addiu" sequence for MIPS16 mode. */
1873 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1876 /* We don't treat a bare TLS symbol as a constant. */
1882 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1883 to load symbols of type TYPE into a register. Return 0 if the given
1884 type of symbol cannot be used as an immediate operand.
1886 Otherwise, return the number of instructions needed to load or store
1887 values of mode MODE to or from addresses of type TYPE. Return 0 if
1888 the given type of symbol is not valid in addresses.
1890 In both cases, treat extended MIPS16 instructions as two instructions. */
1893 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1895 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1898 /* A for_each_rtx callback. Stop the search if *X references a
1899 thread-local symbol. */
1902 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1904 return mips_tls_symbol_p (*x);
1907 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1910 mips_cannot_force_const_mem (rtx x)
1912 enum mips_symbol_type type;
1915 /* There is no assembler syntax for expressing an address-sized
1917 if (GET_CODE (x) == HIGH)
1920 /* As an optimization, reject constants that mips_legitimize_move
1923 Suppose we have a multi-instruction sequence that loads constant C
1924 into register R. If R does not get allocated a hard register, and
1925 R is used in an operand that allows both registers and memory
1926 references, reload will consider forcing C into memory and using
1927 one of the instruction's memory alternatives. Returning false
1928 here will force it to use an input reload instead. */
1929 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1932 split_const (x, &base, &offset);
1933 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1934 && type != SYMBOL_FORCE_TO_MEM)
1936 /* The same optimization as for CONST_INT. */
1937 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1940 /* If MIPS16 constant pools live in the text section, they should
1941 not refer to anything that might need run-time relocation. */
1942 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1946 /* TLS symbols must be computed by mips_legitimize_move. */
1947 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1953 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1954 constants when we're using a per-function constant pool. */
1957 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1958 const_rtx x ATTRIBUTE_UNUSED)
1960 return !TARGET_MIPS16_PCREL_LOADS;
1963 /* Return true if register REGNO is a valid base register for mode MODE.
1964 STRICT_P is true if REG_OK_STRICT is in effect. */
1967 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1970 if (!HARD_REGISTER_NUM_P (regno))
1974 regno = reg_renumber[regno];
1977 /* These fake registers will be eliminated to either the stack or
1978 hard frame pointer, both of which are usually valid base registers.
1979 Reload deals with the cases where the eliminated form isn't valid. */
1980 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1983 /* In MIPS16 mode, the stack pointer can only address word and doubleword
1984 values, nothing smaller. There are two problems here:
1986 (a) Instantiating virtual registers can introduce new uses of the
1987 stack pointer. If these virtual registers are valid addresses,
1988 the stack pointer should be too.
1990 (b) Most uses of the stack pointer are not made explicit until
1991 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1992 We don't know until that stage whether we'll be eliminating to the
1993 stack pointer (which needs the restriction) or the hard frame
1994 pointer (which doesn't).
1996 All in all, it seems more consistent to only enforce this restriction
1997 during and after reload. */
1998 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1999 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2001 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2004 /* Return true if X is a valid base register for mode MODE.
2005 STRICT_P is true if REG_OK_STRICT is in effect. */
2008 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2010 if (!strict_p && GET_CODE (x) == SUBREG)
2014 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2017 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2018 can address a value of mode MODE. */
2021 mips_valid_offset_p (rtx x, enum machine_mode mode)
2023 /* Check that X is a signed 16-bit number. */
2024 if (!const_arith_operand (x, Pmode))
2027 /* We may need to split multiword moves, so make sure that every word
2029 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2030 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2036 /* Return true if a LO_SUM can address a value of mode MODE when the
2037 LO_SUM symbol has type SYMBOL_TYPE. */
2040 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2042 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2044 if (mips_symbol_insns (symbol_type, mode) == 0)
2047 /* Check that there is a known low-part relocation. */
2048 if (mips_lo_relocs[symbol_type] == NULL)
2051 /* We may need to split multiword moves, so make sure that each word
2052 can be accessed without inducing a carry. This is mainly needed
2053 for o64, which has historically only guaranteed 64-bit alignment
2054 for 128-bit types. */
2055 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2056 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2062 /* Return true if X is a valid address for machine mode MODE. If it is,
2063 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2067 mips_classify_address (struct mips_address_info *info, rtx x,
2068 enum machine_mode mode, bool strict_p)
2070 switch (GET_CODE (x))
2074 info->type = ADDRESS_REG;
2076 info->offset = const0_rtx;
2077 return mips_valid_base_register_p (info->reg, mode, strict_p);
2080 info->type = ADDRESS_REG;
2081 info->reg = XEXP (x, 0);
2082 info->offset = XEXP (x, 1);
2083 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2084 && mips_valid_offset_p (info->offset, mode));
2087 info->type = ADDRESS_LO_SUM;
2088 info->reg = XEXP (x, 0);
2089 info->offset = XEXP (x, 1);
2090 /* We have to trust the creator of the LO_SUM to do something vaguely
2091 sane. Target-independent code that creates a LO_SUM should also
2092 create and verify the matching HIGH. Target-independent code that
2093 adds an offset to a LO_SUM must prove that the offset will not
2094 induce a carry. Failure to do either of these things would be
2095 a bug, and we are not required to check for it here. The MIPS
2096 backend itself should only create LO_SUMs for valid symbolic
2097 constants, with the high part being either a HIGH or a copy
2100 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2101 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2102 && mips_valid_lo_sum_p (info->symbol_type, mode));
2105 /* Small-integer addresses don't occur very often, but they
2106 are legitimate if $0 is a valid base register. */
2107 info->type = ADDRESS_CONST_INT;
2108 return !TARGET_MIPS16 && SMALL_INT (x);
2113 info->type = ADDRESS_SYMBOLIC;
2114 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2116 && mips_symbol_insns (info->symbol_type, mode) > 0
2117 && !mips_split_p[info->symbol_type]);
2124 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2127 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2129 struct mips_address_info addr;
2131 return mips_classify_address (&addr, x, mode, strict_p);
2134 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2137 mips_stack_address_p (rtx x, enum machine_mode mode)
2139 struct mips_address_info addr;
2141 return (mips_classify_address (&addr, x, mode, false)
2142 && addr.type == ADDRESS_REG
2143 && addr.reg == stack_pointer_rtx);
2146 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2147 address instruction. Note that such addresses are not considered
2148 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2149 is so restricted. */
2152 mips_lwxs_address_p (rtx addr)
2155 && GET_CODE (addr) == PLUS
2156 && REG_P (XEXP (addr, 1)))
2158 rtx offset = XEXP (addr, 0);
2159 if (GET_CODE (offset) == MULT
2160 && REG_P (XEXP (offset, 0))
2161 && CONST_INT_P (XEXP (offset, 1))
2162 && INTVAL (XEXP (offset, 1)) == 4)
2168 /* Return true if a value at OFFSET bytes from base register BASE can be
2169 accessed using an unextended MIPS16 instruction. MODE is the mode of
2172 Usually the offset in an unextended instruction is a 5-bit field.
2173 The offset is unsigned and shifted left once for LH and SH, twice
2174 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2175 an 8-bit immediate field that's shifted left twice. */
2178 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2179 unsigned HOST_WIDE_INT offset)
2181 if (offset % GET_MODE_SIZE (mode) == 0)
2183 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2184 return offset < 256U * GET_MODE_SIZE (mode);
2185 return offset < 32U * GET_MODE_SIZE (mode);
2190 /* Return the number of instructions needed to load or store a value
2191 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2192 Assume that multiword moves may need to be split into word moves
2193 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2196 For MIPS16 code, count extended instructions as two instructions. */
2199 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2201 struct mips_address_info addr;
2204 /* BLKmode is used for single unaligned loads and stores and should
2205 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2206 meaningless, so we have to single it out as a special case one way
2208 if (mode != BLKmode && might_split_p)
2209 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2213 if (mips_classify_address (&addr, x, mode, false))
2218 && !mips16_unextended_reference_p (mode, addr.reg,
2219 UINTVAL (addr.offset)))
2223 case ADDRESS_LO_SUM:
2224 return TARGET_MIPS16 ? factor * 2 : factor;
2226 case ADDRESS_CONST_INT:
2229 case ADDRESS_SYMBOLIC:
2230 return factor * mips_symbol_insns (addr.symbol_type, mode);
2235 /* Return the number of instructions needed to load constant X.
2236 Return 0 if X isn't a valid constant. */
2239 mips_const_insns (rtx x)
2241 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2242 enum mips_symbol_type symbol_type;
2245 switch (GET_CODE (x))
2248 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2250 || !mips_split_p[symbol_type])
2253 /* This is simply an LUI for normal mode. It is an extended
2254 LI followed by an extended SLL for MIPS16. */
2255 return TARGET_MIPS16 ? 4 : 1;
2259 /* Unsigned 8-bit constants can be loaded using an unextended
2260 LI instruction. Unsigned 16-bit constants can be loaded
2261 using an extended LI. Negative constants must be loaded
2262 using LI and then negated. */
2263 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2264 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2265 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2266 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2269 return mips_build_integer (codes, INTVAL (x));
2273 /* Allow zeros for normal mode, where we can use $0. */
2274 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2280 /* See if we can refer to X directly. */
2281 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2282 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2284 /* Otherwise try splitting the constant into a base and offset.
2285 If the offset is a 16-bit value, we can load the base address
2286 into a register and then use (D)ADDIU to add in the offset.
2287 If the offset is larger, we can load the base and offset
2288 into separate registers and add them together with (D)ADDU.
2289 However, the latter is only possible before reload; during
2290 and after reload, we must have the option of forcing the
2291 constant into the pool instead. */
2292 split_const (x, &x, &offset);
2295 int n = mips_const_insns (x);
2298 if (SMALL_INT (offset))
2300 else if (!targetm.cannot_force_const_mem (x))
2301 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2308 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2316 /* X is a doubleword constant that can be handled by splitting it into
2317 two words and loading each word separately. Return the number of
2318 instructions required to do this. */
2321 mips_split_const_insns (rtx x)
2323 unsigned int low, high;
2325 low = mips_const_insns (mips_subword (x, false));
2326 high = mips_const_insns (mips_subword (x, true));
2327 gcc_assert (low > 0 && high > 0);
2331 /* Return the number of instructions needed to implement INSN,
2332 given that it loads from or stores to MEM. Count extended
2333 MIPS16 instructions as two instructions. */
2336 mips_load_store_insns (rtx mem, rtx insn)
2338 enum machine_mode mode;
2342 gcc_assert (MEM_P (mem));
2343 mode = GET_MODE (mem);
2345 /* Try to prove that INSN does not need to be split. */
2346 might_split_p = true;
2347 if (GET_MODE_BITSIZE (mode) == 64)
2349 set = single_set (insn);
2350 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2351 might_split_p = false;
2354 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2357 /* Return the number of instructions needed for an integer division. */
2360 mips_idiv_insns (void)
2365 if (TARGET_CHECK_ZERO_DIV)
2367 if (GENERATE_DIVIDE_TRAPS)
2373 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2378 /* Emit a move from SRC to DEST. Assume that the move expanders can
2379 handle all moves if !can_create_pseudo_p (). The distinction is
2380 important because, unlike emit_move_insn, the move expanders know
2381 how to force Pmode objects into the constant pool even when the
2382 constant pool address is not itself legitimate. */
2385 mips_emit_move (rtx dest, rtx src)
2387 return (can_create_pseudo_p ()
2388 ? emit_move_insn (dest, src)
2389 : emit_move_insn_1 (dest, src));
2392 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2395 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2397 emit_insn (gen_rtx_SET (VOIDmode, target,
2398 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2401 /* Compute (CODE OP0 OP1) and store the result in a new register
2402 of mode MODE. Return that new register. */
2405 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2409 reg = gen_reg_rtx (mode);
2410 mips_emit_binary (code, reg, op0, op1);
2414 /* Copy VALUE to a register and return that register. If new pseudos
2415 are allowed, copy it into a new register, otherwise use DEST. */
2418 mips_force_temporary (rtx dest, rtx value)
2420 if (can_create_pseudo_p ())
2421 return force_reg (Pmode, value);
2424 mips_emit_move (dest, value);
2429 /* Emit a call sequence with call pattern PATTERN and return the call
2430 instruction itself (which is not necessarily the last instruction
2431 emitted). ORIG_ADDR is the original, unlegitimized address,
2432 ADDR is the legitimized form, and LAZY_P is true if the call
2433 address is lazily-bound. */
2436 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2440 insn = emit_call_insn (pattern);
2442 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2444 /* MIPS16 JALRs only take MIPS16 registers. If the target
2445 function requires $25 to be valid on entry, we must copy it
2446 there separately. The move instruction can be put in the
2447 call's delay slot. */
2448 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2449 emit_insn_before (gen_move_insn (reg, addr), insn);
2450 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2454 /* Lazy-binding stubs require $gp to be valid on entry. */
2455 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2459 /* See the comment above load_call<mode> for details. */
2460 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2461 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2462 emit_insn (gen_update_got_version ());
2467 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2468 then add CONST_INT OFFSET to the result. */
2471 mips_unspec_address_offset (rtx base, rtx offset,
2472 enum mips_symbol_type symbol_type)
2474 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2475 UNSPEC_ADDRESS_FIRST + symbol_type);
2476 if (offset != const0_rtx)
2477 base = gen_rtx_PLUS (Pmode, base, offset);
2478 return gen_rtx_CONST (Pmode, base);
2481 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2482 type SYMBOL_TYPE. */
2485 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2489 split_const (address, &base, &offset);
2490 return mips_unspec_address_offset (base, offset, symbol_type);
2493 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2494 high part to BASE and return the result. Just return BASE otherwise.
2495 TEMP is as for mips_force_temporary.
2497 The returned expression can be used as the first operand to a LO_SUM. */
2500 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2501 enum mips_symbol_type symbol_type)
2503 if (mips_split_p[symbol_type])
2505 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2506 addr = mips_force_temporary (temp, addr);
2507 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2512 /* Return an instruction that copies $gp into register REG. We want
2513 GCC to treat the register's value as constant, so that its value
2514 can be rematerialized on demand. */
2517 gen_load_const_gp (rtx reg)
2519 return (Pmode == SImode
2520 ? gen_load_const_gp_si (reg)
2521 : gen_load_const_gp_di (reg));
2524 /* Return a pseudo register that contains the value of $gp throughout
2525 the current function. Such registers are needed by MIPS16 functions,
2526 for which $gp itself is not a valid base register or addition operand. */
2529 mips16_gp_pseudo_reg (void)
2531 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2532 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2534 /* Don't emit an instruction to initialize the pseudo register if
2535 we are being called from the tree optimizers' cost-calculation
2537 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2538 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2542 push_topmost_sequence ();
2544 scan = get_insns ();
2545 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2546 scan = NEXT_INSN (scan);
2548 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2549 emit_insn_after (insn, scan);
2551 pop_topmost_sequence ();
2553 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2556 return cfun->machine->mips16_gp_pseudo_rtx;
2559 /* Return a base register that holds pic_offset_table_rtx.
2560 TEMP, if nonnull, is a scratch Pmode base register. */
2563 mips_pic_base_register (rtx temp)
2566 return pic_offset_table_rtx;
2568 if (can_create_pseudo_p ())
2569 return mips16_gp_pseudo_reg ();
2572 /* The first post-reload split exposes all references to $gp
2573 (both uses and definitions). All references must remain
2574 explicit after that point.
2576 It is safe to introduce uses of $gp at any time, so for
2577 simplicity, we do that before the split too. */
2578 mips_emit_move (temp, pic_offset_table_rtx);
2580 emit_insn (gen_load_const_gp (temp));
2584 /* Create and return a GOT reference of type TYPE for address ADDR.
2585 TEMP, if nonnull, is a scratch Pmode base register. */
2588 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2590 rtx base, high, lo_sum_symbol;
2592 base = mips_pic_base_register (temp);
2594 /* If we used the temporary register to load $gp, we can't use
2595 it for the high part as well. */
2596 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2599 high = mips_unspec_offset_high (temp, base, addr, type);
2600 lo_sum_symbol = mips_unspec_address (addr, type);
2602 if (type == SYMBOL_GOTOFF_CALL)
2603 return (Pmode == SImode
2604 ? gen_unspec_callsi (high, lo_sum_symbol)
2605 : gen_unspec_calldi (high, lo_sum_symbol));
2607 return (Pmode == SImode
2608 ? gen_unspec_gotsi (high, lo_sum_symbol)
2609 : gen_unspec_gotdi (high, lo_sum_symbol));
2612 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2613 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2614 constant in that context and can be split into high and low parts.
2615 If so, and if LOW_OUT is nonnull, emit the high part and store the
2616 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2618 TEMP is as for mips_force_temporary and is used to load the high
2619 part into a register.
2621 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2622 a legitimize SET_SRC for an .md pattern, otherwise the low part
2623 is guaranteed to be a legitimate address for mode MODE. */
2626 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2628 enum mips_symbol_context context;
2629 enum mips_symbol_type symbol_type;
2632 context = (mode == MAX_MACHINE_MODE
2633 ? SYMBOL_CONTEXT_LEA
2634 : SYMBOL_CONTEXT_MEM);
2635 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2637 addr = XEXP (addr, 0);
2638 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2639 && mips_symbol_insns (symbol_type, mode) > 0
2640 && mips_split_hi_p[symbol_type])
2643 switch (symbol_type)
2645 case SYMBOL_GOT_PAGE_OFST:
2646 /* The high part of a page/ofst pair is loaded from the GOT. */
2647 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2658 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2659 && mips_symbol_insns (symbol_type, mode) > 0
2660 && mips_split_p[symbol_type])
2663 switch (symbol_type)
2665 case SYMBOL_GOT_DISP:
2666 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2667 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2670 case SYMBOL_GP_RELATIVE:
2671 high = mips_pic_base_register (temp);
2672 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2676 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2677 high = mips_force_temporary (temp, high);
2678 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2687 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2688 mips_force_temporary; it is only needed when OFFSET is not a
2692 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2694 if (!SMALL_OPERAND (offset))
2700 /* Load the full offset into a register so that we can use
2701 an unextended instruction for the address itself. */
2702 high = GEN_INT (offset);
2707 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2708 The addition inside the macro CONST_HIGH_PART may cause an
2709 overflow, so we need to force a sign-extension check. */
2710 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2711 offset = CONST_LOW_PART (offset);
2713 high = mips_force_temporary (temp, high);
2714 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2716 return plus_constant (reg, offset);
2719 /* The __tls_get_attr symbol. */
2720 static GTY(()) rtx mips_tls_symbol;
2722 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2723 the TLS symbol we are referencing and TYPE is the symbol type to use
2724 (either global dynamic or local dynamic). V0 is an RTX for the
2725 return value location. */
2728 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2732 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2734 if (!mips_tls_symbol)
2735 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2737 loc = mips_unspec_address (sym, type);
2741 emit_insn (gen_rtx_SET (Pmode, a0,
2742 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2743 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2744 const0_rtx, NULL_RTX, false);
2745 RTL_CONST_CALL_P (insn) = 1;
2746 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2747 insn = get_insns ();
2754 /* Return a pseudo register that contains the current thread pointer. */
2761 tp = gen_reg_rtx (Pmode);
2762 if (Pmode == DImode)
2763 emit_insn (gen_tls_get_tp_di (tp));
2765 emit_insn (gen_tls_get_tp_si (tp));
2769 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2770 its address. The return value will be both a valid address and a valid
2771 SET_SRC (either a REG or a LO_SUM). */
2774 mips_legitimize_tls_address (rtx loc)
2776 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2777 enum tls_model model;
2781 sorry ("MIPS16 TLS");
2782 return gen_reg_rtx (Pmode);
2785 model = SYMBOL_REF_TLS_MODEL (loc);
2786 /* Only TARGET_ABICALLS code can have more than one module; other
2787 code must be be static and should not use a GOT. All TLS models
2788 reduce to local exec in this situation. */
2789 if (!TARGET_ABICALLS)
2790 model = TLS_MODEL_LOCAL_EXEC;
2794 case TLS_MODEL_GLOBAL_DYNAMIC:
2795 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2796 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2797 dest = gen_reg_rtx (Pmode);
2798 emit_libcall_block (insn, dest, v0, loc);
2801 case TLS_MODEL_LOCAL_DYNAMIC:
2802 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2803 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2804 tmp1 = gen_reg_rtx (Pmode);
2806 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2807 share the LDM result with other LD model accesses. */
2808 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2810 emit_libcall_block (insn, tmp1, v0, eqv);
2812 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2813 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2814 mips_unspec_address (loc, SYMBOL_DTPREL));
2817 case TLS_MODEL_INITIAL_EXEC:
2818 tp = mips_get_tp ();
2819 tmp1 = gen_reg_rtx (Pmode);
2820 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2821 if (Pmode == DImode)
2822 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2824 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2825 dest = gen_reg_rtx (Pmode);
2826 emit_insn (gen_add3_insn (dest, tmp1, tp));
2829 case TLS_MODEL_LOCAL_EXEC:
2830 tp = mips_get_tp ();
2831 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2832 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2833 mips_unspec_address (loc, SYMBOL_TPREL));
2842 /* If X is not a valid address for mode MODE, force it into a register. */
2845 mips_force_address (rtx x, enum machine_mode mode)
2847 if (!mips_legitimate_address_p (mode, x, false))
2848 x = force_reg (Pmode, x);
2852 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2853 be legitimized in a way that the generic machinery might not expect,
2854 return a new address, otherwise return NULL. MODE is the mode of
2855 the memory being accessed. */
2858 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2859 enum machine_mode mode)
2862 HOST_WIDE_INT offset;
2864 if (mips_tls_symbol_p (x))
2865 return mips_legitimize_tls_address (x);
2867 /* See if the address can split into a high part and a LO_SUM. */
2868 if (mips_split_symbol (NULL, x, mode, &addr))
2869 return mips_force_address (addr, mode);
2871 /* Handle BASE + OFFSET using mips_add_offset. */
2872 mips_split_plus (x, &base, &offset);
2875 if (!mips_valid_base_register_p (base, mode, false))
2876 base = copy_to_mode_reg (Pmode, base);
2877 addr = mips_add_offset (NULL, base, offset);
2878 return mips_force_address (addr, mode);
2884 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2887 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2889 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2890 enum machine_mode mode;
2891 unsigned int i, num_ops;
2894 mode = GET_MODE (dest);
2895 num_ops = mips_build_integer (codes, value);
2897 /* Apply each binary operation to X. Invariant: X is a legitimate
2898 source operand for a SET pattern. */
2899 x = GEN_INT (codes[0].value);
2900 for (i = 1; i < num_ops; i++)
2902 if (!can_create_pseudo_p ())
2904 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2908 x = force_reg (mode, x);
2909 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2912 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2915 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2916 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2920 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2924 /* Split moves of big integers into smaller pieces. */
2925 if (splittable_const_int_operand (src, mode))
2927 mips_move_integer (dest, dest, INTVAL (src));
2931 /* Split moves of symbolic constants into high/low pairs. */
2932 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2934 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2938 /* Generate the appropriate access sequences for TLS symbols. */
2939 if (mips_tls_symbol_p (src))
2941 mips_emit_move (dest, mips_legitimize_tls_address (src));
2945 /* If we have (const (plus symbol offset)), and that expression cannot
2946 be forced into memory, load the symbol first and add in the offset.
2947 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
2948 forced into memory, as it usually produces better code. */
2949 split_const (src, &base, &offset);
2950 if (offset != const0_rtx
2951 && (targetm.cannot_force_const_mem (src)
2952 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
2954 base = mips_force_temporary (dest, base);
2955 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
2959 src = force_const_mem (mode, src);
2961 /* When using explicit relocs, constant pool references are sometimes
2962 not legitimate addresses. */
2963 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
2964 mips_emit_move (dest, src);
2967 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
2968 sequence that is valid. */
2971 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2973 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2975 mips_emit_move (dest, force_reg (mode, src));
2979 /* We need to deal with constants that would be legitimate
2980 immediate_operands but aren't legitimate move_operands. */
2981 if (CONSTANT_P (src) && !move_operand (src, mode))
2983 mips_legitimize_const_move (mode, dest, src);
2984 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2990 /* Return true if value X in context CONTEXT is a small-data address
2991 that can be rewritten as a LO_SUM. */
2994 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
2996 enum mips_symbol_type symbol_type;
2998 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
2999 && !mips_split_p[SYMBOL_GP_RELATIVE]
3000 && mips_symbolic_constant_p (x, context, &symbol_type)
3001 && symbol_type == SYMBOL_GP_RELATIVE);
3004 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3005 containing MEM, or null if none. */
3008 mips_small_data_pattern_1 (rtx *loc, void *data)
3010 enum mips_symbol_context context;
3012 if (GET_CODE (*loc) == LO_SUM)
3017 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3022 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3023 return mips_rewrite_small_data_p (*loc, context);
3026 /* Return true if OP refers to small data symbols directly, not through
3030 mips_small_data_pattern_p (rtx op)
3032 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3035 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3036 DATA is the containing MEM, or null if none. */
3039 mips_rewrite_small_data_1 (rtx *loc, void *data)
3041 enum mips_symbol_context context;
3045 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3049 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3050 if (mips_rewrite_small_data_p (*loc, context))
3051 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3053 if (GET_CODE (*loc) == LO_SUM)
3059 /* Rewrite instruction pattern PATTERN so that it refers to small data
3060 using explicit relocations. */
3063 mips_rewrite_small_data (rtx pattern)
3065 pattern = copy_insn (pattern);
3066 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3070 /* We need a lot of little routines to check the range of MIPS16 immediate
3074 m16_check_op (rtx op, int low, int high, int mask)
3076 return (CONST_INT_P (op)
3077 && IN_RANGE (INTVAL (op), low, high)
3078 && (INTVAL (op) & mask) == 0);
3082 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3084 return m16_check_op (op, 0x1, 0x8, 0);
3088 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3090 return m16_check_op (op, -0x8, 0x7, 0);
3094 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3096 return m16_check_op (op, -0x7, 0x8, 0);
3100 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3102 return m16_check_op (op, -0x10, 0xf, 0);
3106 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3108 return m16_check_op (op, -0xf, 0x10, 0);
3112 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3114 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3118 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3120 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3124 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3126 return m16_check_op (op, -0x80, 0x7f, 0);
3130 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3132 return m16_check_op (op, -0x7f, 0x80, 0);
3136 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3138 return m16_check_op (op, 0x0, 0xff, 0);
3142 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3144 return m16_check_op (op, -0xff, 0x0, 0);
3148 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3150 return m16_check_op (op, -0x1, 0xfe, 0);
3154 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3156 return m16_check_op (op, 0x0, 0xff << 2, 3);
3160 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3162 return m16_check_op (op, -0xff << 2, 0x0, 3);
3166 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3168 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3172 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3174 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3177 /* The cost of loading values from the constant pool. It should be
3178 larger than the cost of any constant we want to synthesize inline. */
3179 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3181 /* Return the cost of X when used as an operand to the MIPS16 instruction
3182 that implements CODE. Return -1 if there is no such instruction, or if
3183 X is not a valid immediate operand for it. */
3186 mips16_constant_cost (int code, HOST_WIDE_INT x)
3193 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3194 other shifts are extended. The shift patterns truncate the shift
3195 count to the right size, so there are no out-of-range values. */
3196 if (IN_RANGE (x, 1, 8))
3198 return COSTS_N_INSNS (1);
3201 if (IN_RANGE (x, -128, 127))
3203 if (SMALL_OPERAND (x))
3204 return COSTS_N_INSNS (1);
3208 /* Like LE, but reject the always-true case. */
3212 /* We add 1 to the immediate and use SLT. */
3215 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3218 if (IN_RANGE (x, 0, 255))
3220 if (SMALL_OPERAND_UNSIGNED (x))
3221 return COSTS_N_INSNS (1);
3226 /* Equality comparisons with 0 are cheap. */
3236 /* Return true if there is a non-MIPS16 instruction that implements CODE
3237 and if that instruction accepts X as an immediate operand. */
3240 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3247 /* All shift counts are truncated to a valid constant. */
3252 /* Likewise rotates, if the target supports rotates at all. */
3258 /* These instructions take 16-bit unsigned immediates. */
3259 return SMALL_OPERAND_UNSIGNED (x);
3264 /* These instructions take 16-bit signed immediates. */
3265 return SMALL_OPERAND (x);
3271 /* The "immediate" forms of these instructions are really
3272 implemented as comparisons with register 0. */
3277 /* Likewise, meaning that the only valid immediate operand is 1. */
3281 /* We add 1 to the immediate and use SLT. */
3282 return SMALL_OPERAND (x + 1);
3285 /* Likewise SLTU, but reject the always-true case. */
3286 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3290 /* The bit position and size are immediate operands. */
3291 return ISA_HAS_EXT_INS;
3294 /* By default assume that $0 can be used for 0. */
3299 /* Return the cost of binary operation X, given that the instruction
3300 sequence for a word-sized or smaller operation has cost SINGLE_COST
3301 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3304 mips_binary_cost (rtx x, int single_cost, int double_cost)
3308 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3313 + rtx_cost (XEXP (x, 0), SET, !optimize_size)
3314 + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size));
3317 /* Return the cost of floating-point multiplications of mode MODE. */
3320 mips_fp_mult_cost (enum machine_mode mode)
3322 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3325 /* Return the cost of floating-point divisions of mode MODE. */
3328 mips_fp_div_cost (enum machine_mode mode)
3330 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3333 /* Return the cost of sign-extending OP to mode MODE, not including the
3334 cost of OP itself. */
3337 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3340 /* Extended loads are as cheap as unextended ones. */
3343 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3344 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3347 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3348 /* We can use SEB or SEH. */
3349 return COSTS_N_INSNS (1);
3351 /* We need to use a shift left and a shift right. */
3352 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3355 /* Return the cost of zero-extending OP to mode MODE, not including the
3356 cost of OP itself. */
3359 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3362 /* Extended loads are as cheap as unextended ones. */
3365 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3366 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3367 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3369 if (GENERATE_MIPS16E)
3370 /* We can use ZEB or ZEH. */
3371 return COSTS_N_INSNS (1);
3374 /* We need to load 0xff or 0xffff into a register and use AND. */
3375 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3377 /* We can use ANDI. */
3378 return COSTS_N_INSNS (1);
3381 /* Implement TARGET_RTX_COSTS. */
3384 mips_rtx_costs (rtx x, int code, int outer_code, int *total,
3387 enum machine_mode mode = GET_MODE (x);
3388 bool float_mode_p = FLOAT_MODE_P (mode);
3392 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3393 appear in the instruction stream, and the cost of a comparison is
3394 really the cost of the branch or scc condition. At the time of
3395 writing, GCC only uses an explicit outer COMPARE code when optabs
3396 is testing whether a constant is expensive enough to force into a
3397 register. We want optabs to pass such constants through the MIPS
3398 expanders instead, so make all constants very cheap here. */
3399 if (outer_code == COMPARE)
3401 gcc_assert (CONSTANT_P (x));
3409 /* Treat *clear_upper32-style ANDs as having zero cost in the
3410 second operand. The cost is entirely in the first operand.
3412 ??? This is needed because we would otherwise try to CSE
3413 the constant operand. Although that's the right thing for
3414 instructions that continue to be a register operation throughout
3415 compilation, it is disastrous for instructions that could
3416 later be converted into a memory operation. */
3418 && outer_code == AND
3419 && UINTVAL (x) == 0xffffffff)
3427 cost = mips16_constant_cost (outer_code, INTVAL (x));
3436 /* When not optimizing for size, we care more about the cost
3437 of hot code, and hot code is often in a loop. If a constant
3438 operand needs to be forced into a register, we will often be
3439 able to hoist the constant load out of the loop, so the load
3440 should not contribute to the cost. */
3442 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3454 if (force_to_mem_operand (x, VOIDmode))
3456 *total = COSTS_N_INSNS (1);
3459 cost = mips_const_insns (x);
3462 /* If the constant is likely to be stored in a GPR, SETs of
3463 single-insn constants are as cheap as register sets; we
3464 never want to CSE them.
3466 Don't reduce the cost of storing a floating-point zero in
3467 FPRs. If we have a zero in an FPR for other reasons, we
3468 can get better cfg-cleanup and delayed-branch results by
3469 using it consistently, rather than using $0 sometimes and
3470 an FPR at other times. Also, moves between floating-point
3471 registers are sometimes cheaper than (D)MTC1 $0. */
3473 && outer_code == SET
3474 && !(float_mode_p && TARGET_HARD_FLOAT))
3476 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3477 want to CSE the constant itself. It is usually better to
3478 have N copies of the last operation in the sequence and one
3479 shared copy of the other operations. (Note that this is
3480 not true for MIPS16 code, where the final operation in the
3481 sequence is often an extended instruction.)
3483 Also, if we have a CONST_INT, we don't know whether it is
3484 for a word or doubleword operation, so we cannot rely on
3485 the result of mips_build_integer. */
3486 else if (!TARGET_MIPS16
3487 && (outer_code == SET || mode == VOIDmode))
3489 *total = COSTS_N_INSNS (cost);
3492 /* The value will need to be fetched from the constant pool. */
3493 *total = CONSTANT_POOL_COST;
3497 /* If the address is legitimate, return the number of
3498 instructions it needs. */
3500 cost = mips_address_insns (addr, mode, true);
3503 *total = COSTS_N_INSNS (cost + 1);
3506 /* Check for a scaled indexed address. */
3507 if (mips_lwxs_address_p (addr))
3509 *total = COSTS_N_INSNS (2);
3512 /* Otherwise use the default handling. */
3516 *total = COSTS_N_INSNS (6);
3520 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3524 /* Check for a *clear_upper32 pattern and treat it like a zero
3525 extension. See the pattern's comment for details. */
3528 && CONST_INT_P (XEXP (x, 1))
3529 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3531 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3532 + rtx_cost (XEXP (x, 0), SET, speed));
3539 /* Double-word operations use two single-word operations. */
3540 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3548 if (CONSTANT_P (XEXP (x, 1)))
3549 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3551 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3556 *total = mips_cost->fp_add;
3558 *total = COSTS_N_INSNS (4);
3562 /* Low-part immediates need an extended MIPS16 instruction. */
3563 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3564 + rtx_cost (XEXP (x, 0), SET, speed));
3579 /* Branch comparisons have VOIDmode, so use the first operand's
3581 mode = GET_MODE (XEXP (x, 0));
3582 if (FLOAT_MODE_P (mode))
3584 *total = mips_cost->fp_add;
3587 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3592 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3593 && TARGET_FUSED_MADD
3594 && !HONOR_NANS (mode)
3595 && !HONOR_SIGNED_ZEROS (mode))
3597 /* See if we can use NMADD or NMSUB. See mips.md for the
3598 associated patterns. */
3599 rtx op0 = XEXP (x, 0);
3600 rtx op1 = XEXP (x, 1);
3601 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3603 *total = (mips_fp_mult_cost (mode)
3604 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3605 + rtx_cost (XEXP (op0, 1), SET, speed)
3606 + rtx_cost (op1, SET, speed));
3609 if (GET_CODE (op1) == MULT)
3611 *total = (mips_fp_mult_cost (mode)
3612 + rtx_cost (op0, SET, speed)
3613 + rtx_cost (XEXP (op1, 0), SET, speed)
3614 + rtx_cost (XEXP (op1, 1), SET, speed));
3623 /* If this is part of a MADD or MSUB, treat the PLUS as
3626 && TARGET_FUSED_MADD
3627 && GET_CODE (XEXP (x, 0)) == MULT)
3630 *total = mips_cost->fp_add;
3634 /* Double-word operations require three single-word operations and
3635 an SLTU. The MIPS16 version then needs to move the result of
3636 the SLTU from $24 to a MIPS16 register. */
3637 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3638 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3643 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3644 && TARGET_FUSED_MADD
3645 && !HONOR_NANS (mode)
3646 && HONOR_SIGNED_ZEROS (mode))
3648 /* See if we can use NMADD or NMSUB. See mips.md for the
3649 associated patterns. */
3650 rtx op = XEXP (x, 0);
3651 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3652 && GET_CODE (XEXP (op, 0)) == MULT)
3654 *total = (mips_fp_mult_cost (mode)
3655 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3656 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3657 + rtx_cost (XEXP (op, 1), SET, speed));
3663 *total = mips_cost->fp_add;
3665 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3670 *total = mips_fp_mult_cost (mode);
3671 else if (mode == DImode && !TARGET_64BIT)
3672 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3673 where the mulsidi3 always includes an MFHI and an MFLO. */
3674 *total = (optimize_size
3675 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3676 : mips_cost->int_mult_si * 3 + 6);
3677 else if (optimize_size)
3678 *total = (ISA_HAS_MUL3 ? 1 : 2);
3679 else if (mode == DImode)
3680 *total = mips_cost->int_mult_di;
3682 *total = mips_cost->int_mult_si;
3686 /* Check for a reciprocal. */
3689 && flag_unsafe_math_optimizations
3690 && XEXP (x, 0) == CONST1_RTX (mode))
3692 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3693 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3694 division as being free. */
3695 *total = rtx_cost (XEXP (x, 1), SET, speed);
3697 *total = (mips_fp_div_cost (mode)
3698 + rtx_cost (XEXP (x, 1), SET, speed));
3707 *total = mips_fp_div_cost (mode);
3716 /* It is our responsibility to make division by a power of 2
3717 as cheap as 2 register additions if we want the division
3718 expanders to be used for such operations; see the setting
3719 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3720 should always produce shorter code than using
3721 expand_sdiv2_pow2. */
3723 && CONST_INT_P (XEXP (x, 1))
3724 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3726 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3729 *total = COSTS_N_INSNS (mips_idiv_insns ());
3731 else if (mode == DImode)
3732 *total = mips_cost->int_div_di;
3734 *total = mips_cost->int_div_si;
3738 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3742 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3746 case UNSIGNED_FLOAT:
3749 case FLOAT_TRUNCATE:
3750 *total = mips_cost->fp_add;
3758 /* Implement TARGET_ADDRESS_COST. */
3761 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3763 return mips_address_insns (addr, SImode, false);
3766 /* Return one word of double-word value OP, taking into account the fixed
3767 endianness of certain registers. HIGH_P is true to select the high part,
3768 false to select the low part. */
3771 mips_subword (rtx op, bool high_p)
3773 unsigned int byte, offset;
3774 enum machine_mode mode;
3776 mode = GET_MODE (op);
3777 if (mode == VOIDmode)
3778 mode = TARGET_64BIT ? TImode : DImode;
3780 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3781 byte = UNITS_PER_WORD;
3785 if (FP_REG_RTX_P (op))
3787 /* Paired FPRs are always ordered little-endian. */
3788 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3789 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3793 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3795 return simplify_gen_subreg (word_mode, op, mode, byte);
3798 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3801 mips_split_64bit_move_p (rtx dest, rtx src)
3806 /* FPR-to-FPR moves can be done in a single instruction, if they're
3808 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3811 /* Check for floating-point loads and stores. */
3812 if (ISA_HAS_LDC1_SDC1)
3814 if (FP_REG_RTX_P (dest) && MEM_P (src))
3816 if (FP_REG_RTX_P (src) && MEM_P (dest))
3822 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
3823 this function handles 64-bit moves for which mips_split_64bit_move_p
3824 holds. For 64-bit targets, this function handles 128-bit moves. */
3827 mips_split_doubleword_move (rtx dest, rtx src)
3831 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
3833 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
3834 emit_insn (gen_move_doubleword_fprdi (dest, src));
3835 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
3836 emit_insn (gen_move_doubleword_fprdf (dest, src));
3837 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
3838 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
3839 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
3840 emit_insn (gen_move_doubleword_fprv2si (dest, src));
3841 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
3842 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
3843 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
3844 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
3845 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
3846 emit_insn (gen_move_doubleword_fprtf (dest, src));
3850 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
3852 low_dest = mips_subword (dest, false);
3853 mips_emit_move (low_dest, mips_subword (src, false));
3855 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
3857 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
3859 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
3861 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
3863 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
3865 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
3869 /* The operation can be split into two normal moves. Decide in
3870 which order to do them. */
3871 low_dest = mips_subword (dest, false);
3872 if (REG_P (low_dest)
3873 && reg_overlap_mentioned_p (low_dest, src))
3875 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3876 mips_emit_move (low_dest, mips_subword (src, false));
3880 mips_emit_move (low_dest, mips_subword (src, false));
3881 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
3886 /* Return the appropriate instructions to move SRC into DEST. Assume
3887 that SRC is operand 1 and DEST is operand 0. */
3890 mips_output_move (rtx dest, rtx src)
3892 enum rtx_code dest_code, src_code;
3893 enum machine_mode mode;
3894 enum mips_symbol_type symbol_type;
3897 dest_code = GET_CODE (dest);
3898 src_code = GET_CODE (src);
3899 mode = GET_MODE (dest);
3900 dbl_p = (GET_MODE_SIZE (mode) == 8);
3902 if (dbl_p && mips_split_64bit_move_p (dest, src))
3905 if ((src_code == REG && GP_REG_P (REGNO (src)))
3906 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
3908 if (dest_code == REG)
3910 if (GP_REG_P (REGNO (dest)))
3911 return "move\t%0,%z1";
3913 /* Moves to HI are handled by special .md insns. */
3914 if (REGNO (dest) == LO_REGNUM)
3917 if (DSP_ACC_REG_P (REGNO (dest)))
3919 static char retval[] = "mt__\t%z1,%q0";
3921 retval[2] = reg_names[REGNO (dest)][4];
3922 retval[3] = reg_names[REGNO (dest)][5];
3926 if (FP_REG_P (REGNO (dest)))
3927 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
3929 if (ALL_COP_REG_P (REGNO (dest)))
3931 static char retval[] = "dmtc_\t%z1,%0";
3933 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
3934 return dbl_p ? retval : retval + 1;
3937 if (dest_code == MEM)
3938 switch (GET_MODE_SIZE (mode))
3940 case 1: return "sb\t%z1,%0";
3941 case 2: return "sh\t%z1,%0";
3942 case 4: return "sw\t%z1,%0";
3943 case 8: return "sd\t%z1,%0";
3946 if (dest_code == REG && GP_REG_P (REGNO (dest)))
3948 if (src_code == REG)
3950 /* Moves from HI are handled by special .md insns. */
3951 if (REGNO (src) == LO_REGNUM)
3953 /* When generating VR4120 or VR4130 code, we use MACC and
3954 DMACC instead of MFLO. This avoids both the normal
3955 MIPS III HI/LO hazards and the errata related to
3958 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
3962 if (DSP_ACC_REG_P (REGNO (src)))
3964 static char retval[] = "mf__\t%0,%q1";
3966 retval[2] = reg_names[REGNO (src)][4];
3967 retval[3] = reg_names[REGNO (src)][5];
3971 if (FP_REG_P (REGNO (src)))
3972 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
3974 if (ALL_COP_REG_P (REGNO (src)))
3976 static char retval[] = "dmfc_\t%0,%1";
3978 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3979 return dbl_p ? retval : retval + 1;
3982 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
3983 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
3986 if (src_code == MEM)
3987 switch (GET_MODE_SIZE (mode))
3989 case 1: return "lbu\t%0,%1";
3990 case 2: return "lhu\t%0,%1";
3991 case 4: return "lw\t%0,%1";
3992 case 8: return "ld\t%0,%1";
3995 if (src_code == CONST_INT)
3997 /* Don't use the X format for the operand itself, because that
3998 will give out-of-range numbers for 64-bit hosts and 32-bit
4001 return "li\t%0,%1\t\t\t# %X1";
4003 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4006 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4010 if (src_code == HIGH)
4011 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4013 if (CONST_GP_P (src))
4014 return "move\t%0,%1";
4016 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4017 && mips_lo_relocs[symbol_type] != 0)
4019 /* A signed 16-bit constant formed by applying a relocation
4020 operator to a symbolic address. */
4021 gcc_assert (!mips_split_p[symbol_type]);
4022 return "li\t%0,%R1";
4025 if (symbolic_operand (src, VOIDmode))
4027 gcc_assert (TARGET_MIPS16
4028 ? TARGET_MIPS16_TEXT_LOADS
4029 : !TARGET_EXPLICIT_RELOCS);
4030 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4033 if (src_code == REG && FP_REG_P (REGNO (src)))
4035 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4037 if (GET_MODE (dest) == V2SFmode)
4038 return "mov.ps\t%0,%1";
4040 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4043 if (dest_code == MEM)
4044 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4046 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4048 if (src_code == MEM)
4049 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4051 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4053 static char retval[] = "l_c_\t%0,%1";
4055 retval[1] = (dbl_p ? 'd' : 'w');
4056 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4059 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4061 static char retval[] = "s_c_\t%1,%0";
4063 retval[1] = (dbl_p ? 'd' : 'w');
4064 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4070 /* Return true if CMP1 is a suitable second operand for integer ordering
4071 test CODE. See also the *sCC patterns in mips.md. */
4074 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4080 return reg_or_0_operand (cmp1, VOIDmode);
4084 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4088 return arith_operand (cmp1, VOIDmode);
4091 return sle_operand (cmp1, VOIDmode);
4094 return sleu_operand (cmp1, VOIDmode);
4101 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4102 integer ordering test *CODE, or if an equivalent combination can
4103 be formed by adjusting *CODE and *CMP1. When returning true, update
4104 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4108 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4109 enum machine_mode mode)
4111 HOST_WIDE_INT plus_one;
4113 if (mips_int_order_operand_ok_p (*code, *cmp1))
4116 if (CONST_INT_P (*cmp1))
4120 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4121 if (INTVAL (*cmp1) < plus_one)
4124 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4130 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4134 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4145 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4146 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4147 is nonnull, it's OK to set TARGET to the inverse of the result and
4148 flip *INVERT_PTR instead. */
4151 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4152 rtx target, rtx cmp0, rtx cmp1)
4154 enum machine_mode mode;
4156 /* First see if there is a MIPS instruction that can do this operation.
4157 If not, try doing the same for the inverse operation. If that also
4158 fails, force CMP1 into a register and try again. */
4159 mode = GET_MODE (cmp0);
4160 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4161 mips_emit_binary (code, target, cmp0, cmp1);
4164 enum rtx_code inv_code = reverse_condition (code);
4165 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4167 cmp1 = force_reg (mode, cmp1);
4168 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4170 else if (invert_ptr == 0)
4174 inv_target = mips_force_binary (GET_MODE (target),
4175 inv_code, cmp0, cmp1);
4176 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4180 *invert_ptr = !*invert_ptr;
4181 mips_emit_binary (inv_code, target, cmp0, cmp1);
4186 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4187 The register will have the same mode as CMP0. */
4190 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4192 if (cmp1 == const0_rtx)
4195 if (uns_arith_operand (cmp1, VOIDmode))
4196 return expand_binop (GET_MODE (cmp0), xor_optab,
4197 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4199 return expand_binop (GET_MODE (cmp0), sub_optab,
4200 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4203 /* Convert *CODE into a code that can be used in a floating-point
4204 scc instruction (C.cond.fmt). Return true if the values of
4205 the condition code registers will be inverted, with 0 indicating
4206 that the condition holds. */
4209 mips_reversed_fp_cond (enum rtx_code *code)
4216 *code = reverse_condition_maybe_unordered (*code);
4224 /* Convert a comparison into something that can be used in a branch or
4225 conditional move. On entry, *OP0 and *OP1 are the values being
4226 compared and *CODE is the code used to compare them.
4228 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4229 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4230 otherwise any standard branch condition can be used. The standard branch
4233 - EQ or NE between two registers.
4234 - any comparison between a register and zero. */
4237 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4242 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4244 if (!need_eq_ne_p && *op1 == const0_rtx)
4246 else if (*code == EQ || *code == NE)
4250 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4254 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4258 /* The comparison needs a separate scc instruction. Store the
4259 result of the scc in *OP0 and compare it against zero. */
4260 bool invert = false;
4261 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4262 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4263 *code = (invert ? EQ : NE);
4267 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4269 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4270 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4276 enum rtx_code cmp_code;
4278 /* Floating-point tests use a separate C.cond.fmt comparison to
4279 set a condition code register. The branch or conditional move
4280 will then compare that register against zero.
4282 Set CMP_CODE to the code of the comparison instruction and
4283 *CODE to the code that the branch or move should use. */
4285 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4287 ? gen_reg_rtx (CCmode)
4288 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4290 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4294 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4295 and OPERAND[3]. Store the result in OPERANDS[0].
4297 On 64-bit targets, the mode of the comparison and target will always be
4298 SImode, thus possibly narrower than that of the comparison's operands. */
4301 mips_expand_scc (rtx operands[])
4303 rtx target = operands[0];
4304 enum rtx_code code = GET_CODE (operands[1]);
4305 rtx op0 = operands[2];
4306 rtx op1 = operands[3];
4308 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4310 if (code == EQ || code == NE)
4313 && reg_imm10_operand (op1, GET_MODE (op1)))
4314 mips_emit_binary (code, target, op0, op1);
4317 rtx zie = mips_zero_if_equal (op0, op1);
4318 mips_emit_binary (code, target, zie, const0_rtx);
4322 mips_emit_int_order_test (code, 0, target, op0, op1);
4325 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4326 CODE and jump to OPERANDS[3] if the condition holds. */
4329 mips_expand_conditional_branch (rtx *operands)
4331 enum rtx_code code = GET_CODE (operands[0]);
4332 rtx op0 = operands[1];
4333 rtx op1 = operands[2];
4336 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4337 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4338 emit_jump_insn (gen_condjump (condition, operands[3]));
4343 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4344 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4347 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4348 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4353 reversed_p = mips_reversed_fp_cond (&cond);
4354 cmp_result = gen_reg_rtx (CCV2mode);
4355 emit_insn (gen_scc_ps (cmp_result,
4356 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4358 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4361 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4365 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4366 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4369 mips_expand_conditional_move (rtx *operands)
4372 enum rtx_code code = GET_CODE (operands[1]);
4373 rtx op0 = XEXP (operands[1], 0);
4374 rtx op1 = XEXP (operands[1], 1);
4376 mips_emit_compare (&code, &op0, &op1, true);
4377 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4378 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4379 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4380 operands[2], operands[3])));
4383 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4386 mips_expand_conditional_trap (rtx comparison)
4389 enum machine_mode mode;
4392 /* MIPS conditional trap instructions don't have GT or LE flavors,
4393 so we must swap the operands and convert to LT and GE respectively. */
4394 code = GET_CODE (comparison);
4401 code = swap_condition (code);
4402 op0 = XEXP (comparison, 1);
4403 op1 = XEXP (comparison, 0);
4407 op0 = XEXP (comparison, 0);
4408 op1 = XEXP (comparison, 1);
4412 mode = GET_MODE (XEXP (comparison, 0));
4413 op0 = force_reg (mode, op0);
4414 if (!arith_operand (op1, mode))
4415 op1 = force_reg (mode, op1);
4417 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4418 gen_rtx_fmt_ee (code, mode, op0, op1),
4422 /* Initialize *CUM for a call to a function of type FNTYPE. */
4425 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4427 memset (cum, 0, sizeof (*cum));
4428 cum->prototype = (fntype && prototype_p (fntype));
4429 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4432 /* Fill INFO with information about a single argument. CUM is the
4433 cumulative state for earlier arguments. MODE is the mode of this
4434 argument and TYPE is its type (if known). NAMED is true if this
4435 is a named (fixed) argument rather than a variable one. */
4438 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4439 enum machine_mode mode, tree type, int named)
4441 bool doubleword_aligned_p;
4442 unsigned int num_bytes, num_words, max_regs;
4444 /* Work out the size of the argument. */
4445 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4446 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4448 /* Decide whether it should go in a floating-point register, assuming
4449 one is free. Later code checks for availability.
4451 The checks against UNITS_PER_FPVALUE handle the soft-float and
4452 single-float cases. */
4456 /* The EABI conventions have traditionally been defined in terms
4457 of TYPE_MODE, regardless of the actual type. */
4458 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4459 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4460 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4465 /* Only leading floating-point scalars are passed in
4466 floating-point registers. We also handle vector floats the same
4467 say, which is OK because they are not covered by the standard ABI. */
4468 info->fpr_p = (!cum->gp_reg_found
4469 && cum->arg_number < 2
4471 || SCALAR_FLOAT_TYPE_P (type)
4472 || VECTOR_FLOAT_TYPE_P (type))
4473 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4474 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4475 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4480 /* Scalar, complex and vector floating-point types are passed in
4481 floating-point registers, as long as this is a named rather
4482 than a variable argument. */
4483 info->fpr_p = (named
4484 && (type == 0 || FLOAT_TYPE_P (type))
4485 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4486 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4487 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4488 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4490 /* ??? According to the ABI documentation, the real and imaginary
4491 parts of complex floats should be passed in individual registers.
4492 The real and imaginary parts of stack arguments are supposed
4493 to be contiguous and there should be an extra word of padding
4496 This has two problems. First, it makes it impossible to use a
4497 single "void *" va_list type, since register and stack arguments
4498 are passed differently. (At the time of writing, MIPSpro cannot
4499 handle complex float varargs correctly.) Second, it's unclear
4500 what should happen when there is only one register free.
4502 For now, we assume that named complex floats should go into FPRs
4503 if there are two FPRs free, otherwise they should be passed in the
4504 same way as a struct containing two floats. */
4506 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4507 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4509 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4510 info->fpr_p = false;
4520 /* See whether the argument has doubleword alignment. */
4521 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4523 /* Set REG_OFFSET to the register count we're interested in.
4524 The EABI allocates the floating-point registers separately,
4525 but the other ABIs allocate them like integer registers. */
4526 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4530 /* Advance to an even register if the argument is doubleword-aligned. */
4531 if (doubleword_aligned_p)
4532 info->reg_offset += info->reg_offset & 1;
4534 /* Work out the offset of a stack argument. */
4535 info->stack_offset = cum->stack_words;
4536 if (doubleword_aligned_p)
4537 info->stack_offset += info->stack_offset & 1;
4539 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4541 /* Partition the argument between registers and stack. */
4542 info->reg_words = MIN (num_words, max_regs);
4543 info->stack_words = num_words - info->reg_words;
4546 /* INFO describes a register argument that has the normal format for the
4547 argument's mode. Return the register it uses, assuming that FPRs are
4548 available if HARD_FLOAT_P. */
4551 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4553 if (!info->fpr_p || !hard_float_p)
4554 return GP_ARG_FIRST + info->reg_offset;
4555 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4556 /* In o32, the second argument is always passed in $f14
4557 for TARGET_DOUBLE_FLOAT, regardless of whether the
4558 first argument was a word or doubleword. */
4559 return FP_ARG_FIRST + 2;
4561 return FP_ARG_FIRST + info->reg_offset;
4564 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4567 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4569 return !TARGET_OLDABI;
4572 /* Implement FUNCTION_ARG. */
4575 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4576 tree type, int named)
4578 struct mips_arg_info info;
4580 /* We will be called with a mode of VOIDmode after the last argument
4581 has been seen. Whatever we return will be passed to the call expander.
4582 If we need a MIPS16 fp_code, return a REG with the code stored as
4584 if (mode == VOIDmode)
4586 if (TARGET_MIPS16 && cum->fp_code != 0)
4587 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4592 mips_get_arg_info (&info, cum, mode, type, named);
4594 /* Return straight away if the whole argument is passed on the stack. */
4595 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4598 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4599 contains a double in its entirety, then that 64-bit chunk is passed
4600 in a floating-point register. */
4602 && TARGET_HARD_FLOAT
4605 && TREE_CODE (type) == RECORD_TYPE
4606 && TYPE_SIZE_UNIT (type)
4607 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4611 /* First check to see if there is any such field. */
4612 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4613 if (TREE_CODE (field) == FIELD_DECL
4614 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4615 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4616 && host_integerp (bit_position (field), 0)
4617 && int_bit_position (field) % BITS_PER_WORD == 0)
4622 /* Now handle the special case by returning a PARALLEL
4623 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4624 chunks are passed in registers. */
4626 HOST_WIDE_INT bitpos;
4629 /* assign_parms checks the mode of ENTRY_PARM, so we must
4630 use the actual mode here. */
4631 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4634 field = TYPE_FIELDS (type);
4635 for (i = 0; i < info.reg_words; i++)
4639 for (; field; field = TREE_CHAIN (field))
4640 if (TREE_CODE (field) == FIELD_DECL
4641 && int_bit_position (field) >= bitpos)
4645 && int_bit_position (field) == bitpos
4646 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4647 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4648 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4650 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4653 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4654 GEN_INT (bitpos / BITS_PER_UNIT));
4656 bitpos += BITS_PER_WORD;
4662 /* Handle the n32/n64 conventions for passing complex floating-point
4663 arguments in FPR pairs. The real part goes in the lower register
4664 and the imaginary part goes in the upper register. */
4667 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4670 enum machine_mode inner;
4673 inner = GET_MODE_INNER (mode);
4674 regno = FP_ARG_FIRST + info.reg_offset;
4675 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4677 /* Real part in registers, imaginary part on stack. */
4678 gcc_assert (info.stack_words == info.reg_words);
4679 return gen_rtx_REG (inner, regno);
4683 gcc_assert (info.stack_words == 0);
4684 real = gen_rtx_EXPR_LIST (VOIDmode,
4685 gen_rtx_REG (inner, regno),
4687 imag = gen_rtx_EXPR_LIST (VOIDmode,
4689 regno + info.reg_words / 2),
4690 GEN_INT (GET_MODE_SIZE (inner)));
4691 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4695 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4698 /* Implement FUNCTION_ARG_ADVANCE. */
4701 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4702 tree type, int named)
4704 struct mips_arg_info info;
4706 mips_get_arg_info (&info, cum, mode, type, named);
4709 cum->gp_reg_found = true;
4711 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4712 an explanation of what this code does. It assumes that we're using
4713 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4715 if (cum->arg_number < 2 && info.fpr_p)
4716 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4718 /* Advance the register count. This has the effect of setting
4719 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4720 argument required us to skip the final GPR and pass the whole
4721 argument on the stack. */
4722 if (mips_abi != ABI_EABI || !info.fpr_p)
4723 cum->num_gprs = info.reg_offset + info.reg_words;
4724 else if (info.reg_words > 0)
4725 cum->num_fprs += MAX_FPRS_PER_FMT;
4727 /* Advance the stack word count. */
4728 if (info.stack_words > 0)
4729 cum->stack_words = info.stack_offset + info.stack_words;
4734 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4737 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4738 enum machine_mode mode, tree type, bool named)
4740 struct mips_arg_info info;
4742 mips_get_arg_info (&info, cum, mode, type, named);
4743 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4746 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4747 PARM_BOUNDARY bits of alignment, but will be given anything up
4748 to STACK_BOUNDARY bits if the type requires it. */
4751 mips_function_arg_boundary (enum machine_mode mode, tree type)
4753 unsigned int alignment;
4755 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4756 if (alignment < PARM_BOUNDARY)
4757 alignment = PARM_BOUNDARY;
4758 if (alignment > STACK_BOUNDARY)
4759 alignment = STACK_BOUNDARY;
4763 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4764 upward rather than downward. In other words, return true if the
4765 first byte of the stack slot has useful data, false if the last
4769 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4771 /* On little-endian targets, the first byte of every stack argument
4772 is passed in the first byte of the stack slot. */
4773 if (!BYTES_BIG_ENDIAN)
4776 /* Otherwise, integral types are padded downward: the last byte of a
4777 stack argument is passed in the last byte of the stack slot. */
4779 ? (INTEGRAL_TYPE_P (type)
4780 || POINTER_TYPE_P (type)
4781 || FIXED_POINT_TYPE_P (type))
4782 : (SCALAR_INT_MODE_P (mode)
4783 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4786 /* Big-endian o64 pads floating-point arguments downward. */
4787 if (mips_abi == ABI_O64)
4788 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4791 /* Other types are padded upward for o32, o64, n32 and n64. */
4792 if (mips_abi != ABI_EABI)
4795 /* Arguments smaller than a stack slot are padded downward. */
4796 if (mode != BLKmode)
4797 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4799 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4802 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4803 if the least significant byte of the register has useful data. Return
4804 the opposite if the most significant byte does. */
4807 mips_pad_reg_upward (enum machine_mode mode, tree type)
4809 /* No shifting is required for floating-point arguments. */
4810 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4811 return !BYTES_BIG_ENDIAN;
4813 /* Otherwise, apply the same padding to register arguments as we do
4814 to stack arguments. */
4815 return mips_pad_arg_upward (mode, type);
4818 /* Return nonzero when an argument must be passed by reference. */
4821 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4822 enum machine_mode mode, const_tree type,
4823 bool named ATTRIBUTE_UNUSED)
4825 if (mips_abi == ABI_EABI)
4829 /* ??? How should SCmode be handled? */
4830 if (mode == DImode || mode == DFmode
4831 || mode == DQmode || mode == UDQmode
4832 || mode == DAmode || mode == UDAmode)
4835 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4836 return size == -1 || size > UNITS_PER_WORD;
4840 /* If we have a variable-sized parameter, we have no choice. */
4841 return targetm.calls.must_pass_in_stack (mode, type);
4845 /* Implement TARGET_CALLEE_COPIES. */
4848 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4849 enum machine_mode mode ATTRIBUTE_UNUSED,
4850 const_tree type ATTRIBUTE_UNUSED, bool named)
4852 return mips_abi == ABI_EABI && named;
4855 /* See whether VALTYPE is a record whose fields should be returned in
4856 floating-point registers. If so, return the number of fields and
4857 list them in FIELDS (which should have two elements). Return 0
4860 For n32 & n64, a structure with one or two fields is returned in
4861 floating-point registers as long as every field has a floating-point
4865 mips_fpr_return_fields (const_tree valtype, tree *fields)
4873 if (TREE_CODE (valtype) != RECORD_TYPE)
4877 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
4879 if (TREE_CODE (field) != FIELD_DECL)
4882 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
4888 fields[i++] = field;
4893 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
4894 a value in the most significant part of $2/$3 if:
4896 - the target is big-endian;
4898 - the value has a structure or union type (we generalize this to
4899 cover aggregates from other languages too); and
4901 - the structure is not returned in floating-point registers. */
4904 mips_return_in_msb (const_tree valtype)
4908 return (TARGET_NEWABI
4909 && TARGET_BIG_ENDIAN
4910 && AGGREGATE_TYPE_P (valtype)
4911 && mips_fpr_return_fields (valtype, fields) == 0);
4914 /* Return true if the function return value MODE will get returned in a
4915 floating-point register. */
4918 mips_return_mode_in_fpr_p (enum machine_mode mode)
4920 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
4921 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
4922 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4923 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
4926 /* Return the representation of an FPR return register when the
4927 value being returned in FP_RETURN has mode VALUE_MODE and the
4928 return type itself has mode TYPE_MODE. On NewABI targets,
4929 the two modes may be different for structures like:
4931 struct __attribute__((packed)) foo { float f; }
4933 where we return the SFmode value of "f" in FP_RETURN, but where
4934 the structure itself has mode BLKmode. */
4937 mips_return_fpr_single (enum machine_mode type_mode,
4938 enum machine_mode value_mode)
4942 x = gen_rtx_REG (value_mode, FP_RETURN);
4943 if (type_mode != value_mode)
4945 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
4946 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
4951 /* Return a composite value in a pair of floating-point registers.
4952 MODE1 and OFFSET1 are the mode and byte offset for the first value,
4953 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
4956 For n32 & n64, $f0 always holds the first value and $f2 the second.
4957 Otherwise the values are packed together as closely as possible. */
4960 mips_return_fpr_pair (enum machine_mode mode,
4961 enum machine_mode mode1, HOST_WIDE_INT offset1,
4962 enum machine_mode mode2, HOST_WIDE_INT offset2)
4966 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
4967 return gen_rtx_PARALLEL
4970 gen_rtx_EXPR_LIST (VOIDmode,
4971 gen_rtx_REG (mode1, FP_RETURN),
4973 gen_rtx_EXPR_LIST (VOIDmode,
4974 gen_rtx_REG (mode2, FP_RETURN + inc),
4975 GEN_INT (offset2))));
4979 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
4980 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
4981 VALTYPE is null and MODE is the mode of the return value. */
4984 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
4991 mode = TYPE_MODE (valtype);
4992 unsigned_p = TYPE_UNSIGNED (valtype);
4994 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
4995 return values, promote the mode here too. */
4996 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
4998 /* Handle structures whose fields are returned in $f0/$f2. */
4999 switch (mips_fpr_return_fields (valtype, fields))
5002 return mips_return_fpr_single (mode,
5003 TYPE_MODE (TREE_TYPE (fields[0])));
5006 return mips_return_fpr_pair (mode,
5007 TYPE_MODE (TREE_TYPE (fields[0])),
5008 int_byte_position (fields[0]),
5009 TYPE_MODE (TREE_TYPE (fields[1])),
5010 int_byte_position (fields[1]));
5013 /* If a value is passed in the most significant part of a register, see
5014 whether we have to round the mode up to a whole number of words. */
5015 if (mips_return_in_msb (valtype))
5017 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5018 if (size % UNITS_PER_WORD != 0)
5020 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5021 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5025 /* For EABI, the class of return register depends entirely on MODE.
5026 For example, "struct { some_type x; }" and "union { some_type x; }"
5027 are returned in the same way as a bare "some_type" would be.
5028 Other ABIs only use FPRs for scalar, complex or vector types. */
5029 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5030 return gen_rtx_REG (mode, GP_RETURN);
5035 /* Handle long doubles for n32 & n64. */
5037 return mips_return_fpr_pair (mode,
5039 DImode, GET_MODE_SIZE (mode) / 2);
5041 if (mips_return_mode_in_fpr_p (mode))
5043 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5044 return mips_return_fpr_pair (mode,
5045 GET_MODE_INNER (mode), 0,
5046 GET_MODE_INNER (mode),
5047 GET_MODE_SIZE (mode) / 2);
5049 return gen_rtx_REG (mode, FP_RETURN);
5053 return gen_rtx_REG (mode, GP_RETURN);
5056 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5057 all BLKmode objects are returned in memory. Under the n32, n64
5058 and embedded ABIs, small structures are returned in a register.
5059 Objects with varying size must still be returned in memory, of
5063 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5065 return (TARGET_OLDABI
5066 ? TYPE_MODE (type) == BLKmode
5067 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5070 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5073 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5074 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5077 CUMULATIVE_ARGS local_cum;
5078 int gp_saved, fp_saved;
5080 /* The caller has advanced CUM up to, but not beyond, the last named
5081 argument. Advance a local copy of CUM past the last "real" named
5082 argument, to find out how many registers are left over. */
5084 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5086 /* Found out how many registers we need to save. */
5087 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5088 fp_saved = (EABI_FLOAT_VARARGS_P
5089 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5098 ptr = plus_constant (virtual_incoming_args_rtx,
5099 REG_PARM_STACK_SPACE (cfun->decl)
5100 - gp_saved * UNITS_PER_WORD);
5101 mem = gen_frame_mem (BLKmode, ptr);
5102 set_mem_alias_set (mem, get_varargs_alias_set ());
5104 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5109 /* We can't use move_block_from_reg, because it will use
5111 enum machine_mode mode;
5114 /* Set OFF to the offset from virtual_incoming_args_rtx of
5115 the first float register. The FP save area lies below
5116 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5117 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5118 off -= fp_saved * UNITS_PER_FPREG;
5120 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5122 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5123 i += MAX_FPRS_PER_FMT)
5127 ptr = plus_constant (virtual_incoming_args_rtx, off);
5128 mem = gen_frame_mem (mode, ptr);
5129 set_mem_alias_set (mem, get_varargs_alias_set ());
5130 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5131 off += UNITS_PER_HWFPVALUE;
5135 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5136 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5137 + fp_saved * UNITS_PER_FPREG);
5140 /* Implement TARGET_BUILTIN_VA_LIST. */
5143 mips_build_builtin_va_list (void)
5145 if (EABI_FLOAT_VARARGS_P)
5147 /* We keep 3 pointers, and two offsets.
5149 Two pointers are to the overflow area, which starts at the CFA.
5150 One of these is constant, for addressing into the GPR save area
5151 below it. The other is advanced up the stack through the
5154 The third pointer is to the bottom of the GPR save area.
5155 Since the FPR save area is just below it, we can address
5156 FPR slots off this pointer.
5158 We also keep two one-byte offsets, which are to be subtracted
5159 from the constant pointers to yield addresses in the GPR and
5160 FPR save areas. These are downcounted as float or non-float
5161 arguments are used, and when they get to zero, the argument
5162 must be obtained from the overflow region. */
5163 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5166 record = lang_hooks.types.make_type (RECORD_TYPE);
5168 f_ovfl = build_decl (BUILTINS_LOCATION,
5169 FIELD_DECL, get_identifier ("__overflow_argptr"),
5171 f_gtop = build_decl (BUILTINS_LOCATION,
5172 FIELD_DECL, get_identifier ("__gpr_top"),
5174 f_ftop = build_decl (BUILTINS_LOCATION,
5175 FIELD_DECL, get_identifier ("__fpr_top"),
5177 f_goff = build_decl (BUILTINS_LOCATION,
5178 FIELD_DECL, get_identifier ("__gpr_offset"),
5179 unsigned_char_type_node);
5180 f_foff = build_decl (BUILTINS_LOCATION,
5181 FIELD_DECL, get_identifier ("__fpr_offset"),
5182 unsigned_char_type_node);
5183 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5184 warn on every user file. */
5185 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5186 array = build_array_type (unsigned_char_type_node,
5187 build_index_type (index));
5188 f_res = build_decl (BUILTINS_LOCATION,
5189 FIELD_DECL, get_identifier ("__reserved"), array);
5191 DECL_FIELD_CONTEXT (f_ovfl) = record;
5192 DECL_FIELD_CONTEXT (f_gtop) = record;
5193 DECL_FIELD_CONTEXT (f_ftop) = record;
5194 DECL_FIELD_CONTEXT (f_goff) = record;
5195 DECL_FIELD_CONTEXT (f_foff) = record;
5196 DECL_FIELD_CONTEXT (f_res) = record;
5198 TYPE_FIELDS (record) = f_ovfl;
5199 TREE_CHAIN (f_ovfl) = f_gtop;
5200 TREE_CHAIN (f_gtop) = f_ftop;
5201 TREE_CHAIN (f_ftop) = f_goff;
5202 TREE_CHAIN (f_goff) = f_foff;
5203 TREE_CHAIN (f_foff) = f_res;
5205 layout_type (record);
5208 else if (TARGET_IRIX && TARGET_IRIX6)
5209 /* On IRIX 6, this type is 'char *'. */
5210 return build_pointer_type (char_type_node);
5212 /* Otherwise, we use 'void *'. */
5213 return ptr_type_node;
5216 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5219 mips_va_start (tree valist, rtx nextarg)
5221 if (EABI_FLOAT_VARARGS_P)
5223 const CUMULATIVE_ARGS *cum;
5224 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5225 tree ovfl, gtop, ftop, goff, foff;
5227 int gpr_save_area_size;
5228 int fpr_save_area_size;
5231 cum = &crtl->args.info;
5233 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5235 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5237 f_ovfl = TYPE_FIELDS (va_list_type_node);
5238 f_gtop = TREE_CHAIN (f_ovfl);
5239 f_ftop = TREE_CHAIN (f_gtop);
5240 f_goff = TREE_CHAIN (f_ftop);
5241 f_foff = TREE_CHAIN (f_goff);
5243 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5245 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5247 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5249 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5251 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5254 /* Emit code to initialize OVFL, which points to the next varargs
5255 stack argument. CUM->STACK_WORDS gives the number of stack
5256 words used by named arguments. */
5257 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5258 if (cum->stack_words > 0)
5259 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5260 size_int (cum->stack_words * UNITS_PER_WORD));
5261 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5262 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5264 /* Emit code to initialize GTOP, the top of the GPR save area. */
5265 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5266 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5267 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5269 /* Emit code to initialize FTOP, the top of the FPR save area.
5270 This address is gpr_save_area_bytes below GTOP, rounded
5271 down to the next fp-aligned boundary. */
5272 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5273 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5274 fpr_offset &= -UNITS_PER_FPVALUE;
5276 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5277 size_int (-fpr_offset));
5278 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5279 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5281 /* Emit code to initialize GOFF, the offset from GTOP of the
5282 next GPR argument. */
5283 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5284 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5285 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5287 /* Likewise emit code to initialize FOFF, the offset from FTOP
5288 of the next FPR argument. */
5289 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5290 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5291 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5295 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5296 std_expand_builtin_va_start (valist, nextarg);
5300 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5303 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5309 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5311 type = build_pointer_type (type);
5313 if (!EABI_FLOAT_VARARGS_P)
5314 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5317 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5318 tree ovfl, top, off, align;
5319 HOST_WIDE_INT size, rsize, osize;
5322 f_ovfl = TYPE_FIELDS (va_list_type_node);
5323 f_gtop = TREE_CHAIN (f_ovfl);
5324 f_ftop = TREE_CHAIN (f_gtop);
5325 f_goff = TREE_CHAIN (f_ftop);
5326 f_foff = TREE_CHAIN (f_goff);
5330 TOP be the top of the GPR or FPR save area;
5331 OFF be the offset from TOP of the next register;
5332 ADDR_RTX be the address of the argument;
5333 SIZE be the number of bytes in the argument type;
5334 RSIZE be the number of bytes used to store the argument
5335 when it's in the register save area; and
5336 OSIZE be the number of bytes used to store it when it's
5337 in the stack overflow area.
5339 The code we want is:
5341 1: off &= -rsize; // round down
5344 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5349 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5350 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5354 [1] and [9] can sometimes be optimized away. */
5356 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5358 size = int_size_in_bytes (type);
5360 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5361 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5363 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5364 unshare_expr (valist), f_ftop, NULL_TREE);
5365 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5366 unshare_expr (valist), f_foff, NULL_TREE);
5368 /* When va_start saves FPR arguments to the stack, each slot
5369 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5370 argument's precision. */
5371 rsize = UNITS_PER_HWFPVALUE;
5373 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5374 (= PARM_BOUNDARY bits). This can be different from RSIZE
5377 (1) On 32-bit targets when TYPE is a structure such as:
5379 struct s { float f; };
5381 Such structures are passed in paired FPRs, so RSIZE
5382 will be 8 bytes. However, the structure only takes
5383 up 4 bytes of memory, so OSIZE will only be 4.
5385 (2) In combinations such as -mgp64 -msingle-float
5386 -fshort-double. Doubles passed in registers will then take
5387 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5388 stack take up UNITS_PER_WORD bytes. */
5389 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5393 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5394 unshare_expr (valist), f_gtop, NULL_TREE);
5395 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5396 unshare_expr (valist), f_goff, NULL_TREE);
5397 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5398 if (rsize > UNITS_PER_WORD)
5400 /* [1] Emit code for: off &= -rsize. */
5401 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5402 build_int_cst (TREE_TYPE (off), -rsize));
5403 gimplify_assign (unshare_expr (off), t, pre_p);
5408 /* [2] Emit code to branch if off == 0. */
5409 t = build2 (NE_EXPR, boolean_type_node, off,
5410 build_int_cst (TREE_TYPE (off), 0));
5411 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5413 /* [5] Emit code for: off -= rsize. We do this as a form of
5414 post-decrement not available to C. */
5415 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5416 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5418 /* [4] Emit code for:
5419 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5420 t = fold_convert (sizetype, t);
5421 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5422 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5423 if (BYTES_BIG_ENDIAN && rsize > size)
5425 u = size_int (rsize - size);
5426 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5428 COND_EXPR_THEN (addr) = t;
5430 if (osize > UNITS_PER_WORD)
5432 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5433 u = size_int (osize - 1);
5434 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5435 unshare_expr (ovfl), u);
5436 t = fold_convert (sizetype, t);
5437 u = size_int (-osize);
5438 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5439 t = fold_convert (TREE_TYPE (ovfl), t);
5440 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5441 unshare_expr (ovfl), t);
5446 /* [10, 11] Emit code for:
5447 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5449 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5450 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5451 if (BYTES_BIG_ENDIAN && osize > size)
5453 u = size_int (osize - size);
5454 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5457 /* String [9] and [10, 11] together. */
5459 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5460 COND_EXPR_ELSE (addr) = t;
5462 addr = fold_convert (build_pointer_type (type), addr);
5463 addr = build_va_arg_indirect_ref (addr);
5467 addr = build_va_arg_indirect_ref (addr);
5472 /* Start a definition of function NAME. MIPS16_P indicates whether the
5473 function contains MIPS16 code. */
5476 mips_start_function_definition (const char *name, bool mips16_p)
5479 fprintf (asm_out_file, "\t.set\tmips16\n");
5481 fprintf (asm_out_file, "\t.set\tnomips16\n");
5483 if (!flag_inhibit_size_directive)
5485 fputs ("\t.ent\t", asm_out_file);
5486 assemble_name (asm_out_file, name);
5487 fputs ("\n", asm_out_file);
5490 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5492 /* Start the definition proper. */
5493 assemble_name (asm_out_file, name);
5494 fputs (":\n", asm_out_file);
5497 /* End a function definition started by mips_start_function_definition. */
5500 mips_end_function_definition (const char *name)
5502 if (!flag_inhibit_size_directive)
5504 fputs ("\t.end\t", asm_out_file);
5505 assemble_name (asm_out_file, name);
5506 fputs ("\n", asm_out_file);
5510 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5513 mips_ok_for_lazy_binding_p (rtx x)
5515 return (TARGET_USE_GOT
5516 && GET_CODE (x) == SYMBOL_REF
5517 && !SYMBOL_REF_BIND_NOW_P (x)
5518 && !mips_symbol_binds_local_p (x));
5521 /* Load function address ADDR into register DEST. TYPE is as for
5522 mips_expand_call. Return true if we used an explicit lazy-binding
5526 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5528 /* If we're generating PIC, and this call is to a global function,
5529 try to allow its address to be resolved lazily. This isn't
5530 possible for sibcalls when $gp is call-saved because the value
5531 of $gp on entry to the stub would be our caller's gp, not ours. */
5532 if (TARGET_EXPLICIT_RELOCS
5533 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5534 && mips_ok_for_lazy_binding_p (addr))
5536 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5537 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5542 mips_emit_move (dest, addr);
5547 /* Each locally-defined hard-float MIPS16 function has a local symbol
5548 associated with it. This hash table maps the function symbol (FUNC)
5549 to the local symbol (LOCAL). */
5550 struct GTY(()) mips16_local_alias {
5554 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5556 /* Hash table callbacks for mips16_local_aliases. */
5559 mips16_local_aliases_hash (const void *entry)
5561 const struct mips16_local_alias *alias;
5563 alias = (const struct mips16_local_alias *) entry;
5564 return htab_hash_string (XSTR (alias->func, 0));
5568 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5570 const struct mips16_local_alias *alias1, *alias2;
5572 alias1 = (const struct mips16_local_alias *) entry1;
5573 alias2 = (const struct mips16_local_alias *) entry2;
5574 return rtx_equal_p (alias1->func, alias2->func);
5577 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5578 Return a local alias for it, creating a new one if necessary. */
5581 mips16_local_alias (rtx func)
5583 struct mips16_local_alias *alias, tmp_alias;
5586 /* Create the hash table if this is the first call. */
5587 if (mips16_local_aliases == NULL)
5588 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5589 mips16_local_aliases_eq, NULL);
5591 /* Look up the function symbol, creating a new entry if need be. */
5592 tmp_alias.func = func;
5593 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5594 gcc_assert (slot != NULL);
5596 alias = (struct mips16_local_alias *) *slot;
5599 const char *func_name, *local_name;
5602 /* Create a new SYMBOL_REF for the local symbol. The choice of
5603 __fn_local_* is based on the __fn_stub_* names that we've
5604 traditionally used for the non-MIPS16 stub. */
5605 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5606 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5607 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5608 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5610 /* Create a new structure to represent the mapping. */
5611 alias = GGC_NEW (struct mips16_local_alias);
5613 alias->local = local;
5616 return alias->local;
5619 /* A chained list of functions for which mips16_build_call_stub has already
5620 generated a stub. NAME is the name of the function and FP_RET_P is true
5621 if the function returns a value in floating-point registers. */
5622 struct mips16_stub {
5623 struct mips16_stub *next;
5627 static struct mips16_stub *mips16_stubs;
5629 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5632 mips16_stub_function (const char *name)
5636 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5637 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5641 /* Return the two-character string that identifies floating-point
5642 return mode MODE in the name of a MIPS16 function stub. */
5645 mips16_call_stub_mode_suffix (enum machine_mode mode)
5649 else if (mode == DFmode)
5651 else if (mode == SCmode)
5653 else if (mode == DCmode)
5655 else if (mode == V2SFmode)
5661 /* Write instructions to move a 32-bit value between general register
5662 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5663 from GPREG to FPREG and 'f' to move in the opposite direction. */
5666 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5668 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5669 reg_names[gpreg], reg_names[fpreg]);
5672 /* Likewise for 64-bit values. */
5675 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5678 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5679 reg_names[gpreg], reg_names[fpreg]);
5680 else if (TARGET_FLOAT64)
5682 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5683 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5684 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5685 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5689 /* Move the least-significant word. */
5690 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5691 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5692 /* ...then the most significant word. */
5693 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5694 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5698 /* Write out code to move floating-point arguments into or out of
5699 general registers. FP_CODE is the code describing which arguments
5700 are present (see the comment above the definition of CUMULATIVE_ARGS
5701 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5704 mips_output_args_xfer (int fp_code, char direction)
5706 unsigned int gparg, fparg, f;
5707 CUMULATIVE_ARGS cum;
5709 /* This code only works for o32 and o64. */
5710 gcc_assert (TARGET_OLDABI);
5712 mips_init_cumulative_args (&cum, NULL);
5714 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5716 enum machine_mode mode;
5717 struct mips_arg_info info;
5721 else if ((f & 3) == 2)
5726 mips_get_arg_info (&info, &cum, mode, NULL, true);
5727 gparg = mips_arg_regno (&info, false);
5728 fparg = mips_arg_regno (&info, true);
5731 mips_output_32bit_xfer (direction, gparg, fparg);
5733 mips_output_64bit_xfer (direction, gparg, fparg);
5735 mips_function_arg_advance (&cum, mode, NULL, true);
5739 /* Write a MIPS16 stub for the current function. This stub is used
5740 for functions which take arguments in the floating-point registers.
5741 It is normal-mode code that moves the floating-point arguments
5742 into the general registers and then jumps to the MIPS16 code. */
5745 mips16_build_function_stub (void)
5747 const char *fnname, *alias_name, *separator;
5748 char *secname, *stubname;
5753 /* Create the name of the stub, and its unique section. */
5754 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5755 alias = mips16_local_alias (symbol);
5757 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5758 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5759 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5760 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5762 /* Build a decl for the stub. */
5763 stubdecl = build_decl (BUILTINS_LOCATION,
5764 FUNCTION_DECL, get_identifier (stubname),
5765 build_function_type (void_type_node, NULL_TREE));
5766 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5767 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
5768 RESULT_DECL, NULL_TREE, void_type_node);
5770 /* Output a comment. */
5771 fprintf (asm_out_file, "\t# Stub function for %s (",
5772 current_function_name ());
5774 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5776 fprintf (asm_out_file, "%s%s", separator,
5777 (f & 3) == 1 ? "float" : "double");
5780 fprintf (asm_out_file, ")\n");
5782 /* Start the function definition. */
5783 assemble_start_function (stubdecl, stubname);
5784 mips_start_function_definition (stubname, false);
5786 /* If generating pic2 code, either set up the global pointer or
5788 if (TARGET_ABICALLS_PIC2)
5790 if (TARGET_ABSOLUTE_ABICALLS)
5791 fprintf (asm_out_file, "\t.option\tpic0\n");
5794 output_asm_insn ("%(.cpload\t%^%)", NULL);
5795 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5796 target function is. Use a local GOT access when loading the
5797 symbol, to cut down on the number of unnecessary GOT entries
5798 for stubs that aren't needed. */
5799 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5804 /* Load the address of the MIPS16 function into $25. Do this first so
5805 that targets with coprocessor interlocks can use an MFC1 to fill the
5807 output_asm_insn ("la\t%^,%0", &symbol);
5809 /* Move the arguments from floating-point registers to general registers. */
5810 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5812 /* Jump to the MIPS16 function. */
5813 output_asm_insn ("jr\t%^", NULL);
5815 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
5816 fprintf (asm_out_file, "\t.option\tpic2\n");
5818 mips_end_function_definition (stubname);
5820 /* If the linker needs to create a dynamic symbol for the target
5821 function, it will associate the symbol with the stub (which,
5822 unlike the target function, follows the proper calling conventions).
5823 It is therefore useful to have a local alias for the target function,
5824 so that it can still be identified as MIPS16 code. As an optimization,
5825 this symbol can also be used for indirect MIPS16 references from
5826 within this file. */
5827 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
5829 switch_to_section (function_section (current_function_decl));
5832 /* The current function is a MIPS16 function that returns a value in an FPR.
5833 Copy the return value from its soft-float to its hard-float location.
5834 libgcc2 has special non-MIPS16 helper functions for each case. */
5837 mips16_copy_fpr_return_value (void)
5839 rtx fn, insn, retval;
5841 enum machine_mode return_mode;
5844 return_type = DECL_RESULT (current_function_decl);
5845 return_mode = DECL_MODE (return_type);
5847 name = ACONCAT (("__mips16_ret_",
5848 mips16_call_stub_mode_suffix (return_mode),
5850 fn = mips16_stub_function (name);
5852 /* The function takes arguments in $2 (and possibly $3), so calls
5853 to it cannot be lazily bound. */
5854 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
5856 /* Model the call as something that takes the GPR return value as
5857 argument and returns an "updated" value. */
5858 retval = gen_rtx_REG (return_mode, GP_RETURN);
5859 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
5860 const0_rtx, NULL_RTX, false);
5861 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
5864 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
5865 RETVAL is the location of the return value, or null if this is
5866 a "call" rather than a "call_value". ARGS_SIZE is the size of the
5867 arguments and FP_CODE is the code built by mips_function_arg;
5868 see the comment above CUMULATIVE_ARGS for details.
5870 There are three alternatives:
5872 - If a stub was needed, emit the call and return the call insn itself.
5874 - If we can avoid using a stub by redirecting the call, set *FN_PTR
5875 to the new target and return null.
5877 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
5880 A stub is needed for calls to functions that, in normal mode,
5881 receive arguments in FPRs or return values in FPRs. The stub
5882 copies the arguments from their soft-float positions to their
5883 hard-float positions, calls the real function, then copies the
5884 return value from its hard-float position to its soft-float
5887 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
5888 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
5889 automatically redirects the JAL to the stub, otherwise the JAL
5890 continues to call FN directly. */
5893 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
5897 struct mips16_stub *l;
5900 /* We don't need to do anything if we aren't in MIPS16 mode, or if
5901 we were invoked with the -msoft-float option. */
5902 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
5905 /* Figure out whether the value might come back in a floating-point
5907 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
5909 /* We don't need to do anything if there were no floating-point
5910 arguments and the value will not be returned in a floating-point
5912 if (fp_code == 0 && !fp_ret_p)
5915 /* We don't need to do anything if this is a call to a special
5916 MIPS16 support function. */
5918 if (mips16_stub_function_p (fn))
5921 /* This code will only work for o32 and o64 abis. The other ABI's
5922 require more sophisticated support. */
5923 gcc_assert (TARGET_OLDABI);
5925 /* If we're calling via a function pointer, use one of the magic
5926 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
5927 Each stub expects the function address to arrive in register $2. */
5928 if (GET_CODE (fn) != SYMBOL_REF
5929 || !call_insn_operand (fn, VOIDmode))
5932 rtx stub_fn, insn, addr;
5935 /* If this is a locally-defined and locally-binding function,
5936 avoid the stub by calling the local alias directly. */
5937 if (mips16_local_function_p (fn))
5939 *fn_ptr = mips16_local_alias (fn);
5943 /* Create a SYMBOL_REF for the libgcc.a function. */
5945 sprintf (buf, "__mips16_call_stub_%s_%d",
5946 mips16_call_stub_mode_suffix (GET_MODE (retval)),
5949 sprintf (buf, "__mips16_call_stub_%d", fp_code);
5950 stub_fn = mips16_stub_function (buf);
5952 /* The function uses $2 as an argument, so calls to it
5953 cannot be lazily bound. */
5954 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
5956 /* Load the target function into $2. */
5957 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
5958 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
5960 /* Emit the call. */
5961 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
5962 args_size, NULL_RTX, lazy_p);
5964 /* Tell GCC that this call does indeed use the value of $2. */
5965 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
5967 /* If we are handling a floating-point return value, we need to
5968 save $18 in the function prologue. Putting a note on the
5969 call will mean that df_regs_ever_live_p ($18) will be true if the
5970 call is not eliminated, and we can check that in the prologue
5973 CALL_INSN_FUNCTION_USAGE (insn) =
5974 gen_rtx_EXPR_LIST (VOIDmode,
5975 gen_rtx_CLOBBER (VOIDmode,
5976 gen_rtx_REG (word_mode, 18)),
5977 CALL_INSN_FUNCTION_USAGE (insn));
5982 /* We know the function we are going to call. If we have already
5983 built a stub, we don't need to do anything further. */
5984 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
5985 for (l = mips16_stubs; l != NULL; l = l->next)
5986 if (strcmp (l->name, fnname) == 0)
5991 const char *separator;
5992 char *secname, *stubname;
5993 tree stubid, stubdecl;
5996 /* If the function does not return in FPRs, the special stub
6000 If the function does return in FPRs, the stub section is named
6001 .mips16.call.fp.FNNAME
6003 Build a decl for the stub. */
6004 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6006 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6008 stubid = get_identifier (stubname);
6009 stubdecl = build_decl (BUILTINS_LOCATION,
6010 FUNCTION_DECL, stubid,
6011 build_function_type (void_type_node, NULL_TREE));
6012 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6013 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6014 RESULT_DECL, NULL_TREE,
6017 /* Output a comment. */
6018 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6020 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6024 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6026 fprintf (asm_out_file, "%s%s", separator,
6027 (f & 3) == 1 ? "float" : "double");
6030 fprintf (asm_out_file, ")\n");
6032 /* Start the function definition. */
6033 assemble_start_function (stubdecl, stubname);
6034 mips_start_function_definition (stubname, false);
6038 /* Load the address of the MIPS16 function into $25. Do this
6039 first so that targets with coprocessor interlocks can use
6040 an MFC1 to fill the delay slot. */
6041 if (TARGET_EXPLICIT_RELOCS)
6043 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6044 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6047 output_asm_insn ("la\t%^,%0", &fn);
6050 /* Move the arguments from general registers to floating-point
6052 mips_output_args_xfer (fp_code, 't');
6056 /* Jump to the previously-loaded address. */
6057 output_asm_insn ("jr\t%^", NULL);
6061 /* Save the return address in $18 and call the non-MIPS16 function.
6062 The stub's caller knows that $18 might be clobbered, even though
6063 $18 is usually a call-saved register. */
6064 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6065 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
6066 output_asm_insn (MIPS_CALL ("jal", &fn, 0), &fn);
6068 /* Move the result from floating-point registers to
6069 general registers. */
6070 switch (GET_MODE (retval))
6073 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6074 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6077 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6078 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6080 /* On 64-bit targets, complex floats are returned in
6081 a single GPR, such that "sd" on a suitably-aligned
6082 target would store the value correctly. */
6083 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6084 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6085 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6086 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6087 reg_names[GP_RETURN],
6088 reg_names[GP_RETURN],
6089 reg_names[GP_RETURN + 1]);
6094 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6095 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6099 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6105 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6108 #ifdef ASM_DECLARE_FUNCTION_SIZE
6109 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6112 mips_end_function_definition (stubname);
6114 /* Record this stub. */
6115 l = XNEW (struct mips16_stub);
6116 l->name = xstrdup (fnname);
6117 l->fp_ret_p = fp_ret_p;
6118 l->next = mips16_stubs;
6122 /* If we expect a floating-point return value, but we've built a
6123 stub which does not expect one, then we're in trouble. We can't
6124 use the existing stub, because it won't handle the floating-point
6125 value. We can't build a new stub, because the linker won't know
6126 which stub to use for the various calls in this object file.
6127 Fortunately, this case is illegal, since it means that a function
6128 was declared in two different ways in a single compilation. */
6129 if (fp_ret_p && !l->fp_ret_p)
6130 error ("cannot handle inconsistent calls to %qs", fnname);
6132 if (retval == NULL_RTX)
6133 insn = gen_call_internal_direct (fn, args_size);
6135 insn = gen_call_value_internal_direct (retval, fn, args_size);
6136 insn = mips_emit_call_insn (insn, fn, fn, false);
6138 /* If we are calling a stub which handles a floating-point return
6139 value, we need to arrange to save $18 in the prologue. We do this
6140 by marking the function call as using the register. The prologue
6141 will later see that it is used, and emit code to save it. */
6143 CALL_INSN_FUNCTION_USAGE (insn) =
6144 gen_rtx_EXPR_LIST (VOIDmode,
6145 gen_rtx_CLOBBER (VOIDmode,
6146 gen_rtx_REG (word_mode, 18)),
6147 CALL_INSN_FUNCTION_USAGE (insn));
6152 /* Expand a call of type TYPE. RESULT is where the result will go (null
6153 for "call"s and "sibcall"s), ADDR is the address of the function,
6154 ARGS_SIZE is the size of the arguments and AUX is the value passed
6155 to us by mips_function_arg. LAZY_P is true if this call already
6156 involves a lazily-bound function address (such as when calling
6157 functions through a MIPS16 hard-float stub).
6159 Return the call itself. */
6162 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6163 rtx args_size, rtx aux, bool lazy_p)
6165 rtx orig_addr, pattern, insn;
6168 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6169 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6172 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6177 if (!call_insn_operand (addr, VOIDmode))
6179 if (type == MIPS_CALL_EPILOGUE)
6180 addr = MIPS_EPILOGUE_TEMP (Pmode);
6182 addr = gen_reg_rtx (Pmode);
6183 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6188 rtx (*fn) (rtx, rtx);
6190 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6191 fn = gen_call_split;
6192 else if (type == MIPS_CALL_SIBCALL)
6193 fn = gen_sibcall_internal;
6195 fn = gen_call_internal;
6197 pattern = fn (addr, args_size);
6199 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6201 /* Handle return values created by mips_return_fpr_pair. */
6202 rtx (*fn) (rtx, rtx, rtx, rtx);
6205 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6206 fn = gen_call_value_multiple_split;
6207 else if (type == MIPS_CALL_SIBCALL)
6208 fn = gen_sibcall_value_multiple_internal;
6210 fn = gen_call_value_multiple_internal;
6212 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6213 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6214 pattern = fn (reg1, addr, args_size, reg2);
6218 rtx (*fn) (rtx, rtx, rtx);
6220 if (type == MIPS_CALL_EPILOGUE && TARGET_SPLIT_CALLS)
6221 fn = gen_call_value_split;
6222 else if (type == MIPS_CALL_SIBCALL)
6223 fn = gen_sibcall_value_internal;
6225 fn = gen_call_value_internal;
6227 /* Handle return values created by mips_return_fpr_single. */
6228 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6229 result = XEXP (XVECEXP (result, 0, 0), 0);
6230 pattern = fn (result, addr, args_size);
6233 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6236 /* Split call instruction INSN into a $gp-clobbering call and
6237 (where necessary) an instruction to restore $gp from its save slot.
6238 CALL_PATTERN is the pattern of the new call. */
6241 mips_split_call (rtx insn, rtx call_pattern)
6245 new_insn = emit_call_insn (call_pattern);
6246 CALL_INSN_FUNCTION_USAGE (new_insn)
6247 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6248 if (!find_reg_note (insn, REG_NORETURN, 0))
6249 /* Pick a temporary register that is suitable for both MIPS16 and
6250 non-MIPS16 code. $4 and $5 are used for returning complex double
6251 values in soft-float code, so $6 is the first suitable candidate. */
6252 mips_restore_gp (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6255 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6258 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6260 if (!TARGET_SIBCALLS)
6263 /* Interrupt handlers need special epilogue code and therefore can't
6265 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6268 /* We can't do a sibcall if the called function is a MIPS16 function
6269 because there is no direct "jx" instruction equivalent to "jalx" to
6270 switch the ISA mode. We only care about cases where the sibling
6271 and normal calls would both be direct. */
6273 && mips_use_mips16_mode_p (decl)
6274 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6277 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6278 functions could be MIPS16 ones unless an attribute explicitly tells
6280 if (TARGET_INTERLINK_MIPS16
6282 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6283 && !mips_nomips16_decl_p (decl)
6284 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6291 /* Emit code to move general operand SRC into condition-code
6292 register DEST given that SCRATCH is a scratch TFmode FPR.
6299 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6302 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6306 /* Change the source to SFmode. */
6308 src = adjust_address (src, SFmode, 0);
6309 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6310 src = gen_rtx_REG (SFmode, true_regnum (src));
6312 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6313 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6315 mips_emit_move (copy_rtx (fp1), src);
6316 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6317 emit_insn (gen_slt_sf (dest, fp2, fp1));
6320 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6321 Assume that the areas do not overlap. */
6324 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6326 HOST_WIDE_INT offset, delta;
6327 unsigned HOST_WIDE_INT bits;
6329 enum machine_mode mode;
6332 /* Work out how many bits to move at a time. If both operands have
6333 half-word alignment, it is usually better to move in half words.
6334 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6335 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6336 Otherwise move word-sized chunks. */
6337 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6338 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6339 bits = BITS_PER_WORD / 2;
6341 bits = BITS_PER_WORD;
6343 mode = mode_for_size (bits, MODE_INT, 0);
6344 delta = bits / BITS_PER_UNIT;
6346 /* Allocate a buffer for the temporary registers. */
6347 regs = XALLOCAVEC (rtx, length / delta);
6349 /* Load as many BITS-sized chunks as possible. Use a normal load if
6350 the source has enough alignment, otherwise use left/right pairs. */
6351 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6353 regs[i] = gen_reg_rtx (mode);
6354 if (MEM_ALIGN (src) >= bits)
6355 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6358 rtx part = adjust_address (src, BLKmode, offset);
6359 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6364 /* Copy the chunks to the destination. */
6365 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6366 if (MEM_ALIGN (dest) >= bits)
6367 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6370 rtx part = adjust_address (dest, BLKmode, offset);
6371 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6375 /* Mop up any left-over bytes. */
6376 if (offset < length)
6378 src = adjust_address (src, BLKmode, offset);
6379 dest = adjust_address (dest, BLKmode, offset);
6380 move_by_pieces (dest, src, length - offset,
6381 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6385 /* Helper function for doing a loop-based block operation on memory
6386 reference MEM. Each iteration of the loop will operate on LENGTH
6389 Create a new base register for use within the loop and point it to
6390 the start of MEM. Create a new memory reference that uses this
6391 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6394 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6395 rtx *loop_reg, rtx *loop_mem)
6397 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6399 /* Although the new mem does not refer to a known location,
6400 it does keep up to LENGTH bytes of alignment. */
6401 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6402 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6405 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6406 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6407 the memory regions do not overlap. */
6410 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6411 HOST_WIDE_INT bytes_per_iter)
6413 rtx label, src_reg, dest_reg, final_src, test;
6414 HOST_WIDE_INT leftover;
6416 leftover = length % bytes_per_iter;
6419 /* Create registers and memory references for use within the loop. */
6420 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6421 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6423 /* Calculate the value that SRC_REG should have after the last iteration
6425 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6428 /* Emit the start of the loop. */
6429 label = gen_label_rtx ();
6432 /* Emit the loop body. */
6433 mips_block_move_straight (dest, src, bytes_per_iter);
6435 /* Move on to the next block. */
6436 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6437 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6439 /* Emit the loop condition. */
6440 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6441 if (Pmode == DImode)
6442 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6444 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6446 /* Mop up any left-over bytes. */
6448 mips_block_move_straight (dest, src, leftover);
6451 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6452 memory reference SRC to memory reference DEST. */
6455 mips_expand_block_move (rtx dest, rtx src, rtx length)
6457 if (CONST_INT_P (length))
6459 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6461 mips_block_move_straight (dest, src, INTVAL (length));
6466 mips_block_move_loop (dest, src, INTVAL (length),
6467 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6474 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6477 mips_expand_synci_loop (rtx begin, rtx end)
6479 rtx inc, label, cmp, cmp_result;
6481 /* Load INC with the cache line size (rdhwr INC,$1). */
6482 inc = gen_reg_rtx (Pmode);
6483 emit_insn (Pmode == SImode
6484 ? gen_rdhwr_synci_step_si (inc)
6485 : gen_rdhwr_synci_step_di (inc));
6487 /* Loop back to here. */
6488 label = gen_label_rtx ();
6491 emit_insn (gen_synci (begin));
6493 cmp = mips_force_binary (Pmode, GTU, begin, end);
6495 mips_emit_binary (PLUS, begin, begin, inc);
6497 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6498 emit_jump_insn (gen_condjump (cmp_result, label));
6501 /* Expand a QI or HI mode atomic memory operation.
6503 GENERATOR contains a pointer to the gen_* function that generates
6504 the SI mode underlying atomic operation using masks that we
6507 RESULT is the return register for the operation. Its value is NULL
6510 MEM is the location of the atomic access.
6512 OLDVAL is the first operand for the operation.
6514 NEWVAL is the optional second operand for the operation. Its value
6515 is NULL if unused. */
6518 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6519 rtx result, rtx mem, rtx oldval, rtx newval)
6521 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6522 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6524 enum machine_mode mode;
6526 mode = GET_MODE (mem);
6528 /* Compute the address of the containing SImode value. */
6529 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6530 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6531 force_reg (Pmode, GEN_INT (-4)));
6533 /* Create a memory reference for it. */
6534 memsi = gen_rtx_MEM (SImode, memsi_addr);
6535 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6536 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6538 /* Work out the byte offset of the QImode or HImode value,
6539 counting from the least significant byte. */
6540 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6541 if (TARGET_BIG_ENDIAN)
6542 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6544 /* Multiply by eight to convert the shift value from bytes to bits. */
6545 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6547 /* Make the final shift an SImode value, so that it can be used in
6548 SImode operations. */
6549 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6551 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6552 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6553 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6554 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6556 /* Compute the equivalent exclusive mask. */
6557 inverted_mask = gen_reg_rtx (SImode);
6558 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6559 gen_rtx_NOT (SImode, mask)));
6561 /* Shift the old value into place. */
6562 if (oldval != const0_rtx)
6564 oldval = convert_modes (SImode, mode, oldval, true);
6565 oldval = force_reg (SImode, oldval);
6566 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6569 /* Do the same for the new value. */
6570 if (newval && newval != const0_rtx)
6572 newval = convert_modes (SImode, mode, newval, true);
6573 newval = force_reg (SImode, newval);
6574 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6577 /* Do the SImode atomic access. */
6579 res = gen_reg_rtx (SImode);
6581 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6583 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6585 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6591 /* Shift and convert the result. */
6592 mips_emit_binary (AND, res, res, mask);
6593 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6594 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6598 /* Return true if it is possible to use left/right accesses for a
6599 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6600 returning true, update *OP, *LEFT and *RIGHT as follows:
6602 *OP is a BLKmode reference to the whole field.
6604 *LEFT is a QImode reference to the first byte if big endian or
6605 the last byte if little endian. This address can be used in the
6606 left-side instructions (LWL, SWL, LDL, SDL).
6608 *RIGHT is a QImode reference to the opposite end of the field and
6609 can be used in the patterning right-side instruction. */
6612 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6613 rtx *left, rtx *right)
6617 /* Check that the operand really is a MEM. Not all the extv and
6618 extzv predicates are checked. */
6622 /* Check that the size is valid. */
6623 if (width != 32 && (!TARGET_64BIT || width != 64))
6626 /* We can only access byte-aligned values. Since we are always passed
6627 a reference to the first byte of the field, it is not necessary to
6628 do anything with BITPOS after this check. */
6629 if (bitpos % BITS_PER_UNIT != 0)
6632 /* Reject aligned bitfields: we want to use a normal load or store
6633 instead of a left/right pair. */
6634 if (MEM_ALIGN (*op) >= width)
6637 /* Adjust *OP to refer to the whole field. This also has the effect
6638 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6639 *op = adjust_address (*op, BLKmode, 0);
6640 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6642 /* Get references to both ends of the field. We deliberately don't
6643 use the original QImode *OP for FIRST since the new BLKmode one
6644 might have a simpler address. */
6645 first = adjust_address (*op, QImode, 0);
6646 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6648 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6649 correspond to the MSB and RIGHT to the LSB. */
6650 if (TARGET_BIG_ENDIAN)
6651 *left = first, *right = last;
6653 *left = last, *right = first;
6658 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6659 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6660 the operation is the equivalent of:
6662 (set DEST (*_extract SRC WIDTH BITPOS))
6664 Return true on success. */
6667 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6668 HOST_WIDE_INT bitpos)
6670 rtx left, right, temp;
6672 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6673 be a paradoxical word_mode subreg. This is the only case in which
6674 we allow the destination to be larger than the source. */
6675 if (GET_CODE (dest) == SUBREG
6676 && GET_MODE (dest) == DImode
6677 && GET_MODE (SUBREG_REG (dest)) == SImode)
6678 dest = SUBREG_REG (dest);
6680 /* After the above adjustment, the destination must be the same
6681 width as the source. */
6682 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6685 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6688 temp = gen_reg_rtx (GET_MODE (dest));
6689 if (GET_MODE (dest) == DImode)
6691 emit_insn (gen_mov_ldl (temp, src, left));
6692 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6696 emit_insn (gen_mov_lwl (temp, src, left));
6697 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6702 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6703 BITPOS and SRC are the operands passed to the expander; the operation
6704 is the equivalent of:
6706 (set (zero_extract DEST WIDTH BITPOS) SRC)
6708 Return true on success. */
6711 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6712 HOST_WIDE_INT bitpos)
6715 enum machine_mode mode;
6717 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6720 mode = mode_for_size (width, MODE_INT, 0);
6721 src = gen_lowpart (mode, src);
6724 emit_insn (gen_mov_sdl (dest, src, left));
6725 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6729 emit_insn (gen_mov_swl (dest, src, left));
6730 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6735 /* Return true if X is a MEM with the same size as MODE. */
6738 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6745 size = MEM_SIZE (x);
6746 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6749 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6750 source of an "ext" instruction or the destination of an "ins"
6751 instruction. OP must be a register operand and the following
6752 conditions must hold:
6754 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6755 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6756 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6758 Also reject lengths equal to a word as they are better handled
6759 by the move patterns. */
6762 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6764 if (!ISA_HAS_EXT_INS
6765 || !register_operand (op, VOIDmode)
6766 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6769 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6772 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6778 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6779 operation if MAXLEN is the maxium length of consecutive bits that
6780 can make up MASK. MODE is the mode of the operation. See
6781 mask_low_and_shift_len for the actual definition. */
6784 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6786 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
6789 /* The canonical form of a mask-low-and-shift-left operation is
6790 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6791 cleared. Thus we need to shift MASK to the right before checking if it
6792 is a valid mask value. MODE is the mode of the operation. If true
6793 return the length of the mask, otherwise return -1. */
6796 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
6798 HOST_WIDE_INT shval;
6800 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
6801 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
6804 /* Return true if -msplit-addresses is selected and should be honored.
6806 -msplit-addresses is a half-way house between explicit relocations
6807 and the traditional assembler macros. It can split absolute 32-bit
6808 symbolic constants into a high/lo_sum pair but uses macros for other
6811 Like explicit relocation support for REL targets, it relies
6812 on GNU extensions in the assembler and the linker.
6814 Although this code should work for -O0, it has traditionally
6815 been treated as an optimization. */
6818 mips_split_addresses_p (void)
6820 return (TARGET_SPLIT_ADDRESSES
6824 && !ABI_HAS_64BIT_SYMBOLS);
6827 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
6830 mips_init_relocs (void)
6832 memset (mips_split_p, '\0', sizeof (mips_split_p));
6833 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
6834 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
6835 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
6837 if (ABI_HAS_64BIT_SYMBOLS)
6839 if (TARGET_EXPLICIT_RELOCS)
6841 mips_split_p[SYMBOL_64_HIGH] = true;
6842 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
6843 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
6845 mips_split_p[SYMBOL_64_MID] = true;
6846 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
6847 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
6849 mips_split_p[SYMBOL_64_LOW] = true;
6850 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
6851 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
6853 mips_split_p[SYMBOL_ABSOLUTE] = true;
6854 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6859 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
6861 mips_split_p[SYMBOL_ABSOLUTE] = true;
6862 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
6863 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
6865 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
6871 /* The high part is provided by a pseudo copy of $gp. */
6872 mips_split_p[SYMBOL_GP_RELATIVE] = true;
6873 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
6875 else if (TARGET_EXPLICIT_RELOCS)
6876 /* Small data constants are kept whole until after reload,
6877 then lowered by mips_rewrite_small_data. */
6878 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
6880 if (TARGET_EXPLICIT_RELOCS)
6882 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
6885 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
6886 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
6890 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
6891 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
6894 /* Expose the use of $28 as soon as possible. */
6895 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
6899 /* The HIGH and LO_SUM are matched by special .md patterns. */
6900 mips_split_p[SYMBOL_GOT_DISP] = true;
6902 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
6903 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
6904 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
6906 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
6907 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
6908 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
6913 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
6915 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
6916 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
6918 /* Expose the use of $28 as soon as possible. */
6919 mips_split_p[SYMBOL_GOT_DISP] = true;
6925 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
6926 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
6927 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
6930 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
6931 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
6933 mips_split_p[SYMBOL_DTPREL] = true;
6934 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
6935 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
6937 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
6939 mips_split_p[SYMBOL_TPREL] = true;
6940 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
6941 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
6943 mips_lo_relocs[SYMBOL_HALF] = "%half(";
6946 /* If OP is an UNSPEC address, return the address to which it refers,
6947 otherwise return OP itself. */
6950 mips_strip_unspec_address (rtx op)
6954 split_const (op, &base, &offset);
6955 if (UNSPEC_ADDRESS_P (base))
6956 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
6960 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6961 in context CONTEXT. RELOCS is the array of relocations to use. */
6964 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
6965 const char **relocs)
6967 enum mips_symbol_type symbol_type;
6970 symbol_type = mips_classify_symbolic_expression (op, context);
6971 gcc_assert (relocs[symbol_type]);
6973 fputs (relocs[symbol_type], file);
6974 output_addr_const (file, mips_strip_unspec_address (op));
6975 for (p = relocs[symbol_type]; *p != 0; p++)
6980 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
6981 The punctuation characters are:
6983 '(' Start a nested ".set noreorder" block.
6984 ')' End a nested ".set noreorder" block.
6985 '[' Start a nested ".set noat" block.
6986 ']' End a nested ".set noat" block.
6987 '<' Start a nested ".set nomacro" block.
6988 '>' End a nested ".set nomacro" block.
6989 '*' Behave like %(%< if generating a delayed-branch sequence.
6990 '#' Print a nop if in a ".set noreorder" block.
6991 '/' Like '#', but do nothing within a delayed-branch sequence.
6992 '?' Print "l" if mips_branch_likely is true
6993 '~' Print a nop if mips_branch_likely is true
6994 '.' Print the name of the register with a hard-wired zero (zero or $0).
6995 '@' Print the name of the assembler temporary register (at or $1).
6996 '^' Print the name of the pic call-through register (t9 or $25).
6997 '+' Print the name of the gp register (usually gp or $28).
6998 '$' Print the name of the stack pointer register (sp or $29).
6999 '|' Print ".set push; .set mips2" if !ISA_HAS_LL_SC.
7000 '-' Print ".set pop" under the same conditions for '|'.
7002 See also mips_init_print_operand_pucnt. */
7005 mips_print_operand_punctuation (FILE *file, int ch)
7010 if (set_noreorder++ == 0)
7011 fputs (".set\tnoreorder\n\t", file);
7015 gcc_assert (set_noreorder > 0);
7016 if (--set_noreorder == 0)
7017 fputs ("\n\t.set\treorder", file);
7021 if (set_noat++ == 0)
7022 fputs (".set\tnoat\n\t", file);
7026 gcc_assert (set_noat > 0);
7027 if (--set_noat == 0)
7028 fputs ("\n\t.set\tat", file);
7032 if (set_nomacro++ == 0)
7033 fputs (".set\tnomacro\n\t", file);
7037 gcc_assert (set_nomacro > 0);
7038 if (--set_nomacro == 0)
7039 fputs ("\n\t.set\tmacro", file);
7043 if (final_sequence != 0)
7045 mips_print_operand_punctuation (file, '(');
7046 mips_print_operand_punctuation (file, '<');
7051 if (set_noreorder != 0)
7052 fputs ("\n\tnop", file);
7056 /* Print an extra newline so that the delayed insn is separated
7057 from the following ones. This looks neater and is consistent
7058 with non-nop delayed sequences. */
7059 if (set_noreorder != 0 && final_sequence == 0)
7060 fputs ("\n\tnop\n", file);
7064 if (mips_branch_likely)
7069 if (mips_branch_likely)
7070 fputs ("\n\tnop", file);
7074 fputs (reg_names[GP_REG_FIRST + 0], file);
7078 fputs (reg_names[GP_REG_FIRST + 1], file);
7082 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7086 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7090 fputs (reg_names[STACK_POINTER_REGNUM], file);
7095 fputs (".set\tpush\n\t.set\tmips2\n\t", file);
7100 fputs ("\n\t.set\tpop", file);
7109 /* Initialize mips_print_operand_punct. */
7112 mips_init_print_operand_punct (void)
7116 for (p = "()[]<>*#/?~.@^+$|-"; *p; p++)
7117 mips_print_operand_punct[(unsigned char) *p] = true;
7120 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7121 associated with condition CODE. Print the condition part of the
7125 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7139 /* Conveniently, the MIPS names for these conditions are the same
7140 as their RTL equivalents. */
7141 fputs (GET_RTX_NAME (code), file);
7145 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7150 /* Likewise floating-point branches. */
7153 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7158 fputs ("c1f", file);
7162 fputs ("c1t", file);
7166 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7171 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7173 'X' Print CONST_INT OP in hexadecimal format.
7174 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7175 'd' Print CONST_INT OP in decimal.
7176 'm' Print one less than CONST_INT OP in decimal.
7177 'h' Print the high-part relocation associated with OP, after stripping
7179 'R' Print the low-part relocation associated with OP.
7180 'C' Print the integer branch condition for comparison OP.
7181 'N' Print the inverse of the integer branch condition for comparison OP.
7182 'F' Print the FPU branch condition for comparison OP.
7183 'W' Print the inverse of the FPU branch condition for comparison OP.
7184 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7185 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7186 't' Like 'T', but with the EQ/NE cases reversed
7187 'Y' Print mips_fp_conditions[INTVAL (OP)]
7188 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7189 'q' Print a DSP accumulator register.
7190 'D' Print the second part of a double-word register or memory operand.
7191 'L' Print the low-order register in a double-word register operand.
7192 'M' Print high-order register in a double-word register operand.
7193 'z' Print $0 if OP is zero, otherwise print OP normally. */
7196 mips_print_operand (FILE *file, rtx op, int letter)
7200 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7202 mips_print_operand_punctuation (file, letter);
7207 code = GET_CODE (op);
7212 if (CONST_INT_P (op))
7213 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7215 output_operand_lossage ("invalid use of '%%%c'", letter);
7219 if (CONST_INT_P (op))
7220 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7222 output_operand_lossage ("invalid use of '%%%c'", letter);
7226 if (CONST_INT_P (op))
7227 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7229 output_operand_lossage ("invalid use of '%%%c'", letter);
7233 if (CONST_INT_P (op))
7234 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7236 output_operand_lossage ("invalid use of '%%%c'", letter);
7242 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7246 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7250 mips_print_int_branch_condition (file, code, letter);
7254 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7258 mips_print_float_branch_condition (file, code, letter);
7262 mips_print_float_branch_condition (file, reverse_condition (code),
7269 int truth = (code == NE) == (letter == 'T');
7270 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7275 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7276 fputs (mips_fp_conditions[UINTVAL (op)], file);
7278 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7285 mips_print_operand (file, op, 0);
7291 if (code == REG && MD_REG_P (REGNO (op)))
7292 fprintf (file, "$ac0");
7293 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7294 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7296 output_operand_lossage ("invalid use of '%%%c'", letter);
7304 unsigned int regno = REGNO (op);
7305 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7306 || (letter == 'L' && TARGET_BIG_ENDIAN)
7309 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7310 output_operand_lossage ("invalid use of '%%%c'", letter);
7311 /* We need to print $0 .. $31 for COP0 registers. */
7312 if (COP0_REG_P (regno))
7313 fprintf (file, "$%s", ®_names[regno][4]);
7315 fprintf (file, "%s", reg_names[regno]);
7321 output_address (plus_constant (XEXP (op, 0), 4));
7322 else if (letter && letter != 'z')
7323 output_operand_lossage ("invalid use of '%%%c'", letter);
7325 output_address (XEXP (op, 0));
7329 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7330 fputs (reg_names[GP_REG_FIRST], file);
7331 else if (letter && letter != 'z')
7332 output_operand_lossage ("invalid use of '%%%c'", letter);
7333 else if (CONST_GP_P (op))
7334 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7336 output_addr_const (file, mips_strip_unspec_address (op));
7342 /* Output address operand X to FILE. */
7345 mips_print_operand_address (FILE *file, rtx x)
7347 struct mips_address_info addr;
7349 if (mips_classify_address (&addr, x, word_mode, true))
7353 mips_print_operand (file, addr.offset, 0);
7354 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7357 case ADDRESS_LO_SUM:
7358 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7360 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7363 case ADDRESS_CONST_INT:
7364 output_addr_const (file, x);
7365 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7368 case ADDRESS_SYMBOLIC:
7369 output_addr_const (file, mips_strip_unspec_address (x));
7375 /* Implement TARGET_ENCODE_SECTION_INFO. */
7378 mips_encode_section_info (tree decl, rtx rtl, int first)
7380 default_encode_section_info (decl, rtl, first);
7382 if (TREE_CODE (decl) == FUNCTION_DECL)
7384 rtx symbol = XEXP (rtl, 0);
7385 tree type = TREE_TYPE (decl);
7387 /* Encode whether the symbol is short or long. */
7388 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7389 || mips_far_type_p (type))
7390 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7394 /* Implement TARGET_SELECT_RTX_SECTION. */
7397 mips_select_rtx_section (enum machine_mode mode, rtx x,
7398 unsigned HOST_WIDE_INT align)
7400 /* ??? Consider using mergeable small data sections. */
7401 if (mips_rtx_constant_in_small_data_p (mode))
7402 return get_named_section (NULL, ".sdata", 0);
7404 return default_elf_select_rtx_section (mode, x, align);
7407 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7409 The complication here is that, with the combination TARGET_ABICALLS
7410 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7411 absolute addresses, and should therefore not be included in the
7412 read-only part of a DSO. Handle such cases by selecting a normal
7413 data section instead of a read-only one. The logic apes that in
7414 default_function_rodata_section. */
7417 mips_function_rodata_section (tree decl)
7419 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7420 return default_function_rodata_section (decl);
7422 if (decl && DECL_SECTION_NAME (decl))
7424 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7425 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7427 char *rname = ASTRDUP (name);
7429 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7431 else if (flag_function_sections
7432 && flag_data_sections
7433 && strncmp (name, ".text.", 6) == 0)
7435 char *rname = ASTRDUP (name);
7436 memcpy (rname + 1, "data", 4);
7437 return get_section (rname, SECTION_WRITE, decl);
7440 return data_section;
7443 /* Implement TARGET_IN_SMALL_DATA_P. */
7446 mips_in_small_data_p (const_tree decl)
7448 unsigned HOST_WIDE_INT size;
7450 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7453 /* We don't yet generate small-data references for -mabicalls
7454 or VxWorks RTP code. See the related -G handling in
7455 mips_override_options. */
7456 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7459 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7463 /* Reject anything that isn't in a known small-data section. */
7464 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7465 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7468 /* If a symbol is defined externally, the assembler will use the
7469 usual -G rules when deciding how to implement macros. */
7470 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7473 else if (TARGET_EMBEDDED_DATA)
7475 /* Don't put constants into the small data section: we want them
7476 to be in ROM rather than RAM. */
7477 if (TREE_CODE (decl) != VAR_DECL)
7480 if (TREE_READONLY (decl)
7481 && !TREE_SIDE_EFFECTS (decl)
7482 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7486 /* Enforce -mlocal-sdata. */
7487 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7490 /* Enforce -mextern-sdata. */
7491 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7493 if (DECL_EXTERNAL (decl))
7495 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7499 /* We have traditionally not treated zero-sized objects as small data,
7500 so this is now effectively part of the ABI. */
7501 size = int_size_in_bytes (TREE_TYPE (decl));
7502 return size > 0 && size <= mips_small_data_threshold;
7505 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7506 anchors for small data: the GP register acts as an anchor in that
7507 case. We also don't want to use them for PC-relative accesses,
7508 where the PC acts as an anchor. */
7511 mips_use_anchors_for_symbol_p (const_rtx symbol)
7513 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7515 case SYMBOL_PC_RELATIVE:
7516 case SYMBOL_GP_RELATIVE:
7520 return default_use_anchors_for_symbol_p (symbol);
7524 /* The MIPS debug format wants all automatic variables and arguments
7525 to be in terms of the virtual frame pointer (stack pointer before
7526 any adjustment in the function), while the MIPS 3.0 linker wants
7527 the frame pointer to be the stack pointer after the initial
7528 adjustment. So, we do the adjustment here. The arg pointer (which
7529 is eliminated) points to the virtual frame pointer, while the frame
7530 pointer (which may be eliminated) points to the stack pointer after
7531 the initial adjustments. */
7534 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7536 rtx offset2 = const0_rtx;
7537 rtx reg = eliminate_constant_term (addr, &offset2);
7540 offset = INTVAL (offset2);
7542 if (reg == stack_pointer_rtx
7543 || reg == frame_pointer_rtx
7544 || reg == hard_frame_pointer_rtx)
7546 offset -= cfun->machine->frame.total_size;
7547 if (reg == hard_frame_pointer_rtx)
7548 offset += cfun->machine->frame.hard_frame_pointer_offset;
7551 /* sdbout_parms does not want this to crash for unrecognized cases. */
7553 else if (reg != arg_pointer_rtx)
7554 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7561 /* Implement ASM_OUTPUT_EXTERNAL. */
7564 mips_output_external (FILE *file, tree decl, const char *name)
7566 default_elf_asm_output_external (file, decl, name);
7568 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7569 set in order to avoid putting out names that are never really
7571 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7573 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7575 /* When using assembler macros, emit .extern directives for
7576 all small-data externs so that the assembler knows how
7579 In most cases it would be safe (though pointless) to emit
7580 .externs for other symbols too. One exception is when an
7581 object is within the -G limit but declared by the user to
7582 be in a section other than .sbss or .sdata. */
7583 fputs ("\t.extern\t", file);
7584 assemble_name (file, name);
7585 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7586 int_size_in_bytes (TREE_TYPE (decl)));
7588 else if (TARGET_IRIX
7589 && mips_abi == ABI_32
7590 && TREE_CODE (decl) == FUNCTION_DECL)
7592 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7593 `.global name .text' directive for every used but
7594 undefined function. If we don't, the linker may perform
7595 an optimization (skipping over the insns that set $gp)
7596 when it is unsafe. */
7597 fputs ("\t.globl ", file);
7598 assemble_name (file, name);
7599 fputs (" .text\n", file);
7604 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7607 mips_output_filename (FILE *stream, const char *name)
7609 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7611 if (write_symbols == DWARF2_DEBUG)
7613 else if (mips_output_filename_first_time)
7615 mips_output_filename_first_time = 0;
7616 num_source_filenames += 1;
7617 current_function_file = name;
7618 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7619 output_quoted_string (stream, name);
7620 putc ('\n', stream);
7622 /* If we are emitting stabs, let dbxout.c handle this (except for
7623 the mips_output_filename_first_time case). */
7624 else if (write_symbols == DBX_DEBUG)
7626 else if (name != current_function_file
7627 && strcmp (name, current_function_file) != 0)
7629 num_source_filenames += 1;
7630 current_function_file = name;
7631 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7632 output_quoted_string (stream, name);
7633 putc ('\n', stream);
7637 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7639 static void ATTRIBUTE_UNUSED
7640 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7645 fputs ("\t.dtprelword\t", file);
7649 fputs ("\t.dtpreldword\t", file);
7655 output_addr_const (file, x);
7656 fputs ("+0x8000", file);
7659 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7662 mips_dwarf_register_span (rtx reg)
7665 enum machine_mode mode;
7667 /* By default, GCC maps increasing register numbers to increasing
7668 memory locations, but paired FPRs are always little-endian,
7669 regardless of the prevailing endianness. */
7670 mode = GET_MODE (reg);
7671 if (FP_REG_P (REGNO (reg))
7672 && TARGET_BIG_ENDIAN
7673 && MAX_FPRS_PER_FMT > 1
7674 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7676 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7677 high = mips_subword (reg, true);
7678 low = mips_subword (reg, false);
7679 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7685 /* Implement ASM_OUTPUT_ASCII. */
7688 mips_output_ascii (FILE *stream, const char *string, size_t len)
7694 fprintf (stream, "\t.ascii\t\"");
7695 for (i = 0; i < len; i++)
7699 c = (unsigned char) string[i];
7702 if (c == '\\' || c == '\"')
7704 putc ('\\', stream);
7712 fprintf (stream, "\\%03o", c);
7716 if (cur_pos > 72 && i+1 < len)
7719 fprintf (stream, "\"\n\t.ascii\t\"");
7722 fprintf (stream, "\"\n");
7725 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7726 macros, mark the symbol as written so that mips_asm_output_external
7727 won't emit an .extern for it. STREAM is the output file, NAME is the
7728 name of the symbol, INIT_STRING is the string that should be written
7729 before the symbol and FINAL_STRING is the string that should be
7730 written after it. FINAL_STRING is a printf format that consumes the
7731 remaining arguments. */
7734 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7735 const char *final_string, ...)
7739 fputs (init_string, stream);
7740 assemble_name (stream, name);
7741 va_start (ap, final_string);
7742 vfprintf (stream, final_string, ap);
7745 if (!TARGET_EXPLICIT_RELOCS)
7747 tree name_tree = get_identifier (name);
7748 TREE_ASM_WRITTEN (name_tree) = 1;
7752 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7753 NAME is the name of the object and ALIGN is the required alignment
7754 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7755 alignment argument. */
7758 mips_declare_common_object (FILE *stream, const char *name,
7759 const char *init_string,
7760 unsigned HOST_WIDE_INT size,
7761 unsigned int align, bool takes_alignment_p)
7763 if (!takes_alignment_p)
7765 size += (align / BITS_PER_UNIT) - 1;
7766 size -= size % (align / BITS_PER_UNIT);
7767 mips_declare_object (stream, name, init_string,
7768 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7771 mips_declare_object (stream, name, init_string,
7772 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7773 size, align / BITS_PER_UNIT);
7776 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7777 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7780 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7781 unsigned HOST_WIDE_INT size,
7784 /* If the target wants uninitialized const declarations in
7785 .rdata then don't put them in .comm. */
7786 if (TARGET_EMBEDDED_DATA
7787 && TARGET_UNINIT_CONST_IN_RODATA
7788 && TREE_CODE (decl) == VAR_DECL
7789 && TREE_READONLY (decl)
7790 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7792 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7793 targetm.asm_out.globalize_label (stream, name);
7795 switch_to_section (readonly_data_section);
7796 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7797 mips_declare_object (stream, name, "",
7798 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7802 mips_declare_common_object (stream, name, "\n\t.comm\t",
7806 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7807 extern int size_directive_output;
7809 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
7810 definitions except that it uses mips_declare_object to emit the label. */
7813 mips_declare_object_name (FILE *stream, const char *name,
7814 tree decl ATTRIBUTE_UNUSED)
7816 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7817 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7820 size_directive_output = 0;
7821 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
7825 size_directive_output = 1;
7826 size = int_size_in_bytes (TREE_TYPE (decl));
7827 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7830 mips_declare_object (stream, name, "", ":\n");
7833 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
7836 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
7840 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
7841 if (!flag_inhibit_size_directive
7842 && DECL_SIZE (decl) != 0
7845 && DECL_INITIAL (decl) == error_mark_node
7846 && !size_directive_output)
7850 size_directive_output = 1;
7851 size = int_size_in_bytes (TREE_TYPE (decl));
7852 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7857 /* Return the FOO in the name of the ".mdebug.FOO" section associated
7858 with the current ABI. */
7861 mips_mdebug_abi_name (void)
7874 return TARGET_64BIT ? "eabi64" : "eabi32";
7880 /* Implement TARGET_ASM_FILE_START. */
7883 mips_file_start (void)
7885 default_file_start ();
7887 /* Generate a special section to describe the ABI switches used to
7888 produce the resultant binary. This is unnecessary on IRIX and
7889 causes unwanted warnings from the native linker. */
7892 /* Record the ABI itself. Modern versions of binutils encode
7893 this information in the ELF header flags, but GDB needs the
7894 information in order to correctly debug binaries produced by
7895 older binutils. See the function mips_gdbarch_init in
7897 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
7898 mips_mdebug_abi_name ());
7900 /* There is no ELF header flag to distinguish long32 forms of the
7901 EABI from long64 forms. Emit a special section to help tools
7902 such as GDB. Do the same for o64, which is sometimes used with
7904 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
7905 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
7906 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
7908 #ifdef HAVE_AS_GNU_ATTRIBUTE
7909 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
7910 (TARGET_HARD_FLOAT_ABI
7911 ? (TARGET_DOUBLE_FLOAT
7912 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
7916 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
7917 if (TARGET_ABICALLS)
7919 fprintf (asm_out_file, "\t.abicalls\n");
7920 if (TARGET_ABICALLS_PIC0)
7921 fprintf (asm_out_file, "\t.option\tpic0\n");
7924 if (flag_verbose_asm)
7925 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
7927 mips_small_data_threshold, mips_arch_info->name, mips_isa);
7930 /* Make the last instruction frame-related and note that it performs
7931 the operation described by FRAME_PATTERN. */
7934 mips_set_frame_expr (rtx frame_pattern)
7938 insn = get_last_insn ();
7939 RTX_FRAME_RELATED_P (insn) = 1;
7940 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7945 /* Return a frame-related rtx that stores REG at MEM.
7946 REG must be a single register. */
7949 mips_frame_set (rtx mem, rtx reg)
7953 /* If we're saving the return address register and the DWARF return
7954 address column differs from the hard register number, adjust the
7955 note reg to refer to the former. */
7956 if (REGNO (reg) == GP_REG_FIRST + 31
7957 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
7958 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
7960 set = gen_rtx_SET (VOIDmode, mem, reg);
7961 RTX_FRAME_RELATED_P (set) = 1;
7966 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
7967 mips16e_s2_s8_regs[X], it must also save the registers in indexes
7968 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
7969 static const unsigned char mips16e_s2_s8_regs[] = {
7970 30, 23, 22, 21, 20, 19, 18
7972 static const unsigned char mips16e_a0_a3_regs[] = {
7976 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
7977 ordered from the uppermost in memory to the lowest in memory. */
7978 static const unsigned char mips16e_save_restore_regs[] = {
7979 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
7982 /* Return the index of the lowest X in the range [0, SIZE) for which
7983 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
7986 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
7991 for (i = 0; i < size; i++)
7992 if (BITSET_P (mask, regs[i]))
7998 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
7999 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8000 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8001 is true for all indexes (X, SIZE). */
8004 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8005 unsigned int size, unsigned int *num_regs_ptr)
8009 i = mips16e_find_first_register (*mask_ptr, regs, size);
8010 for (i++; i < size; i++)
8011 if (!BITSET_P (*mask_ptr, regs[i]))
8014 *mask_ptr |= 1 << regs[i];
8018 /* Return a simplified form of X using the register values in REG_VALUES.
8019 REG_VALUES[R] is the last value assigned to hard register R, or null
8020 if R has not been modified.
8022 This function is rather limited, but is good enough for our purposes. */
8025 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8027 x = avoid_constant_pool_reference (x);
8031 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8032 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8033 x0, GET_MODE (XEXP (x, 0)));
8036 if (ARITHMETIC_P (x))
8038 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8039 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8040 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8044 && reg_values[REGNO (x)]
8045 && !rtx_unstable_p (reg_values[REGNO (x)]))
8046 return reg_values[REGNO (x)];
8051 /* Return true if (set DEST SRC) stores an argument register into its
8052 caller-allocated save slot, storing the number of that argument
8053 register in *REGNO_PTR if so. REG_VALUES is as for
8054 mips16e_collect_propagate_value. */
8057 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8058 unsigned int *regno_ptr)
8060 unsigned int argno, regno;
8061 HOST_WIDE_INT offset, required_offset;
8064 /* Check that this is a word-mode store. */
8065 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8068 /* Check that the register being saved is an unmodified argument
8070 regno = REGNO (src);
8071 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8073 argno = regno - GP_ARG_FIRST;
8075 /* Check whether the address is an appropriate stack-pointer or
8076 frame-pointer access. */
8077 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8078 mips_split_plus (addr, &base, &offset);
8079 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8080 if (base == hard_frame_pointer_rtx)
8081 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8082 else if (base != stack_pointer_rtx)
8084 if (offset != required_offset)
8091 /* A subroutine of mips_expand_prologue, called only when generating
8092 MIPS16e SAVE instructions. Search the start of the function for any
8093 instructions that save argument registers into their caller-allocated
8094 save slots. Delete such instructions and return a value N such that
8095 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8096 instructions redundant. */
8099 mips16e_collect_argument_saves (void)
8101 rtx reg_values[FIRST_PSEUDO_REGISTER];
8102 rtx insn, next, set, dest, src;
8103 unsigned int nargs, regno;
8105 push_topmost_sequence ();
8107 memset (reg_values, 0, sizeof (reg_values));
8108 for (insn = get_insns (); insn; insn = next)
8110 next = NEXT_INSN (insn);
8117 set = PATTERN (insn);
8118 if (GET_CODE (set) != SET)
8121 dest = SET_DEST (set);
8122 src = SET_SRC (set);
8123 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8125 if (!BITSET_P (cfun->machine->frame.mask, regno))
8128 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8131 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8132 reg_values[REGNO (dest)]
8133 = mips16e_collect_propagate_value (src, reg_values);
8137 pop_topmost_sequence ();
8142 /* Return a move between register REGNO and memory location SP + OFFSET.
8143 Make the move a load if RESTORE_P, otherwise make it a frame-related
8147 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8152 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8153 reg = gen_rtx_REG (SImode, regno);
8155 ? gen_rtx_SET (VOIDmode, reg, mem)
8156 : mips_frame_set (mem, reg));
8159 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8160 The instruction must:
8162 - Allocate or deallocate SIZE bytes in total; SIZE is known
8165 - Save or restore as many registers in *MASK_PTR as possible.
8166 The instruction saves the first registers at the top of the
8167 allocated area, with the other registers below it.
8169 - Save NARGS argument registers above the allocated area.
8171 (NARGS is always zero if RESTORE_P.)
8173 The SAVE and RESTORE instructions cannot save and restore all general
8174 registers, so there may be some registers left over for the caller to
8175 handle. Destructively modify *MASK_PTR so that it contains the registers
8176 that still need to be saved or restored. The caller can save these
8177 registers in the memory immediately below *OFFSET_PTR, which is a
8178 byte offset from the bottom of the allocated stack area. */
8181 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8182 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8186 HOST_WIDE_INT offset, top_offset;
8187 unsigned int i, regno;
8190 gcc_assert (cfun->machine->frame.num_fp == 0);
8192 /* Calculate the number of elements in the PARALLEL. We need one element
8193 for the stack adjustment, one for each argument register save, and one
8194 for each additional register move. */
8196 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8197 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8200 /* Create the final PARALLEL. */
8201 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8204 /* Add the stack pointer adjustment. */
8205 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8206 plus_constant (stack_pointer_rtx,
8207 restore_p ? size : -size));
8208 RTX_FRAME_RELATED_P (set) = 1;
8209 XVECEXP (pattern, 0, n++) = set;
8211 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8212 top_offset = restore_p ? size : 0;
8214 /* Save the arguments. */
8215 for (i = 0; i < nargs; i++)
8217 offset = top_offset + i * UNITS_PER_WORD;
8218 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8219 XVECEXP (pattern, 0, n++) = set;
8222 /* Then fill in the other register moves. */
8223 offset = top_offset;
8224 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8226 regno = mips16e_save_restore_regs[i];
8227 if (BITSET_P (*mask_ptr, regno))
8229 offset -= UNITS_PER_WORD;
8230 set = mips16e_save_restore_reg (restore_p, offset, regno);
8231 XVECEXP (pattern, 0, n++) = set;
8232 *mask_ptr &= ~(1 << regno);
8236 /* Tell the caller what offset it should use for the remaining registers. */
8237 *offset_ptr = size + (offset - top_offset);
8239 gcc_assert (n == XVECLEN (pattern, 0));
8244 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8245 pointer. Return true if PATTERN matches the kind of instruction
8246 generated by mips16e_build_save_restore. If INFO is nonnull,
8247 initialize it when returning true. */
8250 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8251 struct mips16e_save_restore_info *info)
8253 unsigned int i, nargs, mask, extra;
8254 HOST_WIDE_INT top_offset, save_offset, offset;
8255 rtx set, reg, mem, base;
8258 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8261 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8262 top_offset = adjust > 0 ? adjust : 0;
8264 /* Interpret all other members of the PARALLEL. */
8265 save_offset = top_offset - UNITS_PER_WORD;
8269 for (n = 1; n < XVECLEN (pattern, 0); n++)
8271 /* Check that we have a SET. */
8272 set = XVECEXP (pattern, 0, n);
8273 if (GET_CODE (set) != SET)
8276 /* Check that the SET is a load (if restoring) or a store
8278 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8282 /* Check that the address is the sum of the stack pointer and a
8283 possibly-zero constant offset. */
8284 mips_split_plus (XEXP (mem, 0), &base, &offset);
8285 if (base != stack_pointer_rtx)
8288 /* Check that SET's other operand is a register. */
8289 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8293 /* Check for argument saves. */
8294 if (offset == top_offset + nargs * UNITS_PER_WORD
8295 && REGNO (reg) == GP_ARG_FIRST + nargs)
8297 else if (offset == save_offset)
8299 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8300 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8303 mask |= 1 << REGNO (reg);
8304 save_offset -= UNITS_PER_WORD;
8310 /* Check that the restrictions on register ranges are met. */
8312 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8313 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8314 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8315 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8319 /* Make sure that the topmost argument register is not saved twice.
8320 The checks above ensure that the same is then true for the other
8321 argument registers. */
8322 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8325 /* Pass back information, if requested. */
8328 info->nargs = nargs;
8330 info->size = (adjust > 0 ? adjust : -adjust);
8336 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8337 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8338 the null terminator. */
8341 mips16e_add_register_range (char *s, unsigned int min_reg,
8342 unsigned int max_reg)
8344 if (min_reg != max_reg)
8345 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8347 s += sprintf (s, ",%s", reg_names[min_reg]);
8351 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8352 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8355 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8357 static char buffer[300];
8359 struct mips16e_save_restore_info info;
8360 unsigned int i, end;
8363 /* Parse the pattern. */
8364 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8367 /* Add the mnemonic. */
8368 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8371 /* Save the arguments. */
8373 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8374 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8375 else if (info.nargs == 1)
8376 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8378 /* Emit the amount of stack space to allocate or deallocate. */
8379 s += sprintf (s, "%d", (int) info.size);
8381 /* Save or restore $16. */
8382 if (BITSET_P (info.mask, 16))
8383 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8385 /* Save or restore $17. */
8386 if (BITSET_P (info.mask, 17))
8387 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8389 /* Save or restore registers in the range $s2...$s8, which
8390 mips16e_s2_s8_regs lists in decreasing order. Note that this
8391 is a software register range; the hardware registers are not
8392 numbered consecutively. */
8393 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8394 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8396 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8397 mips16e_s2_s8_regs[i]);
8399 /* Save or restore registers in the range $a0...$a3. */
8400 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8401 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8403 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8404 mips16e_a0_a3_regs[end - 1]);
8406 /* Save or restore $31. */
8407 if (BITSET_P (info.mask, 31))
8408 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 31]);
8413 /* Return true if the current function has an insn that implicitly
8417 mips_function_has_gp_insn (void)
8419 /* Don't bother rechecking if we found one last time. */
8420 if (!cfun->machine->has_gp_insn_p)
8424 push_topmost_sequence ();
8425 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8426 if (USEFUL_INSN_P (insn)
8427 && (get_attr_got (insn) != GOT_UNSET
8428 || mips_small_data_pattern_p (PATTERN (insn))))
8430 cfun->machine->has_gp_insn_p = true;
8433 pop_topmost_sequence ();
8435 return cfun->machine->has_gp_insn_p;
8438 /* Return true if the current function returns its value in a floating-point
8439 register in MIPS16 mode. */
8442 mips16_cfun_returns_in_fpr_p (void)
8444 tree return_type = DECL_RESULT (current_function_decl);
8445 return (TARGET_MIPS16
8446 && TARGET_HARD_FLOAT_ABI
8447 && !aggregate_value_p (return_type, current_function_decl)
8448 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8451 /* Return the register that should be used as the global pointer
8452 within this function. Return INVALID_REGNUM if the function
8453 doesn't need a global pointer. */
8456 mips_global_pointer (void)
8460 /* $gp is always available unless we're using a GOT. */
8461 if (!TARGET_USE_GOT)
8462 return GLOBAL_POINTER_REGNUM;
8464 /* We must always provide $gp when it is used implicitly. */
8465 if (!TARGET_EXPLICIT_RELOCS)
8466 return GLOBAL_POINTER_REGNUM;
8468 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
8471 return GLOBAL_POINTER_REGNUM;
8473 /* If the function has a nonlocal goto, $gp must hold the correct
8474 global pointer for the target function. */
8475 if (crtl->has_nonlocal_goto)
8476 return GLOBAL_POINTER_REGNUM;
8478 /* There's no need to initialize $gp if it isn't referenced now,
8479 and if we can be sure that no new references will be added during
8481 if (!df_regs_ever_live_p (GLOBAL_POINTER_REGNUM)
8482 && !mips_function_has_gp_insn ())
8484 /* The function doesn't use $gp at the moment. If we're generating
8485 -call_nonpic code, no new uses will be introduced during or after
8487 if (TARGET_ABICALLS_PIC0)
8488 return INVALID_REGNUM;
8490 /* We need to handle the following implicit gp references:
8492 - Reload can sometimes introduce constant pool references
8493 into a function that otherwise didn't need them. For example,
8494 suppose we have an instruction like:
8496 (set (reg:DF R1) (float:DF (reg:SI R2)))
8498 If R2 turns out to be constant such as 1, the instruction may
8499 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8500 the option of using this constant if R2 doesn't get allocated
8503 In cases like these, reload will have added the constant to the
8504 pool but no instruction will yet refer to it.
8506 - MIPS16 functions that return in FPRs need to call an
8507 external libgcc routine. */
8508 if (!crtl->uses_const_pool
8509 && !mips16_cfun_returns_in_fpr_p ())
8510 return INVALID_REGNUM;
8513 /* We need a global pointer, but perhaps we can use a call-clobbered
8514 register instead of $gp. */
8515 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8516 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8517 if (!df_regs_ever_live_p (regno)
8518 && call_really_used_regs[regno]
8519 && !fixed_regs[regno]
8520 && regno != PIC_FUNCTION_ADDR_REGNUM)
8523 return GLOBAL_POINTER_REGNUM;
8526 /* Return true if REGNO is a register that is ordinarily call-clobbered
8527 but must nevertheless be preserved by an interrupt handler. */
8530 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8532 if (MD_REG_P (regno))
8535 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8538 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8540 /* $0 is hard-wired. */
8541 if (regno == GP_REG_FIRST)
8544 /* The interrupt handler can treat kernel registers as
8545 scratch registers. */
8546 if (KERNEL_REG_P (regno))
8549 /* The function will return the stack pointer to its original value
8551 if (regno == STACK_POINTER_REGNUM)
8554 /* Otherwise, return true for registers that aren't ordinarily
8556 return call_really_used_regs[regno];
8562 /* Return true if the current function should treat register REGNO
8566 mips_cfun_call_saved_reg_p (unsigned int regno)
8568 /* Interrupt handlers need to save extra registers. */
8569 if (cfun->machine->interrupt_handler_p
8570 && mips_interrupt_extra_call_saved_reg_p (regno))
8573 /* call_insns preserve $28 unless they explicitly say otherwise,
8574 so call_really_used_regs[] treats $28 as call-saved. However,
8575 we want the ABI property rather than the default call_insn
8577 return (regno == GLOBAL_POINTER_REGNUM
8578 ? TARGET_CALL_SAVED_GP
8579 : !call_really_used_regs[regno]);
8582 /* Return true if the function body might clobber register REGNO.
8583 We know that REGNO is call-saved. */
8586 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
8588 /* Some functions should be treated as clobbering all call-saved
8590 if (crtl->saves_all_registers)
8593 /* DF handles cases where a register is explicitly referenced in
8594 the rtl. Incoming values are passed in call-clobbered registers,
8595 so we can assume that any live call-saved register is set within
8597 if (df_regs_ever_live_p (regno))
8600 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8601 These clobbers are not explicit in the rtl. */
8602 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8605 /* If we're using a call-saved global pointer, the function's
8606 prologue will need to set it up. */
8607 if (cfun->machine->global_pointer == regno)
8610 /* The function's prologue will need to set the frame pointer if
8611 frame_pointer_needed. */
8612 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
8615 /* If a MIPS16 function returns a value in FPRs, its epilogue
8616 will need to call an external libgcc routine. This yet-to-be
8617 generated call_insn will clobber $31. */
8618 if (regno == GP_REG_FIRST + 31 && mips16_cfun_returns_in_fpr_p ())
8621 /* If REGNO is ordinarily call-clobbered, we must assume that any
8622 called function could modify it. */
8623 if (cfun->machine->interrupt_handler_p
8624 && !current_function_is_leaf
8625 && mips_interrupt_extra_call_saved_reg_p (regno))
8631 /* Return true if the current function must save register REGNO. */
8634 mips_save_reg_p (unsigned int regno)
8636 if (mips_cfun_call_saved_reg_p (regno))
8638 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
8641 /* Save both registers in an FPR pair if either one is used. This is
8642 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8643 register to be used without the even register. */
8644 if (FP_REG_P (regno)
8645 && MAX_FPRS_PER_FMT == 2
8646 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
8650 /* We need to save the incoming return address if __builtin_eh_return
8651 is being used to set a different return address. */
8652 if (regno == GP_REG_FIRST + 31 && crtl->calls_eh_return)
8658 /* Populate the current function's mips_frame_info structure.
8660 MIPS stack frames look like:
8662 +-------------------------------+
8664 | incoming stack arguments |
8666 +-------------------------------+
8668 | caller-allocated save area |
8669 A | for register arguments |
8671 +-------------------------------+ <-- incoming stack pointer
8673 | callee-allocated save area |
8674 B | for arguments that are |
8675 | split between registers and |
8678 +-------------------------------+ <-- arg_pointer_rtx
8680 C | callee-allocated save area |
8681 | for register varargs |
8683 +-------------------------------+ <-- frame_pointer_rtx
8684 | | + cop0_sp_offset
8685 | COP0 reg save area | + UNITS_PER_WORD
8687 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
8688 | | + UNITS_PER_WORD
8689 | accumulator save area |
8691 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
8692 | | + UNITS_PER_HWFPVALUE
8695 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
8696 | | + UNITS_PER_WORD
8699 +-------------------------------+ <-- frame_pointer_rtx with
8700 | | \ -fstack-protector
8701 | local variables | | var_size
8703 +-------------------------------+
8705 | $gp save area | | cprestore_size
8707 P +-------------------------------+ <-- hard_frame_pointer_rtx for
8709 | outgoing stack arguments | |
8711 +-------------------------------+ | args_size
8713 | caller-allocated save area | |
8714 | for register arguments | |
8716 +-------------------------------+ <-- stack_pointer_rtx
8717 frame_pointer_rtx without
8719 hard_frame_pointer_rtx for
8722 At least two of A, B and C will be empty.
8724 Dynamic stack allocations such as alloca insert data at point P.
8725 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
8726 hard_frame_pointer_rtx unchanged. */
8729 mips_compute_frame_info (void)
8731 struct mips_frame_info *frame;
8732 HOST_WIDE_INT offset, size;
8733 unsigned int regno, i;
8735 /* Set this function's interrupt properties. */
8736 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
8739 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
8740 else if (TARGET_HARD_FLOAT)
8741 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
8742 else if (TARGET_MIPS16)
8743 error ("interrupt handlers cannot be MIPS16 functions");
8746 cfun->machine->interrupt_handler_p = true;
8747 cfun->machine->use_shadow_register_set_p =
8748 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
8749 cfun->machine->keep_interrupts_masked_p =
8750 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
8751 cfun->machine->use_debug_exception_return_p =
8752 mips_use_debug_exception_return_p (TREE_TYPE
8753 (current_function_decl));
8757 frame = &cfun->machine->frame;
8758 memset (frame, 0, sizeof (*frame));
8759 size = get_frame_size ();
8761 cfun->machine->global_pointer = mips_global_pointer ();
8763 /* The first two blocks contain the outgoing argument area and the $gp save
8764 slot. This area isn't needed in leaf functions, but if the
8765 target-independent frame size is nonzero, we have already committed to
8766 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
8767 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
8769 /* The MIPS 3.0 linker does not like functions that dynamically
8770 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
8771 looks like we are trying to create a second frame pointer to the
8772 function, so allocate some stack space to make it happy. */
8773 if (cfun->calls_alloca)
8774 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
8776 frame->args_size = 0;
8777 frame->cprestore_size = 0;
8781 frame->args_size = crtl->outgoing_args_size;
8782 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
8784 offset = frame->args_size + frame->cprestore_size;
8786 /* Move above the local variables. */
8787 frame->var_size = MIPS_STACK_ALIGN (size);
8788 offset += frame->var_size;
8790 /* Find out which GPRs we need to save. */
8791 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8792 if (mips_save_reg_p (regno))
8795 frame->mask |= 1 << (regno - GP_REG_FIRST);
8798 /* If this function calls eh_return, we must also save and restore the
8799 EH data registers. */
8800 if (crtl->calls_eh_return)
8801 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
8804 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
8807 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
8808 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
8809 save all later registers too. */
8810 if (GENERATE_MIPS16E_SAVE_RESTORE)
8812 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
8813 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
8814 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
8815 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
8818 /* Move above the GPR save area. */
8819 if (frame->num_gp > 0)
8821 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
8822 frame->gp_sp_offset = offset - UNITS_PER_WORD;
8825 /* Find out which FPRs we need to save. This loop must iterate over
8826 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
8827 if (TARGET_HARD_FLOAT)
8828 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
8829 if (mips_save_reg_p (regno))
8831 frame->num_fp += MAX_FPRS_PER_FMT;
8832 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
8835 /* Move above the FPR save area. */
8836 if (frame->num_fp > 0)
8838 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
8839 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
8842 /* Add in space for the interrupt context information. */
8843 if (cfun->machine->interrupt_handler_p)
8846 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
8849 frame->acc_mask |= (1 << 0);
8852 /* Check accumulators 1, 2, 3. */
8853 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
8854 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
8857 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
8860 /* All interrupt context functions need space to preserve STATUS. */
8861 frame->num_cop0_regs++;
8863 /* If we don't keep interrupts masked, we need to save EPC. */
8864 if (!cfun->machine->keep_interrupts_masked_p)
8865 frame->num_cop0_regs++;
8868 /* Move above the accumulator save area. */
8869 if (frame->num_acc > 0)
8871 /* Each accumulator needs 2 words. */
8872 offset += frame->num_acc * 2 * UNITS_PER_WORD;
8873 frame->acc_sp_offset = offset - UNITS_PER_WORD;
8876 /* Move above the COP0 register save area. */
8877 if (frame->num_cop0_regs > 0)
8879 offset += frame->num_cop0_regs * UNITS_PER_WORD;
8880 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
8883 /* Move above the callee-allocated varargs save area. */
8884 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
8885 frame->arg_pointer_offset = offset;
8887 /* Move above the callee-allocated area for pretend stack arguments. */
8888 offset += crtl->args.pretend_args_size;
8889 frame->total_size = offset;
8891 /* Work out the offsets of the save areas from the top of the frame. */
8892 if (frame->gp_sp_offset > 0)
8893 frame->gp_save_offset = frame->gp_sp_offset - offset;
8894 if (frame->fp_sp_offset > 0)
8895 frame->fp_save_offset = frame->fp_sp_offset - offset;
8896 if (frame->acc_sp_offset > 0)
8897 frame->acc_save_offset = frame->acc_sp_offset - offset;
8898 if (frame->num_cop0_regs > 0)
8899 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
8901 /* MIPS16 code offsets the frame pointer by the size of the outgoing
8902 arguments. This tends to increase the chances of using unextended
8903 instructions for local variables and incoming arguments. */
8905 frame->hard_frame_pointer_offset = frame->args_size;
8908 /* Return the style of GP load sequence that is being used for the
8909 current function. */
8911 enum mips_loadgp_style
8912 mips_current_loadgp_style (void)
8914 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
8920 if (TARGET_ABSOLUTE_ABICALLS)
8921 return LOADGP_ABSOLUTE;
8923 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
8926 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
8929 mips_frame_pointer_required (void)
8931 /* If the function contains dynamic stack allocations, we need to
8932 use the frame pointer to access the static parts of the frame. */
8933 if (cfun->calls_alloca)
8936 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
8937 reload may be unable to compute the address of a local variable,
8938 since there is no way to add a large constant to the stack pointer
8939 without using a second temporary register. */
8942 mips_compute_frame_info ();
8943 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
8950 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
8951 or argument pointer. TO is either the stack pointer or hard frame
8955 mips_initial_elimination_offset (int from, int to)
8957 HOST_WIDE_INT offset;
8959 mips_compute_frame_info ();
8961 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
8964 case FRAME_POINTER_REGNUM:
8965 if (FRAME_GROWS_DOWNWARD)
8966 offset = (cfun->machine->frame.args_size
8967 + cfun->machine->frame.cprestore_size
8968 + cfun->machine->frame.var_size);
8973 case ARG_POINTER_REGNUM:
8974 offset = cfun->machine->frame.arg_pointer_offset;
8981 if (to == HARD_FRAME_POINTER_REGNUM)
8982 offset -= cfun->machine->frame.hard_frame_pointer_offset;
8987 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
8990 mips_extra_live_on_entry (bitmap regs)
8994 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
8995 the global pointer. */
8996 if (!TARGET_ABSOLUTE_ABICALLS)
8997 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
8999 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9000 the global pointer. */
9002 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9004 /* See the comment above load_call<mode> for details. */
9005 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9009 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9013 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9018 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
9021 /* Emit code to change the current function's return address to
9022 ADDRESS. SCRATCH is available as a scratch register, if needed.
9023 ADDRESS and SCRATCH are both word-mode GPRs. */
9026 mips_set_return_address (rtx address, rtx scratch)
9030 gcc_assert (BITSET_P (cfun->machine->frame.mask, 31));
9031 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9032 cfun->machine->frame.gp_sp_offset);
9033 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9036 /* Return a MEM rtx for the cprestore slot, using TEMP as a temporary base
9037 register if need be. */
9040 mips_cprestore_slot (rtx temp)
9042 const struct mips_frame_info *frame;
9044 HOST_WIDE_INT offset;
9046 frame = &cfun->machine->frame;
9047 if (frame_pointer_needed)
9049 base = hard_frame_pointer_rtx;
9050 offset = frame->args_size - frame->hard_frame_pointer_offset;
9054 base = stack_pointer_rtx;
9055 offset = frame->args_size;
9057 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9060 /* Restore $gp from its save slot, using TEMP as a temporary base register
9061 if need be. This function is for o32 and o64 abicalls only. */
9064 mips_restore_gp (rtx temp)
9066 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
9068 if (cfun->machine->global_pointer == INVALID_REGNUM)
9073 mips_emit_move (temp, mips_cprestore_slot (temp));
9074 mips_emit_move (pic_offset_table_rtx, temp);
9077 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp));
9078 if (!TARGET_EXPLICIT_RELOCS)
9079 emit_insn (gen_blockage ());
9082 /* A function to save or store a register. The first argument is the
9083 register and the second is the stack slot. */
9084 typedef void (*mips_save_restore_fn) (rtx, rtx);
9086 /* Use FN to save or restore register REGNO. MODE is the register's
9087 mode and OFFSET is the offset of its save slot from the current
9091 mips_save_restore_reg (enum machine_mode mode, int regno,
9092 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9096 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9097 fn (gen_rtx_REG (mode, regno), mem);
9100 /* Call FN for each accumlator that is saved by the current function.
9101 SP_OFFSET is the offset of the current stack pointer from the start
9105 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9107 HOST_WIDE_INT offset;
9110 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9111 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9113 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9114 offset -= UNITS_PER_WORD;
9115 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9116 offset -= UNITS_PER_WORD;
9119 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9120 if (BITSET_P (cfun->machine->frame.acc_mask,
9121 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9123 mips_save_restore_reg (word_mode, regno, offset, fn);
9124 offset -= UNITS_PER_WORD;
9128 /* Call FN for each register that is saved by the current function.
9129 SP_OFFSET is the offset of the current stack pointer from the start
9133 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9134 mips_save_restore_fn fn)
9136 enum machine_mode fpr_mode;
9137 HOST_WIDE_INT offset;
9140 /* Save registers starting from high to low. The debuggers prefer at least
9141 the return register be stored at func+4, and also it allows us not to
9142 need a nop in the epilogue if at least one register is reloaded in
9143 addition to return address. */
9144 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9145 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9146 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9148 mips_save_restore_reg (word_mode, regno, offset, fn);
9149 offset -= UNITS_PER_WORD;
9152 /* This loop must iterate over the same space as its companion in
9153 mips_compute_frame_info. */
9154 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9155 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9156 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9157 regno >= FP_REG_FIRST;
9158 regno -= MAX_FPRS_PER_FMT)
9159 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9161 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9162 offset -= GET_MODE_SIZE (fpr_mode);
9166 /* If we're generating n32 or n64 abicalls, and the current function
9167 does not use $28 as its global pointer, emit a cplocal directive.
9168 Use pic_offset_table_rtx as the argument to the directive. */
9171 mips_output_cplocal (void)
9173 if (!TARGET_EXPLICIT_RELOCS
9174 && cfun->machine->global_pointer != INVALID_REGNUM
9175 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9176 output_asm_insn (".cplocal %+", 0);
9179 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9182 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9186 #ifdef SDB_DEBUGGING_INFO
9187 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9188 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9191 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9192 floating-point arguments. */
9194 && TARGET_HARD_FLOAT_ABI
9195 && crtl->args.info.fp_code != 0)
9196 mips16_build_function_stub ();
9198 /* Get the function name the same way that toplev.c does before calling
9199 assemble_start_function. This is needed so that the name used here
9200 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9201 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9202 mips_start_function_definition (fnname, TARGET_MIPS16);
9204 /* Stop mips_file_end from treating this function as external. */
9205 if (TARGET_IRIX && mips_abi == ABI_32)
9206 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
9208 /* Output MIPS-specific frame information. */
9209 if (!flag_inhibit_size_directive)
9211 const struct mips_frame_info *frame;
9213 frame = &cfun->machine->frame;
9215 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9217 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9218 "# vars= " HOST_WIDE_INT_PRINT_DEC
9220 ", args= " HOST_WIDE_INT_PRINT_DEC
9221 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9222 reg_names[frame_pointer_needed
9223 ? HARD_FRAME_POINTER_REGNUM
9224 : STACK_POINTER_REGNUM],
9225 (frame_pointer_needed
9226 ? frame->total_size - frame->hard_frame_pointer_offset
9227 : frame->total_size),
9228 reg_names[GP_REG_FIRST + 31],
9230 frame->num_gp, frame->num_fp,
9232 frame->cprestore_size);
9234 /* .mask MASK, OFFSET. */
9235 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9236 frame->mask, frame->gp_save_offset);
9238 /* .fmask MASK, OFFSET. */
9239 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9240 frame->fmask, frame->fp_save_offset);
9243 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9244 Also emit the ".set noreorder; .set nomacro" sequence for functions
9246 if (mips_current_loadgp_style () == LOADGP_OLDABI)
9250 /* This is a fixed-form sequence. The position of the
9251 first two instructions is important because of the
9252 way _gp_disp is defined. */
9253 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9254 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9255 output_asm_insn ("sll\t$2,16", 0);
9256 output_asm_insn ("addu\t$2,$3", 0);
9258 /* .cpload must be in a .set noreorder but not a .set nomacro block. */
9259 else if (!cfun->machine->all_noreorder_p)
9260 output_asm_insn ("%(.cpload\t%^%)", 0);
9262 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
9264 else if (cfun->machine->all_noreorder_p)
9265 output_asm_insn ("%(%<", 0);
9267 /* Tell the assembler which register we're using as the global
9268 pointer. This is needed for thunks, since they can use either
9269 explicit relocs or assembler macros. */
9270 mips_output_cplocal ();
9273 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9276 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9277 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9281 /* Reinstate the normal $gp. */
9282 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9283 mips_output_cplocal ();
9285 if (cfun->machine->all_noreorder_p)
9287 /* Avoid using %>%) since it adds excess whitespace. */
9288 output_asm_insn (".set\tmacro", 0);
9289 output_asm_insn (".set\treorder", 0);
9290 set_noreorder = set_nomacro = 0;
9293 /* Get the function name the same way that toplev.c does before calling
9294 assemble_start_function. This is needed so that the name used here
9295 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9296 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9297 mips_end_function_definition (fnname);
9300 /* Save register REG to MEM. Make the instruction frame-related. */
9303 mips_save_reg (rtx reg, rtx mem)
9305 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9309 if (mips_split_64bit_move_p (mem, reg))
9310 mips_split_doubleword_move (mem, reg);
9312 mips_emit_move (mem, reg);
9314 x1 = mips_frame_set (mips_subword (mem, false),
9315 mips_subword (reg, false));
9316 x2 = mips_frame_set (mips_subword (mem, true),
9317 mips_subword (reg, true));
9318 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9322 if (REGNO (reg) == HI_REGNUM)
9325 emit_insn (gen_mfhidi_ti (MIPS_PROLOGUE_TEMP (DImode),
9326 gen_rtx_REG (TImode, MD_REG_FIRST)));
9328 emit_insn (gen_mfhisi_di (MIPS_PROLOGUE_TEMP (SImode),
9329 gen_rtx_REG (DImode, MD_REG_FIRST)));
9330 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9332 else if ((TARGET_MIPS16
9333 && REGNO (reg) != GP_REG_FIRST + 31
9334 && !M16_REG_P (REGNO (reg)))
9335 || ACC_REG_P (REGNO (reg)))
9337 /* If the register has no direct store instruction, move it
9338 through a temporary. Note that there's a special MIPS16
9339 instruction to save $31. */
9340 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
9341 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9344 mips_emit_move (mem, reg);
9346 mips_set_frame_expr (mips_frame_set (mem, reg));
9350 /* The __gnu_local_gp symbol. */
9352 static GTY(()) rtx mips_gnu_local_gp;
9354 /* If we're generating n32 or n64 abicalls, emit instructions
9355 to set up the global pointer. */
9358 mips_emit_loadgp (void)
9360 rtx addr, offset, incoming_address, base, index, pic_reg;
9362 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9363 switch (mips_current_loadgp_style ())
9365 case LOADGP_ABSOLUTE:
9366 if (mips_gnu_local_gp == NULL)
9368 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9369 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9371 emit_insn (Pmode == SImode
9372 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9373 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9377 /* Added by mips_output_function_prologue. */
9381 addr = XEXP (DECL_RTL (current_function_decl), 0);
9382 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9383 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9384 emit_insn (Pmode == SImode
9385 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9386 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9390 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9391 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9392 emit_insn (Pmode == SImode
9393 ? gen_loadgp_rtp_si (pic_reg, base, index)
9394 : gen_loadgp_rtp_di (pic_reg, base, index));
9402 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9404 /* Emit a blockage if there are implicit uses of the GP register.
9405 This includes profiled functions, because FUNCTION_PROFILE uses
9407 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9408 emit_insn (gen_loadgp_blockage ());
9411 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9414 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9416 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9419 /* Expand the "prologue" pattern. */
9422 mips_expand_prologue (void)
9424 const struct mips_frame_info *frame;
9429 if (cfun->machine->global_pointer != INVALID_REGNUM)
9430 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9432 frame = &cfun->machine->frame;
9433 size = frame->total_size;
9435 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9436 bytes beforehand; this is enough to cover the register save area
9437 without going out of range. */
9438 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
9439 || frame->num_cop0_regs > 0)
9441 HOST_WIDE_INT step1;
9443 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9444 if (GENERATE_MIPS16E_SAVE_RESTORE)
9446 HOST_WIDE_INT offset;
9447 unsigned int mask, regno;
9449 /* Try to merge argument stores into the save instruction. */
9450 nargs = mips16e_collect_argument_saves ();
9452 /* Build the save instruction. */
9454 insn = mips16e_build_save_restore (false, &mask, &offset,
9456 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9459 /* Check if we need to save other registers. */
9460 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9461 if (BITSET_P (mask, regno - GP_REG_FIRST))
9463 offset -= UNITS_PER_WORD;
9464 mips_save_restore_reg (word_mode, regno,
9465 offset, mips_save_reg);
9470 if (cfun->machine->interrupt_handler_p)
9472 HOST_WIDE_INT offset;
9475 /* If this interrupt is using a shadow register set, we need to
9476 get the stack pointer from the previous register set. */
9477 if (cfun->machine->use_shadow_register_set_p)
9478 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
9479 stack_pointer_rtx));
9481 if (!cfun->machine->keep_interrupts_masked_p)
9483 /* Move from COP0 Cause to K0. */
9484 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
9485 gen_rtx_REG (SImode,
9486 COP0_CAUSE_REG_NUM)));
9487 /* Move from COP0 EPC to K1. */
9488 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9489 gen_rtx_REG (SImode,
9490 COP0_EPC_REG_NUM)));
9493 /* Allocate the first part of the frame. */
9494 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
9496 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9499 /* Start at the uppermost location for saving. */
9500 offset = frame->cop0_sp_offset - size;
9501 if (!cfun->machine->keep_interrupts_masked_p)
9503 /* Push EPC into its stack slot. */
9504 mem = gen_frame_mem (word_mode,
9505 plus_constant (stack_pointer_rtx,
9507 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
9508 offset -= UNITS_PER_WORD;
9511 /* Move from COP0 Status to K1. */
9512 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9513 gen_rtx_REG (SImode,
9514 COP0_STATUS_REG_NUM)));
9516 /* Right justify the RIPL in k0. */
9517 if (!cfun->machine->keep_interrupts_masked_p)
9518 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
9519 gen_rtx_REG (SImode, K0_REG_NUM),
9520 GEN_INT (CAUSE_IPL)));
9522 /* Push Status into its stack slot. */
9523 mem = gen_frame_mem (word_mode,
9524 plus_constant (stack_pointer_rtx, offset));
9525 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
9526 offset -= UNITS_PER_WORD;
9528 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
9529 if (!cfun->machine->keep_interrupts_masked_p)
9530 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9533 gen_rtx_REG (SImode, K0_REG_NUM)));
9535 if (!cfun->machine->keep_interrupts_masked_p)
9536 /* Enable interrupts by clearing the KSU ERL and EXL bits.
9537 IE is already the correct value, so we don't have to do
9538 anything explicit. */
9539 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9542 gen_rtx_REG (SImode, GP_REG_FIRST)));
9544 /* Disable interrupts by clearing the KSU, ERL, EXL,
9546 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
9549 gen_rtx_REG (SImode, GP_REG_FIRST)));
9553 insn = gen_add3_insn (stack_pointer_rtx,
9556 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9559 mips_for_each_saved_acc (size, mips_save_reg);
9560 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
9564 /* Allocate the rest of the frame. */
9567 if (SMALL_OPERAND (-size))
9568 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
9570 GEN_INT (-size)))) = 1;
9573 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
9576 /* There are no instructions to add or subtract registers
9577 from the stack pointer, so use the frame pointer as a
9578 temporary. We should always be using a frame pointer
9579 in this case anyway. */
9580 gcc_assert (frame_pointer_needed);
9581 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9582 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
9583 hard_frame_pointer_rtx,
9584 MIPS_PROLOGUE_TEMP (Pmode)));
9585 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
9588 emit_insn (gen_sub3_insn (stack_pointer_rtx,
9590 MIPS_PROLOGUE_TEMP (Pmode)));
9592 /* Describe the combined effect of the previous instructions. */
9594 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9595 plus_constant (stack_pointer_rtx, -size)));
9599 /* Set up the frame pointer, if we're using one. */
9600 if (frame_pointer_needed)
9602 HOST_WIDE_INT offset;
9604 offset = frame->hard_frame_pointer_offset;
9607 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9608 RTX_FRAME_RELATED_P (insn) = 1;
9610 else if (SMALL_OPERAND (offset))
9612 insn = gen_add3_insn (hard_frame_pointer_rtx,
9613 stack_pointer_rtx, GEN_INT (offset));
9614 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9618 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
9619 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
9620 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
9621 hard_frame_pointer_rtx,
9622 MIPS_PROLOGUE_TEMP (Pmode)));
9624 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
9625 plus_constant (stack_pointer_rtx, offset)));
9629 mips_emit_loadgp ();
9631 /* Initialize the $gp save slot. */
9632 if (frame->cprestore_size > 0
9633 && cfun->machine->global_pointer != INVALID_REGNUM)
9636 mips_emit_move (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9638 else if (TARGET_ABICALLS_PIC2)
9639 emit_insn (gen_cprestore (GEN_INT (frame->args_size)));
9641 emit_move_insn (mips_cprestore_slot (MIPS_PROLOGUE_TEMP (Pmode)),
9642 pic_offset_table_rtx);
9645 /* We need to search back to the last use of K0 or K1. */
9646 if (cfun->machine->interrupt_handler_p)
9648 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
9650 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
9652 /* Emit a move from K1 to COP0 Status after insn. */
9653 gcc_assert (insn != NULL_RTX);
9654 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
9655 gen_rtx_REG (SImode, K1_REG_NUM)),
9659 /* If we are profiling, make sure no instructions are scheduled before
9660 the call to mcount. */
9662 emit_insn (gen_blockage ());
9665 /* Emit instructions to restore register REG from slot MEM. */
9668 mips_restore_reg (rtx reg, rtx mem)
9670 /* There's no MIPS16 instruction to load $31 directly. Load into
9671 $7 instead and adjust the return insn appropriately. */
9672 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
9673 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
9675 if (REGNO (reg) == HI_REGNUM)
9677 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9679 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9680 MIPS_EPILOGUE_TEMP (DImode),
9681 gen_rtx_REG (DImode, LO_REGNUM)));
9683 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9684 MIPS_EPILOGUE_TEMP (SImode),
9685 gen_rtx_REG (SImode, LO_REGNUM)));
9687 else if ((TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
9688 || ACC_REG_P (REGNO (reg)))
9690 /* Can't restore directly; move through a temporary. */
9691 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
9692 mips_emit_move (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
9695 mips_emit_move (reg, mem);
9698 /* Emit any instructions needed before a return. */
9701 mips_expand_before_return (void)
9703 /* When using a call-clobbered gp, we start out with unified call
9704 insns that include instructions to restore the gp. We then split
9705 these unified calls after reload. These split calls explicitly
9706 clobber gp, so there is no need to define
9707 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
9709 For consistency, we should also insert an explicit clobber of $28
9710 before return insns, so that the post-reload optimizers know that
9711 the register is not live on exit. */
9712 if (TARGET_CALL_CLOBBERED_GP)
9713 emit_clobber (pic_offset_table_rtx);
9716 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
9720 mips_expand_epilogue (bool sibcall_p)
9722 const struct mips_frame_info *frame;
9723 HOST_WIDE_INT step1, step2;
9724 rtx base, target, insn;
9726 if (!sibcall_p && mips_can_use_return_insn ())
9728 emit_jump_insn (gen_return ());
9732 /* In MIPS16 mode, if the return value should go into a floating-point
9733 register, we need to call a helper routine to copy it over. */
9734 if (mips16_cfun_returns_in_fpr_p ())
9735 mips16_copy_fpr_return_value ();
9737 /* Split the frame into two. STEP1 is the amount of stack we should
9738 deallocate before restoring the registers. STEP2 is the amount we
9739 should deallocate afterwards.
9741 Start off by assuming that no registers need to be restored. */
9742 frame = &cfun->machine->frame;
9743 step1 = frame->total_size;
9746 /* Work out which register holds the frame address. */
9747 if (!frame_pointer_needed)
9748 base = stack_pointer_rtx;
9751 base = hard_frame_pointer_rtx;
9752 step1 -= frame->hard_frame_pointer_offset;
9755 /* If we need to restore registers, deallocate as much stack as
9756 possible in the second step without going out of range. */
9757 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
9758 || frame->num_cop0_regs > 0)
9760 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
9764 /* Set TARGET to BASE + STEP1. */
9770 /* Get an rtx for STEP1 that we can add to BASE. */
9771 adjust = GEN_INT (step1);
9772 if (!SMALL_OPERAND (step1))
9774 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
9775 adjust = MIPS_EPILOGUE_TEMP (Pmode);
9778 /* Normal mode code can copy the result straight into $sp. */
9780 target = stack_pointer_rtx;
9782 emit_insn (gen_add3_insn (target, base, adjust));
9785 /* Copy TARGET into the stack pointer. */
9786 if (target != stack_pointer_rtx)
9787 mips_emit_move (stack_pointer_rtx, target);
9789 /* If we're using addressing macros, $gp is implicitly used by all
9790 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
9792 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
9793 emit_insn (gen_blockage ());
9795 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
9797 unsigned int regno, mask;
9798 HOST_WIDE_INT offset;
9801 /* Generate the restore instruction. */
9803 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
9805 /* Restore any other registers manually. */
9806 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9807 if (BITSET_P (mask, regno - GP_REG_FIRST))
9809 offset -= UNITS_PER_WORD;
9810 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
9813 /* Restore the remaining registers and deallocate the final bit
9815 emit_insn (restore);
9819 /* Restore the registers. */
9820 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
9821 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
9824 if (cfun->machine->interrupt_handler_p)
9826 HOST_WIDE_INT offset;
9829 offset = frame->cop0_sp_offset - (frame->total_size - step2);
9830 if (!cfun->machine->keep_interrupts_masked_p)
9832 /* Restore the original EPC. */
9833 mem = gen_frame_mem (word_mode,
9834 plus_constant (stack_pointer_rtx, offset));
9835 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
9836 offset -= UNITS_PER_WORD;
9838 /* Move to COP0 EPC. */
9839 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
9840 gen_rtx_REG (SImode, K0_REG_NUM)));
9843 /* Restore the original Status. */
9844 mem = gen_frame_mem (word_mode,
9845 plus_constant (stack_pointer_rtx, offset));
9846 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
9847 offset -= UNITS_PER_WORD;
9849 /* If we don't use shoadow register set, we need to update SP. */
9850 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
9851 emit_insn (gen_add3_insn (stack_pointer_rtx,
9855 /* Move to COP0 Status. */
9856 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
9857 gen_rtx_REG (SImode, K0_REG_NUM)));
9861 /* Deallocate the final bit of the frame. */
9863 emit_insn (gen_add3_insn (stack_pointer_rtx,
9869 /* Add in the __builtin_eh_return stack adjustment. We need to
9870 use a temporary in MIPS16 code. */
9871 if (crtl->calls_eh_return)
9875 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
9876 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
9877 MIPS_EPILOGUE_TEMP (Pmode),
9878 EH_RETURN_STACKADJ_RTX));
9879 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
9882 emit_insn (gen_add3_insn (stack_pointer_rtx,
9884 EH_RETURN_STACKADJ_RTX));
9889 mips_expand_before_return ();
9890 if (cfun->machine->interrupt_handler_p)
9892 /* Interrupt handlers generate eret or deret. */
9893 if (cfun->machine->use_debug_exception_return_p)
9894 emit_jump_insn (gen_mips_deret ());
9896 emit_jump_insn (gen_mips_eret ());
9902 /* When generating MIPS16 code, the normal
9903 mips_for_each_saved_gpr_and_fpr path will restore the return
9904 address into $7 rather than $31. */
9906 && !GENERATE_MIPS16E_SAVE_RESTORE
9907 && BITSET_P (frame->mask, 31))
9908 regno = GP_REG_FIRST + 7;
9910 regno = GP_REG_FIRST + 31;
9911 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
9915 /* Search from the beginning to the first use of K0 or K1. */
9916 if (cfun->machine->interrupt_handler_p
9917 && !cfun->machine->keep_interrupts_masked_p)
9919 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
9921 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
9923 gcc_assert (insn != NULL_RTX);
9924 /* Insert disable interrupts before the first use of K0 or K1. */
9925 emit_insn_before (gen_mips_di (), insn);
9926 emit_insn_before (gen_mips_ehb (), insn);
9930 /* Return nonzero if this function is known to have a null epilogue.
9931 This allows the optimizer to omit jumps to jumps if no stack
9935 mips_can_use_return_insn (void)
9937 /* Interrupt handlers need to go through the epilogue. */
9938 if (cfun->machine->interrupt_handler_p)
9941 if (!reload_completed)
9947 /* In MIPS16 mode, a function that returns a floating-point value
9948 needs to arrange to copy the return value into the floating-point
9950 if (mips16_cfun_returns_in_fpr_p ())
9953 return cfun->machine->frame.total_size == 0;
9956 /* Return true if register REGNO can store a value of mode MODE.
9957 The result of this function is cached in mips_hard_regno_mode_ok. */
9960 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
9963 enum mode_class mclass;
9965 if (mode == CCV2mode)
9968 && (regno - ST_REG_FIRST) % 2 == 0);
9970 if (mode == CCV4mode)
9973 && (regno - ST_REG_FIRST) % 4 == 0);
9978 return regno == FPSW_REGNUM;
9980 return (ST_REG_P (regno)
9982 || FP_REG_P (regno));
9985 size = GET_MODE_SIZE (mode);
9986 mclass = GET_MODE_CLASS (mode);
9988 if (GP_REG_P (regno))
9989 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
9991 if (FP_REG_P (regno)
9992 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
9993 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
9995 /* Allow TFmode for CCmode reloads. */
9996 if (mode == TFmode && ISA_HAS_8CC)
9999 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10000 if (TARGET_LOONGSON_VECTORS
10001 && (mode == V2SImode
10002 || mode == V4HImode
10003 || mode == V8QImode
10004 || mode == DImode))
10007 if (mclass == MODE_FLOAT
10008 || mclass == MODE_COMPLEX_FLOAT
10009 || mclass == MODE_VECTOR_FLOAT)
10010 return size <= UNITS_PER_FPVALUE;
10012 /* Allow integer modes that fit into a single register. We need
10013 to put integers into FPRs when using instructions like CVT
10014 and TRUNC. There's no point allowing sizes smaller than a word,
10015 because the FPU has no appropriate load/store instructions. */
10016 if (mclass == MODE_INT)
10017 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10020 if (ACC_REG_P (regno)
10021 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10023 if (MD_REG_P (regno))
10025 /* After a multiplication or division, clobbering HI makes
10026 the value of LO unpredictable, and vice versa. This means
10027 that, for all interesting cases, HI and LO are effectively
10030 We model this by requiring that any value that uses HI
10032 if (size <= UNITS_PER_WORD * 2)
10033 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10037 /* DSP accumulators do not have the same restrictions as
10038 HI and LO, so we can treat them as normal doubleword
10040 if (size <= UNITS_PER_WORD)
10043 if (size <= UNITS_PER_WORD * 2
10044 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10049 if (ALL_COP_REG_P (regno))
10050 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10052 if (regno == GOT_VERSION_REGNUM)
10053 return mode == SImode;
10058 /* Implement HARD_REGNO_NREGS. */
10061 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10063 if (ST_REG_P (regno))
10064 /* The size of FP status registers is always 4, because they only hold
10065 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10066 return (GET_MODE_SIZE (mode) + 3) / 4;
10068 if (FP_REG_P (regno))
10069 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10071 /* All other registers are word-sized. */
10072 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10075 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10076 in mips_hard_regno_nregs. */
10079 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10085 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10086 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10088 size = MIN (size, 4);
10089 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10091 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10093 size = MIN (size, UNITS_PER_FPREG);
10094 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10096 if (!hard_reg_set_empty_p (left))
10097 size = MIN (size, UNITS_PER_WORD);
10098 return (GET_MODE_SIZE (mode) + size - 1) / size;
10101 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10104 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10105 enum machine_mode to ATTRIBUTE_UNUSED,
10106 enum reg_class rclass)
10108 /* There are several problems with changing the modes of values
10109 in floating-point registers:
10111 - When a multi-word value is stored in paired floating-point
10112 registers, the first register always holds the low word.
10113 We therefore can't allow FPRs to change between single-word
10114 and multi-word modes on big-endian targets.
10116 - GCC assumes that each word of a multiword register can be accessed
10117 individually using SUBREGs. This is not true for floating-point
10118 registers if they are bigger than a word.
10120 - Loading a 32-bit value into a 64-bit floating-point register
10121 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10122 We can't allow FPRs to change from SImode to to a wider mode on
10125 - If the FPU has already interpreted a value in one format, we must
10126 not ask it to treat the value as having a different format.
10128 We therefore disallow all mode changes involving FPRs. */
10129 return reg_classes_intersect_p (FP_REGS, rclass);
10132 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10135 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10140 return TARGET_HARD_FLOAT;
10143 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10146 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10153 /* Implement MODES_TIEABLE_P. */
10156 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10158 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10159 prefer to put one of them in FPRs. */
10160 return (mode1 == mode2
10161 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10162 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10165 /* Implement PREFERRED_RELOAD_CLASS. */
10168 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10170 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10173 if (reg_class_subset_p (FP_REGS, rclass)
10174 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10177 if (reg_class_subset_p (GR_REGS, rclass))
10180 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10186 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10187 Return a "canonical" class to represent it in later calculations. */
10189 static enum reg_class
10190 mips_canonicalize_move_class (enum reg_class rclass)
10192 /* All moves involving accumulator registers have the same cost. */
10193 if (reg_class_subset_p (rclass, ACC_REGS))
10196 /* Likewise promote subclasses of general registers to the most
10197 interesting containing class. */
10198 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10200 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10201 rclass = GENERAL_REGS;
10206 /* Return the cost of moving a value of mode MODE from a register of
10207 class FROM to a GPR. Return 0 for classes that are unions of other
10208 classes handled by this function. */
10211 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10212 enum reg_class from)
10217 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10221 /* MFLO and MFHI. */
10229 /* LUI followed by MOVF. */
10235 /* This choice of value is historical. */
10243 /* Return the cost of moving a value of mode MODE from a GPR to a
10244 register of class TO. Return 0 for classes that are unions of
10245 other classes handled by this function. */
10248 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10253 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10257 /* MTLO and MTHI. */
10265 /* A secondary reload through an FPR scratch. */
10266 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10267 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10272 /* This choice of value is historical. */
10280 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10281 maximum of the move costs for subclasses; regclass will work out
10282 the maximum for us. */
10285 mips_register_move_cost (enum machine_mode mode,
10286 enum reg_class from, enum reg_class to)
10288 enum reg_class dregs;
10291 from = mips_canonicalize_move_class (from);
10292 to = mips_canonicalize_move_class (to);
10294 /* Handle moves that can be done without using general-purpose registers. */
10295 if (from == FP_REGS)
10297 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10301 /* The sequence generated by mips_expand_fcc_reload. */
10305 /* Handle cases in which only one class deviates from the ideal. */
10306 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10308 return mips_move_from_gpr_cost (mode, to);
10310 return mips_move_to_gpr_cost (mode, from);
10312 /* Handles cases that require a GPR temporary. */
10313 cost1 = mips_move_to_gpr_cost (mode, from);
10316 cost2 = mips_move_from_gpr_cost (mode, to);
10318 return cost1 + cost2;
10324 /* Implement TARGET_IRA_COVER_CLASSES. */
10326 static const enum reg_class *
10327 mips_ira_cover_classes (void)
10329 static const enum reg_class acc_classes[] = {
10330 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10331 ST_REGS, LIM_REG_CLASSES
10333 static const enum reg_class no_acc_classes[] = {
10334 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10335 ST_REGS, LIM_REG_CLASSES
10338 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10339 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10340 as a cover class only works well when we keep per-register costs.
10341 Using it when not optimizing can cause us to think accumulators
10342 have the same cost as GPRs in cases where GPRs are actually much
10344 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10347 /* Return the register class required for a secondary register when
10348 copying between one of the registers in RCLASS and value X, which
10349 has mode MODE. X is the source of the move if IN_P, otherwise it
10350 is the destination. Return NO_REGS if no secondary register is
10354 mips_secondary_reload_class (enum reg_class rclass,
10355 enum machine_mode mode, rtx x, bool in_p)
10359 /* If X is a constant that cannot be loaded into $25, it must be loaded
10360 into some other GPR. No other register class allows a direct move. */
10361 if (mips_dangerous_for_la25_p (x))
10362 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10364 regno = true_regnum (x);
10367 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10368 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10374 /* Copying from accumulator registers to anywhere other than a general
10375 register requires a temporary general register. */
10376 if (reg_class_subset_p (rclass, ACC_REGS))
10377 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10378 if (ACC_REG_P (regno))
10379 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10381 /* We can only copy a value to a condition code register from a
10382 floating-point register, and even then we require a scratch
10383 floating-point register. We can only copy a value out of a
10384 condition-code register into a general register. */
10385 if (reg_class_subset_p (rclass, ST_REGS))
10389 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10391 if (ST_REG_P (regno))
10395 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10398 if (reg_class_subset_p (rclass, FP_REGS))
10401 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10402 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10403 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10406 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10407 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10410 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
10411 /* We can force the constant to memory and use lwc1
10412 and ldc1. As above, we will use pairs of lwc1s if
10413 ldc1 is not supported. */
10416 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10417 /* In this case we can use mov.fmt. */
10420 /* Otherwise, we need to reload through an integer register. */
10423 if (FP_REG_P (regno))
10424 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10429 /* Implement TARGET_MODE_REP_EXTENDED. */
10432 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10434 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10435 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10436 return SIGN_EXTEND;
10441 /* Implement TARGET_VALID_POINTER_MODE. */
10444 mips_valid_pointer_mode (enum machine_mode mode)
10446 return mode == SImode || (TARGET_64BIT && mode == DImode);
10449 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10452 mips_vector_mode_supported_p (enum machine_mode mode)
10457 return TARGET_PAIRED_SINGLE_FLOAT;
10472 return TARGET_LOONGSON_VECTORS;
10479 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10482 mips_scalar_mode_supported_p (enum machine_mode mode)
10484 if (ALL_FIXED_POINT_MODE_P (mode)
10485 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
10488 return default_scalar_mode_supported_p (mode);
10491 /* Implement TARGET_INIT_LIBFUNCS. */
10493 #include "config/gofast.h"
10496 mips_init_libfuncs (void)
10498 if (TARGET_FIX_VR4120)
10500 /* Register the special divsi3 and modsi3 functions needed to work
10501 around VR4120 division errata. */
10502 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10503 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
10506 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
10508 /* Register the MIPS16 -mhard-float stubs. */
10509 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
10510 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
10511 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
10512 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
10514 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
10515 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
10516 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
10517 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
10518 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
10519 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
10520 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
10522 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
10523 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
10524 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
10526 if (TARGET_DOUBLE_FLOAT)
10528 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
10529 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
10530 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
10531 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
10533 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
10534 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
10535 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
10536 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
10537 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
10538 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
10539 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
10541 set_conv_libfunc (sext_optab, DFmode, SFmode,
10542 "__mips16_extendsfdf2");
10543 set_conv_libfunc (trunc_optab, SFmode, DFmode,
10544 "__mips16_truncdfsf2");
10545 set_conv_libfunc (sfix_optab, SImode, DFmode,
10546 "__mips16_fix_truncdfsi");
10547 set_conv_libfunc (sfloat_optab, DFmode, SImode,
10548 "__mips16_floatsidf");
10549 set_conv_libfunc (ufloat_optab, DFmode, SImode,
10550 "__mips16_floatunsidf");
10554 /* Register the gofast functions if selected using --enable-gofast. */
10555 gofast_maybe_init_libfuncs ();
10557 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
10558 on an external non-MIPS16 routine to implement __sync_synchronize. */
10560 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
10563 /* Return the length of INSN. LENGTH is the initial length computed by
10564 attributes in the machine-description file. */
10567 mips_adjust_insn_length (rtx insn, int length)
10569 /* A unconditional jump has an unfilled delay slot if it is not part
10570 of a sequence. A conditional jump normally has a delay slot, but
10571 does not on MIPS16. */
10572 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
10575 /* See how many nops might be needed to avoid hardware hazards. */
10576 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
10577 switch (get_attr_hazard (insn))
10591 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
10592 the .md file length attributes are 4-based for both modes.
10593 Adjust the MIPS16 ones here. */
10600 /* Return an asm sequence to start a noat block and load the address
10601 of a label into $1. */
10604 mips_output_load_label (void)
10606 if (TARGET_EXPLICIT_RELOCS)
10610 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
10613 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
10616 if (ISA_HAS_LOAD_DELAY)
10617 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
10618 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
10622 if (Pmode == DImode)
10623 return "%[dla\t%@,%0";
10625 return "%[la\t%@,%0";
10629 /* Return the assembly code for INSN, which has the operands given by
10630 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
10631 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
10632 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
10633 version of BRANCH_IF_TRUE. */
10636 mips_output_conditional_branch (rtx insn, rtx *operands,
10637 const char *branch_if_true,
10638 const char *branch_if_false)
10640 unsigned int length;
10641 rtx taken, not_taken;
10643 gcc_assert (LABEL_P (operands[1]));
10645 length = get_attr_length (insn);
10648 /* Just a simple conditional branch. */
10649 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
10650 return branch_if_true;
10653 /* Generate a reversed branch around a direct jump. This fallback does
10654 not use branch-likely instructions. */
10655 mips_branch_likely = false;
10656 not_taken = gen_label_rtx ();
10657 taken = operands[1];
10659 /* Generate the reversed branch to NOT_TAKEN. */
10660 operands[1] = not_taken;
10661 output_asm_insn (branch_if_false, operands);
10663 /* If INSN has a delay slot, we must provide delay slots for both the
10664 branch to NOT_TAKEN and the conditional jump. We must also ensure
10665 that INSN's delay slot is executed in the appropriate cases. */
10666 if (final_sequence)
10668 /* This first delay slot will always be executed, so use INSN's
10669 delay slot if is not annulled. */
10670 if (!INSN_ANNULLED_BRANCH_P (insn))
10672 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10673 asm_out_file, optimize, 1, NULL);
10674 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10677 output_asm_insn ("nop", 0);
10678 fprintf (asm_out_file, "\n");
10681 /* Output the unconditional branch to TAKEN. */
10683 output_asm_insn ("j\t%0%/", &taken);
10686 output_asm_insn (mips_output_load_label (), &taken);
10687 output_asm_insn ("jr\t%@%]%/", 0);
10690 /* Now deal with its delay slot; see above. */
10691 if (final_sequence)
10693 /* This delay slot will only be executed if the branch is taken.
10694 Use INSN's delay slot if is annulled. */
10695 if (INSN_ANNULLED_BRANCH_P (insn))
10697 final_scan_insn (XVECEXP (final_sequence, 0, 1),
10698 asm_out_file, optimize, 1, NULL);
10699 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
10702 output_asm_insn ("nop", 0);
10703 fprintf (asm_out_file, "\n");
10706 /* Output NOT_TAKEN. */
10707 targetm.asm_out.internal_label (asm_out_file, "L",
10708 CODE_LABEL_NUMBER (not_taken));
10712 /* Return the assembly code for INSN, which branches to OPERANDS[1]
10713 if some ordering condition is true. The condition is given by
10714 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
10715 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
10716 its second is always zero. */
10719 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
10721 const char *branch[2];
10723 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
10724 Make BRANCH[0] branch on the inverse condition. */
10725 switch (GET_CODE (operands[0]))
10727 /* These cases are equivalent to comparisons against zero. */
10729 inverted_p = !inverted_p;
10730 /* Fall through. */
10732 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
10733 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
10736 /* These cases are always true or always false. */
10738 inverted_p = !inverted_p;
10739 /* Fall through. */
10741 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
10742 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
10746 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
10747 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
10750 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
10753 /* Return or emit the assembly code for __sync_*() loop LOOP. The
10754 loop should support both normal and likely branches, using %? and
10755 %~ where appropriate. If BARRIER_BEFORE is true a sync sequence is
10756 emitted before the loop. A sync is always emitted after the loop.
10757 OPERANDS are the insn operands. */
10760 mips_output_sync_loop (bool barrier_before,
10761 const char *loop, rtx *operands)
10763 if (barrier_before)
10764 output_asm_insn ("sync", NULL);
10765 /* Use branch-likely instructions to work around the LL/SC R10000 errata. */
10766 mips_branch_likely = TARGET_FIX_R10000;
10768 /* If the target needs a sync after the loop, emit the loop now and
10769 return the sync. */
10771 if (TARGET_SYNC_AFTER_SC)
10773 output_asm_insn (loop, operands);
10780 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
10781 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
10783 When working around R4000 and R4400 errata, we need to make sure that
10784 the division is not immediately followed by a shift[1][2]. We also
10785 need to stop the division from being put into a branch delay slot[3].
10786 The easiest way to avoid both problems is to add a nop after the
10787 division. When a divide-by-zero check is needed, this nop can be
10788 used to fill the branch delay slot.
10790 [1] If a double-word or a variable shift executes immediately
10791 after starting an integer division, the shift may give an
10792 incorrect result. See quotations of errata #16 and #28 from
10793 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10794 in mips.md for details.
10796 [2] A similar bug to [1] exists for all revisions of the
10797 R4000 and the R4400 when run in an MC configuration.
10798 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
10800 "19. In this following sequence:
10802 ddiv (or ddivu or div or divu)
10803 dsll32 (or dsrl32, dsra32)
10805 if an MPT stall occurs, while the divide is slipping the cpu
10806 pipeline, then the following double shift would end up with an
10809 Workaround: The compiler needs to avoid generating any
10810 sequence with divide followed by extended double shift."
10812 This erratum is also present in "MIPS R4400MC Errata, Processor
10813 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
10814 & 3.0" as errata #10 and #4, respectively.
10816 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
10817 (also valid for MIPS R4000MC processors):
10819 "52. R4000SC: This bug does not apply for the R4000PC.
10821 There are two flavors of this bug:
10823 1) If the instruction just after divide takes an RF exception
10824 (tlb-refill, tlb-invalid) and gets an instruction cache
10825 miss (both primary and secondary) and the line which is
10826 currently in secondary cache at this index had the first
10827 data word, where the bits 5..2 are set, then R4000 would
10828 get a wrong result for the div.
10833 ------------------- # end-of page. -tlb-refill
10838 ------------------- # end-of page. -tlb-invalid
10841 2) If the divide is in the taken branch delay slot, where the
10842 target takes RF exception and gets an I-cache miss for the
10843 exception vector or where I-cache miss occurs for the
10844 target address, under the above mentioned scenarios, the
10845 div would get wrong results.
10848 j r2 # to next page mapped or unmapped
10849 div r8,r9 # this bug would be there as long
10850 # as there is an ICache miss and
10851 nop # the "data pattern" is present
10854 beq r0, r0, NextPage # to Next page
10858 This bug is present for div, divu, ddiv, and ddivu
10861 Workaround: For item 1), OS could make sure that the next page
10862 after the divide instruction is also mapped. For item 2), the
10863 compiler could make sure that the divide instruction is not in
10864 the branch delay slot."
10866 These processors have PRId values of 0x00004220 and 0x00004300 for
10867 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
10870 mips_output_division (const char *division, rtx *operands)
10875 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
10877 output_asm_insn (s, operands);
10880 if (TARGET_CHECK_ZERO_DIV)
10884 output_asm_insn (s, operands);
10885 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
10887 else if (GENERATE_DIVIDE_TRAPS)
10889 output_asm_insn (s, operands);
10890 s = "teq\t%2,%.,7";
10894 output_asm_insn ("%(bne\t%2,%.,1f", operands);
10895 output_asm_insn (s, operands);
10896 s = "break\t7%)\n1:";
10902 /* Return true if IN_INSN is a multiply-add or multiply-subtract
10903 instruction and if OUT_INSN assigns to the accumulator operand. */
10906 mips_linked_madd_p (rtx out_insn, rtx in_insn)
10910 x = single_set (in_insn);
10916 if (GET_CODE (x) == PLUS
10917 && GET_CODE (XEXP (x, 0)) == MULT
10918 && reg_set_p (XEXP (x, 1), out_insn))
10921 if (GET_CODE (x) == MINUS
10922 && GET_CODE (XEXP (x, 1)) == MULT
10923 && reg_set_p (XEXP (x, 0), out_insn))
10929 /* True if the dependency between OUT_INSN and IN_INSN is on the store
10930 data rather than the address. We need this because the cprestore
10931 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
10932 which causes the default routine to abort. We just return false
10936 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10938 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10941 return !store_data_bypass_p (out_insn, in_insn);
10945 /* Variables and flags used in scheduler hooks when tuning for
10949 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
10952 /* If true, then next ALU1/2 instruction will go to ALU1. */
10955 /* If true, then next FALU1/2 unstruction will go to FALU1. */
10958 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
10959 int alu1_core_unit_code;
10960 int alu2_core_unit_code;
10961 int falu1_core_unit_code;
10962 int falu2_core_unit_code;
10964 /* True if current cycle has a multi instruction.
10965 This flag is used in mips_ls2_dfa_post_advance_cycle. */
10966 bool cycle_has_multi_p;
10968 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
10969 These are used in mips_ls2_dfa_post_advance_cycle to initialize
10971 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
10972 instruction to go ALU1. */
10973 rtx alu1_turn_enabled_insn;
10974 rtx alu2_turn_enabled_insn;
10975 rtx falu1_turn_enabled_insn;
10976 rtx falu2_turn_enabled_insn;
10979 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
10980 dependencies have no cost, except on the 20Kc where output-dependence
10981 is treated like input-dependence. */
10984 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
10985 rtx dep ATTRIBUTE_UNUSED, int cost)
10987 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
10990 if (REG_NOTE_KIND (link) != 0)
10995 /* Return the number of instructions that can be issued per cycle. */
10998 mips_issue_rate (void)
11002 case PROCESSOR_74KC:
11003 case PROCESSOR_74KF2_1:
11004 case PROCESSOR_74KF1_1:
11005 case PROCESSOR_74KF3_2:
11006 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11007 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11008 but in reality only a maximum of 3 insns can be issued as
11009 floating-point loads and stores also require a slot in the
11011 case PROCESSOR_R10000:
11012 /* All R10K Processors are quad-issue (being the first MIPS
11013 processors to support this feature). */
11016 case PROCESSOR_20KC:
11017 case PROCESSOR_R4130:
11018 case PROCESSOR_R5400:
11019 case PROCESSOR_R5500:
11020 case PROCESSOR_R7000:
11021 case PROCESSOR_R9000:
11022 case PROCESSOR_OCTEON:
11025 case PROCESSOR_SB1:
11026 case PROCESSOR_SB1A:
11027 /* This is actually 4, but we get better performance if we claim 3.
11028 This is partly because of unwanted speculative code motion with the
11029 larger number, and partly because in most common cases we can't
11030 reach the theoretical max of 4. */
11033 case PROCESSOR_LOONGSON_2E:
11034 case PROCESSOR_LOONGSON_2F:
11042 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11045 mips_ls2_init_dfa_post_cycle_insn (void)
11048 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11049 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11053 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11054 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11058 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11059 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11063 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11064 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11067 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11068 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11069 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11070 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11073 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11074 Init data used in mips_dfa_post_advance_cycle. */
11077 mips_init_dfa_post_cycle_insn (void)
11079 if (TUNE_LOONGSON_2EF)
11080 mips_ls2_init_dfa_post_cycle_insn ();
11083 /* Initialize STATE when scheduling for Loongson 2E/2F.
11084 Support round-robin dispatch scheme by enabling only one of
11085 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11089 mips_ls2_dfa_post_advance_cycle (state_t state)
11091 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
11093 /* Though there are no non-pipelined ALU1 insns,
11094 we can get an instruction of type 'multi' before reload. */
11095 gcc_assert (mips_ls2.cycle_has_multi_p);
11096 mips_ls2.alu1_turn_p = false;
11099 mips_ls2.cycle_has_multi_p = false;
11101 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
11102 /* We have a non-pipelined alu instruction in the core,
11103 adjust round-robin counter. */
11104 mips_ls2.alu1_turn_p = true;
11106 if (mips_ls2.alu1_turn_p)
11108 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
11109 gcc_unreachable ();
11113 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
11114 gcc_unreachable ();
11117 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
11119 /* There are no non-pipelined FALU1 insns. */
11120 gcc_unreachable ();
11121 mips_ls2.falu1_turn_p = false;
11124 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
11125 /* We have a non-pipelined falu instruction in the core,
11126 adjust round-robin counter. */
11127 mips_ls2.falu1_turn_p = true;
11129 if (mips_ls2.falu1_turn_p)
11131 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
11132 gcc_unreachable ();
11136 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
11137 gcc_unreachable ();
11141 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
11142 This hook is being called at the start of each cycle. */
11145 mips_dfa_post_advance_cycle (void)
11147 if (TUNE_LOONGSON_2EF)
11148 mips_ls2_dfa_post_advance_cycle (curr_state);
11151 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
11152 be as wide as the scheduling freedom in the DFA. */
11155 mips_multipass_dfa_lookahead (void)
11157 /* Can schedule up to 4 of the 6 function units in any one cycle. */
11161 if (TUNE_LOONGSON_2EF)
11170 /* Remove the instruction at index LOWER from ready queue READY and
11171 reinsert it in front of the instruction at index HIGHER. LOWER must
11175 mips_promote_ready (rtx *ready, int lower, int higher)
11180 new_head = ready[lower];
11181 for (i = lower; i < higher; i++)
11182 ready[i] = ready[i + 1];
11183 ready[i] = new_head;
11186 /* If the priority of the instruction at POS2 in the ready queue READY
11187 is within LIMIT units of that of the instruction at POS1, swap the
11188 instructions if POS2 is not already less than POS1. */
11191 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
11194 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
11198 temp = ready[pos1];
11199 ready[pos1] = ready[pos2];
11200 ready[pos2] = temp;
11204 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
11205 that may clobber hi or lo. */
11206 static rtx mips_macc_chains_last_hilo;
11208 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
11209 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
11212 mips_macc_chains_record (rtx insn)
11214 if (get_attr_may_clobber_hilo (insn))
11215 mips_macc_chains_last_hilo = insn;
11218 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
11219 has NREADY elements, looking for a multiply-add or multiply-subtract
11220 instruction that is cumulative with mips_macc_chains_last_hilo.
11221 If there is one, promote it ahead of anything else that might
11222 clobber hi or lo. */
11225 mips_macc_chains_reorder (rtx *ready, int nready)
11229 if (mips_macc_chains_last_hilo != 0)
11230 for (i = nready - 1; i >= 0; i--)
11231 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
11233 for (j = nready - 1; j > i; j--)
11234 if (recog_memoized (ready[j]) >= 0
11235 && get_attr_may_clobber_hilo (ready[j]))
11237 mips_promote_ready (ready, i, j);
11244 /* The last instruction to be scheduled. */
11245 static rtx vr4130_last_insn;
11247 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
11248 points to an rtx that is initially an instruction. Nullify the rtx
11249 if the instruction uses the value of register X. */
11252 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
11257 insn_ptr = (rtx *) data;
11260 && reg_referenced_p (x, PATTERN (*insn_ptr)))
11264 /* Return true if there is true register dependence between vr4130_last_insn
11268 vr4130_true_reg_dependence_p (rtx insn)
11270 note_stores (PATTERN (vr4130_last_insn),
11271 vr4130_true_reg_dependence_p_1, &insn);
11275 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
11276 the ready queue and that INSN2 is the instruction after it, return
11277 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
11278 in which INSN1 and INSN2 can probably issue in parallel, but for
11279 which (INSN2, INSN1) should be less sensitive to instruction
11280 alignment than (INSN1, INSN2). See 4130.md for more details. */
11283 vr4130_swap_insns_p (rtx insn1, rtx insn2)
11285 sd_iterator_def sd_it;
11288 /* Check for the following case:
11290 1) there is some other instruction X with an anti dependence on INSN1;
11291 2) X has a higher priority than INSN2; and
11292 3) X is an arithmetic instruction (and thus has no unit restrictions).
11294 If INSN1 is the last instruction blocking X, it would better to
11295 choose (INSN1, X) over (INSN2, INSN1). */
11296 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
11297 if (DEP_TYPE (dep) == REG_DEP_ANTI
11298 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
11299 && recog_memoized (DEP_CON (dep)) >= 0
11300 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
11303 if (vr4130_last_insn != 0
11304 && recog_memoized (insn1) >= 0
11305 && recog_memoized (insn2) >= 0)
11307 /* See whether INSN1 and INSN2 use different execution units,
11308 or if they are both ALU-type instructions. If so, they can
11309 probably execute in parallel. */
11310 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
11311 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
11312 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
11314 /* If only one of the instructions has a dependence on
11315 vr4130_last_insn, prefer to schedule the other one first. */
11316 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
11317 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
11318 if (dep1_p != dep2_p)
11321 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
11322 is not an ALU-type instruction and if INSN1 uses the same
11323 execution unit. (Note that if this condition holds, we already
11324 know that INSN2 uses a different execution unit.) */
11325 if (class1 != VR4130_CLASS_ALU
11326 && recog_memoized (vr4130_last_insn) >= 0
11327 && class1 == get_attr_vr4130_class (vr4130_last_insn))
11334 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
11335 queue with at least two instructions. Swap the first two if
11336 vr4130_swap_insns_p says that it could be worthwhile. */
11339 vr4130_reorder (rtx *ready, int nready)
11341 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
11342 mips_promote_ready (ready, nready - 2, nready - 1);
11345 /* Record whether last 74k AGEN instruction was a load or store. */
11346 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
11348 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
11349 resets to TYPE_UNKNOWN state. */
11352 mips_74k_agen_init (rtx insn)
11354 if (!insn || !NONJUMP_INSN_P (insn))
11355 mips_last_74k_agen_insn = TYPE_UNKNOWN;
11358 enum attr_type type = get_attr_type (insn);
11359 if (type == TYPE_LOAD || type == TYPE_STORE)
11360 mips_last_74k_agen_insn = type;
11364 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
11365 loads to be grouped together, and multiple stores to be grouped
11366 together. Swap things around in the ready queue to make this happen. */
11369 mips_74k_agen_reorder (rtx *ready, int nready)
11372 int store_pos, load_pos;
11377 for (i = nready - 1; i >= 0; i--)
11379 rtx insn = ready[i];
11380 if (USEFUL_INSN_P (insn))
11381 switch (get_attr_type (insn))
11384 if (store_pos == -1)
11389 if (load_pos == -1)
11398 if (load_pos == -1 || store_pos == -1)
11401 switch (mips_last_74k_agen_insn)
11404 /* Prefer to schedule loads since they have a higher latency. */
11406 /* Swap loads to the front of the queue. */
11407 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
11410 /* Swap stores to the front of the queue. */
11411 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
11418 /* Implement TARGET_SCHED_INIT. */
11421 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11422 int max_ready ATTRIBUTE_UNUSED)
11424 mips_macc_chains_last_hilo = 0;
11425 vr4130_last_insn = 0;
11426 mips_74k_agen_init (NULL_RTX);
11428 /* When scheduling for Loongson2, branch instructions go to ALU1,
11429 therefore basic block is most likely to start with round-robin counter
11430 pointed to ALU2. */
11431 mips_ls2.alu1_turn_p = false;
11432 mips_ls2.falu1_turn_p = true;
11435 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
11438 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11439 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
11441 if (!reload_completed
11442 && TUNE_MACC_CHAINS
11444 mips_macc_chains_reorder (ready, *nreadyp);
11446 if (reload_completed
11448 && !TARGET_VR4130_ALIGN
11450 vr4130_reorder (ready, *nreadyp);
11453 mips_74k_agen_reorder (ready, *nreadyp);
11455 return mips_issue_rate ();
11458 /* Update round-robin counters for ALU1/2 and FALU1/2. */
11461 mips_ls2_variable_issue (rtx insn)
11463 if (mips_ls2.alu1_turn_p)
11465 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
11466 mips_ls2.alu1_turn_p = false;
11470 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
11471 mips_ls2.alu1_turn_p = true;
11474 if (mips_ls2.falu1_turn_p)
11476 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
11477 mips_ls2.falu1_turn_p = false;
11481 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
11482 mips_ls2.falu1_turn_p = true;
11485 if (recog_memoized (insn) >= 0)
11486 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
11489 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
11492 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
11493 rtx insn, int more)
11495 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
11496 if (USEFUL_INSN_P (insn))
11499 if (!reload_completed && TUNE_MACC_CHAINS)
11500 mips_macc_chains_record (insn);
11501 vr4130_last_insn = insn;
11503 mips_74k_agen_init (insn);
11504 else if (TUNE_LOONGSON_2EF)
11505 mips_ls2_variable_issue (insn);
11508 /* Instructions of type 'multi' should all be split before
11509 the second scheduling pass. */
11510 gcc_assert (!reload_completed
11511 || recog_memoized (insn) < 0
11512 || get_attr_type (insn) != TYPE_MULTI);
11517 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
11518 return the first operand of the associated PREF or PREFX insn. */
11521 mips_prefetch_cookie (rtx write, rtx locality)
11523 /* store_streamed / load_streamed. */
11524 if (INTVAL (locality) <= 0)
11525 return GEN_INT (INTVAL (write) + 4);
11527 /* store / load. */
11528 if (INTVAL (locality) <= 2)
11531 /* store_retained / load_retained. */
11532 return GEN_INT (INTVAL (write) + 6);
11535 /* Flags that indicate when a built-in function is available.
11537 BUILTIN_AVAIL_NON_MIPS16
11538 The function is available on the current target, but only
11539 in non-MIPS16 mode. */
11540 #define BUILTIN_AVAIL_NON_MIPS16 1
11542 /* Declare an availability predicate for built-in functions that
11543 require non-MIPS16 mode and also require COND to be true.
11544 NAME is the main part of the predicate's name. */
11545 #define AVAIL_NON_MIPS16(NAME, COND) \
11546 static unsigned int \
11547 mips_builtin_avail_##NAME (void) \
11549 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
11552 /* This structure describes a single built-in function. */
11553 struct mips_builtin_description {
11554 /* The code of the main .md file instruction. See mips_builtin_type
11555 for more information. */
11556 enum insn_code icode;
11558 /* The floating-point comparison code to use with ICODE, if any. */
11559 enum mips_fp_condition cond;
11561 /* The name of the built-in function. */
11564 /* Specifies how the function should be expanded. */
11565 enum mips_builtin_type builtin_type;
11567 /* The function's prototype. */
11568 enum mips_function_type function_type;
11570 /* Whether the function is available. */
11571 unsigned int (*avail) (void);
11574 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
11575 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
11576 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
11577 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
11578 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
11579 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
11580 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
11581 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
11582 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
11584 /* Construct a mips_builtin_description from the given arguments.
11586 INSN is the name of the associated instruction pattern, without the
11587 leading CODE_FOR_mips_.
11589 CODE is the floating-point condition code associated with the
11590 function. It can be 'f' if the field is not applicable.
11592 NAME is the name of the function itself, without the leading
11595 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
11597 AVAIL is the name of the availability predicate, without the leading
11598 mips_builtin_avail_. */
11599 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
11600 FUNCTION_TYPE, AVAIL) \
11601 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
11602 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
11603 mips_builtin_avail_ ## AVAIL }
11605 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
11606 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
11607 are as for MIPS_BUILTIN. */
11608 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11609 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
11611 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
11612 are subject to mips_builtin_avail_<AVAIL>. */
11613 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
11614 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
11615 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
11616 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
11617 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
11619 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
11620 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
11621 while the any and all forms are subject to mips_builtin_avail_mips3d. */
11622 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
11623 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
11624 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
11626 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
11627 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
11629 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
11630 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
11632 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
11633 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
11636 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
11637 are subject to mips_builtin_avail_mips3d. */
11638 #define CMP_4S_BUILTINS(INSN, COND) \
11639 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
11640 MIPS_BUILTIN_CMP_ANY, \
11641 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
11642 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
11643 MIPS_BUILTIN_CMP_ALL, \
11644 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
11646 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
11647 instruction requires mips_builtin_avail_<AVAIL>. */
11648 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
11649 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
11650 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11652 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
11653 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
11656 /* Define all the built-in functions related to C.cond.fmt condition COND. */
11657 #define CMP_BUILTINS(COND) \
11658 MOVTF_BUILTINS (c, COND, paired_single), \
11659 MOVTF_BUILTINS (cabs, COND, mips3d), \
11660 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
11661 CMP_PS_BUILTINS (c, COND, paired_single), \
11662 CMP_PS_BUILTINS (cabs, COND, mips3d), \
11663 CMP_4S_BUILTINS (c, COND), \
11664 CMP_4S_BUILTINS (cabs, COND)
11666 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
11667 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
11668 and AVAIL are as for MIPS_BUILTIN. */
11669 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
11670 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
11671 FUNCTION_TYPE, AVAIL)
11673 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
11674 branch instruction. AVAIL is as for MIPS_BUILTIN. */
11675 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
11676 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
11677 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
11679 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
11680 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11681 builtin_description field. */
11682 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
11683 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
11684 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
11685 FUNCTION_TYPE, mips_builtin_avail_loongson }
11687 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
11688 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
11689 builtin_description field. */
11690 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
11691 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
11693 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
11694 We use functions of this form when the same insn can be usefully applied
11695 to more than one datatype. */
11696 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
11697 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
11699 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
11700 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
11701 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
11702 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
11703 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
11704 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
11706 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
11707 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
11708 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
11709 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
11710 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
11711 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
11712 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
11713 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
11714 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
11715 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
11716 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
11717 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
11718 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
11719 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
11720 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
11721 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
11722 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
11723 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
11724 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
11725 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
11726 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
11727 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
11728 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
11729 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
11730 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
11731 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
11732 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
11733 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
11734 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
11736 static const struct mips_builtin_description mips_builtins[] = {
11737 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11738 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11739 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11740 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
11741 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
11742 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
11743 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
11744 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
11746 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
11747 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11748 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11749 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11750 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
11752 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
11753 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
11754 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11755 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11756 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11757 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11759 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
11760 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
11761 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
11762 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
11763 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
11764 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
11766 MIPS_FP_CONDITIONS (CMP_BUILTINS),
11768 /* Built-in functions for the SB-1 processor. */
11769 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
11771 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
11772 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11773 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11774 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11775 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11776 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11777 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11778 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11779 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11780 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11781 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11782 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
11783 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
11784 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
11785 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
11786 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
11787 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
11788 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11789 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11790 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
11791 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
11792 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
11793 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
11794 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11795 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11796 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11797 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11798 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
11799 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
11800 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
11801 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
11802 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11803 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11804 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11805 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
11806 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
11807 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11808 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
11809 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
11810 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11811 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
11812 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11813 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11814 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
11815 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
11816 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
11817 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
11818 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
11819 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11820 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11821 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
11822 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11823 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11824 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
11825 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11826 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11827 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
11828 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
11829 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11830 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
11831 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
11832 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
11833 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
11834 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11835 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
11836 BPOSGE_BUILTIN (32, dsp),
11838 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
11839 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
11840 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11841 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11842 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11843 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11844 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11845 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11846 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11847 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11848 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
11849 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11850 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11851 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11852 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11853 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11854 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
11855 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11856 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
11857 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
11858 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11859 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
11860 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
11861 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11862 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11863 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11864 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
11865 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11866 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11867 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11868 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11869 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11870 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
11871 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11872 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
11874 /* Built-in functions for the DSP ASE (32-bit only). */
11875 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11876 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11877 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11878 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
11879 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11880 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11881 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11882 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11883 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
11884 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11885 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11886 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11887 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
11888 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11889 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11890 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
11891 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
11892 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11893 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
11894 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
11895 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
11897 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
11898 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11899 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11900 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11901 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11902 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
11903 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
11904 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11905 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
11906 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
11907 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11908 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11909 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11910 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11911 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11912 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
11914 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
11915 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
11916 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
11917 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
11918 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11919 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11920 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11921 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11922 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11923 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11924 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
11925 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
11926 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11927 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11928 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11929 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11930 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
11931 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11932 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11933 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11934 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
11935 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
11936 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11937 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
11938 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11939 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11940 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11941 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11942 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11943 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11944 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11945 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11946 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11947 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11948 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11949 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11950 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11951 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11952 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
11953 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
11954 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11955 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11956 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11957 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11958 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11959 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11960 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11961 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11962 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
11963 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11964 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11965 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11966 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11967 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
11968 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
11969 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11970 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11971 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11972 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
11973 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11974 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
11975 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
11976 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
11977 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
11978 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11979 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11980 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11981 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11982 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11983 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11984 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11985 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11986 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
11987 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
11988 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
11989 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
11990 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
11991 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
11992 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
11993 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
11994 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
11995 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
11996 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
11997 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
11998 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
11999 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12000 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12001 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12002 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12003 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12004 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12005 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12006 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12007 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12008 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12009 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12010 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12011 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12012 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12013 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12015 /* Sundry other built-in functions. */
12016 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12019 /* MODE is a vector mode whose elements have type TYPE. Return the type
12020 of the vector itself. */
12023 mips_builtin_vector_type (tree type, enum machine_mode mode)
12025 static tree types[2 * (int) MAX_MACHINE_MODE];
12028 mode_index = (int) mode;
12030 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12031 mode_index += MAX_MACHINE_MODE;
12033 if (types[mode_index] == NULL_TREE)
12034 types[mode_index] = build_vector_type_for_mode (type, mode);
12035 return types[mode_index];
12038 /* Return a type for 'const volatile void *'. */
12041 mips_build_cvpointer_type (void)
12045 if (cache == NULL_TREE)
12046 cache = build_pointer_type (build_qualified_type
12048 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12052 /* Source-level argument types. */
12053 #define MIPS_ATYPE_VOID void_type_node
12054 #define MIPS_ATYPE_INT integer_type_node
12055 #define MIPS_ATYPE_POINTER ptr_type_node
12056 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12058 /* Standard mode-based argument types. */
12059 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12060 #define MIPS_ATYPE_SI intSI_type_node
12061 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12062 #define MIPS_ATYPE_DI intDI_type_node
12063 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12064 #define MIPS_ATYPE_SF float_type_node
12065 #define MIPS_ATYPE_DF double_type_node
12067 /* Vector argument types. */
12068 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12069 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12070 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12071 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12072 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12073 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12074 #define MIPS_ATYPE_UV2SI \
12075 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12076 #define MIPS_ATYPE_UV4HI \
12077 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
12078 #define MIPS_ATYPE_UV8QI \
12079 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
12081 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
12082 their associated MIPS_ATYPEs. */
12083 #define MIPS_FTYPE_ATYPES1(A, B) \
12084 MIPS_ATYPE_##A, MIPS_ATYPE_##B
12086 #define MIPS_FTYPE_ATYPES2(A, B, C) \
12087 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
12089 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
12090 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
12092 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
12093 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
12096 /* Return the function type associated with function prototype TYPE. */
12099 mips_build_function_type (enum mips_function_type type)
12101 static tree types[(int) MIPS_MAX_FTYPE_MAX];
12103 if (types[(int) type] == NULL_TREE)
12106 #define DEF_MIPS_FTYPE(NUM, ARGS) \
12107 case MIPS_FTYPE_NAME##NUM ARGS: \
12108 types[(int) type] \
12109 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
12112 #include "config/mips/mips-ftypes.def"
12113 #undef DEF_MIPS_FTYPE
12115 gcc_unreachable ();
12118 return types[(int) type];
12121 /* Implement TARGET_INIT_BUILTINS. */
12124 mips_init_builtins (void)
12126 const struct mips_builtin_description *d;
12129 /* Iterate through all of the bdesc arrays, initializing all of the
12130 builtin functions. */
12131 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
12133 d = &mips_builtins[i];
12135 add_builtin_function (d->name,
12136 mips_build_function_type (d->function_type),
12137 i, BUILT_IN_MD, NULL, NULL);
12141 /* Take argument ARGNO from EXP's argument list and convert it into a
12142 form suitable for input operand OPNO of instruction ICODE. Return the
12146 mips_prepare_builtin_arg (enum insn_code icode,
12147 unsigned int opno, tree exp, unsigned int argno)
12151 enum machine_mode mode;
12153 arg = CALL_EXPR_ARG (exp, argno);
12154 value = expand_normal (arg);
12155 mode = insn_data[icode].operand[opno].mode;
12156 if (!insn_data[icode].operand[opno].predicate (value, mode))
12158 /* We need to get the mode from ARG for two reasons:
12160 - to cope with address operands, where MODE is the mode of the
12161 memory, rather than of VALUE itself.
12163 - to cope with special predicates like pmode_register_operand,
12164 where MODE is VOIDmode. */
12165 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
12167 /* Check the predicate again. */
12168 if (!insn_data[icode].operand[opno].predicate (value, mode))
12170 error ("invalid argument to built-in function");
12178 /* Return an rtx suitable for output operand OP of instruction ICODE.
12179 If TARGET is non-null, try to use it where possible. */
12182 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
12184 enum machine_mode mode;
12186 mode = insn_data[icode].operand[op].mode;
12187 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
12188 target = gen_reg_rtx (mode);
12193 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
12194 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
12195 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
12196 suggests a good place to put the result. */
12199 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
12202 rtx ops[MAX_RECOG_OPERANDS];
12205 /* Map any target to operand 0. */
12209 target = mips_prepare_builtin_target (icode, opno, target);
12210 ops[opno] = target;
12214 /* Map the arguments to the other operands. The n_operands value
12215 for an expander includes match_dups and match_scratches as well as
12216 match_operands, so n_operands is only an upper bound on the number
12217 of arguments to the expander function. */
12218 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
12219 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
12220 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
12225 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
12229 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
12233 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
12237 gcc_unreachable ();
12242 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
12243 function; TYPE says which. EXP is the CALL_EXPR that calls the
12244 function, ICODE is the instruction that should be used to compare
12245 the first two arguments, and COND is the condition it should test.
12246 TARGET, if nonnull, suggests a good place to put the result. */
12249 mips_expand_builtin_movtf (enum mips_builtin_type type,
12250 enum insn_code icode, enum mips_fp_condition cond,
12251 rtx target, tree exp)
12253 rtx cmp_result, op0, op1;
12255 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
12256 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
12257 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
12258 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
12260 icode = CODE_FOR_mips_cond_move_tf_ps;
12261 target = mips_prepare_builtin_target (icode, 0, target);
12262 if (type == MIPS_BUILTIN_MOVT)
12264 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
12265 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
12269 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
12270 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
12272 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
12276 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
12277 into TARGET otherwise. Return TARGET. */
12280 mips_builtin_branch_and_move (rtx condition, rtx target,
12281 rtx value_if_true, rtx value_if_false)
12283 rtx true_label, done_label;
12285 true_label = gen_label_rtx ();
12286 done_label = gen_label_rtx ();
12288 /* First assume that CONDITION is false. */
12289 mips_emit_move (target, value_if_false);
12291 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
12292 emit_jump_insn (gen_condjump (condition, true_label));
12293 emit_jump_insn (gen_jump (done_label));
12296 /* Fix TARGET if CONDITION is true. */
12297 emit_label (true_label);
12298 mips_emit_move (target, value_if_true);
12300 emit_label (done_label);
12304 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
12305 the CALL_EXPR that calls the function, ICODE is the code of the
12306 comparison instruction, and COND is the condition it should test.
12307 TARGET, if nonnull, suggests a good place to put the boolean result. */
12310 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
12311 enum insn_code icode, enum mips_fp_condition cond,
12312 rtx target, tree exp)
12314 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
12317 if (target == 0 || GET_MODE (target) != SImode)
12318 target = gen_reg_rtx (SImode);
12320 /* The instruction should have a target operand, an operand for each
12321 argument, and an operand for COND. */
12322 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
12324 /* Prepare the operands to the comparison. */
12325 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
12326 for (argno = 0; argno < call_expr_nargs (exp); argno++)
12327 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
12329 switch (insn_data[icode].n_operands)
12332 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
12337 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
12338 args[2], args[3], GEN_INT (cond)));
12342 gcc_unreachable ();
12345 /* If the comparison sets more than one register, we define the result
12346 to be 0 if all registers are false and -1 if all registers are true.
12347 The value of the complete result is indeterminate otherwise. */
12348 switch (builtin_type)
12350 case MIPS_BUILTIN_CMP_ALL:
12351 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
12352 return mips_builtin_branch_and_move (condition, target,
12353 const0_rtx, const1_rtx);
12355 case MIPS_BUILTIN_CMP_UPPER:
12356 case MIPS_BUILTIN_CMP_LOWER:
12357 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
12358 condition = gen_single_cc (cmp_result, offset);
12359 return mips_builtin_branch_and_move (condition, target,
12360 const1_rtx, const0_rtx);
12363 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
12364 return mips_builtin_branch_and_move (condition, target,
12365 const1_rtx, const0_rtx);
12369 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
12370 if nonnull, suggests a good place to put the boolean result. */
12373 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
12375 rtx condition, cmp_result;
12378 if (target == 0 || GET_MODE (target) != SImode)
12379 target = gen_reg_rtx (SImode);
12381 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
12383 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
12388 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
12389 return mips_builtin_branch_and_move (condition, target,
12390 const1_rtx, const0_rtx);
12393 /* Implement TARGET_EXPAND_BUILTIN. */
12396 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
12397 enum machine_mode mode, int ignore)
12400 unsigned int fcode, avail;
12401 const struct mips_builtin_description *d;
12403 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12404 fcode = DECL_FUNCTION_CODE (fndecl);
12405 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
12406 d = &mips_builtins[fcode];
12407 avail = d->avail ();
12408 gcc_assert (avail != 0);
12411 error ("built-in function %qE not supported for MIPS16",
12412 DECL_NAME (fndecl));
12413 return ignore ? const0_rtx : CONST0_RTX (mode);
12415 switch (d->builtin_type)
12417 case MIPS_BUILTIN_DIRECT:
12418 return mips_expand_builtin_direct (d->icode, target, exp, true);
12420 case MIPS_BUILTIN_DIRECT_NO_TARGET:
12421 return mips_expand_builtin_direct (d->icode, target, exp, false);
12423 case MIPS_BUILTIN_MOVT:
12424 case MIPS_BUILTIN_MOVF:
12425 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
12426 d->cond, target, exp);
12428 case MIPS_BUILTIN_CMP_ANY:
12429 case MIPS_BUILTIN_CMP_ALL:
12430 case MIPS_BUILTIN_CMP_UPPER:
12431 case MIPS_BUILTIN_CMP_LOWER:
12432 case MIPS_BUILTIN_CMP_SINGLE:
12433 return mips_expand_builtin_compare (d->builtin_type, d->icode,
12434 d->cond, target, exp);
12436 case MIPS_BUILTIN_BPOSGE32:
12437 return mips_expand_builtin_bposge (d->builtin_type, target);
12439 gcc_unreachable ();
12442 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
12443 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
12444 struct mips16_constant {
12445 struct mips16_constant *next;
12448 enum machine_mode mode;
12451 /* Information about an incomplete MIPS16 constant pool. FIRST is the
12452 first constant, HIGHEST_ADDRESS is the highest address that the first
12453 byte of the pool can have, and INSN_ADDRESS is the current instruction
12455 struct mips16_constant_pool {
12456 struct mips16_constant *first;
12457 int highest_address;
12461 /* Add constant VALUE to POOL and return its label. MODE is the
12462 value's mode (used for CONST_INTs, etc.). */
12465 mips16_add_constant (struct mips16_constant_pool *pool,
12466 rtx value, enum machine_mode mode)
12468 struct mips16_constant **p, *c;
12469 bool first_of_size_p;
12471 /* See whether the constant is already in the pool. If so, return the
12472 existing label, otherwise leave P pointing to the place where the
12473 constant should be added.
12475 Keep the pool sorted in increasing order of mode size so that we can
12476 reduce the number of alignments needed. */
12477 first_of_size_p = true;
12478 for (p = &pool->first; *p != 0; p = &(*p)->next)
12480 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
12481 return (*p)->label;
12482 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
12484 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
12485 first_of_size_p = false;
12488 /* In the worst case, the constant needed by the earliest instruction
12489 will end up at the end of the pool. The entire pool must then be
12490 accessible from that instruction.
12492 When adding the first constant, set the pool's highest address to
12493 the address of the first out-of-range byte. Adjust this address
12494 downwards each time a new constant is added. */
12495 if (pool->first == 0)
12496 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
12497 of the instruction with the lowest two bits clear. The base PC
12498 value for LDPC has the lowest three bits clear. Assume the worst
12499 case here; namely that the PC-relative instruction occupies the
12500 last 2 bytes in an aligned word. */
12501 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
12502 pool->highest_address -= GET_MODE_SIZE (mode);
12503 if (first_of_size_p)
12504 /* Take into account the worst possible padding due to alignment. */
12505 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
12507 /* Create a new entry. */
12508 c = XNEW (struct mips16_constant);
12511 c->label = gen_label_rtx ();
12518 /* Output constant VALUE after instruction INSN and return the last
12519 instruction emitted. MODE is the mode of the constant. */
12522 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
12524 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
12526 rtx size = GEN_INT (GET_MODE_SIZE (mode));
12527 return emit_insn_after (gen_consttable_int (value, size), insn);
12530 if (SCALAR_FLOAT_MODE_P (mode))
12531 return emit_insn_after (gen_consttable_float (value), insn);
12533 if (VECTOR_MODE_P (mode))
12537 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
12538 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
12539 CONST_VECTOR_ELT (value, i), insn);
12543 gcc_unreachable ();
12546 /* Dump out the constants in CONSTANTS after INSN. */
12549 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
12551 struct mips16_constant *c, *next;
12555 for (c = constants; c != NULL; c = next)
12557 /* If necessary, increase the alignment of PC. */
12558 if (align < GET_MODE_SIZE (c->mode))
12560 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
12561 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
12563 align = GET_MODE_SIZE (c->mode);
12565 insn = emit_label_after (c->label, insn);
12566 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
12572 emit_barrier_after (insn);
12575 /* Return the length of instruction INSN. */
12578 mips16_insn_length (rtx insn)
12582 rtx body = PATTERN (insn);
12583 if (GET_CODE (body) == ADDR_VEC)
12584 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
12585 if (GET_CODE (body) == ADDR_DIFF_VEC)
12586 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
12588 return get_attr_length (insn);
12591 /* If *X is a symbolic constant that refers to the constant pool, add
12592 the constant to POOL and rewrite *X to use the constant's label. */
12595 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
12597 rtx base, offset, label;
12599 split_const (*x, &base, &offset);
12600 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
12602 label = mips16_add_constant (pool, get_pool_constant (base),
12603 get_pool_mode (base));
12604 base = gen_rtx_LABEL_REF (Pmode, label);
12605 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
12609 /* This structure is used to communicate with mips16_rewrite_pool_refs.
12610 INSN is the instruction we're rewriting and POOL points to the current
12612 struct mips16_rewrite_pool_refs_info {
12614 struct mips16_constant_pool *pool;
12617 /* Rewrite *X so that constant pool references refer to the constant's
12618 label instead. DATA points to a mips16_rewrite_pool_refs_info
12622 mips16_rewrite_pool_refs (rtx *x, void *data)
12624 struct mips16_rewrite_pool_refs_info *info =
12625 (struct mips16_rewrite_pool_refs_info *) data;
12627 if (force_to_mem_operand (*x, Pmode))
12629 rtx mem = force_const_mem (GET_MODE (*x), *x);
12630 validate_change (info->insn, x, mem, false);
12635 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
12639 if (TARGET_MIPS16_TEXT_LOADS)
12640 mips16_rewrite_pool_constant (info->pool, x);
12642 return GET_CODE (*x) == CONST ? -1 : 0;
12645 /* Build MIPS16 constant pools. */
12648 mips16_lay_out_constants (void)
12650 struct mips16_constant_pool pool;
12651 struct mips16_rewrite_pool_refs_info info;
12654 if (!TARGET_MIPS16_PCREL_LOADS)
12657 split_all_insns_noflow ();
12659 memset (&pool, 0, sizeof (pool));
12660 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12662 /* Rewrite constant pool references in INSN. */
12667 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
12670 pool.insn_address += mips16_insn_length (insn);
12672 if (pool.first != NULL)
12674 /* If there are no natural barriers between the first user of
12675 the pool and the highest acceptable address, we'll need to
12676 create a new instruction to jump around the constant pool.
12677 In the worst case, this instruction will be 4 bytes long.
12679 If it's too late to do this transformation after INSN,
12680 do it immediately before INSN. */
12681 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
12685 label = gen_label_rtx ();
12687 jump = emit_jump_insn_before (gen_jump (label), insn);
12688 JUMP_LABEL (jump) = label;
12689 LABEL_NUSES (label) = 1;
12690 barrier = emit_barrier_after (jump);
12692 emit_label_after (label, barrier);
12693 pool.insn_address += 4;
12696 /* See whether the constant pool is now out of range of the first
12697 user. If so, output the constants after the previous barrier.
12698 Note that any instructions between BARRIER and INSN (inclusive)
12699 will use negative offsets to refer to the pool. */
12700 if (pool.insn_address > pool.highest_address)
12702 mips16_emit_constants (pool.first, barrier);
12706 else if (BARRIER_P (insn))
12710 mips16_emit_constants (pool.first, get_last_insn ());
12713 /* Return true if it is worth r10k_simplify_address's while replacing
12714 an address with X. We are looking for constants, and for addresses
12715 at a known offset from the incoming stack pointer. */
12718 r10k_simplified_address_p (rtx x)
12720 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
12722 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
12725 /* X is an expression that appears in INSN. Try to use the UD chains
12726 to simplify it, returning the simplified form on success and the
12727 original form otherwise. Replace the incoming value of $sp with
12728 virtual_incoming_args_rtx (which should never occur in X otherwise). */
12731 r10k_simplify_address (rtx x, rtx insn)
12733 rtx newx, op0, op1, set, def_insn, note;
12735 struct df_link *defs;
12740 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12741 if (op0 != XEXP (x, 0))
12742 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
12743 op0, GET_MODE (XEXP (x, 0)));
12745 else if (BINARY_P (x))
12747 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12748 op1 = r10k_simplify_address (XEXP (x, 1), insn);
12749 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
12750 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
12752 else if (GET_CODE (x) == LO_SUM)
12754 /* LO_SUMs can be offset from HIGHs, if we know they won't
12755 overflow. See mips_classify_address for the rationale behind
12757 op0 = r10k_simplify_address (XEXP (x, 0), insn);
12758 if (GET_CODE (op0) == HIGH)
12759 newx = XEXP (x, 1);
12761 else if (REG_P (x))
12763 /* Uses are recorded by regno_reg_rtx, not X itself. */
12764 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
12766 defs = DF_REF_CHAIN (use);
12768 /* Require a single definition. */
12769 if (defs && defs->next == NULL)
12772 if (DF_REF_IS_ARTIFICIAL (def))
12774 /* Replace the incoming value of $sp with
12775 virtual_incoming_args_rtx. */
12776 if (x == stack_pointer_rtx
12777 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
12778 newx = virtual_incoming_args_rtx;
12780 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
12783 /* Make sure that DEF_INSN is a single set of REG. */
12784 def_insn = DF_REF_INSN (def);
12785 if (NONJUMP_INSN_P (def_insn))
12787 set = single_set (def_insn);
12788 if (set && rtx_equal_p (SET_DEST (set), x))
12790 /* Prefer to use notes, since the def-use chains
12791 are often shorter. */
12792 note = find_reg_equal_equiv_note (def_insn);
12794 newx = XEXP (note, 0);
12796 newx = SET_SRC (set);
12797 newx = r10k_simplify_address (newx, def_insn);
12803 if (newx && r10k_simplified_address_p (newx))
12808 /* Return true if ADDRESS is known to be an uncached address
12809 on R10K systems. */
12812 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
12814 unsigned HOST_WIDE_INT upper;
12816 /* Check for KSEG1. */
12817 if (address + 0x60000000 < 0x20000000)
12820 /* Check for uncached XKPHYS addresses. */
12821 if (Pmode == DImode)
12823 upper = (address >> 40) & 0xf9ffff;
12824 if (upper == 0x900000 || upper == 0xb80000)
12830 /* Return true if we can prove that an access to address X in instruction
12831 INSN would be safe from R10K speculation. This X is a general
12832 expression; it might not be a legitimate address. */
12835 r10k_safe_address_p (rtx x, rtx insn)
12838 HOST_WIDE_INT offset_val;
12840 x = r10k_simplify_address (x, insn);
12842 /* Check for references to the stack frame. It doesn't really matter
12843 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
12844 allows us to assume that accesses to any part of the eventual frame
12845 is safe from speculation at any point in the function. */
12846 mips_split_plus (x, &base, &offset_val);
12847 if (base == virtual_incoming_args_rtx
12848 && offset_val >= -cfun->machine->frame.total_size
12849 && offset_val < cfun->machine->frame.args_size)
12852 /* Check for uncached addresses. */
12853 if (CONST_INT_P (x))
12854 return r10k_uncached_address_p (INTVAL (x));
12856 /* Check for accesses to a static object. */
12857 split_const (x, &base, &offset);
12858 return offset_within_block_p (base, INTVAL (offset));
12861 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
12862 an in-range access to an automatic variable, or to an object with
12863 a link-time-constant address. */
12866 r10k_safe_mem_expr_p (tree expr, rtx offset)
12868 if (expr == NULL_TREE
12869 || offset == NULL_RTX
12870 || !CONST_INT_P (offset)
12871 || INTVAL (offset) < 0
12872 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
12875 while (TREE_CODE (expr) == COMPONENT_REF)
12877 expr = TREE_OPERAND (expr, 0);
12878 if (expr == NULL_TREE)
12882 return DECL_P (expr);
12885 /* A for_each_rtx callback for which DATA points to the instruction
12886 containing *X. Stop the search if we find a MEM that is not safe
12887 from R10K speculation. */
12890 r10k_needs_protection_p_1 (rtx *loc, void *data)
12898 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
12901 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
12907 /* A note_stores callback for which DATA points to an instruction pointer.
12908 If *DATA is nonnull, make it null if it X contains a MEM that is not
12909 safe from R10K speculation. */
12912 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12917 insn_ptr = (rtx *) data;
12918 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
12919 *insn_ptr = NULL_RTX;
12922 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
12923 Return nonzero if the call is not to a declared function. */
12926 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
12935 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
12941 /* Return true if instruction INSN needs to be protected by an R10K
12945 r10k_needs_protection_p (rtx insn)
12948 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
12950 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
12952 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
12953 return insn == NULL_RTX;
12956 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
12959 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
12960 edge is unconditional. */
12963 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
12968 FOR_EACH_EDGE (e, ei, bb->preds)
12969 if (!single_succ_p (e->src)
12970 || !TEST_BIT (protected_bbs, e->src->index)
12971 || (e->flags & EDGE_COMPLEX) != 0)
12976 /* Implement -mr10k-cache-barrier= for the current function. */
12979 r10k_insert_cache_barriers (void)
12981 int *rev_post_order;
12984 sbitmap protected_bbs;
12985 rtx insn, end, unprotected_region;
12989 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
12993 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. */
12994 compute_bb_for_insn ();
12996 /* Create def-use chains. */
12997 df_set_flags (DF_EQ_NOTES);
12998 df_chain_add_problem (DF_UD_CHAIN);
13001 /* Calculate dominators. */
13002 calculate_dominance_info (CDI_DOMINATORS);
13004 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13005 X is protected by a cache barrier. */
13006 protected_bbs = sbitmap_alloc (last_basic_block);
13007 sbitmap_zero (protected_bbs);
13009 /* Iterate over the basic blocks in reverse post-order. */
13010 rev_post_order = XNEWVEC (int, last_basic_block);
13011 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13012 for (i = 0; i < n; i++)
13014 bb = BASIC_BLOCK (rev_post_order[i]);
13016 /* If this block is only reached by unconditional edges, and if the
13017 source of every edge is protected, the beginning of the block is
13019 if (r10k_protected_bb_p (bb, protected_bbs))
13020 unprotected_region = NULL_RTX;
13022 unprotected_region = pc_rtx;
13023 end = NEXT_INSN (BB_END (bb));
13025 /* UNPROTECTED_REGION is:
13027 - null if we are processing a protected region,
13028 - pc_rtx if we are processing an unprotected region but have
13029 not yet found the first instruction in it
13030 - the first instruction in an unprotected region otherwise. */
13031 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13033 if (unprotected_region && INSN_P (insn))
13035 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13036 /* This CACHE instruction protects the following code. */
13037 unprotected_region = NULL_RTX;
13040 /* See if INSN is the first instruction in this
13041 unprotected region. */
13042 if (unprotected_region == pc_rtx)
13043 unprotected_region = insn;
13045 /* See if INSN needs to be protected. If so,
13046 we must insert a cache barrier somewhere between
13047 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13048 clear which position is better performance-wise,
13049 but as a tie-breaker, we assume that it is better
13050 to allow delay slots to be back-filled where
13051 possible, and that it is better not to insert
13052 barriers in the middle of already-scheduled code.
13053 We therefore insert the barrier at the beginning
13055 if (r10k_needs_protection_p (insn))
13057 emit_insn_before (gen_r10k_cache_barrier (),
13058 unprotected_region);
13059 unprotected_region = NULL_RTX;
13065 /* The called function is not required to protect the exit path.
13066 The code that follows a call is therefore unprotected. */
13067 unprotected_region = pc_rtx;
13070 /* Record whether the end of this block is protected. */
13071 if (unprotected_region == NULL_RTX)
13072 SET_BIT (protected_bbs, bb->index);
13074 XDELETEVEC (rev_post_order);
13076 sbitmap_free (protected_bbs);
13078 free_dominance_info (CDI_DOMINATORS);
13080 df_finish_pass (false);
13082 free_bb_for_insn ();
13085 /* A temporary variable used by for_each_rtx callbacks, etc. */
13086 static rtx mips_sim_insn;
13088 /* A structure representing the state of the processor pipeline.
13089 Used by the mips_sim_* family of functions. */
13091 /* The maximum number of instructions that can be issued in a cycle.
13092 (Caches mips_issue_rate.) */
13093 unsigned int issue_rate;
13095 /* The current simulation time. */
13098 /* How many more instructions can be issued in the current cycle. */
13099 unsigned int insns_left;
13101 /* LAST_SET[X].INSN is the last instruction to set register X.
13102 LAST_SET[X].TIME is the time at which that instruction was issued.
13103 INSN is null if no instruction has yet set register X. */
13107 } last_set[FIRST_PSEUDO_REGISTER];
13109 /* The pipeline's current DFA state. */
13113 /* Reset STATE to the initial simulation state. */
13116 mips_sim_reset (struct mips_sim *state)
13119 state->insns_left = state->issue_rate;
13120 memset (&state->last_set, 0, sizeof (state->last_set));
13121 state_reset (state->dfa_state);
13124 /* Initialize STATE before its first use. DFA_STATE points to an
13125 allocated but uninitialized DFA state. */
13128 mips_sim_init (struct mips_sim *state, state_t dfa_state)
13130 state->issue_rate = mips_issue_rate ();
13131 state->dfa_state = dfa_state;
13132 mips_sim_reset (state);
13135 /* Advance STATE by one clock cycle. */
13138 mips_sim_next_cycle (struct mips_sim *state)
13141 state->insns_left = state->issue_rate;
13142 state_transition (state->dfa_state, 0);
13145 /* Advance simulation state STATE until instruction INSN can read
13149 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
13151 unsigned int regno, end_regno;
13153 end_regno = END_REGNO (reg);
13154 for (regno = REGNO (reg); regno < end_regno; regno++)
13155 if (state->last_set[regno].insn != 0)
13159 t = (state->last_set[regno].time
13160 + insn_latency (state->last_set[regno].insn, insn));
13161 while (state->time < t)
13162 mips_sim_next_cycle (state);
13166 /* A for_each_rtx callback. If *X is a register, advance simulation state
13167 DATA until mips_sim_insn can read the register's value. */
13170 mips_sim_wait_regs_2 (rtx *x, void *data)
13173 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
13177 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
13180 mips_sim_wait_regs_1 (rtx *x, void *data)
13182 for_each_rtx (x, mips_sim_wait_regs_2, data);
13185 /* Advance simulation state STATE until all of INSN's register
13186 dependencies are satisfied. */
13189 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
13191 mips_sim_insn = insn;
13192 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
13195 /* Advance simulation state STATE until the units required by
13196 instruction INSN are available. */
13199 mips_sim_wait_units (struct mips_sim *state, rtx insn)
13203 tmp_state = alloca (state_size ());
13204 while (state->insns_left == 0
13205 || (memcpy (tmp_state, state->dfa_state, state_size ()),
13206 state_transition (tmp_state, insn) >= 0))
13207 mips_sim_next_cycle (state);
13210 /* Advance simulation state STATE until INSN is ready to issue. */
13213 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
13215 mips_sim_wait_regs (state, insn);
13216 mips_sim_wait_units (state, insn);
13219 /* mips_sim_insn has just set X. Update the LAST_SET array
13220 in simulation state DATA. */
13223 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
13225 struct mips_sim *state;
13227 state = (struct mips_sim *) data;
13230 unsigned int regno, end_regno;
13232 end_regno = END_REGNO (x);
13233 for (regno = REGNO (x); regno < end_regno; regno++)
13235 state->last_set[regno].insn = mips_sim_insn;
13236 state->last_set[regno].time = state->time;
13241 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
13242 can issue immediately (i.e., that mips_sim_wait_insn has already
13246 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
13248 state_transition (state->dfa_state, insn);
13249 state->insns_left--;
13251 mips_sim_insn = insn;
13252 note_stores (PATTERN (insn), mips_sim_record_set, state);
13255 /* Simulate issuing a NOP in state STATE. */
13258 mips_sim_issue_nop (struct mips_sim *state)
13260 if (state->insns_left == 0)
13261 mips_sim_next_cycle (state);
13262 state->insns_left--;
13265 /* Update simulation state STATE so that it's ready to accept the instruction
13266 after INSN. INSN should be part of the main rtl chain, not a member of a
13270 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
13272 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
13274 mips_sim_issue_nop (state);
13276 switch (GET_CODE (SEQ_BEGIN (insn)))
13280 /* We can't predict the processor state after a call or label. */
13281 mips_sim_reset (state);
13285 /* The delay slots of branch likely instructions are only executed
13286 when the branch is taken. Therefore, if the caller has simulated
13287 the delay slot instruction, STATE does not really reflect the state
13288 of the pipeline for the instruction after the delay slot. Also,
13289 branch likely instructions tend to incur a penalty when not taken,
13290 so there will probably be an extra delay between the branch and
13291 the instruction after the delay slot. */
13292 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
13293 mips_sim_reset (state);
13301 /* The VR4130 pipeline issues aligned pairs of instructions together,
13302 but it stalls the second instruction if it depends on the first.
13303 In order to cut down the amount of logic required, this dependence
13304 check is not based on a full instruction decode. Instead, any non-SPECIAL
13305 instruction is assumed to modify the register specified by bits 20-16
13306 (which is usually the "rt" field).
13308 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
13309 input, so we can end up with a false dependence between the branch
13310 and its delay slot. If this situation occurs in instruction INSN,
13311 try to avoid it by swapping rs and rt. */
13314 vr4130_avoid_branch_rt_conflict (rtx insn)
13318 first = SEQ_BEGIN (insn);
13319 second = SEQ_END (insn);
13321 && NONJUMP_INSN_P (second)
13322 && GET_CODE (PATTERN (first)) == SET
13323 && GET_CODE (SET_DEST (PATTERN (first))) == PC
13324 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
13326 /* Check for the right kind of condition. */
13327 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
13328 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
13329 && REG_P (XEXP (cond, 0))
13330 && REG_P (XEXP (cond, 1))
13331 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
13332 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
13334 /* SECOND mentions the rt register but not the rs register. */
13335 rtx tmp = XEXP (cond, 0);
13336 XEXP (cond, 0) = XEXP (cond, 1);
13337 XEXP (cond, 1) = tmp;
13342 /* Implement -mvr4130-align. Go through each basic block and simulate the
13343 processor pipeline. If we find that a pair of instructions could execute
13344 in parallel, and the first of those instructions is not 8-byte aligned,
13345 insert a nop to make it aligned. */
13348 vr4130_align_insns (void)
13350 struct mips_sim state;
13351 rtx insn, subinsn, last, last2, next;
13356 /* LAST is the last instruction before INSN to have a nonzero length.
13357 LAST2 is the last such instruction before LAST. */
13361 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
13364 mips_sim_init (&state, alloca (state_size ()));
13365 for (insn = get_insns (); insn != 0; insn = next)
13367 unsigned int length;
13369 next = NEXT_INSN (insn);
13371 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
13372 This isn't really related to the alignment pass, but we do it on
13373 the fly to avoid a separate instruction walk. */
13374 vr4130_avoid_branch_rt_conflict (insn);
13376 if (USEFUL_INSN_P (insn))
13377 FOR_EACH_SUBINSN (subinsn, insn)
13379 mips_sim_wait_insn (&state, subinsn);
13381 /* If we want this instruction to issue in parallel with the
13382 previous one, make sure that the previous instruction is
13383 aligned. There are several reasons why this isn't worthwhile
13384 when the second instruction is a call:
13386 - Calls are less likely to be performance critical,
13387 - There's a good chance that the delay slot can execute
13388 in parallel with the call.
13389 - The return address would then be unaligned.
13391 In general, if we're going to insert a nop between instructions
13392 X and Y, it's better to insert it immediately after X. That
13393 way, if the nop makes Y aligned, it will also align any labels
13394 between X and Y. */
13395 if (state.insns_left != state.issue_rate
13396 && !CALL_P (subinsn))
13398 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
13400 /* SUBINSN is the first instruction in INSN and INSN is
13401 aligned. We want to align the previous instruction
13402 instead, so insert a nop between LAST2 and LAST.
13404 Note that LAST could be either a single instruction
13405 or a branch with a delay slot. In the latter case,
13406 LAST, like INSN, is already aligned, but the delay
13407 slot must have some extra delay that stops it from
13408 issuing at the same time as the branch. We therefore
13409 insert a nop before the branch in order to align its
13411 emit_insn_after (gen_nop (), last2);
13414 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
13416 /* SUBINSN is the delay slot of INSN, but INSN is
13417 currently unaligned. Insert a nop between
13418 LAST and INSN to align it. */
13419 emit_insn_after (gen_nop (), last);
13423 mips_sim_issue_insn (&state, subinsn);
13425 mips_sim_finish_insn (&state, insn);
13427 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
13428 length = get_attr_length (insn);
13431 /* If the instruction is an asm statement or multi-instruction
13432 mips.md patern, the length is only an estimate. Insert an
13433 8 byte alignment after it so that the following instructions
13434 can be handled correctly. */
13435 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
13436 && (recog_memoized (insn) < 0 || length >= 8))
13438 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
13439 next = NEXT_INSN (next);
13440 mips_sim_next_cycle (&state);
13443 else if (length & 4)
13444 aligned_p = !aligned_p;
13449 /* See whether INSN is an aligned label. */
13450 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
13456 /* This structure records that the current function has a LO_SUM
13457 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
13458 the largest offset applied to BASE by all such LO_SUMs. */
13459 struct mips_lo_sum_offset {
13461 HOST_WIDE_INT offset;
13464 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
13467 mips_hash_base (rtx base)
13469 int do_not_record_p;
13471 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
13474 /* Hash-table callbacks for mips_lo_sum_offsets. */
13477 mips_lo_sum_offset_hash (const void *entry)
13479 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
13483 mips_lo_sum_offset_eq (const void *entry, const void *value)
13485 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
13486 (const_rtx) value);
13489 /* Look up symbolic constant X in HTAB, which is a hash table of
13490 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
13491 paired with a recorded LO_SUM, otherwise record X in the table. */
13494 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
13498 struct mips_lo_sum_offset *entry;
13500 /* Split X into a base and offset. */
13501 split_const (x, &base, &offset);
13502 if (UNSPEC_ADDRESS_P (base))
13503 base = UNSPEC_ADDRESS (base);
13505 /* Look up the base in the hash table. */
13506 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
13510 entry = (struct mips_lo_sum_offset *) *slot;
13511 if (option == INSERT)
13515 entry = XNEW (struct mips_lo_sum_offset);
13516 entry->base = base;
13517 entry->offset = INTVAL (offset);
13522 if (INTVAL (offset) > entry->offset)
13523 entry->offset = INTVAL (offset);
13526 return INTVAL (offset) <= entry->offset;
13529 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
13530 Record every LO_SUM in *LOC. */
13533 mips_record_lo_sum (rtx *loc, void *data)
13535 if (GET_CODE (*loc) == LO_SUM)
13536 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
13540 /* Return true if INSN is a SET of an orphaned high-part relocation.
13541 HTAB is a hash table of mips_lo_sum_offsets that describes all the
13542 LO_SUMs in the current function. */
13545 mips_orphaned_high_part_p (htab_t htab, rtx insn)
13547 enum mips_symbol_type type;
13550 set = single_set (insn);
13553 /* Check for %his. */
13555 if (GET_CODE (x) == HIGH
13556 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
13557 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
13559 /* Check for local %gots (and %got_pages, which is redundant but OK). */
13560 if (GET_CODE (x) == UNSPEC
13561 && XINT (x, 1) == UNSPEC_LOAD_GOT
13562 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
13563 SYMBOL_CONTEXT_LEA, &type)
13564 && type == SYMBOL_GOTOFF_PAGE)
13565 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
13570 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
13571 INSN and a previous instruction, avoid it by inserting nops after
13574 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
13575 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
13576 before using the value of that register. *HILO_DELAY counts the
13577 number of instructions since the last hilo hazard (that is,
13578 the number of instructions since the last MFLO or MFHI).
13580 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
13581 for the next instruction.
13583 LO_REG is an rtx for the LO register, used in dependence checking. */
13586 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
13587 rtx *delayed_reg, rtx lo_reg)
13592 pattern = PATTERN (insn);
13594 /* Do not put the whole function in .set noreorder if it contains
13595 an asm statement. We don't know whether there will be hazards
13596 between the asm statement and the gcc-generated code. */
13597 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
13598 cfun->machine->all_noreorder_p = false;
13600 /* Ignore zero-length instructions (barriers and the like). */
13601 ninsns = get_attr_length (insn) / 4;
13605 /* Work out how many nops are needed. Note that we only care about
13606 registers that are explicitly mentioned in the instruction's pattern.
13607 It doesn't matter that calls use the argument registers or that they
13608 clobber hi and lo. */
13609 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
13610 nops = 2 - *hilo_delay;
13611 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
13616 /* Insert the nops between this instruction and the previous one.
13617 Each new nop takes us further from the last hilo hazard. */
13618 *hilo_delay += nops;
13620 emit_insn_after (gen_hazard_nop (), after);
13622 /* Set up the state for the next instruction. */
13623 *hilo_delay += ninsns;
13625 if (INSN_CODE (insn) >= 0)
13626 switch (get_attr_hazard (insn))
13636 set = single_set (insn);
13638 *delayed_reg = SET_DEST (set);
13643 /* Go through the instruction stream and insert nops where necessary.
13644 Also delete any high-part relocations whose partnering low parts
13645 are now all dead. See if the whole function can then be put into
13646 .set noreorder and .set nomacro. */
13649 mips_reorg_process_insns (void)
13651 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
13655 /* Force all instructions to be split into their final form. */
13656 split_all_insns_noflow ();
13658 /* Recalculate instruction lengths without taking nops into account. */
13659 cfun->machine->ignore_hazard_length_p = true;
13660 shorten_branches (get_insns ());
13662 cfun->machine->all_noreorder_p = true;
13664 /* We don't track MIPS16 PC-relative offsets closely enough to make
13665 a good job of "set .noreorder" code in MIPS16 mode. */
13667 cfun->machine->all_noreorder_p = false;
13669 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
13670 if (!TARGET_EXPLICIT_RELOCS)
13671 cfun->machine->all_noreorder_p = false;
13673 /* Profiled functions can't be all noreorder because the profiler
13674 support uses assembler macros. */
13676 cfun->machine->all_noreorder_p = false;
13678 /* Code compiled with -mfix-vr4120 can't be all noreorder because
13679 we rely on the assembler to work around some errata. */
13680 if (TARGET_FIX_VR4120)
13681 cfun->machine->all_noreorder_p = false;
13683 /* The same is true for -mfix-vr4130 if we might generate MFLO or
13684 MFHI instructions. Note that we avoid using MFLO and MFHI if
13685 the VR4130 MACC and DMACC instructions are available instead;
13686 see the *mfhilo_{si,di}_macc patterns. */
13687 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
13688 cfun->machine->all_noreorder_p = false;
13690 htab = htab_create (37, mips_lo_sum_offset_hash,
13691 mips_lo_sum_offset_eq, free);
13693 /* Make a first pass over the instructions, recording all the LO_SUMs. */
13694 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13695 FOR_EACH_SUBINSN (subinsn, insn)
13696 if (INSN_P (subinsn))
13697 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
13702 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
13704 /* Make a second pass over the instructions. Delete orphaned
13705 high-part relocations or turn them into NOPs. Avoid hazards
13706 by inserting NOPs. */
13707 for (insn = get_insns (); insn != 0; insn = next_insn)
13709 next_insn = NEXT_INSN (insn);
13712 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
13714 /* If we find an orphaned high-part relocation in a delay
13715 slot, it's easier to turn that instruction into a NOP than
13716 to delete it. The delay slot will be a NOP either way. */
13717 FOR_EACH_SUBINSN (subinsn, insn)
13718 if (INSN_P (subinsn))
13720 if (mips_orphaned_high_part_p (htab, subinsn))
13722 PATTERN (subinsn) = gen_nop ();
13723 INSN_CODE (subinsn) = CODE_FOR_nop;
13725 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
13726 &delayed_reg, lo_reg);
13732 /* INSN is a single instruction. Delete it if it's an
13733 orphaned high-part relocation. */
13734 if (mips_orphaned_high_part_p (htab, insn))
13735 delete_insn (insn);
13736 /* Also delete cache barriers if the last instruction
13737 was an annulled branch. INSN will not be speculatively
13739 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
13741 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
13742 delete_insn (insn);
13745 mips_avoid_hazard (last_insn, insn, &hilo_delay,
13746 &delayed_reg, lo_reg);
13753 htab_delete (htab);
13756 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
13761 mips16_lay_out_constants ();
13762 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
13763 r10k_insert_cache_barriers ();
13764 if (optimize > 0 && flag_delayed_branch)
13765 dbr_schedule (get_insns ());
13766 mips_reorg_process_insns ();
13768 && TARGET_EXPLICIT_RELOCS
13770 && TARGET_VR4130_ALIGN)
13771 vr4130_align_insns ();
13774 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
13775 in order to avoid duplicating too much logic from elsewhere. */
13778 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13779 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13782 rtx this_rtx, temp1, temp2, insn, fnaddr;
13783 bool use_sibcall_p;
13785 /* Pretend to be a post-reload pass while generating rtl. */
13786 reload_completed = 1;
13788 /* Mark the end of the (empty) prologue. */
13789 emit_note (NOTE_INSN_PROLOGUE_END);
13791 /* Determine if we can use a sibcall to call FUNCTION directly. */
13792 fnaddr = XEXP (DECL_RTL (function), 0);
13793 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
13794 && const_call_insn_operand (fnaddr, Pmode));
13796 /* Determine if we need to load FNADDR from the GOT. */
13798 && (mips_got_symbol_type_p
13799 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
13801 /* Pick a global pointer. Use a call-clobbered register if
13802 TARGET_CALL_SAVED_GP. */
13803 cfun->machine->global_pointer
13804 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
13805 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
13807 /* Set up the global pointer for n32 or n64 abicalls. */
13808 mips_emit_loadgp ();
13811 /* We need two temporary registers in some cases. */
13812 temp1 = gen_rtx_REG (Pmode, 2);
13813 temp2 = gen_rtx_REG (Pmode, 3);
13815 /* Find out which register contains the "this" pointer. */
13816 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13817 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
13819 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
13821 /* Add DELTA to THIS_RTX. */
13824 rtx offset = GEN_INT (delta);
13825 if (!SMALL_OPERAND (delta))
13827 mips_emit_move (temp1, offset);
13830 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
13833 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
13834 if (vcall_offset != 0)
13838 /* Set TEMP1 to *THIS_RTX. */
13839 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
13841 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
13842 addr = mips_add_offset (temp2, temp1, vcall_offset);
13844 /* Load the offset and add it to THIS_RTX. */
13845 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
13846 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
13849 /* Jump to the target function. Use a sibcall if direct jumps are
13850 allowed, otherwise load the address into a register first. */
13853 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
13854 SIBLING_CALL_P (insn) = 1;
13858 /* This is messy. GAS treats "la $25,foo" as part of a call
13859 sequence and may allow a global "foo" to be lazily bound.
13860 The general move patterns therefore reject this combination.
13862 In this context, lazy binding would actually be OK
13863 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
13864 TARGET_CALL_SAVED_GP; see mips_load_call_address.
13865 We must therefore load the address via a temporary
13866 register if mips_dangerous_for_la25_p.
13868 If we jump to the temporary register rather than $25,
13869 the assembler can use the move insn to fill the jump's
13872 We can use the same technique for MIPS16 code, where $25
13873 is not a valid JR register. */
13874 if (TARGET_USE_PIC_FN_ADDR_REG
13876 && !mips_dangerous_for_la25_p (fnaddr))
13877 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
13878 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
13880 if (TARGET_USE_PIC_FN_ADDR_REG
13881 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
13882 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
13883 emit_jump_insn (gen_indirect_jump (temp1));
13886 /* Run just enough of rest_of_compilation. This sequence was
13887 "borrowed" from alpha.c. */
13888 insn = get_insns ();
13889 insn_locators_alloc ();
13890 split_all_insns_noflow ();
13891 mips16_lay_out_constants ();
13892 shorten_branches (insn);
13893 final_start_function (insn, file, 1);
13894 final (insn, file, 1);
13895 final_end_function ();
13896 free_after_compilation (cfun);
13898 /* Clean up the vars set above. Note that final_end_function resets
13899 the global pointer for us. */
13900 reload_completed = 0;
13903 /* The last argument passed to mips_set_mips16_mode, or negative if the
13904 function hasn't been called yet.
13906 There are two copies of this information. One is saved and restored
13907 by the PCH process while the other is specific to this compiler
13908 invocation. The information calculated by mips_set_mips16_mode
13909 is invalid unless the two variables are the same. */
13910 static int was_mips16_p = -1;
13911 static GTY(()) int was_mips16_pch_p = -1;
13913 /* Set up the target-dependent global state so that it matches the
13914 current function's ISA mode. */
13917 mips_set_mips16_mode (int mips16_p)
13919 if (mips16_p == was_mips16_p
13920 && mips16_p == was_mips16_pch_p)
13923 /* Restore base settings of various flags. */
13924 target_flags = mips_base_target_flags;
13925 flag_schedule_insns = mips_base_schedule_insns;
13926 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
13927 flag_move_loop_invariants = mips_base_move_loop_invariants;
13928 align_loops = mips_base_align_loops;
13929 align_jumps = mips_base_align_jumps;
13930 align_functions = mips_base_align_functions;
13934 /* Switch to MIPS16 mode. */
13935 target_flags |= MASK_MIPS16;
13937 /* Don't run the scheduler before reload, since it tends to
13938 increase register pressure. */
13939 flag_schedule_insns = 0;
13941 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
13942 the whole function to be in a single section. */
13943 flag_reorder_blocks_and_partition = 0;
13945 /* Don't move loop invariants, because it tends to increase
13946 register pressure. It also introduces an extra move in cases
13947 where the constant is the first operand in a two-operand binary
13948 instruction, or when it forms a register argument to a functon
13950 flag_move_loop_invariants = 0;
13952 target_flags |= MASK_EXPLICIT_RELOCS;
13954 /* Experiments suggest we get the best overall section-anchor
13955 results from using the range of an unextended LW or SW. Code
13956 that makes heavy use of byte or short accesses can do better
13957 with ranges of 0...31 and 0...63 respectively, but most code is
13958 sensitive to the range of LW and SW instead. */
13959 targetm.min_anchor_offset = 0;
13960 targetm.max_anchor_offset = 127;
13962 targetm.const_anchor = 0;
13964 if (flag_pic && !TARGET_OLDABI)
13965 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
13968 sorry ("MIPS16 -mxgot code");
13970 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
13971 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
13975 /* Switch to normal (non-MIPS16) mode. */
13976 target_flags &= ~MASK_MIPS16;
13978 /* Provide default values for align_* for 64-bit targets. */
13981 if (align_loops == 0)
13983 if (align_jumps == 0)
13985 if (align_functions == 0)
13986 align_functions = 8;
13989 targetm.min_anchor_offset = -32768;
13990 targetm.max_anchor_offset = 32767;
13992 targetm.const_anchor = 0x8000;
13995 /* (Re)initialize MIPS target internals for new ISA. */
13996 mips_init_relocs ();
13998 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
13999 /* Reinitialize target-dependent state. */
14002 was_mips16_p = mips16_p;
14003 was_mips16_pch_p = mips16_p;
14006 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
14007 function should use the MIPS16 ISA and switch modes accordingly. */
14010 mips_set_current_function (tree fndecl)
14012 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
14015 /* Allocate a chunk of memory for per-function machine-dependent data. */
14017 static struct machine_function *
14018 mips_init_machine_status (void)
14020 return ((struct machine_function *)
14021 ggc_alloc_cleared (sizeof (struct machine_function)));
14024 /* Return the processor associated with the given ISA level, or null
14025 if the ISA isn't valid. */
14027 static const struct mips_cpu_info *
14028 mips_cpu_info_from_isa (int isa)
14032 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
14033 if (mips_cpu_info_table[i].isa == isa)
14034 return mips_cpu_info_table + i;
14039 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14040 with a final "000" replaced by "k". Ignore case.
14042 Note: this function is shared between GCC and GAS. */
14045 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
14047 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
14048 given++, canonical++;
14050 return ((*given == 0 && *canonical == 0)
14051 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
14054 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
14055 CPU name. We've traditionally allowed a lot of variation here.
14057 Note: this function is shared between GCC and GAS. */
14060 mips_matching_cpu_name_p (const char *canonical, const char *given)
14062 /* First see if the name matches exactly, or with a final "000"
14063 turned into "k". */
14064 if (mips_strict_matching_cpu_name_p (canonical, given))
14067 /* If not, try comparing based on numerical designation alone.
14068 See if GIVEN is an unadorned number, or 'r' followed by a number. */
14069 if (TOLOWER (*given) == 'r')
14071 if (!ISDIGIT (*given))
14074 /* Skip over some well-known prefixes in the canonical name,
14075 hoping to find a number there too. */
14076 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
14078 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
14080 else if (TOLOWER (canonical[0]) == 'r')
14083 return mips_strict_matching_cpu_name_p (canonical, given);
14086 /* Return the mips_cpu_info entry for the processor or ISA given
14087 by CPU_STRING. Return null if the string isn't recognized.
14089 A similar function exists in GAS. */
14091 static const struct mips_cpu_info *
14092 mips_parse_cpu (const char *cpu_string)
14097 /* In the past, we allowed upper-case CPU names, but it doesn't
14098 work well with the multilib machinery. */
14099 for (s = cpu_string; *s != 0; s++)
14102 warning (0, "CPU names must be lower case");
14106 /* 'from-abi' selects the most compatible architecture for the given
14107 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
14108 EABIs, we have to decide whether we're using the 32-bit or 64-bit
14110 if (strcasecmp (cpu_string, "from-abi") == 0)
14111 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
14112 : ABI_NEEDS_64BIT_REGS ? 3
14113 : (TARGET_64BIT ? 3 : 1));
14115 /* 'default' has traditionally been a no-op. Probably not very useful. */
14116 if (strcasecmp (cpu_string, "default") == 0)
14119 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
14120 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
14121 return mips_cpu_info_table + i;
14126 /* Set up globals to generate code for the ISA or processor
14127 described by INFO. */
14130 mips_set_architecture (const struct mips_cpu_info *info)
14134 mips_arch_info = info;
14135 mips_arch = info->cpu;
14136 mips_isa = info->isa;
14140 /* Likewise for tuning. */
14143 mips_set_tune (const struct mips_cpu_info *info)
14147 mips_tune_info = info;
14148 mips_tune = info->cpu;
14152 /* Implement TARGET_HANDLE_OPTION. */
14155 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
14160 if (strcmp (arg, "32") == 0)
14162 else if (strcmp (arg, "o64") == 0)
14163 mips_abi = ABI_O64;
14164 else if (strcmp (arg, "n32") == 0)
14165 mips_abi = ABI_N32;
14166 else if (strcmp (arg, "64") == 0)
14168 else if (strcmp (arg, "eabi") == 0)
14169 mips_abi = ABI_EABI;
14176 return mips_parse_cpu (arg) != 0;
14179 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
14180 return mips_isa_option_info != 0;
14182 case OPT_mno_flush_func:
14183 mips_cache_flush_func = NULL;
14186 case OPT_mcode_readable_:
14187 if (strcmp (arg, "yes") == 0)
14188 mips_code_readable = CODE_READABLE_YES;
14189 else if (strcmp (arg, "pcrel") == 0)
14190 mips_code_readable = CODE_READABLE_PCREL;
14191 else if (strcmp (arg, "no") == 0)
14192 mips_code_readable = CODE_READABLE_NO;
14197 case OPT_mr10k_cache_barrier_:
14198 if (strcmp (arg, "load-store") == 0)
14199 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
14200 else if (strcmp (arg, "store") == 0)
14201 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
14202 else if (strcmp (arg, "none") == 0)
14203 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
14213 /* Implement OVERRIDE_OPTIONS. */
14216 mips_override_options (void)
14218 int i, start, regno, mode;
14220 /* Process flags as though we were generating non-MIPS16 code. */
14221 mips_base_mips16 = TARGET_MIPS16;
14222 target_flags &= ~MASK_MIPS16;
14224 #ifdef SUBTARGET_OVERRIDE_OPTIONS
14225 SUBTARGET_OVERRIDE_OPTIONS;
14228 /* Set the small data limit. */
14229 mips_small_data_threshold = (g_switch_set
14231 : MIPS_DEFAULT_GVALUE);
14233 /* The following code determines the architecture and register size.
14234 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
14235 The GAS and GCC code should be kept in sync as much as possible. */
14237 if (mips_arch_string != 0)
14238 mips_set_architecture (mips_parse_cpu (mips_arch_string));
14240 if (mips_isa_option_info != 0)
14242 if (mips_arch_info == 0)
14243 mips_set_architecture (mips_isa_option_info);
14244 else if (mips_arch_info->isa != mips_isa_option_info->isa)
14245 error ("%<-%s%> conflicts with the other architecture options, "
14246 "which specify a %s processor",
14247 mips_isa_option_info->name,
14248 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
14251 if (mips_arch_info == 0)
14253 #ifdef MIPS_CPU_STRING_DEFAULT
14254 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
14256 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
14260 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
14261 error ("%<-march=%s%> is not compatible with the selected ABI",
14262 mips_arch_info->name);
14264 /* Optimize for mips_arch, unless -mtune selects a different processor. */
14265 if (mips_tune_string != 0)
14266 mips_set_tune (mips_parse_cpu (mips_tune_string));
14268 if (mips_tune_info == 0)
14269 mips_set_tune (mips_arch_info);
14271 if ((target_flags_explicit & MASK_64BIT) != 0)
14273 /* The user specified the size of the integer registers. Make sure
14274 it agrees with the ABI and ISA. */
14275 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
14276 error ("%<-mgp64%> used with a 32-bit processor");
14277 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
14278 error ("%<-mgp32%> used with a 64-bit ABI");
14279 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
14280 error ("%<-mgp64%> used with a 32-bit ABI");
14284 /* Infer the integer register size from the ABI and processor.
14285 Restrict ourselves to 32-bit registers if that's all the
14286 processor has, or if the ABI cannot handle 64-bit registers. */
14287 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
14288 target_flags &= ~MASK_64BIT;
14290 target_flags |= MASK_64BIT;
14293 if ((target_flags_explicit & MASK_FLOAT64) != 0)
14295 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
14296 error ("unsupported combination: %s", "-mfp64 -msingle-float");
14297 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
14298 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
14299 else if (!TARGET_64BIT && TARGET_FLOAT64)
14301 if (!ISA_HAS_MXHC1)
14302 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
14303 " the target supports the mfhc1 and mthc1 instructions");
14304 else if (mips_abi != ABI_32)
14305 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
14311 /* -msingle-float selects 32-bit float registers. Otherwise the
14312 float registers should be the same size as the integer ones. */
14313 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
14314 target_flags |= MASK_FLOAT64;
14316 target_flags &= ~MASK_FLOAT64;
14319 /* End of code shared with GAS. */
14321 /* If no -mlong* option was given, infer it from the other options. */
14322 if ((target_flags_explicit & MASK_LONG64) == 0)
14324 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
14325 target_flags |= MASK_LONG64;
14327 target_flags &= ~MASK_LONG64;
14330 if (!TARGET_OLDABI)
14331 flag_pcc_struct_return = 0;
14333 /* Decide which rtx_costs structure to use. */
14335 mips_cost = &mips_rtx_cost_optimize_size;
14337 mips_cost = &mips_rtx_cost_data[mips_tune];
14339 /* If the user hasn't specified a branch cost, use the processor's
14341 if (mips_branch_cost == 0)
14342 mips_branch_cost = mips_cost->branch_cost;
14344 /* If neither -mbranch-likely nor -mno-branch-likely was given
14345 on the command line, set MASK_BRANCHLIKELY based on the target
14346 architecture and tuning flags. Annulled delay slots are a
14347 size win, so we only consider the processor-specific tuning
14348 for !optimize_size. */
14349 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
14351 if (ISA_HAS_BRANCHLIKELY
14353 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
14354 target_flags |= MASK_BRANCHLIKELY;
14356 target_flags &= ~MASK_BRANCHLIKELY;
14358 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
14359 warning (0, "the %qs architecture does not support branch-likely"
14360 " instructions", mips_arch_info->name);
14362 /* The effect of -mabicalls isn't defined for the EABI. */
14363 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
14365 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
14366 target_flags &= ~MASK_ABICALLS;
14369 if (TARGET_ABICALLS_PIC2)
14370 /* We need to set flag_pic for executables as well as DSOs
14371 because we may reference symbols that are not defined in
14372 the final executable. (MIPS does not use things like
14373 copy relocs, for example.)
14375 There is a body of code that uses __PIC__ to distinguish
14376 between -mabicalls and -mno-abicalls code. The non-__PIC__
14377 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
14378 long as any indirect jumps use $25. */
14381 /* -mvr4130-align is a "speed over size" optimization: it usually produces
14382 faster code, but at the expense of more nops. Enable it at -O3 and
14384 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
14385 target_flags |= MASK_VR4130_ALIGN;
14387 /* Prefer a call to memcpy over inline code when optimizing for size,
14388 though see MOVE_RATIO in mips.h. */
14389 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
14390 target_flags |= MASK_MEMCPY;
14392 /* If we have a nonzero small-data limit, check that the -mgpopt
14393 setting is consistent with the other target flags. */
14394 if (mips_small_data_threshold > 0)
14398 if (!TARGET_EXPLICIT_RELOCS)
14399 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
14401 TARGET_LOCAL_SDATA = false;
14402 TARGET_EXTERN_SDATA = false;
14406 if (TARGET_VXWORKS_RTP)
14407 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
14409 if (TARGET_ABICALLS)
14410 warning (0, "cannot use small-data accesses for %qs",
14415 #ifdef MIPS_TFMODE_FORMAT
14416 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
14419 /* Make sure that the user didn't turn off paired single support when
14420 MIPS-3D support is requested. */
14422 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
14423 && !TARGET_PAIRED_SINGLE_FLOAT)
14424 error ("%<-mips3d%> requires %<-mpaired-single%>");
14426 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
14428 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
14430 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
14431 and TARGET_HARD_FLOAT_ABI are both true. */
14432 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
14433 error ("%qs must be used with %qs",
14434 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
14435 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
14437 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
14439 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
14440 warning (0, "the %qs architecture does not support paired-single"
14441 " instructions", mips_arch_info->name);
14443 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14444 && !TARGET_CACHE_BUILTIN)
14446 error ("%qs requires a target that provides the %qs instruction",
14447 "-mr10k-cache-barrier", "cache");
14448 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
14451 /* If TARGET_DSPR2, enable MASK_DSP. */
14453 target_flags |= MASK_DSP;
14455 /* .eh_frame addresses should be the same width as a C pointer.
14456 Most MIPS ABIs support only one pointer size, so the assembler
14457 will usually know exactly how big an .eh_frame address is.
14459 Unfortunately, this is not true of the 64-bit EABI. The ABI was
14460 originally defined to use 64-bit pointers (i.e. it is LP64), and
14461 this is still the default mode. However, we also support an n32-like
14462 ILP32 mode, which is selected by -mlong32. The problem is that the
14463 assembler has traditionally not had an -mlong option, so it has
14464 traditionally not known whether we're using the ILP32 or LP64 form.
14466 As it happens, gas versions up to and including 2.19 use _32-bit_
14467 addresses for EABI64 .cfi_* directives. This is wrong for the
14468 default LP64 mode, so we can't use the directives by default.
14469 Moreover, since gas's current behavior is at odds with gcc's
14470 default behavior, it seems unwise to rely on future versions
14471 of gas behaving the same way. We therefore avoid using .cfi
14472 directives for -mlong32 as well. */
14473 if (mips_abi == ABI_EABI && TARGET_64BIT)
14474 flag_dwarf2_cfi_asm = 0;
14476 mips_init_print_operand_punct ();
14478 /* Set up array to map GCC register number to debug register number.
14479 Ignore the special purpose register numbers. */
14481 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14483 mips_dbx_regno[i] = INVALID_REGNUM;
14484 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
14485 mips_dwarf_regno[i] = i;
14487 mips_dwarf_regno[i] = INVALID_REGNUM;
14490 start = GP_DBX_FIRST - GP_REG_FIRST;
14491 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
14492 mips_dbx_regno[i] = i + start;
14494 start = FP_DBX_FIRST - FP_REG_FIRST;
14495 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
14496 mips_dbx_regno[i] = i + start;
14498 /* Accumulator debug registers use big-endian ordering. */
14499 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
14500 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
14501 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
14502 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
14503 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
14505 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
14506 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
14509 /* Set up mips_hard_regno_mode_ok. */
14510 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
14511 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
14512 mips_hard_regno_mode_ok[mode][regno]
14513 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
14515 /* Function to allocate machine-dependent function status. */
14516 init_machine_status = &mips_init_machine_status;
14518 /* Default to working around R4000 errata only if the processor
14519 was selected explicitly. */
14520 if ((target_flags_explicit & MASK_FIX_R4000) == 0
14521 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
14522 target_flags |= MASK_FIX_R4000;
14524 /* Default to working around R4400 errata only if the processor
14525 was selected explicitly. */
14526 if ((target_flags_explicit & MASK_FIX_R4400) == 0
14527 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
14528 target_flags |= MASK_FIX_R4400;
14530 /* Default to working around R10000 errata only if the processor
14531 was selected explicitly. */
14532 if ((target_flags_explicit & MASK_FIX_R10000) == 0
14533 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
14534 target_flags |= MASK_FIX_R10000;
14536 /* Make sure that branch-likely instructions available when using
14537 -mfix-r10000. The instructions are not available if either:
14539 1. -mno-branch-likely was passed.
14540 2. The selected ISA does not support branch-likely and
14541 the command line does not include -mbranch-likely. */
14542 if (TARGET_FIX_R10000
14543 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
14544 ? !ISA_HAS_BRANCHLIKELY
14545 : !TARGET_BRANCHLIKELY))
14546 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
14548 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
14550 warning (0, "the %qs architecture does not support the synci "
14551 "instruction", mips_arch_info->name);
14552 target_flags &= ~MASK_SYNCI;
14555 /* Save base state of options. */
14556 mips_base_target_flags = target_flags;
14557 mips_base_schedule_insns = flag_schedule_insns;
14558 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
14559 mips_base_move_loop_invariants = flag_move_loop_invariants;
14560 mips_base_align_loops = align_loops;
14561 mips_base_align_jumps = align_jumps;
14562 mips_base_align_functions = align_functions;
14564 /* Now select the ISA mode.
14566 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
14567 MIPS16 mode afterwards if need be. */
14568 mips_set_mips16_mode (false);
14571 /* Swap the register information for registers I and I + 1, which
14572 currently have the wrong endianness. Note that the registers'
14573 fixedness and call-clobberedness might have been set on the
14577 mips_swap_registers (unsigned int i)
14582 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
14583 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
14585 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
14586 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
14587 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
14588 SWAP_STRING (reg_names[i], reg_names[i + 1]);
14594 /* Implement CONDITIONAL_REGISTER_USAGE. */
14597 mips_conditional_register_usage (void)
14602 /* These DSP control register fields are global. */
14603 global_regs[CCDSP_PO_REGNUM] = 1;
14604 global_regs[CCDSP_SC_REGNUM] = 1;
14610 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
14611 fixed_regs[regno] = call_used_regs[regno] = 1;
14613 if (!TARGET_HARD_FLOAT)
14617 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
14618 fixed_regs[regno] = call_used_regs[regno] = 1;
14619 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
14620 fixed_regs[regno] = call_used_regs[regno] = 1;
14622 else if (! ISA_HAS_8CC)
14626 /* We only have a single condition-code register. We implement
14627 this by fixing all the condition-code registers and generating
14628 RTL that refers directly to ST_REG_FIRST. */
14629 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
14630 fixed_regs[regno] = call_used_regs[regno] = 1;
14632 /* In MIPS16 mode, we permit the $t temporary registers to be used
14633 for reload. We prohibit the unused $s registers, since they
14634 are call-saved, and saving them via a MIPS16 register would
14635 probably waste more time than just reloading the value. */
14638 fixed_regs[18] = call_used_regs[18] = 1;
14639 fixed_regs[19] = call_used_regs[19] = 1;
14640 fixed_regs[20] = call_used_regs[20] = 1;
14641 fixed_regs[21] = call_used_regs[21] = 1;
14642 fixed_regs[22] = call_used_regs[22] = 1;
14643 fixed_regs[23] = call_used_regs[23] = 1;
14644 fixed_regs[26] = call_used_regs[26] = 1;
14645 fixed_regs[27] = call_used_regs[27] = 1;
14646 fixed_regs[30] = call_used_regs[30] = 1;
14648 /* $f20-$f23 are call-clobbered for n64. */
14649 if (mips_abi == ABI_64)
14652 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
14653 call_really_used_regs[regno] = call_used_regs[regno] = 1;
14655 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
14657 if (mips_abi == ABI_N32)
14660 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
14661 call_really_used_regs[regno] = call_used_regs[regno] = 1;
14663 /* Make sure that double-register accumulator values are correctly
14664 ordered for the current endianness. */
14665 if (TARGET_LITTLE_ENDIAN)
14667 unsigned int regno;
14669 mips_swap_registers (MD_REG_FIRST);
14670 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
14671 mips_swap_registers (regno);
14675 /* Initialize vector TARGET to VALS. */
14678 mips_expand_vector_init (rtx target, rtx vals)
14680 enum machine_mode mode;
14681 enum machine_mode inner;
14682 unsigned int i, n_elts;
14685 mode = GET_MODE (target);
14686 inner = GET_MODE_INNER (mode);
14687 n_elts = GET_MODE_NUNITS (mode);
14689 gcc_assert (VECTOR_MODE_P (mode));
14691 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
14692 for (i = 0; i < n_elts; i++)
14693 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
14694 XVECEXP (vals, 0, i));
14696 emit_move_insn (target, mem);
14699 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
14700 other registers for instructions for which it is possible. This
14701 encourages the compiler to use CMP in cases where an XOR would
14702 require some register shuffling. */
14705 mips_order_regs_for_local_alloc (void)
14709 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
14710 reg_alloc_order[i] = i;
14714 /* It really doesn't matter where we put register 0, since it is
14715 a fixed register anyhow. */
14716 reg_alloc_order[0] = 24;
14717 reg_alloc_order[24] = 0;
14721 /* Implement EPILOGUE_USES. */
14724 mips_epilogue_uses (unsigned int regno)
14726 /* Say that the epilogue uses the return address register. Note that
14727 in the case of sibcalls, the values "used by the epilogue" are
14728 considered live at the start of the called function. */
14732 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
14733 See the comment above load_call<mode> for details. */
14734 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
14737 /* An interrupt handler must preserve some registers that are
14738 ordinarily call-clobbered. */
14739 if (cfun->machine->interrupt_handler_p
14740 && mips_interrupt_extra_call_saved_reg_p (regno))
14746 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
14749 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
14751 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
14755 /* Implement FINAL_PRESCAN_INSN. */
14758 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
14762 /* We need to emit ".set noat" before an instruction that accesses
14764 if (recog_memoized (insn) >= 0)
14765 for (i = 0; i < noperands; i++)
14766 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
14767 if (set_noat++ == 0)
14768 fprintf (asm_out_file, "\t.set\tnoat\n");
14771 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
14774 mips_final_postscan_insn (FILE *file, rtx insn, rtx *opvec, int noperands)
14778 /* Close any ".set noat" block opened by mips_final_prescan_insn. */
14779 if (recog_memoized (insn) >= 0)
14780 for (i = 0; i < noperands; i++)
14781 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
14782 if (--set_noat == 0)
14783 fprintf (file, "\t.set\tat\n");
14786 /* Initialize the GCC target structure. */
14787 #undef TARGET_ASM_ALIGNED_HI_OP
14788 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
14789 #undef TARGET_ASM_ALIGNED_SI_OP
14790 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
14791 #undef TARGET_ASM_ALIGNED_DI_OP
14792 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
14794 #undef TARGET_LEGITIMIZE_ADDRESS
14795 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
14797 #undef TARGET_ASM_FUNCTION_PROLOGUE
14798 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
14799 #undef TARGET_ASM_FUNCTION_EPILOGUE
14800 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
14801 #undef TARGET_ASM_SELECT_RTX_SECTION
14802 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
14803 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
14804 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
14806 #undef TARGET_SCHED_INIT
14807 #define TARGET_SCHED_INIT mips_sched_init
14808 #undef TARGET_SCHED_REORDER
14809 #define TARGET_SCHED_REORDER mips_sched_reorder
14810 #undef TARGET_SCHED_REORDER2
14811 #define TARGET_SCHED_REORDER2 mips_sched_reorder
14812 #undef TARGET_SCHED_VARIABLE_ISSUE
14813 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
14814 #undef TARGET_SCHED_ADJUST_COST
14815 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
14816 #undef TARGET_SCHED_ISSUE_RATE
14817 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
14818 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
14819 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
14820 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
14821 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
14822 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
14823 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
14824 mips_multipass_dfa_lookahead
14826 #undef TARGET_DEFAULT_TARGET_FLAGS
14827 #define TARGET_DEFAULT_TARGET_FLAGS \
14829 | TARGET_CPU_DEFAULT \
14830 | TARGET_ENDIAN_DEFAULT \
14831 | TARGET_FP_EXCEPTIONS_DEFAULT \
14832 | MASK_CHECK_ZERO_DIV \
14834 #undef TARGET_HANDLE_OPTION
14835 #define TARGET_HANDLE_OPTION mips_handle_option
14837 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
14838 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
14840 #undef TARGET_INSERT_ATTRIBUTES
14841 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
14842 #undef TARGET_MERGE_DECL_ATTRIBUTES
14843 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
14844 #undef TARGET_SET_CURRENT_FUNCTION
14845 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
14847 #undef TARGET_VALID_POINTER_MODE
14848 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
14849 #undef TARGET_RTX_COSTS
14850 #define TARGET_RTX_COSTS mips_rtx_costs
14851 #undef TARGET_ADDRESS_COST
14852 #define TARGET_ADDRESS_COST mips_address_cost
14854 #undef TARGET_IN_SMALL_DATA_P
14855 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
14857 #undef TARGET_MACHINE_DEPENDENT_REORG
14858 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
14860 #undef TARGET_ASM_FILE_START
14861 #define TARGET_ASM_FILE_START mips_file_start
14862 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
14863 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
14865 #undef TARGET_INIT_LIBFUNCS
14866 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
14868 #undef TARGET_BUILD_BUILTIN_VA_LIST
14869 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
14870 #undef TARGET_EXPAND_BUILTIN_VA_START
14871 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
14872 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
14873 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
14875 #undef TARGET_PROMOTE_FUNCTION_MODE
14876 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
14877 #undef TARGET_PROMOTE_PROTOTYPES
14878 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
14880 #undef TARGET_RETURN_IN_MEMORY
14881 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
14882 #undef TARGET_RETURN_IN_MSB
14883 #define TARGET_RETURN_IN_MSB mips_return_in_msb
14885 #undef TARGET_ASM_OUTPUT_MI_THUNK
14886 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
14887 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
14888 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
14890 #undef TARGET_SETUP_INCOMING_VARARGS
14891 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
14892 #undef TARGET_STRICT_ARGUMENT_NAMING
14893 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
14894 #undef TARGET_MUST_PASS_IN_STACK
14895 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
14896 #undef TARGET_PASS_BY_REFERENCE
14897 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
14898 #undef TARGET_CALLEE_COPIES
14899 #define TARGET_CALLEE_COPIES mips_callee_copies
14900 #undef TARGET_ARG_PARTIAL_BYTES
14901 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
14903 #undef TARGET_MODE_REP_EXTENDED
14904 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
14906 #undef TARGET_VECTOR_MODE_SUPPORTED_P
14907 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
14909 #undef TARGET_SCALAR_MODE_SUPPORTED_P
14910 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
14912 #undef TARGET_INIT_BUILTINS
14913 #define TARGET_INIT_BUILTINS mips_init_builtins
14914 #undef TARGET_EXPAND_BUILTIN
14915 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
14917 #undef TARGET_HAVE_TLS
14918 #define TARGET_HAVE_TLS HAVE_AS_TLS
14920 #undef TARGET_CANNOT_FORCE_CONST_MEM
14921 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
14923 #undef TARGET_ENCODE_SECTION_INFO
14924 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
14926 #undef TARGET_ATTRIBUTE_TABLE
14927 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
14928 /* All our function attributes are related to how out-of-line copies should
14929 be compiled or called. They don't in themselves prevent inlining. */
14930 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
14931 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
14933 #undef TARGET_EXTRA_LIVE_ON_ENTRY
14934 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
14936 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
14937 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
14938 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
14939 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
14941 #undef TARGET_COMP_TYPE_ATTRIBUTES
14942 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
14944 #ifdef HAVE_AS_DTPRELWORD
14945 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14946 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
14948 #undef TARGET_DWARF_REGISTER_SPAN
14949 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
14951 #undef TARGET_IRA_COVER_CLASSES
14952 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
14954 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
14955 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
14957 #undef TARGET_LEGITIMATE_ADDRESS_P
14958 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
14960 #undef TARGET_FRAME_POINTER_REQUIRED
14961 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
14963 struct gcc_target targetm = TARGET_INITIALIZER;
14965 #include "gt-mips.h"