1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Classifies an address.
132 A natural register + offset address. The register satisfies
133 mips_valid_base_register_p and the offset is a const_arith_operand.
136 A LO_SUM rtx. The first operand is a valid base register and
137 the second operand is a symbolic address.
140 A signed 16-bit constant address.
143 A constant symbolic address. */
144 enum mips_address_type {
151 /* Enumerates the setting of the -mr10k-cache-barrier option. */
152 enum mips_r10k_cache_barrier_setting {
153 R10K_CACHE_BARRIER_NONE,
154 R10K_CACHE_BARRIER_STORE,
155 R10K_CACHE_BARRIER_LOAD_STORE
158 /* Macros to create an enumeration identifier for a function prototype. */
159 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
160 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
161 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
162 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
164 /* Classifies the prototype of a built-in function. */
165 enum mips_function_type {
166 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
167 #include "config/mips/mips-ftypes.def"
168 #undef DEF_MIPS_FTYPE
172 /* Specifies how a built-in function should be converted into rtl. */
173 enum mips_builtin_type {
174 /* The function corresponds directly to an .md pattern. The return
175 value is mapped to operand 0 and the arguments are mapped to
176 operands 1 and above. */
179 /* The function corresponds directly to an .md pattern. There is no return
180 value and the arguments are mapped to operands 0 and above. */
181 MIPS_BUILTIN_DIRECT_NO_TARGET,
183 /* The function corresponds to a comparison instruction followed by
184 a mips_cond_move_tf_ps pattern. The first two arguments are the
185 values to compare and the second two arguments are the vector
186 operands for the movt.ps or movf.ps instruction (in assembly order). */
190 /* The function corresponds to a V2SF comparison instruction. Operand 0
191 of this instruction is the result of the comparison, which has mode
192 CCV2 or CCV4. The function arguments are mapped to operands 1 and
193 above. The function's return value is an SImode boolean that is
194 true under the following conditions:
196 MIPS_BUILTIN_CMP_ANY: one of the registers is true
197 MIPS_BUILTIN_CMP_ALL: all of the registers are true
198 MIPS_BUILTIN_CMP_LOWER: the first register is true
199 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
200 MIPS_BUILTIN_CMP_ANY,
201 MIPS_BUILTIN_CMP_ALL,
202 MIPS_BUILTIN_CMP_UPPER,
203 MIPS_BUILTIN_CMP_LOWER,
205 /* As above, but the instruction only sets a single $fcc register. */
206 MIPS_BUILTIN_CMP_SINGLE,
208 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
209 MIPS_BUILTIN_BPOSGE32
212 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
213 #define MIPS_FP_CONDITIONS(MACRO) \
231 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
232 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
233 enum mips_fp_condition {
234 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
237 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
238 #define STRINGIFY(X) #X
239 static const char *const mips_fp_conditions[] = {
240 MIPS_FP_CONDITIONS (STRINGIFY)
243 /* Information about a function's frame layout. */
244 struct GTY(()) mips_frame_info {
245 /* The size of the frame in bytes. */
246 HOST_WIDE_INT total_size;
248 /* The number of bytes allocated to variables. */
249 HOST_WIDE_INT var_size;
251 /* The number of bytes allocated to outgoing function arguments. */
252 HOST_WIDE_INT args_size;
254 /* The number of bytes allocated to the .cprestore slot, or 0 if there
256 HOST_WIDE_INT cprestore_size;
258 /* Bit X is set if the function saves or restores GPR X. */
261 /* Likewise FPR X. */
264 /* Likewise doubleword accumulator X ($acX). */
265 unsigned int acc_mask;
267 /* The number of GPRs, FPRs, doubleword accumulators and COP0
271 unsigned int num_acc;
272 unsigned int num_cop0_regs;
274 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
275 save slots from the top of the frame, or zero if no such slots are
277 HOST_WIDE_INT gp_save_offset;
278 HOST_WIDE_INT fp_save_offset;
279 HOST_WIDE_INT acc_save_offset;
280 HOST_WIDE_INT cop0_save_offset;
282 /* Likewise, but giving offsets from the bottom of the frame. */
283 HOST_WIDE_INT gp_sp_offset;
284 HOST_WIDE_INT fp_sp_offset;
285 HOST_WIDE_INT acc_sp_offset;
286 HOST_WIDE_INT cop0_sp_offset;
288 /* The offset of arg_pointer_rtx from the bottom of the frame. */
289 HOST_WIDE_INT arg_pointer_offset;
291 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
292 HOST_WIDE_INT hard_frame_pointer_offset;
295 struct GTY(()) machine_function {
296 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
297 rtx mips16_gp_pseudo_rtx;
299 /* The number of extra stack bytes taken up by register varargs.
300 This area is allocated by the callee at the very top of the frame. */
303 /* The current frame information, calculated by mips_compute_frame_info. */
304 struct mips_frame_info frame;
306 /* The register to use as the function's global pointer, or INVALID_REGNUM
307 if the function doesn't need one. */
308 unsigned int global_pointer;
310 /* How many instructions it takes to load a label into $AT, or 0 if
311 this property hasn't yet been calculated. */
312 unsigned int load_label_length;
314 /* True if mips_adjust_insn_length should ignore an instruction's
316 bool ignore_hazard_length_p;
318 /* True if the whole function is suitable for .set noreorder and
320 bool all_noreorder_p;
322 /* True if the function has "inflexible" and "flexible" references
323 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
324 and mips_cfun_has_flexible_gp_ref_p for details. */
325 bool has_inflexible_gp_insn_p;
326 bool has_flexible_gp_insn_p;
328 /* True if the function's prologue must load the global pointer
329 value into pic_offset_table_rtx and store the same value in
330 the function's cprestore slot (if any). Even if this value
331 is currently false, we may decide to set it to true later;
332 see mips_must_initialize_gp_p () for details. */
333 bool must_initialize_gp_p;
335 /* True if the current function must restore $gp after any potential
336 clobber. This value is only meaningful during the first post-epilogue
337 split_insns pass; see mips_must_initialize_gp_p () for details. */
338 bool must_restore_gp_when_clobbered_p;
340 /* True if we have emitted an instruction to initialize
341 mips16_gp_pseudo_rtx. */
342 bool initialized_mips16_gp_pseudo_p;
344 /* True if this is an interrupt handler. */
345 bool interrupt_handler_p;
347 /* True if this is an interrupt handler that uses shadow registers. */
348 bool use_shadow_register_set_p;
350 /* True if this is an interrupt handler that should keep interrupts
352 bool keep_interrupts_masked_p;
354 /* True if this is an interrupt handler that should use DERET
356 bool use_debug_exception_return_p;
359 /* Information about a single argument. */
360 struct mips_arg_info {
361 /* True if the argument is passed in a floating-point register, or
362 would have been if we hadn't run out of registers. */
365 /* The number of words passed in registers, rounded up. */
366 unsigned int reg_words;
368 /* For EABI, the offset of the first register from GP_ARG_FIRST or
369 FP_ARG_FIRST. For other ABIs, the offset of the first register from
370 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
371 comment for details).
373 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
375 unsigned int reg_offset;
377 /* The number of words that must be passed on the stack, rounded up. */
378 unsigned int stack_words;
380 /* The offset from the start of the stack overflow area of the argument's
381 first stack word. Only meaningful when STACK_WORDS is nonzero. */
382 unsigned int stack_offset;
385 /* Information about an address described by mips_address_type.
391 REG is the base register and OFFSET is the constant offset.
394 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
395 is the type of symbol it references.
398 SYMBOL_TYPE is the type of symbol that the address references. */
399 struct mips_address_info {
400 enum mips_address_type type;
403 enum mips_symbol_type symbol_type;
406 /* One stage in a constant building sequence. These sequences have
410 A = A CODE[1] VALUE[1]
411 A = A CODE[2] VALUE[2]
414 where A is an accumulator, each CODE[i] is a binary rtl operation
415 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
416 struct mips_integer_op {
418 unsigned HOST_WIDE_INT value;
421 /* The largest number of operations needed to load an integer constant.
422 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
423 When the lowest bit is clear, we can try, but reject a sequence with
424 an extra SLL at the end. */
425 #define MIPS_MAX_INTEGER_OPS 7
427 /* Information about a MIPS16e SAVE or RESTORE instruction. */
428 struct mips16e_save_restore_info {
429 /* The number of argument registers saved by a SAVE instruction.
430 0 for RESTORE instructions. */
433 /* Bit X is set if the instruction saves or restores GPR X. */
436 /* The total number of bytes to allocate. */
440 /* Global variables for machine-dependent things. */
442 /* The -G setting, or the configuration's default small-data limit if
443 no -G option is given. */
444 static unsigned int mips_small_data_threshold;
446 /* The number of file directives written by mips_output_filename. */
447 int num_source_filenames;
449 /* The name that appeared in the last .file directive written by
450 mips_output_filename, or "" if mips_output_filename hasn't
451 written anything yet. */
452 const char *current_function_file = "";
454 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
457 /* Arrays that map GCC register numbers to debugger register numbers. */
458 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
459 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
461 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
462 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
463 struct mips_asm_switch mips_nomacro = { "macro", 0 };
464 struct mips_asm_switch mips_noat = { "at", 0 };
466 /* True if we're writing out a branch-likely instruction rather than a
468 static bool mips_branch_likely;
470 /* The current instruction-set architecture. */
471 enum processor_type mips_arch;
472 const struct mips_cpu_info *mips_arch_info;
474 /* The processor that we should tune the code for. */
475 enum processor_type mips_tune;
476 const struct mips_cpu_info *mips_tune_info;
478 /* The ISA level associated with mips_arch. */
481 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
482 static const struct mips_cpu_info *mips_isa_option_info;
484 /* Which ABI to use. */
485 int mips_abi = MIPS_ABI_DEFAULT;
487 /* Which cost information to use. */
488 const struct mips_rtx_cost_data *mips_cost;
490 /* The ambient target flags, excluding MASK_MIPS16. */
491 static int mips_base_target_flags;
493 /* True if MIPS16 is the default mode. */
494 bool mips_base_mips16;
496 /* The ambient values of other global variables. */
497 static int mips_base_schedule_insns; /* flag_schedule_insns */
498 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
499 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
500 static int mips_base_align_loops; /* align_loops */
501 static int mips_base_align_jumps; /* align_jumps */
502 static int mips_base_align_functions; /* align_functions */
504 /* The -mcode-readable setting. */
505 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
507 /* The -mr10k-cache-barrier setting. */
508 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
510 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
511 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
513 /* Index C is true if character C is a valid PRINT_OPERAND punctation
515 bool mips_print_operand_punct[256];
517 static GTY (()) int mips_output_filename_first_time = 1;
519 /* mips_split_p[X] is true if symbols of type X can be split by
520 mips_split_symbol. */
521 bool mips_split_p[NUM_SYMBOL_TYPES];
523 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
524 can be split by mips_split_symbol. */
525 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
527 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
528 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
529 if they are matched by a special .md file pattern. */
530 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
532 /* Likewise for HIGHs. */
533 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
535 /* Index R is the smallest register class that contains register R. */
536 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
537 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
538 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
539 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
540 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
541 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
542 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
543 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
544 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
545 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
546 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
547 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
548 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
549 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
550 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
551 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
552 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
553 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
554 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
555 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
556 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
557 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
558 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
559 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
560 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
561 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
562 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
563 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
564 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
565 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
566 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
567 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
568 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
569 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
570 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
571 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
572 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
573 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
574 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
575 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
576 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
577 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
578 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
579 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
580 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
581 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
582 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
583 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
586 /* The value of TARGET_ATTRIBUTE_TABLE. */
587 static const struct attribute_spec mips_attribute_table[] = {
588 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
589 { "long_call", 0, 0, false, true, true, NULL },
590 { "far", 0, 0, false, true, true, NULL },
591 { "near", 0, 0, false, true, true, NULL },
592 /* We would really like to treat "mips16" and "nomips16" as type
593 attributes, but GCC doesn't provide the hooks we need to support
594 the right conversion rules. As declaration attributes, they affect
595 code generation but don't carry other semantics. */
596 { "mips16", 0, 0, true, false, false, NULL },
597 { "nomips16", 0, 0, true, false, false, NULL },
598 /* Allow functions to be specified as interrupt handlers */
599 { "interrupt", 0, 0, false, true, true, NULL },
600 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
601 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
602 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
603 { NULL, 0, 0, false, false, false, NULL }
606 /* A table describing all the processors GCC knows about. Names are
607 matched in the order listed. The first mention of an ISA level is
608 taken as the canonical name for that ISA.
610 To ease comparison, please keep this table in the same order
611 as GAS's mips_cpu_info_table. Please also make sure that
612 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
613 options correctly. */
614 static const struct mips_cpu_info mips_cpu_info_table[] = {
615 /* Entries for generic ISAs. */
616 { "mips1", PROCESSOR_R3000, 1, 0 },
617 { "mips2", PROCESSOR_R6000, 2, 0 },
618 { "mips3", PROCESSOR_R4000, 3, 0 },
619 { "mips4", PROCESSOR_R8000, 4, 0 },
620 /* Prefer not to use branch-likely instructions for generic MIPS32rX
621 and MIPS64rX code. The instructions were officially deprecated
622 in revisions 2 and earlier, but revision 3 is likely to downgrade
623 that to a recommendation to avoid the instructions in code that
624 isn't tuned to a specific processor. */
625 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
626 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
627 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
628 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
629 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
631 /* MIPS I processors. */
632 { "r3000", PROCESSOR_R3000, 1, 0 },
633 { "r2000", PROCESSOR_R3000, 1, 0 },
634 { "r3900", PROCESSOR_R3900, 1, 0 },
636 /* MIPS II processors. */
637 { "r6000", PROCESSOR_R6000, 2, 0 },
639 /* MIPS III processors. */
640 { "r4000", PROCESSOR_R4000, 3, 0 },
641 { "vr4100", PROCESSOR_R4100, 3, 0 },
642 { "vr4111", PROCESSOR_R4111, 3, 0 },
643 { "vr4120", PROCESSOR_R4120, 3, 0 },
644 { "vr4130", PROCESSOR_R4130, 3, 0 },
645 { "vr4300", PROCESSOR_R4300, 3, 0 },
646 { "r4400", PROCESSOR_R4000, 3, 0 },
647 { "r4600", PROCESSOR_R4600, 3, 0 },
648 { "orion", PROCESSOR_R4600, 3, 0 },
649 { "r4650", PROCESSOR_R4650, 3, 0 },
650 /* ST Loongson 2E/2F processors. */
651 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
652 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
654 /* MIPS IV processors. */
655 { "r8000", PROCESSOR_R8000, 4, 0 },
656 { "r10000", PROCESSOR_R10000, 4, 0 },
657 { "r12000", PROCESSOR_R10000, 4, 0 },
658 { "r14000", PROCESSOR_R10000, 4, 0 },
659 { "r16000", PROCESSOR_R10000, 4, 0 },
660 { "vr5000", PROCESSOR_R5000, 4, 0 },
661 { "vr5400", PROCESSOR_R5400, 4, 0 },
662 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
663 { "rm7000", PROCESSOR_R7000, 4, 0 },
664 { "rm9000", PROCESSOR_R9000, 4, 0 },
666 /* MIPS32 processors. */
667 { "4kc", PROCESSOR_4KC, 32, 0 },
668 { "4km", PROCESSOR_4KC, 32, 0 },
669 { "4kp", PROCESSOR_4KP, 32, 0 },
670 { "4ksc", PROCESSOR_4KC, 32, 0 },
672 /* MIPS32 Release 2 processors. */
673 { "m4k", PROCESSOR_M4K, 33, 0 },
674 { "4kec", PROCESSOR_4KC, 33, 0 },
675 { "4kem", PROCESSOR_4KC, 33, 0 },
676 { "4kep", PROCESSOR_4KP, 33, 0 },
677 { "4ksd", PROCESSOR_4KC, 33, 0 },
679 { "24kc", PROCESSOR_24KC, 33, 0 },
680 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
681 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
682 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
683 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
684 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
686 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
687 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
688 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
689 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
690 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
691 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
693 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
694 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
695 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
696 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
697 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
698 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
700 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
701 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
702 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
703 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
704 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
705 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
706 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
708 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
709 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
710 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
711 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
713 /* MIPS64 processors. */
714 { "5kc", PROCESSOR_5KC, 64, 0 },
715 { "5kf", PROCESSOR_5KF, 64, 0 },
716 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
717 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
718 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
719 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
720 { "xlr", PROCESSOR_XLR, 64, 0 },
722 /* MIPS64 Release 2 processors. */
723 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
726 /* Default costs. If these are used for a processor we should look
727 up the actual costs. */
728 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
729 COSTS_N_INSNS (7), /* fp_mult_sf */ \
730 COSTS_N_INSNS (8), /* fp_mult_df */ \
731 COSTS_N_INSNS (23), /* fp_div_sf */ \
732 COSTS_N_INSNS (36), /* fp_div_df */ \
733 COSTS_N_INSNS (10), /* int_mult_si */ \
734 COSTS_N_INSNS (10), /* int_mult_di */ \
735 COSTS_N_INSNS (69), /* int_div_si */ \
736 COSTS_N_INSNS (69), /* int_div_di */ \
737 2, /* branch_cost */ \
738 4 /* memory_latency */
740 /* Floating-point costs for processors without an FPU. Just assume that
741 all floating-point libcalls are very expensive. */
742 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
743 COSTS_N_INSNS (256), /* fp_mult_sf */ \
744 COSTS_N_INSNS (256), /* fp_mult_df */ \
745 COSTS_N_INSNS (256), /* fp_div_sf */ \
746 COSTS_N_INSNS (256) /* fp_div_df */
748 /* Costs to use when optimizing for size. */
749 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
750 COSTS_N_INSNS (1), /* fp_add */
751 COSTS_N_INSNS (1), /* fp_mult_sf */
752 COSTS_N_INSNS (1), /* fp_mult_df */
753 COSTS_N_INSNS (1), /* fp_div_sf */
754 COSTS_N_INSNS (1), /* fp_div_df */
755 COSTS_N_INSNS (1), /* int_mult_si */
756 COSTS_N_INSNS (1), /* int_mult_di */
757 COSTS_N_INSNS (1), /* int_div_si */
758 COSTS_N_INSNS (1), /* int_div_di */
760 4 /* memory_latency */
763 /* Costs to use when optimizing for speed, indexed by processor. */
764 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
766 COSTS_N_INSNS (2), /* fp_add */
767 COSTS_N_INSNS (4), /* fp_mult_sf */
768 COSTS_N_INSNS (5), /* fp_mult_df */
769 COSTS_N_INSNS (12), /* fp_div_sf */
770 COSTS_N_INSNS (19), /* fp_div_df */
771 COSTS_N_INSNS (12), /* int_mult_si */
772 COSTS_N_INSNS (12), /* int_mult_di */
773 COSTS_N_INSNS (35), /* int_div_si */
774 COSTS_N_INSNS (35), /* int_div_di */
776 4 /* memory_latency */
780 COSTS_N_INSNS (6), /* int_mult_si */
781 COSTS_N_INSNS (6), /* int_mult_di */
782 COSTS_N_INSNS (36), /* int_div_si */
783 COSTS_N_INSNS (36), /* int_div_di */
785 4 /* memory_latency */
789 COSTS_N_INSNS (36), /* int_mult_si */
790 COSTS_N_INSNS (36), /* int_mult_di */
791 COSTS_N_INSNS (37), /* int_div_si */
792 COSTS_N_INSNS (37), /* int_div_di */
794 4 /* memory_latency */
798 COSTS_N_INSNS (4), /* int_mult_si */
799 COSTS_N_INSNS (11), /* int_mult_di */
800 COSTS_N_INSNS (36), /* int_div_si */
801 COSTS_N_INSNS (68), /* int_div_di */
803 4 /* memory_latency */
806 COSTS_N_INSNS (4), /* fp_add */
807 COSTS_N_INSNS (4), /* fp_mult_sf */
808 COSTS_N_INSNS (5), /* fp_mult_df */
809 COSTS_N_INSNS (17), /* fp_div_sf */
810 COSTS_N_INSNS (32), /* fp_div_df */
811 COSTS_N_INSNS (4), /* int_mult_si */
812 COSTS_N_INSNS (11), /* int_mult_di */
813 COSTS_N_INSNS (36), /* int_div_si */
814 COSTS_N_INSNS (68), /* int_div_di */
816 4 /* memory_latency */
819 COSTS_N_INSNS (4), /* fp_add */
820 COSTS_N_INSNS (4), /* fp_mult_sf */
821 COSTS_N_INSNS (5), /* fp_mult_df */
822 COSTS_N_INSNS (17), /* fp_div_sf */
823 COSTS_N_INSNS (32), /* fp_div_df */
824 COSTS_N_INSNS (4), /* int_mult_si */
825 COSTS_N_INSNS (7), /* int_mult_di */
826 COSTS_N_INSNS (42), /* int_div_si */
827 COSTS_N_INSNS (72), /* int_div_di */
829 4 /* memory_latency */
833 COSTS_N_INSNS (5), /* int_mult_si */
834 COSTS_N_INSNS (5), /* int_mult_di */
835 COSTS_N_INSNS (41), /* int_div_si */
836 COSTS_N_INSNS (41), /* int_div_di */
838 4 /* memory_latency */
841 COSTS_N_INSNS (8), /* fp_add */
842 COSTS_N_INSNS (8), /* fp_mult_sf */
843 COSTS_N_INSNS (10), /* fp_mult_df */
844 COSTS_N_INSNS (34), /* fp_div_sf */
845 COSTS_N_INSNS (64), /* fp_div_df */
846 COSTS_N_INSNS (5), /* int_mult_si */
847 COSTS_N_INSNS (5), /* int_mult_di */
848 COSTS_N_INSNS (41), /* int_div_si */
849 COSTS_N_INSNS (41), /* int_div_di */
851 4 /* memory_latency */
854 COSTS_N_INSNS (4), /* fp_add */
855 COSTS_N_INSNS (4), /* fp_mult_sf */
856 COSTS_N_INSNS (5), /* fp_mult_df */
857 COSTS_N_INSNS (17), /* fp_div_sf */
858 COSTS_N_INSNS (32), /* fp_div_df */
859 COSTS_N_INSNS (5), /* int_mult_si */
860 COSTS_N_INSNS (5), /* int_mult_di */
861 COSTS_N_INSNS (41), /* int_div_si */
862 COSTS_N_INSNS (41), /* int_div_di */
864 4 /* memory_latency */
868 COSTS_N_INSNS (5), /* int_mult_si */
869 COSTS_N_INSNS (5), /* int_mult_di */
870 COSTS_N_INSNS (41), /* int_div_si */
871 COSTS_N_INSNS (41), /* int_div_di */
873 4 /* memory_latency */
876 COSTS_N_INSNS (8), /* fp_add */
877 COSTS_N_INSNS (8), /* fp_mult_sf */
878 COSTS_N_INSNS (10), /* fp_mult_df */
879 COSTS_N_INSNS (34), /* fp_div_sf */
880 COSTS_N_INSNS (64), /* fp_div_df */
881 COSTS_N_INSNS (5), /* int_mult_si */
882 COSTS_N_INSNS (5), /* int_mult_di */
883 COSTS_N_INSNS (41), /* int_div_si */
884 COSTS_N_INSNS (41), /* int_div_di */
886 4 /* memory_latency */
889 COSTS_N_INSNS (4), /* fp_add */
890 COSTS_N_INSNS (4), /* fp_mult_sf */
891 COSTS_N_INSNS (5), /* fp_mult_df */
892 COSTS_N_INSNS (17), /* fp_div_sf */
893 COSTS_N_INSNS (32), /* fp_div_df */
894 COSTS_N_INSNS (5), /* int_mult_si */
895 COSTS_N_INSNS (5), /* int_mult_di */
896 COSTS_N_INSNS (41), /* int_div_si */
897 COSTS_N_INSNS (41), /* int_div_di */
899 4 /* memory_latency */
902 COSTS_N_INSNS (6), /* fp_add */
903 COSTS_N_INSNS (6), /* fp_mult_sf */
904 COSTS_N_INSNS (7), /* fp_mult_df */
905 COSTS_N_INSNS (25), /* fp_div_sf */
906 COSTS_N_INSNS (48), /* fp_div_df */
907 COSTS_N_INSNS (5), /* int_mult_si */
908 COSTS_N_INSNS (5), /* int_mult_di */
909 COSTS_N_INSNS (41), /* int_div_si */
910 COSTS_N_INSNS (41), /* int_div_di */
912 4 /* memory_latency */
926 COSTS_N_INSNS (5), /* int_mult_si */
927 COSTS_N_INSNS (5), /* int_mult_di */
928 COSTS_N_INSNS (72), /* int_div_si */
929 COSTS_N_INSNS (72), /* int_div_di */
931 4 /* memory_latency */
934 COSTS_N_INSNS (2), /* fp_add */
935 COSTS_N_INSNS (4), /* fp_mult_sf */
936 COSTS_N_INSNS (5), /* fp_mult_df */
937 COSTS_N_INSNS (12), /* fp_div_sf */
938 COSTS_N_INSNS (19), /* fp_div_df */
939 COSTS_N_INSNS (2), /* int_mult_si */
940 COSTS_N_INSNS (2), /* int_mult_di */
941 COSTS_N_INSNS (35), /* int_div_si */
942 COSTS_N_INSNS (35), /* int_div_di */
944 4 /* memory_latency */
947 COSTS_N_INSNS (3), /* fp_add */
948 COSTS_N_INSNS (5), /* fp_mult_sf */
949 COSTS_N_INSNS (6), /* fp_mult_df */
950 COSTS_N_INSNS (15), /* fp_div_sf */
951 COSTS_N_INSNS (16), /* fp_div_df */
952 COSTS_N_INSNS (17), /* int_mult_si */
953 COSTS_N_INSNS (17), /* int_mult_di */
954 COSTS_N_INSNS (38), /* int_div_si */
955 COSTS_N_INSNS (38), /* int_div_di */
957 6 /* memory_latency */
960 COSTS_N_INSNS (6), /* fp_add */
961 COSTS_N_INSNS (7), /* fp_mult_sf */
962 COSTS_N_INSNS (8), /* fp_mult_df */
963 COSTS_N_INSNS (23), /* fp_div_sf */
964 COSTS_N_INSNS (36), /* fp_div_df */
965 COSTS_N_INSNS (10), /* int_mult_si */
966 COSTS_N_INSNS (10), /* int_mult_di */
967 COSTS_N_INSNS (69), /* int_div_si */
968 COSTS_N_INSNS (69), /* int_div_di */
970 6 /* memory_latency */
982 /* The only costs that appear to be updated here are
983 integer multiplication. */
985 COSTS_N_INSNS (4), /* int_mult_si */
986 COSTS_N_INSNS (6), /* int_mult_di */
987 COSTS_N_INSNS (69), /* int_div_si */
988 COSTS_N_INSNS (69), /* int_div_di */
990 4 /* memory_latency */
1002 COSTS_N_INSNS (6), /* fp_add */
1003 COSTS_N_INSNS (4), /* fp_mult_sf */
1004 COSTS_N_INSNS (5), /* fp_mult_df */
1005 COSTS_N_INSNS (23), /* fp_div_sf */
1006 COSTS_N_INSNS (36), /* fp_div_df */
1007 COSTS_N_INSNS (5), /* int_mult_si */
1008 COSTS_N_INSNS (5), /* int_mult_di */
1009 COSTS_N_INSNS (36), /* int_div_si */
1010 COSTS_N_INSNS (36), /* int_div_di */
1011 1, /* branch_cost */
1012 4 /* memory_latency */
1015 COSTS_N_INSNS (6), /* fp_add */
1016 COSTS_N_INSNS (5), /* fp_mult_sf */
1017 COSTS_N_INSNS (6), /* fp_mult_df */
1018 COSTS_N_INSNS (30), /* fp_div_sf */
1019 COSTS_N_INSNS (59), /* fp_div_df */
1020 COSTS_N_INSNS (3), /* int_mult_si */
1021 COSTS_N_INSNS (4), /* int_mult_di */
1022 COSTS_N_INSNS (42), /* int_div_si */
1023 COSTS_N_INSNS (74), /* int_div_di */
1024 1, /* branch_cost */
1025 4 /* memory_latency */
1028 COSTS_N_INSNS (6), /* fp_add */
1029 COSTS_N_INSNS (5), /* fp_mult_sf */
1030 COSTS_N_INSNS (6), /* fp_mult_df */
1031 COSTS_N_INSNS (30), /* fp_div_sf */
1032 COSTS_N_INSNS (59), /* fp_div_df */
1033 COSTS_N_INSNS (5), /* int_mult_si */
1034 COSTS_N_INSNS (9), /* int_mult_di */
1035 COSTS_N_INSNS (42), /* int_div_si */
1036 COSTS_N_INSNS (74), /* int_div_di */
1037 1, /* branch_cost */
1038 4 /* memory_latency */
1041 /* The only costs that are changed here are
1042 integer multiplication. */
1043 COSTS_N_INSNS (6), /* fp_add */
1044 COSTS_N_INSNS (7), /* fp_mult_sf */
1045 COSTS_N_INSNS (8), /* fp_mult_df */
1046 COSTS_N_INSNS (23), /* fp_div_sf */
1047 COSTS_N_INSNS (36), /* fp_div_df */
1048 COSTS_N_INSNS (5), /* int_mult_si */
1049 COSTS_N_INSNS (9), /* int_mult_di */
1050 COSTS_N_INSNS (69), /* int_div_si */
1051 COSTS_N_INSNS (69), /* int_div_di */
1052 1, /* branch_cost */
1053 4 /* memory_latency */
1059 /* The only costs that are changed here are
1060 integer multiplication. */
1061 COSTS_N_INSNS (6), /* fp_add */
1062 COSTS_N_INSNS (7), /* fp_mult_sf */
1063 COSTS_N_INSNS (8), /* fp_mult_df */
1064 COSTS_N_INSNS (23), /* fp_div_sf */
1065 COSTS_N_INSNS (36), /* fp_div_df */
1066 COSTS_N_INSNS (3), /* int_mult_si */
1067 COSTS_N_INSNS (8), /* int_mult_di */
1068 COSTS_N_INSNS (69), /* int_div_si */
1069 COSTS_N_INSNS (69), /* int_div_di */
1070 1, /* branch_cost */
1071 4 /* memory_latency */
1074 COSTS_N_INSNS (2), /* fp_add */
1075 COSTS_N_INSNS (2), /* fp_mult_sf */
1076 COSTS_N_INSNS (2), /* fp_mult_df */
1077 COSTS_N_INSNS (12), /* fp_div_sf */
1078 COSTS_N_INSNS (19), /* fp_div_df */
1079 COSTS_N_INSNS (5), /* int_mult_si */
1080 COSTS_N_INSNS (9), /* int_mult_di */
1081 COSTS_N_INSNS (34), /* int_div_si */
1082 COSTS_N_INSNS (66), /* int_div_di */
1083 1, /* branch_cost */
1084 4 /* memory_latency */
1087 /* These costs are the same as the SB-1A below. */
1088 COSTS_N_INSNS (4), /* fp_add */
1089 COSTS_N_INSNS (4), /* fp_mult_sf */
1090 COSTS_N_INSNS (4), /* fp_mult_df */
1091 COSTS_N_INSNS (24), /* fp_div_sf */
1092 COSTS_N_INSNS (32), /* fp_div_df */
1093 COSTS_N_INSNS (3), /* int_mult_si */
1094 COSTS_N_INSNS (4), /* int_mult_di */
1095 COSTS_N_INSNS (36), /* int_div_si */
1096 COSTS_N_INSNS (68), /* int_div_di */
1097 1, /* branch_cost */
1098 4 /* memory_latency */
1101 /* These costs are the same as the SB-1 above. */
1102 COSTS_N_INSNS (4), /* fp_add */
1103 COSTS_N_INSNS (4), /* fp_mult_sf */
1104 COSTS_N_INSNS (4), /* fp_mult_df */
1105 COSTS_N_INSNS (24), /* fp_div_sf */
1106 COSTS_N_INSNS (32), /* fp_div_df */
1107 COSTS_N_INSNS (3), /* int_mult_si */
1108 COSTS_N_INSNS (4), /* int_mult_di */
1109 COSTS_N_INSNS (36), /* int_div_si */
1110 COSTS_N_INSNS (68), /* int_div_di */
1111 1, /* branch_cost */
1112 4 /* memory_latency */
1119 COSTS_N_INSNS (8), /* int_mult_si */
1120 COSTS_N_INSNS (8), /* int_mult_di */
1121 COSTS_N_INSNS (72), /* int_div_si */
1122 COSTS_N_INSNS (72), /* int_div_di */
1123 1, /* branch_cost */
1124 4 /* memory_latency */
1128 static rtx mips_find_pic_call_symbol (rtx, rtx);
1130 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1131 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1132 struct GTY (()) mflip_mips16_entry {
1136 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1138 /* Hash table callbacks for mflip_mips16_htab. */
1141 mflip_mips16_htab_hash (const void *entry)
1143 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1147 mflip_mips16_htab_eq (const void *entry, const void *name)
1149 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1150 (const char *) name) == 0;
1153 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1154 mode, false if it should next add an attribute for the opposite mode. */
1155 static GTY(()) bool mips16_flipper;
1157 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1158 for -mflip-mips16. Return true if it should use "mips16" and false if
1159 it should use "nomips16". */
1162 mflip_mips16_use_mips16_p (tree decl)
1164 struct mflip_mips16_entry *entry;
1169 /* Use the opposite of the command-line setting for anonymous decls. */
1170 if (!DECL_NAME (decl))
1171 return !mips_base_mips16;
1173 if (!mflip_mips16_htab)
1174 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1175 mflip_mips16_htab_eq, NULL);
1177 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1178 hash = htab_hash_string (name);
1179 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1180 entry = (struct mflip_mips16_entry *) *slot;
1183 mips16_flipper = !mips16_flipper;
1184 entry = GGC_NEW (struct mflip_mips16_entry);
1186 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1189 return entry->mips16_p;
1192 /* Predicates to test for presence of "near" and "far"/"long_call"
1193 attributes on the given TYPE. */
1196 mips_near_type_p (const_tree type)
1198 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1202 mips_far_type_p (const_tree type)
1204 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1205 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1208 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1211 mips_mips16_decl_p (const_tree decl)
1213 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1217 mips_nomips16_decl_p (const_tree decl)
1219 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1222 /* Check if the interrupt attribute is set for a function. */
1225 mips_interrupt_type_p (tree type)
1227 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1230 /* Check if the attribute to use shadow register set is set for a function. */
1233 mips_use_shadow_register_set_p (tree type)
1235 return lookup_attribute ("use_shadow_register_set",
1236 TYPE_ATTRIBUTES (type)) != NULL;
1239 /* Check if the attribute to keep interrupts masked is set for a function. */
1242 mips_keep_interrupts_masked_p (tree type)
1244 return lookup_attribute ("keep_interrupts_masked",
1245 TYPE_ATTRIBUTES (type)) != NULL;
1248 /* Check if the attribute to use debug exception return is set for
1252 mips_use_debug_exception_return_p (tree type)
1254 return lookup_attribute ("use_debug_exception_return",
1255 TYPE_ATTRIBUTES (type)) != NULL;
1258 /* Return true if function DECL is a MIPS16 function. Return the ambient
1259 setting if DECL is null. */
1262 mips_use_mips16_mode_p (tree decl)
1266 /* Nested functions must use the same frame pointer as their
1267 parent and must therefore use the same ISA mode. */
1268 tree parent = decl_function_context (decl);
1271 if (mips_mips16_decl_p (decl))
1273 if (mips_nomips16_decl_p (decl))
1276 return mips_base_mips16;
1279 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1282 mips_comp_type_attributes (const_tree type1, const_tree type2)
1284 /* Disallow mixed near/far attributes. */
1285 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1287 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1292 /* Implement TARGET_INSERT_ATTRIBUTES. */
1295 mips_insert_attributes (tree decl, tree *attributes)
1298 bool mips16_p, nomips16_p;
1300 /* Check for "mips16" and "nomips16" attributes. */
1301 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1302 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1303 if (TREE_CODE (decl) != FUNCTION_DECL)
1306 error ("%qs attribute only applies to functions", "mips16");
1308 error ("%qs attribute only applies to functions", "nomips16");
1312 mips16_p |= mips_mips16_decl_p (decl);
1313 nomips16_p |= mips_nomips16_decl_p (decl);
1314 if (mips16_p || nomips16_p)
1316 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1317 if (mips16_p && nomips16_p)
1318 error ("%qE cannot have both %<mips16%> and "
1319 "%<nomips16%> attributes",
1322 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1324 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1325 "mips16" attribute, arbitrarily pick one. We must pick the same
1326 setting for duplicate declarations of a function. */
1327 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1328 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1333 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1336 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1338 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1339 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1340 error ("%qE redeclared with conflicting %qs attributes",
1341 DECL_NAME (newdecl), "mips16");
1342 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1343 error ("%qE redeclared with conflicting %qs attributes",
1344 DECL_NAME (newdecl), "nomips16");
1346 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1347 DECL_ATTRIBUTES (newdecl));
1350 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1351 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1354 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1356 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1358 *base_ptr = XEXP (x, 0);
1359 *offset_ptr = INTVAL (XEXP (x, 1));
1368 static unsigned int mips_build_integer (struct mips_integer_op *,
1369 unsigned HOST_WIDE_INT);
1371 /* A subroutine of mips_build_integer, with the same interface.
1372 Assume that the final action in the sequence should be a left shift. */
1375 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1377 unsigned int i, shift;
1379 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1380 since signed numbers are easier to load than unsigned ones. */
1382 while ((value & 1) == 0)
1383 value /= 2, shift++;
1385 i = mips_build_integer (codes, value);
1386 codes[i].code = ASHIFT;
1387 codes[i].value = shift;
1391 /* As for mips_build_shift, but assume that the final action will be
1392 an IOR or PLUS operation. */
1395 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1397 unsigned HOST_WIDE_INT high;
1400 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1401 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1403 /* The constant is too complex to load with a simple LUI/ORI pair,
1404 so we want to give the recursive call as many trailing zeros as
1405 possible. In this case, we know bit 16 is set and that the
1406 low 16 bits form a negative number. If we subtract that number
1407 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1408 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1409 codes[i].code = PLUS;
1410 codes[i].value = CONST_LOW_PART (value);
1414 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1415 bits gives a value with at least 17 trailing zeros. */
1416 i = mips_build_integer (codes, high);
1417 codes[i].code = IOR;
1418 codes[i].value = value & 0xffff;
1423 /* Fill CODES with a sequence of rtl operations to load VALUE.
1424 Return the number of operations needed. */
1427 mips_build_integer (struct mips_integer_op *codes,
1428 unsigned HOST_WIDE_INT value)
1430 if (SMALL_OPERAND (value)
1431 || SMALL_OPERAND_UNSIGNED (value)
1432 || LUI_OPERAND (value))
1434 /* The value can be loaded with a single instruction. */
1435 codes[0].code = UNKNOWN;
1436 codes[0].value = value;
1439 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1441 /* Either the constant is a simple LUI/ORI combination or its
1442 lowest bit is set. We don't want to shift in this case. */
1443 return mips_build_lower (codes, value);
1445 else if ((value & 0xffff) == 0)
1447 /* The constant will need at least three actions. The lowest
1448 16 bits are clear, so the final action will be a shift. */
1449 return mips_build_shift (codes, value);
1453 /* The final action could be a shift, add or inclusive OR.
1454 Rather than use a complex condition to select the best
1455 approach, try both mips_build_shift and mips_build_lower
1456 and pick the one that gives the shortest sequence.
1457 Note that this case is only used once per constant. */
1458 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1459 unsigned int cost, alt_cost;
1461 cost = mips_build_shift (codes, value);
1462 alt_cost = mips_build_lower (alt_codes, value);
1463 if (alt_cost < cost)
1465 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1472 /* Return true if symbols of type TYPE require a GOT access. */
1475 mips_got_symbol_type_p (enum mips_symbol_type type)
1479 case SYMBOL_GOT_PAGE_OFST:
1480 case SYMBOL_GOT_DISP:
1488 /* Return true if X is a thread-local symbol. */
1491 mips_tls_symbol_p (rtx x)
1493 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1496 /* Return true if SYMBOL_REF X is associated with a global symbol
1497 (in the STB_GLOBAL sense). */
1500 mips_global_symbol_p (const_rtx x)
1502 const_tree decl = SYMBOL_REF_DECL (x);
1505 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1507 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1508 or weak symbols. Relocations in the object file will be against
1509 the target symbol, so it's that symbol's binding that matters here. */
1510 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1513 /* Return true if function X is a libgcc MIPS16 stub function. */
1516 mips16_stub_function_p (const_rtx x)
1518 return (GET_CODE (x) == SYMBOL_REF
1519 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1522 /* Return true if function X is a locally-defined and locally-binding
1526 mips16_local_function_p (const_rtx x)
1528 return (GET_CODE (x) == SYMBOL_REF
1529 && SYMBOL_REF_LOCAL_P (x)
1530 && !SYMBOL_REF_EXTERNAL_P (x)
1531 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1534 /* Return true if SYMBOL_REF X binds locally. */
1537 mips_symbol_binds_local_p (const_rtx x)
1539 return (SYMBOL_REF_DECL (x)
1540 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1541 : SYMBOL_REF_LOCAL_P (x));
1544 /* Return true if rtx constants of mode MODE should be put into a small
1548 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1550 return (!TARGET_EMBEDDED_DATA
1551 && TARGET_LOCAL_SDATA
1552 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1555 /* Return true if X should not be moved directly into register $25.
1556 We need this because many versions of GAS will treat "la $25,foo" as
1557 part of a call sequence and so allow a global "foo" to be lazily bound. */
1560 mips_dangerous_for_la25_p (rtx x)
1562 return (!TARGET_EXPLICIT_RELOCS
1564 && GET_CODE (x) == SYMBOL_REF
1565 && mips_global_symbol_p (x));
1568 /* Return true if calls to X might need $25 to be valid on entry. */
1571 mips_use_pic_fn_addr_reg_p (const_rtx x)
1573 if (!TARGET_USE_PIC_FN_ADDR_REG)
1576 /* MIPS16 stub functions are guaranteed not to use $25. */
1577 if (mips16_stub_function_p (x))
1580 if (GET_CODE (x) == SYMBOL_REF)
1582 /* If PLTs and copy relocations are available, the static linker
1583 will make sure that $25 is valid on entry to the target function. */
1584 if (TARGET_ABICALLS_PIC0)
1587 /* Locally-defined functions use absolute accesses to set up
1588 the global pointer. */
1589 if (TARGET_ABSOLUTE_ABICALLS
1590 && mips_symbol_binds_local_p (x)
1591 && !SYMBOL_REF_EXTERNAL_P (x))
1598 /* Return the method that should be used to access SYMBOL_REF or
1599 LABEL_REF X in context CONTEXT. */
1601 static enum mips_symbol_type
1602 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1605 return SYMBOL_GOT_DISP;
1607 if (GET_CODE (x) == LABEL_REF)
1609 /* LABEL_REFs are used for jump tables as well as text labels.
1610 Only return SYMBOL_PC_RELATIVE if we know the label is in
1611 the text section. */
1612 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1613 return SYMBOL_PC_RELATIVE;
1615 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1616 return SYMBOL_GOT_PAGE_OFST;
1618 return SYMBOL_ABSOLUTE;
1621 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1623 if (SYMBOL_REF_TLS_MODEL (x))
1626 if (CONSTANT_POOL_ADDRESS_P (x))
1628 if (TARGET_MIPS16_TEXT_LOADS)
1629 return SYMBOL_PC_RELATIVE;
1631 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1632 return SYMBOL_PC_RELATIVE;
1634 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1635 return SYMBOL_GP_RELATIVE;
1638 /* Do not use small-data accesses for weak symbols; they may end up
1640 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1641 return SYMBOL_GP_RELATIVE;
1643 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1645 if (TARGET_ABICALLS_PIC2
1646 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1648 /* There are three cases to consider:
1650 - o32 PIC (either with or without explicit relocs)
1651 - n32/n64 PIC without explicit relocs
1652 - n32/n64 PIC with explicit relocs
1654 In the first case, both local and global accesses will use an
1655 R_MIPS_GOT16 relocation. We must correctly predict which of
1656 the two semantics (local or global) the assembler and linker
1657 will apply. The choice depends on the symbol's binding rather
1658 than its visibility.
1660 In the second case, the assembler will not use R_MIPS_GOT16
1661 relocations, but it chooses between local and global accesses
1662 in the same way as for o32 PIC.
1664 In the third case we have more freedom since both forms of
1665 access will work for any kind of symbol. However, there seems
1666 little point in doing things differently. */
1667 if (mips_global_symbol_p (x))
1668 return SYMBOL_GOT_DISP;
1670 return SYMBOL_GOT_PAGE_OFST;
1673 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1674 return SYMBOL_FORCE_TO_MEM;
1676 return SYMBOL_ABSOLUTE;
1679 /* Classify the base of symbolic expression X, given that X appears in
1682 static enum mips_symbol_type
1683 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1687 split_const (x, &x, &offset);
1688 if (UNSPEC_ADDRESS_P (x))
1689 return UNSPEC_ADDRESS_TYPE (x);
1691 return mips_classify_symbol (x, context);
1694 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1695 is the alignment in bytes of SYMBOL_REF X. */
1698 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1700 HOST_WIDE_INT align;
1702 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1703 return IN_RANGE (offset, 0, align - 1);
1706 /* Return true if X is a symbolic constant that can be used in context
1707 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1710 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1711 enum mips_symbol_type *symbol_type)
1715 split_const (x, &x, &offset);
1716 if (UNSPEC_ADDRESS_P (x))
1718 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1719 x = UNSPEC_ADDRESS (x);
1721 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1723 *symbol_type = mips_classify_symbol (x, context);
1724 if (*symbol_type == SYMBOL_TLS)
1730 if (offset == const0_rtx)
1733 /* Check whether a nonzero offset is valid for the underlying
1735 switch (*symbol_type)
1737 case SYMBOL_ABSOLUTE:
1738 case SYMBOL_FORCE_TO_MEM:
1739 case SYMBOL_32_HIGH:
1740 case SYMBOL_64_HIGH:
1743 /* If the target has 64-bit pointers and the object file only
1744 supports 32-bit symbols, the values of those symbols will be
1745 sign-extended. In this case we can't allow an arbitrary offset
1746 in case the 32-bit value X + OFFSET has a different sign from X. */
1747 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1748 return offset_within_block_p (x, INTVAL (offset));
1750 /* In other cases the relocations can handle any offset. */
1753 case SYMBOL_PC_RELATIVE:
1754 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1755 In this case, we no longer have access to the underlying constant,
1756 but the original symbol-based access was known to be valid. */
1757 if (GET_CODE (x) == LABEL_REF)
1762 case SYMBOL_GP_RELATIVE:
1763 /* Make sure that the offset refers to something within the
1764 same object block. This should guarantee that the final
1765 PC- or GP-relative offset is within the 16-bit limit. */
1766 return offset_within_block_p (x, INTVAL (offset));
1768 case SYMBOL_GOT_PAGE_OFST:
1769 case SYMBOL_GOTOFF_PAGE:
1770 /* If the symbol is global, the GOT entry will contain the symbol's
1771 address, and we will apply a 16-bit offset after loading it.
1772 If the symbol is local, the linker should provide enough local
1773 GOT entries for a 16-bit offset, but larger offsets may lead
1775 return SMALL_INT (offset);
1779 /* There is no carry between the HI and LO REL relocations, so the
1780 offset is only valid if we know it won't lead to such a carry. */
1781 return mips_offset_within_alignment_p (x, INTVAL (offset));
1783 case SYMBOL_GOT_DISP:
1784 case SYMBOL_GOTOFF_DISP:
1785 case SYMBOL_GOTOFF_CALL:
1786 case SYMBOL_GOTOFF_LOADGP:
1789 case SYMBOL_GOTTPREL:
1797 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1798 single instruction. We rely on the fact that, in the worst case,
1799 all instructions involved in a MIPS16 address calculation are usually
1803 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1807 case SYMBOL_ABSOLUTE:
1808 /* When using 64-bit symbols, we need 5 preparatory instructions,
1811 lui $at,%highest(symbol)
1812 daddiu $at,$at,%higher(symbol)
1814 daddiu $at,$at,%hi(symbol)
1817 The final address is then $at + %lo(symbol). With 32-bit
1818 symbols we just need a preparatory LUI for normal mode and
1819 a preparatory LI and SLL for MIPS16. */
1820 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1822 case SYMBOL_GP_RELATIVE:
1823 /* Treat GP-relative accesses as taking a single instruction on
1824 MIPS16 too; the copy of $gp can often be shared. */
1827 case SYMBOL_PC_RELATIVE:
1828 /* PC-relative constants can be only be used with ADDIUPC,
1829 DADDIUPC, LWPC and LDPC. */
1830 if (mode == MAX_MACHINE_MODE
1831 || GET_MODE_SIZE (mode) == 4
1832 || GET_MODE_SIZE (mode) == 8)
1835 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1838 case SYMBOL_FORCE_TO_MEM:
1839 /* LEAs will be converted into constant-pool references by
1841 if (mode == MAX_MACHINE_MODE)
1844 /* The constant must be loaded and then dereferenced. */
1847 case SYMBOL_GOT_DISP:
1848 /* The constant will have to be loaded from the GOT before it
1849 is used in an address. */
1850 if (mode != MAX_MACHINE_MODE)
1855 case SYMBOL_GOT_PAGE_OFST:
1856 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1857 local/global classification is accurate. The worst cases are:
1859 (1) For local symbols when generating o32 or o64 code. The assembler
1865 ...and the final address will be $at + %lo(symbol).
1867 (2) For global symbols when -mxgot. The assembler will use:
1869 lui $at,%got_hi(symbol)
1872 ...and the final address will be $at + %got_lo(symbol). */
1875 case SYMBOL_GOTOFF_PAGE:
1876 case SYMBOL_GOTOFF_DISP:
1877 case SYMBOL_GOTOFF_CALL:
1878 case SYMBOL_GOTOFF_LOADGP:
1879 case SYMBOL_32_HIGH:
1880 case SYMBOL_64_HIGH:
1886 case SYMBOL_GOTTPREL:
1889 /* A 16-bit constant formed by a single relocation, or a 32-bit
1890 constant formed from a high 16-bit relocation and a low 16-bit
1891 relocation. Use mips_split_p to determine which. 32-bit
1892 constants need an "lui; addiu" sequence for normal mode and
1893 an "li; sll; addiu" sequence for MIPS16 mode. */
1894 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1897 /* We don't treat a bare TLS symbol as a constant. */
1903 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1904 to load symbols of type TYPE into a register. Return 0 if the given
1905 type of symbol cannot be used as an immediate operand.
1907 Otherwise, return the number of instructions needed to load or store
1908 values of mode MODE to or from addresses of type TYPE. Return 0 if
1909 the given type of symbol is not valid in addresses.
1911 In both cases, treat extended MIPS16 instructions as two instructions. */
1914 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1916 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1919 /* A for_each_rtx callback. Stop the search if *X references a
1920 thread-local symbol. */
1923 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1925 return mips_tls_symbol_p (*x);
1928 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1931 mips_cannot_force_const_mem (rtx x)
1933 enum mips_symbol_type type;
1936 /* There is no assembler syntax for expressing an address-sized
1938 if (GET_CODE (x) == HIGH)
1941 /* As an optimization, reject constants that mips_legitimize_move
1944 Suppose we have a multi-instruction sequence that loads constant C
1945 into register R. If R does not get allocated a hard register, and
1946 R is used in an operand that allows both registers and memory
1947 references, reload will consider forcing C into memory and using
1948 one of the instruction's memory alternatives. Returning false
1949 here will force it to use an input reload instead. */
1950 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1953 split_const (x, &base, &offset);
1954 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1955 && type != SYMBOL_FORCE_TO_MEM)
1957 /* The same optimization as for CONST_INT. */
1958 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1961 /* If MIPS16 constant pools live in the text section, they should
1962 not refer to anything that might need run-time relocation. */
1963 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1967 /* TLS symbols must be computed by mips_legitimize_move. */
1968 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
1974 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
1975 constants when we're using a per-function constant pool. */
1978 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1979 const_rtx x ATTRIBUTE_UNUSED)
1981 return !TARGET_MIPS16_PCREL_LOADS;
1984 /* Return true if register REGNO is a valid base register for mode MODE.
1985 STRICT_P is true if REG_OK_STRICT is in effect. */
1988 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
1991 if (!HARD_REGISTER_NUM_P (regno))
1995 regno = reg_renumber[regno];
1998 /* These fake registers will be eliminated to either the stack or
1999 hard frame pointer, both of which are usually valid base registers.
2000 Reload deals with the cases where the eliminated form isn't valid. */
2001 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2004 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2005 values, nothing smaller. There are two problems here:
2007 (a) Instantiating virtual registers can introduce new uses of the
2008 stack pointer. If these virtual registers are valid addresses,
2009 the stack pointer should be too.
2011 (b) Most uses of the stack pointer are not made explicit until
2012 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2013 We don't know until that stage whether we'll be eliminating to the
2014 stack pointer (which needs the restriction) or the hard frame
2015 pointer (which doesn't).
2017 All in all, it seems more consistent to only enforce this restriction
2018 during and after reload. */
2019 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2020 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2022 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2025 /* Return true if X is a valid base register for mode MODE.
2026 STRICT_P is true if REG_OK_STRICT is in effect. */
2029 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2031 if (!strict_p && GET_CODE (x) == SUBREG)
2035 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2038 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2039 can address a value of mode MODE. */
2042 mips_valid_offset_p (rtx x, enum machine_mode mode)
2044 /* Check that X is a signed 16-bit number. */
2045 if (!const_arith_operand (x, Pmode))
2048 /* We may need to split multiword moves, so make sure that every word
2050 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2051 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2057 /* Return true if a LO_SUM can address a value of mode MODE when the
2058 LO_SUM symbol has type SYMBOL_TYPE. */
2061 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2063 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2065 if (mips_symbol_insns (symbol_type, mode) == 0)
2068 /* Check that there is a known low-part relocation. */
2069 if (mips_lo_relocs[symbol_type] == NULL)
2072 /* We may need to split multiword moves, so make sure that each word
2073 can be accessed without inducing a carry. This is mainly needed
2074 for o64, which has historically only guaranteed 64-bit alignment
2075 for 128-bit types. */
2076 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2077 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2083 /* Return true if X is a valid address for machine mode MODE. If it is,
2084 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2088 mips_classify_address (struct mips_address_info *info, rtx x,
2089 enum machine_mode mode, bool strict_p)
2091 switch (GET_CODE (x))
2095 info->type = ADDRESS_REG;
2097 info->offset = const0_rtx;
2098 return mips_valid_base_register_p (info->reg, mode, strict_p);
2101 info->type = ADDRESS_REG;
2102 info->reg = XEXP (x, 0);
2103 info->offset = XEXP (x, 1);
2104 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2105 && mips_valid_offset_p (info->offset, mode));
2108 info->type = ADDRESS_LO_SUM;
2109 info->reg = XEXP (x, 0);
2110 info->offset = XEXP (x, 1);
2111 /* We have to trust the creator of the LO_SUM to do something vaguely
2112 sane. Target-independent code that creates a LO_SUM should also
2113 create and verify the matching HIGH. Target-independent code that
2114 adds an offset to a LO_SUM must prove that the offset will not
2115 induce a carry. Failure to do either of these things would be
2116 a bug, and we are not required to check for it here. The MIPS
2117 backend itself should only create LO_SUMs for valid symbolic
2118 constants, with the high part being either a HIGH or a copy
2121 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2122 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2123 && mips_valid_lo_sum_p (info->symbol_type, mode));
2126 /* Small-integer addresses don't occur very often, but they
2127 are legitimate if $0 is a valid base register. */
2128 info->type = ADDRESS_CONST_INT;
2129 return !TARGET_MIPS16 && SMALL_INT (x);
2134 info->type = ADDRESS_SYMBOLIC;
2135 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2137 && mips_symbol_insns (info->symbol_type, mode) > 0
2138 && !mips_split_p[info->symbol_type]);
2145 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2148 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2150 struct mips_address_info addr;
2152 return mips_classify_address (&addr, x, mode, strict_p);
2155 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2158 mips_stack_address_p (rtx x, enum machine_mode mode)
2160 struct mips_address_info addr;
2162 return (mips_classify_address (&addr, x, mode, false)
2163 && addr.type == ADDRESS_REG
2164 && addr.reg == stack_pointer_rtx);
2167 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2168 address instruction. Note that such addresses are not considered
2169 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2170 is so restricted. */
2173 mips_lwxs_address_p (rtx addr)
2176 && GET_CODE (addr) == PLUS
2177 && REG_P (XEXP (addr, 1)))
2179 rtx offset = XEXP (addr, 0);
2180 if (GET_CODE (offset) == MULT
2181 && REG_P (XEXP (offset, 0))
2182 && CONST_INT_P (XEXP (offset, 1))
2183 && INTVAL (XEXP (offset, 1)) == 4)
2189 /* Return true if a value at OFFSET bytes from base register BASE can be
2190 accessed using an unextended MIPS16 instruction. MODE is the mode of
2193 Usually the offset in an unextended instruction is a 5-bit field.
2194 The offset is unsigned and shifted left once for LH and SH, twice
2195 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2196 an 8-bit immediate field that's shifted left twice. */
2199 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2200 unsigned HOST_WIDE_INT offset)
2202 if (offset % GET_MODE_SIZE (mode) == 0)
2204 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2205 return offset < 256U * GET_MODE_SIZE (mode);
2206 return offset < 32U * GET_MODE_SIZE (mode);
2211 /* Return the number of instructions needed to load or store a value
2212 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2213 Assume that multiword moves may need to be split into word moves
2214 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2217 For MIPS16 code, count extended instructions as two instructions. */
2220 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2222 struct mips_address_info addr;
2225 /* BLKmode is used for single unaligned loads and stores and should
2226 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2227 meaningless, so we have to single it out as a special case one way
2229 if (mode != BLKmode && might_split_p)
2230 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2234 if (mips_classify_address (&addr, x, mode, false))
2239 && !mips16_unextended_reference_p (mode, addr.reg,
2240 UINTVAL (addr.offset)))
2244 case ADDRESS_LO_SUM:
2245 return TARGET_MIPS16 ? factor * 2 : factor;
2247 case ADDRESS_CONST_INT:
2250 case ADDRESS_SYMBOLIC:
2251 return factor * mips_symbol_insns (addr.symbol_type, mode);
2256 /* Return the number of instructions needed to load constant X.
2257 Return 0 if X isn't a valid constant. */
2260 mips_const_insns (rtx x)
2262 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2263 enum mips_symbol_type symbol_type;
2266 switch (GET_CODE (x))
2269 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2271 || !mips_split_p[symbol_type])
2274 /* This is simply an LUI for normal mode. It is an extended
2275 LI followed by an extended SLL for MIPS16. */
2276 return TARGET_MIPS16 ? 4 : 1;
2280 /* Unsigned 8-bit constants can be loaded using an unextended
2281 LI instruction. Unsigned 16-bit constants can be loaded
2282 using an extended LI. Negative constants must be loaded
2283 using LI and then negated. */
2284 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2285 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2286 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2287 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2290 return mips_build_integer (codes, INTVAL (x));
2294 /* Allow zeros for normal mode, where we can use $0. */
2295 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2301 /* See if we can refer to X directly. */
2302 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2303 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2305 /* Otherwise try splitting the constant into a base and offset.
2306 If the offset is a 16-bit value, we can load the base address
2307 into a register and then use (D)ADDIU to add in the offset.
2308 If the offset is larger, we can load the base and offset
2309 into separate registers and add them together with (D)ADDU.
2310 However, the latter is only possible before reload; during
2311 and after reload, we must have the option of forcing the
2312 constant into the pool instead. */
2313 split_const (x, &x, &offset);
2316 int n = mips_const_insns (x);
2319 if (SMALL_INT (offset))
2321 else if (!targetm.cannot_force_const_mem (x))
2322 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2329 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2337 /* X is a doubleword constant that can be handled by splitting it into
2338 two words and loading each word separately. Return the number of
2339 instructions required to do this. */
2342 mips_split_const_insns (rtx x)
2344 unsigned int low, high;
2346 low = mips_const_insns (mips_subword (x, false));
2347 high = mips_const_insns (mips_subword (x, true));
2348 gcc_assert (low > 0 && high > 0);
2352 /* Return the number of instructions needed to implement INSN,
2353 given that it loads from or stores to MEM. Count extended
2354 MIPS16 instructions as two instructions. */
2357 mips_load_store_insns (rtx mem, rtx insn)
2359 enum machine_mode mode;
2363 gcc_assert (MEM_P (mem));
2364 mode = GET_MODE (mem);
2366 /* Try to prove that INSN does not need to be split. */
2367 might_split_p = true;
2368 if (GET_MODE_BITSIZE (mode) == 64)
2370 set = single_set (insn);
2371 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2372 might_split_p = false;
2375 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2378 /* Return the number of instructions needed for an integer division. */
2381 mips_idiv_insns (void)
2386 if (TARGET_CHECK_ZERO_DIV)
2388 if (GENERATE_DIVIDE_TRAPS)
2394 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2399 /* Emit a move from SRC to DEST. Assume that the move expanders can
2400 handle all moves if !can_create_pseudo_p (). The distinction is
2401 important because, unlike emit_move_insn, the move expanders know
2402 how to force Pmode objects into the constant pool even when the
2403 constant pool address is not itself legitimate. */
2406 mips_emit_move (rtx dest, rtx src)
2408 return (can_create_pseudo_p ()
2409 ? emit_move_insn (dest, src)
2410 : emit_move_insn_1 (dest, src));
2413 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2416 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2418 emit_insn (gen_rtx_SET (VOIDmode, target,
2419 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2422 /* Compute (CODE OP0 OP1) and store the result in a new register
2423 of mode MODE. Return that new register. */
2426 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2430 reg = gen_reg_rtx (mode);
2431 mips_emit_binary (code, reg, op0, op1);
2435 /* Copy VALUE to a register and return that register. If new pseudos
2436 are allowed, copy it into a new register, otherwise use DEST. */
2439 mips_force_temporary (rtx dest, rtx value)
2441 if (can_create_pseudo_p ())
2442 return force_reg (Pmode, value);
2445 mips_emit_move (dest, value);
2450 /* Emit a call sequence with call pattern PATTERN and return the call
2451 instruction itself (which is not necessarily the last instruction
2452 emitted). ORIG_ADDR is the original, unlegitimized address,
2453 ADDR is the legitimized form, and LAZY_P is true if the call
2454 address is lazily-bound. */
2457 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2461 insn = emit_call_insn (pattern);
2463 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2465 /* MIPS16 JALRs only take MIPS16 registers. If the target
2466 function requires $25 to be valid on entry, we must copy it
2467 there separately. The move instruction can be put in the
2468 call's delay slot. */
2469 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2470 emit_insn_before (gen_move_insn (reg, addr), insn);
2471 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2475 /* Lazy-binding stubs require $gp to be valid on entry. */
2476 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2480 /* See the comment above load_call<mode> for details. */
2481 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2482 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2483 emit_insn (gen_update_got_version ());
2488 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2489 then add CONST_INT OFFSET to the result. */
2492 mips_unspec_address_offset (rtx base, rtx offset,
2493 enum mips_symbol_type symbol_type)
2495 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2496 UNSPEC_ADDRESS_FIRST + symbol_type);
2497 if (offset != const0_rtx)
2498 base = gen_rtx_PLUS (Pmode, base, offset);
2499 return gen_rtx_CONST (Pmode, base);
2502 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2503 type SYMBOL_TYPE. */
2506 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2510 split_const (address, &base, &offset);
2511 return mips_unspec_address_offset (base, offset, symbol_type);
2514 /* If OP is an UNSPEC address, return the address to which it refers,
2515 otherwise return OP itself. */
2518 mips_strip_unspec_address (rtx op)
2522 split_const (op, &base, &offset);
2523 if (UNSPEC_ADDRESS_P (base))
2524 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2528 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2529 high part to BASE and return the result. Just return BASE otherwise.
2530 TEMP is as for mips_force_temporary.
2532 The returned expression can be used as the first operand to a LO_SUM. */
2535 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2536 enum mips_symbol_type symbol_type)
2538 if (mips_split_p[symbol_type])
2540 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2541 addr = mips_force_temporary (temp, addr);
2542 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2547 /* Return an instruction that copies $gp into register REG. We want
2548 GCC to treat the register's value as constant, so that its value
2549 can be rematerialized on demand. */
2552 gen_load_const_gp (rtx reg)
2554 return (Pmode == SImode
2555 ? gen_load_const_gp_si (reg)
2556 : gen_load_const_gp_di (reg));
2559 /* Return a pseudo register that contains the value of $gp throughout
2560 the current function. Such registers are needed by MIPS16 functions,
2561 for which $gp itself is not a valid base register or addition operand. */
2564 mips16_gp_pseudo_reg (void)
2566 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2567 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2569 /* Don't emit an instruction to initialize the pseudo register if
2570 we are being called from the tree optimizers' cost-calculation
2572 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2573 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2577 push_topmost_sequence ();
2579 scan = get_insns ();
2580 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2581 scan = NEXT_INSN (scan);
2583 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2584 emit_insn_after (insn, scan);
2586 pop_topmost_sequence ();
2588 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2591 return cfun->machine->mips16_gp_pseudo_rtx;
2594 /* Return a base register that holds pic_offset_table_rtx.
2595 TEMP, if nonnull, is a scratch Pmode base register. */
2598 mips_pic_base_register (rtx temp)
2601 return pic_offset_table_rtx;
2603 if (can_create_pseudo_p ())
2604 return mips16_gp_pseudo_reg ();
2607 /* The first post-reload split exposes all references to $gp
2608 (both uses and definitions). All references must remain
2609 explicit after that point.
2611 It is safe to introduce uses of $gp at any time, so for
2612 simplicity, we do that before the split too. */
2613 mips_emit_move (temp, pic_offset_table_rtx);
2615 emit_insn (gen_load_const_gp (temp));
2619 /* Return the RHS of a load_call<mode> insn. */
2622 mips_unspec_call (rtx reg, rtx symbol)
2626 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2627 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2630 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2631 reference. Return NULL_RTX otherwise. */
2634 mips_strip_unspec_call (rtx src)
2636 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2637 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2641 /* Create and return a GOT reference of type TYPE for address ADDR.
2642 TEMP, if nonnull, is a scratch Pmode base register. */
2645 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2647 rtx base, high, lo_sum_symbol;
2649 base = mips_pic_base_register (temp);
2651 /* If we used the temporary register to load $gp, we can't use
2652 it for the high part as well. */
2653 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2656 high = mips_unspec_offset_high (temp, base, addr, type);
2657 lo_sum_symbol = mips_unspec_address (addr, type);
2659 if (type == SYMBOL_GOTOFF_CALL)
2660 return mips_unspec_call (high, lo_sum_symbol);
2662 return (Pmode == SImode
2663 ? gen_unspec_gotsi (high, lo_sum_symbol)
2664 : gen_unspec_gotdi (high, lo_sum_symbol));
2667 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2668 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2669 constant in that context and can be split into high and low parts.
2670 If so, and if LOW_OUT is nonnull, emit the high part and store the
2671 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2673 TEMP is as for mips_force_temporary and is used to load the high
2674 part into a register.
2676 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2677 a legitimize SET_SRC for an .md pattern, otherwise the low part
2678 is guaranteed to be a legitimate address for mode MODE. */
2681 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2683 enum mips_symbol_context context;
2684 enum mips_symbol_type symbol_type;
2687 context = (mode == MAX_MACHINE_MODE
2688 ? SYMBOL_CONTEXT_LEA
2689 : SYMBOL_CONTEXT_MEM);
2690 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2692 addr = XEXP (addr, 0);
2693 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2694 && mips_symbol_insns (symbol_type, mode) > 0
2695 && mips_split_hi_p[symbol_type])
2698 switch (symbol_type)
2700 case SYMBOL_GOT_PAGE_OFST:
2701 /* The high part of a page/ofst pair is loaded from the GOT. */
2702 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2713 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2714 && mips_symbol_insns (symbol_type, mode) > 0
2715 && mips_split_p[symbol_type])
2718 switch (symbol_type)
2720 case SYMBOL_GOT_DISP:
2721 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2722 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2725 case SYMBOL_GP_RELATIVE:
2726 high = mips_pic_base_register (temp);
2727 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2731 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2732 high = mips_force_temporary (temp, high);
2733 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2742 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2743 mips_force_temporary; it is only needed when OFFSET is not a
2747 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2749 if (!SMALL_OPERAND (offset))
2755 /* Load the full offset into a register so that we can use
2756 an unextended instruction for the address itself. */
2757 high = GEN_INT (offset);
2762 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2763 The addition inside the macro CONST_HIGH_PART may cause an
2764 overflow, so we need to force a sign-extension check. */
2765 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2766 offset = CONST_LOW_PART (offset);
2768 high = mips_force_temporary (temp, high);
2769 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2771 return plus_constant (reg, offset);
2774 /* The __tls_get_attr symbol. */
2775 static GTY(()) rtx mips_tls_symbol;
2777 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2778 the TLS symbol we are referencing and TYPE is the symbol type to use
2779 (either global dynamic or local dynamic). V0 is an RTX for the
2780 return value location. */
2783 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2787 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2789 if (!mips_tls_symbol)
2790 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2792 loc = mips_unspec_address (sym, type);
2796 emit_insn (gen_rtx_SET (Pmode, a0,
2797 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2798 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2799 const0_rtx, NULL_RTX, false);
2800 RTL_CONST_CALL_P (insn) = 1;
2801 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2802 insn = get_insns ();
2809 /* Return a pseudo register that contains the current thread pointer. */
2816 tp = gen_reg_rtx (Pmode);
2817 if (Pmode == DImode)
2818 emit_insn (gen_tls_get_tp_di (tp));
2820 emit_insn (gen_tls_get_tp_si (tp));
2824 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2825 its address. The return value will be both a valid address and a valid
2826 SET_SRC (either a REG or a LO_SUM). */
2829 mips_legitimize_tls_address (rtx loc)
2831 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2832 enum tls_model model;
2836 sorry ("MIPS16 TLS");
2837 return gen_reg_rtx (Pmode);
2840 model = SYMBOL_REF_TLS_MODEL (loc);
2841 /* Only TARGET_ABICALLS code can have more than one module; other
2842 code must be be static and should not use a GOT. All TLS models
2843 reduce to local exec in this situation. */
2844 if (!TARGET_ABICALLS)
2845 model = TLS_MODEL_LOCAL_EXEC;
2849 case TLS_MODEL_GLOBAL_DYNAMIC:
2850 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2851 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2852 dest = gen_reg_rtx (Pmode);
2853 emit_libcall_block (insn, dest, v0, loc);
2856 case TLS_MODEL_LOCAL_DYNAMIC:
2857 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2858 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2859 tmp1 = gen_reg_rtx (Pmode);
2861 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2862 share the LDM result with other LD model accesses. */
2863 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2865 emit_libcall_block (insn, tmp1, v0, eqv);
2867 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2868 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2869 mips_unspec_address (loc, SYMBOL_DTPREL));
2872 case TLS_MODEL_INITIAL_EXEC:
2873 tp = mips_get_tp ();
2874 tmp1 = gen_reg_rtx (Pmode);
2875 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2876 if (Pmode == DImode)
2877 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2879 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2880 dest = gen_reg_rtx (Pmode);
2881 emit_insn (gen_add3_insn (dest, tmp1, tp));
2884 case TLS_MODEL_LOCAL_EXEC:
2885 tp = mips_get_tp ();
2886 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2887 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2888 mips_unspec_address (loc, SYMBOL_TPREL));
2897 /* If X is not a valid address for mode MODE, force it into a register. */
2900 mips_force_address (rtx x, enum machine_mode mode)
2902 if (!mips_legitimate_address_p (mode, x, false))
2903 x = force_reg (Pmode, x);
2907 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2908 be legitimized in a way that the generic machinery might not expect,
2909 return a new address, otherwise return NULL. MODE is the mode of
2910 the memory being accessed. */
2913 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2914 enum machine_mode mode)
2917 HOST_WIDE_INT offset;
2919 if (mips_tls_symbol_p (x))
2920 return mips_legitimize_tls_address (x);
2922 /* See if the address can split into a high part and a LO_SUM. */
2923 if (mips_split_symbol (NULL, x, mode, &addr))
2924 return mips_force_address (addr, mode);
2926 /* Handle BASE + OFFSET using mips_add_offset. */
2927 mips_split_plus (x, &base, &offset);
2930 if (!mips_valid_base_register_p (base, mode, false))
2931 base = copy_to_mode_reg (Pmode, base);
2932 addr = mips_add_offset (NULL, base, offset);
2933 return mips_force_address (addr, mode);
2939 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
2942 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
2944 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2945 enum machine_mode mode;
2946 unsigned int i, num_ops;
2949 mode = GET_MODE (dest);
2950 num_ops = mips_build_integer (codes, value);
2952 /* Apply each binary operation to X. Invariant: X is a legitimate
2953 source operand for a SET pattern. */
2954 x = GEN_INT (codes[0].value);
2955 for (i = 1; i < num_ops; i++)
2957 if (!can_create_pseudo_p ())
2959 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2963 x = force_reg (mode, x);
2964 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2967 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2970 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2971 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2975 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2979 /* Split moves of big integers into smaller pieces. */
2980 if (splittable_const_int_operand (src, mode))
2982 mips_move_integer (dest, dest, INTVAL (src));
2986 /* Split moves of symbolic constants into high/low pairs. */
2987 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
2989 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
2993 /* Generate the appropriate access sequences for TLS symbols. */
2994 if (mips_tls_symbol_p (src))
2996 mips_emit_move (dest, mips_legitimize_tls_address (src));
3000 /* If we have (const (plus symbol offset)), and that expression cannot
3001 be forced into memory, load the symbol first and add in the offset.
3002 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3003 forced into memory, as it usually produces better code. */
3004 split_const (src, &base, &offset);
3005 if (offset != const0_rtx
3006 && (targetm.cannot_force_const_mem (src)
3007 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3009 base = mips_force_temporary (dest, base);
3010 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3014 src = force_const_mem (mode, src);
3016 /* When using explicit relocs, constant pool references are sometimes
3017 not legitimate addresses. */
3018 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3019 mips_emit_move (dest, src);
3022 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3023 sequence that is valid. */
3026 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3028 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3030 mips_emit_move (dest, force_reg (mode, src));
3034 /* We need to deal with constants that would be legitimate
3035 immediate_operands but aren't legitimate move_operands. */
3036 if (CONSTANT_P (src) && !move_operand (src, mode))
3038 mips_legitimize_const_move (mode, dest, src);
3039 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3045 /* Return true if value X in context CONTEXT is a small-data address
3046 that can be rewritten as a LO_SUM. */
3049 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3051 enum mips_symbol_type symbol_type;
3053 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3054 && !mips_split_p[SYMBOL_GP_RELATIVE]
3055 && mips_symbolic_constant_p (x, context, &symbol_type)
3056 && symbol_type == SYMBOL_GP_RELATIVE);
3059 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3060 containing MEM, or null if none. */
3063 mips_small_data_pattern_1 (rtx *loc, void *data)
3065 enum mips_symbol_context context;
3067 if (GET_CODE (*loc) == LO_SUM)
3072 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3077 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3078 return mips_rewrite_small_data_p (*loc, context);
3081 /* Return true if OP refers to small data symbols directly, not through
3085 mips_small_data_pattern_p (rtx op)
3087 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3090 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3091 DATA is the containing MEM, or null if none. */
3094 mips_rewrite_small_data_1 (rtx *loc, void *data)
3096 enum mips_symbol_context context;
3100 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3104 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3105 if (mips_rewrite_small_data_p (*loc, context))
3106 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3108 if (GET_CODE (*loc) == LO_SUM)
3114 /* Rewrite instruction pattern PATTERN so that it refers to small data
3115 using explicit relocations. */
3118 mips_rewrite_small_data (rtx pattern)
3120 pattern = copy_insn (pattern);
3121 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3125 /* We need a lot of little routines to check the range of MIPS16 immediate
3129 m16_check_op (rtx op, int low, int high, int mask)
3131 return (CONST_INT_P (op)
3132 && IN_RANGE (INTVAL (op), low, high)
3133 && (INTVAL (op) & mask) == 0);
3137 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3139 return m16_check_op (op, 0x1, 0x8, 0);
3143 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3145 return m16_check_op (op, -0x8, 0x7, 0);
3149 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3151 return m16_check_op (op, -0x7, 0x8, 0);
3155 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3157 return m16_check_op (op, -0x10, 0xf, 0);
3161 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3163 return m16_check_op (op, -0xf, 0x10, 0);
3167 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3169 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3173 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3175 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3179 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3181 return m16_check_op (op, -0x80, 0x7f, 0);
3185 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3187 return m16_check_op (op, -0x7f, 0x80, 0);
3191 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3193 return m16_check_op (op, 0x0, 0xff, 0);
3197 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3199 return m16_check_op (op, -0xff, 0x0, 0);
3203 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3205 return m16_check_op (op, -0x1, 0xfe, 0);
3209 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3211 return m16_check_op (op, 0x0, 0xff << 2, 3);
3215 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3217 return m16_check_op (op, -0xff << 2, 0x0, 3);
3221 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3223 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3227 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3229 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3232 /* The cost of loading values from the constant pool. It should be
3233 larger than the cost of any constant we want to synthesize inline. */
3234 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3236 /* Return the cost of X when used as an operand to the MIPS16 instruction
3237 that implements CODE. Return -1 if there is no such instruction, or if
3238 X is not a valid immediate operand for it. */
3241 mips16_constant_cost (int code, HOST_WIDE_INT x)
3248 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3249 other shifts are extended. The shift patterns truncate the shift
3250 count to the right size, so there are no out-of-range values. */
3251 if (IN_RANGE (x, 1, 8))
3253 return COSTS_N_INSNS (1);
3256 if (IN_RANGE (x, -128, 127))
3258 if (SMALL_OPERAND (x))
3259 return COSTS_N_INSNS (1);
3263 /* Like LE, but reject the always-true case. */
3267 /* We add 1 to the immediate and use SLT. */
3270 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3273 if (IN_RANGE (x, 0, 255))
3275 if (SMALL_OPERAND_UNSIGNED (x))
3276 return COSTS_N_INSNS (1);
3281 /* Equality comparisons with 0 are cheap. */
3291 /* Return true if there is a non-MIPS16 instruction that implements CODE
3292 and if that instruction accepts X as an immediate operand. */
3295 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3302 /* All shift counts are truncated to a valid constant. */
3307 /* Likewise rotates, if the target supports rotates at all. */
3313 /* These instructions take 16-bit unsigned immediates. */
3314 return SMALL_OPERAND_UNSIGNED (x);
3319 /* These instructions take 16-bit signed immediates. */
3320 return SMALL_OPERAND (x);
3326 /* The "immediate" forms of these instructions are really
3327 implemented as comparisons with register 0. */
3332 /* Likewise, meaning that the only valid immediate operand is 1. */
3336 /* We add 1 to the immediate and use SLT. */
3337 return SMALL_OPERAND (x + 1);
3340 /* Likewise SLTU, but reject the always-true case. */
3341 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3345 /* The bit position and size are immediate operands. */
3346 return ISA_HAS_EXT_INS;
3349 /* By default assume that $0 can be used for 0. */
3354 /* Return the cost of binary operation X, given that the instruction
3355 sequence for a word-sized or smaller operation has cost SINGLE_COST
3356 and that the sequence of a double-word operation has cost DOUBLE_COST. */
3359 mips_binary_cost (rtx x, int single_cost, int double_cost)
3363 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3368 + rtx_cost (XEXP (x, 0), SET, !optimize_size)
3369 + rtx_cost (XEXP (x, 1), GET_CODE (x), !optimize_size));
3372 /* Return the cost of floating-point multiplications of mode MODE. */
3375 mips_fp_mult_cost (enum machine_mode mode)
3377 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3380 /* Return the cost of floating-point divisions of mode MODE. */
3383 mips_fp_div_cost (enum machine_mode mode)
3385 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3388 /* Return the cost of sign-extending OP to mode MODE, not including the
3389 cost of OP itself. */
3392 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3395 /* Extended loads are as cheap as unextended ones. */
3398 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3399 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3402 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3403 /* We can use SEB or SEH. */
3404 return COSTS_N_INSNS (1);
3406 /* We need to use a shift left and a shift right. */
3407 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3410 /* Return the cost of zero-extending OP to mode MODE, not including the
3411 cost of OP itself. */
3414 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3417 /* Extended loads are as cheap as unextended ones. */
3420 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3421 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3422 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3424 if (GENERATE_MIPS16E)
3425 /* We can use ZEB or ZEH. */
3426 return COSTS_N_INSNS (1);
3429 /* We need to load 0xff or 0xffff into a register and use AND. */
3430 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3432 /* We can use ANDI. */
3433 return COSTS_N_INSNS (1);
3436 /* Implement TARGET_RTX_COSTS. */
3439 mips_rtx_costs (rtx x, int code, int outer_code, int *total,
3442 enum machine_mode mode = GET_MODE (x);
3443 bool float_mode_p = FLOAT_MODE_P (mode);
3447 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3448 appear in the instruction stream, and the cost of a comparison is
3449 really the cost of the branch or scc condition. At the time of
3450 writing, GCC only uses an explicit outer COMPARE code when optabs
3451 is testing whether a constant is expensive enough to force into a
3452 register. We want optabs to pass such constants through the MIPS
3453 expanders instead, so make all constants very cheap here. */
3454 if (outer_code == COMPARE)
3456 gcc_assert (CONSTANT_P (x));
3464 /* Treat *clear_upper32-style ANDs as having zero cost in the
3465 second operand. The cost is entirely in the first operand.
3467 ??? This is needed because we would otherwise try to CSE
3468 the constant operand. Although that's the right thing for
3469 instructions that continue to be a register operation throughout
3470 compilation, it is disastrous for instructions that could
3471 later be converted into a memory operation. */
3473 && outer_code == AND
3474 && UINTVAL (x) == 0xffffffff)
3482 cost = mips16_constant_cost (outer_code, INTVAL (x));
3491 /* When not optimizing for size, we care more about the cost
3492 of hot code, and hot code is often in a loop. If a constant
3493 operand needs to be forced into a register, we will often be
3494 able to hoist the constant load out of the loop, so the load
3495 should not contribute to the cost. */
3497 || mips_immediate_operand_p (outer_code, INTVAL (x)))
3509 if (force_to_mem_operand (x, VOIDmode))
3511 *total = COSTS_N_INSNS (1);
3514 cost = mips_const_insns (x);
3517 /* If the constant is likely to be stored in a GPR, SETs of
3518 single-insn constants are as cheap as register sets; we
3519 never want to CSE them.
3521 Don't reduce the cost of storing a floating-point zero in
3522 FPRs. If we have a zero in an FPR for other reasons, we
3523 can get better cfg-cleanup and delayed-branch results by
3524 using it consistently, rather than using $0 sometimes and
3525 an FPR at other times. Also, moves between floating-point
3526 registers are sometimes cheaper than (D)MTC1 $0. */
3528 && outer_code == SET
3529 && !(float_mode_p && TARGET_HARD_FLOAT))
3531 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3532 want to CSE the constant itself. It is usually better to
3533 have N copies of the last operation in the sequence and one
3534 shared copy of the other operations. (Note that this is
3535 not true for MIPS16 code, where the final operation in the
3536 sequence is often an extended instruction.)
3538 Also, if we have a CONST_INT, we don't know whether it is
3539 for a word or doubleword operation, so we cannot rely on
3540 the result of mips_build_integer. */
3541 else if (!TARGET_MIPS16
3542 && (outer_code == SET || mode == VOIDmode))
3544 *total = COSTS_N_INSNS (cost);
3547 /* The value will need to be fetched from the constant pool. */
3548 *total = CONSTANT_POOL_COST;
3552 /* If the address is legitimate, return the number of
3553 instructions it needs. */
3555 cost = mips_address_insns (addr, mode, true);
3558 *total = COSTS_N_INSNS (cost + 1);
3561 /* Check for a scaled indexed address. */
3562 if (mips_lwxs_address_p (addr))
3564 *total = COSTS_N_INSNS (2);
3567 /* Otherwise use the default handling. */
3571 *total = COSTS_N_INSNS (6);
3575 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3579 /* Check for a *clear_upper32 pattern and treat it like a zero
3580 extension. See the pattern's comment for details. */
3583 && CONST_INT_P (XEXP (x, 1))
3584 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3586 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3587 + rtx_cost (XEXP (x, 0), SET, speed));
3594 /* Double-word operations use two single-word operations. */
3595 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2));
3603 if (CONSTANT_P (XEXP (x, 1)))
3604 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3606 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12));
3611 *total = mips_cost->fp_add;
3613 *total = COSTS_N_INSNS (4);
3617 /* Low-part immediates need an extended MIPS16 instruction. */
3618 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3619 + rtx_cost (XEXP (x, 0), SET, speed));
3634 /* Branch comparisons have VOIDmode, so use the first operand's
3636 mode = GET_MODE (XEXP (x, 0));
3637 if (FLOAT_MODE_P (mode))
3639 *total = mips_cost->fp_add;
3642 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4));
3647 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3648 && TARGET_FUSED_MADD
3649 && !HONOR_NANS (mode)
3650 && !HONOR_SIGNED_ZEROS (mode))
3652 /* See if we can use NMADD or NMSUB. See mips.md for the
3653 associated patterns. */
3654 rtx op0 = XEXP (x, 0);
3655 rtx op1 = XEXP (x, 1);
3656 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3658 *total = (mips_fp_mult_cost (mode)
3659 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3660 + rtx_cost (XEXP (op0, 1), SET, speed)
3661 + rtx_cost (op1, SET, speed));
3664 if (GET_CODE (op1) == MULT)
3666 *total = (mips_fp_mult_cost (mode)
3667 + rtx_cost (op0, SET, speed)
3668 + rtx_cost (XEXP (op1, 0), SET, speed)
3669 + rtx_cost (XEXP (op1, 1), SET, speed));
3678 /* If this is part of a MADD or MSUB, treat the PLUS as
3681 && TARGET_FUSED_MADD
3682 && GET_CODE (XEXP (x, 0)) == MULT)
3685 *total = mips_cost->fp_add;
3689 /* Double-word operations require three single-word operations and
3690 an SLTU. The MIPS16 version then needs to move the result of
3691 the SLTU from $24 to a MIPS16 register. */
3692 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3693 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4));
3698 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3699 && TARGET_FUSED_MADD
3700 && !HONOR_NANS (mode)
3701 && HONOR_SIGNED_ZEROS (mode))
3703 /* See if we can use NMADD or NMSUB. See mips.md for the
3704 associated patterns. */
3705 rtx op = XEXP (x, 0);
3706 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3707 && GET_CODE (XEXP (op, 0)) == MULT)
3709 *total = (mips_fp_mult_cost (mode)
3710 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3711 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3712 + rtx_cost (XEXP (op, 1), SET, speed));
3718 *total = mips_cost->fp_add;
3720 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3725 *total = mips_fp_mult_cost (mode);
3726 else if (mode == DImode && !TARGET_64BIT)
3727 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3728 where the mulsidi3 always includes an MFHI and an MFLO. */
3729 *total = (optimize_size
3730 ? COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)
3731 : mips_cost->int_mult_si * 3 + 6);
3732 else if (optimize_size)
3733 *total = (ISA_HAS_MUL3 ? 1 : 2);
3734 else if (mode == DImode)
3735 *total = mips_cost->int_mult_di;
3737 *total = mips_cost->int_mult_si;
3741 /* Check for a reciprocal. */
3744 && flag_unsafe_math_optimizations
3745 && XEXP (x, 0) == CONST1_RTX (mode))
3747 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3748 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3749 division as being free. */
3750 *total = rtx_cost (XEXP (x, 1), SET, speed);
3752 *total = (mips_fp_div_cost (mode)
3753 + rtx_cost (XEXP (x, 1), SET, speed));
3762 *total = mips_fp_div_cost (mode);
3771 /* It is our responsibility to make division by a power of 2
3772 as cheap as 2 register additions if we want the division
3773 expanders to be used for such operations; see the setting
3774 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3775 should always produce shorter code than using
3776 expand_sdiv2_pow2. */
3778 && CONST_INT_P (XEXP (x, 1))
3779 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3781 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3784 *total = COSTS_N_INSNS (mips_idiv_insns ());
3786 else if (mode == DImode)
3787 *total = mips_cost->int_div_di;
3789 *total = mips_cost->int_div_si;
3793 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3797 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3801 case UNSIGNED_FLOAT:
3804 case FLOAT_TRUNCATE:
3805 *total = mips_cost->fp_add;
3813 /* Implement TARGET_ADDRESS_COST. */
3816 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3818 return mips_address_insns (addr, SImode, false);
3821 /* Information about a single instruction in a multi-instruction
3823 struct mips_multi_member {
3824 /* True if this is a label, false if it is code. */
3827 /* The output_asm_insn format of the instruction. */
3830 /* The operands to the instruction. */
3831 rtx operands[MAX_RECOG_OPERANDS];
3833 typedef struct mips_multi_member mips_multi_member;
3835 /* Vector definitions for the above. */
3836 DEF_VEC_O(mips_multi_member);
3837 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3839 /* The instructions that make up the current multi-insn sequence. */
3840 static VEC (mips_multi_member, heap) *mips_multi_members;
3842 /* How many instructions (as opposed to labels) are in the current
3843 multi-insn sequence. */
3844 static unsigned int mips_multi_num_insns;
3846 /* Start a new multi-insn sequence. */
3849 mips_multi_start (void)
3851 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3852 mips_multi_num_insns = 0;
3855 /* Add a new, uninitialized member to the current multi-insn sequence. */
3857 static struct mips_multi_member *
3858 mips_multi_add (void)
3860 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3863 /* Add a normal insn with the given asm format to the current multi-insn
3864 sequence. The other arguments are a null-terminated list of operands. */
3867 mips_multi_add_insn (const char *format, ...)
3869 struct mips_multi_member *member;
3874 member = mips_multi_add ();
3875 member->is_label_p = false;
3876 member->format = format;
3877 va_start (ap, format);
3879 while ((op = va_arg (ap, rtx)))
3880 member->operands[i++] = op;
3882 mips_multi_num_insns++;
3885 /* Add the given label definition to the current multi-insn sequence.
3886 The definition should include the colon. */
3889 mips_multi_add_label (const char *label)
3891 struct mips_multi_member *member;
3893 member = mips_multi_add ();
3894 member->is_label_p = true;
3895 member->format = label;
3898 /* Return the index of the last member of the current multi-insn sequence. */
3901 mips_multi_last_index (void)
3903 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3906 /* Add a copy of an existing instruction to the current multi-insn
3907 sequence. I is the index of the instruction that should be copied. */
3910 mips_multi_copy_insn (unsigned int i)
3912 struct mips_multi_member *member;
3914 member = mips_multi_add ();
3915 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3917 gcc_assert (!member->is_label_p);
3920 /* Change the operand of an existing instruction in the current
3921 multi-insn sequence. I is the index of the instruction,
3922 OP is the index of the operand, and X is the new value. */
3925 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3927 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3930 /* Write out the asm code for the current multi-insn sequence. */
3933 mips_multi_write (void)
3935 struct mips_multi_member *member;
3939 VEC_iterate (mips_multi_member, mips_multi_members, i, member);
3941 if (member->is_label_p)
3942 fprintf (asm_out_file, "%s\n", member->format);
3944 output_asm_insn (member->format, member->operands);
3947 /* Return one word of double-word value OP, taking into account the fixed
3948 endianness of certain registers. HIGH_P is true to select the high part,
3949 false to select the low part. */
3952 mips_subword (rtx op, bool high_p)
3954 unsigned int byte, offset;
3955 enum machine_mode mode;
3957 mode = GET_MODE (op);
3958 if (mode == VOIDmode)
3959 mode = TARGET_64BIT ? TImode : DImode;
3961 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
3962 byte = UNITS_PER_WORD;
3966 if (FP_REG_RTX_P (op))
3968 /* Paired FPRs are always ordered little-endian. */
3969 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
3970 return gen_rtx_REG (word_mode, REGNO (op) + offset);
3974 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
3976 return simplify_gen_subreg (word_mode, op, mode, byte);
3979 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
3982 mips_split_64bit_move_p (rtx dest, rtx src)
3987 /* FPR-to-FPR moves can be done in a single instruction, if they're
3989 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
3992 /* Check for floating-point loads and stores. */
3993 if (ISA_HAS_LDC1_SDC1)
3995 if (FP_REG_RTX_P (dest) && MEM_P (src))
3997 if (FP_REG_RTX_P (src) && MEM_P (dest))
4003 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4004 this function handles 64-bit moves for which mips_split_64bit_move_p
4005 holds. For 64-bit targets, this function handles 128-bit moves. */
4008 mips_split_doubleword_move (rtx dest, rtx src)
4012 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4014 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4015 emit_insn (gen_move_doubleword_fprdi (dest, src));
4016 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4017 emit_insn (gen_move_doubleword_fprdf (dest, src));
4018 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4019 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4020 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4021 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4022 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4023 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4024 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4025 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4026 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4027 emit_insn (gen_move_doubleword_fprtf (dest, src));
4031 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4033 low_dest = mips_subword (dest, false);
4034 mips_emit_move (low_dest, mips_subword (src, false));
4036 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4038 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4040 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4042 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4044 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4046 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4050 /* The operation can be split into two normal moves. Decide in
4051 which order to do them. */
4052 low_dest = mips_subword (dest, false);
4053 if (REG_P (low_dest)
4054 && reg_overlap_mentioned_p (low_dest, src))
4056 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4057 mips_emit_move (low_dest, mips_subword (src, false));
4061 mips_emit_move (low_dest, mips_subword (src, false));
4062 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4067 /* Return the appropriate instructions to move SRC into DEST. Assume
4068 that SRC is operand 1 and DEST is operand 0. */
4071 mips_output_move (rtx dest, rtx src)
4073 enum rtx_code dest_code, src_code;
4074 enum machine_mode mode;
4075 enum mips_symbol_type symbol_type;
4078 dest_code = GET_CODE (dest);
4079 src_code = GET_CODE (src);
4080 mode = GET_MODE (dest);
4081 dbl_p = (GET_MODE_SIZE (mode) == 8);
4083 if (dbl_p && mips_split_64bit_move_p (dest, src))
4086 if ((src_code == REG && GP_REG_P (REGNO (src)))
4087 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4089 if (dest_code == REG)
4091 if (GP_REG_P (REGNO (dest)))
4092 return "move\t%0,%z1";
4094 /* Moves to HI are handled by special .md insns. */
4095 if (REGNO (dest) == LO_REGNUM)
4098 if (DSP_ACC_REG_P (REGNO (dest)))
4100 static char retval[] = "mt__\t%z1,%q0";
4102 retval[2] = reg_names[REGNO (dest)][4];
4103 retval[3] = reg_names[REGNO (dest)][5];
4107 if (FP_REG_P (REGNO (dest)))
4108 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4110 if (ALL_COP_REG_P (REGNO (dest)))
4112 static char retval[] = "dmtc_\t%z1,%0";
4114 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4115 return dbl_p ? retval : retval + 1;
4118 if (dest_code == MEM)
4119 switch (GET_MODE_SIZE (mode))
4121 case 1: return "sb\t%z1,%0";
4122 case 2: return "sh\t%z1,%0";
4123 case 4: return "sw\t%z1,%0";
4124 case 8: return "sd\t%z1,%0";
4127 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4129 if (src_code == REG)
4131 /* Moves from HI are handled by special .md insns. */
4132 if (REGNO (src) == LO_REGNUM)
4134 /* When generating VR4120 or VR4130 code, we use MACC and
4135 DMACC instead of MFLO. This avoids both the normal
4136 MIPS III HI/LO hazards and the errata related to
4139 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4143 if (DSP_ACC_REG_P (REGNO (src)))
4145 static char retval[] = "mf__\t%0,%q1";
4147 retval[2] = reg_names[REGNO (src)][4];
4148 retval[3] = reg_names[REGNO (src)][5];
4152 if (FP_REG_P (REGNO (src)))
4153 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4155 if (ALL_COP_REG_P (REGNO (src)))
4157 static char retval[] = "dmfc_\t%0,%1";
4159 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4160 return dbl_p ? retval : retval + 1;
4163 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4164 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4167 if (src_code == MEM)
4168 switch (GET_MODE_SIZE (mode))
4170 case 1: return "lbu\t%0,%1";
4171 case 2: return "lhu\t%0,%1";
4172 case 4: return "lw\t%0,%1";
4173 case 8: return "ld\t%0,%1";
4176 if (src_code == CONST_INT)
4178 /* Don't use the X format for the operand itself, because that
4179 will give out-of-range numbers for 64-bit hosts and 32-bit
4182 return "li\t%0,%1\t\t\t# %X1";
4184 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4187 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4191 if (src_code == HIGH)
4192 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4194 if (CONST_GP_P (src))
4195 return "move\t%0,%1";
4197 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4198 && mips_lo_relocs[symbol_type] != 0)
4200 /* A signed 16-bit constant formed by applying a relocation
4201 operator to a symbolic address. */
4202 gcc_assert (!mips_split_p[symbol_type]);
4203 return "li\t%0,%R1";
4206 if (symbolic_operand (src, VOIDmode))
4208 gcc_assert (TARGET_MIPS16
4209 ? TARGET_MIPS16_TEXT_LOADS
4210 : !TARGET_EXPLICIT_RELOCS);
4211 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4214 if (src_code == REG && FP_REG_P (REGNO (src)))
4216 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4218 if (GET_MODE (dest) == V2SFmode)
4219 return "mov.ps\t%0,%1";
4221 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4224 if (dest_code == MEM)
4225 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4227 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4229 if (src_code == MEM)
4230 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4232 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4234 static char retval[] = "l_c_\t%0,%1";
4236 retval[1] = (dbl_p ? 'd' : 'w');
4237 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4240 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4242 static char retval[] = "s_c_\t%1,%0";
4244 retval[1] = (dbl_p ? 'd' : 'w');
4245 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4251 /* Return true if CMP1 is a suitable second operand for integer ordering
4252 test CODE. See also the *sCC patterns in mips.md. */
4255 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4261 return reg_or_0_operand (cmp1, VOIDmode);
4265 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4269 return arith_operand (cmp1, VOIDmode);
4272 return sle_operand (cmp1, VOIDmode);
4275 return sleu_operand (cmp1, VOIDmode);
4282 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4283 integer ordering test *CODE, or if an equivalent combination can
4284 be formed by adjusting *CODE and *CMP1. When returning true, update
4285 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4289 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4290 enum machine_mode mode)
4292 HOST_WIDE_INT plus_one;
4294 if (mips_int_order_operand_ok_p (*code, *cmp1))
4297 if (CONST_INT_P (*cmp1))
4301 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4302 if (INTVAL (*cmp1) < plus_one)
4305 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4311 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4315 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4326 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4327 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4328 is nonnull, it's OK to set TARGET to the inverse of the result and
4329 flip *INVERT_PTR instead. */
4332 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4333 rtx target, rtx cmp0, rtx cmp1)
4335 enum machine_mode mode;
4337 /* First see if there is a MIPS instruction that can do this operation.
4338 If not, try doing the same for the inverse operation. If that also
4339 fails, force CMP1 into a register and try again. */
4340 mode = GET_MODE (cmp0);
4341 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4342 mips_emit_binary (code, target, cmp0, cmp1);
4345 enum rtx_code inv_code = reverse_condition (code);
4346 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4348 cmp1 = force_reg (mode, cmp1);
4349 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4351 else if (invert_ptr == 0)
4355 inv_target = mips_force_binary (GET_MODE (target),
4356 inv_code, cmp0, cmp1);
4357 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4361 *invert_ptr = !*invert_ptr;
4362 mips_emit_binary (inv_code, target, cmp0, cmp1);
4367 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4368 The register will have the same mode as CMP0. */
4371 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4373 if (cmp1 == const0_rtx)
4376 if (uns_arith_operand (cmp1, VOIDmode))
4377 return expand_binop (GET_MODE (cmp0), xor_optab,
4378 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4380 return expand_binop (GET_MODE (cmp0), sub_optab,
4381 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4384 /* Convert *CODE into a code that can be used in a floating-point
4385 scc instruction (C.cond.fmt). Return true if the values of
4386 the condition code registers will be inverted, with 0 indicating
4387 that the condition holds. */
4390 mips_reversed_fp_cond (enum rtx_code *code)
4397 *code = reverse_condition_maybe_unordered (*code);
4405 /* Convert a comparison into something that can be used in a branch or
4406 conditional move. On entry, *OP0 and *OP1 are the values being
4407 compared and *CODE is the code used to compare them.
4409 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4410 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4411 otherwise any standard branch condition can be used. The standard branch
4414 - EQ or NE between two registers.
4415 - any comparison between a register and zero. */
4418 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4423 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4425 if (!need_eq_ne_p && *op1 == const0_rtx)
4427 else if (*code == EQ || *code == NE)
4431 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4435 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4439 /* The comparison needs a separate scc instruction. Store the
4440 result of the scc in *OP0 and compare it against zero. */
4441 bool invert = false;
4442 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4443 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4444 *code = (invert ? EQ : NE);
4448 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4450 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4451 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4457 enum rtx_code cmp_code;
4459 /* Floating-point tests use a separate C.cond.fmt comparison to
4460 set a condition code register. The branch or conditional move
4461 will then compare that register against zero.
4463 Set CMP_CODE to the code of the comparison instruction and
4464 *CODE to the code that the branch or move should use. */
4466 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4468 ? gen_reg_rtx (CCmode)
4469 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4471 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4475 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4476 and OPERAND[3]. Store the result in OPERANDS[0].
4478 On 64-bit targets, the mode of the comparison and target will always be
4479 SImode, thus possibly narrower than that of the comparison's operands. */
4482 mips_expand_scc (rtx operands[])
4484 rtx target = operands[0];
4485 enum rtx_code code = GET_CODE (operands[1]);
4486 rtx op0 = operands[2];
4487 rtx op1 = operands[3];
4489 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4491 if (code == EQ || code == NE)
4494 && reg_imm10_operand (op1, GET_MODE (op1)))
4495 mips_emit_binary (code, target, op0, op1);
4498 rtx zie = mips_zero_if_equal (op0, op1);
4499 mips_emit_binary (code, target, zie, const0_rtx);
4503 mips_emit_int_order_test (code, 0, target, op0, op1);
4506 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4507 CODE and jump to OPERANDS[3] if the condition holds. */
4510 mips_expand_conditional_branch (rtx *operands)
4512 enum rtx_code code = GET_CODE (operands[0]);
4513 rtx op0 = operands[1];
4514 rtx op1 = operands[2];
4517 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4518 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4519 emit_jump_insn (gen_condjump (condition, operands[3]));
4524 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4525 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4528 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4529 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4534 reversed_p = mips_reversed_fp_cond (&cond);
4535 cmp_result = gen_reg_rtx (CCV2mode);
4536 emit_insn (gen_scc_ps (cmp_result,
4537 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4539 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4542 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4546 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4547 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4550 mips_expand_conditional_move (rtx *operands)
4553 enum rtx_code code = GET_CODE (operands[1]);
4554 rtx op0 = XEXP (operands[1], 0);
4555 rtx op1 = XEXP (operands[1], 1);
4557 mips_emit_compare (&code, &op0, &op1, true);
4558 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4559 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4560 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4561 operands[2], operands[3])));
4564 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4567 mips_expand_conditional_trap (rtx comparison)
4570 enum machine_mode mode;
4573 /* MIPS conditional trap instructions don't have GT or LE flavors,
4574 so we must swap the operands and convert to LT and GE respectively. */
4575 code = GET_CODE (comparison);
4582 code = swap_condition (code);
4583 op0 = XEXP (comparison, 1);
4584 op1 = XEXP (comparison, 0);
4588 op0 = XEXP (comparison, 0);
4589 op1 = XEXP (comparison, 1);
4593 mode = GET_MODE (XEXP (comparison, 0));
4594 op0 = force_reg (mode, op0);
4595 if (!arith_operand (op1, mode))
4596 op1 = force_reg (mode, op1);
4598 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4599 gen_rtx_fmt_ee (code, mode, op0, op1),
4603 /* Initialize *CUM for a call to a function of type FNTYPE. */
4606 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4608 memset (cum, 0, sizeof (*cum));
4609 cum->prototype = (fntype && prototype_p (fntype));
4610 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4613 /* Fill INFO with information about a single argument. CUM is the
4614 cumulative state for earlier arguments. MODE is the mode of this
4615 argument and TYPE is its type (if known). NAMED is true if this
4616 is a named (fixed) argument rather than a variable one. */
4619 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4620 enum machine_mode mode, tree type, int named)
4622 bool doubleword_aligned_p;
4623 unsigned int num_bytes, num_words, max_regs;
4625 /* Work out the size of the argument. */
4626 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4627 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4629 /* Decide whether it should go in a floating-point register, assuming
4630 one is free. Later code checks for availability.
4632 The checks against UNITS_PER_FPVALUE handle the soft-float and
4633 single-float cases. */
4637 /* The EABI conventions have traditionally been defined in terms
4638 of TYPE_MODE, regardless of the actual type. */
4639 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4640 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4641 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4646 /* Only leading floating-point scalars are passed in
4647 floating-point registers. We also handle vector floats the same
4648 say, which is OK because they are not covered by the standard ABI. */
4649 info->fpr_p = (!cum->gp_reg_found
4650 && cum->arg_number < 2
4652 || SCALAR_FLOAT_TYPE_P (type)
4653 || VECTOR_FLOAT_TYPE_P (type))
4654 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4655 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4656 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4661 /* Scalar, complex and vector floating-point types are passed in
4662 floating-point registers, as long as this is a named rather
4663 than a variable argument. */
4664 info->fpr_p = (named
4665 && (type == 0 || FLOAT_TYPE_P (type))
4666 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4667 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4668 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4669 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4671 /* ??? According to the ABI documentation, the real and imaginary
4672 parts of complex floats should be passed in individual registers.
4673 The real and imaginary parts of stack arguments are supposed
4674 to be contiguous and there should be an extra word of padding
4677 This has two problems. First, it makes it impossible to use a
4678 single "void *" va_list type, since register and stack arguments
4679 are passed differently. (At the time of writing, MIPSpro cannot
4680 handle complex float varargs correctly.) Second, it's unclear
4681 what should happen when there is only one register free.
4683 For now, we assume that named complex floats should go into FPRs
4684 if there are two FPRs free, otherwise they should be passed in the
4685 same way as a struct containing two floats. */
4687 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4688 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4690 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4691 info->fpr_p = false;
4701 /* See whether the argument has doubleword alignment. */
4702 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4704 /* Set REG_OFFSET to the register count we're interested in.
4705 The EABI allocates the floating-point registers separately,
4706 but the other ABIs allocate them like integer registers. */
4707 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4711 /* Advance to an even register if the argument is doubleword-aligned. */
4712 if (doubleword_aligned_p)
4713 info->reg_offset += info->reg_offset & 1;
4715 /* Work out the offset of a stack argument. */
4716 info->stack_offset = cum->stack_words;
4717 if (doubleword_aligned_p)
4718 info->stack_offset += info->stack_offset & 1;
4720 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4722 /* Partition the argument between registers and stack. */
4723 info->reg_words = MIN (num_words, max_regs);
4724 info->stack_words = num_words - info->reg_words;
4727 /* INFO describes a register argument that has the normal format for the
4728 argument's mode. Return the register it uses, assuming that FPRs are
4729 available if HARD_FLOAT_P. */
4732 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4734 if (!info->fpr_p || !hard_float_p)
4735 return GP_ARG_FIRST + info->reg_offset;
4736 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4737 /* In o32, the second argument is always passed in $f14
4738 for TARGET_DOUBLE_FLOAT, regardless of whether the
4739 first argument was a word or doubleword. */
4740 return FP_ARG_FIRST + 2;
4742 return FP_ARG_FIRST + info->reg_offset;
4745 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4748 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4750 return !TARGET_OLDABI;
4753 /* Implement FUNCTION_ARG. */
4756 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4757 tree type, int named)
4759 struct mips_arg_info info;
4761 /* We will be called with a mode of VOIDmode after the last argument
4762 has been seen. Whatever we return will be passed to the call expander.
4763 If we need a MIPS16 fp_code, return a REG with the code stored as
4765 if (mode == VOIDmode)
4767 if (TARGET_MIPS16 && cum->fp_code != 0)
4768 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4773 mips_get_arg_info (&info, cum, mode, type, named);
4775 /* Return straight away if the whole argument is passed on the stack. */
4776 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4779 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4780 contains a double in its entirety, then that 64-bit chunk is passed
4781 in a floating-point register. */
4783 && TARGET_HARD_FLOAT
4786 && TREE_CODE (type) == RECORD_TYPE
4787 && TYPE_SIZE_UNIT (type)
4788 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4792 /* First check to see if there is any such field. */
4793 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4794 if (TREE_CODE (field) == FIELD_DECL
4795 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4796 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4797 && host_integerp (bit_position (field), 0)
4798 && int_bit_position (field) % BITS_PER_WORD == 0)
4803 /* Now handle the special case by returning a PARALLEL
4804 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4805 chunks are passed in registers. */
4807 HOST_WIDE_INT bitpos;
4810 /* assign_parms checks the mode of ENTRY_PARM, so we must
4811 use the actual mode here. */
4812 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4815 field = TYPE_FIELDS (type);
4816 for (i = 0; i < info.reg_words; i++)
4820 for (; field; field = TREE_CHAIN (field))
4821 if (TREE_CODE (field) == FIELD_DECL
4822 && int_bit_position (field) >= bitpos)
4826 && int_bit_position (field) == bitpos
4827 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4828 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4829 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4831 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4834 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4835 GEN_INT (bitpos / BITS_PER_UNIT));
4837 bitpos += BITS_PER_WORD;
4843 /* Handle the n32/n64 conventions for passing complex floating-point
4844 arguments in FPR pairs. The real part goes in the lower register
4845 and the imaginary part goes in the upper register. */
4848 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4851 enum machine_mode inner;
4854 inner = GET_MODE_INNER (mode);
4855 regno = FP_ARG_FIRST + info.reg_offset;
4856 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4858 /* Real part in registers, imaginary part on stack. */
4859 gcc_assert (info.stack_words == info.reg_words);
4860 return gen_rtx_REG (inner, regno);
4864 gcc_assert (info.stack_words == 0);
4865 real = gen_rtx_EXPR_LIST (VOIDmode,
4866 gen_rtx_REG (inner, regno),
4868 imag = gen_rtx_EXPR_LIST (VOIDmode,
4870 regno + info.reg_words / 2),
4871 GEN_INT (GET_MODE_SIZE (inner)));
4872 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4876 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4879 /* Implement FUNCTION_ARG_ADVANCE. */
4882 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4883 tree type, int named)
4885 struct mips_arg_info info;
4887 mips_get_arg_info (&info, cum, mode, type, named);
4890 cum->gp_reg_found = true;
4892 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4893 an explanation of what this code does. It assumes that we're using
4894 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4896 if (cum->arg_number < 2 && info.fpr_p)
4897 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4899 /* Advance the register count. This has the effect of setting
4900 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4901 argument required us to skip the final GPR and pass the whole
4902 argument on the stack. */
4903 if (mips_abi != ABI_EABI || !info.fpr_p)
4904 cum->num_gprs = info.reg_offset + info.reg_words;
4905 else if (info.reg_words > 0)
4906 cum->num_fprs += MAX_FPRS_PER_FMT;
4908 /* Advance the stack word count. */
4909 if (info.stack_words > 0)
4910 cum->stack_words = info.stack_offset + info.stack_words;
4915 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4918 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4919 enum machine_mode mode, tree type, bool named)
4921 struct mips_arg_info info;
4923 mips_get_arg_info (&info, cum, mode, type, named);
4924 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4927 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4928 PARM_BOUNDARY bits of alignment, but will be given anything up
4929 to STACK_BOUNDARY bits if the type requires it. */
4932 mips_function_arg_boundary (enum machine_mode mode, tree type)
4934 unsigned int alignment;
4936 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
4937 if (alignment < PARM_BOUNDARY)
4938 alignment = PARM_BOUNDARY;
4939 if (alignment > STACK_BOUNDARY)
4940 alignment = STACK_BOUNDARY;
4944 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4945 upward rather than downward. In other words, return true if the
4946 first byte of the stack slot has useful data, false if the last
4950 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
4952 /* On little-endian targets, the first byte of every stack argument
4953 is passed in the first byte of the stack slot. */
4954 if (!BYTES_BIG_ENDIAN)
4957 /* Otherwise, integral types are padded downward: the last byte of a
4958 stack argument is passed in the last byte of the stack slot. */
4960 ? (INTEGRAL_TYPE_P (type)
4961 || POINTER_TYPE_P (type)
4962 || FIXED_POINT_TYPE_P (type))
4963 : (SCALAR_INT_MODE_P (mode)
4964 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
4967 /* Big-endian o64 pads floating-point arguments downward. */
4968 if (mips_abi == ABI_O64)
4969 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4972 /* Other types are padded upward for o32, o64, n32 and n64. */
4973 if (mips_abi != ABI_EABI)
4976 /* Arguments smaller than a stack slot are padded downward. */
4977 if (mode != BLKmode)
4978 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
4980 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
4983 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4984 if the least significant byte of the register has useful data. Return
4985 the opposite if the most significant byte does. */
4988 mips_pad_reg_upward (enum machine_mode mode, tree type)
4990 /* No shifting is required for floating-point arguments. */
4991 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4992 return !BYTES_BIG_ENDIAN;
4994 /* Otherwise, apply the same padding to register arguments as we do
4995 to stack arguments. */
4996 return mips_pad_arg_upward (mode, type);
4999 /* Return nonzero when an argument must be passed by reference. */
5002 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5003 enum machine_mode mode, const_tree type,
5004 bool named ATTRIBUTE_UNUSED)
5006 if (mips_abi == ABI_EABI)
5010 /* ??? How should SCmode be handled? */
5011 if (mode == DImode || mode == DFmode
5012 || mode == DQmode || mode == UDQmode
5013 || mode == DAmode || mode == UDAmode)
5016 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5017 return size == -1 || size > UNITS_PER_WORD;
5021 /* If we have a variable-sized parameter, we have no choice. */
5022 return targetm.calls.must_pass_in_stack (mode, type);
5026 /* Implement TARGET_CALLEE_COPIES. */
5029 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5030 enum machine_mode mode ATTRIBUTE_UNUSED,
5031 const_tree type ATTRIBUTE_UNUSED, bool named)
5033 return mips_abi == ABI_EABI && named;
5036 /* See whether VALTYPE is a record whose fields should be returned in
5037 floating-point registers. If so, return the number of fields and
5038 list them in FIELDS (which should have two elements). Return 0
5041 For n32 & n64, a structure with one or two fields is returned in
5042 floating-point registers as long as every field has a floating-point
5046 mips_fpr_return_fields (const_tree valtype, tree *fields)
5054 if (TREE_CODE (valtype) != RECORD_TYPE)
5058 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
5060 if (TREE_CODE (field) != FIELD_DECL)
5063 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5069 fields[i++] = field;
5074 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5075 a value in the most significant part of $2/$3 if:
5077 - the target is big-endian;
5079 - the value has a structure or union type (we generalize this to
5080 cover aggregates from other languages too); and
5082 - the structure is not returned in floating-point registers. */
5085 mips_return_in_msb (const_tree valtype)
5089 return (TARGET_NEWABI
5090 && TARGET_BIG_ENDIAN
5091 && AGGREGATE_TYPE_P (valtype)
5092 && mips_fpr_return_fields (valtype, fields) == 0);
5095 /* Return true if the function return value MODE will get returned in a
5096 floating-point register. */
5099 mips_return_mode_in_fpr_p (enum machine_mode mode)
5101 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5102 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5103 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5104 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5107 /* Return the representation of an FPR return register when the
5108 value being returned in FP_RETURN has mode VALUE_MODE and the
5109 return type itself has mode TYPE_MODE. On NewABI targets,
5110 the two modes may be different for structures like:
5112 struct __attribute__((packed)) foo { float f; }
5114 where we return the SFmode value of "f" in FP_RETURN, but where
5115 the structure itself has mode BLKmode. */
5118 mips_return_fpr_single (enum machine_mode type_mode,
5119 enum machine_mode value_mode)
5123 x = gen_rtx_REG (value_mode, FP_RETURN);
5124 if (type_mode != value_mode)
5126 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5127 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5132 /* Return a composite value in a pair of floating-point registers.
5133 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5134 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5137 For n32 & n64, $f0 always holds the first value and $f2 the second.
5138 Otherwise the values are packed together as closely as possible. */
5141 mips_return_fpr_pair (enum machine_mode mode,
5142 enum machine_mode mode1, HOST_WIDE_INT offset1,
5143 enum machine_mode mode2, HOST_WIDE_INT offset2)
5147 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5148 return gen_rtx_PARALLEL
5151 gen_rtx_EXPR_LIST (VOIDmode,
5152 gen_rtx_REG (mode1, FP_RETURN),
5154 gen_rtx_EXPR_LIST (VOIDmode,
5155 gen_rtx_REG (mode2, FP_RETURN + inc),
5156 GEN_INT (offset2))));
5160 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5161 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5162 VALTYPE is null and MODE is the mode of the return value. */
5165 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5172 mode = TYPE_MODE (valtype);
5173 unsigned_p = TYPE_UNSIGNED (valtype);
5175 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5176 return values, promote the mode here too. */
5177 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5179 /* Handle structures whose fields are returned in $f0/$f2. */
5180 switch (mips_fpr_return_fields (valtype, fields))
5183 return mips_return_fpr_single (mode,
5184 TYPE_MODE (TREE_TYPE (fields[0])));
5187 return mips_return_fpr_pair (mode,
5188 TYPE_MODE (TREE_TYPE (fields[0])),
5189 int_byte_position (fields[0]),
5190 TYPE_MODE (TREE_TYPE (fields[1])),
5191 int_byte_position (fields[1]));
5194 /* If a value is passed in the most significant part of a register, see
5195 whether we have to round the mode up to a whole number of words. */
5196 if (mips_return_in_msb (valtype))
5198 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5199 if (size % UNITS_PER_WORD != 0)
5201 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5202 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5206 /* For EABI, the class of return register depends entirely on MODE.
5207 For example, "struct { some_type x; }" and "union { some_type x; }"
5208 are returned in the same way as a bare "some_type" would be.
5209 Other ABIs only use FPRs for scalar, complex or vector types. */
5210 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5211 return gen_rtx_REG (mode, GP_RETURN);
5216 /* Handle long doubles for n32 & n64. */
5218 return mips_return_fpr_pair (mode,
5220 DImode, GET_MODE_SIZE (mode) / 2);
5222 if (mips_return_mode_in_fpr_p (mode))
5224 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5225 return mips_return_fpr_pair (mode,
5226 GET_MODE_INNER (mode), 0,
5227 GET_MODE_INNER (mode),
5228 GET_MODE_SIZE (mode) / 2);
5230 return gen_rtx_REG (mode, FP_RETURN);
5234 return gen_rtx_REG (mode, GP_RETURN);
5237 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5238 all BLKmode objects are returned in memory. Under the n32, n64
5239 and embedded ABIs, small structures are returned in a register.
5240 Objects with varying size must still be returned in memory, of
5244 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5246 return (TARGET_OLDABI
5247 ? TYPE_MODE (type) == BLKmode
5248 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5251 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5254 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5255 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5258 CUMULATIVE_ARGS local_cum;
5259 int gp_saved, fp_saved;
5261 /* The caller has advanced CUM up to, but not beyond, the last named
5262 argument. Advance a local copy of CUM past the last "real" named
5263 argument, to find out how many registers are left over. */
5265 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5267 /* Found out how many registers we need to save. */
5268 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5269 fp_saved = (EABI_FLOAT_VARARGS_P
5270 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5279 ptr = plus_constant (virtual_incoming_args_rtx,
5280 REG_PARM_STACK_SPACE (cfun->decl)
5281 - gp_saved * UNITS_PER_WORD);
5282 mem = gen_frame_mem (BLKmode, ptr);
5283 set_mem_alias_set (mem, get_varargs_alias_set ());
5285 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5290 /* We can't use move_block_from_reg, because it will use
5292 enum machine_mode mode;
5295 /* Set OFF to the offset from virtual_incoming_args_rtx of
5296 the first float register. The FP save area lies below
5297 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5298 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5299 off -= fp_saved * UNITS_PER_FPREG;
5301 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5303 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5304 i += MAX_FPRS_PER_FMT)
5308 ptr = plus_constant (virtual_incoming_args_rtx, off);
5309 mem = gen_frame_mem (mode, ptr);
5310 set_mem_alias_set (mem, get_varargs_alias_set ());
5311 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5312 off += UNITS_PER_HWFPVALUE;
5316 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5317 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5318 + fp_saved * UNITS_PER_FPREG);
5321 /* Implement TARGET_BUILTIN_VA_LIST. */
5324 mips_build_builtin_va_list (void)
5326 if (EABI_FLOAT_VARARGS_P)
5328 /* We keep 3 pointers, and two offsets.
5330 Two pointers are to the overflow area, which starts at the CFA.
5331 One of these is constant, for addressing into the GPR save area
5332 below it. The other is advanced up the stack through the
5335 The third pointer is to the bottom of the GPR save area.
5336 Since the FPR save area is just below it, we can address
5337 FPR slots off this pointer.
5339 We also keep two one-byte offsets, which are to be subtracted
5340 from the constant pointers to yield addresses in the GPR and
5341 FPR save areas. These are downcounted as float or non-float
5342 arguments are used, and when they get to zero, the argument
5343 must be obtained from the overflow region. */
5344 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5347 record = lang_hooks.types.make_type (RECORD_TYPE);
5349 f_ovfl = build_decl (BUILTINS_LOCATION,
5350 FIELD_DECL, get_identifier ("__overflow_argptr"),
5352 f_gtop = build_decl (BUILTINS_LOCATION,
5353 FIELD_DECL, get_identifier ("__gpr_top"),
5355 f_ftop = build_decl (BUILTINS_LOCATION,
5356 FIELD_DECL, get_identifier ("__fpr_top"),
5358 f_goff = build_decl (BUILTINS_LOCATION,
5359 FIELD_DECL, get_identifier ("__gpr_offset"),
5360 unsigned_char_type_node);
5361 f_foff = build_decl (BUILTINS_LOCATION,
5362 FIELD_DECL, get_identifier ("__fpr_offset"),
5363 unsigned_char_type_node);
5364 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5365 warn on every user file. */
5366 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5367 array = build_array_type (unsigned_char_type_node,
5368 build_index_type (index));
5369 f_res = build_decl (BUILTINS_LOCATION,
5370 FIELD_DECL, get_identifier ("__reserved"), array);
5372 DECL_FIELD_CONTEXT (f_ovfl) = record;
5373 DECL_FIELD_CONTEXT (f_gtop) = record;
5374 DECL_FIELD_CONTEXT (f_ftop) = record;
5375 DECL_FIELD_CONTEXT (f_goff) = record;
5376 DECL_FIELD_CONTEXT (f_foff) = record;
5377 DECL_FIELD_CONTEXT (f_res) = record;
5379 TYPE_FIELDS (record) = f_ovfl;
5380 TREE_CHAIN (f_ovfl) = f_gtop;
5381 TREE_CHAIN (f_gtop) = f_ftop;
5382 TREE_CHAIN (f_ftop) = f_goff;
5383 TREE_CHAIN (f_goff) = f_foff;
5384 TREE_CHAIN (f_foff) = f_res;
5386 layout_type (record);
5389 else if (TARGET_IRIX && TARGET_IRIX6)
5390 /* On IRIX 6, this type is 'char *'. */
5391 return build_pointer_type (char_type_node);
5393 /* Otherwise, we use 'void *'. */
5394 return ptr_type_node;
5397 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5400 mips_va_start (tree valist, rtx nextarg)
5402 if (EABI_FLOAT_VARARGS_P)
5404 const CUMULATIVE_ARGS *cum;
5405 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5406 tree ovfl, gtop, ftop, goff, foff;
5408 int gpr_save_area_size;
5409 int fpr_save_area_size;
5412 cum = &crtl->args.info;
5414 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5416 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5418 f_ovfl = TYPE_FIELDS (va_list_type_node);
5419 f_gtop = TREE_CHAIN (f_ovfl);
5420 f_ftop = TREE_CHAIN (f_gtop);
5421 f_goff = TREE_CHAIN (f_ftop);
5422 f_foff = TREE_CHAIN (f_goff);
5424 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5426 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5428 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5430 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5432 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5435 /* Emit code to initialize OVFL, which points to the next varargs
5436 stack argument. CUM->STACK_WORDS gives the number of stack
5437 words used by named arguments. */
5438 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5439 if (cum->stack_words > 0)
5440 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5441 size_int (cum->stack_words * UNITS_PER_WORD));
5442 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5443 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5445 /* Emit code to initialize GTOP, the top of the GPR save area. */
5446 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5447 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5448 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5450 /* Emit code to initialize FTOP, the top of the FPR save area.
5451 This address is gpr_save_area_bytes below GTOP, rounded
5452 down to the next fp-aligned boundary. */
5453 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5454 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5455 fpr_offset &= -UNITS_PER_FPVALUE;
5457 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5458 size_int (-fpr_offset));
5459 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5460 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5462 /* Emit code to initialize GOFF, the offset from GTOP of the
5463 next GPR argument. */
5464 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5465 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5466 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5468 /* Likewise emit code to initialize FOFF, the offset from FTOP
5469 of the next FPR argument. */
5470 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5471 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5472 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5476 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5477 std_expand_builtin_va_start (valist, nextarg);
5481 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5484 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5490 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5492 type = build_pointer_type (type);
5494 if (!EABI_FLOAT_VARARGS_P)
5495 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5498 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5499 tree ovfl, top, off, align;
5500 HOST_WIDE_INT size, rsize, osize;
5503 f_ovfl = TYPE_FIELDS (va_list_type_node);
5504 f_gtop = TREE_CHAIN (f_ovfl);
5505 f_ftop = TREE_CHAIN (f_gtop);
5506 f_goff = TREE_CHAIN (f_ftop);
5507 f_foff = TREE_CHAIN (f_goff);
5511 TOP be the top of the GPR or FPR save area;
5512 OFF be the offset from TOP of the next register;
5513 ADDR_RTX be the address of the argument;
5514 SIZE be the number of bytes in the argument type;
5515 RSIZE be the number of bytes used to store the argument
5516 when it's in the register save area; and
5517 OSIZE be the number of bytes used to store it when it's
5518 in the stack overflow area.
5520 The code we want is:
5522 1: off &= -rsize; // round down
5525 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5530 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5531 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5535 [1] and [9] can sometimes be optimized away. */
5537 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5539 size = int_size_in_bytes (type);
5541 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5542 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5544 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5545 unshare_expr (valist), f_ftop, NULL_TREE);
5546 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5547 unshare_expr (valist), f_foff, NULL_TREE);
5549 /* When va_start saves FPR arguments to the stack, each slot
5550 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5551 argument's precision. */
5552 rsize = UNITS_PER_HWFPVALUE;
5554 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5555 (= PARM_BOUNDARY bits). This can be different from RSIZE
5558 (1) On 32-bit targets when TYPE is a structure such as:
5560 struct s { float f; };
5562 Such structures are passed in paired FPRs, so RSIZE
5563 will be 8 bytes. However, the structure only takes
5564 up 4 bytes of memory, so OSIZE will only be 4.
5566 (2) In combinations such as -mgp64 -msingle-float
5567 -fshort-double. Doubles passed in registers will then take
5568 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5569 stack take up UNITS_PER_WORD bytes. */
5570 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5574 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5575 unshare_expr (valist), f_gtop, NULL_TREE);
5576 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5577 unshare_expr (valist), f_goff, NULL_TREE);
5578 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5579 if (rsize > UNITS_PER_WORD)
5581 /* [1] Emit code for: off &= -rsize. */
5582 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5583 build_int_cst (TREE_TYPE (off), -rsize));
5584 gimplify_assign (unshare_expr (off), t, pre_p);
5589 /* [2] Emit code to branch if off == 0. */
5590 t = build2 (NE_EXPR, boolean_type_node, off,
5591 build_int_cst (TREE_TYPE (off), 0));
5592 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5594 /* [5] Emit code for: off -= rsize. We do this as a form of
5595 post-decrement not available to C. */
5596 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5597 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5599 /* [4] Emit code for:
5600 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5601 t = fold_convert (sizetype, t);
5602 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5603 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5604 if (BYTES_BIG_ENDIAN && rsize > size)
5606 u = size_int (rsize - size);
5607 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5609 COND_EXPR_THEN (addr) = t;
5611 if (osize > UNITS_PER_WORD)
5613 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5614 u = size_int (osize - 1);
5615 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5616 unshare_expr (ovfl), u);
5617 t = fold_convert (sizetype, t);
5618 u = size_int (-osize);
5619 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5620 t = fold_convert (TREE_TYPE (ovfl), t);
5621 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5622 unshare_expr (ovfl), t);
5627 /* [10, 11] Emit code for:
5628 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5630 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5631 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5632 if (BYTES_BIG_ENDIAN && osize > size)
5634 u = size_int (osize - size);
5635 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5638 /* String [9] and [10, 11] together. */
5640 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5641 COND_EXPR_ELSE (addr) = t;
5643 addr = fold_convert (build_pointer_type (type), addr);
5644 addr = build_va_arg_indirect_ref (addr);
5648 addr = build_va_arg_indirect_ref (addr);
5653 /* Start a definition of function NAME. MIPS16_P indicates whether the
5654 function contains MIPS16 code. */
5657 mips_start_function_definition (const char *name, bool mips16_p)
5660 fprintf (asm_out_file, "\t.set\tmips16\n");
5662 fprintf (asm_out_file, "\t.set\tnomips16\n");
5664 if (!flag_inhibit_size_directive)
5666 fputs ("\t.ent\t", asm_out_file);
5667 assemble_name (asm_out_file, name);
5668 fputs ("\n", asm_out_file);
5671 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5673 /* Start the definition proper. */
5674 assemble_name (asm_out_file, name);
5675 fputs (":\n", asm_out_file);
5678 /* End a function definition started by mips_start_function_definition. */
5681 mips_end_function_definition (const char *name)
5683 if (!flag_inhibit_size_directive)
5685 fputs ("\t.end\t", asm_out_file);
5686 assemble_name (asm_out_file, name);
5687 fputs ("\n", asm_out_file);
5691 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5694 mips_ok_for_lazy_binding_p (rtx x)
5696 return (TARGET_USE_GOT
5697 && GET_CODE (x) == SYMBOL_REF
5698 && !SYMBOL_REF_BIND_NOW_P (x)
5699 && !mips_symbol_binds_local_p (x));
5702 /* Load function address ADDR into register DEST. TYPE is as for
5703 mips_expand_call. Return true if we used an explicit lazy-binding
5707 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5709 /* If we're generating PIC, and this call is to a global function,
5710 try to allow its address to be resolved lazily. This isn't
5711 possible for sibcalls when $gp is call-saved because the value
5712 of $gp on entry to the stub would be our caller's gp, not ours. */
5713 if (TARGET_EXPLICIT_RELOCS
5714 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5715 && mips_ok_for_lazy_binding_p (addr))
5717 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5718 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5723 mips_emit_move (dest, addr);
5728 /* Each locally-defined hard-float MIPS16 function has a local symbol
5729 associated with it. This hash table maps the function symbol (FUNC)
5730 to the local symbol (LOCAL). */
5731 struct GTY(()) mips16_local_alias {
5735 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5737 /* Hash table callbacks for mips16_local_aliases. */
5740 mips16_local_aliases_hash (const void *entry)
5742 const struct mips16_local_alias *alias;
5744 alias = (const struct mips16_local_alias *) entry;
5745 return htab_hash_string (XSTR (alias->func, 0));
5749 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5751 const struct mips16_local_alias *alias1, *alias2;
5753 alias1 = (const struct mips16_local_alias *) entry1;
5754 alias2 = (const struct mips16_local_alias *) entry2;
5755 return rtx_equal_p (alias1->func, alias2->func);
5758 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5759 Return a local alias for it, creating a new one if necessary. */
5762 mips16_local_alias (rtx func)
5764 struct mips16_local_alias *alias, tmp_alias;
5767 /* Create the hash table if this is the first call. */
5768 if (mips16_local_aliases == NULL)
5769 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5770 mips16_local_aliases_eq, NULL);
5772 /* Look up the function symbol, creating a new entry if need be. */
5773 tmp_alias.func = func;
5774 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5775 gcc_assert (slot != NULL);
5777 alias = (struct mips16_local_alias *) *slot;
5780 const char *func_name, *local_name;
5783 /* Create a new SYMBOL_REF for the local symbol. The choice of
5784 __fn_local_* is based on the __fn_stub_* names that we've
5785 traditionally used for the non-MIPS16 stub. */
5786 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5787 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5788 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5789 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5791 /* Create a new structure to represent the mapping. */
5792 alias = GGC_NEW (struct mips16_local_alias);
5794 alias->local = local;
5797 return alias->local;
5800 /* A chained list of functions for which mips16_build_call_stub has already
5801 generated a stub. NAME is the name of the function and FP_RET_P is true
5802 if the function returns a value in floating-point registers. */
5803 struct mips16_stub {
5804 struct mips16_stub *next;
5808 static struct mips16_stub *mips16_stubs;
5810 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5813 mips16_stub_function (const char *name)
5817 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5818 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5822 /* Return the two-character string that identifies floating-point
5823 return mode MODE in the name of a MIPS16 function stub. */
5826 mips16_call_stub_mode_suffix (enum machine_mode mode)
5830 else if (mode == DFmode)
5832 else if (mode == SCmode)
5834 else if (mode == DCmode)
5836 else if (mode == V2SFmode)
5842 /* Write instructions to move a 32-bit value between general register
5843 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5844 from GPREG to FPREG and 'f' to move in the opposite direction. */
5847 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5849 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5850 reg_names[gpreg], reg_names[fpreg]);
5853 /* Likewise for 64-bit values. */
5856 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5859 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5860 reg_names[gpreg], reg_names[fpreg]);
5861 else if (TARGET_FLOAT64)
5863 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5864 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5865 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5866 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5870 /* Move the least-significant word. */
5871 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5872 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5873 /* ...then the most significant word. */
5874 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5875 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5879 /* Write out code to move floating-point arguments into or out of
5880 general registers. FP_CODE is the code describing which arguments
5881 are present (see the comment above the definition of CUMULATIVE_ARGS
5882 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5885 mips_output_args_xfer (int fp_code, char direction)
5887 unsigned int gparg, fparg, f;
5888 CUMULATIVE_ARGS cum;
5890 /* This code only works for o32 and o64. */
5891 gcc_assert (TARGET_OLDABI);
5893 mips_init_cumulative_args (&cum, NULL);
5895 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5897 enum machine_mode mode;
5898 struct mips_arg_info info;
5902 else if ((f & 3) == 2)
5907 mips_get_arg_info (&info, &cum, mode, NULL, true);
5908 gparg = mips_arg_regno (&info, false);
5909 fparg = mips_arg_regno (&info, true);
5912 mips_output_32bit_xfer (direction, gparg, fparg);
5914 mips_output_64bit_xfer (direction, gparg, fparg);
5916 mips_function_arg_advance (&cum, mode, NULL, true);
5920 /* Write a MIPS16 stub for the current function. This stub is used
5921 for functions which take arguments in the floating-point registers.
5922 It is normal-mode code that moves the floating-point arguments
5923 into the general registers and then jumps to the MIPS16 code. */
5926 mips16_build_function_stub (void)
5928 const char *fnname, *alias_name, *separator;
5929 char *secname, *stubname;
5934 /* Create the name of the stub, and its unique section. */
5935 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5936 alias = mips16_local_alias (symbol);
5938 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
5939 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
5940 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
5941 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
5943 /* Build a decl for the stub. */
5944 stubdecl = build_decl (BUILTINS_LOCATION,
5945 FUNCTION_DECL, get_identifier (stubname),
5946 build_function_type (void_type_node, NULL_TREE));
5947 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
5948 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
5949 RESULT_DECL, NULL_TREE, void_type_node);
5951 /* Output a comment. */
5952 fprintf (asm_out_file, "\t# Stub function for %s (",
5953 current_function_name ());
5955 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
5957 fprintf (asm_out_file, "%s%s", separator,
5958 (f & 3) == 1 ? "float" : "double");
5961 fprintf (asm_out_file, ")\n");
5963 /* Start the function definition. */
5964 assemble_start_function (stubdecl, stubname);
5965 mips_start_function_definition (stubname, false);
5967 /* If generating pic2 code, either set up the global pointer or
5969 if (TARGET_ABICALLS_PIC2)
5971 if (TARGET_ABSOLUTE_ABICALLS)
5972 fprintf (asm_out_file, "\t.option\tpic0\n");
5975 output_asm_insn ("%(.cpload\t%^%)", NULL);
5976 /* Emit an R_MIPS_NONE relocation to tell the linker what the
5977 target function is. Use a local GOT access when loading the
5978 symbol, to cut down on the number of unnecessary GOT entries
5979 for stubs that aren't needed. */
5980 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
5985 /* Load the address of the MIPS16 function into $25. Do this first so
5986 that targets with coprocessor interlocks can use an MFC1 to fill the
5988 output_asm_insn ("la\t%^,%0", &symbol);
5990 /* Move the arguments from floating-point registers to general registers. */
5991 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
5993 /* Jump to the MIPS16 function. */
5994 output_asm_insn ("jr\t%^", NULL);
5996 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
5997 fprintf (asm_out_file, "\t.option\tpic2\n");
5999 mips_end_function_definition (stubname);
6001 /* If the linker needs to create a dynamic symbol for the target
6002 function, it will associate the symbol with the stub (which,
6003 unlike the target function, follows the proper calling conventions).
6004 It is therefore useful to have a local alias for the target function,
6005 so that it can still be identified as MIPS16 code. As an optimization,
6006 this symbol can also be used for indirect MIPS16 references from
6007 within this file. */
6008 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6010 switch_to_section (function_section (current_function_decl));
6013 /* The current function is a MIPS16 function that returns a value in an FPR.
6014 Copy the return value from its soft-float to its hard-float location.
6015 libgcc2 has special non-MIPS16 helper functions for each case. */
6018 mips16_copy_fpr_return_value (void)
6020 rtx fn, insn, retval;
6022 enum machine_mode return_mode;
6025 return_type = DECL_RESULT (current_function_decl);
6026 return_mode = DECL_MODE (return_type);
6028 name = ACONCAT (("__mips16_ret_",
6029 mips16_call_stub_mode_suffix (return_mode),
6031 fn = mips16_stub_function (name);
6033 /* The function takes arguments in $2 (and possibly $3), so calls
6034 to it cannot be lazily bound. */
6035 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6037 /* Model the call as something that takes the GPR return value as
6038 argument and returns an "updated" value. */
6039 retval = gen_rtx_REG (return_mode, GP_RETURN);
6040 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6041 const0_rtx, NULL_RTX, false);
6042 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6045 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6046 RETVAL is the location of the return value, or null if this is
6047 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6048 arguments and FP_CODE is the code built by mips_function_arg;
6049 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6051 There are three alternatives:
6053 - If a stub was needed, emit the call and return the call insn itself.
6055 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6056 to the new target and return null.
6058 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6061 A stub is needed for calls to functions that, in normal mode,
6062 receive arguments in FPRs or return values in FPRs. The stub
6063 copies the arguments from their soft-float positions to their
6064 hard-float positions, calls the real function, then copies the
6065 return value from its hard-float position to its soft-float
6068 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6069 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6070 automatically redirects the JAL to the stub, otherwise the JAL
6071 continues to call FN directly. */
6074 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6078 struct mips16_stub *l;
6081 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6082 we were invoked with the -msoft-float option. */
6083 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6086 /* Figure out whether the value might come back in a floating-point
6088 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6090 /* We don't need to do anything if there were no floating-point
6091 arguments and the value will not be returned in a floating-point
6093 if (fp_code == 0 && !fp_ret_p)
6096 /* We don't need to do anything if this is a call to a special
6097 MIPS16 support function. */
6099 if (mips16_stub_function_p (fn))
6102 /* This code will only work for o32 and o64 abis. The other ABI's
6103 require more sophisticated support. */
6104 gcc_assert (TARGET_OLDABI);
6106 /* If we're calling via a function pointer, use one of the magic
6107 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6108 Each stub expects the function address to arrive in register $2. */
6109 if (GET_CODE (fn) != SYMBOL_REF
6110 || !call_insn_operand (fn, VOIDmode))
6113 rtx stub_fn, insn, addr;
6116 /* If this is a locally-defined and locally-binding function,
6117 avoid the stub by calling the local alias directly. */
6118 if (mips16_local_function_p (fn))
6120 *fn_ptr = mips16_local_alias (fn);
6124 /* Create a SYMBOL_REF for the libgcc.a function. */
6126 sprintf (buf, "__mips16_call_stub_%s_%d",
6127 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6130 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6131 stub_fn = mips16_stub_function (buf);
6133 /* The function uses $2 as an argument, so calls to it
6134 cannot be lazily bound. */
6135 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6137 /* Load the target function into $2. */
6138 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6139 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6141 /* Emit the call. */
6142 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6143 args_size, NULL_RTX, lazy_p);
6145 /* Tell GCC that this call does indeed use the value of $2. */
6146 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6148 /* If we are handling a floating-point return value, we need to
6149 save $18 in the function prologue. Putting a note on the
6150 call will mean that df_regs_ever_live_p ($18) will be true if the
6151 call is not eliminated, and we can check that in the prologue
6154 CALL_INSN_FUNCTION_USAGE (insn) =
6155 gen_rtx_EXPR_LIST (VOIDmode,
6156 gen_rtx_CLOBBER (VOIDmode,
6157 gen_rtx_REG (word_mode, 18)),
6158 CALL_INSN_FUNCTION_USAGE (insn));
6163 /* We know the function we are going to call. If we have already
6164 built a stub, we don't need to do anything further. */
6165 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6166 for (l = mips16_stubs; l != NULL; l = l->next)
6167 if (strcmp (l->name, fnname) == 0)
6172 const char *separator;
6173 char *secname, *stubname;
6174 tree stubid, stubdecl;
6177 /* If the function does not return in FPRs, the special stub
6181 If the function does return in FPRs, the stub section is named
6182 .mips16.call.fp.FNNAME
6184 Build a decl for the stub. */
6185 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6187 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6189 stubid = get_identifier (stubname);
6190 stubdecl = build_decl (BUILTINS_LOCATION,
6191 FUNCTION_DECL, stubid,
6192 build_function_type (void_type_node, NULL_TREE));
6193 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6194 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6195 RESULT_DECL, NULL_TREE,
6198 /* Output a comment. */
6199 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6201 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6205 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6207 fprintf (asm_out_file, "%s%s", separator,
6208 (f & 3) == 1 ? "float" : "double");
6211 fprintf (asm_out_file, ")\n");
6213 /* Start the function definition. */
6214 assemble_start_function (stubdecl, stubname);
6215 mips_start_function_definition (stubname, false);
6219 /* Load the address of the MIPS16 function into $25. Do this
6220 first so that targets with coprocessor interlocks can use
6221 an MFC1 to fill the delay slot. */
6222 if (TARGET_EXPLICIT_RELOCS)
6224 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6225 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6228 output_asm_insn ("la\t%^,%0", &fn);
6231 /* Move the arguments from general registers to floating-point
6233 mips_output_args_xfer (fp_code, 't');
6237 /* Jump to the previously-loaded address. */
6238 output_asm_insn ("jr\t%^", NULL);
6242 /* Save the return address in $18 and call the non-MIPS16 function.
6243 The stub's caller knows that $18 might be clobbered, even though
6244 $18 is usually a call-saved register. */
6245 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6246 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6247 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6249 /* Move the result from floating-point registers to
6250 general registers. */
6251 switch (GET_MODE (retval))
6254 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6255 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6258 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6259 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6261 /* On 64-bit targets, complex floats are returned in
6262 a single GPR, such that "sd" on a suitably-aligned
6263 target would store the value correctly. */
6264 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6265 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6266 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6267 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6268 reg_names[GP_RETURN],
6269 reg_names[GP_RETURN],
6270 reg_names[GP_RETURN + 1]);
6275 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6276 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6280 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6286 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6289 #ifdef ASM_DECLARE_FUNCTION_SIZE
6290 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6293 mips_end_function_definition (stubname);
6295 /* Record this stub. */
6296 l = XNEW (struct mips16_stub);
6297 l->name = xstrdup (fnname);
6298 l->fp_ret_p = fp_ret_p;
6299 l->next = mips16_stubs;
6303 /* If we expect a floating-point return value, but we've built a
6304 stub which does not expect one, then we're in trouble. We can't
6305 use the existing stub, because it won't handle the floating-point
6306 value. We can't build a new stub, because the linker won't know
6307 which stub to use for the various calls in this object file.
6308 Fortunately, this case is illegal, since it means that a function
6309 was declared in two different ways in a single compilation. */
6310 if (fp_ret_p && !l->fp_ret_p)
6311 error ("cannot handle inconsistent calls to %qs", fnname);
6313 if (retval == NULL_RTX)
6314 insn = gen_call_internal_direct (fn, args_size);
6316 insn = gen_call_value_internal_direct (retval, fn, args_size);
6317 insn = mips_emit_call_insn (insn, fn, fn, false);
6319 /* If we are calling a stub which handles a floating-point return
6320 value, we need to arrange to save $18 in the prologue. We do this
6321 by marking the function call as using the register. The prologue
6322 will later see that it is used, and emit code to save it. */
6324 CALL_INSN_FUNCTION_USAGE (insn) =
6325 gen_rtx_EXPR_LIST (VOIDmode,
6326 gen_rtx_CLOBBER (VOIDmode,
6327 gen_rtx_REG (word_mode, 18)),
6328 CALL_INSN_FUNCTION_USAGE (insn));
6333 /* Expand a call of type TYPE. RESULT is where the result will go (null
6334 for "call"s and "sibcall"s), ADDR is the address of the function,
6335 ARGS_SIZE is the size of the arguments and AUX is the value passed
6336 to us by mips_function_arg. LAZY_P is true if this call already
6337 involves a lazily-bound function address (such as when calling
6338 functions through a MIPS16 hard-float stub).
6340 Return the call itself. */
6343 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6344 rtx args_size, rtx aux, bool lazy_p)
6346 rtx orig_addr, pattern, insn;
6349 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6350 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6353 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6358 if (!call_insn_operand (addr, VOIDmode))
6360 if (type == MIPS_CALL_EPILOGUE)
6361 addr = MIPS_EPILOGUE_TEMP (Pmode);
6363 addr = gen_reg_rtx (Pmode);
6364 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6369 rtx (*fn) (rtx, rtx);
6371 if (type == MIPS_CALL_SIBCALL)
6372 fn = gen_sibcall_internal;
6374 fn = gen_call_internal;
6376 pattern = fn (addr, args_size);
6378 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6380 /* Handle return values created by mips_return_fpr_pair. */
6381 rtx (*fn) (rtx, rtx, rtx, rtx);
6384 if (type == MIPS_CALL_SIBCALL)
6385 fn = gen_sibcall_value_multiple_internal;
6387 fn = gen_call_value_multiple_internal;
6389 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6390 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6391 pattern = fn (reg1, addr, args_size, reg2);
6395 rtx (*fn) (rtx, rtx, rtx);
6397 if (type == MIPS_CALL_SIBCALL)
6398 fn = gen_sibcall_value_internal;
6400 fn = gen_call_value_internal;
6402 /* Handle return values created by mips_return_fpr_single. */
6403 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6404 result = XEXP (XVECEXP (result, 0, 0), 0);
6405 pattern = fn (result, addr, args_size);
6408 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6411 /* Split call instruction INSN into a $gp-clobbering call and
6412 (where necessary) an instruction to restore $gp from its save slot.
6413 CALL_PATTERN is the pattern of the new call. */
6416 mips_split_call (rtx insn, rtx call_pattern)
6420 new_insn = emit_call_insn (call_pattern);
6421 CALL_INSN_FUNCTION_USAGE (new_insn)
6422 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6423 if (!find_reg_note (insn, REG_NORETURN, 0))
6424 /* Pick a temporary register that is suitable for both MIPS16 and
6425 non-MIPS16 code. $4 and $5 are used for returning complex double
6426 values in soft-float code, so $6 is the first suitable candidate. */
6427 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6430 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6433 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6435 if (!TARGET_SIBCALLS)
6438 /* Interrupt handlers need special epilogue code and therefore can't
6440 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6443 /* We can't do a sibcall if the called function is a MIPS16 function
6444 because there is no direct "jx" instruction equivalent to "jalx" to
6445 switch the ISA mode. We only care about cases where the sibling
6446 and normal calls would both be direct. */
6448 && mips_use_mips16_mode_p (decl)
6449 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6452 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6453 functions could be MIPS16 ones unless an attribute explicitly tells
6455 if (TARGET_INTERLINK_MIPS16
6457 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6458 && !mips_nomips16_decl_p (decl)
6459 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6466 /* Emit code to move general operand SRC into condition-code
6467 register DEST given that SCRATCH is a scratch TFmode FPR.
6474 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6477 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6481 /* Change the source to SFmode. */
6483 src = adjust_address (src, SFmode, 0);
6484 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6485 src = gen_rtx_REG (SFmode, true_regnum (src));
6487 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6488 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6490 mips_emit_move (copy_rtx (fp1), src);
6491 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6492 emit_insn (gen_slt_sf (dest, fp2, fp1));
6495 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6496 Assume that the areas do not overlap. */
6499 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6501 HOST_WIDE_INT offset, delta;
6502 unsigned HOST_WIDE_INT bits;
6504 enum machine_mode mode;
6507 /* Work out how many bits to move at a time. If both operands have
6508 half-word alignment, it is usually better to move in half words.
6509 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6510 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6511 Otherwise move word-sized chunks. */
6512 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6513 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6514 bits = BITS_PER_WORD / 2;
6516 bits = BITS_PER_WORD;
6518 mode = mode_for_size (bits, MODE_INT, 0);
6519 delta = bits / BITS_PER_UNIT;
6521 /* Allocate a buffer for the temporary registers. */
6522 regs = XALLOCAVEC (rtx, length / delta);
6524 /* Load as many BITS-sized chunks as possible. Use a normal load if
6525 the source has enough alignment, otherwise use left/right pairs. */
6526 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6528 regs[i] = gen_reg_rtx (mode);
6529 if (MEM_ALIGN (src) >= bits)
6530 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6533 rtx part = adjust_address (src, BLKmode, offset);
6534 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6539 /* Copy the chunks to the destination. */
6540 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6541 if (MEM_ALIGN (dest) >= bits)
6542 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6545 rtx part = adjust_address (dest, BLKmode, offset);
6546 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6550 /* Mop up any left-over bytes. */
6551 if (offset < length)
6553 src = adjust_address (src, BLKmode, offset);
6554 dest = adjust_address (dest, BLKmode, offset);
6555 move_by_pieces (dest, src, length - offset,
6556 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6560 /* Helper function for doing a loop-based block operation on memory
6561 reference MEM. Each iteration of the loop will operate on LENGTH
6564 Create a new base register for use within the loop and point it to
6565 the start of MEM. Create a new memory reference that uses this
6566 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6569 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6570 rtx *loop_reg, rtx *loop_mem)
6572 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6574 /* Although the new mem does not refer to a known location,
6575 it does keep up to LENGTH bytes of alignment. */
6576 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6577 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6580 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6581 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6582 the memory regions do not overlap. */
6585 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6586 HOST_WIDE_INT bytes_per_iter)
6588 rtx label, src_reg, dest_reg, final_src, test;
6589 HOST_WIDE_INT leftover;
6591 leftover = length % bytes_per_iter;
6594 /* Create registers and memory references for use within the loop. */
6595 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6596 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6598 /* Calculate the value that SRC_REG should have after the last iteration
6600 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6603 /* Emit the start of the loop. */
6604 label = gen_label_rtx ();
6607 /* Emit the loop body. */
6608 mips_block_move_straight (dest, src, bytes_per_iter);
6610 /* Move on to the next block. */
6611 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6612 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6614 /* Emit the loop condition. */
6615 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6616 if (Pmode == DImode)
6617 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6619 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6621 /* Mop up any left-over bytes. */
6623 mips_block_move_straight (dest, src, leftover);
6626 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6627 memory reference SRC to memory reference DEST. */
6630 mips_expand_block_move (rtx dest, rtx src, rtx length)
6632 if (CONST_INT_P (length))
6634 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6636 mips_block_move_straight (dest, src, INTVAL (length));
6641 mips_block_move_loop (dest, src, INTVAL (length),
6642 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6649 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6652 mips_expand_synci_loop (rtx begin, rtx end)
6654 rtx inc, label, cmp, cmp_result;
6656 /* Load INC with the cache line size (rdhwr INC,$1). */
6657 inc = gen_reg_rtx (Pmode);
6658 emit_insn (Pmode == SImode
6659 ? gen_rdhwr_synci_step_si (inc)
6660 : gen_rdhwr_synci_step_di (inc));
6662 /* Loop back to here. */
6663 label = gen_label_rtx ();
6666 emit_insn (gen_synci (begin));
6668 cmp = mips_force_binary (Pmode, GTU, begin, end);
6670 mips_emit_binary (PLUS, begin, begin, inc);
6672 cmp_result = gen_rtx_EQ (VOIDmode, cmp, const0_rtx);
6673 emit_jump_insn (gen_condjump (cmp_result, label));
6676 /* Expand a QI or HI mode atomic memory operation.
6678 GENERATOR contains a pointer to the gen_* function that generates
6679 the SI mode underlying atomic operation using masks that we
6682 RESULT is the return register for the operation. Its value is NULL
6685 MEM is the location of the atomic access.
6687 OLDVAL is the first operand for the operation.
6689 NEWVAL is the optional second operand for the operation. Its value
6690 is NULL if unused. */
6693 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6694 rtx result, rtx mem, rtx oldval, rtx newval)
6696 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6697 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6699 enum machine_mode mode;
6701 mode = GET_MODE (mem);
6703 /* Compute the address of the containing SImode value. */
6704 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6705 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6706 force_reg (Pmode, GEN_INT (-4)));
6708 /* Create a memory reference for it. */
6709 memsi = gen_rtx_MEM (SImode, memsi_addr);
6710 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6711 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6713 /* Work out the byte offset of the QImode or HImode value,
6714 counting from the least significant byte. */
6715 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6716 if (TARGET_BIG_ENDIAN)
6717 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6719 /* Multiply by eight to convert the shift value from bytes to bits. */
6720 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6722 /* Make the final shift an SImode value, so that it can be used in
6723 SImode operations. */
6724 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6726 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6727 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6728 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6729 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6731 /* Compute the equivalent exclusive mask. */
6732 inverted_mask = gen_reg_rtx (SImode);
6733 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6734 gen_rtx_NOT (SImode, mask)));
6736 /* Shift the old value into place. */
6737 if (oldval != const0_rtx)
6739 oldval = convert_modes (SImode, mode, oldval, true);
6740 oldval = force_reg (SImode, oldval);
6741 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6744 /* Do the same for the new value. */
6745 if (newval && newval != const0_rtx)
6747 newval = convert_modes (SImode, mode, newval, true);
6748 newval = force_reg (SImode, newval);
6749 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6752 /* Do the SImode atomic access. */
6754 res = gen_reg_rtx (SImode);
6756 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6758 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6760 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6766 /* Shift and convert the result. */
6767 mips_emit_binary (AND, res, res, mask);
6768 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6769 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6773 /* Return true if it is possible to use left/right accesses for a
6774 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6775 returning true, update *OP, *LEFT and *RIGHT as follows:
6777 *OP is a BLKmode reference to the whole field.
6779 *LEFT is a QImode reference to the first byte if big endian or
6780 the last byte if little endian. This address can be used in the
6781 left-side instructions (LWL, SWL, LDL, SDL).
6783 *RIGHT is a QImode reference to the opposite end of the field and
6784 can be used in the patterning right-side instruction. */
6787 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6788 rtx *left, rtx *right)
6792 /* Check that the operand really is a MEM. Not all the extv and
6793 extzv predicates are checked. */
6797 /* Check that the size is valid. */
6798 if (width != 32 && (!TARGET_64BIT || width != 64))
6801 /* We can only access byte-aligned values. Since we are always passed
6802 a reference to the first byte of the field, it is not necessary to
6803 do anything with BITPOS after this check. */
6804 if (bitpos % BITS_PER_UNIT != 0)
6807 /* Reject aligned bitfields: we want to use a normal load or store
6808 instead of a left/right pair. */
6809 if (MEM_ALIGN (*op) >= width)
6812 /* Adjust *OP to refer to the whole field. This also has the effect
6813 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6814 *op = adjust_address (*op, BLKmode, 0);
6815 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6817 /* Get references to both ends of the field. We deliberately don't
6818 use the original QImode *OP for FIRST since the new BLKmode one
6819 might have a simpler address. */
6820 first = adjust_address (*op, QImode, 0);
6821 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6823 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6824 correspond to the MSB and RIGHT to the LSB. */
6825 if (TARGET_BIG_ENDIAN)
6826 *left = first, *right = last;
6828 *left = last, *right = first;
6833 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6834 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6835 the operation is the equivalent of:
6837 (set DEST (*_extract SRC WIDTH BITPOS))
6839 Return true on success. */
6842 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6843 HOST_WIDE_INT bitpos)
6845 rtx left, right, temp;
6847 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6848 be a paradoxical word_mode subreg. This is the only case in which
6849 we allow the destination to be larger than the source. */
6850 if (GET_CODE (dest) == SUBREG
6851 && GET_MODE (dest) == DImode
6852 && GET_MODE (SUBREG_REG (dest)) == SImode)
6853 dest = SUBREG_REG (dest);
6855 /* After the above adjustment, the destination must be the same
6856 width as the source. */
6857 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6860 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6863 temp = gen_reg_rtx (GET_MODE (dest));
6864 if (GET_MODE (dest) == DImode)
6866 emit_insn (gen_mov_ldl (temp, src, left));
6867 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6871 emit_insn (gen_mov_lwl (temp, src, left));
6872 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6877 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6878 BITPOS and SRC are the operands passed to the expander; the operation
6879 is the equivalent of:
6881 (set (zero_extract DEST WIDTH BITPOS) SRC)
6883 Return true on success. */
6886 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6887 HOST_WIDE_INT bitpos)
6890 enum machine_mode mode;
6892 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6895 mode = mode_for_size (width, MODE_INT, 0);
6896 src = gen_lowpart (mode, src);
6899 emit_insn (gen_mov_sdl (dest, src, left));
6900 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6904 emit_insn (gen_mov_swl (dest, src, left));
6905 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6910 /* Return true if X is a MEM with the same size as MODE. */
6913 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
6920 size = MEM_SIZE (x);
6921 return size && INTVAL (size) == GET_MODE_SIZE (mode);
6924 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
6925 source of an "ext" instruction or the destination of an "ins"
6926 instruction. OP must be a register operand and the following
6927 conditions must hold:
6929 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
6930 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6931 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
6933 Also reject lengths equal to a word as they are better handled
6934 by the move patterns. */
6937 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
6939 if (!ISA_HAS_EXT_INS
6940 || !register_operand (op, VOIDmode)
6941 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
6944 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
6947 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
6953 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
6954 operation if MAXLEN is the maxium length of consecutive bits that
6955 can make up MASK. MODE is the mode of the operation. See
6956 mask_low_and_shift_len for the actual definition. */
6959 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
6961 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
6964 /* Return true iff OP1 and OP2 are valid operands together for the
6965 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
6966 see the table in the comment before the pattern. */
6969 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
6971 return (memory_operand (op1, mode)
6972 ? and_load_operand (op2, mode)
6973 : and_reg_operand (op2, mode));
6976 /* The canonical form of a mask-low-and-shift-left operation is
6977 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
6978 cleared. Thus we need to shift MASK to the right before checking if it
6979 is a valid mask value. MODE is the mode of the operation. If true
6980 return the length of the mask, otherwise return -1. */
6983 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
6985 HOST_WIDE_INT shval;
6987 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
6988 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
6991 /* Return true if -msplit-addresses is selected and should be honored.
6993 -msplit-addresses is a half-way house between explicit relocations
6994 and the traditional assembler macros. It can split absolute 32-bit
6995 symbolic constants into a high/lo_sum pair but uses macros for other
6998 Like explicit relocation support for REL targets, it relies
6999 on GNU extensions in the assembler and the linker.
7001 Although this code should work for -O0, it has traditionally
7002 been treated as an optimization. */
7005 mips_split_addresses_p (void)
7007 return (TARGET_SPLIT_ADDRESSES
7011 && !ABI_HAS_64BIT_SYMBOLS);
7014 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7017 mips_init_relocs (void)
7019 memset (mips_split_p, '\0', sizeof (mips_split_p));
7020 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7021 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7022 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7024 if (ABI_HAS_64BIT_SYMBOLS)
7026 if (TARGET_EXPLICIT_RELOCS)
7028 mips_split_p[SYMBOL_64_HIGH] = true;
7029 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7030 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7032 mips_split_p[SYMBOL_64_MID] = true;
7033 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7034 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7036 mips_split_p[SYMBOL_64_LOW] = true;
7037 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7038 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7040 mips_split_p[SYMBOL_ABSOLUTE] = true;
7041 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7046 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7048 mips_split_p[SYMBOL_ABSOLUTE] = true;
7049 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7050 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7052 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7058 /* The high part is provided by a pseudo copy of $gp. */
7059 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7060 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7062 else if (TARGET_EXPLICIT_RELOCS)
7063 /* Small data constants are kept whole until after reload,
7064 then lowered by mips_rewrite_small_data. */
7065 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7067 if (TARGET_EXPLICIT_RELOCS)
7069 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7072 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7073 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7077 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7078 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7081 /* Expose the use of $28 as soon as possible. */
7082 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7086 /* The HIGH and LO_SUM are matched by special .md patterns. */
7087 mips_split_p[SYMBOL_GOT_DISP] = true;
7089 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7090 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7091 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7093 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7094 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7095 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7100 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7102 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7103 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7105 /* Expose the use of $28 as soon as possible. */
7106 mips_split_p[SYMBOL_GOT_DISP] = true;
7112 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7113 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7114 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7117 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7118 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7120 mips_split_p[SYMBOL_DTPREL] = true;
7121 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7122 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7124 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7126 mips_split_p[SYMBOL_TPREL] = true;
7127 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7128 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7130 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7133 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7134 in context CONTEXT. RELOCS is the array of relocations to use. */
7137 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7138 const char **relocs)
7140 enum mips_symbol_type symbol_type;
7143 symbol_type = mips_classify_symbolic_expression (op, context);
7144 gcc_assert (relocs[symbol_type]);
7146 fputs (relocs[symbol_type], file);
7147 output_addr_const (file, mips_strip_unspec_address (op));
7148 for (p = relocs[symbol_type]; *p != 0; p++)
7153 /* Start a new block with the given asm switch enabled. If we need
7154 to print a directive, emit PREFIX before it and SUFFIX after it. */
7157 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7158 const char *prefix, const char *suffix)
7160 if (asm_switch->nesting_level == 0)
7161 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7162 asm_switch->nesting_level++;
7165 /* Likewise, but end a block. */
7168 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7169 const char *prefix, const char *suffix)
7171 gcc_assert (asm_switch->nesting_level);
7172 asm_switch->nesting_level--;
7173 if (asm_switch->nesting_level == 0)
7174 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7177 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7178 that either print a complete line or print nothing. */
7181 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7183 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7187 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7189 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7192 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7193 The punctuation characters are:
7195 '(' Start a nested ".set noreorder" block.
7196 ')' End a nested ".set noreorder" block.
7197 '[' Start a nested ".set noat" block.
7198 ']' End a nested ".set noat" block.
7199 '<' Start a nested ".set nomacro" block.
7200 '>' End a nested ".set nomacro" block.
7201 '*' Behave like %(%< if generating a delayed-branch sequence.
7202 '#' Print a nop if in a ".set noreorder" block.
7203 '/' Like '#', but do nothing within a delayed-branch sequence.
7204 '?' Print "l" if mips_branch_likely is true
7205 '~' Print a nop if mips_branch_likely is true
7206 '.' Print the name of the register with a hard-wired zero (zero or $0).
7207 '@' Print the name of the assembler temporary register (at or $1).
7208 '^' Print the name of the pic call-through register (t9 or $25).
7209 '+' Print the name of the gp register (usually gp or $28).
7210 '$' Print the name of the stack pointer register (sp or $29).
7212 See also mips_init_print_operand_pucnt. */
7215 mips_print_operand_punctuation (FILE *file, int ch)
7220 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7224 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7228 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7232 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7236 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7240 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7244 if (final_sequence != 0)
7246 mips_print_operand_punctuation (file, '(');
7247 mips_print_operand_punctuation (file, '<');
7252 if (mips_noreorder.nesting_level > 0)
7253 fputs ("\n\tnop", file);
7257 /* Print an extra newline so that the delayed insn is separated
7258 from the following ones. This looks neater and is consistent
7259 with non-nop delayed sequences. */
7260 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7261 fputs ("\n\tnop\n", file);
7265 if (mips_branch_likely)
7270 if (mips_branch_likely)
7271 fputs ("\n\tnop", file);
7275 fputs (reg_names[GP_REG_FIRST + 0], file);
7279 fputs (reg_names[AT_REGNUM], file);
7283 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7287 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7291 fputs (reg_names[STACK_POINTER_REGNUM], file);
7300 /* Initialize mips_print_operand_punct. */
7303 mips_init_print_operand_punct (void)
7307 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7308 mips_print_operand_punct[(unsigned char) *p] = true;
7311 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7312 associated with condition CODE. Print the condition part of the
7316 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7330 /* Conveniently, the MIPS names for these conditions are the same
7331 as their RTL equivalents. */
7332 fputs (GET_RTX_NAME (code), file);
7336 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7341 /* Likewise floating-point branches. */
7344 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7349 fputs ("c1f", file);
7353 fputs ("c1t", file);
7357 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7362 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7364 'X' Print CONST_INT OP in hexadecimal format.
7365 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7366 'd' Print CONST_INT OP in decimal.
7367 'm' Print one less than CONST_INT OP in decimal.
7368 'h' Print the high-part relocation associated with OP, after stripping
7370 'R' Print the low-part relocation associated with OP.
7371 'C' Print the integer branch condition for comparison OP.
7372 'N' Print the inverse of the integer branch condition for comparison OP.
7373 'F' Print the FPU branch condition for comparison OP.
7374 'W' Print the inverse of the FPU branch condition for comparison OP.
7375 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7376 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7377 't' Like 'T', but with the EQ/NE cases reversed
7378 'Y' Print mips_fp_conditions[INTVAL (OP)]
7379 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7380 'q' Print a DSP accumulator register.
7381 'D' Print the second part of a double-word register or memory operand.
7382 'L' Print the low-order register in a double-word register operand.
7383 'M' Print high-order register in a double-word register operand.
7384 'z' Print $0 if OP is zero, otherwise print OP normally. */
7387 mips_print_operand (FILE *file, rtx op, int letter)
7391 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7393 mips_print_operand_punctuation (file, letter);
7398 code = GET_CODE (op);
7403 if (CONST_INT_P (op))
7404 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7406 output_operand_lossage ("invalid use of '%%%c'", letter);
7410 if (CONST_INT_P (op))
7411 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7413 output_operand_lossage ("invalid use of '%%%c'", letter);
7417 if (CONST_INT_P (op))
7418 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7420 output_operand_lossage ("invalid use of '%%%c'", letter);
7424 if (CONST_INT_P (op))
7425 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7427 output_operand_lossage ("invalid use of '%%%c'", letter);
7433 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7437 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7441 mips_print_int_branch_condition (file, code, letter);
7445 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7449 mips_print_float_branch_condition (file, code, letter);
7453 mips_print_float_branch_condition (file, reverse_condition (code),
7460 int truth = (code == NE) == (letter == 'T');
7461 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7466 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7467 fputs (mips_fp_conditions[UINTVAL (op)], file);
7469 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7476 mips_print_operand (file, op, 0);
7482 if (code == REG && MD_REG_P (REGNO (op)))
7483 fprintf (file, "$ac0");
7484 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7485 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7487 output_operand_lossage ("invalid use of '%%%c'", letter);
7495 unsigned int regno = REGNO (op);
7496 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7497 || (letter == 'L' && TARGET_BIG_ENDIAN)
7500 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7501 output_operand_lossage ("invalid use of '%%%c'", letter);
7502 /* We need to print $0 .. $31 for COP0 registers. */
7503 if (COP0_REG_P (regno))
7504 fprintf (file, "$%s", ®_names[regno][4]);
7506 fprintf (file, "%s", reg_names[regno]);
7512 output_address (plus_constant (XEXP (op, 0), 4));
7513 else if (letter && letter != 'z')
7514 output_operand_lossage ("invalid use of '%%%c'", letter);
7516 output_address (XEXP (op, 0));
7520 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7521 fputs (reg_names[GP_REG_FIRST], file);
7522 else if (letter && letter != 'z')
7523 output_operand_lossage ("invalid use of '%%%c'", letter);
7524 else if (CONST_GP_P (op))
7525 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7527 output_addr_const (file, mips_strip_unspec_address (op));
7533 /* Output address operand X to FILE. */
7536 mips_print_operand_address (FILE *file, rtx x)
7538 struct mips_address_info addr;
7540 if (mips_classify_address (&addr, x, word_mode, true))
7544 mips_print_operand (file, addr.offset, 0);
7545 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7548 case ADDRESS_LO_SUM:
7549 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7551 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7554 case ADDRESS_CONST_INT:
7555 output_addr_const (file, x);
7556 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7559 case ADDRESS_SYMBOLIC:
7560 output_addr_const (file, mips_strip_unspec_address (x));
7566 /* Implement TARGET_ENCODE_SECTION_INFO. */
7569 mips_encode_section_info (tree decl, rtx rtl, int first)
7571 default_encode_section_info (decl, rtl, first);
7573 if (TREE_CODE (decl) == FUNCTION_DECL)
7575 rtx symbol = XEXP (rtl, 0);
7576 tree type = TREE_TYPE (decl);
7578 /* Encode whether the symbol is short or long. */
7579 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7580 || mips_far_type_p (type))
7581 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7585 /* Implement TARGET_SELECT_RTX_SECTION. */
7588 mips_select_rtx_section (enum machine_mode mode, rtx x,
7589 unsigned HOST_WIDE_INT align)
7591 /* ??? Consider using mergeable small data sections. */
7592 if (mips_rtx_constant_in_small_data_p (mode))
7593 return get_named_section (NULL, ".sdata", 0);
7595 return default_elf_select_rtx_section (mode, x, align);
7598 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7600 The complication here is that, with the combination TARGET_ABICALLS
7601 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7602 absolute addresses, and should therefore not be included in the
7603 read-only part of a DSO. Handle such cases by selecting a normal
7604 data section instead of a read-only one. The logic apes that in
7605 default_function_rodata_section. */
7608 mips_function_rodata_section (tree decl)
7610 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7611 return default_function_rodata_section (decl);
7613 if (decl && DECL_SECTION_NAME (decl))
7615 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7616 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7618 char *rname = ASTRDUP (name);
7620 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7622 else if (flag_function_sections
7623 && flag_data_sections
7624 && strncmp (name, ".text.", 6) == 0)
7626 char *rname = ASTRDUP (name);
7627 memcpy (rname + 1, "data", 4);
7628 return get_section (rname, SECTION_WRITE, decl);
7631 return data_section;
7634 /* Implement TARGET_IN_SMALL_DATA_P. */
7637 mips_in_small_data_p (const_tree decl)
7639 unsigned HOST_WIDE_INT size;
7641 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7644 /* We don't yet generate small-data references for -mabicalls
7645 or VxWorks RTP code. See the related -G handling in
7646 mips_override_options. */
7647 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7650 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7654 /* Reject anything that isn't in a known small-data section. */
7655 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7656 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7659 /* If a symbol is defined externally, the assembler will use the
7660 usual -G rules when deciding how to implement macros. */
7661 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7664 else if (TARGET_EMBEDDED_DATA)
7666 /* Don't put constants into the small data section: we want them
7667 to be in ROM rather than RAM. */
7668 if (TREE_CODE (decl) != VAR_DECL)
7671 if (TREE_READONLY (decl)
7672 && !TREE_SIDE_EFFECTS (decl)
7673 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7677 /* Enforce -mlocal-sdata. */
7678 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7681 /* Enforce -mextern-sdata. */
7682 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7684 if (DECL_EXTERNAL (decl))
7686 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7690 /* We have traditionally not treated zero-sized objects as small data,
7691 so this is now effectively part of the ABI. */
7692 size = int_size_in_bytes (TREE_TYPE (decl));
7693 return size > 0 && size <= mips_small_data_threshold;
7696 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7697 anchors for small data: the GP register acts as an anchor in that
7698 case. We also don't want to use them for PC-relative accesses,
7699 where the PC acts as an anchor. */
7702 mips_use_anchors_for_symbol_p (const_rtx symbol)
7704 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7706 case SYMBOL_PC_RELATIVE:
7707 case SYMBOL_GP_RELATIVE:
7711 return default_use_anchors_for_symbol_p (symbol);
7715 /* The MIPS debug format wants all automatic variables and arguments
7716 to be in terms of the virtual frame pointer (stack pointer before
7717 any adjustment in the function), while the MIPS 3.0 linker wants
7718 the frame pointer to be the stack pointer after the initial
7719 adjustment. So, we do the adjustment here. The arg pointer (which
7720 is eliminated) points to the virtual frame pointer, while the frame
7721 pointer (which may be eliminated) points to the stack pointer after
7722 the initial adjustments. */
7725 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7727 rtx offset2 = const0_rtx;
7728 rtx reg = eliminate_constant_term (addr, &offset2);
7731 offset = INTVAL (offset2);
7733 if (reg == stack_pointer_rtx
7734 || reg == frame_pointer_rtx
7735 || reg == hard_frame_pointer_rtx)
7737 offset -= cfun->machine->frame.total_size;
7738 if (reg == hard_frame_pointer_rtx)
7739 offset += cfun->machine->frame.hard_frame_pointer_offset;
7742 /* sdbout_parms does not want this to crash for unrecognized cases. */
7744 else if (reg != arg_pointer_rtx)
7745 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7752 /* Implement ASM_OUTPUT_EXTERNAL. */
7755 mips_output_external (FILE *file, tree decl, const char *name)
7757 default_elf_asm_output_external (file, decl, name);
7759 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7760 set in order to avoid putting out names that are never really
7762 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7764 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7766 /* When using assembler macros, emit .extern directives for
7767 all small-data externs so that the assembler knows how
7770 In most cases it would be safe (though pointless) to emit
7771 .externs for other symbols too. One exception is when an
7772 object is within the -G limit but declared by the user to
7773 be in a section other than .sbss or .sdata. */
7774 fputs ("\t.extern\t", file);
7775 assemble_name (file, name);
7776 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7777 int_size_in_bytes (TREE_TYPE (decl)));
7779 else if (TARGET_IRIX
7780 && mips_abi == ABI_32
7781 && TREE_CODE (decl) == FUNCTION_DECL)
7783 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
7784 `.global name .text' directive for every used but
7785 undefined function. If we don't, the linker may perform
7786 an optimization (skipping over the insns that set $gp)
7787 when it is unsafe. */
7788 fputs ("\t.globl ", file);
7789 assemble_name (file, name);
7790 fputs (" .text\n", file);
7795 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7798 mips_output_filename (FILE *stream, const char *name)
7800 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7802 if (write_symbols == DWARF2_DEBUG)
7804 else if (mips_output_filename_first_time)
7806 mips_output_filename_first_time = 0;
7807 num_source_filenames += 1;
7808 current_function_file = name;
7809 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7810 output_quoted_string (stream, name);
7811 putc ('\n', stream);
7813 /* If we are emitting stabs, let dbxout.c handle this (except for
7814 the mips_output_filename_first_time case). */
7815 else if (write_symbols == DBX_DEBUG)
7817 else if (name != current_function_file
7818 && strcmp (name, current_function_file) != 0)
7820 num_source_filenames += 1;
7821 current_function_file = name;
7822 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7823 output_quoted_string (stream, name);
7824 putc ('\n', stream);
7828 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7830 static void ATTRIBUTE_UNUSED
7831 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7836 fputs ("\t.dtprelword\t", file);
7840 fputs ("\t.dtpreldword\t", file);
7846 output_addr_const (file, x);
7847 fputs ("+0x8000", file);
7850 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7853 mips_dwarf_register_span (rtx reg)
7856 enum machine_mode mode;
7858 /* By default, GCC maps increasing register numbers to increasing
7859 memory locations, but paired FPRs are always little-endian,
7860 regardless of the prevailing endianness. */
7861 mode = GET_MODE (reg);
7862 if (FP_REG_P (REGNO (reg))
7863 && TARGET_BIG_ENDIAN
7864 && MAX_FPRS_PER_FMT > 1
7865 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7867 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7868 high = mips_subword (reg, true);
7869 low = mips_subword (reg, false);
7870 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7876 /* Implement ASM_OUTPUT_ASCII. */
7879 mips_output_ascii (FILE *stream, const char *string, size_t len)
7885 fprintf (stream, "\t.ascii\t\"");
7886 for (i = 0; i < len; i++)
7890 c = (unsigned char) string[i];
7893 if (c == '\\' || c == '\"')
7895 putc ('\\', stream);
7903 fprintf (stream, "\\%03o", c);
7907 if (cur_pos > 72 && i+1 < len)
7910 fprintf (stream, "\"\n\t.ascii\t\"");
7913 fprintf (stream, "\"\n");
7916 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7917 macros, mark the symbol as written so that mips_asm_output_external
7918 won't emit an .extern for it. STREAM is the output file, NAME is the
7919 name of the symbol, INIT_STRING is the string that should be written
7920 before the symbol and FINAL_STRING is the string that should be
7921 written after it. FINAL_STRING is a printf format that consumes the
7922 remaining arguments. */
7925 mips_declare_object (FILE *stream, const char *name, const char *init_string,
7926 const char *final_string, ...)
7930 fputs (init_string, stream);
7931 assemble_name (stream, name);
7932 va_start (ap, final_string);
7933 vfprintf (stream, final_string, ap);
7936 if (!TARGET_EXPLICIT_RELOCS)
7938 tree name_tree = get_identifier (name);
7939 TREE_ASM_WRITTEN (name_tree) = 1;
7943 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
7944 NAME is the name of the object and ALIGN is the required alignment
7945 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
7946 alignment argument. */
7949 mips_declare_common_object (FILE *stream, const char *name,
7950 const char *init_string,
7951 unsigned HOST_WIDE_INT size,
7952 unsigned int align, bool takes_alignment_p)
7954 if (!takes_alignment_p)
7956 size += (align / BITS_PER_UNIT) - 1;
7957 size -= size % (align / BITS_PER_UNIT);
7958 mips_declare_object (stream, name, init_string,
7959 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
7962 mips_declare_object (stream, name, init_string,
7963 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
7964 size, align / BITS_PER_UNIT);
7967 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
7968 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
7971 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
7972 unsigned HOST_WIDE_INT size,
7975 /* If the target wants uninitialized const declarations in
7976 .rdata then don't put them in .comm. */
7977 if (TARGET_EMBEDDED_DATA
7978 && TARGET_UNINIT_CONST_IN_RODATA
7979 && TREE_CODE (decl) == VAR_DECL
7980 && TREE_READONLY (decl)
7981 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
7983 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
7984 targetm.asm_out.globalize_label (stream, name);
7986 switch_to_section (readonly_data_section);
7987 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
7988 mips_declare_object (stream, name, "",
7989 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
7993 mips_declare_common_object (stream, name, "\n\t.comm\t",
7997 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7998 extern int size_directive_output;
8000 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8001 definitions except that it uses mips_declare_object to emit the label. */
8004 mips_declare_object_name (FILE *stream, const char *name,
8005 tree decl ATTRIBUTE_UNUSED)
8007 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8008 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8011 size_directive_output = 0;
8012 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8016 size_directive_output = 1;
8017 size = int_size_in_bytes (TREE_TYPE (decl));
8018 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8021 mips_declare_object (stream, name, "", ":\n");
8024 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8027 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8031 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8032 if (!flag_inhibit_size_directive
8033 && DECL_SIZE (decl) != 0
8036 && DECL_INITIAL (decl) == error_mark_node
8037 && !size_directive_output)
8041 size_directive_output = 1;
8042 size = int_size_in_bytes (TREE_TYPE (decl));
8043 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8048 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8049 with the current ABI. */
8052 mips_mdebug_abi_name (void)
8065 return TARGET_64BIT ? "eabi64" : "eabi32";
8071 /* Implement TARGET_ASM_FILE_START. */
8074 mips_file_start (void)
8076 default_file_start ();
8078 /* Generate a special section to describe the ABI switches used to
8079 produce the resultant binary. This is unnecessary on IRIX and
8080 causes unwanted warnings from the native linker. */
8083 /* Record the ABI itself. Modern versions of binutils encode
8084 this information in the ELF header flags, but GDB needs the
8085 information in order to correctly debug binaries produced by
8086 older binutils. See the function mips_gdbarch_init in
8088 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8089 mips_mdebug_abi_name ());
8091 /* There is no ELF header flag to distinguish long32 forms of the
8092 EABI from long64 forms. Emit a special section to help tools
8093 such as GDB. Do the same for o64, which is sometimes used with
8095 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8096 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8097 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8099 #ifdef HAVE_AS_GNU_ATTRIBUTE
8100 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
8101 (TARGET_HARD_FLOAT_ABI
8102 ? (TARGET_DOUBLE_FLOAT
8103 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
8107 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8108 if (TARGET_ABICALLS)
8110 fprintf (asm_out_file, "\t.abicalls\n");
8111 if (TARGET_ABICALLS_PIC0)
8112 fprintf (asm_out_file, "\t.option\tpic0\n");
8115 if (flag_verbose_asm)
8116 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8118 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8121 /* Make the last instruction frame-related and note that it performs
8122 the operation described by FRAME_PATTERN. */
8125 mips_set_frame_expr (rtx frame_pattern)
8129 insn = get_last_insn ();
8130 RTX_FRAME_RELATED_P (insn) = 1;
8131 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8136 /* Return a frame-related rtx that stores REG at MEM.
8137 REG must be a single register. */
8140 mips_frame_set (rtx mem, rtx reg)
8144 /* If we're saving the return address register and the DWARF return
8145 address column differs from the hard register number, adjust the
8146 note reg to refer to the former. */
8147 if (REGNO (reg) == RETURN_ADDR_REGNUM
8148 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8149 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8151 set = gen_rtx_SET (VOIDmode, mem, reg);
8152 RTX_FRAME_RELATED_P (set) = 1;
8157 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8158 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8159 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8160 static const unsigned char mips16e_s2_s8_regs[] = {
8161 30, 23, 22, 21, 20, 19, 18
8163 static const unsigned char mips16e_a0_a3_regs[] = {
8167 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8168 ordered from the uppermost in memory to the lowest in memory. */
8169 static const unsigned char mips16e_save_restore_regs[] = {
8170 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8173 /* Return the index of the lowest X in the range [0, SIZE) for which
8174 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8177 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8182 for (i = 0; i < size; i++)
8183 if (BITSET_P (mask, regs[i]))
8189 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8190 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8191 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8192 is true for all indexes (X, SIZE). */
8195 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8196 unsigned int size, unsigned int *num_regs_ptr)
8200 i = mips16e_find_first_register (*mask_ptr, regs, size);
8201 for (i++; i < size; i++)
8202 if (!BITSET_P (*mask_ptr, regs[i]))
8205 *mask_ptr |= 1 << regs[i];
8209 /* Return a simplified form of X using the register values in REG_VALUES.
8210 REG_VALUES[R] is the last value assigned to hard register R, or null
8211 if R has not been modified.
8213 This function is rather limited, but is good enough for our purposes. */
8216 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8218 x = avoid_constant_pool_reference (x);
8222 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8223 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8224 x0, GET_MODE (XEXP (x, 0)));
8227 if (ARITHMETIC_P (x))
8229 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8230 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8231 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8235 && reg_values[REGNO (x)]
8236 && !rtx_unstable_p (reg_values[REGNO (x)]))
8237 return reg_values[REGNO (x)];
8242 /* Return true if (set DEST SRC) stores an argument register into its
8243 caller-allocated save slot, storing the number of that argument
8244 register in *REGNO_PTR if so. REG_VALUES is as for
8245 mips16e_collect_propagate_value. */
8248 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8249 unsigned int *regno_ptr)
8251 unsigned int argno, regno;
8252 HOST_WIDE_INT offset, required_offset;
8255 /* Check that this is a word-mode store. */
8256 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8259 /* Check that the register being saved is an unmodified argument
8261 regno = REGNO (src);
8262 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8264 argno = regno - GP_ARG_FIRST;
8266 /* Check whether the address is an appropriate stack-pointer or
8267 frame-pointer access. */
8268 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8269 mips_split_plus (addr, &base, &offset);
8270 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8271 if (base == hard_frame_pointer_rtx)
8272 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8273 else if (base != stack_pointer_rtx)
8275 if (offset != required_offset)
8282 /* A subroutine of mips_expand_prologue, called only when generating
8283 MIPS16e SAVE instructions. Search the start of the function for any
8284 instructions that save argument registers into their caller-allocated
8285 save slots. Delete such instructions and return a value N such that
8286 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8287 instructions redundant. */
8290 mips16e_collect_argument_saves (void)
8292 rtx reg_values[FIRST_PSEUDO_REGISTER];
8293 rtx insn, next, set, dest, src;
8294 unsigned int nargs, regno;
8296 push_topmost_sequence ();
8298 memset (reg_values, 0, sizeof (reg_values));
8299 for (insn = get_insns (); insn; insn = next)
8301 next = NEXT_INSN (insn);
8302 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8308 set = PATTERN (insn);
8309 if (GET_CODE (set) != SET)
8312 dest = SET_DEST (set);
8313 src = SET_SRC (set);
8314 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8316 if (!BITSET_P (cfun->machine->frame.mask, regno))
8319 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8322 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8323 reg_values[REGNO (dest)]
8324 = mips16e_collect_propagate_value (src, reg_values);
8328 pop_topmost_sequence ();
8333 /* Return a move between register REGNO and memory location SP + OFFSET.
8334 Make the move a load if RESTORE_P, otherwise make it a frame-related
8338 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8343 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8344 reg = gen_rtx_REG (SImode, regno);
8346 ? gen_rtx_SET (VOIDmode, reg, mem)
8347 : mips_frame_set (mem, reg));
8350 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8351 The instruction must:
8353 - Allocate or deallocate SIZE bytes in total; SIZE is known
8356 - Save or restore as many registers in *MASK_PTR as possible.
8357 The instruction saves the first registers at the top of the
8358 allocated area, with the other registers below it.
8360 - Save NARGS argument registers above the allocated area.
8362 (NARGS is always zero if RESTORE_P.)
8364 The SAVE and RESTORE instructions cannot save and restore all general
8365 registers, so there may be some registers left over for the caller to
8366 handle. Destructively modify *MASK_PTR so that it contains the registers
8367 that still need to be saved or restored. The caller can save these
8368 registers in the memory immediately below *OFFSET_PTR, which is a
8369 byte offset from the bottom of the allocated stack area. */
8372 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8373 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8377 HOST_WIDE_INT offset, top_offset;
8378 unsigned int i, regno;
8381 gcc_assert (cfun->machine->frame.num_fp == 0);
8383 /* Calculate the number of elements in the PARALLEL. We need one element
8384 for the stack adjustment, one for each argument register save, and one
8385 for each additional register move. */
8387 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8388 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8391 /* Create the final PARALLEL. */
8392 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8395 /* Add the stack pointer adjustment. */
8396 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8397 plus_constant (stack_pointer_rtx,
8398 restore_p ? size : -size));
8399 RTX_FRAME_RELATED_P (set) = 1;
8400 XVECEXP (pattern, 0, n++) = set;
8402 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8403 top_offset = restore_p ? size : 0;
8405 /* Save the arguments. */
8406 for (i = 0; i < nargs; i++)
8408 offset = top_offset + i * UNITS_PER_WORD;
8409 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8410 XVECEXP (pattern, 0, n++) = set;
8413 /* Then fill in the other register moves. */
8414 offset = top_offset;
8415 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8417 regno = mips16e_save_restore_regs[i];
8418 if (BITSET_P (*mask_ptr, regno))
8420 offset -= UNITS_PER_WORD;
8421 set = mips16e_save_restore_reg (restore_p, offset, regno);
8422 XVECEXP (pattern, 0, n++) = set;
8423 *mask_ptr &= ~(1 << regno);
8427 /* Tell the caller what offset it should use for the remaining registers. */
8428 *offset_ptr = size + (offset - top_offset);
8430 gcc_assert (n == XVECLEN (pattern, 0));
8435 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8436 pointer. Return true if PATTERN matches the kind of instruction
8437 generated by mips16e_build_save_restore. If INFO is nonnull,
8438 initialize it when returning true. */
8441 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8442 struct mips16e_save_restore_info *info)
8444 unsigned int i, nargs, mask, extra;
8445 HOST_WIDE_INT top_offset, save_offset, offset;
8446 rtx set, reg, mem, base;
8449 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8452 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8453 top_offset = adjust > 0 ? adjust : 0;
8455 /* Interpret all other members of the PARALLEL. */
8456 save_offset = top_offset - UNITS_PER_WORD;
8460 for (n = 1; n < XVECLEN (pattern, 0); n++)
8462 /* Check that we have a SET. */
8463 set = XVECEXP (pattern, 0, n);
8464 if (GET_CODE (set) != SET)
8467 /* Check that the SET is a load (if restoring) or a store
8469 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8473 /* Check that the address is the sum of the stack pointer and a
8474 possibly-zero constant offset. */
8475 mips_split_plus (XEXP (mem, 0), &base, &offset);
8476 if (base != stack_pointer_rtx)
8479 /* Check that SET's other operand is a register. */
8480 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8484 /* Check for argument saves. */
8485 if (offset == top_offset + nargs * UNITS_PER_WORD
8486 && REGNO (reg) == GP_ARG_FIRST + nargs)
8488 else if (offset == save_offset)
8490 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8491 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8494 mask |= 1 << REGNO (reg);
8495 save_offset -= UNITS_PER_WORD;
8501 /* Check that the restrictions on register ranges are met. */
8503 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8504 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8505 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8506 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8510 /* Make sure that the topmost argument register is not saved twice.
8511 The checks above ensure that the same is then true for the other
8512 argument registers. */
8513 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8516 /* Pass back information, if requested. */
8519 info->nargs = nargs;
8521 info->size = (adjust > 0 ? adjust : -adjust);
8527 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8528 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8529 the null terminator. */
8532 mips16e_add_register_range (char *s, unsigned int min_reg,
8533 unsigned int max_reg)
8535 if (min_reg != max_reg)
8536 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8538 s += sprintf (s, ",%s", reg_names[min_reg]);
8542 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8543 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8546 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8548 static char buffer[300];
8550 struct mips16e_save_restore_info info;
8551 unsigned int i, end;
8554 /* Parse the pattern. */
8555 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8558 /* Add the mnemonic. */
8559 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8562 /* Save the arguments. */
8564 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8565 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8566 else if (info.nargs == 1)
8567 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8569 /* Emit the amount of stack space to allocate or deallocate. */
8570 s += sprintf (s, "%d", (int) info.size);
8572 /* Save or restore $16. */
8573 if (BITSET_P (info.mask, 16))
8574 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8576 /* Save or restore $17. */
8577 if (BITSET_P (info.mask, 17))
8578 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8580 /* Save or restore registers in the range $s2...$s8, which
8581 mips16e_s2_s8_regs lists in decreasing order. Note that this
8582 is a software register range; the hardware registers are not
8583 numbered consecutively. */
8584 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8585 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8587 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8588 mips16e_s2_s8_regs[i]);
8590 /* Save or restore registers in the range $a0...$a3. */
8591 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8592 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8594 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8595 mips16e_a0_a3_regs[end - 1]);
8597 /* Save or restore $31. */
8598 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8599 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8604 /* Return true if the current function returns its value in a floating-point
8605 register in MIPS16 mode. */
8608 mips16_cfun_returns_in_fpr_p (void)
8610 tree return_type = DECL_RESULT (current_function_decl);
8611 return (TARGET_MIPS16
8612 && TARGET_HARD_FLOAT_ABI
8613 && !aggregate_value_p (return_type, current_function_decl)
8614 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8617 /* Return true if predicate PRED is true for at least one instruction.
8618 Cache the result in *CACHE, and assume that the result is true
8619 if *CACHE is already true. */
8622 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8628 push_topmost_sequence ();
8629 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8630 if (USEFUL_INSN_P (insn) && pred (insn))
8635 pop_topmost_sequence ();
8640 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8641 See mips_cfun_has_inflexible_gp_ref_p for details. */
8644 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8646 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8647 indicate that the target could be a traditional MIPS
8648 lazily-binding stub. */
8649 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8652 /* Return true if the current function refers to the global pointer
8653 in a way that forces $28 to be valid. This means that we can't
8654 change the choice of global pointer, even for NewABI code.
8656 One example of this (and one which needs several checks) is that
8657 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8658 (This restriction does not apply to PLTs.) */
8661 mips_cfun_has_inflexible_gp_ref_p (void)
8663 /* If the function has a nonlocal goto, $28 must hold the correct
8664 global pointer for the target function. That is, the target
8665 of the goto implicitly uses $28. */
8666 if (crtl->has_nonlocal_goto)
8669 if (TARGET_ABICALLS_PIC2)
8671 /* Symbolic accesses implicitly use the global pointer unless
8672 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8673 might go to traditional MIPS lazy-binding stubs. */
8674 if (!TARGET_EXPLICIT_RELOCS)
8677 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8678 can be lazily-bound. */
8682 /* MIPS16 functions that return in FPRs need to call an
8683 external libgcc routine. This call is only made explict
8684 during mips_expand_epilogue, and it too might be lazily bound. */
8685 if (mips16_cfun_returns_in_fpr_p ())
8689 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8690 mips_insn_has_inflexible_gp_ref_p);
8693 /* Return true if INSN refers to the global pointer in a "flexible" way.
8694 See mips_cfun_has_flexible_gp_ref_p for details. */
8697 mips_insn_has_flexible_gp_ref_p (rtx insn)
8699 return (get_attr_got (insn) != GOT_UNSET
8700 || mips_small_data_pattern_p (PATTERN (insn))
8701 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8704 /* Return true if the current function references the global pointer,
8705 but if those references do not inherently require the global pointer
8706 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8709 mips_cfun_has_flexible_gp_ref_p (void)
8711 /* Reload can sometimes introduce constant pool references
8712 into a function that otherwise didn't need them. For example,
8713 suppose we have an instruction like:
8715 (set (reg:DF R1) (float:DF (reg:SI R2)))
8717 If R2 turns out to be a constant such as 1, the instruction may
8718 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8719 the option of using this constant if R2 doesn't get allocated
8722 In cases like these, reload will have added the constant to the
8723 pool but no instruction will yet refer to it. */
8724 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8727 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8728 mips_insn_has_flexible_gp_ref_p);
8731 /* Return the register that should be used as the global pointer
8732 within this function. Return INVALID_REGNUM if the function
8733 doesn't need a global pointer. */
8736 mips_global_pointer (void)
8740 /* $gp is always available unless we're using a GOT. */
8741 if (!TARGET_USE_GOT)
8742 return GLOBAL_POINTER_REGNUM;
8744 /* If there are inflexible references to $gp, we must use the
8745 standard register. */
8746 if (mips_cfun_has_inflexible_gp_ref_p ())
8747 return GLOBAL_POINTER_REGNUM;
8749 /* If there are no current references to $gp, then the only uses
8750 we can introduce later are those involved in long branches. */
8751 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8752 return INVALID_REGNUM;
8754 /* If the global pointer is call-saved, try to use a call-clobbered
8756 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8757 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8758 if (!df_regs_ever_live_p (regno)
8759 && call_really_used_regs[regno]
8760 && !fixed_regs[regno]
8761 && regno != PIC_FUNCTION_ADDR_REGNUM)
8764 return GLOBAL_POINTER_REGNUM;
8767 /* Return true if the current function's prologue must load the global
8768 pointer value into pic_offset_table_rtx and store the same value in
8769 the function's cprestore slot (if any).
8771 One problem we have to deal with is that, when emitting GOT-based
8772 position independent code, long-branch sequences will need to load
8773 the address of the branch target from the GOT. We don't know until
8774 the very end of compilation whether (and where) the function needs
8775 long branches, so we must ensure that _any_ branch can access the
8776 global pointer in some form. However, we do not want to pessimize
8777 the usual case in which all branches are short.
8779 We handle this as follows:
8781 (1) During reload, we set cfun->machine->global_pointer to
8782 INVALID_REGNUM if we _know_ that the current function
8783 doesn't need a global pointer. This is only valid if
8784 long branches don't need the GOT.
8786 Otherwise, we assume that we might need a global pointer
8787 and pick an appropriate register.
8789 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8790 we ensure that the global pointer is available at every
8791 block boundary bar entry and exit. We do this in one of two ways:
8793 - If the function has a cprestore slot, we ensure that this
8794 slot is valid at every branch. However, as explained in
8795 point (6) below, there is no guarantee that pic_offset_table_rtx
8796 itself is valid if new uses of the global pointer are introduced
8797 after the first post-epilogue split.
8799 We guarantee that the cprestore slot is valid by loading it
8800 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8801 this register live at every block boundary bar function entry
8802 and exit. It is then invalid to move the load (and thus the
8803 preceding store) across a block boundary.
8805 - If the function has no cprestore slot, we guarantee that
8806 pic_offset_table_rtx itself is valid at every branch.
8808 See mips_eh_uses for the handling of the register liveness.
8810 (3) During prologue and epilogue generation, we emit "ghost"
8811 placeholder instructions to manipulate the global pointer.
8813 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8814 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8815 that the function needs a global pointer. (There is no need to set
8816 them earlier than this, and doing it as late as possible leads to
8817 fewer false positives.)
8819 (5) If cfun->machine->must_initialize_gp_p is true during a
8820 split_insns pass, we split the ghost instructions into real
8821 instructions. These split instructions can then be optimized in
8822 the usual way. Otherwise, we keep the ghost instructions intact,
8823 and optimize for the case where they aren't needed. We still
8824 have the option of splitting them later, if we need to introduce
8825 new uses of the global pointer.
8827 For example, the scheduler ignores a ghost instruction that
8828 stores $28 to the stack, but it handles the split form of
8829 the ghost instruction as an ordinary store.
8831 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8832 is true during the first post-epilogue split_insns pass, we split
8833 calls and restore_gp patterns into instructions that explicitly
8834 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8835 we split these patterns into instructions that _don't_ load from
8838 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8839 time of the split, then any instructions that exist at that time
8840 can make free use of pic_offset_table_rtx. However, if we want
8841 to introduce new uses of the global pointer after the split,
8842 we must explicitly load the value from the cprestore slot, since
8843 pic_offset_table_rtx itself might not be valid at a given point
8846 The idea is that we want to be able to delete redundant
8847 loads from the cprestore slot in the usual case where no
8848 long branches are needed.
8850 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8851 of md_reorg, we decide whether the global pointer is needed for
8852 long branches. If so, we set cfun->machine->must_initialize_gp_p
8853 to true and split the ghost instructions into real instructions
8856 Note that the ghost instructions must have a zero length for three reasons:
8858 - Giving the length of the underlying $gp sequence might cause
8859 us to use long branches in cases where they aren't really needed.
8861 - They would perturb things like alignment calculations.
8863 - More importantly, the hazard detection in md_reorg relies on
8864 empty instructions having a zero length.
8866 If we find a long branch and split the ghost instructions at the
8867 end of md_reorg, the split could introduce more long branches.
8868 That isn't a problem though, because we still do the split before
8869 the final shorten_branches pass.
8871 This is extremely ugly, but it seems like the best compromise between
8872 correctness and efficiency. */
8875 mips_must_initialize_gp_p (void)
8877 return cfun->machine->must_initialize_gp_p;
8880 /* Return true if REGNO is a register that is ordinarily call-clobbered
8881 but must nevertheless be preserved by an interrupt handler. */
8884 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8886 if (MD_REG_P (regno))
8889 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8892 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8894 /* $0 is hard-wired. */
8895 if (regno == GP_REG_FIRST)
8898 /* The interrupt handler can treat kernel registers as
8899 scratch registers. */
8900 if (KERNEL_REG_P (regno))
8903 /* The function will return the stack pointer to its original value
8905 if (regno == STACK_POINTER_REGNUM)
8908 /* Otherwise, return true for registers that aren't ordinarily
8910 return call_really_used_regs[regno];
8916 /* Return true if the current function should treat register REGNO
8920 mips_cfun_call_saved_reg_p (unsigned int regno)
8922 /* Interrupt handlers need to save extra registers. */
8923 if (cfun->machine->interrupt_handler_p
8924 && mips_interrupt_extra_call_saved_reg_p (regno))
8927 /* call_insns preserve $28 unless they explicitly say otherwise,
8928 so call_really_used_regs[] treats $28 as call-saved. However,
8929 we want the ABI property rather than the default call_insn
8931 return (regno == GLOBAL_POINTER_REGNUM
8932 ? TARGET_CALL_SAVED_GP
8933 : !call_really_used_regs[regno]);
8936 /* Return true if the function body might clobber register REGNO.
8937 We know that REGNO is call-saved. */
8940 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
8942 /* Some functions should be treated as clobbering all call-saved
8944 if (crtl->saves_all_registers)
8947 /* DF handles cases where a register is explicitly referenced in
8948 the rtl. Incoming values are passed in call-clobbered registers,
8949 so we can assume that any live call-saved register is set within
8951 if (df_regs_ever_live_p (regno))
8954 /* Check for registers that are clobbered by FUNCTION_PROFILER.
8955 These clobbers are not explicit in the rtl. */
8956 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
8959 /* If we're using a call-saved global pointer, the function's
8960 prologue will need to set it up. */
8961 if (cfun->machine->global_pointer == regno)
8964 /* The function's prologue will need to set the frame pointer if
8965 frame_pointer_needed. */
8966 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
8969 /* If a MIPS16 function returns a value in FPRs, its epilogue
8970 will need to call an external libgcc routine. This yet-to-be
8971 generated call_insn will clobber $31. */
8972 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
8975 /* If REGNO is ordinarily call-clobbered, we must assume that any
8976 called function could modify it. */
8977 if (cfun->machine->interrupt_handler_p
8978 && !current_function_is_leaf
8979 && mips_interrupt_extra_call_saved_reg_p (regno))
8985 /* Return true if the current function must save register REGNO. */
8988 mips_save_reg_p (unsigned int regno)
8990 if (mips_cfun_call_saved_reg_p (regno))
8992 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
8995 /* Save both registers in an FPR pair if either one is used. This is
8996 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
8997 register to be used without the even register. */
8998 if (FP_REG_P (regno)
8999 && MAX_FPRS_PER_FMT == 2
9000 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9004 /* We need to save the incoming return address if __builtin_eh_return
9005 is being used to set a different return address. */
9006 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9012 /* Populate the current function's mips_frame_info structure.
9014 MIPS stack frames look like:
9016 +-------------------------------+
9018 | incoming stack arguments |
9020 +-------------------------------+
9022 | caller-allocated save area |
9023 A | for register arguments |
9025 +-------------------------------+ <-- incoming stack pointer
9027 | callee-allocated save area |
9028 B | for arguments that are |
9029 | split between registers and |
9032 +-------------------------------+ <-- arg_pointer_rtx
9034 C | callee-allocated save area |
9035 | for register varargs |
9037 +-------------------------------+ <-- frame_pointer_rtx
9038 | | + cop0_sp_offset
9039 | COP0 reg save area | + UNITS_PER_WORD
9041 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9042 | | + UNITS_PER_WORD
9043 | accumulator save area |
9045 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9046 | | + UNITS_PER_HWFPVALUE
9049 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9050 | | + UNITS_PER_WORD
9053 +-------------------------------+ <-- frame_pointer_rtx with
9054 | | \ -fstack-protector
9055 | local variables | | var_size
9057 +-------------------------------+
9059 | $gp save area | | cprestore_size
9061 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9063 | outgoing stack arguments | |
9065 +-------------------------------+ | args_size
9067 | caller-allocated save area | |
9068 | for register arguments | |
9070 +-------------------------------+ <-- stack_pointer_rtx
9071 frame_pointer_rtx without
9073 hard_frame_pointer_rtx for
9076 At least two of A, B and C will be empty.
9078 Dynamic stack allocations such as alloca insert data at point P.
9079 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9080 hard_frame_pointer_rtx unchanged. */
9083 mips_compute_frame_info (void)
9085 struct mips_frame_info *frame;
9086 HOST_WIDE_INT offset, size;
9087 unsigned int regno, i;
9089 /* Set this function's interrupt properties. */
9090 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9093 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9094 else if (TARGET_HARD_FLOAT)
9095 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9096 else if (TARGET_MIPS16)
9097 error ("interrupt handlers cannot be MIPS16 functions");
9100 cfun->machine->interrupt_handler_p = true;
9101 cfun->machine->use_shadow_register_set_p =
9102 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9103 cfun->machine->keep_interrupts_masked_p =
9104 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9105 cfun->machine->use_debug_exception_return_p =
9106 mips_use_debug_exception_return_p (TREE_TYPE
9107 (current_function_decl));
9111 frame = &cfun->machine->frame;
9112 memset (frame, 0, sizeof (*frame));
9113 size = get_frame_size ();
9115 cfun->machine->global_pointer = mips_global_pointer ();
9117 /* The first two blocks contain the outgoing argument area and the $gp save
9118 slot. This area isn't needed in leaf functions, but if the
9119 target-independent frame size is nonzero, we have already committed to
9120 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9121 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9123 /* The MIPS 3.0 linker does not like functions that dynamically
9124 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9125 looks like we are trying to create a second frame pointer to the
9126 function, so allocate some stack space to make it happy. */
9127 if (cfun->calls_alloca)
9128 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9130 frame->args_size = 0;
9131 frame->cprestore_size = 0;
9135 frame->args_size = crtl->outgoing_args_size;
9136 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9138 offset = frame->args_size + frame->cprestore_size;
9140 /* Move above the local variables. */
9141 frame->var_size = MIPS_STACK_ALIGN (size);
9142 offset += frame->var_size;
9144 /* Find out which GPRs we need to save. */
9145 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9146 if (mips_save_reg_p (regno))
9149 frame->mask |= 1 << (regno - GP_REG_FIRST);
9152 /* If this function calls eh_return, we must also save and restore the
9153 EH data registers. */
9154 if (crtl->calls_eh_return)
9155 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9158 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9161 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9162 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9163 save all later registers too. */
9164 if (GENERATE_MIPS16E_SAVE_RESTORE)
9166 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9167 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9168 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9169 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9172 /* Move above the GPR save area. */
9173 if (frame->num_gp > 0)
9175 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9176 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9179 /* Find out which FPRs we need to save. This loop must iterate over
9180 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9181 if (TARGET_HARD_FLOAT)
9182 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9183 if (mips_save_reg_p (regno))
9185 frame->num_fp += MAX_FPRS_PER_FMT;
9186 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9189 /* Move above the FPR save area. */
9190 if (frame->num_fp > 0)
9192 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9193 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9196 /* Add in space for the interrupt context information. */
9197 if (cfun->machine->interrupt_handler_p)
9200 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9203 frame->acc_mask |= (1 << 0);
9206 /* Check accumulators 1, 2, 3. */
9207 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9208 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9211 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9214 /* All interrupt context functions need space to preserve STATUS. */
9215 frame->num_cop0_regs++;
9217 /* If we don't keep interrupts masked, we need to save EPC. */
9218 if (!cfun->machine->keep_interrupts_masked_p)
9219 frame->num_cop0_regs++;
9222 /* Move above the accumulator save area. */
9223 if (frame->num_acc > 0)
9225 /* Each accumulator needs 2 words. */
9226 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9227 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9230 /* Move above the COP0 register save area. */
9231 if (frame->num_cop0_regs > 0)
9233 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9234 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9237 /* Move above the callee-allocated varargs save area. */
9238 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9239 frame->arg_pointer_offset = offset;
9241 /* Move above the callee-allocated area for pretend stack arguments. */
9242 offset += crtl->args.pretend_args_size;
9243 frame->total_size = offset;
9245 /* Work out the offsets of the save areas from the top of the frame. */
9246 if (frame->gp_sp_offset > 0)
9247 frame->gp_save_offset = frame->gp_sp_offset - offset;
9248 if (frame->fp_sp_offset > 0)
9249 frame->fp_save_offset = frame->fp_sp_offset - offset;
9250 if (frame->acc_sp_offset > 0)
9251 frame->acc_save_offset = frame->acc_sp_offset - offset;
9252 if (frame->num_cop0_regs > 0)
9253 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9255 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9256 arguments. This tends to increase the chances of using unextended
9257 instructions for local variables and incoming arguments. */
9259 frame->hard_frame_pointer_offset = frame->args_size;
9262 /* Return the style of GP load sequence that is being used for the
9263 current function. */
9265 enum mips_loadgp_style
9266 mips_current_loadgp_style (void)
9268 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9274 if (TARGET_ABSOLUTE_ABICALLS)
9275 return LOADGP_ABSOLUTE;
9277 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9280 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9283 mips_frame_pointer_required (void)
9285 /* If the function contains dynamic stack allocations, we need to
9286 use the frame pointer to access the static parts of the frame. */
9287 if (cfun->calls_alloca)
9290 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9291 reload may be unable to compute the address of a local variable,
9292 since there is no way to add a large constant to the stack pointer
9293 without using a second temporary register. */
9296 mips_compute_frame_info ();
9297 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9304 /* Make sure that we're not trying to eliminate to the wrong hard frame
9308 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9310 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9313 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9314 or argument pointer. TO is either the stack pointer or hard frame
9318 mips_initial_elimination_offset (int from, int to)
9320 HOST_WIDE_INT offset;
9322 mips_compute_frame_info ();
9324 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9327 case FRAME_POINTER_REGNUM:
9328 if (FRAME_GROWS_DOWNWARD)
9329 offset = (cfun->machine->frame.args_size
9330 + cfun->machine->frame.cprestore_size
9331 + cfun->machine->frame.var_size);
9336 case ARG_POINTER_REGNUM:
9337 offset = cfun->machine->frame.arg_pointer_offset;
9344 if (to == HARD_FRAME_POINTER_REGNUM)
9345 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9350 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9353 mips_extra_live_on_entry (bitmap regs)
9357 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9358 the global pointer. */
9359 if (!TARGET_ABSOLUTE_ABICALLS)
9360 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9362 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9363 the global pointer. */
9365 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9367 /* See the comment above load_call<mode> for details. */
9368 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9372 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9376 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9381 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9384 /* Emit code to change the current function's return address to
9385 ADDRESS. SCRATCH is available as a scratch register, if needed.
9386 ADDRESS and SCRATCH are both word-mode GPRs. */
9389 mips_set_return_address (rtx address, rtx scratch)
9393 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9394 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9395 cfun->machine->frame.gp_sp_offset);
9396 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9399 /* Return true if the current function has a cprestore slot. */
9402 mips_cfun_has_cprestore_slot_p (void)
9404 return (cfun->machine->global_pointer != INVALID_REGNUM
9405 && cfun->machine->frame.cprestore_size > 0);
9408 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9409 cprestore slot. LOAD_P is true if the caller wants to load from
9410 the cprestore slot; it is false if the caller wants to store to
9414 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9417 const struct mips_frame_info *frame;
9419 frame = &cfun->machine->frame;
9420 /* .cprestore always uses the stack pointer instead of the frame pointer.
9421 We have a free choice for direct stores for non-MIPS16 functions,
9422 and for MIPS16 functions whose cprestore slot is in range of the
9423 stack pointer. Using the stack pointer would sometimes give more
9424 (early) scheduling freedom, but using the frame pointer would
9425 sometimes give more (late) scheduling freedom. It's hard to
9426 predict which applies to a given function, so let's keep things
9429 Loads must always use the frame pointer in functions that call
9430 alloca, and there's little benefit to using the stack pointer
9432 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9434 *base = hard_frame_pointer_rtx;
9435 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9439 *base = stack_pointer_rtx;
9440 *offset = frame->args_size;
9444 /* Return true if X is the load or store address of the cprestore slot;
9445 LOAD_P says which. */
9448 mips_cprestore_address_p (rtx x, bool load_p)
9450 rtx given_base, required_base;
9451 HOST_WIDE_INT given_offset, required_offset;
9453 mips_split_plus (x, &given_base, &given_offset);
9454 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9455 return given_base == required_base && given_offset == required_offset;
9458 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9459 going to load from it, false if we are going to store to it.
9460 Use TEMP as a temporary register if need be. */
9463 mips_cprestore_slot (rtx temp, bool load_p)
9466 HOST_WIDE_INT offset;
9468 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9469 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9472 /* Emit instructions to save global pointer value GP into cprestore
9473 slot MEM. OFFSET is the offset that MEM applies to the base register.
9475 MEM may not be a legitimate address. If it isn't, TEMP is a
9476 temporary register that can be used, otherwise it is a SCRATCH. */
9479 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9481 if (TARGET_CPRESTORE_DIRECTIVE)
9483 gcc_assert (gp == pic_offset_table_rtx);
9484 emit_insn (gen_cprestore (mem, offset));
9487 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9490 /* Restore $gp from its save slot, using TEMP as a temporary base register
9491 if need be. This function is for o32 and o64 abicalls only.
9493 See mips_must_initialize_gp_p for details about how we manage the
9497 mips_restore_gp_from_cprestore_slot (rtx temp)
9499 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9501 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9506 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9507 mips_emit_move (pic_offset_table_rtx, temp);
9510 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9511 if (!TARGET_EXPLICIT_RELOCS)
9512 emit_insn (gen_blockage ());
9515 /* A function to save or store a register. The first argument is the
9516 register and the second is the stack slot. */
9517 typedef void (*mips_save_restore_fn) (rtx, rtx);
9519 /* Use FN to save or restore register REGNO. MODE is the register's
9520 mode and OFFSET is the offset of its save slot from the current
9524 mips_save_restore_reg (enum machine_mode mode, int regno,
9525 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9529 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9530 fn (gen_rtx_REG (mode, regno), mem);
9533 /* Call FN for each accumlator that is saved by the current function.
9534 SP_OFFSET is the offset of the current stack pointer from the start
9538 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9540 HOST_WIDE_INT offset;
9543 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9544 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9546 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9547 offset -= UNITS_PER_WORD;
9548 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9549 offset -= UNITS_PER_WORD;
9552 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9553 if (BITSET_P (cfun->machine->frame.acc_mask,
9554 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9556 mips_save_restore_reg (word_mode, regno, offset, fn);
9557 offset -= UNITS_PER_WORD;
9561 /* Call FN for each register that is saved by the current function.
9562 SP_OFFSET is the offset of the current stack pointer from the start
9566 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9567 mips_save_restore_fn fn)
9569 enum machine_mode fpr_mode;
9570 HOST_WIDE_INT offset;
9573 /* Save registers starting from high to low. The debuggers prefer at least
9574 the return register be stored at func+4, and also it allows us not to
9575 need a nop in the epilogue if at least one register is reloaded in
9576 addition to return address. */
9577 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9578 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9579 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9581 mips_save_restore_reg (word_mode, regno, offset, fn);
9582 offset -= UNITS_PER_WORD;
9585 /* This loop must iterate over the same space as its companion in
9586 mips_compute_frame_info. */
9587 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9588 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9589 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9590 regno >= FP_REG_FIRST;
9591 regno -= MAX_FPRS_PER_FMT)
9592 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9594 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9595 offset -= GET_MODE_SIZE (fpr_mode);
9599 /* Return true if a move between register REGNO and its save slot (MEM)
9600 can be done in a single move. LOAD_P is true if we are loading
9601 from the slot, false if we are storing to it. */
9604 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9606 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9607 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9610 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9611 GET_MODE (mem), mem, load_p) == NO_REGS;
9614 /* Emit a move from SRC to DEST, given that one of them is a register
9615 save slot and that the other is a register. TEMP is a temporary
9616 GPR of the same mode that is available if need be. */
9619 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9626 regno = REGNO (src);
9631 regno = REGNO (dest);
9635 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9637 /* We don't yet know whether we'll need this instruction or not.
9638 Postpone the decision by emitting a ghost move. This move
9639 is specifically not frame-related; only the split version is. */
9641 emit_insn (gen_move_gpdi (dest, src));
9643 emit_insn (gen_move_gpsi (dest, src));
9647 if (regno == HI_REGNUM)
9651 mips_emit_move (temp, src);
9653 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9654 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9656 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9657 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9662 emit_insn (gen_mfhidi_ti (temp,
9663 gen_rtx_REG (TImode, MD_REG_FIRST)));
9665 emit_insn (gen_mfhisi_di (temp,
9666 gen_rtx_REG (DImode, MD_REG_FIRST)));
9667 mips_emit_move (dest, temp);
9670 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9671 mips_emit_move (dest, src);
9674 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9675 mips_emit_move (temp, src);
9676 mips_emit_move (dest, temp);
9679 mips_set_frame_expr (mips_frame_set (dest, src));
9682 /* If we're generating n32 or n64 abicalls, and the current function
9683 does not use $28 as its global pointer, emit a cplocal directive.
9684 Use pic_offset_table_rtx as the argument to the directive. */
9687 mips_output_cplocal (void)
9689 if (!TARGET_EXPLICIT_RELOCS
9690 && mips_must_initialize_gp_p ()
9691 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9692 output_asm_insn (".cplocal %+", 0);
9695 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9698 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9702 #ifdef SDB_DEBUGGING_INFO
9703 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9704 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9707 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9708 floating-point arguments. */
9710 && TARGET_HARD_FLOAT_ABI
9711 && crtl->args.info.fp_code != 0)
9712 mips16_build_function_stub ();
9714 /* Get the function name the same way that toplev.c does before calling
9715 assemble_start_function. This is needed so that the name used here
9716 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9717 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9718 mips_start_function_definition (fnname, TARGET_MIPS16);
9720 /* Stop mips_file_end from treating this function as external. */
9721 if (TARGET_IRIX && mips_abi == ABI_32)
9722 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
9724 /* Output MIPS-specific frame information. */
9725 if (!flag_inhibit_size_directive)
9727 const struct mips_frame_info *frame;
9729 frame = &cfun->machine->frame;
9731 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9733 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9734 "# vars= " HOST_WIDE_INT_PRINT_DEC
9736 ", args= " HOST_WIDE_INT_PRINT_DEC
9737 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9738 reg_names[frame_pointer_needed
9739 ? HARD_FRAME_POINTER_REGNUM
9740 : STACK_POINTER_REGNUM],
9741 (frame_pointer_needed
9742 ? frame->total_size - frame->hard_frame_pointer_offset
9743 : frame->total_size),
9744 reg_names[RETURN_ADDR_REGNUM],
9746 frame->num_gp, frame->num_fp,
9748 frame->cprestore_size);
9750 /* .mask MASK, OFFSET. */
9751 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9752 frame->mask, frame->gp_save_offset);
9754 /* .fmask MASK, OFFSET. */
9755 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9756 frame->fmask, frame->fp_save_offset);
9759 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9760 Also emit the ".set noreorder; .set nomacro" sequence for functions
9762 if (mips_must_initialize_gp_p ()
9763 && mips_current_loadgp_style () == LOADGP_OLDABI)
9767 /* This is a fixed-form sequence. The position of the
9768 first two instructions is important because of the
9769 way _gp_disp is defined. */
9770 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9771 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9772 output_asm_insn ("sll\t$2,16", 0);
9773 output_asm_insn ("addu\t$2,$3", 0);
9777 /* .cpload must be in a .set noreorder but not a
9778 .set nomacro block. */
9779 mips_push_asm_switch (&mips_noreorder);
9780 output_asm_insn (".cpload\t%^", 0);
9781 if (!cfun->machine->all_noreorder_p)
9782 mips_pop_asm_switch (&mips_noreorder);
9784 mips_push_asm_switch (&mips_nomacro);
9787 else if (cfun->machine->all_noreorder_p)
9789 mips_push_asm_switch (&mips_noreorder);
9790 mips_push_asm_switch (&mips_nomacro);
9793 /* Tell the assembler which register we're using as the global
9794 pointer. This is needed for thunks, since they can use either
9795 explicit relocs or assembler macros. */
9796 mips_output_cplocal ();
9799 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9802 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9803 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9807 /* Reinstate the normal $gp. */
9808 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9809 mips_output_cplocal ();
9811 if (cfun->machine->all_noreorder_p)
9813 mips_pop_asm_switch (&mips_nomacro);
9814 mips_pop_asm_switch (&mips_noreorder);
9817 /* Get the function name the same way that toplev.c does before calling
9818 assemble_start_function. This is needed so that the name used here
9819 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9820 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9821 mips_end_function_definition (fnname);
9824 /* Save register REG to MEM. Make the instruction frame-related. */
9827 mips_save_reg (rtx reg, rtx mem)
9829 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9833 if (mips_split_64bit_move_p (mem, reg))
9834 mips_split_doubleword_move (mem, reg);
9836 mips_emit_move (mem, reg);
9838 x1 = mips_frame_set (mips_subword (mem, false),
9839 mips_subword (reg, false));
9840 x2 = mips_frame_set (mips_subword (mem, true),
9841 mips_subword (reg, true));
9842 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9845 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9848 /* The __gnu_local_gp symbol. */
9850 static GTY(()) rtx mips_gnu_local_gp;
9852 /* If we're generating n32 or n64 abicalls, emit instructions
9853 to set up the global pointer. */
9856 mips_emit_loadgp (void)
9858 rtx addr, offset, incoming_address, base, index, pic_reg;
9860 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9861 switch (mips_current_loadgp_style ())
9863 case LOADGP_ABSOLUTE:
9864 if (mips_gnu_local_gp == NULL)
9866 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9867 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9869 emit_insn (Pmode == SImode
9870 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9871 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9875 /* Added by mips_output_function_prologue. */
9879 addr = XEXP (DECL_RTL (current_function_decl), 0);
9880 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9881 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9882 emit_insn (Pmode == SImode
9883 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9884 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9888 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9889 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9890 emit_insn (Pmode == SImode
9891 ? gen_loadgp_rtp_si (pic_reg, base, index)
9892 : gen_loadgp_rtp_di (pic_reg, base, index));
9900 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9902 /* Emit a blockage if there are implicit uses of the GP register.
9903 This includes profiled functions, because FUNCTION_PROFILE uses
9905 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9906 emit_insn (gen_loadgp_blockage ());
9909 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9912 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9914 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9917 /* Expand the "prologue" pattern. */
9920 mips_expand_prologue (void)
9922 const struct mips_frame_info *frame;
9927 if (cfun->machine->global_pointer != INVALID_REGNUM)
9929 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
9930 or implicitly. If so, we can commit to using a global pointer
9931 straight away, otherwise we need to defer the decision. */
9932 if (mips_cfun_has_inflexible_gp_ref_p ()
9933 || mips_cfun_has_flexible_gp_ref_p ())
9935 cfun->machine->must_initialize_gp_p = true;
9936 cfun->machine->must_restore_gp_when_clobbered_p = true;
9939 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
9942 frame = &cfun->machine->frame;
9943 size = frame->total_size;
9945 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
9946 bytes beforehand; this is enough to cover the register save area
9947 without going out of range. */
9948 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
9949 || frame->num_cop0_regs > 0)
9951 HOST_WIDE_INT step1;
9953 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
9954 if (GENERATE_MIPS16E_SAVE_RESTORE)
9956 HOST_WIDE_INT offset;
9957 unsigned int mask, regno;
9959 /* Try to merge argument stores into the save instruction. */
9960 nargs = mips16e_collect_argument_saves ();
9962 /* Build the save instruction. */
9964 insn = mips16e_build_save_restore (false, &mask, &offset,
9966 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
9969 /* Check if we need to save other registers. */
9970 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
9971 if (BITSET_P (mask, regno - GP_REG_FIRST))
9973 offset -= UNITS_PER_WORD;
9974 mips_save_restore_reg (word_mode, regno,
9975 offset, mips_save_reg);
9980 if (cfun->machine->interrupt_handler_p)
9982 HOST_WIDE_INT offset;
9985 /* If this interrupt is using a shadow register set, we need to
9986 get the stack pointer from the previous register set. */
9987 if (cfun->machine->use_shadow_register_set_p)
9988 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
9989 stack_pointer_rtx));
9991 if (!cfun->machine->keep_interrupts_masked_p)
9993 /* Move from COP0 Cause to K0. */
9994 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
9995 gen_rtx_REG (SImode,
9996 COP0_CAUSE_REG_NUM)));
9997 /* Move from COP0 EPC to K1. */
9998 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
9999 gen_rtx_REG (SImode,
10000 COP0_EPC_REG_NUM)));
10003 /* Allocate the first part of the frame. */
10004 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10006 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10009 /* Start at the uppermost location for saving. */
10010 offset = frame->cop0_sp_offset - size;
10011 if (!cfun->machine->keep_interrupts_masked_p)
10013 /* Push EPC into its stack slot. */
10014 mem = gen_frame_mem (word_mode,
10015 plus_constant (stack_pointer_rtx,
10017 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10018 offset -= UNITS_PER_WORD;
10021 /* Move from COP0 Status to K1. */
10022 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10023 gen_rtx_REG (SImode,
10024 COP0_STATUS_REG_NUM)));
10026 /* Right justify the RIPL in k0. */
10027 if (!cfun->machine->keep_interrupts_masked_p)
10028 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10029 gen_rtx_REG (SImode, K0_REG_NUM),
10030 GEN_INT (CAUSE_IPL)));
10032 /* Push Status into its stack slot. */
10033 mem = gen_frame_mem (word_mode,
10034 plus_constant (stack_pointer_rtx, offset));
10035 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10036 offset -= UNITS_PER_WORD;
10038 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10039 if (!cfun->machine->keep_interrupts_masked_p)
10040 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10043 gen_rtx_REG (SImode, K0_REG_NUM)));
10045 if (!cfun->machine->keep_interrupts_masked_p)
10046 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10047 IE is already the correct value, so we don't have to do
10048 anything explicit. */
10049 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10052 gen_rtx_REG (SImode, GP_REG_FIRST)));
10054 /* Disable interrupts by clearing the KSU, ERL, EXL,
10056 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10059 gen_rtx_REG (SImode, GP_REG_FIRST)));
10063 insn = gen_add3_insn (stack_pointer_rtx,
10066 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10069 mips_for_each_saved_acc (size, mips_save_reg);
10070 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10074 /* Allocate the rest of the frame. */
10077 if (SMALL_OPERAND (-size))
10078 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10080 GEN_INT (-size)))) = 1;
10083 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10086 /* There are no instructions to add or subtract registers
10087 from the stack pointer, so use the frame pointer as a
10088 temporary. We should always be using a frame pointer
10089 in this case anyway. */
10090 gcc_assert (frame_pointer_needed);
10091 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10092 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10093 hard_frame_pointer_rtx,
10094 MIPS_PROLOGUE_TEMP (Pmode)));
10095 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10098 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10100 MIPS_PROLOGUE_TEMP (Pmode)));
10102 /* Describe the combined effect of the previous instructions. */
10103 mips_set_frame_expr
10104 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10105 plus_constant (stack_pointer_rtx, -size)));
10109 /* Set up the frame pointer, if we're using one. */
10110 if (frame_pointer_needed)
10112 HOST_WIDE_INT offset;
10114 offset = frame->hard_frame_pointer_offset;
10117 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10118 RTX_FRAME_RELATED_P (insn) = 1;
10120 else if (SMALL_OPERAND (offset))
10122 insn = gen_add3_insn (hard_frame_pointer_rtx,
10123 stack_pointer_rtx, GEN_INT (offset));
10124 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10128 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10129 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10130 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10131 hard_frame_pointer_rtx,
10132 MIPS_PROLOGUE_TEMP (Pmode)));
10133 mips_set_frame_expr
10134 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10135 plus_constant (stack_pointer_rtx, offset)));
10139 mips_emit_loadgp ();
10141 /* Initialize the $gp save slot. */
10142 if (mips_cfun_has_cprestore_slot_p ())
10144 rtx base, mem, gp, temp;
10145 HOST_WIDE_INT offset;
10147 mips_get_cprestore_base_and_offset (&base, &offset, false);
10148 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10149 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10150 temp = (SMALL_OPERAND (offset)
10151 ? gen_rtx_SCRATCH (Pmode)
10152 : MIPS_PROLOGUE_TEMP (Pmode));
10153 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10155 mips_get_cprestore_base_and_offset (&base, &offset, true);
10156 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10157 emit_insn (gen_use_cprestore (mem));
10160 /* We need to search back to the last use of K0 or K1. */
10161 if (cfun->machine->interrupt_handler_p)
10163 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10165 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10167 /* Emit a move from K1 to COP0 Status after insn. */
10168 gcc_assert (insn != NULL_RTX);
10169 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10170 gen_rtx_REG (SImode, K1_REG_NUM)),
10174 /* If we are profiling, make sure no instructions are scheduled before
10175 the call to mcount. */
10177 emit_insn (gen_blockage ());
10180 /* Emit instructions to restore register REG from slot MEM. */
10183 mips_restore_reg (rtx reg, rtx mem)
10185 /* There's no MIPS16 instruction to load $31 directly. Load into
10186 $7 instead and adjust the return insn appropriately. */
10187 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10188 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10190 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10193 /* Emit any instructions needed before a return. */
10196 mips_expand_before_return (void)
10198 /* When using a call-clobbered gp, we start out with unified call
10199 insns that include instructions to restore the gp. We then split
10200 these unified calls after reload. These split calls explicitly
10201 clobber gp, so there is no need to define
10202 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10204 For consistency, we should also insert an explicit clobber of $28
10205 before return insns, so that the post-reload optimizers know that
10206 the register is not live on exit. */
10207 if (TARGET_CALL_CLOBBERED_GP)
10208 emit_clobber (pic_offset_table_rtx);
10211 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10215 mips_expand_epilogue (bool sibcall_p)
10217 const struct mips_frame_info *frame;
10218 HOST_WIDE_INT step1, step2;
10219 rtx base, target, insn;
10221 if (!sibcall_p && mips_can_use_return_insn ())
10223 emit_jump_insn (gen_return ());
10227 /* In MIPS16 mode, if the return value should go into a floating-point
10228 register, we need to call a helper routine to copy it over. */
10229 if (mips16_cfun_returns_in_fpr_p ())
10230 mips16_copy_fpr_return_value ();
10232 /* Split the frame into two. STEP1 is the amount of stack we should
10233 deallocate before restoring the registers. STEP2 is the amount we
10234 should deallocate afterwards.
10236 Start off by assuming that no registers need to be restored. */
10237 frame = &cfun->machine->frame;
10238 step1 = frame->total_size;
10241 /* Work out which register holds the frame address. */
10242 if (!frame_pointer_needed)
10243 base = stack_pointer_rtx;
10246 base = hard_frame_pointer_rtx;
10247 step1 -= frame->hard_frame_pointer_offset;
10250 /* If we need to restore registers, deallocate as much stack as
10251 possible in the second step without going out of range. */
10252 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10253 || frame->num_cop0_regs > 0)
10255 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10259 /* Set TARGET to BASE + STEP1. */
10265 /* Get an rtx for STEP1 that we can add to BASE. */
10266 adjust = GEN_INT (step1);
10267 if (!SMALL_OPERAND (step1))
10269 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10270 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10273 /* Normal mode code can copy the result straight into $sp. */
10274 if (!TARGET_MIPS16)
10275 target = stack_pointer_rtx;
10277 emit_insn (gen_add3_insn (target, base, adjust));
10280 /* Copy TARGET into the stack pointer. */
10281 if (target != stack_pointer_rtx)
10282 mips_emit_move (stack_pointer_rtx, target);
10284 /* If we're using addressing macros, $gp is implicitly used by all
10285 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10287 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10288 emit_insn (gen_blockage ());
10290 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10292 unsigned int regno, mask;
10293 HOST_WIDE_INT offset;
10296 /* Generate the restore instruction. */
10297 mask = frame->mask;
10298 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10300 /* Restore any other registers manually. */
10301 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10302 if (BITSET_P (mask, regno - GP_REG_FIRST))
10304 offset -= UNITS_PER_WORD;
10305 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10308 /* Restore the remaining registers and deallocate the final bit
10310 emit_insn (restore);
10314 /* Restore the registers. */
10315 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10316 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10319 if (cfun->machine->interrupt_handler_p)
10321 HOST_WIDE_INT offset;
10324 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10325 if (!cfun->machine->keep_interrupts_masked_p)
10327 /* Restore the original EPC. */
10328 mem = gen_frame_mem (word_mode,
10329 plus_constant (stack_pointer_rtx, offset));
10330 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10331 offset -= UNITS_PER_WORD;
10333 /* Move to COP0 EPC. */
10334 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10335 gen_rtx_REG (SImode, K0_REG_NUM)));
10338 /* Restore the original Status. */
10339 mem = gen_frame_mem (word_mode,
10340 plus_constant (stack_pointer_rtx, offset));
10341 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10342 offset -= UNITS_PER_WORD;
10344 /* If we don't use shoadow register set, we need to update SP. */
10345 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10346 emit_insn (gen_add3_insn (stack_pointer_rtx,
10350 /* Move to COP0 Status. */
10351 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10352 gen_rtx_REG (SImode, K0_REG_NUM)));
10356 /* Deallocate the final bit of the frame. */
10358 emit_insn (gen_add3_insn (stack_pointer_rtx,
10364 /* Add in the __builtin_eh_return stack adjustment. We need to
10365 use a temporary in MIPS16 code. */
10366 if (crtl->calls_eh_return)
10370 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10371 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10372 MIPS_EPILOGUE_TEMP (Pmode),
10373 EH_RETURN_STACKADJ_RTX));
10374 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10377 emit_insn (gen_add3_insn (stack_pointer_rtx,
10379 EH_RETURN_STACKADJ_RTX));
10384 mips_expand_before_return ();
10385 if (cfun->machine->interrupt_handler_p)
10387 /* Interrupt handlers generate eret or deret. */
10388 if (cfun->machine->use_debug_exception_return_p)
10389 emit_jump_insn (gen_mips_deret ());
10391 emit_jump_insn (gen_mips_eret ());
10395 unsigned int regno;
10397 /* When generating MIPS16 code, the normal
10398 mips_for_each_saved_gpr_and_fpr path will restore the return
10399 address into $7 rather than $31. */
10401 && !GENERATE_MIPS16E_SAVE_RESTORE
10402 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10403 regno = GP_REG_FIRST + 7;
10405 regno = RETURN_ADDR_REGNUM;
10406 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10410 /* Search from the beginning to the first use of K0 or K1. */
10411 if (cfun->machine->interrupt_handler_p
10412 && !cfun->machine->keep_interrupts_masked_p)
10414 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10416 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10418 gcc_assert (insn != NULL_RTX);
10419 /* Insert disable interrupts before the first use of K0 or K1. */
10420 emit_insn_before (gen_mips_di (), insn);
10421 emit_insn_before (gen_mips_ehb (), insn);
10425 /* Return nonzero if this function is known to have a null epilogue.
10426 This allows the optimizer to omit jumps to jumps if no stack
10430 mips_can_use_return_insn (void)
10432 /* Interrupt handlers need to go through the epilogue. */
10433 if (cfun->machine->interrupt_handler_p)
10436 if (!reload_completed)
10442 /* In MIPS16 mode, a function that returns a floating-point value
10443 needs to arrange to copy the return value into the floating-point
10445 if (mips16_cfun_returns_in_fpr_p ())
10448 return cfun->machine->frame.total_size == 0;
10451 /* Return true if register REGNO can store a value of mode MODE.
10452 The result of this function is cached in mips_hard_regno_mode_ok. */
10455 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10458 enum mode_class mclass;
10460 if (mode == CCV2mode)
10461 return (ISA_HAS_8CC
10462 && ST_REG_P (regno)
10463 && (regno - ST_REG_FIRST) % 2 == 0);
10465 if (mode == CCV4mode)
10466 return (ISA_HAS_8CC
10467 && ST_REG_P (regno)
10468 && (regno - ST_REG_FIRST) % 4 == 0);
10470 if (mode == CCmode)
10473 return regno == FPSW_REGNUM;
10475 return (ST_REG_P (regno)
10476 || GP_REG_P (regno)
10477 || FP_REG_P (regno));
10480 size = GET_MODE_SIZE (mode);
10481 mclass = GET_MODE_CLASS (mode);
10483 if (GP_REG_P (regno))
10484 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10486 if (FP_REG_P (regno)
10487 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10488 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10490 /* Allow TFmode for CCmode reloads. */
10491 if (mode == TFmode && ISA_HAS_8CC)
10494 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10495 if (TARGET_LOONGSON_VECTORS
10496 && (mode == V2SImode
10497 || mode == V4HImode
10498 || mode == V8QImode
10499 || mode == DImode))
10502 if (mclass == MODE_FLOAT
10503 || mclass == MODE_COMPLEX_FLOAT
10504 || mclass == MODE_VECTOR_FLOAT)
10505 return size <= UNITS_PER_FPVALUE;
10507 /* Allow integer modes that fit into a single register. We need
10508 to put integers into FPRs when using instructions like CVT
10509 and TRUNC. There's no point allowing sizes smaller than a word,
10510 because the FPU has no appropriate load/store instructions. */
10511 if (mclass == MODE_INT)
10512 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10515 if (ACC_REG_P (regno)
10516 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10518 if (MD_REG_P (regno))
10520 /* After a multiplication or division, clobbering HI makes
10521 the value of LO unpredictable, and vice versa. This means
10522 that, for all interesting cases, HI and LO are effectively
10525 We model this by requiring that any value that uses HI
10527 if (size <= UNITS_PER_WORD * 2)
10528 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10532 /* DSP accumulators do not have the same restrictions as
10533 HI and LO, so we can treat them as normal doubleword
10535 if (size <= UNITS_PER_WORD)
10538 if (size <= UNITS_PER_WORD * 2
10539 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10544 if (ALL_COP_REG_P (regno))
10545 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10547 if (regno == GOT_VERSION_REGNUM)
10548 return mode == SImode;
10553 /* Implement HARD_REGNO_NREGS. */
10556 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10558 if (ST_REG_P (regno))
10559 /* The size of FP status registers is always 4, because they only hold
10560 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10561 return (GET_MODE_SIZE (mode) + 3) / 4;
10563 if (FP_REG_P (regno))
10564 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10566 /* All other registers are word-sized. */
10567 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10570 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10571 in mips_hard_regno_nregs. */
10574 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10580 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10581 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10583 size = MIN (size, 4);
10584 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10586 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10588 size = MIN (size, UNITS_PER_FPREG);
10589 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10591 if (!hard_reg_set_empty_p (left))
10592 size = MIN (size, UNITS_PER_WORD);
10593 return (GET_MODE_SIZE (mode) + size - 1) / size;
10596 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10599 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10600 enum machine_mode to ATTRIBUTE_UNUSED,
10601 enum reg_class rclass)
10603 /* There are several problems with changing the modes of values
10604 in floating-point registers:
10606 - When a multi-word value is stored in paired floating-point
10607 registers, the first register always holds the low word.
10608 We therefore can't allow FPRs to change between single-word
10609 and multi-word modes on big-endian targets.
10611 - GCC assumes that each word of a multiword register can be accessed
10612 individually using SUBREGs. This is not true for floating-point
10613 registers if they are bigger than a word.
10615 - Loading a 32-bit value into a 64-bit floating-point register
10616 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10617 We can't allow FPRs to change from SImode to to a wider mode on
10620 - If the FPU has already interpreted a value in one format, we must
10621 not ask it to treat the value as having a different format.
10623 We therefore disallow all mode changes involving FPRs. */
10624 return reg_classes_intersect_p (FP_REGS, rclass);
10627 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10630 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10635 return TARGET_HARD_FLOAT;
10638 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10641 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10648 /* Implement MODES_TIEABLE_P. */
10651 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10653 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10654 prefer to put one of them in FPRs. */
10655 return (mode1 == mode2
10656 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10657 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10660 /* Implement PREFERRED_RELOAD_CLASS. */
10663 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10665 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10668 if (reg_class_subset_p (FP_REGS, rclass)
10669 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10672 if (reg_class_subset_p (GR_REGS, rclass))
10675 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10681 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10682 Return a "canonical" class to represent it in later calculations. */
10684 static enum reg_class
10685 mips_canonicalize_move_class (enum reg_class rclass)
10687 /* All moves involving accumulator registers have the same cost. */
10688 if (reg_class_subset_p (rclass, ACC_REGS))
10691 /* Likewise promote subclasses of general registers to the most
10692 interesting containing class. */
10693 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10695 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10696 rclass = GENERAL_REGS;
10701 /* Return the cost of moving a value of mode MODE from a register of
10702 class FROM to a GPR. Return 0 for classes that are unions of other
10703 classes handled by this function. */
10706 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10707 enum reg_class from)
10712 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10716 /* MFLO and MFHI. */
10724 /* LUI followed by MOVF. */
10730 /* This choice of value is historical. */
10738 /* Return the cost of moving a value of mode MODE from a GPR to a
10739 register of class TO. Return 0 for classes that are unions of
10740 other classes handled by this function. */
10743 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10748 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10752 /* MTLO and MTHI. */
10760 /* A secondary reload through an FPR scratch. */
10761 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10762 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10767 /* This choice of value is historical. */
10775 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10776 maximum of the move costs for subclasses; regclass will work out
10777 the maximum for us. */
10780 mips_register_move_cost (enum machine_mode mode,
10781 enum reg_class from, enum reg_class to)
10783 enum reg_class dregs;
10786 from = mips_canonicalize_move_class (from);
10787 to = mips_canonicalize_move_class (to);
10789 /* Handle moves that can be done without using general-purpose registers. */
10790 if (from == FP_REGS)
10792 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10796 /* The sequence generated by mips_expand_fcc_reload. */
10800 /* Handle cases in which only one class deviates from the ideal. */
10801 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10803 return mips_move_from_gpr_cost (mode, to);
10805 return mips_move_to_gpr_cost (mode, from);
10807 /* Handles cases that require a GPR temporary. */
10808 cost1 = mips_move_to_gpr_cost (mode, from);
10811 cost2 = mips_move_from_gpr_cost (mode, to);
10813 return cost1 + cost2;
10819 /* Implement TARGET_IRA_COVER_CLASSES. */
10821 static const enum reg_class *
10822 mips_ira_cover_classes (void)
10824 static const enum reg_class acc_classes[] = {
10825 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10826 ST_REGS, LIM_REG_CLASSES
10828 static const enum reg_class no_acc_classes[] = {
10829 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10830 ST_REGS, LIM_REG_CLASSES
10833 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10834 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10835 as a cover class only works well when we keep per-register costs.
10836 Using it when not optimizing can cause us to think accumulators
10837 have the same cost as GPRs in cases where GPRs are actually much
10839 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10842 /* Return the register class required for a secondary register when
10843 copying between one of the registers in RCLASS and value X, which
10844 has mode MODE. X is the source of the move if IN_P, otherwise it
10845 is the destination. Return NO_REGS if no secondary register is
10849 mips_secondary_reload_class (enum reg_class rclass,
10850 enum machine_mode mode, rtx x, bool in_p)
10854 /* If X is a constant that cannot be loaded into $25, it must be loaded
10855 into some other GPR. No other register class allows a direct move. */
10856 if (mips_dangerous_for_la25_p (x))
10857 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10859 regno = true_regnum (x);
10862 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10863 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10869 /* Copying from accumulator registers to anywhere other than a general
10870 register requires a temporary general register. */
10871 if (reg_class_subset_p (rclass, ACC_REGS))
10872 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10873 if (ACC_REG_P (regno))
10874 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10876 /* We can only copy a value to a condition code register from a
10877 floating-point register, and even then we require a scratch
10878 floating-point register. We can only copy a value out of a
10879 condition-code register into a general register. */
10880 if (reg_class_subset_p (rclass, ST_REGS))
10884 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10886 if (ST_REG_P (regno))
10890 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10893 if (reg_class_subset_p (rclass, FP_REGS))
10896 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10897 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10898 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10901 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10902 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10905 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
10906 /* We can force the constant to memory and use lwc1
10907 and ldc1. As above, we will use pairs of lwc1s if
10908 ldc1 is not supported. */
10911 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10912 /* In this case we can use mov.fmt. */
10915 /* Otherwise, we need to reload through an integer register. */
10918 if (FP_REG_P (regno))
10919 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10924 /* Implement TARGET_MODE_REP_EXTENDED. */
10927 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10929 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
10930 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10931 return SIGN_EXTEND;
10936 /* Implement TARGET_VALID_POINTER_MODE. */
10939 mips_valid_pointer_mode (enum machine_mode mode)
10941 return mode == SImode || (TARGET_64BIT && mode == DImode);
10944 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10947 mips_vector_mode_supported_p (enum machine_mode mode)
10952 return TARGET_PAIRED_SINGLE_FLOAT;
10967 return TARGET_LOONGSON_VECTORS;
10974 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10977 mips_scalar_mode_supported_p (enum machine_mode mode)
10979 if (ALL_FIXED_POINT_MODE_P (mode)
10980 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
10983 return default_scalar_mode_supported_p (mode);
10986 /* Implement TARGET_INIT_LIBFUNCS. */
10988 #include "config/gofast.h"
10991 mips_init_libfuncs (void)
10993 if (TARGET_FIX_VR4120)
10995 /* Register the special divsi3 and modsi3 functions needed to work
10996 around VR4120 division errata. */
10997 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
10998 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11001 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11003 /* Register the MIPS16 -mhard-float stubs. */
11004 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11005 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11006 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11007 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11009 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11010 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11011 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11012 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11013 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11014 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11015 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11017 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11018 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11019 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11021 if (TARGET_DOUBLE_FLOAT)
11023 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11024 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11025 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11026 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11028 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11029 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11030 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11031 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11032 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11033 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11034 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11036 set_conv_libfunc (sext_optab, DFmode, SFmode,
11037 "__mips16_extendsfdf2");
11038 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11039 "__mips16_truncdfsf2");
11040 set_conv_libfunc (sfix_optab, SImode, DFmode,
11041 "__mips16_fix_truncdfsi");
11042 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11043 "__mips16_floatsidf");
11044 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11045 "__mips16_floatunsidf");
11049 /* Register the gofast functions if selected using --enable-gofast. */
11050 gofast_maybe_init_libfuncs ();
11052 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11053 on an external non-MIPS16 routine to implement __sync_synchronize. */
11055 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11058 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11061 mips_process_load_label (rtx target)
11063 rtx base, gp, intop;
11064 HOST_WIDE_INT offset;
11066 mips_multi_start ();
11070 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11071 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11075 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11076 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11080 gp = pic_offset_table_rtx;
11081 if (mips_cfun_has_cprestore_slot_p ())
11083 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11084 mips_get_cprestore_base_and_offset (&base, &offset, true);
11085 if (!SMALL_OPERAND (offset))
11087 intop = GEN_INT (CONST_HIGH_PART (offset));
11088 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11089 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11092 offset = CONST_LOW_PART (offset);
11094 intop = GEN_INT (offset);
11095 if (ISA_HAS_LOAD_DELAY)
11096 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11098 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11100 if (ISA_HAS_LOAD_DELAY)
11101 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11103 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11104 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11109 /* Return the number of instructions needed to load a label into $AT. */
11111 static unsigned int
11112 mips_load_label_length (void)
11114 if (cfun->machine->load_label_length == 0)
11116 mips_process_load_label (pc_rtx);
11117 cfun->machine->load_label_length = mips_multi_num_insns;
11119 return cfun->machine->load_label_length;
11122 /* Emit an asm sequence to start a noat block and load the address
11123 of a label into $1. */
11126 mips_output_load_label (rtx target)
11128 mips_push_asm_switch (&mips_noat);
11129 if (TARGET_EXPLICIT_RELOCS)
11131 mips_process_load_label (target);
11132 mips_multi_write ();
11136 if (Pmode == DImode)
11137 output_asm_insn ("dla\t%@,%0", &target);
11139 output_asm_insn ("la\t%@,%0", &target);
11143 /* Return the length of INSN. LENGTH is the initial length computed by
11144 attributes in the machine-description file. */
11147 mips_adjust_insn_length (rtx insn, int length)
11149 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11150 of a PIC long-branch sequence. Substitute the correct value. */
11151 if (length == MAX_PIC_BRANCH_LENGTH
11152 && INSN_CODE (insn) >= 0
11153 && get_attr_type (insn) == TYPE_BRANCH)
11155 /* Add the branch-over instruction and its delay slot, if this
11156 is a conditional branch. */
11157 length = simplejump_p (insn) ? 0 : 8;
11159 /* Load the label into $AT and jump to it. Ignore the delay
11160 slot of the jump. */
11161 length += mips_load_label_length () + 4;
11164 /* A unconditional jump has an unfilled delay slot if it is not part
11165 of a sequence. A conditional jump normally has a delay slot, but
11166 does not on MIPS16. */
11167 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11170 /* See how many nops might be needed to avoid hardware hazards. */
11171 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11172 switch (get_attr_hazard (insn))
11186 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11187 the .md file length attributes are 4-based for both modes.
11188 Adjust the MIPS16 ones here. */
11195 /* Return the assembly code for INSN, which has the operands given by
11196 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11197 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11198 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11199 version of BRANCH_IF_TRUE. */
11202 mips_output_conditional_branch (rtx insn, rtx *operands,
11203 const char *branch_if_true,
11204 const char *branch_if_false)
11206 unsigned int length;
11207 rtx taken, not_taken;
11209 gcc_assert (LABEL_P (operands[0]));
11211 length = get_attr_length (insn);
11214 /* Just a simple conditional branch. */
11215 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11216 return branch_if_true;
11219 /* Generate a reversed branch around a direct jump. This fallback does
11220 not use branch-likely instructions. */
11221 mips_branch_likely = false;
11222 not_taken = gen_label_rtx ();
11223 taken = operands[0];
11225 /* Generate the reversed branch to NOT_TAKEN. */
11226 operands[0] = not_taken;
11227 output_asm_insn (branch_if_false, operands);
11229 /* If INSN has a delay slot, we must provide delay slots for both the
11230 branch to NOT_TAKEN and the conditional jump. We must also ensure
11231 that INSN's delay slot is executed in the appropriate cases. */
11232 if (final_sequence)
11234 /* This first delay slot will always be executed, so use INSN's
11235 delay slot if is not annulled. */
11236 if (!INSN_ANNULLED_BRANCH_P (insn))
11238 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11239 asm_out_file, optimize, 1, NULL);
11240 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11243 output_asm_insn ("nop", 0);
11244 fprintf (asm_out_file, "\n");
11247 /* Output the unconditional branch to TAKEN. */
11248 if (TARGET_ABSOLUTE_JUMPS)
11249 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11252 mips_output_load_label (taken);
11253 output_asm_insn ("jr\t%@%]%/", 0);
11256 /* Now deal with its delay slot; see above. */
11257 if (final_sequence)
11259 /* This delay slot will only be executed if the branch is taken.
11260 Use INSN's delay slot if is annulled. */
11261 if (INSN_ANNULLED_BRANCH_P (insn))
11263 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11264 asm_out_file, optimize, 1, NULL);
11265 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11268 output_asm_insn ("nop", 0);
11269 fprintf (asm_out_file, "\n");
11272 /* Output NOT_TAKEN. */
11273 targetm.asm_out.internal_label (asm_out_file, "L",
11274 CODE_LABEL_NUMBER (not_taken));
11278 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11279 if some ordering condition is true. The condition is given by
11280 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11281 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11282 its second is always zero. */
11285 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11287 const char *branch[2];
11289 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11290 Make BRANCH[0] branch on the inverse condition. */
11291 switch (GET_CODE (operands[1]))
11293 /* These cases are equivalent to comparisons against zero. */
11295 inverted_p = !inverted_p;
11296 /* Fall through. */
11298 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11299 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11302 /* These cases are always true or always false. */
11304 inverted_p = !inverted_p;
11305 /* Fall through. */
11307 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11308 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11312 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11313 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11316 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11319 /* Start a block of code that needs access to the LL, SC and SYNC
11323 mips_start_ll_sc_sync_block (void)
11325 if (!ISA_HAS_LL_SC)
11327 output_asm_insn (".set\tpush", 0);
11328 output_asm_insn (".set\tmips2", 0);
11332 /* End a block started by mips_start_ll_sc_sync_block. */
11335 mips_end_ll_sc_sync_block (void)
11337 if (!ISA_HAS_LL_SC)
11338 output_asm_insn (".set\tpop", 0);
11341 /* Output and/or return the asm template for a sync instruction. */
11344 mips_output_sync (void)
11346 mips_start_ll_sc_sync_block ();
11347 output_asm_insn ("sync", 0);
11348 mips_end_ll_sc_sync_block ();
11352 /* Return the asm template associated with sync_insn1 value TYPE.
11353 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11355 static const char *
11356 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11360 case SYNC_INSN1_MOVE:
11361 return "move\t%0,%z2";
11362 case SYNC_INSN1_LI:
11363 return "li\t%0,%2";
11364 case SYNC_INSN1_ADDU:
11365 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11366 case SYNC_INSN1_ADDIU:
11367 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11368 case SYNC_INSN1_SUBU:
11369 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11370 case SYNC_INSN1_AND:
11371 return "and\t%0,%1,%z2";
11372 case SYNC_INSN1_ANDI:
11373 return "andi\t%0,%1,%2";
11374 case SYNC_INSN1_OR:
11375 return "or\t%0,%1,%z2";
11376 case SYNC_INSN1_ORI:
11377 return "ori\t%0,%1,%2";
11378 case SYNC_INSN1_XOR:
11379 return "xor\t%0,%1,%z2";
11380 case SYNC_INSN1_XORI:
11381 return "xori\t%0,%1,%2";
11383 gcc_unreachable ();
11386 /* Return the asm template associated with sync_insn2 value TYPE. */
11388 static const char *
11389 mips_sync_insn2_template (enum attr_sync_insn2 type)
11393 case SYNC_INSN2_NOP:
11394 gcc_unreachable ();
11395 case SYNC_INSN2_AND:
11396 return "and\t%0,%1,%z2";
11397 case SYNC_INSN2_XOR:
11398 return "xor\t%0,%1,%z2";
11399 case SYNC_INSN2_NOT:
11400 return "nor\t%0,%1,%.";
11402 gcc_unreachable ();
11405 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11406 the value of the one of the sync_* attributes. Return the operand
11407 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11408 have the associated attribute. */
11411 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11414 default_value = operands[index - 1];
11415 return default_value;
11418 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11419 sequence for it. */
11422 mips_process_sync_loop (rtx insn, rtx *operands)
11424 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11425 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11426 unsigned int tmp3_insn;
11427 enum attr_sync_insn1 insn1;
11428 enum attr_sync_insn2 insn2;
11431 /* Read an operand from the sync_WHAT attribute and store it in
11432 variable WHAT. DEFAULT is the default value if no attribute
11434 #define READ_OPERAND(WHAT, DEFAULT) \
11435 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11438 /* Read the memory. */
11439 READ_OPERAND (mem, 0);
11441 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11443 /* Read the other attributes. */
11444 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11445 READ_OPERAND (oldval, at);
11446 READ_OPERAND (newval, at);
11447 READ_OPERAND (inclusive_mask, 0);
11448 READ_OPERAND (exclusive_mask, 0);
11449 READ_OPERAND (required_oldval, 0);
11450 READ_OPERAND (insn1_op2, 0);
11451 insn1 = get_attr_sync_insn1 (insn);
11452 insn2 = get_attr_sync_insn2 (insn);
11454 mips_multi_start ();
11456 /* Output the release side of the memory barrier. */
11457 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11459 if (required_oldval == 0 && TARGET_OCTEON)
11461 /* Octeon doesn't reorder reads, so a full barrier can be
11462 created by using SYNCW to order writes combined with the
11463 write from the following SC. When the SC successfully
11464 completes, we know that all preceding writes are also
11465 committed to the coherent memory system. It is possible
11466 for a single SYNCW to fail, but a pair of them will never
11467 fail, so we use two. */
11468 mips_multi_add_insn ("syncw", NULL);
11469 mips_multi_add_insn ("syncw", NULL);
11472 mips_multi_add_insn ("sync", NULL);
11475 /* Output the branch-back label. */
11476 mips_multi_add_label ("1:");
11478 /* OLDVAL = *MEM. */
11479 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11480 oldval, mem, NULL);
11482 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11483 if (required_oldval)
11485 if (inclusive_mask == 0)
11489 gcc_assert (oldval != at);
11490 mips_multi_add_insn ("and\t%0,%1,%2",
11491 at, oldval, inclusive_mask, NULL);
11494 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11497 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11498 if (exclusive_mask == 0)
11502 gcc_assert (oldval != at);
11503 mips_multi_add_insn ("and\t%0,%1,%z2",
11504 at, oldval, exclusive_mask, NULL);
11508 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11510 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11511 at least one instruction in that case. */
11512 if (insn1 == SYNC_INSN1_MOVE
11513 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11517 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11518 newval, oldval, insn1_op2, NULL);
11522 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11523 if (insn2 == SYNC_INSN2_NOP)
11527 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11528 newval, tmp2, inclusive_mask, NULL);
11531 tmp3_insn = mips_multi_last_index ();
11533 /* $AT = $TMP1 | $TMP3. */
11534 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11536 mips_multi_set_operand (tmp3_insn, 0, at);
11541 gcc_assert (tmp1 != tmp3);
11542 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11545 /* if (!commit (*MEM = $AT)) goto 1.
11547 This will sometimes be a delayed branch; see the write code below
11549 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11550 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11552 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11553 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11555 mips_multi_copy_insn (tmp3_insn);
11556 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11559 mips_multi_add_insn ("nop", NULL);
11561 /* Output the acquire side of the memory barrier. */
11562 if (TARGET_SYNC_AFTER_SC)
11563 mips_multi_add_insn ("sync", NULL);
11565 /* Output the exit label, if needed. */
11566 if (required_oldval)
11567 mips_multi_add_label ("2:");
11569 #undef READ_OPERAND
11572 /* Output and/or return the asm template for sync loop INSN, which has
11573 the operands given by OPERANDS. */
11576 mips_output_sync_loop (rtx insn, rtx *operands)
11578 mips_process_sync_loop (insn, operands);
11580 /* Use branch-likely instructions to work around the LL/SC R10000
11582 mips_branch_likely = TARGET_FIX_R10000;
11584 mips_push_asm_switch (&mips_noreorder);
11585 mips_push_asm_switch (&mips_nomacro);
11586 mips_push_asm_switch (&mips_noat);
11587 mips_start_ll_sc_sync_block ();
11589 mips_multi_write ();
11591 mips_end_ll_sc_sync_block ();
11592 mips_pop_asm_switch (&mips_noat);
11593 mips_pop_asm_switch (&mips_nomacro);
11594 mips_pop_asm_switch (&mips_noreorder);
11599 /* Return the number of individual instructions in sync loop INSN,
11600 which has the operands given by OPERANDS. */
11603 mips_sync_loop_insns (rtx insn, rtx *operands)
11605 mips_process_sync_loop (insn, operands);
11606 return mips_multi_num_insns;
11609 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11610 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11612 When working around R4000 and R4400 errata, we need to make sure that
11613 the division is not immediately followed by a shift[1][2]. We also
11614 need to stop the division from being put into a branch delay slot[3].
11615 The easiest way to avoid both problems is to add a nop after the
11616 division. When a divide-by-zero check is needed, this nop can be
11617 used to fill the branch delay slot.
11619 [1] If a double-word or a variable shift executes immediately
11620 after starting an integer division, the shift may give an
11621 incorrect result. See quotations of errata #16 and #28 from
11622 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11623 in mips.md for details.
11625 [2] A similar bug to [1] exists for all revisions of the
11626 R4000 and the R4400 when run in an MC configuration.
11627 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11629 "19. In this following sequence:
11631 ddiv (or ddivu or div or divu)
11632 dsll32 (or dsrl32, dsra32)
11634 if an MPT stall occurs, while the divide is slipping the cpu
11635 pipeline, then the following double shift would end up with an
11638 Workaround: The compiler needs to avoid generating any
11639 sequence with divide followed by extended double shift."
11641 This erratum is also present in "MIPS R4400MC Errata, Processor
11642 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11643 & 3.0" as errata #10 and #4, respectively.
11645 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11646 (also valid for MIPS R4000MC processors):
11648 "52. R4000SC: This bug does not apply for the R4000PC.
11650 There are two flavors of this bug:
11652 1) If the instruction just after divide takes an RF exception
11653 (tlb-refill, tlb-invalid) and gets an instruction cache
11654 miss (both primary and secondary) and the line which is
11655 currently in secondary cache at this index had the first
11656 data word, where the bits 5..2 are set, then R4000 would
11657 get a wrong result for the div.
11662 ------------------- # end-of page. -tlb-refill
11667 ------------------- # end-of page. -tlb-invalid
11670 2) If the divide is in the taken branch delay slot, where the
11671 target takes RF exception and gets an I-cache miss for the
11672 exception vector or where I-cache miss occurs for the
11673 target address, under the above mentioned scenarios, the
11674 div would get wrong results.
11677 j r2 # to next page mapped or unmapped
11678 div r8,r9 # this bug would be there as long
11679 # as there is an ICache miss and
11680 nop # the "data pattern" is present
11683 beq r0, r0, NextPage # to Next page
11687 This bug is present for div, divu, ddiv, and ddivu
11690 Workaround: For item 1), OS could make sure that the next page
11691 after the divide instruction is also mapped. For item 2), the
11692 compiler could make sure that the divide instruction is not in
11693 the branch delay slot."
11695 These processors have PRId values of 0x00004220 and 0x00004300 for
11696 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11699 mips_output_division (const char *division, rtx *operands)
11704 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11706 output_asm_insn (s, operands);
11709 if (TARGET_CHECK_ZERO_DIV)
11713 output_asm_insn (s, operands);
11714 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11716 else if (GENERATE_DIVIDE_TRAPS)
11718 output_asm_insn (s, operands);
11719 s = "teq\t%2,%.,7";
11723 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11724 output_asm_insn (s, operands);
11725 s = "break\t7%)\n1:";
11731 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11732 instruction and if OUT_INSN assigns to the accumulator operand. */
11735 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11739 x = single_set (in_insn);
11745 if (GET_CODE (x) == PLUS
11746 && GET_CODE (XEXP (x, 0)) == MULT
11747 && reg_set_p (XEXP (x, 1), out_insn))
11750 if (GET_CODE (x) == MINUS
11751 && GET_CODE (XEXP (x, 1)) == MULT
11752 && reg_set_p (XEXP (x, 0), out_insn))
11758 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11759 data rather than the address. We need this because the cprestore
11760 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11761 which causes the default routine to abort. We just return false
11765 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11767 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11770 return !store_data_bypass_p (out_insn, in_insn);
11774 /* Variables and flags used in scheduler hooks when tuning for
11778 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11781 /* If true, then next ALU1/2 instruction will go to ALU1. */
11784 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11787 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11788 int alu1_core_unit_code;
11789 int alu2_core_unit_code;
11790 int falu1_core_unit_code;
11791 int falu2_core_unit_code;
11793 /* True if current cycle has a multi instruction.
11794 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11795 bool cycle_has_multi_p;
11797 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11798 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11800 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11801 instruction to go ALU1. */
11802 rtx alu1_turn_enabled_insn;
11803 rtx alu2_turn_enabled_insn;
11804 rtx falu1_turn_enabled_insn;
11805 rtx falu2_turn_enabled_insn;
11808 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11809 dependencies have no cost, except on the 20Kc where output-dependence
11810 is treated like input-dependence. */
11813 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11814 rtx dep ATTRIBUTE_UNUSED, int cost)
11816 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11819 if (REG_NOTE_KIND (link) != 0)
11824 /* Return the number of instructions that can be issued per cycle. */
11827 mips_issue_rate (void)
11831 case PROCESSOR_74KC:
11832 case PROCESSOR_74KF2_1:
11833 case PROCESSOR_74KF1_1:
11834 case PROCESSOR_74KF3_2:
11835 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11836 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11837 but in reality only a maximum of 3 insns can be issued as
11838 floating-point loads and stores also require a slot in the
11840 case PROCESSOR_R10000:
11841 /* All R10K Processors are quad-issue (being the first MIPS
11842 processors to support this feature). */
11845 case PROCESSOR_20KC:
11846 case PROCESSOR_R4130:
11847 case PROCESSOR_R5400:
11848 case PROCESSOR_R5500:
11849 case PROCESSOR_R7000:
11850 case PROCESSOR_R9000:
11851 case PROCESSOR_OCTEON:
11854 case PROCESSOR_SB1:
11855 case PROCESSOR_SB1A:
11856 /* This is actually 4, but we get better performance if we claim 3.
11857 This is partly because of unwanted speculative code motion with the
11858 larger number, and partly because in most common cases we can't
11859 reach the theoretical max of 4. */
11862 case PROCESSOR_LOONGSON_2E:
11863 case PROCESSOR_LOONGSON_2F:
11871 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11874 mips_ls2_init_dfa_post_cycle_insn (void)
11877 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11878 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11882 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11883 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11887 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11888 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11892 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11893 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11896 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11897 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11898 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11899 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11902 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11903 Init data used in mips_dfa_post_advance_cycle. */
11906 mips_init_dfa_post_cycle_insn (void)
11908 if (TUNE_LOONGSON_2EF)
11909 mips_ls2_init_dfa_post_cycle_insn ();
11912 /* Initialize STATE when scheduling for Loongson 2E/2F.
11913 Support round-robin dispatch scheme by enabling only one of
11914 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
11918 mips_ls2_dfa_post_advance_cycle (state_t state)
11920 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
11922 /* Though there are no non-pipelined ALU1 insns,
11923 we can get an instruction of type 'multi' before reload. */
11924 gcc_assert (mips_ls2.cycle_has_multi_p);
11925 mips_ls2.alu1_turn_p = false;
11928 mips_ls2.cycle_has_multi_p = false;
11930 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
11931 /* We have a non-pipelined alu instruction in the core,
11932 adjust round-robin counter. */
11933 mips_ls2.alu1_turn_p = true;
11935 if (mips_ls2.alu1_turn_p)
11937 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
11938 gcc_unreachable ();
11942 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
11943 gcc_unreachable ();
11946 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
11948 /* There are no non-pipelined FALU1 insns. */
11949 gcc_unreachable ();
11950 mips_ls2.falu1_turn_p = false;
11953 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
11954 /* We have a non-pipelined falu instruction in the core,
11955 adjust round-robin counter. */
11956 mips_ls2.falu1_turn_p = true;
11958 if (mips_ls2.falu1_turn_p)
11960 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
11961 gcc_unreachable ();
11965 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
11966 gcc_unreachable ();
11970 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
11971 This hook is being called at the start of each cycle. */
11974 mips_dfa_post_advance_cycle (void)
11976 if (TUNE_LOONGSON_2EF)
11977 mips_ls2_dfa_post_advance_cycle (curr_state);
11980 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
11981 be as wide as the scheduling freedom in the DFA. */
11984 mips_multipass_dfa_lookahead (void)
11986 /* Can schedule up to 4 of the 6 function units in any one cycle. */
11990 if (TUNE_LOONGSON_2EF)
11999 /* Remove the instruction at index LOWER from ready queue READY and
12000 reinsert it in front of the instruction at index HIGHER. LOWER must
12004 mips_promote_ready (rtx *ready, int lower, int higher)
12009 new_head = ready[lower];
12010 for (i = lower; i < higher; i++)
12011 ready[i] = ready[i + 1];
12012 ready[i] = new_head;
12015 /* If the priority of the instruction at POS2 in the ready queue READY
12016 is within LIMIT units of that of the instruction at POS1, swap the
12017 instructions if POS2 is not already less than POS1. */
12020 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12023 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12027 temp = ready[pos1];
12028 ready[pos1] = ready[pos2];
12029 ready[pos2] = temp;
12033 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12034 that may clobber hi or lo. */
12035 static rtx mips_macc_chains_last_hilo;
12037 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12038 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12041 mips_macc_chains_record (rtx insn)
12043 if (get_attr_may_clobber_hilo (insn))
12044 mips_macc_chains_last_hilo = insn;
12047 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12048 has NREADY elements, looking for a multiply-add or multiply-subtract
12049 instruction that is cumulative with mips_macc_chains_last_hilo.
12050 If there is one, promote it ahead of anything else that might
12051 clobber hi or lo. */
12054 mips_macc_chains_reorder (rtx *ready, int nready)
12058 if (mips_macc_chains_last_hilo != 0)
12059 for (i = nready - 1; i >= 0; i--)
12060 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12062 for (j = nready - 1; j > i; j--)
12063 if (recog_memoized (ready[j]) >= 0
12064 && get_attr_may_clobber_hilo (ready[j]))
12066 mips_promote_ready (ready, i, j);
12073 /* The last instruction to be scheduled. */
12074 static rtx vr4130_last_insn;
12076 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12077 points to an rtx that is initially an instruction. Nullify the rtx
12078 if the instruction uses the value of register X. */
12081 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12086 insn_ptr = (rtx *) data;
12089 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12093 /* Return true if there is true register dependence between vr4130_last_insn
12097 vr4130_true_reg_dependence_p (rtx insn)
12099 note_stores (PATTERN (vr4130_last_insn),
12100 vr4130_true_reg_dependence_p_1, &insn);
12104 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12105 the ready queue and that INSN2 is the instruction after it, return
12106 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12107 in which INSN1 and INSN2 can probably issue in parallel, but for
12108 which (INSN2, INSN1) should be less sensitive to instruction
12109 alignment than (INSN1, INSN2). See 4130.md for more details. */
12112 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12114 sd_iterator_def sd_it;
12117 /* Check for the following case:
12119 1) there is some other instruction X with an anti dependence on INSN1;
12120 2) X has a higher priority than INSN2; and
12121 3) X is an arithmetic instruction (and thus has no unit restrictions).
12123 If INSN1 is the last instruction blocking X, it would better to
12124 choose (INSN1, X) over (INSN2, INSN1). */
12125 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12126 if (DEP_TYPE (dep) == REG_DEP_ANTI
12127 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12128 && recog_memoized (DEP_CON (dep)) >= 0
12129 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12132 if (vr4130_last_insn != 0
12133 && recog_memoized (insn1) >= 0
12134 && recog_memoized (insn2) >= 0)
12136 /* See whether INSN1 and INSN2 use different execution units,
12137 or if they are both ALU-type instructions. If so, they can
12138 probably execute in parallel. */
12139 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12140 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12141 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12143 /* If only one of the instructions has a dependence on
12144 vr4130_last_insn, prefer to schedule the other one first. */
12145 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12146 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12147 if (dep1_p != dep2_p)
12150 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12151 is not an ALU-type instruction and if INSN1 uses the same
12152 execution unit. (Note that if this condition holds, we already
12153 know that INSN2 uses a different execution unit.) */
12154 if (class1 != VR4130_CLASS_ALU
12155 && recog_memoized (vr4130_last_insn) >= 0
12156 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12163 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12164 queue with at least two instructions. Swap the first two if
12165 vr4130_swap_insns_p says that it could be worthwhile. */
12168 vr4130_reorder (rtx *ready, int nready)
12170 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12171 mips_promote_ready (ready, nready - 2, nready - 1);
12174 /* Record whether last 74k AGEN instruction was a load or store. */
12175 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12177 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12178 resets to TYPE_UNKNOWN state. */
12181 mips_74k_agen_init (rtx insn)
12183 if (!insn || CALL_P (insn) || JUMP_P (insn))
12184 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12187 enum attr_type type = get_attr_type (insn);
12188 if (type == TYPE_LOAD || type == TYPE_STORE)
12189 mips_last_74k_agen_insn = type;
12193 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12194 loads to be grouped together, and multiple stores to be grouped
12195 together. Swap things around in the ready queue to make this happen. */
12198 mips_74k_agen_reorder (rtx *ready, int nready)
12201 int store_pos, load_pos;
12206 for (i = nready - 1; i >= 0; i--)
12208 rtx insn = ready[i];
12209 if (USEFUL_INSN_P (insn))
12210 switch (get_attr_type (insn))
12213 if (store_pos == -1)
12218 if (load_pos == -1)
12227 if (load_pos == -1 || store_pos == -1)
12230 switch (mips_last_74k_agen_insn)
12233 /* Prefer to schedule loads since they have a higher latency. */
12235 /* Swap loads to the front of the queue. */
12236 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12239 /* Swap stores to the front of the queue. */
12240 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12247 /* Implement TARGET_SCHED_INIT. */
12250 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12251 int max_ready ATTRIBUTE_UNUSED)
12253 mips_macc_chains_last_hilo = 0;
12254 vr4130_last_insn = 0;
12255 mips_74k_agen_init (NULL_RTX);
12257 /* When scheduling for Loongson2, branch instructions go to ALU1,
12258 therefore basic block is most likely to start with round-robin counter
12259 pointed to ALU2. */
12260 mips_ls2.alu1_turn_p = false;
12261 mips_ls2.falu1_turn_p = true;
12264 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12267 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12268 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12270 if (!reload_completed
12271 && TUNE_MACC_CHAINS
12273 mips_macc_chains_reorder (ready, *nreadyp);
12275 if (reload_completed
12277 && !TARGET_VR4130_ALIGN
12279 vr4130_reorder (ready, *nreadyp);
12282 mips_74k_agen_reorder (ready, *nreadyp);
12284 return mips_issue_rate ();
12287 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12290 mips_ls2_variable_issue (rtx insn)
12292 if (mips_ls2.alu1_turn_p)
12294 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12295 mips_ls2.alu1_turn_p = false;
12299 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12300 mips_ls2.alu1_turn_p = true;
12303 if (mips_ls2.falu1_turn_p)
12305 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12306 mips_ls2.falu1_turn_p = false;
12310 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12311 mips_ls2.falu1_turn_p = true;
12314 if (recog_memoized (insn) >= 0)
12315 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12318 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12321 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12322 rtx insn, int more)
12324 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12325 if (USEFUL_INSN_P (insn))
12327 if (get_attr_type (insn) != TYPE_GHOST)
12329 if (!reload_completed && TUNE_MACC_CHAINS)
12330 mips_macc_chains_record (insn);
12331 vr4130_last_insn = insn;
12333 mips_74k_agen_init (insn);
12334 else if (TUNE_LOONGSON_2EF)
12335 mips_ls2_variable_issue (insn);
12338 /* Instructions of type 'multi' should all be split before
12339 the second scheduling pass. */
12340 gcc_assert (!reload_completed
12341 || recog_memoized (insn) < 0
12342 || get_attr_type (insn) != TYPE_MULTI);
12347 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12348 return the first operand of the associated PREF or PREFX insn. */
12351 mips_prefetch_cookie (rtx write, rtx locality)
12353 /* store_streamed / load_streamed. */
12354 if (INTVAL (locality) <= 0)
12355 return GEN_INT (INTVAL (write) + 4);
12357 /* store / load. */
12358 if (INTVAL (locality) <= 2)
12361 /* store_retained / load_retained. */
12362 return GEN_INT (INTVAL (write) + 6);
12365 /* Flags that indicate when a built-in function is available.
12367 BUILTIN_AVAIL_NON_MIPS16
12368 The function is available on the current target, but only
12369 in non-MIPS16 mode. */
12370 #define BUILTIN_AVAIL_NON_MIPS16 1
12372 /* Declare an availability predicate for built-in functions that
12373 require non-MIPS16 mode and also require COND to be true.
12374 NAME is the main part of the predicate's name. */
12375 #define AVAIL_NON_MIPS16(NAME, COND) \
12376 static unsigned int \
12377 mips_builtin_avail_##NAME (void) \
12379 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12382 /* This structure describes a single built-in function. */
12383 struct mips_builtin_description {
12384 /* The code of the main .md file instruction. See mips_builtin_type
12385 for more information. */
12386 enum insn_code icode;
12388 /* The floating-point comparison code to use with ICODE, if any. */
12389 enum mips_fp_condition cond;
12391 /* The name of the built-in function. */
12394 /* Specifies how the function should be expanded. */
12395 enum mips_builtin_type builtin_type;
12397 /* The function's prototype. */
12398 enum mips_function_type function_type;
12400 /* Whether the function is available. */
12401 unsigned int (*avail) (void);
12404 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12405 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12406 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12407 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12408 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12409 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12410 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12411 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12412 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12414 /* Construct a mips_builtin_description from the given arguments.
12416 INSN is the name of the associated instruction pattern, without the
12417 leading CODE_FOR_mips_.
12419 CODE is the floating-point condition code associated with the
12420 function. It can be 'f' if the field is not applicable.
12422 NAME is the name of the function itself, without the leading
12425 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12427 AVAIL is the name of the availability predicate, without the leading
12428 mips_builtin_avail_. */
12429 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12430 FUNCTION_TYPE, AVAIL) \
12431 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12432 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12433 mips_builtin_avail_ ## AVAIL }
12435 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12436 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12437 are as for MIPS_BUILTIN. */
12438 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12439 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12441 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12442 are subject to mips_builtin_avail_<AVAIL>. */
12443 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12444 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12445 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12446 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12447 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12449 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12450 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12451 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12452 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12453 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12454 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12456 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12457 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12459 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12460 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12462 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12463 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12466 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12467 are subject to mips_builtin_avail_mips3d. */
12468 #define CMP_4S_BUILTINS(INSN, COND) \
12469 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12470 MIPS_BUILTIN_CMP_ANY, \
12471 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12472 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12473 MIPS_BUILTIN_CMP_ALL, \
12474 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12476 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12477 instruction requires mips_builtin_avail_<AVAIL>. */
12478 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12479 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12480 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12482 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12483 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12486 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12487 #define CMP_BUILTINS(COND) \
12488 MOVTF_BUILTINS (c, COND, paired_single), \
12489 MOVTF_BUILTINS (cabs, COND, mips3d), \
12490 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12491 CMP_PS_BUILTINS (c, COND, paired_single), \
12492 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12493 CMP_4S_BUILTINS (c, COND), \
12494 CMP_4S_BUILTINS (cabs, COND)
12496 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12497 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12498 and AVAIL are as for MIPS_BUILTIN. */
12499 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12500 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12501 FUNCTION_TYPE, AVAIL)
12503 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12504 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12505 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12506 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12507 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12509 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12510 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12511 builtin_description field. */
12512 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12513 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12514 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12515 FUNCTION_TYPE, mips_builtin_avail_loongson }
12517 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12518 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12519 builtin_description field. */
12520 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12521 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12523 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12524 We use functions of this form when the same insn can be usefully applied
12525 to more than one datatype. */
12526 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12527 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12529 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12530 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12531 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12532 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12533 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12534 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12536 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12537 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12538 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12539 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12540 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12541 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12542 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12543 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12544 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12545 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12546 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12547 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12548 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12549 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12550 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12551 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12552 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12553 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12554 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12555 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12556 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12557 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12558 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12559 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12560 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12561 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12562 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12563 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12564 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12566 static const struct mips_builtin_description mips_builtins[] = {
12567 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12568 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12569 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12570 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12571 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12572 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12573 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12574 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12576 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12577 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12578 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12579 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12580 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12582 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12583 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12584 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12585 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12586 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12587 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12589 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12590 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12591 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12592 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12593 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12594 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12596 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12598 /* Built-in functions for the SB-1 processor. */
12599 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12601 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12602 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12603 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12604 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12605 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12606 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12607 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12608 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12609 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12610 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12611 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12612 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12613 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12614 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12615 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12616 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12617 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12618 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12619 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12620 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12621 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12622 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12623 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12624 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12625 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12626 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12627 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12628 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12629 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12630 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12631 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12632 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12633 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12634 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12635 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12636 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12637 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12638 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12639 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12640 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12641 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12642 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12643 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12644 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12645 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12646 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12647 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12648 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12649 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12650 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12651 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12652 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12653 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12654 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12655 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12656 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12657 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12658 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12659 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12660 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12661 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12662 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12663 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12664 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12665 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12666 BPOSGE_BUILTIN (32, dsp),
12668 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12669 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12670 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12671 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12672 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12673 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12674 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12675 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12676 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12677 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12678 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12679 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12680 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12681 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12682 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12683 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12684 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12685 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12686 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12687 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12688 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12689 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12690 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12691 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12692 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12693 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12694 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12695 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12696 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12697 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12698 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12699 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12700 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12701 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12702 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12704 /* Built-in functions for the DSP ASE (32-bit only). */
12705 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12706 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12707 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12708 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12709 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12710 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12711 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12712 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12713 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12714 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12715 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12716 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12717 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12718 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12719 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12720 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12721 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12722 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12723 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12724 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12725 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12727 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12728 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12729 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12730 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12731 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12732 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12733 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12734 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12735 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
12736 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
12737 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12738 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12739 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12740 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12741 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12742 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12744 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12745 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12746 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12747 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12748 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12749 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12750 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12751 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12752 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12753 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12754 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12755 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12756 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12757 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12758 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12759 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12760 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12761 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12762 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12763 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12764 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12765 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12766 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12767 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12768 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12769 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12770 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12771 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12772 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12773 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12774 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12775 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12776 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12777 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12778 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12779 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12780 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12781 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12782 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12783 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12784 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12785 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12786 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12787 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12788 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12789 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12790 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12791 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12792 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12793 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12794 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12795 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12796 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12797 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12798 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12799 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12800 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12801 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12802 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
12803 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12804 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
12805 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
12806 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
12807 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
12808 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12809 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12810 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12811 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12812 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12813 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12814 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12815 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12816 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12817 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12818 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12819 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12820 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12821 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12822 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12823 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12824 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12825 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12826 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
12827 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
12828 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12829 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12830 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12831 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12832 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12833 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12834 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12835 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12836 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12837 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12838 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12839 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12840 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12841 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12842 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12843 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12845 /* Sundry other built-in functions. */
12846 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12849 /* MODE is a vector mode whose elements have type TYPE. Return the type
12850 of the vector itself. */
12853 mips_builtin_vector_type (tree type, enum machine_mode mode)
12855 static tree types[2 * (int) MAX_MACHINE_MODE];
12858 mode_index = (int) mode;
12860 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12861 mode_index += MAX_MACHINE_MODE;
12863 if (types[mode_index] == NULL_TREE)
12864 types[mode_index] = build_vector_type_for_mode (type, mode);
12865 return types[mode_index];
12868 /* Return a type for 'const volatile void *'. */
12871 mips_build_cvpointer_type (void)
12875 if (cache == NULL_TREE)
12876 cache = build_pointer_type (build_qualified_type
12878 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12882 /* Source-level argument types. */
12883 #define MIPS_ATYPE_VOID void_type_node
12884 #define MIPS_ATYPE_INT integer_type_node
12885 #define MIPS_ATYPE_POINTER ptr_type_node
12886 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12888 /* Standard mode-based argument types. */
12889 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12890 #define MIPS_ATYPE_SI intSI_type_node
12891 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12892 #define MIPS_ATYPE_DI intDI_type_node
12893 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12894 #define MIPS_ATYPE_SF float_type_node
12895 #define MIPS_ATYPE_DF double_type_node
12897 /* Vector argument types. */
12898 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12899 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12900 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12901 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12902 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12903 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12904 #define MIPS_ATYPE_UV2SI \
12905 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12906 #define MIPS_ATYPE_UV4HI \
12907 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
12908 #define MIPS_ATYPE_UV8QI \
12909 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
12911 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
12912 their associated MIPS_ATYPEs. */
12913 #define MIPS_FTYPE_ATYPES1(A, B) \
12914 MIPS_ATYPE_##A, MIPS_ATYPE_##B
12916 #define MIPS_FTYPE_ATYPES2(A, B, C) \
12917 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
12919 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
12920 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
12922 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
12923 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
12926 /* Return the function type associated with function prototype TYPE. */
12929 mips_build_function_type (enum mips_function_type type)
12931 static tree types[(int) MIPS_MAX_FTYPE_MAX];
12933 if (types[(int) type] == NULL_TREE)
12936 #define DEF_MIPS_FTYPE(NUM, ARGS) \
12937 case MIPS_FTYPE_NAME##NUM ARGS: \
12938 types[(int) type] \
12939 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
12942 #include "config/mips/mips-ftypes.def"
12943 #undef DEF_MIPS_FTYPE
12945 gcc_unreachable ();
12948 return types[(int) type];
12951 /* Implement TARGET_INIT_BUILTINS. */
12954 mips_init_builtins (void)
12956 const struct mips_builtin_description *d;
12959 /* Iterate through all of the bdesc arrays, initializing all of the
12960 builtin functions. */
12961 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
12963 d = &mips_builtins[i];
12965 add_builtin_function (d->name,
12966 mips_build_function_type (d->function_type),
12967 i, BUILT_IN_MD, NULL, NULL);
12971 /* Take argument ARGNO from EXP's argument list and convert it into a
12972 form suitable for input operand OPNO of instruction ICODE. Return the
12976 mips_prepare_builtin_arg (enum insn_code icode,
12977 unsigned int opno, tree exp, unsigned int argno)
12981 enum machine_mode mode;
12983 arg = CALL_EXPR_ARG (exp, argno);
12984 value = expand_normal (arg);
12985 mode = insn_data[icode].operand[opno].mode;
12986 if (!insn_data[icode].operand[opno].predicate (value, mode))
12988 /* We need to get the mode from ARG for two reasons:
12990 - to cope with address operands, where MODE is the mode of the
12991 memory, rather than of VALUE itself.
12993 - to cope with special predicates like pmode_register_operand,
12994 where MODE is VOIDmode. */
12995 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
12997 /* Check the predicate again. */
12998 if (!insn_data[icode].operand[opno].predicate (value, mode))
13000 error ("invalid argument to built-in function");
13008 /* Return an rtx suitable for output operand OP of instruction ICODE.
13009 If TARGET is non-null, try to use it where possible. */
13012 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
13014 enum machine_mode mode;
13016 mode = insn_data[icode].operand[op].mode;
13017 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
13018 target = gen_reg_rtx (mode);
13023 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13024 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13025 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13026 suggests a good place to put the result. */
13029 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13032 rtx ops[MAX_RECOG_OPERANDS];
13035 /* Map any target to operand 0. */
13039 target = mips_prepare_builtin_target (icode, opno, target);
13040 ops[opno] = target;
13044 /* Map the arguments to the other operands. The n_operands value
13045 for an expander includes match_dups and match_scratches as well as
13046 match_operands, so n_operands is only an upper bound on the number
13047 of arguments to the expander function. */
13048 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
13049 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
13050 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
13055 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
13059 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
13063 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
13067 gcc_unreachable ();
13072 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13073 function; TYPE says which. EXP is the CALL_EXPR that calls the
13074 function, ICODE is the instruction that should be used to compare
13075 the first two arguments, and COND is the condition it should test.
13076 TARGET, if nonnull, suggests a good place to put the result. */
13079 mips_expand_builtin_movtf (enum mips_builtin_type type,
13080 enum insn_code icode, enum mips_fp_condition cond,
13081 rtx target, tree exp)
13083 rtx cmp_result, op0, op1;
13085 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13086 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
13087 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
13088 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
13090 icode = CODE_FOR_mips_cond_move_tf_ps;
13091 target = mips_prepare_builtin_target (icode, 0, target);
13092 if (type == MIPS_BUILTIN_MOVT)
13094 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
13095 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
13099 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
13100 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
13102 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
13106 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13107 into TARGET otherwise. Return TARGET. */
13110 mips_builtin_branch_and_move (rtx condition, rtx target,
13111 rtx value_if_true, rtx value_if_false)
13113 rtx true_label, done_label;
13115 true_label = gen_label_rtx ();
13116 done_label = gen_label_rtx ();
13118 /* First assume that CONDITION is false. */
13119 mips_emit_move (target, value_if_false);
13121 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13122 emit_jump_insn (gen_condjump (condition, true_label));
13123 emit_jump_insn (gen_jump (done_label));
13126 /* Fix TARGET if CONDITION is true. */
13127 emit_label (true_label);
13128 mips_emit_move (target, value_if_true);
13130 emit_label (done_label);
13134 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13135 the CALL_EXPR that calls the function, ICODE is the code of the
13136 comparison instruction, and COND is the condition it should test.
13137 TARGET, if nonnull, suggests a good place to put the boolean result. */
13140 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13141 enum insn_code icode, enum mips_fp_condition cond,
13142 rtx target, tree exp)
13144 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
13147 if (target == 0 || GET_MODE (target) != SImode)
13148 target = gen_reg_rtx (SImode);
13150 /* The instruction should have a target operand, an operand for each
13151 argument, and an operand for COND. */
13152 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
13154 /* Prepare the operands to the comparison. */
13155 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13156 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13157 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
13159 switch (insn_data[icode].n_operands)
13162 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13167 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13168 args[2], args[3], GEN_INT (cond)));
13172 gcc_unreachable ();
13175 /* If the comparison sets more than one register, we define the result
13176 to be 0 if all registers are false and -1 if all registers are true.
13177 The value of the complete result is indeterminate otherwise. */
13178 switch (builtin_type)
13180 case MIPS_BUILTIN_CMP_ALL:
13181 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13182 return mips_builtin_branch_and_move (condition, target,
13183 const0_rtx, const1_rtx);
13185 case MIPS_BUILTIN_CMP_UPPER:
13186 case MIPS_BUILTIN_CMP_LOWER:
13187 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13188 condition = gen_single_cc (cmp_result, offset);
13189 return mips_builtin_branch_and_move (condition, target,
13190 const1_rtx, const0_rtx);
13193 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13194 return mips_builtin_branch_and_move (condition, target,
13195 const1_rtx, const0_rtx);
13199 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13200 if nonnull, suggests a good place to put the boolean result. */
13203 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13205 rtx condition, cmp_result;
13208 if (target == 0 || GET_MODE (target) != SImode)
13209 target = gen_reg_rtx (SImode);
13211 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13213 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13218 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13219 return mips_builtin_branch_and_move (condition, target,
13220 const1_rtx, const0_rtx);
13223 /* Implement TARGET_EXPAND_BUILTIN. */
13226 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13227 enum machine_mode mode, int ignore)
13230 unsigned int fcode, avail;
13231 const struct mips_builtin_description *d;
13233 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13234 fcode = DECL_FUNCTION_CODE (fndecl);
13235 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13236 d = &mips_builtins[fcode];
13237 avail = d->avail ();
13238 gcc_assert (avail != 0);
13241 error ("built-in function %qE not supported for MIPS16",
13242 DECL_NAME (fndecl));
13243 return ignore ? const0_rtx : CONST0_RTX (mode);
13245 switch (d->builtin_type)
13247 case MIPS_BUILTIN_DIRECT:
13248 return mips_expand_builtin_direct (d->icode, target, exp, true);
13250 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13251 return mips_expand_builtin_direct (d->icode, target, exp, false);
13253 case MIPS_BUILTIN_MOVT:
13254 case MIPS_BUILTIN_MOVF:
13255 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13256 d->cond, target, exp);
13258 case MIPS_BUILTIN_CMP_ANY:
13259 case MIPS_BUILTIN_CMP_ALL:
13260 case MIPS_BUILTIN_CMP_UPPER:
13261 case MIPS_BUILTIN_CMP_LOWER:
13262 case MIPS_BUILTIN_CMP_SINGLE:
13263 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13264 d->cond, target, exp);
13266 case MIPS_BUILTIN_BPOSGE32:
13267 return mips_expand_builtin_bposge (d->builtin_type, target);
13269 gcc_unreachable ();
13272 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13273 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13274 struct mips16_constant {
13275 struct mips16_constant *next;
13278 enum machine_mode mode;
13281 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13282 first constant, HIGHEST_ADDRESS is the highest address that the first
13283 byte of the pool can have, and INSN_ADDRESS is the current instruction
13285 struct mips16_constant_pool {
13286 struct mips16_constant *first;
13287 int highest_address;
13291 /* Add constant VALUE to POOL and return its label. MODE is the
13292 value's mode (used for CONST_INTs, etc.). */
13295 mips16_add_constant (struct mips16_constant_pool *pool,
13296 rtx value, enum machine_mode mode)
13298 struct mips16_constant **p, *c;
13299 bool first_of_size_p;
13301 /* See whether the constant is already in the pool. If so, return the
13302 existing label, otherwise leave P pointing to the place where the
13303 constant should be added.
13305 Keep the pool sorted in increasing order of mode size so that we can
13306 reduce the number of alignments needed. */
13307 first_of_size_p = true;
13308 for (p = &pool->first; *p != 0; p = &(*p)->next)
13310 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13311 return (*p)->label;
13312 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13314 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13315 first_of_size_p = false;
13318 /* In the worst case, the constant needed by the earliest instruction
13319 will end up at the end of the pool. The entire pool must then be
13320 accessible from that instruction.
13322 When adding the first constant, set the pool's highest address to
13323 the address of the first out-of-range byte. Adjust this address
13324 downwards each time a new constant is added. */
13325 if (pool->first == 0)
13326 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13327 of the instruction with the lowest two bits clear. The base PC
13328 value for LDPC has the lowest three bits clear. Assume the worst
13329 case here; namely that the PC-relative instruction occupies the
13330 last 2 bytes in an aligned word. */
13331 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13332 pool->highest_address -= GET_MODE_SIZE (mode);
13333 if (first_of_size_p)
13334 /* Take into account the worst possible padding due to alignment. */
13335 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13337 /* Create a new entry. */
13338 c = XNEW (struct mips16_constant);
13341 c->label = gen_label_rtx ();
13348 /* Output constant VALUE after instruction INSN and return the last
13349 instruction emitted. MODE is the mode of the constant. */
13352 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13354 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13356 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13357 return emit_insn_after (gen_consttable_int (value, size), insn);
13360 if (SCALAR_FLOAT_MODE_P (mode))
13361 return emit_insn_after (gen_consttable_float (value), insn);
13363 if (VECTOR_MODE_P (mode))
13367 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13368 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13369 CONST_VECTOR_ELT (value, i), insn);
13373 gcc_unreachable ();
13376 /* Dump out the constants in CONSTANTS after INSN. */
13379 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13381 struct mips16_constant *c, *next;
13385 for (c = constants; c != NULL; c = next)
13387 /* If necessary, increase the alignment of PC. */
13388 if (align < GET_MODE_SIZE (c->mode))
13390 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13391 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13393 align = GET_MODE_SIZE (c->mode);
13395 insn = emit_label_after (c->label, insn);
13396 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13402 emit_barrier_after (insn);
13405 /* Return the length of instruction INSN. */
13408 mips16_insn_length (rtx insn)
13412 rtx body = PATTERN (insn);
13413 if (GET_CODE (body) == ADDR_VEC)
13414 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13415 if (GET_CODE (body) == ADDR_DIFF_VEC)
13416 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13418 return get_attr_length (insn);
13421 /* If *X is a symbolic constant that refers to the constant pool, add
13422 the constant to POOL and rewrite *X to use the constant's label. */
13425 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13427 rtx base, offset, label;
13429 split_const (*x, &base, &offset);
13430 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13432 label = mips16_add_constant (pool, get_pool_constant (base),
13433 get_pool_mode (base));
13434 base = gen_rtx_LABEL_REF (Pmode, label);
13435 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13439 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13440 INSN is the instruction we're rewriting and POOL points to the current
13442 struct mips16_rewrite_pool_refs_info {
13444 struct mips16_constant_pool *pool;
13447 /* Rewrite *X so that constant pool references refer to the constant's
13448 label instead. DATA points to a mips16_rewrite_pool_refs_info
13452 mips16_rewrite_pool_refs (rtx *x, void *data)
13454 struct mips16_rewrite_pool_refs_info *info =
13455 (struct mips16_rewrite_pool_refs_info *) data;
13457 if (force_to_mem_operand (*x, Pmode))
13459 rtx mem = force_const_mem (GET_MODE (*x), *x);
13460 validate_change (info->insn, x, mem, false);
13465 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13469 if (TARGET_MIPS16_TEXT_LOADS)
13470 mips16_rewrite_pool_constant (info->pool, x);
13472 return GET_CODE (*x) == CONST ? -1 : 0;
13475 /* Return whether CFG is used in mips_reorg. */
13478 mips_cfg_in_reorg (void)
13480 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13481 || TARGET_RELAX_PIC_CALLS);
13484 /* Build MIPS16 constant pools. */
13487 mips16_lay_out_constants (void)
13489 struct mips16_constant_pool pool;
13490 struct mips16_rewrite_pool_refs_info info;
13493 if (!TARGET_MIPS16_PCREL_LOADS)
13496 if (mips_cfg_in_reorg ())
13497 split_all_insns ();
13499 split_all_insns_noflow ();
13501 memset (&pool, 0, sizeof (pool));
13502 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13504 /* Rewrite constant pool references in INSN. */
13505 if (USEFUL_INSN_P (insn))
13509 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13512 pool.insn_address += mips16_insn_length (insn);
13514 if (pool.first != NULL)
13516 /* If there are no natural barriers between the first user of
13517 the pool and the highest acceptable address, we'll need to
13518 create a new instruction to jump around the constant pool.
13519 In the worst case, this instruction will be 4 bytes long.
13521 If it's too late to do this transformation after INSN,
13522 do it immediately before INSN. */
13523 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13527 label = gen_label_rtx ();
13529 jump = emit_jump_insn_before (gen_jump (label), insn);
13530 JUMP_LABEL (jump) = label;
13531 LABEL_NUSES (label) = 1;
13532 barrier = emit_barrier_after (jump);
13534 emit_label_after (label, barrier);
13535 pool.insn_address += 4;
13538 /* See whether the constant pool is now out of range of the first
13539 user. If so, output the constants after the previous barrier.
13540 Note that any instructions between BARRIER and INSN (inclusive)
13541 will use negative offsets to refer to the pool. */
13542 if (pool.insn_address > pool.highest_address)
13544 mips16_emit_constants (pool.first, barrier);
13548 else if (BARRIER_P (insn))
13552 mips16_emit_constants (pool.first, get_last_insn ());
13555 /* Return true if it is worth r10k_simplify_address's while replacing
13556 an address with X. We are looking for constants, and for addresses
13557 at a known offset from the incoming stack pointer. */
13560 r10k_simplified_address_p (rtx x)
13562 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13564 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13567 /* X is an expression that appears in INSN. Try to use the UD chains
13568 to simplify it, returning the simplified form on success and the
13569 original form otherwise. Replace the incoming value of $sp with
13570 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13573 r10k_simplify_address (rtx x, rtx insn)
13575 rtx newx, op0, op1, set, def_insn, note;
13577 struct df_link *defs;
13582 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13583 if (op0 != XEXP (x, 0))
13584 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13585 op0, GET_MODE (XEXP (x, 0)));
13587 else if (BINARY_P (x))
13589 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13590 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13591 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13592 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13594 else if (GET_CODE (x) == LO_SUM)
13596 /* LO_SUMs can be offset from HIGHs, if we know they won't
13597 overflow. See mips_classify_address for the rationale behind
13599 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13600 if (GET_CODE (op0) == HIGH)
13601 newx = XEXP (x, 1);
13603 else if (REG_P (x))
13605 /* Uses are recorded by regno_reg_rtx, not X itself. */
13606 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13608 defs = DF_REF_CHAIN (use);
13610 /* Require a single definition. */
13611 if (defs && defs->next == NULL)
13614 if (DF_REF_IS_ARTIFICIAL (def))
13616 /* Replace the incoming value of $sp with
13617 virtual_incoming_args_rtx. */
13618 if (x == stack_pointer_rtx
13619 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13620 newx = virtual_incoming_args_rtx;
13622 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13625 /* Make sure that DEF_INSN is a single set of REG. */
13626 def_insn = DF_REF_INSN (def);
13627 if (NONJUMP_INSN_P (def_insn))
13629 set = single_set (def_insn);
13630 if (set && rtx_equal_p (SET_DEST (set), x))
13632 /* Prefer to use notes, since the def-use chains
13633 are often shorter. */
13634 note = find_reg_equal_equiv_note (def_insn);
13636 newx = XEXP (note, 0);
13638 newx = SET_SRC (set);
13639 newx = r10k_simplify_address (newx, def_insn);
13645 if (newx && r10k_simplified_address_p (newx))
13650 /* Return true if ADDRESS is known to be an uncached address
13651 on R10K systems. */
13654 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13656 unsigned HOST_WIDE_INT upper;
13658 /* Check for KSEG1. */
13659 if (address + 0x60000000 < 0x20000000)
13662 /* Check for uncached XKPHYS addresses. */
13663 if (Pmode == DImode)
13665 upper = (address >> 40) & 0xf9ffff;
13666 if (upper == 0x900000 || upper == 0xb80000)
13672 /* Return true if we can prove that an access to address X in instruction
13673 INSN would be safe from R10K speculation. This X is a general
13674 expression; it might not be a legitimate address. */
13677 r10k_safe_address_p (rtx x, rtx insn)
13680 HOST_WIDE_INT offset_val;
13682 x = r10k_simplify_address (x, insn);
13684 /* Check for references to the stack frame. It doesn't really matter
13685 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13686 allows us to assume that accesses to any part of the eventual frame
13687 is safe from speculation at any point in the function. */
13688 mips_split_plus (x, &base, &offset_val);
13689 if (base == virtual_incoming_args_rtx
13690 && offset_val >= -cfun->machine->frame.total_size
13691 && offset_val < cfun->machine->frame.args_size)
13694 /* Check for uncached addresses. */
13695 if (CONST_INT_P (x))
13696 return r10k_uncached_address_p (INTVAL (x));
13698 /* Check for accesses to a static object. */
13699 split_const (x, &base, &offset);
13700 return offset_within_block_p (base, INTVAL (offset));
13703 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13704 an in-range access to an automatic variable, or to an object with
13705 a link-time-constant address. */
13708 r10k_safe_mem_expr_p (tree expr, rtx offset)
13710 if (expr == NULL_TREE
13711 || offset == NULL_RTX
13712 || !CONST_INT_P (offset)
13713 || INTVAL (offset) < 0
13714 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13717 while (TREE_CODE (expr) == COMPONENT_REF)
13719 expr = TREE_OPERAND (expr, 0);
13720 if (expr == NULL_TREE)
13724 return DECL_P (expr);
13727 /* A for_each_rtx callback for which DATA points to the instruction
13728 containing *X. Stop the search if we find a MEM that is not safe
13729 from R10K speculation. */
13732 r10k_needs_protection_p_1 (rtx *loc, void *data)
13740 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13743 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13749 /* A note_stores callback for which DATA points to an instruction pointer.
13750 If *DATA is nonnull, make it null if it X contains a MEM that is not
13751 safe from R10K speculation. */
13754 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13759 insn_ptr = (rtx *) data;
13760 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13761 *insn_ptr = NULL_RTX;
13764 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13765 Return nonzero if the call is not to a declared function. */
13768 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13777 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13783 /* Return true if instruction INSN needs to be protected by an R10K
13787 r10k_needs_protection_p (rtx insn)
13790 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13792 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13794 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13795 return insn == NULL_RTX;
13798 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13801 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13802 edge is unconditional. */
13805 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13810 FOR_EACH_EDGE (e, ei, bb->preds)
13811 if (!single_succ_p (e->src)
13812 || !TEST_BIT (protected_bbs, e->src->index)
13813 || (e->flags & EDGE_COMPLEX) != 0)
13818 /* Implement -mr10k-cache-barrier= for the current function. */
13821 r10k_insert_cache_barriers (void)
13823 int *rev_post_order;
13826 sbitmap protected_bbs;
13827 rtx insn, end, unprotected_region;
13831 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13835 /* Calculate dominators. */
13836 calculate_dominance_info (CDI_DOMINATORS);
13838 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13839 X is protected by a cache barrier. */
13840 protected_bbs = sbitmap_alloc (last_basic_block);
13841 sbitmap_zero (protected_bbs);
13843 /* Iterate over the basic blocks in reverse post-order. */
13844 rev_post_order = XNEWVEC (int, last_basic_block);
13845 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13846 for (i = 0; i < n; i++)
13848 bb = BASIC_BLOCK (rev_post_order[i]);
13850 /* If this block is only reached by unconditional edges, and if the
13851 source of every edge is protected, the beginning of the block is
13853 if (r10k_protected_bb_p (bb, protected_bbs))
13854 unprotected_region = NULL_RTX;
13856 unprotected_region = pc_rtx;
13857 end = NEXT_INSN (BB_END (bb));
13859 /* UNPROTECTED_REGION is:
13861 - null if we are processing a protected region,
13862 - pc_rtx if we are processing an unprotected region but have
13863 not yet found the first instruction in it
13864 - the first instruction in an unprotected region otherwise. */
13865 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13867 if (unprotected_region && USEFUL_INSN_P (insn))
13869 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13870 /* This CACHE instruction protects the following code. */
13871 unprotected_region = NULL_RTX;
13874 /* See if INSN is the first instruction in this
13875 unprotected region. */
13876 if (unprotected_region == pc_rtx)
13877 unprotected_region = insn;
13879 /* See if INSN needs to be protected. If so,
13880 we must insert a cache barrier somewhere between
13881 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13882 clear which position is better performance-wise,
13883 but as a tie-breaker, we assume that it is better
13884 to allow delay slots to be back-filled where
13885 possible, and that it is better not to insert
13886 barriers in the middle of already-scheduled code.
13887 We therefore insert the barrier at the beginning
13889 if (r10k_needs_protection_p (insn))
13891 emit_insn_before (gen_r10k_cache_barrier (),
13892 unprotected_region);
13893 unprotected_region = NULL_RTX;
13899 /* The called function is not required to protect the exit path.
13900 The code that follows a call is therefore unprotected. */
13901 unprotected_region = pc_rtx;
13904 /* Record whether the end of this block is protected. */
13905 if (unprotected_region == NULL_RTX)
13906 SET_BIT (protected_bbs, bb->index);
13908 XDELETEVEC (rev_post_order);
13910 sbitmap_free (protected_bbs);
13912 free_dominance_info (CDI_DOMINATORS);
13915 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
13919 mips_call_expr_from_insn (rtx insn)
13923 if (!CALL_P (insn))
13926 x = PATTERN (insn);
13927 if (GET_CODE (x) == PARALLEL)
13928 x = XVECEXP (x, 0, 0);
13929 if (GET_CODE (x) == SET)
13932 gcc_assert (GET_CODE (x) == CALL);
13936 /* REG is set in DEF. See if the definition is one of the ways we load a
13937 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
13938 it is return the symbol reference of the function, otherwise return
13942 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
13946 if (DF_REF_IS_ARTIFICIAL (def))
13949 def_insn = DF_REF_INSN (def);
13950 set = single_set (def_insn);
13951 if (set && rtx_equal_p (SET_DEST (set), reg))
13953 rtx note, src, symbol;
13955 /* First, look at REG_EQUAL/EQUIV notes. */
13956 note = find_reg_equal_equiv_note (def_insn);
13957 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
13958 return XEXP (note, 0);
13960 /* For %call16 references we don't have REG_EQUAL. */
13961 src = SET_SRC (set);
13962 symbol = mips_strip_unspec_call (src);
13965 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
13969 /* Follow simple register copies. */
13971 return mips_find_pic_call_symbol (def_insn, src);
13977 /* Find the definition of the use of REG in INSN. See if the definition is
13978 one of the ways we load a register with a symbol address for a
13979 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
13980 the function, otherwise return NULL_RTX. */
13983 mips_find_pic_call_symbol (rtx insn, rtx reg)
13986 struct df_link *defs;
13989 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
13992 defs = DF_REF_CHAIN (use);
13995 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
13999 /* If we have more than one definition, they need to be identical. */
14000 for (defs = defs->next; defs; defs = defs->next)
14004 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14005 if (!rtx_equal_p (symbol, other))
14012 /* Replace the args_size operand of the call expression CALL with the
14013 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14016 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14020 args_size = XEXP (call, 1);
14021 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14022 gen_rtvec (2, args_size, symbol),
14026 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14027 if instead of the arg_size argument it contains the call attributes. If
14028 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14029 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14033 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14035 rtx args_size, symbol;
14037 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14040 args_size = operands[args_size_opno];
14041 if (GET_CODE (args_size) != UNSPEC)
14043 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14045 symbol = XVECEXP (args_size, 0, 1);
14046 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14048 operands[args_size_opno] = symbol;
14052 /* Use DF to annotate PIC indirect calls with the function symbol they
14056 mips_annotate_pic_calls (void)
14062 FOR_BB_INSNS (bb, insn)
14064 rtx call, reg, symbol;
14066 call = mips_call_expr_from_insn (insn);
14069 gcc_assert (MEM_P (XEXP (call, 0)));
14070 reg = XEXP (XEXP (call, 0), 0);
14074 symbol = mips_find_pic_call_symbol (insn, reg);
14076 mips_annotate_pic_call_expr (call, symbol);
14080 /* A temporary variable used by for_each_rtx callbacks, etc. */
14081 static rtx mips_sim_insn;
14083 /* A structure representing the state of the processor pipeline.
14084 Used by the mips_sim_* family of functions. */
14086 /* The maximum number of instructions that can be issued in a cycle.
14087 (Caches mips_issue_rate.) */
14088 unsigned int issue_rate;
14090 /* The current simulation time. */
14093 /* How many more instructions can be issued in the current cycle. */
14094 unsigned int insns_left;
14096 /* LAST_SET[X].INSN is the last instruction to set register X.
14097 LAST_SET[X].TIME is the time at which that instruction was issued.
14098 INSN is null if no instruction has yet set register X. */
14102 } last_set[FIRST_PSEUDO_REGISTER];
14104 /* The pipeline's current DFA state. */
14108 /* Reset STATE to the initial simulation state. */
14111 mips_sim_reset (struct mips_sim *state)
14114 state->insns_left = state->issue_rate;
14115 memset (&state->last_set, 0, sizeof (state->last_set));
14116 state_reset (state->dfa_state);
14119 /* Initialize STATE before its first use. DFA_STATE points to an
14120 allocated but uninitialized DFA state. */
14123 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14125 state->issue_rate = mips_issue_rate ();
14126 state->dfa_state = dfa_state;
14127 mips_sim_reset (state);
14130 /* Advance STATE by one clock cycle. */
14133 mips_sim_next_cycle (struct mips_sim *state)
14136 state->insns_left = state->issue_rate;
14137 state_transition (state->dfa_state, 0);
14140 /* Advance simulation state STATE until instruction INSN can read
14144 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14146 unsigned int regno, end_regno;
14148 end_regno = END_REGNO (reg);
14149 for (regno = REGNO (reg); regno < end_regno; regno++)
14150 if (state->last_set[regno].insn != 0)
14154 t = (state->last_set[regno].time
14155 + insn_latency (state->last_set[regno].insn, insn));
14156 while (state->time < t)
14157 mips_sim_next_cycle (state);
14161 /* A for_each_rtx callback. If *X is a register, advance simulation state
14162 DATA until mips_sim_insn can read the register's value. */
14165 mips_sim_wait_regs_2 (rtx *x, void *data)
14168 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14172 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14175 mips_sim_wait_regs_1 (rtx *x, void *data)
14177 for_each_rtx (x, mips_sim_wait_regs_2, data);
14180 /* Advance simulation state STATE until all of INSN's register
14181 dependencies are satisfied. */
14184 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14186 mips_sim_insn = insn;
14187 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14190 /* Advance simulation state STATE until the units required by
14191 instruction INSN are available. */
14194 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14198 tmp_state = alloca (state_size ());
14199 while (state->insns_left == 0
14200 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14201 state_transition (tmp_state, insn) >= 0))
14202 mips_sim_next_cycle (state);
14205 /* Advance simulation state STATE until INSN is ready to issue. */
14208 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14210 mips_sim_wait_regs (state, insn);
14211 mips_sim_wait_units (state, insn);
14214 /* mips_sim_insn has just set X. Update the LAST_SET array
14215 in simulation state DATA. */
14218 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14220 struct mips_sim *state;
14222 state = (struct mips_sim *) data;
14225 unsigned int regno, end_regno;
14227 end_regno = END_REGNO (x);
14228 for (regno = REGNO (x); regno < end_regno; regno++)
14230 state->last_set[regno].insn = mips_sim_insn;
14231 state->last_set[regno].time = state->time;
14236 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14237 can issue immediately (i.e., that mips_sim_wait_insn has already
14241 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14243 state_transition (state->dfa_state, insn);
14244 state->insns_left--;
14246 mips_sim_insn = insn;
14247 note_stores (PATTERN (insn), mips_sim_record_set, state);
14250 /* Simulate issuing a NOP in state STATE. */
14253 mips_sim_issue_nop (struct mips_sim *state)
14255 if (state->insns_left == 0)
14256 mips_sim_next_cycle (state);
14257 state->insns_left--;
14260 /* Update simulation state STATE so that it's ready to accept the instruction
14261 after INSN. INSN should be part of the main rtl chain, not a member of a
14265 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14267 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14269 mips_sim_issue_nop (state);
14271 switch (GET_CODE (SEQ_BEGIN (insn)))
14275 /* We can't predict the processor state after a call or label. */
14276 mips_sim_reset (state);
14280 /* The delay slots of branch likely instructions are only executed
14281 when the branch is taken. Therefore, if the caller has simulated
14282 the delay slot instruction, STATE does not really reflect the state
14283 of the pipeline for the instruction after the delay slot. Also,
14284 branch likely instructions tend to incur a penalty when not taken,
14285 so there will probably be an extra delay between the branch and
14286 the instruction after the delay slot. */
14287 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14288 mips_sim_reset (state);
14296 /* The VR4130 pipeline issues aligned pairs of instructions together,
14297 but it stalls the second instruction if it depends on the first.
14298 In order to cut down the amount of logic required, this dependence
14299 check is not based on a full instruction decode. Instead, any non-SPECIAL
14300 instruction is assumed to modify the register specified by bits 20-16
14301 (which is usually the "rt" field).
14303 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14304 input, so we can end up with a false dependence between the branch
14305 and its delay slot. If this situation occurs in instruction INSN,
14306 try to avoid it by swapping rs and rt. */
14309 vr4130_avoid_branch_rt_conflict (rtx insn)
14313 first = SEQ_BEGIN (insn);
14314 second = SEQ_END (insn);
14316 && NONJUMP_INSN_P (second)
14317 && GET_CODE (PATTERN (first)) == SET
14318 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14319 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14321 /* Check for the right kind of condition. */
14322 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14323 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14324 && REG_P (XEXP (cond, 0))
14325 && REG_P (XEXP (cond, 1))
14326 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14327 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14329 /* SECOND mentions the rt register but not the rs register. */
14330 rtx tmp = XEXP (cond, 0);
14331 XEXP (cond, 0) = XEXP (cond, 1);
14332 XEXP (cond, 1) = tmp;
14337 /* Implement -mvr4130-align. Go through each basic block and simulate the
14338 processor pipeline. If we find that a pair of instructions could execute
14339 in parallel, and the first of those instructions is not 8-byte aligned,
14340 insert a nop to make it aligned. */
14343 vr4130_align_insns (void)
14345 struct mips_sim state;
14346 rtx insn, subinsn, last, last2, next;
14351 /* LAST is the last instruction before INSN to have a nonzero length.
14352 LAST2 is the last such instruction before LAST. */
14356 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14359 mips_sim_init (&state, alloca (state_size ()));
14360 for (insn = get_insns (); insn != 0; insn = next)
14362 unsigned int length;
14364 next = NEXT_INSN (insn);
14366 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14367 This isn't really related to the alignment pass, but we do it on
14368 the fly to avoid a separate instruction walk. */
14369 vr4130_avoid_branch_rt_conflict (insn);
14371 if (USEFUL_INSN_P (insn))
14372 FOR_EACH_SUBINSN (subinsn, insn)
14374 mips_sim_wait_insn (&state, subinsn);
14376 /* If we want this instruction to issue in parallel with the
14377 previous one, make sure that the previous instruction is
14378 aligned. There are several reasons why this isn't worthwhile
14379 when the second instruction is a call:
14381 - Calls are less likely to be performance critical,
14382 - There's a good chance that the delay slot can execute
14383 in parallel with the call.
14384 - The return address would then be unaligned.
14386 In general, if we're going to insert a nop between instructions
14387 X and Y, it's better to insert it immediately after X. That
14388 way, if the nop makes Y aligned, it will also align any labels
14389 between X and Y. */
14390 if (state.insns_left != state.issue_rate
14391 && !CALL_P (subinsn))
14393 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14395 /* SUBINSN is the first instruction in INSN and INSN is
14396 aligned. We want to align the previous instruction
14397 instead, so insert a nop between LAST2 and LAST.
14399 Note that LAST could be either a single instruction
14400 or a branch with a delay slot. In the latter case,
14401 LAST, like INSN, is already aligned, but the delay
14402 slot must have some extra delay that stops it from
14403 issuing at the same time as the branch. We therefore
14404 insert a nop before the branch in order to align its
14406 emit_insn_after (gen_nop (), last2);
14409 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14411 /* SUBINSN is the delay slot of INSN, but INSN is
14412 currently unaligned. Insert a nop between
14413 LAST and INSN to align it. */
14414 emit_insn_after (gen_nop (), last);
14418 mips_sim_issue_insn (&state, subinsn);
14420 mips_sim_finish_insn (&state, insn);
14422 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14423 length = get_attr_length (insn);
14426 /* If the instruction is an asm statement or multi-instruction
14427 mips.md patern, the length is only an estimate. Insert an
14428 8 byte alignment after it so that the following instructions
14429 can be handled correctly. */
14430 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14431 && (recog_memoized (insn) < 0 || length >= 8))
14433 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14434 next = NEXT_INSN (next);
14435 mips_sim_next_cycle (&state);
14438 else if (length & 4)
14439 aligned_p = !aligned_p;
14444 /* See whether INSN is an aligned label. */
14445 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14451 /* This structure records that the current function has a LO_SUM
14452 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14453 the largest offset applied to BASE by all such LO_SUMs. */
14454 struct mips_lo_sum_offset {
14456 HOST_WIDE_INT offset;
14459 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14462 mips_hash_base (rtx base)
14464 int do_not_record_p;
14466 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14469 /* Hash-table callbacks for mips_lo_sum_offsets. */
14472 mips_lo_sum_offset_hash (const void *entry)
14474 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14478 mips_lo_sum_offset_eq (const void *entry, const void *value)
14480 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14481 (const_rtx) value);
14484 /* Look up symbolic constant X in HTAB, which is a hash table of
14485 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14486 paired with a recorded LO_SUM, otherwise record X in the table. */
14489 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14493 struct mips_lo_sum_offset *entry;
14495 /* Split X into a base and offset. */
14496 split_const (x, &base, &offset);
14497 if (UNSPEC_ADDRESS_P (base))
14498 base = UNSPEC_ADDRESS (base);
14500 /* Look up the base in the hash table. */
14501 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14505 entry = (struct mips_lo_sum_offset *) *slot;
14506 if (option == INSERT)
14510 entry = XNEW (struct mips_lo_sum_offset);
14511 entry->base = base;
14512 entry->offset = INTVAL (offset);
14517 if (INTVAL (offset) > entry->offset)
14518 entry->offset = INTVAL (offset);
14521 return INTVAL (offset) <= entry->offset;
14524 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14525 Record every LO_SUM in *LOC. */
14528 mips_record_lo_sum (rtx *loc, void *data)
14530 if (GET_CODE (*loc) == LO_SUM)
14531 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14535 /* Return true if INSN is a SET of an orphaned high-part relocation.
14536 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14537 LO_SUMs in the current function. */
14540 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14542 enum mips_symbol_type type;
14545 set = single_set (insn);
14548 /* Check for %his. */
14550 if (GET_CODE (x) == HIGH
14551 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14552 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14554 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14555 if (GET_CODE (x) == UNSPEC
14556 && XINT (x, 1) == UNSPEC_LOAD_GOT
14557 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14558 SYMBOL_CONTEXT_LEA, &type)
14559 && type == SYMBOL_GOTOFF_PAGE)
14560 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14565 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14566 INSN and a previous instruction, avoid it by inserting nops after
14569 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14570 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14571 before using the value of that register. *HILO_DELAY counts the
14572 number of instructions since the last hilo hazard (that is,
14573 the number of instructions since the last MFLO or MFHI).
14575 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14576 for the next instruction.
14578 LO_REG is an rtx for the LO register, used in dependence checking. */
14581 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14582 rtx *delayed_reg, rtx lo_reg)
14587 pattern = PATTERN (insn);
14589 /* Do not put the whole function in .set noreorder if it contains
14590 an asm statement. We don't know whether there will be hazards
14591 between the asm statement and the gcc-generated code. */
14592 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14593 cfun->machine->all_noreorder_p = false;
14595 /* Ignore zero-length instructions (barriers and the like). */
14596 ninsns = get_attr_length (insn) / 4;
14600 /* Work out how many nops are needed. Note that we only care about
14601 registers that are explicitly mentioned in the instruction's pattern.
14602 It doesn't matter that calls use the argument registers or that they
14603 clobber hi and lo. */
14604 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14605 nops = 2 - *hilo_delay;
14606 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14611 /* Insert the nops between this instruction and the previous one.
14612 Each new nop takes us further from the last hilo hazard. */
14613 *hilo_delay += nops;
14615 emit_insn_after (gen_hazard_nop (), after);
14617 /* Set up the state for the next instruction. */
14618 *hilo_delay += ninsns;
14620 if (INSN_CODE (insn) >= 0)
14621 switch (get_attr_hazard (insn))
14631 set = single_set (insn);
14633 *delayed_reg = SET_DEST (set);
14638 /* Go through the instruction stream and insert nops where necessary.
14639 Also delete any high-part relocations whose partnering low parts
14640 are now all dead. See if the whole function can then be put into
14641 .set noreorder and .set nomacro. */
14644 mips_reorg_process_insns (void)
14646 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14650 /* Force all instructions to be split into their final form. */
14651 split_all_insns_noflow ();
14653 /* Recalculate instruction lengths without taking nops into account. */
14654 cfun->machine->ignore_hazard_length_p = true;
14655 shorten_branches (get_insns ());
14657 cfun->machine->all_noreorder_p = true;
14659 /* We don't track MIPS16 PC-relative offsets closely enough to make
14660 a good job of "set .noreorder" code in MIPS16 mode. */
14662 cfun->machine->all_noreorder_p = false;
14664 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14665 if (!TARGET_EXPLICIT_RELOCS)
14666 cfun->machine->all_noreorder_p = false;
14668 /* Profiled functions can't be all noreorder because the profiler
14669 support uses assembler macros. */
14671 cfun->machine->all_noreorder_p = false;
14673 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14674 we rely on the assembler to work around some errata. */
14675 if (TARGET_FIX_VR4120)
14676 cfun->machine->all_noreorder_p = false;
14678 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14679 MFHI instructions. Note that we avoid using MFLO and MFHI if
14680 the VR4130 MACC and DMACC instructions are available instead;
14681 see the *mfhilo_{si,di}_macc patterns. */
14682 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14683 cfun->machine->all_noreorder_p = false;
14685 htab = htab_create (37, mips_lo_sum_offset_hash,
14686 mips_lo_sum_offset_eq, free);
14688 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14689 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14690 FOR_EACH_SUBINSN (subinsn, insn)
14691 if (USEFUL_INSN_P (subinsn))
14692 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14697 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14699 /* Make a second pass over the instructions. Delete orphaned
14700 high-part relocations or turn them into NOPs. Avoid hazards
14701 by inserting NOPs. */
14702 for (insn = get_insns (); insn != 0; insn = next_insn)
14704 next_insn = NEXT_INSN (insn);
14705 if (USEFUL_INSN_P (insn))
14707 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14709 /* If we find an orphaned high-part relocation in a delay
14710 slot, it's easier to turn that instruction into a NOP than
14711 to delete it. The delay slot will be a NOP either way. */
14712 FOR_EACH_SUBINSN (subinsn, insn)
14713 if (INSN_P (subinsn))
14715 if (mips_orphaned_high_part_p (htab, subinsn))
14717 PATTERN (subinsn) = gen_nop ();
14718 INSN_CODE (subinsn) = CODE_FOR_nop;
14720 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14721 &delayed_reg, lo_reg);
14727 /* INSN is a single instruction. Delete it if it's an
14728 orphaned high-part relocation. */
14729 if (mips_orphaned_high_part_p (htab, insn))
14730 delete_insn (insn);
14731 /* Also delete cache barriers if the last instruction
14732 was an annulled branch. INSN will not be speculatively
14734 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14736 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14737 delete_insn (insn);
14740 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14741 &delayed_reg, lo_reg);
14748 htab_delete (htab);
14751 /* If we are using a GOT, but have not decided to use a global pointer yet,
14752 see whether we need one to implement long branches. Convert the ghost
14753 global-pointer instructions into real ones if so. */
14756 mips_expand_ghost_gp_insns (void)
14761 /* Quick exit if we already know that we will or won't need a
14763 if (!TARGET_USE_GOT
14764 || cfun->machine->global_pointer == INVALID_REGNUM
14765 || mips_must_initialize_gp_p ())
14768 shorten_branches (get_insns ());
14770 /* Look for a branch that is longer than normal. The normal length for
14771 non-MIPS16 branches is 8, because the length includes the delay slot.
14772 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14773 but they have no delay slot. */
14774 normal_length = (TARGET_MIPS16 ? 4 : 8);
14775 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14777 && USEFUL_INSN_P (insn)
14778 && get_attr_length (insn) > normal_length)
14781 if (insn == NULL_RTX)
14784 /* We've now established that we need $gp. */
14785 cfun->machine->must_initialize_gp_p = true;
14786 split_all_insns_noflow ();
14791 /* Subroutine of mips_reorg to manage passes that require DF. */
14794 mips_df_reorg (void)
14796 /* Create def-use chains. */
14797 df_set_flags (DF_EQ_NOTES);
14798 df_chain_add_problem (DF_UD_CHAIN);
14801 if (TARGET_RELAX_PIC_CALLS)
14802 mips_annotate_pic_calls ();
14804 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
14805 r10k_insert_cache_barriers ();
14807 df_finish_pass (false);
14810 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14815 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14816 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14817 to date if the CFG is available. */
14818 if (mips_cfg_in_reorg ())
14819 compute_bb_for_insn ();
14820 mips16_lay_out_constants ();
14821 if (mips_cfg_in_reorg ())
14824 free_bb_for_insn ();
14827 if (optimize > 0 && flag_delayed_branch)
14828 dbr_schedule (get_insns ());
14829 mips_reorg_process_insns ();
14831 && TARGET_EXPLICIT_RELOCS
14833 && TARGET_VR4130_ALIGN)
14834 vr4130_align_insns ();
14835 if (mips_expand_ghost_gp_insns ())
14836 /* The expansion could invalidate some of the VR4130 alignment
14837 optimizations, but this should be an extremely rare case anyhow. */
14838 mips_reorg_process_insns ();
14841 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14842 in order to avoid duplicating too much logic from elsewhere. */
14845 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14846 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14849 rtx this_rtx, temp1, temp2, insn, fnaddr;
14850 bool use_sibcall_p;
14852 /* Pretend to be a post-reload pass while generating rtl. */
14853 reload_completed = 1;
14855 /* Mark the end of the (empty) prologue. */
14856 emit_note (NOTE_INSN_PROLOGUE_END);
14858 /* Determine if we can use a sibcall to call FUNCTION directly. */
14859 fnaddr = XEXP (DECL_RTL (function), 0);
14860 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
14861 && const_call_insn_operand (fnaddr, Pmode));
14863 /* Determine if we need to load FNADDR from the GOT. */
14865 && (mips_got_symbol_type_p
14866 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
14868 /* Pick a global pointer. Use a call-clobbered register if
14869 TARGET_CALL_SAVED_GP. */
14870 cfun->machine->global_pointer
14871 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
14872 cfun->machine->must_initialize_gp_p = true;
14873 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
14875 /* Set up the global pointer for n32 or n64 abicalls. */
14876 mips_emit_loadgp ();
14879 /* We need two temporary registers in some cases. */
14880 temp1 = gen_rtx_REG (Pmode, 2);
14881 temp2 = gen_rtx_REG (Pmode, 3);
14883 /* Find out which register contains the "this" pointer. */
14884 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14885 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
14887 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
14889 /* Add DELTA to THIS_RTX. */
14892 rtx offset = GEN_INT (delta);
14893 if (!SMALL_OPERAND (delta))
14895 mips_emit_move (temp1, offset);
14898 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
14901 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
14902 if (vcall_offset != 0)
14906 /* Set TEMP1 to *THIS_RTX. */
14907 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
14909 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
14910 addr = mips_add_offset (temp2, temp1, vcall_offset);
14912 /* Load the offset and add it to THIS_RTX. */
14913 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
14914 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
14917 /* Jump to the target function. Use a sibcall if direct jumps are
14918 allowed, otherwise load the address into a register first. */
14921 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
14922 SIBLING_CALL_P (insn) = 1;
14926 /* This is messy. GAS treats "la $25,foo" as part of a call
14927 sequence and may allow a global "foo" to be lazily bound.
14928 The general move patterns therefore reject this combination.
14930 In this context, lazy binding would actually be OK
14931 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
14932 TARGET_CALL_SAVED_GP; see mips_load_call_address.
14933 We must therefore load the address via a temporary
14934 register if mips_dangerous_for_la25_p.
14936 If we jump to the temporary register rather than $25,
14937 the assembler can use the move insn to fill the jump's
14940 We can use the same technique for MIPS16 code, where $25
14941 is not a valid JR register. */
14942 if (TARGET_USE_PIC_FN_ADDR_REG
14944 && !mips_dangerous_for_la25_p (fnaddr))
14945 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
14946 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
14948 if (TARGET_USE_PIC_FN_ADDR_REG
14949 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
14950 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
14951 emit_jump_insn (gen_indirect_jump (temp1));
14954 /* Run just enough of rest_of_compilation. This sequence was
14955 "borrowed" from alpha.c. */
14956 insn = get_insns ();
14957 insn_locators_alloc ();
14958 split_all_insns_noflow ();
14959 mips16_lay_out_constants ();
14960 shorten_branches (insn);
14961 final_start_function (insn, file, 1);
14962 final (insn, file, 1);
14963 final_end_function ();
14965 /* Clean up the vars set above. Note that final_end_function resets
14966 the global pointer for us. */
14967 reload_completed = 0;
14970 /* The last argument passed to mips_set_mips16_mode, or negative if the
14971 function hasn't been called yet.
14973 There are two copies of this information. One is saved and restored
14974 by the PCH process while the other is specific to this compiler
14975 invocation. The information calculated by mips_set_mips16_mode
14976 is invalid unless the two variables are the same. */
14977 static int was_mips16_p = -1;
14978 static GTY(()) int was_mips16_pch_p = -1;
14980 /* Set up the target-dependent global state so that it matches the
14981 current function's ISA mode. */
14984 mips_set_mips16_mode (int mips16_p)
14986 if (mips16_p == was_mips16_p
14987 && mips16_p == was_mips16_pch_p)
14990 /* Restore base settings of various flags. */
14991 target_flags = mips_base_target_flags;
14992 flag_schedule_insns = mips_base_schedule_insns;
14993 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
14994 flag_move_loop_invariants = mips_base_move_loop_invariants;
14995 align_loops = mips_base_align_loops;
14996 align_jumps = mips_base_align_jumps;
14997 align_functions = mips_base_align_functions;
15001 /* Switch to MIPS16 mode. */
15002 target_flags |= MASK_MIPS16;
15004 /* Don't run the scheduler before reload, since it tends to
15005 increase register pressure. */
15006 flag_schedule_insns = 0;
15008 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15009 the whole function to be in a single section. */
15010 flag_reorder_blocks_and_partition = 0;
15012 /* Don't move loop invariants, because it tends to increase
15013 register pressure. It also introduces an extra move in cases
15014 where the constant is the first operand in a two-operand binary
15015 instruction, or when it forms a register argument to a functon
15017 flag_move_loop_invariants = 0;
15019 target_flags |= MASK_EXPLICIT_RELOCS;
15021 /* Experiments suggest we get the best overall section-anchor
15022 results from using the range of an unextended LW or SW. Code
15023 that makes heavy use of byte or short accesses can do better
15024 with ranges of 0...31 and 0...63 respectively, but most code is
15025 sensitive to the range of LW and SW instead. */
15026 targetm.min_anchor_offset = 0;
15027 targetm.max_anchor_offset = 127;
15029 targetm.const_anchor = 0;
15031 /* MIPS16 has no BAL instruction. */
15032 target_flags &= ~MASK_RELAX_PIC_CALLS;
15034 if (flag_pic && !TARGET_OLDABI)
15035 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15038 sorry ("MIPS16 -mxgot code");
15040 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15041 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15045 /* Switch to normal (non-MIPS16) mode. */
15046 target_flags &= ~MASK_MIPS16;
15048 /* Provide default values for align_* for 64-bit targets. */
15051 if (align_loops == 0)
15053 if (align_jumps == 0)
15055 if (align_functions == 0)
15056 align_functions = 8;
15059 targetm.min_anchor_offset = -32768;
15060 targetm.max_anchor_offset = 32767;
15062 targetm.const_anchor = 0x8000;
15065 /* (Re)initialize MIPS target internals for new ISA. */
15066 mips_init_relocs ();
15068 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
15069 /* Reinitialize target-dependent state. */
15072 was_mips16_p = mips16_p;
15073 was_mips16_pch_p = mips16_p;
15076 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15077 function should use the MIPS16 ISA and switch modes accordingly. */
15080 mips_set_current_function (tree fndecl)
15082 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15085 /* Allocate a chunk of memory for per-function machine-dependent data. */
15087 static struct machine_function *
15088 mips_init_machine_status (void)
15090 return ((struct machine_function *)
15091 ggc_alloc_cleared (sizeof (struct machine_function)));
15094 /* Return the processor associated with the given ISA level, or null
15095 if the ISA isn't valid. */
15097 static const struct mips_cpu_info *
15098 mips_cpu_info_from_isa (int isa)
15102 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15103 if (mips_cpu_info_table[i].isa == isa)
15104 return mips_cpu_info_table + i;
15109 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15110 with a final "000" replaced by "k". Ignore case.
15112 Note: this function is shared between GCC and GAS. */
15115 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15117 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15118 given++, canonical++;
15120 return ((*given == 0 && *canonical == 0)
15121 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15124 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15125 CPU name. We've traditionally allowed a lot of variation here.
15127 Note: this function is shared between GCC and GAS. */
15130 mips_matching_cpu_name_p (const char *canonical, const char *given)
15132 /* First see if the name matches exactly, or with a final "000"
15133 turned into "k". */
15134 if (mips_strict_matching_cpu_name_p (canonical, given))
15137 /* If not, try comparing based on numerical designation alone.
15138 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15139 if (TOLOWER (*given) == 'r')
15141 if (!ISDIGIT (*given))
15144 /* Skip over some well-known prefixes in the canonical name,
15145 hoping to find a number there too. */
15146 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15148 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15150 else if (TOLOWER (canonical[0]) == 'r')
15153 return mips_strict_matching_cpu_name_p (canonical, given);
15156 /* Return the mips_cpu_info entry for the processor or ISA given
15157 by CPU_STRING. Return null if the string isn't recognized.
15159 A similar function exists in GAS. */
15161 static const struct mips_cpu_info *
15162 mips_parse_cpu (const char *cpu_string)
15167 /* In the past, we allowed upper-case CPU names, but it doesn't
15168 work well with the multilib machinery. */
15169 for (s = cpu_string; *s != 0; s++)
15172 warning (0, "CPU names must be lower case");
15176 /* 'from-abi' selects the most compatible architecture for the given
15177 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15178 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15180 if (strcasecmp (cpu_string, "from-abi") == 0)
15181 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15182 : ABI_NEEDS_64BIT_REGS ? 3
15183 : (TARGET_64BIT ? 3 : 1));
15185 /* 'default' has traditionally been a no-op. Probably not very useful. */
15186 if (strcasecmp (cpu_string, "default") == 0)
15189 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15190 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15191 return mips_cpu_info_table + i;
15196 /* Set up globals to generate code for the ISA or processor
15197 described by INFO. */
15200 mips_set_architecture (const struct mips_cpu_info *info)
15204 mips_arch_info = info;
15205 mips_arch = info->cpu;
15206 mips_isa = info->isa;
15210 /* Likewise for tuning. */
15213 mips_set_tune (const struct mips_cpu_info *info)
15217 mips_tune_info = info;
15218 mips_tune = info->cpu;
15222 /* Implement TARGET_HANDLE_OPTION. */
15225 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
15230 if (strcmp (arg, "32") == 0)
15232 else if (strcmp (arg, "o64") == 0)
15233 mips_abi = ABI_O64;
15234 else if (strcmp (arg, "n32") == 0)
15235 mips_abi = ABI_N32;
15236 else if (strcmp (arg, "64") == 0)
15238 else if (strcmp (arg, "eabi") == 0)
15239 mips_abi = ABI_EABI;
15246 return mips_parse_cpu (arg) != 0;
15249 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15250 return mips_isa_option_info != 0;
15252 case OPT_mno_flush_func:
15253 mips_cache_flush_func = NULL;
15256 case OPT_mcode_readable_:
15257 if (strcmp (arg, "yes") == 0)
15258 mips_code_readable = CODE_READABLE_YES;
15259 else if (strcmp (arg, "pcrel") == 0)
15260 mips_code_readable = CODE_READABLE_PCREL;
15261 else if (strcmp (arg, "no") == 0)
15262 mips_code_readable = CODE_READABLE_NO;
15267 case OPT_mr10k_cache_barrier_:
15268 if (strcmp (arg, "load-store") == 0)
15269 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15270 else if (strcmp (arg, "store") == 0)
15271 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15272 else if (strcmp (arg, "none") == 0)
15273 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15283 /* Implement OVERRIDE_OPTIONS. */
15286 mips_override_options (void)
15288 int i, start, regno, mode;
15290 /* Process flags as though we were generating non-MIPS16 code. */
15291 mips_base_mips16 = TARGET_MIPS16;
15292 target_flags &= ~MASK_MIPS16;
15294 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15295 SUBTARGET_OVERRIDE_OPTIONS;
15298 /* Set the small data limit. */
15299 mips_small_data_threshold = (g_switch_set
15301 : MIPS_DEFAULT_GVALUE);
15303 /* The following code determines the architecture and register size.
15304 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15305 The GAS and GCC code should be kept in sync as much as possible. */
15307 if (mips_arch_string != 0)
15308 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15310 if (mips_isa_option_info != 0)
15312 if (mips_arch_info == 0)
15313 mips_set_architecture (mips_isa_option_info);
15314 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15315 error ("%<-%s%> conflicts with the other architecture options, "
15316 "which specify a %s processor",
15317 mips_isa_option_info->name,
15318 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15321 if (mips_arch_info == 0)
15323 #ifdef MIPS_CPU_STRING_DEFAULT
15324 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15326 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15330 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15331 error ("%<-march=%s%> is not compatible with the selected ABI",
15332 mips_arch_info->name);
15334 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15335 if (mips_tune_string != 0)
15336 mips_set_tune (mips_parse_cpu (mips_tune_string));
15338 if (mips_tune_info == 0)
15339 mips_set_tune (mips_arch_info);
15341 if ((target_flags_explicit & MASK_64BIT) != 0)
15343 /* The user specified the size of the integer registers. Make sure
15344 it agrees with the ABI and ISA. */
15345 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15346 error ("%<-mgp64%> used with a 32-bit processor");
15347 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15348 error ("%<-mgp32%> used with a 64-bit ABI");
15349 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15350 error ("%<-mgp64%> used with a 32-bit ABI");
15354 /* Infer the integer register size from the ABI and processor.
15355 Restrict ourselves to 32-bit registers if that's all the
15356 processor has, or if the ABI cannot handle 64-bit registers. */
15357 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15358 target_flags &= ~MASK_64BIT;
15360 target_flags |= MASK_64BIT;
15363 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15365 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15366 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15367 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15368 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15369 else if (!TARGET_64BIT && TARGET_FLOAT64)
15371 if (!ISA_HAS_MXHC1)
15372 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15373 " the target supports the mfhc1 and mthc1 instructions");
15374 else if (mips_abi != ABI_32)
15375 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15381 /* -msingle-float selects 32-bit float registers. Otherwise the
15382 float registers should be the same size as the integer ones. */
15383 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15384 target_flags |= MASK_FLOAT64;
15386 target_flags &= ~MASK_FLOAT64;
15389 /* End of code shared with GAS. */
15391 /* If no -mlong* option was given, infer it from the other options. */
15392 if ((target_flags_explicit & MASK_LONG64) == 0)
15394 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15395 target_flags |= MASK_LONG64;
15397 target_flags &= ~MASK_LONG64;
15400 if (!TARGET_OLDABI)
15401 flag_pcc_struct_return = 0;
15403 /* Decide which rtx_costs structure to use. */
15405 mips_cost = &mips_rtx_cost_optimize_size;
15407 mips_cost = &mips_rtx_cost_data[mips_tune];
15409 /* If the user hasn't specified a branch cost, use the processor's
15411 if (mips_branch_cost == 0)
15412 mips_branch_cost = mips_cost->branch_cost;
15414 /* If neither -mbranch-likely nor -mno-branch-likely was given
15415 on the command line, set MASK_BRANCHLIKELY based on the target
15416 architecture and tuning flags. Annulled delay slots are a
15417 size win, so we only consider the processor-specific tuning
15418 for !optimize_size. */
15419 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15421 if (ISA_HAS_BRANCHLIKELY
15423 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15424 target_flags |= MASK_BRANCHLIKELY;
15426 target_flags &= ~MASK_BRANCHLIKELY;
15428 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15429 warning (0, "the %qs architecture does not support branch-likely"
15430 " instructions", mips_arch_info->name);
15432 /* The effect of -mabicalls isn't defined for the EABI. */
15433 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15435 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15436 target_flags &= ~MASK_ABICALLS;
15439 if (TARGET_ABICALLS_PIC2)
15440 /* We need to set flag_pic for executables as well as DSOs
15441 because we may reference symbols that are not defined in
15442 the final executable. (MIPS does not use things like
15443 copy relocs, for example.)
15445 There is a body of code that uses __PIC__ to distinguish
15446 between -mabicalls and -mno-abicalls code. The non-__PIC__
15447 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15448 long as any indirect jumps use $25. */
15451 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15452 faster code, but at the expense of more nops. Enable it at -O3 and
15454 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15455 target_flags |= MASK_VR4130_ALIGN;
15457 /* Prefer a call to memcpy over inline code when optimizing for size,
15458 though see MOVE_RATIO in mips.h. */
15459 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15460 target_flags |= MASK_MEMCPY;
15462 /* If we have a nonzero small-data limit, check that the -mgpopt
15463 setting is consistent with the other target flags. */
15464 if (mips_small_data_threshold > 0)
15468 if (!TARGET_EXPLICIT_RELOCS)
15469 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15471 TARGET_LOCAL_SDATA = false;
15472 TARGET_EXTERN_SDATA = false;
15476 if (TARGET_VXWORKS_RTP)
15477 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15479 if (TARGET_ABICALLS)
15480 warning (0, "cannot use small-data accesses for %qs",
15485 #ifdef MIPS_TFMODE_FORMAT
15486 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15489 /* Make sure that the user didn't turn off paired single support when
15490 MIPS-3D support is requested. */
15492 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15493 && !TARGET_PAIRED_SINGLE_FLOAT)
15494 error ("%<-mips3d%> requires %<-mpaired-single%>");
15496 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15498 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15500 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15501 and TARGET_HARD_FLOAT_ABI are both true. */
15502 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15503 error ("%qs must be used with %qs",
15504 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15505 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15507 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15509 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15510 warning (0, "the %qs architecture does not support paired-single"
15511 " instructions", mips_arch_info->name);
15513 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15514 && !TARGET_CACHE_BUILTIN)
15516 error ("%qs requires a target that provides the %qs instruction",
15517 "-mr10k-cache-barrier", "cache");
15518 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15521 /* If TARGET_DSPR2, enable MASK_DSP. */
15523 target_flags |= MASK_DSP;
15525 /* .eh_frame addresses should be the same width as a C pointer.
15526 Most MIPS ABIs support only one pointer size, so the assembler
15527 will usually know exactly how big an .eh_frame address is.
15529 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15530 originally defined to use 64-bit pointers (i.e. it is LP64), and
15531 this is still the default mode. However, we also support an n32-like
15532 ILP32 mode, which is selected by -mlong32. The problem is that the
15533 assembler has traditionally not had an -mlong option, so it has
15534 traditionally not known whether we're using the ILP32 or LP64 form.
15536 As it happens, gas versions up to and including 2.19 use _32-bit_
15537 addresses for EABI64 .cfi_* directives. This is wrong for the
15538 default LP64 mode, so we can't use the directives by default.
15539 Moreover, since gas's current behavior is at odds with gcc's
15540 default behavior, it seems unwise to rely on future versions
15541 of gas behaving the same way. We therefore avoid using .cfi
15542 directives for -mlong32 as well. */
15543 if (mips_abi == ABI_EABI && TARGET_64BIT)
15544 flag_dwarf2_cfi_asm = 0;
15546 /* .cfi_* directives generate a read-only section, so fall back on
15547 manual .eh_frame creation if we need the section to be writable. */
15548 if (TARGET_WRITABLE_EH_FRAME)
15549 flag_dwarf2_cfi_asm = 0;
15551 mips_init_print_operand_punct ();
15553 /* Set up array to map GCC register number to debug register number.
15554 Ignore the special purpose register numbers. */
15556 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15558 mips_dbx_regno[i] = INVALID_REGNUM;
15559 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15560 mips_dwarf_regno[i] = i;
15562 mips_dwarf_regno[i] = INVALID_REGNUM;
15565 start = GP_DBX_FIRST - GP_REG_FIRST;
15566 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15567 mips_dbx_regno[i] = i + start;
15569 start = FP_DBX_FIRST - FP_REG_FIRST;
15570 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15571 mips_dbx_regno[i] = i + start;
15573 /* Accumulator debug registers use big-endian ordering. */
15574 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15575 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15576 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15577 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15578 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15580 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15581 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15584 /* Set up mips_hard_regno_mode_ok. */
15585 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15586 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15587 mips_hard_regno_mode_ok[mode][regno]
15588 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15590 /* Function to allocate machine-dependent function status. */
15591 init_machine_status = &mips_init_machine_status;
15593 /* Default to working around R4000 errata only if the processor
15594 was selected explicitly. */
15595 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15596 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15597 target_flags |= MASK_FIX_R4000;
15599 /* Default to working around R4400 errata only if the processor
15600 was selected explicitly. */
15601 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15602 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15603 target_flags |= MASK_FIX_R4400;
15605 /* Default to working around R10000 errata only if the processor
15606 was selected explicitly. */
15607 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15608 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15609 target_flags |= MASK_FIX_R10000;
15611 /* Make sure that branch-likely instructions available when using
15612 -mfix-r10000. The instructions are not available if either:
15614 1. -mno-branch-likely was passed.
15615 2. The selected ISA does not support branch-likely and
15616 the command line does not include -mbranch-likely. */
15617 if (TARGET_FIX_R10000
15618 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15619 ? !ISA_HAS_BRANCHLIKELY
15620 : !TARGET_BRANCHLIKELY))
15621 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15623 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15625 warning (0, "the %qs architecture does not support the synci "
15626 "instruction", mips_arch_info->name);
15627 target_flags &= ~MASK_SYNCI;
15630 /* Only optimize PIC indirect calls if they are actually required. */
15631 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15632 target_flags &= ~MASK_RELAX_PIC_CALLS;
15634 /* Save base state of options. */
15635 mips_base_target_flags = target_flags;
15636 mips_base_schedule_insns = flag_schedule_insns;
15637 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15638 mips_base_move_loop_invariants = flag_move_loop_invariants;
15639 mips_base_align_loops = align_loops;
15640 mips_base_align_jumps = align_jumps;
15641 mips_base_align_functions = align_functions;
15643 /* Now select the ISA mode.
15645 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15646 MIPS16 mode afterwards if need be. */
15647 mips_set_mips16_mode (false);
15650 /* Swap the register information for registers I and I + 1, which
15651 currently have the wrong endianness. Note that the registers'
15652 fixedness and call-clobberedness might have been set on the
15656 mips_swap_registers (unsigned int i)
15661 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15662 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15664 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15665 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15666 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15667 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15673 /* Implement CONDITIONAL_REGISTER_USAGE. */
15676 mips_conditional_register_usage (void)
15681 /* These DSP control register fields are global. */
15682 global_regs[CCDSP_PO_REGNUM] = 1;
15683 global_regs[CCDSP_SC_REGNUM] = 1;
15689 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15690 fixed_regs[regno] = call_used_regs[regno] = 1;
15692 if (!TARGET_HARD_FLOAT)
15696 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15697 fixed_regs[regno] = call_used_regs[regno] = 1;
15698 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15699 fixed_regs[regno] = call_used_regs[regno] = 1;
15701 else if (! ISA_HAS_8CC)
15705 /* We only have a single condition-code register. We implement
15706 this by fixing all the condition-code registers and generating
15707 RTL that refers directly to ST_REG_FIRST. */
15708 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15709 fixed_regs[regno] = call_used_regs[regno] = 1;
15711 /* In MIPS16 mode, we permit the $t temporary registers to be used
15712 for reload. We prohibit the unused $s registers, since they
15713 are call-saved, and saving them via a MIPS16 register would
15714 probably waste more time than just reloading the value. */
15717 fixed_regs[18] = call_used_regs[18] = 1;
15718 fixed_regs[19] = call_used_regs[19] = 1;
15719 fixed_regs[20] = call_used_regs[20] = 1;
15720 fixed_regs[21] = call_used_regs[21] = 1;
15721 fixed_regs[22] = call_used_regs[22] = 1;
15722 fixed_regs[23] = call_used_regs[23] = 1;
15723 fixed_regs[26] = call_used_regs[26] = 1;
15724 fixed_regs[27] = call_used_regs[27] = 1;
15725 fixed_regs[30] = call_used_regs[30] = 1;
15727 /* $f20-$f23 are call-clobbered for n64. */
15728 if (mips_abi == ABI_64)
15731 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15732 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15734 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15736 if (mips_abi == ABI_N32)
15739 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15740 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15742 /* Make sure that double-register accumulator values are correctly
15743 ordered for the current endianness. */
15744 if (TARGET_LITTLE_ENDIAN)
15746 unsigned int regno;
15748 mips_swap_registers (MD_REG_FIRST);
15749 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15750 mips_swap_registers (regno);
15754 /* Initialize vector TARGET to VALS. */
15757 mips_expand_vector_init (rtx target, rtx vals)
15759 enum machine_mode mode;
15760 enum machine_mode inner;
15761 unsigned int i, n_elts;
15764 mode = GET_MODE (target);
15765 inner = GET_MODE_INNER (mode);
15766 n_elts = GET_MODE_NUNITS (mode);
15768 gcc_assert (VECTOR_MODE_P (mode));
15770 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15771 for (i = 0; i < n_elts; i++)
15772 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15773 XVECEXP (vals, 0, i));
15775 emit_move_insn (target, mem);
15778 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15779 other registers for instructions for which it is possible. This
15780 encourages the compiler to use CMP in cases where an XOR would
15781 require some register shuffling. */
15784 mips_order_regs_for_local_alloc (void)
15788 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15789 reg_alloc_order[i] = i;
15793 /* It really doesn't matter where we put register 0, since it is
15794 a fixed register anyhow. */
15795 reg_alloc_order[0] = 24;
15796 reg_alloc_order[24] = 0;
15800 /* Implement EH_USES. */
15803 mips_eh_uses (unsigned int regno)
15805 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
15807 /* We need to force certain registers to be live in order to handle
15808 PIC long branches correctly. See mips_must_initialize_gp_p for
15810 if (mips_cfun_has_cprestore_slot_p ())
15812 if (regno == CPRESTORE_SLOT_REGNUM)
15817 if (cfun->machine->global_pointer == regno)
15825 /* Implement EPILOGUE_USES. */
15828 mips_epilogue_uses (unsigned int regno)
15830 /* Say that the epilogue uses the return address register. Note that
15831 in the case of sibcalls, the values "used by the epilogue" are
15832 considered live at the start of the called function. */
15833 if (regno == RETURN_ADDR_REGNUM)
15836 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15837 See the comment above load_call<mode> for details. */
15838 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
15841 /* An interrupt handler must preserve some registers that are
15842 ordinarily call-clobbered. */
15843 if (cfun->machine->interrupt_handler_p
15844 && mips_interrupt_extra_call_saved_reg_p (regno))
15850 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15853 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
15855 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
15858 /* Return true if INSN needs to be wrapped in ".set noat".
15859 INSN has NOPERANDS operands, stored in OPVEC. */
15862 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
15866 if (recog_memoized (insn) >= 0)
15867 for (i = 0; i < noperands; i++)
15868 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
15873 /* Implement FINAL_PRESCAN_INSN. */
15876 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
15878 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15879 mips_push_asm_switch (&mips_noat);
15882 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
15885 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
15886 rtx *opvec, int noperands)
15888 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15889 mips_pop_asm_switch (&mips_noat);
15892 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE. */
15895 mips_asm_trampoline_template (FILE *f)
15897 if (ptr_mode == DImode)
15898 fprintf (f, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n");
15900 fprintf (f, "\t.word\t0x03e00821\t\t# move $1,$31\n");
15901 fprintf (f, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");
15902 fprintf (f, "\t.word\t0x00000000\t\t# nop\n");
15903 if (ptr_mode == DImode)
15905 fprintf (f, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n");
15906 fprintf (f, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n");
15910 fprintf (f, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n");
15911 fprintf (f, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n");
15913 fprintf (f, "\t.word\t0x03200008\t\t# jr $25\n");
15914 if (ptr_mode == DImode)
15916 fprintf (f, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n");
15917 fprintf (f, "\t.word\t0x00000000\t\t# <padding>\n");
15918 fprintf (f, "\t.dword\t0x00000000\t\t# <function address>\n");
15919 fprintf (f, "\t.dword\t0x00000000\t\t# <static chain value>\n");
15923 fprintf (f, "\t.word\t0x0020f821\t\t# move $31,$1\n");
15924 fprintf (f, "\t.word\t0x00000000\t\t# <function address>\n");
15925 fprintf (f, "\t.word\t0x00000000\t\t# <static chain value>\n");
15929 /* Implement TARGET_TRAMPOLINE_INIT. */
15932 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
15934 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
15935 rtx mem, addr, end_addr;
15937 emit_block_move (m_tramp, assemble_trampoline_template (),
15938 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
15940 mem = adjust_address (m_tramp, ptr_mode, ptr_mode == DImode ? 32 : 28);
15941 mips_emit_move (mem, force_reg (ptr_mode, fnaddr));
15942 mem = adjust_address (mem, ptr_mode, GET_MODE_SIZE (ptr_mode));
15943 mips_emit_move (mem, force_reg (ptr_mode, chain_value));
15945 addr = force_reg (ptr_mode, XEXP (m_tramp, 0));
15946 end_addr = gen_reg_rtx (ptr_mode);
15947 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
15948 emit_insn (gen_clear_cache (addr, end_addr));
15952 /* Initialize the GCC target structure. */
15953 #undef TARGET_ASM_ALIGNED_HI_OP
15954 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
15955 #undef TARGET_ASM_ALIGNED_SI_OP
15956 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
15957 #undef TARGET_ASM_ALIGNED_DI_OP
15958 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
15960 #undef TARGET_LEGITIMIZE_ADDRESS
15961 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
15963 #undef TARGET_ASM_FUNCTION_PROLOGUE
15964 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
15965 #undef TARGET_ASM_FUNCTION_EPILOGUE
15966 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
15967 #undef TARGET_ASM_SELECT_RTX_SECTION
15968 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
15969 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
15970 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
15972 #undef TARGET_SCHED_INIT
15973 #define TARGET_SCHED_INIT mips_sched_init
15974 #undef TARGET_SCHED_REORDER
15975 #define TARGET_SCHED_REORDER mips_sched_reorder
15976 #undef TARGET_SCHED_REORDER2
15977 #define TARGET_SCHED_REORDER2 mips_sched_reorder
15978 #undef TARGET_SCHED_VARIABLE_ISSUE
15979 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
15980 #undef TARGET_SCHED_ADJUST_COST
15981 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
15982 #undef TARGET_SCHED_ISSUE_RATE
15983 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
15984 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
15985 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
15986 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
15987 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
15988 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
15989 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
15990 mips_multipass_dfa_lookahead
15992 #undef TARGET_DEFAULT_TARGET_FLAGS
15993 #define TARGET_DEFAULT_TARGET_FLAGS \
15995 | TARGET_CPU_DEFAULT \
15996 | TARGET_ENDIAN_DEFAULT \
15997 | TARGET_FP_EXCEPTIONS_DEFAULT \
15998 | MASK_CHECK_ZERO_DIV \
16000 #undef TARGET_HANDLE_OPTION
16001 #define TARGET_HANDLE_OPTION mips_handle_option
16003 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16004 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16006 #undef TARGET_INSERT_ATTRIBUTES
16007 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16008 #undef TARGET_MERGE_DECL_ATTRIBUTES
16009 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16010 #undef TARGET_SET_CURRENT_FUNCTION
16011 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16013 #undef TARGET_VALID_POINTER_MODE
16014 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16015 #undef TARGET_RTX_COSTS
16016 #define TARGET_RTX_COSTS mips_rtx_costs
16017 #undef TARGET_ADDRESS_COST
16018 #define TARGET_ADDRESS_COST mips_address_cost
16020 #undef TARGET_IN_SMALL_DATA_P
16021 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16023 #undef TARGET_MACHINE_DEPENDENT_REORG
16024 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16026 #undef TARGET_ASM_FILE_START
16027 #define TARGET_ASM_FILE_START mips_file_start
16028 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16029 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16031 #undef TARGET_INIT_LIBFUNCS
16032 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16034 #undef TARGET_BUILD_BUILTIN_VA_LIST
16035 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16036 #undef TARGET_EXPAND_BUILTIN_VA_START
16037 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16038 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16039 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16041 #undef TARGET_PROMOTE_FUNCTION_MODE
16042 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16043 #undef TARGET_PROMOTE_PROTOTYPES
16044 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16046 #undef TARGET_RETURN_IN_MEMORY
16047 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16048 #undef TARGET_RETURN_IN_MSB
16049 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16051 #undef TARGET_ASM_OUTPUT_MI_THUNK
16052 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16053 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16054 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16056 #undef TARGET_SETUP_INCOMING_VARARGS
16057 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16058 #undef TARGET_STRICT_ARGUMENT_NAMING
16059 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16060 #undef TARGET_MUST_PASS_IN_STACK
16061 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16062 #undef TARGET_PASS_BY_REFERENCE
16063 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16064 #undef TARGET_CALLEE_COPIES
16065 #define TARGET_CALLEE_COPIES mips_callee_copies
16066 #undef TARGET_ARG_PARTIAL_BYTES
16067 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16069 #undef TARGET_MODE_REP_EXTENDED
16070 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16072 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16073 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16075 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16076 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16078 #undef TARGET_INIT_BUILTINS
16079 #define TARGET_INIT_BUILTINS mips_init_builtins
16080 #undef TARGET_EXPAND_BUILTIN
16081 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16083 #undef TARGET_HAVE_TLS
16084 #define TARGET_HAVE_TLS HAVE_AS_TLS
16086 #undef TARGET_CANNOT_FORCE_CONST_MEM
16087 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16089 #undef TARGET_ENCODE_SECTION_INFO
16090 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16092 #undef TARGET_ATTRIBUTE_TABLE
16093 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16094 /* All our function attributes are related to how out-of-line copies should
16095 be compiled or called. They don't in themselves prevent inlining. */
16096 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16097 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16099 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16100 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16102 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16103 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16104 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16105 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16107 #undef TARGET_COMP_TYPE_ATTRIBUTES
16108 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16110 #ifdef HAVE_AS_DTPRELWORD
16111 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16112 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16114 #undef TARGET_DWARF_REGISTER_SPAN
16115 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16117 #undef TARGET_IRA_COVER_CLASSES
16118 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16120 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16121 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16123 #undef TARGET_LEGITIMATE_ADDRESS_P
16124 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16126 #undef TARGET_FRAME_POINTER_REQUIRED
16127 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16129 #undef TARGET_CAN_ELIMINATE
16130 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16132 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
16133 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mips_asm_trampoline_template
16134 #undef TARGET_TRAMPOLINE_INIT
16135 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16137 struct gcc_target targetm = TARGET_INITIALIZER;
16139 #include "gt-mips.h"