1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky, lich@inria.inria.fr.
6 Changes by Michael Meissner, meissner@osf.org.
7 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
8 Brendan Eich, brendan@microunity.com.
10 This file is part of GCC.
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
54 #include "target-def.h"
55 #include "integrate.h"
56 #include "langhooks.h"
57 #include "cfglayout.h"
58 #include "sched-int.h"
61 #include "diagnostic.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Enumerates the setting of the -mr10k-cache-barrier option. */
186 enum mips_r10k_cache_barrier_setting {
187 R10K_CACHE_BARRIER_NONE,
188 R10K_CACHE_BARRIER_STORE,
189 R10K_CACHE_BARRIER_LOAD_STORE
192 /* Macros to create an enumeration identifier for a function prototype. */
193 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
194 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
195 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
196 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
198 /* Classifies the prototype of a built-in function. */
199 enum mips_function_type {
200 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
201 #include "config/mips/mips-ftypes.def"
202 #undef DEF_MIPS_FTYPE
206 /* Specifies how a built-in function should be converted into rtl. */
207 enum mips_builtin_type {
208 /* The function corresponds directly to an .md pattern. The return
209 value is mapped to operand 0 and the arguments are mapped to
210 operands 1 and above. */
213 /* The function corresponds directly to an .md pattern. There is no return
214 value and the arguments are mapped to operands 0 and above. */
215 MIPS_BUILTIN_DIRECT_NO_TARGET,
217 /* The function corresponds to a comparison instruction followed by
218 a mips_cond_move_tf_ps pattern. The first two arguments are the
219 values to compare and the second two arguments are the vector
220 operands for the movt.ps or movf.ps instruction (in assembly order). */
224 /* The function corresponds to a V2SF comparison instruction. Operand 0
225 of this instruction is the result of the comparison, which has mode
226 CCV2 or CCV4. The function arguments are mapped to operands 1 and
227 above. The function's return value is an SImode boolean that is
228 true under the following conditions:
230 MIPS_BUILTIN_CMP_ANY: one of the registers is true
231 MIPS_BUILTIN_CMP_ALL: all of the registers are true
232 MIPS_BUILTIN_CMP_LOWER: the first register is true
233 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
234 MIPS_BUILTIN_CMP_ANY,
235 MIPS_BUILTIN_CMP_ALL,
236 MIPS_BUILTIN_CMP_UPPER,
237 MIPS_BUILTIN_CMP_LOWER,
239 /* As above, but the instruction only sets a single $fcc register. */
240 MIPS_BUILTIN_CMP_SINGLE,
242 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
243 MIPS_BUILTIN_BPOSGE32
246 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
247 #define MIPS_FP_CONDITIONS(MACRO) \
265 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
266 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
267 enum mips_fp_condition {
268 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
271 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
272 #define STRINGIFY(X) #X
273 static const char *const mips_fp_conditions[] = {
274 MIPS_FP_CONDITIONS (STRINGIFY)
277 /* Information about a function's frame layout. */
278 struct GTY(()) mips_frame_info {
279 /* The size of the frame in bytes. */
280 HOST_WIDE_INT total_size;
282 /* The number of bytes allocated to variables. */
283 HOST_WIDE_INT var_size;
285 /* The number of bytes allocated to outgoing function arguments. */
286 HOST_WIDE_INT args_size;
288 /* The number of bytes allocated to the .cprestore slot, or 0 if there
290 HOST_WIDE_INT cprestore_size;
292 /* Bit X is set if the function saves or restores GPR X. */
295 /* Likewise FPR X. */
298 /* Likewise doubleword accumulator X ($acX). */
299 unsigned int acc_mask;
301 /* The number of GPRs, FPRs, doubleword accumulators and COP0
305 unsigned int num_acc;
306 unsigned int num_cop0_regs;
308 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
309 save slots from the top of the frame, or zero if no such slots are
311 HOST_WIDE_INT gp_save_offset;
312 HOST_WIDE_INT fp_save_offset;
313 HOST_WIDE_INT acc_save_offset;
314 HOST_WIDE_INT cop0_save_offset;
316 /* Likewise, but giving offsets from the bottom of the frame. */
317 HOST_WIDE_INT gp_sp_offset;
318 HOST_WIDE_INT fp_sp_offset;
319 HOST_WIDE_INT acc_sp_offset;
320 HOST_WIDE_INT cop0_sp_offset;
322 /* Similar, but the value passed to _mcount. */
323 HOST_WIDE_INT ra_fp_offset;
325 /* The offset of arg_pointer_rtx from the bottom of the frame. */
326 HOST_WIDE_INT arg_pointer_offset;
328 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
329 HOST_WIDE_INT hard_frame_pointer_offset;
332 struct GTY(()) machine_function {
333 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
334 rtx mips16_gp_pseudo_rtx;
336 /* The number of extra stack bytes taken up by register varargs.
337 This area is allocated by the callee at the very top of the frame. */
340 /* The current frame information, calculated by mips_compute_frame_info. */
341 struct mips_frame_info frame;
343 /* The register to use as the function's global pointer, or INVALID_REGNUM
344 if the function doesn't need one. */
345 unsigned int global_pointer;
347 /* How many instructions it takes to load a label into $AT, or 0 if
348 this property hasn't yet been calculated. */
349 unsigned int load_label_length;
351 /* True if mips_adjust_insn_length should ignore an instruction's
353 bool ignore_hazard_length_p;
355 /* True if the whole function is suitable for .set noreorder and
357 bool all_noreorder_p;
359 /* True if the function has "inflexible" and "flexible" references
360 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
361 and mips_cfun_has_flexible_gp_ref_p for details. */
362 bool has_inflexible_gp_insn_p;
363 bool has_flexible_gp_insn_p;
365 /* True if the function's prologue must load the global pointer
366 value into pic_offset_table_rtx and store the same value in
367 the function's cprestore slot (if any). Even if this value
368 is currently false, we may decide to set it to true later;
369 see mips_must_initialize_gp_p () for details. */
370 bool must_initialize_gp_p;
372 /* True if the current function must restore $gp after any potential
373 clobber. This value is only meaningful during the first post-epilogue
374 split_insns pass; see mips_must_initialize_gp_p () for details. */
375 bool must_restore_gp_when_clobbered_p;
377 /* True if we have emitted an instruction to initialize
378 mips16_gp_pseudo_rtx. */
379 bool initialized_mips16_gp_pseudo_p;
381 /* True if this is an interrupt handler. */
382 bool interrupt_handler_p;
384 /* True if this is an interrupt handler that uses shadow registers. */
385 bool use_shadow_register_set_p;
387 /* True if this is an interrupt handler that should keep interrupts
389 bool keep_interrupts_masked_p;
391 /* True if this is an interrupt handler that should use DERET
393 bool use_debug_exception_return_p;
396 /* Information about a single argument. */
397 struct mips_arg_info {
398 /* True if the argument is passed in a floating-point register, or
399 would have been if we hadn't run out of registers. */
402 /* The number of words passed in registers, rounded up. */
403 unsigned int reg_words;
405 /* For EABI, the offset of the first register from GP_ARG_FIRST or
406 FP_ARG_FIRST. For other ABIs, the offset of the first register from
407 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
408 comment for details).
410 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
412 unsigned int reg_offset;
414 /* The number of words that must be passed on the stack, rounded up. */
415 unsigned int stack_words;
417 /* The offset from the start of the stack overflow area of the argument's
418 first stack word. Only meaningful when STACK_WORDS is nonzero. */
419 unsigned int stack_offset;
422 /* Information about an address described by mips_address_type.
428 REG is the base register and OFFSET is the constant offset.
431 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
432 is the type of symbol it references.
435 SYMBOL_TYPE is the type of symbol that the address references. */
436 struct mips_address_info {
437 enum mips_address_type type;
440 enum mips_symbol_type symbol_type;
443 /* One stage in a constant building sequence. These sequences have
447 A = A CODE[1] VALUE[1]
448 A = A CODE[2] VALUE[2]
451 where A is an accumulator, each CODE[i] is a binary rtl operation
452 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
453 struct mips_integer_op {
455 unsigned HOST_WIDE_INT value;
458 /* The largest number of operations needed to load an integer constant.
459 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
460 When the lowest bit is clear, we can try, but reject a sequence with
461 an extra SLL at the end. */
462 #define MIPS_MAX_INTEGER_OPS 7
464 /* Information about a MIPS16e SAVE or RESTORE instruction. */
465 struct mips16e_save_restore_info {
466 /* The number of argument registers saved by a SAVE instruction.
467 0 for RESTORE instructions. */
470 /* Bit X is set if the instruction saves or restores GPR X. */
473 /* The total number of bytes to allocate. */
477 /* Global variables for machine-dependent things. */
479 /* The -G setting, or the configuration's default small-data limit if
480 no -G option is given. */
481 static unsigned int mips_small_data_threshold;
483 /* The number of file directives written by mips_output_filename. */
484 int num_source_filenames;
486 /* The name that appeared in the last .file directive written by
487 mips_output_filename, or "" if mips_output_filename hasn't
488 written anything yet. */
489 const char *current_function_file = "";
491 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
494 /* Arrays that map GCC register numbers to debugger register numbers. */
495 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
496 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
498 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
499 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
500 struct mips_asm_switch mips_nomacro = { "macro", 0 };
501 struct mips_asm_switch mips_noat = { "at", 0 };
503 /* True if we're writing out a branch-likely instruction rather than a
505 static bool mips_branch_likely;
507 /* The current instruction-set architecture. */
508 enum processor_type mips_arch;
509 const struct mips_cpu_info *mips_arch_info;
511 /* The processor that we should tune the code for. */
512 enum processor_type mips_tune;
513 const struct mips_cpu_info *mips_tune_info;
515 /* The ISA level associated with mips_arch. */
518 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
519 static const struct mips_cpu_info *mips_isa_option_info;
521 /* Which ABI to use. */
522 int mips_abi = MIPS_ABI_DEFAULT;
524 /* Which cost information to use. */
525 const struct mips_rtx_cost_data *mips_cost;
527 /* The ambient target flags, excluding MASK_MIPS16. */
528 static int mips_base_target_flags;
530 /* True if MIPS16 is the default mode. */
531 bool mips_base_mips16;
533 /* The ambient values of other global variables. */
534 static int mips_base_schedule_insns; /* flag_schedule_insns */
535 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
536 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
537 static int mips_base_align_loops; /* align_loops */
538 static int mips_base_align_jumps; /* align_jumps */
539 static int mips_base_align_functions; /* align_functions */
541 /* The -mcode-readable setting. */
542 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
544 /* The -mr10k-cache-barrier setting. */
545 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
547 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
548 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
550 /* Index C is true if character C is a valid PRINT_OPERAND punctation
552 bool mips_print_operand_punct[256];
554 static GTY (()) int mips_output_filename_first_time = 1;
556 /* mips_split_p[X] is true if symbols of type X can be split by
557 mips_split_symbol. */
558 bool mips_split_p[NUM_SYMBOL_TYPES];
560 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
561 can be split by mips_split_symbol. */
562 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
564 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
565 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
566 if they are matched by a special .md file pattern. */
567 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
569 /* Likewise for HIGHs. */
570 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
572 /* Index R is the smallest register class that contains register R. */
573 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
574 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
575 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
576 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
577 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
578 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
579 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
580 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
581 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
582 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
583 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
584 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
585 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
586 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
587 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
588 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
589 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
590 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
591 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
592 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
593 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
594 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
595 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
596 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
597 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
598 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
599 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
600 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
601 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
602 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
603 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
604 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
605 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
606 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
607 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
608 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
609 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
610 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
611 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
612 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
613 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
614 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
615 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
616 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
617 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
618 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
619 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
620 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
623 /* The value of TARGET_ATTRIBUTE_TABLE. */
624 static const struct attribute_spec mips_attribute_table[] = {
625 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
626 { "long_call", 0, 0, false, true, true, NULL },
627 { "far", 0, 0, false, true, true, NULL },
628 { "near", 0, 0, false, true, true, NULL },
629 /* We would really like to treat "mips16" and "nomips16" as type
630 attributes, but GCC doesn't provide the hooks we need to support
631 the right conversion rules. As declaration attributes, they affect
632 code generation but don't carry other semantics. */
633 { "mips16", 0, 0, true, false, false, NULL },
634 { "nomips16", 0, 0, true, false, false, NULL },
635 /* Allow functions to be specified as interrupt handlers */
636 { "interrupt", 0, 0, false, true, true, NULL },
637 { "use_shadow_register_set", 0, 0, false, true, true, NULL },
638 { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
639 { "use_debug_exception_return", 0, 0, false, true, true, NULL },
640 { NULL, 0, 0, false, false, false, NULL }
643 /* A table describing all the processors GCC knows about. Names are
644 matched in the order listed. The first mention of an ISA level is
645 taken as the canonical name for that ISA.
647 To ease comparison, please keep this table in the same order
648 as GAS's mips_cpu_info_table. Please also make sure that
649 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
650 options correctly. */
651 static const struct mips_cpu_info mips_cpu_info_table[] = {
652 /* Entries for generic ISAs. */
653 { "mips1", PROCESSOR_R3000, 1, 0 },
654 { "mips2", PROCESSOR_R6000, 2, 0 },
655 { "mips3", PROCESSOR_R4000, 3, 0 },
656 { "mips4", PROCESSOR_R8000, 4, 0 },
657 /* Prefer not to use branch-likely instructions for generic MIPS32rX
658 and MIPS64rX code. The instructions were officially deprecated
659 in revisions 2 and earlier, but revision 3 is likely to downgrade
660 that to a recommendation to avoid the instructions in code that
661 isn't tuned to a specific processor. */
662 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
663 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
664 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
665 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
666 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
668 /* MIPS I processors. */
669 { "r3000", PROCESSOR_R3000, 1, 0 },
670 { "r2000", PROCESSOR_R3000, 1, 0 },
671 { "r3900", PROCESSOR_R3900, 1, 0 },
673 /* MIPS II processors. */
674 { "r6000", PROCESSOR_R6000, 2, 0 },
676 /* MIPS III processors. */
677 { "r4000", PROCESSOR_R4000, 3, 0 },
678 { "vr4100", PROCESSOR_R4100, 3, 0 },
679 { "vr4111", PROCESSOR_R4111, 3, 0 },
680 { "vr4120", PROCESSOR_R4120, 3, 0 },
681 { "vr4130", PROCESSOR_R4130, 3, 0 },
682 { "vr4300", PROCESSOR_R4300, 3, 0 },
683 { "r4400", PROCESSOR_R4000, 3, 0 },
684 { "r4600", PROCESSOR_R4600, 3, 0 },
685 { "orion", PROCESSOR_R4600, 3, 0 },
686 { "r4650", PROCESSOR_R4650, 3, 0 },
687 /* ST Loongson 2E/2F processors. */
688 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
689 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
691 /* MIPS IV processors. */
692 { "r8000", PROCESSOR_R8000, 4, 0 },
693 { "r10000", PROCESSOR_R10000, 4, 0 },
694 { "r12000", PROCESSOR_R10000, 4, 0 },
695 { "r14000", PROCESSOR_R10000, 4, 0 },
696 { "r16000", PROCESSOR_R10000, 4, 0 },
697 { "vr5000", PROCESSOR_R5000, 4, 0 },
698 { "vr5400", PROCESSOR_R5400, 4, 0 },
699 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
700 { "rm7000", PROCESSOR_R7000, 4, 0 },
701 { "rm9000", PROCESSOR_R9000, 4, 0 },
703 /* MIPS32 processors. */
704 { "4kc", PROCESSOR_4KC, 32, 0 },
705 { "4km", PROCESSOR_4KC, 32, 0 },
706 { "4kp", PROCESSOR_4KP, 32, 0 },
707 { "4ksc", PROCESSOR_4KC, 32, 0 },
709 /* MIPS32 Release 2 processors. */
710 { "m4k", PROCESSOR_M4K, 33, 0 },
711 { "4kec", PROCESSOR_4KC, 33, 0 },
712 { "4kem", PROCESSOR_4KC, 33, 0 },
713 { "4kep", PROCESSOR_4KP, 33, 0 },
714 { "4ksd", PROCESSOR_4KC, 33, 0 },
716 { "24kc", PROCESSOR_24KC, 33, 0 },
717 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
718 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
719 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
720 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
721 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
723 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
724 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
725 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
726 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
727 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
728 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
730 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
731 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
732 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
733 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
734 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
735 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
737 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
738 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
739 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
740 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
741 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
742 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
743 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
745 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
746 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
747 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
748 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
750 /* MIPS64 processors. */
751 { "5kc", PROCESSOR_5KC, 64, 0 },
752 { "5kf", PROCESSOR_5KF, 64, 0 },
753 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
754 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
755 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
756 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
757 { "xlr", PROCESSOR_XLR, 64, 0 },
759 /* MIPS64 Release 2 processors. */
760 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
763 /* Default costs. If these are used for a processor we should look
764 up the actual costs. */
765 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
766 COSTS_N_INSNS (7), /* fp_mult_sf */ \
767 COSTS_N_INSNS (8), /* fp_mult_df */ \
768 COSTS_N_INSNS (23), /* fp_div_sf */ \
769 COSTS_N_INSNS (36), /* fp_div_df */ \
770 COSTS_N_INSNS (10), /* int_mult_si */ \
771 COSTS_N_INSNS (10), /* int_mult_di */ \
772 COSTS_N_INSNS (69), /* int_div_si */ \
773 COSTS_N_INSNS (69), /* int_div_di */ \
774 2, /* branch_cost */ \
775 4 /* memory_latency */
777 /* Floating-point costs for processors without an FPU. Just assume that
778 all floating-point libcalls are very expensive. */
779 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
780 COSTS_N_INSNS (256), /* fp_mult_sf */ \
781 COSTS_N_INSNS (256), /* fp_mult_df */ \
782 COSTS_N_INSNS (256), /* fp_div_sf */ \
783 COSTS_N_INSNS (256) /* fp_div_df */
785 /* Costs to use when optimizing for size. */
786 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
787 COSTS_N_INSNS (1), /* fp_add */
788 COSTS_N_INSNS (1), /* fp_mult_sf */
789 COSTS_N_INSNS (1), /* fp_mult_df */
790 COSTS_N_INSNS (1), /* fp_div_sf */
791 COSTS_N_INSNS (1), /* fp_div_df */
792 COSTS_N_INSNS (1), /* int_mult_si */
793 COSTS_N_INSNS (1), /* int_mult_di */
794 COSTS_N_INSNS (1), /* int_div_si */
795 COSTS_N_INSNS (1), /* int_div_di */
797 4 /* memory_latency */
800 /* Costs to use when optimizing for speed, indexed by processor. */
801 static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
803 COSTS_N_INSNS (2), /* fp_add */
804 COSTS_N_INSNS (4), /* fp_mult_sf */
805 COSTS_N_INSNS (5), /* fp_mult_df */
806 COSTS_N_INSNS (12), /* fp_div_sf */
807 COSTS_N_INSNS (19), /* fp_div_df */
808 COSTS_N_INSNS (12), /* int_mult_si */
809 COSTS_N_INSNS (12), /* int_mult_di */
810 COSTS_N_INSNS (35), /* int_div_si */
811 COSTS_N_INSNS (35), /* int_div_di */
813 4 /* memory_latency */
817 COSTS_N_INSNS (6), /* int_mult_si */
818 COSTS_N_INSNS (6), /* int_mult_di */
819 COSTS_N_INSNS (36), /* int_div_si */
820 COSTS_N_INSNS (36), /* int_div_di */
822 4 /* memory_latency */
826 COSTS_N_INSNS (36), /* int_mult_si */
827 COSTS_N_INSNS (36), /* int_mult_di */
828 COSTS_N_INSNS (37), /* int_div_si */
829 COSTS_N_INSNS (37), /* int_div_di */
831 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* int_mult_si */
836 COSTS_N_INSNS (11), /* int_mult_di */
837 COSTS_N_INSNS (36), /* int_div_si */
838 COSTS_N_INSNS (68), /* int_div_di */
840 4 /* memory_latency */
843 COSTS_N_INSNS (4), /* fp_add */
844 COSTS_N_INSNS (4), /* fp_mult_sf */
845 COSTS_N_INSNS (5), /* fp_mult_df */
846 COSTS_N_INSNS (17), /* fp_div_sf */
847 COSTS_N_INSNS (32), /* fp_div_df */
848 COSTS_N_INSNS (4), /* int_mult_si */
849 COSTS_N_INSNS (11), /* int_mult_di */
850 COSTS_N_INSNS (36), /* int_div_si */
851 COSTS_N_INSNS (68), /* int_div_di */
853 4 /* memory_latency */
856 COSTS_N_INSNS (4), /* fp_add */
857 COSTS_N_INSNS (4), /* fp_mult_sf */
858 COSTS_N_INSNS (5), /* fp_mult_df */
859 COSTS_N_INSNS (17), /* fp_div_sf */
860 COSTS_N_INSNS (32), /* fp_div_df */
861 COSTS_N_INSNS (4), /* int_mult_si */
862 COSTS_N_INSNS (7), /* int_mult_di */
863 COSTS_N_INSNS (42), /* int_div_si */
864 COSTS_N_INSNS (72), /* int_div_di */
866 4 /* memory_latency */
870 COSTS_N_INSNS (5), /* int_mult_si */
871 COSTS_N_INSNS (5), /* int_mult_di */
872 COSTS_N_INSNS (41), /* int_div_si */
873 COSTS_N_INSNS (41), /* int_div_di */
875 4 /* memory_latency */
878 COSTS_N_INSNS (8), /* fp_add */
879 COSTS_N_INSNS (8), /* fp_mult_sf */
880 COSTS_N_INSNS (10), /* fp_mult_df */
881 COSTS_N_INSNS (34), /* fp_div_sf */
882 COSTS_N_INSNS (64), /* fp_div_df */
883 COSTS_N_INSNS (5), /* int_mult_si */
884 COSTS_N_INSNS (5), /* int_mult_di */
885 COSTS_N_INSNS (41), /* int_div_si */
886 COSTS_N_INSNS (41), /* int_div_di */
888 4 /* memory_latency */
891 COSTS_N_INSNS (4), /* fp_add */
892 COSTS_N_INSNS (4), /* fp_mult_sf */
893 COSTS_N_INSNS (5), /* fp_mult_df */
894 COSTS_N_INSNS (17), /* fp_div_sf */
895 COSTS_N_INSNS (32), /* fp_div_df */
896 COSTS_N_INSNS (5), /* int_mult_si */
897 COSTS_N_INSNS (5), /* int_mult_di */
898 COSTS_N_INSNS (41), /* int_div_si */
899 COSTS_N_INSNS (41), /* int_div_di */
901 4 /* memory_latency */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (41), /* int_div_si */
908 COSTS_N_INSNS (41), /* int_div_di */
910 4 /* memory_latency */
913 COSTS_N_INSNS (8), /* fp_add */
914 COSTS_N_INSNS (8), /* fp_mult_sf */
915 COSTS_N_INSNS (10), /* fp_mult_df */
916 COSTS_N_INSNS (34), /* fp_div_sf */
917 COSTS_N_INSNS (64), /* fp_div_df */
918 COSTS_N_INSNS (5), /* int_mult_si */
919 COSTS_N_INSNS (5), /* int_mult_di */
920 COSTS_N_INSNS (41), /* int_div_si */
921 COSTS_N_INSNS (41), /* int_div_di */
923 4 /* memory_latency */
926 COSTS_N_INSNS (4), /* fp_add */
927 COSTS_N_INSNS (4), /* fp_mult_sf */
928 COSTS_N_INSNS (5), /* fp_mult_df */
929 COSTS_N_INSNS (17), /* fp_div_sf */
930 COSTS_N_INSNS (32), /* fp_div_df */
931 COSTS_N_INSNS (5), /* int_mult_si */
932 COSTS_N_INSNS (5), /* int_mult_di */
933 COSTS_N_INSNS (41), /* int_div_si */
934 COSTS_N_INSNS (41), /* int_div_di */
936 4 /* memory_latency */
939 COSTS_N_INSNS (6), /* fp_add */
940 COSTS_N_INSNS (6), /* fp_mult_sf */
941 COSTS_N_INSNS (7), /* fp_mult_df */
942 COSTS_N_INSNS (25), /* fp_div_sf */
943 COSTS_N_INSNS (48), /* fp_div_df */
944 COSTS_N_INSNS (5), /* int_mult_si */
945 COSTS_N_INSNS (5), /* int_mult_di */
946 COSTS_N_INSNS (41), /* int_div_si */
947 COSTS_N_INSNS (41), /* int_div_di */
949 4 /* memory_latency */
963 COSTS_N_INSNS (5), /* int_mult_si */
964 COSTS_N_INSNS (5), /* int_mult_di */
965 COSTS_N_INSNS (72), /* int_div_si */
966 COSTS_N_INSNS (72), /* int_div_di */
968 4 /* memory_latency */
971 COSTS_N_INSNS (2), /* fp_add */
972 COSTS_N_INSNS (4), /* fp_mult_sf */
973 COSTS_N_INSNS (5), /* fp_mult_df */
974 COSTS_N_INSNS (12), /* fp_div_sf */
975 COSTS_N_INSNS (19), /* fp_div_df */
976 COSTS_N_INSNS (2), /* int_mult_si */
977 COSTS_N_INSNS (2), /* int_mult_di */
978 COSTS_N_INSNS (35), /* int_div_si */
979 COSTS_N_INSNS (35), /* int_div_di */
981 4 /* memory_latency */
984 COSTS_N_INSNS (3), /* fp_add */
985 COSTS_N_INSNS (5), /* fp_mult_sf */
986 COSTS_N_INSNS (6), /* fp_mult_df */
987 COSTS_N_INSNS (15), /* fp_div_sf */
988 COSTS_N_INSNS (16), /* fp_div_df */
989 COSTS_N_INSNS (17), /* int_mult_si */
990 COSTS_N_INSNS (17), /* int_mult_di */
991 COSTS_N_INSNS (38), /* int_div_si */
992 COSTS_N_INSNS (38), /* int_div_di */
994 6 /* memory_latency */
997 COSTS_N_INSNS (6), /* fp_add */
998 COSTS_N_INSNS (7), /* fp_mult_sf */
999 COSTS_N_INSNS (8), /* fp_mult_df */
1000 COSTS_N_INSNS (23), /* fp_div_sf */
1001 COSTS_N_INSNS (36), /* fp_div_df */
1002 COSTS_N_INSNS (10), /* int_mult_si */
1003 COSTS_N_INSNS (10), /* int_mult_di */
1004 COSTS_N_INSNS (69), /* int_div_si */
1005 COSTS_N_INSNS (69), /* int_div_di */
1006 2, /* branch_cost */
1007 6 /* memory_latency */
1019 /* The only costs that appear to be updated here are
1020 integer multiplication. */
1022 COSTS_N_INSNS (4), /* int_mult_si */
1023 COSTS_N_INSNS (6), /* int_mult_di */
1024 COSTS_N_INSNS (69), /* int_div_si */
1025 COSTS_N_INSNS (69), /* int_div_di */
1026 1, /* branch_cost */
1027 4 /* memory_latency */
1039 COSTS_N_INSNS (6), /* fp_add */
1040 COSTS_N_INSNS (4), /* fp_mult_sf */
1041 COSTS_N_INSNS (5), /* fp_mult_df */
1042 COSTS_N_INSNS (23), /* fp_div_sf */
1043 COSTS_N_INSNS (36), /* fp_div_df */
1044 COSTS_N_INSNS (5), /* int_mult_si */
1045 COSTS_N_INSNS (5), /* int_mult_di */
1046 COSTS_N_INSNS (36), /* int_div_si */
1047 COSTS_N_INSNS (36), /* int_div_di */
1048 1, /* branch_cost */
1049 4 /* memory_latency */
1052 COSTS_N_INSNS (6), /* fp_add */
1053 COSTS_N_INSNS (5), /* fp_mult_sf */
1054 COSTS_N_INSNS (6), /* fp_mult_df */
1055 COSTS_N_INSNS (30), /* fp_div_sf */
1056 COSTS_N_INSNS (59), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (4), /* int_mult_di */
1059 COSTS_N_INSNS (42), /* int_div_si */
1060 COSTS_N_INSNS (74), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1065 COSTS_N_INSNS (6), /* fp_add */
1066 COSTS_N_INSNS (5), /* fp_mult_sf */
1067 COSTS_N_INSNS (6), /* fp_mult_df */
1068 COSTS_N_INSNS (30), /* fp_div_sf */
1069 COSTS_N_INSNS (59), /* fp_div_df */
1070 COSTS_N_INSNS (5), /* int_mult_si */
1071 COSTS_N_INSNS (9), /* int_mult_di */
1072 COSTS_N_INSNS (42), /* int_div_si */
1073 COSTS_N_INSNS (74), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 /* The only costs that are changed here are
1079 integer multiplication. */
1080 COSTS_N_INSNS (6), /* fp_add */
1081 COSTS_N_INSNS (7), /* fp_mult_sf */
1082 COSTS_N_INSNS (8), /* fp_mult_df */
1083 COSTS_N_INSNS (23), /* fp_div_sf */
1084 COSTS_N_INSNS (36), /* fp_div_df */
1085 COSTS_N_INSNS (5), /* int_mult_si */
1086 COSTS_N_INSNS (9), /* int_mult_di */
1087 COSTS_N_INSNS (69), /* int_div_si */
1088 COSTS_N_INSNS (69), /* int_div_di */
1089 1, /* branch_cost */
1090 4 /* memory_latency */
1096 /* The only costs that are changed here are
1097 integer multiplication. */
1098 COSTS_N_INSNS (6), /* fp_add */
1099 COSTS_N_INSNS (7), /* fp_mult_sf */
1100 COSTS_N_INSNS (8), /* fp_mult_df */
1101 COSTS_N_INSNS (23), /* fp_div_sf */
1102 COSTS_N_INSNS (36), /* fp_div_df */
1103 COSTS_N_INSNS (3), /* int_mult_si */
1104 COSTS_N_INSNS (8), /* int_mult_di */
1105 COSTS_N_INSNS (69), /* int_div_si */
1106 COSTS_N_INSNS (69), /* int_div_di */
1107 1, /* branch_cost */
1108 4 /* memory_latency */
1111 COSTS_N_INSNS (2), /* fp_add */
1112 COSTS_N_INSNS (2), /* fp_mult_sf */
1113 COSTS_N_INSNS (2), /* fp_mult_df */
1114 COSTS_N_INSNS (12), /* fp_div_sf */
1115 COSTS_N_INSNS (19), /* fp_div_df */
1116 COSTS_N_INSNS (5), /* int_mult_si */
1117 COSTS_N_INSNS (9), /* int_mult_di */
1118 COSTS_N_INSNS (34), /* int_div_si */
1119 COSTS_N_INSNS (66), /* int_div_di */
1120 1, /* branch_cost */
1121 4 /* memory_latency */
1124 /* These costs are the same as the SB-1A below. */
1125 COSTS_N_INSNS (4), /* fp_add */
1126 COSTS_N_INSNS (4), /* fp_mult_sf */
1127 COSTS_N_INSNS (4), /* fp_mult_df */
1128 COSTS_N_INSNS (24), /* fp_div_sf */
1129 COSTS_N_INSNS (32), /* fp_div_df */
1130 COSTS_N_INSNS (3), /* int_mult_si */
1131 COSTS_N_INSNS (4), /* int_mult_di */
1132 COSTS_N_INSNS (36), /* int_div_si */
1133 COSTS_N_INSNS (68), /* int_div_di */
1134 1, /* branch_cost */
1135 4 /* memory_latency */
1138 /* These costs are the same as the SB-1 above. */
1139 COSTS_N_INSNS (4), /* fp_add */
1140 COSTS_N_INSNS (4), /* fp_mult_sf */
1141 COSTS_N_INSNS (4), /* fp_mult_df */
1142 COSTS_N_INSNS (24), /* fp_div_sf */
1143 COSTS_N_INSNS (32), /* fp_div_df */
1144 COSTS_N_INSNS (3), /* int_mult_si */
1145 COSTS_N_INSNS (4), /* int_mult_di */
1146 COSTS_N_INSNS (36), /* int_div_si */
1147 COSTS_N_INSNS (68), /* int_div_di */
1148 1, /* branch_cost */
1149 4 /* memory_latency */
1156 COSTS_N_INSNS (8), /* int_mult_si */
1157 COSTS_N_INSNS (8), /* int_mult_di */
1158 COSTS_N_INSNS (72), /* int_div_si */
1159 COSTS_N_INSNS (72), /* int_div_di */
1160 1, /* branch_cost */
1161 4 /* memory_latency */
1165 static rtx mips_find_pic_call_symbol (rtx, rtx);
1167 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1168 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1169 struct GTY (()) mflip_mips16_entry {
1173 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1175 /* Hash table callbacks for mflip_mips16_htab. */
1178 mflip_mips16_htab_hash (const void *entry)
1180 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1184 mflip_mips16_htab_eq (const void *entry, const void *name)
1186 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1187 (const char *) name) == 0;
1190 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1191 mode, false if it should next add an attribute for the opposite mode. */
1192 static GTY(()) bool mips16_flipper;
1194 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1195 for -mflip-mips16. Return true if it should use "mips16" and false if
1196 it should use "nomips16". */
1199 mflip_mips16_use_mips16_p (tree decl)
1201 struct mflip_mips16_entry *entry;
1206 /* Use the opposite of the command-line setting for anonymous decls. */
1207 if (!DECL_NAME (decl))
1208 return !mips_base_mips16;
1210 if (!mflip_mips16_htab)
1211 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1212 mflip_mips16_htab_eq, NULL);
1214 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1215 hash = htab_hash_string (name);
1216 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1217 entry = (struct mflip_mips16_entry *) *slot;
1220 mips16_flipper = !mips16_flipper;
1221 entry = GGC_NEW (struct mflip_mips16_entry);
1223 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1226 return entry->mips16_p;
1229 /* Predicates to test for presence of "near" and "far"/"long_call"
1230 attributes on the given TYPE. */
1233 mips_near_type_p (const_tree type)
1235 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1239 mips_far_type_p (const_tree type)
1241 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1242 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1245 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1248 mips_mips16_decl_p (const_tree decl)
1250 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1254 mips_nomips16_decl_p (const_tree decl)
1256 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1259 /* Check if the interrupt attribute is set for a function. */
1262 mips_interrupt_type_p (tree type)
1264 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1267 /* Check if the attribute to use shadow register set is set for a function. */
1270 mips_use_shadow_register_set_p (tree type)
1272 return lookup_attribute ("use_shadow_register_set",
1273 TYPE_ATTRIBUTES (type)) != NULL;
1276 /* Check if the attribute to keep interrupts masked is set for a function. */
1279 mips_keep_interrupts_masked_p (tree type)
1281 return lookup_attribute ("keep_interrupts_masked",
1282 TYPE_ATTRIBUTES (type)) != NULL;
1285 /* Check if the attribute to use debug exception return is set for
1289 mips_use_debug_exception_return_p (tree type)
1291 return lookup_attribute ("use_debug_exception_return",
1292 TYPE_ATTRIBUTES (type)) != NULL;
1295 /* Return true if function DECL is a MIPS16 function. Return the ambient
1296 setting if DECL is null. */
1299 mips_use_mips16_mode_p (tree decl)
1303 /* Nested functions must use the same frame pointer as their
1304 parent and must therefore use the same ISA mode. */
1305 tree parent = decl_function_context (decl);
1308 if (mips_mips16_decl_p (decl))
1310 if (mips_nomips16_decl_p (decl))
1313 return mips_base_mips16;
1316 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1319 mips_comp_type_attributes (const_tree type1, const_tree type2)
1321 /* Disallow mixed near/far attributes. */
1322 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1324 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1329 /* Implement TARGET_INSERT_ATTRIBUTES. */
1332 mips_insert_attributes (tree decl, tree *attributes)
1335 bool mips16_p, nomips16_p;
1337 /* Check for "mips16" and "nomips16" attributes. */
1338 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1339 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1340 if (TREE_CODE (decl) != FUNCTION_DECL)
1343 error ("%qs attribute only applies to functions", "mips16");
1345 error ("%qs attribute only applies to functions", "nomips16");
1349 mips16_p |= mips_mips16_decl_p (decl);
1350 nomips16_p |= mips_nomips16_decl_p (decl);
1351 if (mips16_p || nomips16_p)
1353 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1354 if (mips16_p && nomips16_p)
1355 error ("%qE cannot have both %<mips16%> and "
1356 "%<nomips16%> attributes",
1359 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1361 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1362 "mips16" attribute, arbitrarily pick one. We must pick the same
1363 setting for duplicate declarations of a function. */
1364 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1365 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1370 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1373 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1375 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1376 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1377 error ("%qE redeclared with conflicting %qs attributes",
1378 DECL_NAME (newdecl), "mips16");
1379 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1380 error ("%qE redeclared with conflicting %qs attributes",
1381 DECL_NAME (newdecl), "nomips16");
1383 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1384 DECL_ATTRIBUTES (newdecl));
1387 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1388 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1391 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1393 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1395 *base_ptr = XEXP (x, 0);
1396 *offset_ptr = INTVAL (XEXP (x, 1));
1405 static unsigned int mips_build_integer (struct mips_integer_op *,
1406 unsigned HOST_WIDE_INT);
1408 /* A subroutine of mips_build_integer, with the same interface.
1409 Assume that the final action in the sequence should be a left shift. */
1412 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1414 unsigned int i, shift;
1416 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1417 since signed numbers are easier to load than unsigned ones. */
1419 while ((value & 1) == 0)
1420 value /= 2, shift++;
1422 i = mips_build_integer (codes, value);
1423 codes[i].code = ASHIFT;
1424 codes[i].value = shift;
1428 /* As for mips_build_shift, but assume that the final action will be
1429 an IOR or PLUS operation. */
1432 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1434 unsigned HOST_WIDE_INT high;
1437 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1438 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1440 /* The constant is too complex to load with a simple LUI/ORI pair,
1441 so we want to give the recursive call as many trailing zeros as
1442 possible. In this case, we know bit 16 is set and that the
1443 low 16 bits form a negative number. If we subtract that number
1444 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1445 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1446 codes[i].code = PLUS;
1447 codes[i].value = CONST_LOW_PART (value);
1451 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1452 bits gives a value with at least 17 trailing zeros. */
1453 i = mips_build_integer (codes, high);
1454 codes[i].code = IOR;
1455 codes[i].value = value & 0xffff;
1460 /* Fill CODES with a sequence of rtl operations to load VALUE.
1461 Return the number of operations needed. */
1464 mips_build_integer (struct mips_integer_op *codes,
1465 unsigned HOST_WIDE_INT value)
1467 if (SMALL_OPERAND (value)
1468 || SMALL_OPERAND_UNSIGNED (value)
1469 || LUI_OPERAND (value))
1471 /* The value can be loaded with a single instruction. */
1472 codes[0].code = UNKNOWN;
1473 codes[0].value = value;
1476 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1478 /* Either the constant is a simple LUI/ORI combination or its
1479 lowest bit is set. We don't want to shift in this case. */
1480 return mips_build_lower (codes, value);
1482 else if ((value & 0xffff) == 0)
1484 /* The constant will need at least three actions. The lowest
1485 16 bits are clear, so the final action will be a shift. */
1486 return mips_build_shift (codes, value);
1490 /* The final action could be a shift, add or inclusive OR.
1491 Rather than use a complex condition to select the best
1492 approach, try both mips_build_shift and mips_build_lower
1493 and pick the one that gives the shortest sequence.
1494 Note that this case is only used once per constant. */
1495 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1496 unsigned int cost, alt_cost;
1498 cost = mips_build_shift (codes, value);
1499 alt_cost = mips_build_lower (alt_codes, value);
1500 if (alt_cost < cost)
1502 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1509 /* Return true if symbols of type TYPE require a GOT access. */
1512 mips_got_symbol_type_p (enum mips_symbol_type type)
1516 case SYMBOL_GOT_PAGE_OFST:
1517 case SYMBOL_GOT_DISP:
1525 /* Return true if X is a thread-local symbol. */
1528 mips_tls_symbol_p (rtx x)
1530 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1533 /* Return true if SYMBOL_REF X is associated with a global symbol
1534 (in the STB_GLOBAL sense). */
1537 mips_global_symbol_p (const_rtx x)
1539 const_tree decl = SYMBOL_REF_DECL (x);
1542 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1544 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1545 or weak symbols. Relocations in the object file will be against
1546 the target symbol, so it's that symbol's binding that matters here. */
1547 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1550 /* Return true if function X is a libgcc MIPS16 stub function. */
1553 mips16_stub_function_p (const_rtx x)
1555 return (GET_CODE (x) == SYMBOL_REF
1556 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1559 /* Return true if function X is a locally-defined and locally-binding
1563 mips16_local_function_p (const_rtx x)
1565 return (GET_CODE (x) == SYMBOL_REF
1566 && SYMBOL_REF_LOCAL_P (x)
1567 && !SYMBOL_REF_EXTERNAL_P (x)
1568 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1571 /* Return true if SYMBOL_REF X binds locally. */
1574 mips_symbol_binds_local_p (const_rtx x)
1576 return (SYMBOL_REF_DECL (x)
1577 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1578 : SYMBOL_REF_LOCAL_P (x));
1581 /* Return true if rtx constants of mode MODE should be put into a small
1585 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1587 return (!TARGET_EMBEDDED_DATA
1588 && TARGET_LOCAL_SDATA
1589 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1592 /* Return true if X should not be moved directly into register $25.
1593 We need this because many versions of GAS will treat "la $25,foo" as
1594 part of a call sequence and so allow a global "foo" to be lazily bound. */
1597 mips_dangerous_for_la25_p (rtx x)
1599 return (!TARGET_EXPLICIT_RELOCS
1601 && GET_CODE (x) == SYMBOL_REF
1602 && mips_global_symbol_p (x));
1605 /* Return true if calls to X might need $25 to be valid on entry. */
1608 mips_use_pic_fn_addr_reg_p (const_rtx x)
1610 if (!TARGET_USE_PIC_FN_ADDR_REG)
1613 /* MIPS16 stub functions are guaranteed not to use $25. */
1614 if (mips16_stub_function_p (x))
1617 if (GET_CODE (x) == SYMBOL_REF)
1619 /* If PLTs and copy relocations are available, the static linker
1620 will make sure that $25 is valid on entry to the target function. */
1621 if (TARGET_ABICALLS_PIC0)
1624 /* Locally-defined functions use absolute accesses to set up
1625 the global pointer. */
1626 if (TARGET_ABSOLUTE_ABICALLS
1627 && mips_symbol_binds_local_p (x)
1628 && !SYMBOL_REF_EXTERNAL_P (x))
1635 /* Return the method that should be used to access SYMBOL_REF or
1636 LABEL_REF X in context CONTEXT. */
1638 static enum mips_symbol_type
1639 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1642 return SYMBOL_GOT_DISP;
1644 if (GET_CODE (x) == LABEL_REF)
1646 /* LABEL_REFs are used for jump tables as well as text labels.
1647 Only return SYMBOL_PC_RELATIVE if we know the label is in
1648 the text section. */
1649 if (TARGET_MIPS16_SHORT_JUMP_TABLES)
1650 return SYMBOL_PC_RELATIVE;
1652 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1653 return SYMBOL_GOT_PAGE_OFST;
1655 return SYMBOL_ABSOLUTE;
1658 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1660 if (SYMBOL_REF_TLS_MODEL (x))
1663 if (CONSTANT_POOL_ADDRESS_P (x))
1665 if (TARGET_MIPS16_TEXT_LOADS)
1666 return SYMBOL_PC_RELATIVE;
1668 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1669 return SYMBOL_PC_RELATIVE;
1671 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1672 return SYMBOL_GP_RELATIVE;
1675 /* Do not use small-data accesses for weak symbols; they may end up
1677 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1678 return SYMBOL_GP_RELATIVE;
1680 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1682 if (TARGET_ABICALLS_PIC2
1683 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1685 /* There are three cases to consider:
1687 - o32 PIC (either with or without explicit relocs)
1688 - n32/n64 PIC without explicit relocs
1689 - n32/n64 PIC with explicit relocs
1691 In the first case, both local and global accesses will use an
1692 R_MIPS_GOT16 relocation. We must correctly predict which of
1693 the two semantics (local or global) the assembler and linker
1694 will apply. The choice depends on the symbol's binding rather
1695 than its visibility.
1697 In the second case, the assembler will not use R_MIPS_GOT16
1698 relocations, but it chooses between local and global accesses
1699 in the same way as for o32 PIC.
1701 In the third case we have more freedom since both forms of
1702 access will work for any kind of symbol. However, there seems
1703 little point in doing things differently. */
1704 if (mips_global_symbol_p (x))
1705 return SYMBOL_GOT_DISP;
1707 return SYMBOL_GOT_PAGE_OFST;
1710 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1711 return SYMBOL_FORCE_TO_MEM;
1713 return SYMBOL_ABSOLUTE;
1716 /* Classify the base of symbolic expression X, given that X appears in
1719 static enum mips_symbol_type
1720 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1724 split_const (x, &x, &offset);
1725 if (UNSPEC_ADDRESS_P (x))
1726 return UNSPEC_ADDRESS_TYPE (x);
1728 return mips_classify_symbol (x, context);
1731 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1732 is the alignment in bytes of SYMBOL_REF X. */
1735 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1737 HOST_WIDE_INT align;
1739 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1740 return IN_RANGE (offset, 0, align - 1);
1743 /* Return true if X is a symbolic constant that can be used in context
1744 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1747 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1748 enum mips_symbol_type *symbol_type)
1752 split_const (x, &x, &offset);
1753 if (UNSPEC_ADDRESS_P (x))
1755 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1756 x = UNSPEC_ADDRESS (x);
1758 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1760 *symbol_type = mips_classify_symbol (x, context);
1761 if (*symbol_type == SYMBOL_TLS)
1767 if (offset == const0_rtx)
1770 /* Check whether a nonzero offset is valid for the underlying
1772 switch (*symbol_type)
1774 case SYMBOL_ABSOLUTE:
1775 case SYMBOL_FORCE_TO_MEM:
1776 case SYMBOL_32_HIGH:
1777 case SYMBOL_64_HIGH:
1780 /* If the target has 64-bit pointers and the object file only
1781 supports 32-bit symbols, the values of those symbols will be
1782 sign-extended. In this case we can't allow an arbitrary offset
1783 in case the 32-bit value X + OFFSET has a different sign from X. */
1784 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1785 return offset_within_block_p (x, INTVAL (offset));
1787 /* In other cases the relocations can handle any offset. */
1790 case SYMBOL_PC_RELATIVE:
1791 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1792 In this case, we no longer have access to the underlying constant,
1793 but the original symbol-based access was known to be valid. */
1794 if (GET_CODE (x) == LABEL_REF)
1799 case SYMBOL_GP_RELATIVE:
1800 /* Make sure that the offset refers to something within the
1801 same object block. This should guarantee that the final
1802 PC- or GP-relative offset is within the 16-bit limit. */
1803 return offset_within_block_p (x, INTVAL (offset));
1805 case SYMBOL_GOT_PAGE_OFST:
1806 case SYMBOL_GOTOFF_PAGE:
1807 /* If the symbol is global, the GOT entry will contain the symbol's
1808 address, and we will apply a 16-bit offset after loading it.
1809 If the symbol is local, the linker should provide enough local
1810 GOT entries for a 16-bit offset, but larger offsets may lead
1812 return SMALL_INT (offset);
1816 /* There is no carry between the HI and LO REL relocations, so the
1817 offset is only valid if we know it won't lead to such a carry. */
1818 return mips_offset_within_alignment_p (x, INTVAL (offset));
1820 case SYMBOL_GOT_DISP:
1821 case SYMBOL_GOTOFF_DISP:
1822 case SYMBOL_GOTOFF_CALL:
1823 case SYMBOL_GOTOFF_LOADGP:
1826 case SYMBOL_GOTTPREL:
1834 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1835 single instruction. We rely on the fact that, in the worst case,
1836 all instructions involved in a MIPS16 address calculation are usually
1840 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1844 case SYMBOL_ABSOLUTE:
1845 /* When using 64-bit symbols, we need 5 preparatory instructions,
1848 lui $at,%highest(symbol)
1849 daddiu $at,$at,%higher(symbol)
1851 daddiu $at,$at,%hi(symbol)
1854 The final address is then $at + %lo(symbol). With 32-bit
1855 symbols we just need a preparatory LUI for normal mode and
1856 a preparatory LI and SLL for MIPS16. */
1857 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1859 case SYMBOL_GP_RELATIVE:
1860 /* Treat GP-relative accesses as taking a single instruction on
1861 MIPS16 too; the copy of $gp can often be shared. */
1864 case SYMBOL_PC_RELATIVE:
1865 /* PC-relative constants can be only be used with ADDIUPC,
1866 DADDIUPC, LWPC and LDPC. */
1867 if (mode == MAX_MACHINE_MODE
1868 || GET_MODE_SIZE (mode) == 4
1869 || GET_MODE_SIZE (mode) == 8)
1872 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1875 case SYMBOL_FORCE_TO_MEM:
1876 /* LEAs will be converted into constant-pool references by
1878 if (mode == MAX_MACHINE_MODE)
1881 /* The constant must be loaded and then dereferenced. */
1884 case SYMBOL_GOT_DISP:
1885 /* The constant will have to be loaded from the GOT before it
1886 is used in an address. */
1887 if (mode != MAX_MACHINE_MODE)
1892 case SYMBOL_GOT_PAGE_OFST:
1893 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1894 local/global classification is accurate. The worst cases are:
1896 (1) For local symbols when generating o32 or o64 code. The assembler
1902 ...and the final address will be $at + %lo(symbol).
1904 (2) For global symbols when -mxgot. The assembler will use:
1906 lui $at,%got_hi(symbol)
1909 ...and the final address will be $at + %got_lo(symbol). */
1912 case SYMBOL_GOTOFF_PAGE:
1913 case SYMBOL_GOTOFF_DISP:
1914 case SYMBOL_GOTOFF_CALL:
1915 case SYMBOL_GOTOFF_LOADGP:
1916 case SYMBOL_32_HIGH:
1917 case SYMBOL_64_HIGH:
1923 case SYMBOL_GOTTPREL:
1926 /* A 16-bit constant formed by a single relocation, or a 32-bit
1927 constant formed from a high 16-bit relocation and a low 16-bit
1928 relocation. Use mips_split_p to determine which. 32-bit
1929 constants need an "lui; addiu" sequence for normal mode and
1930 an "li; sll; addiu" sequence for MIPS16 mode. */
1931 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1934 /* We don't treat a bare TLS symbol as a constant. */
1940 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1941 to load symbols of type TYPE into a register. Return 0 if the given
1942 type of symbol cannot be used as an immediate operand.
1944 Otherwise, return the number of instructions needed to load or store
1945 values of mode MODE to or from addresses of type TYPE. Return 0 if
1946 the given type of symbol is not valid in addresses.
1948 In both cases, treat extended MIPS16 instructions as two instructions. */
1951 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1953 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1956 /* A for_each_rtx callback. Stop the search if *X references a
1957 thread-local symbol. */
1960 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1962 return mips_tls_symbol_p (*x);
1965 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1968 mips_cannot_force_const_mem (rtx x)
1970 enum mips_symbol_type type;
1973 /* There is no assembler syntax for expressing an address-sized
1975 if (GET_CODE (x) == HIGH)
1978 /* As an optimization, reject constants that mips_legitimize_move
1981 Suppose we have a multi-instruction sequence that loads constant C
1982 into register R. If R does not get allocated a hard register, and
1983 R is used in an operand that allows both registers and memory
1984 references, reload will consider forcing C into memory and using
1985 one of the instruction's memory alternatives. Returning false
1986 here will force it to use an input reload instead. */
1987 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
1990 split_const (x, &base, &offset);
1991 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
1992 && type != SYMBOL_FORCE_TO_MEM)
1994 /* The same optimization as for CONST_INT. */
1995 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1998 /* If MIPS16 constant pools live in the text section, they should
1999 not refer to anything that might need run-time relocation. */
2000 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2004 /* TLS symbols must be computed by mips_legitimize_move. */
2005 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2011 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2012 constants when we're using a per-function constant pool. */
2015 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2016 const_rtx x ATTRIBUTE_UNUSED)
2018 return !TARGET_MIPS16_PCREL_LOADS;
2021 /* Return true if register REGNO is a valid base register for mode MODE.
2022 STRICT_P is true if REG_OK_STRICT is in effect. */
2025 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2028 if (!HARD_REGISTER_NUM_P (regno))
2032 regno = reg_renumber[regno];
2035 /* These fake registers will be eliminated to either the stack or
2036 hard frame pointer, both of which are usually valid base registers.
2037 Reload deals with the cases where the eliminated form isn't valid. */
2038 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2041 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2042 values, nothing smaller. There are two problems here:
2044 (a) Instantiating virtual registers can introduce new uses of the
2045 stack pointer. If these virtual registers are valid addresses,
2046 the stack pointer should be too.
2048 (b) Most uses of the stack pointer are not made explicit until
2049 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2050 We don't know until that stage whether we'll be eliminating to the
2051 stack pointer (which needs the restriction) or the hard frame
2052 pointer (which doesn't).
2054 All in all, it seems more consistent to only enforce this restriction
2055 during and after reload. */
2056 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2057 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2059 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2062 /* Return true if X is a valid base register for mode MODE.
2063 STRICT_P is true if REG_OK_STRICT is in effect. */
2066 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2068 if (!strict_p && GET_CODE (x) == SUBREG)
2072 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2075 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2076 can address a value of mode MODE. */
2079 mips_valid_offset_p (rtx x, enum machine_mode mode)
2081 /* Check that X is a signed 16-bit number. */
2082 if (!const_arith_operand (x, Pmode))
2085 /* We may need to split multiword moves, so make sure that every word
2087 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2088 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2094 /* Return true if a LO_SUM can address a value of mode MODE when the
2095 LO_SUM symbol has type SYMBOL_TYPE. */
2098 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2100 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2102 if (mips_symbol_insns (symbol_type, mode) == 0)
2105 /* Check that there is a known low-part relocation. */
2106 if (mips_lo_relocs[symbol_type] == NULL)
2109 /* We may need to split multiword moves, so make sure that each word
2110 can be accessed without inducing a carry. This is mainly needed
2111 for o64, which has historically only guaranteed 64-bit alignment
2112 for 128-bit types. */
2113 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2114 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2120 /* Return true if X is a valid address for machine mode MODE. If it is,
2121 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2125 mips_classify_address (struct mips_address_info *info, rtx x,
2126 enum machine_mode mode, bool strict_p)
2128 switch (GET_CODE (x))
2132 info->type = ADDRESS_REG;
2134 info->offset = const0_rtx;
2135 return mips_valid_base_register_p (info->reg, mode, strict_p);
2138 info->type = ADDRESS_REG;
2139 info->reg = XEXP (x, 0);
2140 info->offset = XEXP (x, 1);
2141 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2142 && mips_valid_offset_p (info->offset, mode));
2145 info->type = ADDRESS_LO_SUM;
2146 info->reg = XEXP (x, 0);
2147 info->offset = XEXP (x, 1);
2148 /* We have to trust the creator of the LO_SUM to do something vaguely
2149 sane. Target-independent code that creates a LO_SUM should also
2150 create and verify the matching HIGH. Target-independent code that
2151 adds an offset to a LO_SUM must prove that the offset will not
2152 induce a carry. Failure to do either of these things would be
2153 a bug, and we are not required to check for it here. The MIPS
2154 backend itself should only create LO_SUMs for valid symbolic
2155 constants, with the high part being either a HIGH or a copy
2158 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2159 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2160 && mips_valid_lo_sum_p (info->symbol_type, mode));
2163 /* Small-integer addresses don't occur very often, but they
2164 are legitimate if $0 is a valid base register. */
2165 info->type = ADDRESS_CONST_INT;
2166 return !TARGET_MIPS16 && SMALL_INT (x);
2171 info->type = ADDRESS_SYMBOLIC;
2172 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2174 && mips_symbol_insns (info->symbol_type, mode) > 0
2175 && !mips_split_p[info->symbol_type]);
2182 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2185 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2187 struct mips_address_info addr;
2189 return mips_classify_address (&addr, x, mode, strict_p);
2192 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2195 mips_stack_address_p (rtx x, enum machine_mode mode)
2197 struct mips_address_info addr;
2199 return (mips_classify_address (&addr, x, mode, false)
2200 && addr.type == ADDRESS_REG
2201 && addr.reg == stack_pointer_rtx);
2204 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2205 address instruction. Note that such addresses are not considered
2206 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2207 is so restricted. */
2210 mips_lwxs_address_p (rtx addr)
2213 && GET_CODE (addr) == PLUS
2214 && REG_P (XEXP (addr, 1)))
2216 rtx offset = XEXP (addr, 0);
2217 if (GET_CODE (offset) == MULT
2218 && REG_P (XEXP (offset, 0))
2219 && CONST_INT_P (XEXP (offset, 1))
2220 && INTVAL (XEXP (offset, 1)) == 4)
2226 /* Return true if a value at OFFSET bytes from base register BASE can be
2227 accessed using an unextended MIPS16 instruction. MODE is the mode of
2230 Usually the offset in an unextended instruction is a 5-bit field.
2231 The offset is unsigned and shifted left once for LH and SH, twice
2232 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2233 an 8-bit immediate field that's shifted left twice. */
2236 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2237 unsigned HOST_WIDE_INT offset)
2239 if (offset % GET_MODE_SIZE (mode) == 0)
2241 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2242 return offset < 256U * GET_MODE_SIZE (mode);
2243 return offset < 32U * GET_MODE_SIZE (mode);
2248 /* Return the number of instructions needed to load or store a value
2249 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2250 Assume that multiword moves may need to be split into word moves
2251 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2254 For MIPS16 code, count extended instructions as two instructions. */
2257 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2259 struct mips_address_info addr;
2262 /* BLKmode is used for single unaligned loads and stores and should
2263 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2264 meaningless, so we have to single it out as a special case one way
2266 if (mode != BLKmode && might_split_p)
2267 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2271 if (mips_classify_address (&addr, x, mode, false))
2276 && !mips16_unextended_reference_p (mode, addr.reg,
2277 UINTVAL (addr.offset)))
2281 case ADDRESS_LO_SUM:
2282 return TARGET_MIPS16 ? factor * 2 : factor;
2284 case ADDRESS_CONST_INT:
2287 case ADDRESS_SYMBOLIC:
2288 return factor * mips_symbol_insns (addr.symbol_type, mode);
2293 /* Return the number of instructions needed to load constant X.
2294 Return 0 if X isn't a valid constant. */
2297 mips_const_insns (rtx x)
2299 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2300 enum mips_symbol_type symbol_type;
2303 switch (GET_CODE (x))
2306 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2308 || !mips_split_p[symbol_type])
2311 /* This is simply an LUI for normal mode. It is an extended
2312 LI followed by an extended SLL for MIPS16. */
2313 return TARGET_MIPS16 ? 4 : 1;
2317 /* Unsigned 8-bit constants can be loaded using an unextended
2318 LI instruction. Unsigned 16-bit constants can be loaded
2319 using an extended LI. Negative constants must be loaded
2320 using LI and then negated. */
2321 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2322 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2323 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2324 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2327 return mips_build_integer (codes, INTVAL (x));
2331 /* Allow zeros for normal mode, where we can use $0. */
2332 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2338 /* See if we can refer to X directly. */
2339 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2340 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2342 /* Otherwise try splitting the constant into a base and offset.
2343 If the offset is a 16-bit value, we can load the base address
2344 into a register and then use (D)ADDIU to add in the offset.
2345 If the offset is larger, we can load the base and offset
2346 into separate registers and add them together with (D)ADDU.
2347 However, the latter is only possible before reload; during
2348 and after reload, we must have the option of forcing the
2349 constant into the pool instead. */
2350 split_const (x, &x, &offset);
2353 int n = mips_const_insns (x);
2356 if (SMALL_INT (offset))
2358 else if (!targetm.cannot_force_const_mem (x))
2359 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2366 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2374 /* X is a doubleword constant that can be handled by splitting it into
2375 two words and loading each word separately. Return the number of
2376 instructions required to do this. */
2379 mips_split_const_insns (rtx x)
2381 unsigned int low, high;
2383 low = mips_const_insns (mips_subword (x, false));
2384 high = mips_const_insns (mips_subword (x, true));
2385 gcc_assert (low > 0 && high > 0);
2389 /* Return the number of instructions needed to implement INSN,
2390 given that it loads from or stores to MEM. Count extended
2391 MIPS16 instructions as two instructions. */
2394 mips_load_store_insns (rtx mem, rtx insn)
2396 enum machine_mode mode;
2400 gcc_assert (MEM_P (mem));
2401 mode = GET_MODE (mem);
2403 /* Try to prove that INSN does not need to be split. */
2404 might_split_p = true;
2405 if (GET_MODE_BITSIZE (mode) == 64)
2407 set = single_set (insn);
2408 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2409 might_split_p = false;
2412 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2415 /* Return the number of instructions needed for an integer division. */
2418 mips_idiv_insns (void)
2423 if (TARGET_CHECK_ZERO_DIV)
2425 if (GENERATE_DIVIDE_TRAPS)
2431 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2436 /* Emit a move from SRC to DEST. Assume that the move expanders can
2437 handle all moves if !can_create_pseudo_p (). The distinction is
2438 important because, unlike emit_move_insn, the move expanders know
2439 how to force Pmode objects into the constant pool even when the
2440 constant pool address is not itself legitimate. */
2443 mips_emit_move (rtx dest, rtx src)
2445 return (can_create_pseudo_p ()
2446 ? emit_move_insn (dest, src)
2447 : emit_move_insn_1 (dest, src));
2450 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2453 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2455 emit_insn (gen_rtx_SET (VOIDmode, target,
2456 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2459 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2460 Return that new register. */
2463 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2467 reg = gen_reg_rtx (mode);
2468 mips_emit_unary (code, reg, op0);
2472 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2475 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2477 emit_insn (gen_rtx_SET (VOIDmode, target,
2478 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2481 /* Compute (CODE OP0 OP1) and store the result in a new register
2482 of mode MODE. Return that new register. */
2485 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2489 reg = gen_reg_rtx (mode);
2490 mips_emit_binary (code, reg, op0, op1);
2494 /* Copy VALUE to a register and return that register. If new pseudos
2495 are allowed, copy it into a new register, otherwise use DEST. */
2498 mips_force_temporary (rtx dest, rtx value)
2500 if (can_create_pseudo_p ())
2501 return force_reg (Pmode, value);
2504 mips_emit_move (dest, value);
2509 /* Emit a call sequence with call pattern PATTERN and return the call
2510 instruction itself (which is not necessarily the last instruction
2511 emitted). ORIG_ADDR is the original, unlegitimized address,
2512 ADDR is the legitimized form, and LAZY_P is true if the call
2513 address is lazily-bound. */
2516 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2520 insn = emit_call_insn (pattern);
2522 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2524 /* MIPS16 JALRs only take MIPS16 registers. If the target
2525 function requires $25 to be valid on entry, we must copy it
2526 there separately. The move instruction can be put in the
2527 call's delay slot. */
2528 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2529 emit_insn_before (gen_move_insn (reg, addr), insn);
2530 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2534 /* Lazy-binding stubs require $gp to be valid on entry. */
2535 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2539 /* See the comment above load_call<mode> for details. */
2540 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2541 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2542 emit_insn (gen_update_got_version ());
2547 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2548 then add CONST_INT OFFSET to the result. */
2551 mips_unspec_address_offset (rtx base, rtx offset,
2552 enum mips_symbol_type symbol_type)
2554 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2555 UNSPEC_ADDRESS_FIRST + symbol_type);
2556 if (offset != const0_rtx)
2557 base = gen_rtx_PLUS (Pmode, base, offset);
2558 return gen_rtx_CONST (Pmode, base);
2561 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2562 type SYMBOL_TYPE. */
2565 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2569 split_const (address, &base, &offset);
2570 return mips_unspec_address_offset (base, offset, symbol_type);
2573 /* If OP is an UNSPEC address, return the address to which it refers,
2574 otherwise return OP itself. */
2577 mips_strip_unspec_address (rtx op)
2581 split_const (op, &base, &offset);
2582 if (UNSPEC_ADDRESS_P (base))
2583 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2587 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2588 high part to BASE and return the result. Just return BASE otherwise.
2589 TEMP is as for mips_force_temporary.
2591 The returned expression can be used as the first operand to a LO_SUM. */
2594 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2595 enum mips_symbol_type symbol_type)
2597 if (mips_split_p[symbol_type])
2599 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2600 addr = mips_force_temporary (temp, addr);
2601 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2606 /* Return an instruction that copies $gp into register REG. We want
2607 GCC to treat the register's value as constant, so that its value
2608 can be rematerialized on demand. */
2611 gen_load_const_gp (rtx reg)
2613 return (Pmode == SImode
2614 ? gen_load_const_gp_si (reg)
2615 : gen_load_const_gp_di (reg));
2618 /* Return a pseudo register that contains the value of $gp throughout
2619 the current function. Such registers are needed by MIPS16 functions,
2620 for which $gp itself is not a valid base register or addition operand. */
2623 mips16_gp_pseudo_reg (void)
2625 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2626 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2628 /* Don't emit an instruction to initialize the pseudo register if
2629 we are being called from the tree optimizers' cost-calculation
2631 if (!cfun->machine->initialized_mips16_gp_pseudo_p
2632 && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl))
2636 push_topmost_sequence ();
2638 scan = get_insns ();
2639 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2640 scan = NEXT_INSN (scan);
2642 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2643 emit_insn_after (insn, scan);
2645 pop_topmost_sequence ();
2647 cfun->machine->initialized_mips16_gp_pseudo_p = true;
2650 return cfun->machine->mips16_gp_pseudo_rtx;
2653 /* Return a base register that holds pic_offset_table_rtx.
2654 TEMP, if nonnull, is a scratch Pmode base register. */
2657 mips_pic_base_register (rtx temp)
2660 return pic_offset_table_rtx;
2662 if (can_create_pseudo_p ())
2663 return mips16_gp_pseudo_reg ();
2666 /* The first post-reload split exposes all references to $gp
2667 (both uses and definitions). All references must remain
2668 explicit after that point.
2670 It is safe to introduce uses of $gp at any time, so for
2671 simplicity, we do that before the split too. */
2672 mips_emit_move (temp, pic_offset_table_rtx);
2674 emit_insn (gen_load_const_gp (temp));
2678 /* Return the RHS of a load_call<mode> insn. */
2681 mips_unspec_call (rtx reg, rtx symbol)
2685 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2686 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2689 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2690 reference. Return NULL_RTX otherwise. */
2693 mips_strip_unspec_call (rtx src)
2695 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2696 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2700 /* Create and return a GOT reference of type TYPE for address ADDR.
2701 TEMP, if nonnull, is a scratch Pmode base register. */
2704 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2706 rtx base, high, lo_sum_symbol;
2708 base = mips_pic_base_register (temp);
2710 /* If we used the temporary register to load $gp, we can't use
2711 it for the high part as well. */
2712 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2715 high = mips_unspec_offset_high (temp, base, addr, type);
2716 lo_sum_symbol = mips_unspec_address (addr, type);
2718 if (type == SYMBOL_GOTOFF_CALL)
2719 return mips_unspec_call (high, lo_sum_symbol);
2721 return (Pmode == SImode
2722 ? gen_unspec_gotsi (high, lo_sum_symbol)
2723 : gen_unspec_gotdi (high, lo_sum_symbol));
2726 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2727 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2728 constant in that context and can be split into high and low parts.
2729 If so, and if LOW_OUT is nonnull, emit the high part and store the
2730 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2732 TEMP is as for mips_force_temporary and is used to load the high
2733 part into a register.
2735 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2736 a legitimize SET_SRC for an .md pattern, otherwise the low part
2737 is guaranteed to be a legitimate address for mode MODE. */
2740 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2742 enum mips_symbol_context context;
2743 enum mips_symbol_type symbol_type;
2746 context = (mode == MAX_MACHINE_MODE
2747 ? SYMBOL_CONTEXT_LEA
2748 : SYMBOL_CONTEXT_MEM);
2749 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2751 addr = XEXP (addr, 0);
2752 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2753 && mips_symbol_insns (symbol_type, mode) > 0
2754 && mips_split_hi_p[symbol_type])
2757 switch (symbol_type)
2759 case SYMBOL_GOT_PAGE_OFST:
2760 /* The high part of a page/ofst pair is loaded from the GOT. */
2761 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2772 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2773 && mips_symbol_insns (symbol_type, mode) > 0
2774 && mips_split_p[symbol_type])
2777 switch (symbol_type)
2779 case SYMBOL_GOT_DISP:
2780 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2781 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2784 case SYMBOL_GP_RELATIVE:
2785 high = mips_pic_base_register (temp);
2786 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2790 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2791 high = mips_force_temporary (temp, high);
2792 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2801 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2802 mips_force_temporary; it is only needed when OFFSET is not a
2806 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2808 if (!SMALL_OPERAND (offset))
2814 /* Load the full offset into a register so that we can use
2815 an unextended instruction for the address itself. */
2816 high = GEN_INT (offset);
2821 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2822 The addition inside the macro CONST_HIGH_PART may cause an
2823 overflow, so we need to force a sign-extension check. */
2824 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2825 offset = CONST_LOW_PART (offset);
2827 high = mips_force_temporary (temp, high);
2828 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2830 return plus_constant (reg, offset);
2833 /* The __tls_get_attr symbol. */
2834 static GTY(()) rtx mips_tls_symbol;
2836 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2837 the TLS symbol we are referencing and TYPE is the symbol type to use
2838 (either global dynamic or local dynamic). V0 is an RTX for the
2839 return value location. */
2842 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2846 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2848 if (!mips_tls_symbol)
2849 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2851 loc = mips_unspec_address (sym, type);
2855 emit_insn (gen_rtx_SET (Pmode, a0,
2856 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2857 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2858 const0_rtx, NULL_RTX, false);
2859 RTL_CONST_CALL_P (insn) = 1;
2860 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2861 insn = get_insns ();
2868 /* Return a pseudo register that contains the current thread pointer. */
2875 tp = gen_reg_rtx (Pmode);
2876 if (Pmode == DImode)
2877 emit_insn (gen_tls_get_tp_di (tp));
2879 emit_insn (gen_tls_get_tp_si (tp));
2883 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2884 its address. The return value will be both a valid address and a valid
2885 SET_SRC (either a REG or a LO_SUM). */
2888 mips_legitimize_tls_address (rtx loc)
2890 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2891 enum tls_model model;
2895 sorry ("MIPS16 TLS");
2896 return gen_reg_rtx (Pmode);
2899 model = SYMBOL_REF_TLS_MODEL (loc);
2900 /* Only TARGET_ABICALLS code can have more than one module; other
2901 code must be be static and should not use a GOT. All TLS models
2902 reduce to local exec in this situation. */
2903 if (!TARGET_ABICALLS)
2904 model = TLS_MODEL_LOCAL_EXEC;
2908 case TLS_MODEL_GLOBAL_DYNAMIC:
2909 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2910 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2911 dest = gen_reg_rtx (Pmode);
2912 emit_libcall_block (insn, dest, v0, loc);
2915 case TLS_MODEL_LOCAL_DYNAMIC:
2916 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2917 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2918 tmp1 = gen_reg_rtx (Pmode);
2920 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2921 share the LDM result with other LD model accesses. */
2922 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2924 emit_libcall_block (insn, tmp1, v0, eqv);
2926 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2927 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2928 mips_unspec_address (loc, SYMBOL_DTPREL));
2931 case TLS_MODEL_INITIAL_EXEC:
2932 tp = mips_get_tp ();
2933 tmp1 = gen_reg_rtx (Pmode);
2934 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2935 if (Pmode == DImode)
2936 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2938 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2939 dest = gen_reg_rtx (Pmode);
2940 emit_insn (gen_add3_insn (dest, tmp1, tp));
2943 case TLS_MODEL_LOCAL_EXEC:
2944 tp = mips_get_tp ();
2945 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2946 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2947 mips_unspec_address (loc, SYMBOL_TPREL));
2956 /* If X is not a valid address for mode MODE, force it into a register. */
2959 mips_force_address (rtx x, enum machine_mode mode)
2961 if (!mips_legitimate_address_p (mode, x, false))
2962 x = force_reg (Pmode, x);
2966 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2967 be legitimized in a way that the generic machinery might not expect,
2968 return a new address, otherwise return NULL. MODE is the mode of
2969 the memory being accessed. */
2972 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2973 enum machine_mode mode)
2976 HOST_WIDE_INT offset;
2978 if (mips_tls_symbol_p (x))
2979 return mips_legitimize_tls_address (x);
2981 /* See if the address can split into a high part and a LO_SUM. */
2982 if (mips_split_symbol (NULL, x, mode, &addr))
2983 return mips_force_address (addr, mode);
2985 /* Handle BASE + OFFSET using mips_add_offset. */
2986 mips_split_plus (x, &base, &offset);
2989 if (!mips_valid_base_register_p (base, mode, false))
2990 base = copy_to_mode_reg (Pmode, base);
2991 addr = mips_add_offset (NULL, base, offset);
2992 return mips_force_address (addr, mode);
2998 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3001 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3003 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3004 enum machine_mode mode;
3005 unsigned int i, num_ops;
3008 mode = GET_MODE (dest);
3009 num_ops = mips_build_integer (codes, value);
3011 /* Apply each binary operation to X. Invariant: X is a legitimate
3012 source operand for a SET pattern. */
3013 x = GEN_INT (codes[0].value);
3014 for (i = 1; i < num_ops; i++)
3016 if (!can_create_pseudo_p ())
3018 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3022 x = force_reg (mode, x);
3023 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3026 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3029 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3030 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3034 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3038 /* Split moves of big integers into smaller pieces. */
3039 if (splittable_const_int_operand (src, mode))
3041 mips_move_integer (dest, dest, INTVAL (src));
3045 /* Split moves of symbolic constants into high/low pairs. */
3046 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3048 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3052 /* Generate the appropriate access sequences for TLS symbols. */
3053 if (mips_tls_symbol_p (src))
3055 mips_emit_move (dest, mips_legitimize_tls_address (src));
3059 /* If we have (const (plus symbol offset)), and that expression cannot
3060 be forced into memory, load the symbol first and add in the offset.
3061 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3062 forced into memory, as it usually produces better code. */
3063 split_const (src, &base, &offset);
3064 if (offset != const0_rtx
3065 && (targetm.cannot_force_const_mem (src)
3066 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3068 base = mips_force_temporary (dest, base);
3069 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3073 src = force_const_mem (mode, src);
3075 /* When using explicit relocs, constant pool references are sometimes
3076 not legitimate addresses. */
3077 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3078 mips_emit_move (dest, src);
3081 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3082 sequence that is valid. */
3085 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3087 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3089 mips_emit_move (dest, force_reg (mode, src));
3093 /* We need to deal with constants that would be legitimate
3094 immediate_operands but aren't legitimate move_operands. */
3095 if (CONSTANT_P (src) && !move_operand (src, mode))
3097 mips_legitimize_const_move (mode, dest, src);
3098 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3104 /* Return true if value X in context CONTEXT is a small-data address
3105 that can be rewritten as a LO_SUM. */
3108 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3110 enum mips_symbol_type symbol_type;
3112 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3113 && !mips_split_p[SYMBOL_GP_RELATIVE]
3114 && mips_symbolic_constant_p (x, context, &symbol_type)
3115 && symbol_type == SYMBOL_GP_RELATIVE);
3118 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3119 containing MEM, or null if none. */
3122 mips_small_data_pattern_1 (rtx *loc, void *data)
3124 enum mips_symbol_context context;
3126 if (GET_CODE (*loc) == LO_SUM)
3131 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3136 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3137 return mips_rewrite_small_data_p (*loc, context);
3140 /* Return true if OP refers to small data symbols directly, not through
3144 mips_small_data_pattern_p (rtx op)
3146 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3149 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3150 DATA is the containing MEM, or null if none. */
3153 mips_rewrite_small_data_1 (rtx *loc, void *data)
3155 enum mips_symbol_context context;
3159 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3163 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3164 if (mips_rewrite_small_data_p (*loc, context))
3165 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3167 if (GET_CODE (*loc) == LO_SUM)
3173 /* Rewrite instruction pattern PATTERN so that it refers to small data
3174 using explicit relocations. */
3177 mips_rewrite_small_data (rtx pattern)
3179 pattern = copy_insn (pattern);
3180 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3184 /* We need a lot of little routines to check the range of MIPS16 immediate
3188 m16_check_op (rtx op, int low, int high, int mask)
3190 return (CONST_INT_P (op)
3191 && IN_RANGE (INTVAL (op), low, high)
3192 && (INTVAL (op) & mask) == 0);
3196 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3198 return m16_check_op (op, 0x1, 0x8, 0);
3202 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3204 return m16_check_op (op, -0x8, 0x7, 0);
3208 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3210 return m16_check_op (op, -0x7, 0x8, 0);
3214 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3216 return m16_check_op (op, -0x10, 0xf, 0);
3220 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3222 return m16_check_op (op, -0xf, 0x10, 0);
3226 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3228 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3232 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3234 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3238 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3240 return m16_check_op (op, -0x80, 0x7f, 0);
3244 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3246 return m16_check_op (op, -0x7f, 0x80, 0);
3250 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3252 return m16_check_op (op, 0x0, 0xff, 0);
3256 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3258 return m16_check_op (op, -0xff, 0x0, 0);
3262 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3264 return m16_check_op (op, -0x1, 0xfe, 0);
3268 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3270 return m16_check_op (op, 0x0, 0xff << 2, 3);
3274 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3276 return m16_check_op (op, -0xff << 2, 0x0, 3);
3280 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3282 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3286 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3288 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3291 /* The cost of loading values from the constant pool. It should be
3292 larger than the cost of any constant we want to synthesize inline. */
3293 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3295 /* Return the cost of X when used as an operand to the MIPS16 instruction
3296 that implements CODE. Return -1 if there is no such instruction, or if
3297 X is not a valid immediate operand for it. */
3300 mips16_constant_cost (int code, HOST_WIDE_INT x)
3307 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3308 other shifts are extended. The shift patterns truncate the shift
3309 count to the right size, so there are no out-of-range values. */
3310 if (IN_RANGE (x, 1, 8))
3312 return COSTS_N_INSNS (1);
3315 if (IN_RANGE (x, -128, 127))
3317 if (SMALL_OPERAND (x))
3318 return COSTS_N_INSNS (1);
3322 /* Like LE, but reject the always-true case. */
3326 /* We add 1 to the immediate and use SLT. */
3329 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3332 if (IN_RANGE (x, 0, 255))
3334 if (SMALL_OPERAND_UNSIGNED (x))
3335 return COSTS_N_INSNS (1);
3340 /* Equality comparisons with 0 are cheap. */
3350 /* Return true if there is a non-MIPS16 instruction that implements CODE
3351 and if that instruction accepts X as an immediate operand. */
3354 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3361 /* All shift counts are truncated to a valid constant. */
3366 /* Likewise rotates, if the target supports rotates at all. */
3372 /* These instructions take 16-bit unsigned immediates. */
3373 return SMALL_OPERAND_UNSIGNED (x);
3378 /* These instructions take 16-bit signed immediates. */
3379 return SMALL_OPERAND (x);
3385 /* The "immediate" forms of these instructions are really
3386 implemented as comparisons with register 0. */
3391 /* Likewise, meaning that the only valid immediate operand is 1. */
3395 /* We add 1 to the immediate and use SLT. */
3396 return SMALL_OPERAND (x + 1);
3399 /* Likewise SLTU, but reject the always-true case. */
3400 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3404 /* The bit position and size are immediate operands. */
3405 return ISA_HAS_EXT_INS;
3408 /* By default assume that $0 can be used for 0. */
3413 /* Return the cost of binary operation X, given that the instruction
3414 sequence for a word-sized or smaller operation has cost SINGLE_COST
3415 and that the sequence of a double-word operation has cost DOUBLE_COST.
3416 If SPEED is true, optimize for speed otherwise optimize for size. */
3419 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3423 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3428 + rtx_cost (XEXP (x, 0), SET, speed)
3429 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3432 /* Return the cost of floating-point multiplications of mode MODE. */
3435 mips_fp_mult_cost (enum machine_mode mode)
3437 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3440 /* Return the cost of floating-point divisions of mode MODE. */
3443 mips_fp_div_cost (enum machine_mode mode)
3445 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3448 /* Return the cost of sign-extending OP to mode MODE, not including the
3449 cost of OP itself. */
3452 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3455 /* Extended loads are as cheap as unextended ones. */
3458 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3459 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3462 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3463 /* We can use SEB or SEH. */
3464 return COSTS_N_INSNS (1);
3466 /* We need to use a shift left and a shift right. */
3467 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3470 /* Return the cost of zero-extending OP to mode MODE, not including the
3471 cost of OP itself. */
3474 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3477 /* Extended loads are as cheap as unextended ones. */
3480 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3481 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3482 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3484 if (GENERATE_MIPS16E)
3485 /* We can use ZEB or ZEH. */
3486 return COSTS_N_INSNS (1);
3489 /* We need to load 0xff or 0xffff into a register and use AND. */
3490 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3492 /* We can use ANDI. */
3493 return COSTS_N_INSNS (1);
3496 /* Implement TARGET_RTX_COSTS. */
3499 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3501 enum machine_mode mode = GET_MODE (x);
3502 bool float_mode_p = FLOAT_MODE_P (mode);
3506 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3507 appear in the instruction stream, and the cost of a comparison is
3508 really the cost of the branch or scc condition. At the time of
3509 writing, GCC only uses an explicit outer COMPARE code when optabs
3510 is testing whether a constant is expensive enough to force into a
3511 register. We want optabs to pass such constants through the MIPS
3512 expanders instead, so make all constants very cheap here. */
3513 if (outer_code == COMPARE)
3515 gcc_assert (CONSTANT_P (x));
3523 /* Treat *clear_upper32-style ANDs as having zero cost in the
3524 second operand. The cost is entirely in the first operand.
3526 ??? This is needed because we would otherwise try to CSE
3527 the constant operand. Although that's the right thing for
3528 instructions that continue to be a register operation throughout
3529 compilation, it is disastrous for instructions that could
3530 later be converted into a memory operation. */
3532 && outer_code == AND
3533 && UINTVAL (x) == 0xffffffff)
3541 cost = mips16_constant_cost (outer_code, INTVAL (x));
3550 /* When not optimizing for size, we care more about the cost
3551 of hot code, and hot code is often in a loop. If a constant
3552 operand needs to be forced into a register, we will often be
3553 able to hoist the constant load out of the loop, so the load
3554 should not contribute to the cost. */
3555 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3567 if (force_to_mem_operand (x, VOIDmode))
3569 *total = COSTS_N_INSNS (1);
3572 cost = mips_const_insns (x);
3575 /* If the constant is likely to be stored in a GPR, SETs of
3576 single-insn constants are as cheap as register sets; we
3577 never want to CSE them.
3579 Don't reduce the cost of storing a floating-point zero in
3580 FPRs. If we have a zero in an FPR for other reasons, we
3581 can get better cfg-cleanup and delayed-branch results by
3582 using it consistently, rather than using $0 sometimes and
3583 an FPR at other times. Also, moves between floating-point
3584 registers are sometimes cheaper than (D)MTC1 $0. */
3586 && outer_code == SET
3587 && !(float_mode_p && TARGET_HARD_FLOAT))
3589 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3590 want to CSE the constant itself. It is usually better to
3591 have N copies of the last operation in the sequence and one
3592 shared copy of the other operations. (Note that this is
3593 not true for MIPS16 code, where the final operation in the
3594 sequence is often an extended instruction.)
3596 Also, if we have a CONST_INT, we don't know whether it is
3597 for a word or doubleword operation, so we cannot rely on
3598 the result of mips_build_integer. */
3599 else if (!TARGET_MIPS16
3600 && (outer_code == SET || mode == VOIDmode))
3602 *total = COSTS_N_INSNS (cost);
3605 /* The value will need to be fetched from the constant pool. */
3606 *total = CONSTANT_POOL_COST;
3610 /* If the address is legitimate, return the number of
3611 instructions it needs. */
3613 cost = mips_address_insns (addr, mode, true);
3616 *total = COSTS_N_INSNS (cost + 1);
3619 /* Check for a scaled indexed address. */
3620 if (mips_lwxs_address_p (addr))
3622 *total = COSTS_N_INSNS (2);
3625 /* Otherwise use the default handling. */
3629 *total = COSTS_N_INSNS (6);
3633 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3637 /* Check for a *clear_upper32 pattern and treat it like a zero
3638 extension. See the pattern's comment for details. */
3641 && CONST_INT_P (XEXP (x, 1))
3642 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3644 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3645 + rtx_cost (XEXP (x, 0), SET, speed));
3652 /* Double-word operations use two single-word operations. */
3653 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3662 if (CONSTANT_P (XEXP (x, 1)))
3663 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3666 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3672 *total = mips_cost->fp_add;
3674 *total = COSTS_N_INSNS (4);
3678 /* Low-part immediates need an extended MIPS16 instruction. */
3679 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3680 + rtx_cost (XEXP (x, 0), SET, speed));
3695 /* Branch comparisons have VOIDmode, so use the first operand's
3697 mode = GET_MODE (XEXP (x, 0));
3698 if (FLOAT_MODE_P (mode))
3700 *total = mips_cost->fp_add;
3703 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3709 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3710 && TARGET_FUSED_MADD
3711 && !HONOR_NANS (mode)
3712 && !HONOR_SIGNED_ZEROS (mode))
3714 /* See if we can use NMADD or NMSUB. See mips.md for the
3715 associated patterns. */
3716 rtx op0 = XEXP (x, 0);
3717 rtx op1 = XEXP (x, 1);
3718 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3720 *total = (mips_fp_mult_cost (mode)
3721 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3722 + rtx_cost (XEXP (op0, 1), SET, speed)
3723 + rtx_cost (op1, SET, speed));
3726 if (GET_CODE (op1) == MULT)
3728 *total = (mips_fp_mult_cost (mode)
3729 + rtx_cost (op0, SET, speed)
3730 + rtx_cost (XEXP (op1, 0), SET, speed)
3731 + rtx_cost (XEXP (op1, 1), SET, speed));
3740 /* If this is part of a MADD or MSUB, treat the PLUS as
3743 && TARGET_FUSED_MADD
3744 && GET_CODE (XEXP (x, 0)) == MULT)
3747 *total = mips_cost->fp_add;
3751 /* Double-word operations require three single-word operations and
3752 an SLTU. The MIPS16 version then needs to move the result of
3753 the SLTU from $24 to a MIPS16 register. */
3754 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3755 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3761 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3762 && TARGET_FUSED_MADD
3763 && !HONOR_NANS (mode)
3764 && HONOR_SIGNED_ZEROS (mode))
3766 /* See if we can use NMADD or NMSUB. See mips.md for the
3767 associated patterns. */
3768 rtx op = XEXP (x, 0);
3769 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3770 && GET_CODE (XEXP (op, 0)) == MULT)
3772 *total = (mips_fp_mult_cost (mode)
3773 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3774 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3775 + rtx_cost (XEXP (op, 1), SET, speed));
3781 *total = mips_cost->fp_add;
3783 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3788 *total = mips_fp_mult_cost (mode);
3789 else if (mode == DImode && !TARGET_64BIT)
3790 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3791 where the mulsidi3 always includes an MFHI and an MFLO. */
3793 ? mips_cost->int_mult_si * 3 + 6
3794 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3796 *total = (ISA_HAS_MUL3 ? 1 : 2);
3797 else if (mode == DImode)
3798 *total = mips_cost->int_mult_di;
3800 *total = mips_cost->int_mult_si;
3804 /* Check for a reciprocal. */
3807 && flag_unsafe_math_optimizations
3808 && XEXP (x, 0) == CONST1_RTX (mode))
3810 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3811 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3812 division as being free. */
3813 *total = rtx_cost (XEXP (x, 1), SET, speed);
3815 *total = (mips_fp_div_cost (mode)
3816 + rtx_cost (XEXP (x, 1), SET, speed));
3825 *total = mips_fp_div_cost (mode);
3834 /* It is our responsibility to make division by a power of 2
3835 as cheap as 2 register additions if we want the division
3836 expanders to be used for such operations; see the setting
3837 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3838 should always produce shorter code than using
3839 expand_sdiv2_pow2. */
3841 && CONST_INT_P (XEXP (x, 1))
3842 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3844 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3847 *total = COSTS_N_INSNS (mips_idiv_insns ());
3849 else if (mode == DImode)
3850 *total = mips_cost->int_div_di;
3852 *total = mips_cost->int_div_si;
3856 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3860 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3864 case UNSIGNED_FLOAT:
3867 case FLOAT_TRUNCATE:
3868 *total = mips_cost->fp_add;
3876 /* Implement TARGET_ADDRESS_COST. */
3879 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3881 return mips_address_insns (addr, SImode, false);
3884 /* Information about a single instruction in a multi-instruction
3886 struct mips_multi_member {
3887 /* True if this is a label, false if it is code. */
3890 /* The output_asm_insn format of the instruction. */
3893 /* The operands to the instruction. */
3894 rtx operands[MAX_RECOG_OPERANDS];
3896 typedef struct mips_multi_member mips_multi_member;
3898 /* Vector definitions for the above. */
3899 DEF_VEC_O(mips_multi_member);
3900 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3902 /* The instructions that make up the current multi-insn sequence. */
3903 static VEC (mips_multi_member, heap) *mips_multi_members;
3905 /* How many instructions (as opposed to labels) are in the current
3906 multi-insn sequence. */
3907 static unsigned int mips_multi_num_insns;
3909 /* Start a new multi-insn sequence. */
3912 mips_multi_start (void)
3914 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3915 mips_multi_num_insns = 0;
3918 /* Add a new, uninitialized member to the current multi-insn sequence. */
3920 static struct mips_multi_member *
3921 mips_multi_add (void)
3923 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3926 /* Add a normal insn with the given asm format to the current multi-insn
3927 sequence. The other arguments are a null-terminated list of operands. */
3930 mips_multi_add_insn (const char *format, ...)
3932 struct mips_multi_member *member;
3937 member = mips_multi_add ();
3938 member->is_label_p = false;
3939 member->format = format;
3940 va_start (ap, format);
3942 while ((op = va_arg (ap, rtx)))
3943 member->operands[i++] = op;
3945 mips_multi_num_insns++;
3948 /* Add the given label definition to the current multi-insn sequence.
3949 The definition should include the colon. */
3952 mips_multi_add_label (const char *label)
3954 struct mips_multi_member *member;
3956 member = mips_multi_add ();
3957 member->is_label_p = true;
3958 member->format = label;
3961 /* Return the index of the last member of the current multi-insn sequence. */
3964 mips_multi_last_index (void)
3966 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3969 /* Add a copy of an existing instruction to the current multi-insn
3970 sequence. I is the index of the instruction that should be copied. */
3973 mips_multi_copy_insn (unsigned int i)
3975 struct mips_multi_member *member;
3977 member = mips_multi_add ();
3978 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
3980 gcc_assert (!member->is_label_p);
3983 /* Change the operand of an existing instruction in the current
3984 multi-insn sequence. I is the index of the instruction,
3985 OP is the index of the operand, and X is the new value. */
3988 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
3990 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
3993 /* Write out the asm code for the current multi-insn sequence. */
3996 mips_multi_write (void)
3998 struct mips_multi_member *member;
4002 VEC_iterate (mips_multi_member, mips_multi_members, i, member);
4004 if (member->is_label_p)
4005 fprintf (asm_out_file, "%s\n", member->format);
4007 output_asm_insn (member->format, member->operands);
4010 /* Return one word of double-word value OP, taking into account the fixed
4011 endianness of certain registers. HIGH_P is true to select the high part,
4012 false to select the low part. */
4015 mips_subword (rtx op, bool high_p)
4017 unsigned int byte, offset;
4018 enum machine_mode mode;
4020 mode = GET_MODE (op);
4021 if (mode == VOIDmode)
4022 mode = TARGET_64BIT ? TImode : DImode;
4024 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4025 byte = UNITS_PER_WORD;
4029 if (FP_REG_RTX_P (op))
4031 /* Paired FPRs are always ordered little-endian. */
4032 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4033 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4037 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4039 return simplify_gen_subreg (word_mode, op, mode, byte);
4042 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4045 mips_split_64bit_move_p (rtx dest, rtx src)
4050 /* FPR-to-FPR moves can be done in a single instruction, if they're
4052 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4055 /* Check for floating-point loads and stores. */
4056 if (ISA_HAS_LDC1_SDC1)
4058 if (FP_REG_RTX_P (dest) && MEM_P (src))
4060 if (FP_REG_RTX_P (src) && MEM_P (dest))
4066 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4067 this function handles 64-bit moves for which mips_split_64bit_move_p
4068 holds. For 64-bit targets, this function handles 128-bit moves. */
4071 mips_split_doubleword_move (rtx dest, rtx src)
4075 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4077 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4078 emit_insn (gen_move_doubleword_fprdi (dest, src));
4079 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4080 emit_insn (gen_move_doubleword_fprdf (dest, src));
4081 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4082 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4083 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4084 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4085 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4086 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4087 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4088 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4089 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4090 emit_insn (gen_move_doubleword_fprtf (dest, src));
4094 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4096 low_dest = mips_subword (dest, false);
4097 mips_emit_move (low_dest, mips_subword (src, false));
4099 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4101 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4103 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4105 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4107 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4109 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4113 /* The operation can be split into two normal moves. Decide in
4114 which order to do them. */
4115 low_dest = mips_subword (dest, false);
4116 if (REG_P (low_dest)
4117 && reg_overlap_mentioned_p (low_dest, src))
4119 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4120 mips_emit_move (low_dest, mips_subword (src, false));
4124 mips_emit_move (low_dest, mips_subword (src, false));
4125 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4130 /* Return the appropriate instructions to move SRC into DEST. Assume
4131 that SRC is operand 1 and DEST is operand 0. */
4134 mips_output_move (rtx dest, rtx src)
4136 enum rtx_code dest_code, src_code;
4137 enum machine_mode mode;
4138 enum mips_symbol_type symbol_type;
4141 dest_code = GET_CODE (dest);
4142 src_code = GET_CODE (src);
4143 mode = GET_MODE (dest);
4144 dbl_p = (GET_MODE_SIZE (mode) == 8);
4146 if (dbl_p && mips_split_64bit_move_p (dest, src))
4149 if ((src_code == REG && GP_REG_P (REGNO (src)))
4150 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4152 if (dest_code == REG)
4154 if (GP_REG_P (REGNO (dest)))
4155 return "move\t%0,%z1";
4157 /* Moves to HI are handled by special .md insns. */
4158 if (REGNO (dest) == LO_REGNUM)
4161 if (DSP_ACC_REG_P (REGNO (dest)))
4163 static char retval[] = "mt__\t%z1,%q0";
4165 retval[2] = reg_names[REGNO (dest)][4];
4166 retval[3] = reg_names[REGNO (dest)][5];
4170 if (FP_REG_P (REGNO (dest)))
4171 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4173 if (ALL_COP_REG_P (REGNO (dest)))
4175 static char retval[] = "dmtc_\t%z1,%0";
4177 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4178 return dbl_p ? retval : retval + 1;
4181 if (dest_code == MEM)
4182 switch (GET_MODE_SIZE (mode))
4184 case 1: return "sb\t%z1,%0";
4185 case 2: return "sh\t%z1,%0";
4186 case 4: return "sw\t%z1,%0";
4187 case 8: return "sd\t%z1,%0";
4190 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4192 if (src_code == REG)
4194 /* Moves from HI are handled by special .md insns. */
4195 if (REGNO (src) == LO_REGNUM)
4197 /* When generating VR4120 or VR4130 code, we use MACC and
4198 DMACC instead of MFLO. This avoids both the normal
4199 MIPS III HI/LO hazards and the errata related to
4202 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4206 if (DSP_ACC_REG_P (REGNO (src)))
4208 static char retval[] = "mf__\t%0,%q1";
4210 retval[2] = reg_names[REGNO (src)][4];
4211 retval[3] = reg_names[REGNO (src)][5];
4215 if (FP_REG_P (REGNO (src)))
4216 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4218 if (ALL_COP_REG_P (REGNO (src)))
4220 static char retval[] = "dmfc_\t%0,%1";
4222 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4223 return dbl_p ? retval : retval + 1;
4226 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4227 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4230 if (src_code == MEM)
4231 switch (GET_MODE_SIZE (mode))
4233 case 1: return "lbu\t%0,%1";
4234 case 2: return "lhu\t%0,%1";
4235 case 4: return "lw\t%0,%1";
4236 case 8: return "ld\t%0,%1";
4239 if (src_code == CONST_INT)
4241 /* Don't use the X format for the operand itself, because that
4242 will give out-of-range numbers for 64-bit hosts and 32-bit
4245 return "li\t%0,%1\t\t\t# %X1";
4247 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4250 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4254 if (src_code == HIGH)
4255 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4257 if (CONST_GP_P (src))
4258 return "move\t%0,%1";
4260 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4261 && mips_lo_relocs[symbol_type] != 0)
4263 /* A signed 16-bit constant formed by applying a relocation
4264 operator to a symbolic address. */
4265 gcc_assert (!mips_split_p[symbol_type]);
4266 return "li\t%0,%R1";
4269 if (symbolic_operand (src, VOIDmode))
4271 gcc_assert (TARGET_MIPS16
4272 ? TARGET_MIPS16_TEXT_LOADS
4273 : !TARGET_EXPLICIT_RELOCS);
4274 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4277 if (src_code == REG && FP_REG_P (REGNO (src)))
4279 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4281 if (GET_MODE (dest) == V2SFmode)
4282 return "mov.ps\t%0,%1";
4284 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4287 if (dest_code == MEM)
4288 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4290 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4292 if (src_code == MEM)
4293 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4295 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4297 static char retval[] = "l_c_\t%0,%1";
4299 retval[1] = (dbl_p ? 'd' : 'w');
4300 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4303 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4305 static char retval[] = "s_c_\t%1,%0";
4307 retval[1] = (dbl_p ? 'd' : 'w');
4308 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4314 /* Return true if CMP1 is a suitable second operand for integer ordering
4315 test CODE. See also the *sCC patterns in mips.md. */
4318 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4324 return reg_or_0_operand (cmp1, VOIDmode);
4328 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4332 return arith_operand (cmp1, VOIDmode);
4335 return sle_operand (cmp1, VOIDmode);
4338 return sleu_operand (cmp1, VOIDmode);
4345 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4346 integer ordering test *CODE, or if an equivalent combination can
4347 be formed by adjusting *CODE and *CMP1. When returning true, update
4348 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4352 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4353 enum machine_mode mode)
4355 HOST_WIDE_INT plus_one;
4357 if (mips_int_order_operand_ok_p (*code, *cmp1))
4360 if (CONST_INT_P (*cmp1))
4364 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4365 if (INTVAL (*cmp1) < plus_one)
4368 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4374 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4378 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4389 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4390 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4391 is nonnull, it's OK to set TARGET to the inverse of the result and
4392 flip *INVERT_PTR instead. */
4395 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4396 rtx target, rtx cmp0, rtx cmp1)
4398 enum machine_mode mode;
4400 /* First see if there is a MIPS instruction that can do this operation.
4401 If not, try doing the same for the inverse operation. If that also
4402 fails, force CMP1 into a register and try again. */
4403 mode = GET_MODE (cmp0);
4404 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4405 mips_emit_binary (code, target, cmp0, cmp1);
4408 enum rtx_code inv_code = reverse_condition (code);
4409 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4411 cmp1 = force_reg (mode, cmp1);
4412 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4414 else if (invert_ptr == 0)
4418 inv_target = mips_force_binary (GET_MODE (target),
4419 inv_code, cmp0, cmp1);
4420 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4424 *invert_ptr = !*invert_ptr;
4425 mips_emit_binary (inv_code, target, cmp0, cmp1);
4430 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4431 The register will have the same mode as CMP0. */
4434 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4436 if (cmp1 == const0_rtx)
4439 if (uns_arith_operand (cmp1, VOIDmode))
4440 return expand_binop (GET_MODE (cmp0), xor_optab,
4441 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4443 return expand_binop (GET_MODE (cmp0), sub_optab,
4444 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4447 /* Convert *CODE into a code that can be used in a floating-point
4448 scc instruction (C.cond.fmt). Return true if the values of
4449 the condition code registers will be inverted, with 0 indicating
4450 that the condition holds. */
4453 mips_reversed_fp_cond (enum rtx_code *code)
4460 *code = reverse_condition_maybe_unordered (*code);
4468 /* Convert a comparison into something that can be used in a branch or
4469 conditional move. On entry, *OP0 and *OP1 are the values being
4470 compared and *CODE is the code used to compare them.
4472 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4473 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4474 otherwise any standard branch condition can be used. The standard branch
4477 - EQ or NE between two registers.
4478 - any comparison between a register and zero. */
4481 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4486 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4488 if (!need_eq_ne_p && *op1 == const0_rtx)
4490 else if (*code == EQ || *code == NE)
4494 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4498 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4502 /* The comparison needs a separate scc instruction. Store the
4503 result of the scc in *OP0 and compare it against zero. */
4504 bool invert = false;
4505 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4506 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4507 *code = (invert ? EQ : NE);
4511 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4513 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4514 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4520 enum rtx_code cmp_code;
4522 /* Floating-point tests use a separate C.cond.fmt comparison to
4523 set a condition code register. The branch or conditional move
4524 will then compare that register against zero.
4526 Set CMP_CODE to the code of the comparison instruction and
4527 *CODE to the code that the branch or move should use. */
4529 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4531 ? gen_reg_rtx (CCmode)
4532 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4534 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4538 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4539 and OPERAND[3]. Store the result in OPERANDS[0].
4541 On 64-bit targets, the mode of the comparison and target will always be
4542 SImode, thus possibly narrower than that of the comparison's operands. */
4545 mips_expand_scc (rtx operands[])
4547 rtx target = operands[0];
4548 enum rtx_code code = GET_CODE (operands[1]);
4549 rtx op0 = operands[2];
4550 rtx op1 = operands[3];
4552 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4554 if (code == EQ || code == NE)
4557 && reg_imm10_operand (op1, GET_MODE (op1)))
4558 mips_emit_binary (code, target, op0, op1);
4561 rtx zie = mips_zero_if_equal (op0, op1);
4562 mips_emit_binary (code, target, zie, const0_rtx);
4566 mips_emit_int_order_test (code, 0, target, op0, op1);
4569 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4570 CODE and jump to OPERANDS[3] if the condition holds. */
4573 mips_expand_conditional_branch (rtx *operands)
4575 enum rtx_code code = GET_CODE (operands[0]);
4576 rtx op0 = operands[1];
4577 rtx op1 = operands[2];
4580 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4581 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4582 emit_jump_insn (gen_condjump (condition, operands[3]));
4587 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4588 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4591 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4592 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4597 reversed_p = mips_reversed_fp_cond (&cond);
4598 cmp_result = gen_reg_rtx (CCV2mode);
4599 emit_insn (gen_scc_ps (cmp_result,
4600 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4602 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4605 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4609 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4610 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4613 mips_expand_conditional_move (rtx *operands)
4616 enum rtx_code code = GET_CODE (operands[1]);
4617 rtx op0 = XEXP (operands[1], 0);
4618 rtx op1 = XEXP (operands[1], 1);
4620 mips_emit_compare (&code, &op0, &op1, true);
4621 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4622 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4623 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4624 operands[2], operands[3])));
4627 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4630 mips_expand_conditional_trap (rtx comparison)
4633 enum machine_mode mode;
4636 /* MIPS conditional trap instructions don't have GT or LE flavors,
4637 so we must swap the operands and convert to LT and GE respectively. */
4638 code = GET_CODE (comparison);
4645 code = swap_condition (code);
4646 op0 = XEXP (comparison, 1);
4647 op1 = XEXP (comparison, 0);
4651 op0 = XEXP (comparison, 0);
4652 op1 = XEXP (comparison, 1);
4656 mode = GET_MODE (XEXP (comparison, 0));
4657 op0 = force_reg (mode, op0);
4658 if (!arith_operand (op1, mode))
4659 op1 = force_reg (mode, op1);
4661 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4662 gen_rtx_fmt_ee (code, mode, op0, op1),
4666 /* Initialize *CUM for a call to a function of type FNTYPE. */
4669 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4671 memset (cum, 0, sizeof (*cum));
4672 cum->prototype = (fntype && prototype_p (fntype));
4673 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4676 /* Fill INFO with information about a single argument. CUM is the
4677 cumulative state for earlier arguments. MODE is the mode of this
4678 argument and TYPE is its type (if known). NAMED is true if this
4679 is a named (fixed) argument rather than a variable one. */
4682 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4683 enum machine_mode mode, tree type, int named)
4685 bool doubleword_aligned_p;
4686 unsigned int num_bytes, num_words, max_regs;
4688 /* Work out the size of the argument. */
4689 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4690 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4692 /* Decide whether it should go in a floating-point register, assuming
4693 one is free. Later code checks for availability.
4695 The checks against UNITS_PER_FPVALUE handle the soft-float and
4696 single-float cases. */
4700 /* The EABI conventions have traditionally been defined in terms
4701 of TYPE_MODE, regardless of the actual type. */
4702 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4703 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4704 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4709 /* Only leading floating-point scalars are passed in
4710 floating-point registers. We also handle vector floats the same
4711 say, which is OK because they are not covered by the standard ABI. */
4712 info->fpr_p = (!cum->gp_reg_found
4713 && cum->arg_number < 2
4715 || SCALAR_FLOAT_TYPE_P (type)
4716 || VECTOR_FLOAT_TYPE_P (type))
4717 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4718 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4719 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4724 /* Scalar, complex and vector floating-point types are passed in
4725 floating-point registers, as long as this is a named rather
4726 than a variable argument. */
4727 info->fpr_p = (named
4728 && (type == 0 || FLOAT_TYPE_P (type))
4729 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4730 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4731 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4732 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4734 /* ??? According to the ABI documentation, the real and imaginary
4735 parts of complex floats should be passed in individual registers.
4736 The real and imaginary parts of stack arguments are supposed
4737 to be contiguous and there should be an extra word of padding
4740 This has two problems. First, it makes it impossible to use a
4741 single "void *" va_list type, since register and stack arguments
4742 are passed differently. (At the time of writing, MIPSpro cannot
4743 handle complex float varargs correctly.) Second, it's unclear
4744 what should happen when there is only one register free.
4746 For now, we assume that named complex floats should go into FPRs
4747 if there are two FPRs free, otherwise they should be passed in the
4748 same way as a struct containing two floats. */
4750 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4751 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4753 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4754 info->fpr_p = false;
4764 /* See whether the argument has doubleword alignment. */
4765 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
4767 /* Set REG_OFFSET to the register count we're interested in.
4768 The EABI allocates the floating-point registers separately,
4769 but the other ABIs allocate them like integer registers. */
4770 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4774 /* Advance to an even register if the argument is doubleword-aligned. */
4775 if (doubleword_aligned_p)
4776 info->reg_offset += info->reg_offset & 1;
4778 /* Work out the offset of a stack argument. */
4779 info->stack_offset = cum->stack_words;
4780 if (doubleword_aligned_p)
4781 info->stack_offset += info->stack_offset & 1;
4783 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4785 /* Partition the argument between registers and stack. */
4786 info->reg_words = MIN (num_words, max_regs);
4787 info->stack_words = num_words - info->reg_words;
4790 /* INFO describes a register argument that has the normal format for the
4791 argument's mode. Return the register it uses, assuming that FPRs are
4792 available if HARD_FLOAT_P. */
4795 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4797 if (!info->fpr_p || !hard_float_p)
4798 return GP_ARG_FIRST + info->reg_offset;
4799 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4800 /* In o32, the second argument is always passed in $f14
4801 for TARGET_DOUBLE_FLOAT, regardless of whether the
4802 first argument was a word or doubleword. */
4803 return FP_ARG_FIRST + 2;
4805 return FP_ARG_FIRST + info->reg_offset;
4808 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4811 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4813 return !TARGET_OLDABI;
4816 /* Implement FUNCTION_ARG. */
4819 mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
4820 tree type, int named)
4822 struct mips_arg_info info;
4824 /* We will be called with a mode of VOIDmode after the last argument
4825 has been seen. Whatever we return will be passed to the call expander.
4826 If we need a MIPS16 fp_code, return a REG with the code stored as
4828 if (mode == VOIDmode)
4830 if (TARGET_MIPS16 && cum->fp_code != 0)
4831 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4836 mips_get_arg_info (&info, cum, mode, type, named);
4838 /* Return straight away if the whole argument is passed on the stack. */
4839 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4842 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4843 contains a double in its entirety, then that 64-bit chunk is passed
4844 in a floating-point register. */
4846 && TARGET_HARD_FLOAT
4849 && TREE_CODE (type) == RECORD_TYPE
4850 && TYPE_SIZE_UNIT (type)
4851 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4855 /* First check to see if there is any such field. */
4856 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4857 if (TREE_CODE (field) == FIELD_DECL
4858 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4859 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4860 && host_integerp (bit_position (field), 0)
4861 && int_bit_position (field) % BITS_PER_WORD == 0)
4866 /* Now handle the special case by returning a PARALLEL
4867 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4868 chunks are passed in registers. */
4870 HOST_WIDE_INT bitpos;
4873 /* assign_parms checks the mode of ENTRY_PARM, so we must
4874 use the actual mode here. */
4875 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4878 field = TYPE_FIELDS (type);
4879 for (i = 0; i < info.reg_words; i++)
4883 for (; field; field = TREE_CHAIN (field))
4884 if (TREE_CODE (field) == FIELD_DECL
4885 && int_bit_position (field) >= bitpos)
4889 && int_bit_position (field) == bitpos
4890 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4891 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4892 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4894 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4897 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4898 GEN_INT (bitpos / BITS_PER_UNIT));
4900 bitpos += BITS_PER_WORD;
4906 /* Handle the n32/n64 conventions for passing complex floating-point
4907 arguments in FPR pairs. The real part goes in the lower register
4908 and the imaginary part goes in the upper register. */
4911 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4914 enum machine_mode inner;
4917 inner = GET_MODE_INNER (mode);
4918 regno = FP_ARG_FIRST + info.reg_offset;
4919 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4921 /* Real part in registers, imaginary part on stack. */
4922 gcc_assert (info.stack_words == info.reg_words);
4923 return gen_rtx_REG (inner, regno);
4927 gcc_assert (info.stack_words == 0);
4928 real = gen_rtx_EXPR_LIST (VOIDmode,
4929 gen_rtx_REG (inner, regno),
4931 imag = gen_rtx_EXPR_LIST (VOIDmode,
4933 regno + info.reg_words / 2),
4934 GEN_INT (GET_MODE_SIZE (inner)));
4935 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4939 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4942 /* Implement FUNCTION_ARG_ADVANCE. */
4945 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4946 tree type, int named)
4948 struct mips_arg_info info;
4950 mips_get_arg_info (&info, cum, mode, type, named);
4953 cum->gp_reg_found = true;
4955 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4956 an explanation of what this code does. It assumes that we're using
4957 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4959 if (cum->arg_number < 2 && info.fpr_p)
4960 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4962 /* Advance the register count. This has the effect of setting
4963 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4964 argument required us to skip the final GPR and pass the whole
4965 argument on the stack. */
4966 if (mips_abi != ABI_EABI || !info.fpr_p)
4967 cum->num_gprs = info.reg_offset + info.reg_words;
4968 else if (info.reg_words > 0)
4969 cum->num_fprs += MAX_FPRS_PER_FMT;
4971 /* Advance the stack word count. */
4972 if (info.stack_words > 0)
4973 cum->stack_words = info.stack_offset + info.stack_words;
4978 /* Implement TARGET_ARG_PARTIAL_BYTES. */
4981 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
4982 enum machine_mode mode, tree type, bool named)
4984 struct mips_arg_info info;
4986 mips_get_arg_info (&info, cum, mode, type, named);
4987 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
4990 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
4991 PARM_BOUNDARY bits of alignment, but will be given anything up
4992 to STACK_BOUNDARY bits if the type requires it. */
4995 mips_function_arg_boundary (enum machine_mode mode, tree type)
4997 unsigned int alignment;
4999 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5000 if (alignment < PARM_BOUNDARY)
5001 alignment = PARM_BOUNDARY;
5002 if (alignment > STACK_BOUNDARY)
5003 alignment = STACK_BOUNDARY;
5007 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5008 upward rather than downward. In other words, return true if the
5009 first byte of the stack slot has useful data, false if the last
5013 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5015 /* On little-endian targets, the first byte of every stack argument
5016 is passed in the first byte of the stack slot. */
5017 if (!BYTES_BIG_ENDIAN)
5020 /* Otherwise, integral types are padded downward: the last byte of a
5021 stack argument is passed in the last byte of the stack slot. */
5023 ? (INTEGRAL_TYPE_P (type)
5024 || POINTER_TYPE_P (type)
5025 || FIXED_POINT_TYPE_P (type))
5026 : (SCALAR_INT_MODE_P (mode)
5027 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5030 /* Big-endian o64 pads floating-point arguments downward. */
5031 if (mips_abi == ABI_O64)
5032 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5035 /* Other types are padded upward for o32, o64, n32 and n64. */
5036 if (mips_abi != ABI_EABI)
5039 /* Arguments smaller than a stack slot are padded downward. */
5040 if (mode != BLKmode)
5041 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5043 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5046 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5047 if the least significant byte of the register has useful data. Return
5048 the opposite if the most significant byte does. */
5051 mips_pad_reg_upward (enum machine_mode mode, tree type)
5053 /* No shifting is required for floating-point arguments. */
5054 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5055 return !BYTES_BIG_ENDIAN;
5057 /* Otherwise, apply the same padding to register arguments as we do
5058 to stack arguments. */
5059 return mips_pad_arg_upward (mode, type);
5062 /* Return nonzero when an argument must be passed by reference. */
5065 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5066 enum machine_mode mode, const_tree type,
5067 bool named ATTRIBUTE_UNUSED)
5069 if (mips_abi == ABI_EABI)
5073 /* ??? How should SCmode be handled? */
5074 if (mode == DImode || mode == DFmode
5075 || mode == DQmode || mode == UDQmode
5076 || mode == DAmode || mode == UDAmode)
5079 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5080 return size == -1 || size > UNITS_PER_WORD;
5084 /* If we have a variable-sized parameter, we have no choice. */
5085 return targetm.calls.must_pass_in_stack (mode, type);
5089 /* Implement TARGET_CALLEE_COPIES. */
5092 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5093 enum machine_mode mode ATTRIBUTE_UNUSED,
5094 const_tree type ATTRIBUTE_UNUSED, bool named)
5096 return mips_abi == ABI_EABI && named;
5099 /* See whether VALTYPE is a record whose fields should be returned in
5100 floating-point registers. If so, return the number of fields and
5101 list them in FIELDS (which should have two elements). Return 0
5104 For n32 & n64, a structure with one or two fields is returned in
5105 floating-point registers as long as every field has a floating-point
5109 mips_fpr_return_fields (const_tree valtype, tree *fields)
5117 if (TREE_CODE (valtype) != RECORD_TYPE)
5121 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
5123 if (TREE_CODE (field) != FIELD_DECL)
5126 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5132 fields[i++] = field;
5137 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5138 a value in the most significant part of $2/$3 if:
5140 - the target is big-endian;
5142 - the value has a structure or union type (we generalize this to
5143 cover aggregates from other languages too); and
5145 - the structure is not returned in floating-point registers. */
5148 mips_return_in_msb (const_tree valtype)
5152 return (TARGET_NEWABI
5153 && TARGET_BIG_ENDIAN
5154 && AGGREGATE_TYPE_P (valtype)
5155 && mips_fpr_return_fields (valtype, fields) == 0);
5158 /* Return true if the function return value MODE will get returned in a
5159 floating-point register. */
5162 mips_return_mode_in_fpr_p (enum machine_mode mode)
5164 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5165 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5166 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5167 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5170 /* Return the representation of an FPR return register when the
5171 value being returned in FP_RETURN has mode VALUE_MODE and the
5172 return type itself has mode TYPE_MODE. On NewABI targets,
5173 the two modes may be different for structures like:
5175 struct __attribute__((packed)) foo { float f; }
5177 where we return the SFmode value of "f" in FP_RETURN, but where
5178 the structure itself has mode BLKmode. */
5181 mips_return_fpr_single (enum machine_mode type_mode,
5182 enum machine_mode value_mode)
5186 x = gen_rtx_REG (value_mode, FP_RETURN);
5187 if (type_mode != value_mode)
5189 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5190 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5195 /* Return a composite value in a pair of floating-point registers.
5196 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5197 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5200 For n32 & n64, $f0 always holds the first value and $f2 the second.
5201 Otherwise the values are packed together as closely as possible. */
5204 mips_return_fpr_pair (enum machine_mode mode,
5205 enum machine_mode mode1, HOST_WIDE_INT offset1,
5206 enum machine_mode mode2, HOST_WIDE_INT offset2)
5210 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5211 return gen_rtx_PARALLEL
5214 gen_rtx_EXPR_LIST (VOIDmode,
5215 gen_rtx_REG (mode1, FP_RETURN),
5217 gen_rtx_EXPR_LIST (VOIDmode,
5218 gen_rtx_REG (mode2, FP_RETURN + inc),
5219 GEN_INT (offset2))));
5223 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5224 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5225 VALTYPE is null and MODE is the mode of the return value. */
5228 mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode)
5235 mode = TYPE_MODE (valtype);
5236 unsigned_p = TYPE_UNSIGNED (valtype);
5238 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5239 return values, promote the mode here too. */
5240 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5242 /* Handle structures whose fields are returned in $f0/$f2. */
5243 switch (mips_fpr_return_fields (valtype, fields))
5246 return mips_return_fpr_single (mode,
5247 TYPE_MODE (TREE_TYPE (fields[0])));
5250 return mips_return_fpr_pair (mode,
5251 TYPE_MODE (TREE_TYPE (fields[0])),
5252 int_byte_position (fields[0]),
5253 TYPE_MODE (TREE_TYPE (fields[1])),
5254 int_byte_position (fields[1]));
5257 /* If a value is passed in the most significant part of a register, see
5258 whether we have to round the mode up to a whole number of words. */
5259 if (mips_return_in_msb (valtype))
5261 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5262 if (size % UNITS_PER_WORD != 0)
5264 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5265 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5269 /* For EABI, the class of return register depends entirely on MODE.
5270 For example, "struct { some_type x; }" and "union { some_type x; }"
5271 are returned in the same way as a bare "some_type" would be.
5272 Other ABIs only use FPRs for scalar, complex or vector types. */
5273 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5274 return gen_rtx_REG (mode, GP_RETURN);
5279 /* Handle long doubles for n32 & n64. */
5281 return mips_return_fpr_pair (mode,
5283 DImode, GET_MODE_SIZE (mode) / 2);
5285 if (mips_return_mode_in_fpr_p (mode))
5287 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5288 return mips_return_fpr_pair (mode,
5289 GET_MODE_INNER (mode), 0,
5290 GET_MODE_INNER (mode),
5291 GET_MODE_SIZE (mode) / 2);
5293 return gen_rtx_REG (mode, FP_RETURN);
5297 return gen_rtx_REG (mode, GP_RETURN);
5300 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5301 all BLKmode objects are returned in memory. Under the n32, n64
5302 and embedded ABIs, small structures are returned in a register.
5303 Objects with varying size must still be returned in memory, of
5307 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5309 return (TARGET_OLDABI
5310 ? TYPE_MODE (type) == BLKmode
5311 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5314 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5317 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5318 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5321 CUMULATIVE_ARGS local_cum;
5322 int gp_saved, fp_saved;
5324 /* The caller has advanced CUM up to, but not beyond, the last named
5325 argument. Advance a local copy of CUM past the last "real" named
5326 argument, to find out how many registers are left over. */
5328 FUNCTION_ARG_ADVANCE (local_cum, mode, type, true);
5330 /* Found out how many registers we need to save. */
5331 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5332 fp_saved = (EABI_FLOAT_VARARGS_P
5333 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5342 ptr = plus_constant (virtual_incoming_args_rtx,
5343 REG_PARM_STACK_SPACE (cfun->decl)
5344 - gp_saved * UNITS_PER_WORD);
5345 mem = gen_frame_mem (BLKmode, ptr);
5346 set_mem_alias_set (mem, get_varargs_alias_set ());
5348 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5353 /* We can't use move_block_from_reg, because it will use
5355 enum machine_mode mode;
5358 /* Set OFF to the offset from virtual_incoming_args_rtx of
5359 the first float register. The FP save area lies below
5360 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5361 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5362 off -= fp_saved * UNITS_PER_FPREG;
5364 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5366 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5367 i += MAX_FPRS_PER_FMT)
5371 ptr = plus_constant (virtual_incoming_args_rtx, off);
5372 mem = gen_frame_mem (mode, ptr);
5373 set_mem_alias_set (mem, get_varargs_alias_set ());
5374 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5375 off += UNITS_PER_HWFPVALUE;
5379 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5380 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5381 + fp_saved * UNITS_PER_FPREG);
5384 /* Implement TARGET_BUILTIN_VA_LIST. */
5387 mips_build_builtin_va_list (void)
5389 if (EABI_FLOAT_VARARGS_P)
5391 /* We keep 3 pointers, and two offsets.
5393 Two pointers are to the overflow area, which starts at the CFA.
5394 One of these is constant, for addressing into the GPR save area
5395 below it. The other is advanced up the stack through the
5398 The third pointer is to the bottom of the GPR save area.
5399 Since the FPR save area is just below it, we can address
5400 FPR slots off this pointer.
5402 We also keep two one-byte offsets, which are to be subtracted
5403 from the constant pointers to yield addresses in the GPR and
5404 FPR save areas. These are downcounted as float or non-float
5405 arguments are used, and when they get to zero, the argument
5406 must be obtained from the overflow region. */
5407 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5410 record = lang_hooks.types.make_type (RECORD_TYPE);
5412 f_ovfl = build_decl (BUILTINS_LOCATION,
5413 FIELD_DECL, get_identifier ("__overflow_argptr"),
5415 f_gtop = build_decl (BUILTINS_LOCATION,
5416 FIELD_DECL, get_identifier ("__gpr_top"),
5418 f_ftop = build_decl (BUILTINS_LOCATION,
5419 FIELD_DECL, get_identifier ("__fpr_top"),
5421 f_goff = build_decl (BUILTINS_LOCATION,
5422 FIELD_DECL, get_identifier ("__gpr_offset"),
5423 unsigned_char_type_node);
5424 f_foff = build_decl (BUILTINS_LOCATION,
5425 FIELD_DECL, get_identifier ("__fpr_offset"),
5426 unsigned_char_type_node);
5427 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5428 warn on every user file. */
5429 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5430 array = build_array_type (unsigned_char_type_node,
5431 build_index_type (index));
5432 f_res = build_decl (BUILTINS_LOCATION,
5433 FIELD_DECL, get_identifier ("__reserved"), array);
5435 DECL_FIELD_CONTEXT (f_ovfl) = record;
5436 DECL_FIELD_CONTEXT (f_gtop) = record;
5437 DECL_FIELD_CONTEXT (f_ftop) = record;
5438 DECL_FIELD_CONTEXT (f_goff) = record;
5439 DECL_FIELD_CONTEXT (f_foff) = record;
5440 DECL_FIELD_CONTEXT (f_res) = record;
5442 TYPE_FIELDS (record) = f_ovfl;
5443 TREE_CHAIN (f_ovfl) = f_gtop;
5444 TREE_CHAIN (f_gtop) = f_ftop;
5445 TREE_CHAIN (f_ftop) = f_goff;
5446 TREE_CHAIN (f_goff) = f_foff;
5447 TREE_CHAIN (f_foff) = f_res;
5449 layout_type (record);
5452 else if (TARGET_IRIX6)
5453 /* On IRIX 6, this type is 'char *'. */
5454 return build_pointer_type (char_type_node);
5456 /* Otherwise, we use 'void *'. */
5457 return ptr_type_node;
5460 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5463 mips_va_start (tree valist, rtx nextarg)
5465 if (EABI_FLOAT_VARARGS_P)
5467 const CUMULATIVE_ARGS *cum;
5468 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5469 tree ovfl, gtop, ftop, goff, foff;
5471 int gpr_save_area_size;
5472 int fpr_save_area_size;
5475 cum = &crtl->args.info;
5477 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5479 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5481 f_ovfl = TYPE_FIELDS (va_list_type_node);
5482 f_gtop = TREE_CHAIN (f_ovfl);
5483 f_ftop = TREE_CHAIN (f_gtop);
5484 f_goff = TREE_CHAIN (f_ftop);
5485 f_foff = TREE_CHAIN (f_goff);
5487 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5489 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5491 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5493 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5495 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5498 /* Emit code to initialize OVFL, which points to the next varargs
5499 stack argument. CUM->STACK_WORDS gives the number of stack
5500 words used by named arguments. */
5501 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5502 if (cum->stack_words > 0)
5503 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5504 size_int (cum->stack_words * UNITS_PER_WORD));
5505 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5506 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5508 /* Emit code to initialize GTOP, the top of the GPR save area. */
5509 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5510 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5511 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5513 /* Emit code to initialize FTOP, the top of the FPR save area.
5514 This address is gpr_save_area_bytes below GTOP, rounded
5515 down to the next fp-aligned boundary. */
5516 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5517 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5518 fpr_offset &= -UNITS_PER_FPVALUE;
5520 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5521 size_int (-fpr_offset));
5522 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5523 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5525 /* Emit code to initialize GOFF, the offset from GTOP of the
5526 next GPR argument. */
5527 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5528 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5529 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5531 /* Likewise emit code to initialize FOFF, the offset from FTOP
5532 of the next FPR argument. */
5533 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5534 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5535 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5539 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5540 std_expand_builtin_va_start (valist, nextarg);
5544 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5547 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5553 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5555 type = build_pointer_type (type);
5557 if (!EABI_FLOAT_VARARGS_P)
5558 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5561 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5562 tree ovfl, top, off, align;
5563 HOST_WIDE_INT size, rsize, osize;
5566 f_ovfl = TYPE_FIELDS (va_list_type_node);
5567 f_gtop = TREE_CHAIN (f_ovfl);
5568 f_ftop = TREE_CHAIN (f_gtop);
5569 f_goff = TREE_CHAIN (f_ftop);
5570 f_foff = TREE_CHAIN (f_goff);
5574 TOP be the top of the GPR or FPR save area;
5575 OFF be the offset from TOP of the next register;
5576 ADDR_RTX be the address of the argument;
5577 SIZE be the number of bytes in the argument type;
5578 RSIZE be the number of bytes used to store the argument
5579 when it's in the register save area; and
5580 OSIZE be the number of bytes used to store it when it's
5581 in the stack overflow area.
5583 The code we want is:
5585 1: off &= -rsize; // round down
5588 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5593 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5594 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5598 [1] and [9] can sometimes be optimized away. */
5600 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5602 size = int_size_in_bytes (type);
5604 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5605 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5607 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5608 unshare_expr (valist), f_ftop, NULL_TREE);
5609 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5610 unshare_expr (valist), f_foff, NULL_TREE);
5612 /* When va_start saves FPR arguments to the stack, each slot
5613 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5614 argument's precision. */
5615 rsize = UNITS_PER_HWFPVALUE;
5617 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5618 (= PARM_BOUNDARY bits). This can be different from RSIZE
5621 (1) On 32-bit targets when TYPE is a structure such as:
5623 struct s { float f; };
5625 Such structures are passed in paired FPRs, so RSIZE
5626 will be 8 bytes. However, the structure only takes
5627 up 4 bytes of memory, so OSIZE will only be 4.
5629 (2) In combinations such as -mgp64 -msingle-float
5630 -fshort-double. Doubles passed in registers will then take
5631 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5632 stack take up UNITS_PER_WORD bytes. */
5633 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5637 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5638 unshare_expr (valist), f_gtop, NULL_TREE);
5639 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5640 unshare_expr (valist), f_goff, NULL_TREE);
5641 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5642 if (rsize > UNITS_PER_WORD)
5644 /* [1] Emit code for: off &= -rsize. */
5645 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5646 build_int_cst (TREE_TYPE (off), -rsize));
5647 gimplify_assign (unshare_expr (off), t, pre_p);
5652 /* [2] Emit code to branch if off == 0. */
5653 t = build2 (NE_EXPR, boolean_type_node, off,
5654 build_int_cst (TREE_TYPE (off), 0));
5655 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5657 /* [5] Emit code for: off -= rsize. We do this as a form of
5658 post-decrement not available to C. */
5659 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5660 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5662 /* [4] Emit code for:
5663 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5664 t = fold_convert (sizetype, t);
5665 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5666 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5667 if (BYTES_BIG_ENDIAN && rsize > size)
5669 u = size_int (rsize - size);
5670 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5672 COND_EXPR_THEN (addr) = t;
5674 if (osize > UNITS_PER_WORD)
5676 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5677 u = size_int (osize - 1);
5678 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5679 unshare_expr (ovfl), u);
5680 t = fold_convert (sizetype, t);
5681 u = size_int (-osize);
5682 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5683 t = fold_convert (TREE_TYPE (ovfl), t);
5684 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5685 unshare_expr (ovfl), t);
5690 /* [10, 11] Emit code for:
5691 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5693 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5694 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5695 if (BYTES_BIG_ENDIAN && osize > size)
5697 u = size_int (osize - size);
5698 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5701 /* String [9] and [10, 11] together. */
5703 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5704 COND_EXPR_ELSE (addr) = t;
5706 addr = fold_convert (build_pointer_type (type), addr);
5707 addr = build_va_arg_indirect_ref (addr);
5711 addr = build_va_arg_indirect_ref (addr);
5716 /* Start a definition of function NAME. MIPS16_P indicates whether the
5717 function contains MIPS16 code. */
5720 mips_start_function_definition (const char *name, bool mips16_p)
5723 fprintf (asm_out_file, "\t.set\tmips16\n");
5725 fprintf (asm_out_file, "\t.set\tnomips16\n");
5727 if (!flag_inhibit_size_directive)
5729 fputs ("\t.ent\t", asm_out_file);
5730 assemble_name (asm_out_file, name);
5731 fputs ("\n", asm_out_file);
5734 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5736 /* Start the definition proper. */
5737 assemble_name (asm_out_file, name);
5738 fputs (":\n", asm_out_file);
5741 /* End a function definition started by mips_start_function_definition. */
5744 mips_end_function_definition (const char *name)
5746 if (!flag_inhibit_size_directive)
5748 fputs ("\t.end\t", asm_out_file);
5749 assemble_name (asm_out_file, name);
5750 fputs ("\n", asm_out_file);
5754 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5757 mips_ok_for_lazy_binding_p (rtx x)
5759 return (TARGET_USE_GOT
5760 && GET_CODE (x) == SYMBOL_REF
5761 && !SYMBOL_REF_BIND_NOW_P (x)
5762 && !mips_symbol_binds_local_p (x));
5765 /* Load function address ADDR into register DEST. TYPE is as for
5766 mips_expand_call. Return true if we used an explicit lazy-binding
5770 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5772 /* If we're generating PIC, and this call is to a global function,
5773 try to allow its address to be resolved lazily. This isn't
5774 possible for sibcalls when $gp is call-saved because the value
5775 of $gp on entry to the stub would be our caller's gp, not ours. */
5776 if (TARGET_EXPLICIT_RELOCS
5777 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5778 && mips_ok_for_lazy_binding_p (addr))
5780 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5781 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5786 mips_emit_move (dest, addr);
5791 /* Each locally-defined hard-float MIPS16 function has a local symbol
5792 associated with it. This hash table maps the function symbol (FUNC)
5793 to the local symbol (LOCAL). */
5794 struct GTY(()) mips16_local_alias {
5798 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5800 /* Hash table callbacks for mips16_local_aliases. */
5803 mips16_local_aliases_hash (const void *entry)
5805 const struct mips16_local_alias *alias;
5807 alias = (const struct mips16_local_alias *) entry;
5808 return htab_hash_string (XSTR (alias->func, 0));
5812 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5814 const struct mips16_local_alias *alias1, *alias2;
5816 alias1 = (const struct mips16_local_alias *) entry1;
5817 alias2 = (const struct mips16_local_alias *) entry2;
5818 return rtx_equal_p (alias1->func, alias2->func);
5821 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5822 Return a local alias for it, creating a new one if necessary. */
5825 mips16_local_alias (rtx func)
5827 struct mips16_local_alias *alias, tmp_alias;
5830 /* Create the hash table if this is the first call. */
5831 if (mips16_local_aliases == NULL)
5832 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5833 mips16_local_aliases_eq, NULL);
5835 /* Look up the function symbol, creating a new entry if need be. */
5836 tmp_alias.func = func;
5837 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5838 gcc_assert (slot != NULL);
5840 alias = (struct mips16_local_alias *) *slot;
5843 const char *func_name, *local_name;
5846 /* Create a new SYMBOL_REF for the local symbol. The choice of
5847 __fn_local_* is based on the __fn_stub_* names that we've
5848 traditionally used for the non-MIPS16 stub. */
5849 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5850 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5851 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5852 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5854 /* Create a new structure to represent the mapping. */
5855 alias = GGC_NEW (struct mips16_local_alias);
5857 alias->local = local;
5860 return alias->local;
5863 /* A chained list of functions for which mips16_build_call_stub has already
5864 generated a stub. NAME is the name of the function and FP_RET_P is true
5865 if the function returns a value in floating-point registers. */
5866 struct mips16_stub {
5867 struct mips16_stub *next;
5871 static struct mips16_stub *mips16_stubs;
5873 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5876 mips16_stub_function (const char *name)
5880 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5881 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5885 /* Return the two-character string that identifies floating-point
5886 return mode MODE in the name of a MIPS16 function stub. */
5889 mips16_call_stub_mode_suffix (enum machine_mode mode)
5893 else if (mode == DFmode)
5895 else if (mode == SCmode)
5897 else if (mode == DCmode)
5899 else if (mode == V2SFmode)
5905 /* Write instructions to move a 32-bit value between general register
5906 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5907 from GPREG to FPREG and 'f' to move in the opposite direction. */
5910 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5912 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5913 reg_names[gpreg], reg_names[fpreg]);
5916 /* Likewise for 64-bit values. */
5919 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5922 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5923 reg_names[gpreg], reg_names[fpreg]);
5924 else if (TARGET_FLOAT64)
5926 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5927 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5928 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5929 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
5933 /* Move the least-significant word. */
5934 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5935 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5936 /* ...then the most significant word. */
5937 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5938 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
5942 /* Write out code to move floating-point arguments into or out of
5943 general registers. FP_CODE is the code describing which arguments
5944 are present (see the comment above the definition of CUMULATIVE_ARGS
5945 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5948 mips_output_args_xfer (int fp_code, char direction)
5950 unsigned int gparg, fparg, f;
5951 CUMULATIVE_ARGS cum;
5953 /* This code only works for o32 and o64. */
5954 gcc_assert (TARGET_OLDABI);
5956 mips_init_cumulative_args (&cum, NULL);
5958 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
5960 enum machine_mode mode;
5961 struct mips_arg_info info;
5965 else if ((f & 3) == 2)
5970 mips_get_arg_info (&info, &cum, mode, NULL, true);
5971 gparg = mips_arg_regno (&info, false);
5972 fparg = mips_arg_regno (&info, true);
5975 mips_output_32bit_xfer (direction, gparg, fparg);
5977 mips_output_64bit_xfer (direction, gparg, fparg);
5979 mips_function_arg_advance (&cum, mode, NULL, true);
5983 /* Write a MIPS16 stub for the current function. This stub is used
5984 for functions which take arguments in the floating-point registers.
5985 It is normal-mode code that moves the floating-point arguments
5986 into the general registers and then jumps to the MIPS16 code. */
5989 mips16_build_function_stub (void)
5991 const char *fnname, *alias_name, *separator;
5992 char *secname, *stubname;
5997 /* Create the name of the stub, and its unique section. */
5998 symbol = XEXP (DECL_RTL (current_function_decl), 0);
5999 alias = mips16_local_alias (symbol);
6001 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6002 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6003 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6004 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6006 /* Build a decl for the stub. */
6007 stubdecl = build_decl (BUILTINS_LOCATION,
6008 FUNCTION_DECL, get_identifier (stubname),
6009 build_function_type (void_type_node, NULL_TREE));
6010 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6011 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6012 RESULT_DECL, NULL_TREE, void_type_node);
6014 /* Output a comment. */
6015 fprintf (asm_out_file, "\t# Stub function for %s (",
6016 current_function_name ());
6018 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6020 fprintf (asm_out_file, "%s%s", separator,
6021 (f & 3) == 1 ? "float" : "double");
6024 fprintf (asm_out_file, ")\n");
6026 /* Start the function definition. */
6027 assemble_start_function (stubdecl, stubname);
6028 mips_start_function_definition (stubname, false);
6030 /* If generating pic2 code, either set up the global pointer or
6032 if (TARGET_ABICALLS_PIC2)
6034 if (TARGET_ABSOLUTE_ABICALLS)
6035 fprintf (asm_out_file, "\t.option\tpic0\n");
6038 output_asm_insn ("%(.cpload\t%^%)", NULL);
6039 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6040 target function is. Use a local GOT access when loading the
6041 symbol, to cut down on the number of unnecessary GOT entries
6042 for stubs that aren't needed. */
6043 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6048 /* Load the address of the MIPS16 function into $25. Do this first so
6049 that targets with coprocessor interlocks can use an MFC1 to fill the
6051 output_asm_insn ("la\t%^,%0", &symbol);
6053 /* Move the arguments from floating-point registers to general registers. */
6054 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6056 /* Jump to the MIPS16 function. */
6057 output_asm_insn ("jr\t%^", NULL);
6059 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6060 fprintf (asm_out_file, "\t.option\tpic2\n");
6062 mips_end_function_definition (stubname);
6064 /* If the linker needs to create a dynamic symbol for the target
6065 function, it will associate the symbol with the stub (which,
6066 unlike the target function, follows the proper calling conventions).
6067 It is therefore useful to have a local alias for the target function,
6068 so that it can still be identified as MIPS16 code. As an optimization,
6069 this symbol can also be used for indirect MIPS16 references from
6070 within this file. */
6071 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6073 switch_to_section (function_section (current_function_decl));
6076 /* The current function is a MIPS16 function that returns a value in an FPR.
6077 Copy the return value from its soft-float to its hard-float location.
6078 libgcc2 has special non-MIPS16 helper functions for each case. */
6081 mips16_copy_fpr_return_value (void)
6083 rtx fn, insn, retval;
6085 enum machine_mode return_mode;
6088 return_type = DECL_RESULT (current_function_decl);
6089 return_mode = DECL_MODE (return_type);
6091 name = ACONCAT (("__mips16_ret_",
6092 mips16_call_stub_mode_suffix (return_mode),
6094 fn = mips16_stub_function (name);
6096 /* The function takes arguments in $2 (and possibly $3), so calls
6097 to it cannot be lazily bound. */
6098 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6100 /* Model the call as something that takes the GPR return value as
6101 argument and returns an "updated" value. */
6102 retval = gen_rtx_REG (return_mode, GP_RETURN);
6103 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6104 const0_rtx, NULL_RTX, false);
6105 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6108 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6109 RETVAL is the location of the return value, or null if this is
6110 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6111 arguments and FP_CODE is the code built by mips_function_arg;
6112 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6114 There are three alternatives:
6116 - If a stub was needed, emit the call and return the call insn itself.
6118 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6119 to the new target and return null.
6121 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6124 A stub is needed for calls to functions that, in normal mode,
6125 receive arguments in FPRs or return values in FPRs. The stub
6126 copies the arguments from their soft-float positions to their
6127 hard-float positions, calls the real function, then copies the
6128 return value from its hard-float position to its soft-float
6131 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6132 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6133 automatically redirects the JAL to the stub, otherwise the JAL
6134 continues to call FN directly. */
6137 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6141 struct mips16_stub *l;
6144 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6145 we were invoked with the -msoft-float option. */
6146 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6149 /* Figure out whether the value might come back in a floating-point
6151 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6153 /* We don't need to do anything if there were no floating-point
6154 arguments and the value will not be returned in a floating-point
6156 if (fp_code == 0 && !fp_ret_p)
6159 /* We don't need to do anything if this is a call to a special
6160 MIPS16 support function. */
6162 if (mips16_stub_function_p (fn))
6165 /* This code will only work for o32 and o64 abis. The other ABI's
6166 require more sophisticated support. */
6167 gcc_assert (TARGET_OLDABI);
6169 /* If we're calling via a function pointer, use one of the magic
6170 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6171 Each stub expects the function address to arrive in register $2. */
6172 if (GET_CODE (fn) != SYMBOL_REF
6173 || !call_insn_operand (fn, VOIDmode))
6176 rtx stub_fn, insn, addr;
6179 /* If this is a locally-defined and locally-binding function,
6180 avoid the stub by calling the local alias directly. */
6181 if (mips16_local_function_p (fn))
6183 *fn_ptr = mips16_local_alias (fn);
6187 /* Create a SYMBOL_REF for the libgcc.a function. */
6189 sprintf (buf, "__mips16_call_stub_%s_%d",
6190 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6193 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6194 stub_fn = mips16_stub_function (buf);
6196 /* The function uses $2 as an argument, so calls to it
6197 cannot be lazily bound. */
6198 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6200 /* Load the target function into $2. */
6201 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6202 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6204 /* Emit the call. */
6205 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6206 args_size, NULL_RTX, lazy_p);
6208 /* Tell GCC that this call does indeed use the value of $2. */
6209 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6211 /* If we are handling a floating-point return value, we need to
6212 save $18 in the function prologue. Putting a note on the
6213 call will mean that df_regs_ever_live_p ($18) will be true if the
6214 call is not eliminated, and we can check that in the prologue
6217 CALL_INSN_FUNCTION_USAGE (insn) =
6218 gen_rtx_EXPR_LIST (VOIDmode,
6219 gen_rtx_CLOBBER (VOIDmode,
6220 gen_rtx_REG (word_mode, 18)),
6221 CALL_INSN_FUNCTION_USAGE (insn));
6226 /* We know the function we are going to call. If we have already
6227 built a stub, we don't need to do anything further. */
6228 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6229 for (l = mips16_stubs; l != NULL; l = l->next)
6230 if (strcmp (l->name, fnname) == 0)
6235 const char *separator;
6236 char *secname, *stubname;
6237 tree stubid, stubdecl;
6240 /* If the function does not return in FPRs, the special stub
6244 If the function does return in FPRs, the stub section is named
6245 .mips16.call.fp.FNNAME
6247 Build a decl for the stub. */
6248 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6250 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6252 stubid = get_identifier (stubname);
6253 stubdecl = build_decl (BUILTINS_LOCATION,
6254 FUNCTION_DECL, stubid,
6255 build_function_type (void_type_node, NULL_TREE));
6256 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6257 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6258 RESULT_DECL, NULL_TREE,
6261 /* Output a comment. */
6262 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6264 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6268 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6270 fprintf (asm_out_file, "%s%s", separator,
6271 (f & 3) == 1 ? "float" : "double");
6274 fprintf (asm_out_file, ")\n");
6276 /* Start the function definition. */
6277 assemble_start_function (stubdecl, stubname);
6278 mips_start_function_definition (stubname, false);
6282 /* Load the address of the MIPS16 function into $25. Do this
6283 first so that targets with coprocessor interlocks can use
6284 an MFC1 to fill the delay slot. */
6285 if (TARGET_EXPLICIT_RELOCS)
6287 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6288 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6291 output_asm_insn ("la\t%^,%0", &fn);
6294 /* Move the arguments from general registers to floating-point
6296 mips_output_args_xfer (fp_code, 't');
6300 /* Jump to the previously-loaded address. */
6301 output_asm_insn ("jr\t%^", NULL);
6305 /* Save the return address in $18 and call the non-MIPS16 function.
6306 The stub's caller knows that $18 might be clobbered, even though
6307 $18 is usually a call-saved register. */
6308 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6309 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6310 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6312 /* Move the result from floating-point registers to
6313 general registers. */
6314 switch (GET_MODE (retval))
6317 mips_output_32bit_xfer ('f', GP_RETURN + 1,
6318 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6321 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6322 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6324 /* On 64-bit targets, complex floats are returned in
6325 a single GPR, such that "sd" on a suitably-aligned
6326 target would store the value correctly. */
6327 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6328 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6329 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6330 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6331 reg_names[GP_RETURN],
6332 reg_names[GP_RETURN],
6333 reg_names[GP_RETURN + 1]);
6338 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6339 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6343 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6349 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6352 #ifdef ASM_DECLARE_FUNCTION_SIZE
6353 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6356 mips_end_function_definition (stubname);
6358 /* Record this stub. */
6359 l = XNEW (struct mips16_stub);
6360 l->name = xstrdup (fnname);
6361 l->fp_ret_p = fp_ret_p;
6362 l->next = mips16_stubs;
6366 /* If we expect a floating-point return value, but we've built a
6367 stub which does not expect one, then we're in trouble. We can't
6368 use the existing stub, because it won't handle the floating-point
6369 value. We can't build a new stub, because the linker won't know
6370 which stub to use for the various calls in this object file.
6371 Fortunately, this case is illegal, since it means that a function
6372 was declared in two different ways in a single compilation. */
6373 if (fp_ret_p && !l->fp_ret_p)
6374 error ("cannot handle inconsistent calls to %qs", fnname);
6376 if (retval == NULL_RTX)
6377 insn = gen_call_internal_direct (fn, args_size);
6379 insn = gen_call_value_internal_direct (retval, fn, args_size);
6380 insn = mips_emit_call_insn (insn, fn, fn, false);
6382 /* If we are calling a stub which handles a floating-point return
6383 value, we need to arrange to save $18 in the prologue. We do this
6384 by marking the function call as using the register. The prologue
6385 will later see that it is used, and emit code to save it. */
6387 CALL_INSN_FUNCTION_USAGE (insn) =
6388 gen_rtx_EXPR_LIST (VOIDmode,
6389 gen_rtx_CLOBBER (VOIDmode,
6390 gen_rtx_REG (word_mode, 18)),
6391 CALL_INSN_FUNCTION_USAGE (insn));
6396 /* Expand a call of type TYPE. RESULT is where the result will go (null
6397 for "call"s and "sibcall"s), ADDR is the address of the function,
6398 ARGS_SIZE is the size of the arguments and AUX is the value passed
6399 to us by mips_function_arg. LAZY_P is true if this call already
6400 involves a lazily-bound function address (such as when calling
6401 functions through a MIPS16 hard-float stub).
6403 Return the call itself. */
6406 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6407 rtx args_size, rtx aux, bool lazy_p)
6409 rtx orig_addr, pattern, insn;
6412 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6413 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6416 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6421 if (!call_insn_operand (addr, VOIDmode))
6423 if (type == MIPS_CALL_EPILOGUE)
6424 addr = MIPS_EPILOGUE_TEMP (Pmode);
6426 addr = gen_reg_rtx (Pmode);
6427 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6432 rtx (*fn) (rtx, rtx);
6434 if (type == MIPS_CALL_SIBCALL)
6435 fn = gen_sibcall_internal;
6437 fn = gen_call_internal;
6439 pattern = fn (addr, args_size);
6441 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6443 /* Handle return values created by mips_return_fpr_pair. */
6444 rtx (*fn) (rtx, rtx, rtx, rtx);
6447 if (type == MIPS_CALL_SIBCALL)
6448 fn = gen_sibcall_value_multiple_internal;
6450 fn = gen_call_value_multiple_internal;
6452 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6453 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6454 pattern = fn (reg1, addr, args_size, reg2);
6458 rtx (*fn) (rtx, rtx, rtx);
6460 if (type == MIPS_CALL_SIBCALL)
6461 fn = gen_sibcall_value_internal;
6463 fn = gen_call_value_internal;
6465 /* Handle return values created by mips_return_fpr_single. */
6466 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6467 result = XEXP (XVECEXP (result, 0, 0), 0);
6468 pattern = fn (result, addr, args_size);
6471 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6474 /* Split call instruction INSN into a $gp-clobbering call and
6475 (where necessary) an instruction to restore $gp from its save slot.
6476 CALL_PATTERN is the pattern of the new call. */
6479 mips_split_call (rtx insn, rtx call_pattern)
6483 new_insn = emit_call_insn (call_pattern);
6484 CALL_INSN_FUNCTION_USAGE (new_insn)
6485 = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn));
6486 if (!find_reg_note (insn, REG_NORETURN, 0))
6487 /* Pick a temporary register that is suitable for both MIPS16 and
6488 non-MIPS16 code. $4 and $5 are used for returning complex double
6489 values in soft-float code, so $6 is the first suitable candidate. */
6490 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6493 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6496 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6498 if (!TARGET_SIBCALLS)
6501 /* Interrupt handlers need special epilogue code and therefore can't
6503 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6506 /* We can't do a sibcall if the called function is a MIPS16 function
6507 because there is no direct "jx" instruction equivalent to "jalx" to
6508 switch the ISA mode. We only care about cases where the sibling
6509 and normal calls would both be direct. */
6511 && mips_use_mips16_mode_p (decl)
6512 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6515 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6516 functions could be MIPS16 ones unless an attribute explicitly tells
6518 if (TARGET_INTERLINK_MIPS16
6520 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6521 && !mips_nomips16_decl_p (decl)
6522 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6529 /* Emit code to move general operand SRC into condition-code
6530 register DEST given that SCRATCH is a scratch TFmode FPR.
6537 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6540 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6544 /* Change the source to SFmode. */
6546 src = adjust_address (src, SFmode, 0);
6547 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6548 src = gen_rtx_REG (SFmode, true_regnum (src));
6550 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6551 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6553 mips_emit_move (copy_rtx (fp1), src);
6554 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6555 emit_insn (gen_slt_sf (dest, fp2, fp1));
6558 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6559 Assume that the areas do not overlap. */
6562 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6564 HOST_WIDE_INT offset, delta;
6565 unsigned HOST_WIDE_INT bits;
6567 enum machine_mode mode;
6570 /* Work out how many bits to move at a time. If both operands have
6571 half-word alignment, it is usually better to move in half words.
6572 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6573 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6574 Otherwise move word-sized chunks. */
6575 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6576 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6577 bits = BITS_PER_WORD / 2;
6579 bits = BITS_PER_WORD;
6581 mode = mode_for_size (bits, MODE_INT, 0);
6582 delta = bits / BITS_PER_UNIT;
6584 /* Allocate a buffer for the temporary registers. */
6585 regs = XALLOCAVEC (rtx, length / delta);
6587 /* Load as many BITS-sized chunks as possible. Use a normal load if
6588 the source has enough alignment, otherwise use left/right pairs. */
6589 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6591 regs[i] = gen_reg_rtx (mode);
6592 if (MEM_ALIGN (src) >= bits)
6593 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6596 rtx part = adjust_address (src, BLKmode, offset);
6597 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6602 /* Copy the chunks to the destination. */
6603 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6604 if (MEM_ALIGN (dest) >= bits)
6605 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6608 rtx part = adjust_address (dest, BLKmode, offset);
6609 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6613 /* Mop up any left-over bytes. */
6614 if (offset < length)
6616 src = adjust_address (src, BLKmode, offset);
6617 dest = adjust_address (dest, BLKmode, offset);
6618 move_by_pieces (dest, src, length - offset,
6619 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6623 /* Helper function for doing a loop-based block operation on memory
6624 reference MEM. Each iteration of the loop will operate on LENGTH
6627 Create a new base register for use within the loop and point it to
6628 the start of MEM. Create a new memory reference that uses this
6629 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6632 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6633 rtx *loop_reg, rtx *loop_mem)
6635 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6637 /* Although the new mem does not refer to a known location,
6638 it does keep up to LENGTH bytes of alignment. */
6639 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6640 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6643 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6644 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6645 the memory regions do not overlap. */
6648 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6649 HOST_WIDE_INT bytes_per_iter)
6651 rtx label, src_reg, dest_reg, final_src, test;
6652 HOST_WIDE_INT leftover;
6654 leftover = length % bytes_per_iter;
6657 /* Create registers and memory references for use within the loop. */
6658 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6659 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6661 /* Calculate the value that SRC_REG should have after the last iteration
6663 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6666 /* Emit the start of the loop. */
6667 label = gen_label_rtx ();
6670 /* Emit the loop body. */
6671 mips_block_move_straight (dest, src, bytes_per_iter);
6673 /* Move on to the next block. */
6674 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6675 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6677 /* Emit the loop condition. */
6678 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6679 if (Pmode == DImode)
6680 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6682 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6684 /* Mop up any left-over bytes. */
6686 mips_block_move_straight (dest, src, leftover);
6689 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6690 memory reference SRC to memory reference DEST. */
6693 mips_expand_block_move (rtx dest, rtx src, rtx length)
6695 if (CONST_INT_P (length))
6697 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6699 mips_block_move_straight (dest, src, INTVAL (length));
6704 mips_block_move_loop (dest, src, INTVAL (length),
6705 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6712 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6715 mips_expand_synci_loop (rtx begin, rtx end)
6717 rtx inc, label, end_label, cmp_result, mask, length;
6719 /* Create end_label. */
6720 end_label = gen_label_rtx ();
6722 /* Check if begin equals end. */
6723 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6724 emit_jump_insn (gen_condjump (cmp_result, end_label));
6726 /* Load INC with the cache line size (rdhwr INC,$1). */
6727 inc = gen_reg_rtx (Pmode);
6728 emit_insn (Pmode == SImode
6729 ? gen_rdhwr_synci_step_si (inc)
6730 : gen_rdhwr_synci_step_di (inc));
6732 /* Check if inc is 0. */
6733 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6734 emit_jump_insn (gen_condjump (cmp_result, end_label));
6736 /* Calculate mask. */
6737 mask = mips_force_unary (Pmode, NEG, inc);
6739 /* Mask out begin by mask. */
6740 begin = mips_force_binary (Pmode, AND, begin, mask);
6742 /* Calculate length. */
6743 length = mips_force_binary (Pmode, MINUS, end, begin);
6745 /* Loop back to here. */
6746 label = gen_label_rtx ();
6749 emit_insn (gen_synci (begin));
6751 /* Update length. */
6752 mips_emit_binary (MINUS, length, length, inc);
6755 mips_emit_binary (PLUS, begin, begin, inc);
6757 /* Check if length is greater than 0. */
6758 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6759 emit_jump_insn (gen_condjump (cmp_result, label));
6761 emit_label (end_label);
6764 /* Expand a QI or HI mode atomic memory operation.
6766 GENERATOR contains a pointer to the gen_* function that generates
6767 the SI mode underlying atomic operation using masks that we
6770 RESULT is the return register for the operation. Its value is NULL
6773 MEM is the location of the atomic access.
6775 OLDVAL is the first operand for the operation.
6777 NEWVAL is the optional second operand for the operation. Its value
6778 is NULL if unused. */
6781 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6782 rtx result, rtx mem, rtx oldval, rtx newval)
6784 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6785 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6787 enum machine_mode mode;
6789 mode = GET_MODE (mem);
6791 /* Compute the address of the containing SImode value. */
6792 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6793 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6794 force_reg (Pmode, GEN_INT (-4)));
6796 /* Create a memory reference for it. */
6797 memsi = gen_rtx_MEM (SImode, memsi_addr);
6798 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6799 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6801 /* Work out the byte offset of the QImode or HImode value,
6802 counting from the least significant byte. */
6803 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6804 if (TARGET_BIG_ENDIAN)
6805 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6807 /* Multiply by eight to convert the shift value from bytes to bits. */
6808 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6810 /* Make the final shift an SImode value, so that it can be used in
6811 SImode operations. */
6812 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6814 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6815 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6816 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6817 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6819 /* Compute the equivalent exclusive mask. */
6820 inverted_mask = gen_reg_rtx (SImode);
6821 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6822 gen_rtx_NOT (SImode, mask)));
6824 /* Shift the old value into place. */
6825 if (oldval != const0_rtx)
6827 oldval = convert_modes (SImode, mode, oldval, true);
6828 oldval = force_reg (SImode, oldval);
6829 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6832 /* Do the same for the new value. */
6833 if (newval && newval != const0_rtx)
6835 newval = convert_modes (SImode, mode, newval, true);
6836 newval = force_reg (SImode, newval);
6837 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6840 /* Do the SImode atomic access. */
6842 res = gen_reg_rtx (SImode);
6844 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6846 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6848 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6854 /* Shift and convert the result. */
6855 mips_emit_binary (AND, res, res, mask);
6856 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6857 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6861 /* Return true if it is possible to use left/right accesses for a
6862 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6863 returning true, update *OP, *LEFT and *RIGHT as follows:
6865 *OP is a BLKmode reference to the whole field.
6867 *LEFT is a QImode reference to the first byte if big endian or
6868 the last byte if little endian. This address can be used in the
6869 left-side instructions (LWL, SWL, LDL, SDL).
6871 *RIGHT is a QImode reference to the opposite end of the field and
6872 can be used in the patterning right-side instruction. */
6875 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6876 rtx *left, rtx *right)
6880 /* Check that the operand really is a MEM. Not all the extv and
6881 extzv predicates are checked. */
6885 /* Check that the size is valid. */
6886 if (width != 32 && (!TARGET_64BIT || width != 64))
6889 /* We can only access byte-aligned values. Since we are always passed
6890 a reference to the first byte of the field, it is not necessary to
6891 do anything with BITPOS after this check. */
6892 if (bitpos % BITS_PER_UNIT != 0)
6895 /* Reject aligned bitfields: we want to use a normal load or store
6896 instead of a left/right pair. */
6897 if (MEM_ALIGN (*op) >= width)
6900 /* Adjust *OP to refer to the whole field. This also has the effect
6901 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6902 *op = adjust_address (*op, BLKmode, 0);
6903 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6905 /* Get references to both ends of the field. We deliberately don't
6906 use the original QImode *OP for FIRST since the new BLKmode one
6907 might have a simpler address. */
6908 first = adjust_address (*op, QImode, 0);
6909 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6911 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6912 correspond to the MSB and RIGHT to the LSB. */
6913 if (TARGET_BIG_ENDIAN)
6914 *left = first, *right = last;
6916 *left = last, *right = first;
6921 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6922 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6923 the operation is the equivalent of:
6925 (set DEST (*_extract SRC WIDTH BITPOS))
6927 Return true on success. */
6930 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
6931 HOST_WIDE_INT bitpos)
6933 rtx left, right, temp;
6935 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6936 be a paradoxical word_mode subreg. This is the only case in which
6937 we allow the destination to be larger than the source. */
6938 if (GET_CODE (dest) == SUBREG
6939 && GET_MODE (dest) == DImode
6940 && GET_MODE (SUBREG_REG (dest)) == SImode)
6941 dest = SUBREG_REG (dest);
6943 /* After the above adjustment, the destination must be the same
6944 width as the source. */
6945 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
6948 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
6951 temp = gen_reg_rtx (GET_MODE (dest));
6952 if (GET_MODE (dest) == DImode)
6954 emit_insn (gen_mov_ldl (temp, src, left));
6955 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
6959 emit_insn (gen_mov_lwl (temp, src, left));
6960 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
6965 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
6966 BITPOS and SRC are the operands passed to the expander; the operation
6967 is the equivalent of:
6969 (set (zero_extract DEST WIDTH BITPOS) SRC)
6971 Return true on success. */
6974 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
6975 HOST_WIDE_INT bitpos)
6978 enum machine_mode mode;
6980 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
6983 mode = mode_for_size (width, MODE_INT, 0);
6984 src = gen_lowpart (mode, src);
6987 emit_insn (gen_mov_sdl (dest, src, left));
6988 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
6992 emit_insn (gen_mov_swl (dest, src, left));
6993 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
6998 /* Return true if X is a MEM with the same size as MODE. */
7001 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7008 size = MEM_SIZE (x);
7009 return size && INTVAL (size) == GET_MODE_SIZE (mode);
7012 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7013 source of an "ext" instruction or the destination of an "ins"
7014 instruction. OP must be a register operand and the following
7015 conditions must hold:
7017 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7018 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7019 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7021 Also reject lengths equal to a word as they are better handled
7022 by the move patterns. */
7025 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7027 if (!ISA_HAS_EXT_INS
7028 || !register_operand (op, VOIDmode)
7029 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7032 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7035 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7041 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7042 operation if MAXLEN is the maxium length of consecutive bits that
7043 can make up MASK. MODE is the mode of the operation. See
7044 mask_low_and_shift_len for the actual definition. */
7047 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7049 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7052 /* Return true iff OP1 and OP2 are valid operands together for the
7053 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7054 see the table in the comment before the pattern. */
7057 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7059 return (memory_operand (op1, mode)
7060 ? and_load_operand (op2, mode)
7061 : and_reg_operand (op2, mode));
7064 /* The canonical form of a mask-low-and-shift-left operation is
7065 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7066 cleared. Thus we need to shift MASK to the right before checking if it
7067 is a valid mask value. MODE is the mode of the operation. If true
7068 return the length of the mask, otherwise return -1. */
7071 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7073 HOST_WIDE_INT shval;
7075 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7076 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7079 /* Return true if -msplit-addresses is selected and should be honored.
7081 -msplit-addresses is a half-way house between explicit relocations
7082 and the traditional assembler macros. It can split absolute 32-bit
7083 symbolic constants into a high/lo_sum pair but uses macros for other
7086 Like explicit relocation support for REL targets, it relies
7087 on GNU extensions in the assembler and the linker.
7089 Although this code should work for -O0, it has traditionally
7090 been treated as an optimization. */
7093 mips_split_addresses_p (void)
7095 return (TARGET_SPLIT_ADDRESSES
7099 && !ABI_HAS_64BIT_SYMBOLS);
7102 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7105 mips_init_relocs (void)
7107 memset (mips_split_p, '\0', sizeof (mips_split_p));
7108 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7109 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7110 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7112 if (ABI_HAS_64BIT_SYMBOLS)
7114 if (TARGET_EXPLICIT_RELOCS)
7116 mips_split_p[SYMBOL_64_HIGH] = true;
7117 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7118 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7120 mips_split_p[SYMBOL_64_MID] = true;
7121 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7122 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7124 mips_split_p[SYMBOL_64_LOW] = true;
7125 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7126 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7128 mips_split_p[SYMBOL_ABSOLUTE] = true;
7129 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7134 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7136 mips_split_p[SYMBOL_ABSOLUTE] = true;
7137 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7138 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7140 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7146 /* The high part is provided by a pseudo copy of $gp. */
7147 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7148 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7150 else if (TARGET_EXPLICIT_RELOCS)
7151 /* Small data constants are kept whole until after reload,
7152 then lowered by mips_rewrite_small_data. */
7153 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7155 if (TARGET_EXPLICIT_RELOCS)
7157 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7160 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7161 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7165 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7166 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7169 /* Expose the use of $28 as soon as possible. */
7170 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7174 /* The HIGH and LO_SUM are matched by special .md patterns. */
7175 mips_split_p[SYMBOL_GOT_DISP] = true;
7177 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7178 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7179 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7181 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7182 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7183 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7188 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7190 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7191 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7193 /* Expose the use of $28 as soon as possible. */
7194 mips_split_p[SYMBOL_GOT_DISP] = true;
7200 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7201 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7202 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7205 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7206 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7208 mips_split_p[SYMBOL_DTPREL] = true;
7209 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7210 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7212 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7214 mips_split_p[SYMBOL_TPREL] = true;
7215 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7216 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7218 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7221 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7222 in context CONTEXT. RELOCS is the array of relocations to use. */
7225 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7226 const char **relocs)
7228 enum mips_symbol_type symbol_type;
7231 symbol_type = mips_classify_symbolic_expression (op, context);
7232 gcc_assert (relocs[symbol_type]);
7234 fputs (relocs[symbol_type], file);
7235 output_addr_const (file, mips_strip_unspec_address (op));
7236 for (p = relocs[symbol_type]; *p != 0; p++)
7241 /* Start a new block with the given asm switch enabled. If we need
7242 to print a directive, emit PREFIX before it and SUFFIX after it. */
7245 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7246 const char *prefix, const char *suffix)
7248 if (asm_switch->nesting_level == 0)
7249 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7250 asm_switch->nesting_level++;
7253 /* Likewise, but end a block. */
7256 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7257 const char *prefix, const char *suffix)
7259 gcc_assert (asm_switch->nesting_level);
7260 asm_switch->nesting_level--;
7261 if (asm_switch->nesting_level == 0)
7262 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7265 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7266 that either print a complete line or print nothing. */
7269 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7271 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7275 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7277 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7280 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7281 The punctuation characters are:
7283 '(' Start a nested ".set noreorder" block.
7284 ')' End a nested ".set noreorder" block.
7285 '[' Start a nested ".set noat" block.
7286 ']' End a nested ".set noat" block.
7287 '<' Start a nested ".set nomacro" block.
7288 '>' End a nested ".set nomacro" block.
7289 '*' Behave like %(%< if generating a delayed-branch sequence.
7290 '#' Print a nop if in a ".set noreorder" block.
7291 '/' Like '#', but do nothing within a delayed-branch sequence.
7292 '?' Print "l" if mips_branch_likely is true
7293 '~' Print a nop if mips_branch_likely is true
7294 '.' Print the name of the register with a hard-wired zero (zero or $0).
7295 '@' Print the name of the assembler temporary register (at or $1).
7296 '^' Print the name of the pic call-through register (t9 or $25).
7297 '+' Print the name of the gp register (usually gp or $28).
7298 '$' Print the name of the stack pointer register (sp or $29).
7300 See also mips_init_print_operand_pucnt. */
7303 mips_print_operand_punctuation (FILE *file, int ch)
7308 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7312 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7316 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7320 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7324 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7328 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7332 if (final_sequence != 0)
7334 mips_print_operand_punctuation (file, '(');
7335 mips_print_operand_punctuation (file, '<');
7340 if (mips_noreorder.nesting_level > 0)
7341 fputs ("\n\tnop", file);
7345 /* Print an extra newline so that the delayed insn is separated
7346 from the following ones. This looks neater and is consistent
7347 with non-nop delayed sequences. */
7348 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7349 fputs ("\n\tnop\n", file);
7353 if (mips_branch_likely)
7358 if (mips_branch_likely)
7359 fputs ("\n\tnop", file);
7363 fputs (reg_names[GP_REG_FIRST + 0], file);
7367 fputs (reg_names[AT_REGNUM], file);
7371 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7375 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7379 fputs (reg_names[STACK_POINTER_REGNUM], file);
7388 /* Initialize mips_print_operand_punct. */
7391 mips_init_print_operand_punct (void)
7395 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7396 mips_print_operand_punct[(unsigned char) *p] = true;
7399 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7400 associated with condition CODE. Print the condition part of the
7404 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7418 /* Conveniently, the MIPS names for these conditions are the same
7419 as their RTL equivalents. */
7420 fputs (GET_RTX_NAME (code), file);
7424 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7429 /* Likewise floating-point branches. */
7432 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7437 fputs ("c1f", file);
7441 fputs ("c1t", file);
7445 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7450 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
7452 'X' Print CONST_INT OP in hexadecimal format.
7453 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7454 'd' Print CONST_INT OP in decimal.
7455 'm' Print one less than CONST_INT OP in decimal.
7456 'h' Print the high-part relocation associated with OP, after stripping
7458 'R' Print the low-part relocation associated with OP.
7459 'C' Print the integer branch condition for comparison OP.
7460 'N' Print the inverse of the integer branch condition for comparison OP.
7461 'F' Print the FPU branch condition for comparison OP.
7462 'W' Print the inverse of the FPU branch condition for comparison OP.
7463 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7464 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7465 't' Like 'T', but with the EQ/NE cases reversed
7466 'Y' Print mips_fp_conditions[INTVAL (OP)]
7467 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7468 'q' Print a DSP accumulator register.
7469 'D' Print the second part of a double-word register or memory operand.
7470 'L' Print the low-order register in a double-word register operand.
7471 'M' Print high-order register in a double-word register operand.
7472 'z' Print $0 if OP is zero, otherwise print OP normally. */
7475 mips_print_operand (FILE *file, rtx op, int letter)
7479 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
7481 mips_print_operand_punctuation (file, letter);
7486 code = GET_CODE (op);
7491 if (CONST_INT_P (op))
7492 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7494 output_operand_lossage ("invalid use of '%%%c'", letter);
7498 if (CONST_INT_P (op))
7499 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7501 output_operand_lossage ("invalid use of '%%%c'", letter);
7505 if (CONST_INT_P (op))
7506 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7508 output_operand_lossage ("invalid use of '%%%c'", letter);
7512 if (CONST_INT_P (op))
7513 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7515 output_operand_lossage ("invalid use of '%%%c'", letter);
7521 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7525 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7529 mips_print_int_branch_condition (file, code, letter);
7533 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7537 mips_print_float_branch_condition (file, code, letter);
7541 mips_print_float_branch_condition (file, reverse_condition (code),
7548 int truth = (code == NE) == (letter == 'T');
7549 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7554 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7555 fputs (mips_fp_conditions[UINTVAL (op)], file);
7557 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7564 mips_print_operand (file, op, 0);
7570 if (code == REG && MD_REG_P (REGNO (op)))
7571 fprintf (file, "$ac0");
7572 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7573 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7575 output_operand_lossage ("invalid use of '%%%c'", letter);
7583 unsigned int regno = REGNO (op);
7584 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7585 || (letter == 'L' && TARGET_BIG_ENDIAN)
7588 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7589 output_operand_lossage ("invalid use of '%%%c'", letter);
7590 /* We need to print $0 .. $31 for COP0 registers. */
7591 if (COP0_REG_P (regno))
7592 fprintf (file, "$%s", ®_names[regno][4]);
7594 fprintf (file, "%s", reg_names[regno]);
7600 output_address (plus_constant (XEXP (op, 0), 4));
7601 else if (letter && letter != 'z')
7602 output_operand_lossage ("invalid use of '%%%c'", letter);
7604 output_address (XEXP (op, 0));
7608 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7609 fputs (reg_names[GP_REG_FIRST], file);
7610 else if (letter && letter != 'z')
7611 output_operand_lossage ("invalid use of '%%%c'", letter);
7612 else if (CONST_GP_P (op))
7613 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7615 output_addr_const (file, mips_strip_unspec_address (op));
7621 /* Output address operand X to FILE. */
7624 mips_print_operand_address (FILE *file, rtx x)
7626 struct mips_address_info addr;
7628 if (mips_classify_address (&addr, x, word_mode, true))
7632 mips_print_operand (file, addr.offset, 0);
7633 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7636 case ADDRESS_LO_SUM:
7637 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7639 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7642 case ADDRESS_CONST_INT:
7643 output_addr_const (file, x);
7644 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7647 case ADDRESS_SYMBOLIC:
7648 output_addr_const (file, mips_strip_unspec_address (x));
7654 /* Implement TARGET_ENCODE_SECTION_INFO. */
7657 mips_encode_section_info (tree decl, rtx rtl, int first)
7659 default_encode_section_info (decl, rtl, first);
7661 if (TREE_CODE (decl) == FUNCTION_DECL)
7663 rtx symbol = XEXP (rtl, 0);
7664 tree type = TREE_TYPE (decl);
7666 /* Encode whether the symbol is short or long. */
7667 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7668 || mips_far_type_p (type))
7669 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7673 /* Implement TARGET_SELECT_RTX_SECTION. */
7676 mips_select_rtx_section (enum machine_mode mode, rtx x,
7677 unsigned HOST_WIDE_INT align)
7679 /* ??? Consider using mergeable small data sections. */
7680 if (mips_rtx_constant_in_small_data_p (mode))
7681 return get_named_section (NULL, ".sdata", 0);
7683 return default_elf_select_rtx_section (mode, x, align);
7686 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7688 The complication here is that, with the combination TARGET_ABICALLS
7689 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7690 absolute addresses, and should therefore not be included in the
7691 read-only part of a DSO. Handle such cases by selecting a normal
7692 data section instead of a read-only one. The logic apes that in
7693 default_function_rodata_section. */
7696 mips_function_rodata_section (tree decl)
7698 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7699 return default_function_rodata_section (decl);
7701 if (decl && DECL_SECTION_NAME (decl))
7703 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7704 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7706 char *rname = ASTRDUP (name);
7708 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7710 else if (flag_function_sections
7711 && flag_data_sections
7712 && strncmp (name, ".text.", 6) == 0)
7714 char *rname = ASTRDUP (name);
7715 memcpy (rname + 1, "data", 4);
7716 return get_section (rname, SECTION_WRITE, decl);
7719 return data_section;
7722 /* Implement TARGET_IN_SMALL_DATA_P. */
7725 mips_in_small_data_p (const_tree decl)
7727 unsigned HOST_WIDE_INT size;
7729 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7732 /* We don't yet generate small-data references for -mabicalls
7733 or VxWorks RTP code. See the related -G handling in
7734 mips_override_options. */
7735 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7738 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7742 /* Reject anything that isn't in a known small-data section. */
7743 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7744 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7747 /* If a symbol is defined externally, the assembler will use the
7748 usual -G rules when deciding how to implement macros. */
7749 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7752 else if (TARGET_EMBEDDED_DATA)
7754 /* Don't put constants into the small data section: we want them
7755 to be in ROM rather than RAM. */
7756 if (TREE_CODE (decl) != VAR_DECL)
7759 if (TREE_READONLY (decl)
7760 && !TREE_SIDE_EFFECTS (decl)
7761 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7765 /* Enforce -mlocal-sdata. */
7766 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7769 /* Enforce -mextern-sdata. */
7770 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7772 if (DECL_EXTERNAL (decl))
7774 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7778 /* We have traditionally not treated zero-sized objects as small data,
7779 so this is now effectively part of the ABI. */
7780 size = int_size_in_bytes (TREE_TYPE (decl));
7781 return size > 0 && size <= mips_small_data_threshold;
7784 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7785 anchors for small data: the GP register acts as an anchor in that
7786 case. We also don't want to use them for PC-relative accesses,
7787 where the PC acts as an anchor. */
7790 mips_use_anchors_for_symbol_p (const_rtx symbol)
7792 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7794 case SYMBOL_PC_RELATIVE:
7795 case SYMBOL_GP_RELATIVE:
7799 return default_use_anchors_for_symbol_p (symbol);
7803 /* The MIPS debug format wants all automatic variables and arguments
7804 to be in terms of the virtual frame pointer (stack pointer before
7805 any adjustment in the function), while the MIPS 3.0 linker wants
7806 the frame pointer to be the stack pointer after the initial
7807 adjustment. So, we do the adjustment here. The arg pointer (which
7808 is eliminated) points to the virtual frame pointer, while the frame
7809 pointer (which may be eliminated) points to the stack pointer after
7810 the initial adjustments. */
7813 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7815 rtx offset2 = const0_rtx;
7816 rtx reg = eliminate_constant_term (addr, &offset2);
7819 offset = INTVAL (offset2);
7821 if (reg == stack_pointer_rtx
7822 || reg == frame_pointer_rtx
7823 || reg == hard_frame_pointer_rtx)
7825 offset -= cfun->machine->frame.total_size;
7826 if (reg == hard_frame_pointer_rtx)
7827 offset += cfun->machine->frame.hard_frame_pointer_offset;
7830 /* sdbout_parms does not want this to crash for unrecognized cases. */
7832 else if (reg != arg_pointer_rtx)
7833 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7840 /* Implement ASM_OUTPUT_EXTERNAL. */
7843 mips_output_external (FILE *file, tree decl, const char *name)
7845 default_elf_asm_output_external (file, decl, name);
7847 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7848 set in order to avoid putting out names that are never really
7850 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7852 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7854 /* When using assembler macros, emit .extern directives for
7855 all small-data externs so that the assembler knows how
7858 In most cases it would be safe (though pointless) to emit
7859 .externs for other symbols too. One exception is when an
7860 object is within the -G limit but declared by the user to
7861 be in a section other than .sbss or .sdata. */
7862 fputs ("\t.extern\t", file);
7863 assemble_name (file, name);
7864 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7865 int_size_in_bytes (TREE_TYPE (decl)));
7870 /* Implement ASM_OUTPUT_SOURCE_FILENAME. */
7873 mips_output_filename (FILE *stream, const char *name)
7875 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7877 if (write_symbols == DWARF2_DEBUG)
7879 else if (mips_output_filename_first_time)
7881 mips_output_filename_first_time = 0;
7882 num_source_filenames += 1;
7883 current_function_file = name;
7884 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7885 output_quoted_string (stream, name);
7886 putc ('\n', stream);
7888 /* If we are emitting stabs, let dbxout.c handle this (except for
7889 the mips_output_filename_first_time case). */
7890 else if (write_symbols == DBX_DEBUG)
7892 else if (name != current_function_file
7893 && strcmp (name, current_function_file) != 0)
7895 num_source_filenames += 1;
7896 current_function_file = name;
7897 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7898 output_quoted_string (stream, name);
7899 putc ('\n', stream);
7903 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7905 static void ATTRIBUTE_UNUSED
7906 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7911 fputs ("\t.dtprelword\t", file);
7915 fputs ("\t.dtpreldword\t", file);
7921 output_addr_const (file, x);
7922 fputs ("+0x8000", file);
7925 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7928 mips_dwarf_register_span (rtx reg)
7931 enum machine_mode mode;
7933 /* By default, GCC maps increasing register numbers to increasing
7934 memory locations, but paired FPRs are always little-endian,
7935 regardless of the prevailing endianness. */
7936 mode = GET_MODE (reg);
7937 if (FP_REG_P (REGNO (reg))
7938 && TARGET_BIG_ENDIAN
7939 && MAX_FPRS_PER_FMT > 1
7940 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
7942 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
7943 high = mips_subword (reg, true);
7944 low = mips_subword (reg, false);
7945 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
7951 /* Implement ASM_OUTPUT_ASCII. */
7954 mips_output_ascii (FILE *stream, const char *string, size_t len)
7960 fprintf (stream, "\t.ascii\t\"");
7961 for (i = 0; i < len; i++)
7965 c = (unsigned char) string[i];
7968 if (c == '\\' || c == '\"')
7970 putc ('\\', stream);
7978 fprintf (stream, "\\%03o", c);
7982 if (cur_pos > 72 && i+1 < len)
7985 fprintf (stream, "\"\n\t.ascii\t\"");
7988 fprintf (stream, "\"\n");
7991 /* Emit either a label, .comm, or .lcomm directive. When using assembler
7992 macros, mark the symbol as written so that mips_asm_output_external
7993 won't emit an .extern for it. STREAM is the output file, NAME is the
7994 name of the symbol, INIT_STRING is the string that should be written
7995 before the symbol and FINAL_STRING is the string that should be
7996 written after it. FINAL_STRING is a printf format that consumes the
7997 remaining arguments. */
8000 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8001 const char *final_string, ...)
8005 fputs (init_string, stream);
8006 assemble_name (stream, name);
8007 va_start (ap, final_string);
8008 vfprintf (stream, final_string, ap);
8011 if (!TARGET_EXPLICIT_RELOCS)
8013 tree name_tree = get_identifier (name);
8014 TREE_ASM_WRITTEN (name_tree) = 1;
8018 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8019 NAME is the name of the object and ALIGN is the required alignment
8020 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8021 alignment argument. */
8024 mips_declare_common_object (FILE *stream, const char *name,
8025 const char *init_string,
8026 unsigned HOST_WIDE_INT size,
8027 unsigned int align, bool takes_alignment_p)
8029 if (!takes_alignment_p)
8031 size += (align / BITS_PER_UNIT) - 1;
8032 size -= size % (align / BITS_PER_UNIT);
8033 mips_declare_object (stream, name, init_string,
8034 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8037 mips_declare_object (stream, name, init_string,
8038 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8039 size, align / BITS_PER_UNIT);
8042 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8043 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8046 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8047 unsigned HOST_WIDE_INT size,
8050 /* If the target wants uninitialized const declarations in
8051 .rdata then don't put them in .comm. */
8052 if (TARGET_EMBEDDED_DATA
8053 && TARGET_UNINIT_CONST_IN_RODATA
8054 && TREE_CODE (decl) == VAR_DECL
8055 && TREE_READONLY (decl)
8056 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8058 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8059 targetm.asm_out.globalize_label (stream, name);
8061 switch_to_section (readonly_data_section);
8062 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8063 mips_declare_object (stream, name, "",
8064 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8068 mips_declare_common_object (stream, name, "\n\t.comm\t",
8072 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8073 extern int size_directive_output;
8075 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8076 definitions except that it uses mips_declare_object to emit the label. */
8079 mips_declare_object_name (FILE *stream, const char *name,
8080 tree decl ATTRIBUTE_UNUSED)
8082 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8083 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8086 size_directive_output = 0;
8087 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8091 size_directive_output = 1;
8092 size = int_size_in_bytes (TREE_TYPE (decl));
8093 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8096 mips_declare_object (stream, name, "", ":\n");
8099 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8102 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8106 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8107 if (!flag_inhibit_size_directive
8108 && DECL_SIZE (decl) != 0
8111 && DECL_INITIAL (decl) == error_mark_node
8112 && !size_directive_output)
8116 size_directive_output = 1;
8117 size = int_size_in_bytes (TREE_TYPE (decl));
8118 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8123 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8124 with the current ABI. */
8127 mips_mdebug_abi_name (void)
8140 return TARGET_64BIT ? "eabi64" : "eabi32";
8146 /* Implement TARGET_ASM_FILE_START. */
8149 mips_file_start (void)
8151 default_file_start ();
8153 /* Generate a special section to describe the ABI switches used to
8154 produce the resultant binary. This is unnecessary on IRIX and
8155 causes unwanted warnings from the native linker. */
8158 /* Record the ABI itself. Modern versions of binutils encode
8159 this information in the ELF header flags, but GDB needs the
8160 information in order to correctly debug binaries produced by
8161 older binutils. See the function mips_gdbarch_init in
8163 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8164 mips_mdebug_abi_name ());
8166 /* There is no ELF header flag to distinguish long32 forms of the
8167 EABI from long64 forms. Emit a special section to help tools
8168 such as GDB. Do the same for o64, which is sometimes used with
8170 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8171 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8172 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8174 #ifdef HAVE_AS_GNU_ATTRIBUTE
8175 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
8176 (TARGET_HARD_FLOAT_ABI
8177 ? (TARGET_DOUBLE_FLOAT
8178 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
8182 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8183 if (TARGET_ABICALLS)
8185 fprintf (asm_out_file, "\t.abicalls\n");
8186 if (TARGET_ABICALLS_PIC0)
8187 fprintf (asm_out_file, "\t.option\tpic0\n");
8190 if (flag_verbose_asm)
8191 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8193 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8196 /* Make the last instruction frame-related and note that it performs
8197 the operation described by FRAME_PATTERN. */
8200 mips_set_frame_expr (rtx frame_pattern)
8204 insn = get_last_insn ();
8205 RTX_FRAME_RELATED_P (insn) = 1;
8206 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8211 /* Return a frame-related rtx that stores REG at MEM.
8212 REG must be a single register. */
8215 mips_frame_set (rtx mem, rtx reg)
8219 /* If we're saving the return address register and the DWARF return
8220 address column differs from the hard register number, adjust the
8221 note reg to refer to the former. */
8222 if (REGNO (reg) == RETURN_ADDR_REGNUM
8223 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8224 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8226 set = gen_rtx_SET (VOIDmode, mem, reg);
8227 RTX_FRAME_RELATED_P (set) = 1;
8232 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8233 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8234 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8235 static const unsigned char mips16e_s2_s8_regs[] = {
8236 30, 23, 22, 21, 20, 19, 18
8238 static const unsigned char mips16e_a0_a3_regs[] = {
8242 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8243 ordered from the uppermost in memory to the lowest in memory. */
8244 static const unsigned char mips16e_save_restore_regs[] = {
8245 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8248 /* Return the index of the lowest X in the range [0, SIZE) for which
8249 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8252 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8257 for (i = 0; i < size; i++)
8258 if (BITSET_P (mask, regs[i]))
8264 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8265 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8266 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8267 is true for all indexes (X, SIZE). */
8270 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8271 unsigned int size, unsigned int *num_regs_ptr)
8275 i = mips16e_find_first_register (*mask_ptr, regs, size);
8276 for (i++; i < size; i++)
8277 if (!BITSET_P (*mask_ptr, regs[i]))
8280 *mask_ptr |= 1 << regs[i];
8284 /* Return a simplified form of X using the register values in REG_VALUES.
8285 REG_VALUES[R] is the last value assigned to hard register R, or null
8286 if R has not been modified.
8288 This function is rather limited, but is good enough for our purposes. */
8291 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8293 x = avoid_constant_pool_reference (x);
8297 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8298 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8299 x0, GET_MODE (XEXP (x, 0)));
8302 if (ARITHMETIC_P (x))
8304 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8305 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8306 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8310 && reg_values[REGNO (x)]
8311 && !rtx_unstable_p (reg_values[REGNO (x)]))
8312 return reg_values[REGNO (x)];
8317 /* Return true if (set DEST SRC) stores an argument register into its
8318 caller-allocated save slot, storing the number of that argument
8319 register in *REGNO_PTR if so. REG_VALUES is as for
8320 mips16e_collect_propagate_value. */
8323 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8324 unsigned int *regno_ptr)
8326 unsigned int argno, regno;
8327 HOST_WIDE_INT offset, required_offset;
8330 /* Check that this is a word-mode store. */
8331 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8334 /* Check that the register being saved is an unmodified argument
8336 regno = REGNO (src);
8337 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8339 argno = regno - GP_ARG_FIRST;
8341 /* Check whether the address is an appropriate stack-pointer or
8342 frame-pointer access. */
8343 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8344 mips_split_plus (addr, &base, &offset);
8345 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8346 if (base == hard_frame_pointer_rtx)
8347 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8348 else if (base != stack_pointer_rtx)
8350 if (offset != required_offset)
8357 /* A subroutine of mips_expand_prologue, called only when generating
8358 MIPS16e SAVE instructions. Search the start of the function for any
8359 instructions that save argument registers into their caller-allocated
8360 save slots. Delete such instructions and return a value N such that
8361 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8362 instructions redundant. */
8365 mips16e_collect_argument_saves (void)
8367 rtx reg_values[FIRST_PSEUDO_REGISTER];
8368 rtx insn, next, set, dest, src;
8369 unsigned int nargs, regno;
8371 push_topmost_sequence ();
8373 memset (reg_values, 0, sizeof (reg_values));
8374 for (insn = get_insns (); insn; insn = next)
8376 next = NEXT_INSN (insn);
8377 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8383 set = PATTERN (insn);
8384 if (GET_CODE (set) != SET)
8387 dest = SET_DEST (set);
8388 src = SET_SRC (set);
8389 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8391 if (!BITSET_P (cfun->machine->frame.mask, regno))
8394 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8397 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8398 reg_values[REGNO (dest)]
8399 = mips16e_collect_propagate_value (src, reg_values);
8403 pop_topmost_sequence ();
8408 /* Return a move between register REGNO and memory location SP + OFFSET.
8409 Make the move a load if RESTORE_P, otherwise make it a frame-related
8413 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8418 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8419 reg = gen_rtx_REG (SImode, regno);
8421 ? gen_rtx_SET (VOIDmode, reg, mem)
8422 : mips_frame_set (mem, reg));
8425 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8426 The instruction must:
8428 - Allocate or deallocate SIZE bytes in total; SIZE is known
8431 - Save or restore as many registers in *MASK_PTR as possible.
8432 The instruction saves the first registers at the top of the
8433 allocated area, with the other registers below it.
8435 - Save NARGS argument registers above the allocated area.
8437 (NARGS is always zero if RESTORE_P.)
8439 The SAVE and RESTORE instructions cannot save and restore all general
8440 registers, so there may be some registers left over for the caller to
8441 handle. Destructively modify *MASK_PTR so that it contains the registers
8442 that still need to be saved or restored. The caller can save these
8443 registers in the memory immediately below *OFFSET_PTR, which is a
8444 byte offset from the bottom of the allocated stack area. */
8447 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8448 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8452 HOST_WIDE_INT offset, top_offset;
8453 unsigned int i, regno;
8456 gcc_assert (cfun->machine->frame.num_fp == 0);
8458 /* Calculate the number of elements in the PARALLEL. We need one element
8459 for the stack adjustment, one for each argument register save, and one
8460 for each additional register move. */
8462 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8463 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8466 /* Create the final PARALLEL. */
8467 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8470 /* Add the stack pointer adjustment. */
8471 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8472 plus_constant (stack_pointer_rtx,
8473 restore_p ? size : -size));
8474 RTX_FRAME_RELATED_P (set) = 1;
8475 XVECEXP (pattern, 0, n++) = set;
8477 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8478 top_offset = restore_p ? size : 0;
8480 /* Save the arguments. */
8481 for (i = 0; i < nargs; i++)
8483 offset = top_offset + i * UNITS_PER_WORD;
8484 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8485 XVECEXP (pattern, 0, n++) = set;
8488 /* Then fill in the other register moves. */
8489 offset = top_offset;
8490 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8492 regno = mips16e_save_restore_regs[i];
8493 if (BITSET_P (*mask_ptr, regno))
8495 offset -= UNITS_PER_WORD;
8496 set = mips16e_save_restore_reg (restore_p, offset, regno);
8497 XVECEXP (pattern, 0, n++) = set;
8498 *mask_ptr &= ~(1 << regno);
8502 /* Tell the caller what offset it should use for the remaining registers. */
8503 *offset_ptr = size + (offset - top_offset);
8505 gcc_assert (n == XVECLEN (pattern, 0));
8510 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8511 pointer. Return true if PATTERN matches the kind of instruction
8512 generated by mips16e_build_save_restore. If INFO is nonnull,
8513 initialize it when returning true. */
8516 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8517 struct mips16e_save_restore_info *info)
8519 unsigned int i, nargs, mask, extra;
8520 HOST_WIDE_INT top_offset, save_offset, offset;
8521 rtx set, reg, mem, base;
8524 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8527 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8528 top_offset = adjust > 0 ? adjust : 0;
8530 /* Interpret all other members of the PARALLEL. */
8531 save_offset = top_offset - UNITS_PER_WORD;
8535 for (n = 1; n < XVECLEN (pattern, 0); n++)
8537 /* Check that we have a SET. */
8538 set = XVECEXP (pattern, 0, n);
8539 if (GET_CODE (set) != SET)
8542 /* Check that the SET is a load (if restoring) or a store
8544 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8548 /* Check that the address is the sum of the stack pointer and a
8549 possibly-zero constant offset. */
8550 mips_split_plus (XEXP (mem, 0), &base, &offset);
8551 if (base != stack_pointer_rtx)
8554 /* Check that SET's other operand is a register. */
8555 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8559 /* Check for argument saves. */
8560 if (offset == top_offset + nargs * UNITS_PER_WORD
8561 && REGNO (reg) == GP_ARG_FIRST + nargs)
8563 else if (offset == save_offset)
8565 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8566 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8569 mask |= 1 << REGNO (reg);
8570 save_offset -= UNITS_PER_WORD;
8576 /* Check that the restrictions on register ranges are met. */
8578 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8579 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8580 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8581 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8585 /* Make sure that the topmost argument register is not saved twice.
8586 The checks above ensure that the same is then true for the other
8587 argument registers. */
8588 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8591 /* Pass back information, if requested. */
8594 info->nargs = nargs;
8596 info->size = (adjust > 0 ? adjust : -adjust);
8602 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8603 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8604 the null terminator. */
8607 mips16e_add_register_range (char *s, unsigned int min_reg,
8608 unsigned int max_reg)
8610 if (min_reg != max_reg)
8611 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8613 s += sprintf (s, ",%s", reg_names[min_reg]);
8617 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8618 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8621 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8623 static char buffer[300];
8625 struct mips16e_save_restore_info info;
8626 unsigned int i, end;
8629 /* Parse the pattern. */
8630 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8633 /* Add the mnemonic. */
8634 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8637 /* Save the arguments. */
8639 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8640 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8641 else if (info.nargs == 1)
8642 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8644 /* Emit the amount of stack space to allocate or deallocate. */
8645 s += sprintf (s, "%d", (int) info.size);
8647 /* Save or restore $16. */
8648 if (BITSET_P (info.mask, 16))
8649 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8651 /* Save or restore $17. */
8652 if (BITSET_P (info.mask, 17))
8653 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8655 /* Save or restore registers in the range $s2...$s8, which
8656 mips16e_s2_s8_regs lists in decreasing order. Note that this
8657 is a software register range; the hardware registers are not
8658 numbered consecutively. */
8659 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8660 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8662 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8663 mips16e_s2_s8_regs[i]);
8665 /* Save or restore registers in the range $a0...$a3. */
8666 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8667 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8669 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8670 mips16e_a0_a3_regs[end - 1]);
8672 /* Save or restore $31. */
8673 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8674 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8679 /* Return true if the current function returns its value in a floating-point
8680 register in MIPS16 mode. */
8683 mips16_cfun_returns_in_fpr_p (void)
8685 tree return_type = DECL_RESULT (current_function_decl);
8686 return (TARGET_MIPS16
8687 && TARGET_HARD_FLOAT_ABI
8688 && !aggregate_value_p (return_type, current_function_decl)
8689 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8692 /* Return true if predicate PRED is true for at least one instruction.
8693 Cache the result in *CACHE, and assume that the result is true
8694 if *CACHE is already true. */
8697 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8703 push_topmost_sequence ();
8704 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8705 if (USEFUL_INSN_P (insn) && pred (insn))
8710 pop_topmost_sequence ();
8715 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8716 See mips_cfun_has_inflexible_gp_ref_p for details. */
8719 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8721 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8722 indicate that the target could be a traditional MIPS
8723 lazily-binding stub. */
8724 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8727 /* Return true if the current function refers to the global pointer
8728 in a way that forces $28 to be valid. This means that we can't
8729 change the choice of global pointer, even for NewABI code.
8731 One example of this (and one which needs several checks) is that
8732 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8733 (This restriction does not apply to PLTs.) */
8736 mips_cfun_has_inflexible_gp_ref_p (void)
8738 /* If the function has a nonlocal goto, $28 must hold the correct
8739 global pointer for the target function. That is, the target
8740 of the goto implicitly uses $28. */
8741 if (crtl->has_nonlocal_goto)
8744 if (TARGET_ABICALLS_PIC2)
8746 /* Symbolic accesses implicitly use the global pointer unless
8747 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8748 might go to traditional MIPS lazy-binding stubs. */
8749 if (!TARGET_EXPLICIT_RELOCS)
8752 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8753 can be lazily-bound. */
8757 /* MIPS16 functions that return in FPRs need to call an
8758 external libgcc routine. This call is only made explict
8759 during mips_expand_epilogue, and it too might be lazily bound. */
8760 if (mips16_cfun_returns_in_fpr_p ())
8764 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8765 mips_insn_has_inflexible_gp_ref_p);
8768 /* Return true if INSN refers to the global pointer in a "flexible" way.
8769 See mips_cfun_has_flexible_gp_ref_p for details. */
8772 mips_insn_has_flexible_gp_ref_p (rtx insn)
8774 return (get_attr_got (insn) != GOT_UNSET
8775 || mips_small_data_pattern_p (PATTERN (insn))
8776 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8779 /* Return true if the current function references the global pointer,
8780 but if those references do not inherently require the global pointer
8781 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8784 mips_cfun_has_flexible_gp_ref_p (void)
8786 /* Reload can sometimes introduce constant pool references
8787 into a function that otherwise didn't need them. For example,
8788 suppose we have an instruction like:
8790 (set (reg:DF R1) (float:DF (reg:SI R2)))
8792 If R2 turns out to be a constant such as 1, the instruction may
8793 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8794 the option of using this constant if R2 doesn't get allocated
8797 In cases like these, reload will have added the constant to the
8798 pool but no instruction will yet refer to it. */
8799 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8802 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8803 mips_insn_has_flexible_gp_ref_p);
8806 /* Return the register that should be used as the global pointer
8807 within this function. Return INVALID_REGNUM if the function
8808 doesn't need a global pointer. */
8811 mips_global_pointer (void)
8815 /* $gp is always available unless we're using a GOT. */
8816 if (!TARGET_USE_GOT)
8817 return GLOBAL_POINTER_REGNUM;
8819 /* If there are inflexible references to $gp, we must use the
8820 standard register. */
8821 if (mips_cfun_has_inflexible_gp_ref_p ())
8822 return GLOBAL_POINTER_REGNUM;
8824 /* If there are no current references to $gp, then the only uses
8825 we can introduce later are those involved in long branches. */
8826 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8827 return INVALID_REGNUM;
8829 /* If the global pointer is call-saved, try to use a call-clobbered
8831 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8832 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8833 if (!df_regs_ever_live_p (regno)
8834 && call_really_used_regs[regno]
8835 && !fixed_regs[regno]
8836 && regno != PIC_FUNCTION_ADDR_REGNUM)
8839 return GLOBAL_POINTER_REGNUM;
8842 /* Return true if the current function's prologue must load the global
8843 pointer value into pic_offset_table_rtx and store the same value in
8844 the function's cprestore slot (if any).
8846 One problem we have to deal with is that, when emitting GOT-based
8847 position independent code, long-branch sequences will need to load
8848 the address of the branch target from the GOT. We don't know until
8849 the very end of compilation whether (and where) the function needs
8850 long branches, so we must ensure that _any_ branch can access the
8851 global pointer in some form. However, we do not want to pessimize
8852 the usual case in which all branches are short.
8854 We handle this as follows:
8856 (1) During reload, we set cfun->machine->global_pointer to
8857 INVALID_REGNUM if we _know_ that the current function
8858 doesn't need a global pointer. This is only valid if
8859 long branches don't need the GOT.
8861 Otherwise, we assume that we might need a global pointer
8862 and pick an appropriate register.
8864 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8865 we ensure that the global pointer is available at every
8866 block boundary bar entry and exit. We do this in one of two ways:
8868 - If the function has a cprestore slot, we ensure that this
8869 slot is valid at every branch. However, as explained in
8870 point (6) below, there is no guarantee that pic_offset_table_rtx
8871 itself is valid if new uses of the global pointer are introduced
8872 after the first post-epilogue split.
8874 We guarantee that the cprestore slot is valid by loading it
8875 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8876 this register live at every block boundary bar function entry
8877 and exit. It is then invalid to move the load (and thus the
8878 preceding store) across a block boundary.
8880 - If the function has no cprestore slot, we guarantee that
8881 pic_offset_table_rtx itself is valid at every branch.
8883 See mips_eh_uses for the handling of the register liveness.
8885 (3) During prologue and epilogue generation, we emit "ghost"
8886 placeholder instructions to manipulate the global pointer.
8888 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8889 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8890 that the function needs a global pointer. (There is no need to set
8891 them earlier than this, and doing it as late as possible leads to
8892 fewer false positives.)
8894 (5) If cfun->machine->must_initialize_gp_p is true during a
8895 split_insns pass, we split the ghost instructions into real
8896 instructions. These split instructions can then be optimized in
8897 the usual way. Otherwise, we keep the ghost instructions intact,
8898 and optimize for the case where they aren't needed. We still
8899 have the option of splitting them later, if we need to introduce
8900 new uses of the global pointer.
8902 For example, the scheduler ignores a ghost instruction that
8903 stores $28 to the stack, but it handles the split form of
8904 the ghost instruction as an ordinary store.
8906 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8907 is true during the first post-epilogue split_insns pass, we split
8908 calls and restore_gp patterns into instructions that explicitly
8909 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8910 we split these patterns into instructions that _don't_ load from
8913 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8914 time of the split, then any instructions that exist at that time
8915 can make free use of pic_offset_table_rtx. However, if we want
8916 to introduce new uses of the global pointer after the split,
8917 we must explicitly load the value from the cprestore slot, since
8918 pic_offset_table_rtx itself might not be valid at a given point
8921 The idea is that we want to be able to delete redundant
8922 loads from the cprestore slot in the usual case where no
8923 long branches are needed.
8925 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8926 of md_reorg, we decide whether the global pointer is needed for
8927 long branches. If so, we set cfun->machine->must_initialize_gp_p
8928 to true and split the ghost instructions into real instructions
8931 Note that the ghost instructions must have a zero length for three reasons:
8933 - Giving the length of the underlying $gp sequence might cause
8934 us to use long branches in cases where they aren't really needed.
8936 - They would perturb things like alignment calculations.
8938 - More importantly, the hazard detection in md_reorg relies on
8939 empty instructions having a zero length.
8941 If we find a long branch and split the ghost instructions at the
8942 end of md_reorg, the split could introduce more long branches.
8943 That isn't a problem though, because we still do the split before
8944 the final shorten_branches pass.
8946 This is extremely ugly, but it seems like the best compromise between
8947 correctness and efficiency. */
8950 mips_must_initialize_gp_p (void)
8952 return cfun->machine->must_initialize_gp_p;
8955 /* Return true if REGNO is a register that is ordinarily call-clobbered
8956 but must nevertheless be preserved by an interrupt handler. */
8959 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
8961 if (MD_REG_P (regno))
8964 if (TARGET_DSP && DSP_ACC_REG_P (regno))
8967 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
8969 /* $0 is hard-wired. */
8970 if (regno == GP_REG_FIRST)
8973 /* The interrupt handler can treat kernel registers as
8974 scratch registers. */
8975 if (KERNEL_REG_P (regno))
8978 /* The function will return the stack pointer to its original value
8980 if (regno == STACK_POINTER_REGNUM)
8983 /* Otherwise, return true for registers that aren't ordinarily
8985 return call_really_used_regs[regno];
8991 /* Return true if the current function should treat register REGNO
8995 mips_cfun_call_saved_reg_p (unsigned int regno)
8997 /* Interrupt handlers need to save extra registers. */
8998 if (cfun->machine->interrupt_handler_p
8999 && mips_interrupt_extra_call_saved_reg_p (regno))
9002 /* call_insns preserve $28 unless they explicitly say otherwise,
9003 so call_really_used_regs[] treats $28 as call-saved. However,
9004 we want the ABI property rather than the default call_insn
9006 return (regno == GLOBAL_POINTER_REGNUM
9007 ? TARGET_CALL_SAVED_GP
9008 : !call_really_used_regs[regno]);
9011 /* Return true if the function body might clobber register REGNO.
9012 We know that REGNO is call-saved. */
9015 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9017 /* Some functions should be treated as clobbering all call-saved
9019 if (crtl->saves_all_registers)
9022 /* DF handles cases where a register is explicitly referenced in
9023 the rtl. Incoming values are passed in call-clobbered registers,
9024 so we can assume that any live call-saved register is set within
9026 if (df_regs_ever_live_p (regno))
9029 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9030 These clobbers are not explicit in the rtl. */
9031 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9034 /* If we're using a call-saved global pointer, the function's
9035 prologue will need to set it up. */
9036 if (cfun->machine->global_pointer == regno)
9039 /* The function's prologue will need to set the frame pointer if
9040 frame_pointer_needed. */
9041 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9044 /* If a MIPS16 function returns a value in FPRs, its epilogue
9045 will need to call an external libgcc routine. This yet-to-be
9046 generated call_insn will clobber $31. */
9047 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9050 /* If REGNO is ordinarily call-clobbered, we must assume that any
9051 called function could modify it. */
9052 if (cfun->machine->interrupt_handler_p
9053 && !current_function_is_leaf
9054 && mips_interrupt_extra_call_saved_reg_p (regno))
9060 /* Return true if the current function must save register REGNO. */
9063 mips_save_reg_p (unsigned int regno)
9065 if (mips_cfun_call_saved_reg_p (regno))
9067 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9070 /* Save both registers in an FPR pair if either one is used. This is
9071 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9072 register to be used without the even register. */
9073 if (FP_REG_P (regno)
9074 && MAX_FPRS_PER_FMT == 2
9075 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9079 /* We need to save the incoming return address if __builtin_eh_return
9080 is being used to set a different return address. */
9081 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9087 /* Populate the current function's mips_frame_info structure.
9089 MIPS stack frames look like:
9091 +-------------------------------+
9093 | incoming stack arguments |
9095 +-------------------------------+
9097 | caller-allocated save area |
9098 A | for register arguments |
9100 +-------------------------------+ <-- incoming stack pointer
9102 | callee-allocated save area |
9103 B | for arguments that are |
9104 | split between registers and |
9107 +-------------------------------+ <-- arg_pointer_rtx
9109 C | callee-allocated save area |
9110 | for register varargs |
9112 +-------------------------------+ <-- frame_pointer_rtx
9113 | | + cop0_sp_offset
9114 | COP0 reg save area | + UNITS_PER_WORD
9116 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9117 | | + UNITS_PER_WORD
9118 | accumulator save area |
9120 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9121 | | + UNITS_PER_HWFPVALUE
9124 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9125 | | + UNITS_PER_WORD
9128 +-------------------------------+ <-- frame_pointer_rtx with
9129 | | \ -fstack-protector
9130 | local variables | | var_size
9132 +-------------------------------+
9134 | $gp save area | | cprestore_size
9136 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9138 | outgoing stack arguments | |
9140 +-------------------------------+ | args_size
9142 | caller-allocated save area | |
9143 | for register arguments | |
9145 +-------------------------------+ <-- stack_pointer_rtx
9146 frame_pointer_rtx without
9148 hard_frame_pointer_rtx for
9151 At least two of A, B and C will be empty.
9153 Dynamic stack allocations such as alloca insert data at point P.
9154 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9155 hard_frame_pointer_rtx unchanged. */
9158 mips_compute_frame_info (void)
9160 struct mips_frame_info *frame;
9161 HOST_WIDE_INT offset, size;
9162 unsigned int regno, i;
9164 /* Set this function's interrupt properties. */
9165 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9168 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9169 else if (TARGET_HARD_FLOAT)
9170 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9171 else if (TARGET_MIPS16)
9172 error ("interrupt handlers cannot be MIPS16 functions");
9175 cfun->machine->interrupt_handler_p = true;
9176 cfun->machine->use_shadow_register_set_p =
9177 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9178 cfun->machine->keep_interrupts_masked_p =
9179 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9180 cfun->machine->use_debug_exception_return_p =
9181 mips_use_debug_exception_return_p (TREE_TYPE
9182 (current_function_decl));
9186 frame = &cfun->machine->frame;
9187 memset (frame, 0, sizeof (*frame));
9188 size = get_frame_size ();
9190 cfun->machine->global_pointer = mips_global_pointer ();
9192 /* The first two blocks contain the outgoing argument area and the $gp save
9193 slot. This area isn't needed in leaf functions, but if the
9194 target-independent frame size is nonzero, we have already committed to
9195 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9196 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9198 /* The MIPS 3.0 linker does not like functions that dynamically
9199 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9200 looks like we are trying to create a second frame pointer to the
9201 function, so allocate some stack space to make it happy. */
9202 if (cfun->calls_alloca)
9203 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9205 frame->args_size = 0;
9206 frame->cprestore_size = 0;
9210 frame->args_size = crtl->outgoing_args_size;
9211 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9213 offset = frame->args_size + frame->cprestore_size;
9215 /* Move above the local variables. */
9216 frame->var_size = MIPS_STACK_ALIGN (size);
9217 offset += frame->var_size;
9219 /* Find out which GPRs we need to save. */
9220 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9221 if (mips_save_reg_p (regno))
9224 frame->mask |= 1 << (regno - GP_REG_FIRST);
9227 /* If this function calls eh_return, we must also save and restore the
9228 EH data registers. */
9229 if (crtl->calls_eh_return)
9230 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9233 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9236 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9237 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9238 save all later registers too. */
9239 if (GENERATE_MIPS16E_SAVE_RESTORE)
9241 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9242 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9243 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9244 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9247 /* Move above the GPR save area. */
9248 if (frame->num_gp > 0)
9250 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9251 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9254 /* Find out which FPRs we need to save. This loop must iterate over
9255 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9256 if (TARGET_HARD_FLOAT)
9257 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9258 if (mips_save_reg_p (regno))
9260 frame->num_fp += MAX_FPRS_PER_FMT;
9261 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9264 /* Move above the FPR save area. */
9265 if (frame->num_fp > 0)
9267 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9268 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9271 /* Add in space for the interrupt context information. */
9272 if (cfun->machine->interrupt_handler_p)
9275 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9278 frame->acc_mask |= (1 << 0);
9281 /* Check accumulators 1, 2, 3. */
9282 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9283 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9286 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9289 /* All interrupt context functions need space to preserve STATUS. */
9290 frame->num_cop0_regs++;
9292 /* If we don't keep interrupts masked, we need to save EPC. */
9293 if (!cfun->machine->keep_interrupts_masked_p)
9294 frame->num_cop0_regs++;
9297 /* Move above the accumulator save area. */
9298 if (frame->num_acc > 0)
9300 /* Each accumulator needs 2 words. */
9301 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9302 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9305 /* Move above the COP0 register save area. */
9306 if (frame->num_cop0_regs > 0)
9308 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9309 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9312 /* Move above the callee-allocated varargs save area. */
9313 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9314 frame->arg_pointer_offset = offset;
9316 /* Move above the callee-allocated area for pretend stack arguments. */
9317 offset += crtl->args.pretend_args_size;
9318 frame->total_size = offset;
9320 /* Work out the offsets of the save areas from the top of the frame. */
9321 if (frame->gp_sp_offset > 0)
9322 frame->gp_save_offset = frame->gp_sp_offset - offset;
9323 if (frame->fp_sp_offset > 0)
9324 frame->fp_save_offset = frame->fp_sp_offset - offset;
9325 if (frame->acc_sp_offset > 0)
9326 frame->acc_save_offset = frame->acc_sp_offset - offset;
9327 if (frame->num_cop0_regs > 0)
9328 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9330 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9331 arguments. This tends to increase the chances of using unextended
9332 instructions for local variables and incoming arguments. */
9334 frame->hard_frame_pointer_offset = frame->args_size;
9337 /* Return the style of GP load sequence that is being used for the
9338 current function. */
9340 enum mips_loadgp_style
9341 mips_current_loadgp_style (void)
9343 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9349 if (TARGET_ABSOLUTE_ABICALLS)
9350 return LOADGP_ABSOLUTE;
9352 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9355 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9358 mips_frame_pointer_required (void)
9360 /* If the function contains dynamic stack allocations, we need to
9361 use the frame pointer to access the static parts of the frame. */
9362 if (cfun->calls_alloca)
9365 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9366 reload may be unable to compute the address of a local variable,
9367 since there is no way to add a large constant to the stack pointer
9368 without using a second temporary register. */
9371 mips_compute_frame_info ();
9372 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9379 /* Make sure that we're not trying to eliminate to the wrong hard frame
9383 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9385 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9388 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9389 or argument pointer. TO is either the stack pointer or hard frame
9393 mips_initial_elimination_offset (int from, int to)
9395 HOST_WIDE_INT offset;
9397 mips_compute_frame_info ();
9399 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9402 case FRAME_POINTER_REGNUM:
9403 if (FRAME_GROWS_DOWNWARD)
9404 offset = (cfun->machine->frame.args_size
9405 + cfun->machine->frame.cprestore_size
9406 + cfun->machine->frame.var_size);
9411 case ARG_POINTER_REGNUM:
9412 offset = cfun->machine->frame.arg_pointer_offset;
9419 if (to == HARD_FRAME_POINTER_REGNUM)
9420 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9425 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9428 mips_extra_live_on_entry (bitmap regs)
9432 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9433 the global pointer. */
9434 if (!TARGET_ABSOLUTE_ABICALLS)
9435 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9437 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9438 the global pointer. */
9440 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9442 /* See the comment above load_call<mode> for details. */
9443 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9447 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9451 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9456 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9459 /* Emit code to change the current function's return address to
9460 ADDRESS. SCRATCH is available as a scratch register, if needed.
9461 ADDRESS and SCRATCH are both word-mode GPRs. */
9464 mips_set_return_address (rtx address, rtx scratch)
9468 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9469 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9470 cfun->machine->frame.gp_sp_offset);
9471 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9474 /* Return true if the current function has a cprestore slot. */
9477 mips_cfun_has_cprestore_slot_p (void)
9479 return (cfun->machine->global_pointer != INVALID_REGNUM
9480 && cfun->machine->frame.cprestore_size > 0);
9483 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9484 cprestore slot. LOAD_P is true if the caller wants to load from
9485 the cprestore slot; it is false if the caller wants to store to
9489 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9492 const struct mips_frame_info *frame;
9494 frame = &cfun->machine->frame;
9495 /* .cprestore always uses the stack pointer instead of the frame pointer.
9496 We have a free choice for direct stores for non-MIPS16 functions,
9497 and for MIPS16 functions whose cprestore slot is in range of the
9498 stack pointer. Using the stack pointer would sometimes give more
9499 (early) scheduling freedom, but using the frame pointer would
9500 sometimes give more (late) scheduling freedom. It's hard to
9501 predict which applies to a given function, so let's keep things
9504 Loads must always use the frame pointer in functions that call
9505 alloca, and there's little benefit to using the stack pointer
9507 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9509 *base = hard_frame_pointer_rtx;
9510 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9514 *base = stack_pointer_rtx;
9515 *offset = frame->args_size;
9519 /* Return true if X is the load or store address of the cprestore slot;
9520 LOAD_P says which. */
9523 mips_cprestore_address_p (rtx x, bool load_p)
9525 rtx given_base, required_base;
9526 HOST_WIDE_INT given_offset, required_offset;
9528 mips_split_plus (x, &given_base, &given_offset);
9529 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9530 return given_base == required_base && given_offset == required_offset;
9533 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9534 going to load from it, false if we are going to store to it.
9535 Use TEMP as a temporary register if need be. */
9538 mips_cprestore_slot (rtx temp, bool load_p)
9541 HOST_WIDE_INT offset;
9543 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9544 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9547 /* Emit instructions to save global pointer value GP into cprestore
9548 slot MEM. OFFSET is the offset that MEM applies to the base register.
9550 MEM may not be a legitimate address. If it isn't, TEMP is a
9551 temporary register that can be used, otherwise it is a SCRATCH. */
9554 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9556 if (TARGET_CPRESTORE_DIRECTIVE)
9558 gcc_assert (gp == pic_offset_table_rtx);
9559 emit_insn (gen_cprestore (mem, offset));
9562 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9565 /* Restore $gp from its save slot, using TEMP as a temporary base register
9566 if need be. This function is for o32 and o64 abicalls only.
9568 See mips_must_initialize_gp_p for details about how we manage the
9572 mips_restore_gp_from_cprestore_slot (rtx temp)
9574 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9576 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9578 emit_note (NOTE_INSN_DELETED);
9584 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9585 mips_emit_move (pic_offset_table_rtx, temp);
9588 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9589 if (!TARGET_EXPLICIT_RELOCS)
9590 emit_insn (gen_blockage ());
9593 /* A function to save or store a register. The first argument is the
9594 register and the second is the stack slot. */
9595 typedef void (*mips_save_restore_fn) (rtx, rtx);
9597 /* Use FN to save or restore register REGNO. MODE is the register's
9598 mode and OFFSET is the offset of its save slot from the current
9602 mips_save_restore_reg (enum machine_mode mode, int regno,
9603 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9607 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9608 fn (gen_rtx_REG (mode, regno), mem);
9611 /* Call FN for each accumlator that is saved by the current function.
9612 SP_OFFSET is the offset of the current stack pointer from the start
9616 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9618 HOST_WIDE_INT offset;
9621 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9622 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9624 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9625 offset -= UNITS_PER_WORD;
9626 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9627 offset -= UNITS_PER_WORD;
9630 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9631 if (BITSET_P (cfun->machine->frame.acc_mask,
9632 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9634 mips_save_restore_reg (word_mode, regno, offset, fn);
9635 offset -= UNITS_PER_WORD;
9639 /* Call FN for each register that is saved by the current function.
9640 SP_OFFSET is the offset of the current stack pointer from the start
9644 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9645 mips_save_restore_fn fn)
9647 enum machine_mode fpr_mode;
9648 HOST_WIDE_INT offset;
9651 /* Save registers starting from high to low. The debuggers prefer at least
9652 the return register be stored at func+4, and also it allows us not to
9653 need a nop in the epilogue if at least one register is reloaded in
9654 addition to return address. */
9655 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9656 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9657 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9659 /* Record the ra offset for use by mips_function_profiler. */
9660 if (regno == RETURN_ADDR_REGNUM)
9661 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9662 mips_save_restore_reg (word_mode, regno, offset, fn);
9663 offset -= UNITS_PER_WORD;
9666 /* This loop must iterate over the same space as its companion in
9667 mips_compute_frame_info. */
9668 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9669 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9670 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9671 regno >= FP_REG_FIRST;
9672 regno -= MAX_FPRS_PER_FMT)
9673 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9675 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9676 offset -= GET_MODE_SIZE (fpr_mode);
9680 /* Return true if a move between register REGNO and its save slot (MEM)
9681 can be done in a single move. LOAD_P is true if we are loading
9682 from the slot, false if we are storing to it. */
9685 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9687 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9688 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9691 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9692 GET_MODE (mem), mem, load_p) == NO_REGS;
9695 /* Emit a move from SRC to DEST, given that one of them is a register
9696 save slot and that the other is a register. TEMP is a temporary
9697 GPR of the same mode that is available if need be. */
9700 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9707 regno = REGNO (src);
9712 regno = REGNO (dest);
9716 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9718 /* We don't yet know whether we'll need this instruction or not.
9719 Postpone the decision by emitting a ghost move. This move
9720 is specifically not frame-related; only the split version is. */
9722 emit_insn (gen_move_gpdi (dest, src));
9724 emit_insn (gen_move_gpsi (dest, src));
9728 if (regno == HI_REGNUM)
9732 mips_emit_move (temp, src);
9734 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9735 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9737 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9738 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9743 emit_insn (gen_mfhidi_ti (temp,
9744 gen_rtx_REG (TImode, MD_REG_FIRST)));
9746 emit_insn (gen_mfhisi_di (temp,
9747 gen_rtx_REG (DImode, MD_REG_FIRST)));
9748 mips_emit_move (dest, temp);
9751 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9752 mips_emit_move (dest, src);
9755 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9756 mips_emit_move (temp, src);
9757 mips_emit_move (dest, temp);
9760 mips_set_frame_expr (mips_frame_set (dest, src));
9763 /* If we're generating n32 or n64 abicalls, and the current function
9764 does not use $28 as its global pointer, emit a cplocal directive.
9765 Use pic_offset_table_rtx as the argument to the directive. */
9768 mips_output_cplocal (void)
9770 if (!TARGET_EXPLICIT_RELOCS
9771 && mips_must_initialize_gp_p ()
9772 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9773 output_asm_insn (".cplocal %+", 0);
9776 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9779 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9783 #ifdef SDB_DEBUGGING_INFO
9784 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9785 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9788 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9789 floating-point arguments. */
9791 && TARGET_HARD_FLOAT_ABI
9792 && crtl->args.info.fp_code != 0)
9793 mips16_build_function_stub ();
9795 /* Get the function name the same way that toplev.c does before calling
9796 assemble_start_function. This is needed so that the name used here
9797 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9798 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9799 mips_start_function_definition (fnname, TARGET_MIPS16);
9801 /* Output MIPS-specific frame information. */
9802 if (!flag_inhibit_size_directive)
9804 const struct mips_frame_info *frame;
9806 frame = &cfun->machine->frame;
9808 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9810 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9811 "# vars= " HOST_WIDE_INT_PRINT_DEC
9813 ", args= " HOST_WIDE_INT_PRINT_DEC
9814 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9815 reg_names[frame_pointer_needed
9816 ? HARD_FRAME_POINTER_REGNUM
9817 : STACK_POINTER_REGNUM],
9818 (frame_pointer_needed
9819 ? frame->total_size - frame->hard_frame_pointer_offset
9820 : frame->total_size),
9821 reg_names[RETURN_ADDR_REGNUM],
9823 frame->num_gp, frame->num_fp,
9825 frame->cprestore_size);
9827 /* .mask MASK, OFFSET. */
9828 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9829 frame->mask, frame->gp_save_offset);
9831 /* .fmask MASK, OFFSET. */
9832 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9833 frame->fmask, frame->fp_save_offset);
9836 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9837 Also emit the ".set noreorder; .set nomacro" sequence for functions
9839 if (mips_must_initialize_gp_p ()
9840 && mips_current_loadgp_style () == LOADGP_OLDABI)
9844 /* This is a fixed-form sequence. The position of the
9845 first two instructions is important because of the
9846 way _gp_disp is defined. */
9847 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9848 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9849 output_asm_insn ("sll\t$2,16", 0);
9850 output_asm_insn ("addu\t$2,$3", 0);
9854 /* .cpload must be in a .set noreorder but not a
9855 .set nomacro block. */
9856 mips_push_asm_switch (&mips_noreorder);
9857 output_asm_insn (".cpload\t%^", 0);
9858 if (!cfun->machine->all_noreorder_p)
9859 mips_pop_asm_switch (&mips_noreorder);
9861 mips_push_asm_switch (&mips_nomacro);
9864 else if (cfun->machine->all_noreorder_p)
9866 mips_push_asm_switch (&mips_noreorder);
9867 mips_push_asm_switch (&mips_nomacro);
9870 /* Tell the assembler which register we're using as the global
9871 pointer. This is needed for thunks, since they can use either
9872 explicit relocs or assembler macros. */
9873 mips_output_cplocal ();
9876 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9879 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9880 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9884 /* Reinstate the normal $gp. */
9885 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9886 mips_output_cplocal ();
9888 if (cfun->machine->all_noreorder_p)
9890 mips_pop_asm_switch (&mips_nomacro);
9891 mips_pop_asm_switch (&mips_noreorder);
9894 /* Get the function name the same way that toplev.c does before calling
9895 assemble_start_function. This is needed so that the name used here
9896 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9897 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9898 mips_end_function_definition (fnname);
9901 /* Save register REG to MEM. Make the instruction frame-related. */
9904 mips_save_reg (rtx reg, rtx mem)
9906 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
9910 if (mips_split_64bit_move_p (mem, reg))
9911 mips_split_doubleword_move (mem, reg);
9913 mips_emit_move (mem, reg);
9915 x1 = mips_frame_set (mips_subword (mem, false),
9916 mips_subword (reg, false));
9917 x2 = mips_frame_set (mips_subword (mem, true),
9918 mips_subword (reg, true));
9919 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
9922 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
9925 /* The __gnu_local_gp symbol. */
9927 static GTY(()) rtx mips_gnu_local_gp;
9929 /* If we're generating n32 or n64 abicalls, emit instructions
9930 to set up the global pointer. */
9933 mips_emit_loadgp (void)
9935 rtx addr, offset, incoming_address, base, index, pic_reg;
9937 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
9938 switch (mips_current_loadgp_style ())
9940 case LOADGP_ABSOLUTE:
9941 if (mips_gnu_local_gp == NULL)
9943 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
9944 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
9946 emit_insn (Pmode == SImode
9947 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
9948 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
9952 /* Added by mips_output_function_prologue. */
9956 addr = XEXP (DECL_RTL (current_function_decl), 0);
9957 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
9958 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
9959 emit_insn (Pmode == SImode
9960 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
9961 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
9965 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
9966 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
9967 emit_insn (Pmode == SImode
9968 ? gen_loadgp_rtp_si (pic_reg, base, index)
9969 : gen_loadgp_rtp_di (pic_reg, base, index));
9977 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
9979 /* Emit a blockage if there are implicit uses of the GP register.
9980 This includes profiled functions, because FUNCTION_PROFILE uses
9982 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
9983 emit_insn (gen_loadgp_blockage ());
9986 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
9989 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
9991 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
9994 /* Expand the "prologue" pattern. */
9997 mips_expand_prologue (void)
9999 const struct mips_frame_info *frame;
10000 HOST_WIDE_INT size;
10001 unsigned int nargs;
10004 if (cfun->machine->global_pointer != INVALID_REGNUM)
10006 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10007 or implicitly. If so, we can commit to using a global pointer
10008 straight away, otherwise we need to defer the decision. */
10009 if (mips_cfun_has_inflexible_gp_ref_p ()
10010 || mips_cfun_has_flexible_gp_ref_p ())
10012 cfun->machine->must_initialize_gp_p = true;
10013 cfun->machine->must_restore_gp_when_clobbered_p = true;
10016 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10019 frame = &cfun->machine->frame;
10020 size = frame->total_size;
10022 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10023 bytes beforehand; this is enough to cover the register save area
10024 without going out of range. */
10025 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10026 || frame->num_cop0_regs > 0)
10028 HOST_WIDE_INT step1;
10030 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10031 if (GENERATE_MIPS16E_SAVE_RESTORE)
10033 HOST_WIDE_INT offset;
10034 unsigned int mask, regno;
10036 /* Try to merge argument stores into the save instruction. */
10037 nargs = mips16e_collect_argument_saves ();
10039 /* Build the save instruction. */
10040 mask = frame->mask;
10041 insn = mips16e_build_save_restore (false, &mask, &offset,
10043 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10046 /* Check if we need to save other registers. */
10047 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10048 if (BITSET_P (mask, regno - GP_REG_FIRST))
10050 offset -= UNITS_PER_WORD;
10051 mips_save_restore_reg (word_mode, regno,
10052 offset, mips_save_reg);
10057 if (cfun->machine->interrupt_handler_p)
10059 HOST_WIDE_INT offset;
10062 /* If this interrupt is using a shadow register set, we need to
10063 get the stack pointer from the previous register set. */
10064 if (cfun->machine->use_shadow_register_set_p)
10065 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10066 stack_pointer_rtx));
10068 if (!cfun->machine->keep_interrupts_masked_p)
10070 /* Move from COP0 Cause to K0. */
10071 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10072 gen_rtx_REG (SImode,
10073 COP0_CAUSE_REG_NUM)));
10074 /* Move from COP0 EPC to K1. */
10075 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10076 gen_rtx_REG (SImode,
10077 COP0_EPC_REG_NUM)));
10080 /* Allocate the first part of the frame. */
10081 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10083 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10086 /* Start at the uppermost location for saving. */
10087 offset = frame->cop0_sp_offset - size;
10088 if (!cfun->machine->keep_interrupts_masked_p)
10090 /* Push EPC into its stack slot. */
10091 mem = gen_frame_mem (word_mode,
10092 plus_constant (stack_pointer_rtx,
10094 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10095 offset -= UNITS_PER_WORD;
10098 /* Move from COP0 Status to K1. */
10099 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10100 gen_rtx_REG (SImode,
10101 COP0_STATUS_REG_NUM)));
10103 /* Right justify the RIPL in k0. */
10104 if (!cfun->machine->keep_interrupts_masked_p)
10105 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10106 gen_rtx_REG (SImode, K0_REG_NUM),
10107 GEN_INT (CAUSE_IPL)));
10109 /* Push Status into its stack slot. */
10110 mem = gen_frame_mem (word_mode,
10111 plus_constant (stack_pointer_rtx, offset));
10112 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10113 offset -= UNITS_PER_WORD;
10115 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10116 if (!cfun->machine->keep_interrupts_masked_p)
10117 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10120 gen_rtx_REG (SImode, K0_REG_NUM)));
10122 if (!cfun->machine->keep_interrupts_masked_p)
10123 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10124 IE is already the correct value, so we don't have to do
10125 anything explicit. */
10126 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10129 gen_rtx_REG (SImode, GP_REG_FIRST)));
10131 /* Disable interrupts by clearing the KSU, ERL, EXL,
10133 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10136 gen_rtx_REG (SImode, GP_REG_FIRST)));
10140 insn = gen_add3_insn (stack_pointer_rtx,
10143 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10146 mips_for_each_saved_acc (size, mips_save_reg);
10147 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10151 /* Allocate the rest of the frame. */
10154 if (SMALL_OPERAND (-size))
10155 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10157 GEN_INT (-size)))) = 1;
10160 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10163 /* There are no instructions to add or subtract registers
10164 from the stack pointer, so use the frame pointer as a
10165 temporary. We should always be using a frame pointer
10166 in this case anyway. */
10167 gcc_assert (frame_pointer_needed);
10168 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10169 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10170 hard_frame_pointer_rtx,
10171 MIPS_PROLOGUE_TEMP (Pmode)));
10172 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10175 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10177 MIPS_PROLOGUE_TEMP (Pmode)));
10179 /* Describe the combined effect of the previous instructions. */
10180 mips_set_frame_expr
10181 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10182 plus_constant (stack_pointer_rtx, -size)));
10186 /* Set up the frame pointer, if we're using one. */
10187 if (frame_pointer_needed)
10189 HOST_WIDE_INT offset;
10191 offset = frame->hard_frame_pointer_offset;
10194 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10195 RTX_FRAME_RELATED_P (insn) = 1;
10197 else if (SMALL_OPERAND (offset))
10199 insn = gen_add3_insn (hard_frame_pointer_rtx,
10200 stack_pointer_rtx, GEN_INT (offset));
10201 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10205 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10206 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10207 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10208 hard_frame_pointer_rtx,
10209 MIPS_PROLOGUE_TEMP (Pmode)));
10210 mips_set_frame_expr
10211 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10212 plus_constant (stack_pointer_rtx, offset)));
10216 mips_emit_loadgp ();
10218 /* Initialize the $gp save slot. */
10219 if (mips_cfun_has_cprestore_slot_p ())
10221 rtx base, mem, gp, temp;
10222 HOST_WIDE_INT offset;
10224 mips_get_cprestore_base_and_offset (&base, &offset, false);
10225 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10226 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10227 temp = (SMALL_OPERAND (offset)
10228 ? gen_rtx_SCRATCH (Pmode)
10229 : MIPS_PROLOGUE_TEMP (Pmode));
10230 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10232 mips_get_cprestore_base_and_offset (&base, &offset, true);
10233 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10234 emit_insn (gen_use_cprestore (mem));
10237 /* We need to search back to the last use of K0 or K1. */
10238 if (cfun->machine->interrupt_handler_p)
10240 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10242 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10244 /* Emit a move from K1 to COP0 Status after insn. */
10245 gcc_assert (insn != NULL_RTX);
10246 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10247 gen_rtx_REG (SImode, K1_REG_NUM)),
10251 /* If we are profiling, make sure no instructions are scheduled before
10252 the call to mcount. */
10254 emit_insn (gen_blockage ());
10257 /* Emit instructions to restore register REG from slot MEM. */
10260 mips_restore_reg (rtx reg, rtx mem)
10262 /* There's no MIPS16 instruction to load $31 directly. Load into
10263 $7 instead and adjust the return insn appropriately. */
10264 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10265 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10267 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10270 /* Emit any instructions needed before a return. */
10273 mips_expand_before_return (void)
10275 /* When using a call-clobbered gp, we start out with unified call
10276 insns that include instructions to restore the gp. We then split
10277 these unified calls after reload. These split calls explicitly
10278 clobber gp, so there is no need to define
10279 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10281 For consistency, we should also insert an explicit clobber of $28
10282 before return insns, so that the post-reload optimizers know that
10283 the register is not live on exit. */
10284 if (TARGET_CALL_CLOBBERED_GP)
10285 emit_clobber (pic_offset_table_rtx);
10288 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10292 mips_expand_epilogue (bool sibcall_p)
10294 const struct mips_frame_info *frame;
10295 HOST_WIDE_INT step1, step2;
10296 rtx base, target, insn;
10298 if (!sibcall_p && mips_can_use_return_insn ())
10300 emit_jump_insn (gen_return ());
10304 /* In MIPS16 mode, if the return value should go into a floating-point
10305 register, we need to call a helper routine to copy it over. */
10306 if (mips16_cfun_returns_in_fpr_p ())
10307 mips16_copy_fpr_return_value ();
10309 /* Split the frame into two. STEP1 is the amount of stack we should
10310 deallocate before restoring the registers. STEP2 is the amount we
10311 should deallocate afterwards.
10313 Start off by assuming that no registers need to be restored. */
10314 frame = &cfun->machine->frame;
10315 step1 = frame->total_size;
10318 /* Work out which register holds the frame address. */
10319 if (!frame_pointer_needed)
10320 base = stack_pointer_rtx;
10323 base = hard_frame_pointer_rtx;
10324 step1 -= frame->hard_frame_pointer_offset;
10327 /* If we need to restore registers, deallocate as much stack as
10328 possible in the second step without going out of range. */
10329 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10330 || frame->num_cop0_regs > 0)
10332 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10336 /* Set TARGET to BASE + STEP1. */
10342 /* Get an rtx for STEP1 that we can add to BASE. */
10343 adjust = GEN_INT (step1);
10344 if (!SMALL_OPERAND (step1))
10346 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10347 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10350 /* Normal mode code can copy the result straight into $sp. */
10351 if (!TARGET_MIPS16)
10352 target = stack_pointer_rtx;
10354 emit_insn (gen_add3_insn (target, base, adjust));
10357 /* Copy TARGET into the stack pointer. */
10358 if (target != stack_pointer_rtx)
10359 mips_emit_move (stack_pointer_rtx, target);
10361 /* If we're using addressing macros, $gp is implicitly used by all
10362 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10364 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10365 emit_insn (gen_blockage ());
10367 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10369 unsigned int regno, mask;
10370 HOST_WIDE_INT offset;
10373 /* Generate the restore instruction. */
10374 mask = frame->mask;
10375 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10377 /* Restore any other registers manually. */
10378 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10379 if (BITSET_P (mask, regno - GP_REG_FIRST))
10381 offset -= UNITS_PER_WORD;
10382 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10385 /* Restore the remaining registers and deallocate the final bit
10387 emit_insn (restore);
10391 /* Restore the registers. */
10392 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10393 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10396 if (cfun->machine->interrupt_handler_p)
10398 HOST_WIDE_INT offset;
10401 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10402 if (!cfun->machine->keep_interrupts_masked_p)
10404 /* Restore the original EPC. */
10405 mem = gen_frame_mem (word_mode,
10406 plus_constant (stack_pointer_rtx, offset));
10407 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10408 offset -= UNITS_PER_WORD;
10410 /* Move to COP0 EPC. */
10411 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10412 gen_rtx_REG (SImode, K0_REG_NUM)));
10415 /* Restore the original Status. */
10416 mem = gen_frame_mem (word_mode,
10417 plus_constant (stack_pointer_rtx, offset));
10418 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10419 offset -= UNITS_PER_WORD;
10421 /* If we don't use shoadow register set, we need to update SP. */
10422 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10423 emit_insn (gen_add3_insn (stack_pointer_rtx,
10427 /* Move to COP0 Status. */
10428 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10429 gen_rtx_REG (SImode, K0_REG_NUM)));
10433 /* Deallocate the final bit of the frame. */
10435 emit_insn (gen_add3_insn (stack_pointer_rtx,
10441 /* Add in the __builtin_eh_return stack adjustment. We need to
10442 use a temporary in MIPS16 code. */
10443 if (crtl->calls_eh_return)
10447 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10448 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10449 MIPS_EPILOGUE_TEMP (Pmode),
10450 EH_RETURN_STACKADJ_RTX));
10451 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10454 emit_insn (gen_add3_insn (stack_pointer_rtx,
10456 EH_RETURN_STACKADJ_RTX));
10461 mips_expand_before_return ();
10462 if (cfun->machine->interrupt_handler_p)
10464 /* Interrupt handlers generate eret or deret. */
10465 if (cfun->machine->use_debug_exception_return_p)
10466 emit_jump_insn (gen_mips_deret ());
10468 emit_jump_insn (gen_mips_eret ());
10472 unsigned int regno;
10474 /* When generating MIPS16 code, the normal
10475 mips_for_each_saved_gpr_and_fpr path will restore the return
10476 address into $7 rather than $31. */
10478 && !GENERATE_MIPS16E_SAVE_RESTORE
10479 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10480 regno = GP_REG_FIRST + 7;
10482 regno = RETURN_ADDR_REGNUM;
10483 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10487 /* Search from the beginning to the first use of K0 or K1. */
10488 if (cfun->machine->interrupt_handler_p
10489 && !cfun->machine->keep_interrupts_masked_p)
10491 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10493 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10495 gcc_assert (insn != NULL_RTX);
10496 /* Insert disable interrupts before the first use of K0 or K1. */
10497 emit_insn_before (gen_mips_di (), insn);
10498 emit_insn_before (gen_mips_ehb (), insn);
10502 /* Return nonzero if this function is known to have a null epilogue.
10503 This allows the optimizer to omit jumps to jumps if no stack
10507 mips_can_use_return_insn (void)
10509 /* Interrupt handlers need to go through the epilogue. */
10510 if (cfun->machine->interrupt_handler_p)
10513 if (!reload_completed)
10519 /* In MIPS16 mode, a function that returns a floating-point value
10520 needs to arrange to copy the return value into the floating-point
10522 if (mips16_cfun_returns_in_fpr_p ())
10525 return cfun->machine->frame.total_size == 0;
10528 /* Return true if register REGNO can store a value of mode MODE.
10529 The result of this function is cached in mips_hard_regno_mode_ok. */
10532 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10535 enum mode_class mclass;
10537 if (mode == CCV2mode)
10538 return (ISA_HAS_8CC
10539 && ST_REG_P (regno)
10540 && (regno - ST_REG_FIRST) % 2 == 0);
10542 if (mode == CCV4mode)
10543 return (ISA_HAS_8CC
10544 && ST_REG_P (regno)
10545 && (regno - ST_REG_FIRST) % 4 == 0);
10547 if (mode == CCmode)
10550 return regno == FPSW_REGNUM;
10552 return (ST_REG_P (regno)
10553 || GP_REG_P (regno)
10554 || FP_REG_P (regno));
10557 size = GET_MODE_SIZE (mode);
10558 mclass = GET_MODE_CLASS (mode);
10560 if (GP_REG_P (regno))
10561 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10563 if (FP_REG_P (regno)
10564 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10565 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10567 /* Allow TFmode for CCmode reloads. */
10568 if (mode == TFmode && ISA_HAS_8CC)
10571 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10572 if (TARGET_LOONGSON_VECTORS
10573 && (mode == V2SImode
10574 || mode == V4HImode
10575 || mode == V8QImode
10576 || mode == DImode))
10579 if (mclass == MODE_FLOAT
10580 || mclass == MODE_COMPLEX_FLOAT
10581 || mclass == MODE_VECTOR_FLOAT)
10582 return size <= UNITS_PER_FPVALUE;
10584 /* Allow integer modes that fit into a single register. We need
10585 to put integers into FPRs when using instructions like CVT
10586 and TRUNC. There's no point allowing sizes smaller than a word,
10587 because the FPU has no appropriate load/store instructions. */
10588 if (mclass == MODE_INT)
10589 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10592 if (ACC_REG_P (regno)
10593 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10595 if (MD_REG_P (regno))
10597 /* After a multiplication or division, clobbering HI makes
10598 the value of LO unpredictable, and vice versa. This means
10599 that, for all interesting cases, HI and LO are effectively
10602 We model this by requiring that any value that uses HI
10604 if (size <= UNITS_PER_WORD * 2)
10605 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10609 /* DSP accumulators do not have the same restrictions as
10610 HI and LO, so we can treat them as normal doubleword
10612 if (size <= UNITS_PER_WORD)
10615 if (size <= UNITS_PER_WORD * 2
10616 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10621 if (ALL_COP_REG_P (regno))
10622 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10624 if (regno == GOT_VERSION_REGNUM)
10625 return mode == SImode;
10630 /* Implement HARD_REGNO_NREGS. */
10633 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10635 if (ST_REG_P (regno))
10636 /* The size of FP status registers is always 4, because they only hold
10637 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10638 return (GET_MODE_SIZE (mode) + 3) / 4;
10640 if (FP_REG_P (regno))
10641 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10643 /* All other registers are word-sized. */
10644 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10647 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10648 in mips_hard_regno_nregs. */
10651 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10657 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10658 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10660 size = MIN (size, 4);
10661 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10663 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10665 size = MIN (size, UNITS_PER_FPREG);
10666 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10668 if (!hard_reg_set_empty_p (left))
10669 size = MIN (size, UNITS_PER_WORD);
10670 return (GET_MODE_SIZE (mode) + size - 1) / size;
10673 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10676 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10677 enum machine_mode to ATTRIBUTE_UNUSED,
10678 enum reg_class rclass)
10680 /* There are several problems with changing the modes of values
10681 in floating-point registers:
10683 - When a multi-word value is stored in paired floating-point
10684 registers, the first register always holds the low word.
10685 We therefore can't allow FPRs to change between single-word
10686 and multi-word modes on big-endian targets.
10688 - GCC assumes that each word of a multiword register can be accessed
10689 individually using SUBREGs. This is not true for floating-point
10690 registers if they are bigger than a word.
10692 - Loading a 32-bit value into a 64-bit floating-point register
10693 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10694 We can't allow FPRs to change from SImode to to a wider mode on
10697 - If the FPU has already interpreted a value in one format, we must
10698 not ask it to treat the value as having a different format.
10700 We therefore disallow all mode changes involving FPRs. */
10701 return reg_classes_intersect_p (FP_REGS, rclass);
10704 /* Implement target hook small_register_classes_for_mode_p. */
10707 mips_small_register_classes_for_mode_p (enum machine_mode mode
10710 return TARGET_MIPS16;
10713 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10716 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10721 return TARGET_HARD_FLOAT;
10724 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10727 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10734 /* Implement MODES_TIEABLE_P. */
10737 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10739 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10740 prefer to put one of them in FPRs. */
10741 return (mode1 == mode2
10742 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10743 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10746 /* Implement PREFERRED_RELOAD_CLASS. */
10749 mips_preferred_reload_class (rtx x, enum reg_class rclass)
10751 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10754 if (reg_class_subset_p (FP_REGS, rclass)
10755 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10758 if (reg_class_subset_p (GR_REGS, rclass))
10761 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10767 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10768 Return a "canonical" class to represent it in later calculations. */
10770 static enum reg_class
10771 mips_canonicalize_move_class (enum reg_class rclass)
10773 /* All moves involving accumulator registers have the same cost. */
10774 if (reg_class_subset_p (rclass, ACC_REGS))
10777 /* Likewise promote subclasses of general registers to the most
10778 interesting containing class. */
10779 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10781 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10782 rclass = GENERAL_REGS;
10787 /* Return the cost of moving a value of mode MODE from a register of
10788 class FROM to a GPR. Return 0 for classes that are unions of other
10789 classes handled by this function. */
10792 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10793 enum reg_class from)
10798 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10802 /* MFLO and MFHI. */
10810 /* LUI followed by MOVF. */
10816 /* This choice of value is historical. */
10824 /* Return the cost of moving a value of mode MODE from a GPR to a
10825 register of class TO. Return 0 for classes that are unions of
10826 other classes handled by this function. */
10829 mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to)
10834 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10838 /* MTLO and MTHI. */
10846 /* A secondary reload through an FPR scratch. */
10847 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10848 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10853 /* This choice of value is historical. */
10861 /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the
10862 maximum of the move costs for subclasses; regclass will work out
10863 the maximum for us. */
10866 mips_register_move_cost (enum machine_mode mode,
10867 enum reg_class from, enum reg_class to)
10869 enum reg_class dregs;
10872 from = mips_canonicalize_move_class (from);
10873 to = mips_canonicalize_move_class (to);
10875 /* Handle moves that can be done without using general-purpose registers. */
10876 if (from == FP_REGS)
10878 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10882 /* The sequence generated by mips_expand_fcc_reload. */
10886 /* Handle cases in which only one class deviates from the ideal. */
10887 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
10889 return mips_move_from_gpr_cost (mode, to);
10891 return mips_move_to_gpr_cost (mode, from);
10893 /* Handles cases that require a GPR temporary. */
10894 cost1 = mips_move_to_gpr_cost (mode, from);
10897 cost2 = mips_move_from_gpr_cost (mode, to);
10899 return cost1 + cost2;
10905 /* Implement TARGET_IRA_COVER_CLASSES. */
10907 static const enum reg_class *
10908 mips_ira_cover_classes (void)
10910 static const enum reg_class acc_classes[] = {
10911 GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10912 ST_REGS, LIM_REG_CLASSES
10914 static const enum reg_class no_acc_classes[] = {
10915 GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
10916 ST_REGS, LIM_REG_CLASSES
10919 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10920 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10921 as a cover class only works well when we keep per-register costs.
10922 Using it when not optimizing can cause us to think accumulators
10923 have the same cost as GPRs in cases where GPRs are actually much
10925 return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes;
10928 /* Return the register class required for a secondary register when
10929 copying between one of the registers in RCLASS and value X, which
10930 has mode MODE. X is the source of the move if IN_P, otherwise it
10931 is the destination. Return NO_REGS if no secondary register is
10935 mips_secondary_reload_class (enum reg_class rclass,
10936 enum machine_mode mode, rtx x, bool in_p)
10940 /* If X is a constant that cannot be loaded into $25, it must be loaded
10941 into some other GPR. No other register class allows a direct move. */
10942 if (mips_dangerous_for_la25_p (x))
10943 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
10945 regno = true_regnum (x);
10948 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
10949 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
10955 /* Copying from accumulator registers to anywhere other than a general
10956 register requires a temporary general register. */
10957 if (reg_class_subset_p (rclass, ACC_REGS))
10958 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10959 if (ACC_REG_P (regno))
10960 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10962 /* We can only copy a value to a condition code register from a
10963 floating-point register, and even then we require a scratch
10964 floating-point register. We can only copy a value out of a
10965 condition-code register into a general register. */
10966 if (reg_class_subset_p (rclass, ST_REGS))
10970 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
10972 if (ST_REG_P (regno))
10976 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
10979 if (reg_class_subset_p (rclass, FP_REGS))
10982 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
10983 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
10984 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
10987 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
10988 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
10991 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x))
10992 /* We can force the constant to memory and use lwc1
10993 and ldc1. As above, we will use pairs of lwc1s if
10994 ldc1 is not supported. */
10997 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
10998 /* In this case we can use mov.fmt. */
11001 /* Otherwise, we need to reload through an integer register. */
11004 if (FP_REG_P (regno))
11005 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11010 /* Implement TARGET_MODE_REP_EXTENDED. */
11013 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11015 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11016 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11017 return SIGN_EXTEND;
11022 /* Implement TARGET_VALID_POINTER_MODE. */
11025 mips_valid_pointer_mode (enum machine_mode mode)
11027 return mode == SImode || (TARGET_64BIT && mode == DImode);
11030 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11033 mips_vector_mode_supported_p (enum machine_mode mode)
11038 return TARGET_PAIRED_SINGLE_FLOAT;
11053 return TARGET_LOONGSON_VECTORS;
11060 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11063 mips_scalar_mode_supported_p (enum machine_mode mode)
11065 if (ALL_FIXED_POINT_MODE_P (mode)
11066 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11069 return default_scalar_mode_supported_p (mode);
11072 /* Implement TARGET_INIT_LIBFUNCS. */
11074 #include "config/gofast.h"
11077 mips_init_libfuncs (void)
11079 if (TARGET_FIX_VR4120)
11081 /* Register the special divsi3 and modsi3 functions needed to work
11082 around VR4120 division errata. */
11083 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11084 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11087 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11089 /* Register the MIPS16 -mhard-float stubs. */
11090 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11091 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11092 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11093 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11095 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11096 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11097 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11098 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11099 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11100 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11101 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11103 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11104 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11105 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11107 if (TARGET_DOUBLE_FLOAT)
11109 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11110 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11111 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11112 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11114 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11115 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11116 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11117 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11118 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11119 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11120 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11122 set_conv_libfunc (sext_optab, DFmode, SFmode,
11123 "__mips16_extendsfdf2");
11124 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11125 "__mips16_truncdfsf2");
11126 set_conv_libfunc (sfix_optab, SImode, DFmode,
11127 "__mips16_fix_truncdfsi");
11128 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11129 "__mips16_floatsidf");
11130 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11131 "__mips16_floatunsidf");
11135 /* Register the gofast functions if selected using --enable-gofast. */
11136 gofast_maybe_init_libfuncs ();
11138 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11139 on an external non-MIPS16 routine to implement __sync_synchronize. */
11141 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11144 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11147 mips_process_load_label (rtx target)
11149 rtx base, gp, intop;
11150 HOST_WIDE_INT offset;
11152 mips_multi_start ();
11156 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11157 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11161 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11162 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11166 gp = pic_offset_table_rtx;
11167 if (mips_cfun_has_cprestore_slot_p ())
11169 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11170 mips_get_cprestore_base_and_offset (&base, &offset, true);
11171 if (!SMALL_OPERAND (offset))
11173 intop = GEN_INT (CONST_HIGH_PART (offset));
11174 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11175 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11178 offset = CONST_LOW_PART (offset);
11180 intop = GEN_INT (offset);
11181 if (ISA_HAS_LOAD_DELAY)
11182 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11184 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11186 if (ISA_HAS_LOAD_DELAY)
11187 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11189 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11190 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11195 /* Return the number of instructions needed to load a label into $AT. */
11197 static unsigned int
11198 mips_load_label_length (void)
11200 if (cfun->machine->load_label_length == 0)
11202 mips_process_load_label (pc_rtx);
11203 cfun->machine->load_label_length = mips_multi_num_insns;
11205 return cfun->machine->load_label_length;
11208 /* Emit an asm sequence to start a noat block and load the address
11209 of a label into $1. */
11212 mips_output_load_label (rtx target)
11214 mips_push_asm_switch (&mips_noat);
11215 if (TARGET_EXPLICIT_RELOCS)
11217 mips_process_load_label (target);
11218 mips_multi_write ();
11222 if (Pmode == DImode)
11223 output_asm_insn ("dla\t%@,%0", &target);
11225 output_asm_insn ("la\t%@,%0", &target);
11229 /* Return the length of INSN. LENGTH is the initial length computed by
11230 attributes in the machine-description file. */
11233 mips_adjust_insn_length (rtx insn, int length)
11235 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11236 of a PIC long-branch sequence. Substitute the correct value. */
11237 if (length == MAX_PIC_BRANCH_LENGTH
11238 && INSN_CODE (insn) >= 0
11239 && get_attr_type (insn) == TYPE_BRANCH)
11241 /* Add the branch-over instruction and its delay slot, if this
11242 is a conditional branch. */
11243 length = simplejump_p (insn) ? 0 : 8;
11245 /* Load the label into $AT and jump to it. Ignore the delay
11246 slot of the jump. */
11247 length += mips_load_label_length () + 4;
11250 /* A unconditional jump has an unfilled delay slot if it is not part
11251 of a sequence. A conditional jump normally has a delay slot, but
11252 does not on MIPS16. */
11253 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11256 /* See how many nops might be needed to avoid hardware hazards. */
11257 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11258 switch (get_attr_hazard (insn))
11272 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11273 the .md file length attributes are 4-based for both modes.
11274 Adjust the MIPS16 ones here. */
11281 /* Return the assembly code for INSN, which has the operands given by
11282 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11283 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11284 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11285 version of BRANCH_IF_TRUE. */
11288 mips_output_conditional_branch (rtx insn, rtx *operands,
11289 const char *branch_if_true,
11290 const char *branch_if_false)
11292 unsigned int length;
11293 rtx taken, not_taken;
11295 gcc_assert (LABEL_P (operands[0]));
11297 length = get_attr_length (insn);
11300 /* Just a simple conditional branch. */
11301 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11302 return branch_if_true;
11305 /* Generate a reversed branch around a direct jump. This fallback does
11306 not use branch-likely instructions. */
11307 mips_branch_likely = false;
11308 not_taken = gen_label_rtx ();
11309 taken = operands[0];
11311 /* Generate the reversed branch to NOT_TAKEN. */
11312 operands[0] = not_taken;
11313 output_asm_insn (branch_if_false, operands);
11315 /* If INSN has a delay slot, we must provide delay slots for both the
11316 branch to NOT_TAKEN and the conditional jump. We must also ensure
11317 that INSN's delay slot is executed in the appropriate cases. */
11318 if (final_sequence)
11320 /* This first delay slot will always be executed, so use INSN's
11321 delay slot if is not annulled. */
11322 if (!INSN_ANNULLED_BRANCH_P (insn))
11324 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11325 asm_out_file, optimize, 1, NULL);
11326 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11329 output_asm_insn ("nop", 0);
11330 fprintf (asm_out_file, "\n");
11333 /* Output the unconditional branch to TAKEN. */
11334 if (TARGET_ABSOLUTE_JUMPS)
11335 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11338 mips_output_load_label (taken);
11339 output_asm_insn ("jr\t%@%]%/", 0);
11342 /* Now deal with its delay slot; see above. */
11343 if (final_sequence)
11345 /* This delay slot will only be executed if the branch is taken.
11346 Use INSN's delay slot if is annulled. */
11347 if (INSN_ANNULLED_BRANCH_P (insn))
11349 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11350 asm_out_file, optimize, 1, NULL);
11351 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11354 output_asm_insn ("nop", 0);
11355 fprintf (asm_out_file, "\n");
11358 /* Output NOT_TAKEN. */
11359 targetm.asm_out.internal_label (asm_out_file, "L",
11360 CODE_LABEL_NUMBER (not_taken));
11364 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11365 if some ordering condition is true. The condition is given by
11366 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11367 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11368 its second is always zero. */
11371 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11373 const char *branch[2];
11375 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11376 Make BRANCH[0] branch on the inverse condition. */
11377 switch (GET_CODE (operands[1]))
11379 /* These cases are equivalent to comparisons against zero. */
11381 inverted_p = !inverted_p;
11382 /* Fall through. */
11384 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11385 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11388 /* These cases are always true or always false. */
11390 inverted_p = !inverted_p;
11391 /* Fall through. */
11393 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11394 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11398 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11399 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11402 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11405 /* Start a block of code that needs access to the LL, SC and SYNC
11409 mips_start_ll_sc_sync_block (void)
11411 if (!ISA_HAS_LL_SC)
11413 output_asm_insn (".set\tpush", 0);
11414 output_asm_insn (".set\tmips2", 0);
11418 /* End a block started by mips_start_ll_sc_sync_block. */
11421 mips_end_ll_sc_sync_block (void)
11423 if (!ISA_HAS_LL_SC)
11424 output_asm_insn (".set\tpop", 0);
11427 /* Output and/or return the asm template for a sync instruction. */
11430 mips_output_sync (void)
11432 mips_start_ll_sc_sync_block ();
11433 output_asm_insn ("sync", 0);
11434 mips_end_ll_sc_sync_block ();
11438 /* Return the asm template associated with sync_insn1 value TYPE.
11439 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11441 static const char *
11442 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11446 case SYNC_INSN1_MOVE:
11447 return "move\t%0,%z2";
11448 case SYNC_INSN1_LI:
11449 return "li\t%0,%2";
11450 case SYNC_INSN1_ADDU:
11451 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11452 case SYNC_INSN1_ADDIU:
11453 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11454 case SYNC_INSN1_SUBU:
11455 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11456 case SYNC_INSN1_AND:
11457 return "and\t%0,%1,%z2";
11458 case SYNC_INSN1_ANDI:
11459 return "andi\t%0,%1,%2";
11460 case SYNC_INSN1_OR:
11461 return "or\t%0,%1,%z2";
11462 case SYNC_INSN1_ORI:
11463 return "ori\t%0,%1,%2";
11464 case SYNC_INSN1_XOR:
11465 return "xor\t%0,%1,%z2";
11466 case SYNC_INSN1_XORI:
11467 return "xori\t%0,%1,%2";
11469 gcc_unreachable ();
11472 /* Return the asm template associated with sync_insn2 value TYPE. */
11474 static const char *
11475 mips_sync_insn2_template (enum attr_sync_insn2 type)
11479 case SYNC_INSN2_NOP:
11480 gcc_unreachable ();
11481 case SYNC_INSN2_AND:
11482 return "and\t%0,%1,%z2";
11483 case SYNC_INSN2_XOR:
11484 return "xor\t%0,%1,%z2";
11485 case SYNC_INSN2_NOT:
11486 return "nor\t%0,%1,%.";
11488 gcc_unreachable ();
11491 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11492 the value of the one of the sync_* attributes. Return the operand
11493 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11494 have the associated attribute. */
11497 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11500 default_value = operands[index - 1];
11501 return default_value;
11504 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11505 sequence for it. */
11508 mips_process_sync_loop (rtx insn, rtx *operands)
11510 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11511 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11512 unsigned int tmp3_insn;
11513 enum attr_sync_insn1 insn1;
11514 enum attr_sync_insn2 insn2;
11517 /* Read an operand from the sync_WHAT attribute and store it in
11518 variable WHAT. DEFAULT is the default value if no attribute
11520 #define READ_OPERAND(WHAT, DEFAULT) \
11521 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11524 /* Read the memory. */
11525 READ_OPERAND (mem, 0);
11527 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11529 /* Read the other attributes. */
11530 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11531 READ_OPERAND (oldval, at);
11532 READ_OPERAND (newval, at);
11533 READ_OPERAND (inclusive_mask, 0);
11534 READ_OPERAND (exclusive_mask, 0);
11535 READ_OPERAND (required_oldval, 0);
11536 READ_OPERAND (insn1_op2, 0);
11537 insn1 = get_attr_sync_insn1 (insn);
11538 insn2 = get_attr_sync_insn2 (insn);
11540 mips_multi_start ();
11542 /* Output the release side of the memory barrier. */
11543 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11545 if (required_oldval == 0 && TARGET_OCTEON)
11547 /* Octeon doesn't reorder reads, so a full barrier can be
11548 created by using SYNCW to order writes combined with the
11549 write from the following SC. When the SC successfully
11550 completes, we know that all preceding writes are also
11551 committed to the coherent memory system. It is possible
11552 for a single SYNCW to fail, but a pair of them will never
11553 fail, so we use two. */
11554 mips_multi_add_insn ("syncw", NULL);
11555 mips_multi_add_insn ("syncw", NULL);
11558 mips_multi_add_insn ("sync", NULL);
11561 /* Output the branch-back label. */
11562 mips_multi_add_label ("1:");
11564 /* OLDVAL = *MEM. */
11565 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11566 oldval, mem, NULL);
11568 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11569 if (required_oldval)
11571 if (inclusive_mask == 0)
11575 gcc_assert (oldval != at);
11576 mips_multi_add_insn ("and\t%0,%1,%2",
11577 at, oldval, inclusive_mask, NULL);
11580 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11583 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11584 if (exclusive_mask == 0)
11588 gcc_assert (oldval != at);
11589 mips_multi_add_insn ("and\t%0,%1,%z2",
11590 at, oldval, exclusive_mask, NULL);
11594 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11596 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11597 at least one instruction in that case. */
11598 if (insn1 == SYNC_INSN1_MOVE
11599 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11603 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11604 newval, oldval, insn1_op2, NULL);
11608 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11609 if (insn2 == SYNC_INSN2_NOP)
11613 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11614 newval, tmp2, inclusive_mask, NULL);
11617 tmp3_insn = mips_multi_last_index ();
11619 /* $AT = $TMP1 | $TMP3. */
11620 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11622 mips_multi_set_operand (tmp3_insn, 0, at);
11627 gcc_assert (tmp1 != tmp3);
11628 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11631 /* if (!commit (*MEM = $AT)) goto 1.
11633 This will sometimes be a delayed branch; see the write code below
11635 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11636 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11638 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11639 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11641 mips_multi_copy_insn (tmp3_insn);
11642 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11645 mips_multi_add_insn ("nop", NULL);
11647 /* Output the acquire side of the memory barrier. */
11648 if (TARGET_SYNC_AFTER_SC)
11649 mips_multi_add_insn ("sync", NULL);
11651 /* Output the exit label, if needed. */
11652 if (required_oldval)
11653 mips_multi_add_label ("2:");
11655 #undef READ_OPERAND
11658 /* Output and/or return the asm template for sync loop INSN, which has
11659 the operands given by OPERANDS. */
11662 mips_output_sync_loop (rtx insn, rtx *operands)
11664 mips_process_sync_loop (insn, operands);
11666 /* Use branch-likely instructions to work around the LL/SC R10000
11668 mips_branch_likely = TARGET_FIX_R10000;
11670 mips_push_asm_switch (&mips_noreorder);
11671 mips_push_asm_switch (&mips_nomacro);
11672 mips_push_asm_switch (&mips_noat);
11673 mips_start_ll_sc_sync_block ();
11675 mips_multi_write ();
11677 mips_end_ll_sc_sync_block ();
11678 mips_pop_asm_switch (&mips_noat);
11679 mips_pop_asm_switch (&mips_nomacro);
11680 mips_pop_asm_switch (&mips_noreorder);
11685 /* Return the number of individual instructions in sync loop INSN,
11686 which has the operands given by OPERANDS. */
11689 mips_sync_loop_insns (rtx insn, rtx *operands)
11691 mips_process_sync_loop (insn, operands);
11692 return mips_multi_num_insns;
11695 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11696 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11698 When working around R4000 and R4400 errata, we need to make sure that
11699 the division is not immediately followed by a shift[1][2]. We also
11700 need to stop the division from being put into a branch delay slot[3].
11701 The easiest way to avoid both problems is to add a nop after the
11702 division. When a divide-by-zero check is needed, this nop can be
11703 used to fill the branch delay slot.
11705 [1] If a double-word or a variable shift executes immediately
11706 after starting an integer division, the shift may give an
11707 incorrect result. See quotations of errata #16 and #28 from
11708 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11709 in mips.md for details.
11711 [2] A similar bug to [1] exists for all revisions of the
11712 R4000 and the R4400 when run in an MC configuration.
11713 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11715 "19. In this following sequence:
11717 ddiv (or ddivu or div or divu)
11718 dsll32 (or dsrl32, dsra32)
11720 if an MPT stall occurs, while the divide is slipping the cpu
11721 pipeline, then the following double shift would end up with an
11724 Workaround: The compiler needs to avoid generating any
11725 sequence with divide followed by extended double shift."
11727 This erratum is also present in "MIPS R4400MC Errata, Processor
11728 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11729 & 3.0" as errata #10 and #4, respectively.
11731 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11732 (also valid for MIPS R4000MC processors):
11734 "52. R4000SC: This bug does not apply for the R4000PC.
11736 There are two flavors of this bug:
11738 1) If the instruction just after divide takes an RF exception
11739 (tlb-refill, tlb-invalid) and gets an instruction cache
11740 miss (both primary and secondary) and the line which is
11741 currently in secondary cache at this index had the first
11742 data word, where the bits 5..2 are set, then R4000 would
11743 get a wrong result for the div.
11748 ------------------- # end-of page. -tlb-refill
11753 ------------------- # end-of page. -tlb-invalid
11756 2) If the divide is in the taken branch delay slot, where the
11757 target takes RF exception and gets an I-cache miss for the
11758 exception vector or where I-cache miss occurs for the
11759 target address, under the above mentioned scenarios, the
11760 div would get wrong results.
11763 j r2 # to next page mapped or unmapped
11764 div r8,r9 # this bug would be there as long
11765 # as there is an ICache miss and
11766 nop # the "data pattern" is present
11769 beq r0, r0, NextPage # to Next page
11773 This bug is present for div, divu, ddiv, and ddivu
11776 Workaround: For item 1), OS could make sure that the next page
11777 after the divide instruction is also mapped. For item 2), the
11778 compiler could make sure that the divide instruction is not in
11779 the branch delay slot."
11781 These processors have PRId values of 0x00004220 and 0x00004300 for
11782 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11785 mips_output_division (const char *division, rtx *operands)
11790 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11792 output_asm_insn (s, operands);
11795 if (TARGET_CHECK_ZERO_DIV)
11799 output_asm_insn (s, operands);
11800 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11802 else if (GENERATE_DIVIDE_TRAPS)
11804 /* Avoid long replay penalty on load miss by putting the trap before
11807 output_asm_insn ("teq\t%2,%.,7", operands);
11810 output_asm_insn (s, operands);
11811 s = "teq\t%2,%.,7";
11816 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11817 output_asm_insn (s, operands);
11818 s = "break\t7%)\n1:";
11824 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11825 instruction and if OUT_INSN assigns to the accumulator operand. */
11828 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11832 x = single_set (in_insn);
11838 if (GET_CODE (x) == PLUS
11839 && GET_CODE (XEXP (x, 0)) == MULT
11840 && reg_set_p (XEXP (x, 1), out_insn))
11843 if (GET_CODE (x) == MINUS
11844 && GET_CODE (XEXP (x, 1)) == MULT
11845 && reg_set_p (XEXP (x, 0), out_insn))
11851 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11852 data rather than the address. We need this because the cprestore
11853 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11854 which causes the default routine to abort. We just return false
11858 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11860 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11863 return !store_data_bypass_p (out_insn, in_insn);
11867 /* Variables and flags used in scheduler hooks when tuning for
11871 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11874 /* If true, then next ALU1/2 instruction will go to ALU1. */
11877 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11880 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11881 int alu1_core_unit_code;
11882 int alu2_core_unit_code;
11883 int falu1_core_unit_code;
11884 int falu2_core_unit_code;
11886 /* True if current cycle has a multi instruction.
11887 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11888 bool cycle_has_multi_p;
11890 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11891 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11893 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11894 instruction to go ALU1. */
11895 rtx alu1_turn_enabled_insn;
11896 rtx alu2_turn_enabled_insn;
11897 rtx falu1_turn_enabled_insn;
11898 rtx falu2_turn_enabled_insn;
11901 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11902 dependencies have no cost, except on the 20Kc where output-dependence
11903 is treated like input-dependence. */
11906 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
11907 rtx dep ATTRIBUTE_UNUSED, int cost)
11909 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
11912 if (REG_NOTE_KIND (link) != 0)
11917 /* Return the number of instructions that can be issued per cycle. */
11920 mips_issue_rate (void)
11924 case PROCESSOR_74KC:
11925 case PROCESSOR_74KF2_1:
11926 case PROCESSOR_74KF1_1:
11927 case PROCESSOR_74KF3_2:
11928 /* The 74k is not strictly quad-issue cpu, but can be seen as one
11929 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
11930 but in reality only a maximum of 3 insns can be issued as
11931 floating-point loads and stores also require a slot in the
11933 case PROCESSOR_R10000:
11934 /* All R10K Processors are quad-issue (being the first MIPS
11935 processors to support this feature). */
11938 case PROCESSOR_20KC:
11939 case PROCESSOR_R4130:
11940 case PROCESSOR_R5400:
11941 case PROCESSOR_R5500:
11942 case PROCESSOR_R7000:
11943 case PROCESSOR_R9000:
11944 case PROCESSOR_OCTEON:
11947 case PROCESSOR_SB1:
11948 case PROCESSOR_SB1A:
11949 /* This is actually 4, but we get better performance if we claim 3.
11950 This is partly because of unwanted speculative code motion with the
11951 larger number, and partly because in most common cases we can't
11952 reach the theoretical max of 4. */
11955 case PROCESSOR_LOONGSON_2E:
11956 case PROCESSOR_LOONGSON_2F:
11964 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
11967 mips_ls2_init_dfa_post_cycle_insn (void)
11970 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
11971 mips_ls2.alu1_turn_enabled_insn = get_insns ();
11975 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
11976 mips_ls2.alu2_turn_enabled_insn = get_insns ();
11980 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
11981 mips_ls2.falu1_turn_enabled_insn = get_insns ();
11985 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
11986 mips_ls2.falu2_turn_enabled_insn = get_insns ();
11989 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
11990 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
11991 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
11992 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
11995 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
11996 Init data used in mips_dfa_post_advance_cycle. */
11999 mips_init_dfa_post_cycle_insn (void)
12001 if (TUNE_LOONGSON_2EF)
12002 mips_ls2_init_dfa_post_cycle_insn ();
12005 /* Initialize STATE when scheduling for Loongson 2E/2F.
12006 Support round-robin dispatch scheme by enabling only one of
12007 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12011 mips_ls2_dfa_post_advance_cycle (state_t state)
12013 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12015 /* Though there are no non-pipelined ALU1 insns,
12016 we can get an instruction of type 'multi' before reload. */
12017 gcc_assert (mips_ls2.cycle_has_multi_p);
12018 mips_ls2.alu1_turn_p = false;
12021 mips_ls2.cycle_has_multi_p = false;
12023 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12024 /* We have a non-pipelined alu instruction in the core,
12025 adjust round-robin counter. */
12026 mips_ls2.alu1_turn_p = true;
12028 if (mips_ls2.alu1_turn_p)
12030 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12031 gcc_unreachable ();
12035 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12036 gcc_unreachable ();
12039 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12041 /* There are no non-pipelined FALU1 insns. */
12042 gcc_unreachable ();
12043 mips_ls2.falu1_turn_p = false;
12046 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12047 /* We have a non-pipelined falu instruction in the core,
12048 adjust round-robin counter. */
12049 mips_ls2.falu1_turn_p = true;
12051 if (mips_ls2.falu1_turn_p)
12053 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12054 gcc_unreachable ();
12058 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12059 gcc_unreachable ();
12063 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12064 This hook is being called at the start of each cycle. */
12067 mips_dfa_post_advance_cycle (void)
12069 if (TUNE_LOONGSON_2EF)
12070 mips_ls2_dfa_post_advance_cycle (curr_state);
12073 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12074 be as wide as the scheduling freedom in the DFA. */
12077 mips_multipass_dfa_lookahead (void)
12079 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12083 if (TUNE_LOONGSON_2EF)
12092 /* Remove the instruction at index LOWER from ready queue READY and
12093 reinsert it in front of the instruction at index HIGHER. LOWER must
12097 mips_promote_ready (rtx *ready, int lower, int higher)
12102 new_head = ready[lower];
12103 for (i = lower; i < higher; i++)
12104 ready[i] = ready[i + 1];
12105 ready[i] = new_head;
12108 /* If the priority of the instruction at POS2 in the ready queue READY
12109 is within LIMIT units of that of the instruction at POS1, swap the
12110 instructions if POS2 is not already less than POS1. */
12113 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12116 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12120 temp = ready[pos1];
12121 ready[pos1] = ready[pos2];
12122 ready[pos2] = temp;
12126 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12127 that may clobber hi or lo. */
12128 static rtx mips_macc_chains_last_hilo;
12130 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12131 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12134 mips_macc_chains_record (rtx insn)
12136 if (get_attr_may_clobber_hilo (insn))
12137 mips_macc_chains_last_hilo = insn;
12140 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12141 has NREADY elements, looking for a multiply-add or multiply-subtract
12142 instruction that is cumulative with mips_macc_chains_last_hilo.
12143 If there is one, promote it ahead of anything else that might
12144 clobber hi or lo. */
12147 mips_macc_chains_reorder (rtx *ready, int nready)
12151 if (mips_macc_chains_last_hilo != 0)
12152 for (i = nready - 1; i >= 0; i--)
12153 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12155 for (j = nready - 1; j > i; j--)
12156 if (recog_memoized (ready[j]) >= 0
12157 && get_attr_may_clobber_hilo (ready[j]))
12159 mips_promote_ready (ready, i, j);
12166 /* The last instruction to be scheduled. */
12167 static rtx vr4130_last_insn;
12169 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12170 points to an rtx that is initially an instruction. Nullify the rtx
12171 if the instruction uses the value of register X. */
12174 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12179 insn_ptr = (rtx *) data;
12182 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12186 /* Return true if there is true register dependence between vr4130_last_insn
12190 vr4130_true_reg_dependence_p (rtx insn)
12192 note_stores (PATTERN (vr4130_last_insn),
12193 vr4130_true_reg_dependence_p_1, &insn);
12197 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12198 the ready queue and that INSN2 is the instruction after it, return
12199 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12200 in which INSN1 and INSN2 can probably issue in parallel, but for
12201 which (INSN2, INSN1) should be less sensitive to instruction
12202 alignment than (INSN1, INSN2). See 4130.md for more details. */
12205 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12207 sd_iterator_def sd_it;
12210 /* Check for the following case:
12212 1) there is some other instruction X with an anti dependence on INSN1;
12213 2) X has a higher priority than INSN2; and
12214 3) X is an arithmetic instruction (and thus has no unit restrictions).
12216 If INSN1 is the last instruction blocking X, it would better to
12217 choose (INSN1, X) over (INSN2, INSN1). */
12218 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12219 if (DEP_TYPE (dep) == REG_DEP_ANTI
12220 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12221 && recog_memoized (DEP_CON (dep)) >= 0
12222 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12225 if (vr4130_last_insn != 0
12226 && recog_memoized (insn1) >= 0
12227 && recog_memoized (insn2) >= 0)
12229 /* See whether INSN1 and INSN2 use different execution units,
12230 or if they are both ALU-type instructions. If so, they can
12231 probably execute in parallel. */
12232 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12233 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12234 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12236 /* If only one of the instructions has a dependence on
12237 vr4130_last_insn, prefer to schedule the other one first. */
12238 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12239 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12240 if (dep1_p != dep2_p)
12243 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12244 is not an ALU-type instruction and if INSN1 uses the same
12245 execution unit. (Note that if this condition holds, we already
12246 know that INSN2 uses a different execution unit.) */
12247 if (class1 != VR4130_CLASS_ALU
12248 && recog_memoized (vr4130_last_insn) >= 0
12249 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12256 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12257 queue with at least two instructions. Swap the first two if
12258 vr4130_swap_insns_p says that it could be worthwhile. */
12261 vr4130_reorder (rtx *ready, int nready)
12263 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12264 mips_promote_ready (ready, nready - 2, nready - 1);
12267 /* Record whether last 74k AGEN instruction was a load or store. */
12268 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12270 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12271 resets to TYPE_UNKNOWN state. */
12274 mips_74k_agen_init (rtx insn)
12276 if (!insn || CALL_P (insn) || JUMP_P (insn))
12277 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12280 enum attr_type type = get_attr_type (insn);
12281 if (type == TYPE_LOAD || type == TYPE_STORE)
12282 mips_last_74k_agen_insn = type;
12286 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12287 loads to be grouped together, and multiple stores to be grouped
12288 together. Swap things around in the ready queue to make this happen. */
12291 mips_74k_agen_reorder (rtx *ready, int nready)
12294 int store_pos, load_pos;
12299 for (i = nready - 1; i >= 0; i--)
12301 rtx insn = ready[i];
12302 if (USEFUL_INSN_P (insn))
12303 switch (get_attr_type (insn))
12306 if (store_pos == -1)
12311 if (load_pos == -1)
12320 if (load_pos == -1 || store_pos == -1)
12323 switch (mips_last_74k_agen_insn)
12326 /* Prefer to schedule loads since they have a higher latency. */
12328 /* Swap loads to the front of the queue. */
12329 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12332 /* Swap stores to the front of the queue. */
12333 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12340 /* Implement TARGET_SCHED_INIT. */
12343 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12344 int max_ready ATTRIBUTE_UNUSED)
12346 mips_macc_chains_last_hilo = 0;
12347 vr4130_last_insn = 0;
12348 mips_74k_agen_init (NULL_RTX);
12350 /* When scheduling for Loongson2, branch instructions go to ALU1,
12351 therefore basic block is most likely to start with round-robin counter
12352 pointed to ALU2. */
12353 mips_ls2.alu1_turn_p = false;
12354 mips_ls2.falu1_turn_p = true;
12357 /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12360 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12361 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12363 if (!reload_completed
12364 && TUNE_MACC_CHAINS
12366 mips_macc_chains_reorder (ready, *nreadyp);
12368 if (reload_completed
12370 && !TARGET_VR4130_ALIGN
12372 vr4130_reorder (ready, *nreadyp);
12375 mips_74k_agen_reorder (ready, *nreadyp);
12377 return mips_issue_rate ();
12380 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12383 mips_ls2_variable_issue (rtx insn)
12385 if (mips_ls2.alu1_turn_p)
12387 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12388 mips_ls2.alu1_turn_p = false;
12392 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12393 mips_ls2.alu1_turn_p = true;
12396 if (mips_ls2.falu1_turn_p)
12398 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12399 mips_ls2.falu1_turn_p = false;
12403 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12404 mips_ls2.falu1_turn_p = true;
12407 if (recog_memoized (insn) >= 0)
12408 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12411 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12414 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12415 rtx insn, int more)
12417 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12418 if (USEFUL_INSN_P (insn))
12420 if (get_attr_type (insn) != TYPE_GHOST)
12422 if (!reload_completed && TUNE_MACC_CHAINS)
12423 mips_macc_chains_record (insn);
12424 vr4130_last_insn = insn;
12426 mips_74k_agen_init (insn);
12427 else if (TUNE_LOONGSON_2EF)
12428 mips_ls2_variable_issue (insn);
12431 /* Instructions of type 'multi' should all be split before
12432 the second scheduling pass. */
12433 gcc_assert (!reload_completed
12434 || recog_memoized (insn) < 0
12435 || get_attr_type (insn) != TYPE_MULTI);
12440 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12441 return the first operand of the associated PREF or PREFX insn. */
12444 mips_prefetch_cookie (rtx write, rtx locality)
12446 /* store_streamed / load_streamed. */
12447 if (INTVAL (locality) <= 0)
12448 return GEN_INT (INTVAL (write) + 4);
12450 /* store / load. */
12451 if (INTVAL (locality) <= 2)
12454 /* store_retained / load_retained. */
12455 return GEN_INT (INTVAL (write) + 6);
12458 /* Flags that indicate when a built-in function is available.
12460 BUILTIN_AVAIL_NON_MIPS16
12461 The function is available on the current target, but only
12462 in non-MIPS16 mode. */
12463 #define BUILTIN_AVAIL_NON_MIPS16 1
12465 /* Declare an availability predicate for built-in functions that
12466 require non-MIPS16 mode and also require COND to be true.
12467 NAME is the main part of the predicate's name. */
12468 #define AVAIL_NON_MIPS16(NAME, COND) \
12469 static unsigned int \
12470 mips_builtin_avail_##NAME (void) \
12472 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12475 /* This structure describes a single built-in function. */
12476 struct mips_builtin_description {
12477 /* The code of the main .md file instruction. See mips_builtin_type
12478 for more information. */
12479 enum insn_code icode;
12481 /* The floating-point comparison code to use with ICODE, if any. */
12482 enum mips_fp_condition cond;
12484 /* The name of the built-in function. */
12487 /* Specifies how the function should be expanded. */
12488 enum mips_builtin_type builtin_type;
12490 /* The function's prototype. */
12491 enum mips_function_type function_type;
12493 /* Whether the function is available. */
12494 unsigned int (*avail) (void);
12497 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12498 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12499 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12500 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12501 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12502 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12503 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12504 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12505 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12507 /* Construct a mips_builtin_description from the given arguments.
12509 INSN is the name of the associated instruction pattern, without the
12510 leading CODE_FOR_mips_.
12512 CODE is the floating-point condition code associated with the
12513 function. It can be 'f' if the field is not applicable.
12515 NAME is the name of the function itself, without the leading
12518 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12520 AVAIL is the name of the availability predicate, without the leading
12521 mips_builtin_avail_. */
12522 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12523 FUNCTION_TYPE, AVAIL) \
12524 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12525 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12526 mips_builtin_avail_ ## AVAIL }
12528 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12529 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12530 are as for MIPS_BUILTIN. */
12531 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12532 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12534 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12535 are subject to mips_builtin_avail_<AVAIL>. */
12536 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12537 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12538 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12539 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12540 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12542 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12543 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12544 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12545 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12546 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12547 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12549 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12550 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12552 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12553 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12555 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12556 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12559 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12560 are subject to mips_builtin_avail_mips3d. */
12561 #define CMP_4S_BUILTINS(INSN, COND) \
12562 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12563 MIPS_BUILTIN_CMP_ANY, \
12564 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12565 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12566 MIPS_BUILTIN_CMP_ALL, \
12567 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12569 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12570 instruction requires mips_builtin_avail_<AVAIL>. */
12571 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12572 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12573 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12575 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12576 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12579 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12580 #define CMP_BUILTINS(COND) \
12581 MOVTF_BUILTINS (c, COND, paired_single), \
12582 MOVTF_BUILTINS (cabs, COND, mips3d), \
12583 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12584 CMP_PS_BUILTINS (c, COND, paired_single), \
12585 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12586 CMP_4S_BUILTINS (c, COND), \
12587 CMP_4S_BUILTINS (cabs, COND)
12589 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12590 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12591 and AVAIL are as for MIPS_BUILTIN. */
12592 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12593 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12594 FUNCTION_TYPE, AVAIL)
12596 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12597 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12598 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12599 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12600 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12602 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12603 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12604 builtin_description field. */
12605 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12606 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12607 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12608 FUNCTION_TYPE, mips_builtin_avail_loongson }
12610 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12611 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12612 builtin_description field. */
12613 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12614 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12616 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12617 We use functions of this form when the same insn can be usefully applied
12618 to more than one datatype. */
12619 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12620 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12622 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12623 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12624 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12625 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12626 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12627 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12629 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12630 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12631 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12632 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12633 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12634 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12635 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12636 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12637 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12638 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12639 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12640 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12641 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12642 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12643 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12644 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12645 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12646 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12647 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12648 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12649 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12650 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12651 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12652 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12653 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12654 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12655 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12656 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12657 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12659 static const struct mips_builtin_description mips_builtins[] = {
12660 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12661 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12662 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12663 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12664 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12665 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12666 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12667 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12669 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12670 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12671 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12672 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12673 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12675 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12676 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12677 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12678 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12679 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12680 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12682 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12683 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12684 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12685 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12686 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12687 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12689 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12691 /* Built-in functions for the SB-1 processor. */
12692 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12694 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12695 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12696 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12697 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12698 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12699 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12700 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12701 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12702 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12703 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12704 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12705 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12706 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12707 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12708 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12709 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12710 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12711 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12712 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12713 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12714 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12715 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12716 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12717 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12718 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12719 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12720 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12721 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12722 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12723 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12724 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12725 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12726 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12727 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12728 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12729 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12730 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12731 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12732 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12733 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12734 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12735 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12736 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12737 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12738 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12739 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12740 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12741 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12742 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12743 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12744 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12745 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12746 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12747 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12748 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12749 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12750 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12751 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12752 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12753 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12754 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12755 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12756 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12757 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12758 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12759 BPOSGE_BUILTIN (32, dsp),
12761 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12762 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12763 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12764 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12765 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12766 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12767 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12768 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12769 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12770 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12771 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12772 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12773 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12774 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12775 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12776 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12777 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12778 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12779 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12780 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12781 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12782 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12783 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12784 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12785 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12786 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12787 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12788 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12789 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12790 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12791 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12792 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12793 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12794 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12795 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12797 /* Built-in functions for the DSP ASE (32-bit only). */
12798 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12799 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12800 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12801 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12802 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12803 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12804 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12805 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12806 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12807 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12808 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12809 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12810 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12811 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12812 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12813 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12814 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12815 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12816 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12817 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12818 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12820 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12821 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12822 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12823 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12824 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12825 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32),
12826 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32),
12827 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12828 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32),
12829 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32),
12830 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12831 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12832 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12833 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12834 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12835 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12837 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12838 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12839 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12840 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12841 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12842 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12843 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12844 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12845 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12846 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12847 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12848 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12849 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12850 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12851 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12852 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12853 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12854 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12855 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12856 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12857 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12858 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12859 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12860 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12861 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12862 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12863 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12864 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12865 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12866 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12867 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12868 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12869 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12870 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12871 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12872 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12873 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12874 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12875 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
12876 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
12877 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12878 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12879 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12880 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12881 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12882 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12883 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12884 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12885 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
12886 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12887 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12888 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12889 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12890 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
12891 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
12892 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12893 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12894 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12895 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
12896 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12897 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
12898 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
12899 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
12900 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
12901 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12902 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12903 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12904 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12905 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12906 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12907 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12908 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12909 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
12910 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
12911 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
12912 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
12913 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12914 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12915 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12916 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12917 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12918 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12919 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
12920 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
12921 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12922 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12923 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12924 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12925 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12926 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12927 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12928 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12929 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12930 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12931 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12932 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12933 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12934 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12935 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12936 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12938 /* Sundry other built-in functions. */
12939 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
12942 /* MODE is a vector mode whose elements have type TYPE. Return the type
12943 of the vector itself. */
12946 mips_builtin_vector_type (tree type, enum machine_mode mode)
12948 static tree types[2 * (int) MAX_MACHINE_MODE];
12951 mode_index = (int) mode;
12953 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
12954 mode_index += MAX_MACHINE_MODE;
12956 if (types[mode_index] == NULL_TREE)
12957 types[mode_index] = build_vector_type_for_mode (type, mode);
12958 return types[mode_index];
12961 /* Return a type for 'const volatile void *'. */
12964 mips_build_cvpointer_type (void)
12968 if (cache == NULL_TREE)
12969 cache = build_pointer_type (build_qualified_type
12971 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
12975 /* Source-level argument types. */
12976 #define MIPS_ATYPE_VOID void_type_node
12977 #define MIPS_ATYPE_INT integer_type_node
12978 #define MIPS_ATYPE_POINTER ptr_type_node
12979 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
12981 /* Standard mode-based argument types. */
12982 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
12983 #define MIPS_ATYPE_SI intSI_type_node
12984 #define MIPS_ATYPE_USI unsigned_intSI_type_node
12985 #define MIPS_ATYPE_DI intDI_type_node
12986 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
12987 #define MIPS_ATYPE_SF float_type_node
12988 #define MIPS_ATYPE_DF double_type_node
12990 /* Vector argument types. */
12991 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
12992 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
12993 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
12994 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
12995 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
12996 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
12997 #define MIPS_ATYPE_UV2SI \
12998 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
12999 #define MIPS_ATYPE_UV4HI \
13000 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13001 #define MIPS_ATYPE_UV8QI \
13002 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13004 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13005 their associated MIPS_ATYPEs. */
13006 #define MIPS_FTYPE_ATYPES1(A, B) \
13007 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13009 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13010 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13012 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13013 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13015 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13016 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13019 /* Return the function type associated with function prototype TYPE. */
13022 mips_build_function_type (enum mips_function_type type)
13024 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13026 if (types[(int) type] == NULL_TREE)
13029 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13030 case MIPS_FTYPE_NAME##NUM ARGS: \
13031 types[(int) type] \
13032 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13035 #include "config/mips/mips-ftypes.def"
13036 #undef DEF_MIPS_FTYPE
13038 gcc_unreachable ();
13041 return types[(int) type];
13044 /* Implement TARGET_INIT_BUILTINS. */
13047 mips_init_builtins (void)
13049 const struct mips_builtin_description *d;
13052 /* Iterate through all of the bdesc arrays, initializing all of the
13053 builtin functions. */
13054 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13056 d = &mips_builtins[i];
13058 add_builtin_function (d->name,
13059 mips_build_function_type (d->function_type),
13060 i, BUILT_IN_MD, NULL, NULL);
13064 /* Take argument ARGNO from EXP's argument list and convert it into a
13065 form suitable for input operand OPNO of instruction ICODE. Return the
13069 mips_prepare_builtin_arg (enum insn_code icode,
13070 unsigned int opno, tree exp, unsigned int argno)
13074 enum machine_mode mode;
13076 arg = CALL_EXPR_ARG (exp, argno);
13077 value = expand_normal (arg);
13078 mode = insn_data[icode].operand[opno].mode;
13079 if (!insn_data[icode].operand[opno].predicate (value, mode))
13081 /* We need to get the mode from ARG for two reasons:
13083 - to cope with address operands, where MODE is the mode of the
13084 memory, rather than of VALUE itself.
13086 - to cope with special predicates like pmode_register_operand,
13087 where MODE is VOIDmode. */
13088 value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
13090 /* Check the predicate again. */
13091 if (!insn_data[icode].operand[opno].predicate (value, mode))
13093 error ("invalid argument to built-in function");
13101 /* Return an rtx suitable for output operand OP of instruction ICODE.
13102 If TARGET is non-null, try to use it where possible. */
13105 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
13107 enum machine_mode mode;
13109 mode = insn_data[icode].operand[op].mode;
13110 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
13111 target = gen_reg_rtx (mode);
13116 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13117 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13118 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13119 suggests a good place to put the result. */
13122 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13125 rtx ops[MAX_RECOG_OPERANDS];
13128 /* Map any target to operand 0. */
13132 target = mips_prepare_builtin_target (icode, opno, target);
13133 ops[opno] = target;
13137 /* Map the arguments to the other operands. The n_operands value
13138 for an expander includes match_dups and match_scratches as well as
13139 match_operands, so n_operands is only an upper bound on the number
13140 of arguments to the expander function. */
13141 gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
13142 for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
13143 ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
13148 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
13152 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
13156 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
13160 gcc_unreachable ();
13165 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13166 function; TYPE says which. EXP is the CALL_EXPR that calls the
13167 function, ICODE is the instruction that should be used to compare
13168 the first two arguments, and COND is the condition it should test.
13169 TARGET, if nonnull, suggests a good place to put the result. */
13172 mips_expand_builtin_movtf (enum mips_builtin_type type,
13173 enum insn_code icode, enum mips_fp_condition cond,
13174 rtx target, tree exp)
13176 rtx cmp_result, op0, op1;
13178 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13179 op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
13180 op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
13181 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
13183 icode = CODE_FOR_mips_cond_move_tf_ps;
13184 target = mips_prepare_builtin_target (icode, 0, target);
13185 if (type == MIPS_BUILTIN_MOVT)
13187 op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
13188 op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
13192 op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
13193 op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
13195 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
13199 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13200 into TARGET otherwise. Return TARGET. */
13203 mips_builtin_branch_and_move (rtx condition, rtx target,
13204 rtx value_if_true, rtx value_if_false)
13206 rtx true_label, done_label;
13208 true_label = gen_label_rtx ();
13209 done_label = gen_label_rtx ();
13211 /* First assume that CONDITION is false. */
13212 mips_emit_move (target, value_if_false);
13214 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13215 emit_jump_insn (gen_condjump (condition, true_label));
13216 emit_jump_insn (gen_jump (done_label));
13219 /* Fix TARGET if CONDITION is true. */
13220 emit_label (true_label);
13221 mips_emit_move (target, value_if_true);
13223 emit_label (done_label);
13227 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13228 the CALL_EXPR that calls the function, ICODE is the code of the
13229 comparison instruction, and COND is the condition it should test.
13230 TARGET, if nonnull, suggests a good place to put the boolean result. */
13233 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13234 enum insn_code icode, enum mips_fp_condition cond,
13235 rtx target, tree exp)
13237 rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
13240 if (target == 0 || GET_MODE (target) != SImode)
13241 target = gen_reg_rtx (SImode);
13243 /* The instruction should have a target operand, an operand for each
13244 argument, and an operand for COND. */
13245 gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
13247 /* Prepare the operands to the comparison. */
13248 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
13249 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13250 args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
13252 switch (insn_data[icode].n_operands)
13255 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13260 emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
13261 args[2], args[3], GEN_INT (cond)));
13265 gcc_unreachable ();
13268 /* If the comparison sets more than one register, we define the result
13269 to be 0 if all registers are false and -1 if all registers are true.
13270 The value of the complete result is indeterminate otherwise. */
13271 switch (builtin_type)
13273 case MIPS_BUILTIN_CMP_ALL:
13274 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13275 return mips_builtin_branch_and_move (condition, target,
13276 const0_rtx, const1_rtx);
13278 case MIPS_BUILTIN_CMP_UPPER:
13279 case MIPS_BUILTIN_CMP_LOWER:
13280 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13281 condition = gen_single_cc (cmp_result, offset);
13282 return mips_builtin_branch_and_move (condition, target,
13283 const1_rtx, const0_rtx);
13286 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13287 return mips_builtin_branch_and_move (condition, target,
13288 const1_rtx, const0_rtx);
13292 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13293 if nonnull, suggests a good place to put the boolean result. */
13296 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13298 rtx condition, cmp_result;
13301 if (target == 0 || GET_MODE (target) != SImode)
13302 target = gen_reg_rtx (SImode);
13304 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13306 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13311 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13312 return mips_builtin_branch_and_move (condition, target,
13313 const1_rtx, const0_rtx);
13316 /* Implement TARGET_EXPAND_BUILTIN. */
13319 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13320 enum machine_mode mode, int ignore)
13323 unsigned int fcode, avail;
13324 const struct mips_builtin_description *d;
13326 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13327 fcode = DECL_FUNCTION_CODE (fndecl);
13328 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13329 d = &mips_builtins[fcode];
13330 avail = d->avail ();
13331 gcc_assert (avail != 0);
13334 error ("built-in function %qE not supported for MIPS16",
13335 DECL_NAME (fndecl));
13336 return ignore ? const0_rtx : CONST0_RTX (mode);
13338 switch (d->builtin_type)
13340 case MIPS_BUILTIN_DIRECT:
13341 return mips_expand_builtin_direct (d->icode, target, exp, true);
13343 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13344 return mips_expand_builtin_direct (d->icode, target, exp, false);
13346 case MIPS_BUILTIN_MOVT:
13347 case MIPS_BUILTIN_MOVF:
13348 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13349 d->cond, target, exp);
13351 case MIPS_BUILTIN_CMP_ANY:
13352 case MIPS_BUILTIN_CMP_ALL:
13353 case MIPS_BUILTIN_CMP_UPPER:
13354 case MIPS_BUILTIN_CMP_LOWER:
13355 case MIPS_BUILTIN_CMP_SINGLE:
13356 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13357 d->cond, target, exp);
13359 case MIPS_BUILTIN_BPOSGE32:
13360 return mips_expand_builtin_bposge (d->builtin_type, target);
13362 gcc_unreachable ();
13365 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13366 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13367 struct mips16_constant {
13368 struct mips16_constant *next;
13371 enum machine_mode mode;
13374 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13375 first constant, HIGHEST_ADDRESS is the highest address that the first
13376 byte of the pool can have, and INSN_ADDRESS is the current instruction
13378 struct mips16_constant_pool {
13379 struct mips16_constant *first;
13380 int highest_address;
13384 /* Add constant VALUE to POOL and return its label. MODE is the
13385 value's mode (used for CONST_INTs, etc.). */
13388 mips16_add_constant (struct mips16_constant_pool *pool,
13389 rtx value, enum machine_mode mode)
13391 struct mips16_constant **p, *c;
13392 bool first_of_size_p;
13394 /* See whether the constant is already in the pool. If so, return the
13395 existing label, otherwise leave P pointing to the place where the
13396 constant should be added.
13398 Keep the pool sorted in increasing order of mode size so that we can
13399 reduce the number of alignments needed. */
13400 first_of_size_p = true;
13401 for (p = &pool->first; *p != 0; p = &(*p)->next)
13403 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13404 return (*p)->label;
13405 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13407 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13408 first_of_size_p = false;
13411 /* In the worst case, the constant needed by the earliest instruction
13412 will end up at the end of the pool. The entire pool must then be
13413 accessible from that instruction.
13415 When adding the first constant, set the pool's highest address to
13416 the address of the first out-of-range byte. Adjust this address
13417 downwards each time a new constant is added. */
13418 if (pool->first == 0)
13419 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13420 of the instruction with the lowest two bits clear. The base PC
13421 value for LDPC has the lowest three bits clear. Assume the worst
13422 case here; namely that the PC-relative instruction occupies the
13423 last 2 bytes in an aligned word. */
13424 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13425 pool->highest_address -= GET_MODE_SIZE (mode);
13426 if (first_of_size_p)
13427 /* Take into account the worst possible padding due to alignment. */
13428 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13430 /* Create a new entry. */
13431 c = XNEW (struct mips16_constant);
13434 c->label = gen_label_rtx ();
13441 /* Output constant VALUE after instruction INSN and return the last
13442 instruction emitted. MODE is the mode of the constant. */
13445 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13447 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13449 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13450 return emit_insn_after (gen_consttable_int (value, size), insn);
13453 if (SCALAR_FLOAT_MODE_P (mode))
13454 return emit_insn_after (gen_consttable_float (value), insn);
13456 if (VECTOR_MODE_P (mode))
13460 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13461 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13462 CONST_VECTOR_ELT (value, i), insn);
13466 gcc_unreachable ();
13469 /* Dump out the constants in CONSTANTS after INSN. */
13472 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13474 struct mips16_constant *c, *next;
13478 for (c = constants; c != NULL; c = next)
13480 /* If necessary, increase the alignment of PC. */
13481 if (align < GET_MODE_SIZE (c->mode))
13483 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13484 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13486 align = GET_MODE_SIZE (c->mode);
13488 insn = emit_label_after (c->label, insn);
13489 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13495 emit_barrier_after (insn);
13498 /* Return the length of instruction INSN. */
13501 mips16_insn_length (rtx insn)
13505 rtx body = PATTERN (insn);
13506 if (GET_CODE (body) == ADDR_VEC)
13507 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13508 if (GET_CODE (body) == ADDR_DIFF_VEC)
13509 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13511 return get_attr_length (insn);
13514 /* If *X is a symbolic constant that refers to the constant pool, add
13515 the constant to POOL and rewrite *X to use the constant's label. */
13518 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13520 rtx base, offset, label;
13522 split_const (*x, &base, &offset);
13523 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13525 label = mips16_add_constant (pool, get_pool_constant (base),
13526 get_pool_mode (base));
13527 base = gen_rtx_LABEL_REF (Pmode, label);
13528 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13532 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13533 INSN is the instruction we're rewriting and POOL points to the current
13535 struct mips16_rewrite_pool_refs_info {
13537 struct mips16_constant_pool *pool;
13540 /* Rewrite *X so that constant pool references refer to the constant's
13541 label instead. DATA points to a mips16_rewrite_pool_refs_info
13545 mips16_rewrite_pool_refs (rtx *x, void *data)
13547 struct mips16_rewrite_pool_refs_info *info =
13548 (struct mips16_rewrite_pool_refs_info *) data;
13550 if (force_to_mem_operand (*x, Pmode))
13552 rtx mem = force_const_mem (GET_MODE (*x), *x);
13553 validate_change (info->insn, x, mem, false);
13558 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13562 if (TARGET_MIPS16_TEXT_LOADS)
13563 mips16_rewrite_pool_constant (info->pool, x);
13565 return GET_CODE (*x) == CONST ? -1 : 0;
13568 /* Return whether CFG is used in mips_reorg. */
13571 mips_cfg_in_reorg (void)
13573 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13574 || TARGET_RELAX_PIC_CALLS);
13577 /* Build MIPS16 constant pools. */
13580 mips16_lay_out_constants (void)
13582 struct mips16_constant_pool pool;
13583 struct mips16_rewrite_pool_refs_info info;
13586 if (!TARGET_MIPS16_PCREL_LOADS)
13589 if (mips_cfg_in_reorg ())
13590 split_all_insns ();
13592 split_all_insns_noflow ();
13594 memset (&pool, 0, sizeof (pool));
13595 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13597 /* Rewrite constant pool references in INSN. */
13598 if (USEFUL_INSN_P (insn))
13602 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13605 pool.insn_address += mips16_insn_length (insn);
13607 if (pool.first != NULL)
13609 /* If there are no natural barriers between the first user of
13610 the pool and the highest acceptable address, we'll need to
13611 create a new instruction to jump around the constant pool.
13612 In the worst case, this instruction will be 4 bytes long.
13614 If it's too late to do this transformation after INSN,
13615 do it immediately before INSN. */
13616 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13620 label = gen_label_rtx ();
13622 jump = emit_jump_insn_before (gen_jump (label), insn);
13623 JUMP_LABEL (jump) = label;
13624 LABEL_NUSES (label) = 1;
13625 barrier = emit_barrier_after (jump);
13627 emit_label_after (label, barrier);
13628 pool.insn_address += 4;
13631 /* See whether the constant pool is now out of range of the first
13632 user. If so, output the constants after the previous barrier.
13633 Note that any instructions between BARRIER and INSN (inclusive)
13634 will use negative offsets to refer to the pool. */
13635 if (pool.insn_address > pool.highest_address)
13637 mips16_emit_constants (pool.first, barrier);
13641 else if (BARRIER_P (insn))
13645 mips16_emit_constants (pool.first, get_last_insn ());
13648 /* Return true if it is worth r10k_simplify_address's while replacing
13649 an address with X. We are looking for constants, and for addresses
13650 at a known offset from the incoming stack pointer. */
13653 r10k_simplified_address_p (rtx x)
13655 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13657 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13660 /* X is an expression that appears in INSN. Try to use the UD chains
13661 to simplify it, returning the simplified form on success and the
13662 original form otherwise. Replace the incoming value of $sp with
13663 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13666 r10k_simplify_address (rtx x, rtx insn)
13668 rtx newx, op0, op1, set, def_insn, note;
13670 struct df_link *defs;
13675 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13676 if (op0 != XEXP (x, 0))
13677 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13678 op0, GET_MODE (XEXP (x, 0)));
13680 else if (BINARY_P (x))
13682 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13683 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13684 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13685 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13687 else if (GET_CODE (x) == LO_SUM)
13689 /* LO_SUMs can be offset from HIGHs, if we know they won't
13690 overflow. See mips_classify_address for the rationale behind
13692 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13693 if (GET_CODE (op0) == HIGH)
13694 newx = XEXP (x, 1);
13696 else if (REG_P (x))
13698 /* Uses are recorded by regno_reg_rtx, not X itself. */
13699 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13701 defs = DF_REF_CHAIN (use);
13703 /* Require a single definition. */
13704 if (defs && defs->next == NULL)
13707 if (DF_REF_IS_ARTIFICIAL (def))
13709 /* Replace the incoming value of $sp with
13710 virtual_incoming_args_rtx. */
13711 if (x == stack_pointer_rtx
13712 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13713 newx = virtual_incoming_args_rtx;
13715 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13718 /* Make sure that DEF_INSN is a single set of REG. */
13719 def_insn = DF_REF_INSN (def);
13720 if (NONJUMP_INSN_P (def_insn))
13722 set = single_set (def_insn);
13723 if (set && rtx_equal_p (SET_DEST (set), x))
13725 /* Prefer to use notes, since the def-use chains
13726 are often shorter. */
13727 note = find_reg_equal_equiv_note (def_insn);
13729 newx = XEXP (note, 0);
13731 newx = SET_SRC (set);
13732 newx = r10k_simplify_address (newx, def_insn);
13738 if (newx && r10k_simplified_address_p (newx))
13743 /* Return true if ADDRESS is known to be an uncached address
13744 on R10K systems. */
13747 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13749 unsigned HOST_WIDE_INT upper;
13751 /* Check for KSEG1. */
13752 if (address + 0x60000000 < 0x20000000)
13755 /* Check for uncached XKPHYS addresses. */
13756 if (Pmode == DImode)
13758 upper = (address >> 40) & 0xf9ffff;
13759 if (upper == 0x900000 || upper == 0xb80000)
13765 /* Return true if we can prove that an access to address X in instruction
13766 INSN would be safe from R10K speculation. This X is a general
13767 expression; it might not be a legitimate address. */
13770 r10k_safe_address_p (rtx x, rtx insn)
13773 HOST_WIDE_INT offset_val;
13775 x = r10k_simplify_address (x, insn);
13777 /* Check for references to the stack frame. It doesn't really matter
13778 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13779 allows us to assume that accesses to any part of the eventual frame
13780 is safe from speculation at any point in the function. */
13781 mips_split_plus (x, &base, &offset_val);
13782 if (base == virtual_incoming_args_rtx
13783 && offset_val >= -cfun->machine->frame.total_size
13784 && offset_val < cfun->machine->frame.args_size)
13787 /* Check for uncached addresses. */
13788 if (CONST_INT_P (x))
13789 return r10k_uncached_address_p (INTVAL (x));
13791 /* Check for accesses to a static object. */
13792 split_const (x, &base, &offset);
13793 return offset_within_block_p (base, INTVAL (offset));
13796 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13797 an in-range access to an automatic variable, or to an object with
13798 a link-time-constant address. */
13801 r10k_safe_mem_expr_p (tree expr, rtx offset)
13803 if (expr == NULL_TREE
13804 || offset == NULL_RTX
13805 || !CONST_INT_P (offset)
13806 || INTVAL (offset) < 0
13807 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13810 while (TREE_CODE (expr) == COMPONENT_REF)
13812 expr = TREE_OPERAND (expr, 0);
13813 if (expr == NULL_TREE)
13817 return DECL_P (expr);
13820 /* A for_each_rtx callback for which DATA points to the instruction
13821 containing *X. Stop the search if we find a MEM that is not safe
13822 from R10K speculation. */
13825 r10k_needs_protection_p_1 (rtx *loc, void *data)
13833 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13836 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13842 /* A note_stores callback for which DATA points to an instruction pointer.
13843 If *DATA is nonnull, make it null if it X contains a MEM that is not
13844 safe from R10K speculation. */
13847 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13852 insn_ptr = (rtx *) data;
13853 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13854 *insn_ptr = NULL_RTX;
13857 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13858 Return nonzero if the call is not to a declared function. */
13861 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13870 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13876 /* Return true if instruction INSN needs to be protected by an R10K
13880 r10k_needs_protection_p (rtx insn)
13883 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13885 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13887 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13888 return insn == NULL_RTX;
13891 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
13894 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
13895 edge is unconditional. */
13898 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
13903 FOR_EACH_EDGE (e, ei, bb->preds)
13904 if (!single_succ_p (e->src)
13905 || !TEST_BIT (protected_bbs, e->src->index)
13906 || (e->flags & EDGE_COMPLEX) != 0)
13911 /* Implement -mr10k-cache-barrier= for the current function. */
13914 r10k_insert_cache_barriers (void)
13916 int *rev_post_order;
13919 sbitmap protected_bbs;
13920 rtx insn, end, unprotected_region;
13924 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
13928 /* Calculate dominators. */
13929 calculate_dominance_info (CDI_DOMINATORS);
13931 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
13932 X is protected by a cache barrier. */
13933 protected_bbs = sbitmap_alloc (last_basic_block);
13934 sbitmap_zero (protected_bbs);
13936 /* Iterate over the basic blocks in reverse post-order. */
13937 rev_post_order = XNEWVEC (int, last_basic_block);
13938 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
13939 for (i = 0; i < n; i++)
13941 bb = BASIC_BLOCK (rev_post_order[i]);
13943 /* If this block is only reached by unconditional edges, and if the
13944 source of every edge is protected, the beginning of the block is
13946 if (r10k_protected_bb_p (bb, protected_bbs))
13947 unprotected_region = NULL_RTX;
13949 unprotected_region = pc_rtx;
13950 end = NEXT_INSN (BB_END (bb));
13952 /* UNPROTECTED_REGION is:
13954 - null if we are processing a protected region,
13955 - pc_rtx if we are processing an unprotected region but have
13956 not yet found the first instruction in it
13957 - the first instruction in an unprotected region otherwise. */
13958 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
13960 if (unprotected_region && USEFUL_INSN_P (insn))
13962 if (recog_memoized (insn) == CODE_FOR_mips_cache)
13963 /* This CACHE instruction protects the following code. */
13964 unprotected_region = NULL_RTX;
13967 /* See if INSN is the first instruction in this
13968 unprotected region. */
13969 if (unprotected_region == pc_rtx)
13970 unprotected_region = insn;
13972 /* See if INSN needs to be protected. If so,
13973 we must insert a cache barrier somewhere between
13974 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
13975 clear which position is better performance-wise,
13976 but as a tie-breaker, we assume that it is better
13977 to allow delay slots to be back-filled where
13978 possible, and that it is better not to insert
13979 barriers in the middle of already-scheduled code.
13980 We therefore insert the barrier at the beginning
13982 if (r10k_needs_protection_p (insn))
13984 emit_insn_before (gen_r10k_cache_barrier (),
13985 unprotected_region);
13986 unprotected_region = NULL_RTX;
13992 /* The called function is not required to protect the exit path.
13993 The code that follows a call is therefore unprotected. */
13994 unprotected_region = pc_rtx;
13997 /* Record whether the end of this block is protected. */
13998 if (unprotected_region == NULL_RTX)
13999 SET_BIT (protected_bbs, bb->index);
14001 XDELETEVEC (rev_post_order);
14003 sbitmap_free (protected_bbs);
14005 free_dominance_info (CDI_DOMINATORS);
14008 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14012 mips_call_expr_from_insn (rtx insn)
14016 if (!CALL_P (insn))
14019 x = PATTERN (insn);
14020 if (GET_CODE (x) == PARALLEL)
14021 x = XVECEXP (x, 0, 0);
14022 if (GET_CODE (x) == SET)
14025 gcc_assert (GET_CODE (x) == CALL);
14029 /* REG is set in DEF. See if the definition is one of the ways we load a
14030 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14031 it is return the symbol reference of the function, otherwise return
14035 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
14039 if (DF_REF_IS_ARTIFICIAL (def))
14042 def_insn = DF_REF_INSN (def);
14043 set = single_set (def_insn);
14044 if (set && rtx_equal_p (SET_DEST (set), reg))
14046 rtx note, src, symbol;
14048 /* First, look at REG_EQUAL/EQUIV notes. */
14049 note = find_reg_equal_equiv_note (def_insn);
14050 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14051 return XEXP (note, 0);
14053 /* For %call16 references we don't have REG_EQUAL. */
14054 src = SET_SRC (set);
14055 symbol = mips_strip_unspec_call (src);
14058 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14062 /* Follow simple register copies. */
14064 return mips_find_pic_call_symbol (def_insn, src);
14070 /* Find the definition of the use of REG in INSN. See if the definition is
14071 one of the ways we load a register with a symbol address for a
14072 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14073 the function, otherwise return NULL_RTX. */
14076 mips_find_pic_call_symbol (rtx insn, rtx reg)
14079 struct df_link *defs;
14082 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14085 defs = DF_REF_CHAIN (use);
14088 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14092 /* If we have more than one definition, they need to be identical. */
14093 for (defs = defs->next; defs; defs = defs->next)
14097 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14098 if (!rtx_equal_p (symbol, other))
14105 /* Replace the args_size operand of the call expression CALL with the
14106 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14109 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14113 args_size = XEXP (call, 1);
14114 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14115 gen_rtvec (2, args_size, symbol),
14119 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14120 if instead of the arg_size argument it contains the call attributes. If
14121 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14122 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14126 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14128 rtx args_size, symbol;
14130 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14133 args_size = operands[args_size_opno];
14134 if (GET_CODE (args_size) != UNSPEC)
14136 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14138 symbol = XVECEXP (args_size, 0, 1);
14139 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14141 operands[args_size_opno] = symbol;
14145 /* Use DF to annotate PIC indirect calls with the function symbol they
14149 mips_annotate_pic_calls (void)
14155 FOR_BB_INSNS (bb, insn)
14157 rtx call, reg, symbol;
14159 call = mips_call_expr_from_insn (insn);
14162 gcc_assert (MEM_P (XEXP (call, 0)));
14163 reg = XEXP (XEXP (call, 0), 0);
14167 symbol = mips_find_pic_call_symbol (insn, reg);
14169 mips_annotate_pic_call_expr (call, symbol);
14173 /* A temporary variable used by for_each_rtx callbacks, etc. */
14174 static rtx mips_sim_insn;
14176 /* A structure representing the state of the processor pipeline.
14177 Used by the mips_sim_* family of functions. */
14179 /* The maximum number of instructions that can be issued in a cycle.
14180 (Caches mips_issue_rate.) */
14181 unsigned int issue_rate;
14183 /* The current simulation time. */
14186 /* How many more instructions can be issued in the current cycle. */
14187 unsigned int insns_left;
14189 /* LAST_SET[X].INSN is the last instruction to set register X.
14190 LAST_SET[X].TIME is the time at which that instruction was issued.
14191 INSN is null if no instruction has yet set register X. */
14195 } last_set[FIRST_PSEUDO_REGISTER];
14197 /* The pipeline's current DFA state. */
14201 /* Reset STATE to the initial simulation state. */
14204 mips_sim_reset (struct mips_sim *state)
14207 state->insns_left = state->issue_rate;
14208 memset (&state->last_set, 0, sizeof (state->last_set));
14209 state_reset (state->dfa_state);
14212 /* Initialize STATE before its first use. DFA_STATE points to an
14213 allocated but uninitialized DFA state. */
14216 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14218 state->issue_rate = mips_issue_rate ();
14219 state->dfa_state = dfa_state;
14220 mips_sim_reset (state);
14223 /* Advance STATE by one clock cycle. */
14226 mips_sim_next_cycle (struct mips_sim *state)
14229 state->insns_left = state->issue_rate;
14230 state_transition (state->dfa_state, 0);
14233 /* Advance simulation state STATE until instruction INSN can read
14237 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14239 unsigned int regno, end_regno;
14241 end_regno = END_REGNO (reg);
14242 for (regno = REGNO (reg); regno < end_regno; regno++)
14243 if (state->last_set[regno].insn != 0)
14247 t = (state->last_set[regno].time
14248 + insn_latency (state->last_set[regno].insn, insn));
14249 while (state->time < t)
14250 mips_sim_next_cycle (state);
14254 /* A for_each_rtx callback. If *X is a register, advance simulation state
14255 DATA until mips_sim_insn can read the register's value. */
14258 mips_sim_wait_regs_2 (rtx *x, void *data)
14261 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14265 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14268 mips_sim_wait_regs_1 (rtx *x, void *data)
14270 for_each_rtx (x, mips_sim_wait_regs_2, data);
14273 /* Advance simulation state STATE until all of INSN's register
14274 dependencies are satisfied. */
14277 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14279 mips_sim_insn = insn;
14280 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14283 /* Advance simulation state STATE until the units required by
14284 instruction INSN are available. */
14287 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14291 tmp_state = alloca (state_size ());
14292 while (state->insns_left == 0
14293 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14294 state_transition (tmp_state, insn) >= 0))
14295 mips_sim_next_cycle (state);
14298 /* Advance simulation state STATE until INSN is ready to issue. */
14301 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14303 mips_sim_wait_regs (state, insn);
14304 mips_sim_wait_units (state, insn);
14307 /* mips_sim_insn has just set X. Update the LAST_SET array
14308 in simulation state DATA. */
14311 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14313 struct mips_sim *state;
14315 state = (struct mips_sim *) data;
14318 unsigned int regno, end_regno;
14320 end_regno = END_REGNO (x);
14321 for (regno = REGNO (x); regno < end_regno; regno++)
14323 state->last_set[regno].insn = mips_sim_insn;
14324 state->last_set[regno].time = state->time;
14329 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14330 can issue immediately (i.e., that mips_sim_wait_insn has already
14334 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14336 state_transition (state->dfa_state, insn);
14337 state->insns_left--;
14339 mips_sim_insn = insn;
14340 note_stores (PATTERN (insn), mips_sim_record_set, state);
14343 /* Simulate issuing a NOP in state STATE. */
14346 mips_sim_issue_nop (struct mips_sim *state)
14348 if (state->insns_left == 0)
14349 mips_sim_next_cycle (state);
14350 state->insns_left--;
14353 /* Update simulation state STATE so that it's ready to accept the instruction
14354 after INSN. INSN should be part of the main rtl chain, not a member of a
14358 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14360 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14362 mips_sim_issue_nop (state);
14364 switch (GET_CODE (SEQ_BEGIN (insn)))
14368 /* We can't predict the processor state after a call or label. */
14369 mips_sim_reset (state);
14373 /* The delay slots of branch likely instructions are only executed
14374 when the branch is taken. Therefore, if the caller has simulated
14375 the delay slot instruction, STATE does not really reflect the state
14376 of the pipeline for the instruction after the delay slot. Also,
14377 branch likely instructions tend to incur a penalty when not taken,
14378 so there will probably be an extra delay between the branch and
14379 the instruction after the delay slot. */
14380 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14381 mips_sim_reset (state);
14389 /* The VR4130 pipeline issues aligned pairs of instructions together,
14390 but it stalls the second instruction if it depends on the first.
14391 In order to cut down the amount of logic required, this dependence
14392 check is not based on a full instruction decode. Instead, any non-SPECIAL
14393 instruction is assumed to modify the register specified by bits 20-16
14394 (which is usually the "rt" field).
14396 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14397 input, so we can end up with a false dependence between the branch
14398 and its delay slot. If this situation occurs in instruction INSN,
14399 try to avoid it by swapping rs and rt. */
14402 vr4130_avoid_branch_rt_conflict (rtx insn)
14406 first = SEQ_BEGIN (insn);
14407 second = SEQ_END (insn);
14409 && NONJUMP_INSN_P (second)
14410 && GET_CODE (PATTERN (first)) == SET
14411 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14412 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14414 /* Check for the right kind of condition. */
14415 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14416 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14417 && REG_P (XEXP (cond, 0))
14418 && REG_P (XEXP (cond, 1))
14419 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14420 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14422 /* SECOND mentions the rt register but not the rs register. */
14423 rtx tmp = XEXP (cond, 0);
14424 XEXP (cond, 0) = XEXP (cond, 1);
14425 XEXP (cond, 1) = tmp;
14430 /* Implement -mvr4130-align. Go through each basic block and simulate the
14431 processor pipeline. If we find that a pair of instructions could execute
14432 in parallel, and the first of those instructions is not 8-byte aligned,
14433 insert a nop to make it aligned. */
14436 vr4130_align_insns (void)
14438 struct mips_sim state;
14439 rtx insn, subinsn, last, last2, next;
14444 /* LAST is the last instruction before INSN to have a nonzero length.
14445 LAST2 is the last such instruction before LAST. */
14449 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14452 mips_sim_init (&state, alloca (state_size ()));
14453 for (insn = get_insns (); insn != 0; insn = next)
14455 unsigned int length;
14457 next = NEXT_INSN (insn);
14459 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14460 This isn't really related to the alignment pass, but we do it on
14461 the fly to avoid a separate instruction walk. */
14462 vr4130_avoid_branch_rt_conflict (insn);
14464 if (USEFUL_INSN_P (insn))
14465 FOR_EACH_SUBINSN (subinsn, insn)
14467 mips_sim_wait_insn (&state, subinsn);
14469 /* If we want this instruction to issue in parallel with the
14470 previous one, make sure that the previous instruction is
14471 aligned. There are several reasons why this isn't worthwhile
14472 when the second instruction is a call:
14474 - Calls are less likely to be performance critical,
14475 - There's a good chance that the delay slot can execute
14476 in parallel with the call.
14477 - The return address would then be unaligned.
14479 In general, if we're going to insert a nop between instructions
14480 X and Y, it's better to insert it immediately after X. That
14481 way, if the nop makes Y aligned, it will also align any labels
14482 between X and Y. */
14483 if (state.insns_left != state.issue_rate
14484 && !CALL_P (subinsn))
14486 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14488 /* SUBINSN is the first instruction in INSN and INSN is
14489 aligned. We want to align the previous instruction
14490 instead, so insert a nop between LAST2 and LAST.
14492 Note that LAST could be either a single instruction
14493 or a branch with a delay slot. In the latter case,
14494 LAST, like INSN, is already aligned, but the delay
14495 slot must have some extra delay that stops it from
14496 issuing at the same time as the branch. We therefore
14497 insert a nop before the branch in order to align its
14499 emit_insn_after (gen_nop (), last2);
14502 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14504 /* SUBINSN is the delay slot of INSN, but INSN is
14505 currently unaligned. Insert a nop between
14506 LAST and INSN to align it. */
14507 emit_insn_after (gen_nop (), last);
14511 mips_sim_issue_insn (&state, subinsn);
14513 mips_sim_finish_insn (&state, insn);
14515 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14516 length = get_attr_length (insn);
14519 /* If the instruction is an asm statement or multi-instruction
14520 mips.md patern, the length is only an estimate. Insert an
14521 8 byte alignment after it so that the following instructions
14522 can be handled correctly. */
14523 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14524 && (recog_memoized (insn) < 0 || length >= 8))
14526 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14527 next = NEXT_INSN (next);
14528 mips_sim_next_cycle (&state);
14531 else if (length & 4)
14532 aligned_p = !aligned_p;
14537 /* See whether INSN is an aligned label. */
14538 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14544 /* This structure records that the current function has a LO_SUM
14545 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14546 the largest offset applied to BASE by all such LO_SUMs. */
14547 struct mips_lo_sum_offset {
14549 HOST_WIDE_INT offset;
14552 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14555 mips_hash_base (rtx base)
14557 int do_not_record_p;
14559 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14562 /* Hash-table callbacks for mips_lo_sum_offsets. */
14565 mips_lo_sum_offset_hash (const void *entry)
14567 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14571 mips_lo_sum_offset_eq (const void *entry, const void *value)
14573 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14574 (const_rtx) value);
14577 /* Look up symbolic constant X in HTAB, which is a hash table of
14578 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14579 paired with a recorded LO_SUM, otherwise record X in the table. */
14582 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14586 struct mips_lo_sum_offset *entry;
14588 /* Split X into a base and offset. */
14589 split_const (x, &base, &offset);
14590 if (UNSPEC_ADDRESS_P (base))
14591 base = UNSPEC_ADDRESS (base);
14593 /* Look up the base in the hash table. */
14594 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14598 entry = (struct mips_lo_sum_offset *) *slot;
14599 if (option == INSERT)
14603 entry = XNEW (struct mips_lo_sum_offset);
14604 entry->base = base;
14605 entry->offset = INTVAL (offset);
14610 if (INTVAL (offset) > entry->offset)
14611 entry->offset = INTVAL (offset);
14614 return INTVAL (offset) <= entry->offset;
14617 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14618 Record every LO_SUM in *LOC. */
14621 mips_record_lo_sum (rtx *loc, void *data)
14623 if (GET_CODE (*loc) == LO_SUM)
14624 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14628 /* Return true if INSN is a SET of an orphaned high-part relocation.
14629 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14630 LO_SUMs in the current function. */
14633 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14635 enum mips_symbol_type type;
14638 set = single_set (insn);
14641 /* Check for %his. */
14643 if (GET_CODE (x) == HIGH
14644 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14645 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14647 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14648 if (GET_CODE (x) == UNSPEC
14649 && XINT (x, 1) == UNSPEC_LOAD_GOT
14650 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14651 SYMBOL_CONTEXT_LEA, &type)
14652 && type == SYMBOL_GOTOFF_PAGE)
14653 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14658 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14659 INSN and a previous instruction, avoid it by inserting nops after
14662 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14663 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14664 before using the value of that register. *HILO_DELAY counts the
14665 number of instructions since the last hilo hazard (that is,
14666 the number of instructions since the last MFLO or MFHI).
14668 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14669 for the next instruction.
14671 LO_REG is an rtx for the LO register, used in dependence checking. */
14674 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14675 rtx *delayed_reg, rtx lo_reg)
14680 pattern = PATTERN (insn);
14682 /* Do not put the whole function in .set noreorder if it contains
14683 an asm statement. We don't know whether there will be hazards
14684 between the asm statement and the gcc-generated code. */
14685 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14686 cfun->machine->all_noreorder_p = false;
14688 /* Ignore zero-length instructions (barriers and the like). */
14689 ninsns = get_attr_length (insn) / 4;
14693 /* Work out how many nops are needed. Note that we only care about
14694 registers that are explicitly mentioned in the instruction's pattern.
14695 It doesn't matter that calls use the argument registers or that they
14696 clobber hi and lo. */
14697 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14698 nops = 2 - *hilo_delay;
14699 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14704 /* Insert the nops between this instruction and the previous one.
14705 Each new nop takes us further from the last hilo hazard. */
14706 *hilo_delay += nops;
14708 emit_insn_after (gen_hazard_nop (), after);
14710 /* Set up the state for the next instruction. */
14711 *hilo_delay += ninsns;
14713 if (INSN_CODE (insn) >= 0)
14714 switch (get_attr_hazard (insn))
14724 set = single_set (insn);
14726 *delayed_reg = SET_DEST (set);
14731 /* Go through the instruction stream and insert nops where necessary.
14732 Also delete any high-part relocations whose partnering low parts
14733 are now all dead. See if the whole function can then be put into
14734 .set noreorder and .set nomacro. */
14737 mips_reorg_process_insns (void)
14739 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14743 /* Force all instructions to be split into their final form. */
14744 split_all_insns_noflow ();
14746 /* Recalculate instruction lengths without taking nops into account. */
14747 cfun->machine->ignore_hazard_length_p = true;
14748 shorten_branches (get_insns ());
14750 cfun->machine->all_noreorder_p = true;
14752 /* We don't track MIPS16 PC-relative offsets closely enough to make
14753 a good job of "set .noreorder" code in MIPS16 mode. */
14755 cfun->machine->all_noreorder_p = false;
14757 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14758 if (!TARGET_EXPLICIT_RELOCS)
14759 cfun->machine->all_noreorder_p = false;
14761 /* Profiled functions can't be all noreorder because the profiler
14762 support uses assembler macros. */
14764 cfun->machine->all_noreorder_p = false;
14766 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14767 we rely on the assembler to work around some errata. */
14768 if (TARGET_FIX_VR4120)
14769 cfun->machine->all_noreorder_p = false;
14771 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14772 MFHI instructions. Note that we avoid using MFLO and MFHI if
14773 the VR4130 MACC and DMACC instructions are available instead;
14774 see the *mfhilo_{si,di}_macc patterns. */
14775 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14776 cfun->machine->all_noreorder_p = false;
14778 htab = htab_create (37, mips_lo_sum_offset_hash,
14779 mips_lo_sum_offset_eq, free);
14781 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14782 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14783 FOR_EACH_SUBINSN (subinsn, insn)
14784 if (USEFUL_INSN_P (subinsn))
14785 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14790 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14792 /* Make a second pass over the instructions. Delete orphaned
14793 high-part relocations or turn them into NOPs. Avoid hazards
14794 by inserting NOPs. */
14795 for (insn = get_insns (); insn != 0; insn = next_insn)
14797 next_insn = NEXT_INSN (insn);
14798 if (USEFUL_INSN_P (insn))
14800 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14802 /* If we find an orphaned high-part relocation in a delay
14803 slot, it's easier to turn that instruction into a NOP than
14804 to delete it. The delay slot will be a NOP either way. */
14805 FOR_EACH_SUBINSN (subinsn, insn)
14806 if (INSN_P (subinsn))
14808 if (mips_orphaned_high_part_p (htab, subinsn))
14810 PATTERN (subinsn) = gen_nop ();
14811 INSN_CODE (subinsn) = CODE_FOR_nop;
14813 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14814 &delayed_reg, lo_reg);
14820 /* INSN is a single instruction. Delete it if it's an
14821 orphaned high-part relocation. */
14822 if (mips_orphaned_high_part_p (htab, insn))
14823 delete_insn (insn);
14824 /* Also delete cache barriers if the last instruction
14825 was an annulled branch. INSN will not be speculatively
14827 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14829 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14830 delete_insn (insn);
14833 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14834 &delayed_reg, lo_reg);
14841 htab_delete (htab);
14844 /* If we are using a GOT, but have not decided to use a global pointer yet,
14845 see whether we need one to implement long branches. Convert the ghost
14846 global-pointer instructions into real ones if so. */
14849 mips_expand_ghost_gp_insns (void)
14854 /* Quick exit if we already know that we will or won't need a
14856 if (!TARGET_USE_GOT
14857 || cfun->machine->global_pointer == INVALID_REGNUM
14858 || mips_must_initialize_gp_p ())
14861 shorten_branches (get_insns ());
14863 /* Look for a branch that is longer than normal. The normal length for
14864 non-MIPS16 branches is 8, because the length includes the delay slot.
14865 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14866 but they have no delay slot. */
14867 normal_length = (TARGET_MIPS16 ? 4 : 8);
14868 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14870 && USEFUL_INSN_P (insn)
14871 && get_attr_length (insn) > normal_length)
14874 if (insn == NULL_RTX)
14877 /* We've now established that we need $gp. */
14878 cfun->machine->must_initialize_gp_p = true;
14879 split_all_insns_noflow ();
14884 /* Subroutine of mips_reorg to manage passes that require DF. */
14887 mips_df_reorg (void)
14889 /* Create def-use chains. */
14890 df_set_flags (DF_EQ_NOTES);
14891 df_chain_add_problem (DF_UD_CHAIN);
14894 if (TARGET_RELAX_PIC_CALLS)
14895 mips_annotate_pic_calls ();
14897 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
14898 r10k_insert_cache_barriers ();
14900 df_finish_pass (false);
14903 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
14908 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
14909 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
14910 to date if the CFG is available. */
14911 if (mips_cfg_in_reorg ())
14912 compute_bb_for_insn ();
14913 mips16_lay_out_constants ();
14914 if (mips_cfg_in_reorg ())
14917 free_bb_for_insn ();
14920 if (optimize > 0 && flag_delayed_branch)
14921 dbr_schedule (get_insns ());
14922 mips_reorg_process_insns ();
14924 && TARGET_EXPLICIT_RELOCS
14926 && TARGET_VR4130_ALIGN)
14927 vr4130_align_insns ();
14928 if (mips_expand_ghost_gp_insns ())
14929 /* The expansion could invalidate some of the VR4130 alignment
14930 optimizations, but this should be an extremely rare case anyhow. */
14931 mips_reorg_process_insns ();
14934 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
14935 in order to avoid duplicating too much logic from elsewhere. */
14938 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14939 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14942 rtx this_rtx, temp1, temp2, insn, fnaddr;
14943 bool use_sibcall_p;
14945 /* Pretend to be a post-reload pass while generating rtl. */
14946 reload_completed = 1;
14948 /* Mark the end of the (empty) prologue. */
14949 emit_note (NOTE_INSN_PROLOGUE_END);
14951 /* Determine if we can use a sibcall to call FUNCTION directly. */
14952 fnaddr = XEXP (DECL_RTL (function), 0);
14953 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
14954 && const_call_insn_operand (fnaddr, Pmode));
14956 /* Determine if we need to load FNADDR from the GOT. */
14958 && (mips_got_symbol_type_p
14959 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
14961 /* Pick a global pointer. Use a call-clobbered register if
14962 TARGET_CALL_SAVED_GP. */
14963 cfun->machine->global_pointer
14964 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
14965 cfun->machine->must_initialize_gp_p = true;
14966 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
14968 /* Set up the global pointer for n32 or n64 abicalls. */
14969 mips_emit_loadgp ();
14972 /* We need two temporary registers in some cases. */
14973 temp1 = gen_rtx_REG (Pmode, 2);
14974 temp2 = gen_rtx_REG (Pmode, 3);
14976 /* Find out which register contains the "this" pointer. */
14977 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14978 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
14980 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
14982 /* Add DELTA to THIS_RTX. */
14985 rtx offset = GEN_INT (delta);
14986 if (!SMALL_OPERAND (delta))
14988 mips_emit_move (temp1, offset);
14991 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
14994 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
14995 if (vcall_offset != 0)
14999 /* Set TEMP1 to *THIS_RTX. */
15000 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15002 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15003 addr = mips_add_offset (temp2, temp1, vcall_offset);
15005 /* Load the offset and add it to THIS_RTX. */
15006 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15007 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15010 /* Jump to the target function. Use a sibcall if direct jumps are
15011 allowed, otherwise load the address into a register first. */
15014 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15015 SIBLING_CALL_P (insn) = 1;
15019 /* This is messy. GAS treats "la $25,foo" as part of a call
15020 sequence and may allow a global "foo" to be lazily bound.
15021 The general move patterns therefore reject this combination.
15023 In this context, lazy binding would actually be OK
15024 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15025 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15026 We must therefore load the address via a temporary
15027 register if mips_dangerous_for_la25_p.
15029 If we jump to the temporary register rather than $25,
15030 the assembler can use the move insn to fill the jump's
15033 We can use the same technique for MIPS16 code, where $25
15034 is not a valid JR register. */
15035 if (TARGET_USE_PIC_FN_ADDR_REG
15037 && !mips_dangerous_for_la25_p (fnaddr))
15038 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15039 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15041 if (TARGET_USE_PIC_FN_ADDR_REG
15042 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15043 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15044 emit_jump_insn (gen_indirect_jump (temp1));
15047 /* Run just enough of rest_of_compilation. This sequence was
15048 "borrowed" from alpha.c. */
15049 insn = get_insns ();
15050 insn_locators_alloc ();
15051 split_all_insns_noflow ();
15052 mips16_lay_out_constants ();
15053 shorten_branches (insn);
15054 final_start_function (insn, file, 1);
15055 final (insn, file, 1);
15056 final_end_function ();
15058 /* Clean up the vars set above. Note that final_end_function resets
15059 the global pointer for us. */
15060 reload_completed = 0;
15063 /* The last argument passed to mips_set_mips16_mode, or negative if the
15064 function hasn't been called yet.
15066 There are two copies of this information. One is saved and restored
15067 by the PCH process while the other is specific to this compiler
15068 invocation. The information calculated by mips_set_mips16_mode
15069 is invalid unless the two variables are the same. */
15070 static int was_mips16_p = -1;
15071 static GTY(()) int was_mips16_pch_p = -1;
15073 /* Set up the target-dependent global state so that it matches the
15074 current function's ISA mode. */
15077 mips_set_mips16_mode (int mips16_p)
15079 if (mips16_p == was_mips16_p
15080 && mips16_p == was_mips16_pch_p)
15083 /* Restore base settings of various flags. */
15084 target_flags = mips_base_target_flags;
15085 flag_schedule_insns = mips_base_schedule_insns;
15086 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15087 flag_move_loop_invariants = mips_base_move_loop_invariants;
15088 align_loops = mips_base_align_loops;
15089 align_jumps = mips_base_align_jumps;
15090 align_functions = mips_base_align_functions;
15094 /* Switch to MIPS16 mode. */
15095 target_flags |= MASK_MIPS16;
15097 /* Don't run the scheduler before reload, since it tends to
15098 increase register pressure. */
15099 flag_schedule_insns = 0;
15101 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15102 the whole function to be in a single section. */
15103 flag_reorder_blocks_and_partition = 0;
15105 /* Don't move loop invariants, because it tends to increase
15106 register pressure. It also introduces an extra move in cases
15107 where the constant is the first operand in a two-operand binary
15108 instruction, or when it forms a register argument to a functon
15110 flag_move_loop_invariants = 0;
15112 target_flags |= MASK_EXPLICIT_RELOCS;
15114 /* Experiments suggest we get the best overall section-anchor
15115 results from using the range of an unextended LW or SW. Code
15116 that makes heavy use of byte or short accesses can do better
15117 with ranges of 0...31 and 0...63 respectively, but most code is
15118 sensitive to the range of LW and SW instead. */
15119 targetm.min_anchor_offset = 0;
15120 targetm.max_anchor_offset = 127;
15122 targetm.const_anchor = 0;
15124 /* MIPS16 has no BAL instruction. */
15125 target_flags &= ~MASK_RELAX_PIC_CALLS;
15127 if (flag_pic && !TARGET_OLDABI)
15128 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15131 sorry ("MIPS16 -mxgot code");
15133 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15134 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15138 /* Switch to normal (non-MIPS16) mode. */
15139 target_flags &= ~MASK_MIPS16;
15141 /* Provide default values for align_* for 64-bit targets. */
15144 if (align_loops == 0)
15146 if (align_jumps == 0)
15148 if (align_functions == 0)
15149 align_functions = 8;
15152 targetm.min_anchor_offset = -32768;
15153 targetm.max_anchor_offset = 32767;
15155 targetm.const_anchor = 0x8000;
15158 /* (Re)initialize MIPS target internals for new ISA. */
15159 mips_init_relocs ();
15161 if (was_mips16_p >= 0 || was_mips16_pch_p >= 0)
15162 /* Reinitialize target-dependent state. */
15165 was_mips16_p = mips16_p;
15166 was_mips16_pch_p = mips16_p;
15169 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15170 function should use the MIPS16 ISA and switch modes accordingly. */
15173 mips_set_current_function (tree fndecl)
15175 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15178 /* Allocate a chunk of memory for per-function machine-dependent data. */
15180 static struct machine_function *
15181 mips_init_machine_status (void)
15183 return ((struct machine_function *)
15184 ggc_alloc_cleared (sizeof (struct machine_function)));
15187 /* Return the processor associated with the given ISA level, or null
15188 if the ISA isn't valid. */
15190 static const struct mips_cpu_info *
15191 mips_cpu_info_from_isa (int isa)
15195 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15196 if (mips_cpu_info_table[i].isa == isa)
15197 return mips_cpu_info_table + i;
15202 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15203 with a final "000" replaced by "k". Ignore case.
15205 Note: this function is shared between GCC and GAS. */
15208 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15210 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15211 given++, canonical++;
15213 return ((*given == 0 && *canonical == 0)
15214 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15217 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15218 CPU name. We've traditionally allowed a lot of variation here.
15220 Note: this function is shared between GCC and GAS. */
15223 mips_matching_cpu_name_p (const char *canonical, const char *given)
15225 /* First see if the name matches exactly, or with a final "000"
15226 turned into "k". */
15227 if (mips_strict_matching_cpu_name_p (canonical, given))
15230 /* If not, try comparing based on numerical designation alone.
15231 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15232 if (TOLOWER (*given) == 'r')
15234 if (!ISDIGIT (*given))
15237 /* Skip over some well-known prefixes in the canonical name,
15238 hoping to find a number there too. */
15239 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15241 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15243 else if (TOLOWER (canonical[0]) == 'r')
15246 return mips_strict_matching_cpu_name_p (canonical, given);
15249 /* Return the mips_cpu_info entry for the processor or ISA given
15250 by CPU_STRING. Return null if the string isn't recognized.
15252 A similar function exists in GAS. */
15254 static const struct mips_cpu_info *
15255 mips_parse_cpu (const char *cpu_string)
15260 /* In the past, we allowed upper-case CPU names, but it doesn't
15261 work well with the multilib machinery. */
15262 for (s = cpu_string; *s != 0; s++)
15265 warning (0, "CPU names must be lower case");
15269 /* 'from-abi' selects the most compatible architecture for the given
15270 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15271 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15273 if (strcasecmp (cpu_string, "from-abi") == 0)
15274 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15275 : ABI_NEEDS_64BIT_REGS ? 3
15276 : (TARGET_64BIT ? 3 : 1));
15278 /* 'default' has traditionally been a no-op. Probably not very useful. */
15279 if (strcasecmp (cpu_string, "default") == 0)
15282 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15283 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15284 return mips_cpu_info_table + i;
15289 /* Set up globals to generate code for the ISA or processor
15290 described by INFO. */
15293 mips_set_architecture (const struct mips_cpu_info *info)
15297 mips_arch_info = info;
15298 mips_arch = info->cpu;
15299 mips_isa = info->isa;
15303 /* Likewise for tuning. */
15306 mips_set_tune (const struct mips_cpu_info *info)
15310 mips_tune_info = info;
15311 mips_tune = info->cpu;
15315 /* Implement TARGET_HANDLE_OPTION. */
15318 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
15323 if (strcmp (arg, "32") == 0)
15325 else if (strcmp (arg, "o64") == 0)
15326 mips_abi = ABI_O64;
15327 else if (strcmp (arg, "n32") == 0)
15328 mips_abi = ABI_N32;
15329 else if (strcmp (arg, "64") == 0)
15331 else if (strcmp (arg, "eabi") == 0)
15332 mips_abi = ABI_EABI;
15339 return mips_parse_cpu (arg) != 0;
15342 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15343 return mips_isa_option_info != 0;
15345 case OPT_mno_flush_func:
15346 mips_cache_flush_func = NULL;
15349 case OPT_mcode_readable_:
15350 if (strcmp (arg, "yes") == 0)
15351 mips_code_readable = CODE_READABLE_YES;
15352 else if (strcmp (arg, "pcrel") == 0)
15353 mips_code_readable = CODE_READABLE_PCREL;
15354 else if (strcmp (arg, "no") == 0)
15355 mips_code_readable = CODE_READABLE_NO;
15360 case OPT_mr10k_cache_barrier_:
15361 if (strcmp (arg, "load-store") == 0)
15362 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15363 else if (strcmp (arg, "store") == 0)
15364 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15365 else if (strcmp (arg, "none") == 0)
15366 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15376 /* Implement OVERRIDE_OPTIONS. */
15379 mips_override_options (void)
15381 int i, start, regno, mode;
15383 /* Process flags as though we were generating non-MIPS16 code. */
15384 mips_base_mips16 = TARGET_MIPS16;
15385 target_flags &= ~MASK_MIPS16;
15387 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15388 SUBTARGET_OVERRIDE_OPTIONS;
15391 /* Set the small data limit. */
15392 mips_small_data_threshold = (g_switch_set
15394 : MIPS_DEFAULT_GVALUE);
15396 /* The following code determines the architecture and register size.
15397 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15398 The GAS and GCC code should be kept in sync as much as possible. */
15400 if (mips_arch_string != 0)
15401 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15403 if (mips_isa_option_info != 0)
15405 if (mips_arch_info == 0)
15406 mips_set_architecture (mips_isa_option_info);
15407 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15408 error ("%<-%s%> conflicts with the other architecture options, "
15409 "which specify a %s processor",
15410 mips_isa_option_info->name,
15411 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15414 if (mips_arch_info == 0)
15416 #ifdef MIPS_CPU_STRING_DEFAULT
15417 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15419 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15423 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15424 error ("%<-march=%s%> is not compatible with the selected ABI",
15425 mips_arch_info->name);
15427 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15428 if (mips_tune_string != 0)
15429 mips_set_tune (mips_parse_cpu (mips_tune_string));
15431 if (mips_tune_info == 0)
15432 mips_set_tune (mips_arch_info);
15434 if ((target_flags_explicit & MASK_64BIT) != 0)
15436 /* The user specified the size of the integer registers. Make sure
15437 it agrees with the ABI and ISA. */
15438 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15439 error ("%<-mgp64%> used with a 32-bit processor");
15440 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15441 error ("%<-mgp32%> used with a 64-bit ABI");
15442 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15443 error ("%<-mgp64%> used with a 32-bit ABI");
15447 /* Infer the integer register size from the ABI and processor.
15448 Restrict ourselves to 32-bit registers if that's all the
15449 processor has, or if the ABI cannot handle 64-bit registers. */
15450 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15451 target_flags &= ~MASK_64BIT;
15453 target_flags |= MASK_64BIT;
15456 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15458 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15459 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15460 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15461 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15462 else if (!TARGET_64BIT && TARGET_FLOAT64)
15464 if (!ISA_HAS_MXHC1)
15465 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15466 " the target supports the mfhc1 and mthc1 instructions");
15467 else if (mips_abi != ABI_32)
15468 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15474 /* -msingle-float selects 32-bit float registers. Otherwise the
15475 float registers should be the same size as the integer ones. */
15476 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15477 target_flags |= MASK_FLOAT64;
15479 target_flags &= ~MASK_FLOAT64;
15482 /* End of code shared with GAS. */
15484 /* If no -mlong* option was given, infer it from the other options. */
15485 if ((target_flags_explicit & MASK_LONG64) == 0)
15487 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15488 target_flags |= MASK_LONG64;
15490 target_flags &= ~MASK_LONG64;
15493 if (!TARGET_OLDABI)
15494 flag_pcc_struct_return = 0;
15496 /* Decide which rtx_costs structure to use. */
15498 mips_cost = &mips_rtx_cost_optimize_size;
15500 mips_cost = &mips_rtx_cost_data[mips_tune];
15502 /* If the user hasn't specified a branch cost, use the processor's
15504 if (mips_branch_cost == 0)
15505 mips_branch_cost = mips_cost->branch_cost;
15507 /* If neither -mbranch-likely nor -mno-branch-likely was given
15508 on the command line, set MASK_BRANCHLIKELY based on the target
15509 architecture and tuning flags. Annulled delay slots are a
15510 size win, so we only consider the processor-specific tuning
15511 for !optimize_size. */
15512 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15514 if (ISA_HAS_BRANCHLIKELY
15516 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15517 target_flags |= MASK_BRANCHLIKELY;
15519 target_flags &= ~MASK_BRANCHLIKELY;
15521 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15522 warning (0, "the %qs architecture does not support branch-likely"
15523 " instructions", mips_arch_info->name);
15525 /* The effect of -mabicalls isn't defined for the EABI. */
15526 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15528 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15529 target_flags &= ~MASK_ABICALLS;
15532 if (TARGET_ABICALLS_PIC2)
15533 /* We need to set flag_pic for executables as well as DSOs
15534 because we may reference symbols that are not defined in
15535 the final executable. (MIPS does not use things like
15536 copy relocs, for example.)
15538 There is a body of code that uses __PIC__ to distinguish
15539 between -mabicalls and -mno-abicalls code. The non-__PIC__
15540 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15541 long as any indirect jumps use $25. */
15544 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15545 faster code, but at the expense of more nops. Enable it at -O3 and
15547 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15548 target_flags |= MASK_VR4130_ALIGN;
15550 /* Prefer a call to memcpy over inline code when optimizing for size,
15551 though see MOVE_RATIO in mips.h. */
15552 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15553 target_flags |= MASK_MEMCPY;
15555 /* If we have a nonzero small-data limit, check that the -mgpopt
15556 setting is consistent with the other target flags. */
15557 if (mips_small_data_threshold > 0)
15561 if (!TARGET_EXPLICIT_RELOCS)
15562 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15564 TARGET_LOCAL_SDATA = false;
15565 TARGET_EXTERN_SDATA = false;
15569 if (TARGET_VXWORKS_RTP)
15570 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15572 if (TARGET_ABICALLS)
15573 warning (0, "cannot use small-data accesses for %qs",
15578 #ifdef MIPS_TFMODE_FORMAT
15579 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15582 /* Make sure that the user didn't turn off paired single support when
15583 MIPS-3D support is requested. */
15585 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15586 && !TARGET_PAIRED_SINGLE_FLOAT)
15587 error ("%<-mips3d%> requires %<-mpaired-single%>");
15589 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15591 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15593 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15594 and TARGET_HARD_FLOAT_ABI are both true. */
15595 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15596 error ("%qs must be used with %qs",
15597 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15598 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15600 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15602 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15603 warning (0, "the %qs architecture does not support paired-single"
15604 " instructions", mips_arch_info->name);
15606 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15607 && !TARGET_CACHE_BUILTIN)
15609 error ("%qs requires a target that provides the %qs instruction",
15610 "-mr10k-cache-barrier", "cache");
15611 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15614 /* If TARGET_DSPR2, enable MASK_DSP. */
15616 target_flags |= MASK_DSP;
15618 /* .eh_frame addresses should be the same width as a C pointer.
15619 Most MIPS ABIs support only one pointer size, so the assembler
15620 will usually know exactly how big an .eh_frame address is.
15622 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15623 originally defined to use 64-bit pointers (i.e. it is LP64), and
15624 this is still the default mode. However, we also support an n32-like
15625 ILP32 mode, which is selected by -mlong32. The problem is that the
15626 assembler has traditionally not had an -mlong option, so it has
15627 traditionally not known whether we're using the ILP32 or LP64 form.
15629 As it happens, gas versions up to and including 2.19 use _32-bit_
15630 addresses for EABI64 .cfi_* directives. This is wrong for the
15631 default LP64 mode, so we can't use the directives by default.
15632 Moreover, since gas's current behavior is at odds with gcc's
15633 default behavior, it seems unwise to rely on future versions
15634 of gas behaving the same way. We therefore avoid using .cfi
15635 directives for -mlong32 as well. */
15636 if (mips_abi == ABI_EABI && TARGET_64BIT)
15637 flag_dwarf2_cfi_asm = 0;
15639 /* .cfi_* directives generate a read-only section, so fall back on
15640 manual .eh_frame creation if we need the section to be writable. */
15641 if (TARGET_WRITABLE_EH_FRAME)
15642 flag_dwarf2_cfi_asm = 0;
15644 mips_init_print_operand_punct ();
15646 /* Set up array to map GCC register number to debug register number.
15647 Ignore the special purpose register numbers. */
15649 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15651 mips_dbx_regno[i] = INVALID_REGNUM;
15652 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15653 mips_dwarf_regno[i] = i;
15655 mips_dwarf_regno[i] = INVALID_REGNUM;
15658 start = GP_DBX_FIRST - GP_REG_FIRST;
15659 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15660 mips_dbx_regno[i] = i + start;
15662 start = FP_DBX_FIRST - FP_REG_FIRST;
15663 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15664 mips_dbx_regno[i] = i + start;
15666 /* Accumulator debug registers use big-endian ordering. */
15667 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15668 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15669 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15670 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15671 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15673 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15674 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15677 /* Set up mips_hard_regno_mode_ok. */
15678 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15679 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15680 mips_hard_regno_mode_ok[mode][regno]
15681 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15683 /* Function to allocate machine-dependent function status. */
15684 init_machine_status = &mips_init_machine_status;
15686 /* Default to working around R4000 errata only if the processor
15687 was selected explicitly. */
15688 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15689 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15690 target_flags |= MASK_FIX_R4000;
15692 /* Default to working around R4400 errata only if the processor
15693 was selected explicitly. */
15694 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15695 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15696 target_flags |= MASK_FIX_R4400;
15698 /* Default to working around R10000 errata only if the processor
15699 was selected explicitly. */
15700 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15701 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15702 target_flags |= MASK_FIX_R10000;
15704 /* Make sure that branch-likely instructions available when using
15705 -mfix-r10000. The instructions are not available if either:
15707 1. -mno-branch-likely was passed.
15708 2. The selected ISA does not support branch-likely and
15709 the command line does not include -mbranch-likely. */
15710 if (TARGET_FIX_R10000
15711 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15712 ? !ISA_HAS_BRANCHLIKELY
15713 : !TARGET_BRANCHLIKELY))
15714 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15716 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15718 warning (0, "the %qs architecture does not support the synci "
15719 "instruction", mips_arch_info->name);
15720 target_flags &= ~MASK_SYNCI;
15723 /* Only optimize PIC indirect calls if they are actually required. */
15724 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15725 target_flags &= ~MASK_RELAX_PIC_CALLS;
15727 /* Save base state of options. */
15728 mips_base_target_flags = target_flags;
15729 mips_base_schedule_insns = flag_schedule_insns;
15730 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15731 mips_base_move_loop_invariants = flag_move_loop_invariants;
15732 mips_base_align_loops = align_loops;
15733 mips_base_align_jumps = align_jumps;
15734 mips_base_align_functions = align_functions;
15736 /* Now select the ISA mode.
15738 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15739 MIPS16 mode afterwards if need be. */
15740 mips_set_mips16_mode (false);
15743 /* Swap the register information for registers I and I + 1, which
15744 currently have the wrong endianness. Note that the registers'
15745 fixedness and call-clobberedness might have been set on the
15749 mips_swap_registers (unsigned int i)
15754 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15755 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15757 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15758 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15759 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15760 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15766 /* Implement CONDITIONAL_REGISTER_USAGE. */
15769 mips_conditional_register_usage (void)
15774 /* These DSP control register fields are global. */
15775 global_regs[CCDSP_PO_REGNUM] = 1;
15776 global_regs[CCDSP_SC_REGNUM] = 1;
15782 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15783 fixed_regs[regno] = call_used_regs[regno] = 1;
15785 if (!TARGET_HARD_FLOAT)
15789 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15790 fixed_regs[regno] = call_used_regs[regno] = 1;
15791 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15792 fixed_regs[regno] = call_used_regs[regno] = 1;
15794 else if (! ISA_HAS_8CC)
15798 /* We only have a single condition-code register. We implement
15799 this by fixing all the condition-code registers and generating
15800 RTL that refers directly to ST_REG_FIRST. */
15801 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15802 fixed_regs[regno] = call_used_regs[regno] = 1;
15804 /* In MIPS16 mode, we permit the $t temporary registers to be used
15805 for reload. We prohibit the unused $s registers, since they
15806 are call-saved, and saving them via a MIPS16 register would
15807 probably waste more time than just reloading the value. */
15810 fixed_regs[18] = call_used_regs[18] = 1;
15811 fixed_regs[19] = call_used_regs[19] = 1;
15812 fixed_regs[20] = call_used_regs[20] = 1;
15813 fixed_regs[21] = call_used_regs[21] = 1;
15814 fixed_regs[22] = call_used_regs[22] = 1;
15815 fixed_regs[23] = call_used_regs[23] = 1;
15816 fixed_regs[26] = call_used_regs[26] = 1;
15817 fixed_regs[27] = call_used_regs[27] = 1;
15818 fixed_regs[30] = call_used_regs[30] = 1;
15820 /* $f20-$f23 are call-clobbered for n64. */
15821 if (mips_abi == ABI_64)
15824 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15825 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15827 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15829 if (mips_abi == ABI_N32)
15832 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15833 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15835 /* Make sure that double-register accumulator values are correctly
15836 ordered for the current endianness. */
15837 if (TARGET_LITTLE_ENDIAN)
15839 unsigned int regno;
15841 mips_swap_registers (MD_REG_FIRST);
15842 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15843 mips_swap_registers (regno);
15847 /* Initialize vector TARGET to VALS. */
15850 mips_expand_vector_init (rtx target, rtx vals)
15852 enum machine_mode mode;
15853 enum machine_mode inner;
15854 unsigned int i, n_elts;
15857 mode = GET_MODE (target);
15858 inner = GET_MODE_INNER (mode);
15859 n_elts = GET_MODE_NUNITS (mode);
15861 gcc_assert (VECTOR_MODE_P (mode));
15863 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
15864 for (i = 0; i < n_elts; i++)
15865 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
15866 XVECEXP (vals, 0, i));
15868 emit_move_insn (target, mem);
15871 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
15872 other registers for instructions for which it is possible. This
15873 encourages the compiler to use CMP in cases where an XOR would
15874 require some register shuffling. */
15877 mips_order_regs_for_local_alloc (void)
15881 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15882 reg_alloc_order[i] = i;
15886 /* It really doesn't matter where we put register 0, since it is
15887 a fixed register anyhow. */
15888 reg_alloc_order[0] = 24;
15889 reg_alloc_order[24] = 0;
15893 /* Implement EH_USES. */
15896 mips_eh_uses (unsigned int regno)
15898 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
15900 /* We need to force certain registers to be live in order to handle
15901 PIC long branches correctly. See mips_must_initialize_gp_p for
15903 if (mips_cfun_has_cprestore_slot_p ())
15905 if (regno == CPRESTORE_SLOT_REGNUM)
15910 if (cfun->machine->global_pointer == regno)
15918 /* Implement EPILOGUE_USES. */
15921 mips_epilogue_uses (unsigned int regno)
15923 /* Say that the epilogue uses the return address register. Note that
15924 in the case of sibcalls, the values "used by the epilogue" are
15925 considered live at the start of the called function. */
15926 if (regno == RETURN_ADDR_REGNUM)
15929 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
15930 See the comment above load_call<mode> for details. */
15931 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
15934 /* An interrupt handler must preserve some registers that are
15935 ordinarily call-clobbered. */
15936 if (cfun->machine->interrupt_handler_p
15937 && mips_interrupt_extra_call_saved_reg_p (regno))
15943 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
15946 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
15948 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
15951 /* Return true if INSN needs to be wrapped in ".set noat".
15952 INSN has NOPERANDS operands, stored in OPVEC. */
15955 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
15959 if (recog_memoized (insn) >= 0)
15960 for (i = 0; i < noperands; i++)
15961 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
15966 /* Implement FINAL_PRESCAN_INSN. */
15969 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
15971 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15972 mips_push_asm_switch (&mips_noat);
15975 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
15978 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
15979 rtx *opvec, int noperands)
15981 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
15982 mips_pop_asm_switch (&mips_noat);
15985 /* Return the function that is used to expand the <u>mulsidi3 pattern.
15986 EXT_CODE is the code of the extension used. Return NULL if widening
15987 multiplication shouldn't be used. */
15990 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
15994 signed_p = ext_code == SIGN_EXTEND;
15997 /* Don't use widening multiplication with MULT when we have DMUL. Even
15998 with the extension of its input operands DMUL is faster. Note that
15999 the extension is not needed for signed multiplication. In order to
16000 ensure that we always remove the redundant sign-extension in this
16001 case we still expand mulsidi3 for DMUL. */
16003 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16004 if (TARGET_FIX_R4000)
16006 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16010 if (TARGET_FIX_R4000)
16011 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16013 return signed_p ? gen_mips_mult : gen_mips_multu;
16014 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16018 /* Return the size in bytes of the trampoline code, padded to
16019 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16020 function address immediately follow. */
16023 mips_trampoline_code_size (void)
16025 if (TARGET_USE_PIC_FN_ADDR_REG)
16027 else if (ptr_mode == DImode)
16029 else if (ISA_HAS_LOAD_DELAY)
16035 /* Implement TARGET_TRAMPOLINE_INIT. */
16038 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16040 rtx addr, end_addr, high, low, opcode, mem;
16043 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16045 /* Work out the offsets of the pointers from the start of the
16046 trampoline code. */
16047 end_addr_offset = mips_trampoline_code_size ();
16048 static_chain_offset = end_addr_offset;
16049 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16051 /* Get pointers to the beginning and end of the code block. */
16052 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16053 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16055 #define OP(X) gen_int_mode (X, SImode)
16057 /* Build up the code in TRAMPOLINE. */
16059 if (TARGET_USE_PIC_FN_ADDR_REG)
16061 /* $25 contains the address of the trampoline. Emit code of the form:
16063 l[wd] $1, target_function_offset($25)
16064 l[wd] $static_chain, static_chain_offset($25)
16067 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16068 target_function_offset,
16069 PIC_FUNCTION_ADDR_REGNUM));
16070 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16071 static_chain_offset,
16072 PIC_FUNCTION_ADDR_REGNUM));
16073 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16074 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16076 else if (ptr_mode == DImode)
16078 /* It's too cumbersome to create the full 64-bit address, so let's
16084 1: l[wd] $25, target_function_offset - 12($31)
16085 l[wd] $static_chain, static_chain_offset - 12($31)
16089 where 12 is the offset of "1:" from the start of the code block. */
16090 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16091 trampoline[i++] = OP (MIPS_BAL (1));
16092 trampoline[i++] = OP (MIPS_NOP);
16093 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16094 target_function_offset - 12,
16095 RETURN_ADDR_REGNUM));
16096 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16097 static_chain_offset - 12,
16098 RETURN_ADDR_REGNUM));
16099 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16100 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16104 /* If the target has load delays, emit:
16106 lui $1, %hi(end_addr)
16107 lw $25, %lo(end_addr + ...)($1)
16108 lw $static_chain, %lo(end_addr + ...)($1)
16114 lui $1, %hi(end_addr)
16115 lw $25, %lo(end_addr + ...)($1)
16117 lw $static_chain, %lo(end_addr + ...)($1). */
16119 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16120 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16121 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16122 NULL, false, OPTAB_WIDEN);
16123 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16124 NULL, false, OPTAB_WIDEN);
16125 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16127 /* Emit the LUI. */
16128 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16129 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16130 NULL, false, OPTAB_WIDEN);
16132 /* Emit the load of the target function. */
16133 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16134 target_function_offset - end_addr_offset,
16136 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16137 NULL, false, OPTAB_WIDEN);
16139 /* Emit the JR here, if we can. */
16140 if (!ISA_HAS_LOAD_DELAY)
16141 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16143 /* Emit the load of the static chain register. */
16144 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16145 static_chain_offset - end_addr_offset,
16147 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16148 NULL, false, OPTAB_WIDEN);
16150 /* Emit the JR, if we couldn't above. */
16151 if (ISA_HAS_LOAD_DELAY)
16153 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16154 trampoline[i++] = OP (MIPS_NOP);
16160 /* Copy the trampoline code. Leave any padding uninitialized. */
16161 for (j = 0; j < i; j++)
16163 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16164 mips_emit_move (mem, trampoline[j]);
16167 /* Set up the static chain pointer field. */
16168 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16169 mips_emit_move (mem, chain_value);
16171 /* Set up the target function field. */
16172 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16173 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16175 /* Flush the code part of the trampoline. */
16176 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16177 emit_insn (gen_clear_cache (addr, end_addr));
16180 /* Implement FUNCTION_PROFILER. */
16182 void mips_function_profiler (FILE *file)
16185 sorry ("mips16 function profiling");
16186 if (TARGET_LONG_CALLS)
16188 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16189 if (Pmode == DImode)
16190 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16192 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16194 mips_push_asm_switch (&mips_noat);
16195 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16196 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16197 /* _mcount treats $2 as the static chain register. */
16198 if (cfun->static_chain_decl != NULL)
16199 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16200 reg_names[STATIC_CHAIN_REGNUM]);
16201 if (TARGET_MCOUNT_RA_ADDRESS)
16203 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16204 ra save location. */
16205 if (cfun->machine->frame.ra_fp_offset == 0)
16206 /* ra not saved, pass zero. */
16207 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16209 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16210 Pmode == DImode ? "dla" : "la", reg_names[12],
16211 cfun->machine->frame.ra_fp_offset,
16212 reg_names[STACK_POINTER_REGNUM]);
16214 if (!TARGET_NEWABI)
16216 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16217 TARGET_64BIT ? "dsubu" : "subu",
16218 reg_names[STACK_POINTER_REGNUM],
16219 reg_names[STACK_POINTER_REGNUM],
16220 Pmode == DImode ? 16 : 8);
16222 if (TARGET_LONG_CALLS)
16223 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16225 fprintf (file, "\tjal\t_mcount\n");
16226 mips_pop_asm_switch (&mips_noat);
16227 /* _mcount treats $2 as the static chain register. */
16228 if (cfun->static_chain_decl != NULL)
16229 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16233 /* Initialize the GCC target structure. */
16234 #undef TARGET_ASM_ALIGNED_HI_OP
16235 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16236 #undef TARGET_ASM_ALIGNED_SI_OP
16237 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16238 #undef TARGET_ASM_ALIGNED_DI_OP
16239 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16241 #undef TARGET_LEGITIMIZE_ADDRESS
16242 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16244 #undef TARGET_ASM_FUNCTION_PROLOGUE
16245 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16246 #undef TARGET_ASM_FUNCTION_EPILOGUE
16247 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16248 #undef TARGET_ASM_SELECT_RTX_SECTION
16249 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16250 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16251 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16253 #undef TARGET_SCHED_INIT
16254 #define TARGET_SCHED_INIT mips_sched_init
16255 #undef TARGET_SCHED_REORDER
16256 #define TARGET_SCHED_REORDER mips_sched_reorder
16257 #undef TARGET_SCHED_REORDER2
16258 #define TARGET_SCHED_REORDER2 mips_sched_reorder
16259 #undef TARGET_SCHED_VARIABLE_ISSUE
16260 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16261 #undef TARGET_SCHED_ADJUST_COST
16262 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16263 #undef TARGET_SCHED_ISSUE_RATE
16264 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16265 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16266 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16267 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16268 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16269 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16270 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16271 mips_multipass_dfa_lookahead
16272 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16273 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16274 mips_small_register_classes_for_mode_p
16276 #undef TARGET_DEFAULT_TARGET_FLAGS
16277 #define TARGET_DEFAULT_TARGET_FLAGS \
16279 | TARGET_CPU_DEFAULT \
16280 | TARGET_ENDIAN_DEFAULT \
16281 | TARGET_FP_EXCEPTIONS_DEFAULT \
16282 | MASK_CHECK_ZERO_DIV \
16284 #undef TARGET_HANDLE_OPTION
16285 #define TARGET_HANDLE_OPTION mips_handle_option
16287 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16288 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16290 #undef TARGET_INSERT_ATTRIBUTES
16291 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16292 #undef TARGET_MERGE_DECL_ATTRIBUTES
16293 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16294 #undef TARGET_SET_CURRENT_FUNCTION
16295 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16297 #undef TARGET_VALID_POINTER_MODE
16298 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16299 #undef TARGET_RTX_COSTS
16300 #define TARGET_RTX_COSTS mips_rtx_costs
16301 #undef TARGET_ADDRESS_COST
16302 #define TARGET_ADDRESS_COST mips_address_cost
16304 #undef TARGET_IN_SMALL_DATA_P
16305 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16307 #undef TARGET_MACHINE_DEPENDENT_REORG
16308 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16310 #undef TARGET_ASM_FILE_START
16311 #define TARGET_ASM_FILE_START mips_file_start
16312 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16313 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16315 #undef TARGET_INIT_LIBFUNCS
16316 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16318 #undef TARGET_BUILD_BUILTIN_VA_LIST
16319 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16320 #undef TARGET_EXPAND_BUILTIN_VA_START
16321 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16322 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16323 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16325 #undef TARGET_PROMOTE_FUNCTION_MODE
16326 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16327 #undef TARGET_PROMOTE_PROTOTYPES
16328 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16330 #undef TARGET_RETURN_IN_MEMORY
16331 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16332 #undef TARGET_RETURN_IN_MSB
16333 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16335 #undef TARGET_ASM_OUTPUT_MI_THUNK
16336 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16337 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16338 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16340 #undef TARGET_SETUP_INCOMING_VARARGS
16341 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16342 #undef TARGET_STRICT_ARGUMENT_NAMING
16343 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16344 #undef TARGET_MUST_PASS_IN_STACK
16345 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16346 #undef TARGET_PASS_BY_REFERENCE
16347 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16348 #undef TARGET_CALLEE_COPIES
16349 #define TARGET_CALLEE_COPIES mips_callee_copies
16350 #undef TARGET_ARG_PARTIAL_BYTES
16351 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16353 #undef TARGET_MODE_REP_EXTENDED
16354 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16356 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16357 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16359 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16360 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16362 #undef TARGET_INIT_BUILTINS
16363 #define TARGET_INIT_BUILTINS mips_init_builtins
16364 #undef TARGET_EXPAND_BUILTIN
16365 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16367 #undef TARGET_HAVE_TLS
16368 #define TARGET_HAVE_TLS HAVE_AS_TLS
16370 #undef TARGET_CANNOT_FORCE_CONST_MEM
16371 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16373 #undef TARGET_ENCODE_SECTION_INFO
16374 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16376 #undef TARGET_ATTRIBUTE_TABLE
16377 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16378 /* All our function attributes are related to how out-of-line copies should
16379 be compiled or called. They don't in themselves prevent inlining. */
16380 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16381 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16383 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16384 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16386 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16387 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16388 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16389 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16391 #undef TARGET_COMP_TYPE_ATTRIBUTES
16392 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16394 #ifdef HAVE_AS_DTPRELWORD
16395 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16396 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16398 #undef TARGET_DWARF_REGISTER_SPAN
16399 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16401 #undef TARGET_IRA_COVER_CLASSES
16402 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16404 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16405 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16407 #undef TARGET_LEGITIMATE_ADDRESS_P
16408 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16410 #undef TARGET_FRAME_POINTER_REQUIRED
16411 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16413 #undef TARGET_CAN_ELIMINATE
16414 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16416 #undef TARGET_TRAMPOLINE_INIT
16417 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16419 struct gcc_target targetm = TARGET_INITIALIZER;
16421 #include "gt-mips.h"