1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
278 static int mips_symbol_insns (enum mips_symbol_type);
279 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
280 static rtx mips_force_temporary (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static section *mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static section *mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static bool mips_use_anchors_for_symbol_p (rtx);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
412 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
414 /* Structure to be filled in by compute_frame_size with register
415 save masks, and offsets for the current function. */
417 struct mips_frame_info GTY(())
419 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
420 HOST_WIDE_INT var_size; /* # bytes that variables take up */
421 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
422 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
423 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
424 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
425 unsigned int mask; /* mask of saved gp registers */
426 unsigned int fmask; /* mask of saved fp registers */
427 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
428 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
429 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
430 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
431 bool initialized; /* true if frame size already calculated */
432 int num_gp; /* number of gp registers saved */
433 int num_fp; /* number of fp registers saved */
436 struct machine_function GTY(()) {
437 /* Pseudo-reg holding the value of $28 in a mips16 function which
438 refers to GP relative global variables. */
439 rtx mips16_gp_pseudo_rtx;
441 /* The number of extra stack bytes taken up by register varargs.
442 This area is allocated by the callee at the very top of the frame. */
445 /* Current frame information, calculated by compute_frame_size. */
446 struct mips_frame_info frame;
448 /* The register to use as the global pointer within this function. */
449 unsigned int global_pointer;
451 /* True if mips_adjust_insn_length should ignore an instruction's
453 bool ignore_hazard_length_p;
455 /* True if the whole function is suitable for .set noreorder and
457 bool all_noreorder_p;
459 /* True if the function is known to have an instruction that needs $gp. */
463 /* Information about a single argument. */
466 /* True if the argument is passed in a floating-point register, or
467 would have been if we hadn't run out of registers. */
470 /* The number of words passed in registers, rounded up. */
471 unsigned int reg_words;
473 /* For EABI, the offset of the first register from GP_ARG_FIRST or
474 FP_ARG_FIRST. For other ABIs, the offset of the first register from
475 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
476 comment for details).
478 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
480 unsigned int reg_offset;
482 /* The number of words that must be passed on the stack, rounded up. */
483 unsigned int stack_words;
485 /* The offset from the start of the stack overflow area of the argument's
486 first stack word. Only meaningful when STACK_WORDS is nonzero. */
487 unsigned int stack_offset;
491 /* Information about an address described by mips_address_type.
497 REG is the base register and OFFSET is the constant offset.
500 REG is the register that contains the high part of the address,
501 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
502 is the type of OFFSET's symbol.
505 SYMBOL_TYPE is the type of symbol being referenced. */
507 struct mips_address_info
509 enum mips_address_type type;
512 enum mips_symbol_type symbol_type;
516 /* One stage in a constant building sequence. These sequences have
520 A = A CODE[1] VALUE[1]
521 A = A CODE[2] VALUE[2]
524 where A is an accumulator, each CODE[i] is a binary rtl operation
525 and each VALUE[i] is a constant integer. */
526 struct mips_integer_op {
528 unsigned HOST_WIDE_INT value;
532 /* The largest number of operations needed to load an integer constant.
533 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
534 When the lowest bit is clear, we can try, but reject a sequence with
535 an extra SLL at the end. */
536 #define MIPS_MAX_INTEGER_OPS 7
539 /* Global variables for machine-dependent things. */
541 /* Threshold for data being put into the small data/bss area, instead
542 of the normal data area. */
543 int mips_section_threshold = -1;
545 /* Count the number of .file directives, so that .loc is up to date. */
546 int num_source_filenames = 0;
548 /* Count the number of sdb related labels are generated (to find block
549 start and end boundaries). */
550 int sdb_label_count = 0;
552 /* Next label # for each statement for Silicon Graphics IRIS systems. */
555 /* Linked list of all externals that are to be emitted when optimizing
556 for the global pointer if they haven't been declared by the end of
557 the program with an appropriate .comm or initialization. */
559 struct extern_list GTY (())
561 struct extern_list *next; /* next external */
562 const char *name; /* name of the external */
563 int size; /* size in bytes */
566 static GTY (()) struct extern_list *extern_head = 0;
568 /* Name of the file containing the current function. */
569 const char *current_function_file = "";
571 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
577 /* The next branch instruction is a branch likely, not branch normal. */
578 int mips_branch_likely;
580 /* The operands passed to the last cmpMM expander. */
583 /* The target cpu for code generation. */
584 enum processor_type mips_arch;
585 const struct mips_cpu_info *mips_arch_info;
587 /* The target cpu for optimization and scheduling. */
588 enum processor_type mips_tune;
589 const struct mips_cpu_info *mips_tune_info;
591 /* Which instruction set architecture to use. */
594 /* Which ABI to use. */
595 int mips_abi = MIPS_ABI_DEFAULT;
597 /* Cost information to use. */
598 const struct mips_rtx_cost_data *mips_cost;
600 /* Whether we are generating mips16 hard float code. In mips16 mode
601 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
602 -msoft-float was not specified by the user, which means that we
603 should arrange to call mips32 hard floating point code. */
604 int mips16_hard_float;
606 /* The architecture selected by -mipsN. */
607 static const struct mips_cpu_info *mips_isa_info;
609 /* If TRUE, we split addresses into their high and low parts in the RTL. */
610 int mips_split_addresses;
612 /* Mode used for saving/restoring general purpose registers. */
613 static enum machine_mode gpr_mode;
615 /* Array giving truth value on whether or not a given hard register
616 can support a given mode. */
617 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
619 /* List of all MIPS punctuation characters used by print_operand. */
620 char mips_print_operand_punct[256];
622 /* Map GCC register number to debugger register number. */
623 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
625 /* A copy of the original flag_delayed_branch: see override_options. */
626 static int mips_flag_delayed_branch;
628 static GTY (()) int mips_output_filename_first_time = 1;
630 /* mips_split_p[X] is true if symbols of type X can be split by
631 mips_split_symbol(). */
632 bool mips_split_p[NUM_SYMBOL_TYPES];
634 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
635 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
636 if they are matched by a special .md file pattern. */
637 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
639 /* Likewise for HIGHs. */
640 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
642 /* Map hard register number to register class */
643 const enum reg_class mips_regno_to_class[] =
645 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
646 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
649 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
650 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
651 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
652 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 HI_REG, LO_REG, NO_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
663 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
664 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
690 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
691 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "24k", PROCESSOR_24K, 33 },
753 { "24kc", PROCESSOR_24K, 33 }, /* 24K no FPU */
754 { "24kf", PROCESSOR_24K, 33 }, /* 24K 1:2 FPU */
755 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "5kc", PROCESSOR_5KC, 64 },
759 { "5kf", PROCESSOR_5KF, 64 },
760 { "20kc", PROCESSOR_20KC, 64 },
761 { "sb1", PROCESSOR_SB1, 64 },
762 { "sb1a", PROCESSOR_SB1A, 64 },
763 { "sr71000", PROCESSOR_SR71000, 64 },
769 /* Default costs. If these are used for a processor we should look
770 up the actual costs. */
771 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
772 COSTS_N_INSNS (7), /* fp_mult_sf */ \
773 COSTS_N_INSNS (8), /* fp_mult_df */ \
774 COSTS_N_INSNS (23), /* fp_div_sf */ \
775 COSTS_N_INSNS (36), /* fp_div_df */ \
776 COSTS_N_INSNS (10), /* int_mult_si */ \
777 COSTS_N_INSNS (10), /* int_mult_di */ \
778 COSTS_N_INSNS (69), /* int_div_si */ \
779 COSTS_N_INSNS (69), /* int_div_di */ \
780 2, /* branch_cost */ \
781 4 /* memory_latency */
783 /* Need to replace these with the costs of calling the appropriate
785 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
786 COSTS_N_INSNS (256), /* fp_mult_sf */ \
787 COSTS_N_INSNS (256), /* fp_mult_df */ \
788 COSTS_N_INSNS (256), /* fp_div_sf */ \
789 COSTS_N_INSNS (256) /* fp_div_df */
791 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
794 COSTS_N_INSNS (2), /* fp_add */
795 COSTS_N_INSNS (4), /* fp_mult_sf */
796 COSTS_N_INSNS (5), /* fp_mult_df */
797 COSTS_N_INSNS (12), /* fp_div_sf */
798 COSTS_N_INSNS (19), /* fp_div_df */
799 COSTS_N_INSNS (12), /* int_mult_si */
800 COSTS_N_INSNS (12), /* int_mult_di */
801 COSTS_N_INSNS (35), /* int_div_si */
802 COSTS_N_INSNS (35), /* int_div_di */
804 4 /* memory_latency */
809 COSTS_N_INSNS (6), /* int_mult_si */
810 COSTS_N_INSNS (6), /* int_mult_di */
811 COSTS_N_INSNS (36), /* int_div_si */
812 COSTS_N_INSNS (36), /* int_div_di */
814 4 /* memory_latency */
818 COSTS_N_INSNS (36), /* int_mult_si */
819 COSTS_N_INSNS (36), /* int_mult_di */
820 COSTS_N_INSNS (37), /* int_div_si */
821 COSTS_N_INSNS (37), /* int_div_di */
823 4 /* memory_latency */
827 COSTS_N_INSNS (4), /* int_mult_si */
828 COSTS_N_INSNS (11), /* int_mult_di */
829 COSTS_N_INSNS (36), /* int_div_si */
830 COSTS_N_INSNS (68), /* int_div_di */
832 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* fp_add */
836 COSTS_N_INSNS (4), /* fp_mult_sf */
837 COSTS_N_INSNS (5), /* fp_mult_df */
838 COSTS_N_INSNS (17), /* fp_div_sf */
839 COSTS_N_INSNS (32), /* fp_div_df */
840 COSTS_N_INSNS (4), /* int_mult_si */
841 COSTS_N_INSNS (11), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (68), /* int_div_di */
845 4 /* memory_latency */
851 COSTS_N_INSNS (8), /* fp_add */
852 COSTS_N_INSNS (8), /* fp_mult_sf */
853 COSTS_N_INSNS (10), /* fp_mult_df */
854 COSTS_N_INSNS (34), /* fp_div_sf */
855 COSTS_N_INSNS (64), /* fp_div_df */
856 COSTS_N_INSNS (5), /* int_mult_si */
857 COSTS_N_INSNS (5), /* int_mult_di */
858 COSTS_N_INSNS (41), /* int_div_si */
859 COSTS_N_INSNS (41), /* int_div_di */
861 4 /* memory_latency */
864 COSTS_N_INSNS (4), /* fp_add */
865 COSTS_N_INSNS (4), /* fp_mult_sf */
866 COSTS_N_INSNS (5), /* fp_mult_df */
867 COSTS_N_INSNS (17), /* fp_div_sf */
868 COSTS_N_INSNS (32), /* fp_div_df */
869 COSTS_N_INSNS (5), /* int_mult_si */
870 COSTS_N_INSNS (5), /* int_mult_di */
871 COSTS_N_INSNS (41), /* int_div_si */
872 COSTS_N_INSNS (41), /* int_div_di */
874 4 /* memory_latency */
880 COSTS_N_INSNS (2), /* fp_add */
881 COSTS_N_INSNS (4), /* fp_mult_sf */
882 COSTS_N_INSNS (5), /* fp_mult_df */
883 COSTS_N_INSNS (12), /* fp_div_sf */
884 COSTS_N_INSNS (19), /* fp_div_df */
885 COSTS_N_INSNS (2), /* int_mult_si */
886 COSTS_N_INSNS (2), /* int_mult_di */
887 COSTS_N_INSNS (35), /* int_div_si */
888 COSTS_N_INSNS (35), /* int_div_di */
890 4 /* memory_latency */
893 COSTS_N_INSNS (3), /* fp_add */
894 COSTS_N_INSNS (5), /* fp_mult_sf */
895 COSTS_N_INSNS (6), /* fp_mult_df */
896 COSTS_N_INSNS (15), /* fp_div_sf */
897 COSTS_N_INSNS (16), /* fp_div_df */
898 COSTS_N_INSNS (17), /* int_mult_si */
899 COSTS_N_INSNS (17), /* int_mult_di */
900 COSTS_N_INSNS (38), /* int_div_si */
901 COSTS_N_INSNS (38), /* int_div_di */
903 6 /* memory_latency */
906 COSTS_N_INSNS (6), /* fp_add */
907 COSTS_N_INSNS (7), /* fp_mult_sf */
908 COSTS_N_INSNS (8), /* fp_mult_df */
909 COSTS_N_INSNS (23), /* fp_div_sf */
910 COSTS_N_INSNS (36), /* fp_div_df */
911 COSTS_N_INSNS (10), /* int_mult_si */
912 COSTS_N_INSNS (10), /* int_mult_di */
913 COSTS_N_INSNS (69), /* int_div_si */
914 COSTS_N_INSNS (69), /* int_div_di */
916 6 /* memory_latency */
928 /* The only costs that appear to be updated here are
929 integer multiplication. */
931 COSTS_N_INSNS (4), /* int_mult_si */
932 COSTS_N_INSNS (6), /* int_mult_di */
933 COSTS_N_INSNS (69), /* int_div_si */
934 COSTS_N_INSNS (69), /* int_div_di */
936 4 /* memory_latency */
948 COSTS_N_INSNS (6), /* fp_add */
949 COSTS_N_INSNS (4), /* fp_mult_sf */
950 COSTS_N_INSNS (5), /* fp_mult_df */
951 COSTS_N_INSNS (23), /* fp_div_sf */
952 COSTS_N_INSNS (36), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (5), /* int_mult_di */
955 COSTS_N_INSNS (36), /* int_div_si */
956 COSTS_N_INSNS (36), /* int_div_di */
958 4 /* memory_latency */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (5), /* fp_mult_sf */
963 COSTS_N_INSNS (6), /* fp_mult_df */
964 COSTS_N_INSNS (30), /* fp_div_sf */
965 COSTS_N_INSNS (59), /* fp_div_df */
966 COSTS_N_INSNS (3), /* int_mult_si */
967 COSTS_N_INSNS (4), /* int_mult_di */
968 COSTS_N_INSNS (42), /* int_div_si */
969 COSTS_N_INSNS (74), /* int_div_di */
971 4 /* memory_latency */
974 COSTS_N_INSNS (6), /* fp_add */
975 COSTS_N_INSNS (5), /* fp_mult_sf */
976 COSTS_N_INSNS (6), /* fp_mult_df */
977 COSTS_N_INSNS (30), /* fp_div_sf */
978 COSTS_N_INSNS (59), /* fp_div_df */
979 COSTS_N_INSNS (5), /* int_mult_si */
980 COSTS_N_INSNS (9), /* int_mult_di */
981 COSTS_N_INSNS (42), /* int_div_si */
982 COSTS_N_INSNS (74), /* int_div_di */
984 4 /* memory_latency */
987 /* The only costs that are changed here are
988 integer multiplication. */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (7), /* fp_mult_sf */
991 COSTS_N_INSNS (8), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (5), /* int_mult_si */
995 COSTS_N_INSNS (9), /* int_mult_di */
996 COSTS_N_INSNS (69), /* int_div_si */
997 COSTS_N_INSNS (69), /* int_div_di */
999 4 /* memory_latency */
1005 /* The only costs that are changed here are
1006 integer multiplication. */
1007 COSTS_N_INSNS (6), /* fp_add */
1008 COSTS_N_INSNS (7), /* fp_mult_sf */
1009 COSTS_N_INSNS (8), /* fp_mult_df */
1010 COSTS_N_INSNS (23), /* fp_div_sf */
1011 COSTS_N_INSNS (36), /* fp_div_df */
1012 COSTS_N_INSNS (3), /* int_mult_si */
1013 COSTS_N_INSNS (8), /* int_mult_di */
1014 COSTS_N_INSNS (69), /* int_div_si */
1015 COSTS_N_INSNS (69), /* int_div_di */
1016 1, /* branch_cost */
1017 4 /* memory_latency */
1020 /* These costs are the same as the SB-1A below. */
1021 COSTS_N_INSNS (4), /* fp_add */
1022 COSTS_N_INSNS (4), /* fp_mult_sf */
1023 COSTS_N_INSNS (4), /* fp_mult_df */
1024 COSTS_N_INSNS (24), /* fp_div_sf */
1025 COSTS_N_INSNS (32), /* fp_div_df */
1026 COSTS_N_INSNS (3), /* int_mult_si */
1027 COSTS_N_INSNS (4), /* int_mult_di */
1028 COSTS_N_INSNS (36), /* int_div_si */
1029 COSTS_N_INSNS (68), /* int_div_di */
1030 1, /* branch_cost */
1031 4 /* memory_latency */
1034 /* These costs are the same as the SB-1 above. */
1035 COSTS_N_INSNS (4), /* fp_add */
1036 COSTS_N_INSNS (4), /* fp_mult_sf */
1037 COSTS_N_INSNS (4), /* fp_mult_df */
1038 COSTS_N_INSNS (24), /* fp_div_sf */
1039 COSTS_N_INSNS (32), /* fp_div_df */
1040 COSTS_N_INSNS (3), /* int_mult_si */
1041 COSTS_N_INSNS (4), /* int_mult_di */
1042 COSTS_N_INSNS (36), /* int_div_si */
1043 COSTS_N_INSNS (68), /* int_div_di */
1044 1, /* branch_cost */
1045 4 /* memory_latency */
1053 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1054 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1055 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1058 /* Initialize the GCC target structure. */
1059 #undef TARGET_ASM_ALIGNED_HI_OP
1060 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1061 #undef TARGET_ASM_ALIGNED_SI_OP
1062 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1063 #undef TARGET_ASM_ALIGNED_DI_OP
1064 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1066 #undef TARGET_ASM_FUNCTION_PROLOGUE
1067 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1068 #undef TARGET_ASM_FUNCTION_EPILOGUE
1069 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1070 #undef TARGET_ASM_SELECT_RTX_SECTION
1071 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1072 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1073 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1075 #undef TARGET_SCHED_REORDER
1076 #define TARGET_SCHED_REORDER mips_sched_reorder
1077 #undef TARGET_SCHED_VARIABLE_ISSUE
1078 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1079 #undef TARGET_SCHED_ADJUST_COST
1080 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1081 #undef TARGET_SCHED_ISSUE_RATE
1082 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1083 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1084 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1085 mips_multipass_dfa_lookahead
1087 #undef TARGET_DEFAULT_TARGET_FLAGS
1088 #define TARGET_DEFAULT_TARGET_FLAGS \
1090 | TARGET_CPU_DEFAULT \
1091 | TARGET_ENDIAN_DEFAULT \
1092 | TARGET_FP_EXCEPTIONS_DEFAULT \
1093 | MASK_CHECK_ZERO_DIV \
1095 #undef TARGET_HANDLE_OPTION
1096 #define TARGET_HANDLE_OPTION mips_handle_option
1098 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1099 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1101 #undef TARGET_VALID_POINTER_MODE
1102 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1103 #undef TARGET_RTX_COSTS
1104 #define TARGET_RTX_COSTS mips_rtx_costs
1105 #undef TARGET_ADDRESS_COST
1106 #define TARGET_ADDRESS_COST mips_address_cost
1108 #undef TARGET_IN_SMALL_DATA_P
1109 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1111 #undef TARGET_MACHINE_DEPENDENT_REORG
1112 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1114 #undef TARGET_ASM_FILE_START
1115 #undef TARGET_ASM_FILE_END
1116 #define TARGET_ASM_FILE_START mips_file_start
1117 #define TARGET_ASM_FILE_END mips_file_end
1118 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1119 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1121 #undef TARGET_INIT_LIBFUNCS
1122 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1124 #undef TARGET_BUILD_BUILTIN_VA_LIST
1125 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1126 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1127 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1129 #undef TARGET_PROMOTE_FUNCTION_ARGS
1130 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1131 #undef TARGET_PROMOTE_FUNCTION_RETURN
1132 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1133 #undef TARGET_PROMOTE_PROTOTYPES
1134 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1136 #undef TARGET_RETURN_IN_MEMORY
1137 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1138 #undef TARGET_RETURN_IN_MSB
1139 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1141 #undef TARGET_ASM_OUTPUT_MI_THUNK
1142 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1143 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1144 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1146 #undef TARGET_SETUP_INCOMING_VARARGS
1147 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1148 #undef TARGET_STRICT_ARGUMENT_NAMING
1149 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1150 #undef TARGET_MUST_PASS_IN_STACK
1151 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1152 #undef TARGET_PASS_BY_REFERENCE
1153 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1154 #undef TARGET_CALLEE_COPIES
1155 #define TARGET_CALLEE_COPIES mips_callee_copies
1156 #undef TARGET_ARG_PARTIAL_BYTES
1157 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1159 #undef TARGET_MODE_REP_EXTENDED
1160 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1162 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1163 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1165 #undef TARGET_INIT_BUILTINS
1166 #define TARGET_INIT_BUILTINS mips_init_builtins
1167 #undef TARGET_EXPAND_BUILTIN
1168 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1170 #undef TARGET_HAVE_TLS
1171 #define TARGET_HAVE_TLS HAVE_AS_TLS
1173 #undef TARGET_CANNOT_FORCE_CONST_MEM
1174 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1176 #undef TARGET_ENCODE_SECTION_INFO
1177 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1179 #undef TARGET_ATTRIBUTE_TABLE
1180 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1182 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1183 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1185 #undef TARGET_MIN_ANCHOR_OFFSET
1186 #define TARGET_MIN_ANCHOR_OFFSET -32768
1187 #undef TARGET_MAX_ANCHOR_OFFSET
1188 #define TARGET_MAX_ANCHOR_OFFSET 32767
1189 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1190 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1191 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1192 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1194 struct gcc_target targetm = TARGET_INITIALIZER;
1196 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1198 static enum mips_symbol_type
1199 mips_classify_symbol (rtx x)
1201 if (GET_CODE (x) == LABEL_REF)
1204 return SYMBOL_CONSTANT_POOL;
1205 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1206 return SYMBOL_GOT_LOCAL;
1207 return SYMBOL_GENERAL;
1210 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1212 if (SYMBOL_REF_TLS_MODEL (x))
1215 if (CONSTANT_POOL_ADDRESS_P (x))
1218 return SYMBOL_CONSTANT_POOL;
1220 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1221 return SYMBOL_SMALL_DATA;
1224 if (SYMBOL_REF_SMALL_P (x))
1225 return SYMBOL_SMALL_DATA;
1227 if (TARGET_ABICALLS)
1229 if (SYMBOL_REF_DECL (x) == 0)
1231 if (!SYMBOL_REF_LOCAL_P (x))
1232 return SYMBOL_GOT_GLOBAL;
1236 /* Don't use GOT accesses for locally-binding symbols if
1237 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1240 - o32 PIC (either with or without explicit relocs)
1241 - n32/n64 PIC without explicit relocs
1242 - n32/n64 PIC with explicit relocs
1244 In the first case, both local and global accesses will use an
1245 R_MIPS_GOT16 relocation. We must correctly predict which of
1246 the two semantics (local or global) the assembler and linker
1247 will apply. The choice doesn't depend on the symbol's
1248 visibility, so we deliberately ignore decl_visibility and
1251 In the second case, the assembler will not use R_MIPS_GOT16
1252 relocations, but it chooses between local and global accesses
1253 in the same way as for o32 PIC.
1255 In the third case we have more freedom since both forms of
1256 access will work for any kind of symbol. However, there seems
1257 little point in doing things differently. */
1258 if (DECL_P (SYMBOL_REF_DECL (x))
1259 && TREE_PUBLIC (SYMBOL_REF_DECL (x))
1260 && !(TARGET_ABSOLUTE_ABICALLS
1261 && targetm.binds_local_p (SYMBOL_REF_DECL (x))))
1262 return SYMBOL_GOT_GLOBAL;
1265 if (!TARGET_ABSOLUTE_ABICALLS)
1266 return SYMBOL_GOT_LOCAL;
1269 return SYMBOL_GENERAL;
1273 /* Split X into a base and a constant offset, storing them in *BASE
1274 and *OFFSET respectively. */
1277 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1281 if (GET_CODE (x) == CONST)
1284 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1286 *offset += INTVAL (XEXP (x, 1));
1293 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1294 to the same object as SYMBOL, or to the same object_block. */
1297 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1299 if (GET_CODE (symbol) != SYMBOL_REF)
1302 if (CONSTANT_POOL_ADDRESS_P (symbol)
1304 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1307 if (SYMBOL_REF_DECL (symbol) != 0
1309 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1312 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1313 && SYMBOL_REF_BLOCK (symbol)
1314 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1315 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1316 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1323 /* Return true if X is a symbolic constant that can be calculated in
1324 the same way as a bare symbol. If it is, store the type of the
1325 symbol in *SYMBOL_TYPE. */
1328 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1330 HOST_WIDE_INT offset;
1332 mips_split_const (x, &x, &offset);
1333 if (UNSPEC_ADDRESS_P (x))
1334 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1335 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1337 *symbol_type = mips_classify_symbol (x);
1338 if (*symbol_type == SYMBOL_TLS)
1347 /* Check whether a nonzero offset is valid for the underlying
1349 switch (*symbol_type)
1351 case SYMBOL_GENERAL:
1352 case SYMBOL_64_HIGH:
1355 /* If the target has 64-bit pointers and the object file only
1356 supports 32-bit symbols, the values of those symbols will be
1357 sign-extended. In this case we can't allow an arbitrary offset
1358 in case the 32-bit value X + OFFSET has a different sign from X. */
1359 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1360 return mips_offset_within_object_p (x, offset);
1362 /* In other cases the relocations can handle any offset. */
1365 case SYMBOL_CONSTANT_POOL:
1366 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1367 In this case, we no longer have access to the underlying constant,
1368 but the original symbol-based access was known to be valid. */
1369 if (GET_CODE (x) == LABEL_REF)
1374 case SYMBOL_SMALL_DATA:
1375 /* Make sure that the offset refers to something within the
1376 underlying object. This should guarantee that the final
1377 PC- or GP-relative offset is within the 16-bit limit. */
1378 return mips_offset_within_object_p (x, offset);
1380 case SYMBOL_GOT_LOCAL:
1381 case SYMBOL_GOTOFF_PAGE:
1382 /* The linker should provide enough local GOT entries for a
1383 16-bit offset. Larger offsets may lead to GOT overflow. */
1384 return SMALL_OPERAND (offset);
1386 case SYMBOL_GOT_GLOBAL:
1387 case SYMBOL_GOTOFF_GLOBAL:
1388 case SYMBOL_GOTOFF_CALL:
1389 case SYMBOL_GOTOFF_LOADGP:
1394 case SYMBOL_GOTTPREL:
1402 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1405 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1407 if (regno >= FIRST_PSEUDO_REGISTER)
1411 regno = reg_renumber[regno];
1414 /* These fake registers will be eliminated to either the stack or
1415 hard frame pointer, both of which are usually valid base registers.
1416 Reload deals with the cases where the eliminated form isn't valid. */
1417 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1420 /* In mips16 mode, the stack pointer can only address word and doubleword
1421 values, nothing smaller. There are two problems here:
1423 (a) Instantiating virtual registers can introduce new uses of the
1424 stack pointer. If these virtual registers are valid addresses,
1425 the stack pointer should be too.
1427 (b) Most uses of the stack pointer are not made explicit until
1428 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1429 We don't know until that stage whether we'll be eliminating to the
1430 stack pointer (which needs the restriction) or the hard frame
1431 pointer (which doesn't).
1433 All in all, it seems more consistent to only enforce this restriction
1434 during and after reload. */
1435 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1436 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1438 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1442 /* Return true if X is a valid base register for the given mode.
1443 Allow only hard registers if STRICT. */
1446 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1448 if (!strict && GET_CODE (x) == SUBREG)
1452 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1456 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1457 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1460 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1461 enum machine_mode mode)
1463 switch (symbol_type)
1465 case SYMBOL_GENERAL:
1466 return !TARGET_MIPS16;
1468 case SYMBOL_SMALL_DATA:
1471 case SYMBOL_CONSTANT_POOL:
1472 /* PC-relative addressing is only available for lw and ld. */
1473 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1475 case SYMBOL_GOT_LOCAL:
1478 case SYMBOL_GOT_GLOBAL:
1479 /* The address will have to be loaded from the GOT first. */
1482 case SYMBOL_GOTOFF_PAGE:
1483 case SYMBOL_GOTOFF_GLOBAL:
1484 case SYMBOL_GOTOFF_CALL:
1485 case SYMBOL_GOTOFF_LOADGP:
1490 case SYMBOL_GOTTPREL:
1492 case SYMBOL_64_HIGH:
1501 /* Return true if X is a valid address for machine mode MODE. If it is,
1502 fill in INFO appropriately. STRICT is true if we should only accept
1503 hard base registers. */
1506 mips_classify_address (struct mips_address_info *info, rtx x,
1507 enum machine_mode mode, int strict)
1509 switch (GET_CODE (x))
1513 info->type = ADDRESS_REG;
1515 info->offset = const0_rtx;
1516 return mips_valid_base_register_p (info->reg, mode, strict);
1519 info->type = ADDRESS_REG;
1520 info->reg = XEXP (x, 0);
1521 info->offset = XEXP (x, 1);
1522 return (mips_valid_base_register_p (info->reg, mode, strict)
1523 && const_arith_operand (info->offset, VOIDmode));
1526 info->type = ADDRESS_LO_SUM;
1527 info->reg = XEXP (x, 0);
1528 info->offset = XEXP (x, 1);
1529 return (mips_valid_base_register_p (info->reg, mode, strict)
1530 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1531 && mips_symbolic_address_p (info->symbol_type, mode)
1532 && mips_lo_relocs[info->symbol_type] != 0);
1535 /* Small-integer addresses don't occur very often, but they
1536 are legitimate if $0 is a valid base register. */
1537 info->type = ADDRESS_CONST_INT;
1538 return !TARGET_MIPS16 && SMALL_INT (x);
1543 info->type = ADDRESS_SYMBOLIC;
1544 return (mips_symbolic_constant_p (x, &info->symbol_type)
1545 && mips_symbolic_address_p (info->symbol_type, mode)
1546 && !mips_split_p[info->symbol_type]);
1553 /* Return true if X is a thread-local symbol. */
1556 mips_tls_operand_p (rtx x)
1558 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1561 /* Return true if X can not be forced into a constant pool. */
1564 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1566 return mips_tls_operand_p (*x);
1569 /* Return true if X can not be forced into a constant pool. */
1572 mips_cannot_force_const_mem (rtx x)
1575 HOST_WIDE_INT offset;
1579 /* As an optimization, reject constants that mips_legitimize_move
1582 Suppose we have a multi-instruction sequence that loads constant C
1583 into register R. If R does not get allocated a hard register, and
1584 R is used in an operand that allows both registers and memory
1585 references, reload will consider forcing C into memory and using
1586 one of the instruction's memory alternatives. Returning false
1587 here will force it to use an input reload instead. */
1588 if (GET_CODE (x) == CONST_INT)
1591 mips_split_const (x, &base, &offset);
1592 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1596 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1602 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1603 constant pools, but normal-mode code doesn't need to. */
1606 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1607 rtx x ATTRIBUTE_UNUSED)
1609 return !TARGET_MIPS16;
1612 /* Return the number of instructions needed to load a symbol of the
1613 given type into a register. If valid in an address, the same number
1614 of instructions are needed for loads and stores. Treat extended
1615 mips16 instructions as two instructions. */
1618 mips_symbol_insns (enum mips_symbol_type type)
1622 case SYMBOL_GENERAL:
1623 /* In mips16 code, general symbols must be fetched from the
1628 /* When using 64-bit symbols, we need 5 preparatory instructions,
1631 lui $at,%highest(symbol)
1632 daddiu $at,$at,%higher(symbol)
1634 daddiu $at,$at,%hi(symbol)
1637 The final address is then $at + %lo(symbol). With 32-bit
1638 symbols we just need a preparatory lui. */
1639 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1641 case SYMBOL_SMALL_DATA:
1644 case SYMBOL_CONSTANT_POOL:
1645 /* This case is for mips16 only. Assume we'll need an
1646 extended instruction. */
1649 case SYMBOL_GOT_LOCAL:
1650 case SYMBOL_GOT_GLOBAL:
1651 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1652 the local/global classification is accurate. See override_options
1655 The worst cases are:
1657 (1) For local symbols when generating o32 or o64 code. The assembler
1663 ...and the final address will be $at + %lo(symbol).
1665 (2) For global symbols when -mxgot. The assembler will use:
1667 lui $at,%got_hi(symbol)
1670 ...and the final address will be $at + %got_lo(symbol). */
1673 case SYMBOL_GOTOFF_PAGE:
1674 case SYMBOL_GOTOFF_GLOBAL:
1675 case SYMBOL_GOTOFF_CALL:
1676 case SYMBOL_GOTOFF_LOADGP:
1677 case SYMBOL_64_HIGH:
1683 case SYMBOL_GOTTPREL:
1685 /* Check whether the offset is a 16- or 32-bit value. */
1686 return mips_split_p[type] ? 2 : 1;
1689 /* We don't treat a bare TLS symbol as a constant. */
1695 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1698 mips_stack_address_p (rtx x, enum machine_mode mode)
1700 struct mips_address_info addr;
1702 return (mips_classify_address (&addr, x, mode, false)
1703 && addr.type == ADDRESS_REG
1704 && addr.reg == stack_pointer_rtx);
1707 /* Return true if a value at OFFSET bytes from BASE can be accessed
1708 using an unextended mips16 instruction. MODE is the mode of the
1711 Usually the offset in an unextended instruction is a 5-bit field.
1712 The offset is unsigned and shifted left once for HIs, twice
1713 for SIs, and so on. An exception is SImode accesses off the
1714 stack pointer, which have an 8-bit immediate field. */
1717 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1720 && GET_CODE (offset) == CONST_INT
1721 && INTVAL (offset) >= 0
1722 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1724 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1725 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1726 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1732 /* Return the number of instructions needed to load or store a value
1733 of mode MODE at X. Return 0 if X isn't valid for MODE.
1735 For mips16 code, count extended instructions as two instructions. */
1738 mips_address_insns (rtx x, enum machine_mode mode)
1740 struct mips_address_info addr;
1743 if (mode == BLKmode)
1744 /* BLKmode is used for single unaligned loads and stores. */
1747 /* Each word of a multi-word value will be accessed individually. */
1748 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1750 if (mips_classify_address (&addr, x, mode, false))
1755 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1759 case ADDRESS_LO_SUM:
1760 return (TARGET_MIPS16 ? factor * 2 : factor);
1762 case ADDRESS_CONST_INT:
1765 case ADDRESS_SYMBOLIC:
1766 return factor * mips_symbol_insns (addr.symbol_type);
1772 /* Likewise for constant X. */
1775 mips_const_insns (rtx x)
1777 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1778 enum mips_symbol_type symbol_type;
1779 HOST_WIDE_INT offset;
1781 switch (GET_CODE (x))
1785 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1786 || !mips_split_p[symbol_type])
1793 /* Unsigned 8-bit constants can be loaded using an unextended
1794 LI instruction. Unsigned 16-bit constants can be loaded
1795 using an extended LI. Negative constants must be loaded
1796 using LI and then negated. */
1797 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1798 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1799 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1800 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1803 return mips_build_integer (codes, INTVAL (x));
1807 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1813 /* See if we can refer to X directly. */
1814 if (mips_symbolic_constant_p (x, &symbol_type))
1815 return mips_symbol_insns (symbol_type);
1817 /* Otherwise try splitting the constant into a base and offset.
1818 16-bit offsets can be added using an extra addiu. Larger offsets
1819 must be calculated separately and then added to the base. */
1820 mips_split_const (x, &x, &offset);
1823 int n = mips_const_insns (x);
1826 if (SMALL_OPERAND (offset))
1829 return n + 1 + mips_build_integer (codes, offset);
1836 return mips_symbol_insns (mips_classify_symbol (x));
1844 /* Return the number of instructions needed for memory reference X.
1845 Count extended mips16 instructions as two instructions. */
1848 mips_fetch_insns (rtx x)
1850 gcc_assert (MEM_P (x));
1851 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1855 /* Return the number of instructions needed for an integer division. */
1858 mips_idiv_insns (void)
1863 if (TARGET_CHECK_ZERO_DIV)
1865 if (GENERATE_DIVIDE_TRAPS)
1871 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1876 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1877 returns a nonzero value if X is a legitimate address for a memory
1878 operand of the indicated MODE. STRICT is nonzero if this function
1879 is called during reload. */
1882 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1884 struct mips_address_info addr;
1886 return mips_classify_address (&addr, x, mode, strict);
1890 /* Copy VALUE to a register and return that register. If new psuedos
1891 are allowed, copy it into a new register, otherwise use DEST. */
1894 mips_force_temporary (rtx dest, rtx value)
1896 if (!no_new_pseudos)
1897 return force_reg (Pmode, value);
1900 emit_move_insn (copy_rtx (dest), value);
1906 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1907 and is used to load the high part into a register. */
1910 mips_split_symbol (rtx temp, rtx addr)
1915 high = mips16_gp_pseudo_reg ();
1917 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1918 return gen_rtx_LO_SUM (Pmode, high, addr);
1922 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1923 type SYMBOL_TYPE. */
1926 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1929 HOST_WIDE_INT offset;
1931 mips_split_const (address, &base, &offset);
1932 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1933 UNSPEC_ADDRESS_FIRST + symbol_type);
1934 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1938 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1939 high part to BASE and return the result. Just return BASE otherwise.
1940 TEMP is available as a temporary register if needed.
1942 The returned expression can be used as the first operand to a LO_SUM. */
1945 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1946 enum mips_symbol_type symbol_type)
1948 if (mips_split_p[symbol_type])
1950 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1951 addr = mips_force_temporary (temp, addr);
1952 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1958 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1959 mips_force_temporary; it is only needed when OFFSET is not a
1963 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1965 if (!SMALL_OPERAND (offset))
1970 /* Load the full offset into a register so that we can use
1971 an unextended instruction for the address itself. */
1972 high = GEN_INT (offset);
1977 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1978 high = GEN_INT (CONST_HIGH_PART (offset));
1979 offset = CONST_LOW_PART (offset);
1981 high = mips_force_temporary (temp, high);
1982 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1984 return plus_constant (reg, offset);
1987 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
1988 referencing, and TYPE is the symbol type to use (either global
1989 dynamic or local dynamic). V0 is an RTX for the return value
1990 location. The entire insn sequence is returned. */
1992 static GTY(()) rtx mips_tls_symbol;
1995 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
1997 rtx insn, loc, tga, a0;
1999 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2001 if (!mips_tls_symbol)
2002 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2004 loc = mips_unspec_address (sym, type);
2008 emit_insn (gen_rtx_SET (Pmode, a0,
2009 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2010 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2011 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2012 CONST_OR_PURE_CALL_P (insn) = 1;
2013 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2014 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2015 insn = get_insns ();
2022 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2023 return value will be a valid address and move_operand (either a REG
2027 mips_legitimize_tls_address (rtx loc)
2029 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2030 enum tls_model model;
2032 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2033 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2035 model = SYMBOL_REF_TLS_MODEL (loc);
2039 case TLS_MODEL_GLOBAL_DYNAMIC:
2040 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2041 dest = gen_reg_rtx (Pmode);
2042 emit_libcall_block (insn, dest, v0, loc);
2045 case TLS_MODEL_LOCAL_DYNAMIC:
2046 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2047 tmp1 = gen_reg_rtx (Pmode);
2049 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2050 share the LDM result with other LD model accesses. */
2051 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2053 emit_libcall_block (insn, tmp1, v0, eqv);
2055 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2056 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2057 mips_unspec_address (loc, SYMBOL_DTPREL));
2060 case TLS_MODEL_INITIAL_EXEC:
2061 tmp1 = gen_reg_rtx (Pmode);
2062 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2063 if (Pmode == DImode)
2065 emit_insn (gen_tls_get_tp_di (v1));
2066 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2070 emit_insn (gen_tls_get_tp_si (v1));
2071 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2073 dest = gen_reg_rtx (Pmode);
2074 emit_insn (gen_add3_insn (dest, tmp1, v1));
2077 case TLS_MODEL_LOCAL_EXEC:
2079 if (Pmode == DImode)
2080 emit_insn (gen_tls_get_tp_di (v1));
2082 emit_insn (gen_tls_get_tp_si (v1));
2084 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2085 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2086 mips_unspec_address (loc, SYMBOL_TPREL));
2096 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2097 be legitimized in a way that the generic machinery might not expect,
2098 put the new address in *XLOC and return true. MODE is the mode of
2099 the memory being accessed. */
2102 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2104 enum mips_symbol_type symbol_type;
2106 if (mips_tls_operand_p (*xloc))
2108 *xloc = mips_legitimize_tls_address (*xloc);
2112 /* See if the address can split into a high part and a LO_SUM. */
2113 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2114 && mips_symbolic_address_p (symbol_type, mode)
2115 && mips_split_p[symbol_type])
2117 *xloc = mips_split_symbol (0, *xloc);
2121 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2123 /* Handle REG + CONSTANT using mips_add_offset. */
2126 reg = XEXP (*xloc, 0);
2127 if (!mips_valid_base_register_p (reg, mode, 0))
2128 reg = copy_to_mode_reg (Pmode, reg);
2129 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2137 /* Subroutine of mips_build_integer (with the same interface).
2138 Assume that the final action in the sequence should be a left shift. */
2141 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2143 unsigned int i, shift;
2145 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2146 since signed numbers are easier to load than unsigned ones. */
2148 while ((value & 1) == 0)
2149 value /= 2, shift++;
2151 i = mips_build_integer (codes, value);
2152 codes[i].code = ASHIFT;
2153 codes[i].value = shift;
2158 /* As for mips_build_shift, but assume that the final action will be
2159 an IOR or PLUS operation. */
2162 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2164 unsigned HOST_WIDE_INT high;
2167 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2168 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2170 /* The constant is too complex to load with a simple lui/ori pair
2171 so our goal is to clear as many trailing zeros as possible.
2172 In this case, we know bit 16 is set and that the low 16 bits
2173 form a negative number. If we subtract that number from VALUE,
2174 we will clear at least the lowest 17 bits, maybe more. */
2175 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2176 codes[i].code = PLUS;
2177 codes[i].value = CONST_LOW_PART (value);
2181 i = mips_build_integer (codes, high);
2182 codes[i].code = IOR;
2183 codes[i].value = value & 0xffff;
2189 /* Fill CODES with a sequence of rtl operations to load VALUE.
2190 Return the number of operations needed. */
2193 mips_build_integer (struct mips_integer_op *codes,
2194 unsigned HOST_WIDE_INT value)
2196 if (SMALL_OPERAND (value)
2197 || SMALL_OPERAND_UNSIGNED (value)
2198 || LUI_OPERAND (value))
2200 /* The value can be loaded with a single instruction. */
2201 codes[0].code = UNKNOWN;
2202 codes[0].value = value;
2205 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2207 /* Either the constant is a simple LUI/ORI combination or its
2208 lowest bit is set. We don't want to shift in this case. */
2209 return mips_build_lower (codes, value);
2211 else if ((value & 0xffff) == 0)
2213 /* The constant will need at least three actions. The lowest
2214 16 bits are clear, so the final action will be a shift. */
2215 return mips_build_shift (codes, value);
2219 /* The final action could be a shift, add or inclusive OR.
2220 Rather than use a complex condition to select the best
2221 approach, try both mips_build_shift and mips_build_lower
2222 and pick the one that gives the shortest sequence.
2223 Note that this case is only used once per constant. */
2224 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2225 unsigned int cost, alt_cost;
2227 cost = mips_build_shift (codes, value);
2228 alt_cost = mips_build_lower (alt_codes, value);
2229 if (alt_cost < cost)
2231 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2239 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2242 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2244 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2245 enum machine_mode mode;
2246 unsigned int i, cost;
2249 mode = GET_MODE (dest);
2250 cost = mips_build_integer (codes, value);
2252 /* Apply each binary operation to X. Invariant: X is a legitimate
2253 source operand for a SET pattern. */
2254 x = GEN_INT (codes[0].value);
2255 for (i = 1; i < cost; i++)
2259 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2263 x = force_reg (mode, x);
2264 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2267 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2271 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2272 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2276 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2279 HOST_WIDE_INT offset;
2281 /* Split moves of big integers into smaller pieces. */
2282 if (splittable_const_int_operand (src, mode))
2284 mips_move_integer (dest, dest, INTVAL (src));
2288 /* Split moves of symbolic constants into high/low pairs. */
2289 if (splittable_symbolic_operand (src, mode))
2291 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2295 if (mips_tls_operand_p (src))
2297 emit_move_insn (dest, mips_legitimize_tls_address (src));
2301 /* If we have (const (plus symbol offset)), load the symbol first
2302 and then add in the offset. This is usually better than forcing
2303 the constant into memory, at least in non-mips16 code. */
2304 mips_split_const (src, &base, &offset);
2307 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2309 base = mips_force_temporary (dest, base);
2310 emit_move_insn (dest, mips_add_offset (0, base, offset));
2314 src = force_const_mem (mode, src);
2316 /* When using explicit relocs, constant pool references are sometimes
2317 not legitimate addresses. */
2318 if (!memory_operand (src, VOIDmode))
2319 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2320 emit_move_insn (dest, src);
2324 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2325 sequence that is valid. */
2328 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2330 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2332 emit_move_insn (dest, force_reg (mode, src));
2336 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2337 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2338 && REG_P (src) && MD_REG_P (REGNO (src))
2339 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2341 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2342 if (GET_MODE_SIZE (mode) <= 4)
2343 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2344 gen_rtx_REG (SImode, REGNO (src)),
2345 gen_rtx_REG (SImode, other_regno)));
2347 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2348 gen_rtx_REG (DImode, REGNO (src)),
2349 gen_rtx_REG (DImode, other_regno)));
2353 /* We need to deal with constants that would be legitimate
2354 immediate_operands but not legitimate move_operands. */
2355 if (CONSTANT_P (src) && !move_operand (src, mode))
2357 mips_legitimize_const_move (mode, dest, src);
2358 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2364 /* We need a lot of little routines to check constant values on the
2365 mips16. These are used to figure out how long the instruction will
2366 be. It would be much better to do this using constraints, but
2367 there aren't nearly enough letters available. */
2370 m16_check_op (rtx op, int low, int high, int mask)
2372 return (GET_CODE (op) == CONST_INT
2373 && INTVAL (op) >= low
2374 && INTVAL (op) <= high
2375 && (INTVAL (op) & mask) == 0);
2379 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2381 return m16_check_op (op, 0x1, 0x8, 0);
2385 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2387 return m16_check_op (op, - 0x8, 0x7, 0);
2391 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2393 return m16_check_op (op, - 0x7, 0x8, 0);
2397 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2399 return m16_check_op (op, - 0x10, 0xf, 0);
2403 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2405 return m16_check_op (op, - 0xf, 0x10, 0);
2409 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2411 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2415 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2417 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2421 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2423 return m16_check_op (op, - 0x80, 0x7f, 0);
2427 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2429 return m16_check_op (op, - 0x7f, 0x80, 0);
2433 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2435 return m16_check_op (op, 0x0, 0xff, 0);
2439 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2441 return m16_check_op (op, - 0xff, 0x0, 0);
2445 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2447 return m16_check_op (op, - 0x1, 0xfe, 0);
2451 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2453 return m16_check_op (op, 0x0, 0xff << 2, 3);
2457 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2459 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2463 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2465 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2469 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2471 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2475 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2477 enum machine_mode mode = GET_MODE (x);
2478 bool float_mode_p = FLOAT_MODE_P (mode);
2485 /* A number between 1 and 8 inclusive is efficient for a shift.
2486 Otherwise, we will need an extended instruction. */
2487 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2488 || (outer_code) == LSHIFTRT)
2490 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2493 *total = COSTS_N_INSNS (1);
2497 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2498 if ((outer_code) == XOR
2499 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2505 /* We may be able to use slt or sltu for a comparison with a
2506 signed 16 bit value. (The boundary conditions aren't quite
2507 right, but this is just a heuristic anyhow.) */
2508 if (((outer_code) == LT || (outer_code) == LE
2509 || (outer_code) == GE || (outer_code) == GT
2510 || (outer_code) == LTU || (outer_code) == LEU
2511 || (outer_code) == GEU || (outer_code) == GTU)
2512 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2518 /* Equality comparisons with 0 are cheap. */
2519 if (((outer_code) == EQ || (outer_code) == NE)
2526 /* Constants in the range 0...255 can be loaded with an unextended
2527 instruction. They are therefore as cheap as a register move.
2529 Given the choice between "li R1,0...255" and "move R1,R2"
2530 (where R2 is a known constant), it is usually better to use "li",
2531 since we do not want to unnecessarily extend the lifetime
2533 if (outer_code == SET
2535 && INTVAL (x) < 256)
2543 /* These can be used anywhere. */
2548 /* Otherwise fall through to the handling below because
2549 we'll need to construct the constant. */
2555 if (LEGITIMATE_CONSTANT_P (x))
2557 *total = COSTS_N_INSNS (1);
2562 /* The value will need to be fetched from the constant pool. */
2563 *total = CONSTANT_POOL_COST;
2569 /* If the address is legitimate, return the number of
2570 instructions it needs, otherwise use the default handling. */
2571 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2574 *total = COSTS_N_INSNS (n + 1);
2581 *total = COSTS_N_INSNS (6);
2585 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2591 if (mode == DImode && !TARGET_64BIT)
2593 *total = COSTS_N_INSNS (2);
2601 if (mode == DImode && !TARGET_64BIT)
2603 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2611 *total = COSTS_N_INSNS (1);
2613 *total = COSTS_N_INSNS (4);
2617 *total = COSTS_N_INSNS (1);
2624 *total = mips_cost->fp_add;
2628 else if (mode == DImode && !TARGET_64BIT)
2630 *total = COSTS_N_INSNS (4);
2636 if (mode == DImode && !TARGET_64BIT)
2638 *total = COSTS_N_INSNS (4);
2645 *total = mips_cost->fp_mult_sf;
2647 else if (mode == DFmode)
2648 *total = mips_cost->fp_mult_df;
2650 else if (mode == SImode)
2651 *total = mips_cost->int_mult_si;
2654 *total = mips_cost->int_mult_di;
2663 *total = mips_cost->fp_div_sf;
2665 *total = mips_cost->fp_div_df;
2674 *total = mips_cost->int_div_di;
2676 *total = mips_cost->int_div_si;
2681 /* A sign extend from SImode to DImode in 64 bit mode is often
2682 zero instructions, because the result can often be used
2683 directly by another instruction; we'll call it one. */
2684 if (TARGET_64BIT && mode == DImode
2685 && GET_MODE (XEXP (x, 0)) == SImode)
2686 *total = COSTS_N_INSNS (1);
2688 *total = COSTS_N_INSNS (2);
2692 if (TARGET_64BIT && mode == DImode
2693 && GET_MODE (XEXP (x, 0)) == SImode)
2694 *total = COSTS_N_INSNS (2);
2696 *total = COSTS_N_INSNS (1);
2700 case UNSIGNED_FLOAT:
2703 case FLOAT_TRUNCATE:
2705 *total = mips_cost->fp_add;
2713 /* Provide the costs of an addressing mode that contains ADDR.
2714 If ADDR is not a valid address, its cost is irrelevant. */
2717 mips_address_cost (rtx addr)
2719 return mips_address_insns (addr, SImode);
2722 /* Return one word of double-word value OP, taking into account the fixed
2723 endianness of certain registers. HIGH_P is true to select the high part,
2724 false to select the low part. */
2727 mips_subword (rtx op, int high_p)
2730 enum machine_mode mode;
2732 mode = GET_MODE (op);
2733 if (mode == VOIDmode)
2736 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2737 byte = UNITS_PER_WORD;
2743 if (FP_REG_P (REGNO (op)))
2744 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2745 if (ACC_HI_REG_P (REGNO (op)))
2746 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2750 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2752 return simplify_gen_subreg (word_mode, op, mode, byte);
2756 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2759 mips_split_64bit_move_p (rtx dest, rtx src)
2764 /* FP->FP moves can be done in a single instruction. */
2765 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2768 /* Check for floating-point loads and stores. They can be done using
2769 ldc1 and sdc1 on MIPS II and above. */
2772 if (FP_REG_RTX_P (dest) && MEM_P (src))
2774 if (FP_REG_RTX_P (src) && MEM_P (dest))
2781 /* Split a 64-bit move from SRC to DEST assuming that
2782 mips_split_64bit_move_p holds.
2784 Moves into and out of FPRs cause some difficulty here. Such moves
2785 will always be DFmode, since paired FPRs are not allowed to store
2786 DImode values. The most natural representation would be two separate
2787 32-bit moves, such as:
2789 (set (reg:SI $f0) (mem:SI ...))
2790 (set (reg:SI $f1) (mem:SI ...))
2792 However, the second insn is invalid because odd-numbered FPRs are
2793 not allowed to store independent values. Use the patterns load_df_low,
2794 load_df_high and store_df_high instead. */
2797 mips_split_64bit_move (rtx dest, rtx src)
2799 if (FP_REG_RTX_P (dest))
2801 /* Loading an FPR from memory or from GPRs. */
2802 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2803 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2806 else if (FP_REG_RTX_P (src))
2808 /* Storing an FPR into memory or GPRs. */
2809 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2810 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2814 /* The operation can be split into two normal moves. Decide in
2815 which order to do them. */
2818 low_dest = mips_subword (dest, 0);
2819 if (REG_P (low_dest)
2820 && reg_overlap_mentioned_p (low_dest, src))
2822 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2823 emit_move_insn (low_dest, mips_subword (src, 0));
2827 emit_move_insn (low_dest, mips_subword (src, 0));
2828 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2833 /* Return the appropriate instructions to move SRC into DEST. Assume
2834 that SRC is operand 1 and DEST is operand 0. */
2837 mips_output_move (rtx dest, rtx src)
2839 enum rtx_code dest_code, src_code;
2842 dest_code = GET_CODE (dest);
2843 src_code = GET_CODE (src);
2844 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2846 if (dbl_p && mips_split_64bit_move_p (dest, src))
2849 if ((src_code == REG && GP_REG_P (REGNO (src)))
2850 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2852 if (dest_code == REG)
2854 if (GP_REG_P (REGNO (dest)))
2855 return "move\t%0,%z1";
2857 if (MD_REG_P (REGNO (dest)))
2860 if (DSP_ACC_REG_P (REGNO (dest)))
2862 static char retval[] = "mt__\t%z1,%q0";
2863 retval[2] = reg_names[REGNO (dest)][4];
2864 retval[3] = reg_names[REGNO (dest)][5];
2868 if (FP_REG_P (REGNO (dest)))
2869 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2871 if (ALL_COP_REG_P (REGNO (dest)))
2873 static char retval[] = "dmtc_\t%z1,%0";
2875 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2876 return (dbl_p ? retval : retval + 1);
2879 if (dest_code == MEM)
2880 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2882 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2884 if (src_code == REG)
2886 if (DSP_ACC_REG_P (REGNO (src)))
2888 static char retval[] = "mf__\t%0,%q1";
2889 retval[2] = reg_names[REGNO (src)][4];
2890 retval[3] = reg_names[REGNO (src)][5];
2894 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2895 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2897 if (FP_REG_P (REGNO (src)))
2898 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2900 if (ALL_COP_REG_P (REGNO (src)))
2902 static char retval[] = "dmfc_\t%0,%1";
2904 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2905 return (dbl_p ? retval : retval + 1);
2909 if (src_code == MEM)
2910 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2912 if (src_code == CONST_INT)
2914 /* Don't use the X format, because that will give out of
2915 range numbers for 64 bit hosts and 32 bit targets. */
2917 return "li\t%0,%1\t\t\t# %X1";
2919 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2922 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2926 if (src_code == HIGH)
2927 return "lui\t%0,%h1";
2929 if (CONST_GP_P (src))
2930 return "move\t%0,%1";
2932 if (symbolic_operand (src, VOIDmode))
2933 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2935 if (src_code == REG && FP_REG_P (REGNO (src)))
2937 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2939 if (GET_MODE (dest) == V2SFmode)
2940 return "mov.ps\t%0,%1";
2942 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2945 if (dest_code == MEM)
2946 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2948 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2950 if (src_code == MEM)
2951 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2953 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2955 static char retval[] = "l_c_\t%0,%1";
2957 retval[1] = (dbl_p ? 'd' : 'w');
2958 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2961 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2963 static char retval[] = "s_c_\t%1,%0";
2965 retval[1] = (dbl_p ? 'd' : 'w');
2966 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2972 /* Restore $gp from its save slot. Valid only when using o32 or
2976 mips_restore_gp (void)
2980 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2982 address = mips_add_offset (pic_offset_table_rtx,
2983 frame_pointer_needed
2984 ? hard_frame_pointer_rtx
2985 : stack_pointer_rtx,
2986 current_function_outgoing_args_size);
2987 slot = gen_rtx_MEM (Pmode, address);
2989 emit_move_insn (pic_offset_table_rtx, slot);
2990 if (!TARGET_EXPLICIT_RELOCS)
2991 emit_insn (gen_blockage ());
2994 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2997 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2999 emit_insn (gen_rtx_SET (VOIDmode, target,
3000 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3003 /* Return true if CMP1 is a suitable second operand for relational
3004 operator CODE. See also the *sCC patterns in mips.md. */
3007 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3013 return reg_or_0_operand (cmp1, VOIDmode);
3017 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3021 return arith_operand (cmp1, VOIDmode);
3024 return sle_operand (cmp1, VOIDmode);
3027 return sleu_operand (cmp1, VOIDmode);
3034 /* Canonicalize LE or LEU comparisons into LT comparisons when
3035 possible to avoid extra instructions or inverting the
3039 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3040 enum machine_mode mode)
3042 HOST_WIDE_INT original, plus_one;
3044 if (GET_CODE (*cmp1) != CONST_INT)
3047 original = INTVAL (*cmp1);
3048 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3053 if (original < plus_one)
3056 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3065 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3078 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3079 result in TARGET. CMP0 and TARGET are register_operands that have
3080 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3081 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3084 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3085 rtx target, rtx cmp0, rtx cmp1)
3087 /* First see if there is a MIPS instruction that can do this operation
3088 with CMP1 in its current form. If not, try to canonicalize the
3089 comparison to LT. If that fails, try doing the same for the
3090 inverse operation. If that also fails, force CMP1 into a register
3092 if (mips_relational_operand_ok_p (code, cmp1))
3093 mips_emit_binary (code, target, cmp0, cmp1);
3094 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3095 mips_emit_binary (code, target, cmp0, cmp1);
3098 enum rtx_code inv_code = reverse_condition (code);
3099 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3101 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3102 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3104 else if (invert_ptr == 0)
3106 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3107 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3108 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3112 *invert_ptr = !*invert_ptr;
3113 mips_emit_binary (inv_code, target, cmp0, cmp1);
3118 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3119 The register will have the same mode as CMP0. */
3122 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3124 if (cmp1 == const0_rtx)
3127 if (uns_arith_operand (cmp1, VOIDmode))
3128 return expand_binop (GET_MODE (cmp0), xor_optab,
3129 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3131 return expand_binop (GET_MODE (cmp0), sub_optab,
3132 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3135 /* Convert *CODE into a code that can be used in a floating-point
3136 scc instruction (c.<cond>.<fmt>). Return true if the values of
3137 the condition code registers will be inverted, with 0 indicating
3138 that the condition holds. */
3141 mips_reverse_fp_cond_p (enum rtx_code *code)
3148 *code = reverse_condition_maybe_unordered (*code);
3156 /* Convert a comparison into something that can be used in a branch or
3157 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3158 being compared and *CODE is the code used to compare them.
3160 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3161 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3162 otherwise any standard branch condition can be used. The standard branch
3165 - EQ/NE between two registers.
3166 - any comparison between a register and zero. */
3169 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3171 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3173 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3175 *op0 = cmp_operands[0];
3176 *op1 = cmp_operands[1];
3178 else if (*code == EQ || *code == NE)
3182 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3187 *op0 = cmp_operands[0];
3188 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3193 /* The comparison needs a separate scc instruction. Store the
3194 result of the scc in *OP0 and compare it against zero. */
3195 bool invert = false;
3196 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3198 mips_emit_int_relational (*code, &invert, *op0,
3199 cmp_operands[0], cmp_operands[1]);
3200 *code = (invert ? EQ : NE);
3205 enum rtx_code cmp_code;
3207 /* Floating-point tests use a separate c.cond.fmt comparison to
3208 set a condition code register. The branch or conditional move
3209 will then compare that register against zero.
3211 Set CMP_CODE to the code of the comparison instruction and
3212 *CODE to the code that the branch or move should use. */
3214 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3216 ? gen_reg_rtx (CCmode)
3217 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3219 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3223 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3224 Store the result in TARGET and return true if successful.
3226 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3229 mips_emit_scc (enum rtx_code code, rtx target)
3231 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3234 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3235 if (code == EQ || code == NE)
3237 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3238 mips_emit_binary (code, target, zie, const0_rtx);
3241 mips_emit_int_relational (code, 0, target,
3242 cmp_operands[0], cmp_operands[1]);
3246 /* Emit the common code for doing conditional branches.
3247 operand[0] is the label to jump to.
3248 The comparison operands are saved away by cmp{si,di,sf,df}. */
3251 gen_conditional_branch (rtx *operands, enum rtx_code code)
3253 rtx op0, op1, condition;
3255 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3256 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3257 emit_jump_insn (gen_condjump (condition, operands[0]));
3262 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3263 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3266 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3267 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3272 reversed_p = mips_reverse_fp_cond_p (&cond);
3273 cmp_result = gen_reg_rtx (CCV2mode);
3274 emit_insn (gen_scc_ps (cmp_result,
3275 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3277 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3280 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3284 /* Emit the common code for conditional moves. OPERANDS is the array
3285 of operands passed to the conditional move define_expand. */
3288 gen_conditional_move (rtx *operands)
3293 code = GET_CODE (operands[1]);
3294 mips_emit_compare (&code, &op0, &op1, true);
3295 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3296 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3297 gen_rtx_fmt_ee (code,
3300 operands[2], operands[3])));
3303 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3304 the conditional_trap expander. */
3307 mips_gen_conditional_trap (rtx *operands)
3310 enum rtx_code cmp_code = GET_CODE (operands[0]);
3311 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3313 /* MIPS conditional trap machine instructions don't have GT or LE
3314 flavors, so we must invert the comparison and convert to LT and
3315 GE, respectively. */
3318 case GT: cmp_code = LT; break;
3319 case LE: cmp_code = GE; break;
3320 case GTU: cmp_code = LTU; break;
3321 case LEU: cmp_code = GEU; break;
3324 if (cmp_code == GET_CODE (operands[0]))
3326 op0 = cmp_operands[0];
3327 op1 = cmp_operands[1];
3331 op0 = cmp_operands[1];
3332 op1 = cmp_operands[0];
3334 op0 = force_reg (mode, op0);
3335 if (!arith_operand (op1, mode))
3336 op1 = force_reg (mode, op1);
3338 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3339 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3343 /* Load function address ADDR into register DEST. SIBCALL_P is true
3344 if the address is needed for a sibling call. */
3347 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3349 /* If we're generating PIC, and this call is to a global function,
3350 try to allow its address to be resolved lazily. This isn't
3351 possible for NewABI sibcalls since the value of $gp on entry
3352 to the stub would be our caller's gp, not ours. */
3353 if (TARGET_EXPLICIT_RELOCS
3354 && !(sibcall_p && TARGET_NEWABI)
3355 && global_got_operand (addr, VOIDmode))
3357 rtx high, lo_sum_symbol;
3359 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3360 addr, SYMBOL_GOTOFF_CALL);
3361 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3362 if (Pmode == SImode)
3363 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3365 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3368 emit_move_insn (dest, addr);
3372 /* Expand a call or call_value instruction. RESULT is where the
3373 result will go (null for calls), ADDR is the address of the
3374 function, ARGS_SIZE is the size of the arguments and AUX is
3375 the value passed to us by mips_function_arg. SIBCALL_P is true
3376 if we are expanding a sibling call, false if we're expanding
3380 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3382 rtx orig_addr, pattern, insn;
3385 if (!call_insn_operand (addr, VOIDmode))
3387 addr = gen_reg_rtx (Pmode);
3388 mips_load_call_address (addr, orig_addr, sibcall_p);
3392 && mips16_hard_float
3393 && build_mips16_call_stub (result, addr, args_size,
3394 aux == 0 ? 0 : (int) GET_MODE (aux)))
3398 pattern = (sibcall_p
3399 ? gen_sibcall_internal (addr, args_size)
3400 : gen_call_internal (addr, args_size));
3401 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3405 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3406 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3409 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3410 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3413 pattern = (sibcall_p
3414 ? gen_sibcall_value_internal (result, addr, args_size)
3415 : gen_call_value_internal (result, addr, args_size));
3417 insn = emit_call_insn (pattern);
3419 /* Lazy-binding stubs require $gp to be valid on entry. */
3420 if (global_got_operand (orig_addr, VOIDmode))
3421 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3425 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3428 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3429 tree exp ATTRIBUTE_UNUSED)
3431 return TARGET_SIBCALLS;
3434 /* Emit code to move general operand SRC into condition-code
3435 register DEST. SCRATCH is a scratch TFmode float register.
3442 where FP1 and FP2 are single-precision float registers
3443 taken from SCRATCH. */
3446 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3450 /* Change the source to SFmode. */
3452 src = adjust_address (src, SFmode, 0);
3453 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3454 src = gen_rtx_REG (SFmode, true_regnum (src));
3456 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3457 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3459 emit_move_insn (copy_rtx (fp1), src);
3460 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3461 emit_insn (gen_slt_sf (dest, fp2, fp1));
3464 /* Emit code to change the current function's return address to
3465 ADDRESS. SCRATCH is available as a scratch register, if needed.
3466 ADDRESS and SCRATCH are both word-mode GPRs. */
3469 mips_set_return_address (rtx address, rtx scratch)
3473 compute_frame_size (get_frame_size ());
3474 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3475 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3476 cfun->machine->frame.gp_sp_offset);
3478 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3481 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3482 Assume that the areas do not overlap. */
3485 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3487 HOST_WIDE_INT offset, delta;
3488 unsigned HOST_WIDE_INT bits;
3490 enum machine_mode mode;
3493 /* Work out how many bits to move at a time. If both operands have
3494 half-word alignment, it is usually better to move in half words.
3495 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3496 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3497 Otherwise move word-sized chunks. */
3498 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3499 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3500 bits = BITS_PER_WORD / 2;
3502 bits = BITS_PER_WORD;
3504 mode = mode_for_size (bits, MODE_INT, 0);
3505 delta = bits / BITS_PER_UNIT;
3507 /* Allocate a buffer for the temporary registers. */
3508 regs = alloca (sizeof (rtx) * length / delta);
3510 /* Load as many BITS-sized chunks as possible. Use a normal load if
3511 the source has enough alignment, otherwise use left/right pairs. */
3512 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3514 regs[i] = gen_reg_rtx (mode);
3515 if (MEM_ALIGN (src) >= bits)
3516 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3519 rtx part = adjust_address (src, BLKmode, offset);
3520 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3525 /* Copy the chunks to the destination. */
3526 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3527 if (MEM_ALIGN (dest) >= bits)
3528 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3531 rtx part = adjust_address (dest, BLKmode, offset);
3532 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3536 /* Mop up any left-over bytes. */
3537 if (offset < length)
3539 src = adjust_address (src, BLKmode, offset);
3540 dest = adjust_address (dest, BLKmode, offset);
3541 move_by_pieces (dest, src, length - offset,
3542 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3546 #define MAX_MOVE_REGS 4
3547 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3550 /* Helper function for doing a loop-based block operation on memory
3551 reference MEM. Each iteration of the loop will operate on LENGTH
3554 Create a new base register for use within the loop and point it to
3555 the start of MEM. Create a new memory reference that uses this
3556 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3559 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3560 rtx *loop_reg, rtx *loop_mem)
3562 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3564 /* Although the new mem does not refer to a known location,
3565 it does keep up to LENGTH bytes of alignment. */
3566 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3567 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3571 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3572 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3573 memory regions do not overlap. */
3576 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3578 rtx label, src_reg, dest_reg, final_src;
3579 HOST_WIDE_INT leftover;
3581 leftover = length % MAX_MOVE_BYTES;
3584 /* Create registers and memory references for use within the loop. */
3585 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3586 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3588 /* Calculate the value that SRC_REG should have after the last iteration
3590 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3593 /* Emit the start of the loop. */
3594 label = gen_label_rtx ();
3597 /* Emit the loop body. */
3598 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3600 /* Move on to the next block. */
3601 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3602 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3604 /* Emit the loop condition. */
3605 if (Pmode == DImode)
3606 emit_insn (gen_cmpdi (src_reg, final_src));
3608 emit_insn (gen_cmpsi (src_reg, final_src));
3609 emit_jump_insn (gen_bne (label));
3611 /* Mop up any left-over bytes. */
3613 mips_block_move_straight (dest, src, leftover);
3616 /* Expand a movmemsi instruction. */
3619 mips_expand_block_move (rtx dest, rtx src, rtx length)
3621 if (GET_CODE (length) == CONST_INT)
3623 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3625 mips_block_move_straight (dest, src, INTVAL (length));
3630 mips_block_move_loop (dest, src, INTVAL (length));
3637 /* Argument support functions. */
3639 /* Initialize CUMULATIVE_ARGS for a function. */
3642 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3643 rtx libname ATTRIBUTE_UNUSED)
3645 static CUMULATIVE_ARGS zero_cum;
3646 tree param, next_param;
3649 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3651 /* Determine if this function has variable arguments. This is
3652 indicated by the last argument being 'void_type_mode' if there
3653 are no variable arguments. The standard MIPS calling sequence
3654 passes all arguments in the general purpose registers in this case. */
3656 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3657 param != 0; param = next_param)
3659 next_param = TREE_CHAIN (param);
3660 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3661 cum->gp_reg_found = 1;
3666 /* Fill INFO with information about a single argument. CUM is the
3667 cumulative state for earlier arguments. MODE is the mode of this
3668 argument and TYPE is its type (if known). NAMED is true if this
3669 is a named (fixed) argument rather than a variable one. */
3672 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3673 tree type, int named, struct mips_arg_info *info)
3675 bool doubleword_aligned_p;
3676 unsigned int num_bytes, num_words, max_regs;
3678 /* Work out the size of the argument. */
3679 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3680 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3682 /* Decide whether it should go in a floating-point register, assuming
3683 one is free. Later code checks for availability.
3685 The checks against UNITS_PER_FPVALUE handle the soft-float and
3686 single-float cases. */
3690 /* The EABI conventions have traditionally been defined in terms
3691 of TYPE_MODE, regardless of the actual type. */
3692 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3693 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3694 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3699 /* Only leading floating-point scalars are passed in
3700 floating-point registers. We also handle vector floats the same
3701 say, which is OK because they are not covered by the standard ABI. */
3702 info->fpr_p = (!cum->gp_reg_found
3703 && cum->arg_number < 2
3704 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3705 || VECTOR_FLOAT_TYPE_P (type))
3706 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3707 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3708 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3713 /* Scalar and complex floating-point types are passed in
3714 floating-point registers. */
3715 info->fpr_p = (named
3716 && (type == 0 || FLOAT_TYPE_P (type))
3717 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3718 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3719 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3720 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3722 /* ??? According to the ABI documentation, the real and imaginary
3723 parts of complex floats should be passed in individual registers.
3724 The real and imaginary parts of stack arguments are supposed
3725 to be contiguous and there should be an extra word of padding
3728 This has two problems. First, it makes it impossible to use a
3729 single "void *" va_list type, since register and stack arguments
3730 are passed differently. (At the time of writing, MIPSpro cannot
3731 handle complex float varargs correctly.) Second, it's unclear
3732 what should happen when there is only one register free.
3734 For now, we assume that named complex floats should go into FPRs
3735 if there are two FPRs free, otherwise they should be passed in the
3736 same way as a struct containing two floats. */
3738 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3739 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3741 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3742 info->fpr_p = false;
3752 /* See whether the argument has doubleword alignment. */
3753 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3755 /* Set REG_OFFSET to the register count we're interested in.
3756 The EABI allocates the floating-point registers separately,
3757 but the other ABIs allocate them like integer registers. */
3758 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3762 /* Advance to an even register if the argument is doubleword-aligned. */
3763 if (doubleword_aligned_p)
3764 info->reg_offset += info->reg_offset & 1;
3766 /* Work out the offset of a stack argument. */
3767 info->stack_offset = cum->stack_words;
3768 if (doubleword_aligned_p)
3769 info->stack_offset += info->stack_offset & 1;
3771 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3773 /* Partition the argument between registers and stack. */
3774 info->reg_words = MIN (num_words, max_regs);
3775 info->stack_words = num_words - info->reg_words;
3779 /* Implement FUNCTION_ARG_ADVANCE. */
3782 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3783 tree type, int named)
3785 struct mips_arg_info info;
3787 mips_arg_info (cum, mode, type, named, &info);
3790 cum->gp_reg_found = true;
3792 /* See the comment above the cumulative args structure in mips.h
3793 for an explanation of what this code does. It assumes the O32
3794 ABI, which passes at most 2 arguments in float registers. */
3795 if (cum->arg_number < 2 && info.fpr_p)
3796 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3798 if (mips_abi != ABI_EABI || !info.fpr_p)
3799 cum->num_gprs = info.reg_offset + info.reg_words;
3800 else if (info.reg_words > 0)
3801 cum->num_fprs += FP_INC;
3803 if (info.stack_words > 0)
3804 cum->stack_words = info.stack_offset + info.stack_words;
3809 /* Implement FUNCTION_ARG. */
3812 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3813 tree type, int named)
3815 struct mips_arg_info info;
3817 /* We will be called with a mode of VOIDmode after the last argument
3818 has been seen. Whatever we return will be passed to the call
3819 insn. If we need a mips16 fp_code, return a REG with the code
3820 stored as the mode. */
3821 if (mode == VOIDmode)
3823 if (TARGET_MIPS16 && cum->fp_code != 0)
3824 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3830 mips_arg_info (cum, mode, type, named, &info);
3832 /* Return straight away if the whole argument is passed on the stack. */
3833 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3837 && TREE_CODE (type) == RECORD_TYPE
3839 && TYPE_SIZE_UNIT (type)
3840 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3843 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3844 structure contains a double in its entirety, then that 64 bit
3845 chunk is passed in a floating point register. */
3848 /* First check to see if there is any such field. */
3849 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3850 if (TREE_CODE (field) == FIELD_DECL
3851 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3852 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3853 && host_integerp (bit_position (field), 0)
3854 && int_bit_position (field) % BITS_PER_WORD == 0)
3859 /* Now handle the special case by returning a PARALLEL
3860 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3861 chunks are passed in registers. */
3863 HOST_WIDE_INT bitpos;
3866 /* assign_parms checks the mode of ENTRY_PARM, so we must
3867 use the actual mode here. */
3868 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3871 field = TYPE_FIELDS (type);
3872 for (i = 0; i < info.reg_words; i++)
3876 for (; field; field = TREE_CHAIN (field))
3877 if (TREE_CODE (field) == FIELD_DECL
3878 && int_bit_position (field) >= bitpos)
3882 && int_bit_position (field) == bitpos
3883 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3884 && !TARGET_SOFT_FLOAT
3885 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3886 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3888 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3891 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3892 GEN_INT (bitpos / BITS_PER_UNIT));
3894 bitpos += BITS_PER_WORD;
3900 /* Handle the n32/n64 conventions for passing complex floating-point
3901 arguments in FPR pairs. The real part goes in the lower register
3902 and the imaginary part goes in the upper register. */
3905 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3908 enum machine_mode inner;
3911 inner = GET_MODE_INNER (mode);
3912 reg = FP_ARG_FIRST + info.reg_offset;
3913 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3915 /* Real part in registers, imaginary part on stack. */
3916 gcc_assert (info.stack_words == info.reg_words);
3917 return gen_rtx_REG (inner, reg);
3921 gcc_assert (info.stack_words == 0);
3922 real = gen_rtx_EXPR_LIST (VOIDmode,
3923 gen_rtx_REG (inner, reg),
3925 imag = gen_rtx_EXPR_LIST (VOIDmode,
3927 reg + info.reg_words / 2),
3928 GEN_INT (GET_MODE_SIZE (inner)));
3929 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3934 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3935 else if (info.reg_offset == 1)
3936 /* This code handles the special o32 case in which the second word
3937 of the argument structure is passed in floating-point registers. */
3938 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3940 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3944 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3947 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3948 enum machine_mode mode, tree type, bool named)
3950 struct mips_arg_info info;
3952 mips_arg_info (cum, mode, type, named, &info);
3953 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3957 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3958 PARM_BOUNDARY bits of alignment, but will be given anything up
3959 to STACK_BOUNDARY bits if the type requires it. */
3962 function_arg_boundary (enum machine_mode mode, tree type)
3964 unsigned int alignment;
3966 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3967 if (alignment < PARM_BOUNDARY)
3968 alignment = PARM_BOUNDARY;
3969 if (alignment > STACK_BOUNDARY)
3970 alignment = STACK_BOUNDARY;
3974 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3975 upward rather than downward. In other words, return true if the
3976 first byte of the stack slot has useful data, false if the last
3980 mips_pad_arg_upward (enum machine_mode mode, tree type)
3982 /* On little-endian targets, the first byte of every stack argument
3983 is passed in the first byte of the stack slot. */
3984 if (!BYTES_BIG_ENDIAN)
3987 /* Otherwise, integral types are padded downward: the last byte of a
3988 stack argument is passed in the last byte of the stack slot. */
3990 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3991 : GET_MODE_CLASS (mode) == MODE_INT)
3994 /* Big-endian o64 pads floating-point arguments downward. */
3995 if (mips_abi == ABI_O64)
3996 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3999 /* Other types are padded upward for o32, o64, n32 and n64. */
4000 if (mips_abi != ABI_EABI)
4003 /* Arguments smaller than a stack slot are padded downward. */
4004 if (mode != BLKmode)
4005 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4007 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4011 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4012 if the least significant byte of the register has useful data. Return
4013 the opposite if the most significant byte does. */
4016 mips_pad_reg_upward (enum machine_mode mode, tree type)
4018 /* No shifting is required for floating-point arguments. */
4019 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4020 return !BYTES_BIG_ENDIAN;
4022 /* Otherwise, apply the same padding to register arguments as we do
4023 to stack arguments. */
4024 return mips_pad_arg_upward (mode, type);
4028 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4029 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4032 CUMULATIVE_ARGS local_cum;
4033 int gp_saved, fp_saved;
4035 /* The caller has advanced CUM up to, but not beyond, the last named
4036 argument. Advance a local copy of CUM past the last "real" named
4037 argument, to find out how many registers are left over. */
4040 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4042 /* Found out how many registers we need to save. */
4043 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4044 fp_saved = (EABI_FLOAT_VARARGS_P
4045 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4054 ptr = plus_constant (virtual_incoming_args_rtx,
4055 REG_PARM_STACK_SPACE (cfun->decl)
4056 - gp_saved * UNITS_PER_WORD);
4057 mem = gen_rtx_MEM (BLKmode, ptr);
4058 set_mem_alias_set (mem, get_varargs_alias_set ());
4060 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4065 /* We can't use move_block_from_reg, because it will use
4067 enum machine_mode mode;
4070 /* Set OFF to the offset from virtual_incoming_args_rtx of
4071 the first float register. The FP save area lies below
4072 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4073 off = -gp_saved * UNITS_PER_WORD;
4074 off &= ~(UNITS_PER_FPVALUE - 1);
4075 off -= fp_saved * UNITS_PER_FPREG;
4077 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4079 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4083 ptr = plus_constant (virtual_incoming_args_rtx, off);
4084 mem = gen_rtx_MEM (mode, ptr);
4085 set_mem_alias_set (mem, get_varargs_alias_set ());
4086 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4087 off += UNITS_PER_HWFPVALUE;
4091 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4092 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4093 + fp_saved * UNITS_PER_FPREG);
4096 /* Create the va_list data type.
4097 We keep 3 pointers, and two offsets.
4098 Two pointers are to the overflow area, which starts at the CFA.
4099 One of these is constant, for addressing into the GPR save area below it.
4100 The other is advanced up the stack through the overflow region.
4101 The third pointer is to the GPR save area. Since the FPR save area
4102 is just below it, we can address FPR slots off this pointer.
4103 We also keep two one-byte offsets, which are to be subtracted from the
4104 constant pointers to yield addresses in the GPR and FPR save areas.
4105 These are downcounted as float or non-float arguments are used,
4106 and when they get to zero, the argument must be obtained from the
4108 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4109 pointer is enough. It's started at the GPR save area, and is
4111 Note that the GPR save area is not constant size, due to optimization
4112 in the prologue. Hence, we can't use a design with two pointers
4113 and two offsets, although we could have designed this with two pointers
4114 and three offsets. */
4117 mips_build_builtin_va_list (void)
4119 if (EABI_FLOAT_VARARGS_P)
4121 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4124 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4126 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4128 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4130 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4132 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4133 unsigned_char_type_node);
4134 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4135 unsigned_char_type_node);
4136 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4137 warn on every user file. */
4138 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4139 array = build_array_type (unsigned_char_type_node,
4140 build_index_type (index));
4141 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4143 DECL_FIELD_CONTEXT (f_ovfl) = record;
4144 DECL_FIELD_CONTEXT (f_gtop) = record;
4145 DECL_FIELD_CONTEXT (f_ftop) = record;
4146 DECL_FIELD_CONTEXT (f_goff) = record;
4147 DECL_FIELD_CONTEXT (f_foff) = record;
4148 DECL_FIELD_CONTEXT (f_res) = record;
4150 TYPE_FIELDS (record) = f_ovfl;
4151 TREE_CHAIN (f_ovfl) = f_gtop;
4152 TREE_CHAIN (f_gtop) = f_ftop;
4153 TREE_CHAIN (f_ftop) = f_goff;
4154 TREE_CHAIN (f_goff) = f_foff;
4155 TREE_CHAIN (f_foff) = f_res;
4157 layout_type (record);
4160 else if (TARGET_IRIX && TARGET_IRIX6)
4161 /* On IRIX 6, this type is 'char *'. */
4162 return build_pointer_type (char_type_node);
4164 /* Otherwise, we use 'void *'. */
4165 return ptr_type_node;
4168 /* Implement va_start. */
4171 mips_va_start (tree valist, rtx nextarg)
4173 if (EABI_FLOAT_VARARGS_P)
4175 const CUMULATIVE_ARGS *cum;
4176 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4177 tree ovfl, gtop, ftop, goff, foff;
4179 int gpr_save_area_size;
4180 int fpr_save_area_size;
4183 cum = ¤t_function_args_info;
4185 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4187 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4189 f_ovfl = TYPE_FIELDS (va_list_type_node);
4190 f_gtop = TREE_CHAIN (f_ovfl);
4191 f_ftop = TREE_CHAIN (f_gtop);
4192 f_goff = TREE_CHAIN (f_ftop);
4193 f_foff = TREE_CHAIN (f_goff);
4195 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4197 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4199 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4201 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4203 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4206 /* Emit code to initialize OVFL, which points to the next varargs
4207 stack argument. CUM->STACK_WORDS gives the number of stack
4208 words used by named arguments. */
4209 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4210 if (cum->stack_words > 0)
4211 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4212 build_int_cst (NULL_TREE,
4213 cum->stack_words * UNITS_PER_WORD));
4214 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4215 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4217 /* Emit code to initialize GTOP, the top of the GPR save area. */
4218 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4219 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4220 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4222 /* Emit code to initialize FTOP, the top of the FPR save area.
4223 This address is gpr_save_area_bytes below GTOP, rounded
4224 down to the next fp-aligned boundary. */
4225 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4226 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4227 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4229 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4230 build_int_cst (NULL_TREE, -fpr_offset));
4231 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4232 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4234 /* Emit code to initialize GOFF, the offset from GTOP of the
4235 next GPR argument. */
4236 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4237 build_int_cst (NULL_TREE, gpr_save_area_size));
4238 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4240 /* Likewise emit code to initialize FOFF, the offset from FTOP
4241 of the next FPR argument. */
4242 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4243 build_int_cst (NULL_TREE, fpr_save_area_size));
4244 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4248 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4249 std_expand_builtin_va_start (valist, nextarg);
4253 /* Implement va_arg. */
4256 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4258 HOST_WIDE_INT size, rsize;
4262 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4265 type = build_pointer_type (type);
4267 size = int_size_in_bytes (type);
4268 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4270 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4271 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4274 /* Not a simple merged stack. */
4276 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4277 tree ovfl, top, off, align;
4278 HOST_WIDE_INT osize;
4281 f_ovfl = TYPE_FIELDS (va_list_type_node);
4282 f_gtop = TREE_CHAIN (f_ovfl);
4283 f_ftop = TREE_CHAIN (f_gtop);
4284 f_goff = TREE_CHAIN (f_ftop);
4285 f_foff = TREE_CHAIN (f_goff);
4287 /* We maintain separate pointers and offsets for floating-point
4288 and integer arguments, but we need similar code in both cases.
4291 TOP be the top of the register save area;
4292 OFF be the offset from TOP of the next register;
4293 ADDR_RTX be the address of the argument;
4294 RSIZE be the number of bytes used to store the argument
4295 when it's in the register save area;
4296 OSIZE be the number of bytes used to store it when it's
4297 in the stack overflow area; and
4298 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4300 The code we want is:
4302 1: off &= -rsize; // round down
4305 4: addr_rtx = top - off;
4310 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4311 10: addr_rtx = ovfl + PADDING;
4315 [1] and [9] can sometimes be optimized away. */
4317 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4320 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4321 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4323 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4325 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4328 /* When floating-point registers are saved to the stack,
4329 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4330 of the float's precision. */
4331 rsize = UNITS_PER_HWFPVALUE;
4333 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4334 (= PARM_BOUNDARY bits). This can be different from RSIZE
4337 (1) On 32-bit targets when TYPE is a structure such as:
4339 struct s { float f; };
4341 Such structures are passed in paired FPRs, so RSIZE
4342 will be 8 bytes. However, the structure only takes
4343 up 4 bytes of memory, so OSIZE will only be 4.
4345 (2) In combinations such as -mgp64 -msingle-float
4346 -fshort-double. Doubles passed in registers
4347 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4348 but those passed on the stack take up
4349 UNITS_PER_WORD bytes. */
4350 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4354 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4356 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4358 if (rsize > UNITS_PER_WORD)
4360 /* [1] Emit code for: off &= -rsize. */
4361 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4362 build_int_cst (NULL_TREE, -rsize));
4363 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4364 gimplify_and_add (t, pre_p);
4369 /* [2] Emit code to branch if off == 0. */
4370 t = build2 (NE_EXPR, boolean_type_node, off,
4371 build_int_cst (TREE_TYPE (off), 0));
4372 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4374 /* [5] Emit code for: off -= rsize. We do this as a form of
4375 post-increment not available to C. Also widen for the
4376 coming pointer arithmetic. */
4377 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4378 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4379 t = fold_convert (sizetype, t);
4380 t = fold_convert (TREE_TYPE (top), t);
4382 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4383 the argument has RSIZE - SIZE bytes of leading padding. */
4384 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4385 if (BYTES_BIG_ENDIAN && rsize > size)
4387 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4389 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4391 COND_EXPR_THEN (addr) = t;
4393 if (osize > UNITS_PER_WORD)
4395 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4396 u = fold_convert (TREE_TYPE (ovfl),
4397 build_int_cst (NULL_TREE, osize - 1));
4398 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4399 u = fold_convert (TREE_TYPE (ovfl),
4400 build_int_cst (NULL_TREE, -osize));
4401 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4402 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4407 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4408 post-increment ovfl by osize. On big-endian machines,
4409 the argument has OSIZE - SIZE bytes of leading padding. */
4410 u = fold_convert (TREE_TYPE (ovfl),
4411 build_int_cst (NULL_TREE, osize));
4412 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4413 if (BYTES_BIG_ENDIAN && osize > size)
4415 u = fold_convert (TREE_TYPE (t),
4416 build_int_cst (NULL_TREE, osize - size));
4417 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4420 /* String [9] and [10,11] together. */
4422 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4423 COND_EXPR_ELSE (addr) = t;
4425 addr = fold_convert (build_pointer_type (type), addr);
4426 addr = build_va_arg_indirect_ref (addr);
4430 addr = build_va_arg_indirect_ref (addr);
4435 /* Return true if it is possible to use left/right accesses for a
4436 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4437 returning true, update *OP, *LEFT and *RIGHT as follows:
4439 *OP is a BLKmode reference to the whole field.
4441 *LEFT is a QImode reference to the first byte if big endian or
4442 the last byte if little endian. This address can be used in the
4443 left-side instructions (lwl, swl, ldl, sdl).
4445 *RIGHT is a QImode reference to the opposite end of the field and
4446 can be used in the patterning right-side instruction. */
4449 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4450 rtx *left, rtx *right)
4454 /* Check that the operand really is a MEM. Not all the extv and
4455 extzv predicates are checked. */
4459 /* Check that the size is valid. */
4460 if (width != 32 && (!TARGET_64BIT || width != 64))
4463 /* We can only access byte-aligned values. Since we are always passed
4464 a reference to the first byte of the field, it is not necessary to
4465 do anything with BITPOS after this check. */
4466 if (bitpos % BITS_PER_UNIT != 0)
4469 /* Reject aligned bitfields: we want to use a normal load or store
4470 instead of a left/right pair. */
4471 if (MEM_ALIGN (*op) >= width)
4474 /* Adjust *OP to refer to the whole field. This also has the effect
4475 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4476 *op = adjust_address (*op, BLKmode, 0);
4477 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4479 /* Get references to both ends of the field. We deliberately don't
4480 use the original QImode *OP for FIRST since the new BLKmode one
4481 might have a simpler address. */
4482 first = adjust_address (*op, QImode, 0);
4483 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4485 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4486 be the upper word and RIGHT the lower word. */
4487 if (TARGET_BIG_ENDIAN)
4488 *left = first, *right = last;
4490 *left = last, *right = first;
4496 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4497 Return true on success. We only handle cases where zero_extract is
4498 equivalent to sign_extract. */
4501 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4503 rtx left, right, temp;
4505 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4506 paradoxical word_mode subreg. This is the only case in which
4507 we allow the destination to be larger than the source. */
4508 if (GET_CODE (dest) == SUBREG
4509 && GET_MODE (dest) == DImode
4510 && SUBREG_BYTE (dest) == 0
4511 && GET_MODE (SUBREG_REG (dest)) == SImode)
4512 dest = SUBREG_REG (dest);
4514 /* After the above adjustment, the destination must be the same
4515 width as the source. */
4516 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4519 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4522 temp = gen_reg_rtx (GET_MODE (dest));
4523 if (GET_MODE (dest) == DImode)
4525 emit_insn (gen_mov_ldl (temp, src, left));
4526 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4530 emit_insn (gen_mov_lwl (temp, src, left));
4531 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4537 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4541 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4544 enum machine_mode mode;
4546 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4549 mode = mode_for_size (width, MODE_INT, 0);
4550 src = gen_lowpart (mode, src);
4554 emit_insn (gen_mov_sdl (dest, src, left));
4555 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4559 emit_insn (gen_mov_swl (dest, src, left));
4560 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4565 /* Return true if X is a MEM with the same size as MODE. */
4568 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4575 size = MEM_SIZE (x);
4576 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4579 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4580 source of an "ext" instruction or the destination of an "ins"
4581 instruction. OP must be a register operand and the following
4582 conditions must hold:
4584 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4585 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4586 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4588 Also reject lengths equal to a word as they are better handled
4589 by the move patterns. */
4592 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4594 HOST_WIDE_INT len, pos;
4596 if (!ISA_HAS_EXT_INS
4597 || !register_operand (op, VOIDmode)
4598 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4601 len = INTVAL (size);
4602 pos = INTVAL (position);
4604 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4605 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4611 /* Set up globals to generate code for the ISA or processor
4612 described by INFO. */
4615 mips_set_architecture (const struct mips_cpu_info *info)
4619 mips_arch_info = info;
4620 mips_arch = info->cpu;
4621 mips_isa = info->isa;
4626 /* Likewise for tuning. */
4629 mips_set_tune (const struct mips_cpu_info *info)
4633 mips_tune_info = info;
4634 mips_tune = info->cpu;
4638 /* Implement TARGET_HANDLE_OPTION. */
4641 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4646 if (strcmp (arg, "32") == 0)
4648 else if (strcmp (arg, "o64") == 0)
4650 else if (strcmp (arg, "n32") == 0)
4652 else if (strcmp (arg, "64") == 0)
4654 else if (strcmp (arg, "eabi") == 0)
4655 mips_abi = ABI_EABI;
4662 return mips_parse_cpu (arg) != 0;
4665 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4666 return mips_isa_info != 0;
4668 case OPT_mno_flush_func:
4669 mips_cache_flush_func = NULL;
4677 /* Set up the threshold for data to go into the small data area, instead
4678 of the normal data area, and detect any conflicts in the switches. */
4681 override_options (void)
4683 int i, start, regno;
4684 enum machine_mode mode;
4686 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4688 /* The following code determines the architecture and register size.
4689 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4690 The GAS and GCC code should be kept in sync as much as possible. */
4692 if (mips_arch_string != 0)
4693 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4695 if (mips_isa_info != 0)
4697 if (mips_arch_info == 0)
4698 mips_set_architecture (mips_isa_info);
4699 else if (mips_arch_info->isa != mips_isa_info->isa)
4700 error ("-%s conflicts with the other architecture options, "
4701 "which specify a %s processor",
4702 mips_isa_info->name,
4703 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4706 if (mips_arch_info == 0)
4708 #ifdef MIPS_CPU_STRING_DEFAULT
4709 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4711 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4715 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4716 error ("-march=%s is not compatible with the selected ABI",
4717 mips_arch_info->name);
4719 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4720 if (mips_tune_string != 0)
4721 mips_set_tune (mips_parse_cpu (mips_tune_string));
4723 if (mips_tune_info == 0)
4724 mips_set_tune (mips_arch_info);
4726 /* Set cost structure for the processor. */
4727 mips_cost = &mips_rtx_cost_data[mips_tune];
4729 if ((target_flags_explicit & MASK_64BIT) != 0)
4731 /* The user specified the size of the integer registers. Make sure
4732 it agrees with the ABI and ISA. */
4733 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4734 error ("-mgp64 used with a 32-bit processor");
4735 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4736 error ("-mgp32 used with a 64-bit ABI");
4737 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4738 error ("-mgp64 used with a 32-bit ABI");
4742 /* Infer the integer register size from the ABI and processor.
4743 Restrict ourselves to 32-bit registers if that's all the
4744 processor has, or if the ABI cannot handle 64-bit registers. */
4745 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4746 target_flags &= ~MASK_64BIT;
4748 target_flags |= MASK_64BIT;
4751 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4753 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4754 only one right answer here. */
4755 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4756 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4757 else if (!TARGET_64BIT && TARGET_FLOAT64)
4758 error ("unsupported combination: %s", "-mgp32 -mfp64");
4759 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4760 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4764 /* -msingle-float selects 32-bit float registers. Otherwise the
4765 float registers should be the same size as the integer ones. */
4766 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4767 target_flags |= MASK_FLOAT64;
4769 target_flags &= ~MASK_FLOAT64;
4772 /* End of code shared with GAS. */
4774 if ((target_flags_explicit & MASK_LONG64) == 0)
4776 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4777 target_flags |= MASK_LONG64;
4779 target_flags &= ~MASK_LONG64;
4782 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4783 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4785 /* For some configurations, it is useful to have -march control
4786 the default setting of MASK_SOFT_FLOAT. */
4787 switch ((int) mips_arch)
4789 case PROCESSOR_R4100:
4790 case PROCESSOR_R4111:
4791 case PROCESSOR_R4120:
4792 case PROCESSOR_R4130:
4793 target_flags |= MASK_SOFT_FLOAT;
4797 target_flags &= ~MASK_SOFT_FLOAT;
4803 flag_pcc_struct_return = 0;
4805 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4807 /* If neither -mbranch-likely nor -mno-branch-likely was given
4808 on the command line, set MASK_BRANCHLIKELY based on the target
4811 By default, we enable use of Branch Likely instructions on
4812 all architectures which support them with the following
4813 exceptions: when creating MIPS32 or MIPS64 code, and when
4814 tuning for architectures where their use tends to hurt
4817 The MIPS32 and MIPS64 architecture specifications say "Software
4818 is strongly encouraged to avoid use of Branch Likely
4819 instructions, as they will be removed from a future revision
4820 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4821 issue those instructions unless instructed to do so by
4823 if (ISA_HAS_BRANCHLIKELY
4824 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4825 && !(TUNE_MIPS5500 || TUNE_SB1))
4826 target_flags |= MASK_BRANCHLIKELY;
4828 target_flags &= ~MASK_BRANCHLIKELY;
4830 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4831 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4833 /* The effect of -mabicalls isn't defined for the EABI. */
4834 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4836 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4837 target_flags &= ~MASK_ABICALLS;
4840 if (TARGET_ABICALLS)
4842 /* We need to set flag_pic for executables as well as DSOs
4843 because we may reference symbols that are not defined in
4844 the final executable. (MIPS does not use things like
4845 copy relocs, for example.)
4847 Also, there is a body of code that uses __PIC__ to distinguish
4848 between -mabicalls and -mno-abicalls code. */
4850 if (mips_section_threshold > 0)
4851 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4854 /* mips_split_addresses is a half-way house between explicit
4855 relocations and the traditional assembler macros. It can
4856 split absolute 32-bit symbolic constants into a high/lo_sum
4857 pair but uses macros for other sorts of access.
4859 Like explicit relocation support for REL targets, it relies
4860 on GNU extensions in the assembler and the linker.
4862 Although this code should work for -O0, it has traditionally
4863 been treated as an optimization. */
4864 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4865 && optimize && !flag_pic
4866 && !ABI_HAS_64BIT_SYMBOLS)
4867 mips_split_addresses = 1;
4869 mips_split_addresses = 0;
4871 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4872 faster code, but at the expense of more nops. Enable it at -O3 and
4874 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4875 target_flags |= MASK_VR4130_ALIGN;
4877 /* When compiling for the mips16, we cannot use floating point. We
4878 record the original hard float value in mips16_hard_float. */
4881 if (TARGET_SOFT_FLOAT)
4882 mips16_hard_float = 0;
4884 mips16_hard_float = 1;
4885 target_flags |= MASK_SOFT_FLOAT;
4887 /* Don't run the scheduler before reload, since it tends to
4888 increase register pressure. */
4889 flag_schedule_insns = 0;
4891 /* Don't do hot/cold partitioning. The constant layout code expects
4892 the whole function to be in a single section. */
4893 flag_reorder_blocks_and_partition = 0;
4895 /* Silently disable -mexplicit-relocs since it doesn't apply
4896 to mips16 code. Even so, it would overly pedantic to warn
4897 about "-mips16 -mexplicit-relocs", especially given that
4898 we use a %gprel() operator. */
4899 target_flags &= ~MASK_EXPLICIT_RELOCS;
4902 /* When using explicit relocs, we call dbr_schedule from within
4904 if (TARGET_EXPLICIT_RELOCS)
4906 mips_flag_delayed_branch = flag_delayed_branch;
4907 flag_delayed_branch = 0;
4910 #ifdef MIPS_TFMODE_FORMAT
4911 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4914 /* Make sure that the user didn't turn off paired single support when
4915 MIPS-3D support is requested. */
4916 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4917 && !TARGET_PAIRED_SINGLE_FLOAT)
4918 error ("-mips3d requires -mpaired-single");
4920 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4922 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4924 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4925 and TARGET_HARD_FLOAT are both true. */
4926 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4927 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4929 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4931 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4932 error ("-mips3d/-mpaired-single must be used with -mips64");
4934 if (TARGET_MIPS16 && TARGET_DSP)
4935 error ("-mips16 and -mdsp cannot be used together");
4937 mips_print_operand_punct['?'] = 1;
4938 mips_print_operand_punct['#'] = 1;
4939 mips_print_operand_punct['/'] = 1;
4940 mips_print_operand_punct['&'] = 1;
4941 mips_print_operand_punct['!'] = 1;
4942 mips_print_operand_punct['*'] = 1;
4943 mips_print_operand_punct['@'] = 1;
4944 mips_print_operand_punct['.'] = 1;
4945 mips_print_operand_punct['('] = 1;
4946 mips_print_operand_punct[')'] = 1;
4947 mips_print_operand_punct['['] = 1;
4948 mips_print_operand_punct[']'] = 1;
4949 mips_print_operand_punct['<'] = 1;
4950 mips_print_operand_punct['>'] = 1;
4951 mips_print_operand_punct['{'] = 1;
4952 mips_print_operand_punct['}'] = 1;
4953 mips_print_operand_punct['^'] = 1;
4954 mips_print_operand_punct['$'] = 1;
4955 mips_print_operand_punct['+'] = 1;
4956 mips_print_operand_punct['~'] = 1;
4958 /* Set up array to map GCC register number to debug register number.
4959 Ignore the special purpose register numbers. */
4961 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4962 mips_dbx_regno[i] = -1;
4964 start = GP_DBX_FIRST - GP_REG_FIRST;
4965 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4966 mips_dbx_regno[i] = i + start;
4968 start = FP_DBX_FIRST - FP_REG_FIRST;
4969 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4970 mips_dbx_regno[i] = i + start;
4972 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4973 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4975 /* Set up array giving whether a given register can hold a given mode. */
4977 for (mode = VOIDmode;
4978 mode != MAX_MACHINE_MODE;
4979 mode = (enum machine_mode) ((int)mode + 1))
4981 register int size = GET_MODE_SIZE (mode);
4982 register enum mode_class class = GET_MODE_CLASS (mode);
4984 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4988 if (mode == CCV2mode)
4991 && (regno - ST_REG_FIRST) % 2 == 0);
4993 else if (mode == CCV4mode)
4996 && (regno - ST_REG_FIRST) % 4 == 0);
4998 else if (mode == CCmode)
5001 temp = (regno == FPSW_REGNUM);
5003 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5004 || FP_REG_P (regno));
5007 else if (GP_REG_P (regno))
5008 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5010 else if (FP_REG_P (regno))
5011 temp = ((regno % FP_INC) == 0)
5012 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5013 || class == MODE_VECTOR_FLOAT)
5014 && size <= UNITS_PER_FPVALUE)
5015 /* Allow integer modes that fit into a single
5016 register. We need to put integers into FPRs
5017 when using instructions like cvt and trunc.
5018 We can't allow sizes smaller than a word,
5019 the FPU has no appropriate load/store
5020 instructions for those. */
5021 || (class == MODE_INT
5022 && size >= MIN_UNITS_PER_WORD
5023 && size <= UNITS_PER_FPREG)
5024 /* Allow TFmode for CCmode reloads. */
5025 || (ISA_HAS_8CC && mode == TFmode));
5027 else if (ACC_REG_P (regno))
5028 temp = (INTEGRAL_MODE_P (mode)
5029 && (size <= UNITS_PER_WORD
5030 || (ACC_HI_REG_P (regno)
5031 && size == 2 * UNITS_PER_WORD)));
5033 else if (ALL_COP_REG_P (regno))
5034 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5038 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5042 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5043 initialized yet, so we can't use that here. */
5044 gpr_mode = TARGET_64BIT ? DImode : SImode;
5046 /* Provide default values for align_* for 64-bit targets. */
5047 if (TARGET_64BIT && !TARGET_MIPS16)
5049 if (align_loops == 0)
5051 if (align_jumps == 0)
5053 if (align_functions == 0)
5054 align_functions = 8;
5057 /* Function to allocate machine-dependent function status. */
5058 init_machine_status = &mips_init_machine_status;
5060 if (ABI_HAS_64BIT_SYMBOLS)
5062 if (TARGET_EXPLICIT_RELOCS)
5064 mips_split_p[SYMBOL_64_HIGH] = true;
5065 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5066 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5068 mips_split_p[SYMBOL_64_MID] = true;
5069 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5070 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5072 mips_split_p[SYMBOL_64_LOW] = true;
5073 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5074 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5076 mips_split_p[SYMBOL_GENERAL] = true;
5077 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5082 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5084 mips_split_p[SYMBOL_GENERAL] = true;
5085 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5086 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5092 /* The high part is provided by a pseudo copy of $gp. */
5093 mips_split_p[SYMBOL_SMALL_DATA] = true;
5094 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5097 if (TARGET_EXPLICIT_RELOCS)
5099 /* Small data constants are kept whole until after reload,
5100 then lowered by mips_rewrite_small_data. */
5101 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5103 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5106 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5107 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5111 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5112 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5117 /* The HIGH and LO_SUM are matched by special .md patterns. */
5118 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5120 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5121 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5122 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5124 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5125 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5126 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5131 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5133 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5134 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5140 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5141 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5142 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5145 /* Thread-local relocation operators. */
5146 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5147 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5148 mips_split_p[SYMBOL_DTPREL] = 1;
5149 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5150 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5151 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5152 mips_split_p[SYMBOL_TPREL] = 1;
5153 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5154 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5156 /* We don't have a thread pointer access instruction on MIPS16, or
5157 appropriate TLS relocations. */
5159 targetm.have_tls = false;
5161 /* Default to working around R4000 errata only if the processor
5162 was selected explicitly. */
5163 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5164 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5165 target_flags |= MASK_FIX_R4000;
5167 /* Default to working around R4400 errata only if the processor
5168 was selected explicitly. */
5169 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5170 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5171 target_flags |= MASK_FIX_R4400;
5174 /* Implement CONDITIONAL_REGISTER_USAGE. */
5177 mips_conditional_register_usage (void)
5183 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5184 fixed_regs[regno] = call_used_regs[regno] = 1;
5186 if (!TARGET_HARD_FLOAT)
5190 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5191 fixed_regs[regno] = call_used_regs[regno] = 1;
5192 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5193 fixed_regs[regno] = call_used_regs[regno] = 1;
5195 else if (! ISA_HAS_8CC)
5199 /* We only have a single condition code register. We
5200 implement this by hiding all the condition code registers,
5201 and generating RTL that refers directly to ST_REG_FIRST. */
5202 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5203 fixed_regs[regno] = call_used_regs[regno] = 1;
5205 /* In mips16 mode, we permit the $t temporary registers to be used
5206 for reload. We prohibit the unused $s registers, since they
5207 are caller saved, and saving them via a mips16 register would
5208 probably waste more time than just reloading the value. */
5211 fixed_regs[18] = call_used_regs[18] = 1;
5212 fixed_regs[19] = call_used_regs[19] = 1;
5213 fixed_regs[20] = call_used_regs[20] = 1;
5214 fixed_regs[21] = call_used_regs[21] = 1;
5215 fixed_regs[22] = call_used_regs[22] = 1;
5216 fixed_regs[23] = call_used_regs[23] = 1;
5217 fixed_regs[26] = call_used_regs[26] = 1;
5218 fixed_regs[27] = call_used_regs[27] = 1;
5219 fixed_regs[30] = call_used_regs[30] = 1;
5221 /* fp20-23 are now caller saved. */
5222 if (mips_abi == ABI_64)
5225 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5226 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5228 /* Odd registers from fp21 to fp31 are now caller saved. */
5229 if (mips_abi == ABI_N32)
5232 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5233 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5237 /* Allocate a chunk of memory for per-function machine-dependent data. */
5238 static struct machine_function *
5239 mips_init_machine_status (void)
5241 return ((struct machine_function *)
5242 ggc_alloc_cleared (sizeof (struct machine_function)));
5245 /* On the mips16, we want to allocate $24 (T_REG) before other
5246 registers for instructions for which it is possible. This helps
5247 avoid shuffling registers around in order to set up for an xor,
5248 encouraging the compiler to use a cmp instead. */
5251 mips_order_regs_for_local_alloc (void)
5255 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5256 reg_alloc_order[i] = i;
5260 /* It really doesn't matter where we put register 0, since it is
5261 a fixed register anyhow. */
5262 reg_alloc_order[0] = 24;
5263 reg_alloc_order[24] = 0;
5268 /* The MIPS debug format wants all automatic variables and arguments
5269 to be in terms of the virtual frame pointer (stack pointer before
5270 any adjustment in the function), while the MIPS 3.0 linker wants
5271 the frame pointer to be the stack pointer after the initial
5272 adjustment. So, we do the adjustment here. The arg pointer (which
5273 is eliminated) points to the virtual frame pointer, while the frame
5274 pointer (which may be eliminated) points to the stack pointer after
5275 the initial adjustments. */
5278 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5280 rtx offset2 = const0_rtx;
5281 rtx reg = eliminate_constant_term (addr, &offset2);
5284 offset = INTVAL (offset2);
5286 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5287 || reg == hard_frame_pointer_rtx)
5289 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5290 ? compute_frame_size (get_frame_size ())
5291 : cfun->machine->frame.total_size;
5293 /* MIPS16 frame is smaller */
5294 if (frame_pointer_needed && TARGET_MIPS16)
5295 frame_size -= cfun->machine->frame.args_size;
5297 offset = offset - frame_size;
5300 /* sdbout_parms does not want this to crash for unrecognized cases. */
5302 else if (reg != arg_pointer_rtx)
5303 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5310 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5312 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5313 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5314 'h' OP is HIGH, prints %hi(X),
5315 'd' output integer constant in decimal,
5316 'z' if the operand is 0, use $0 instead of normal operand.
5317 'D' print second part of double-word register or memory operand.
5318 'L' print low-order register of double-word register operand.
5319 'M' print high-order register of double-word register operand.
5320 'C' print part of opcode for a branch condition.
5321 'F' print part of opcode for a floating-point branch condition.
5322 'N' print part of opcode for a branch condition, inverted.
5323 'W' print part of opcode for a floating-point branch condition, inverted.
5324 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5325 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5326 't' like 'T', but with the EQ/NE cases reversed
5327 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5328 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5329 'R' print the reloc associated with LO_SUM
5330 'q' print DSP accumulator registers
5332 The punctuation characters are:
5334 '(' Turn on .set noreorder
5335 ')' Turn on .set reorder
5336 '[' Turn on .set noat
5338 '<' Turn on .set nomacro
5339 '>' Turn on .set macro
5340 '{' Turn on .set volatile (not GAS)
5341 '}' Turn on .set novolatile (not GAS)
5342 '&' Turn on .set noreorder if filling delay slots
5343 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5344 '!' Turn on .set nomacro if filling delay slots
5345 '#' Print nop if in a .set noreorder section.
5346 '/' Like '#', but does nothing within a delayed branch sequence
5347 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5348 '@' Print the name of the assembler temporary register (at or $1).
5349 '.' Print the name of the register with a hard-wired zero (zero or $0).
5350 '^' Print the name of the pic call-through register (t9 or $25).
5351 '$' Print the name of the stack pointer register (sp or $29).
5352 '+' Print the name of the gp register (usually gp or $28).
5353 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5356 print_operand (FILE *file, rtx op, int letter)
5358 register enum rtx_code code;
5360 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5365 if (mips_branch_likely)
5370 fputs (reg_names [GP_REG_FIRST + 1], file);
5374 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5378 fputs (reg_names [GP_REG_FIRST + 0], file);
5382 fputs (reg_names[STACK_POINTER_REGNUM], file);
5386 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5390 if (final_sequence != 0 && set_noreorder++ == 0)
5391 fputs (".set\tnoreorder\n\t", file);
5395 if (final_sequence != 0)
5397 if (set_noreorder++ == 0)
5398 fputs (".set\tnoreorder\n\t", file);
5400 if (set_nomacro++ == 0)
5401 fputs (".set\tnomacro\n\t", file);
5406 if (final_sequence != 0 && set_nomacro++ == 0)
5407 fputs ("\n\t.set\tnomacro", file);
5411 if (set_noreorder != 0)
5412 fputs ("\n\tnop", file);
5416 /* Print an extra newline so that the delayed insn is separated
5417 from the following ones. This looks neater and is consistent
5418 with non-nop delayed sequences. */
5419 if (set_noreorder != 0 && final_sequence == 0)
5420 fputs ("\n\tnop\n", file);
5424 if (set_noreorder++ == 0)
5425 fputs (".set\tnoreorder\n\t", file);
5429 if (set_noreorder == 0)
5430 error ("internal error: %%) found without a %%( in assembler pattern");
5432 else if (--set_noreorder == 0)
5433 fputs ("\n\t.set\treorder", file);
5438 if (set_noat++ == 0)
5439 fputs (".set\tnoat\n\t", file);
5444 error ("internal error: %%] found without a %%[ in assembler pattern");
5445 else if (--set_noat == 0)
5446 fputs ("\n\t.set\tat", file);
5451 if (set_nomacro++ == 0)
5452 fputs (".set\tnomacro\n\t", file);
5456 if (set_nomacro == 0)
5457 error ("internal error: %%> found without a %%< in assembler pattern");
5458 else if (--set_nomacro == 0)
5459 fputs ("\n\t.set\tmacro", file);
5464 if (set_volatile++ == 0)
5465 fputs ("#.set\tvolatile\n\t", file);
5469 if (set_volatile == 0)
5470 error ("internal error: %%} found without a %%{ in assembler pattern");
5471 else if (--set_volatile == 0)
5472 fputs ("\n\t#.set\tnovolatile", file);
5478 if (align_labels_log > 0)
5479 ASM_OUTPUT_ALIGN (file, align_labels_log);
5484 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5493 error ("PRINT_OPERAND null pointer");
5497 code = GET_CODE (op);
5502 case EQ: fputs ("eq", file); break;
5503 case NE: fputs ("ne", file); break;
5504 case GT: fputs ("gt", file); break;
5505 case GE: fputs ("ge", file); break;
5506 case LT: fputs ("lt", file); break;
5507 case LE: fputs ("le", file); break;
5508 case GTU: fputs ("gtu", file); break;
5509 case GEU: fputs ("geu", file); break;
5510 case LTU: fputs ("ltu", file); break;
5511 case LEU: fputs ("leu", file); break;
5513 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5516 else if (letter == 'N')
5519 case EQ: fputs ("ne", file); break;
5520 case NE: fputs ("eq", file); break;
5521 case GT: fputs ("le", file); break;
5522 case GE: fputs ("lt", file); break;
5523 case LT: fputs ("ge", file); break;
5524 case LE: fputs ("gt", file); break;
5525 case GTU: fputs ("leu", file); break;
5526 case GEU: fputs ("ltu", file); break;
5527 case LTU: fputs ("geu", file); break;
5528 case LEU: fputs ("gtu", file); break;
5530 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5533 else if (letter == 'F')
5536 case EQ: fputs ("c1f", file); break;
5537 case NE: fputs ("c1t", file); break;
5539 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5542 else if (letter == 'W')
5545 case EQ: fputs ("c1t", file); break;
5546 case NE: fputs ("c1f", file); break;
5548 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5551 else if (letter == 'h')
5553 if (GET_CODE (op) == HIGH)
5556 print_operand_reloc (file, op, mips_hi_relocs);
5559 else if (letter == 'R')
5560 print_operand_reloc (file, op, mips_lo_relocs);
5562 else if (letter == 'Y')
5564 if (GET_CODE (op) == CONST_INT
5565 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5566 < ARRAY_SIZE (mips_fp_conditions)))
5567 fputs (mips_fp_conditions[INTVAL (op)], file);
5569 output_operand_lossage ("invalid %%Y value");
5572 else if (letter == 'Z')
5576 print_operand (file, op, 0);
5581 else if (letter == 'q')
5586 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5588 regnum = REGNO (op);
5589 if (MD_REG_P (regnum))
5590 fprintf (file, "$ac0");
5591 else if (DSP_ACC_REG_P (regnum))
5592 fprintf (file, "$ac%c", reg_names[regnum][3]);
5594 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5597 else if (code == REG || code == SUBREG)
5599 register int regnum;
5602 regnum = REGNO (op);
5604 regnum = true_regnum (op);
5606 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5607 || (letter == 'L' && WORDS_BIG_ENDIAN)
5611 fprintf (file, "%s", reg_names[regnum]);
5614 else if (code == MEM)
5617 output_address (plus_constant (XEXP (op, 0), 4));
5619 output_address (XEXP (op, 0));
5622 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5623 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5625 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5626 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5628 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5629 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5631 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5632 fputs (reg_names[GP_REG_FIRST], file);
5634 else if (letter == 'd' || letter == 'x' || letter == 'X')
5635 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5637 else if (letter == 'T' || letter == 't')
5639 int truth = (code == NE) == (letter == 'T');
5640 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5643 else if (CONST_GP_P (op))
5644 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5647 output_addr_const (file, op);
5651 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5652 RELOCS is the array of relocations to use. */
5655 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5657 enum mips_symbol_type symbol_type;
5660 HOST_WIDE_INT offset;
5662 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5663 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5665 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5666 mips_split_const (op, &base, &offset);
5667 if (UNSPEC_ADDRESS_P (base))
5668 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5670 fputs (relocs[symbol_type], file);
5671 output_addr_const (file, op);
5672 for (p = relocs[symbol_type]; *p != 0; p++)
5677 /* Output address operand X to FILE. */
5680 print_operand_address (FILE *file, rtx x)
5682 struct mips_address_info addr;
5684 if (mips_classify_address (&addr, x, word_mode, true))
5688 print_operand (file, addr.offset, 0);
5689 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5692 case ADDRESS_LO_SUM:
5693 print_operand (file, addr.offset, 'R');
5694 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5697 case ADDRESS_CONST_INT:
5698 output_addr_const (file, x);
5699 fprintf (file, "(%s)", reg_names[0]);
5702 case ADDRESS_SYMBOLIC:
5703 output_addr_const (file, x);
5709 /* When using assembler macros, keep track of all of small-data externs
5710 so that mips_file_end can emit the appropriate declarations for them.
5712 In most cases it would be safe (though pointless) to emit .externs
5713 for other symbols too. One exception is when an object is within
5714 the -G limit but declared by the user to be in a section other
5715 than .sbss or .sdata. */
5718 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5720 register struct extern_list *p;
5722 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5724 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5725 p->next = extern_head;
5727 p->size = int_size_in_bytes (TREE_TYPE (decl));
5731 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5733 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5734 p->next = extern_head;
5745 irix_output_external_libcall (rtx fun)
5747 register struct extern_list *p;
5749 if (mips_abi == ABI_32)
5751 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5752 p->next = extern_head;
5753 p->name = XSTR (fun, 0);
5760 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5761 put out a MIPS ECOFF file and a stab. */
5764 mips_output_filename (FILE *stream, const char *name)
5767 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5769 if (write_symbols == DWARF2_DEBUG)
5771 else if (mips_output_filename_first_time)
5773 mips_output_filename_first_time = 0;
5774 num_source_filenames += 1;
5775 current_function_file = name;
5776 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5777 output_quoted_string (stream, name);
5778 putc ('\n', stream);
5781 /* If we are emitting stabs, let dbxout.c handle this (except for
5782 the mips_output_filename_first_time case). */
5783 else if (write_symbols == DBX_DEBUG)
5786 else if (name != current_function_file
5787 && strcmp (name, current_function_file) != 0)
5789 num_source_filenames += 1;
5790 current_function_file = name;
5791 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5792 output_quoted_string (stream, name);
5793 putc ('\n', stream);
5797 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5798 that should be written before the opening quote, such as "\t.ascii\t"
5799 for real string data or "\t# " for a comment. */
5802 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5807 register const unsigned char *string =
5808 (const unsigned char *)string_param;
5810 fprintf (stream, "%s\"", prefix);
5811 for (i = 0; i < len; i++)
5813 register int c = string[i];
5817 if (c == '\\' || c == '\"')
5819 putc ('\\', stream);
5827 fprintf (stream, "\\%03o", c);
5831 if (cur_pos > 72 && i+1 < len)
5834 fprintf (stream, "\"\n%s\"", prefix);
5837 fprintf (stream, "\"\n");
5840 /* Implement TARGET_ASM_FILE_START. */
5843 mips_file_start (void)
5845 default_file_start ();
5849 /* Generate a special section to describe the ABI switches used to
5850 produce the resultant binary. This used to be done by the assembler
5851 setting bits in the ELF header's flags field, but we have run out of
5852 bits. GDB needs this information in order to be able to correctly
5853 debug these binaries. See the function mips_gdbarch_init() in
5854 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5855 causes unnecessary IRIX 6 ld warnings. */
5856 const char * abi_string = NULL;
5860 case ABI_32: abi_string = "abi32"; break;
5861 case ABI_N32: abi_string = "abiN32"; break;
5862 case ABI_64: abi_string = "abi64"; break;
5863 case ABI_O64: abi_string = "abiO64"; break;
5864 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5868 /* Note - we use fprintf directly rather than calling switch_to_section
5869 because in this way we can avoid creating an allocated section. We
5870 do not want this section to take up any space in the running
5872 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5874 /* There is no ELF header flag to distinguish long32 forms of the
5875 EABI from long64 forms. Emit a special section to help tools
5876 such as GDB. Do the same for o64, which is sometimes used with
5878 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5879 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5880 TARGET_LONG64 ? 64 : 32);
5882 /* Restore the default section. */
5883 fprintf (asm_out_file, "\t.previous\n");
5886 /* Generate the pseudo ops that System V.4 wants. */
5887 if (TARGET_ABICALLS)
5888 fprintf (asm_out_file, "\t.abicalls\n");
5891 fprintf (asm_out_file, "\t.set\tmips16\n");
5893 if (flag_verbose_asm)
5894 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5896 mips_section_threshold, mips_arch_info->name, mips_isa);
5899 #ifdef BSS_SECTION_ASM_OP
5900 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5901 in the use of sbss. */
5904 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5905 unsigned HOST_WIDE_INT size, int align)
5907 extern tree last_assemble_variable_decl;
5909 if (mips_in_small_data_p (decl))
5910 switch_to_section (get_named_section (NULL, ".sbss", 0));
5912 switch_to_section (bss_section);
5913 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5914 last_assemble_variable_decl = decl;
5915 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5916 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5920 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5921 .externs for any small-data variables that turned out to be external. */
5924 mips_file_end (void)
5927 struct extern_list *p;
5931 fputs ("\n", asm_out_file);
5933 for (p = extern_head; p != 0; p = p->next)
5935 name_tree = get_identifier (p->name);
5937 /* Positively ensure only one .extern for any given symbol. */
5938 if (!TREE_ASM_WRITTEN (name_tree)
5939 && TREE_SYMBOL_REFERENCED (name_tree))
5941 TREE_ASM_WRITTEN (name_tree) = 1;
5942 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5943 `.global name .text' directive for every used but
5944 undefined function. If we don't, the linker may perform
5945 an optimization (skipping over the insns that set $gp)
5946 when it is unsafe. */
5947 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5949 fputs ("\t.globl ", asm_out_file);
5950 assemble_name (asm_out_file, p->name);
5951 fputs (" .text\n", asm_out_file);
5955 fputs ("\t.extern\t", asm_out_file);
5956 assemble_name (asm_out_file, p->name);
5957 fprintf (asm_out_file, ", %d\n", p->size);
5964 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5965 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5968 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5969 unsigned HOST_WIDE_INT size,
5972 /* If the target wants uninitialized const declarations in
5973 .rdata then don't put them in .comm. */
5974 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5975 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5976 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5978 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5979 targetm.asm_out.globalize_label (stream, name);
5981 switch_to_section (readonly_data_section);
5982 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5983 mips_declare_object (stream, name, "",
5984 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5988 mips_declare_common_object (stream, name, "\n\t.comm\t",
5992 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5993 NAME is the name of the object and ALIGN is the required alignment
5994 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5995 alignment argument. */
5998 mips_declare_common_object (FILE *stream, const char *name,
5999 const char *init_string,
6000 unsigned HOST_WIDE_INT size,
6001 unsigned int align, bool takes_alignment_p)
6003 if (!takes_alignment_p)
6005 size += (align / BITS_PER_UNIT) - 1;
6006 size -= size % (align / BITS_PER_UNIT);
6007 mips_declare_object (stream, name, init_string,
6008 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6011 mips_declare_object (stream, name, init_string,
6012 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6013 size, align / BITS_PER_UNIT);
6016 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6017 macros, mark the symbol as written so that mips_file_end won't emit an
6018 .extern for it. STREAM is the output file, NAME is the name of the
6019 symbol, INIT_STRING is the string that should be written before the
6020 symbol and FINAL_STRING is the string that should be written after it.
6021 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6024 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6025 const char *final_string, ...)
6029 fputs (init_string, stream);
6030 assemble_name (stream, name);
6031 va_start (ap, final_string);
6032 vfprintf (stream, final_string, ap);
6035 if (!TARGET_EXPLICIT_RELOCS)
6037 tree name_tree = get_identifier (name);
6038 TREE_ASM_WRITTEN (name_tree) = 1;
6042 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6043 extern int size_directive_output;
6045 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6046 definitions except that it uses mips_declare_object() to emit the label. */
6049 mips_declare_object_name (FILE *stream, const char *name,
6050 tree decl ATTRIBUTE_UNUSED)
6052 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6053 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6056 size_directive_output = 0;
6057 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6061 size_directive_output = 1;
6062 size = int_size_in_bytes (TREE_TYPE (decl));
6063 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6066 mips_declare_object (stream, name, "", ":\n");
6069 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6072 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6076 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6077 if (!flag_inhibit_size_directive
6078 && DECL_SIZE (decl) != 0
6079 && !at_end && top_level
6080 && DECL_INITIAL (decl) == error_mark_node
6081 && !size_directive_output)
6085 size_directive_output = 1;
6086 size = int_size_in_bytes (TREE_TYPE (decl));
6087 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6092 /* Return true if X is a small data address that can be rewritten
6096 mips_rewrite_small_data_p (rtx x)
6098 enum mips_symbol_type symbol_type;
6100 return (TARGET_EXPLICIT_RELOCS
6101 && mips_symbolic_constant_p (x, &symbol_type)
6102 && symbol_type == SYMBOL_SMALL_DATA);
6106 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6109 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6111 if (GET_CODE (*loc) == LO_SUM)
6114 return mips_rewrite_small_data_p (*loc);
6117 /* Return true if OP refers to small data symbols directly, not through
6121 mips_small_data_pattern_p (rtx op)
6123 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6126 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6129 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6131 if (mips_rewrite_small_data_p (*loc))
6132 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6134 if (GET_CODE (*loc) == LO_SUM)
6140 /* If possible, rewrite OP so that it refers to small data using
6141 explicit relocations. */
6144 mips_rewrite_small_data (rtx op)
6146 op = copy_insn (op);
6147 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6151 /* Return true if the current function has an insn that implicitly
6155 mips_function_has_gp_insn (void)
6157 /* Don't bother rechecking if we found one last time. */
6158 if (!cfun->machine->has_gp_insn_p)
6162 push_topmost_sequence ();
6163 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6165 && GET_CODE (PATTERN (insn)) != USE
6166 && GET_CODE (PATTERN (insn)) != CLOBBER
6167 && (get_attr_got (insn) != GOT_UNSET
6168 || small_data_pattern (PATTERN (insn), VOIDmode)))
6170 pop_topmost_sequence ();
6172 cfun->machine->has_gp_insn_p = (insn != 0);
6174 return cfun->machine->has_gp_insn_p;
6178 /* Return the register that should be used as the global pointer
6179 within this function. Return 0 if the function doesn't need
6180 a global pointer. */
6183 mips_global_pointer (void)
6187 /* $gp is always available in non-abicalls code. */
6188 if (!TARGET_ABICALLS)
6189 return GLOBAL_POINTER_REGNUM;
6191 /* We must always provide $gp when it is used implicitly. */
6192 if (!TARGET_EXPLICIT_RELOCS)
6193 return GLOBAL_POINTER_REGNUM;
6195 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6197 if (current_function_profile)
6198 return GLOBAL_POINTER_REGNUM;
6200 /* If the function has a nonlocal goto, $gp must hold the correct
6201 global pointer for the target function. */
6202 if (current_function_has_nonlocal_goto)
6203 return GLOBAL_POINTER_REGNUM;
6205 /* If the gp is never referenced, there's no need to initialize it.
6206 Note that reload can sometimes introduce constant pool references
6207 into a function that otherwise didn't need them. For example,
6208 suppose we have an instruction like:
6210 (set (reg:DF R1) (float:DF (reg:SI R2)))
6212 If R2 turns out to be constant such as 1, the instruction may have a
6213 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6214 using this constant if R2 doesn't get allocated to a register.
6216 In cases like these, reload will have added the constant to the pool
6217 but no instruction will yet refer to it. */
6218 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6219 && !current_function_uses_const_pool
6220 && !mips_function_has_gp_insn ())
6223 /* We need a global pointer, but perhaps we can use a call-clobbered
6224 register instead of $gp. */
6225 if (TARGET_NEWABI && current_function_is_leaf)
6226 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6227 if (!regs_ever_live[regno]
6228 && call_used_regs[regno]
6229 && !fixed_regs[regno]
6230 && regno != PIC_FUNCTION_ADDR_REGNUM)
6233 return GLOBAL_POINTER_REGNUM;
6237 /* Return true if the current function must save REGNO. */
6240 mips_save_reg_p (unsigned int regno)
6242 /* We only need to save $gp for NewABI PIC. */
6243 if (regno == GLOBAL_POINTER_REGNUM)
6244 return (TARGET_ABICALLS && TARGET_NEWABI
6245 && cfun->machine->global_pointer == regno);
6247 /* Check call-saved registers. */
6248 if (regs_ever_live[regno] && !call_used_regs[regno])
6251 /* We need to save the old frame pointer before setting up a new one. */
6252 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6255 /* We need to save the incoming return address if it is ever clobbered
6256 within the function. */
6257 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6264 return_type = DECL_RESULT (current_function_decl);
6266 /* $18 is a special case in mips16 code. It may be used to call
6267 a function which returns a floating point value, but it is
6268 marked in call_used_regs. */
6269 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6272 /* $31 is also a special case. It will be used to copy a return
6273 value into the floating point registers if the return value is
6275 if (regno == GP_REG_FIRST + 31
6276 && mips16_hard_float
6277 && !aggregate_value_p (return_type, current_function_decl)
6278 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6279 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6287 /* Return the bytes needed to compute the frame pointer from the current
6288 stack pointer. SIZE is the size (in bytes) of the local variables.
6290 MIPS stack frames look like:
6292 Before call After call
6293 +-----------------------+ +-----------------------+
6296 | caller's temps. | | caller's temps. |
6298 +-----------------------+ +-----------------------+
6300 | arguments on stack. | | arguments on stack. |
6302 +-----------------------+ +-----------------------+
6303 | 4 words to save | | 4 words to save |
6304 | arguments passed | | arguments passed |
6305 | in registers, even | | in registers, even |
6306 SP->| if not passed. | VFP->| if not passed. |
6307 +-----------------------+ +-----------------------+
6309 | fp register save |
6311 +-----------------------+
6313 | gp register save |
6315 +-----------------------+
6319 +-----------------------+
6321 | alloca allocations |
6323 +-----------------------+
6325 | GP save for V.4 abi |
6327 +-----------------------+
6329 | arguments on stack |
6331 +-----------------------+
6333 | arguments passed |
6334 | in registers, even |
6335 low SP->| if not passed. |
6336 memory +-----------------------+
6341 compute_frame_size (HOST_WIDE_INT size)
6344 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6345 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6346 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6347 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6348 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6349 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6350 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6351 unsigned int mask; /* mask of saved gp registers */
6352 unsigned int fmask; /* mask of saved fp registers */
6354 cfun->machine->global_pointer = mips_global_pointer ();
6360 var_size = MIPS_STACK_ALIGN (size);
6361 args_size = current_function_outgoing_args_size;
6362 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6364 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6365 functions. If the function has local variables, we're committed
6366 to allocating it anyway. Otherwise reclaim it here. */
6367 if (var_size == 0 && current_function_is_leaf)
6368 cprestore_size = args_size = 0;
6370 /* The MIPS 3.0 linker does not like functions that dynamically
6371 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6372 looks like we are trying to create a second frame pointer to the
6373 function, so allocate some stack space to make it happy. */
6375 if (args_size == 0 && current_function_calls_alloca)
6376 args_size = 4 * UNITS_PER_WORD;
6378 total_size = var_size + args_size + cprestore_size;
6380 /* Calculate space needed for gp registers. */
6381 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6382 if (mips_save_reg_p (regno))
6384 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6385 mask |= 1 << (regno - GP_REG_FIRST);
6388 /* We need to restore these for the handler. */
6389 if (current_function_calls_eh_return)
6394 regno = EH_RETURN_DATA_REGNO (i);
6395 if (regno == INVALID_REGNUM)
6397 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6398 mask |= 1 << (regno - GP_REG_FIRST);
6402 /* This loop must iterate over the same space as its companion in
6403 save_restore_insns. */
6404 for (regno = (FP_REG_LAST - FP_INC + 1);
6405 regno >= FP_REG_FIRST;
6408 if (mips_save_reg_p (regno))
6410 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6411 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6415 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6416 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6418 /* Add in the space required for saving incoming register arguments. */
6419 total_size += current_function_pretend_args_size;
6420 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6422 /* Save other computed information. */
6423 cfun->machine->frame.total_size = total_size;
6424 cfun->machine->frame.var_size = var_size;
6425 cfun->machine->frame.args_size = args_size;
6426 cfun->machine->frame.cprestore_size = cprestore_size;
6427 cfun->machine->frame.gp_reg_size = gp_reg_size;
6428 cfun->machine->frame.fp_reg_size = fp_reg_size;
6429 cfun->machine->frame.mask = mask;
6430 cfun->machine->frame.fmask = fmask;
6431 cfun->machine->frame.initialized = reload_completed;
6432 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6433 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6437 HOST_WIDE_INT offset;
6439 offset = (args_size + cprestore_size + var_size
6440 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6441 cfun->machine->frame.gp_sp_offset = offset;
6442 cfun->machine->frame.gp_save_offset = offset - total_size;
6446 cfun->machine->frame.gp_sp_offset = 0;
6447 cfun->machine->frame.gp_save_offset = 0;
6452 HOST_WIDE_INT offset;
6454 offset = (args_size + cprestore_size + var_size
6455 + gp_reg_rounded + fp_reg_size
6456 - FP_INC * UNITS_PER_FPREG);
6457 cfun->machine->frame.fp_sp_offset = offset;
6458 cfun->machine->frame.fp_save_offset = offset - total_size;
6462 cfun->machine->frame.fp_sp_offset = 0;
6463 cfun->machine->frame.fp_save_offset = 0;
6466 /* Ok, we're done. */
6470 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6471 pointer or argument pointer. TO is either the stack pointer or
6472 hard frame pointer. */
6475 mips_initial_elimination_offset (int from, int to)
6477 HOST_WIDE_INT offset;
6479 compute_frame_size (get_frame_size ());
6481 /* Set OFFSET to the offset from the stack pointer. */
6484 case FRAME_POINTER_REGNUM:
6488 case ARG_POINTER_REGNUM:
6489 offset = (cfun->machine->frame.total_size
6490 - current_function_pretend_args_size);
6497 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6498 offset -= cfun->machine->frame.args_size;
6503 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6504 back to a previous frame. */
6506 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6511 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6514 /* Use FN to save or restore register REGNO. MODE is the register's
6515 mode and OFFSET is the offset of its save slot from the current
6519 mips_save_restore_reg (enum machine_mode mode, int regno,
6520 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6524 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6526 fn (gen_rtx_REG (mode, regno), mem);
6530 /* Call FN for each register that is saved by the current function.
6531 SP_OFFSET is the offset of the current stack pointer from the start
6535 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6537 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6539 enum machine_mode fpr_mode;
6540 HOST_WIDE_INT offset;
6543 /* Save registers starting from high to low. The debuggers prefer at least
6544 the return register be stored at func+4, and also it allows us not to
6545 need a nop in the epilog if at least one register is reloaded in
6546 addition to return address. */
6547 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6548 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6549 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6551 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6552 offset -= GET_MODE_SIZE (gpr_mode);
6555 /* This loop must iterate over the same space as its companion in
6556 compute_frame_size. */
6557 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6558 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6559 for (regno = (FP_REG_LAST - FP_INC + 1);
6560 regno >= FP_REG_FIRST;
6562 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6564 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6565 offset -= GET_MODE_SIZE (fpr_mode);
6570 /* If we're generating n32 or n64 abicalls, and the current function
6571 does not use $28 as its global pointer, emit a cplocal directive.
6572 Use pic_offset_table_rtx as the argument to the directive. */
6575 mips_output_cplocal (void)
6577 if (!TARGET_EXPLICIT_RELOCS
6578 && cfun->machine->global_pointer > 0
6579 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6580 output_asm_insn (".cplocal %+", 0);
6583 /* Return the style of GP load sequence that is being used for the
6584 current function. */
6586 enum mips_loadgp_style
6587 mips_current_loadgp_style (void)
6589 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6592 if (TARGET_ABSOLUTE_ABICALLS)
6593 return LOADGP_ABSOLUTE;
6595 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6598 /* The __gnu_local_gp symbol. */
6600 static GTY(()) rtx mips_gnu_local_gp;
6602 /* If we're generating n32 or n64 abicalls, emit instructions
6603 to set up the global pointer. */
6606 mips_emit_loadgp (void)
6608 rtx addr, offset, incoming_address;
6610 switch (mips_current_loadgp_style ())
6612 case LOADGP_ABSOLUTE:
6613 if (mips_gnu_local_gp == NULL)
6615 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6616 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6618 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6622 addr = XEXP (DECL_RTL (current_function_decl), 0);
6623 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6624 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6625 emit_insn (gen_loadgp (offset, incoming_address));
6626 if (!TARGET_EXPLICIT_RELOCS)
6627 emit_insn (gen_loadgp_blockage ());
6635 /* Set up the stack and frame (if desired) for the function. */
6638 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6641 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6643 #ifdef SDB_DEBUGGING_INFO
6644 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6645 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6648 /* In mips16 mode, we may need to generate a 32 bit to handle
6649 floating point arguments. The linker will arrange for any 32 bit
6650 functions to call this stub, which will then jump to the 16 bit
6652 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6653 && current_function_args_info.fp_code != 0)
6654 build_mips16_function_stub (file);
6656 if (!FUNCTION_NAME_ALREADY_DECLARED)
6658 /* Get the function name the same way that toplev.c does before calling
6659 assemble_start_function. This is needed so that the name used here
6660 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6661 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6663 if (!flag_inhibit_size_directive)
6665 fputs ("\t.ent\t", file);
6666 assemble_name (file, fnname);
6670 assemble_name (file, fnname);
6671 fputs (":\n", file);
6674 /* Stop mips_file_end from treating this function as external. */
6675 if (TARGET_IRIX && mips_abi == ABI_32)
6676 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6678 if (!flag_inhibit_size_directive)
6680 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6682 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6683 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6684 ", args= " HOST_WIDE_INT_PRINT_DEC
6685 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6686 (reg_names[(frame_pointer_needed)
6687 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6688 ((frame_pointer_needed && TARGET_MIPS16)
6689 ? tsize - cfun->machine->frame.args_size
6691 reg_names[GP_REG_FIRST + 31],
6692 cfun->machine->frame.var_size,
6693 cfun->machine->frame.num_gp,
6694 cfun->machine->frame.num_fp,
6695 cfun->machine->frame.args_size,
6696 cfun->machine->frame.cprestore_size);
6698 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6699 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6700 cfun->machine->frame.mask,
6701 cfun->machine->frame.gp_save_offset);
6702 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6703 cfun->machine->frame.fmask,
6704 cfun->machine->frame.fp_save_offset);
6707 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6708 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6711 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6713 /* Handle the initialization of $gp for SVR4 PIC. */
6714 if (!cfun->machine->all_noreorder_p)
6715 output_asm_insn ("%(.cpload\t%^%)", 0);
6717 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6719 else if (cfun->machine->all_noreorder_p)
6720 output_asm_insn ("%(%<", 0);
6722 /* Tell the assembler which register we're using as the global
6723 pointer. This is needed for thunks, since they can use either
6724 explicit relocs or assembler macros. */
6725 mips_output_cplocal ();
6728 /* Make the last instruction frame related and note that it performs
6729 the operation described by FRAME_PATTERN. */
6732 mips_set_frame_expr (rtx frame_pattern)
6736 insn = get_last_insn ();
6737 RTX_FRAME_RELATED_P (insn) = 1;
6738 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6744 /* Return a frame-related rtx that stores REG at MEM.
6745 REG must be a single register. */
6748 mips_frame_set (rtx mem, rtx reg)
6752 /* If we're saving the return address register and the dwarf return
6753 address column differs from the hard register number, adjust the
6754 note reg to refer to the former. */
6755 if (REGNO (reg) == GP_REG_FIRST + 31
6756 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6757 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6759 set = gen_rtx_SET (VOIDmode, mem, reg);
6760 RTX_FRAME_RELATED_P (set) = 1;
6766 /* Save register REG to MEM. Make the instruction frame-related. */
6769 mips_save_reg (rtx reg, rtx mem)
6771 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6775 if (mips_split_64bit_move_p (mem, reg))
6776 mips_split_64bit_move (mem, reg);
6778 emit_move_insn (mem, reg);
6780 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6781 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6782 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6787 && REGNO (reg) != GP_REG_FIRST + 31
6788 && !M16_REG_P (REGNO (reg)))
6790 /* Save a non-mips16 register by moving it through a temporary.
6791 We don't need to do this for $31 since there's a special
6792 instruction for it. */
6793 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6794 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6797 emit_move_insn (mem, reg);
6799 mips_set_frame_expr (mips_frame_set (mem, reg));
6804 /* Expand the prologue into a bunch of separate insns. */
6807 mips_expand_prologue (void)
6811 if (cfun->machine->global_pointer > 0)
6812 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6814 size = compute_frame_size (get_frame_size ());
6816 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6817 bytes beforehand; this is enough to cover the register save area
6818 without going out of range. */
6819 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6821 HOST_WIDE_INT step1;
6823 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6824 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6826 GEN_INT (-step1)))) = 1;
6828 mips_for_each_saved_reg (size, mips_save_reg);
6831 /* Allocate the rest of the frame. */
6834 if (SMALL_OPERAND (-size))
6835 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6837 GEN_INT (-size)))) = 1;
6840 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6843 /* There are no instructions to add or subtract registers
6844 from the stack pointer, so use the frame pointer as a
6845 temporary. We should always be using a frame pointer
6846 in this case anyway. */
6847 gcc_assert (frame_pointer_needed);
6848 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6849 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6850 hard_frame_pointer_rtx,
6851 MIPS_PROLOGUE_TEMP (Pmode)));
6852 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6855 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6857 MIPS_PROLOGUE_TEMP (Pmode)));
6859 /* Describe the combined effect of the previous instructions. */
6861 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6862 plus_constant (stack_pointer_rtx, -size)));
6866 /* Set up the frame pointer, if we're using one. In mips16 code,
6867 we point the frame pointer ahead of the outgoing argument area.
6868 This should allow more variables & incoming arguments to be
6869 accessed with unextended instructions. */
6870 if (frame_pointer_needed)
6872 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6874 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6875 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6877 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6882 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6883 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6884 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6885 hard_frame_pointer_rtx,
6886 MIPS_PROLOGUE_TEMP (Pmode)));
6888 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6889 plus_constant (stack_pointer_rtx,
6890 cfun->machine->frame.args_size)));
6894 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6895 stack_pointer_rtx)) = 1;
6898 mips_emit_loadgp ();
6900 /* If generating o32/o64 abicalls, save $gp on the stack. */
6901 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6902 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6904 /* If we are profiling, make sure no instructions are scheduled before
6905 the call to mcount. */
6907 if (current_function_profile)
6908 emit_insn (gen_blockage ());
6911 /* Do any necessary cleanup after a function to restore stack, frame,
6914 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6917 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6918 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6920 /* Reinstate the normal $gp. */
6921 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6922 mips_output_cplocal ();
6924 if (cfun->machine->all_noreorder_p)
6926 /* Avoid using %>%) since it adds excess whitespace. */
6927 output_asm_insn (".set\tmacro", 0);
6928 output_asm_insn (".set\treorder", 0);
6929 set_noreorder = set_nomacro = 0;
6932 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6936 /* Get the function name the same way that toplev.c does before calling
6937 assemble_start_function. This is needed so that the name used here
6938 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6939 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6940 fputs ("\t.end\t", file);
6941 assemble_name (file, fnname);
6946 /* Emit instructions to restore register REG from slot MEM. */
6949 mips_restore_reg (rtx reg, rtx mem)
6951 /* There's no mips16 instruction to load $31 directly. Load into
6952 $7 instead and adjust the return insn appropriately. */
6953 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6954 reg = gen_rtx_REG (GET_MODE (reg), 7);
6956 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6958 /* Can't restore directly; move through a temporary. */
6959 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6960 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6963 emit_move_insn (reg, mem);
6967 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6968 if this epilogue precedes a sibling call, false if it is for a normal
6969 "epilogue" pattern. */
6972 mips_expand_epilogue (int sibcall_p)
6974 HOST_WIDE_INT step1, step2;
6977 if (!sibcall_p && mips_can_use_return_insn ())
6979 emit_jump_insn (gen_return ());
6983 /* Split the frame into two. STEP1 is the amount of stack we should
6984 deallocate before restoring the registers. STEP2 is the amount we
6985 should deallocate afterwards.
6987 Start off by assuming that no registers need to be restored. */
6988 step1 = cfun->machine->frame.total_size;
6991 /* Work out which register holds the frame address. Account for the
6992 frame pointer offset used by mips16 code. */
6993 if (!frame_pointer_needed)
6994 base = stack_pointer_rtx;
6997 base = hard_frame_pointer_rtx;
6999 step1 -= cfun->machine->frame.args_size;
7002 /* If we need to restore registers, deallocate as much stack as
7003 possible in the second step without going out of range. */
7004 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7006 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7010 /* Set TARGET to BASE + STEP1. */
7016 /* Get an rtx for STEP1 that we can add to BASE. */
7017 adjust = GEN_INT (step1);
7018 if (!SMALL_OPERAND (step1))
7020 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7021 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7024 /* Normal mode code can copy the result straight into $sp. */
7026 target = stack_pointer_rtx;
7028 emit_insn (gen_add3_insn (target, base, adjust));
7031 /* Copy TARGET into the stack pointer. */
7032 if (target != stack_pointer_rtx)
7033 emit_move_insn (stack_pointer_rtx, target);
7035 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7036 implicitly used by all SYMBOL_REFs. We must emit a blockage
7037 insn before restoring it. */
7038 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7039 emit_insn (gen_blockage ());
7041 /* Restore the registers. */
7042 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7045 /* Deallocate the final bit of the frame. */
7047 emit_insn (gen_add3_insn (stack_pointer_rtx,
7051 /* Add in the __builtin_eh_return stack adjustment. We need to
7052 use a temporary in mips16 code. */
7053 if (current_function_calls_eh_return)
7057 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7058 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7059 MIPS_EPILOGUE_TEMP (Pmode),
7060 EH_RETURN_STACKADJ_RTX));
7061 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7064 emit_insn (gen_add3_insn (stack_pointer_rtx,
7066 EH_RETURN_STACKADJ_RTX));
7071 /* The mips16 loads the return address into $7, not $31. */
7072 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7073 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7074 GP_REG_FIRST + 7)));
7076 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7077 GP_REG_FIRST + 31)));
7081 /* Return nonzero if this function is known to have a null epilogue.
7082 This allows the optimizer to omit jumps to jumps if no stack
7086 mips_can_use_return_insn (void)
7090 if (! reload_completed)
7093 if (regs_ever_live[31] || current_function_profile)
7096 return_type = DECL_RESULT (current_function_decl);
7098 /* In mips16 mode, a function which returns a floating point value
7099 needs to arrange to copy the return value into the floating point
7102 && mips16_hard_float
7103 && ! aggregate_value_p (return_type, current_function_decl)
7104 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7105 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7108 if (cfun->machine->frame.initialized)
7109 return cfun->machine->frame.total_size == 0;
7111 return compute_frame_size (get_frame_size ()) == 0;
7114 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7115 in order to avoid duplicating too much logic from elsewhere. */
7118 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7119 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7122 rtx this, temp1, temp2, insn, fnaddr;
7124 /* Pretend to be a post-reload pass while generating rtl. */
7126 reload_completed = 1;
7127 reset_block_changes ();
7129 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7130 for TARGET_NEWABI since the latter is a call-saved register. */
7131 if (TARGET_ABICALLS)
7132 cfun->machine->global_pointer
7133 = REGNO (pic_offset_table_rtx)
7134 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7136 /* Set up the global pointer for n32 or n64 abicalls. */
7137 mips_emit_loadgp ();
7139 /* We need two temporary registers in some cases. */
7140 temp1 = gen_rtx_REG (Pmode, 2);
7141 temp2 = gen_rtx_REG (Pmode, 3);
7143 /* Find out which register contains the "this" pointer. */
7144 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7145 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7147 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7149 /* Add DELTA to THIS. */
7152 rtx offset = GEN_INT (delta);
7153 if (!SMALL_OPERAND (delta))
7155 emit_move_insn (temp1, offset);
7158 emit_insn (gen_add3_insn (this, this, offset));
7161 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7162 if (vcall_offset != 0)
7166 /* Set TEMP1 to *THIS. */
7167 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7169 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7170 addr = mips_add_offset (temp2, temp1, vcall_offset);
7172 /* Load the offset and add it to THIS. */
7173 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7174 emit_insn (gen_add3_insn (this, this, temp1));
7177 /* Jump to the target function. Use a sibcall if direct jumps are
7178 allowed, otherwise load the address into a register first. */
7179 fnaddr = XEXP (DECL_RTL (function), 0);
7180 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7182 /* This is messy. gas treats "la $25,foo" as part of a call
7183 sequence and may allow a global "foo" to be lazily bound.
7184 The general move patterns therefore reject this combination.
7186 In this context, lazy binding would actually be OK for o32 and o64,
7187 but it's still wrong for n32 and n64; see mips_load_call_address.
7188 We must therefore load the address via a temporary register if
7189 mips_dangerous_for_la25_p.
7191 If we jump to the temporary register rather than $25, the assembler
7192 can use the move insn to fill the jump's delay slot. */
7193 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7194 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7195 mips_load_call_address (temp1, fnaddr, true);
7197 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7198 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7199 emit_jump_insn (gen_indirect_jump (temp1));
7203 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7204 SIBLING_CALL_P (insn) = 1;
7207 /* Run just enough of rest_of_compilation. This sequence was
7208 "borrowed" from alpha.c. */
7209 insn = get_insns ();
7210 insn_locators_initialize ();
7211 split_all_insns_noflow ();
7213 mips16_lay_out_constants ();
7214 shorten_branches (insn);
7215 final_start_function (insn, file, 1);
7216 final (insn, file, 1);
7217 final_end_function ();
7219 /* Clean up the vars set above. Note that final_end_function resets
7220 the global pointer for us. */
7221 reload_completed = 0;
7225 /* Returns nonzero if X contains a SYMBOL_REF. */
7228 symbolic_expression_p (rtx x)
7230 if (GET_CODE (x) == SYMBOL_REF)
7233 if (GET_CODE (x) == CONST)
7234 return symbolic_expression_p (XEXP (x, 0));
7237 return symbolic_expression_p (XEXP (x, 0));
7239 if (ARITHMETIC_P (x))
7240 return (symbolic_expression_p (XEXP (x, 0))
7241 || symbolic_expression_p (XEXP (x, 1)));
7246 /* Choose the section to use for the constant rtx expression X that has
7250 mips_select_rtx_section (enum machine_mode mode, rtx x,
7251 unsigned HOST_WIDE_INT align)
7255 /* In mips16 mode, the constant table always goes in the same section
7256 as the function, so that constants can be loaded using PC relative
7258 return function_section (current_function_decl);
7260 else if (TARGET_EMBEDDED_DATA)
7262 /* For embedded applications, always put constants in read-only data,
7263 in order to reduce RAM usage. */
7264 return mergeable_constant_section (mode, align, 0);
7268 /* For hosted applications, always put constants in small data if
7269 possible, as this gives the best performance. */
7270 /* ??? Consider using mergeable small data sections. */
7272 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7273 && mips_section_threshold > 0)
7274 return get_named_section (NULL, ".sdata", 0);
7275 else if (flag_pic && symbolic_expression_p (x))
7276 return get_named_section (NULL, ".data.rel.ro", 3);
7278 return mergeable_constant_section (mode, align, 0);
7282 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7284 The complication here is that, with the combination TARGET_ABICALLS
7285 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7286 therefore not be included in the read-only part of a DSO. Handle such
7287 cases by selecting a normal data section instead of a read-only one.
7288 The logic apes that in default_function_rodata_section. */
7291 mips_function_rodata_section (tree decl)
7293 if (!TARGET_ABICALLS || TARGET_GPWORD)
7294 return default_function_rodata_section (decl);
7296 if (decl && DECL_SECTION_NAME (decl))
7298 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7299 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7301 char *rname = ASTRDUP (name);
7303 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7305 else if (flag_function_sections && flag_data_sections
7306 && strncmp (name, ".text.", 6) == 0)
7308 char *rname = ASTRDUP (name);
7309 memcpy (rname + 1, "data", 4);
7310 return get_section (rname, SECTION_WRITE, decl);
7313 return data_section;
7316 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7317 access DECL using %gp_rel(...)($gp). */
7320 mips_in_small_data_p (tree decl)
7324 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7327 /* We don't yet generate small-data references for -mabicalls. See related
7328 -G handling in override_options. */
7329 if (TARGET_ABICALLS)
7332 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7336 /* Reject anything that isn't in a known small-data section. */
7337 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7338 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7341 /* If a symbol is defined externally, the assembler will use the
7342 usual -G rules when deciding how to implement macros. */
7343 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7346 else if (TARGET_EMBEDDED_DATA)
7348 /* Don't put constants into the small data section: we want them
7349 to be in ROM rather than RAM. */
7350 if (TREE_CODE (decl) != VAR_DECL)
7353 if (TREE_READONLY (decl)
7354 && !TREE_SIDE_EFFECTS (decl)
7355 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7359 size = int_size_in_bytes (TREE_TYPE (decl));
7360 return (size > 0 && size <= mips_section_threshold);
7363 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7364 anchors for small data: the GP register acts as an anchor in that
7365 case. We also don't want to use them for PC-relative accesses,
7366 where the PC acts as an anchor. */
7369 mips_use_anchors_for_symbol_p (rtx symbol)
7371 switch (mips_classify_symbol (symbol))
7373 case SYMBOL_CONSTANT_POOL:
7374 case SYMBOL_SMALL_DATA:
7382 /* See whether VALTYPE is a record whose fields should be returned in
7383 floating-point registers. If so, return the number of fields and
7384 list them in FIELDS (which should have two elements). Return 0
7387 For n32 & n64, a structure with one or two fields is returned in
7388 floating-point registers as long as every field has a floating-point
7392 mips_fpr_return_fields (tree valtype, tree *fields)
7400 if (TREE_CODE (valtype) != RECORD_TYPE)
7404 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7406 if (TREE_CODE (field) != FIELD_DECL)
7409 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7415 fields[i++] = field;
7421 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7422 a value in the most significant part of $2/$3 if:
7424 - the target is big-endian;
7426 - the value has a structure or union type (we generalize this to
7427 cover aggregates from other languages too); and
7429 - the structure is not returned in floating-point registers. */
7432 mips_return_in_msb (tree valtype)
7436 return (TARGET_NEWABI
7437 && TARGET_BIG_ENDIAN
7438 && AGGREGATE_TYPE_P (valtype)
7439 && mips_fpr_return_fields (valtype, fields) == 0);
7443 /* Return a composite value in a pair of floating-point registers.
7444 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7445 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7448 For n32 & n64, $f0 always holds the first value and $f2 the second.
7449 Otherwise the values are packed together as closely as possible. */
7452 mips_return_fpr_pair (enum machine_mode mode,
7453 enum machine_mode mode1, HOST_WIDE_INT offset1,
7454 enum machine_mode mode2, HOST_WIDE_INT offset2)
7458 inc = (TARGET_NEWABI ? 2 : FP_INC);
7459 return gen_rtx_PARALLEL
7462 gen_rtx_EXPR_LIST (VOIDmode,
7463 gen_rtx_REG (mode1, FP_RETURN),
7465 gen_rtx_EXPR_LIST (VOIDmode,
7466 gen_rtx_REG (mode2, FP_RETURN + inc),
7467 GEN_INT (offset2))));
7472 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7473 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7474 VALTYPE is null and MODE is the mode of the return value. */
7477 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7478 enum machine_mode mode)
7485 mode = TYPE_MODE (valtype);
7486 unsignedp = TYPE_UNSIGNED (valtype);
7488 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7489 true, we must promote the mode just as PROMOTE_MODE does. */
7490 mode = promote_mode (valtype, mode, &unsignedp, 1);
7492 /* Handle structures whose fields are returned in $f0/$f2. */
7493 switch (mips_fpr_return_fields (valtype, fields))
7496 return gen_rtx_REG (mode, FP_RETURN);
7499 return mips_return_fpr_pair (mode,
7500 TYPE_MODE (TREE_TYPE (fields[0])),
7501 int_byte_position (fields[0]),
7502 TYPE_MODE (TREE_TYPE (fields[1])),
7503 int_byte_position (fields[1]));
7506 /* If a value is passed in the most significant part of a register, see
7507 whether we have to round the mode up to a whole number of words. */
7508 if (mips_return_in_msb (valtype))
7510 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7511 if (size % UNITS_PER_WORD != 0)
7513 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7514 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7518 /* For EABI, the class of return register depends entirely on MODE.
7519 For example, "struct { some_type x; }" and "union { some_type x; }"
7520 are returned in the same way as a bare "some_type" would be.
7521 Other ABIs only use FPRs for scalar, complex or vector types. */
7522 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7523 return gen_rtx_REG (mode, GP_RETURN);
7526 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7527 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7528 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7529 return gen_rtx_REG (mode, FP_RETURN);
7531 /* Handle long doubles for n32 & n64. */
7533 return mips_return_fpr_pair (mode,
7535 DImode, GET_MODE_SIZE (mode) / 2);
7537 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7538 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7539 return mips_return_fpr_pair (mode,
7540 GET_MODE_INNER (mode), 0,
7541 GET_MODE_INNER (mode),
7542 GET_MODE_SIZE (mode) / 2);
7544 return gen_rtx_REG (mode, GP_RETURN);
7547 /* Return nonzero when an argument must be passed by reference. */
7550 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7551 enum machine_mode mode, tree type,
7552 bool named ATTRIBUTE_UNUSED)
7554 if (mips_abi == ABI_EABI)
7558 /* ??? How should SCmode be handled? */
7559 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7562 size = int_size_in_bytes (type);
7563 return size == -1 || size > UNITS_PER_WORD;
7567 /* If we have a variable-sized parameter, we have no choice. */
7568 return targetm.calls.must_pass_in_stack (mode, type);
7573 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7574 enum machine_mode mode ATTRIBUTE_UNUSED,
7575 tree type ATTRIBUTE_UNUSED, bool named)
7577 return mips_abi == ABI_EABI && named;
7580 /* Return true if registers of class CLASS cannot change from mode FROM
7584 mips_cannot_change_mode_class (enum machine_mode from,
7585 enum machine_mode to, enum reg_class class)
7587 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7588 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7590 if (TARGET_BIG_ENDIAN)
7592 /* When a multi-word value is stored in paired floating-point
7593 registers, the first register always holds the low word.
7594 We therefore can't allow FPRs to change between single-word
7595 and multi-word modes. */
7596 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7601 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7602 in LO and HI, the high word always comes first. We therefore
7603 can't allow values stored in HI to change between single-word
7604 and multi-word modes.
7605 This rule applies to both the original HI/LO pair and the new
7606 DSP accumulators. */
7607 if (reg_classes_intersect_p (ACC_REGS, class))
7611 /* Loading a 32-bit value into a 64-bit floating-point register
7612 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7613 We can't allow 64-bit float registers to change from SImode to
7617 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7618 && reg_classes_intersect_p (FP_REGS, class))
7623 /* Return true if X should not be moved directly into register $25.
7624 We need this because many versions of GAS will treat "la $25,foo" as
7625 part of a call sequence and so allow a global "foo" to be lazily bound. */
7628 mips_dangerous_for_la25_p (rtx x)
7630 HOST_WIDE_INT offset;
7632 if (TARGET_EXPLICIT_RELOCS)
7635 mips_split_const (x, &x, &offset);
7636 return global_got_operand (x, VOIDmode);
7639 /* Implement PREFERRED_RELOAD_CLASS. */
7642 mips_preferred_reload_class (rtx x, enum reg_class class)
7644 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7647 if (TARGET_HARD_FLOAT
7648 && FLOAT_MODE_P (GET_MODE (x))
7649 && reg_class_subset_p (FP_REGS, class))
7652 if (reg_class_subset_p (GR_REGS, class))
7655 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7661 /* This function returns the register class required for a secondary
7662 register when copying between one of the registers in CLASS, and X,
7663 using MODE. If IN_P is nonzero, the copy is going from X to the
7664 register, otherwise the register is the source. A return value of
7665 NO_REGS means that no secondary register is required. */
7668 mips_secondary_reload_class (enum reg_class class,
7669 enum machine_mode mode, rtx x, int in_p)
7671 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7675 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7676 regno = true_regnum (x);
7678 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7680 if (mips_dangerous_for_la25_p (x))
7683 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7687 /* Copying from HI or LO to anywhere other than a general register
7688 requires a general register.
7689 This rule applies to both the original HI/LO pair and the new
7690 DSP accumulators. */
7691 if (reg_class_subset_p (class, ACC_REGS))
7693 if (TARGET_MIPS16 && in_p)
7695 /* We can't really copy to HI or LO at all in mips16 mode. */
7698 return gp_reg_p ? NO_REGS : gr_regs;
7700 if (ACC_REG_P (regno))
7702 if (TARGET_MIPS16 && ! in_p)
7704 /* We can't really copy to HI or LO at all in mips16 mode. */
7707 return class == gr_regs ? NO_REGS : gr_regs;
7710 /* We can only copy a value to a condition code register from a
7711 floating point register, and even then we require a scratch
7712 floating point register. We can only copy a value out of a
7713 condition code register into a general register. */
7714 if (class == ST_REGS)
7718 return gp_reg_p ? NO_REGS : gr_regs;
7720 if (ST_REG_P (regno))
7724 return class == gr_regs ? NO_REGS : gr_regs;
7727 if (class == FP_REGS)
7731 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7734 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7736 /* We can use the l.s and l.d macros to load floating-point
7737 constants. ??? For l.s, we could probably get better
7738 code by returning GR_REGS here. */
7741 else if (gp_reg_p || x == CONST0_RTX (mode))
7743 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7746 else if (FP_REG_P (regno))
7748 /* In this case we can use mov.s or mov.d. */
7753 /* Otherwise, we need to reload through an integer register. */
7758 /* In mips16 mode, going between memory and anything but M16_REGS
7759 requires an M16_REG. */
7762 if (class != M16_REGS && class != M16_NA_REGS)
7770 if (class == M16_REGS || class == M16_NA_REGS)
7779 /* Implement CLASS_MAX_NREGS.
7781 Usually all registers are word-sized. The only supported exception
7782 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7783 registers. A word-based calculation is correct even in that case,
7784 since -msingle-float disallows multi-FPR values.
7786 The FP status registers are an exception to this rule. They are always
7787 4 bytes wide as they only hold condition code modes, and CCmode is always
7788 considered to be 4 bytes wide. */
7791 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7792 enum machine_mode mode)
7794 if (class == ST_REGS)
7795 return (GET_MODE_SIZE (mode) + 3) / 4;
7797 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7801 mips_valid_pointer_mode (enum machine_mode mode)
7803 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7806 /* Target hook for vector_mode_supported_p. */
7809 mips_vector_mode_supported_p (enum machine_mode mode)
7814 return TARGET_PAIRED_SINGLE_FLOAT;
7825 /* If we can access small data directly (using gp-relative relocation
7826 operators) return the small data pointer, otherwise return null.
7828 For each mips16 function which refers to GP relative symbols, we
7829 use a pseudo register, initialized at the start of the function, to
7830 hold the $gp value. */
7833 mips16_gp_pseudo_reg (void)
7835 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7840 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7842 /* We want to initialize this to a value which gcc will believe
7845 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7846 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7847 gen_rtx_CONST (Pmode, unspec));
7848 insn = get_insns ();
7851 push_topmost_sequence ();
7852 /* We need to emit the initialization after the FUNCTION_BEG
7853 note, so that it will be integrated. */
7854 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7856 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7858 if (scan == NULL_RTX)
7859 scan = get_insns ();
7860 insn = emit_insn_after (insn, scan);
7861 pop_topmost_sequence ();
7864 return cfun->machine->mips16_gp_pseudo_rtx;
7867 /* Write out code to move floating point arguments in or out of
7868 general registers. Output the instructions to FILE. FP_CODE is
7869 the code describing which arguments are present (see the comment at
7870 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7871 we are copying from the floating point registers. */
7874 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7880 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7881 gcc_assert (TARGET_OLDABI);
7887 gparg = GP_ARG_FIRST;
7888 fparg = FP_ARG_FIRST;
7889 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7893 if ((fparg & 1) != 0)
7895 fprintf (file, "\t%s\t%s,%s\n", s,
7896 reg_names[gparg], reg_names[fparg]);
7898 else if ((f & 3) == 2)
7901 fprintf (file, "\td%s\t%s,%s\n", s,
7902 reg_names[gparg], reg_names[fparg]);
7905 if ((fparg & 1) != 0)
7907 if (TARGET_BIG_ENDIAN)
7908 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7909 reg_names[gparg], reg_names[fparg + 1], s,
7910 reg_names[gparg + 1], reg_names[fparg]);
7912 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7913 reg_names[gparg], reg_names[fparg], s,
7914 reg_names[gparg + 1], reg_names[fparg + 1]);
7927 /* Build a mips16 function stub. This is used for functions which
7928 take arguments in the floating point registers. It is 32 bit code
7929 that moves the floating point args into the general registers, and
7930 then jumps to the 16 bit code. */
7933 build_mips16_function_stub (FILE *file)
7936 char *secname, *stubname;
7937 tree stubid, stubdecl;
7941 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7942 secname = (char *) alloca (strlen (fnname) + 20);
7943 sprintf (secname, ".mips16.fn.%s", fnname);
7944 stubname = (char *) alloca (strlen (fnname) + 20);
7945 sprintf (stubname, "__fn_stub_%s", fnname);
7946 stubid = get_identifier (stubname);
7947 stubdecl = build_decl (FUNCTION_DECL, stubid,
7948 build_function_type (void_type_node, NULL_TREE));
7949 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7951 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7953 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7955 fprintf (file, "%s%s",
7956 need_comma ? ", " : "",
7957 (f & 3) == 1 ? "float" : "double");
7960 fprintf (file, ")\n");
7962 fprintf (file, "\t.set\tnomips16\n");
7963 switch_to_section (function_section (stubdecl));
7964 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7966 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7967 within a .ent, and we cannot emit another .ent. */
7968 if (!FUNCTION_NAME_ALREADY_DECLARED)
7970 fputs ("\t.ent\t", file);
7971 assemble_name (file, stubname);
7975 assemble_name (file, stubname);
7976 fputs (":\n", file);
7978 /* We don't want the assembler to insert any nops here. */
7979 fprintf (file, "\t.set\tnoreorder\n");
7981 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7983 fprintf (asm_out_file, "\t.set\tnoat\n");
7984 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7985 assemble_name (file, fnname);
7986 fprintf (file, "\n");
7987 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7988 fprintf (asm_out_file, "\t.set\tat\n");
7990 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7991 with one of the mfc1 instructions, because the result is not
7992 available for one instruction, so if the very first instruction
7993 in the function refers to the register, it will see the wrong
7995 fprintf (file, "\tnop\n");
7997 fprintf (file, "\t.set\treorder\n");
7999 if (!FUNCTION_NAME_ALREADY_DECLARED)
8001 fputs ("\t.end\t", file);
8002 assemble_name (file, stubname);
8006 fprintf (file, "\t.set\tmips16\n");
8008 switch_to_section (function_section (current_function_decl));
8011 /* We keep a list of functions for which we have already built stubs
8012 in build_mips16_call_stub. */
8016 struct mips16_stub *next;
8021 static struct mips16_stub *mips16_stubs;
8023 /* Build a call stub for a mips16 call. A stub is needed if we are
8024 passing any floating point values which should go into the floating
8025 point registers. If we are, and the call turns out to be to a 32
8026 bit function, the stub will be used to move the values into the
8027 floating point registers before calling the 32 bit function. The
8028 linker will magically adjust the function call to either the 16 bit
8029 function or the 32 bit stub, depending upon where the function call
8030 is actually defined.
8032 Similarly, we need a stub if the return value might come back in a
8033 floating point register.
8035 RETVAL is the location of the return value, or null if this is
8036 a call rather than a call_value. FN is the address of the
8037 function and ARG_SIZE is the size of the arguments. FP_CODE
8038 is the code built by function_arg. This function returns a nonzero
8039 value if it builds the call instruction itself. */
8042 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8046 char *secname, *stubname;
8047 struct mips16_stub *l;
8048 tree stubid, stubdecl;
8052 /* We don't need to do anything if we aren't in mips16 mode, or if
8053 we were invoked with the -msoft-float option. */
8054 if (! TARGET_MIPS16 || ! mips16_hard_float)
8057 /* Figure out whether the value might come back in a floating point
8059 fpret = (retval != 0
8060 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8061 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8063 /* We don't need to do anything if there were no floating point
8064 arguments and the value will not be returned in a floating point
8066 if (fp_code == 0 && ! fpret)
8069 /* We don't need to do anything if this is a call to a special
8070 mips16 support function. */
8071 if (GET_CODE (fn) == SYMBOL_REF
8072 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8075 /* This code will only work for o32 and o64 abis. The other ABI's
8076 require more sophisticated support. */
8077 gcc_assert (TARGET_OLDABI);
8079 /* We can only handle SFmode and DFmode floating point return
8082 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8084 /* If we're calling via a function pointer, then we must always call
8085 via a stub. There are magic stubs provided in libgcc.a for each
8086 of the required cases. Each of them expects the function address
8087 to arrive in register $2. */
8089 if (GET_CODE (fn) != SYMBOL_REF)
8095 /* ??? If this code is modified to support other ABI's, we need
8096 to handle PARALLEL return values here. */
8098 sprintf (buf, "__mips16_call_stub_%s%d",
8100 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8103 id = get_identifier (buf);
8104 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8106 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8108 if (retval == NULL_RTX)
8109 insn = gen_call_internal (stub_fn, arg_size);
8111 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8112 insn = emit_call_insn (insn);
8114 /* Put the register usage information on the CALL. */
8115 CALL_INSN_FUNCTION_USAGE (insn) =
8116 gen_rtx_EXPR_LIST (VOIDmode,
8117 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8118 CALL_INSN_FUNCTION_USAGE (insn));
8120 /* If we are handling a floating point return value, we need to
8121 save $18 in the function prologue. Putting a note on the
8122 call will mean that regs_ever_live[$18] will be true if the
8123 call is not eliminated, and we can check that in the prologue
8126 CALL_INSN_FUNCTION_USAGE (insn) =
8127 gen_rtx_EXPR_LIST (VOIDmode,
8128 gen_rtx_USE (VOIDmode,
8129 gen_rtx_REG (word_mode, 18)),
8130 CALL_INSN_FUNCTION_USAGE (insn));
8132 /* Return 1 to tell the caller that we've generated the call
8137 /* We know the function we are going to call. If we have already
8138 built a stub, we don't need to do anything further. */
8140 fnname = XSTR (fn, 0);
8141 for (l = mips16_stubs; l != NULL; l = l->next)
8142 if (strcmp (l->name, fnname) == 0)
8147 /* Build a special purpose stub. When the linker sees a
8148 function call in mips16 code, it will check where the target
8149 is defined. If the target is a 32 bit call, the linker will
8150 search for the section defined here. It can tell which
8151 symbol this section is associated with by looking at the
8152 relocation information (the name is unreliable, since this
8153 might be a static function). If such a section is found, the
8154 linker will redirect the call to the start of the magic
8157 If the function does not return a floating point value, the
8158 special stub section is named
8161 If the function does return a floating point value, the stub
8163 .mips16.call.fp.FNNAME
8166 secname = (char *) alloca (strlen (fnname) + 40);
8167 sprintf (secname, ".mips16.call.%s%s",
8170 stubname = (char *) alloca (strlen (fnname) + 20);
8171 sprintf (stubname, "__call_stub_%s%s",
8174 stubid = get_identifier (stubname);
8175 stubdecl = build_decl (FUNCTION_DECL, stubid,
8176 build_function_type (void_type_node, NULL_TREE));
8177 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8179 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8181 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8185 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8187 fprintf (asm_out_file, "%s%s",
8188 need_comma ? ", " : "",
8189 (f & 3) == 1 ? "float" : "double");
8192 fprintf (asm_out_file, ")\n");
8194 fprintf (asm_out_file, "\t.set\tnomips16\n");
8195 assemble_start_function (stubdecl, stubname);
8197 if (!FUNCTION_NAME_ALREADY_DECLARED)
8199 fputs ("\t.ent\t", asm_out_file);
8200 assemble_name (asm_out_file, stubname);
8201 fputs ("\n", asm_out_file);
8203 assemble_name (asm_out_file, stubname);
8204 fputs (":\n", asm_out_file);
8207 /* We build the stub code by hand. That's the only way we can
8208 do it, since we can't generate 32 bit code during a 16 bit
8211 /* We don't want the assembler to insert any nops here. */
8212 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8214 mips16_fp_args (asm_out_file, fp_code, 0);
8218 fprintf (asm_out_file, "\t.set\tnoat\n");
8219 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8221 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8222 fprintf (asm_out_file, "\t.set\tat\n");
8223 /* Unfortunately, we can't fill the jump delay slot. We
8224 can't fill with one of the mtc1 instructions, because the
8225 result is not available for one instruction, so if the
8226 very first instruction in the function refers to the
8227 register, it will see the wrong value. */
8228 fprintf (asm_out_file, "\tnop\n");
8232 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8233 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8234 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8235 /* As above, we can't fill the delay slot. */
8236 fprintf (asm_out_file, "\tnop\n");
8237 if (GET_MODE (retval) == SFmode)
8238 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8239 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8242 if (TARGET_BIG_ENDIAN)
8244 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8245 reg_names[GP_REG_FIRST + 2],
8246 reg_names[FP_REG_FIRST + 1]);
8247 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8248 reg_names[GP_REG_FIRST + 3],
8249 reg_names[FP_REG_FIRST + 0]);
8253 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8254 reg_names[GP_REG_FIRST + 2],
8255 reg_names[FP_REG_FIRST + 0]);
8256 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8257 reg_names[GP_REG_FIRST + 3],
8258 reg_names[FP_REG_FIRST + 1]);
8261 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8262 /* As above, we can't fill the delay slot. */
8263 fprintf (asm_out_file, "\tnop\n");
8266 fprintf (asm_out_file, "\t.set\treorder\n");
8268 #ifdef ASM_DECLARE_FUNCTION_SIZE
8269 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8272 if (!FUNCTION_NAME_ALREADY_DECLARED)
8274 fputs ("\t.end\t", asm_out_file);
8275 assemble_name (asm_out_file, stubname);
8276 fputs ("\n", asm_out_file);
8279 fprintf (asm_out_file, "\t.set\tmips16\n");
8281 /* Record this stub. */
8282 l = (struct mips16_stub *) xmalloc (sizeof *l);
8283 l->name = xstrdup (fnname);
8285 l->next = mips16_stubs;
8289 /* If we expect a floating point return value, but we've built a
8290 stub which does not expect one, then we're in trouble. We can't
8291 use the existing stub, because it won't handle the floating point
8292 value. We can't build a new stub, because the linker won't know
8293 which stub to use for the various calls in this object file.
8294 Fortunately, this case is illegal, since it means that a function
8295 was declared in two different ways in a single compilation. */
8296 if (fpret && ! l->fpret)
8297 error ("cannot handle inconsistent calls to %qs", fnname);
8299 /* If we are calling a stub which handles a floating point return
8300 value, we need to arrange to save $18 in the prologue. We do
8301 this by marking the function call as using the register. The
8302 prologue will later see that it is used, and emit code to save
8309 if (retval == NULL_RTX)
8310 insn = gen_call_internal (fn, arg_size);
8312 insn = gen_call_value_internal (retval, fn, arg_size);
8313 insn = emit_call_insn (insn);
8315 CALL_INSN_FUNCTION_USAGE (insn) =
8316 gen_rtx_EXPR_LIST (VOIDmode,
8317 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8318 CALL_INSN_FUNCTION_USAGE (insn));
8320 /* Return 1 to tell the caller that we've generated the call
8325 /* Return 0 to let the caller generate the call insn. */
8329 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8330 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8332 struct mips16_constant {
8333 struct mips16_constant *next;
8336 enum machine_mode mode;
8339 /* Information about an incomplete mips16 constant pool. FIRST is the
8340 first constant, HIGHEST_ADDRESS is the highest address that the first
8341 byte of the pool can have, and INSN_ADDRESS is the current instruction
8344 struct mips16_constant_pool {
8345 struct mips16_constant *first;
8346 int highest_address;
8350 /* Add constant VALUE to POOL and return its label. MODE is the
8351 value's mode (used for CONST_INTs, etc.). */
8354 add_constant (struct mips16_constant_pool *pool,
8355 rtx value, enum machine_mode mode)
8357 struct mips16_constant **p, *c;
8358 bool first_of_size_p;
8360 /* See whether the constant is already in the pool. If so, return the
8361 existing label, otherwise leave P pointing to the place where the
8362 constant should be added.
8364 Keep the pool sorted in increasing order of mode size so that we can
8365 reduce the number of alignments needed. */
8366 first_of_size_p = true;
8367 for (p = &pool->first; *p != 0; p = &(*p)->next)
8369 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8371 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8373 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8374 first_of_size_p = false;
8377 /* In the worst case, the constant needed by the earliest instruction
8378 will end up at the end of the pool. The entire pool must then be
8379 accessible from that instruction.
8381 When adding the first constant, set the pool's highest address to
8382 the address of the first out-of-range byte. Adjust this address
8383 downwards each time a new constant is added. */
8384 if (pool->first == 0)
8385 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8386 is the address of the instruction with the lowest two bits clear.
8387 The base PC value for ld has the lowest three bits clear. Assume
8388 the worst case here. */
8389 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8390 pool->highest_address -= GET_MODE_SIZE (mode);
8391 if (first_of_size_p)
8392 /* Take into account the worst possible padding due to alignment. */
8393 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8395 /* Create a new entry. */
8396 c = (struct mips16_constant *) xmalloc (sizeof *c);
8399 c->label = gen_label_rtx ();
8406 /* Output constant VALUE after instruction INSN and return the last
8407 instruction emitted. MODE is the mode of the constant. */
8410 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8412 switch (GET_MODE_CLASS (mode))
8416 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8417 return emit_insn_after (gen_consttable_int (value, size), insn);
8421 return emit_insn_after (gen_consttable_float (value), insn);
8423 case MODE_VECTOR_FLOAT:
8424 case MODE_VECTOR_INT:
8427 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8428 insn = dump_constants_1 (GET_MODE_INNER (mode),
8429 CONST_VECTOR_ELT (value, i), insn);
8439 /* Dump out the constants in CONSTANTS after INSN. */
8442 dump_constants (struct mips16_constant *constants, rtx insn)
8444 struct mips16_constant *c, *next;
8448 for (c = constants; c != NULL; c = next)
8450 /* If necessary, increase the alignment of PC. */
8451 if (align < GET_MODE_SIZE (c->mode))
8453 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8454 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8456 align = GET_MODE_SIZE (c->mode);
8458 insn = emit_label_after (c->label, insn);
8459 insn = dump_constants_1 (c->mode, c->value, insn);
8465 emit_barrier_after (insn);
8468 /* Return the length of instruction INSN. */
8471 mips16_insn_length (rtx insn)
8475 rtx body = PATTERN (insn);
8476 if (GET_CODE (body) == ADDR_VEC)
8477 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8478 if (GET_CODE (body) == ADDR_DIFF_VEC)
8479 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8481 return get_attr_length (insn);
8484 /* Rewrite *X so that constant pool references refer to the constant's
8485 label instead. DATA points to the constant pool structure. */
8488 mips16_rewrite_pool_refs (rtx *x, void *data)
8490 struct mips16_constant_pool *pool = data;
8491 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8492 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8493 get_pool_constant (*x),
8494 get_pool_mode (*x)));
8498 /* Build MIPS16 constant pools. */
8501 mips16_lay_out_constants (void)
8503 struct mips16_constant_pool pool;
8507 memset (&pool, 0, sizeof (pool));
8508 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8510 /* Rewrite constant pool references in INSN. */
8512 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8514 pool.insn_address += mips16_insn_length (insn);
8516 if (pool.first != NULL)
8518 /* If there are no natural barriers between the first user of
8519 the pool and the highest acceptable address, we'll need to
8520 create a new instruction to jump around the constant pool.
8521 In the worst case, this instruction will be 4 bytes long.
8523 If it's too late to do this transformation after INSN,
8524 do it immediately before INSN. */
8525 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8529 label = gen_label_rtx ();
8531 jump = emit_jump_insn_before (gen_jump (label), insn);
8532 JUMP_LABEL (jump) = label;
8533 LABEL_NUSES (label) = 1;
8534 barrier = emit_barrier_after (jump);
8536 emit_label_after (label, barrier);
8537 pool.insn_address += 4;
8540 /* See whether the constant pool is now out of range of the first
8541 user. If so, output the constants after the previous barrier.
8542 Note that any instructions between BARRIER and INSN (inclusive)
8543 will use negative offsets to refer to the pool. */
8544 if (pool.insn_address > pool.highest_address)
8546 dump_constants (pool.first, barrier);
8550 else if (BARRIER_P (insn))
8554 dump_constants (pool.first, get_last_insn ());
8557 /* A temporary variable used by for_each_rtx callbacks, etc. */
8558 static rtx mips_sim_insn;
8560 /* A structure representing the state of the processor pipeline.
8561 Used by the mips_sim_* family of functions. */
8563 /* The maximum number of instructions that can be issued in a cycle.
8564 (Caches mips_issue_rate.) */
8565 unsigned int issue_rate;
8567 /* The current simulation time. */
8570 /* How many more instructions can be issued in the current cycle. */
8571 unsigned int insns_left;
8573 /* LAST_SET[X].INSN is the last instruction to set register X.
8574 LAST_SET[X].TIME is the time at which that instruction was issued.
8575 INSN is null if no instruction has yet set register X. */
8579 } last_set[FIRST_PSEUDO_REGISTER];
8581 /* The pipeline's current DFA state. */
8585 /* Reset STATE to the initial simulation state. */
8588 mips_sim_reset (struct mips_sim *state)
8591 state->insns_left = state->issue_rate;
8592 memset (&state->last_set, 0, sizeof (state->last_set));
8593 state_reset (state->dfa_state);
8596 /* Initialize STATE before its first use. DFA_STATE points to an
8597 allocated but uninitialized DFA state. */
8600 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8602 state->issue_rate = mips_issue_rate ();
8603 state->dfa_state = dfa_state;
8604 mips_sim_reset (state);
8607 /* Advance STATE by one clock cycle. */
8610 mips_sim_next_cycle (struct mips_sim *state)
8613 state->insns_left = state->issue_rate;
8614 state_transition (state->dfa_state, 0);
8617 /* Advance simulation state STATE until instruction INSN can read
8621 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8625 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8626 if (state->last_set[REGNO (reg) + i].insn != 0)
8630 t = state->last_set[REGNO (reg) + i].time;
8631 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8632 while (state->time < t)
8633 mips_sim_next_cycle (state);
8637 /* A for_each_rtx callback. If *X is a register, advance simulation state
8638 DATA until mips_sim_insn can read the register's value. */
8641 mips_sim_wait_regs_2 (rtx *x, void *data)
8644 mips_sim_wait_reg (data, mips_sim_insn, *x);
8648 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8651 mips_sim_wait_regs_1 (rtx *x, void *data)
8653 for_each_rtx (x, mips_sim_wait_regs_2, data);
8656 /* Advance simulation state STATE until all of INSN's register
8657 dependencies are satisfied. */
8660 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8662 mips_sim_insn = insn;
8663 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8666 /* Advance simulation state STATE until the units required by
8667 instruction INSN are available. */
8670 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8674 tmp_state = alloca (state_size ());
8675 while (state->insns_left == 0
8676 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8677 state_transition (tmp_state, insn) >= 0))
8678 mips_sim_next_cycle (state);
8681 /* Advance simulation state STATE until INSN is ready to issue. */
8684 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8686 mips_sim_wait_regs (state, insn);
8687 mips_sim_wait_units (state, insn);
8690 /* mips_sim_insn has just set X. Update the LAST_SET array
8691 in simulation state DATA. */
8694 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8696 struct mips_sim *state;
8701 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8703 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8704 state->last_set[REGNO (x) + i].time = state->time;
8708 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8709 can issue immediately (i.e., that mips_sim_wait_insn has already
8713 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8715 state_transition (state->dfa_state, insn);
8716 state->insns_left--;
8718 mips_sim_insn = insn;
8719 note_stores (PATTERN (insn), mips_sim_record_set, state);
8722 /* Simulate issuing a NOP in state STATE. */
8725 mips_sim_issue_nop (struct mips_sim *state)
8727 if (state->insns_left == 0)
8728 mips_sim_next_cycle (state);
8729 state->insns_left--;
8732 /* Update simulation state STATE so that it's ready to accept the instruction
8733 after INSN. INSN should be part of the main rtl chain, not a member of a
8737 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8739 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8741 mips_sim_issue_nop (state);
8743 switch (GET_CODE (SEQ_BEGIN (insn)))
8747 /* We can't predict the processor state after a call or label. */
8748 mips_sim_reset (state);
8752 /* The delay slots of branch likely instructions are only executed
8753 when the branch is taken. Therefore, if the caller has simulated
8754 the delay slot instruction, STATE does not really reflect the state
8755 of the pipeline for the instruction after the delay slot. Also,
8756 branch likely instructions tend to incur a penalty when not taken,
8757 so there will probably be an extra delay between the branch and
8758 the instruction after the delay slot. */
8759 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8760 mips_sim_reset (state);
8768 /* The VR4130 pipeline issues aligned pairs of instructions together,
8769 but it stalls the second instruction if it depends on the first.
8770 In order to cut down the amount of logic required, this dependence
8771 check is not based on a full instruction decode. Instead, any non-SPECIAL
8772 instruction is assumed to modify the register specified by bits 20-16
8773 (which is usually the "rt" field).
8775 In beq, beql, bne and bnel instructions, the rt field is actually an
8776 input, so we can end up with a false dependence between the branch
8777 and its delay slot. If this situation occurs in instruction INSN,
8778 try to avoid it by swapping rs and rt. */
8781 vr4130_avoid_branch_rt_conflict (rtx insn)
8785 first = SEQ_BEGIN (insn);
8786 second = SEQ_END (insn);
8788 && NONJUMP_INSN_P (second)
8789 && GET_CODE (PATTERN (first)) == SET
8790 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8791 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8793 /* Check for the right kind of condition. */
8794 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8795 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8796 && REG_P (XEXP (cond, 0))
8797 && REG_P (XEXP (cond, 1))
8798 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8799 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8801 /* SECOND mentions the rt register but not the rs register. */
8802 rtx tmp = XEXP (cond, 0);
8803 XEXP (cond, 0) = XEXP (cond, 1);
8804 XEXP (cond, 1) = tmp;
8809 /* Implement -mvr4130-align. Go through each basic block and simulate the
8810 processor pipeline. If we find that a pair of instructions could execute
8811 in parallel, and the first of those instruction is not 8-byte aligned,
8812 insert a nop to make it aligned. */
8815 vr4130_align_insns (void)
8817 struct mips_sim state;
8818 rtx insn, subinsn, last, last2, next;
8823 /* LAST is the last instruction before INSN to have a nonzero length.
8824 LAST2 is the last such instruction before LAST. */
8828 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8831 mips_sim_init (&state, alloca (state_size ()));
8832 for (insn = get_insns (); insn != 0; insn = next)
8834 unsigned int length;
8836 next = NEXT_INSN (insn);
8838 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8839 This isn't really related to the alignment pass, but we do it on
8840 the fly to avoid a separate instruction walk. */
8841 vr4130_avoid_branch_rt_conflict (insn);
8843 if (USEFUL_INSN_P (insn))
8844 FOR_EACH_SUBINSN (subinsn, insn)
8846 mips_sim_wait_insn (&state, subinsn);
8848 /* If we want this instruction to issue in parallel with the
8849 previous one, make sure that the previous instruction is
8850 aligned. There are several reasons why this isn't worthwhile
8851 when the second instruction is a call:
8853 - Calls are less likely to be performance critical,
8854 - There's a good chance that the delay slot can execute
8855 in parallel with the call.
8856 - The return address would then be unaligned.
8858 In general, if we're going to insert a nop between instructions
8859 X and Y, it's better to insert it immediately after X. That
8860 way, if the nop makes Y aligned, it will also align any labels
8862 if (state.insns_left != state.issue_rate
8863 && !CALL_P (subinsn))
8865 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8867 /* SUBINSN is the first instruction in INSN and INSN is
8868 aligned. We want to align the previous instruction
8869 instead, so insert a nop between LAST2 and LAST.
8871 Note that LAST could be either a single instruction
8872 or a branch with a delay slot. In the latter case,
8873 LAST, like INSN, is already aligned, but the delay
8874 slot must have some extra delay that stops it from
8875 issuing at the same time as the branch. We therefore
8876 insert a nop before the branch in order to align its
8878 emit_insn_after (gen_nop (), last2);
8881 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8883 /* SUBINSN is the delay slot of INSN, but INSN is
8884 currently unaligned. Insert a nop between
8885 LAST and INSN to align it. */
8886 emit_insn_after (gen_nop (), last);
8890 mips_sim_issue_insn (&state, subinsn);
8892 mips_sim_finish_insn (&state, insn);
8894 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8895 length = get_attr_length (insn);
8898 /* If the instruction is an asm statement or multi-instruction
8899 mips.md patern, the length is only an estimate. Insert an
8900 8 byte alignment after it so that the following instructions
8901 can be handled correctly. */
8902 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8903 && (recog_memoized (insn) < 0 || length >= 8))
8905 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8906 next = NEXT_INSN (next);
8907 mips_sim_next_cycle (&state);
8910 else if (length & 4)
8911 aligned_p = !aligned_p;
8916 /* See whether INSN is an aligned label. */
8917 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8923 /* Subroutine of mips_reorg. If there is a hazard between INSN
8924 and a previous instruction, avoid it by inserting nops after
8927 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8928 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8929 before using the value of that register. *HILO_DELAY counts the
8930 number of instructions since the last hilo hazard (that is,
8931 the number of instructions since the last mflo or mfhi).
8933 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8934 for the next instruction.
8936 LO_REG is an rtx for the LO register, used in dependence checking. */
8939 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8940 rtx *delayed_reg, rtx lo_reg)
8948 pattern = PATTERN (insn);
8950 /* Do not put the whole function in .set noreorder if it contains
8951 an asm statement. We don't know whether there will be hazards
8952 between the asm statement and the gcc-generated code. */
8953 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8954 cfun->machine->all_noreorder_p = false;
8956 /* Ignore zero-length instructions (barriers and the like). */
8957 ninsns = get_attr_length (insn) / 4;
8961 /* Work out how many nops are needed. Note that we only care about
8962 registers that are explicitly mentioned in the instruction's pattern.
8963 It doesn't matter that calls use the argument registers or that they
8964 clobber hi and lo. */
8965 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8966 nops = 2 - *hilo_delay;
8967 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8972 /* Insert the nops between this instruction and the previous one.
8973 Each new nop takes us further from the last hilo hazard. */
8974 *hilo_delay += nops;
8976 emit_insn_after (gen_hazard_nop (), after);
8978 /* Set up the state for the next instruction. */
8979 *hilo_delay += ninsns;
8981 if (INSN_CODE (insn) >= 0)
8982 switch (get_attr_hazard (insn))
8992 set = single_set (insn);
8993 gcc_assert (set != 0);
8994 *delayed_reg = SET_DEST (set);
9000 /* Go through the instruction stream and insert nops where necessary.
9001 See if the whole function can then be put into .set noreorder &
9005 mips_avoid_hazards (void)
9007 rtx insn, last_insn, lo_reg, delayed_reg;
9010 /* Force all instructions to be split into their final form. */
9011 split_all_insns_noflow ();
9013 /* Recalculate instruction lengths without taking nops into account. */
9014 cfun->machine->ignore_hazard_length_p = true;
9015 shorten_branches (get_insns ());
9017 cfun->machine->all_noreorder_p = true;
9019 /* Profiled functions can't be all noreorder because the profiler
9020 support uses assembler macros. */
9021 if (current_function_profile)
9022 cfun->machine->all_noreorder_p = false;
9024 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9025 we rely on the assembler to work around some errata. */
9026 if (TARGET_FIX_VR4120)
9027 cfun->machine->all_noreorder_p = false;
9029 /* The same is true for -mfix-vr4130 if we might generate mflo or
9030 mfhi instructions. Note that we avoid using mflo and mfhi if
9031 the VR4130 macc and dmacc instructions are available instead;
9032 see the *mfhilo_{si,di}_macc patterns. */
9033 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9034 cfun->machine->all_noreorder_p = false;
9039 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9041 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9044 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9045 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9046 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9047 &hilo_delay, &delayed_reg, lo_reg);
9049 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9050 &delayed_reg, lo_reg);
9057 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9063 mips16_lay_out_constants ();
9064 else if (TARGET_EXPLICIT_RELOCS)
9066 if (mips_flag_delayed_branch)
9067 dbr_schedule (get_insns ());
9068 mips_avoid_hazards ();
9069 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9070 vr4130_align_insns ();
9074 /* This function does three things:
9076 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9077 - Register the mips16 hardware floating point stubs.
9078 - Register the gofast functions if selected using --enable-gofast. */
9080 #include "config/gofast.h"
9083 mips_init_libfuncs (void)
9085 if (TARGET_FIX_VR4120)
9087 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9088 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9091 if (TARGET_MIPS16 && mips16_hard_float)
9093 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9094 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9095 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9096 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9098 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9099 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9100 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9101 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9102 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9103 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9105 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9106 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9108 if (TARGET_DOUBLE_FLOAT)
9110 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9111 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9112 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9113 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9115 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9116 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9117 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9118 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9119 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9120 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9122 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9123 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9125 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9126 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9130 gofast_maybe_init_libfuncs ();
9133 /* Return a number assessing the cost of moving a register in class
9134 FROM to class TO. The classes are expressed using the enumeration
9135 values such as `GENERAL_REGS'. A value of 2 is the default; other
9136 values are interpreted relative to that.
9138 It is not required that the cost always equal 2 when FROM is the
9139 same as TO; on some machines it is expensive to move between
9140 registers if they are not general registers.
9142 If reload sees an insn consisting of a single `set' between two
9143 hard registers, and if `REGISTER_MOVE_COST' applied to their
9144 classes returns a value of 2, reload does not check to ensure that
9145 the constraints of the insn are met. Setting a cost of other than
9146 2 will allow reload to verify that the constraints are met. You
9147 should do this if the `movM' pattern's constraints do not allow
9150 ??? We make the cost of moving from HI/LO into general
9151 registers the same as for one of moving general registers to
9152 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9153 pseudo to HI/LO. This might hurt optimizations though, it
9154 isn't clear if it is wise. And it might not work in all cases. We
9155 could solve the DImode LO reg problem by using a multiply, just
9156 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9157 problem by using divide instructions. divu puts the remainder in
9158 the HI reg, so doing a divide by -1 will move the value in the HI
9159 reg for all values except -1. We could handle that case by using a
9160 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9161 a compare/branch to test the input value to see which instruction
9162 we need to use. This gets pretty messy, but it is feasible. */
9165 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9166 enum reg_class to, enum reg_class from)
9168 if (from == M16_REGS && GR_REG_CLASS_P (to))
9170 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9172 else if (GR_REG_CLASS_P (from))
9176 else if (to == M16_NA_REGS)
9178 else if (GR_REG_CLASS_P (to))
9185 else if (to == FP_REGS)
9187 else if (reg_class_subset_p (to, ACC_REGS))
9194 else if (COP_REG_CLASS_P (to))
9199 else if (from == FP_REGS)
9201 if (GR_REG_CLASS_P (to))
9203 else if (to == FP_REGS)
9205 else if (to == ST_REGS)
9208 else if (reg_class_subset_p (from, ACC_REGS))
9210 if (GR_REG_CLASS_P (to))
9218 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9220 else if (COP_REG_CLASS_P (from))
9226 ??? What cases are these? Shouldn't we return 2 here? */
9231 /* Return the length of INSN. LENGTH is the initial length computed by
9232 attributes in the machine-description file. */
9235 mips_adjust_insn_length (rtx insn, int length)
9237 /* A unconditional jump has an unfilled delay slot if it is not part
9238 of a sequence. A conditional jump normally has a delay slot, but
9239 does not on MIPS16. */
9240 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9243 /* See how many nops might be needed to avoid hardware hazards. */
9244 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9245 switch (get_attr_hazard (insn))
9259 /* All MIPS16 instructions are a measly two bytes. */
9267 /* Return an asm sequence to start a noat block and load the address
9268 of a label into $1. */
9271 mips_output_load_label (void)
9273 if (TARGET_EXPLICIT_RELOCS)
9277 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9280 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9283 if (ISA_HAS_LOAD_DELAY)
9284 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9285 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9289 if (Pmode == DImode)
9290 return "%[dla\t%@,%0";
9292 return "%[la\t%@,%0";
9296 /* Return the assembly code for INSN, which has the operands given by
9297 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9298 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9299 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9300 version of BRANCH_IF_TRUE. */
9303 mips_output_conditional_branch (rtx insn, rtx *operands,
9304 const char *branch_if_true,
9305 const char *branch_if_false)
9307 unsigned int length;
9308 rtx taken, not_taken;
9310 length = get_attr_length (insn);
9313 /* Just a simple conditional branch. */
9314 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9315 return branch_if_true;
9318 /* Generate a reversed branch around a direct jump. This fallback does
9319 not use branch-likely instructions. */
9320 mips_branch_likely = false;
9321 not_taken = gen_label_rtx ();
9322 taken = operands[1];
9324 /* Generate the reversed branch to NOT_TAKEN. */
9325 operands[1] = not_taken;
9326 output_asm_insn (branch_if_false, operands);
9328 /* If INSN has a delay slot, we must provide delay slots for both the
9329 branch to NOT_TAKEN and the conditional jump. We must also ensure
9330 that INSN's delay slot is executed in the appropriate cases. */
9333 /* This first delay slot will always be executed, so use INSN's
9334 delay slot if is not annulled. */
9335 if (!INSN_ANNULLED_BRANCH_P (insn))
9337 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9338 asm_out_file, optimize, 1, NULL);
9339 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9342 output_asm_insn ("nop", 0);
9343 fprintf (asm_out_file, "\n");
9346 /* Output the unconditional branch to TAKEN. */
9348 output_asm_insn ("j\t%0%/", &taken);
9351 output_asm_insn (mips_output_load_label (), &taken);
9352 output_asm_insn ("jr\t%@%]%/", 0);
9355 /* Now deal with its delay slot; see above. */
9358 /* This delay slot will only be executed if the branch is taken.
9359 Use INSN's delay slot if is annulled. */
9360 if (INSN_ANNULLED_BRANCH_P (insn))
9362 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9363 asm_out_file, optimize, 1, NULL);
9364 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9367 output_asm_insn ("nop", 0);
9368 fprintf (asm_out_file, "\n");
9371 /* Output NOT_TAKEN. */
9372 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9373 CODE_LABEL_NUMBER (not_taken));
9377 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9378 if some ordered condition is true. The condition is given by
9379 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9380 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9381 its second is always zero. */
9384 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9386 const char *branch[2];
9388 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9389 Make BRANCH[0] branch on the inverse condition. */
9390 switch (GET_CODE (operands[0]))
9392 /* These cases are equivalent to comparisons against zero. */
9394 inverted_p = !inverted_p;
9397 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9398 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9401 /* These cases are always true or always false. */
9403 inverted_p = !inverted_p;
9406 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9407 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9411 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9412 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9415 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9418 /* Used to output div or ddiv instruction DIVISION, which has the operands
9419 given by OPERANDS. Add in a divide-by-zero check if needed.
9421 When working around R4000 and R4400 errata, we need to make sure that
9422 the division is not immediately followed by a shift[1][2]. We also
9423 need to stop the division from being put into a branch delay slot[3].
9424 The easiest way to avoid both problems is to add a nop after the
9425 division. When a divide-by-zero check is needed, this nop can be
9426 used to fill the branch delay slot.
9428 [1] If a double-word or a variable shift executes immediately
9429 after starting an integer division, the shift may give an
9430 incorrect result. See quotations of errata #16 and #28 from
9431 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9432 in mips.md for details.
9434 [2] A similar bug to [1] exists for all revisions of the
9435 R4000 and the R4400 when run in an MC configuration.
9436 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9438 "19. In this following sequence:
9440 ddiv (or ddivu or div or divu)
9441 dsll32 (or dsrl32, dsra32)
9443 if an MPT stall occurs, while the divide is slipping the cpu
9444 pipeline, then the following double shift would end up with an
9447 Workaround: The compiler needs to avoid generating any
9448 sequence with divide followed by extended double shift."
9450 This erratum is also present in "MIPS R4400MC Errata, Processor
9451 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9452 & 3.0" as errata #10 and #4, respectively.
9454 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9455 (also valid for MIPS R4000MC processors):
9457 "52. R4000SC: This bug does not apply for the R4000PC.
9459 There are two flavors of this bug:
9461 1) If the instruction just after divide takes an RF exception
9462 (tlb-refill, tlb-invalid) and gets an instruction cache
9463 miss (both primary and secondary) and the line which is
9464 currently in secondary cache at this index had the first
9465 data word, where the bits 5..2 are set, then R4000 would
9466 get a wrong result for the div.
9471 ------------------- # end-of page. -tlb-refill
9476 ------------------- # end-of page. -tlb-invalid
9479 2) If the divide is in the taken branch delay slot, where the
9480 target takes RF exception and gets an I-cache miss for the
9481 exception vector or where I-cache miss occurs for the
9482 target address, under the above mentioned scenarios, the
9483 div would get wrong results.
9486 j r2 # to next page mapped or unmapped
9487 div r8,r9 # this bug would be there as long
9488 # as there is an ICache miss and
9489 nop # the "data pattern" is present
9492 beq r0, r0, NextPage # to Next page
9496 This bug is present for div, divu, ddiv, and ddivu
9499 Workaround: For item 1), OS could make sure that the next page
9500 after the divide instruction is also mapped. For item 2), the
9501 compiler could make sure that the divide instruction is not in
9502 the branch delay slot."
9504 These processors have PRId values of 0x00004220 and 0x00004300 for
9505 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9508 mips_output_division (const char *division, rtx *operands)
9513 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9515 output_asm_insn (s, operands);
9518 if (TARGET_CHECK_ZERO_DIV)
9522 output_asm_insn (s, operands);
9523 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9525 else if (GENERATE_DIVIDE_TRAPS)
9527 output_asm_insn (s, operands);
9532 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9533 output_asm_insn (s, operands);
9534 s = "break\t7%)\n1:";
9540 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9541 with a final "000" replaced by "k". Ignore case.
9543 Note: this function is shared between GCC and GAS. */
9546 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9548 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9549 given++, canonical++;
9551 return ((*given == 0 && *canonical == 0)
9552 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9556 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9557 CPU name. We've traditionally allowed a lot of variation here.
9559 Note: this function is shared between GCC and GAS. */
9562 mips_matching_cpu_name_p (const char *canonical, const char *given)
9564 /* First see if the name matches exactly, or with a final "000"
9566 if (mips_strict_matching_cpu_name_p (canonical, given))
9569 /* If not, try comparing based on numerical designation alone.
9570 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9571 if (TOLOWER (*given) == 'r')
9573 if (!ISDIGIT (*given))
9576 /* Skip over some well-known prefixes in the canonical name,
9577 hoping to find a number there too. */
9578 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9580 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9582 else if (TOLOWER (canonical[0]) == 'r')
9585 return mips_strict_matching_cpu_name_p (canonical, given);
9589 /* Return the mips_cpu_info entry for the processor or ISA given
9590 by CPU_STRING. Return null if the string isn't recognized.
9592 A similar function exists in GAS. */
9594 static const struct mips_cpu_info *
9595 mips_parse_cpu (const char *cpu_string)
9597 const struct mips_cpu_info *p;
9600 /* In the past, we allowed upper-case CPU names, but it doesn't
9601 work well with the multilib machinery. */
9602 for (s = cpu_string; *s != 0; s++)
9605 warning (0, "the cpu name must be lower case");
9609 /* 'from-abi' selects the most compatible architecture for the given
9610 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9611 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9612 version. Look first at the -mgp options, if given, otherwise base
9613 the choice on MASK_64BIT in TARGET_DEFAULT. */
9614 if (strcasecmp (cpu_string, "from-abi") == 0)
9615 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9616 : ABI_NEEDS_64BIT_REGS ? 3
9617 : (TARGET_64BIT ? 3 : 1));
9619 /* 'default' has traditionally been a no-op. Probably not very useful. */
9620 if (strcasecmp (cpu_string, "default") == 0)
9623 for (p = mips_cpu_info_table; p->name != 0; p++)
9624 if (mips_matching_cpu_name_p (p->name, cpu_string))
9631 /* Return the processor associated with the given ISA level, or null
9632 if the ISA isn't valid. */
9634 static const struct mips_cpu_info *
9635 mips_cpu_info_from_isa (int isa)
9637 const struct mips_cpu_info *p;
9639 for (p = mips_cpu_info_table; p->name != 0; p++)
9646 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9647 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9648 they only hold condition code modes, and CCmode is always considered to
9649 be 4 bytes wide. All other registers are word sized. */
9652 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9654 if (ST_REG_P (regno))
9655 return ((GET_MODE_SIZE (mode) + 3) / 4);
9656 else if (! FP_REG_P (regno))
9657 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9659 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9662 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9663 all BLKmode objects are returned in memory. Under the new (N32 and
9664 64-bit MIPS ABIs) small structures are returned in a register.
9665 Objects with varying size must still be returned in memory, of
9669 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9672 return (TYPE_MODE (type) == BLKmode);
9674 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9675 || (int_size_in_bytes (type) == -1));
9679 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9681 return !TARGET_OLDABI;
9684 /* Return true if INSN is a multiply-add or multiply-subtract
9685 instruction and PREV assigns to the accumulator operand. */
9688 mips_linked_madd_p (rtx prev, rtx insn)
9692 x = single_set (insn);
9698 if (GET_CODE (x) == PLUS
9699 && GET_CODE (XEXP (x, 0)) == MULT
9700 && reg_set_p (XEXP (x, 1), prev))
9703 if (GET_CODE (x) == MINUS
9704 && GET_CODE (XEXP (x, 1)) == MULT
9705 && reg_set_p (XEXP (x, 0), prev))
9711 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9712 that may clobber hi or lo. */
9714 static rtx mips_macc_chains_last_hilo;
9716 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9717 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9720 mips_macc_chains_record (rtx insn)
9722 if (get_attr_may_clobber_hilo (insn))
9723 mips_macc_chains_last_hilo = insn;
9726 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9727 has NREADY elements, looking for a multiply-add or multiply-subtract
9728 instruction that is cumulative with mips_macc_chains_last_hilo.
9729 If there is one, promote it ahead of anything else that might
9730 clobber hi or lo. */
9733 mips_macc_chains_reorder (rtx *ready, int nready)
9737 if (mips_macc_chains_last_hilo != 0)
9738 for (i = nready - 1; i >= 0; i--)
9739 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9741 for (j = nready - 1; j > i; j--)
9742 if (recog_memoized (ready[j]) >= 0
9743 && get_attr_may_clobber_hilo (ready[j]))
9745 mips_promote_ready (ready, i, j);
9752 /* The last instruction to be scheduled. */
9754 static rtx vr4130_last_insn;
9756 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9757 points to an rtx that is initially an instruction. Nullify the rtx
9758 if the instruction uses the value of register X. */
9761 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9763 rtx *insn_ptr = data;
9766 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9770 /* Return true if there is true register dependence between vr4130_last_insn
9774 vr4130_true_reg_dependence_p (rtx insn)
9776 note_stores (PATTERN (vr4130_last_insn),
9777 vr4130_true_reg_dependence_p_1, &insn);
9781 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9782 the ready queue and that INSN2 is the instruction after it, return
9783 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9784 in which INSN1 and INSN2 can probably issue in parallel, but for
9785 which (INSN2, INSN1) should be less sensitive to instruction
9786 alignment than (INSN1, INSN2). See 4130.md for more details. */
9789 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9793 /* Check for the following case:
9795 1) there is some other instruction X with an anti dependence on INSN1;
9796 2) X has a higher priority than INSN2; and
9797 3) X is an arithmetic instruction (and thus has no unit restrictions).
9799 If INSN1 is the last instruction blocking X, it would better to
9800 choose (INSN1, X) over (INSN2, INSN1). */
9801 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9802 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9803 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9804 && recog_memoized (XEXP (dep, 0)) >= 0
9805 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9808 if (vr4130_last_insn != 0
9809 && recog_memoized (insn1) >= 0
9810 && recog_memoized (insn2) >= 0)
9812 /* See whether INSN1 and INSN2 use different execution units,
9813 or if they are both ALU-type instructions. If so, they can
9814 probably execute in parallel. */
9815 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9816 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9817 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9819 /* If only one of the instructions has a dependence on
9820 vr4130_last_insn, prefer to schedule the other one first. */
9821 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9822 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9826 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9827 is not an ALU-type instruction and if INSN1 uses the same
9828 execution unit. (Note that if this condition holds, we already
9829 know that INSN2 uses a different execution unit.) */
9830 if (class1 != VR4130_CLASS_ALU
9831 && recog_memoized (vr4130_last_insn) >= 0
9832 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9839 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9840 queue with at least two instructions. Swap the first two if
9841 vr4130_swap_insns_p says that it could be worthwhile. */
9844 vr4130_reorder (rtx *ready, int nready)
9846 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9847 mips_promote_ready (ready, nready - 2, nready - 1);
9850 /* Remove the instruction at index LOWER from ready queue READY and
9851 reinsert it in front of the instruction at index HIGHER. LOWER must
9855 mips_promote_ready (rtx *ready, int lower, int higher)
9860 new_head = ready[lower];
9861 for (i = lower; i < higher; i++)
9862 ready[i] = ready[i + 1];
9863 ready[i] = new_head;
9866 /* Implement TARGET_SCHED_REORDER. */
9869 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9870 rtx *ready, int *nreadyp, int cycle)
9872 if (!reload_completed && TUNE_MACC_CHAINS)
9875 mips_macc_chains_last_hilo = 0;
9877 mips_macc_chains_reorder (ready, *nreadyp);
9879 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9882 vr4130_last_insn = 0;
9884 vr4130_reorder (ready, *nreadyp);
9886 return mips_issue_rate ();
9889 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9892 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9895 switch (GET_CODE (PATTERN (insn)))
9899 /* Don't count USEs and CLOBBERs against the issue rate. */
9904 if (!reload_completed && TUNE_MACC_CHAINS)
9905 mips_macc_chains_record (insn);
9906 vr4130_last_insn = insn;
9912 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9913 dependencies have no cost. */
9916 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9917 rtx dep ATTRIBUTE_UNUSED, int cost)
9919 if (REG_NOTE_KIND (link) != 0)
9924 /* Return the number of instructions that can be issued per cycle. */
9927 mips_issue_rate (void)
9931 case PROCESSOR_R4130:
9932 case PROCESSOR_R5400:
9933 case PROCESSOR_R5500:
9934 case PROCESSOR_R7000:
9935 case PROCESSOR_R9000:
9939 case PROCESSOR_SB1A:
9940 /* This is actually 4, but we get better performance if we claim 3.
9941 This is partly because of unwanted speculative code motion with the
9942 larger number, and partly because in most common cases we can't
9943 reach the theoretical max of 4. */
9951 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9952 be as wide as the scheduling freedom in the DFA. */
9955 mips_multipass_dfa_lookahead (void)
9957 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9964 /* Implements a store data bypass check. We need this because the cprestore
9965 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
9966 default routine to abort. We just return false for that case. */
9967 /* ??? Should try to give a better result here than assuming false. */
9970 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
9972 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
9975 return ! store_data_bypass_p (out_insn, in_insn);
9978 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9979 return the first operand of the associated "pref" or "prefx" insn. */
9982 mips_prefetch_cookie (rtx write, rtx locality)
9984 /* store_streamed / load_streamed. */
9985 if (INTVAL (locality) <= 0)
9986 return GEN_INT (INTVAL (write) + 4);
9989 if (INTVAL (locality) <= 2)
9992 /* store_retained / load_retained. */
9993 return GEN_INT (INTVAL (write) + 6);
9996 /* MIPS builtin function support. */
9998 struct builtin_description
10000 /* The code of the main .md file instruction. See mips_builtin_type
10001 for more information. */
10002 enum insn_code icode;
10004 /* The floating-point comparison code to use with ICODE, if any. */
10005 enum mips_fp_condition cond;
10007 /* The name of the builtin function. */
10010 /* Specifies how the function should be expanded. */
10011 enum mips_builtin_type builtin_type;
10013 /* The function's prototype. */
10014 enum mips_function_type function_type;
10016 /* The target flags required for this function. */
10020 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10021 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10022 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10023 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10024 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10026 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10028 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10029 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10030 "__builtin_mips_" #INSN "_" #COND "_s", \
10031 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10032 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10033 "__builtin_mips_" #INSN "_" #COND "_d", \
10034 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10036 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10037 The lower and upper forms require TARGET_FLAGS while the any and all
10038 forms require MASK_MIPS3D. */
10039 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10040 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10041 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10042 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10043 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10044 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10045 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10046 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10047 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10048 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10049 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10050 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10051 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10053 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10054 require MASK_MIPS3D. */
10055 #define CMP_4S_BUILTINS(INSN, COND) \
10056 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10057 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10058 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10060 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10061 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10062 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10065 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10066 instruction requires TARGET_FLAGS. */
10067 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10068 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10069 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10070 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10072 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10073 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10074 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10077 /* Define all the builtins related to c.cond.fmt condition COND. */
10078 #define CMP_BUILTINS(COND) \
10079 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10080 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10081 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10082 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10083 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10084 CMP_4S_BUILTINS (c, COND), \
10085 CMP_4S_BUILTINS (cabs, COND)
10087 static const struct builtin_description mips_bdesc[] =
10089 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10090 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10091 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10092 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10093 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10094 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10095 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10096 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10098 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10099 MASK_PAIRED_SINGLE_FLOAT),
10100 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10101 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10102 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10103 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10105 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10106 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10107 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10108 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10109 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10110 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10112 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10113 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10114 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10115 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10116 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10117 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10119 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10122 /* Builtin functions for the SB-1 processor. */
10124 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10126 static const struct builtin_description sb1_bdesc[] =
10128 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10131 /* Builtin functions for DSP ASE. */
10133 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10134 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10135 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10136 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10138 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10139 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10140 builtin_description fields. */
10141 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10142 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10143 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10145 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10146 branch instruction. TARGET_FLAGS is a builtin_description field. */
10147 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10148 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10149 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10151 static const struct builtin_description dsp_bdesc[] =
10153 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10154 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10155 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10156 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10157 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10158 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10159 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10160 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10161 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10162 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10163 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10164 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10165 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10166 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10167 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10168 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10169 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10170 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10171 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10172 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10173 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10174 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10175 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10176 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10177 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10178 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10179 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10180 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10181 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10182 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10183 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10184 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10185 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10186 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10187 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10188 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10189 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10190 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10191 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10192 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10193 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10194 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10195 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10196 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10197 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10198 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10199 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10200 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10201 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10202 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10203 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10204 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10205 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10206 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10207 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10208 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10209 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10210 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10211 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10212 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10213 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10214 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10215 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10216 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10217 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10218 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10219 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10220 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10221 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10222 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10223 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10224 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10225 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10226 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10227 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10228 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10229 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10230 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10231 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10232 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10233 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10234 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10235 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10236 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10237 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10238 BPOSGE_BUILTIN (32, MASK_DSP)
10241 /* This helps provide a mapping from builtin function codes to bdesc
10246 /* The builtin function table that this entry describes. */
10247 const struct builtin_description *bdesc;
10249 /* The number of entries in the builtin function table. */
10252 /* The target processor that supports these builtin functions.
10253 PROCESSOR_MAX means we enable them for all processors. */
10254 enum processor_type proc;
10257 static const struct bdesc_map bdesc_arrays[] =
10259 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10260 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10261 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10264 /* Take the head of argument list *ARGLIST and convert it into a form
10265 suitable for input operand OP of instruction ICODE. Return the value
10266 and point *ARGLIST at the next element of the list. */
10269 mips_prepare_builtin_arg (enum insn_code icode,
10270 unsigned int op, tree *arglist)
10273 enum machine_mode mode;
10275 value = expand_normal (TREE_VALUE (*arglist));
10276 mode = insn_data[icode].operand[op].mode;
10277 if (!insn_data[icode].operand[op].predicate (value, mode))
10279 value = copy_to_mode_reg (mode, value);
10280 /* Check the predicate again. */
10281 if (!insn_data[icode].operand[op].predicate (value, mode))
10283 error ("invalid argument to builtin function");
10288 *arglist = TREE_CHAIN (*arglist);
10292 /* Return an rtx suitable for output operand OP of instruction ICODE.
10293 If TARGET is non-null, try to use it where possible. */
10296 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10298 enum machine_mode mode;
10300 mode = insn_data[icode].operand[op].mode;
10301 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10302 target = gen_reg_rtx (mode);
10307 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10310 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10311 enum machine_mode mode ATTRIBUTE_UNUSED,
10312 int ignore ATTRIBUTE_UNUSED)
10314 enum insn_code icode;
10315 enum mips_builtin_type type;
10316 tree fndecl, arglist;
10317 unsigned int fcode;
10318 const struct builtin_description *bdesc;
10319 const struct bdesc_map *m;
10321 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10322 arglist = TREE_OPERAND (exp, 1);
10323 fcode = DECL_FUNCTION_CODE (fndecl);
10326 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10328 if (fcode < m->size)
10331 icode = bdesc[fcode].icode;
10332 type = bdesc[fcode].builtin_type;
10342 case MIPS_BUILTIN_DIRECT:
10343 return mips_expand_builtin_direct (icode, target, arglist, true);
10345 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10346 return mips_expand_builtin_direct (icode, target, arglist, false);
10348 case MIPS_BUILTIN_MOVT:
10349 case MIPS_BUILTIN_MOVF:
10350 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10353 case MIPS_BUILTIN_CMP_ANY:
10354 case MIPS_BUILTIN_CMP_ALL:
10355 case MIPS_BUILTIN_CMP_UPPER:
10356 case MIPS_BUILTIN_CMP_LOWER:
10357 case MIPS_BUILTIN_CMP_SINGLE:
10358 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10361 case MIPS_BUILTIN_BPOSGE32:
10362 return mips_expand_builtin_bposge (type, target);
10369 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10372 mips_init_builtins (void)
10374 const struct builtin_description *d;
10375 const struct bdesc_map *m;
10376 tree types[(int) MIPS_MAX_FTYPE_MAX];
10377 tree V2SF_type_node;
10378 tree V2HI_type_node;
10379 tree V4QI_type_node;
10380 unsigned int offset;
10382 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10383 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10386 if (TARGET_PAIRED_SINGLE_FLOAT)
10388 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10390 types[MIPS_V2SF_FTYPE_V2SF]
10391 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10393 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10394 = build_function_type_list (V2SF_type_node,
10395 V2SF_type_node, V2SF_type_node, NULL_TREE);
10397 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10398 = build_function_type_list (V2SF_type_node,
10399 V2SF_type_node, V2SF_type_node,
10400 integer_type_node, NULL_TREE);
10402 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10403 = build_function_type_list (V2SF_type_node,
10404 V2SF_type_node, V2SF_type_node,
10405 V2SF_type_node, V2SF_type_node, NULL_TREE);
10407 types[MIPS_V2SF_FTYPE_SF_SF]
10408 = build_function_type_list (V2SF_type_node,
10409 float_type_node, float_type_node, NULL_TREE);
10411 types[MIPS_INT_FTYPE_V2SF_V2SF]
10412 = build_function_type_list (integer_type_node,
10413 V2SF_type_node, V2SF_type_node, NULL_TREE);
10415 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10416 = build_function_type_list (integer_type_node,
10417 V2SF_type_node, V2SF_type_node,
10418 V2SF_type_node, V2SF_type_node, NULL_TREE);
10420 types[MIPS_INT_FTYPE_SF_SF]
10421 = build_function_type_list (integer_type_node,
10422 float_type_node, float_type_node, NULL_TREE);
10424 types[MIPS_INT_FTYPE_DF_DF]
10425 = build_function_type_list (integer_type_node,
10426 double_type_node, double_type_node, NULL_TREE);
10428 types[MIPS_SF_FTYPE_V2SF]
10429 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10431 types[MIPS_SF_FTYPE_SF]
10432 = build_function_type_list (float_type_node,
10433 float_type_node, NULL_TREE);
10435 types[MIPS_SF_FTYPE_SF_SF]
10436 = build_function_type_list (float_type_node,
10437 float_type_node, float_type_node, NULL_TREE);
10439 types[MIPS_DF_FTYPE_DF]
10440 = build_function_type_list (double_type_node,
10441 double_type_node, NULL_TREE);
10443 types[MIPS_DF_FTYPE_DF_DF]
10444 = build_function_type_list (double_type_node,
10445 double_type_node, double_type_node, NULL_TREE);
10450 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10451 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10453 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10454 = build_function_type_list (V2HI_type_node,
10455 V2HI_type_node, V2HI_type_node,
10458 types[MIPS_SI_FTYPE_SI_SI]
10459 = build_function_type_list (intSI_type_node,
10460 intSI_type_node, intSI_type_node,
10463 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10464 = build_function_type_list (V4QI_type_node,
10465 V4QI_type_node, V4QI_type_node,
10468 types[MIPS_SI_FTYPE_V4QI]
10469 = build_function_type_list (intSI_type_node,
10473 types[MIPS_V2HI_FTYPE_V2HI]
10474 = build_function_type_list (V2HI_type_node,
10478 types[MIPS_SI_FTYPE_SI]
10479 = build_function_type_list (intSI_type_node,
10483 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10484 = build_function_type_list (V4QI_type_node,
10485 V2HI_type_node, V2HI_type_node,
10488 types[MIPS_V2HI_FTYPE_SI_SI]
10489 = build_function_type_list (V2HI_type_node,
10490 intSI_type_node, intSI_type_node,
10493 types[MIPS_SI_FTYPE_V2HI]
10494 = build_function_type_list (intSI_type_node,
10498 types[MIPS_V2HI_FTYPE_V4QI]
10499 = build_function_type_list (V2HI_type_node,
10503 types[MIPS_V4QI_FTYPE_V4QI_SI]
10504 = build_function_type_list (V4QI_type_node,
10505 V4QI_type_node, intSI_type_node,
10508 types[MIPS_V2HI_FTYPE_V2HI_SI]
10509 = build_function_type_list (V2HI_type_node,
10510 V2HI_type_node, intSI_type_node,
10513 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10514 = build_function_type_list (V2HI_type_node,
10515 V4QI_type_node, V2HI_type_node,
10518 types[MIPS_SI_FTYPE_V2HI_V2HI]
10519 = build_function_type_list (intSI_type_node,
10520 V2HI_type_node, V2HI_type_node,
10523 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10524 = build_function_type_list (intDI_type_node,
10525 intDI_type_node, V4QI_type_node, V4QI_type_node,
10528 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10529 = build_function_type_list (intDI_type_node,
10530 intDI_type_node, V2HI_type_node, V2HI_type_node,
10533 types[MIPS_DI_FTYPE_DI_SI_SI]
10534 = build_function_type_list (intDI_type_node,
10535 intDI_type_node, intSI_type_node, intSI_type_node,
10538 types[MIPS_V4QI_FTYPE_SI]
10539 = build_function_type_list (V4QI_type_node,
10543 types[MIPS_V2HI_FTYPE_SI]
10544 = build_function_type_list (V2HI_type_node,
10548 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10549 = build_function_type_list (void_type_node,
10550 V4QI_type_node, V4QI_type_node,
10553 types[MIPS_SI_FTYPE_V4QI_V4QI]
10554 = build_function_type_list (intSI_type_node,
10555 V4QI_type_node, V4QI_type_node,
10558 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10559 = build_function_type_list (void_type_node,
10560 V2HI_type_node, V2HI_type_node,
10563 types[MIPS_SI_FTYPE_DI_SI]
10564 = build_function_type_list (intSI_type_node,
10565 intDI_type_node, intSI_type_node,
10568 types[MIPS_DI_FTYPE_DI_SI]
10569 = build_function_type_list (intDI_type_node,
10570 intDI_type_node, intSI_type_node,
10573 types[MIPS_VOID_FTYPE_SI_SI]
10574 = build_function_type_list (void_type_node,
10575 intSI_type_node, intSI_type_node,
10578 types[MIPS_SI_FTYPE_PTR_SI]
10579 = build_function_type_list (intSI_type_node,
10580 ptr_type_node, intSI_type_node,
10583 types[MIPS_SI_FTYPE_VOID]
10584 = build_function_type (intSI_type_node, void_list_node);
10587 /* Iterate through all of the bdesc arrays, initializing all of the
10588 builtin functions. */
10591 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10593 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10594 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10595 if ((d->target_flags & target_flags) == d->target_flags)
10596 lang_hooks.builtin_function (d->name, types[d->function_type],
10597 d - m->bdesc + offset,
10598 BUILT_IN_MD, NULL, NULL);
10603 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10604 .md pattern and ARGLIST is the list of function arguments. TARGET,
10605 if nonnull, suggests a good place to put the result.
10606 HAS_TARGET indicates the function must return something. */
10609 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10612 rtx ops[MAX_RECOG_OPERANDS];
10617 /* We save target to ops[0]. */
10618 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10622 /* We need to test if arglist is not zero. Some instructions have extra
10623 clobber registers. */
10624 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10625 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10630 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10634 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10638 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10642 gcc_unreachable ();
10647 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10648 function (TYPE says which). ARGLIST is the list of arguments to the
10649 function, ICODE is the instruction that should be used to compare
10650 the first two arguments, and COND is the condition it should test.
10651 TARGET, if nonnull, suggests a good place to put the result. */
10654 mips_expand_builtin_movtf (enum mips_builtin_type type,
10655 enum insn_code icode, enum mips_fp_condition cond,
10656 rtx target, tree arglist)
10658 rtx cmp_result, op0, op1;
10660 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10661 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10662 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10663 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10665 icode = CODE_FOR_mips_cond_move_tf_ps;
10666 target = mips_prepare_builtin_target (icode, 0, target);
10667 if (type == MIPS_BUILTIN_MOVT)
10669 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10670 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10674 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10675 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10677 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10681 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10682 into TARGET otherwise. Return TARGET. */
10685 mips_builtin_branch_and_move (rtx condition, rtx target,
10686 rtx value_if_true, rtx value_if_false)
10688 rtx true_label, done_label;
10690 true_label = gen_label_rtx ();
10691 done_label = gen_label_rtx ();
10693 /* First assume that CONDITION is false. */
10694 emit_move_insn (target, value_if_false);
10696 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10697 emit_jump_insn (gen_condjump (condition, true_label));
10698 emit_jump_insn (gen_jump (done_label));
10701 /* Fix TARGET if CONDITION is true. */
10702 emit_label (true_label);
10703 emit_move_insn (target, value_if_true);
10705 emit_label (done_label);
10709 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10710 of the comparison instruction and COND is the condition it should test.
10711 ARGLIST is the list of function arguments and TARGET, if nonnull,
10712 suggests a good place to put the boolean result. */
10715 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10716 enum insn_code icode, enum mips_fp_condition cond,
10717 rtx target, tree arglist)
10719 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10722 if (target == 0 || GET_MODE (target) != SImode)
10723 target = gen_reg_rtx (SImode);
10725 /* Prepare the operands to the comparison. */
10726 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10727 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10728 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10730 switch (insn_data[icode].n_operands)
10733 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10737 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10738 ops[3], ops[4], GEN_INT (cond)));
10742 gcc_unreachable ();
10745 /* If the comparison sets more than one register, we define the result
10746 to be 0 if all registers are false and -1 if all registers are true.
10747 The value of the complete result is indeterminate otherwise. */
10748 switch (builtin_type)
10750 case MIPS_BUILTIN_CMP_ALL:
10751 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10752 return mips_builtin_branch_and_move (condition, target,
10753 const0_rtx, const1_rtx);
10755 case MIPS_BUILTIN_CMP_UPPER:
10756 case MIPS_BUILTIN_CMP_LOWER:
10757 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10758 condition = gen_single_cc (cmp_result, offset);
10759 return mips_builtin_branch_and_move (condition, target,
10760 const1_rtx, const0_rtx);
10763 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10764 return mips_builtin_branch_and_move (condition, target,
10765 const1_rtx, const0_rtx);
10769 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10770 suggests a good place to put the boolean result. */
10773 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10775 rtx condition, cmp_result;
10778 if (target == 0 || GET_MODE (target) != SImode)
10779 target = gen_reg_rtx (SImode);
10781 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10783 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10788 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10789 return mips_builtin_branch_and_move (condition, target,
10790 const1_rtx, const0_rtx);
10793 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10794 FIRST is true if this is the first time handling this decl. */
10797 mips_encode_section_info (tree decl, rtx rtl, int first)
10799 default_encode_section_info (decl, rtl, first);
10801 if (TREE_CODE (decl) == FUNCTION_DECL
10802 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10804 rtx symbol = XEXP (rtl, 0);
10805 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10809 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10810 on entry to a function when generating -mshared abicalls code. */
10813 mips_extra_live_on_entry (bitmap regs)
10815 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10816 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10819 /* SImode values are represented as sign-extended to DImode. */
10822 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10824 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10825 return SIGN_EXTEND;
10830 #include "gt-mips.h"