1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
61 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save & restore registers.
78 Use a maximum gap of 0x100 in the mips16 case. We can then use
79 unextended instructions to save and restore registers, and to
80 allocate and deallocate the top part of the frame.
82 The value in the !mips16 case must be a SMALL_OPERAND and must
83 preserve the maximum stack alignment. */
84 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
86 /* True if INSN is a mips.md pattern or asm statement. */
87 #define USEFUL_INSN_P(INSN) \
89 && GET_CODE (PATTERN (INSN)) != USE \
90 && GET_CODE (PATTERN (INSN)) != CLOBBER \
91 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
92 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
94 /* If INSN is a delayed branch sequence, return the first instruction
95 in the sequence, otherwise return INSN itself. */
96 #define SEQ_BEGIN(INSN) \
97 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
98 ? XVECEXP (PATTERN (INSN), 0, 0) \
101 /* Likewise for the last instruction in a delayed branch sequence. */
102 #define SEQ_END(INSN) \
103 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
104 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
107 /* Execute the following loop body with SUBINSN set to each instruction
108 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
109 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
110 for ((SUBINSN) = SEQ_BEGIN (INSN); \
111 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
112 (SUBINSN) = NEXT_INSN (SUBINSN))
114 /* Classifies an address.
117 A natural register + offset address. The register satisfies
118 mips_valid_base_register_p and the offset is a const_arith_operand.
121 A LO_SUM rtx. The first operand is a valid base register and
122 the second operand is a symbolic address.
125 A signed 16-bit constant address.
128 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
129 enum mips_address_type {
136 /* Classifies the prototype of a builtin function. */
137 enum mips_function_type
139 MIPS_V2SF_FTYPE_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
142 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
143 MIPS_V2SF_FTYPE_SF_SF,
144 MIPS_INT_FTYPE_V2SF_V2SF,
145 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
146 MIPS_INT_FTYPE_SF_SF,
147 MIPS_INT_FTYPE_DF_DF,
154 /* For MIPS DSP ASE */
156 MIPS_DI_FTYPE_DI_SI_SI,
157 MIPS_DI_FTYPE_DI_V2HI_V2HI,
158 MIPS_DI_FTYPE_DI_V4QI_V4QI,
160 MIPS_SI_FTYPE_PTR_SI,
164 MIPS_SI_FTYPE_V2HI_V2HI,
166 MIPS_SI_FTYPE_V4QI_V4QI,
169 MIPS_V2HI_FTYPE_SI_SI,
170 MIPS_V2HI_FTYPE_V2HI,
171 MIPS_V2HI_FTYPE_V2HI_SI,
172 MIPS_V2HI_FTYPE_V2HI_V2HI,
173 MIPS_V2HI_FTYPE_V4QI,
174 MIPS_V2HI_FTYPE_V4QI_V2HI,
176 MIPS_V4QI_FTYPE_V2HI_V2HI,
177 MIPS_V4QI_FTYPE_V4QI_SI,
178 MIPS_V4QI_FTYPE_V4QI_V4QI,
179 MIPS_VOID_FTYPE_SI_SI,
180 MIPS_VOID_FTYPE_V2HI_V2HI,
181 MIPS_VOID_FTYPE_V4QI_V4QI,
187 /* Specifies how a builtin function should be converted into rtl. */
188 enum mips_builtin_type
190 /* The builtin corresponds directly to an .md pattern. The return
191 value is mapped to operand 0 and the arguments are mapped to
192 operands 1 and above. */
195 /* The builtin corresponds directly to an .md pattern. There is no return
196 value and the arguments are mapped to operands 0 and above. */
197 MIPS_BUILTIN_DIRECT_NO_TARGET,
199 /* The builtin corresponds to a comparison instruction followed by
200 a mips_cond_move_tf_ps pattern. The first two arguments are the
201 values to compare and the second two arguments are the vector
202 operands for the movt.ps or movf.ps instruction (in assembly order). */
206 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
207 of this instruction is the result of the comparison, which has mode
208 CCV2 or CCV4. The function arguments are mapped to operands 1 and
209 above. The function's return value is an SImode boolean that is
210 true under the following conditions:
212 MIPS_BUILTIN_CMP_ANY: one of the registers is true
213 MIPS_BUILTIN_CMP_ALL: all of the registers are true
214 MIPS_BUILTIN_CMP_LOWER: the first register is true
215 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
216 MIPS_BUILTIN_CMP_ANY,
217 MIPS_BUILTIN_CMP_ALL,
218 MIPS_BUILTIN_CMP_UPPER,
219 MIPS_BUILTIN_CMP_LOWER,
221 /* As above, but the instruction only sets a single $fcc register. */
222 MIPS_BUILTIN_CMP_SINGLE,
224 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
225 MIPS_BUILTIN_BPOSGE32
228 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
229 #define MIPS_FP_CONDITIONS(MACRO) \
247 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
248 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
249 enum mips_fp_condition {
250 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
253 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
254 #define STRINGIFY(X) #X
255 static const char *const mips_fp_conditions[] = {
256 MIPS_FP_CONDITIONS (STRINGIFY)
259 /* A function to save or store a register. The first argument is the
260 register and the second is the stack slot. */
261 typedef void (*mips_save_restore_fn) (rtx, rtx);
263 struct mips16_constant;
264 struct mips_arg_info;
265 struct mips_address_info;
266 struct mips_integer_op;
269 static enum mips_symbol_type mips_classify_symbol (rtx);
270 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
271 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
272 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
273 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
274 static bool mips_classify_address (struct mips_address_info *, rtx,
275 enum machine_mode, int);
276 static bool mips_cannot_force_const_mem (rtx);
277 static bool mips_use_blocks_for_constant_p (enum machine_mode, rtx);
278 static int mips_symbol_insns (enum mips_symbol_type);
279 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
280 static rtx mips_force_temporary (rtx, rtx);
281 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
282 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
283 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
284 static unsigned int mips_build_lower (struct mips_integer_op *,
285 unsigned HOST_WIDE_INT);
286 static unsigned int mips_build_integer (struct mips_integer_op *,
287 unsigned HOST_WIDE_INT);
288 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
289 static int m16_check_op (rtx, int, int, int);
290 static bool mips_rtx_costs (rtx, int, int, int *);
291 static int mips_address_cost (rtx);
292 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
293 static void mips_load_call_address (rtx, rtx, int);
294 static bool mips_function_ok_for_sibcall (tree, tree);
295 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
296 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
297 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
298 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
299 tree, int, struct mips_arg_info *);
300 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
301 static void mips_set_architecture (const struct mips_cpu_info *);
302 static void mips_set_tune (const struct mips_cpu_info *);
303 static bool mips_handle_option (size_t, const char *, int);
304 static struct machine_function *mips_init_machine_status (void);
305 static void print_operand_reloc (FILE *, rtx, const char **);
307 static void irix_output_external_libcall (rtx);
309 static void mips_file_start (void);
310 static void mips_file_end (void);
311 static bool mips_rewrite_small_data_p (rtx);
312 static int mips_small_data_pattern_1 (rtx *, void *);
313 static int mips_rewrite_small_data_1 (rtx *, void *);
314 static bool mips_function_has_gp_insn (void);
315 static unsigned int mips_global_pointer (void);
316 static bool mips_save_reg_p (unsigned int);
317 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
318 mips_save_restore_fn);
319 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
320 static void mips_output_cplocal (void);
321 static void mips_emit_loadgp (void);
322 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
323 static void mips_set_frame_expr (rtx);
324 static rtx mips_frame_set (rtx, rtx);
325 static void mips_save_reg (rtx, rtx);
326 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
327 static void mips_restore_reg (rtx, rtx);
328 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
329 HOST_WIDE_INT, tree);
330 static int symbolic_expression_p (rtx);
331 static section *mips_select_rtx_section (enum machine_mode, rtx,
332 unsigned HOST_WIDE_INT);
333 static section *mips_function_rodata_section (tree);
334 static bool mips_in_small_data_p (tree);
335 static bool mips_use_anchors_for_symbol_p (rtx);
336 static int mips_fpr_return_fields (tree, tree *);
337 static bool mips_return_in_msb (tree);
338 static rtx mips_return_fpr_pair (enum machine_mode mode,
339 enum machine_mode mode1, HOST_WIDE_INT,
340 enum machine_mode mode2, HOST_WIDE_INT);
341 static rtx mips16_gp_pseudo_reg (void);
342 static void mips16_fp_args (FILE *, int, int);
343 static void build_mips16_function_stub (FILE *);
344 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
345 static void dump_constants (struct mips16_constant *, rtx);
346 static int mips16_insn_length (rtx);
347 static int mips16_rewrite_pool_refs (rtx *, void *);
348 static void mips16_lay_out_constants (void);
349 static void mips_sim_reset (struct mips_sim *);
350 static void mips_sim_init (struct mips_sim *, state_t);
351 static void mips_sim_next_cycle (struct mips_sim *);
352 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
353 static int mips_sim_wait_regs_2 (rtx *, void *);
354 static void mips_sim_wait_regs_1 (rtx *, void *);
355 static void mips_sim_wait_regs (struct mips_sim *, rtx);
356 static void mips_sim_wait_units (struct mips_sim *, rtx);
357 static void mips_sim_wait_insn (struct mips_sim *, rtx);
358 static void mips_sim_record_set (rtx, rtx, void *);
359 static void mips_sim_issue_insn (struct mips_sim *, rtx);
360 static void mips_sim_issue_nop (struct mips_sim *);
361 static void mips_sim_finish_insn (struct mips_sim *, rtx);
362 static void vr4130_avoid_branch_rt_conflict (rtx);
363 static void vr4130_align_insns (void);
364 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
365 static void mips_avoid_hazards (void);
366 static void mips_reorg (void);
367 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
368 static bool mips_matching_cpu_name_p (const char *, const char *);
369 static const struct mips_cpu_info *mips_parse_cpu (const char *);
370 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
371 static bool mips_return_in_memory (tree, tree);
372 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
373 static void mips_macc_chains_record (rtx);
374 static void mips_macc_chains_reorder (rtx *, int);
375 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
376 static bool vr4130_true_reg_dependence_p (rtx);
377 static bool vr4130_swap_insns_p (rtx, rtx);
378 static void vr4130_reorder (rtx *, int);
379 static void mips_promote_ready (rtx *, int, int);
380 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
381 static int mips_variable_issue (FILE *, int, rtx, int);
382 static int mips_adjust_cost (rtx, rtx, rtx, int);
383 static int mips_issue_rate (void);
384 static int mips_multipass_dfa_lookahead (void);
385 static void mips_init_libfuncs (void);
386 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
388 static tree mips_build_builtin_va_list (void);
389 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
390 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
392 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
394 static int mips_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode mode,
396 static bool mips_valid_pointer_mode (enum machine_mode);
397 static bool mips_vector_mode_supported_p (enum machine_mode);
398 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
399 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
400 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
401 static void mips_init_builtins (void);
402 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree, bool);
403 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
404 enum insn_code, enum mips_fp_condition,
406 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
407 enum insn_code, enum mips_fp_condition,
409 static rtx mips_expand_builtin_bposge (enum mips_builtin_type, rtx);
410 static void mips_encode_section_info (tree, rtx, int);
411 static void mips_extra_live_on_entry (bitmap);
412 static int mips_mode_rep_extended (enum machine_mode, enum machine_mode);
414 /* Structure to be filled in by compute_frame_size with register
415 save masks, and offsets for the current function. */
417 struct mips_frame_info GTY(())
419 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
420 HOST_WIDE_INT var_size; /* # bytes that variables take up */
421 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
422 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
423 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
424 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
425 unsigned int mask; /* mask of saved gp registers */
426 unsigned int fmask; /* mask of saved fp registers */
427 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
428 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
429 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
430 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
431 bool initialized; /* true if frame size already calculated */
432 int num_gp; /* number of gp registers saved */
433 int num_fp; /* number of fp registers saved */
436 struct machine_function GTY(()) {
437 /* Pseudo-reg holding the value of $28 in a mips16 function which
438 refers to GP relative global variables. */
439 rtx mips16_gp_pseudo_rtx;
441 /* The number of extra stack bytes taken up by register varargs.
442 This area is allocated by the callee at the very top of the frame. */
445 /* Current frame information, calculated by compute_frame_size. */
446 struct mips_frame_info frame;
448 /* The register to use as the global pointer within this function. */
449 unsigned int global_pointer;
451 /* True if mips_adjust_insn_length should ignore an instruction's
453 bool ignore_hazard_length_p;
455 /* True if the whole function is suitable for .set noreorder and
457 bool all_noreorder_p;
459 /* True if the function is known to have an instruction that needs $gp. */
463 /* Information about a single argument. */
466 /* True if the argument is passed in a floating-point register, or
467 would have been if we hadn't run out of registers. */
470 /* The number of words passed in registers, rounded up. */
471 unsigned int reg_words;
473 /* For EABI, the offset of the first register from GP_ARG_FIRST or
474 FP_ARG_FIRST. For other ABIs, the offset of the first register from
475 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
476 comment for details).
478 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
480 unsigned int reg_offset;
482 /* The number of words that must be passed on the stack, rounded up. */
483 unsigned int stack_words;
485 /* The offset from the start of the stack overflow area of the argument's
486 first stack word. Only meaningful when STACK_WORDS is nonzero. */
487 unsigned int stack_offset;
491 /* Information about an address described by mips_address_type.
497 REG is the base register and OFFSET is the constant offset.
500 REG is the register that contains the high part of the address,
501 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
502 is the type of OFFSET's symbol.
505 SYMBOL_TYPE is the type of symbol being referenced. */
507 struct mips_address_info
509 enum mips_address_type type;
512 enum mips_symbol_type symbol_type;
516 /* One stage in a constant building sequence. These sequences have
520 A = A CODE[1] VALUE[1]
521 A = A CODE[2] VALUE[2]
524 where A is an accumulator, each CODE[i] is a binary rtl operation
525 and each VALUE[i] is a constant integer. */
526 struct mips_integer_op {
528 unsigned HOST_WIDE_INT value;
532 /* The largest number of operations needed to load an integer constant.
533 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
534 When the lowest bit is clear, we can try, but reject a sequence with
535 an extra SLL at the end. */
536 #define MIPS_MAX_INTEGER_OPS 7
539 /* Global variables for machine-dependent things. */
541 /* Threshold for data being put into the small data/bss area, instead
542 of the normal data area. */
543 int mips_section_threshold = -1;
545 /* Count the number of .file directives, so that .loc is up to date. */
546 int num_source_filenames = 0;
548 /* Count the number of sdb related labels are generated (to find block
549 start and end boundaries). */
550 int sdb_label_count = 0;
552 /* Next label # for each statement for Silicon Graphics IRIS systems. */
555 /* Linked list of all externals that are to be emitted when optimizing
556 for the global pointer if they haven't been declared by the end of
557 the program with an appropriate .comm or initialization. */
559 struct extern_list GTY (())
561 struct extern_list *next; /* next external */
562 const char *name; /* name of the external */
563 int size; /* size in bytes */
566 static GTY (()) struct extern_list *extern_head = 0;
568 /* Name of the file containing the current function. */
569 const char *current_function_file = "";
571 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
577 /* The next branch instruction is a branch likely, not branch normal. */
578 int mips_branch_likely;
580 /* The operands passed to the last cmpMM expander. */
583 /* The target cpu for code generation. */
584 enum processor_type mips_arch;
585 const struct mips_cpu_info *mips_arch_info;
587 /* The target cpu for optimization and scheduling. */
588 enum processor_type mips_tune;
589 const struct mips_cpu_info *mips_tune_info;
591 /* Which instruction set architecture to use. */
594 /* Which ABI to use. */
595 int mips_abi = MIPS_ABI_DEFAULT;
597 /* Cost information to use. */
598 const struct mips_rtx_cost_data *mips_cost;
600 /* Whether we are generating mips16 hard float code. In mips16 mode
601 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
602 -msoft-float was not specified by the user, which means that we
603 should arrange to call mips32 hard floating point code. */
604 int mips16_hard_float;
606 /* The architecture selected by -mipsN. */
607 static const struct mips_cpu_info *mips_isa_info;
609 /* If TRUE, we split addresses into their high and low parts in the RTL. */
610 int mips_split_addresses;
612 /* Mode used for saving/restoring general purpose registers. */
613 static enum machine_mode gpr_mode;
615 /* Array giving truth value on whether or not a given hard register
616 can support a given mode. */
617 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
619 /* List of all MIPS punctuation characters used by print_operand. */
620 char mips_print_operand_punct[256];
622 /* Map GCC register number to debugger register number. */
623 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
625 /* A copy of the original flag_delayed_branch: see override_options. */
626 static int mips_flag_delayed_branch;
628 static GTY (()) int mips_output_filename_first_time = 1;
630 /* mips_split_p[X] is true if symbols of type X can be split by
631 mips_split_symbol(). */
632 bool mips_split_p[NUM_SYMBOL_TYPES];
634 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
635 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
636 if they are matched by a special .md file pattern. */
637 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
639 /* Likewise for HIGHs. */
640 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
642 /* Map hard register number to register class */
643 const enum reg_class mips_regno_to_class[] =
645 LEA_REGS, LEA_REGS, M16_NA_REGS, V1_REG,
646 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
647 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
648 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
649 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
650 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
651 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
652 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
653 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
654 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
655 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
656 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
657 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
658 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
659 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
660 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
661 HI_REG, LO_REG, NO_REGS, ST_REGS,
662 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
663 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
664 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
665 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
666 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
667 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
668 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
669 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
670 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
671 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
672 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
673 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
674 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
675 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
676 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
677 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
678 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
679 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
680 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
681 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
682 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
683 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
684 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
685 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
686 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
687 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
688 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
689 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
690 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
691 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
694 /* Table of machine dependent attributes. */
695 const struct attribute_spec mips_attribute_table[] =
697 { "long_call", 0, 0, false, true, true, NULL },
698 { NULL, 0, 0, false, false, false, NULL }
701 /* A table describing all the processors gcc knows about. Names are
702 matched in the order listed. The first mention of an ISA level is
703 taken as the canonical name for that ISA.
705 To ease comparison, please keep this table in the same order as
706 gas's mips_cpu_info_table[]. */
707 const struct mips_cpu_info mips_cpu_info_table[] = {
708 /* Entries for generic ISAs */
709 { "mips1", PROCESSOR_R3000, 1 },
710 { "mips2", PROCESSOR_R6000, 2 },
711 { "mips3", PROCESSOR_R4000, 3 },
712 { "mips4", PROCESSOR_R8000, 4 },
713 { "mips32", PROCESSOR_4KC, 32 },
714 { "mips32r2", PROCESSOR_M4K, 33 },
715 { "mips64", PROCESSOR_5KC, 64 },
718 { "r3000", PROCESSOR_R3000, 1 },
719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
720 { "r3900", PROCESSOR_R3900, 1 },
723 { "r6000", PROCESSOR_R6000, 2 },
726 { "r4000", PROCESSOR_R4000, 3 },
727 { "vr4100", PROCESSOR_R4100, 3 },
728 { "vr4111", PROCESSOR_R4111, 3 },
729 { "vr4120", PROCESSOR_R4120, 3 },
730 { "vr4130", PROCESSOR_R4130, 3 },
731 { "vr4300", PROCESSOR_R4300, 3 },
732 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
733 { "r4600", PROCESSOR_R4600, 3 },
734 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
735 { "r4650", PROCESSOR_R4650, 3 },
738 { "r8000", PROCESSOR_R8000, 4 },
739 { "vr5000", PROCESSOR_R5000, 4 },
740 { "vr5400", PROCESSOR_R5400, 4 },
741 { "vr5500", PROCESSOR_R5500, 4 },
742 { "rm7000", PROCESSOR_R7000, 4 },
743 { "rm9000", PROCESSOR_R9000, 4 },
746 { "4kc", PROCESSOR_4KC, 32 },
747 { "4km", PROCESSOR_4KC, 32 }, /* = 4kc */
748 { "4kp", PROCESSOR_4KP, 32 },
750 /* MIPS32 Release 2 */
751 { "m4k", PROCESSOR_M4K, 33 },
752 { "4kec", PROCESSOR_4KC, 33 },
753 { "4kem", PROCESSOR_4KC, 33 },
754 { "4kep", PROCESSOR_4KP, 33 },
755 { "24kc", PROCESSOR_24KC, 33 }, /* 24K no FPU */
756 { "24kf", PROCESSOR_24KF, 33 }, /* 24K 1:2 FPU */
757 { "24kx", PROCESSOR_24KX, 33 }, /* 24K 1:1 FPU */
758 { "24kec", PROCESSOR_24KC, 33 }, /* 24K with DSP */
759 { "24kef", PROCESSOR_24KF, 33 },
760 { "24kex", PROCESSOR_24KX, 33 },
761 { "34kc", PROCESSOR_24KC, 33 }, /* 34K with MT/DSP */
762 { "34kf", PROCESSOR_24KF, 33 },
763 { "34kx", PROCESSOR_24KX, 33 },
766 { "5kc", PROCESSOR_5KC, 64 },
767 { "5kf", PROCESSOR_5KF, 64 },
768 { "20kc", PROCESSOR_20KC, 64 },
769 { "sb1", PROCESSOR_SB1, 64 },
770 { "sb1a", PROCESSOR_SB1A, 64 },
771 { "sr71000", PROCESSOR_SR71000, 64 },
777 /* Default costs. If these are used for a processor we should look
778 up the actual costs. */
779 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
780 COSTS_N_INSNS (7), /* fp_mult_sf */ \
781 COSTS_N_INSNS (8), /* fp_mult_df */ \
782 COSTS_N_INSNS (23), /* fp_div_sf */ \
783 COSTS_N_INSNS (36), /* fp_div_df */ \
784 COSTS_N_INSNS (10), /* int_mult_si */ \
785 COSTS_N_INSNS (10), /* int_mult_di */ \
786 COSTS_N_INSNS (69), /* int_div_si */ \
787 COSTS_N_INSNS (69), /* int_div_di */ \
788 2, /* branch_cost */ \
789 4 /* memory_latency */
791 /* Need to replace these with the costs of calling the appropriate
793 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
794 COSTS_N_INSNS (256), /* fp_mult_sf */ \
795 COSTS_N_INSNS (256), /* fp_mult_df */ \
796 COSTS_N_INSNS (256), /* fp_div_sf */ \
797 COSTS_N_INSNS (256) /* fp_div_df */
799 static struct mips_rtx_cost_data const mips_rtx_cost_data[PROCESSOR_MAX] =
802 COSTS_N_INSNS (2), /* fp_add */
803 COSTS_N_INSNS (4), /* fp_mult_sf */
804 COSTS_N_INSNS (5), /* fp_mult_df */
805 COSTS_N_INSNS (12), /* fp_div_sf */
806 COSTS_N_INSNS (19), /* fp_div_df */
807 COSTS_N_INSNS (12), /* int_mult_si */
808 COSTS_N_INSNS (12), /* int_mult_di */
809 COSTS_N_INSNS (35), /* int_div_si */
810 COSTS_N_INSNS (35), /* int_div_di */
812 4 /* memory_latency */
817 COSTS_N_INSNS (6), /* int_mult_si */
818 COSTS_N_INSNS (6), /* int_mult_di */
819 COSTS_N_INSNS (36), /* int_div_si */
820 COSTS_N_INSNS (36), /* int_div_di */
822 4 /* memory_latency */
826 COSTS_N_INSNS (36), /* int_mult_si */
827 COSTS_N_INSNS (36), /* int_mult_di */
828 COSTS_N_INSNS (37), /* int_div_si */
829 COSTS_N_INSNS (37), /* int_div_di */
831 4 /* memory_latency */
835 COSTS_N_INSNS (4), /* int_mult_si */
836 COSTS_N_INSNS (11), /* int_mult_di */
837 COSTS_N_INSNS (36), /* int_div_si */
838 COSTS_N_INSNS (68), /* int_div_di */
840 4 /* memory_latency */
843 COSTS_N_INSNS (4), /* fp_add */
844 COSTS_N_INSNS (4), /* fp_mult_sf */
845 COSTS_N_INSNS (5), /* fp_mult_df */
846 COSTS_N_INSNS (17), /* fp_div_sf */
847 COSTS_N_INSNS (32), /* fp_div_df */
848 COSTS_N_INSNS (4), /* int_mult_si */
849 COSTS_N_INSNS (11), /* int_mult_di */
850 COSTS_N_INSNS (36), /* int_div_si */
851 COSTS_N_INSNS (68), /* int_div_di */
853 4 /* memory_latency */
860 COSTS_N_INSNS (5), /* int_mult_si */
861 COSTS_N_INSNS (5), /* int_mult_di */
862 COSTS_N_INSNS (41), /* int_div_si */
863 COSTS_N_INSNS (41), /* int_div_di */
865 4 /* memory_latency */
868 COSTS_N_INSNS (8), /* fp_add */
869 COSTS_N_INSNS (8), /* fp_mult_sf */
870 COSTS_N_INSNS (10), /* fp_mult_df */
871 COSTS_N_INSNS (34), /* fp_div_sf */
872 COSTS_N_INSNS (64), /* fp_div_df */
873 COSTS_N_INSNS (5), /* int_mult_si */
874 COSTS_N_INSNS (5), /* int_mult_di */
875 COSTS_N_INSNS (41), /* int_div_si */
876 COSTS_N_INSNS (41), /* int_div_di */
878 4 /* memory_latency */
881 COSTS_N_INSNS (4), /* fp_add */
882 COSTS_N_INSNS (4), /* fp_mult_sf */
883 COSTS_N_INSNS (5), /* fp_mult_df */
884 COSTS_N_INSNS (17), /* fp_div_sf */
885 COSTS_N_INSNS (32), /* fp_div_df */
886 COSTS_N_INSNS (5), /* int_mult_si */
887 COSTS_N_INSNS (5), /* int_mult_di */
888 COSTS_N_INSNS (41), /* int_div_si */
889 COSTS_N_INSNS (41), /* int_div_di */
891 4 /* memory_latency */
897 COSTS_N_INSNS (2), /* fp_add */
898 COSTS_N_INSNS (4), /* fp_mult_sf */
899 COSTS_N_INSNS (5), /* fp_mult_df */
900 COSTS_N_INSNS (12), /* fp_div_sf */
901 COSTS_N_INSNS (19), /* fp_div_df */
902 COSTS_N_INSNS (2), /* int_mult_si */
903 COSTS_N_INSNS (2), /* int_mult_di */
904 COSTS_N_INSNS (35), /* int_div_si */
905 COSTS_N_INSNS (35), /* int_div_di */
907 4 /* memory_latency */
910 COSTS_N_INSNS (3), /* fp_add */
911 COSTS_N_INSNS (5), /* fp_mult_sf */
912 COSTS_N_INSNS (6), /* fp_mult_df */
913 COSTS_N_INSNS (15), /* fp_div_sf */
914 COSTS_N_INSNS (16), /* fp_div_df */
915 COSTS_N_INSNS (17), /* int_mult_si */
916 COSTS_N_INSNS (17), /* int_mult_di */
917 COSTS_N_INSNS (38), /* int_div_si */
918 COSTS_N_INSNS (38), /* int_div_di */
920 6 /* memory_latency */
923 COSTS_N_INSNS (6), /* fp_add */
924 COSTS_N_INSNS (7), /* fp_mult_sf */
925 COSTS_N_INSNS (8), /* fp_mult_df */
926 COSTS_N_INSNS (23), /* fp_div_sf */
927 COSTS_N_INSNS (36), /* fp_div_df */
928 COSTS_N_INSNS (10), /* int_mult_si */
929 COSTS_N_INSNS (10), /* int_mult_di */
930 COSTS_N_INSNS (69), /* int_div_si */
931 COSTS_N_INSNS (69), /* int_div_di */
933 6 /* memory_latency */
945 /* The only costs that appear to be updated here are
946 integer multiplication. */
948 COSTS_N_INSNS (4), /* int_mult_si */
949 COSTS_N_INSNS (6), /* int_mult_di */
950 COSTS_N_INSNS (69), /* int_div_si */
951 COSTS_N_INSNS (69), /* int_div_di */
953 4 /* memory_latency */
965 COSTS_N_INSNS (6), /* fp_add */
966 COSTS_N_INSNS (4), /* fp_mult_sf */
967 COSTS_N_INSNS (5), /* fp_mult_df */
968 COSTS_N_INSNS (23), /* fp_div_sf */
969 COSTS_N_INSNS (36), /* fp_div_df */
970 COSTS_N_INSNS (5), /* int_mult_si */
971 COSTS_N_INSNS (5), /* int_mult_di */
972 COSTS_N_INSNS (36), /* int_div_si */
973 COSTS_N_INSNS (36), /* int_div_di */
975 4 /* memory_latency */
978 COSTS_N_INSNS (6), /* fp_add */
979 COSTS_N_INSNS (5), /* fp_mult_sf */
980 COSTS_N_INSNS (6), /* fp_mult_df */
981 COSTS_N_INSNS (30), /* fp_div_sf */
982 COSTS_N_INSNS (59), /* fp_div_df */
983 COSTS_N_INSNS (3), /* int_mult_si */
984 COSTS_N_INSNS (4), /* int_mult_di */
985 COSTS_N_INSNS (42), /* int_div_si */
986 COSTS_N_INSNS (74), /* int_div_di */
988 4 /* memory_latency */
991 COSTS_N_INSNS (6), /* fp_add */
992 COSTS_N_INSNS (5), /* fp_mult_sf */
993 COSTS_N_INSNS (6), /* fp_mult_df */
994 COSTS_N_INSNS (30), /* fp_div_sf */
995 COSTS_N_INSNS (59), /* fp_div_df */
996 COSTS_N_INSNS (5), /* int_mult_si */
997 COSTS_N_INSNS (9), /* int_mult_di */
998 COSTS_N_INSNS (42), /* int_div_si */
999 COSTS_N_INSNS (74), /* int_div_di */
1000 1, /* branch_cost */
1001 4 /* memory_latency */
1004 /* The only costs that are changed here are
1005 integer multiplication. */
1006 COSTS_N_INSNS (6), /* fp_add */
1007 COSTS_N_INSNS (7), /* fp_mult_sf */
1008 COSTS_N_INSNS (8), /* fp_mult_df */
1009 COSTS_N_INSNS (23), /* fp_div_sf */
1010 COSTS_N_INSNS (36), /* fp_div_df */
1011 COSTS_N_INSNS (5), /* int_mult_si */
1012 COSTS_N_INSNS (9), /* int_mult_di */
1013 COSTS_N_INSNS (69), /* int_div_si */
1014 COSTS_N_INSNS (69), /* int_div_di */
1015 1, /* branch_cost */
1016 4 /* memory_latency */
1022 /* The only costs that are changed here are
1023 integer multiplication. */
1024 COSTS_N_INSNS (6), /* fp_add */
1025 COSTS_N_INSNS (7), /* fp_mult_sf */
1026 COSTS_N_INSNS (8), /* fp_mult_df */
1027 COSTS_N_INSNS (23), /* fp_div_sf */
1028 COSTS_N_INSNS (36), /* fp_div_df */
1029 COSTS_N_INSNS (3), /* int_mult_si */
1030 COSTS_N_INSNS (8), /* int_mult_di */
1031 COSTS_N_INSNS (69), /* int_div_si */
1032 COSTS_N_INSNS (69), /* int_div_di */
1033 1, /* branch_cost */
1034 4 /* memory_latency */
1037 /* These costs are the same as the SB-1A below. */
1038 COSTS_N_INSNS (4), /* fp_add */
1039 COSTS_N_INSNS (4), /* fp_mult_sf */
1040 COSTS_N_INSNS (4), /* fp_mult_df */
1041 COSTS_N_INSNS (24), /* fp_div_sf */
1042 COSTS_N_INSNS (32), /* fp_div_df */
1043 COSTS_N_INSNS (3), /* int_mult_si */
1044 COSTS_N_INSNS (4), /* int_mult_di */
1045 COSTS_N_INSNS (36), /* int_div_si */
1046 COSTS_N_INSNS (68), /* int_div_di */
1047 1, /* branch_cost */
1048 4 /* memory_latency */
1051 /* These costs are the same as the SB-1 above. */
1052 COSTS_N_INSNS (4), /* fp_add */
1053 COSTS_N_INSNS (4), /* fp_mult_sf */
1054 COSTS_N_INSNS (4), /* fp_mult_df */
1055 COSTS_N_INSNS (24), /* fp_div_sf */
1056 COSTS_N_INSNS (32), /* fp_div_df */
1057 COSTS_N_INSNS (3), /* int_mult_si */
1058 COSTS_N_INSNS (4), /* int_mult_di */
1059 COSTS_N_INSNS (36), /* int_div_si */
1060 COSTS_N_INSNS (68), /* int_div_di */
1061 1, /* branch_cost */
1062 4 /* memory_latency */
1070 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
1071 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
1072 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
1075 /* Initialize the GCC target structure. */
1076 #undef TARGET_ASM_ALIGNED_HI_OP
1077 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
1078 #undef TARGET_ASM_ALIGNED_SI_OP
1079 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
1080 #undef TARGET_ASM_ALIGNED_DI_OP
1081 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
1083 #undef TARGET_ASM_FUNCTION_PROLOGUE
1084 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
1085 #undef TARGET_ASM_FUNCTION_EPILOGUE
1086 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
1087 #undef TARGET_ASM_SELECT_RTX_SECTION
1088 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
1089 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
1090 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
1092 #undef TARGET_SCHED_REORDER
1093 #define TARGET_SCHED_REORDER mips_sched_reorder
1094 #undef TARGET_SCHED_VARIABLE_ISSUE
1095 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
1096 #undef TARGET_SCHED_ADJUST_COST
1097 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
1098 #undef TARGET_SCHED_ISSUE_RATE
1099 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
1100 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1101 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
1102 mips_multipass_dfa_lookahead
1104 #undef TARGET_DEFAULT_TARGET_FLAGS
1105 #define TARGET_DEFAULT_TARGET_FLAGS \
1107 | TARGET_CPU_DEFAULT \
1108 | TARGET_ENDIAN_DEFAULT \
1109 | TARGET_FP_EXCEPTIONS_DEFAULT \
1110 | MASK_CHECK_ZERO_DIV \
1112 #undef TARGET_HANDLE_OPTION
1113 #define TARGET_HANDLE_OPTION mips_handle_option
1115 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1116 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
1118 #undef TARGET_VALID_POINTER_MODE
1119 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
1120 #undef TARGET_RTX_COSTS
1121 #define TARGET_RTX_COSTS mips_rtx_costs
1122 #undef TARGET_ADDRESS_COST
1123 #define TARGET_ADDRESS_COST mips_address_cost
1125 #undef TARGET_IN_SMALL_DATA_P
1126 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
1128 #undef TARGET_MACHINE_DEPENDENT_REORG
1129 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
1131 #undef TARGET_ASM_FILE_START
1132 #undef TARGET_ASM_FILE_END
1133 #define TARGET_ASM_FILE_START mips_file_start
1134 #define TARGET_ASM_FILE_END mips_file_end
1135 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
1136 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
1138 #undef TARGET_INIT_LIBFUNCS
1139 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
1141 #undef TARGET_BUILD_BUILTIN_VA_LIST
1142 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
1143 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1144 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
1146 #undef TARGET_PROMOTE_FUNCTION_ARGS
1147 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1148 #undef TARGET_PROMOTE_FUNCTION_RETURN
1149 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1150 #undef TARGET_PROMOTE_PROTOTYPES
1151 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
1153 #undef TARGET_RETURN_IN_MEMORY
1154 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
1155 #undef TARGET_RETURN_IN_MSB
1156 #define TARGET_RETURN_IN_MSB mips_return_in_msb
1158 #undef TARGET_ASM_OUTPUT_MI_THUNK
1159 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
1160 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1161 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1163 #undef TARGET_SETUP_INCOMING_VARARGS
1164 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
1165 #undef TARGET_STRICT_ARGUMENT_NAMING
1166 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
1167 #undef TARGET_MUST_PASS_IN_STACK
1168 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
1169 #undef TARGET_PASS_BY_REFERENCE
1170 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
1171 #undef TARGET_CALLEE_COPIES
1172 #define TARGET_CALLEE_COPIES mips_callee_copies
1173 #undef TARGET_ARG_PARTIAL_BYTES
1174 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
1176 #undef TARGET_MODE_REP_EXTENDED
1177 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
1179 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1180 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
1182 #undef TARGET_INIT_BUILTINS
1183 #define TARGET_INIT_BUILTINS mips_init_builtins
1184 #undef TARGET_EXPAND_BUILTIN
1185 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
1187 #undef TARGET_HAVE_TLS
1188 #define TARGET_HAVE_TLS HAVE_AS_TLS
1190 #undef TARGET_CANNOT_FORCE_CONST_MEM
1191 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
1193 #undef TARGET_ENCODE_SECTION_INFO
1194 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
1196 #undef TARGET_ATTRIBUTE_TABLE
1197 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
1199 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1200 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
1202 #undef TARGET_MIN_ANCHOR_OFFSET
1203 #define TARGET_MIN_ANCHOR_OFFSET -32768
1204 #undef TARGET_MAX_ANCHOR_OFFSET
1205 #define TARGET_MAX_ANCHOR_OFFSET 32767
1206 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1207 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
1208 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
1209 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
1211 struct gcc_target targetm = TARGET_INITIALIZER;
1213 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
1215 static enum mips_symbol_type
1216 mips_classify_symbol (rtx x)
1220 if (GET_CODE (x) == LABEL_REF)
1223 return SYMBOL_CONSTANT_POOL;
1224 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1225 return SYMBOL_GOT_LOCAL;
1226 return SYMBOL_GENERAL;
1229 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1231 if (SYMBOL_REF_TLS_MODEL (x))
1234 if (CONSTANT_POOL_ADDRESS_P (x))
1237 return SYMBOL_CONSTANT_POOL;
1239 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
1240 return SYMBOL_SMALL_DATA;
1243 /* Do not use small-data accesses for weak symbols; they may end up
1245 if (SYMBOL_REF_SMALL_P (x)
1246 && !SYMBOL_REF_WEAK (x))
1247 return SYMBOL_SMALL_DATA;
1249 if (TARGET_ABICALLS)
1251 decl = SYMBOL_REF_DECL (x);
1254 if (!SYMBOL_REF_LOCAL_P (x))
1255 return SYMBOL_GOT_GLOBAL;
1259 /* Don't use GOT accesses for locally-binding symbols if
1260 TARGET_ABSOLUTE_ABICALLS. Otherwise, there are three
1263 - o32 PIC (either with or without explicit relocs)
1264 - n32/n64 PIC without explicit relocs
1265 - n32/n64 PIC with explicit relocs
1267 In the first case, both local and global accesses will use an
1268 R_MIPS_GOT16 relocation. We must correctly predict which of
1269 the two semantics (local or global) the assembler and linker
1270 will apply. The choice doesn't depend on the symbol's
1271 visibility, so we deliberately ignore decl_visibility and
1274 In the second case, the assembler will not use R_MIPS_GOT16
1275 relocations, but it chooses between local and global accesses
1276 in the same way as for o32 PIC.
1278 In the third case we have more freedom since both forms of
1279 access will work for any kind of symbol. However, there seems
1280 little point in doing things differently.
1282 Note that weakref symbols are not TREE_PUBLIC, but their
1283 targets are global or weak symbols. Relocations in the
1284 object file will be against the target symbol, so it's
1285 that symbol's binding that matters here. */
1287 && (TREE_PUBLIC (decl) || DECL_WEAK (decl))
1288 && !(TARGET_ABSOLUTE_ABICALLS && targetm.binds_local_p (decl)))
1289 return SYMBOL_GOT_GLOBAL;
1292 if (!TARGET_ABSOLUTE_ABICALLS)
1293 return SYMBOL_GOT_LOCAL;
1296 return SYMBOL_GENERAL;
1300 /* Split X into a base and a constant offset, storing them in *BASE
1301 and *OFFSET respectively. */
1304 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
1308 if (GET_CODE (x) == CONST)
1311 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
1313 *offset += INTVAL (XEXP (x, 1));
1321 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
1322 to the same object as SYMBOL, or to the same object_block. */
1325 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
1327 if (GET_CODE (symbol) != SYMBOL_REF)
1330 if (CONSTANT_POOL_ADDRESS_P (symbol)
1332 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
1335 if (SYMBOL_REF_DECL (symbol) != 0
1337 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
1340 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
1341 && SYMBOL_REF_BLOCK (symbol)
1342 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
1343 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
1344 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
1351 /* Return true if X is a symbolic constant that can be calculated in
1352 the same way as a bare symbol. If it is, store the type of the
1353 symbol in *SYMBOL_TYPE. */
1356 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
1358 HOST_WIDE_INT offset;
1360 mips_split_const (x, &x, &offset);
1361 if (UNSPEC_ADDRESS_P (x))
1362 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1363 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1365 *symbol_type = mips_classify_symbol (x);
1366 if (*symbol_type == SYMBOL_TLS)
1375 /* Check whether a nonzero offset is valid for the underlying
1377 switch (*symbol_type)
1379 case SYMBOL_GENERAL:
1380 case SYMBOL_64_HIGH:
1383 /* If the target has 64-bit pointers and the object file only
1384 supports 32-bit symbols, the values of those symbols will be
1385 sign-extended. In this case we can't allow an arbitrary offset
1386 in case the 32-bit value X + OFFSET has a different sign from X. */
1387 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1388 return mips_offset_within_object_p (x, offset);
1390 /* In other cases the relocations can handle any offset. */
1393 case SYMBOL_CONSTANT_POOL:
1394 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1395 In this case, we no longer have access to the underlying constant,
1396 but the original symbol-based access was known to be valid. */
1397 if (GET_CODE (x) == LABEL_REF)
1402 case SYMBOL_SMALL_DATA:
1403 /* Make sure that the offset refers to something within the
1404 underlying object. This should guarantee that the final
1405 PC- or GP-relative offset is within the 16-bit limit. */
1406 return mips_offset_within_object_p (x, offset);
1408 case SYMBOL_GOT_LOCAL:
1409 case SYMBOL_GOTOFF_PAGE:
1410 /* The linker should provide enough local GOT entries for a
1411 16-bit offset. Larger offsets may lead to GOT overflow. */
1412 return SMALL_OPERAND (offset);
1414 case SYMBOL_GOT_GLOBAL:
1415 case SYMBOL_GOTOFF_GLOBAL:
1416 case SYMBOL_GOTOFF_CALL:
1417 case SYMBOL_GOTOFF_LOADGP:
1422 case SYMBOL_GOTTPREL:
1430 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1433 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1435 if (regno >= FIRST_PSEUDO_REGISTER)
1439 regno = reg_renumber[regno];
1442 /* These fake registers will be eliminated to either the stack or
1443 hard frame pointer, both of which are usually valid base registers.
1444 Reload deals with the cases where the eliminated form isn't valid. */
1445 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1448 /* In mips16 mode, the stack pointer can only address word and doubleword
1449 values, nothing smaller. There are two problems here:
1451 (a) Instantiating virtual registers can introduce new uses of the
1452 stack pointer. If these virtual registers are valid addresses,
1453 the stack pointer should be too.
1455 (b) Most uses of the stack pointer are not made explicit until
1456 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1457 We don't know until that stage whether we'll be eliminating to the
1458 stack pointer (which needs the restriction) or the hard frame
1459 pointer (which doesn't).
1461 All in all, it seems more consistent to only enforce this restriction
1462 during and after reload. */
1463 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1464 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1466 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1470 /* Return true if X is a valid base register for the given mode.
1471 Allow only hard registers if STRICT. */
1474 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1476 if (!strict && GET_CODE (x) == SUBREG)
1480 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1484 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1485 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1488 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1489 enum machine_mode mode)
1491 switch (symbol_type)
1493 case SYMBOL_GENERAL:
1494 return !TARGET_MIPS16;
1496 case SYMBOL_SMALL_DATA:
1499 case SYMBOL_CONSTANT_POOL:
1500 /* PC-relative addressing is only available for lw and ld. */
1501 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1503 case SYMBOL_GOT_LOCAL:
1506 case SYMBOL_GOT_GLOBAL:
1507 /* The address will have to be loaded from the GOT first. */
1510 case SYMBOL_GOTOFF_PAGE:
1511 case SYMBOL_GOTOFF_GLOBAL:
1512 case SYMBOL_GOTOFF_CALL:
1513 case SYMBOL_GOTOFF_LOADGP:
1518 case SYMBOL_GOTTPREL:
1520 case SYMBOL_64_HIGH:
1529 /* Return true if X is a valid address for machine mode MODE. If it is,
1530 fill in INFO appropriately. STRICT is true if we should only accept
1531 hard base registers. */
1534 mips_classify_address (struct mips_address_info *info, rtx x,
1535 enum machine_mode mode, int strict)
1537 switch (GET_CODE (x))
1541 info->type = ADDRESS_REG;
1543 info->offset = const0_rtx;
1544 return mips_valid_base_register_p (info->reg, mode, strict);
1547 info->type = ADDRESS_REG;
1548 info->reg = XEXP (x, 0);
1549 info->offset = XEXP (x, 1);
1550 return (mips_valid_base_register_p (info->reg, mode, strict)
1551 && const_arith_operand (info->offset, VOIDmode));
1554 info->type = ADDRESS_LO_SUM;
1555 info->reg = XEXP (x, 0);
1556 info->offset = XEXP (x, 1);
1557 return (mips_valid_base_register_p (info->reg, mode, strict)
1558 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1559 && mips_symbolic_address_p (info->symbol_type, mode)
1560 && mips_lo_relocs[info->symbol_type] != 0);
1563 /* Small-integer addresses don't occur very often, but they
1564 are legitimate if $0 is a valid base register. */
1565 info->type = ADDRESS_CONST_INT;
1566 return !TARGET_MIPS16 && SMALL_INT (x);
1571 info->type = ADDRESS_SYMBOLIC;
1572 return (mips_symbolic_constant_p (x, &info->symbol_type)
1573 && mips_symbolic_address_p (info->symbol_type, mode)
1574 && !mips_split_p[info->symbol_type]);
1581 /* Return true if X is a thread-local symbol. */
1584 mips_tls_operand_p (rtx x)
1586 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1589 /* Return true if X can not be forced into a constant pool. */
1592 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1594 return mips_tls_operand_p (*x);
1597 /* Return true if X can not be forced into a constant pool. */
1600 mips_cannot_force_const_mem (rtx x)
1603 HOST_WIDE_INT offset;
1607 /* As an optimization, reject constants that mips_legitimize_move
1610 Suppose we have a multi-instruction sequence that loads constant C
1611 into register R. If R does not get allocated a hard register, and
1612 R is used in an operand that allows both registers and memory
1613 references, reload will consider forcing C into memory and using
1614 one of the instruction's memory alternatives. Returning false
1615 here will force it to use an input reload instead. */
1616 if (GET_CODE (x) == CONST_INT)
1619 mips_split_const (x, &base, &offset);
1620 if (symbolic_operand (base, VOIDmode) && SMALL_OPERAND (offset))
1624 if (TARGET_HAVE_TLS && for_each_rtx (&x, &mips_tls_symbol_ref_1, 0))
1630 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. MIPS16 uses per-function
1631 constant pools, but normal-mode code doesn't need to. */
1634 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
1635 rtx x ATTRIBUTE_UNUSED)
1637 return !TARGET_MIPS16;
1640 /* Return the number of instructions needed to load a symbol of the
1641 given type into a register. If valid in an address, the same number
1642 of instructions are needed for loads and stores. Treat extended
1643 mips16 instructions as two instructions. */
1646 mips_symbol_insns (enum mips_symbol_type type)
1650 case SYMBOL_GENERAL:
1651 /* In mips16 code, general symbols must be fetched from the
1656 /* When using 64-bit symbols, we need 5 preparatory instructions,
1659 lui $at,%highest(symbol)
1660 daddiu $at,$at,%higher(symbol)
1662 daddiu $at,$at,%hi(symbol)
1665 The final address is then $at + %lo(symbol). With 32-bit
1666 symbols we just need a preparatory lui. */
1667 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1669 case SYMBOL_SMALL_DATA:
1672 case SYMBOL_CONSTANT_POOL:
1673 /* This case is for mips16 only. Assume we'll need an
1674 extended instruction. */
1677 case SYMBOL_GOT_LOCAL:
1678 case SYMBOL_GOT_GLOBAL:
1679 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1680 the local/global classification is accurate. See override_options
1683 The worst cases are:
1685 (1) For local symbols when generating o32 or o64 code. The assembler
1691 ...and the final address will be $at + %lo(symbol).
1693 (2) For global symbols when -mxgot. The assembler will use:
1695 lui $at,%got_hi(symbol)
1698 ...and the final address will be $at + %got_lo(symbol). */
1701 case SYMBOL_GOTOFF_PAGE:
1702 case SYMBOL_GOTOFF_GLOBAL:
1703 case SYMBOL_GOTOFF_CALL:
1704 case SYMBOL_GOTOFF_LOADGP:
1705 case SYMBOL_64_HIGH:
1711 case SYMBOL_GOTTPREL:
1713 /* Check whether the offset is a 16- or 32-bit value. */
1714 return mips_split_p[type] ? 2 : 1;
1717 /* We don't treat a bare TLS symbol as a constant. */
1723 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1726 mips_stack_address_p (rtx x, enum machine_mode mode)
1728 struct mips_address_info addr;
1730 return (mips_classify_address (&addr, x, mode, false)
1731 && addr.type == ADDRESS_REG
1732 && addr.reg == stack_pointer_rtx);
1735 /* Return true if a value at OFFSET bytes from BASE can be accessed
1736 using an unextended mips16 instruction. MODE is the mode of the
1739 Usually the offset in an unextended instruction is a 5-bit field.
1740 The offset is unsigned and shifted left once for HIs, twice
1741 for SIs, and so on. An exception is SImode accesses off the
1742 stack pointer, which have an 8-bit immediate field. */
1745 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1748 && GET_CODE (offset) == CONST_INT
1749 && INTVAL (offset) >= 0
1750 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1752 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1753 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1754 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1760 /* Return the number of instructions needed to load or store a value
1761 of mode MODE at X. Return 0 if X isn't valid for MODE.
1763 For mips16 code, count extended instructions as two instructions. */
1766 mips_address_insns (rtx x, enum machine_mode mode)
1768 struct mips_address_info addr;
1771 if (mode == BLKmode)
1772 /* BLKmode is used for single unaligned loads and stores. */
1775 /* Each word of a multi-word value will be accessed individually. */
1776 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1778 if (mips_classify_address (&addr, x, mode, false))
1783 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1787 case ADDRESS_LO_SUM:
1788 return (TARGET_MIPS16 ? factor * 2 : factor);
1790 case ADDRESS_CONST_INT:
1793 case ADDRESS_SYMBOLIC:
1794 return factor * mips_symbol_insns (addr.symbol_type);
1800 /* Likewise for constant X. */
1803 mips_const_insns (rtx x)
1805 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1806 enum mips_symbol_type symbol_type;
1807 HOST_WIDE_INT offset;
1809 switch (GET_CODE (x))
1813 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1814 || !mips_split_p[symbol_type])
1821 /* Unsigned 8-bit constants can be loaded using an unextended
1822 LI instruction. Unsigned 16-bit constants can be loaded
1823 using an extended LI. Negative constants must be loaded
1824 using LI and then negated. */
1825 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1826 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1827 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1828 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1831 return mips_build_integer (codes, INTVAL (x));
1835 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1841 /* See if we can refer to X directly. */
1842 if (mips_symbolic_constant_p (x, &symbol_type))
1843 return mips_symbol_insns (symbol_type);
1845 /* Otherwise try splitting the constant into a base and offset.
1846 16-bit offsets can be added using an extra addiu. Larger offsets
1847 must be calculated separately and then added to the base. */
1848 mips_split_const (x, &x, &offset);
1851 int n = mips_const_insns (x);
1854 if (SMALL_OPERAND (offset))
1857 return n + 1 + mips_build_integer (codes, offset);
1864 return mips_symbol_insns (mips_classify_symbol (x));
1872 /* Return the number of instructions needed for memory reference X.
1873 Count extended mips16 instructions as two instructions. */
1876 mips_fetch_insns (rtx x)
1878 gcc_assert (MEM_P (x));
1879 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1883 /* Return the number of instructions needed for an integer division. */
1886 mips_idiv_insns (void)
1891 if (TARGET_CHECK_ZERO_DIV)
1893 if (GENERATE_DIVIDE_TRAPS)
1899 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1904 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1905 returns a nonzero value if X is a legitimate address for a memory
1906 operand of the indicated MODE. STRICT is nonzero if this function
1907 is called during reload. */
1910 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1912 struct mips_address_info addr;
1914 return mips_classify_address (&addr, x, mode, strict);
1918 /* Copy VALUE to a register and return that register. If new psuedos
1919 are allowed, copy it into a new register, otherwise use DEST. */
1922 mips_force_temporary (rtx dest, rtx value)
1924 if (!no_new_pseudos)
1925 return force_reg (Pmode, value);
1928 emit_move_insn (copy_rtx (dest), value);
1934 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1935 and is used to load the high part into a register. */
1938 mips_split_symbol (rtx temp, rtx addr)
1943 high = mips16_gp_pseudo_reg ();
1945 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1946 return gen_rtx_LO_SUM (Pmode, high, addr);
1950 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1951 type SYMBOL_TYPE. */
1954 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1957 HOST_WIDE_INT offset;
1959 mips_split_const (address, &base, &offset);
1960 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1961 UNSPEC_ADDRESS_FIRST + symbol_type);
1962 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1966 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1967 high part to BASE and return the result. Just return BASE otherwise.
1968 TEMP is available as a temporary register if needed.
1970 The returned expression can be used as the first operand to a LO_SUM. */
1973 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1974 enum mips_symbol_type symbol_type)
1976 if (mips_split_p[symbol_type])
1978 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1979 addr = mips_force_temporary (temp, addr);
1980 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1986 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1987 mips_force_temporary; it is only needed when OFFSET is not a
1991 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1993 if (!SMALL_OPERAND (offset))
1998 /* Load the full offset into a register so that we can use
1999 an unextended instruction for the address itself. */
2000 high = GEN_INT (offset);
2005 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
2006 high = GEN_INT (CONST_HIGH_PART (offset));
2007 offset = CONST_LOW_PART (offset);
2009 high = mips_force_temporary (temp, high);
2010 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2012 return plus_constant (reg, offset);
2015 /* Emit a call to __tls_get_addr. SYM is the TLS symbol we are
2016 referencing, and TYPE is the symbol type to use (either global
2017 dynamic or local dynamic). V0 is an RTX for the return value
2018 location. The entire insn sequence is returned. */
2020 static GTY(()) rtx mips_tls_symbol;
2023 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2025 rtx insn, loc, tga, a0;
2027 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2029 if (!mips_tls_symbol)
2030 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2032 loc = mips_unspec_address (sym, type);
2036 emit_insn (gen_rtx_SET (Pmode, a0,
2037 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2038 tga = gen_rtx_MEM (Pmode, mips_tls_symbol);
2039 insn = emit_call_insn (gen_call_value (v0, tga, const0_rtx, const0_rtx));
2040 CONST_OR_PURE_CALL_P (insn) = 1;
2041 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), v0);
2042 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2043 insn = get_insns ();
2050 /* Generate the code to access LOC, a thread local SYMBOL_REF. The
2051 return value will be a valid address and move_operand (either a REG
2055 mips_legitimize_tls_address (rtx loc)
2057 rtx dest, insn, v0, v1, tmp1, tmp2, eqv;
2058 enum tls_model model;
2060 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2061 v1 = gen_rtx_REG (Pmode, GP_RETURN + 1);
2063 model = SYMBOL_REF_TLS_MODEL (loc);
2064 /* Only TARGET_ABICALLS code can have more than one module; other
2065 code must be be static and should not use a GOT. All TLS models
2066 reduce to local exec in this situation. */
2067 if (!TARGET_ABICALLS)
2068 model = TLS_MODEL_LOCAL_EXEC;
2072 case TLS_MODEL_GLOBAL_DYNAMIC:
2073 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2074 dest = gen_reg_rtx (Pmode);
2075 emit_libcall_block (insn, dest, v0, loc);
2078 case TLS_MODEL_LOCAL_DYNAMIC:
2079 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2080 tmp1 = gen_reg_rtx (Pmode);
2082 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2083 share the LDM result with other LD model accesses. */
2084 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2086 emit_libcall_block (insn, tmp1, v0, eqv);
2088 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2089 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2090 mips_unspec_address (loc, SYMBOL_DTPREL));
2093 case TLS_MODEL_INITIAL_EXEC:
2094 tmp1 = gen_reg_rtx (Pmode);
2095 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2096 if (Pmode == DImode)
2098 emit_insn (gen_tls_get_tp_di (v1));
2099 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2103 emit_insn (gen_tls_get_tp_si (v1));
2104 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2106 dest = gen_reg_rtx (Pmode);
2107 emit_insn (gen_add3_insn (dest, tmp1, v1));
2110 case TLS_MODEL_LOCAL_EXEC:
2111 if (Pmode == DImode)
2112 emit_insn (gen_tls_get_tp_di (v1));
2114 emit_insn (gen_tls_get_tp_si (v1));
2116 tmp1 = mips_unspec_offset_high (NULL, v1, loc, SYMBOL_TPREL);
2117 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2118 mips_unspec_address (loc, SYMBOL_TPREL));
2128 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
2129 be legitimized in a way that the generic machinery might not expect,
2130 put the new address in *XLOC and return true. MODE is the mode of
2131 the memory being accessed. */
2134 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
2136 enum mips_symbol_type symbol_type;
2138 if (mips_tls_operand_p (*xloc))
2140 *xloc = mips_legitimize_tls_address (*xloc);
2144 /* See if the address can split into a high part and a LO_SUM. */
2145 if (mips_symbolic_constant_p (*xloc, &symbol_type)
2146 && mips_symbolic_address_p (symbol_type, mode)
2147 && mips_split_p[symbol_type])
2149 *xloc = mips_split_symbol (0, *xloc);
2153 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
2155 /* Handle REG + CONSTANT using mips_add_offset. */
2158 reg = XEXP (*xloc, 0);
2159 if (!mips_valid_base_register_p (reg, mode, 0))
2160 reg = copy_to_mode_reg (Pmode, reg);
2161 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
2169 /* Subroutine of mips_build_integer (with the same interface).
2170 Assume that the final action in the sequence should be a left shift. */
2173 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
2175 unsigned int i, shift;
2177 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
2178 since signed numbers are easier to load than unsigned ones. */
2180 while ((value & 1) == 0)
2181 value /= 2, shift++;
2183 i = mips_build_integer (codes, value);
2184 codes[i].code = ASHIFT;
2185 codes[i].value = shift;
2190 /* As for mips_build_shift, but assume that the final action will be
2191 an IOR or PLUS operation. */
2194 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
2196 unsigned HOST_WIDE_INT high;
2199 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
2200 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
2202 /* The constant is too complex to load with a simple lui/ori pair
2203 so our goal is to clear as many trailing zeros as possible.
2204 In this case, we know bit 16 is set and that the low 16 bits
2205 form a negative number. If we subtract that number from VALUE,
2206 we will clear at least the lowest 17 bits, maybe more. */
2207 i = mips_build_integer (codes, CONST_HIGH_PART (value));
2208 codes[i].code = PLUS;
2209 codes[i].value = CONST_LOW_PART (value);
2213 i = mips_build_integer (codes, high);
2214 codes[i].code = IOR;
2215 codes[i].value = value & 0xffff;
2221 /* Fill CODES with a sequence of rtl operations to load VALUE.
2222 Return the number of operations needed. */
2225 mips_build_integer (struct mips_integer_op *codes,
2226 unsigned HOST_WIDE_INT value)
2228 if (SMALL_OPERAND (value)
2229 || SMALL_OPERAND_UNSIGNED (value)
2230 || LUI_OPERAND (value))
2232 /* The value can be loaded with a single instruction. */
2233 codes[0].code = UNKNOWN;
2234 codes[0].value = value;
2237 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
2239 /* Either the constant is a simple LUI/ORI combination or its
2240 lowest bit is set. We don't want to shift in this case. */
2241 return mips_build_lower (codes, value);
2243 else if ((value & 0xffff) == 0)
2245 /* The constant will need at least three actions. The lowest
2246 16 bits are clear, so the final action will be a shift. */
2247 return mips_build_shift (codes, value);
2251 /* The final action could be a shift, add or inclusive OR.
2252 Rather than use a complex condition to select the best
2253 approach, try both mips_build_shift and mips_build_lower
2254 and pick the one that gives the shortest sequence.
2255 Note that this case is only used once per constant. */
2256 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
2257 unsigned int cost, alt_cost;
2259 cost = mips_build_shift (codes, value);
2260 alt_cost = mips_build_lower (alt_codes, value);
2261 if (alt_cost < cost)
2263 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
2271 /* Load VALUE into DEST, using TEMP as a temporary register if need be. */
2274 mips_move_integer (rtx dest, rtx temp, unsigned HOST_WIDE_INT value)
2276 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2277 enum machine_mode mode;
2278 unsigned int i, cost;
2281 mode = GET_MODE (dest);
2282 cost = mips_build_integer (codes, value);
2284 /* Apply each binary operation to X. Invariant: X is a legitimate
2285 source operand for a SET pattern. */
2286 x = GEN_INT (codes[0].value);
2287 for (i = 1; i < cost; i++)
2291 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
2295 x = force_reg (mode, x);
2296 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
2299 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
2303 /* Subroutine of mips_legitimize_move. Move constant SRC into register
2304 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2308 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
2311 HOST_WIDE_INT offset;
2313 /* Split moves of big integers into smaller pieces. */
2314 if (splittable_const_int_operand (src, mode))
2316 mips_move_integer (dest, dest, INTVAL (src));
2320 /* Split moves of symbolic constants into high/low pairs. */
2321 if (splittable_symbolic_operand (src, mode))
2323 emit_insn (gen_rtx_SET (VOIDmode, dest, mips_split_symbol (dest, src)));
2327 if (mips_tls_operand_p (src))
2329 emit_move_insn (dest, mips_legitimize_tls_address (src));
2333 /* If we have (const (plus symbol offset)), load the symbol first
2334 and then add in the offset. This is usually better than forcing
2335 the constant into memory, at least in non-mips16 code. */
2336 mips_split_const (src, &base, &offset);
2339 && (!no_new_pseudos || SMALL_OPERAND (offset)))
2341 base = mips_force_temporary (dest, base);
2342 emit_move_insn (dest, mips_add_offset (0, base, offset));
2346 src = force_const_mem (mode, src);
2348 /* When using explicit relocs, constant pool references are sometimes
2349 not legitimate addresses. */
2350 if (!memory_operand (src, VOIDmode))
2351 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
2352 emit_move_insn (dest, src);
2356 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
2357 sequence that is valid. */
2360 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
2362 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
2364 emit_move_insn (dest, force_reg (mode, src));
2368 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
2369 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2370 && REG_P (src) && MD_REG_P (REGNO (src))
2371 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2373 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2374 if (GET_MODE_SIZE (mode) <= 4)
2375 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2376 gen_rtx_REG (SImode, REGNO (src)),
2377 gen_rtx_REG (SImode, other_regno)));
2379 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2380 gen_rtx_REG (DImode, REGNO (src)),
2381 gen_rtx_REG (DImode, other_regno)));
2385 /* We need to deal with constants that would be legitimate
2386 immediate_operands but not legitimate move_operands. */
2387 if (CONSTANT_P (src) && !move_operand (src, mode))
2389 mips_legitimize_const_move (mode, dest, src);
2390 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2396 /* We need a lot of little routines to check constant values on the
2397 mips16. These are used to figure out how long the instruction will
2398 be. It would be much better to do this using constraints, but
2399 there aren't nearly enough letters available. */
2402 m16_check_op (rtx op, int low, int high, int mask)
2404 return (GET_CODE (op) == CONST_INT
2405 && INTVAL (op) >= low
2406 && INTVAL (op) <= high
2407 && (INTVAL (op) & mask) == 0);
2411 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2413 return m16_check_op (op, 0x1, 0x8, 0);
2417 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2419 return m16_check_op (op, - 0x8, 0x7, 0);
2423 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2425 return m16_check_op (op, - 0x7, 0x8, 0);
2429 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2431 return m16_check_op (op, - 0x10, 0xf, 0);
2435 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2437 return m16_check_op (op, - 0xf, 0x10, 0);
2441 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2443 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2447 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2449 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2453 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2455 return m16_check_op (op, - 0x80, 0x7f, 0);
2459 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2461 return m16_check_op (op, - 0x7f, 0x80, 0);
2465 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2467 return m16_check_op (op, 0x0, 0xff, 0);
2471 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2473 return m16_check_op (op, - 0xff, 0x0, 0);
2477 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2479 return m16_check_op (op, - 0x1, 0xfe, 0);
2483 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2485 return m16_check_op (op, 0x0, 0xff << 2, 3);
2489 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2491 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2495 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2497 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2501 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2503 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2507 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2509 enum machine_mode mode = GET_MODE (x);
2510 bool float_mode_p = FLOAT_MODE_P (mode);
2517 /* A number between 1 and 8 inclusive is efficient for a shift.
2518 Otherwise, we will need an extended instruction. */
2519 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2520 || (outer_code) == LSHIFTRT)
2522 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2525 *total = COSTS_N_INSNS (1);
2529 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2530 if ((outer_code) == XOR
2531 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2537 /* We may be able to use slt or sltu for a comparison with a
2538 signed 16 bit value. (The boundary conditions aren't quite
2539 right, but this is just a heuristic anyhow.) */
2540 if (((outer_code) == LT || (outer_code) == LE
2541 || (outer_code) == GE || (outer_code) == GT
2542 || (outer_code) == LTU || (outer_code) == LEU
2543 || (outer_code) == GEU || (outer_code) == GTU)
2544 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2550 /* Equality comparisons with 0 are cheap. */
2551 if (((outer_code) == EQ || (outer_code) == NE)
2558 /* Constants in the range 0...255 can be loaded with an unextended
2559 instruction. They are therefore as cheap as a register move.
2561 Given the choice between "li R1,0...255" and "move R1,R2"
2562 (where R2 is a known constant), it is usually better to use "li",
2563 since we do not want to unnecessarily extend the lifetime
2565 if (outer_code == SET
2567 && INTVAL (x) < 256)
2575 /* These can be used anywhere. */
2580 /* Otherwise fall through to the handling below because
2581 we'll need to construct the constant. */
2587 if (LEGITIMATE_CONSTANT_P (x))
2589 *total = COSTS_N_INSNS (1);
2594 /* The value will need to be fetched from the constant pool. */
2595 *total = CONSTANT_POOL_COST;
2601 /* If the address is legitimate, return the number of
2602 instructions it needs, otherwise use the default handling. */
2603 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2606 *total = COSTS_N_INSNS (n + 1);
2613 *total = COSTS_N_INSNS (6);
2617 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2623 if (mode == DImode && !TARGET_64BIT)
2625 *total = COSTS_N_INSNS (2);
2633 if (mode == DImode && !TARGET_64BIT)
2635 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2643 *total = COSTS_N_INSNS (1);
2645 *total = COSTS_N_INSNS (4);
2649 *total = COSTS_N_INSNS (1);
2656 *total = mips_cost->fp_add;
2660 else if (mode == DImode && !TARGET_64BIT)
2662 *total = COSTS_N_INSNS (4);
2668 if (mode == DImode && !TARGET_64BIT)
2670 *total = COSTS_N_INSNS (4);
2677 *total = mips_cost->fp_mult_sf;
2679 else if (mode == DFmode)
2680 *total = mips_cost->fp_mult_df;
2682 else if (mode == SImode)
2683 *total = mips_cost->int_mult_si;
2686 *total = mips_cost->int_mult_di;
2695 *total = mips_cost->fp_div_sf;
2697 *total = mips_cost->fp_div_df;
2706 *total = mips_cost->int_div_di;
2708 *total = mips_cost->int_div_si;
2713 /* A sign extend from SImode to DImode in 64 bit mode is often
2714 zero instructions, because the result can often be used
2715 directly by another instruction; we'll call it one. */
2716 if (TARGET_64BIT && mode == DImode
2717 && GET_MODE (XEXP (x, 0)) == SImode)
2718 *total = COSTS_N_INSNS (1);
2720 *total = COSTS_N_INSNS (2);
2724 if (TARGET_64BIT && mode == DImode
2725 && GET_MODE (XEXP (x, 0)) == SImode)
2726 *total = COSTS_N_INSNS (2);
2728 *total = COSTS_N_INSNS (1);
2732 case UNSIGNED_FLOAT:
2735 case FLOAT_TRUNCATE:
2737 *total = mips_cost->fp_add;
2745 /* Provide the costs of an addressing mode that contains ADDR.
2746 If ADDR is not a valid address, its cost is irrelevant. */
2749 mips_address_cost (rtx addr)
2751 return mips_address_insns (addr, SImode);
2754 /* Return one word of double-word value OP, taking into account the fixed
2755 endianness of certain registers. HIGH_P is true to select the high part,
2756 false to select the low part. */
2759 mips_subword (rtx op, int high_p)
2762 enum machine_mode mode;
2764 mode = GET_MODE (op);
2765 if (mode == VOIDmode)
2768 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2769 byte = UNITS_PER_WORD;
2775 if (FP_REG_P (REGNO (op)))
2776 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2777 if (ACC_HI_REG_P (REGNO (op)))
2778 return gen_rtx_REG (word_mode, high_p ? REGNO (op) : REGNO (op) + 1);
2782 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2784 return simplify_gen_subreg (word_mode, op, mode, byte);
2788 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2791 mips_split_64bit_move_p (rtx dest, rtx src)
2796 /* FP->FP moves can be done in a single instruction. */
2797 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2800 /* Check for floating-point loads and stores. They can be done using
2801 ldc1 and sdc1 on MIPS II and above. */
2804 if (FP_REG_RTX_P (dest) && MEM_P (src))
2806 if (FP_REG_RTX_P (src) && MEM_P (dest))
2813 /* Split a 64-bit move from SRC to DEST assuming that
2814 mips_split_64bit_move_p holds.
2816 Moves into and out of FPRs cause some difficulty here. Such moves
2817 will always be DFmode, since paired FPRs are not allowed to store
2818 DImode values. The most natural representation would be two separate
2819 32-bit moves, such as:
2821 (set (reg:SI $f0) (mem:SI ...))
2822 (set (reg:SI $f1) (mem:SI ...))
2824 However, the second insn is invalid because odd-numbered FPRs are
2825 not allowed to store independent values. Use the patterns load_df_low,
2826 load_df_high and store_df_high instead. */
2829 mips_split_64bit_move (rtx dest, rtx src)
2831 if (FP_REG_RTX_P (dest))
2833 /* Loading an FPR from memory or from GPRs. */
2834 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2835 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2838 else if (FP_REG_RTX_P (src))
2840 /* Storing an FPR into memory or GPRs. */
2841 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2842 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2846 /* The operation can be split into two normal moves. Decide in
2847 which order to do them. */
2850 low_dest = mips_subword (dest, 0);
2851 if (REG_P (low_dest)
2852 && reg_overlap_mentioned_p (low_dest, src))
2854 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2855 emit_move_insn (low_dest, mips_subword (src, 0));
2859 emit_move_insn (low_dest, mips_subword (src, 0));
2860 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2865 /* Return the appropriate instructions to move SRC into DEST. Assume
2866 that SRC is operand 1 and DEST is operand 0. */
2869 mips_output_move (rtx dest, rtx src)
2871 enum rtx_code dest_code, src_code;
2874 dest_code = GET_CODE (dest);
2875 src_code = GET_CODE (src);
2876 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2878 if (dbl_p && mips_split_64bit_move_p (dest, src))
2881 if ((src_code == REG && GP_REG_P (REGNO (src)))
2882 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2884 if (dest_code == REG)
2886 if (GP_REG_P (REGNO (dest)))
2887 return "move\t%0,%z1";
2889 if (MD_REG_P (REGNO (dest)))
2892 if (DSP_ACC_REG_P (REGNO (dest)))
2894 static char retval[] = "mt__\t%z1,%q0";
2895 retval[2] = reg_names[REGNO (dest)][4];
2896 retval[3] = reg_names[REGNO (dest)][5];
2900 if (FP_REG_P (REGNO (dest)))
2901 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2903 if (ALL_COP_REG_P (REGNO (dest)))
2905 static char retval[] = "dmtc_\t%z1,%0";
2907 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2908 return (dbl_p ? retval : retval + 1);
2911 if (dest_code == MEM)
2912 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2914 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2916 if (src_code == REG)
2918 if (DSP_ACC_REG_P (REGNO (src)))
2920 static char retval[] = "mf__\t%0,%q1";
2921 retval[2] = reg_names[REGNO (src)][4];
2922 retval[3] = reg_names[REGNO (src)][5];
2926 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2927 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2929 if (FP_REG_P (REGNO (src)))
2930 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2932 if (ALL_COP_REG_P (REGNO (src)))
2934 static char retval[] = "dmfc_\t%0,%1";
2936 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2937 return (dbl_p ? retval : retval + 1);
2941 if (src_code == MEM)
2942 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2944 if (src_code == CONST_INT)
2946 /* Don't use the X format, because that will give out of
2947 range numbers for 64 bit hosts and 32 bit targets. */
2949 return "li\t%0,%1\t\t\t# %X1";
2951 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2954 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2958 if (src_code == HIGH)
2959 return "lui\t%0,%h1";
2961 if (CONST_GP_P (src))
2962 return "move\t%0,%1";
2964 if (symbolic_operand (src, VOIDmode))
2965 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2967 if (src_code == REG && FP_REG_P (REGNO (src)))
2969 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2971 if (GET_MODE (dest) == V2SFmode)
2972 return "mov.ps\t%0,%1";
2974 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2977 if (dest_code == MEM)
2978 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2980 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2982 if (src_code == MEM)
2983 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2985 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2987 static char retval[] = "l_c_\t%0,%1";
2989 retval[1] = (dbl_p ? 'd' : 'w');
2990 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2993 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2995 static char retval[] = "s_c_\t%1,%0";
2997 retval[1] = (dbl_p ? 'd' : 'w');
2998 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
3004 /* Restore $gp from its save slot. Valid only when using o32 or
3008 mips_restore_gp (void)
3012 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
3014 address = mips_add_offset (pic_offset_table_rtx,
3015 frame_pointer_needed
3016 ? hard_frame_pointer_rtx
3017 : stack_pointer_rtx,
3018 current_function_outgoing_args_size);
3019 slot = gen_rtx_MEM (Pmode, address);
3021 emit_move_insn (pic_offset_table_rtx, slot);
3022 if (!TARGET_EXPLICIT_RELOCS)
3023 emit_insn (gen_blockage ());
3026 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
3029 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
3031 emit_insn (gen_rtx_SET (VOIDmode, target,
3032 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
3035 /* Return true if CMP1 is a suitable second operand for relational
3036 operator CODE. See also the *sCC patterns in mips.md. */
3039 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
3045 return reg_or_0_operand (cmp1, VOIDmode);
3049 return !TARGET_MIPS16 && cmp1 == const1_rtx;
3053 return arith_operand (cmp1, VOIDmode);
3056 return sle_operand (cmp1, VOIDmode);
3059 return sleu_operand (cmp1, VOIDmode);
3066 /* Canonicalize LE or LEU comparisons into LT comparisons when
3067 possible to avoid extra instructions or inverting the
3071 mips_canonicalize_comparison (enum rtx_code *code, rtx *cmp1,
3072 enum machine_mode mode)
3074 HOST_WIDE_INT original, plus_one;
3076 if (GET_CODE (*cmp1) != CONST_INT)
3079 original = INTVAL (*cmp1);
3080 plus_one = trunc_int_for_mode ((unsigned HOST_WIDE_INT) original + 1, mode);
3085 if (original < plus_one)
3088 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3097 *cmp1 = force_reg (mode, GEN_INT (plus_one));
3110 /* Compare CMP0 and CMP1 using relational operator CODE and store the
3111 result in TARGET. CMP0 and TARGET are register_operands that have
3112 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
3113 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
3116 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
3117 rtx target, rtx cmp0, rtx cmp1)
3119 /* First see if there is a MIPS instruction that can do this operation
3120 with CMP1 in its current form. If not, try to canonicalize the
3121 comparison to LT. If that fails, try doing the same for the
3122 inverse operation. If that also fails, force CMP1 into a register
3124 if (mips_relational_operand_ok_p (code, cmp1))
3125 mips_emit_binary (code, target, cmp0, cmp1);
3126 else if (mips_canonicalize_comparison (&code, &cmp1, GET_MODE (target)))
3127 mips_emit_binary (code, target, cmp0, cmp1);
3130 enum rtx_code inv_code = reverse_condition (code);
3131 if (!mips_relational_operand_ok_p (inv_code, cmp1))
3133 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
3134 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
3136 else if (invert_ptr == 0)
3138 rtx inv_target = gen_reg_rtx (GET_MODE (target));
3139 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
3140 mips_emit_binary (XOR, target, inv_target, const1_rtx);
3144 *invert_ptr = !*invert_ptr;
3145 mips_emit_binary (inv_code, target, cmp0, cmp1);
3150 /* Return a register that is zero iff CMP0 and CMP1 are equal.
3151 The register will have the same mode as CMP0. */
3154 mips_zero_if_equal (rtx cmp0, rtx cmp1)
3156 if (cmp1 == const0_rtx)
3159 if (uns_arith_operand (cmp1, VOIDmode))
3160 return expand_binop (GET_MODE (cmp0), xor_optab,
3161 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3163 return expand_binop (GET_MODE (cmp0), sub_optab,
3164 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
3167 /* Convert *CODE into a code that can be used in a floating-point
3168 scc instruction (c.<cond>.<fmt>). Return true if the values of
3169 the condition code registers will be inverted, with 0 indicating
3170 that the condition holds. */
3173 mips_reverse_fp_cond_p (enum rtx_code *code)
3180 *code = reverse_condition_maybe_unordered (*code);
3188 /* Convert a comparison into something that can be used in a branch or
3189 conditional move. cmp_operands[0] and cmp_operands[1] are the values
3190 being compared and *CODE is the code used to compare them.
3192 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
3193 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
3194 otherwise any standard branch condition can be used. The standard branch
3197 - EQ/NE between two registers.
3198 - any comparison between a register and zero. */
3201 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
3203 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
3205 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
3207 *op0 = cmp_operands[0];
3208 *op1 = cmp_operands[1];
3210 else if (*code == EQ || *code == NE)
3214 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3219 *op0 = cmp_operands[0];
3220 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
3225 /* The comparison needs a separate scc instruction. Store the
3226 result of the scc in *OP0 and compare it against zero. */
3227 bool invert = false;
3228 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
3230 mips_emit_int_relational (*code, &invert, *op0,
3231 cmp_operands[0], cmp_operands[1]);
3232 *code = (invert ? EQ : NE);
3237 enum rtx_code cmp_code;
3239 /* Floating-point tests use a separate c.cond.fmt comparison to
3240 set a condition code register. The branch or conditional move
3241 will then compare that register against zero.
3243 Set CMP_CODE to the code of the comparison instruction and
3244 *CODE to the code that the branch or move should use. */
3246 *code = mips_reverse_fp_cond_p (&cmp_code) ? EQ : NE;
3248 ? gen_reg_rtx (CCmode)
3249 : gen_rtx_REG (CCmode, FPSW_REGNUM));
3251 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
3255 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
3256 Store the result in TARGET and return true if successful.
3258 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
3261 mips_emit_scc (enum rtx_code code, rtx target)
3263 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
3266 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
3267 if (code == EQ || code == NE)
3269 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
3270 mips_emit_binary (code, target, zie, const0_rtx);
3273 mips_emit_int_relational (code, 0, target,
3274 cmp_operands[0], cmp_operands[1]);
3278 /* Emit the common code for doing conditional branches.
3279 operand[0] is the label to jump to.
3280 The comparison operands are saved away by cmp{si,di,sf,df}. */
3283 gen_conditional_branch (rtx *operands, enum rtx_code code)
3285 rtx op0, op1, condition;
3287 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
3288 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3289 emit_jump_insn (gen_condjump (condition, operands[0]));
3294 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
3295 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
3298 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
3299 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
3304 reversed_p = mips_reverse_fp_cond_p (&cond);
3305 cmp_result = gen_reg_rtx (CCV2mode);
3306 emit_insn (gen_scc_ps (cmp_result,
3307 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
3309 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
3312 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
3316 /* Emit the common code for conditional moves. OPERANDS is the array
3317 of operands passed to the conditional move define_expand. */
3320 gen_conditional_move (rtx *operands)
3325 code = GET_CODE (operands[1]);
3326 mips_emit_compare (&code, &op0, &op1, true);
3327 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3328 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
3329 gen_rtx_fmt_ee (code,
3332 operands[2], operands[3])));
3335 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3336 the conditional_trap expander. */
3339 mips_gen_conditional_trap (rtx *operands)
3342 enum rtx_code cmp_code = GET_CODE (operands[0]);
3343 enum machine_mode mode = GET_MODE (cmp_operands[0]);
3345 /* MIPS conditional trap machine instructions don't have GT or LE
3346 flavors, so we must invert the comparison and convert to LT and
3347 GE, respectively. */
3350 case GT: cmp_code = LT; break;
3351 case LE: cmp_code = GE; break;
3352 case GTU: cmp_code = LTU; break;
3353 case LEU: cmp_code = GEU; break;
3356 if (cmp_code == GET_CODE (operands[0]))
3358 op0 = cmp_operands[0];
3359 op1 = cmp_operands[1];
3363 op0 = cmp_operands[1];
3364 op1 = cmp_operands[0];
3366 op0 = force_reg (mode, op0);
3367 if (!arith_operand (op1, mode))
3368 op1 = force_reg (mode, op1);
3370 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3371 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
3375 /* Load function address ADDR into register DEST. SIBCALL_P is true
3376 if the address is needed for a sibling call. */
3379 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3381 /* If we're generating PIC, and this call is to a global function,
3382 try to allow its address to be resolved lazily. This isn't
3383 possible for NewABI sibcalls since the value of $gp on entry
3384 to the stub would be our caller's gp, not ours. */
3385 if (TARGET_EXPLICIT_RELOCS
3386 && !(sibcall_p && TARGET_NEWABI)
3387 && global_got_operand (addr, VOIDmode))
3389 rtx high, lo_sum_symbol;
3391 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3392 addr, SYMBOL_GOTOFF_CALL);
3393 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3394 if (Pmode == SImode)
3395 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3397 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3400 emit_move_insn (dest, addr);
3404 /* Expand a call or call_value instruction. RESULT is where the
3405 result will go (null for calls), ADDR is the address of the
3406 function, ARGS_SIZE is the size of the arguments and AUX is
3407 the value passed to us by mips_function_arg. SIBCALL_P is true
3408 if we are expanding a sibling call, false if we're expanding
3412 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3414 rtx orig_addr, pattern, insn;
3417 if (!call_insn_operand (addr, VOIDmode))
3419 addr = gen_reg_rtx (Pmode);
3420 mips_load_call_address (addr, orig_addr, sibcall_p);
3424 && mips16_hard_float
3425 && build_mips16_call_stub (result, addr, args_size,
3426 aux == 0 ? 0 : (int) GET_MODE (aux)))
3430 pattern = (sibcall_p
3431 ? gen_sibcall_internal (addr, args_size)
3432 : gen_call_internal (addr, args_size));
3433 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3437 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3438 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3441 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3442 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3445 pattern = (sibcall_p
3446 ? gen_sibcall_value_internal (result, addr, args_size)
3447 : gen_call_value_internal (result, addr, args_size));
3449 insn = emit_call_insn (pattern);
3451 /* Lazy-binding stubs require $gp to be valid on entry. */
3452 if (global_got_operand (orig_addr, VOIDmode))
3453 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3457 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3460 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3461 tree exp ATTRIBUTE_UNUSED)
3463 return TARGET_SIBCALLS;
3466 /* Emit code to move general operand SRC into condition-code
3467 register DEST. SCRATCH is a scratch TFmode float register.
3474 where FP1 and FP2 are single-precision float registers
3475 taken from SCRATCH. */
3478 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3482 /* Change the source to SFmode. */
3484 src = adjust_address (src, SFmode, 0);
3485 else if (REG_P (src) || GET_CODE (src) == SUBREG)
3486 src = gen_rtx_REG (SFmode, true_regnum (src));
3488 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3489 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3491 emit_move_insn (copy_rtx (fp1), src);
3492 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3493 emit_insn (gen_slt_sf (dest, fp2, fp1));
3496 /* Emit code to change the current function's return address to
3497 ADDRESS. SCRATCH is available as a scratch register, if needed.
3498 ADDRESS and SCRATCH are both word-mode GPRs. */
3501 mips_set_return_address (rtx address, rtx scratch)
3505 compute_frame_size (get_frame_size ());
3506 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
3507 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
3508 cfun->machine->frame.gp_sp_offset);
3510 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
3513 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3514 Assume that the areas do not overlap. */
3517 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3519 HOST_WIDE_INT offset, delta;
3520 unsigned HOST_WIDE_INT bits;
3522 enum machine_mode mode;
3525 /* Work out how many bits to move at a time. If both operands have
3526 half-word alignment, it is usually better to move in half words.
3527 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3528 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3529 Otherwise move word-sized chunks. */
3530 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3531 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3532 bits = BITS_PER_WORD / 2;
3534 bits = BITS_PER_WORD;
3536 mode = mode_for_size (bits, MODE_INT, 0);
3537 delta = bits / BITS_PER_UNIT;
3539 /* Allocate a buffer for the temporary registers. */
3540 regs = alloca (sizeof (rtx) * length / delta);
3542 /* Load as many BITS-sized chunks as possible. Use a normal load if
3543 the source has enough alignment, otherwise use left/right pairs. */
3544 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3546 regs[i] = gen_reg_rtx (mode);
3547 if (MEM_ALIGN (src) >= bits)
3548 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3551 rtx part = adjust_address (src, BLKmode, offset);
3552 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3557 /* Copy the chunks to the destination. */
3558 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3559 if (MEM_ALIGN (dest) >= bits)
3560 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3563 rtx part = adjust_address (dest, BLKmode, offset);
3564 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3568 /* Mop up any left-over bytes. */
3569 if (offset < length)
3571 src = adjust_address (src, BLKmode, offset);
3572 dest = adjust_address (dest, BLKmode, offset);
3573 move_by_pieces (dest, src, length - offset,
3574 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3578 #define MAX_MOVE_REGS 4
3579 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3582 /* Helper function for doing a loop-based block operation on memory
3583 reference MEM. Each iteration of the loop will operate on LENGTH
3586 Create a new base register for use within the loop and point it to
3587 the start of MEM. Create a new memory reference that uses this
3588 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3591 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3592 rtx *loop_reg, rtx *loop_mem)
3594 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3596 /* Although the new mem does not refer to a known location,
3597 it does keep up to LENGTH bytes of alignment. */
3598 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3599 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3603 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3604 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3605 memory regions do not overlap. */
3608 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3610 rtx label, src_reg, dest_reg, final_src;
3611 HOST_WIDE_INT leftover;
3613 leftover = length % MAX_MOVE_BYTES;
3616 /* Create registers and memory references for use within the loop. */
3617 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3618 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3620 /* Calculate the value that SRC_REG should have after the last iteration
3622 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3625 /* Emit the start of the loop. */
3626 label = gen_label_rtx ();
3629 /* Emit the loop body. */
3630 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3632 /* Move on to the next block. */
3633 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3634 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3636 /* Emit the loop condition. */
3637 if (Pmode == DImode)
3638 emit_insn (gen_cmpdi (src_reg, final_src));
3640 emit_insn (gen_cmpsi (src_reg, final_src));
3641 emit_jump_insn (gen_bne (label));
3643 /* Mop up any left-over bytes. */
3645 mips_block_move_straight (dest, src, leftover);
3648 /* Expand a movmemsi instruction. */
3651 mips_expand_block_move (rtx dest, rtx src, rtx length)
3653 if (GET_CODE (length) == CONST_INT)
3655 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3657 mips_block_move_straight (dest, src, INTVAL (length));
3662 mips_block_move_loop (dest, src, INTVAL (length));
3669 /* Argument support functions. */
3671 /* Initialize CUMULATIVE_ARGS for a function. */
3674 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3675 rtx libname ATTRIBUTE_UNUSED)
3677 static CUMULATIVE_ARGS zero_cum;
3678 tree param, next_param;
3681 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3683 /* Determine if this function has variable arguments. This is
3684 indicated by the last argument being 'void_type_mode' if there
3685 are no variable arguments. The standard MIPS calling sequence
3686 passes all arguments in the general purpose registers in this case. */
3688 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3689 param != 0; param = next_param)
3691 next_param = TREE_CHAIN (param);
3692 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3693 cum->gp_reg_found = 1;
3698 /* Fill INFO with information about a single argument. CUM is the
3699 cumulative state for earlier arguments. MODE is the mode of this
3700 argument and TYPE is its type (if known). NAMED is true if this
3701 is a named (fixed) argument rather than a variable one. */
3704 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3705 tree type, int named, struct mips_arg_info *info)
3707 bool doubleword_aligned_p;
3708 unsigned int num_bytes, num_words, max_regs;
3710 /* Work out the size of the argument. */
3711 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3712 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3714 /* Decide whether it should go in a floating-point register, assuming
3715 one is free. Later code checks for availability.
3717 The checks against UNITS_PER_FPVALUE handle the soft-float and
3718 single-float cases. */
3722 /* The EABI conventions have traditionally been defined in terms
3723 of TYPE_MODE, regardless of the actual type. */
3724 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3725 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3726 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3731 /* Only leading floating-point scalars are passed in
3732 floating-point registers. We also handle vector floats the same
3733 say, which is OK because they are not covered by the standard ABI. */
3734 info->fpr_p = (!cum->gp_reg_found
3735 && cum->arg_number < 2
3736 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3737 || VECTOR_FLOAT_TYPE_P (type))
3738 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3739 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3740 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3745 /* Scalar and complex floating-point types are passed in
3746 floating-point registers. */
3747 info->fpr_p = (named
3748 && (type == 0 || FLOAT_TYPE_P (type))
3749 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3750 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3751 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3752 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3754 /* ??? According to the ABI documentation, the real and imaginary
3755 parts of complex floats should be passed in individual registers.
3756 The real and imaginary parts of stack arguments are supposed
3757 to be contiguous and there should be an extra word of padding
3760 This has two problems. First, it makes it impossible to use a
3761 single "void *" va_list type, since register and stack arguments
3762 are passed differently. (At the time of writing, MIPSpro cannot
3763 handle complex float varargs correctly.) Second, it's unclear
3764 what should happen when there is only one register free.
3766 For now, we assume that named complex floats should go into FPRs
3767 if there are two FPRs free, otherwise they should be passed in the
3768 same way as a struct containing two floats. */
3770 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3771 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3773 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3774 info->fpr_p = false;
3784 /* See whether the argument has doubleword alignment. */
3785 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3787 /* Set REG_OFFSET to the register count we're interested in.
3788 The EABI allocates the floating-point registers separately,
3789 but the other ABIs allocate them like integer registers. */
3790 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3794 /* Advance to an even register if the argument is doubleword-aligned. */
3795 if (doubleword_aligned_p)
3796 info->reg_offset += info->reg_offset & 1;
3798 /* Work out the offset of a stack argument. */
3799 info->stack_offset = cum->stack_words;
3800 if (doubleword_aligned_p)
3801 info->stack_offset += info->stack_offset & 1;
3803 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3805 /* Partition the argument between registers and stack. */
3806 info->reg_words = MIN (num_words, max_regs);
3807 info->stack_words = num_words - info->reg_words;
3811 /* Implement FUNCTION_ARG_ADVANCE. */
3814 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3815 tree type, int named)
3817 struct mips_arg_info info;
3819 mips_arg_info (cum, mode, type, named, &info);
3822 cum->gp_reg_found = true;
3824 /* See the comment above the cumulative args structure in mips.h
3825 for an explanation of what this code does. It assumes the O32
3826 ABI, which passes at most 2 arguments in float registers. */
3827 if (cum->arg_number < 2 && info.fpr_p)
3828 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3830 if (mips_abi != ABI_EABI || !info.fpr_p)
3831 cum->num_gprs = info.reg_offset + info.reg_words;
3832 else if (info.reg_words > 0)
3833 cum->num_fprs += FP_INC;
3835 if (info.stack_words > 0)
3836 cum->stack_words = info.stack_offset + info.stack_words;
3841 /* Implement FUNCTION_ARG. */
3844 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3845 tree type, int named)
3847 struct mips_arg_info info;
3849 /* We will be called with a mode of VOIDmode after the last argument
3850 has been seen. Whatever we return will be passed to the call
3851 insn. If we need a mips16 fp_code, return a REG with the code
3852 stored as the mode. */
3853 if (mode == VOIDmode)
3855 if (TARGET_MIPS16 && cum->fp_code != 0)
3856 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3862 mips_arg_info (cum, mode, type, named, &info);
3864 /* Return straight away if the whole argument is passed on the stack. */
3865 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3869 && TREE_CODE (type) == RECORD_TYPE
3871 && TYPE_SIZE_UNIT (type)
3872 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3875 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3876 structure contains a double in its entirety, then that 64 bit
3877 chunk is passed in a floating point register. */
3880 /* First check to see if there is any such field. */
3881 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3882 if (TREE_CODE (field) == FIELD_DECL
3883 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3884 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3885 && host_integerp (bit_position (field), 0)
3886 && int_bit_position (field) % BITS_PER_WORD == 0)
3891 /* Now handle the special case by returning a PARALLEL
3892 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3893 chunks are passed in registers. */
3895 HOST_WIDE_INT bitpos;
3898 /* assign_parms checks the mode of ENTRY_PARM, so we must
3899 use the actual mode here. */
3900 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3903 field = TYPE_FIELDS (type);
3904 for (i = 0; i < info.reg_words; i++)
3908 for (; field; field = TREE_CHAIN (field))
3909 if (TREE_CODE (field) == FIELD_DECL
3910 && int_bit_position (field) >= bitpos)
3914 && int_bit_position (field) == bitpos
3915 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3916 && !TARGET_SOFT_FLOAT
3917 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3918 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3920 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3923 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3924 GEN_INT (bitpos / BITS_PER_UNIT));
3926 bitpos += BITS_PER_WORD;
3932 /* Handle the n32/n64 conventions for passing complex floating-point
3933 arguments in FPR pairs. The real part goes in the lower register
3934 and the imaginary part goes in the upper register. */
3937 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3940 enum machine_mode inner;
3943 inner = GET_MODE_INNER (mode);
3944 reg = FP_ARG_FIRST + info.reg_offset;
3945 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
3947 /* Real part in registers, imaginary part on stack. */
3948 gcc_assert (info.stack_words == info.reg_words);
3949 return gen_rtx_REG (inner, reg);
3953 gcc_assert (info.stack_words == 0);
3954 real = gen_rtx_EXPR_LIST (VOIDmode,
3955 gen_rtx_REG (inner, reg),
3957 imag = gen_rtx_EXPR_LIST (VOIDmode,
3959 reg + info.reg_words / 2),
3960 GEN_INT (GET_MODE_SIZE (inner)));
3961 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3966 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3967 else if (info.reg_offset == 1)
3968 /* This code handles the special o32 case in which the second word
3969 of the argument structure is passed in floating-point registers. */
3970 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3972 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3976 /* Implement TARGET_ARG_PARTIAL_BYTES. */
3979 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
3980 enum machine_mode mode, tree type, bool named)
3982 struct mips_arg_info info;
3984 mips_arg_info (cum, mode, type, named, &info);
3985 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
3989 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3990 PARM_BOUNDARY bits of alignment, but will be given anything up
3991 to STACK_BOUNDARY bits if the type requires it. */
3994 function_arg_boundary (enum machine_mode mode, tree type)
3996 unsigned int alignment;
3998 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3999 if (alignment < PARM_BOUNDARY)
4000 alignment = PARM_BOUNDARY;
4001 if (alignment > STACK_BOUNDARY)
4002 alignment = STACK_BOUNDARY;
4006 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
4007 upward rather than downward. In other words, return true if the
4008 first byte of the stack slot has useful data, false if the last
4012 mips_pad_arg_upward (enum machine_mode mode, tree type)
4014 /* On little-endian targets, the first byte of every stack argument
4015 is passed in the first byte of the stack slot. */
4016 if (!BYTES_BIG_ENDIAN)
4019 /* Otherwise, integral types are padded downward: the last byte of a
4020 stack argument is passed in the last byte of the stack slot. */
4022 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
4023 : GET_MODE_CLASS (mode) == MODE_INT)
4026 /* Big-endian o64 pads floating-point arguments downward. */
4027 if (mips_abi == ABI_O64)
4028 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4031 /* Other types are padded upward for o32, o64, n32 and n64. */
4032 if (mips_abi != ABI_EABI)
4035 /* Arguments smaller than a stack slot are padded downward. */
4036 if (mode != BLKmode)
4037 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
4039 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
4043 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
4044 if the least significant byte of the register has useful data. Return
4045 the opposite if the most significant byte does. */
4048 mips_pad_reg_upward (enum machine_mode mode, tree type)
4050 /* No shifting is required for floating-point arguments. */
4051 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
4052 return !BYTES_BIG_ENDIAN;
4054 /* Otherwise, apply the same padding to register arguments as we do
4055 to stack arguments. */
4056 return mips_pad_arg_upward (mode, type);
4060 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4061 tree type, int *pretend_size ATTRIBUTE_UNUSED,
4064 CUMULATIVE_ARGS local_cum;
4065 int gp_saved, fp_saved;
4067 /* The caller has advanced CUM up to, but not beyond, the last named
4068 argument. Advance a local copy of CUM past the last "real" named
4069 argument, to find out how many registers are left over. */
4072 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4074 /* Found out how many registers we need to save. */
4075 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4076 fp_saved = (EABI_FLOAT_VARARGS_P
4077 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4086 ptr = plus_constant (virtual_incoming_args_rtx,
4087 REG_PARM_STACK_SPACE (cfun->decl)
4088 - gp_saved * UNITS_PER_WORD);
4089 mem = gen_rtx_MEM (BLKmode, ptr);
4090 set_mem_alias_set (mem, get_varargs_alias_set ());
4092 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
4097 /* We can't use move_block_from_reg, because it will use
4099 enum machine_mode mode;
4102 /* Set OFF to the offset from virtual_incoming_args_rtx of
4103 the first float register. The FP save area lies below
4104 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4105 off = -gp_saved * UNITS_PER_WORD;
4106 off &= ~(UNITS_PER_FPVALUE - 1);
4107 off -= fp_saved * UNITS_PER_FPREG;
4109 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4111 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4115 ptr = plus_constant (virtual_incoming_args_rtx, off);
4116 mem = gen_rtx_MEM (mode, ptr);
4117 set_mem_alias_set (mem, get_varargs_alias_set ());
4118 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
4119 off += UNITS_PER_HWFPVALUE;
4123 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
4124 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
4125 + fp_saved * UNITS_PER_FPREG);
4128 /* Create the va_list data type.
4129 We keep 3 pointers, and two offsets.
4130 Two pointers are to the overflow area, which starts at the CFA.
4131 One of these is constant, for addressing into the GPR save area below it.
4132 The other is advanced up the stack through the overflow region.
4133 The third pointer is to the GPR save area. Since the FPR save area
4134 is just below it, we can address FPR slots off this pointer.
4135 We also keep two one-byte offsets, which are to be subtracted from the
4136 constant pointers to yield addresses in the GPR and FPR save areas.
4137 These are downcounted as float or non-float arguments are used,
4138 and when they get to zero, the argument must be obtained from the
4140 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4141 pointer is enough. It's started at the GPR save area, and is
4143 Note that the GPR save area is not constant size, due to optimization
4144 in the prologue. Hence, we can't use a design with two pointers
4145 and two offsets, although we could have designed this with two pointers
4146 and three offsets. */
4149 mips_build_builtin_va_list (void)
4151 if (EABI_FLOAT_VARARGS_P)
4153 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
4156 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4158 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4160 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4162 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4164 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4165 unsigned_char_type_node);
4166 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4167 unsigned_char_type_node);
4168 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4169 warn on every user file. */
4170 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
4171 array = build_array_type (unsigned_char_type_node,
4172 build_index_type (index));
4173 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4175 DECL_FIELD_CONTEXT (f_ovfl) = record;
4176 DECL_FIELD_CONTEXT (f_gtop) = record;
4177 DECL_FIELD_CONTEXT (f_ftop) = record;
4178 DECL_FIELD_CONTEXT (f_goff) = record;
4179 DECL_FIELD_CONTEXT (f_foff) = record;
4180 DECL_FIELD_CONTEXT (f_res) = record;
4182 TYPE_FIELDS (record) = f_ovfl;
4183 TREE_CHAIN (f_ovfl) = f_gtop;
4184 TREE_CHAIN (f_gtop) = f_ftop;
4185 TREE_CHAIN (f_ftop) = f_goff;
4186 TREE_CHAIN (f_goff) = f_foff;
4187 TREE_CHAIN (f_foff) = f_res;
4189 layout_type (record);
4192 else if (TARGET_IRIX && TARGET_IRIX6)
4193 /* On IRIX 6, this type is 'char *'. */
4194 return build_pointer_type (char_type_node);
4196 /* Otherwise, we use 'void *'. */
4197 return ptr_type_node;
4200 /* Implement va_start. */
4203 mips_va_start (tree valist, rtx nextarg)
4205 if (EABI_FLOAT_VARARGS_P)
4207 const CUMULATIVE_ARGS *cum;
4208 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4209 tree ovfl, gtop, ftop, goff, foff;
4211 int gpr_save_area_size;
4212 int fpr_save_area_size;
4215 cum = ¤t_function_args_info;
4217 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4219 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4221 f_ovfl = TYPE_FIELDS (va_list_type_node);
4222 f_gtop = TREE_CHAIN (f_ovfl);
4223 f_ftop = TREE_CHAIN (f_gtop);
4224 f_goff = TREE_CHAIN (f_ftop);
4225 f_foff = TREE_CHAIN (f_goff);
4227 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4229 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4231 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4233 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4235 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4238 /* Emit code to initialize OVFL, which points to the next varargs
4239 stack argument. CUM->STACK_WORDS gives the number of stack
4240 words used by named arguments. */
4241 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4242 if (cum->stack_words > 0)
4243 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), t,
4244 build_int_cst (NULL_TREE,
4245 cum->stack_words * UNITS_PER_WORD));
4246 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4247 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4249 /* Emit code to initialize GTOP, the top of the GPR save area. */
4250 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4251 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4252 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4254 /* Emit code to initialize FTOP, the top of the FPR save area.
4255 This address is gpr_save_area_bytes below GTOP, rounded
4256 down to the next fp-aligned boundary. */
4257 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4258 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4259 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4261 t = build2 (PLUS_EXPR, TREE_TYPE (ftop), t,
4262 build_int_cst (NULL_TREE, -fpr_offset));
4263 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4264 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4266 /* Emit code to initialize GOFF, the offset from GTOP of the
4267 next GPR argument. */
4268 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
4269 build_int_cst (NULL_TREE, gpr_save_area_size));
4270 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4272 /* Likewise emit code to initialize FOFF, the offset from FTOP
4273 of the next FPR argument. */
4274 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
4275 build_int_cst (NULL_TREE, fpr_save_area_size));
4276 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4280 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
4281 std_expand_builtin_va_start (valist, nextarg);
4285 /* Implement va_arg. */
4288 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4290 HOST_WIDE_INT size, rsize;
4294 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4297 type = build_pointer_type (type);
4299 size = int_size_in_bytes (type);
4300 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4302 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4303 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4306 /* Not a simple merged stack. */
4308 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4309 tree ovfl, top, off, align;
4310 HOST_WIDE_INT osize;
4313 f_ovfl = TYPE_FIELDS (va_list_type_node);
4314 f_gtop = TREE_CHAIN (f_ovfl);
4315 f_ftop = TREE_CHAIN (f_gtop);
4316 f_goff = TREE_CHAIN (f_ftop);
4317 f_foff = TREE_CHAIN (f_goff);
4319 /* We maintain separate pointers and offsets for floating-point
4320 and integer arguments, but we need similar code in both cases.
4323 TOP be the top of the register save area;
4324 OFF be the offset from TOP of the next register;
4325 ADDR_RTX be the address of the argument;
4326 RSIZE be the number of bytes used to store the argument
4327 when it's in the register save area;
4328 OSIZE be the number of bytes used to store it when it's
4329 in the stack overflow area; and
4330 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4332 The code we want is:
4334 1: off &= -rsize; // round down
4337 4: addr_rtx = top - off;
4342 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4343 10: addr_rtx = ovfl + PADDING;
4347 [1] and [9] can sometimes be optimized away. */
4349 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4352 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4353 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4355 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4357 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4360 /* When floating-point registers are saved to the stack,
4361 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4362 of the float's precision. */
4363 rsize = UNITS_PER_HWFPVALUE;
4365 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4366 (= PARM_BOUNDARY bits). This can be different from RSIZE
4369 (1) On 32-bit targets when TYPE is a structure such as:
4371 struct s { float f; };
4373 Such structures are passed in paired FPRs, so RSIZE
4374 will be 8 bytes. However, the structure only takes
4375 up 4 bytes of memory, so OSIZE will only be 4.
4377 (2) In combinations such as -mgp64 -msingle-float
4378 -fshort-double. Doubles passed in registers
4379 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4380 but those passed on the stack take up
4381 UNITS_PER_WORD bytes. */
4382 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4386 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4388 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4390 if (rsize > UNITS_PER_WORD)
4392 /* [1] Emit code for: off &= -rsize. */
4393 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), off,
4394 build_int_cst (NULL_TREE, -rsize));
4395 t = build2 (MODIFY_EXPR, TREE_TYPE (off), off, t);
4396 gimplify_and_add (t, pre_p);
4401 /* [2] Emit code to branch if off == 0. */
4402 t = build2 (NE_EXPR, boolean_type_node, off,
4403 build_int_cst (TREE_TYPE (off), 0));
4404 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
4406 /* [5] Emit code for: off -= rsize. We do this as a form of
4407 post-increment not available to C. Also widen for the
4408 coming pointer arithmetic. */
4409 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
4410 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4411 t = fold_convert (sizetype, t);
4412 t = fold_convert (TREE_TYPE (top), t);
4414 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4415 the argument has RSIZE - SIZE bytes of leading padding. */
4416 t = build2 (MINUS_EXPR, TREE_TYPE (top), top, t);
4417 if (BYTES_BIG_ENDIAN && rsize > size)
4419 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
4421 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4423 COND_EXPR_THEN (addr) = t;
4425 if (osize > UNITS_PER_WORD)
4427 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4428 u = fold_convert (TREE_TYPE (ovfl),
4429 build_int_cst (NULL_TREE, osize - 1));
4430 t = build2 (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4431 u = fold_convert (TREE_TYPE (ovfl),
4432 build_int_cst (NULL_TREE, -osize));
4433 t = build2 (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4434 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4439 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4440 post-increment ovfl by osize. On big-endian machines,
4441 the argument has OSIZE - SIZE bytes of leading padding. */
4442 u = fold_convert (TREE_TYPE (ovfl),
4443 build_int_cst (NULL_TREE, osize));
4444 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4445 if (BYTES_BIG_ENDIAN && osize > size)
4447 u = fold_convert (TREE_TYPE (t),
4448 build_int_cst (NULL_TREE, osize - size));
4449 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, u);
4452 /* String [9] and [10,11] together. */
4454 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4455 COND_EXPR_ELSE (addr) = t;
4457 addr = fold_convert (build_pointer_type (type), addr);
4458 addr = build_va_arg_indirect_ref (addr);
4462 addr = build_va_arg_indirect_ref (addr);
4467 /* Return true if it is possible to use left/right accesses for a
4468 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4469 returning true, update *OP, *LEFT and *RIGHT as follows:
4471 *OP is a BLKmode reference to the whole field.
4473 *LEFT is a QImode reference to the first byte if big endian or
4474 the last byte if little endian. This address can be used in the
4475 left-side instructions (lwl, swl, ldl, sdl).
4477 *RIGHT is a QImode reference to the opposite end of the field and
4478 can be used in the patterning right-side instruction. */
4481 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4482 rtx *left, rtx *right)
4486 /* Check that the operand really is a MEM. Not all the extv and
4487 extzv predicates are checked. */
4491 /* Check that the size is valid. */
4492 if (width != 32 && (!TARGET_64BIT || width != 64))
4495 /* We can only access byte-aligned values. Since we are always passed
4496 a reference to the first byte of the field, it is not necessary to
4497 do anything with BITPOS after this check. */
4498 if (bitpos % BITS_PER_UNIT != 0)
4501 /* Reject aligned bitfields: we want to use a normal load or store
4502 instead of a left/right pair. */
4503 if (MEM_ALIGN (*op) >= width)
4506 /* Adjust *OP to refer to the whole field. This also has the effect
4507 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4508 *op = adjust_address (*op, BLKmode, 0);
4509 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4511 /* Get references to both ends of the field. We deliberately don't
4512 use the original QImode *OP for FIRST since the new BLKmode one
4513 might have a simpler address. */
4514 first = adjust_address (*op, QImode, 0);
4515 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4517 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4518 be the upper word and RIGHT the lower word. */
4519 if (TARGET_BIG_ENDIAN)
4520 *left = first, *right = last;
4522 *left = last, *right = first;
4528 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4529 Return true on success. We only handle cases where zero_extract is
4530 equivalent to sign_extract. */
4533 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4535 rtx left, right, temp;
4537 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4538 paradoxical word_mode subreg. This is the only case in which
4539 we allow the destination to be larger than the source. */
4540 if (GET_CODE (dest) == SUBREG
4541 && GET_MODE (dest) == DImode
4542 && SUBREG_BYTE (dest) == 0
4543 && GET_MODE (SUBREG_REG (dest)) == SImode)
4544 dest = SUBREG_REG (dest);
4546 /* After the above adjustment, the destination must be the same
4547 width as the source. */
4548 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4551 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4554 temp = gen_reg_rtx (GET_MODE (dest));
4555 if (GET_MODE (dest) == DImode)
4557 emit_insn (gen_mov_ldl (temp, src, left));
4558 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4562 emit_insn (gen_mov_lwl (temp, src, left));
4563 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4569 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4573 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4576 enum machine_mode mode;
4578 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4581 mode = mode_for_size (width, MODE_INT, 0);
4582 src = gen_lowpart (mode, src);
4586 emit_insn (gen_mov_sdl (dest, src, left));
4587 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4591 emit_insn (gen_mov_swl (dest, src, left));
4592 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4597 /* Return true if X is a MEM with the same size as MODE. */
4600 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
4607 size = MEM_SIZE (x);
4608 return size && INTVAL (size) == GET_MODE_SIZE (mode);
4611 /* Return true if (zero_extract OP SIZE POSITION) can be used as the
4612 source of an "ext" instruction or the destination of an "ins"
4613 instruction. OP must be a register operand and the following
4614 conditions must hold:
4616 0 <= POSITION < GET_MODE_BITSIZE (GET_MODE (op))
4617 0 < SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4618 0 < POSITION + SIZE <= GET_MODE_BITSIZE (GET_MODE (op))
4620 Also reject lengths equal to a word as they are better handled
4621 by the move patterns. */
4624 mips_use_ins_ext_p (rtx op, rtx size, rtx position)
4626 HOST_WIDE_INT len, pos;
4628 if (!ISA_HAS_EXT_INS
4629 || !register_operand (op, VOIDmode)
4630 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
4633 len = INTVAL (size);
4634 pos = INTVAL (position);
4636 if (len <= 0 || len >= GET_MODE_BITSIZE (GET_MODE (op))
4637 || pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (op)))
4643 /* Set up globals to generate code for the ISA or processor
4644 described by INFO. */
4647 mips_set_architecture (const struct mips_cpu_info *info)
4651 mips_arch_info = info;
4652 mips_arch = info->cpu;
4653 mips_isa = info->isa;
4658 /* Likewise for tuning. */
4661 mips_set_tune (const struct mips_cpu_info *info)
4665 mips_tune_info = info;
4666 mips_tune = info->cpu;
4670 /* Implement TARGET_HANDLE_OPTION. */
4673 mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
4678 if (strcmp (arg, "32") == 0)
4680 else if (strcmp (arg, "o64") == 0)
4682 else if (strcmp (arg, "n32") == 0)
4684 else if (strcmp (arg, "64") == 0)
4686 else if (strcmp (arg, "eabi") == 0)
4687 mips_abi = ABI_EABI;
4694 return mips_parse_cpu (arg) != 0;
4697 mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
4698 return mips_isa_info != 0;
4700 case OPT_mno_flush_func:
4701 mips_cache_flush_func = NULL;
4709 /* Set up the threshold for data to go into the small data area, instead
4710 of the normal data area, and detect any conflicts in the switches. */
4713 override_options (void)
4715 int i, start, regno;
4716 enum machine_mode mode;
4718 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4720 /* The following code determines the architecture and register size.
4721 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4722 The GAS and GCC code should be kept in sync as much as possible. */
4724 if (mips_arch_string != 0)
4725 mips_set_architecture (mips_parse_cpu (mips_arch_string));
4727 if (mips_isa_info != 0)
4729 if (mips_arch_info == 0)
4730 mips_set_architecture (mips_isa_info);
4731 else if (mips_arch_info->isa != mips_isa_info->isa)
4732 error ("-%s conflicts with the other architecture options, "
4733 "which specify a %s processor",
4734 mips_isa_info->name,
4735 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
4738 if (mips_arch_info == 0)
4740 #ifdef MIPS_CPU_STRING_DEFAULT
4741 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
4743 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4747 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4748 error ("-march=%s is not compatible with the selected ABI",
4749 mips_arch_info->name);
4751 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4752 if (mips_tune_string != 0)
4753 mips_set_tune (mips_parse_cpu (mips_tune_string));
4755 if (mips_tune_info == 0)
4756 mips_set_tune (mips_arch_info);
4758 /* Set cost structure for the processor. */
4759 mips_cost = &mips_rtx_cost_data[mips_tune];
4761 if ((target_flags_explicit & MASK_64BIT) != 0)
4763 /* The user specified the size of the integer registers. Make sure
4764 it agrees with the ABI and ISA. */
4765 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4766 error ("-mgp64 used with a 32-bit processor");
4767 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4768 error ("-mgp32 used with a 64-bit ABI");
4769 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4770 error ("-mgp64 used with a 32-bit ABI");
4774 /* Infer the integer register size from the ABI and processor.
4775 Restrict ourselves to 32-bit registers if that's all the
4776 processor has, or if the ABI cannot handle 64-bit registers. */
4777 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4778 target_flags &= ~MASK_64BIT;
4780 target_flags |= MASK_64BIT;
4783 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4785 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4786 only one right answer here. */
4787 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4788 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4789 else if (!TARGET_64BIT && TARGET_FLOAT64)
4790 error ("unsupported combination: %s", "-mgp32 -mfp64");
4791 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4792 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4796 /* -msingle-float selects 32-bit float registers. Otherwise the
4797 float registers should be the same size as the integer ones. */
4798 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4799 target_flags |= MASK_FLOAT64;
4801 target_flags &= ~MASK_FLOAT64;
4804 /* End of code shared with GAS. */
4806 if ((target_flags_explicit & MASK_LONG64) == 0)
4808 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4809 target_flags |= MASK_LONG64;
4811 target_flags &= ~MASK_LONG64;
4814 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4815 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4817 /* For some configurations, it is useful to have -march control
4818 the default setting of MASK_SOFT_FLOAT. */
4819 switch ((int) mips_arch)
4821 case PROCESSOR_R4100:
4822 case PROCESSOR_R4111:
4823 case PROCESSOR_R4120:
4824 case PROCESSOR_R4130:
4825 target_flags |= MASK_SOFT_FLOAT;
4829 target_flags &= ~MASK_SOFT_FLOAT;
4835 flag_pcc_struct_return = 0;
4837 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4839 /* If neither -mbranch-likely nor -mno-branch-likely was given
4840 on the command line, set MASK_BRANCHLIKELY based on the target
4843 By default, we enable use of Branch Likely instructions on
4844 all architectures which support them with the following
4845 exceptions: when creating MIPS32 or MIPS64 code, and when
4846 tuning for architectures where their use tends to hurt
4849 The MIPS32 and MIPS64 architecture specifications say "Software
4850 is strongly encouraged to avoid use of Branch Likely
4851 instructions, as they will be removed from a future revision
4852 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4853 issue those instructions unless instructed to do so by
4855 if (ISA_HAS_BRANCHLIKELY
4856 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4857 && !(TUNE_MIPS5500 || TUNE_SB1))
4858 target_flags |= MASK_BRANCHLIKELY;
4860 target_flags &= ~MASK_BRANCHLIKELY;
4862 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4863 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture");
4865 /* The effect of -mabicalls isn't defined for the EABI. */
4866 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4868 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4869 target_flags &= ~MASK_ABICALLS;
4872 if (TARGET_ABICALLS)
4874 /* We need to set flag_pic for executables as well as DSOs
4875 because we may reference symbols that are not defined in
4876 the final executable. (MIPS does not use things like
4877 copy relocs, for example.)
4879 Also, there is a body of code that uses __PIC__ to distinguish
4880 between -mabicalls and -mno-abicalls code. */
4882 if (mips_section_threshold > 0)
4883 warning (0, "%<-G%> is incompatible with %<-mabicalls%>");
4886 /* mips_split_addresses is a half-way house between explicit
4887 relocations and the traditional assembler macros. It can
4888 split absolute 32-bit symbolic constants into a high/lo_sum
4889 pair but uses macros for other sorts of access.
4891 Like explicit relocation support for REL targets, it relies
4892 on GNU extensions in the assembler and the linker.
4894 Although this code should work for -O0, it has traditionally
4895 been treated as an optimization. */
4896 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4897 && optimize && !flag_pic
4898 && !ABI_HAS_64BIT_SYMBOLS)
4899 mips_split_addresses = 1;
4901 mips_split_addresses = 0;
4903 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4904 faster code, but at the expense of more nops. Enable it at -O3 and
4906 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4907 target_flags |= MASK_VR4130_ALIGN;
4909 /* When compiling for the mips16, we cannot use floating point. We
4910 record the original hard float value in mips16_hard_float. */
4913 if (TARGET_SOFT_FLOAT)
4914 mips16_hard_float = 0;
4916 mips16_hard_float = 1;
4917 target_flags |= MASK_SOFT_FLOAT;
4919 /* Don't run the scheduler before reload, since it tends to
4920 increase register pressure. */
4921 flag_schedule_insns = 0;
4923 /* Don't do hot/cold partitioning. The constant layout code expects
4924 the whole function to be in a single section. */
4925 flag_reorder_blocks_and_partition = 0;
4927 /* Silently disable -mexplicit-relocs since it doesn't apply
4928 to mips16 code. Even so, it would overly pedantic to warn
4929 about "-mips16 -mexplicit-relocs", especially given that
4930 we use a %gprel() operator. */
4931 target_flags &= ~MASK_EXPLICIT_RELOCS;
4934 /* When using explicit relocs, we call dbr_schedule from within
4936 if (TARGET_EXPLICIT_RELOCS)
4938 mips_flag_delayed_branch = flag_delayed_branch;
4939 flag_delayed_branch = 0;
4942 #ifdef MIPS_TFMODE_FORMAT
4943 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4946 /* Make sure that the user didn't turn off paired single support when
4947 MIPS-3D support is requested. */
4948 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
4949 && !TARGET_PAIRED_SINGLE_FLOAT)
4950 error ("-mips3d requires -mpaired-single");
4952 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
4954 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
4956 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4957 and TARGET_HARD_FLOAT are both true. */
4958 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4959 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4961 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4963 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4964 error ("-mips3d/-mpaired-single must be used with -mips64");
4966 if (TARGET_MIPS16 && TARGET_DSP)
4967 error ("-mips16 and -mdsp cannot be used together");
4969 mips_print_operand_punct['?'] = 1;
4970 mips_print_operand_punct['#'] = 1;
4971 mips_print_operand_punct['/'] = 1;
4972 mips_print_operand_punct['&'] = 1;
4973 mips_print_operand_punct['!'] = 1;
4974 mips_print_operand_punct['*'] = 1;
4975 mips_print_operand_punct['@'] = 1;
4976 mips_print_operand_punct['.'] = 1;
4977 mips_print_operand_punct['('] = 1;
4978 mips_print_operand_punct[')'] = 1;
4979 mips_print_operand_punct['['] = 1;
4980 mips_print_operand_punct[']'] = 1;
4981 mips_print_operand_punct['<'] = 1;
4982 mips_print_operand_punct['>'] = 1;
4983 mips_print_operand_punct['{'] = 1;
4984 mips_print_operand_punct['}'] = 1;
4985 mips_print_operand_punct['^'] = 1;
4986 mips_print_operand_punct['$'] = 1;
4987 mips_print_operand_punct['+'] = 1;
4988 mips_print_operand_punct['~'] = 1;
4990 /* Set up array to map GCC register number to debug register number.
4991 Ignore the special purpose register numbers. */
4993 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4994 mips_dbx_regno[i] = -1;
4996 start = GP_DBX_FIRST - GP_REG_FIRST;
4997 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4998 mips_dbx_regno[i] = i + start;
5000 start = FP_DBX_FIRST - FP_REG_FIRST;
5001 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5002 mips_dbx_regno[i] = i + start;
5004 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
5005 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
5007 /* Set up array giving whether a given register can hold a given mode. */
5009 for (mode = VOIDmode;
5010 mode != MAX_MACHINE_MODE;
5011 mode = (enum machine_mode) ((int)mode + 1))
5013 register int size = GET_MODE_SIZE (mode);
5014 register enum mode_class class = GET_MODE_CLASS (mode);
5016 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5020 if (mode == CCV2mode)
5023 && (regno - ST_REG_FIRST) % 2 == 0);
5025 else if (mode == CCV4mode)
5028 && (regno - ST_REG_FIRST) % 4 == 0);
5030 else if (mode == CCmode)
5033 temp = (regno == FPSW_REGNUM);
5035 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5036 || FP_REG_P (regno));
5039 else if (GP_REG_P (regno))
5040 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5042 else if (FP_REG_P (regno))
5043 temp = ((regno % FP_INC) == 0)
5044 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
5045 || class == MODE_VECTOR_FLOAT)
5046 && size <= UNITS_PER_FPVALUE)
5047 /* Allow integer modes that fit into a single
5048 register. We need to put integers into FPRs
5049 when using instructions like cvt and trunc.
5050 We can't allow sizes smaller than a word,
5051 the FPU has no appropriate load/store
5052 instructions for those. */
5053 || (class == MODE_INT
5054 && size >= MIN_UNITS_PER_WORD
5055 && size <= UNITS_PER_FPREG)
5056 /* Allow TFmode for CCmode reloads. */
5057 || (ISA_HAS_8CC && mode == TFmode));
5059 else if (ACC_REG_P (regno))
5060 temp = (INTEGRAL_MODE_P (mode)
5061 && (size <= UNITS_PER_WORD
5062 || (ACC_HI_REG_P (regno)
5063 && size == 2 * UNITS_PER_WORD)));
5065 else if (ALL_COP_REG_P (regno))
5066 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5070 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5074 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5075 initialized yet, so we can't use that here. */
5076 gpr_mode = TARGET_64BIT ? DImode : SImode;
5078 /* Provide default values for align_* for 64-bit targets. */
5079 if (TARGET_64BIT && !TARGET_MIPS16)
5081 if (align_loops == 0)
5083 if (align_jumps == 0)
5085 if (align_functions == 0)
5086 align_functions = 8;
5089 /* Function to allocate machine-dependent function status. */
5090 init_machine_status = &mips_init_machine_status;
5092 if (ABI_HAS_64BIT_SYMBOLS)
5094 if (TARGET_EXPLICIT_RELOCS)
5096 mips_split_p[SYMBOL_64_HIGH] = true;
5097 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
5098 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
5100 mips_split_p[SYMBOL_64_MID] = true;
5101 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
5102 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
5104 mips_split_p[SYMBOL_64_LOW] = true;
5105 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
5106 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
5108 mips_split_p[SYMBOL_GENERAL] = true;
5109 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5114 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
5116 mips_split_p[SYMBOL_GENERAL] = true;
5117 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
5118 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
5124 /* The high part is provided by a pseudo copy of $gp. */
5125 mips_split_p[SYMBOL_SMALL_DATA] = true;
5126 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
5129 if (TARGET_EXPLICIT_RELOCS)
5131 /* Small data constants are kept whole until after reload,
5132 then lowered by mips_rewrite_small_data. */
5133 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
5135 mips_split_p[SYMBOL_GOT_LOCAL] = true;
5138 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
5139 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
5143 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
5144 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
5149 /* The HIGH and LO_SUM are matched by special .md patterns. */
5150 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
5152 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
5153 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
5154 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
5156 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
5157 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
5158 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
5163 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
5165 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
5166 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
5172 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
5173 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
5174 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
5177 /* Thread-local relocation operators. */
5178 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
5179 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
5180 mips_split_p[SYMBOL_DTPREL] = 1;
5181 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
5182 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
5183 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
5184 mips_split_p[SYMBOL_TPREL] = 1;
5185 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
5186 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
5188 /* We don't have a thread pointer access instruction on MIPS16, or
5189 appropriate TLS relocations. */
5191 targetm.have_tls = false;
5193 /* Default to working around R4000 errata only if the processor
5194 was selected explicitly. */
5195 if ((target_flags_explicit & MASK_FIX_R4000) == 0
5196 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
5197 target_flags |= MASK_FIX_R4000;
5199 /* Default to working around R4400 errata only if the processor
5200 was selected explicitly. */
5201 if ((target_flags_explicit & MASK_FIX_R4400) == 0
5202 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
5203 target_flags |= MASK_FIX_R4400;
5206 /* Implement CONDITIONAL_REGISTER_USAGE. */
5209 mips_conditional_register_usage (void)
5215 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
5216 fixed_regs[regno] = call_used_regs[regno] = 1;
5218 if (!TARGET_HARD_FLOAT)
5222 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5223 fixed_regs[regno] = call_used_regs[regno] = 1;
5224 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5225 fixed_regs[regno] = call_used_regs[regno] = 1;
5227 else if (! ISA_HAS_8CC)
5231 /* We only have a single condition code register. We
5232 implement this by hiding all the condition code registers,
5233 and generating RTL that refers directly to ST_REG_FIRST. */
5234 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5235 fixed_regs[regno] = call_used_regs[regno] = 1;
5237 /* In mips16 mode, we permit the $t temporary registers to be used
5238 for reload. We prohibit the unused $s registers, since they
5239 are caller saved, and saving them via a mips16 register would
5240 probably waste more time than just reloading the value. */
5243 fixed_regs[18] = call_used_regs[18] = 1;
5244 fixed_regs[19] = call_used_regs[19] = 1;
5245 fixed_regs[20] = call_used_regs[20] = 1;
5246 fixed_regs[21] = call_used_regs[21] = 1;
5247 fixed_regs[22] = call_used_regs[22] = 1;
5248 fixed_regs[23] = call_used_regs[23] = 1;
5249 fixed_regs[26] = call_used_regs[26] = 1;
5250 fixed_regs[27] = call_used_regs[27] = 1;
5251 fixed_regs[30] = call_used_regs[30] = 1;
5253 /* fp20-23 are now caller saved. */
5254 if (mips_abi == ABI_64)
5257 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5258 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5260 /* Odd registers from fp21 to fp31 are now caller saved. */
5261 if (mips_abi == ABI_N32)
5264 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5265 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5269 /* Allocate a chunk of memory for per-function machine-dependent data. */
5270 static struct machine_function *
5271 mips_init_machine_status (void)
5273 return ((struct machine_function *)
5274 ggc_alloc_cleared (sizeof (struct machine_function)));
5277 /* On the mips16, we want to allocate $24 (T_REG) before other
5278 registers for instructions for which it is possible. This helps
5279 avoid shuffling registers around in order to set up for an xor,
5280 encouraging the compiler to use a cmp instead. */
5283 mips_order_regs_for_local_alloc (void)
5287 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5288 reg_alloc_order[i] = i;
5292 /* It really doesn't matter where we put register 0, since it is
5293 a fixed register anyhow. */
5294 reg_alloc_order[0] = 24;
5295 reg_alloc_order[24] = 0;
5300 /* The MIPS debug format wants all automatic variables and arguments
5301 to be in terms of the virtual frame pointer (stack pointer before
5302 any adjustment in the function), while the MIPS 3.0 linker wants
5303 the frame pointer to be the stack pointer after the initial
5304 adjustment. So, we do the adjustment here. The arg pointer (which
5305 is eliminated) points to the virtual frame pointer, while the frame
5306 pointer (which may be eliminated) points to the stack pointer after
5307 the initial adjustments. */
5310 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5312 rtx offset2 = const0_rtx;
5313 rtx reg = eliminate_constant_term (addr, &offset2);
5316 offset = INTVAL (offset2);
5318 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5319 || reg == hard_frame_pointer_rtx)
5321 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5322 ? compute_frame_size (get_frame_size ())
5323 : cfun->machine->frame.total_size;
5325 /* MIPS16 frame is smaller */
5326 if (frame_pointer_needed && TARGET_MIPS16)
5327 frame_size -= cfun->machine->frame.args_size;
5329 offset = offset - frame_size;
5332 /* sdbout_parms does not want this to crash for unrecognized cases. */
5334 else if (reg != arg_pointer_rtx)
5335 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5342 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5344 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5345 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5346 'h' OP is HIGH, prints %hi(X),
5347 'd' output integer constant in decimal,
5348 'z' if the operand is 0, use $0 instead of normal operand.
5349 'D' print second part of double-word register or memory operand.
5350 'L' print low-order register of double-word register operand.
5351 'M' print high-order register of double-word register operand.
5352 'C' print part of opcode for a branch condition.
5353 'F' print part of opcode for a floating-point branch condition.
5354 'N' print part of opcode for a branch condition, inverted.
5355 'W' print part of opcode for a floating-point branch condition, inverted.
5356 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
5357 'z' for (eq:?I ...), 'n' for (ne:?I ...).
5358 't' like 'T', but with the EQ/NE cases reversed
5359 'Y' for a CONST_INT X, print mips_fp_conditions[X]
5360 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
5361 'R' print the reloc associated with LO_SUM
5362 'q' print DSP accumulator registers
5364 The punctuation characters are:
5366 '(' Turn on .set noreorder
5367 ')' Turn on .set reorder
5368 '[' Turn on .set noat
5370 '<' Turn on .set nomacro
5371 '>' Turn on .set macro
5372 '{' Turn on .set volatile (not GAS)
5373 '}' Turn on .set novolatile (not GAS)
5374 '&' Turn on .set noreorder if filling delay slots
5375 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5376 '!' Turn on .set nomacro if filling delay slots
5377 '#' Print nop if in a .set noreorder section.
5378 '/' Like '#', but does nothing within a delayed branch sequence
5379 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5380 '@' Print the name of the assembler temporary register (at or $1).
5381 '.' Print the name of the register with a hard-wired zero (zero or $0).
5382 '^' Print the name of the pic call-through register (t9 or $25).
5383 '$' Print the name of the stack pointer register (sp or $29).
5384 '+' Print the name of the gp register (usually gp or $28).
5385 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5388 print_operand (FILE *file, rtx op, int letter)
5390 register enum rtx_code code;
5392 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5397 if (mips_branch_likely)
5402 fputs (reg_names [GP_REG_FIRST + 1], file);
5406 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5410 fputs (reg_names [GP_REG_FIRST + 0], file);
5414 fputs (reg_names[STACK_POINTER_REGNUM], file);
5418 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5422 if (final_sequence != 0 && set_noreorder++ == 0)
5423 fputs (".set\tnoreorder\n\t", file);
5427 if (final_sequence != 0)
5429 if (set_noreorder++ == 0)
5430 fputs (".set\tnoreorder\n\t", file);
5432 if (set_nomacro++ == 0)
5433 fputs (".set\tnomacro\n\t", file);
5438 if (final_sequence != 0 && set_nomacro++ == 0)
5439 fputs ("\n\t.set\tnomacro", file);
5443 if (set_noreorder != 0)
5444 fputs ("\n\tnop", file);
5448 /* Print an extra newline so that the delayed insn is separated
5449 from the following ones. This looks neater and is consistent
5450 with non-nop delayed sequences. */
5451 if (set_noreorder != 0 && final_sequence == 0)
5452 fputs ("\n\tnop\n", file);
5456 if (set_noreorder++ == 0)
5457 fputs (".set\tnoreorder\n\t", file);
5461 if (set_noreorder == 0)
5462 error ("internal error: %%) found without a %%( in assembler pattern");
5464 else if (--set_noreorder == 0)
5465 fputs ("\n\t.set\treorder", file);
5470 if (set_noat++ == 0)
5471 fputs (".set\tnoat\n\t", file);
5476 error ("internal error: %%] found without a %%[ in assembler pattern");
5477 else if (--set_noat == 0)
5478 fputs ("\n\t.set\tat", file);
5483 if (set_nomacro++ == 0)
5484 fputs (".set\tnomacro\n\t", file);
5488 if (set_nomacro == 0)
5489 error ("internal error: %%> found without a %%< in assembler pattern");
5490 else if (--set_nomacro == 0)
5491 fputs ("\n\t.set\tmacro", file);
5496 if (set_volatile++ == 0)
5497 fputs ("#.set\tvolatile\n\t", file);
5501 if (set_volatile == 0)
5502 error ("internal error: %%} found without a %%{ in assembler pattern");
5503 else if (--set_volatile == 0)
5504 fputs ("\n\t#.set\tnovolatile", file);
5510 if (align_labels_log > 0)
5511 ASM_OUTPUT_ALIGN (file, align_labels_log);
5516 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5525 error ("PRINT_OPERAND null pointer");
5529 code = GET_CODE (op);
5534 case EQ: fputs ("eq", file); break;
5535 case NE: fputs ("ne", file); break;
5536 case GT: fputs ("gt", file); break;
5537 case GE: fputs ("ge", file); break;
5538 case LT: fputs ("lt", file); break;
5539 case LE: fputs ("le", file); break;
5540 case GTU: fputs ("gtu", file); break;
5541 case GEU: fputs ("geu", file); break;
5542 case LTU: fputs ("ltu", file); break;
5543 case LEU: fputs ("leu", file); break;
5545 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5548 else if (letter == 'N')
5551 case EQ: fputs ("ne", file); break;
5552 case NE: fputs ("eq", file); break;
5553 case GT: fputs ("le", file); break;
5554 case GE: fputs ("lt", file); break;
5555 case LT: fputs ("ge", file); break;
5556 case LE: fputs ("gt", file); break;
5557 case GTU: fputs ("leu", file); break;
5558 case GEU: fputs ("ltu", file); break;
5559 case LTU: fputs ("geu", file); break;
5560 case LEU: fputs ("gtu", file); break;
5562 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5565 else if (letter == 'F')
5568 case EQ: fputs ("c1f", file); break;
5569 case NE: fputs ("c1t", file); break;
5571 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5574 else if (letter == 'W')
5577 case EQ: fputs ("c1t", file); break;
5578 case NE: fputs ("c1f", file); break;
5580 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5583 else if (letter == 'h')
5585 if (GET_CODE (op) == HIGH)
5588 print_operand_reloc (file, op, mips_hi_relocs);
5591 else if (letter == 'R')
5592 print_operand_reloc (file, op, mips_lo_relocs);
5594 else if (letter == 'Y')
5596 if (GET_CODE (op) == CONST_INT
5597 && ((unsigned HOST_WIDE_INT) INTVAL (op)
5598 < ARRAY_SIZE (mips_fp_conditions)))
5599 fputs (mips_fp_conditions[INTVAL (op)], file);
5601 output_operand_lossage ("invalid %%Y value");
5604 else if (letter == 'Z')
5608 print_operand (file, op, 0);
5613 else if (letter == 'q')
5618 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5620 regnum = REGNO (op);
5621 if (MD_REG_P (regnum))
5622 fprintf (file, "$ac0");
5623 else if (DSP_ACC_REG_P (regnum))
5624 fprintf (file, "$ac%c", reg_names[regnum][3]);
5626 fatal_insn ("PRINT_OPERAND, invalid insn for %%q", op);
5629 else if (code == REG || code == SUBREG)
5631 register int regnum;
5634 regnum = REGNO (op);
5636 regnum = true_regnum (op);
5638 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5639 || (letter == 'L' && WORDS_BIG_ENDIAN)
5643 fprintf (file, "%s", reg_names[regnum]);
5646 else if (code == MEM)
5649 output_address (plus_constant (XEXP (op, 0), 4));
5651 output_address (XEXP (op, 0));
5654 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5655 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5657 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5658 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5660 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5661 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5663 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5664 fputs (reg_names[GP_REG_FIRST], file);
5666 else if (letter == 'd' || letter == 'x' || letter == 'X')
5667 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5669 else if (letter == 'T' || letter == 't')
5671 int truth = (code == NE) == (letter == 'T');
5672 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
5675 else if (CONST_GP_P (op))
5676 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5679 output_addr_const (file, op);
5683 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5684 RELOCS is the array of relocations to use. */
5687 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5689 enum mips_symbol_type symbol_type;
5692 HOST_WIDE_INT offset;
5694 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5695 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5697 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5698 mips_split_const (op, &base, &offset);
5699 if (UNSPEC_ADDRESS_P (base))
5700 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5702 fputs (relocs[symbol_type], file);
5703 output_addr_const (file, op);
5704 for (p = relocs[symbol_type]; *p != 0; p++)
5709 /* Output address operand X to FILE. */
5712 print_operand_address (FILE *file, rtx x)
5714 struct mips_address_info addr;
5716 if (mips_classify_address (&addr, x, word_mode, true))
5720 print_operand (file, addr.offset, 0);
5721 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5724 case ADDRESS_LO_SUM:
5725 print_operand (file, addr.offset, 'R');
5726 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5729 case ADDRESS_CONST_INT:
5730 output_addr_const (file, x);
5731 fprintf (file, "(%s)", reg_names[0]);
5734 case ADDRESS_SYMBOLIC:
5735 output_addr_const (file, x);
5741 /* When using assembler macros, keep track of all of small-data externs
5742 so that mips_file_end can emit the appropriate declarations for them.
5744 In most cases it would be safe (though pointless) to emit .externs
5745 for other symbols too. One exception is when an object is within
5746 the -G limit but declared by the user to be in a section other
5747 than .sbss or .sdata. */
5750 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5752 register struct extern_list *p;
5754 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5756 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5757 p->next = extern_head;
5759 p->size = int_size_in_bytes (TREE_TYPE (decl));
5763 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5765 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5766 p->next = extern_head;
5777 irix_output_external_libcall (rtx fun)
5779 register struct extern_list *p;
5781 if (mips_abi == ABI_32)
5783 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5784 p->next = extern_head;
5785 p->name = XSTR (fun, 0);
5792 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5793 put out a MIPS ECOFF file and a stab. */
5796 mips_output_filename (FILE *stream, const char *name)
5799 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5801 if (write_symbols == DWARF2_DEBUG)
5803 else if (mips_output_filename_first_time)
5805 mips_output_filename_first_time = 0;
5806 num_source_filenames += 1;
5807 current_function_file = name;
5808 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5809 output_quoted_string (stream, name);
5810 putc ('\n', stream);
5813 /* If we are emitting stabs, let dbxout.c handle this (except for
5814 the mips_output_filename_first_time case). */
5815 else if (write_symbols == DBX_DEBUG)
5818 else if (name != current_function_file
5819 && strcmp (name, current_function_file) != 0)
5821 num_source_filenames += 1;
5822 current_function_file = name;
5823 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5824 output_quoted_string (stream, name);
5825 putc ('\n', stream);
5829 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5830 that should be written before the opening quote, such as "\t.ascii\t"
5831 for real string data or "\t# " for a comment. */
5834 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5839 register const unsigned char *string =
5840 (const unsigned char *)string_param;
5842 fprintf (stream, "%s\"", prefix);
5843 for (i = 0; i < len; i++)
5845 register int c = string[i];
5849 if (c == '\\' || c == '\"')
5851 putc ('\\', stream);
5859 fprintf (stream, "\\%03o", c);
5863 if (cur_pos > 72 && i+1 < len)
5866 fprintf (stream, "\"\n%s\"", prefix);
5869 fprintf (stream, "\"\n");
5872 /* Implement TARGET_ASM_FILE_START. */
5875 mips_file_start (void)
5877 default_file_start ();
5881 /* Generate a special section to describe the ABI switches used to
5882 produce the resultant binary. This used to be done by the assembler
5883 setting bits in the ELF header's flags field, but we have run out of
5884 bits. GDB needs this information in order to be able to correctly
5885 debug these binaries. See the function mips_gdbarch_init() in
5886 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5887 causes unnecessary IRIX 6 ld warnings. */
5888 const char * abi_string = NULL;
5892 case ABI_32: abi_string = "abi32"; break;
5893 case ABI_N32: abi_string = "abiN32"; break;
5894 case ABI_64: abi_string = "abi64"; break;
5895 case ABI_O64: abi_string = "abiO64"; break;
5896 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5900 /* Note - we use fprintf directly rather than calling switch_to_section
5901 because in this way we can avoid creating an allocated section. We
5902 do not want this section to take up any space in the running
5904 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5906 /* There is no ELF header flag to distinguish long32 forms of the
5907 EABI from long64 forms. Emit a special section to help tools
5908 such as GDB. Do the same for o64, which is sometimes used with
5910 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
5911 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5912 TARGET_LONG64 ? 64 : 32);
5914 /* Restore the default section. */
5915 fprintf (asm_out_file, "\t.previous\n");
5918 /* Generate the pseudo ops that System V.4 wants. */
5919 if (TARGET_ABICALLS)
5920 fprintf (asm_out_file, "\t.abicalls\n");
5923 fprintf (asm_out_file, "\t.set\tmips16\n");
5925 if (flag_verbose_asm)
5926 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5928 mips_section_threshold, mips_arch_info->name, mips_isa);
5931 #ifdef BSS_SECTION_ASM_OP
5932 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5933 in the use of sbss. */
5936 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5937 unsigned HOST_WIDE_INT size, int align)
5939 extern tree last_assemble_variable_decl;
5941 if (mips_in_small_data_p (decl))
5942 switch_to_section (get_named_section (NULL, ".sbss", 0));
5944 switch_to_section (bss_section);
5945 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5946 last_assemble_variable_decl = decl;
5947 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5948 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5952 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5953 .externs for any small-data variables that turned out to be external. */
5956 mips_file_end (void)
5959 struct extern_list *p;
5963 fputs ("\n", asm_out_file);
5965 for (p = extern_head; p != 0; p = p->next)
5967 name_tree = get_identifier (p->name);
5969 /* Positively ensure only one .extern for any given symbol. */
5970 if (!TREE_ASM_WRITTEN (name_tree)
5971 && TREE_SYMBOL_REFERENCED (name_tree))
5973 TREE_ASM_WRITTEN (name_tree) = 1;
5974 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5975 `.global name .text' directive for every used but
5976 undefined function. If we don't, the linker may perform
5977 an optimization (skipping over the insns that set $gp)
5978 when it is unsafe. */
5979 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5981 fputs ("\t.globl ", asm_out_file);
5982 assemble_name (asm_out_file, p->name);
5983 fputs (" .text\n", asm_out_file);
5987 fputs ("\t.extern\t", asm_out_file);
5988 assemble_name (asm_out_file, p->name);
5989 fprintf (asm_out_file, ", %d\n", p->size);
5996 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5997 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
6000 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
6001 unsigned HOST_WIDE_INT size,
6004 /* If the target wants uninitialized const declarations in
6005 .rdata then don't put them in .comm. */
6006 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
6007 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
6008 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
6010 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
6011 targetm.asm_out.globalize_label (stream, name);
6013 switch_to_section (readonly_data_section);
6014 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
6015 mips_declare_object (stream, name, "",
6016 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
6020 mips_declare_common_object (stream, name, "\n\t.comm\t",
6024 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
6025 NAME is the name of the object and ALIGN is the required alignment
6026 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
6027 alignment argument. */
6030 mips_declare_common_object (FILE *stream, const char *name,
6031 const char *init_string,
6032 unsigned HOST_WIDE_INT size,
6033 unsigned int align, bool takes_alignment_p)
6035 if (!takes_alignment_p)
6037 size += (align / BITS_PER_UNIT) - 1;
6038 size -= size % (align / BITS_PER_UNIT);
6039 mips_declare_object (stream, name, init_string,
6040 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
6043 mips_declare_object (stream, name, init_string,
6044 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
6045 size, align / BITS_PER_UNIT);
6048 /* Emit either a label, .comm, or .lcomm directive. When using assembler
6049 macros, mark the symbol as written so that mips_file_end won't emit an
6050 .extern for it. STREAM is the output file, NAME is the name of the
6051 symbol, INIT_STRING is the string that should be written before the
6052 symbol and FINAL_STRING is the string that should be written after it.
6053 FINAL_STRING is a printf() format that consumes the remaining arguments. */
6056 mips_declare_object (FILE *stream, const char *name, const char *init_string,
6057 const char *final_string, ...)
6061 fputs (init_string, stream);
6062 assemble_name (stream, name);
6063 va_start (ap, final_string);
6064 vfprintf (stream, final_string, ap);
6067 if (!TARGET_EXPLICIT_RELOCS)
6069 tree name_tree = get_identifier (name);
6070 TREE_ASM_WRITTEN (name_tree) = 1;
6074 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
6075 extern int size_directive_output;
6077 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
6078 definitions except that it uses mips_declare_object() to emit the label. */
6081 mips_declare_object_name (FILE *stream, const char *name,
6082 tree decl ATTRIBUTE_UNUSED)
6084 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
6085 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
6088 size_directive_output = 0;
6089 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
6093 size_directive_output = 1;
6094 size = int_size_in_bytes (TREE_TYPE (decl));
6095 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6098 mips_declare_object (stream, name, "", ":\n");
6101 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
6104 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
6108 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
6109 if (!flag_inhibit_size_directive
6110 && DECL_SIZE (decl) != 0
6111 && !at_end && top_level
6112 && DECL_INITIAL (decl) == error_mark_node
6113 && !size_directive_output)
6117 size_directive_output = 1;
6118 size = int_size_in_bytes (TREE_TYPE (decl));
6119 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
6124 /* Return true if X is a small data address that can be rewritten
6128 mips_rewrite_small_data_p (rtx x)
6130 enum mips_symbol_type symbol_type;
6132 return (TARGET_EXPLICIT_RELOCS
6133 && mips_symbolic_constant_p (x, &symbol_type)
6134 && symbol_type == SYMBOL_SMALL_DATA);
6138 /* A for_each_rtx callback for mips_small_data_pattern_p. */
6141 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6143 if (GET_CODE (*loc) == LO_SUM)
6146 return mips_rewrite_small_data_p (*loc);
6149 /* Return true if OP refers to small data symbols directly, not through
6153 mips_small_data_pattern_p (rtx op)
6155 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
6158 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
6161 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
6163 if (mips_rewrite_small_data_p (*loc))
6164 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
6166 if (GET_CODE (*loc) == LO_SUM)
6172 /* If possible, rewrite OP so that it refers to small data using
6173 explicit relocations. */
6176 mips_rewrite_small_data (rtx op)
6178 op = copy_insn (op);
6179 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
6183 /* Return true if the current function has an insn that implicitly
6187 mips_function_has_gp_insn (void)
6189 /* Don't bother rechecking if we found one last time. */
6190 if (!cfun->machine->has_gp_insn_p)
6194 push_topmost_sequence ();
6195 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6197 && GET_CODE (PATTERN (insn)) != USE
6198 && GET_CODE (PATTERN (insn)) != CLOBBER
6199 && (get_attr_got (insn) != GOT_UNSET
6200 || small_data_pattern (PATTERN (insn), VOIDmode)))
6202 pop_topmost_sequence ();
6204 cfun->machine->has_gp_insn_p = (insn != 0);
6206 return cfun->machine->has_gp_insn_p;
6210 /* Return the register that should be used as the global pointer
6211 within this function. Return 0 if the function doesn't need
6212 a global pointer. */
6215 mips_global_pointer (void)
6219 /* $gp is always available in non-abicalls code. */
6220 if (!TARGET_ABICALLS)
6221 return GLOBAL_POINTER_REGNUM;
6223 /* We must always provide $gp when it is used implicitly. */
6224 if (!TARGET_EXPLICIT_RELOCS)
6225 return GLOBAL_POINTER_REGNUM;
6227 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6229 if (current_function_profile)
6230 return GLOBAL_POINTER_REGNUM;
6232 /* If the function has a nonlocal goto, $gp must hold the correct
6233 global pointer for the target function. */
6234 if (current_function_has_nonlocal_goto)
6235 return GLOBAL_POINTER_REGNUM;
6237 /* If the gp is never referenced, there's no need to initialize it.
6238 Note that reload can sometimes introduce constant pool references
6239 into a function that otherwise didn't need them. For example,
6240 suppose we have an instruction like:
6242 (set (reg:DF R1) (float:DF (reg:SI R2)))
6244 If R2 turns out to be constant such as 1, the instruction may have a
6245 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6246 using this constant if R2 doesn't get allocated to a register.
6248 In cases like these, reload will have added the constant to the pool
6249 but no instruction will yet refer to it. */
6250 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6251 && !current_function_uses_const_pool
6252 && !mips_function_has_gp_insn ())
6255 /* We need a global pointer, but perhaps we can use a call-clobbered
6256 register instead of $gp. */
6257 if (TARGET_NEWABI && current_function_is_leaf)
6258 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6259 if (!regs_ever_live[regno]
6260 && call_used_regs[regno]
6261 && !fixed_regs[regno]
6262 && regno != PIC_FUNCTION_ADDR_REGNUM)
6265 return GLOBAL_POINTER_REGNUM;
6269 /* Return true if the current function must save REGNO. */
6272 mips_save_reg_p (unsigned int regno)
6274 /* We only need to save $gp for NewABI PIC. */
6275 if (regno == GLOBAL_POINTER_REGNUM)
6276 return (TARGET_ABICALLS && TARGET_NEWABI
6277 && cfun->machine->global_pointer == regno);
6279 /* Check call-saved registers. */
6280 if (regs_ever_live[regno] && !call_used_regs[regno])
6283 /* We need to save the old frame pointer before setting up a new one. */
6284 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6287 /* We need to save the incoming return address if it is ever clobbered
6288 within the function. */
6289 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6296 return_type = DECL_RESULT (current_function_decl);
6298 /* $18 is a special case in mips16 code. It may be used to call
6299 a function which returns a floating point value, but it is
6300 marked in call_used_regs. */
6301 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6304 /* $31 is also a special case. It will be used to copy a return
6305 value into the floating point registers if the return value is
6307 if (regno == GP_REG_FIRST + 31
6308 && mips16_hard_float
6309 && !aggregate_value_p (return_type, current_function_decl)
6310 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6311 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6319 /* Return the bytes needed to compute the frame pointer from the current
6320 stack pointer. SIZE is the size (in bytes) of the local variables.
6322 MIPS stack frames look like:
6324 Before call After call
6325 +-----------------------+ +-----------------------+
6328 | caller's temps. | | caller's temps. |
6330 +-----------------------+ +-----------------------+
6332 | arguments on stack. | | arguments on stack. |
6334 +-----------------------+ +-----------------------+
6335 | 4 words to save | | 4 words to save |
6336 | arguments passed | | arguments passed |
6337 | in registers, even | | in registers, even |
6338 SP->| if not passed. | VFP->| if not passed. |
6339 +-----------------------+ +-----------------------+
6341 | fp register save |
6343 +-----------------------+
6345 | gp register save |
6347 +-----------------------+
6351 +-----------------------+
6353 | alloca allocations |
6355 +-----------------------+
6357 | GP save for V.4 abi |
6359 +-----------------------+
6361 | arguments on stack |
6363 +-----------------------+
6365 | arguments passed |
6366 | in registers, even |
6367 low SP->| if not passed. |
6368 memory +-----------------------+
6373 compute_frame_size (HOST_WIDE_INT size)
6376 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6377 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6378 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6379 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6380 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6381 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6382 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6383 unsigned int mask; /* mask of saved gp registers */
6384 unsigned int fmask; /* mask of saved fp registers */
6386 cfun->machine->global_pointer = mips_global_pointer ();
6392 var_size = MIPS_STACK_ALIGN (size);
6393 args_size = current_function_outgoing_args_size;
6394 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6396 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6397 functions. If the function has local variables, we're committed
6398 to allocating it anyway. Otherwise reclaim it here. */
6399 if (var_size == 0 && current_function_is_leaf)
6400 cprestore_size = args_size = 0;
6402 /* The MIPS 3.0 linker does not like functions that dynamically
6403 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6404 looks like we are trying to create a second frame pointer to the
6405 function, so allocate some stack space to make it happy. */
6407 if (args_size == 0 && current_function_calls_alloca)
6408 args_size = 4 * UNITS_PER_WORD;
6410 total_size = var_size + args_size + cprestore_size;
6412 /* Calculate space needed for gp registers. */
6413 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6414 if (mips_save_reg_p (regno))
6416 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6417 mask |= 1 << (regno - GP_REG_FIRST);
6420 /* We need to restore these for the handler. */
6421 if (current_function_calls_eh_return)
6426 regno = EH_RETURN_DATA_REGNO (i);
6427 if (regno == INVALID_REGNUM)
6429 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6430 mask |= 1 << (regno - GP_REG_FIRST);
6434 /* This loop must iterate over the same space as its companion in
6435 save_restore_insns. */
6436 for (regno = (FP_REG_LAST - FP_INC + 1);
6437 regno >= FP_REG_FIRST;
6440 if (mips_save_reg_p (regno))
6442 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6443 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6447 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6448 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6450 /* Add in the space required for saving incoming register arguments. */
6451 total_size += current_function_pretend_args_size;
6452 total_size += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
6454 /* Save other computed information. */
6455 cfun->machine->frame.total_size = total_size;
6456 cfun->machine->frame.var_size = var_size;
6457 cfun->machine->frame.args_size = args_size;
6458 cfun->machine->frame.cprestore_size = cprestore_size;
6459 cfun->machine->frame.gp_reg_size = gp_reg_size;
6460 cfun->machine->frame.fp_reg_size = fp_reg_size;
6461 cfun->machine->frame.mask = mask;
6462 cfun->machine->frame.fmask = fmask;
6463 cfun->machine->frame.initialized = reload_completed;
6464 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6465 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6469 HOST_WIDE_INT offset;
6471 offset = (args_size + cprestore_size + var_size
6472 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6473 cfun->machine->frame.gp_sp_offset = offset;
6474 cfun->machine->frame.gp_save_offset = offset - total_size;
6478 cfun->machine->frame.gp_sp_offset = 0;
6479 cfun->machine->frame.gp_save_offset = 0;
6484 HOST_WIDE_INT offset;
6486 offset = (args_size + cprestore_size + var_size
6487 + gp_reg_rounded + fp_reg_size
6488 - FP_INC * UNITS_PER_FPREG);
6489 cfun->machine->frame.fp_sp_offset = offset;
6490 cfun->machine->frame.fp_save_offset = offset - total_size;
6494 cfun->machine->frame.fp_sp_offset = 0;
6495 cfun->machine->frame.fp_save_offset = 0;
6498 /* Ok, we're done. */
6502 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6503 pointer or argument pointer. TO is either the stack pointer or
6504 hard frame pointer. */
6507 mips_initial_elimination_offset (int from, int to)
6509 HOST_WIDE_INT offset;
6511 compute_frame_size (get_frame_size ());
6513 /* Set OFFSET to the offset from the stack pointer. */
6516 case FRAME_POINTER_REGNUM:
6520 case ARG_POINTER_REGNUM:
6521 offset = (cfun->machine->frame.total_size
6522 - current_function_pretend_args_size);
6529 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6530 offset -= cfun->machine->frame.args_size;
6535 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6536 back to a previous frame. */
6538 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6543 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6546 /* Use FN to save or restore register REGNO. MODE is the register's
6547 mode and OFFSET is the offset of its save slot from the current
6551 mips_save_restore_reg (enum machine_mode mode, int regno,
6552 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6556 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
6558 fn (gen_rtx_REG (mode, regno), mem);
6562 /* Call FN for each register that is saved by the current function.
6563 SP_OFFSET is the offset of the current stack pointer from the start
6567 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6569 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6571 enum machine_mode fpr_mode;
6572 HOST_WIDE_INT offset;
6575 /* Save registers starting from high to low. The debuggers prefer at least
6576 the return register be stored at func+4, and also it allows us not to
6577 need a nop in the epilog if at least one register is reloaded in
6578 addition to return address. */
6579 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6580 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6581 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6583 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6584 offset -= GET_MODE_SIZE (gpr_mode);
6587 /* This loop must iterate over the same space as its companion in
6588 compute_frame_size. */
6589 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6590 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6591 for (regno = (FP_REG_LAST - FP_INC + 1);
6592 regno >= FP_REG_FIRST;
6594 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6596 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6597 offset -= GET_MODE_SIZE (fpr_mode);
6602 /* If we're generating n32 or n64 abicalls, and the current function
6603 does not use $28 as its global pointer, emit a cplocal directive.
6604 Use pic_offset_table_rtx as the argument to the directive. */
6607 mips_output_cplocal (void)
6609 if (!TARGET_EXPLICIT_RELOCS
6610 && cfun->machine->global_pointer > 0
6611 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6612 output_asm_insn (".cplocal %+", 0);
6615 /* Return the style of GP load sequence that is being used for the
6616 current function. */
6618 enum mips_loadgp_style
6619 mips_current_loadgp_style (void)
6621 if (!TARGET_ABICALLS || cfun->machine->global_pointer == 0)
6624 if (TARGET_ABSOLUTE_ABICALLS)
6625 return LOADGP_ABSOLUTE;
6627 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
6630 /* The __gnu_local_gp symbol. */
6632 static GTY(()) rtx mips_gnu_local_gp;
6634 /* If we're generating n32 or n64 abicalls, emit instructions
6635 to set up the global pointer. */
6638 mips_emit_loadgp (void)
6640 rtx addr, offset, incoming_address;
6642 switch (mips_current_loadgp_style ())
6644 case LOADGP_ABSOLUTE:
6645 if (mips_gnu_local_gp == NULL)
6647 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
6648 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
6650 emit_insn (gen_loadgp_noshared (mips_gnu_local_gp));
6654 addr = XEXP (DECL_RTL (current_function_decl), 0);
6655 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6656 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6657 emit_insn (gen_loadgp (offset, incoming_address));
6658 if (!TARGET_EXPLICIT_RELOCS)
6659 emit_insn (gen_loadgp_blockage ());
6667 /* Set up the stack and frame (if desired) for the function. */
6670 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6673 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6675 #ifdef SDB_DEBUGGING_INFO
6676 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6677 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6680 /* In mips16 mode, we may need to generate a 32 bit to handle
6681 floating point arguments. The linker will arrange for any 32 bit
6682 functions to call this stub, which will then jump to the 16 bit
6684 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6685 && current_function_args_info.fp_code != 0)
6686 build_mips16_function_stub (file);
6688 if (!FUNCTION_NAME_ALREADY_DECLARED)
6690 /* Get the function name the same way that toplev.c does before calling
6691 assemble_start_function. This is needed so that the name used here
6692 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6693 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6695 if (!flag_inhibit_size_directive)
6697 fputs ("\t.ent\t", file);
6698 assemble_name (file, fnname);
6702 assemble_name (file, fnname);
6703 fputs (":\n", file);
6706 /* Stop mips_file_end from treating this function as external. */
6707 if (TARGET_IRIX && mips_abi == ABI_32)
6708 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
6710 if (!flag_inhibit_size_directive)
6712 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6714 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6715 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6716 ", args= " HOST_WIDE_INT_PRINT_DEC
6717 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6718 (reg_names[(frame_pointer_needed)
6719 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6720 ((frame_pointer_needed && TARGET_MIPS16)
6721 ? tsize - cfun->machine->frame.args_size
6723 reg_names[GP_REG_FIRST + 31],
6724 cfun->machine->frame.var_size,
6725 cfun->machine->frame.num_gp,
6726 cfun->machine->frame.num_fp,
6727 cfun->machine->frame.args_size,
6728 cfun->machine->frame.cprestore_size);
6730 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6731 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6732 cfun->machine->frame.mask,
6733 cfun->machine->frame.gp_save_offset);
6734 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6735 cfun->machine->frame.fmask,
6736 cfun->machine->frame.fp_save_offset);
6739 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6740 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6743 if (mips_current_loadgp_style () == LOADGP_OLDABI)
6745 /* Handle the initialization of $gp for SVR4 PIC. */
6746 if (!cfun->machine->all_noreorder_p)
6747 output_asm_insn ("%(.cpload\t%^%)", 0);
6749 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6751 else if (cfun->machine->all_noreorder_p)
6752 output_asm_insn ("%(%<", 0);
6754 /* Tell the assembler which register we're using as the global
6755 pointer. This is needed for thunks, since they can use either
6756 explicit relocs or assembler macros. */
6757 mips_output_cplocal ();
6760 /* Make the last instruction frame related and note that it performs
6761 the operation described by FRAME_PATTERN. */
6764 mips_set_frame_expr (rtx frame_pattern)
6768 insn = get_last_insn ();
6769 RTX_FRAME_RELATED_P (insn) = 1;
6770 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6776 /* Return a frame-related rtx that stores REG at MEM.
6777 REG must be a single register. */
6780 mips_frame_set (rtx mem, rtx reg)
6784 /* If we're saving the return address register and the dwarf return
6785 address column differs from the hard register number, adjust the
6786 note reg to refer to the former. */
6787 if (REGNO (reg) == GP_REG_FIRST + 31
6788 && DWARF_FRAME_RETURN_COLUMN != GP_REG_FIRST + 31)
6789 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
6791 set = gen_rtx_SET (VOIDmode, mem, reg);
6792 RTX_FRAME_RELATED_P (set) = 1;
6798 /* Save register REG to MEM. Make the instruction frame-related. */
6801 mips_save_reg (rtx reg, rtx mem)
6803 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6807 if (mips_split_64bit_move_p (mem, reg))
6808 mips_split_64bit_move (mem, reg);
6810 emit_move_insn (mem, reg);
6812 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6813 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6814 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6819 && REGNO (reg) != GP_REG_FIRST + 31
6820 && !M16_REG_P (REGNO (reg)))
6822 /* Save a non-mips16 register by moving it through a temporary.
6823 We don't need to do this for $31 since there's a special
6824 instruction for it. */
6825 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6826 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6829 emit_move_insn (mem, reg);
6831 mips_set_frame_expr (mips_frame_set (mem, reg));
6836 /* Expand the prologue into a bunch of separate insns. */
6839 mips_expand_prologue (void)
6843 if (cfun->machine->global_pointer > 0)
6844 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6846 size = compute_frame_size (get_frame_size ());
6848 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6849 bytes beforehand; this is enough to cover the register save area
6850 without going out of range. */
6851 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6853 HOST_WIDE_INT step1;
6855 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6856 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6858 GEN_INT (-step1)))) = 1;
6860 mips_for_each_saved_reg (size, mips_save_reg);
6863 /* Allocate the rest of the frame. */
6866 if (SMALL_OPERAND (-size))
6867 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6869 GEN_INT (-size)))) = 1;
6872 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6875 /* There are no instructions to add or subtract registers
6876 from the stack pointer, so use the frame pointer as a
6877 temporary. We should always be using a frame pointer
6878 in this case anyway. */
6879 gcc_assert (frame_pointer_needed);
6880 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6881 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6882 hard_frame_pointer_rtx,
6883 MIPS_PROLOGUE_TEMP (Pmode)));
6884 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6887 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6889 MIPS_PROLOGUE_TEMP (Pmode)));
6891 /* Describe the combined effect of the previous instructions. */
6893 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6894 plus_constant (stack_pointer_rtx, -size)));
6898 /* Set up the frame pointer, if we're using one. In mips16 code,
6899 we point the frame pointer ahead of the outgoing argument area.
6900 This should allow more variables & incoming arguments to be
6901 accessed with unextended instructions. */
6902 if (frame_pointer_needed)
6904 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6906 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6907 if (SMALL_OPERAND (cfun->machine->frame.args_size))
6909 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6914 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), offset);
6915 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6916 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6917 hard_frame_pointer_rtx,
6918 MIPS_PROLOGUE_TEMP (Pmode)));
6920 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
6921 plus_constant (stack_pointer_rtx,
6922 cfun->machine->frame.args_size)));
6926 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6927 stack_pointer_rtx)) = 1;
6930 mips_emit_loadgp ();
6932 /* If generating o32/o64 abicalls, save $gp on the stack. */
6933 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6934 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6936 /* If we are profiling, make sure no instructions are scheduled before
6937 the call to mcount. */
6939 if (current_function_profile)
6940 emit_insn (gen_blockage ());
6943 /* Do any necessary cleanup after a function to restore stack, frame,
6946 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6949 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6950 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6952 /* Reinstate the normal $gp. */
6953 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6954 mips_output_cplocal ();
6956 if (cfun->machine->all_noreorder_p)
6958 /* Avoid using %>%) since it adds excess whitespace. */
6959 output_asm_insn (".set\tmacro", 0);
6960 output_asm_insn (".set\treorder", 0);
6961 set_noreorder = set_nomacro = 0;
6964 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6968 /* Get the function name the same way that toplev.c does before calling
6969 assemble_start_function. This is needed so that the name used here
6970 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6971 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6972 fputs ("\t.end\t", file);
6973 assemble_name (file, fnname);
6978 /* Emit instructions to restore register REG from slot MEM. */
6981 mips_restore_reg (rtx reg, rtx mem)
6983 /* There's no mips16 instruction to load $31 directly. Load into
6984 $7 instead and adjust the return insn appropriately. */
6985 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6986 reg = gen_rtx_REG (GET_MODE (reg), 7);
6988 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6990 /* Can't restore directly; move through a temporary. */
6991 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6992 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6995 emit_move_insn (reg, mem);
6999 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
7000 if this epilogue precedes a sibling call, false if it is for a normal
7001 "epilogue" pattern. */
7004 mips_expand_epilogue (int sibcall_p)
7006 HOST_WIDE_INT step1, step2;
7009 if (!sibcall_p && mips_can_use_return_insn ())
7011 emit_jump_insn (gen_return ());
7015 /* Split the frame into two. STEP1 is the amount of stack we should
7016 deallocate before restoring the registers. STEP2 is the amount we
7017 should deallocate afterwards.
7019 Start off by assuming that no registers need to be restored. */
7020 step1 = cfun->machine->frame.total_size;
7023 /* Work out which register holds the frame address. Account for the
7024 frame pointer offset used by mips16 code. */
7025 if (!frame_pointer_needed)
7026 base = stack_pointer_rtx;
7029 base = hard_frame_pointer_rtx;
7031 step1 -= cfun->machine->frame.args_size;
7034 /* If we need to restore registers, deallocate as much stack as
7035 possible in the second step without going out of range. */
7036 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
7038 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
7042 /* Set TARGET to BASE + STEP1. */
7048 /* Get an rtx for STEP1 that we can add to BASE. */
7049 adjust = GEN_INT (step1);
7050 if (!SMALL_OPERAND (step1))
7052 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
7053 adjust = MIPS_EPILOGUE_TEMP (Pmode);
7056 /* Normal mode code can copy the result straight into $sp. */
7058 target = stack_pointer_rtx;
7060 emit_insn (gen_add3_insn (target, base, adjust));
7063 /* Copy TARGET into the stack pointer. */
7064 if (target != stack_pointer_rtx)
7065 emit_move_insn (stack_pointer_rtx, target);
7067 /* If we're using addressing macros for n32/n64 abicalls, $gp is
7068 implicitly used by all SYMBOL_REFs. We must emit a blockage
7069 insn before restoring it. */
7070 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
7071 emit_insn (gen_blockage ());
7073 /* Restore the registers. */
7074 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
7077 /* Deallocate the final bit of the frame. */
7079 emit_insn (gen_add3_insn (stack_pointer_rtx,
7083 /* Add in the __builtin_eh_return stack adjustment. We need to
7084 use a temporary in mips16 code. */
7085 if (current_function_calls_eh_return)
7089 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
7090 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
7091 MIPS_EPILOGUE_TEMP (Pmode),
7092 EH_RETURN_STACKADJ_RTX));
7093 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
7096 emit_insn (gen_add3_insn (stack_pointer_rtx,
7098 EH_RETURN_STACKADJ_RTX));
7103 /* The mips16 loads the return address into $7, not $31. */
7104 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7105 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7106 GP_REG_FIRST + 7)));
7108 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
7109 GP_REG_FIRST + 31)));
7113 /* Return nonzero if this function is known to have a null epilogue.
7114 This allows the optimizer to omit jumps to jumps if no stack
7118 mips_can_use_return_insn (void)
7122 if (! reload_completed)
7125 if (regs_ever_live[31] || current_function_profile)
7128 return_type = DECL_RESULT (current_function_decl);
7130 /* In mips16 mode, a function which returns a floating point value
7131 needs to arrange to copy the return value into the floating point
7134 && mips16_hard_float
7135 && ! aggregate_value_p (return_type, current_function_decl)
7136 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7137 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7140 if (cfun->machine->frame.initialized)
7141 return cfun->machine->frame.total_size == 0;
7143 return compute_frame_size (get_frame_size ()) == 0;
7146 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
7147 in order to avoid duplicating too much logic from elsewhere. */
7150 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7151 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7154 rtx this, temp1, temp2, insn, fnaddr;
7156 /* Pretend to be a post-reload pass while generating rtl. */
7158 reload_completed = 1;
7159 reset_block_changes ();
7161 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
7162 for TARGET_NEWABI since the latter is a call-saved register. */
7163 if (TARGET_ABICALLS)
7164 cfun->machine->global_pointer
7165 = REGNO (pic_offset_table_rtx)
7166 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
7168 /* Set up the global pointer for n32 or n64 abicalls. */
7169 mips_emit_loadgp ();
7171 /* We need two temporary registers in some cases. */
7172 temp1 = gen_rtx_REG (Pmode, 2);
7173 temp2 = gen_rtx_REG (Pmode, 3);
7175 /* Find out which register contains the "this" pointer. */
7176 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7177 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
7179 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
7181 /* Add DELTA to THIS. */
7184 rtx offset = GEN_INT (delta);
7185 if (!SMALL_OPERAND (delta))
7187 emit_move_insn (temp1, offset);
7190 emit_insn (gen_add3_insn (this, this, offset));
7193 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
7194 if (vcall_offset != 0)
7198 /* Set TEMP1 to *THIS. */
7199 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
7201 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
7202 addr = mips_add_offset (temp2, temp1, vcall_offset);
7204 /* Load the offset and add it to THIS. */
7205 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
7206 emit_insn (gen_add3_insn (this, this, temp1));
7209 /* Jump to the target function. Use a sibcall if direct jumps are
7210 allowed, otherwise load the address into a register first. */
7211 fnaddr = XEXP (DECL_RTL (function), 0);
7212 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7214 /* This is messy. gas treats "la $25,foo" as part of a call
7215 sequence and may allow a global "foo" to be lazily bound.
7216 The general move patterns therefore reject this combination.
7218 In this context, lazy binding would actually be OK for o32 and o64,
7219 but it's still wrong for n32 and n64; see mips_load_call_address.
7220 We must therefore load the address via a temporary register if
7221 mips_dangerous_for_la25_p.
7223 If we jump to the temporary register rather than $25, the assembler
7224 can use the move insn to fill the jump's delay slot. */
7225 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7226 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7227 mips_load_call_address (temp1, fnaddr, true);
7229 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7230 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7231 emit_jump_insn (gen_indirect_jump (temp1));
7235 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7236 SIBLING_CALL_P (insn) = 1;
7239 /* Run just enough of rest_of_compilation. This sequence was
7240 "borrowed" from alpha.c. */
7241 insn = get_insns ();
7242 insn_locators_initialize ();
7243 split_all_insns_noflow ();
7245 mips16_lay_out_constants ();
7246 shorten_branches (insn);
7247 final_start_function (insn, file, 1);
7248 final (insn, file, 1);
7249 final_end_function ();
7251 /* Clean up the vars set above. Note that final_end_function resets
7252 the global pointer for us. */
7253 reload_completed = 0;
7257 /* Returns nonzero if X contains a SYMBOL_REF. */
7260 symbolic_expression_p (rtx x)
7262 if (GET_CODE (x) == SYMBOL_REF)
7265 if (GET_CODE (x) == CONST)
7266 return symbolic_expression_p (XEXP (x, 0));
7269 return symbolic_expression_p (XEXP (x, 0));
7271 if (ARITHMETIC_P (x))
7272 return (symbolic_expression_p (XEXP (x, 0))
7273 || symbolic_expression_p (XEXP (x, 1)));
7278 /* Choose the section to use for the constant rtx expression X that has
7282 mips_select_rtx_section (enum machine_mode mode, rtx x,
7283 unsigned HOST_WIDE_INT align)
7287 /* In mips16 mode, the constant table always goes in the same section
7288 as the function, so that constants can be loaded using PC relative
7290 return function_section (current_function_decl);
7292 else if (TARGET_EMBEDDED_DATA)
7294 /* For embedded applications, always put constants in read-only data,
7295 in order to reduce RAM usage. */
7296 return mergeable_constant_section (mode, align, 0);
7300 /* For hosted applications, always put constants in small data if
7301 possible, as this gives the best performance. */
7302 /* ??? Consider using mergeable small data sections. */
7304 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7305 && mips_section_threshold > 0)
7306 return get_named_section (NULL, ".sdata", 0);
7307 else if (flag_pic && symbolic_expression_p (x))
7308 return get_named_section (NULL, ".data.rel.ro", 3);
7310 return mergeable_constant_section (mode, align, 0);
7314 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7316 The complication here is that, with the combination TARGET_ABICALLS
7317 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
7318 therefore not be included in the read-only part of a DSO. Handle such
7319 cases by selecting a normal data section instead of a read-only one.
7320 The logic apes that in default_function_rodata_section. */
7323 mips_function_rodata_section (tree decl)
7325 if (!TARGET_ABICALLS || TARGET_GPWORD)
7326 return default_function_rodata_section (decl);
7328 if (decl && DECL_SECTION_NAME (decl))
7330 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7331 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7333 char *rname = ASTRDUP (name);
7335 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7337 else if (flag_function_sections && flag_data_sections
7338 && strncmp (name, ".text.", 6) == 0)
7340 char *rname = ASTRDUP (name);
7341 memcpy (rname + 1, "data", 4);
7342 return get_section (rname, SECTION_WRITE, decl);
7345 return data_section;
7348 /* Implement TARGET_IN_SMALL_DATA_P. This function controls whether
7349 locally-defined objects go in a small data section. It also controls
7350 the setting of the SYMBOL_REF_SMALL_P flag, which in turn helps
7351 mips_classify_symbol decide when to use %gp_rel(...)($gp) accesses. */
7354 mips_in_small_data_p (tree decl)
7358 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7361 /* We don't yet generate small-data references for -mabicalls. See related
7362 -G handling in override_options. */
7363 if (TARGET_ABICALLS)
7366 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7370 /* Reject anything that isn't in a known small-data section. */
7371 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7372 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7375 /* If a symbol is defined externally, the assembler will use the
7376 usual -G rules when deciding how to implement macros. */
7377 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7380 else if (TARGET_EMBEDDED_DATA)
7382 /* Don't put constants into the small data section: we want them
7383 to be in ROM rather than RAM. */
7384 if (TREE_CODE (decl) != VAR_DECL)
7387 if (TREE_READONLY (decl)
7388 && !TREE_SIDE_EFFECTS (decl)
7389 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7393 size = int_size_in_bytes (TREE_TYPE (decl));
7394 return (size > 0 && size <= mips_section_threshold);
7397 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7398 anchors for small data: the GP register acts as an anchor in that
7399 case. We also don't want to use them for PC-relative accesses,
7400 where the PC acts as an anchor. */
7403 mips_use_anchors_for_symbol_p (rtx symbol)
7405 switch (mips_classify_symbol (symbol))
7407 case SYMBOL_CONSTANT_POOL:
7408 case SYMBOL_SMALL_DATA:
7416 /* See whether VALTYPE is a record whose fields should be returned in
7417 floating-point registers. If so, return the number of fields and
7418 list them in FIELDS (which should have two elements). Return 0
7421 For n32 & n64, a structure with one or two fields is returned in
7422 floating-point registers as long as every field has a floating-point
7426 mips_fpr_return_fields (tree valtype, tree *fields)
7434 if (TREE_CODE (valtype) != RECORD_TYPE)
7438 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7440 if (TREE_CODE (field) != FIELD_DECL)
7443 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7449 fields[i++] = field;
7455 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7456 a value in the most significant part of $2/$3 if:
7458 - the target is big-endian;
7460 - the value has a structure or union type (we generalize this to
7461 cover aggregates from other languages too); and
7463 - the structure is not returned in floating-point registers. */
7466 mips_return_in_msb (tree valtype)
7470 return (TARGET_NEWABI
7471 && TARGET_BIG_ENDIAN
7472 && AGGREGATE_TYPE_P (valtype)
7473 && mips_fpr_return_fields (valtype, fields) == 0);
7477 /* Return a composite value in a pair of floating-point registers.
7478 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7479 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7482 For n32 & n64, $f0 always holds the first value and $f2 the second.
7483 Otherwise the values are packed together as closely as possible. */
7486 mips_return_fpr_pair (enum machine_mode mode,
7487 enum machine_mode mode1, HOST_WIDE_INT offset1,
7488 enum machine_mode mode2, HOST_WIDE_INT offset2)
7492 inc = (TARGET_NEWABI ? 2 : FP_INC);
7493 return gen_rtx_PARALLEL
7496 gen_rtx_EXPR_LIST (VOIDmode,
7497 gen_rtx_REG (mode1, FP_RETURN),
7499 gen_rtx_EXPR_LIST (VOIDmode,
7500 gen_rtx_REG (mode2, FP_RETURN + inc),
7501 GEN_INT (offset2))));
7506 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7507 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7508 VALTYPE is null and MODE is the mode of the return value. */
7511 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7512 enum machine_mode mode)
7519 mode = TYPE_MODE (valtype);
7520 unsignedp = TYPE_UNSIGNED (valtype);
7522 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7523 true, we must promote the mode just as PROMOTE_MODE does. */
7524 mode = promote_mode (valtype, mode, &unsignedp, 1);
7526 /* Handle structures whose fields are returned in $f0/$f2. */
7527 switch (mips_fpr_return_fields (valtype, fields))
7530 return gen_rtx_REG (mode, FP_RETURN);
7533 return mips_return_fpr_pair (mode,
7534 TYPE_MODE (TREE_TYPE (fields[0])),
7535 int_byte_position (fields[0]),
7536 TYPE_MODE (TREE_TYPE (fields[1])),
7537 int_byte_position (fields[1]));
7540 /* If a value is passed in the most significant part of a register, see
7541 whether we have to round the mode up to a whole number of words. */
7542 if (mips_return_in_msb (valtype))
7544 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7545 if (size % UNITS_PER_WORD != 0)
7547 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7548 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7552 /* For EABI, the class of return register depends entirely on MODE.
7553 For example, "struct { some_type x; }" and "union { some_type x; }"
7554 are returned in the same way as a bare "some_type" would be.
7555 Other ABIs only use FPRs for scalar, complex or vector types. */
7556 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
7557 return gen_rtx_REG (mode, GP_RETURN);
7560 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
7561 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
7562 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7563 return gen_rtx_REG (mode, FP_RETURN);
7565 /* Handle long doubles for n32 & n64. */
7567 return mips_return_fpr_pair (mode,
7569 DImode, GET_MODE_SIZE (mode) / 2);
7571 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7572 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7573 return mips_return_fpr_pair (mode,
7574 GET_MODE_INNER (mode), 0,
7575 GET_MODE_INNER (mode),
7576 GET_MODE_SIZE (mode) / 2);
7578 return gen_rtx_REG (mode, GP_RETURN);
7581 /* Return nonzero when an argument must be passed by reference. */
7584 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7585 enum machine_mode mode, tree type,
7586 bool named ATTRIBUTE_UNUSED)
7588 if (mips_abi == ABI_EABI)
7592 /* ??? How should SCmode be handled? */
7593 if (mode == DImode || mode == DFmode)
7596 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
7597 return size == -1 || size > UNITS_PER_WORD;
7601 /* If we have a variable-sized parameter, we have no choice. */
7602 return targetm.calls.must_pass_in_stack (mode, type);
7607 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7608 enum machine_mode mode ATTRIBUTE_UNUSED,
7609 tree type ATTRIBUTE_UNUSED, bool named)
7611 return mips_abi == ABI_EABI && named;
7614 /* Return true if registers of class CLASS cannot change from mode FROM
7618 mips_cannot_change_mode_class (enum machine_mode from,
7619 enum machine_mode to, enum reg_class class)
7621 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
7622 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
7624 if (TARGET_BIG_ENDIAN)
7626 /* When a multi-word value is stored in paired floating-point
7627 registers, the first register always holds the low word.
7628 We therefore can't allow FPRs to change between single-word
7629 and multi-word modes. */
7630 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
7635 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
7636 in LO and HI, the high word always comes first. We therefore
7637 can't allow values stored in HI to change between single-word
7638 and multi-word modes.
7639 This rule applies to both the original HI/LO pair and the new
7640 DSP accumulators. */
7641 if (reg_classes_intersect_p (ACC_REGS, class))
7645 /* Loading a 32-bit value into a 64-bit floating-point register
7646 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7647 We can't allow 64-bit float registers to change from SImode to
7651 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
7652 && reg_classes_intersect_p (FP_REGS, class))
7657 /* Return true if X should not be moved directly into register $25.
7658 We need this because many versions of GAS will treat "la $25,foo" as
7659 part of a call sequence and so allow a global "foo" to be lazily bound. */
7662 mips_dangerous_for_la25_p (rtx x)
7664 HOST_WIDE_INT offset;
7666 if (TARGET_EXPLICIT_RELOCS)
7669 mips_split_const (x, &x, &offset);
7670 return global_got_operand (x, VOIDmode);
7673 /* Implement PREFERRED_RELOAD_CLASS. */
7676 mips_preferred_reload_class (rtx x, enum reg_class class)
7678 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7681 if (TARGET_HARD_FLOAT
7682 && FLOAT_MODE_P (GET_MODE (x))
7683 && reg_class_subset_p (FP_REGS, class))
7686 if (reg_class_subset_p (GR_REGS, class))
7689 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7695 /* This function returns the register class required for a secondary
7696 register when copying between one of the registers in CLASS, and X,
7697 using MODE. If IN_P is nonzero, the copy is going from X to the
7698 register, otherwise the register is the source. A return value of
7699 NO_REGS means that no secondary register is required. */
7702 mips_secondary_reload_class (enum reg_class class,
7703 enum machine_mode mode, rtx x, int in_p)
7705 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7709 if (REG_P (x)|| GET_CODE (x) == SUBREG)
7710 regno = true_regnum (x);
7712 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7714 if (mips_dangerous_for_la25_p (x))
7717 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7721 /* Copying from HI or LO to anywhere other than a general register
7722 requires a general register.
7723 This rule applies to both the original HI/LO pair and the new
7724 DSP accumulators. */
7725 if (reg_class_subset_p (class, ACC_REGS))
7727 if (TARGET_MIPS16 && in_p)
7729 /* We can't really copy to HI or LO at all in mips16 mode. */
7732 return gp_reg_p ? NO_REGS : gr_regs;
7734 if (ACC_REG_P (regno))
7736 if (TARGET_MIPS16 && ! in_p)
7738 /* We can't really copy to HI or LO at all in mips16 mode. */
7741 return class == gr_regs ? NO_REGS : gr_regs;
7744 /* We can only copy a value to a condition code register from a
7745 floating point register, and even then we require a scratch
7746 floating point register. We can only copy a value out of a
7747 condition code register into a general register. */
7748 if (class == ST_REGS)
7752 return gp_reg_p ? NO_REGS : gr_regs;
7754 if (ST_REG_P (regno))
7758 return class == gr_regs ? NO_REGS : gr_regs;
7761 if (class == FP_REGS)
7765 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7768 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7770 /* We can use the l.s and l.d macros to load floating-point
7771 constants. ??? For l.s, we could probably get better
7772 code by returning GR_REGS here. */
7775 else if (gp_reg_p || x == CONST0_RTX (mode))
7777 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7780 else if (FP_REG_P (regno))
7782 /* In this case we can use mov.s or mov.d. */
7787 /* Otherwise, we need to reload through an integer register. */
7792 /* In mips16 mode, going between memory and anything but M16_REGS
7793 requires an M16_REG. */
7796 if (class != M16_REGS && class != M16_NA_REGS)
7804 if (class == M16_REGS || class == M16_NA_REGS)
7813 /* Implement CLASS_MAX_NREGS.
7815 Usually all registers are word-sized. The only supported exception
7816 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7817 registers. A word-based calculation is correct even in that case,
7818 since -msingle-float disallows multi-FPR values.
7820 The FP status registers are an exception to this rule. They are always
7821 4 bytes wide as they only hold condition code modes, and CCmode is always
7822 considered to be 4 bytes wide. */
7825 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7826 enum machine_mode mode)
7828 if (class == ST_REGS)
7829 return (GET_MODE_SIZE (mode) + 3) / 4;
7831 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7835 mips_valid_pointer_mode (enum machine_mode mode)
7837 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7840 /* Target hook for vector_mode_supported_p. */
7843 mips_vector_mode_supported_p (enum machine_mode mode)
7848 return TARGET_PAIRED_SINGLE_FLOAT;
7859 /* If we can access small data directly (using gp-relative relocation
7860 operators) return the small data pointer, otherwise return null.
7862 For each mips16 function which refers to GP relative symbols, we
7863 use a pseudo register, initialized at the start of the function, to
7864 hold the $gp value. */
7867 mips16_gp_pseudo_reg (void)
7869 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7874 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7876 /* We want to initialize this to a value which gcc will believe
7879 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7880 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7881 gen_rtx_CONST (Pmode, unspec));
7882 insn = get_insns ();
7885 push_topmost_sequence ();
7886 /* We need to emit the initialization after the FUNCTION_BEG
7887 note, so that it will be integrated. */
7888 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7890 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7892 if (scan == NULL_RTX)
7893 scan = get_insns ();
7894 insn = emit_insn_after (insn, scan);
7895 pop_topmost_sequence ();
7898 return cfun->machine->mips16_gp_pseudo_rtx;
7901 /* Write out code to move floating point arguments in or out of
7902 general registers. Output the instructions to FILE. FP_CODE is
7903 the code describing which arguments are present (see the comment at
7904 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7905 we are copying from the floating point registers. */
7908 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7914 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7915 gcc_assert (TARGET_OLDABI);
7921 gparg = GP_ARG_FIRST;
7922 fparg = FP_ARG_FIRST;
7923 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7927 if ((fparg & 1) != 0)
7929 fprintf (file, "\t%s\t%s,%s\n", s,
7930 reg_names[gparg], reg_names[fparg]);
7932 else if ((f & 3) == 2)
7935 fprintf (file, "\td%s\t%s,%s\n", s,
7936 reg_names[gparg], reg_names[fparg]);
7939 if ((fparg & 1) != 0)
7941 if (TARGET_BIG_ENDIAN)
7942 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7943 reg_names[gparg], reg_names[fparg + 1], s,
7944 reg_names[gparg + 1], reg_names[fparg]);
7946 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7947 reg_names[gparg], reg_names[fparg], s,
7948 reg_names[gparg + 1], reg_names[fparg + 1]);
7961 /* Build a mips16 function stub. This is used for functions which
7962 take arguments in the floating point registers. It is 32 bit code
7963 that moves the floating point args into the general registers, and
7964 then jumps to the 16 bit code. */
7967 build_mips16_function_stub (FILE *file)
7970 char *secname, *stubname;
7971 tree stubid, stubdecl;
7975 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7976 secname = (char *) alloca (strlen (fnname) + 20);
7977 sprintf (secname, ".mips16.fn.%s", fnname);
7978 stubname = (char *) alloca (strlen (fnname) + 20);
7979 sprintf (stubname, "__fn_stub_%s", fnname);
7980 stubid = get_identifier (stubname);
7981 stubdecl = build_decl (FUNCTION_DECL, stubid,
7982 build_function_type (void_type_node, NULL_TREE));
7983 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7985 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7987 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7989 fprintf (file, "%s%s",
7990 need_comma ? ", " : "",
7991 (f & 3) == 1 ? "float" : "double");
7994 fprintf (file, ")\n");
7996 fprintf (file, "\t.set\tnomips16\n");
7997 switch_to_section (function_section (stubdecl));
7998 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8000 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8001 within a .ent, and we cannot emit another .ent. */
8002 if (!FUNCTION_NAME_ALREADY_DECLARED)
8004 fputs ("\t.ent\t", file);
8005 assemble_name (file, stubname);
8009 assemble_name (file, stubname);
8010 fputs (":\n", file);
8012 /* We don't want the assembler to insert any nops here. */
8013 fprintf (file, "\t.set\tnoreorder\n");
8015 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8017 fprintf (asm_out_file, "\t.set\tnoat\n");
8018 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8019 assemble_name (file, fnname);
8020 fprintf (file, "\n");
8021 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8022 fprintf (asm_out_file, "\t.set\tat\n");
8024 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8025 with one of the mfc1 instructions, because the result is not
8026 available for one instruction, so if the very first instruction
8027 in the function refers to the register, it will see the wrong
8029 fprintf (file, "\tnop\n");
8031 fprintf (file, "\t.set\treorder\n");
8033 if (!FUNCTION_NAME_ALREADY_DECLARED)
8035 fputs ("\t.end\t", file);
8036 assemble_name (file, stubname);
8040 fprintf (file, "\t.set\tmips16\n");
8042 switch_to_section (function_section (current_function_decl));
8045 /* We keep a list of functions for which we have already built stubs
8046 in build_mips16_call_stub. */
8050 struct mips16_stub *next;
8055 static struct mips16_stub *mips16_stubs;
8057 /* Build a call stub for a mips16 call. A stub is needed if we are
8058 passing any floating point values which should go into the floating
8059 point registers. If we are, and the call turns out to be to a 32
8060 bit function, the stub will be used to move the values into the
8061 floating point registers before calling the 32 bit function. The
8062 linker will magically adjust the function call to either the 16 bit
8063 function or the 32 bit stub, depending upon where the function call
8064 is actually defined.
8066 Similarly, we need a stub if the return value might come back in a
8067 floating point register.
8069 RETVAL is the location of the return value, or null if this is
8070 a call rather than a call_value. FN is the address of the
8071 function and ARG_SIZE is the size of the arguments. FP_CODE
8072 is the code built by function_arg. This function returns a nonzero
8073 value if it builds the call instruction itself. */
8076 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
8080 char *secname, *stubname;
8081 struct mips16_stub *l;
8082 tree stubid, stubdecl;
8086 /* We don't need to do anything if we aren't in mips16 mode, or if
8087 we were invoked with the -msoft-float option. */
8088 if (! TARGET_MIPS16 || ! mips16_hard_float)
8091 /* Figure out whether the value might come back in a floating point
8093 fpret = (retval != 0
8094 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8095 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8097 /* We don't need to do anything if there were no floating point
8098 arguments and the value will not be returned in a floating point
8100 if (fp_code == 0 && ! fpret)
8103 /* We don't need to do anything if this is a call to a special
8104 mips16 support function. */
8105 if (GET_CODE (fn) == SYMBOL_REF
8106 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8109 /* This code will only work for o32 and o64 abis. The other ABI's
8110 require more sophisticated support. */
8111 gcc_assert (TARGET_OLDABI);
8113 /* We can only handle SFmode and DFmode floating point return
8116 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
8118 /* If we're calling via a function pointer, then we must always call
8119 via a stub. There are magic stubs provided in libgcc.a for each
8120 of the required cases. Each of them expects the function address
8121 to arrive in register $2. */
8123 if (GET_CODE (fn) != SYMBOL_REF)
8129 /* ??? If this code is modified to support other ABI's, we need
8130 to handle PARALLEL return values here. */
8132 sprintf (buf, "__mips16_call_stub_%s%d",
8134 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8137 id = get_identifier (buf);
8138 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
8140 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
8142 if (retval == NULL_RTX)
8143 insn = gen_call_internal (stub_fn, arg_size);
8145 insn = gen_call_value_internal (retval, stub_fn, arg_size);
8146 insn = emit_call_insn (insn);
8148 /* Put the register usage information on the CALL. */
8149 CALL_INSN_FUNCTION_USAGE (insn) =
8150 gen_rtx_EXPR_LIST (VOIDmode,
8151 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
8152 CALL_INSN_FUNCTION_USAGE (insn));
8154 /* If we are handling a floating point return value, we need to
8155 save $18 in the function prologue. Putting a note on the
8156 call will mean that regs_ever_live[$18] will be true if the
8157 call is not eliminated, and we can check that in the prologue
8160 CALL_INSN_FUNCTION_USAGE (insn) =
8161 gen_rtx_EXPR_LIST (VOIDmode,
8162 gen_rtx_USE (VOIDmode,
8163 gen_rtx_REG (word_mode, 18)),
8164 CALL_INSN_FUNCTION_USAGE (insn));
8166 /* Return 1 to tell the caller that we've generated the call
8171 /* We know the function we are going to call. If we have already
8172 built a stub, we don't need to do anything further. */
8174 fnname = XSTR (fn, 0);
8175 for (l = mips16_stubs; l != NULL; l = l->next)
8176 if (strcmp (l->name, fnname) == 0)
8181 /* Build a special purpose stub. When the linker sees a
8182 function call in mips16 code, it will check where the target
8183 is defined. If the target is a 32 bit call, the linker will
8184 search for the section defined here. It can tell which
8185 symbol this section is associated with by looking at the
8186 relocation information (the name is unreliable, since this
8187 might be a static function). If such a section is found, the
8188 linker will redirect the call to the start of the magic
8191 If the function does not return a floating point value, the
8192 special stub section is named
8195 If the function does return a floating point value, the stub
8197 .mips16.call.fp.FNNAME
8200 secname = (char *) alloca (strlen (fnname) + 40);
8201 sprintf (secname, ".mips16.call.%s%s",
8204 stubname = (char *) alloca (strlen (fnname) + 20);
8205 sprintf (stubname, "__call_stub_%s%s",
8208 stubid = get_identifier (stubname);
8209 stubdecl = build_decl (FUNCTION_DECL, stubid,
8210 build_function_type (void_type_node, NULL_TREE));
8211 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8213 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8215 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8219 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8221 fprintf (asm_out_file, "%s%s",
8222 need_comma ? ", " : "",
8223 (f & 3) == 1 ? "float" : "double");
8226 fprintf (asm_out_file, ")\n");
8228 fprintf (asm_out_file, "\t.set\tnomips16\n");
8229 assemble_start_function (stubdecl, stubname);
8231 if (!FUNCTION_NAME_ALREADY_DECLARED)
8233 fputs ("\t.ent\t", asm_out_file);
8234 assemble_name (asm_out_file, stubname);
8235 fputs ("\n", asm_out_file);
8237 assemble_name (asm_out_file, stubname);
8238 fputs (":\n", asm_out_file);
8241 /* We build the stub code by hand. That's the only way we can
8242 do it, since we can't generate 32 bit code during a 16 bit
8245 /* We don't want the assembler to insert any nops here. */
8246 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8248 mips16_fp_args (asm_out_file, fp_code, 0);
8252 fprintf (asm_out_file, "\t.set\tnoat\n");
8253 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8255 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8256 fprintf (asm_out_file, "\t.set\tat\n");
8257 /* Unfortunately, we can't fill the jump delay slot. We
8258 can't fill with one of the mtc1 instructions, because the
8259 result is not available for one instruction, so if the
8260 very first instruction in the function refers to the
8261 register, it will see the wrong value. */
8262 fprintf (asm_out_file, "\tnop\n");
8266 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8267 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8268 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8269 /* As above, we can't fill the delay slot. */
8270 fprintf (asm_out_file, "\tnop\n");
8271 if (GET_MODE (retval) == SFmode)
8272 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8273 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8276 if (TARGET_BIG_ENDIAN)
8278 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8279 reg_names[GP_REG_FIRST + 2],
8280 reg_names[FP_REG_FIRST + 1]);
8281 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8282 reg_names[GP_REG_FIRST + 3],
8283 reg_names[FP_REG_FIRST + 0]);
8287 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8288 reg_names[GP_REG_FIRST + 2],
8289 reg_names[FP_REG_FIRST + 0]);
8290 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8291 reg_names[GP_REG_FIRST + 3],
8292 reg_names[FP_REG_FIRST + 1]);
8295 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8296 /* As above, we can't fill the delay slot. */
8297 fprintf (asm_out_file, "\tnop\n");
8300 fprintf (asm_out_file, "\t.set\treorder\n");
8302 #ifdef ASM_DECLARE_FUNCTION_SIZE
8303 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8306 if (!FUNCTION_NAME_ALREADY_DECLARED)
8308 fputs ("\t.end\t", asm_out_file);
8309 assemble_name (asm_out_file, stubname);
8310 fputs ("\n", asm_out_file);
8313 fprintf (asm_out_file, "\t.set\tmips16\n");
8315 /* Record this stub. */
8316 l = (struct mips16_stub *) xmalloc (sizeof *l);
8317 l->name = xstrdup (fnname);
8319 l->next = mips16_stubs;
8323 /* If we expect a floating point return value, but we've built a
8324 stub which does not expect one, then we're in trouble. We can't
8325 use the existing stub, because it won't handle the floating point
8326 value. We can't build a new stub, because the linker won't know
8327 which stub to use for the various calls in this object file.
8328 Fortunately, this case is illegal, since it means that a function
8329 was declared in two different ways in a single compilation. */
8330 if (fpret && ! l->fpret)
8331 error ("cannot handle inconsistent calls to %qs", fnname);
8333 /* If we are calling a stub which handles a floating point return
8334 value, we need to arrange to save $18 in the prologue. We do
8335 this by marking the function call as using the register. The
8336 prologue will later see that it is used, and emit code to save
8343 if (retval == NULL_RTX)
8344 insn = gen_call_internal (fn, arg_size);
8346 insn = gen_call_value_internal (retval, fn, arg_size);
8347 insn = emit_call_insn (insn);
8349 CALL_INSN_FUNCTION_USAGE (insn) =
8350 gen_rtx_EXPR_LIST (VOIDmode,
8351 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8352 CALL_INSN_FUNCTION_USAGE (insn));
8354 /* Return 1 to tell the caller that we've generated the call
8359 /* Return 0 to let the caller generate the call insn. */
8363 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8364 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8366 struct mips16_constant {
8367 struct mips16_constant *next;
8370 enum machine_mode mode;
8373 /* Information about an incomplete mips16 constant pool. FIRST is the
8374 first constant, HIGHEST_ADDRESS is the highest address that the first
8375 byte of the pool can have, and INSN_ADDRESS is the current instruction
8378 struct mips16_constant_pool {
8379 struct mips16_constant *first;
8380 int highest_address;
8384 /* Add constant VALUE to POOL and return its label. MODE is the
8385 value's mode (used for CONST_INTs, etc.). */
8388 add_constant (struct mips16_constant_pool *pool,
8389 rtx value, enum machine_mode mode)
8391 struct mips16_constant **p, *c;
8392 bool first_of_size_p;
8394 /* See whether the constant is already in the pool. If so, return the
8395 existing label, otherwise leave P pointing to the place where the
8396 constant should be added.
8398 Keep the pool sorted in increasing order of mode size so that we can
8399 reduce the number of alignments needed. */
8400 first_of_size_p = true;
8401 for (p = &pool->first; *p != 0; p = &(*p)->next)
8403 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8405 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8407 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8408 first_of_size_p = false;
8411 /* In the worst case, the constant needed by the earliest instruction
8412 will end up at the end of the pool. The entire pool must then be
8413 accessible from that instruction.
8415 When adding the first constant, set the pool's highest address to
8416 the address of the first out-of-range byte. Adjust this address
8417 downwards each time a new constant is added. */
8418 if (pool->first == 0)
8419 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8420 is the address of the instruction with the lowest two bits clear.
8421 The base PC value for ld has the lowest three bits clear. Assume
8422 the worst case here. */
8423 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8424 pool->highest_address -= GET_MODE_SIZE (mode);
8425 if (first_of_size_p)
8426 /* Take into account the worst possible padding due to alignment. */
8427 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8429 /* Create a new entry. */
8430 c = (struct mips16_constant *) xmalloc (sizeof *c);
8433 c->label = gen_label_rtx ();
8440 /* Output constant VALUE after instruction INSN and return the last
8441 instruction emitted. MODE is the mode of the constant. */
8444 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8446 switch (GET_MODE_CLASS (mode))
8450 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8451 return emit_insn_after (gen_consttable_int (value, size), insn);
8455 return emit_insn_after (gen_consttable_float (value), insn);
8457 case MODE_VECTOR_FLOAT:
8458 case MODE_VECTOR_INT:
8461 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8462 insn = dump_constants_1 (GET_MODE_INNER (mode),
8463 CONST_VECTOR_ELT (value, i), insn);
8473 /* Dump out the constants in CONSTANTS after INSN. */
8476 dump_constants (struct mips16_constant *constants, rtx insn)
8478 struct mips16_constant *c, *next;
8482 for (c = constants; c != NULL; c = next)
8484 /* If necessary, increase the alignment of PC. */
8485 if (align < GET_MODE_SIZE (c->mode))
8487 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8488 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8490 align = GET_MODE_SIZE (c->mode);
8492 insn = emit_label_after (c->label, insn);
8493 insn = dump_constants_1 (c->mode, c->value, insn);
8499 emit_barrier_after (insn);
8502 /* Return the length of instruction INSN. */
8505 mips16_insn_length (rtx insn)
8509 rtx body = PATTERN (insn);
8510 if (GET_CODE (body) == ADDR_VEC)
8511 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8512 if (GET_CODE (body) == ADDR_DIFF_VEC)
8513 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8515 return get_attr_length (insn);
8518 /* Rewrite *X so that constant pool references refer to the constant's
8519 label instead. DATA points to the constant pool structure. */
8522 mips16_rewrite_pool_refs (rtx *x, void *data)
8524 struct mips16_constant_pool *pool = data;
8525 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8526 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8527 get_pool_constant (*x),
8528 get_pool_mode (*x)));
8532 /* Build MIPS16 constant pools. */
8535 mips16_lay_out_constants (void)
8537 struct mips16_constant_pool pool;
8541 memset (&pool, 0, sizeof (pool));
8542 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8544 /* Rewrite constant pool references in INSN. */
8546 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8548 pool.insn_address += mips16_insn_length (insn);
8550 if (pool.first != NULL)
8552 /* If there are no natural barriers between the first user of
8553 the pool and the highest acceptable address, we'll need to
8554 create a new instruction to jump around the constant pool.
8555 In the worst case, this instruction will be 4 bytes long.
8557 If it's too late to do this transformation after INSN,
8558 do it immediately before INSN. */
8559 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8563 label = gen_label_rtx ();
8565 jump = emit_jump_insn_before (gen_jump (label), insn);
8566 JUMP_LABEL (jump) = label;
8567 LABEL_NUSES (label) = 1;
8568 barrier = emit_barrier_after (jump);
8570 emit_label_after (label, barrier);
8571 pool.insn_address += 4;
8574 /* See whether the constant pool is now out of range of the first
8575 user. If so, output the constants after the previous barrier.
8576 Note that any instructions between BARRIER and INSN (inclusive)
8577 will use negative offsets to refer to the pool. */
8578 if (pool.insn_address > pool.highest_address)
8580 dump_constants (pool.first, barrier);
8584 else if (BARRIER_P (insn))
8588 dump_constants (pool.first, get_last_insn ());
8591 /* A temporary variable used by for_each_rtx callbacks, etc. */
8592 static rtx mips_sim_insn;
8594 /* A structure representing the state of the processor pipeline.
8595 Used by the mips_sim_* family of functions. */
8597 /* The maximum number of instructions that can be issued in a cycle.
8598 (Caches mips_issue_rate.) */
8599 unsigned int issue_rate;
8601 /* The current simulation time. */
8604 /* How many more instructions can be issued in the current cycle. */
8605 unsigned int insns_left;
8607 /* LAST_SET[X].INSN is the last instruction to set register X.
8608 LAST_SET[X].TIME is the time at which that instruction was issued.
8609 INSN is null if no instruction has yet set register X. */
8613 } last_set[FIRST_PSEUDO_REGISTER];
8615 /* The pipeline's current DFA state. */
8619 /* Reset STATE to the initial simulation state. */
8622 mips_sim_reset (struct mips_sim *state)
8625 state->insns_left = state->issue_rate;
8626 memset (&state->last_set, 0, sizeof (state->last_set));
8627 state_reset (state->dfa_state);
8630 /* Initialize STATE before its first use. DFA_STATE points to an
8631 allocated but uninitialized DFA state. */
8634 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8636 state->issue_rate = mips_issue_rate ();
8637 state->dfa_state = dfa_state;
8638 mips_sim_reset (state);
8641 /* Advance STATE by one clock cycle. */
8644 mips_sim_next_cycle (struct mips_sim *state)
8647 state->insns_left = state->issue_rate;
8648 state_transition (state->dfa_state, 0);
8651 /* Advance simulation state STATE until instruction INSN can read
8655 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8659 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8660 if (state->last_set[REGNO (reg) + i].insn != 0)
8664 t = state->last_set[REGNO (reg) + i].time;
8665 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8666 while (state->time < t)
8667 mips_sim_next_cycle (state);
8671 /* A for_each_rtx callback. If *X is a register, advance simulation state
8672 DATA until mips_sim_insn can read the register's value. */
8675 mips_sim_wait_regs_2 (rtx *x, void *data)
8678 mips_sim_wait_reg (data, mips_sim_insn, *x);
8682 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8685 mips_sim_wait_regs_1 (rtx *x, void *data)
8687 for_each_rtx (x, mips_sim_wait_regs_2, data);
8690 /* Advance simulation state STATE until all of INSN's register
8691 dependencies are satisfied. */
8694 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8696 mips_sim_insn = insn;
8697 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8700 /* Advance simulation state STATE until the units required by
8701 instruction INSN are available. */
8704 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8708 tmp_state = alloca (state_size ());
8709 while (state->insns_left == 0
8710 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8711 state_transition (tmp_state, insn) >= 0))
8712 mips_sim_next_cycle (state);
8715 /* Advance simulation state STATE until INSN is ready to issue. */
8718 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8720 mips_sim_wait_regs (state, insn);
8721 mips_sim_wait_units (state, insn);
8724 /* mips_sim_insn has just set X. Update the LAST_SET array
8725 in simulation state DATA. */
8728 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8730 struct mips_sim *state;
8735 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8737 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8738 state->last_set[REGNO (x) + i].time = state->time;
8742 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8743 can issue immediately (i.e., that mips_sim_wait_insn has already
8747 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8749 state_transition (state->dfa_state, insn);
8750 state->insns_left--;
8752 mips_sim_insn = insn;
8753 note_stores (PATTERN (insn), mips_sim_record_set, state);
8756 /* Simulate issuing a NOP in state STATE. */
8759 mips_sim_issue_nop (struct mips_sim *state)
8761 if (state->insns_left == 0)
8762 mips_sim_next_cycle (state);
8763 state->insns_left--;
8766 /* Update simulation state STATE so that it's ready to accept the instruction
8767 after INSN. INSN should be part of the main rtl chain, not a member of a
8771 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8773 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8775 mips_sim_issue_nop (state);
8777 switch (GET_CODE (SEQ_BEGIN (insn)))
8781 /* We can't predict the processor state after a call or label. */
8782 mips_sim_reset (state);
8786 /* The delay slots of branch likely instructions are only executed
8787 when the branch is taken. Therefore, if the caller has simulated
8788 the delay slot instruction, STATE does not really reflect the state
8789 of the pipeline for the instruction after the delay slot. Also,
8790 branch likely instructions tend to incur a penalty when not taken,
8791 so there will probably be an extra delay between the branch and
8792 the instruction after the delay slot. */
8793 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8794 mips_sim_reset (state);
8802 /* The VR4130 pipeline issues aligned pairs of instructions together,
8803 but it stalls the second instruction if it depends on the first.
8804 In order to cut down the amount of logic required, this dependence
8805 check is not based on a full instruction decode. Instead, any non-SPECIAL
8806 instruction is assumed to modify the register specified by bits 20-16
8807 (which is usually the "rt" field).
8809 In beq, beql, bne and bnel instructions, the rt field is actually an
8810 input, so we can end up with a false dependence between the branch
8811 and its delay slot. If this situation occurs in instruction INSN,
8812 try to avoid it by swapping rs and rt. */
8815 vr4130_avoid_branch_rt_conflict (rtx insn)
8819 first = SEQ_BEGIN (insn);
8820 second = SEQ_END (insn);
8822 && NONJUMP_INSN_P (second)
8823 && GET_CODE (PATTERN (first)) == SET
8824 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8825 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8827 /* Check for the right kind of condition. */
8828 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8829 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8830 && REG_P (XEXP (cond, 0))
8831 && REG_P (XEXP (cond, 1))
8832 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8833 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8835 /* SECOND mentions the rt register but not the rs register. */
8836 rtx tmp = XEXP (cond, 0);
8837 XEXP (cond, 0) = XEXP (cond, 1);
8838 XEXP (cond, 1) = tmp;
8843 /* Implement -mvr4130-align. Go through each basic block and simulate the
8844 processor pipeline. If we find that a pair of instructions could execute
8845 in parallel, and the first of those instruction is not 8-byte aligned,
8846 insert a nop to make it aligned. */
8849 vr4130_align_insns (void)
8851 struct mips_sim state;
8852 rtx insn, subinsn, last, last2, next;
8857 /* LAST is the last instruction before INSN to have a nonzero length.
8858 LAST2 is the last such instruction before LAST. */
8862 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8865 mips_sim_init (&state, alloca (state_size ()));
8866 for (insn = get_insns (); insn != 0; insn = next)
8868 unsigned int length;
8870 next = NEXT_INSN (insn);
8872 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8873 This isn't really related to the alignment pass, but we do it on
8874 the fly to avoid a separate instruction walk. */
8875 vr4130_avoid_branch_rt_conflict (insn);
8877 if (USEFUL_INSN_P (insn))
8878 FOR_EACH_SUBINSN (subinsn, insn)
8880 mips_sim_wait_insn (&state, subinsn);
8882 /* If we want this instruction to issue in parallel with the
8883 previous one, make sure that the previous instruction is
8884 aligned. There are several reasons why this isn't worthwhile
8885 when the second instruction is a call:
8887 - Calls are less likely to be performance critical,
8888 - There's a good chance that the delay slot can execute
8889 in parallel with the call.
8890 - The return address would then be unaligned.
8892 In general, if we're going to insert a nop between instructions
8893 X and Y, it's better to insert it immediately after X. That
8894 way, if the nop makes Y aligned, it will also align any labels
8896 if (state.insns_left != state.issue_rate
8897 && !CALL_P (subinsn))
8899 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8901 /* SUBINSN is the first instruction in INSN and INSN is
8902 aligned. We want to align the previous instruction
8903 instead, so insert a nop between LAST2 and LAST.
8905 Note that LAST could be either a single instruction
8906 or a branch with a delay slot. In the latter case,
8907 LAST, like INSN, is already aligned, but the delay
8908 slot must have some extra delay that stops it from
8909 issuing at the same time as the branch. We therefore
8910 insert a nop before the branch in order to align its
8912 emit_insn_after (gen_nop (), last2);
8915 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8917 /* SUBINSN is the delay slot of INSN, but INSN is
8918 currently unaligned. Insert a nop between
8919 LAST and INSN to align it. */
8920 emit_insn_after (gen_nop (), last);
8924 mips_sim_issue_insn (&state, subinsn);
8926 mips_sim_finish_insn (&state, insn);
8928 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8929 length = get_attr_length (insn);
8932 /* If the instruction is an asm statement or multi-instruction
8933 mips.md patern, the length is only an estimate. Insert an
8934 8 byte alignment after it so that the following instructions
8935 can be handled correctly. */
8936 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8937 && (recog_memoized (insn) < 0 || length >= 8))
8939 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8940 next = NEXT_INSN (next);
8941 mips_sim_next_cycle (&state);
8944 else if (length & 4)
8945 aligned_p = !aligned_p;
8950 /* See whether INSN is an aligned label. */
8951 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8957 /* Subroutine of mips_reorg. If there is a hazard between INSN
8958 and a previous instruction, avoid it by inserting nops after
8961 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8962 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8963 before using the value of that register. *HILO_DELAY counts the
8964 number of instructions since the last hilo hazard (that is,
8965 the number of instructions since the last mflo or mfhi).
8967 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8968 for the next instruction.
8970 LO_REG is an rtx for the LO register, used in dependence checking. */
8973 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8974 rtx *delayed_reg, rtx lo_reg)
8982 pattern = PATTERN (insn);
8984 /* Do not put the whole function in .set noreorder if it contains
8985 an asm statement. We don't know whether there will be hazards
8986 between the asm statement and the gcc-generated code. */
8987 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8988 cfun->machine->all_noreorder_p = false;
8990 /* Ignore zero-length instructions (barriers and the like). */
8991 ninsns = get_attr_length (insn) / 4;
8995 /* Work out how many nops are needed. Note that we only care about
8996 registers that are explicitly mentioned in the instruction's pattern.
8997 It doesn't matter that calls use the argument registers or that they
8998 clobber hi and lo. */
8999 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
9000 nops = 2 - *hilo_delay;
9001 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
9006 /* Insert the nops between this instruction and the previous one.
9007 Each new nop takes us further from the last hilo hazard. */
9008 *hilo_delay += nops;
9010 emit_insn_after (gen_hazard_nop (), after);
9012 /* Set up the state for the next instruction. */
9013 *hilo_delay += ninsns;
9015 if (INSN_CODE (insn) >= 0)
9016 switch (get_attr_hazard (insn))
9026 set = single_set (insn);
9027 gcc_assert (set != 0);
9028 *delayed_reg = SET_DEST (set);
9034 /* Go through the instruction stream and insert nops where necessary.
9035 See if the whole function can then be put into .set noreorder &
9039 mips_avoid_hazards (void)
9041 rtx insn, last_insn, lo_reg, delayed_reg;
9044 /* Force all instructions to be split into their final form. */
9045 split_all_insns_noflow ();
9047 /* Recalculate instruction lengths without taking nops into account. */
9048 cfun->machine->ignore_hazard_length_p = true;
9049 shorten_branches (get_insns ());
9051 cfun->machine->all_noreorder_p = true;
9053 /* Profiled functions can't be all noreorder because the profiler
9054 support uses assembler macros. */
9055 if (current_function_profile)
9056 cfun->machine->all_noreorder_p = false;
9058 /* Code compiled with -mfix-vr4120 can't be all noreorder because
9059 we rely on the assembler to work around some errata. */
9060 if (TARGET_FIX_VR4120)
9061 cfun->machine->all_noreorder_p = false;
9063 /* The same is true for -mfix-vr4130 if we might generate mflo or
9064 mfhi instructions. Note that we avoid using mflo and mfhi if
9065 the VR4130 macc and dmacc instructions are available instead;
9066 see the *mfhilo_{si,di}_macc patterns. */
9067 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
9068 cfun->machine->all_noreorder_p = false;
9073 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
9075 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
9078 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
9079 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
9080 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
9081 &hilo_delay, &delayed_reg, lo_reg);
9083 mips_avoid_hazard (last_insn, insn, &hilo_delay,
9084 &delayed_reg, lo_reg);
9091 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
9097 mips16_lay_out_constants ();
9098 else if (TARGET_EXPLICIT_RELOCS)
9100 if (mips_flag_delayed_branch)
9101 dbr_schedule (get_insns ());
9102 mips_avoid_hazards ();
9103 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
9104 vr4130_align_insns ();
9108 /* This function does three things:
9110 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
9111 - Register the mips16 hardware floating point stubs.
9112 - Register the gofast functions if selected using --enable-gofast. */
9114 #include "config/gofast.h"
9117 mips_init_libfuncs (void)
9119 if (TARGET_FIX_VR4120)
9121 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
9122 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
9125 if (TARGET_MIPS16 && mips16_hard_float)
9127 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
9128 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
9129 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
9130 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
9132 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
9133 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
9134 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
9135 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
9136 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
9137 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
9139 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
9140 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
9142 if (TARGET_DOUBLE_FLOAT)
9144 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
9145 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
9146 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
9147 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
9149 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
9150 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
9151 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
9152 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
9153 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
9154 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
9156 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
9157 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
9159 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
9160 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
9164 gofast_maybe_init_libfuncs ();
9167 /* Return a number assessing the cost of moving a register in class
9168 FROM to class TO. The classes are expressed using the enumeration
9169 values such as `GENERAL_REGS'. A value of 2 is the default; other
9170 values are interpreted relative to that.
9172 It is not required that the cost always equal 2 when FROM is the
9173 same as TO; on some machines it is expensive to move between
9174 registers if they are not general registers.
9176 If reload sees an insn consisting of a single `set' between two
9177 hard registers, and if `REGISTER_MOVE_COST' applied to their
9178 classes returns a value of 2, reload does not check to ensure that
9179 the constraints of the insn are met. Setting a cost of other than
9180 2 will allow reload to verify that the constraints are met. You
9181 should do this if the `movM' pattern's constraints do not allow
9184 ??? We make the cost of moving from HI/LO into general
9185 registers the same as for one of moving general registers to
9186 HI/LO for TARGET_MIPS16 in order to prevent allocating a
9187 pseudo to HI/LO. This might hurt optimizations though, it
9188 isn't clear if it is wise. And it might not work in all cases. We
9189 could solve the DImode LO reg problem by using a multiply, just
9190 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9191 problem by using divide instructions. divu puts the remainder in
9192 the HI reg, so doing a divide by -1 will move the value in the HI
9193 reg for all values except -1. We could handle that case by using a
9194 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9195 a compare/branch to test the input value to see which instruction
9196 we need to use. This gets pretty messy, but it is feasible. */
9199 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
9200 enum reg_class to, enum reg_class from)
9202 if (from == M16_REGS && GR_REG_CLASS_P (to))
9204 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9206 else if (GR_REG_CLASS_P (from))
9210 else if (to == M16_NA_REGS)
9212 else if (GR_REG_CLASS_P (to))
9219 else if (to == FP_REGS)
9221 else if (reg_class_subset_p (to, ACC_REGS))
9228 else if (COP_REG_CLASS_P (to))
9233 else if (from == FP_REGS)
9235 if (GR_REG_CLASS_P (to))
9237 else if (to == FP_REGS)
9239 else if (to == ST_REGS)
9242 else if (reg_class_subset_p (from, ACC_REGS))
9244 if (GR_REG_CLASS_P (to))
9252 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9254 else if (COP_REG_CLASS_P (from))
9260 ??? What cases are these? Shouldn't we return 2 here? */
9265 /* Return the length of INSN. LENGTH is the initial length computed by
9266 attributes in the machine-description file. */
9269 mips_adjust_insn_length (rtx insn, int length)
9271 /* A unconditional jump has an unfilled delay slot if it is not part
9272 of a sequence. A conditional jump normally has a delay slot, but
9273 does not on MIPS16. */
9274 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
9277 /* See how many nops might be needed to avoid hardware hazards. */
9278 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
9279 switch (get_attr_hazard (insn))
9293 /* All MIPS16 instructions are a measly two bytes. */
9301 /* Return an asm sequence to start a noat block and load the address
9302 of a label into $1. */
9305 mips_output_load_label (void)
9307 if (TARGET_EXPLICIT_RELOCS)
9311 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9314 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9317 if (ISA_HAS_LOAD_DELAY)
9318 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9319 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9323 if (Pmode == DImode)
9324 return "%[dla\t%@,%0";
9326 return "%[la\t%@,%0";
9330 /* Return the assembly code for INSN, which has the operands given by
9331 OPERANDS, and which branches to OPERANDS[1] if some condition is true.
9332 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[1]
9333 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
9334 version of BRANCH_IF_TRUE. */
9337 mips_output_conditional_branch (rtx insn, rtx *operands,
9338 const char *branch_if_true,
9339 const char *branch_if_false)
9341 unsigned int length;
9342 rtx taken, not_taken;
9344 length = get_attr_length (insn);
9347 /* Just a simple conditional branch. */
9348 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9349 return branch_if_true;
9352 /* Generate a reversed branch around a direct jump. This fallback does
9353 not use branch-likely instructions. */
9354 mips_branch_likely = false;
9355 not_taken = gen_label_rtx ();
9356 taken = operands[1];
9358 /* Generate the reversed branch to NOT_TAKEN. */
9359 operands[1] = not_taken;
9360 output_asm_insn (branch_if_false, operands);
9362 /* If INSN has a delay slot, we must provide delay slots for both the
9363 branch to NOT_TAKEN and the conditional jump. We must also ensure
9364 that INSN's delay slot is executed in the appropriate cases. */
9367 /* This first delay slot will always be executed, so use INSN's
9368 delay slot if is not annulled. */
9369 if (!INSN_ANNULLED_BRANCH_P (insn))
9371 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9372 asm_out_file, optimize, 1, NULL);
9373 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9376 output_asm_insn ("nop", 0);
9377 fprintf (asm_out_file, "\n");
9380 /* Output the unconditional branch to TAKEN. */
9382 output_asm_insn ("j\t%0%/", &taken);
9385 output_asm_insn (mips_output_load_label (), &taken);
9386 output_asm_insn ("jr\t%@%]%/", 0);
9389 /* Now deal with its delay slot; see above. */
9392 /* This delay slot will only be executed if the branch is taken.
9393 Use INSN's delay slot if is annulled. */
9394 if (INSN_ANNULLED_BRANCH_P (insn))
9396 final_scan_insn (XVECEXP (final_sequence, 0, 1),
9397 asm_out_file, optimize, 1, NULL);
9398 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
9401 output_asm_insn ("nop", 0);
9402 fprintf (asm_out_file, "\n");
9405 /* Output NOT_TAKEN. */
9406 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9407 CODE_LABEL_NUMBER (not_taken));
9411 /* Return the assembly code for INSN, which branches to OPERANDS[1]
9412 if some ordered condition is true. The condition is given by
9413 OPERANDS[0] if !INVERTED_P, otherwise it is the inverse of
9414 OPERANDS[0]. OPERANDS[2] is the comparison's first operand;
9415 its second is always zero. */
9418 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
9420 const char *branch[2];
9422 /* Make BRANCH[1] branch to OPERANDS[1] when the condition is true.
9423 Make BRANCH[0] branch on the inverse condition. */
9424 switch (GET_CODE (operands[0]))
9426 /* These cases are equivalent to comparisons against zero. */
9428 inverted_p = !inverted_p;
9431 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%1");
9432 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%1");
9435 /* These cases are always true or always false. */
9437 inverted_p = !inverted_p;
9440 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%1");
9441 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%1");
9445 branch[!inverted_p] = MIPS_BRANCH ("b%C0z", "%2,%1");
9446 branch[inverted_p] = MIPS_BRANCH ("b%N0z", "%2,%1");
9449 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
9452 /* Used to output div or ddiv instruction DIVISION, which has the operands
9453 given by OPERANDS. Add in a divide-by-zero check if needed.
9455 When working around R4000 and R4400 errata, we need to make sure that
9456 the division is not immediately followed by a shift[1][2]. We also
9457 need to stop the division from being put into a branch delay slot[3].
9458 The easiest way to avoid both problems is to add a nop after the
9459 division. When a divide-by-zero check is needed, this nop can be
9460 used to fill the branch delay slot.
9462 [1] If a double-word or a variable shift executes immediately
9463 after starting an integer division, the shift may give an
9464 incorrect result. See quotations of errata #16 and #28 from
9465 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9466 in mips.md for details.
9468 [2] A similar bug to [1] exists for all revisions of the
9469 R4000 and the R4400 when run in an MC configuration.
9470 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9472 "19. In this following sequence:
9474 ddiv (or ddivu or div or divu)
9475 dsll32 (or dsrl32, dsra32)
9477 if an MPT stall occurs, while the divide is slipping the cpu
9478 pipeline, then the following double shift would end up with an
9481 Workaround: The compiler needs to avoid generating any
9482 sequence with divide followed by extended double shift."
9484 This erratum is also present in "MIPS R4400MC Errata, Processor
9485 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9486 & 3.0" as errata #10 and #4, respectively.
9488 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9489 (also valid for MIPS R4000MC processors):
9491 "52. R4000SC: This bug does not apply for the R4000PC.
9493 There are two flavors of this bug:
9495 1) If the instruction just after divide takes an RF exception
9496 (tlb-refill, tlb-invalid) and gets an instruction cache
9497 miss (both primary and secondary) and the line which is
9498 currently in secondary cache at this index had the first
9499 data word, where the bits 5..2 are set, then R4000 would
9500 get a wrong result for the div.
9505 ------------------- # end-of page. -tlb-refill
9510 ------------------- # end-of page. -tlb-invalid
9513 2) If the divide is in the taken branch delay slot, where the
9514 target takes RF exception and gets an I-cache miss for the
9515 exception vector or where I-cache miss occurs for the
9516 target address, under the above mentioned scenarios, the
9517 div would get wrong results.
9520 j r2 # to next page mapped or unmapped
9521 div r8,r9 # this bug would be there as long
9522 # as there is an ICache miss and
9523 nop # the "data pattern" is present
9526 beq r0, r0, NextPage # to Next page
9530 This bug is present for div, divu, ddiv, and ddivu
9533 Workaround: For item 1), OS could make sure that the next page
9534 after the divide instruction is also mapped. For item 2), the
9535 compiler could make sure that the divide instruction is not in
9536 the branch delay slot."
9538 These processors have PRId values of 0x00004220 and 0x00004300 for
9539 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9542 mips_output_division (const char *division, rtx *operands)
9547 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9549 output_asm_insn (s, operands);
9552 if (TARGET_CHECK_ZERO_DIV)
9556 output_asm_insn (s, operands);
9557 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9559 else if (GENERATE_DIVIDE_TRAPS)
9561 output_asm_insn (s, operands);
9566 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9567 output_asm_insn (s, operands);
9568 s = "break\t7%)\n1:";
9574 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9575 with a final "000" replaced by "k". Ignore case.
9577 Note: this function is shared between GCC and GAS. */
9580 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9582 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9583 given++, canonical++;
9585 return ((*given == 0 && *canonical == 0)
9586 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9590 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9591 CPU name. We've traditionally allowed a lot of variation here.
9593 Note: this function is shared between GCC and GAS. */
9596 mips_matching_cpu_name_p (const char *canonical, const char *given)
9598 /* First see if the name matches exactly, or with a final "000"
9600 if (mips_strict_matching_cpu_name_p (canonical, given))
9603 /* If not, try comparing based on numerical designation alone.
9604 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9605 if (TOLOWER (*given) == 'r')
9607 if (!ISDIGIT (*given))
9610 /* Skip over some well-known prefixes in the canonical name,
9611 hoping to find a number there too. */
9612 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9614 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9616 else if (TOLOWER (canonical[0]) == 'r')
9619 return mips_strict_matching_cpu_name_p (canonical, given);
9623 /* Return the mips_cpu_info entry for the processor or ISA given
9624 by CPU_STRING. Return null if the string isn't recognized.
9626 A similar function exists in GAS. */
9628 static const struct mips_cpu_info *
9629 mips_parse_cpu (const char *cpu_string)
9631 const struct mips_cpu_info *p;
9634 /* In the past, we allowed upper-case CPU names, but it doesn't
9635 work well with the multilib machinery. */
9636 for (s = cpu_string; *s != 0; s++)
9639 warning (0, "the cpu name must be lower case");
9643 /* 'from-abi' selects the most compatible architecture for the given
9644 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9645 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9646 version. Look first at the -mgp options, if given, otherwise base
9647 the choice on MASK_64BIT in TARGET_DEFAULT. */
9648 if (strcasecmp (cpu_string, "from-abi") == 0)
9649 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9650 : ABI_NEEDS_64BIT_REGS ? 3
9651 : (TARGET_64BIT ? 3 : 1));
9653 /* 'default' has traditionally been a no-op. Probably not very useful. */
9654 if (strcasecmp (cpu_string, "default") == 0)
9657 for (p = mips_cpu_info_table; p->name != 0; p++)
9658 if (mips_matching_cpu_name_p (p->name, cpu_string))
9665 /* Return the processor associated with the given ISA level, or null
9666 if the ISA isn't valid. */
9668 static const struct mips_cpu_info *
9669 mips_cpu_info_from_isa (int isa)
9671 const struct mips_cpu_info *p;
9673 for (p = mips_cpu_info_table; p->name != 0; p++)
9680 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9681 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9682 they only hold condition code modes, and CCmode is always considered to
9683 be 4 bytes wide. All other registers are word sized. */
9686 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9688 if (ST_REG_P (regno))
9689 return ((GET_MODE_SIZE (mode) + 3) / 4);
9690 else if (! FP_REG_P (regno))
9691 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9693 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9696 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9697 all BLKmode objects are returned in memory. Under the new (N32 and
9698 64-bit MIPS ABIs) small structures are returned in a register.
9699 Objects with varying size must still be returned in memory, of
9703 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9706 return (TYPE_MODE (type) == BLKmode);
9708 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9709 || (int_size_in_bytes (type) == -1));
9713 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9715 return !TARGET_OLDABI;
9718 /* Return true if INSN is a multiply-add or multiply-subtract
9719 instruction and PREV assigns to the accumulator operand. */
9722 mips_linked_madd_p (rtx prev, rtx insn)
9726 x = single_set (insn);
9732 if (GET_CODE (x) == PLUS
9733 && GET_CODE (XEXP (x, 0)) == MULT
9734 && reg_set_p (XEXP (x, 1), prev))
9737 if (GET_CODE (x) == MINUS
9738 && GET_CODE (XEXP (x, 1)) == MULT
9739 && reg_set_p (XEXP (x, 0), prev))
9745 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9746 that may clobber hi or lo. */
9748 static rtx mips_macc_chains_last_hilo;
9750 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9751 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9754 mips_macc_chains_record (rtx insn)
9756 if (get_attr_may_clobber_hilo (insn))
9757 mips_macc_chains_last_hilo = insn;
9760 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9761 has NREADY elements, looking for a multiply-add or multiply-subtract
9762 instruction that is cumulative with mips_macc_chains_last_hilo.
9763 If there is one, promote it ahead of anything else that might
9764 clobber hi or lo. */
9767 mips_macc_chains_reorder (rtx *ready, int nready)
9771 if (mips_macc_chains_last_hilo != 0)
9772 for (i = nready - 1; i >= 0; i--)
9773 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9775 for (j = nready - 1; j > i; j--)
9776 if (recog_memoized (ready[j]) >= 0
9777 && get_attr_may_clobber_hilo (ready[j]))
9779 mips_promote_ready (ready, i, j);
9786 /* The last instruction to be scheduled. */
9788 static rtx vr4130_last_insn;
9790 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9791 points to an rtx that is initially an instruction. Nullify the rtx
9792 if the instruction uses the value of register X. */
9795 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9797 rtx *insn_ptr = data;
9800 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9804 /* Return true if there is true register dependence between vr4130_last_insn
9808 vr4130_true_reg_dependence_p (rtx insn)
9810 note_stores (PATTERN (vr4130_last_insn),
9811 vr4130_true_reg_dependence_p_1, &insn);
9815 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9816 the ready queue and that INSN2 is the instruction after it, return
9817 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9818 in which INSN1 and INSN2 can probably issue in parallel, but for
9819 which (INSN2, INSN1) should be less sensitive to instruction
9820 alignment than (INSN1, INSN2). See 4130.md for more details. */
9823 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9827 /* Check for the following case:
9829 1) there is some other instruction X with an anti dependence on INSN1;
9830 2) X has a higher priority than INSN2; and
9831 3) X is an arithmetic instruction (and thus has no unit restrictions).
9833 If INSN1 is the last instruction blocking X, it would better to
9834 choose (INSN1, X) over (INSN2, INSN1). */
9835 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9836 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9837 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9838 && recog_memoized (XEXP (dep, 0)) >= 0
9839 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9842 if (vr4130_last_insn != 0
9843 && recog_memoized (insn1) >= 0
9844 && recog_memoized (insn2) >= 0)
9846 /* See whether INSN1 and INSN2 use different execution units,
9847 or if they are both ALU-type instructions. If so, they can
9848 probably execute in parallel. */
9849 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9850 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9851 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9853 /* If only one of the instructions has a dependence on
9854 vr4130_last_insn, prefer to schedule the other one first. */
9855 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9856 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9860 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9861 is not an ALU-type instruction and if INSN1 uses the same
9862 execution unit. (Note that if this condition holds, we already
9863 know that INSN2 uses a different execution unit.) */
9864 if (class1 != VR4130_CLASS_ALU
9865 && recog_memoized (vr4130_last_insn) >= 0
9866 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9873 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9874 queue with at least two instructions. Swap the first two if
9875 vr4130_swap_insns_p says that it could be worthwhile. */
9878 vr4130_reorder (rtx *ready, int nready)
9880 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9881 mips_promote_ready (ready, nready - 2, nready - 1);
9884 /* Remove the instruction at index LOWER from ready queue READY and
9885 reinsert it in front of the instruction at index HIGHER. LOWER must
9889 mips_promote_ready (rtx *ready, int lower, int higher)
9894 new_head = ready[lower];
9895 for (i = lower; i < higher; i++)
9896 ready[i] = ready[i + 1];
9897 ready[i] = new_head;
9900 /* Implement TARGET_SCHED_REORDER. */
9903 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9904 rtx *ready, int *nreadyp, int cycle)
9906 if (!reload_completed && TUNE_MACC_CHAINS)
9909 mips_macc_chains_last_hilo = 0;
9911 mips_macc_chains_reorder (ready, *nreadyp);
9913 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9916 vr4130_last_insn = 0;
9918 vr4130_reorder (ready, *nreadyp);
9920 return mips_issue_rate ();
9923 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9926 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9929 switch (GET_CODE (PATTERN (insn)))
9933 /* Don't count USEs and CLOBBERs against the issue rate. */
9938 if (!reload_completed && TUNE_MACC_CHAINS)
9939 mips_macc_chains_record (insn);
9940 vr4130_last_insn = insn;
9946 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9947 dependencies have no cost. */
9950 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9951 rtx dep ATTRIBUTE_UNUSED, int cost)
9953 if (REG_NOTE_KIND (link) != 0)
9958 /* Return the number of instructions that can be issued per cycle. */
9961 mips_issue_rate (void)
9965 case PROCESSOR_R4130:
9966 case PROCESSOR_R5400:
9967 case PROCESSOR_R5500:
9968 case PROCESSOR_R7000:
9969 case PROCESSOR_R9000:
9973 case PROCESSOR_SB1A:
9974 /* This is actually 4, but we get better performance if we claim 3.
9975 This is partly because of unwanted speculative code motion with the
9976 larger number, and partly because in most common cases we can't
9977 reach the theoretical max of 4. */
9985 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9986 be as wide as the scheduling freedom in the DFA. */
9989 mips_multipass_dfa_lookahead (void)
9991 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9998 /* Implements a store data bypass check. We need this because the cprestore
9999 pattern is type store, but defined using an UNSPEC. This UNSPEC causes the
10000 default routine to abort. We just return false for that case. */
10001 /* ??? Should try to give a better result here than assuming false. */
10004 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
10006 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
10009 return ! store_data_bypass_p (out_insn, in_insn);
10012 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
10013 return the first operand of the associated "pref" or "prefx" insn. */
10016 mips_prefetch_cookie (rtx write, rtx locality)
10018 /* store_streamed / load_streamed. */
10019 if (INTVAL (locality) <= 0)
10020 return GEN_INT (INTVAL (write) + 4);
10022 /* store / load. */
10023 if (INTVAL (locality) <= 2)
10026 /* store_retained / load_retained. */
10027 return GEN_INT (INTVAL (write) + 6);
10030 /* MIPS builtin function support. */
10032 struct builtin_description
10034 /* The code of the main .md file instruction. See mips_builtin_type
10035 for more information. */
10036 enum insn_code icode;
10038 /* The floating-point comparison code to use with ICODE, if any. */
10039 enum mips_fp_condition cond;
10041 /* The name of the builtin function. */
10044 /* Specifies how the function should be expanded. */
10045 enum mips_builtin_type builtin_type;
10047 /* The function's prototype. */
10048 enum mips_function_type function_type;
10050 /* The target flags required for this function. */
10054 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
10055 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
10056 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10057 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10058 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
10060 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
10062 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
10063 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
10064 "__builtin_mips_" #INSN "_" #COND "_s", \
10065 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
10066 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
10067 "__builtin_mips_" #INSN "_" #COND "_d", \
10068 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
10070 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
10071 The lower and upper forms require TARGET_FLAGS while the any and all
10072 forms require MASK_MIPS3D. */
10073 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
10074 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10075 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
10076 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10077 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10078 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
10079 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
10080 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10081 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
10082 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
10083 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10084 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
10085 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
10087 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
10088 require MASK_MIPS3D. */
10089 #define CMP_4S_BUILTINS(INSN, COND) \
10090 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10091 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
10092 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10094 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
10095 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
10096 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10099 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
10100 instruction requires TARGET_FLAGS. */
10101 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
10102 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10103 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
10104 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10106 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
10107 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
10108 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
10111 /* Define all the builtins related to c.cond.fmt condition COND. */
10112 #define CMP_BUILTINS(COND) \
10113 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10114 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
10115 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
10116 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE_FLOAT), \
10117 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
10118 CMP_4S_BUILTINS (c, COND), \
10119 CMP_4S_BUILTINS (cabs, COND)
10121 static const struct builtin_description mips_bdesc[] =
10123 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10124 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10125 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10126 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10127 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE_FLOAT),
10128 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10129 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10130 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT),
10132 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
10133 MASK_PAIRED_SINGLE_FLOAT),
10134 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10135 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10136 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10137 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10139 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10140 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10141 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10142 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10143 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10144 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10146 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
10147 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
10148 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
10149 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
10150 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
10151 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
10153 MIPS_FP_CONDITIONS (CMP_BUILTINS)
10156 /* Builtin functions for the SB-1 processor. */
10158 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
10160 static const struct builtin_description sb1_bdesc[] =
10162 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE_FLOAT)
10165 /* Builtin functions for DSP ASE. */
10167 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
10168 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
10169 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
10170 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
10172 /* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
10173 CODE_FOR_mips_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
10174 builtin_description fields. */
10175 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
10176 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
10177 MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, TARGET_FLAGS }
10179 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
10180 branch instruction. TARGET_FLAGS is a builtin_description field. */
10181 #define BPOSGE_BUILTIN(VALUE, TARGET_FLAGS) \
10182 { CODE_FOR_mips_bposge, 0, "__builtin_mips_bposge" #VALUE, \
10183 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, TARGET_FLAGS }
10185 static const struct builtin_description dsp_bdesc[] =
10187 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10188 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10189 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10190 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10191 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10192 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10193 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10194 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10195 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10196 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10197 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10198 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10199 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10200 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, MASK_DSP),
10201 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, MASK_DSP),
10202 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, MASK_DSP),
10203 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10204 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10205 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, MASK_DSP),
10206 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, MASK_DSP),
10207 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10208 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, MASK_DSP),
10209 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10210 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10211 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10212 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10213 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10214 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10215 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10216 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, MASK_DSP),
10217 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10218 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10219 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10220 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10221 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, MASK_DSP),
10222 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10223 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, MASK_DSP),
10224 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10225 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10226 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, MASK_DSP),
10227 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10228 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10229 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, MASK_DSP),
10230 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10231 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10232 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10233 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, MASK_DSP),
10234 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10235 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10236 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10237 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10238 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, MASK_DSP),
10239 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10240 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10241 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10242 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, MASK_DSP),
10243 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, MASK_DSP),
10244 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, MASK_DSP),
10245 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, MASK_DSP),
10246 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, MASK_DSP),
10247 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10248 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10249 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, MASK_DSP),
10250 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10251 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10252 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, MASK_DSP),
10253 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10254 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10255 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, MASK_DSP),
10256 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, MASK_DSP),
10257 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10258 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, MASK_DSP),
10259 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10260 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10261 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10262 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10263 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10264 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, MASK_DSP),
10265 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10266 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, MASK_DSP),
10267 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, MASK_DSP),
10268 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, MASK_DSP),
10269 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10270 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10271 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_PTR_SI, MASK_DSP),
10272 BPOSGE_BUILTIN (32, MASK_DSP)
10275 /* This helps provide a mapping from builtin function codes to bdesc
10280 /* The builtin function table that this entry describes. */
10281 const struct builtin_description *bdesc;
10283 /* The number of entries in the builtin function table. */
10286 /* The target processor that supports these builtin functions.
10287 PROCESSOR_MAX means we enable them for all processors. */
10288 enum processor_type proc;
10291 static const struct bdesc_map bdesc_arrays[] =
10293 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_MAX },
10294 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 },
10295 { dsp_bdesc, ARRAY_SIZE (dsp_bdesc), PROCESSOR_MAX }
10298 /* Take the head of argument list *ARGLIST and convert it into a form
10299 suitable for input operand OP of instruction ICODE. Return the value
10300 and point *ARGLIST at the next element of the list. */
10303 mips_prepare_builtin_arg (enum insn_code icode,
10304 unsigned int op, tree *arglist)
10307 enum machine_mode mode;
10309 value = expand_normal (TREE_VALUE (*arglist));
10310 mode = insn_data[icode].operand[op].mode;
10311 if (!insn_data[icode].operand[op].predicate (value, mode))
10313 value = copy_to_mode_reg (mode, value);
10314 /* Check the predicate again. */
10315 if (!insn_data[icode].operand[op].predicate (value, mode))
10317 error ("invalid argument to builtin function");
10322 *arglist = TREE_CHAIN (*arglist);
10326 /* Return an rtx suitable for output operand OP of instruction ICODE.
10327 If TARGET is non-null, try to use it where possible. */
10330 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
10332 enum machine_mode mode;
10334 mode = insn_data[icode].operand[op].mode;
10335 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
10336 target = gen_reg_rtx (mode);
10341 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
10344 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10345 enum machine_mode mode ATTRIBUTE_UNUSED,
10346 int ignore ATTRIBUTE_UNUSED)
10348 enum insn_code icode;
10349 enum mips_builtin_type type;
10350 tree fndecl, arglist;
10351 unsigned int fcode;
10352 const struct builtin_description *bdesc;
10353 const struct bdesc_map *m;
10355 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
10356 arglist = TREE_OPERAND (exp, 1);
10357 fcode = DECL_FUNCTION_CODE (fndecl);
10360 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10362 if (fcode < m->size)
10365 icode = bdesc[fcode].icode;
10366 type = bdesc[fcode].builtin_type;
10376 case MIPS_BUILTIN_DIRECT:
10377 return mips_expand_builtin_direct (icode, target, arglist, true);
10379 case MIPS_BUILTIN_DIRECT_NO_TARGET:
10380 return mips_expand_builtin_direct (icode, target, arglist, false);
10382 case MIPS_BUILTIN_MOVT:
10383 case MIPS_BUILTIN_MOVF:
10384 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
10387 case MIPS_BUILTIN_CMP_ANY:
10388 case MIPS_BUILTIN_CMP_ALL:
10389 case MIPS_BUILTIN_CMP_UPPER:
10390 case MIPS_BUILTIN_CMP_LOWER:
10391 case MIPS_BUILTIN_CMP_SINGLE:
10392 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
10395 case MIPS_BUILTIN_BPOSGE32:
10396 return mips_expand_builtin_bposge (type, target);
10403 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
10406 mips_init_builtins (void)
10408 const struct builtin_description *d;
10409 const struct bdesc_map *m;
10410 tree types[(int) MIPS_MAX_FTYPE_MAX];
10411 tree V2SF_type_node;
10412 tree V2HI_type_node;
10413 tree V4QI_type_node;
10414 unsigned int offset;
10416 /* We have only builtins for -mpaired-single, -mips3d and -mdsp. */
10417 if (!TARGET_PAIRED_SINGLE_FLOAT && !TARGET_DSP)
10420 if (TARGET_PAIRED_SINGLE_FLOAT)
10422 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
10424 types[MIPS_V2SF_FTYPE_V2SF]
10425 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
10427 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
10428 = build_function_type_list (V2SF_type_node,
10429 V2SF_type_node, V2SF_type_node, NULL_TREE);
10431 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
10432 = build_function_type_list (V2SF_type_node,
10433 V2SF_type_node, V2SF_type_node,
10434 integer_type_node, NULL_TREE);
10436 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
10437 = build_function_type_list (V2SF_type_node,
10438 V2SF_type_node, V2SF_type_node,
10439 V2SF_type_node, V2SF_type_node, NULL_TREE);
10441 types[MIPS_V2SF_FTYPE_SF_SF]
10442 = build_function_type_list (V2SF_type_node,
10443 float_type_node, float_type_node, NULL_TREE);
10445 types[MIPS_INT_FTYPE_V2SF_V2SF]
10446 = build_function_type_list (integer_type_node,
10447 V2SF_type_node, V2SF_type_node, NULL_TREE);
10449 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
10450 = build_function_type_list (integer_type_node,
10451 V2SF_type_node, V2SF_type_node,
10452 V2SF_type_node, V2SF_type_node, NULL_TREE);
10454 types[MIPS_INT_FTYPE_SF_SF]
10455 = build_function_type_list (integer_type_node,
10456 float_type_node, float_type_node, NULL_TREE);
10458 types[MIPS_INT_FTYPE_DF_DF]
10459 = build_function_type_list (integer_type_node,
10460 double_type_node, double_type_node, NULL_TREE);
10462 types[MIPS_SF_FTYPE_V2SF]
10463 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
10465 types[MIPS_SF_FTYPE_SF]
10466 = build_function_type_list (float_type_node,
10467 float_type_node, NULL_TREE);
10469 types[MIPS_SF_FTYPE_SF_SF]
10470 = build_function_type_list (float_type_node,
10471 float_type_node, float_type_node, NULL_TREE);
10473 types[MIPS_DF_FTYPE_DF]
10474 = build_function_type_list (double_type_node,
10475 double_type_node, NULL_TREE);
10477 types[MIPS_DF_FTYPE_DF_DF]
10478 = build_function_type_list (double_type_node,
10479 double_type_node, double_type_node, NULL_TREE);
10484 V2HI_type_node = build_vector_type_for_mode (intHI_type_node, V2HImode);
10485 V4QI_type_node = build_vector_type_for_mode (intQI_type_node, V4QImode);
10487 types[MIPS_V2HI_FTYPE_V2HI_V2HI]
10488 = build_function_type_list (V2HI_type_node,
10489 V2HI_type_node, V2HI_type_node,
10492 types[MIPS_SI_FTYPE_SI_SI]
10493 = build_function_type_list (intSI_type_node,
10494 intSI_type_node, intSI_type_node,
10497 types[MIPS_V4QI_FTYPE_V4QI_V4QI]
10498 = build_function_type_list (V4QI_type_node,
10499 V4QI_type_node, V4QI_type_node,
10502 types[MIPS_SI_FTYPE_V4QI]
10503 = build_function_type_list (intSI_type_node,
10507 types[MIPS_V2HI_FTYPE_V2HI]
10508 = build_function_type_list (V2HI_type_node,
10512 types[MIPS_SI_FTYPE_SI]
10513 = build_function_type_list (intSI_type_node,
10517 types[MIPS_V4QI_FTYPE_V2HI_V2HI]
10518 = build_function_type_list (V4QI_type_node,
10519 V2HI_type_node, V2HI_type_node,
10522 types[MIPS_V2HI_FTYPE_SI_SI]
10523 = build_function_type_list (V2HI_type_node,
10524 intSI_type_node, intSI_type_node,
10527 types[MIPS_SI_FTYPE_V2HI]
10528 = build_function_type_list (intSI_type_node,
10532 types[MIPS_V2HI_FTYPE_V4QI]
10533 = build_function_type_list (V2HI_type_node,
10537 types[MIPS_V4QI_FTYPE_V4QI_SI]
10538 = build_function_type_list (V4QI_type_node,
10539 V4QI_type_node, intSI_type_node,
10542 types[MIPS_V2HI_FTYPE_V2HI_SI]
10543 = build_function_type_list (V2HI_type_node,
10544 V2HI_type_node, intSI_type_node,
10547 types[MIPS_V2HI_FTYPE_V4QI_V2HI]
10548 = build_function_type_list (V2HI_type_node,
10549 V4QI_type_node, V2HI_type_node,
10552 types[MIPS_SI_FTYPE_V2HI_V2HI]
10553 = build_function_type_list (intSI_type_node,
10554 V2HI_type_node, V2HI_type_node,
10557 types[MIPS_DI_FTYPE_DI_V4QI_V4QI]
10558 = build_function_type_list (intDI_type_node,
10559 intDI_type_node, V4QI_type_node, V4QI_type_node,
10562 types[MIPS_DI_FTYPE_DI_V2HI_V2HI]
10563 = build_function_type_list (intDI_type_node,
10564 intDI_type_node, V2HI_type_node, V2HI_type_node,
10567 types[MIPS_DI_FTYPE_DI_SI_SI]
10568 = build_function_type_list (intDI_type_node,
10569 intDI_type_node, intSI_type_node, intSI_type_node,
10572 types[MIPS_V4QI_FTYPE_SI]
10573 = build_function_type_list (V4QI_type_node,
10577 types[MIPS_V2HI_FTYPE_SI]
10578 = build_function_type_list (V2HI_type_node,
10582 types[MIPS_VOID_FTYPE_V4QI_V4QI]
10583 = build_function_type_list (void_type_node,
10584 V4QI_type_node, V4QI_type_node,
10587 types[MIPS_SI_FTYPE_V4QI_V4QI]
10588 = build_function_type_list (intSI_type_node,
10589 V4QI_type_node, V4QI_type_node,
10592 types[MIPS_VOID_FTYPE_V2HI_V2HI]
10593 = build_function_type_list (void_type_node,
10594 V2HI_type_node, V2HI_type_node,
10597 types[MIPS_SI_FTYPE_DI_SI]
10598 = build_function_type_list (intSI_type_node,
10599 intDI_type_node, intSI_type_node,
10602 types[MIPS_DI_FTYPE_DI_SI]
10603 = build_function_type_list (intDI_type_node,
10604 intDI_type_node, intSI_type_node,
10607 types[MIPS_VOID_FTYPE_SI_SI]
10608 = build_function_type_list (void_type_node,
10609 intSI_type_node, intSI_type_node,
10612 types[MIPS_SI_FTYPE_PTR_SI]
10613 = build_function_type_list (intSI_type_node,
10614 ptr_type_node, intSI_type_node,
10617 types[MIPS_SI_FTYPE_VOID]
10618 = build_function_type (intSI_type_node, void_list_node);
10621 /* Iterate through all of the bdesc arrays, initializing all of the
10622 builtin functions. */
10625 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
10627 if (m->proc == PROCESSOR_MAX || (m->proc == mips_arch))
10628 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
10629 if ((d->target_flags & target_flags) == d->target_flags)
10630 add_builtin_function (d->name, types[d->function_type],
10631 d - m->bdesc + offset,
10632 BUILT_IN_MD, NULL, NULL);
10637 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
10638 .md pattern and ARGLIST is the list of function arguments. TARGET,
10639 if nonnull, suggests a good place to put the result.
10640 HAS_TARGET indicates the function must return something. */
10643 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist,
10646 rtx ops[MAX_RECOG_OPERANDS];
10651 /* We save target to ops[0]. */
10652 ops[0] = mips_prepare_builtin_target (icode, 0, target);
10656 /* We need to test if arglist is not zero. Some instructions have extra
10657 clobber registers. */
10658 for (; i < insn_data[icode].n_operands && arglist != 0; i++)
10659 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10664 emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
10668 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
10672 emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
10676 gcc_unreachable ();
10681 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
10682 function (TYPE says which). ARGLIST is the list of arguments to the
10683 function, ICODE is the instruction that should be used to compare
10684 the first two arguments, and COND is the condition it should test.
10685 TARGET, if nonnull, suggests a good place to put the result. */
10688 mips_expand_builtin_movtf (enum mips_builtin_type type,
10689 enum insn_code icode, enum mips_fp_condition cond,
10690 rtx target, tree arglist)
10692 rtx cmp_result, op0, op1;
10694 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10695 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10696 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10697 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
10699 icode = CODE_FOR_mips_cond_move_tf_ps;
10700 target = mips_prepare_builtin_target (icode, 0, target);
10701 if (type == MIPS_BUILTIN_MOVT)
10703 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10704 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10708 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
10709 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
10711 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
10715 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
10716 into TARGET otherwise. Return TARGET. */
10719 mips_builtin_branch_and_move (rtx condition, rtx target,
10720 rtx value_if_true, rtx value_if_false)
10722 rtx true_label, done_label;
10724 true_label = gen_label_rtx ();
10725 done_label = gen_label_rtx ();
10727 /* First assume that CONDITION is false. */
10728 emit_move_insn (target, value_if_false);
10730 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
10731 emit_jump_insn (gen_condjump (condition, true_label));
10732 emit_jump_insn (gen_jump (done_label));
10735 /* Fix TARGET if CONDITION is true. */
10736 emit_label (true_label);
10737 emit_move_insn (target, value_if_true);
10739 emit_label (done_label);
10743 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
10744 of the comparison instruction and COND is the condition it should test.
10745 ARGLIST is the list of function arguments and TARGET, if nonnull,
10746 suggests a good place to put the boolean result. */
10749 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
10750 enum insn_code icode, enum mips_fp_condition cond,
10751 rtx target, tree arglist)
10753 rtx offset, condition, cmp_result, ops[MAX_RECOG_OPERANDS];
10756 if (target == 0 || GET_MODE (target) != SImode)
10757 target = gen_reg_rtx (SImode);
10759 /* Prepare the operands to the comparison. */
10760 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
10761 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
10762 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
10764 switch (insn_data[icode].n_operands)
10767 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond)));
10771 emit_insn (GEN_FCN (icode) (cmp_result, ops[1], ops[2],
10772 ops[3], ops[4], GEN_INT (cond)));
10776 gcc_unreachable ();
10779 /* If the comparison sets more than one register, we define the result
10780 to be 0 if all registers are false and -1 if all registers are true.
10781 The value of the complete result is indeterminate otherwise. */
10782 switch (builtin_type)
10784 case MIPS_BUILTIN_CMP_ALL:
10785 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
10786 return mips_builtin_branch_and_move (condition, target,
10787 const0_rtx, const1_rtx);
10789 case MIPS_BUILTIN_CMP_UPPER:
10790 case MIPS_BUILTIN_CMP_LOWER:
10791 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
10792 condition = gen_single_cc (cmp_result, offset);
10793 return mips_builtin_branch_and_move (condition, target,
10794 const1_rtx, const0_rtx);
10797 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
10798 return mips_builtin_branch_and_move (condition, target,
10799 const1_rtx, const0_rtx);
10803 /* Expand a bposge builtin of type BUILTIN_TYPE. TARGET, if nonnull,
10804 suggests a good place to put the boolean result. */
10807 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
10809 rtx condition, cmp_result;
10812 if (target == 0 || GET_MODE (target) != SImode)
10813 target = gen_reg_rtx (SImode);
10815 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
10817 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
10822 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
10823 return mips_builtin_branch_and_move (condition, target,
10824 const1_rtx, const0_rtx);
10827 /* Set SYMBOL_REF_FLAGS for the SYMBOL_REF inside RTL, which belongs to DECL.
10828 FIRST is true if this is the first time handling this decl. */
10831 mips_encode_section_info (tree decl, rtx rtl, int first)
10833 default_encode_section_info (decl, rtl, first);
10835 if (TREE_CODE (decl) == FUNCTION_DECL
10836 && lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
10838 rtx symbol = XEXP (rtl, 0);
10839 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
10843 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. PIC_FUNCTION_ADDR_REGNUM is live
10844 on entry to a function when generating -mshared abicalls code. */
10847 mips_extra_live_on_entry (bitmap regs)
10849 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
10850 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10853 /* SImode values are represented as sign-extended to DImode. */
10856 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
10858 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
10859 return SIGN_EXTEND;
10864 #include "gt-mips.h"