1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
63 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
64 #define UNSPEC_ADDRESS_P(X) \
65 (GET_CODE (X) == UNSPEC \
66 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
67 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
69 /* Extract the symbol or label from UNSPEC wrapper X. */
70 #define UNSPEC_ADDRESS(X) \
73 /* Extract the symbol type from UNSPEC wrapper X. */
74 #define UNSPEC_ADDRESS_TYPE(X) \
75 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
77 /* The maximum distance between the top of the stack frame and the
78 value $sp has when we save and restore registers.
80 The value for normal-mode code must be a SMALL_OPERAND and must
81 preserve the maximum stack alignment. We therefore use a value
82 of 0x7ff0 in this case.
84 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
85 up to 0x7f8 bytes and can usually save or restore all the registers
86 that we need to save or restore. (Note that we can only use these
87 instructions for o32, for which the stack alignment is 8 bytes.)
89 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
90 RESTORE are not available. We can then use unextended instructions
91 to save and restore registers, and to allocate and deallocate the top
93 #define MIPS_MAX_FIRST_STACK_STEP \
94 (!TARGET_MIPS16 ? 0x7ff0 \
95 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
96 : TARGET_64BIT ? 0x100 : 0x400)
98 /* True if INSN is a mips.md pattern or asm statement. */
99 #define USEFUL_INSN_P(INSN) \
100 (NONDEBUG_INSN_P (INSN) \
101 && GET_CODE (PATTERN (INSN)) != USE \
102 && GET_CODE (PATTERN (INSN)) != CLOBBER \
103 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
104 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
106 /* If INSN is a delayed branch sequence, return the first instruction
107 in the sequence, otherwise return INSN itself. */
108 #define SEQ_BEGIN(INSN) \
109 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
110 ? XVECEXP (PATTERN (INSN), 0, 0) \
113 /* Likewise for the last instruction in a delayed branch sequence. */
114 #define SEQ_END(INSN) \
115 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
116 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
119 /* Execute the following loop body with SUBINSN set to each instruction
120 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
121 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
122 for ((SUBINSN) = SEQ_BEGIN (INSN); \
123 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
124 (SUBINSN) = NEXT_INSN (SUBINSN))
126 /* True if bit BIT is set in VALUE. */
127 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
129 /* Return the opcode for a ptr_mode load of the form:
131 l[wd] DEST, OFFSET(BASE). */
132 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
133 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
138 /* Return the opcode to move register SRC into register DEST. */
139 #define MIPS_MOVE(DEST, SRC) \
140 ((TARGET_64BIT ? 0x2d : 0x21) \
144 /* Return the opcode for:
147 #define MIPS_LUI(DEST, VALUE) \
148 ((0xf << 26) | ((DEST) << 16) | (VALUE))
150 /* Return the opcode to jump to register DEST. */
151 #define MIPS_JR(DEST) \
152 (((DEST) << 21) | 0x8)
154 /* Return the opcode for:
156 bal . + (1 + OFFSET) * 4. */
157 #define MIPS_BAL(OFFSET) \
158 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
160 /* Return the usual opcode for a nop. */
163 /* Classifies an address.
166 A natural register + offset address. The register satisfies
167 mips_valid_base_register_p and the offset is a const_arith_operand.
170 A LO_SUM rtx. The first operand is a valid base register and
171 the second operand is a symbolic address.
174 A signed 16-bit constant address.
177 A constant symbolic address. */
178 enum mips_address_type {
185 /* Enumerates the setting of the -mr10k-cache-barrier option. */
186 enum mips_r10k_cache_barrier_setting {
187 R10K_CACHE_BARRIER_NONE,
188 R10K_CACHE_BARRIER_STORE,
189 R10K_CACHE_BARRIER_LOAD_STORE
192 /* Macros to create an enumeration identifier for a function prototype. */
193 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
194 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
195 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
196 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
198 /* Classifies the prototype of a built-in function. */
199 enum mips_function_type {
200 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
201 #include "config/mips/mips-ftypes.def"
202 #undef DEF_MIPS_FTYPE
206 /* Specifies how a built-in function should be converted into rtl. */
207 enum mips_builtin_type {
208 /* The function corresponds directly to an .md pattern. The return
209 value is mapped to operand 0 and the arguments are mapped to
210 operands 1 and above. */
213 /* The function corresponds directly to an .md pattern. There is no return
214 value and the arguments are mapped to operands 0 and above. */
215 MIPS_BUILTIN_DIRECT_NO_TARGET,
217 /* The function corresponds to a comparison instruction followed by
218 a mips_cond_move_tf_ps pattern. The first two arguments are the
219 values to compare and the second two arguments are the vector
220 operands for the movt.ps or movf.ps instruction (in assembly order). */
224 /* The function corresponds to a V2SF comparison instruction. Operand 0
225 of this instruction is the result of the comparison, which has mode
226 CCV2 or CCV4. The function arguments are mapped to operands 1 and
227 above. The function's return value is an SImode boolean that is
228 true under the following conditions:
230 MIPS_BUILTIN_CMP_ANY: one of the registers is true
231 MIPS_BUILTIN_CMP_ALL: all of the registers are true
232 MIPS_BUILTIN_CMP_LOWER: the first register is true
233 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
234 MIPS_BUILTIN_CMP_ANY,
235 MIPS_BUILTIN_CMP_ALL,
236 MIPS_BUILTIN_CMP_UPPER,
237 MIPS_BUILTIN_CMP_LOWER,
239 /* As above, but the instruction only sets a single $fcc register. */
240 MIPS_BUILTIN_CMP_SINGLE,
242 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
243 MIPS_BUILTIN_BPOSGE32
246 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
247 #define MIPS_FP_CONDITIONS(MACRO) \
265 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
266 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
267 enum mips_fp_condition {
268 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
271 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
272 #define STRINGIFY(X) #X
273 static const char *const mips_fp_conditions[] = {
274 MIPS_FP_CONDITIONS (STRINGIFY)
277 /* Information about a function's frame layout. */
278 struct GTY(()) mips_frame_info {
279 /* The size of the frame in bytes. */
280 HOST_WIDE_INT total_size;
282 /* The number of bytes allocated to variables. */
283 HOST_WIDE_INT var_size;
285 /* The number of bytes allocated to outgoing function arguments. */
286 HOST_WIDE_INT args_size;
288 /* The number of bytes allocated to the .cprestore slot, or 0 if there
290 HOST_WIDE_INT cprestore_size;
292 /* Bit X is set if the function saves or restores GPR X. */
295 /* Likewise FPR X. */
298 /* Likewise doubleword accumulator X ($acX). */
299 unsigned int acc_mask;
301 /* The number of GPRs, FPRs, doubleword accumulators and COP0
305 unsigned int num_acc;
306 unsigned int num_cop0_regs;
308 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
309 save slots from the top of the frame, or zero if no such slots are
311 HOST_WIDE_INT gp_save_offset;
312 HOST_WIDE_INT fp_save_offset;
313 HOST_WIDE_INT acc_save_offset;
314 HOST_WIDE_INT cop0_save_offset;
316 /* Likewise, but giving offsets from the bottom of the frame. */
317 HOST_WIDE_INT gp_sp_offset;
318 HOST_WIDE_INT fp_sp_offset;
319 HOST_WIDE_INT acc_sp_offset;
320 HOST_WIDE_INT cop0_sp_offset;
322 /* Similar, but the value passed to _mcount. */
323 HOST_WIDE_INT ra_fp_offset;
325 /* The offset of arg_pointer_rtx from the bottom of the frame. */
326 HOST_WIDE_INT arg_pointer_offset;
328 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
329 HOST_WIDE_INT hard_frame_pointer_offset;
332 struct GTY(()) machine_function {
333 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
334 rtx mips16_gp_pseudo_rtx;
336 /* The number of extra stack bytes taken up by register varargs.
337 This area is allocated by the callee at the very top of the frame. */
340 /* The current frame information, calculated by mips_compute_frame_info. */
341 struct mips_frame_info frame;
343 /* The register to use as the function's global pointer, or INVALID_REGNUM
344 if the function doesn't need one. */
345 unsigned int global_pointer;
347 /* How many instructions it takes to load a label into $AT, or 0 if
348 this property hasn't yet been calculated. */
349 unsigned int load_label_num_insns;
351 /* True if mips_adjust_insn_length should ignore an instruction's
353 bool ignore_hazard_length_p;
355 /* True if the whole function is suitable for .set noreorder and
357 bool all_noreorder_p;
359 /* True if the function has "inflexible" and "flexible" references
360 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
361 and mips_cfun_has_flexible_gp_ref_p for details. */
362 bool has_inflexible_gp_insn_p;
363 bool has_flexible_gp_insn_p;
365 /* True if the function's prologue must load the global pointer
366 value into pic_offset_table_rtx and store the same value in
367 the function's cprestore slot (if any). Even if this value
368 is currently false, we may decide to set it to true later;
369 see mips_must_initialize_gp_p () for details. */
370 bool must_initialize_gp_p;
372 /* True if the current function must restore $gp after any potential
373 clobber. This value is only meaningful during the first post-epilogue
374 split_insns pass; see mips_must_initialize_gp_p () for details. */
375 bool must_restore_gp_when_clobbered_p;
377 /* True if this is an interrupt handler. */
378 bool interrupt_handler_p;
380 /* True if this is an interrupt handler that uses shadow registers. */
381 bool use_shadow_register_set_p;
383 /* True if this is an interrupt handler that should keep interrupts
385 bool keep_interrupts_masked_p;
387 /* True if this is an interrupt handler that should use DERET
389 bool use_debug_exception_return_p;
392 /* Information about a single argument. */
393 struct mips_arg_info {
394 /* True if the argument is passed in a floating-point register, or
395 would have been if we hadn't run out of registers. */
398 /* The number of words passed in registers, rounded up. */
399 unsigned int reg_words;
401 /* For EABI, the offset of the first register from GP_ARG_FIRST or
402 FP_ARG_FIRST. For other ABIs, the offset of the first register from
403 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
404 comment for details).
406 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
408 unsigned int reg_offset;
410 /* The number of words that must be passed on the stack, rounded up. */
411 unsigned int stack_words;
413 /* The offset from the start of the stack overflow area of the argument's
414 first stack word. Only meaningful when STACK_WORDS is nonzero. */
415 unsigned int stack_offset;
418 /* Information about an address described by mips_address_type.
424 REG is the base register and OFFSET is the constant offset.
427 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
428 is the type of symbol it references.
431 SYMBOL_TYPE is the type of symbol that the address references. */
432 struct mips_address_info {
433 enum mips_address_type type;
436 enum mips_symbol_type symbol_type;
439 /* One stage in a constant building sequence. These sequences have
443 A = A CODE[1] VALUE[1]
444 A = A CODE[2] VALUE[2]
447 where A is an accumulator, each CODE[i] is a binary rtl operation
448 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
449 struct mips_integer_op {
451 unsigned HOST_WIDE_INT value;
454 /* The largest number of operations needed to load an integer constant.
455 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
456 When the lowest bit is clear, we can try, but reject a sequence with
457 an extra SLL at the end. */
458 #define MIPS_MAX_INTEGER_OPS 7
460 /* Information about a MIPS16e SAVE or RESTORE instruction. */
461 struct mips16e_save_restore_info {
462 /* The number of argument registers saved by a SAVE instruction.
463 0 for RESTORE instructions. */
466 /* Bit X is set if the instruction saves or restores GPR X. */
469 /* The total number of bytes to allocate. */
473 /* Costs of various operations on the different architectures. */
475 struct mips_rtx_cost_data
477 unsigned short fp_add;
478 unsigned short fp_mult_sf;
479 unsigned short fp_mult_df;
480 unsigned short fp_div_sf;
481 unsigned short fp_div_df;
482 unsigned short int_mult_si;
483 unsigned short int_mult_di;
484 unsigned short int_div_si;
485 unsigned short int_div_di;
486 unsigned short branch_cost;
487 unsigned short memory_latency;
490 /* Global variables for machine-dependent things. */
492 /* The -G setting, or the configuration's default small-data limit if
493 no -G option is given. */
494 static unsigned int mips_small_data_threshold;
496 /* The number of file directives written by mips_output_filename. */
497 int num_source_filenames;
499 /* The name that appeared in the last .file directive written by
500 mips_output_filename, or "" if mips_output_filename hasn't
501 written anything yet. */
502 const char *current_function_file = "";
504 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
507 /* Arrays that map GCC register numbers to debugger register numbers. */
508 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
509 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
511 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
512 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
513 struct mips_asm_switch mips_nomacro = { "macro", 0 };
514 struct mips_asm_switch mips_noat = { "at", 0 };
516 /* True if we're writing out a branch-likely instruction rather than a
518 static bool mips_branch_likely;
520 /* The current instruction-set architecture. */
521 enum processor mips_arch;
522 const struct mips_cpu_info *mips_arch_info;
524 /* The processor that we should tune the code for. */
525 enum processor mips_tune;
526 const struct mips_cpu_info *mips_tune_info;
528 /* The ISA level associated with mips_arch. */
531 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
532 static const struct mips_cpu_info *mips_isa_option_info;
534 /* Which ABI to use. */
535 int mips_abi = MIPS_ABI_DEFAULT;
537 /* Which cost information to use. */
538 static const struct mips_rtx_cost_data *mips_cost;
540 /* The ambient target flags, excluding MASK_MIPS16. */
541 static int mips_base_target_flags;
543 /* True if MIPS16 is the default mode. */
544 bool mips_base_mips16;
546 /* The ambient values of other global variables. */
547 static int mips_base_schedule_insns; /* flag_schedule_insns */
548 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
549 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
550 static int mips_base_align_loops; /* align_loops */
551 static int mips_base_align_jumps; /* align_jumps */
552 static int mips_base_align_functions; /* align_functions */
554 /* The -mcode-readable setting. */
555 enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES;
557 /* The -mr10k-cache-barrier setting. */
558 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier;
560 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
561 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
563 /* Index C is true if character C is a valid PRINT_OPERAND punctation
565 static bool mips_print_operand_punct[256];
567 static GTY (()) int mips_output_filename_first_time = 1;
569 /* mips_split_p[X] is true if symbols of type X can be split by
570 mips_split_symbol. */
571 bool mips_split_p[NUM_SYMBOL_TYPES];
573 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
574 can be split by mips_split_symbol. */
575 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
577 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
578 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
579 if they are matched by a special .md file pattern. */
580 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
582 /* Likewise for HIGHs. */
583 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
585 /* Target state for MIPS16. */
586 struct target_globals *mips16_globals;
588 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
589 and returned from mips_sched_reorder2. */
590 static int cached_can_issue_more;
592 /* Index R is the smallest register class that contains register R. */
593 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
594 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
595 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
596 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
597 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
598 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
599 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
600 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
601 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
602 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
603 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
604 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
605 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
606 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
611 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
612 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
613 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
614 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
615 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
616 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
617 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
618 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
623 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
624 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
625 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
626 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
631 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
632 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
633 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
634 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
639 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
640 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
643 /* The value of TARGET_ATTRIBUTE_TABLE. */
644 static const struct attribute_spec mips_attribute_table[] = {
645 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
647 { "long_call", 0, 0, false, true, true, NULL, false },
648 { "far", 0, 0, false, true, true, NULL, false },
649 { "near", 0, 0, false, true, true, NULL, false },
650 /* We would really like to treat "mips16" and "nomips16" as type
651 attributes, but GCC doesn't provide the hooks we need to support
652 the right conversion rules. As declaration attributes, they affect
653 code generation but don't carry other semantics. */
654 { "mips16", 0, 0, true, false, false, NULL, false },
655 { "nomips16", 0, 0, true, false, false, NULL, false },
656 /* Allow functions to be specified as interrupt handlers */
657 { "interrupt", 0, 0, false, true, true, NULL, false },
658 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
659 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
660 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
661 { NULL, 0, 0, false, false, false, NULL, false }
664 /* A table describing all the processors GCC knows about. Names are
665 matched in the order listed. The first mention of an ISA level is
666 taken as the canonical name for that ISA.
668 To ease comparison, please keep this table in the same order
669 as GAS's mips_cpu_info_table. Please also make sure that
670 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
671 options correctly. */
672 static const struct mips_cpu_info mips_cpu_info_table[] = {
673 /* Entries for generic ISAs. */
674 { "mips1", PROCESSOR_R3000, 1, 0 },
675 { "mips2", PROCESSOR_R6000, 2, 0 },
676 { "mips3", PROCESSOR_R4000, 3, 0 },
677 { "mips4", PROCESSOR_R8000, 4, 0 },
678 /* Prefer not to use branch-likely instructions for generic MIPS32rX
679 and MIPS64rX code. The instructions were officially deprecated
680 in revisions 2 and earlier, but revision 3 is likely to downgrade
681 that to a recommendation to avoid the instructions in code that
682 isn't tuned to a specific processor. */
683 { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
684 { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
685 { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
686 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
687 { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
689 /* MIPS I processors. */
690 { "r3000", PROCESSOR_R3000, 1, 0 },
691 { "r2000", PROCESSOR_R3000, 1, 0 },
692 { "r3900", PROCESSOR_R3900, 1, 0 },
694 /* MIPS II processors. */
695 { "r6000", PROCESSOR_R6000, 2, 0 },
697 /* MIPS III processors. */
698 { "r4000", PROCESSOR_R4000, 3, 0 },
699 { "vr4100", PROCESSOR_R4100, 3, 0 },
700 { "vr4111", PROCESSOR_R4111, 3, 0 },
701 { "vr4120", PROCESSOR_R4120, 3, 0 },
702 { "vr4130", PROCESSOR_R4130, 3, 0 },
703 { "vr4300", PROCESSOR_R4300, 3, 0 },
704 { "r4400", PROCESSOR_R4000, 3, 0 },
705 { "r4600", PROCESSOR_R4600, 3, 0 },
706 { "orion", PROCESSOR_R4600, 3, 0 },
707 { "r4650", PROCESSOR_R4650, 3, 0 },
708 /* ST Loongson 2E/2F processors. */
709 { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
710 { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
712 /* MIPS IV processors. */
713 { "r8000", PROCESSOR_R8000, 4, 0 },
714 { "r10000", PROCESSOR_R10000, 4, 0 },
715 { "r12000", PROCESSOR_R10000, 4, 0 },
716 { "r14000", PROCESSOR_R10000, 4, 0 },
717 { "r16000", PROCESSOR_R10000, 4, 0 },
718 { "vr5000", PROCESSOR_R5000, 4, 0 },
719 { "vr5400", PROCESSOR_R5400, 4, 0 },
720 { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
721 { "rm7000", PROCESSOR_R7000, 4, 0 },
722 { "rm9000", PROCESSOR_R9000, 4, 0 },
724 /* MIPS32 processors. */
725 { "4kc", PROCESSOR_4KC, 32, 0 },
726 { "4km", PROCESSOR_4KC, 32, 0 },
727 { "4kp", PROCESSOR_4KP, 32, 0 },
728 { "4ksc", PROCESSOR_4KC, 32, 0 },
730 /* MIPS32 Release 2 processors. */
731 { "m4k", PROCESSOR_M4K, 33, 0 },
732 { "4kec", PROCESSOR_4KC, 33, 0 },
733 { "4kem", PROCESSOR_4KC, 33, 0 },
734 { "4kep", PROCESSOR_4KP, 33, 0 },
735 { "4ksd", PROCESSOR_4KC, 33, 0 },
737 { "24kc", PROCESSOR_24KC, 33, 0 },
738 { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
739 { "24kf", PROCESSOR_24KF2_1, 33, 0 },
740 { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
741 { "24kfx", PROCESSOR_24KF1_1, 33, 0 },
742 { "24kx", PROCESSOR_24KF1_1, 33, 0 },
744 { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
745 { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
746 { "24kef", PROCESSOR_24KF2_1, 33, 0 },
747 { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
748 { "24kefx", PROCESSOR_24KF1_1, 33, 0 },
749 { "24kex", PROCESSOR_24KF1_1, 33, 0 },
751 { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
752 { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
753 { "34kf", PROCESSOR_24KF2_1, 33, 0 },
754 { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
755 { "34kfx", PROCESSOR_24KF1_1, 33, 0 },
756 { "34kx", PROCESSOR_24KF1_1, 33, 0 },
758 { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
759 { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
760 { "74kf", PROCESSOR_74KF2_1, 33, 0 },
761 { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
762 { "74kfx", PROCESSOR_74KF1_1, 33, 0 },
763 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
764 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
766 { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
767 { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
768 { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
769 { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
771 /* MIPS64 processors. */
772 { "5kc", PROCESSOR_5KC, 64, 0 },
773 { "5kf", PROCESSOR_5KF, 64, 0 },
774 { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
775 { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
776 { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
777 { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
778 { "xlr", PROCESSOR_XLR, 64, 0 },
779 { "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
781 /* MIPS64 Release 2 processors. */
782 { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
785 /* Default costs. If these are used for a processor we should look
786 up the actual costs. */
787 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
788 COSTS_N_INSNS (7), /* fp_mult_sf */ \
789 COSTS_N_INSNS (8), /* fp_mult_df */ \
790 COSTS_N_INSNS (23), /* fp_div_sf */ \
791 COSTS_N_INSNS (36), /* fp_div_df */ \
792 COSTS_N_INSNS (10), /* int_mult_si */ \
793 COSTS_N_INSNS (10), /* int_mult_di */ \
794 COSTS_N_INSNS (69), /* int_div_si */ \
795 COSTS_N_INSNS (69), /* int_div_di */ \
796 2, /* branch_cost */ \
797 4 /* memory_latency */
799 /* Floating-point costs for processors without an FPU. Just assume that
800 all floating-point libcalls are very expensive. */
801 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
802 COSTS_N_INSNS (256), /* fp_mult_sf */ \
803 COSTS_N_INSNS (256), /* fp_mult_df */ \
804 COSTS_N_INSNS (256), /* fp_div_sf */ \
805 COSTS_N_INSNS (256) /* fp_div_df */
807 /* Costs to use when optimizing for size. */
808 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
809 COSTS_N_INSNS (1), /* fp_add */
810 COSTS_N_INSNS (1), /* fp_mult_sf */
811 COSTS_N_INSNS (1), /* fp_mult_df */
812 COSTS_N_INSNS (1), /* fp_div_sf */
813 COSTS_N_INSNS (1), /* fp_div_df */
814 COSTS_N_INSNS (1), /* int_mult_si */
815 COSTS_N_INSNS (1), /* int_mult_di */
816 COSTS_N_INSNS (1), /* int_div_si */
817 COSTS_N_INSNS (1), /* int_div_di */
819 4 /* memory_latency */
822 /* Costs to use when optimizing for speed, indexed by processor. */
823 static const struct mips_rtx_cost_data
824 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
826 COSTS_N_INSNS (2), /* fp_add */
827 COSTS_N_INSNS (4), /* fp_mult_sf */
828 COSTS_N_INSNS (5), /* fp_mult_df */
829 COSTS_N_INSNS (12), /* fp_div_sf */
830 COSTS_N_INSNS (19), /* fp_div_df */
831 COSTS_N_INSNS (12), /* int_mult_si */
832 COSTS_N_INSNS (12), /* int_mult_di */
833 COSTS_N_INSNS (35), /* int_div_si */
834 COSTS_N_INSNS (35), /* int_div_di */
836 4 /* memory_latency */
840 COSTS_N_INSNS (6), /* int_mult_si */
841 COSTS_N_INSNS (6), /* int_mult_di */
842 COSTS_N_INSNS (36), /* int_div_si */
843 COSTS_N_INSNS (36), /* int_div_di */
845 4 /* memory_latency */
849 COSTS_N_INSNS (36), /* int_mult_si */
850 COSTS_N_INSNS (36), /* int_mult_di */
851 COSTS_N_INSNS (37), /* int_div_si */
852 COSTS_N_INSNS (37), /* int_div_di */
854 4 /* memory_latency */
858 COSTS_N_INSNS (4), /* int_mult_si */
859 COSTS_N_INSNS (11), /* int_mult_di */
860 COSTS_N_INSNS (36), /* int_div_si */
861 COSTS_N_INSNS (68), /* int_div_di */
863 4 /* memory_latency */
866 COSTS_N_INSNS (4), /* fp_add */
867 COSTS_N_INSNS (4), /* fp_mult_sf */
868 COSTS_N_INSNS (5), /* fp_mult_df */
869 COSTS_N_INSNS (17), /* fp_div_sf */
870 COSTS_N_INSNS (32), /* fp_div_df */
871 COSTS_N_INSNS (4), /* int_mult_si */
872 COSTS_N_INSNS (11), /* int_mult_di */
873 COSTS_N_INSNS (36), /* int_div_si */
874 COSTS_N_INSNS (68), /* int_div_di */
876 4 /* memory_latency */
879 COSTS_N_INSNS (4), /* fp_add */
880 COSTS_N_INSNS (4), /* fp_mult_sf */
881 COSTS_N_INSNS (5), /* fp_mult_df */
882 COSTS_N_INSNS (17), /* fp_div_sf */
883 COSTS_N_INSNS (32), /* fp_div_df */
884 COSTS_N_INSNS (4), /* int_mult_si */
885 COSTS_N_INSNS (7), /* int_mult_di */
886 COSTS_N_INSNS (42), /* int_div_si */
887 COSTS_N_INSNS (72), /* int_div_di */
889 4 /* memory_latency */
893 COSTS_N_INSNS (5), /* int_mult_si */
894 COSTS_N_INSNS (5), /* int_mult_di */
895 COSTS_N_INSNS (41), /* int_div_si */
896 COSTS_N_INSNS (41), /* int_div_di */
898 4 /* memory_latency */
901 COSTS_N_INSNS (8), /* fp_add */
902 COSTS_N_INSNS (8), /* fp_mult_sf */
903 COSTS_N_INSNS (10), /* fp_mult_df */
904 COSTS_N_INSNS (34), /* fp_div_sf */
905 COSTS_N_INSNS (64), /* fp_div_df */
906 COSTS_N_INSNS (5), /* int_mult_si */
907 COSTS_N_INSNS (5), /* int_mult_di */
908 COSTS_N_INSNS (41), /* int_div_si */
909 COSTS_N_INSNS (41), /* int_div_di */
911 4 /* memory_latency */
914 COSTS_N_INSNS (4), /* fp_add */
915 COSTS_N_INSNS (4), /* fp_mult_sf */
916 COSTS_N_INSNS (5), /* fp_mult_df */
917 COSTS_N_INSNS (17), /* fp_div_sf */
918 COSTS_N_INSNS (32), /* fp_div_df */
919 COSTS_N_INSNS (5), /* int_mult_si */
920 COSTS_N_INSNS (5), /* int_mult_di */
921 COSTS_N_INSNS (41), /* int_div_si */
922 COSTS_N_INSNS (41), /* int_div_di */
924 4 /* memory_latency */
928 COSTS_N_INSNS (5), /* int_mult_si */
929 COSTS_N_INSNS (5), /* int_mult_di */
930 COSTS_N_INSNS (41), /* int_div_si */
931 COSTS_N_INSNS (41), /* int_div_di */
933 4 /* memory_latency */
936 COSTS_N_INSNS (8), /* fp_add */
937 COSTS_N_INSNS (8), /* fp_mult_sf */
938 COSTS_N_INSNS (10), /* fp_mult_df */
939 COSTS_N_INSNS (34), /* fp_div_sf */
940 COSTS_N_INSNS (64), /* fp_div_df */
941 COSTS_N_INSNS (5), /* int_mult_si */
942 COSTS_N_INSNS (5), /* int_mult_di */
943 COSTS_N_INSNS (41), /* int_div_si */
944 COSTS_N_INSNS (41), /* int_div_di */
946 4 /* memory_latency */
949 COSTS_N_INSNS (4), /* fp_add */
950 COSTS_N_INSNS (4), /* fp_mult_sf */
951 COSTS_N_INSNS (5), /* fp_mult_df */
952 COSTS_N_INSNS (17), /* fp_div_sf */
953 COSTS_N_INSNS (32), /* fp_div_df */
954 COSTS_N_INSNS (5), /* int_mult_si */
955 COSTS_N_INSNS (5), /* int_mult_di */
956 COSTS_N_INSNS (41), /* int_div_si */
957 COSTS_N_INSNS (41), /* int_div_di */
959 4 /* memory_latency */
962 COSTS_N_INSNS (6), /* fp_add */
963 COSTS_N_INSNS (6), /* fp_mult_sf */
964 COSTS_N_INSNS (7), /* fp_mult_df */
965 COSTS_N_INSNS (25), /* fp_div_sf */
966 COSTS_N_INSNS (48), /* fp_div_df */
967 COSTS_N_INSNS (5), /* int_mult_si */
968 COSTS_N_INSNS (5), /* int_mult_di */
969 COSTS_N_INSNS (41), /* int_div_si */
970 COSTS_N_INSNS (41), /* int_div_di */
972 4 /* memory_latency */
989 COSTS_N_INSNS (5), /* int_mult_si */
990 COSTS_N_INSNS (5), /* int_mult_di */
991 COSTS_N_INSNS (72), /* int_div_si */
992 COSTS_N_INSNS (72), /* int_div_di */
994 4 /* memory_latency */
997 COSTS_N_INSNS (2), /* fp_add */
998 COSTS_N_INSNS (4), /* fp_mult_sf */
999 COSTS_N_INSNS (5), /* fp_mult_df */
1000 COSTS_N_INSNS (12), /* fp_div_sf */
1001 COSTS_N_INSNS (19), /* fp_div_df */
1002 COSTS_N_INSNS (2), /* int_mult_si */
1003 COSTS_N_INSNS (2), /* int_mult_di */
1004 COSTS_N_INSNS (35), /* int_div_si */
1005 COSTS_N_INSNS (35), /* int_div_di */
1006 1, /* branch_cost */
1007 4 /* memory_latency */
1010 COSTS_N_INSNS (3), /* fp_add */
1011 COSTS_N_INSNS (5), /* fp_mult_sf */
1012 COSTS_N_INSNS (6), /* fp_mult_df */
1013 COSTS_N_INSNS (15), /* fp_div_sf */
1014 COSTS_N_INSNS (16), /* fp_div_df */
1015 COSTS_N_INSNS (17), /* int_mult_si */
1016 COSTS_N_INSNS (17), /* int_mult_di */
1017 COSTS_N_INSNS (38), /* int_div_si */
1018 COSTS_N_INSNS (38), /* int_div_di */
1019 2, /* branch_cost */
1020 6 /* memory_latency */
1023 COSTS_N_INSNS (6), /* fp_add */
1024 COSTS_N_INSNS (7), /* fp_mult_sf */
1025 COSTS_N_INSNS (8), /* fp_mult_df */
1026 COSTS_N_INSNS (23), /* fp_div_sf */
1027 COSTS_N_INSNS (36), /* fp_div_df */
1028 COSTS_N_INSNS (10), /* int_mult_si */
1029 COSTS_N_INSNS (10), /* int_mult_di */
1030 COSTS_N_INSNS (69), /* int_div_si */
1031 COSTS_N_INSNS (69), /* int_div_di */
1032 2, /* branch_cost */
1033 6 /* memory_latency */
1045 /* The only costs that appear to be updated here are
1046 integer multiplication. */
1048 COSTS_N_INSNS (4), /* int_mult_si */
1049 COSTS_N_INSNS (6), /* int_mult_di */
1050 COSTS_N_INSNS (69), /* int_div_si */
1051 COSTS_N_INSNS (69), /* int_div_di */
1052 1, /* branch_cost */
1053 4 /* memory_latency */
1065 COSTS_N_INSNS (6), /* fp_add */
1066 COSTS_N_INSNS (4), /* fp_mult_sf */
1067 COSTS_N_INSNS (5), /* fp_mult_df */
1068 COSTS_N_INSNS (23), /* fp_div_sf */
1069 COSTS_N_INSNS (36), /* fp_div_df */
1070 COSTS_N_INSNS (5), /* int_mult_si */
1071 COSTS_N_INSNS (5), /* int_mult_di */
1072 COSTS_N_INSNS (36), /* int_div_si */
1073 COSTS_N_INSNS (36), /* int_div_di */
1074 1, /* branch_cost */
1075 4 /* memory_latency */
1078 COSTS_N_INSNS (6), /* fp_add */
1079 COSTS_N_INSNS (5), /* fp_mult_sf */
1080 COSTS_N_INSNS (6), /* fp_mult_df */
1081 COSTS_N_INSNS (30), /* fp_div_sf */
1082 COSTS_N_INSNS (59), /* fp_div_df */
1083 COSTS_N_INSNS (3), /* int_mult_si */
1084 COSTS_N_INSNS (4), /* int_mult_di */
1085 COSTS_N_INSNS (42), /* int_div_si */
1086 COSTS_N_INSNS (74), /* int_div_di */
1087 1, /* branch_cost */
1088 4 /* memory_latency */
1091 COSTS_N_INSNS (6), /* fp_add */
1092 COSTS_N_INSNS (5), /* fp_mult_sf */
1093 COSTS_N_INSNS (6), /* fp_mult_df */
1094 COSTS_N_INSNS (30), /* fp_div_sf */
1095 COSTS_N_INSNS (59), /* fp_div_df */
1096 COSTS_N_INSNS (5), /* int_mult_si */
1097 COSTS_N_INSNS (9), /* int_mult_di */
1098 COSTS_N_INSNS (42), /* int_div_si */
1099 COSTS_N_INSNS (74), /* int_div_di */
1100 1, /* branch_cost */
1101 4 /* memory_latency */
1104 /* The only costs that are changed here are
1105 integer multiplication. */
1106 COSTS_N_INSNS (6), /* fp_add */
1107 COSTS_N_INSNS (7), /* fp_mult_sf */
1108 COSTS_N_INSNS (8), /* fp_mult_df */
1109 COSTS_N_INSNS (23), /* fp_div_sf */
1110 COSTS_N_INSNS (36), /* fp_div_df */
1111 COSTS_N_INSNS (5), /* int_mult_si */
1112 COSTS_N_INSNS (9), /* int_mult_di */
1113 COSTS_N_INSNS (69), /* int_div_si */
1114 COSTS_N_INSNS (69), /* int_div_di */
1115 1, /* branch_cost */
1116 4 /* memory_latency */
1122 /* The only costs that are changed here are
1123 integer multiplication. */
1124 COSTS_N_INSNS (6), /* fp_add */
1125 COSTS_N_INSNS (7), /* fp_mult_sf */
1126 COSTS_N_INSNS (8), /* fp_mult_df */
1127 COSTS_N_INSNS (23), /* fp_div_sf */
1128 COSTS_N_INSNS (36), /* fp_div_df */
1129 COSTS_N_INSNS (3), /* int_mult_si */
1130 COSTS_N_INSNS (8), /* int_mult_di */
1131 COSTS_N_INSNS (69), /* int_div_si */
1132 COSTS_N_INSNS (69), /* int_div_di */
1133 1, /* branch_cost */
1134 4 /* memory_latency */
1137 COSTS_N_INSNS (2), /* fp_add */
1138 COSTS_N_INSNS (2), /* fp_mult_sf */
1139 COSTS_N_INSNS (2), /* fp_mult_df */
1140 COSTS_N_INSNS (12), /* fp_div_sf */
1141 COSTS_N_INSNS (19), /* fp_div_df */
1142 COSTS_N_INSNS (5), /* int_mult_si */
1143 COSTS_N_INSNS (9), /* int_mult_di */
1144 COSTS_N_INSNS (34), /* int_div_si */
1145 COSTS_N_INSNS (66), /* int_div_di */
1146 1, /* branch_cost */
1147 4 /* memory_latency */
1150 /* These costs are the same as the SB-1A below. */
1151 COSTS_N_INSNS (4), /* fp_add */
1152 COSTS_N_INSNS (4), /* fp_mult_sf */
1153 COSTS_N_INSNS (4), /* fp_mult_df */
1154 COSTS_N_INSNS (24), /* fp_div_sf */
1155 COSTS_N_INSNS (32), /* fp_div_df */
1156 COSTS_N_INSNS (3), /* int_mult_si */
1157 COSTS_N_INSNS (4), /* int_mult_di */
1158 COSTS_N_INSNS (36), /* int_div_si */
1159 COSTS_N_INSNS (68), /* int_div_di */
1160 1, /* branch_cost */
1161 4 /* memory_latency */
1164 /* These costs are the same as the SB-1 above. */
1165 COSTS_N_INSNS (4), /* fp_add */
1166 COSTS_N_INSNS (4), /* fp_mult_sf */
1167 COSTS_N_INSNS (4), /* fp_mult_df */
1168 COSTS_N_INSNS (24), /* fp_div_sf */
1169 COSTS_N_INSNS (32), /* fp_div_df */
1170 COSTS_N_INSNS (3), /* int_mult_si */
1171 COSTS_N_INSNS (4), /* int_mult_di */
1172 COSTS_N_INSNS (36), /* int_div_si */
1173 COSTS_N_INSNS (68), /* int_div_di */
1174 1, /* branch_cost */
1175 4 /* memory_latency */
1182 COSTS_N_INSNS (8), /* int_mult_si */
1183 COSTS_N_INSNS (8), /* int_mult_di */
1184 COSTS_N_INSNS (72), /* int_div_si */
1185 COSTS_N_INSNS (72), /* int_div_di */
1186 1, /* branch_cost */
1187 4 /* memory_latency */
1191 static rtx mips_find_pic_call_symbol (rtx, rtx);
1192 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1194 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1196 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1197 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1198 struct GTY (()) mflip_mips16_entry {
1202 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1204 /* Hash table callbacks for mflip_mips16_htab. */
1207 mflip_mips16_htab_hash (const void *entry)
1209 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1213 mflip_mips16_htab_eq (const void *entry, const void *name)
1215 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1216 (const char *) name) == 0;
1219 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1220 mode, false if it should next add an attribute for the opposite mode. */
1221 static GTY(()) bool mips16_flipper;
1223 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1224 for -mflip-mips16. Return true if it should use "mips16" and false if
1225 it should use "nomips16". */
1228 mflip_mips16_use_mips16_p (tree decl)
1230 struct mflip_mips16_entry *entry;
1235 /* Use the opposite of the command-line setting for anonymous decls. */
1236 if (!DECL_NAME (decl))
1237 return !mips_base_mips16;
1239 if (!mflip_mips16_htab)
1240 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1241 mflip_mips16_htab_eq, NULL);
1243 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1244 hash = htab_hash_string (name);
1245 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1246 entry = (struct mflip_mips16_entry *) *slot;
1249 mips16_flipper = !mips16_flipper;
1250 entry = ggc_alloc_mflip_mips16_entry ();
1252 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1255 return entry->mips16_p;
1258 /* Predicates to test for presence of "near" and "far"/"long_call"
1259 attributes on the given TYPE. */
1262 mips_near_type_p (const_tree type)
1264 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1268 mips_far_type_p (const_tree type)
1270 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1271 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1274 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1277 mips_mips16_decl_p (const_tree decl)
1279 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1283 mips_nomips16_decl_p (const_tree decl)
1285 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1288 /* Check if the interrupt attribute is set for a function. */
1291 mips_interrupt_type_p (tree type)
1293 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1296 /* Check if the attribute to use shadow register set is set for a function. */
1299 mips_use_shadow_register_set_p (tree type)
1301 return lookup_attribute ("use_shadow_register_set",
1302 TYPE_ATTRIBUTES (type)) != NULL;
1305 /* Check if the attribute to keep interrupts masked is set for a function. */
1308 mips_keep_interrupts_masked_p (tree type)
1310 return lookup_attribute ("keep_interrupts_masked",
1311 TYPE_ATTRIBUTES (type)) != NULL;
1314 /* Check if the attribute to use debug exception return is set for
1318 mips_use_debug_exception_return_p (tree type)
1320 return lookup_attribute ("use_debug_exception_return",
1321 TYPE_ATTRIBUTES (type)) != NULL;
1324 /* Return true if function DECL is a MIPS16 function. Return the ambient
1325 setting if DECL is null. */
1328 mips_use_mips16_mode_p (tree decl)
1332 /* Nested functions must use the same frame pointer as their
1333 parent and must therefore use the same ISA mode. */
1334 tree parent = decl_function_context (decl);
1337 if (mips_mips16_decl_p (decl))
1339 if (mips_nomips16_decl_p (decl))
1342 return mips_base_mips16;
1345 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1348 mips_comp_type_attributes (const_tree type1, const_tree type2)
1350 /* Disallow mixed near/far attributes. */
1351 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1353 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1358 /* Implement TARGET_INSERT_ATTRIBUTES. */
1361 mips_insert_attributes (tree decl, tree *attributes)
1364 bool mips16_p, nomips16_p;
1366 /* Check for "mips16" and "nomips16" attributes. */
1367 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1368 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1369 if (TREE_CODE (decl) != FUNCTION_DECL)
1372 error ("%qs attribute only applies to functions", "mips16");
1374 error ("%qs attribute only applies to functions", "nomips16");
1378 mips16_p |= mips_mips16_decl_p (decl);
1379 nomips16_p |= mips_nomips16_decl_p (decl);
1380 if (mips16_p || nomips16_p)
1382 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1383 if (mips16_p && nomips16_p)
1384 error ("%qE cannot have both %<mips16%> and "
1385 "%<nomips16%> attributes",
1388 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1390 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1391 "mips16" attribute, arbitrarily pick one. We must pick the same
1392 setting for duplicate declarations of a function. */
1393 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1394 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1399 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1402 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1404 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1405 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1406 error ("%qE redeclared with conflicting %qs attributes",
1407 DECL_NAME (newdecl), "mips16");
1408 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1409 error ("%qE redeclared with conflicting %qs attributes",
1410 DECL_NAME (newdecl), "nomips16");
1412 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1413 DECL_ATTRIBUTES (newdecl));
1416 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1417 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1420 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1422 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1424 *base_ptr = XEXP (x, 0);
1425 *offset_ptr = INTVAL (XEXP (x, 1));
1434 static unsigned int mips_build_integer (struct mips_integer_op *,
1435 unsigned HOST_WIDE_INT);
1437 /* A subroutine of mips_build_integer, with the same interface.
1438 Assume that the final action in the sequence should be a left shift. */
1441 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1443 unsigned int i, shift;
1445 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1446 since signed numbers are easier to load than unsigned ones. */
1448 while ((value & 1) == 0)
1449 value /= 2, shift++;
1451 i = mips_build_integer (codes, value);
1452 codes[i].code = ASHIFT;
1453 codes[i].value = shift;
1457 /* As for mips_build_shift, but assume that the final action will be
1458 an IOR or PLUS operation. */
1461 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1463 unsigned HOST_WIDE_INT high;
1466 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1467 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1469 /* The constant is too complex to load with a simple LUI/ORI pair,
1470 so we want to give the recursive call as many trailing zeros as
1471 possible. In this case, we know bit 16 is set and that the
1472 low 16 bits form a negative number. If we subtract that number
1473 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1474 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1475 codes[i].code = PLUS;
1476 codes[i].value = CONST_LOW_PART (value);
1480 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1481 bits gives a value with at least 17 trailing zeros. */
1482 i = mips_build_integer (codes, high);
1483 codes[i].code = IOR;
1484 codes[i].value = value & 0xffff;
1489 /* Fill CODES with a sequence of rtl operations to load VALUE.
1490 Return the number of operations needed. */
1493 mips_build_integer (struct mips_integer_op *codes,
1494 unsigned HOST_WIDE_INT value)
1496 if (SMALL_OPERAND (value)
1497 || SMALL_OPERAND_UNSIGNED (value)
1498 || LUI_OPERAND (value))
1500 /* The value can be loaded with a single instruction. */
1501 codes[0].code = UNKNOWN;
1502 codes[0].value = value;
1505 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1507 /* Either the constant is a simple LUI/ORI combination or its
1508 lowest bit is set. We don't want to shift in this case. */
1509 return mips_build_lower (codes, value);
1511 else if ((value & 0xffff) == 0)
1513 /* The constant will need at least three actions. The lowest
1514 16 bits are clear, so the final action will be a shift. */
1515 return mips_build_shift (codes, value);
1519 /* The final action could be a shift, add or inclusive OR.
1520 Rather than use a complex condition to select the best
1521 approach, try both mips_build_shift and mips_build_lower
1522 and pick the one that gives the shortest sequence.
1523 Note that this case is only used once per constant. */
1524 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1525 unsigned int cost, alt_cost;
1527 cost = mips_build_shift (codes, value);
1528 alt_cost = mips_build_lower (alt_codes, value);
1529 if (alt_cost < cost)
1531 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1538 /* Return true if symbols of type TYPE require a GOT access. */
1541 mips_got_symbol_type_p (enum mips_symbol_type type)
1545 case SYMBOL_GOT_PAGE_OFST:
1546 case SYMBOL_GOT_DISP:
1554 /* Return true if X is a thread-local symbol. */
1557 mips_tls_symbol_p (rtx x)
1559 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1562 /* Return true if SYMBOL_REF X is associated with a global symbol
1563 (in the STB_GLOBAL sense). */
1566 mips_global_symbol_p (const_rtx x)
1568 const_tree decl = SYMBOL_REF_DECL (x);
1571 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1573 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1574 or weak symbols. Relocations in the object file will be against
1575 the target symbol, so it's that symbol's binding that matters here. */
1576 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1579 /* Return true if function X is a libgcc MIPS16 stub function. */
1582 mips16_stub_function_p (const_rtx x)
1584 return (GET_CODE (x) == SYMBOL_REF
1585 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1588 /* Return true if function X is a locally-defined and locally-binding
1592 mips16_local_function_p (const_rtx x)
1594 return (GET_CODE (x) == SYMBOL_REF
1595 && SYMBOL_REF_LOCAL_P (x)
1596 && !SYMBOL_REF_EXTERNAL_P (x)
1597 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1600 /* Return true if SYMBOL_REF X binds locally. */
1603 mips_symbol_binds_local_p (const_rtx x)
1605 return (SYMBOL_REF_DECL (x)
1606 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1607 : SYMBOL_REF_LOCAL_P (x));
1610 /* Return true if rtx constants of mode MODE should be put into a small
1614 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1616 return (!TARGET_EMBEDDED_DATA
1617 && TARGET_LOCAL_SDATA
1618 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1621 /* Return true if X should not be moved directly into register $25.
1622 We need this because many versions of GAS will treat "la $25,foo" as
1623 part of a call sequence and so allow a global "foo" to be lazily bound. */
1626 mips_dangerous_for_la25_p (rtx x)
1628 return (!TARGET_EXPLICIT_RELOCS
1630 && GET_CODE (x) == SYMBOL_REF
1631 && mips_global_symbol_p (x));
1634 /* Return true if calls to X might need $25 to be valid on entry. */
1637 mips_use_pic_fn_addr_reg_p (const_rtx x)
1639 if (!TARGET_USE_PIC_FN_ADDR_REG)
1642 /* MIPS16 stub functions are guaranteed not to use $25. */
1643 if (mips16_stub_function_p (x))
1646 if (GET_CODE (x) == SYMBOL_REF)
1648 /* If PLTs and copy relocations are available, the static linker
1649 will make sure that $25 is valid on entry to the target function. */
1650 if (TARGET_ABICALLS_PIC0)
1653 /* Locally-defined functions use absolute accesses to set up
1654 the global pointer. */
1655 if (TARGET_ABSOLUTE_ABICALLS
1656 && mips_symbol_binds_local_p (x)
1657 && !SYMBOL_REF_EXTERNAL_P (x))
1664 /* Return the method that should be used to access SYMBOL_REF or
1665 LABEL_REF X in context CONTEXT. */
1667 static enum mips_symbol_type
1668 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1671 return SYMBOL_GOT_DISP;
1673 if (GET_CODE (x) == LABEL_REF)
1675 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1676 code and if we know that the label is in the current function's
1677 text section. LABEL_REFs are used for jump tables as well as
1678 text labels, so we must check whether jump tables live in the
1680 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1681 && !LABEL_REF_NONLOCAL_P (x))
1682 return SYMBOL_PC_RELATIVE;
1684 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1685 return SYMBOL_GOT_PAGE_OFST;
1687 return SYMBOL_ABSOLUTE;
1690 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1692 if (SYMBOL_REF_TLS_MODEL (x))
1695 if (CONSTANT_POOL_ADDRESS_P (x))
1697 if (TARGET_MIPS16_TEXT_LOADS)
1698 return SYMBOL_PC_RELATIVE;
1700 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1701 return SYMBOL_PC_RELATIVE;
1703 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1704 return SYMBOL_GP_RELATIVE;
1707 /* Do not use small-data accesses for weak symbols; they may end up
1709 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1710 return SYMBOL_GP_RELATIVE;
1712 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1714 if (TARGET_ABICALLS_PIC2
1715 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1717 /* There are three cases to consider:
1719 - o32 PIC (either with or without explicit relocs)
1720 - n32/n64 PIC without explicit relocs
1721 - n32/n64 PIC with explicit relocs
1723 In the first case, both local and global accesses will use an
1724 R_MIPS_GOT16 relocation. We must correctly predict which of
1725 the two semantics (local or global) the assembler and linker
1726 will apply. The choice depends on the symbol's binding rather
1727 than its visibility.
1729 In the second case, the assembler will not use R_MIPS_GOT16
1730 relocations, but it chooses between local and global accesses
1731 in the same way as for o32 PIC.
1733 In the third case we have more freedom since both forms of
1734 access will work for any kind of symbol. However, there seems
1735 little point in doing things differently. */
1736 if (mips_global_symbol_p (x))
1737 return SYMBOL_GOT_DISP;
1739 return SYMBOL_GOT_PAGE_OFST;
1742 if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL)
1743 return SYMBOL_FORCE_TO_MEM;
1745 return SYMBOL_ABSOLUTE;
1748 /* Classify the base of symbolic expression X, given that X appears in
1751 static enum mips_symbol_type
1752 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1756 split_const (x, &x, &offset);
1757 if (UNSPEC_ADDRESS_P (x))
1758 return UNSPEC_ADDRESS_TYPE (x);
1760 return mips_classify_symbol (x, context);
1763 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1764 is the alignment in bytes of SYMBOL_REF X. */
1767 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1769 HOST_WIDE_INT align;
1771 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1772 return IN_RANGE (offset, 0, align - 1);
1775 /* Return true if X is a symbolic constant that can be used in context
1776 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1779 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1780 enum mips_symbol_type *symbol_type)
1784 split_const (x, &x, &offset);
1785 if (UNSPEC_ADDRESS_P (x))
1787 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1788 x = UNSPEC_ADDRESS (x);
1790 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1792 *symbol_type = mips_classify_symbol (x, context);
1793 if (*symbol_type == SYMBOL_TLS)
1799 if (offset == const0_rtx)
1802 /* Check whether a nonzero offset is valid for the underlying
1804 switch (*symbol_type)
1806 case SYMBOL_ABSOLUTE:
1807 case SYMBOL_FORCE_TO_MEM:
1808 case SYMBOL_32_HIGH:
1809 case SYMBOL_64_HIGH:
1812 /* If the target has 64-bit pointers and the object file only
1813 supports 32-bit symbols, the values of those symbols will be
1814 sign-extended. In this case we can't allow an arbitrary offset
1815 in case the 32-bit value X + OFFSET has a different sign from X. */
1816 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1817 return offset_within_block_p (x, INTVAL (offset));
1819 /* In other cases the relocations can handle any offset. */
1822 case SYMBOL_PC_RELATIVE:
1823 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1824 In this case, we no longer have access to the underlying constant,
1825 but the original symbol-based access was known to be valid. */
1826 if (GET_CODE (x) == LABEL_REF)
1831 case SYMBOL_GP_RELATIVE:
1832 /* Make sure that the offset refers to something within the
1833 same object block. This should guarantee that the final
1834 PC- or GP-relative offset is within the 16-bit limit. */
1835 return offset_within_block_p (x, INTVAL (offset));
1837 case SYMBOL_GOT_PAGE_OFST:
1838 case SYMBOL_GOTOFF_PAGE:
1839 /* If the symbol is global, the GOT entry will contain the symbol's
1840 address, and we will apply a 16-bit offset after loading it.
1841 If the symbol is local, the linker should provide enough local
1842 GOT entries for a 16-bit offset, but larger offsets may lead
1844 return SMALL_INT (offset);
1848 /* There is no carry between the HI and LO REL relocations, so the
1849 offset is only valid if we know it won't lead to such a carry. */
1850 return mips_offset_within_alignment_p (x, INTVAL (offset));
1852 case SYMBOL_GOT_DISP:
1853 case SYMBOL_GOTOFF_DISP:
1854 case SYMBOL_GOTOFF_CALL:
1855 case SYMBOL_GOTOFF_LOADGP:
1858 case SYMBOL_GOTTPREL:
1866 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1867 single instruction. We rely on the fact that, in the worst case,
1868 all instructions involved in a MIPS16 address calculation are usually
1872 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1876 case SYMBOL_ABSOLUTE:
1877 /* When using 64-bit symbols, we need 5 preparatory instructions,
1880 lui $at,%highest(symbol)
1881 daddiu $at,$at,%higher(symbol)
1883 daddiu $at,$at,%hi(symbol)
1886 The final address is then $at + %lo(symbol). With 32-bit
1887 symbols we just need a preparatory LUI for normal mode and
1888 a preparatory LI and SLL for MIPS16. */
1889 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1891 case SYMBOL_GP_RELATIVE:
1892 /* Treat GP-relative accesses as taking a single instruction on
1893 MIPS16 too; the copy of $gp can often be shared. */
1896 case SYMBOL_PC_RELATIVE:
1897 /* PC-relative constants can be only be used with ADDIUPC,
1898 DADDIUPC, LWPC and LDPC. */
1899 if (mode == MAX_MACHINE_MODE
1900 || GET_MODE_SIZE (mode) == 4
1901 || GET_MODE_SIZE (mode) == 8)
1904 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1907 case SYMBOL_FORCE_TO_MEM:
1908 /* LEAs will be converted into constant-pool references by
1910 if (mode == MAX_MACHINE_MODE)
1913 /* The constant must be loaded and then dereferenced. */
1916 case SYMBOL_GOT_DISP:
1917 /* The constant will have to be loaded from the GOT before it
1918 is used in an address. */
1919 if (mode != MAX_MACHINE_MODE)
1924 case SYMBOL_GOT_PAGE_OFST:
1925 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1926 local/global classification is accurate. The worst cases are:
1928 (1) For local symbols when generating o32 or o64 code. The assembler
1934 ...and the final address will be $at + %lo(symbol).
1936 (2) For global symbols when -mxgot. The assembler will use:
1938 lui $at,%got_hi(symbol)
1941 ...and the final address will be $at + %got_lo(symbol). */
1944 case SYMBOL_GOTOFF_PAGE:
1945 case SYMBOL_GOTOFF_DISP:
1946 case SYMBOL_GOTOFF_CALL:
1947 case SYMBOL_GOTOFF_LOADGP:
1948 case SYMBOL_32_HIGH:
1949 case SYMBOL_64_HIGH:
1955 case SYMBOL_GOTTPREL:
1958 /* A 16-bit constant formed by a single relocation, or a 32-bit
1959 constant formed from a high 16-bit relocation and a low 16-bit
1960 relocation. Use mips_split_p to determine which. 32-bit
1961 constants need an "lui; addiu" sequence for normal mode and
1962 an "li; sll; addiu" sequence for MIPS16 mode. */
1963 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1966 /* We don't treat a bare TLS symbol as a constant. */
1972 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1973 to load symbols of type TYPE into a register. Return 0 if the given
1974 type of symbol cannot be used as an immediate operand.
1976 Otherwise, return the number of instructions needed to load or store
1977 values of mode MODE to or from addresses of type TYPE. Return 0 if
1978 the given type of symbol is not valid in addresses.
1980 In both cases, treat extended MIPS16 instructions as two instructions. */
1983 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1985 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1988 /* A for_each_rtx callback. Stop the search if *X references a
1989 thread-local symbol. */
1992 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1994 return mips_tls_symbol_p (*x);
1997 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2000 mips_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2002 enum mips_symbol_type type;
2005 /* There is no assembler syntax for expressing an address-sized
2007 if (GET_CODE (x) == HIGH)
2010 /* As an optimization, reject constants that mips_legitimize_move
2013 Suppose we have a multi-instruction sequence that loads constant C
2014 into register R. If R does not get allocated a hard register, and
2015 R is used in an operand that allows both registers and memory
2016 references, reload will consider forcing C into memory and using
2017 one of the instruction's memory alternatives. Returning false
2018 here will force it to use an input reload instead. */
2019 if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x))
2022 split_const (x, &base, &offset);
2023 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)
2024 && type != SYMBOL_FORCE_TO_MEM)
2026 /* The same optimization as for CONST_INT. */
2027 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2030 /* If MIPS16 constant pools live in the text section, they should
2031 not refer to anything that might need run-time relocation. */
2032 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2036 /* TLS symbols must be computed by mips_legitimize_move. */
2037 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2043 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2044 constants when we're using a per-function constant pool. */
2047 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2048 const_rtx x ATTRIBUTE_UNUSED)
2050 return !TARGET_MIPS16_PCREL_LOADS;
2053 /* Return true if register REGNO is a valid base register for mode MODE.
2054 STRICT_P is true if REG_OK_STRICT is in effect. */
2057 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2060 if (!HARD_REGISTER_NUM_P (regno))
2064 regno = reg_renumber[regno];
2067 /* These fake registers will be eliminated to either the stack or
2068 hard frame pointer, both of which are usually valid base registers.
2069 Reload deals with the cases where the eliminated form isn't valid. */
2070 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2073 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2074 values, nothing smaller. There are two problems here:
2076 (a) Instantiating virtual registers can introduce new uses of the
2077 stack pointer. If these virtual registers are valid addresses,
2078 the stack pointer should be too.
2080 (b) Most uses of the stack pointer are not made explicit until
2081 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2082 We don't know until that stage whether we'll be eliminating to the
2083 stack pointer (which needs the restriction) or the hard frame
2084 pointer (which doesn't).
2086 All in all, it seems more consistent to only enforce this restriction
2087 during and after reload. */
2088 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2089 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2091 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2094 /* Return true if X is a valid base register for mode MODE.
2095 STRICT_P is true if REG_OK_STRICT is in effect. */
2098 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2100 if (!strict_p && GET_CODE (x) == SUBREG)
2104 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2107 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2108 can address a value of mode MODE. */
2111 mips_valid_offset_p (rtx x, enum machine_mode mode)
2113 /* Check that X is a signed 16-bit number. */
2114 if (!const_arith_operand (x, Pmode))
2117 /* We may need to split multiword moves, so make sure that every word
2119 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2120 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2126 /* Return true if a LO_SUM can address a value of mode MODE when the
2127 LO_SUM symbol has type SYMBOL_TYPE. */
2130 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2132 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2134 if (mips_symbol_insns (symbol_type, mode) == 0)
2137 /* Check that there is a known low-part relocation. */
2138 if (mips_lo_relocs[symbol_type] == NULL)
2141 /* We may need to split multiword moves, so make sure that each word
2142 can be accessed without inducing a carry. This is mainly needed
2143 for o64, which has historically only guaranteed 64-bit alignment
2144 for 128-bit types. */
2145 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2146 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2152 /* Return true if X is a valid address for machine mode MODE. If it is,
2153 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2157 mips_classify_address (struct mips_address_info *info, rtx x,
2158 enum machine_mode mode, bool strict_p)
2160 switch (GET_CODE (x))
2164 info->type = ADDRESS_REG;
2166 info->offset = const0_rtx;
2167 return mips_valid_base_register_p (info->reg, mode, strict_p);
2170 info->type = ADDRESS_REG;
2171 info->reg = XEXP (x, 0);
2172 info->offset = XEXP (x, 1);
2173 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2174 && mips_valid_offset_p (info->offset, mode));
2177 info->type = ADDRESS_LO_SUM;
2178 info->reg = XEXP (x, 0);
2179 info->offset = XEXP (x, 1);
2180 /* We have to trust the creator of the LO_SUM to do something vaguely
2181 sane. Target-independent code that creates a LO_SUM should also
2182 create and verify the matching HIGH. Target-independent code that
2183 adds an offset to a LO_SUM must prove that the offset will not
2184 induce a carry. Failure to do either of these things would be
2185 a bug, and we are not required to check for it here. The MIPS
2186 backend itself should only create LO_SUMs for valid symbolic
2187 constants, with the high part being either a HIGH or a copy
2190 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2191 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2192 && mips_valid_lo_sum_p (info->symbol_type, mode));
2195 /* Small-integer addresses don't occur very often, but they
2196 are legitimate if $0 is a valid base register. */
2197 info->type = ADDRESS_CONST_INT;
2198 return !TARGET_MIPS16 && SMALL_INT (x);
2203 info->type = ADDRESS_SYMBOLIC;
2204 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2206 && mips_symbol_insns (info->symbol_type, mode) > 0
2207 && !mips_split_p[info->symbol_type]);
2214 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2217 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2219 struct mips_address_info addr;
2221 return mips_classify_address (&addr, x, mode, strict_p);
2224 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2227 mips_stack_address_p (rtx x, enum machine_mode mode)
2229 struct mips_address_info addr;
2231 return (mips_classify_address (&addr, x, mode, false)
2232 && addr.type == ADDRESS_REG
2233 && addr.reg == stack_pointer_rtx);
2236 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2237 address instruction. Note that such addresses are not considered
2238 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2239 is so restricted. */
2242 mips_lwxs_address_p (rtx addr)
2245 && GET_CODE (addr) == PLUS
2246 && REG_P (XEXP (addr, 1)))
2248 rtx offset = XEXP (addr, 0);
2249 if (GET_CODE (offset) == MULT
2250 && REG_P (XEXP (offset, 0))
2251 && CONST_INT_P (XEXP (offset, 1))
2252 && INTVAL (XEXP (offset, 1)) == 4)
2258 /* Return true if a value at OFFSET bytes from base register BASE can be
2259 accessed using an unextended MIPS16 instruction. MODE is the mode of
2262 Usually the offset in an unextended instruction is a 5-bit field.
2263 The offset is unsigned and shifted left once for LH and SH, twice
2264 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2265 an 8-bit immediate field that's shifted left twice. */
2268 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2269 unsigned HOST_WIDE_INT offset)
2271 if (offset % GET_MODE_SIZE (mode) == 0)
2273 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2274 return offset < 256U * GET_MODE_SIZE (mode);
2275 return offset < 32U * GET_MODE_SIZE (mode);
2280 /* Return the number of instructions needed to load or store a value
2281 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2282 Assume that multiword moves may need to be split into word moves
2283 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2286 For MIPS16 code, count extended instructions as two instructions. */
2289 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2291 struct mips_address_info addr;
2294 /* BLKmode is used for single unaligned loads and stores and should
2295 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2296 meaningless, so we have to single it out as a special case one way
2298 if (mode != BLKmode && might_split_p)
2299 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2303 if (mips_classify_address (&addr, x, mode, false))
2308 && !mips16_unextended_reference_p (mode, addr.reg,
2309 UINTVAL (addr.offset)))
2313 case ADDRESS_LO_SUM:
2314 return TARGET_MIPS16 ? factor * 2 : factor;
2316 case ADDRESS_CONST_INT:
2319 case ADDRESS_SYMBOLIC:
2320 return factor * mips_symbol_insns (addr.symbol_type, mode);
2325 /* Return the number of instructions needed to load constant X.
2326 Return 0 if X isn't a valid constant. */
2329 mips_const_insns (rtx x)
2331 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2332 enum mips_symbol_type symbol_type;
2335 switch (GET_CODE (x))
2338 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2340 || !mips_split_p[symbol_type])
2343 /* This is simply an LUI for normal mode. It is an extended
2344 LI followed by an extended SLL for MIPS16. */
2345 return TARGET_MIPS16 ? 4 : 1;
2349 /* Unsigned 8-bit constants can be loaded using an unextended
2350 LI instruction. Unsigned 16-bit constants can be loaded
2351 using an extended LI. Negative constants must be loaded
2352 using LI and then negated. */
2353 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2354 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2355 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2356 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2359 return mips_build_integer (codes, INTVAL (x));
2363 /* Allow zeros for normal mode, where we can use $0. */
2364 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2370 /* See if we can refer to X directly. */
2371 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2372 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2374 /* Otherwise try splitting the constant into a base and offset.
2375 If the offset is a 16-bit value, we can load the base address
2376 into a register and then use (D)ADDIU to add in the offset.
2377 If the offset is larger, we can load the base and offset
2378 into separate registers and add them together with (D)ADDU.
2379 However, the latter is only possible before reload; during
2380 and after reload, we must have the option of forcing the
2381 constant into the pool instead. */
2382 split_const (x, &x, &offset);
2385 int n = mips_const_insns (x);
2388 if (SMALL_INT (offset))
2390 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2391 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2398 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2406 /* X is a doubleword constant that can be handled by splitting it into
2407 two words and loading each word separately. Return the number of
2408 instructions required to do this. */
2411 mips_split_const_insns (rtx x)
2413 unsigned int low, high;
2415 low = mips_const_insns (mips_subword (x, false));
2416 high = mips_const_insns (mips_subword (x, true));
2417 gcc_assert (low > 0 && high > 0);
2421 /* Return the number of instructions needed to implement INSN,
2422 given that it loads from or stores to MEM. Count extended
2423 MIPS16 instructions as two instructions. */
2426 mips_load_store_insns (rtx mem, rtx insn)
2428 enum machine_mode mode;
2432 gcc_assert (MEM_P (mem));
2433 mode = GET_MODE (mem);
2435 /* Try to prove that INSN does not need to be split. */
2436 might_split_p = true;
2437 if (GET_MODE_BITSIZE (mode) == 64)
2439 set = single_set (insn);
2440 if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set)))
2441 might_split_p = false;
2444 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2447 /* Return the number of instructions needed for an integer division. */
2450 mips_idiv_insns (void)
2455 if (TARGET_CHECK_ZERO_DIV)
2457 if (GENERATE_DIVIDE_TRAPS)
2463 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2468 /* Emit a move from SRC to DEST. Assume that the move expanders can
2469 handle all moves if !can_create_pseudo_p (). The distinction is
2470 important because, unlike emit_move_insn, the move expanders know
2471 how to force Pmode objects into the constant pool even when the
2472 constant pool address is not itself legitimate. */
2475 mips_emit_move (rtx dest, rtx src)
2477 return (can_create_pseudo_p ()
2478 ? emit_move_insn (dest, src)
2479 : emit_move_insn_1 (dest, src));
2482 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2485 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2487 emit_insn (gen_rtx_SET (VOIDmode, target,
2488 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2491 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2492 Return that new register. */
2495 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2499 reg = gen_reg_rtx (mode);
2500 mips_emit_unary (code, reg, op0);
2504 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2507 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2509 emit_insn (gen_rtx_SET (VOIDmode, target,
2510 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2513 /* Compute (CODE OP0 OP1) and store the result in a new register
2514 of mode MODE. Return that new register. */
2517 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2521 reg = gen_reg_rtx (mode);
2522 mips_emit_binary (code, reg, op0, op1);
2526 /* Copy VALUE to a register and return that register. If new pseudos
2527 are allowed, copy it into a new register, otherwise use DEST. */
2530 mips_force_temporary (rtx dest, rtx value)
2532 if (can_create_pseudo_p ())
2533 return force_reg (Pmode, value);
2536 mips_emit_move (dest, value);
2541 /* Emit a call sequence with call pattern PATTERN and return the call
2542 instruction itself (which is not necessarily the last instruction
2543 emitted). ORIG_ADDR is the original, unlegitimized address,
2544 ADDR is the legitimized form, and LAZY_P is true if the call
2545 address is lazily-bound. */
2548 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2552 insn = emit_call_insn (pattern);
2554 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2556 /* MIPS16 JALRs only take MIPS16 registers. If the target
2557 function requires $25 to be valid on entry, we must copy it
2558 there separately. The move instruction can be put in the
2559 call's delay slot. */
2560 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2561 emit_insn_before (gen_move_insn (reg, addr), insn);
2562 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2566 /* Lazy-binding stubs require $gp to be valid on entry. */
2567 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2571 /* See the comment above load_call<mode> for details. */
2572 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2573 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2574 emit_insn (gen_update_got_version ());
2579 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2580 then add CONST_INT OFFSET to the result. */
2583 mips_unspec_address_offset (rtx base, rtx offset,
2584 enum mips_symbol_type symbol_type)
2586 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2587 UNSPEC_ADDRESS_FIRST + symbol_type);
2588 if (offset != const0_rtx)
2589 base = gen_rtx_PLUS (Pmode, base, offset);
2590 return gen_rtx_CONST (Pmode, base);
2593 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2594 type SYMBOL_TYPE. */
2597 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2601 split_const (address, &base, &offset);
2602 return mips_unspec_address_offset (base, offset, symbol_type);
2605 /* If OP is an UNSPEC address, return the address to which it refers,
2606 otherwise return OP itself. */
2609 mips_strip_unspec_address (rtx op)
2613 split_const (op, &base, &offset);
2614 if (UNSPEC_ADDRESS_P (base))
2615 op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset));
2619 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2620 high part to BASE and return the result. Just return BASE otherwise.
2621 TEMP is as for mips_force_temporary.
2623 The returned expression can be used as the first operand to a LO_SUM. */
2626 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2627 enum mips_symbol_type symbol_type)
2629 if (mips_split_p[symbol_type])
2631 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2632 addr = mips_force_temporary (temp, addr);
2633 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2638 /* Return an instruction that copies $gp into register REG. We want
2639 GCC to treat the register's value as constant, so that its value
2640 can be rematerialized on demand. */
2643 gen_load_const_gp (rtx reg)
2645 return (Pmode == SImode
2646 ? gen_load_const_gp_si (reg)
2647 : gen_load_const_gp_di (reg));
2650 /* Return a pseudo register that contains the value of $gp throughout
2651 the current function. Such registers are needed by MIPS16 functions,
2652 for which $gp itself is not a valid base register or addition operand. */
2655 mips16_gp_pseudo_reg (void)
2657 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2661 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2663 push_topmost_sequence ();
2665 scan = get_insns ();
2666 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2667 scan = NEXT_INSN (scan);
2669 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2670 emit_insn_after (insn, scan);
2672 pop_topmost_sequence ();
2675 return cfun->machine->mips16_gp_pseudo_rtx;
2678 /* Return a base register that holds pic_offset_table_rtx.
2679 TEMP, if nonnull, is a scratch Pmode base register. */
2682 mips_pic_base_register (rtx temp)
2685 return pic_offset_table_rtx;
2687 if (currently_expanding_to_rtl)
2688 return mips16_gp_pseudo_reg ();
2690 if (can_create_pseudo_p ())
2691 temp = gen_reg_rtx (Pmode);
2694 /* The first post-reload split exposes all references to $gp
2695 (both uses and definitions). All references must remain
2696 explicit after that point.
2698 It is safe to introduce uses of $gp at any time, so for
2699 simplicity, we do that before the split too. */
2700 mips_emit_move (temp, pic_offset_table_rtx);
2702 emit_insn (gen_load_const_gp (temp));
2706 /* Return the RHS of a load_call<mode> insn. */
2709 mips_unspec_call (rtx reg, rtx symbol)
2713 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2714 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2717 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2718 reference. Return NULL_RTX otherwise. */
2721 mips_strip_unspec_call (rtx src)
2723 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2724 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2728 /* Create and return a GOT reference of type TYPE for address ADDR.
2729 TEMP, if nonnull, is a scratch Pmode base register. */
2732 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2734 rtx base, high, lo_sum_symbol;
2736 base = mips_pic_base_register (temp);
2738 /* If we used the temporary register to load $gp, we can't use
2739 it for the high part as well. */
2740 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2743 high = mips_unspec_offset_high (temp, base, addr, type);
2744 lo_sum_symbol = mips_unspec_address (addr, type);
2746 if (type == SYMBOL_GOTOFF_CALL)
2747 return mips_unspec_call (high, lo_sum_symbol);
2749 return (Pmode == SImode
2750 ? gen_unspec_gotsi (high, lo_sum_symbol)
2751 : gen_unspec_gotdi (high, lo_sum_symbol));
2754 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2755 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2756 constant in that context and can be split into high and low parts.
2757 If so, and if LOW_OUT is nonnull, emit the high part and store the
2758 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2760 TEMP is as for mips_force_temporary and is used to load the high
2761 part into a register.
2763 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2764 a legitimize SET_SRC for an .md pattern, otherwise the low part
2765 is guaranteed to be a legitimate address for mode MODE. */
2768 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2770 enum mips_symbol_context context;
2771 enum mips_symbol_type symbol_type;
2774 context = (mode == MAX_MACHINE_MODE
2775 ? SYMBOL_CONTEXT_LEA
2776 : SYMBOL_CONTEXT_MEM);
2777 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2779 addr = XEXP (addr, 0);
2780 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2781 && mips_symbol_insns (symbol_type, mode) > 0
2782 && mips_split_hi_p[symbol_type])
2785 switch (symbol_type)
2787 case SYMBOL_GOT_PAGE_OFST:
2788 /* The high part of a page/ofst pair is loaded from the GOT. */
2789 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2800 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2801 && mips_symbol_insns (symbol_type, mode) > 0
2802 && mips_split_p[symbol_type])
2805 switch (symbol_type)
2807 case SYMBOL_GOT_DISP:
2808 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2809 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2812 case SYMBOL_GP_RELATIVE:
2813 high = mips_pic_base_register (temp);
2814 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2818 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2819 high = mips_force_temporary (temp, high);
2820 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2829 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2830 mips_force_temporary; it is only needed when OFFSET is not a
2834 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2836 if (!SMALL_OPERAND (offset))
2842 /* Load the full offset into a register so that we can use
2843 an unextended instruction for the address itself. */
2844 high = GEN_INT (offset);
2849 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2850 The addition inside the macro CONST_HIGH_PART may cause an
2851 overflow, so we need to force a sign-extension check. */
2852 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2853 offset = CONST_LOW_PART (offset);
2855 high = mips_force_temporary (temp, high);
2856 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2858 return plus_constant (reg, offset);
2861 /* The __tls_get_attr symbol. */
2862 static GTY(()) rtx mips_tls_symbol;
2864 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2865 the TLS symbol we are referencing and TYPE is the symbol type to use
2866 (either global dynamic or local dynamic). V0 is an RTX for the
2867 return value location. */
2870 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2874 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2876 if (!mips_tls_symbol)
2877 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2879 loc = mips_unspec_address (sym, type);
2883 emit_insn (gen_rtx_SET (Pmode, a0,
2884 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2885 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2886 const0_rtx, NULL_RTX, false);
2887 RTL_CONST_CALL_P (insn) = 1;
2888 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2889 insn = get_insns ();
2896 /* Return a pseudo register that contains the current thread pointer. */
2903 tp = gen_reg_rtx (Pmode);
2904 if (Pmode == DImode)
2905 emit_insn (gen_tls_get_tp_di (tp));
2907 emit_insn (gen_tls_get_tp_si (tp));
2911 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2912 its address. The return value will be both a valid address and a valid
2913 SET_SRC (either a REG or a LO_SUM). */
2916 mips_legitimize_tls_address (rtx loc)
2918 rtx dest, insn, v0, tp, tmp1, tmp2, eqv;
2919 enum tls_model model;
2923 sorry ("MIPS16 TLS");
2924 return gen_reg_rtx (Pmode);
2927 model = SYMBOL_REF_TLS_MODEL (loc);
2928 /* Only TARGET_ABICALLS code can have more than one module; other
2929 code must be be static and should not use a GOT. All TLS models
2930 reduce to local exec in this situation. */
2931 if (!TARGET_ABICALLS)
2932 model = TLS_MODEL_LOCAL_EXEC;
2936 case TLS_MODEL_GLOBAL_DYNAMIC:
2937 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2938 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2939 dest = gen_reg_rtx (Pmode);
2940 emit_libcall_block (insn, dest, v0, loc);
2943 case TLS_MODEL_LOCAL_DYNAMIC:
2944 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2945 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2946 tmp1 = gen_reg_rtx (Pmode);
2948 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2949 share the LDM result with other LD model accesses. */
2950 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2952 emit_libcall_block (insn, tmp1, v0, eqv);
2954 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2955 dest = gen_rtx_LO_SUM (Pmode, tmp2,
2956 mips_unspec_address (loc, SYMBOL_DTPREL));
2959 case TLS_MODEL_INITIAL_EXEC:
2960 tp = mips_get_tp ();
2961 tmp1 = gen_reg_rtx (Pmode);
2962 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2963 if (Pmode == DImode)
2964 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2966 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2967 dest = gen_reg_rtx (Pmode);
2968 emit_insn (gen_add3_insn (dest, tmp1, tp));
2971 case TLS_MODEL_LOCAL_EXEC:
2972 tp = mips_get_tp ();
2973 tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL);
2974 dest = gen_rtx_LO_SUM (Pmode, tmp1,
2975 mips_unspec_address (loc, SYMBOL_TPREL));
2984 /* If X is not a valid address for mode MODE, force it into a register. */
2987 mips_force_address (rtx x, enum machine_mode mode)
2989 if (!mips_legitimate_address_p (mode, x, false))
2990 x = force_reg (Pmode, x);
2994 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2995 be legitimized in a way that the generic machinery might not expect,
2996 return a new address, otherwise return NULL. MODE is the mode of
2997 the memory being accessed. */
3000 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3001 enum machine_mode mode)
3004 HOST_WIDE_INT offset;
3006 if (mips_tls_symbol_p (x))
3007 return mips_legitimize_tls_address (x);
3009 /* See if the address can split into a high part and a LO_SUM. */
3010 if (mips_split_symbol (NULL, x, mode, &addr))
3011 return mips_force_address (addr, mode);
3013 /* Handle BASE + OFFSET using mips_add_offset. */
3014 mips_split_plus (x, &base, &offset);
3017 if (!mips_valid_base_register_p (base, mode, false))
3018 base = copy_to_mode_reg (Pmode, base);
3019 addr = mips_add_offset (NULL, base, offset);
3020 return mips_force_address (addr, mode);
3026 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3029 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3031 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3032 enum machine_mode mode;
3033 unsigned int i, num_ops;
3036 mode = GET_MODE (dest);
3037 num_ops = mips_build_integer (codes, value);
3039 /* Apply each binary operation to X. Invariant: X is a legitimate
3040 source operand for a SET pattern. */
3041 x = GEN_INT (codes[0].value);
3042 for (i = 1; i < num_ops; i++)
3044 if (!can_create_pseudo_p ())
3046 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3050 x = force_reg (mode, x);
3051 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3054 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3057 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3058 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3062 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3066 /* Split moves of big integers into smaller pieces. */
3067 if (splittable_const_int_operand (src, mode))
3069 mips_move_integer (dest, dest, INTVAL (src));
3073 /* Split moves of symbolic constants into high/low pairs. */
3074 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3076 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3080 /* Generate the appropriate access sequences for TLS symbols. */
3081 if (mips_tls_symbol_p (src))
3083 mips_emit_move (dest, mips_legitimize_tls_address (src));
3087 /* If we have (const (plus symbol offset)), and that expression cannot
3088 be forced into memory, load the symbol first and add in the offset.
3089 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3090 forced into memory, as it usually produces better code. */
3091 split_const (src, &base, &offset);
3092 if (offset != const0_rtx
3093 && (targetm.cannot_force_const_mem (mode, src)
3094 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3096 base = mips_force_temporary (dest, base);
3097 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3101 src = force_const_mem (mode, src);
3103 /* When using explicit relocs, constant pool references are sometimes
3104 not legitimate addresses. */
3105 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3106 mips_emit_move (dest, src);
3109 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3110 sequence that is valid. */
3113 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3115 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3117 mips_emit_move (dest, force_reg (mode, src));
3121 /* We need to deal with constants that would be legitimate
3122 immediate_operands but aren't legitimate move_operands. */
3123 if (CONSTANT_P (src) && !move_operand (src, mode))
3125 mips_legitimize_const_move (mode, dest, src);
3126 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3132 /* Return true if value X in context CONTEXT is a small-data address
3133 that can be rewritten as a LO_SUM. */
3136 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3138 enum mips_symbol_type symbol_type;
3140 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3141 && !mips_split_p[SYMBOL_GP_RELATIVE]
3142 && mips_symbolic_constant_p (x, context, &symbol_type)
3143 && symbol_type == SYMBOL_GP_RELATIVE);
3146 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3147 containing MEM, or null if none. */
3150 mips_small_data_pattern_1 (rtx *loc, void *data)
3152 enum mips_symbol_context context;
3154 if (GET_CODE (*loc) == LO_SUM)
3159 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3164 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3165 return mips_rewrite_small_data_p (*loc, context);
3168 /* Return true if OP refers to small data symbols directly, not through
3172 mips_small_data_pattern_p (rtx op)
3174 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3177 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3178 DATA is the containing MEM, or null if none. */
3181 mips_rewrite_small_data_1 (rtx *loc, void *data)
3183 enum mips_symbol_context context;
3187 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3191 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3192 if (mips_rewrite_small_data_p (*loc, context))
3193 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3195 if (GET_CODE (*loc) == LO_SUM)
3201 /* Rewrite instruction pattern PATTERN so that it refers to small data
3202 using explicit relocations. */
3205 mips_rewrite_small_data (rtx pattern)
3207 pattern = copy_insn (pattern);
3208 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3212 /* We need a lot of little routines to check the range of MIPS16 immediate
3216 m16_check_op (rtx op, int low, int high, int mask)
3218 return (CONST_INT_P (op)
3219 && IN_RANGE (INTVAL (op), low, high)
3220 && (INTVAL (op) & mask) == 0);
3224 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3226 return m16_check_op (op, 0x1, 0x8, 0);
3230 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3232 return m16_check_op (op, -0x8, 0x7, 0);
3236 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3238 return m16_check_op (op, -0x7, 0x8, 0);
3242 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3244 return m16_check_op (op, -0x10, 0xf, 0);
3248 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3250 return m16_check_op (op, -0xf, 0x10, 0);
3254 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3256 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3260 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3262 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3266 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3268 return m16_check_op (op, -0x80, 0x7f, 0);
3272 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3274 return m16_check_op (op, -0x7f, 0x80, 0);
3278 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3280 return m16_check_op (op, 0x0, 0xff, 0);
3284 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3286 return m16_check_op (op, -0xff, 0x0, 0);
3290 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3292 return m16_check_op (op, -0x1, 0xfe, 0);
3296 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3298 return m16_check_op (op, 0x0, 0xff << 2, 3);
3302 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3304 return m16_check_op (op, -0xff << 2, 0x0, 3);
3308 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3310 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3314 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3316 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3319 /* The cost of loading values from the constant pool. It should be
3320 larger than the cost of any constant we want to synthesize inline. */
3321 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3323 /* Return the cost of X when used as an operand to the MIPS16 instruction
3324 that implements CODE. Return -1 if there is no such instruction, or if
3325 X is not a valid immediate operand for it. */
3328 mips16_constant_cost (int code, HOST_WIDE_INT x)
3335 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3336 other shifts are extended. The shift patterns truncate the shift
3337 count to the right size, so there are no out-of-range values. */
3338 if (IN_RANGE (x, 1, 8))
3340 return COSTS_N_INSNS (1);
3343 if (IN_RANGE (x, -128, 127))
3345 if (SMALL_OPERAND (x))
3346 return COSTS_N_INSNS (1);
3350 /* Like LE, but reject the always-true case. */
3354 /* We add 1 to the immediate and use SLT. */
3357 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3360 if (IN_RANGE (x, 0, 255))
3362 if (SMALL_OPERAND_UNSIGNED (x))
3363 return COSTS_N_INSNS (1);
3368 /* Equality comparisons with 0 are cheap. */
3378 /* Return true if there is a non-MIPS16 instruction that implements CODE
3379 and if that instruction accepts X as an immediate operand. */
3382 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3389 /* All shift counts are truncated to a valid constant. */
3394 /* Likewise rotates, if the target supports rotates at all. */
3400 /* These instructions take 16-bit unsigned immediates. */
3401 return SMALL_OPERAND_UNSIGNED (x);
3406 /* These instructions take 16-bit signed immediates. */
3407 return SMALL_OPERAND (x);
3413 /* The "immediate" forms of these instructions are really
3414 implemented as comparisons with register 0. */
3419 /* Likewise, meaning that the only valid immediate operand is 1. */
3423 /* We add 1 to the immediate and use SLT. */
3424 return SMALL_OPERAND (x + 1);
3427 /* Likewise SLTU, but reject the always-true case. */
3428 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3432 /* The bit position and size are immediate operands. */
3433 return ISA_HAS_EXT_INS;
3436 /* By default assume that $0 can be used for 0. */
3441 /* Return the cost of binary operation X, given that the instruction
3442 sequence for a word-sized or smaller operation has cost SINGLE_COST
3443 and that the sequence of a double-word operation has cost DOUBLE_COST.
3444 If SPEED is true, optimize for speed otherwise optimize for size. */
3447 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3451 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3456 + rtx_cost (XEXP (x, 0), SET, speed)
3457 + rtx_cost (XEXP (x, 1), GET_CODE (x), speed));
3460 /* Return the cost of floating-point multiplications of mode MODE. */
3463 mips_fp_mult_cost (enum machine_mode mode)
3465 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3468 /* Return the cost of floating-point divisions of mode MODE. */
3471 mips_fp_div_cost (enum machine_mode mode)
3473 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3476 /* Return the cost of sign-extending OP to mode MODE, not including the
3477 cost of OP itself. */
3480 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3483 /* Extended loads are as cheap as unextended ones. */
3486 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3487 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3490 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3491 /* We can use SEB or SEH. */
3492 return COSTS_N_INSNS (1);
3494 /* We need to use a shift left and a shift right. */
3495 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3498 /* Return the cost of zero-extending OP to mode MODE, not including the
3499 cost of OP itself. */
3502 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3505 /* Extended loads are as cheap as unextended ones. */
3508 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3509 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3510 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3512 if (GENERATE_MIPS16E)
3513 /* We can use ZEB or ZEH. */
3514 return COSTS_N_INSNS (1);
3517 /* We need to load 0xff or 0xffff into a register and use AND. */
3518 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3520 /* We can use ANDI. */
3521 return COSTS_N_INSNS (1);
3524 /* Implement TARGET_RTX_COSTS. */
3527 mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed)
3529 enum machine_mode mode = GET_MODE (x);
3530 bool float_mode_p = FLOAT_MODE_P (mode);
3534 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3535 appear in the instruction stream, and the cost of a comparison is
3536 really the cost of the branch or scc condition. At the time of
3537 writing, GCC only uses an explicit outer COMPARE code when optabs
3538 is testing whether a constant is expensive enough to force into a
3539 register. We want optabs to pass such constants through the MIPS
3540 expanders instead, so make all constants very cheap here. */
3541 if (outer_code == COMPARE)
3543 gcc_assert (CONSTANT_P (x));
3551 /* Treat *clear_upper32-style ANDs as having zero cost in the
3552 second operand. The cost is entirely in the first operand.
3554 ??? This is needed because we would otherwise try to CSE
3555 the constant operand. Although that's the right thing for
3556 instructions that continue to be a register operation throughout
3557 compilation, it is disastrous for instructions that could
3558 later be converted into a memory operation. */
3560 && outer_code == AND
3561 && UINTVAL (x) == 0xffffffff)
3569 cost = mips16_constant_cost (outer_code, INTVAL (x));
3578 /* When not optimizing for size, we care more about the cost
3579 of hot code, and hot code is often in a loop. If a constant
3580 operand needs to be forced into a register, we will often be
3581 able to hoist the constant load out of the loop, so the load
3582 should not contribute to the cost. */
3583 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3595 if (force_to_mem_operand (x, VOIDmode))
3597 *total = COSTS_N_INSNS (1);
3600 cost = mips_const_insns (x);
3603 /* If the constant is likely to be stored in a GPR, SETs of
3604 single-insn constants are as cheap as register sets; we
3605 never want to CSE them.
3607 Don't reduce the cost of storing a floating-point zero in
3608 FPRs. If we have a zero in an FPR for other reasons, we
3609 can get better cfg-cleanup and delayed-branch results by
3610 using it consistently, rather than using $0 sometimes and
3611 an FPR at other times. Also, moves between floating-point
3612 registers are sometimes cheaper than (D)MTC1 $0. */
3614 && outer_code == SET
3615 && !(float_mode_p && TARGET_HARD_FLOAT))
3617 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3618 want to CSE the constant itself. It is usually better to
3619 have N copies of the last operation in the sequence and one
3620 shared copy of the other operations. (Note that this is
3621 not true for MIPS16 code, where the final operation in the
3622 sequence is often an extended instruction.)
3624 Also, if we have a CONST_INT, we don't know whether it is
3625 for a word or doubleword operation, so we cannot rely on
3626 the result of mips_build_integer. */
3627 else if (!TARGET_MIPS16
3628 && (outer_code == SET || mode == VOIDmode))
3630 *total = COSTS_N_INSNS (cost);
3633 /* The value will need to be fetched from the constant pool. */
3634 *total = CONSTANT_POOL_COST;
3638 /* If the address is legitimate, return the number of
3639 instructions it needs. */
3641 cost = mips_address_insns (addr, mode, true);
3644 *total = COSTS_N_INSNS (cost + 1);
3647 /* Check for a scaled indexed address. */
3648 if (mips_lwxs_address_p (addr))
3650 *total = COSTS_N_INSNS (2);
3653 /* Otherwise use the default handling. */
3657 *total = COSTS_N_INSNS (6);
3661 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3665 /* Check for a *clear_upper32 pattern and treat it like a zero
3666 extension. See the pattern's comment for details. */
3669 && CONST_INT_P (XEXP (x, 1))
3670 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3672 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3673 + rtx_cost (XEXP (x, 0), SET, speed));
3680 /* Double-word operations use two single-word operations. */
3681 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3690 if (CONSTANT_P (XEXP (x, 1)))
3691 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3694 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3700 *total = mips_cost->fp_add;
3702 *total = COSTS_N_INSNS (4);
3706 /* Low-part immediates need an extended MIPS16 instruction. */
3707 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3708 + rtx_cost (XEXP (x, 0), SET, speed));
3723 /* Branch comparisons have VOIDmode, so use the first operand's
3725 mode = GET_MODE (XEXP (x, 0));
3726 if (FLOAT_MODE_P (mode))
3728 *total = mips_cost->fp_add;
3731 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3737 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3738 && TARGET_FUSED_MADD
3739 && !HONOR_NANS (mode)
3740 && !HONOR_SIGNED_ZEROS (mode))
3742 /* See if we can use NMADD or NMSUB. See mips.md for the
3743 associated patterns. */
3744 rtx op0 = XEXP (x, 0);
3745 rtx op1 = XEXP (x, 1);
3746 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3748 *total = (mips_fp_mult_cost (mode)
3749 + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed)
3750 + rtx_cost (XEXP (op0, 1), SET, speed)
3751 + rtx_cost (op1, SET, speed));
3754 if (GET_CODE (op1) == MULT)
3756 *total = (mips_fp_mult_cost (mode)
3757 + rtx_cost (op0, SET, speed)
3758 + rtx_cost (XEXP (op1, 0), SET, speed)
3759 + rtx_cost (XEXP (op1, 1), SET, speed));
3768 /* If this is part of a MADD or MSUB, treat the PLUS as
3771 && TARGET_FUSED_MADD
3772 && GET_CODE (XEXP (x, 0)) == MULT)
3775 *total = mips_cost->fp_add;
3779 /* Double-word operations require three single-word operations and
3780 an SLTU. The MIPS16 version then needs to move the result of
3781 the SLTU from $24 to a MIPS16 register. */
3782 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3783 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3789 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3790 && TARGET_FUSED_MADD
3791 && !HONOR_NANS (mode)
3792 && HONOR_SIGNED_ZEROS (mode))
3794 /* See if we can use NMADD or NMSUB. See mips.md for the
3795 associated patterns. */
3796 rtx op = XEXP (x, 0);
3797 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3798 && GET_CODE (XEXP (op, 0)) == MULT)
3800 *total = (mips_fp_mult_cost (mode)
3801 + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed)
3802 + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed)
3803 + rtx_cost (XEXP (op, 1), SET, speed));
3809 *total = mips_cost->fp_add;
3811 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3816 *total = mips_fp_mult_cost (mode);
3817 else if (mode == DImode && !TARGET_64BIT)
3818 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3819 where the mulsidi3 always includes an MFHI and an MFLO. */
3821 ? mips_cost->int_mult_si * 3 + 6
3822 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3824 *total = (ISA_HAS_MUL3 ? 1 : 2);
3825 else if (mode == DImode)
3826 *total = mips_cost->int_mult_di;
3828 *total = mips_cost->int_mult_si;
3832 /* Check for a reciprocal. */
3835 && flag_unsafe_math_optimizations
3836 && XEXP (x, 0) == CONST1_RTX (mode))
3838 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3839 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3840 division as being free. */
3841 *total = rtx_cost (XEXP (x, 1), SET, speed);
3843 *total = (mips_fp_div_cost (mode)
3844 + rtx_cost (XEXP (x, 1), SET, speed));
3853 *total = mips_fp_div_cost (mode);
3862 /* It is our responsibility to make division by a power of 2
3863 as cheap as 2 register additions if we want the division
3864 expanders to be used for such operations; see the setting
3865 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3866 should always produce shorter code than using
3867 expand_sdiv2_pow2. */
3869 && CONST_INT_P (XEXP (x, 1))
3870 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3872 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed);
3875 *total = COSTS_N_INSNS (mips_idiv_insns ());
3877 else if (mode == DImode)
3878 *total = mips_cost->int_div_di;
3880 *total = mips_cost->int_div_si;
3884 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3888 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3892 case UNSIGNED_FLOAT:
3895 case FLOAT_TRUNCATE:
3896 *total = mips_cost->fp_add;
3904 /* Implement TARGET_ADDRESS_COST. */
3907 mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED)
3909 return mips_address_insns (addr, SImode, false);
3912 /* Information about a single instruction in a multi-instruction
3914 struct mips_multi_member {
3915 /* True if this is a label, false if it is code. */
3918 /* The output_asm_insn format of the instruction. */
3921 /* The operands to the instruction. */
3922 rtx operands[MAX_RECOG_OPERANDS];
3924 typedef struct mips_multi_member mips_multi_member;
3926 /* Vector definitions for the above. */
3927 DEF_VEC_O(mips_multi_member);
3928 DEF_VEC_ALLOC_O(mips_multi_member, heap);
3930 /* The instructions that make up the current multi-insn sequence. */
3931 static VEC (mips_multi_member, heap) *mips_multi_members;
3933 /* How many instructions (as opposed to labels) are in the current
3934 multi-insn sequence. */
3935 static unsigned int mips_multi_num_insns;
3937 /* Start a new multi-insn sequence. */
3940 mips_multi_start (void)
3942 VEC_truncate (mips_multi_member, mips_multi_members, 0);
3943 mips_multi_num_insns = 0;
3946 /* Add a new, uninitialized member to the current multi-insn sequence. */
3948 static struct mips_multi_member *
3949 mips_multi_add (void)
3951 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0);
3954 /* Add a normal insn with the given asm format to the current multi-insn
3955 sequence. The other arguments are a null-terminated list of operands. */
3958 mips_multi_add_insn (const char *format, ...)
3960 struct mips_multi_member *member;
3965 member = mips_multi_add ();
3966 member->is_label_p = false;
3967 member->format = format;
3968 va_start (ap, format);
3970 while ((op = va_arg (ap, rtx)))
3971 member->operands[i++] = op;
3973 mips_multi_num_insns++;
3976 /* Add the given label definition to the current multi-insn sequence.
3977 The definition should include the colon. */
3980 mips_multi_add_label (const char *label)
3982 struct mips_multi_member *member;
3984 member = mips_multi_add ();
3985 member->is_label_p = true;
3986 member->format = label;
3989 /* Return the index of the last member of the current multi-insn sequence. */
3992 mips_multi_last_index (void)
3994 return VEC_length (mips_multi_member, mips_multi_members) - 1;
3997 /* Add a copy of an existing instruction to the current multi-insn
3998 sequence. I is the index of the instruction that should be copied. */
4001 mips_multi_copy_insn (unsigned int i)
4003 struct mips_multi_member *member;
4005 member = mips_multi_add ();
4006 memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i),
4008 gcc_assert (!member->is_label_p);
4011 /* Change the operand of an existing instruction in the current
4012 multi-insn sequence. I is the index of the instruction,
4013 OP is the index of the operand, and X is the new value. */
4016 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4018 VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x;
4021 /* Write out the asm code for the current multi-insn sequence. */
4024 mips_multi_write (void)
4026 struct mips_multi_member *member;
4029 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4030 if (member->is_label_p)
4031 fprintf (asm_out_file, "%s\n", member->format);
4033 output_asm_insn (member->format, member->operands);
4036 /* Return one word of double-word value OP, taking into account the fixed
4037 endianness of certain registers. HIGH_P is true to select the high part,
4038 false to select the low part. */
4041 mips_subword (rtx op, bool high_p)
4043 unsigned int byte, offset;
4044 enum machine_mode mode;
4046 mode = GET_MODE (op);
4047 if (mode == VOIDmode)
4048 mode = TARGET_64BIT ? TImode : DImode;
4050 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4051 byte = UNITS_PER_WORD;
4055 if (FP_REG_RTX_P (op))
4057 /* Paired FPRs are always ordered little-endian. */
4058 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4059 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4063 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4065 return simplify_gen_subreg (word_mode, op, mode, byte);
4068 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4071 mips_split_64bit_move_p (rtx dest, rtx src)
4076 /* FPR-to-FPR moves can be done in a single instruction, if they're
4078 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4081 /* Check for floating-point loads and stores. */
4082 if (ISA_HAS_LDC1_SDC1)
4084 if (FP_REG_RTX_P (dest) && MEM_P (src))
4086 if (FP_REG_RTX_P (src) && MEM_P (dest))
4092 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4093 this function handles 64-bit moves for which mips_split_64bit_move_p
4094 holds. For 64-bit targets, this function handles 128-bit moves. */
4097 mips_split_doubleword_move (rtx dest, rtx src)
4101 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4103 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4104 emit_insn (gen_move_doubleword_fprdi (dest, src));
4105 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4106 emit_insn (gen_move_doubleword_fprdf (dest, src));
4107 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4108 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4109 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4110 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4111 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4112 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4113 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4114 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4115 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4116 emit_insn (gen_move_doubleword_fprtf (dest, src));
4120 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4122 low_dest = mips_subword (dest, false);
4123 mips_emit_move (low_dest, mips_subword (src, false));
4125 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4127 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4129 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4131 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4133 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4135 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4139 /* The operation can be split into two normal moves. Decide in
4140 which order to do them. */
4141 low_dest = mips_subword (dest, false);
4142 if (REG_P (low_dest)
4143 && reg_overlap_mentioned_p (low_dest, src))
4145 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4146 mips_emit_move (low_dest, mips_subword (src, false));
4150 mips_emit_move (low_dest, mips_subword (src, false));
4151 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4156 /* Return the appropriate instructions to move SRC into DEST. Assume
4157 that SRC is operand 1 and DEST is operand 0. */
4160 mips_output_move (rtx dest, rtx src)
4162 enum rtx_code dest_code, src_code;
4163 enum machine_mode mode;
4164 enum mips_symbol_type symbol_type;
4167 dest_code = GET_CODE (dest);
4168 src_code = GET_CODE (src);
4169 mode = GET_MODE (dest);
4170 dbl_p = (GET_MODE_SIZE (mode) == 8);
4172 if (dbl_p && mips_split_64bit_move_p (dest, src))
4175 if ((src_code == REG && GP_REG_P (REGNO (src)))
4176 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4178 if (dest_code == REG)
4180 if (GP_REG_P (REGNO (dest)))
4181 return "move\t%0,%z1";
4183 /* Moves to HI are handled by special .md insns. */
4184 if (REGNO (dest) == LO_REGNUM)
4187 if (DSP_ACC_REG_P (REGNO (dest)))
4189 static char retval[] = "mt__\t%z1,%q0";
4191 retval[2] = reg_names[REGNO (dest)][4];
4192 retval[3] = reg_names[REGNO (dest)][5];
4196 if (FP_REG_P (REGNO (dest)))
4197 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4199 if (ALL_COP_REG_P (REGNO (dest)))
4201 static char retval[] = "dmtc_\t%z1,%0";
4203 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4204 return dbl_p ? retval : retval + 1;
4207 if (dest_code == MEM)
4208 switch (GET_MODE_SIZE (mode))
4210 case 1: return "sb\t%z1,%0";
4211 case 2: return "sh\t%z1,%0";
4212 case 4: return "sw\t%z1,%0";
4213 case 8: return "sd\t%z1,%0";
4216 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4218 if (src_code == REG)
4220 /* Moves from HI are handled by special .md insns. */
4221 if (REGNO (src) == LO_REGNUM)
4223 /* When generating VR4120 or VR4130 code, we use MACC and
4224 DMACC instead of MFLO. This avoids both the normal
4225 MIPS III HI/LO hazards and the errata related to
4228 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4232 if (DSP_ACC_REG_P (REGNO (src)))
4234 static char retval[] = "mf__\t%0,%q1";
4236 retval[2] = reg_names[REGNO (src)][4];
4237 retval[3] = reg_names[REGNO (src)][5];
4241 if (FP_REG_P (REGNO (src)))
4242 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4244 if (ALL_COP_REG_P (REGNO (src)))
4246 static char retval[] = "dmfc_\t%0,%1";
4248 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4249 return dbl_p ? retval : retval + 1;
4252 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
4253 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4256 if (src_code == MEM)
4257 switch (GET_MODE_SIZE (mode))
4259 case 1: return "lbu\t%0,%1";
4260 case 2: return "lhu\t%0,%1";
4261 case 4: return "lw\t%0,%1";
4262 case 8: return "ld\t%0,%1";
4265 if (src_code == CONST_INT)
4267 /* Don't use the X format for the operand itself, because that
4268 will give out-of-range numbers for 64-bit hosts and 32-bit
4271 return "li\t%0,%1\t\t\t# %X1";
4273 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4276 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4280 if (src_code == HIGH)
4281 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4283 if (CONST_GP_P (src))
4284 return "move\t%0,%1";
4286 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4287 && mips_lo_relocs[symbol_type] != 0)
4289 /* A signed 16-bit constant formed by applying a relocation
4290 operator to a symbolic address. */
4291 gcc_assert (!mips_split_p[symbol_type]);
4292 return "li\t%0,%R1";
4295 if (symbolic_operand (src, VOIDmode))
4297 gcc_assert (TARGET_MIPS16
4298 ? TARGET_MIPS16_TEXT_LOADS
4299 : !TARGET_EXPLICIT_RELOCS);
4300 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4303 if (src_code == REG && FP_REG_P (REGNO (src)))
4305 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4307 if (GET_MODE (dest) == V2SFmode)
4308 return "mov.ps\t%0,%1";
4310 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4313 if (dest_code == MEM)
4314 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4316 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4318 if (src_code == MEM)
4319 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4321 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4323 static char retval[] = "l_c_\t%0,%1";
4325 retval[1] = (dbl_p ? 'd' : 'w');
4326 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4329 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4331 static char retval[] = "s_c_\t%1,%0";
4333 retval[1] = (dbl_p ? 'd' : 'w');
4334 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4340 /* Return true if CMP1 is a suitable second operand for integer ordering
4341 test CODE. See also the *sCC patterns in mips.md. */
4344 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4350 return reg_or_0_operand (cmp1, VOIDmode);
4354 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4358 return arith_operand (cmp1, VOIDmode);
4361 return sle_operand (cmp1, VOIDmode);
4364 return sleu_operand (cmp1, VOIDmode);
4371 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4372 integer ordering test *CODE, or if an equivalent combination can
4373 be formed by adjusting *CODE and *CMP1. When returning true, update
4374 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4378 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4379 enum machine_mode mode)
4381 HOST_WIDE_INT plus_one;
4383 if (mips_int_order_operand_ok_p (*code, *cmp1))
4386 if (CONST_INT_P (*cmp1))
4390 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4391 if (INTVAL (*cmp1) < plus_one)
4394 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4400 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4404 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4415 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4416 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4417 is nonnull, it's OK to set TARGET to the inverse of the result and
4418 flip *INVERT_PTR instead. */
4421 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4422 rtx target, rtx cmp0, rtx cmp1)
4424 enum machine_mode mode;
4426 /* First see if there is a MIPS instruction that can do this operation.
4427 If not, try doing the same for the inverse operation. If that also
4428 fails, force CMP1 into a register and try again. */
4429 mode = GET_MODE (cmp0);
4430 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4431 mips_emit_binary (code, target, cmp0, cmp1);
4434 enum rtx_code inv_code = reverse_condition (code);
4435 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4437 cmp1 = force_reg (mode, cmp1);
4438 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4440 else if (invert_ptr == 0)
4444 inv_target = mips_force_binary (GET_MODE (target),
4445 inv_code, cmp0, cmp1);
4446 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4450 *invert_ptr = !*invert_ptr;
4451 mips_emit_binary (inv_code, target, cmp0, cmp1);
4456 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4457 The register will have the same mode as CMP0. */
4460 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4462 if (cmp1 == const0_rtx)
4465 if (uns_arith_operand (cmp1, VOIDmode))
4466 return expand_binop (GET_MODE (cmp0), xor_optab,
4467 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4469 return expand_binop (GET_MODE (cmp0), sub_optab,
4470 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4473 /* Convert *CODE into a code that can be used in a floating-point
4474 scc instruction (C.cond.fmt). Return true if the values of
4475 the condition code registers will be inverted, with 0 indicating
4476 that the condition holds. */
4479 mips_reversed_fp_cond (enum rtx_code *code)
4486 *code = reverse_condition_maybe_unordered (*code);
4494 /* Convert a comparison into something that can be used in a branch or
4495 conditional move. On entry, *OP0 and *OP1 are the values being
4496 compared and *CODE is the code used to compare them.
4498 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4499 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4500 otherwise any standard branch condition can be used. The standard branch
4503 - EQ or NE between two registers.
4504 - any comparison between a register and zero. */
4507 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4512 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4514 if (!need_eq_ne_p && *op1 == const0_rtx)
4516 else if (*code == EQ || *code == NE)
4520 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4524 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4528 /* The comparison needs a separate scc instruction. Store the
4529 result of the scc in *OP0 and compare it against zero. */
4530 bool invert = false;
4531 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4532 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4533 *code = (invert ? EQ : NE);
4537 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4539 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4540 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4546 enum rtx_code cmp_code;
4548 /* Floating-point tests use a separate C.cond.fmt comparison to
4549 set a condition code register. The branch or conditional move
4550 will then compare that register against zero.
4552 Set CMP_CODE to the code of the comparison instruction and
4553 *CODE to the code that the branch or move should use. */
4555 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4557 ? gen_reg_rtx (CCmode)
4558 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4560 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4564 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4565 and OPERAND[3]. Store the result in OPERANDS[0].
4567 On 64-bit targets, the mode of the comparison and target will always be
4568 SImode, thus possibly narrower than that of the comparison's operands. */
4571 mips_expand_scc (rtx operands[])
4573 rtx target = operands[0];
4574 enum rtx_code code = GET_CODE (operands[1]);
4575 rtx op0 = operands[2];
4576 rtx op1 = operands[3];
4578 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4580 if (code == EQ || code == NE)
4583 && reg_imm10_operand (op1, GET_MODE (op1)))
4584 mips_emit_binary (code, target, op0, op1);
4587 rtx zie = mips_zero_if_equal (op0, op1);
4588 mips_emit_binary (code, target, zie, const0_rtx);
4592 mips_emit_int_order_test (code, 0, target, op0, op1);
4595 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4596 CODE and jump to OPERANDS[3] if the condition holds. */
4599 mips_expand_conditional_branch (rtx *operands)
4601 enum rtx_code code = GET_CODE (operands[0]);
4602 rtx op0 = operands[1];
4603 rtx op1 = operands[2];
4606 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4607 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4608 emit_jump_insn (gen_condjump (condition, operands[3]));
4613 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4614 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4617 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4618 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4623 reversed_p = mips_reversed_fp_cond (&cond);
4624 cmp_result = gen_reg_rtx (CCV2mode);
4625 emit_insn (gen_scc_ps (cmp_result,
4626 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4628 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4631 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4635 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4636 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4639 mips_expand_conditional_move (rtx *operands)
4642 enum rtx_code code = GET_CODE (operands[1]);
4643 rtx op0 = XEXP (operands[1], 0);
4644 rtx op1 = XEXP (operands[1], 1);
4646 mips_emit_compare (&code, &op0, &op1, true);
4647 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4648 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4649 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4650 operands[2], operands[3])));
4653 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4656 mips_expand_conditional_trap (rtx comparison)
4659 enum machine_mode mode;
4662 /* MIPS conditional trap instructions don't have GT or LE flavors,
4663 so we must swap the operands and convert to LT and GE respectively. */
4664 code = GET_CODE (comparison);
4671 code = swap_condition (code);
4672 op0 = XEXP (comparison, 1);
4673 op1 = XEXP (comparison, 0);
4677 op0 = XEXP (comparison, 0);
4678 op1 = XEXP (comparison, 1);
4682 mode = GET_MODE (XEXP (comparison, 0));
4683 op0 = force_reg (mode, op0);
4684 if (!arith_operand (op1, mode))
4685 op1 = force_reg (mode, op1);
4687 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4688 gen_rtx_fmt_ee (code, mode, op0, op1),
4692 /* Initialize *CUM for a call to a function of type FNTYPE. */
4695 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4697 memset (cum, 0, sizeof (*cum));
4698 cum->prototype = (fntype && prototype_p (fntype));
4699 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4702 /* Fill INFO with information about a single argument. CUM is the
4703 cumulative state for earlier arguments. MODE is the mode of this
4704 argument and TYPE is its type (if known). NAMED is true if this
4705 is a named (fixed) argument rather than a variable one. */
4708 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4709 enum machine_mode mode, const_tree type, bool named)
4711 bool doubleword_aligned_p;
4712 unsigned int num_bytes, num_words, max_regs;
4714 /* Work out the size of the argument. */
4715 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4716 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4718 /* Decide whether it should go in a floating-point register, assuming
4719 one is free. Later code checks for availability.
4721 The checks against UNITS_PER_FPVALUE handle the soft-float and
4722 single-float cases. */
4726 /* The EABI conventions have traditionally been defined in terms
4727 of TYPE_MODE, regardless of the actual type. */
4728 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4729 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4730 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4735 /* Only leading floating-point scalars are passed in
4736 floating-point registers. We also handle vector floats the same
4737 say, which is OK because they are not covered by the standard ABI. */
4738 info->fpr_p = (!cum->gp_reg_found
4739 && cum->arg_number < 2
4741 || SCALAR_FLOAT_TYPE_P (type)
4742 || VECTOR_FLOAT_TYPE_P (type))
4743 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4744 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4745 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4750 /* Scalar, complex and vector floating-point types are passed in
4751 floating-point registers, as long as this is a named rather
4752 than a variable argument. */
4753 info->fpr_p = (named
4754 && (type == 0 || FLOAT_TYPE_P (type))
4755 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4756 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4757 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
4758 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4760 /* ??? According to the ABI documentation, the real and imaginary
4761 parts of complex floats should be passed in individual registers.
4762 The real and imaginary parts of stack arguments are supposed
4763 to be contiguous and there should be an extra word of padding
4766 This has two problems. First, it makes it impossible to use a
4767 single "void *" va_list type, since register and stack arguments
4768 are passed differently. (At the time of writing, MIPSpro cannot
4769 handle complex float varargs correctly.) Second, it's unclear
4770 what should happen when there is only one register free.
4772 For now, we assume that named complex floats should go into FPRs
4773 if there are two FPRs free, otherwise they should be passed in the
4774 same way as a struct containing two floats. */
4776 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4777 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4779 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4780 info->fpr_p = false;
4790 /* See whether the argument has doubleword alignment. */
4791 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
4794 /* Set REG_OFFSET to the register count we're interested in.
4795 The EABI allocates the floating-point registers separately,
4796 but the other ABIs allocate them like integer registers. */
4797 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4801 /* Advance to an even register if the argument is doubleword-aligned. */
4802 if (doubleword_aligned_p)
4803 info->reg_offset += info->reg_offset & 1;
4805 /* Work out the offset of a stack argument. */
4806 info->stack_offset = cum->stack_words;
4807 if (doubleword_aligned_p)
4808 info->stack_offset += info->stack_offset & 1;
4810 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4812 /* Partition the argument between registers and stack. */
4813 info->reg_words = MIN (num_words, max_regs);
4814 info->stack_words = num_words - info->reg_words;
4817 /* INFO describes a register argument that has the normal format for the
4818 argument's mode. Return the register it uses, assuming that FPRs are
4819 available if HARD_FLOAT_P. */
4822 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
4824 if (!info->fpr_p || !hard_float_p)
4825 return GP_ARG_FIRST + info->reg_offset;
4826 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
4827 /* In o32, the second argument is always passed in $f14
4828 for TARGET_DOUBLE_FLOAT, regardless of whether the
4829 first argument was a word or doubleword. */
4830 return FP_ARG_FIRST + 2;
4832 return FP_ARG_FIRST + info->reg_offset;
4835 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4838 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
4840 return !TARGET_OLDABI;
4843 /* Implement TARGET_FUNCTION_ARG. */
4846 mips_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4847 const_tree type, bool named)
4849 struct mips_arg_info info;
4851 /* We will be called with a mode of VOIDmode after the last argument
4852 has been seen. Whatever we return will be passed to the call expander.
4853 If we need a MIPS16 fp_code, return a REG with the code stored as
4855 if (mode == VOIDmode)
4857 if (TARGET_MIPS16 && cum->fp_code != 0)
4858 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4863 mips_get_arg_info (&info, cum, mode, type, named);
4865 /* Return straight away if the whole argument is passed on the stack. */
4866 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4869 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4870 contains a double in its entirety, then that 64-bit chunk is passed
4871 in a floating-point register. */
4873 && TARGET_HARD_FLOAT
4876 && TREE_CODE (type) == RECORD_TYPE
4877 && TYPE_SIZE_UNIT (type)
4878 && host_integerp (TYPE_SIZE_UNIT (type), 1))
4882 /* First check to see if there is any such field. */
4883 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
4884 if (TREE_CODE (field) == FIELD_DECL
4885 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4886 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4887 && host_integerp (bit_position (field), 0)
4888 && int_bit_position (field) % BITS_PER_WORD == 0)
4893 /* Now handle the special case by returning a PARALLEL
4894 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4895 chunks are passed in registers. */
4897 HOST_WIDE_INT bitpos;
4900 /* assign_parms checks the mode of ENTRY_PARM, so we must
4901 use the actual mode here. */
4902 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4905 field = TYPE_FIELDS (type);
4906 for (i = 0; i < info.reg_words; i++)
4910 for (; field; field = DECL_CHAIN (field))
4911 if (TREE_CODE (field) == FIELD_DECL
4912 && int_bit_position (field) >= bitpos)
4916 && int_bit_position (field) == bitpos
4917 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
4918 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4919 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4921 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4924 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4925 GEN_INT (bitpos / BITS_PER_UNIT));
4927 bitpos += BITS_PER_WORD;
4933 /* Handle the n32/n64 conventions for passing complex floating-point
4934 arguments in FPR pairs. The real part goes in the lower register
4935 and the imaginary part goes in the upper register. */
4938 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
4941 enum machine_mode inner;
4944 inner = GET_MODE_INNER (mode);
4945 regno = FP_ARG_FIRST + info.reg_offset;
4946 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
4948 /* Real part in registers, imaginary part on stack. */
4949 gcc_assert (info.stack_words == info.reg_words);
4950 return gen_rtx_REG (inner, regno);
4954 gcc_assert (info.stack_words == 0);
4955 real = gen_rtx_EXPR_LIST (VOIDmode,
4956 gen_rtx_REG (inner, regno),
4958 imag = gen_rtx_EXPR_LIST (VOIDmode,
4960 regno + info.reg_words / 2),
4961 GEN_INT (GET_MODE_SIZE (inner)));
4962 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
4966 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
4969 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4972 mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4973 const_tree type, bool named)
4975 struct mips_arg_info info;
4977 mips_get_arg_info (&info, cum, mode, type, named);
4980 cum->gp_reg_found = true;
4982 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4983 an explanation of what this code does. It assumes that we're using
4984 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4986 if (cum->arg_number < 2 && info.fpr_p)
4987 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
4989 /* Advance the register count. This has the effect of setting
4990 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4991 argument required us to skip the final GPR and pass the whole
4992 argument on the stack. */
4993 if (mips_abi != ABI_EABI || !info.fpr_p)
4994 cum->num_gprs = info.reg_offset + info.reg_words;
4995 else if (info.reg_words > 0)
4996 cum->num_fprs += MAX_FPRS_PER_FMT;
4998 /* Advance the stack word count. */
4999 if (info.stack_words > 0)
5000 cum->stack_words = info.stack_offset + info.stack_words;
5005 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5008 mips_arg_partial_bytes (CUMULATIVE_ARGS *cum,
5009 enum machine_mode mode, tree type, bool named)
5011 struct mips_arg_info info;
5013 mips_get_arg_info (&info, cum, mode, type, named);
5014 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5017 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5018 least PARM_BOUNDARY bits of alignment, but will be given anything up
5019 to STACK_BOUNDARY bits if the type requires it. */
5022 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5024 unsigned int alignment;
5026 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5027 if (alignment < PARM_BOUNDARY)
5028 alignment = PARM_BOUNDARY;
5029 if (alignment > STACK_BOUNDARY)
5030 alignment = STACK_BOUNDARY;
5034 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5035 upward rather than downward. In other words, return true if the
5036 first byte of the stack slot has useful data, false if the last
5040 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5042 /* On little-endian targets, the first byte of every stack argument
5043 is passed in the first byte of the stack slot. */
5044 if (!BYTES_BIG_ENDIAN)
5047 /* Otherwise, integral types are padded downward: the last byte of a
5048 stack argument is passed in the last byte of the stack slot. */
5050 ? (INTEGRAL_TYPE_P (type)
5051 || POINTER_TYPE_P (type)
5052 || FIXED_POINT_TYPE_P (type))
5053 : (SCALAR_INT_MODE_P (mode)
5054 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5057 /* Big-endian o64 pads floating-point arguments downward. */
5058 if (mips_abi == ABI_O64)
5059 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5062 /* Other types are padded upward for o32, o64, n32 and n64. */
5063 if (mips_abi != ABI_EABI)
5066 /* Arguments smaller than a stack slot are padded downward. */
5067 if (mode != BLKmode)
5068 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5070 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5073 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5074 if the least significant byte of the register has useful data. Return
5075 the opposite if the most significant byte does. */
5078 mips_pad_reg_upward (enum machine_mode mode, tree type)
5080 /* No shifting is required for floating-point arguments. */
5081 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5082 return !BYTES_BIG_ENDIAN;
5084 /* Otherwise, apply the same padding to register arguments as we do
5085 to stack arguments. */
5086 return mips_pad_arg_upward (mode, type);
5089 /* Return nonzero when an argument must be passed by reference. */
5092 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5093 enum machine_mode mode, const_tree type,
5094 bool named ATTRIBUTE_UNUSED)
5096 if (mips_abi == ABI_EABI)
5100 /* ??? How should SCmode be handled? */
5101 if (mode == DImode || mode == DFmode
5102 || mode == DQmode || mode == UDQmode
5103 || mode == DAmode || mode == UDAmode)
5106 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5107 return size == -1 || size > UNITS_PER_WORD;
5111 /* If we have a variable-sized parameter, we have no choice. */
5112 return targetm.calls.must_pass_in_stack (mode, type);
5116 /* Implement TARGET_CALLEE_COPIES. */
5119 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5120 enum machine_mode mode ATTRIBUTE_UNUSED,
5121 const_tree type ATTRIBUTE_UNUSED, bool named)
5123 return mips_abi == ABI_EABI && named;
5126 /* See whether VALTYPE is a record whose fields should be returned in
5127 floating-point registers. If so, return the number of fields and
5128 list them in FIELDS (which should have two elements). Return 0
5131 For n32 & n64, a structure with one or two fields is returned in
5132 floating-point registers as long as every field has a floating-point
5136 mips_fpr_return_fields (const_tree valtype, tree *fields)
5144 if (TREE_CODE (valtype) != RECORD_TYPE)
5148 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5150 if (TREE_CODE (field) != FIELD_DECL)
5153 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5159 fields[i++] = field;
5164 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5165 a value in the most significant part of $2/$3 if:
5167 - the target is big-endian;
5169 - the value has a structure or union type (we generalize this to
5170 cover aggregates from other languages too); and
5172 - the structure is not returned in floating-point registers. */
5175 mips_return_in_msb (const_tree valtype)
5179 return (TARGET_NEWABI
5180 && TARGET_BIG_ENDIAN
5181 && AGGREGATE_TYPE_P (valtype)
5182 && mips_fpr_return_fields (valtype, fields) == 0);
5185 /* Return true if the function return value MODE will get returned in a
5186 floating-point register. */
5189 mips_return_mode_in_fpr_p (enum machine_mode mode)
5191 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5192 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
5193 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5194 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5197 /* Return the representation of an FPR return register when the
5198 value being returned in FP_RETURN has mode VALUE_MODE and the
5199 return type itself has mode TYPE_MODE. On NewABI targets,
5200 the two modes may be different for structures like:
5202 struct __attribute__((packed)) foo { float f; }
5204 where we return the SFmode value of "f" in FP_RETURN, but where
5205 the structure itself has mode BLKmode. */
5208 mips_return_fpr_single (enum machine_mode type_mode,
5209 enum machine_mode value_mode)
5213 x = gen_rtx_REG (value_mode, FP_RETURN);
5214 if (type_mode != value_mode)
5216 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5217 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5222 /* Return a composite value in a pair of floating-point registers.
5223 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5224 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5227 For n32 & n64, $f0 always holds the first value and $f2 the second.
5228 Otherwise the values are packed together as closely as possible. */
5231 mips_return_fpr_pair (enum machine_mode mode,
5232 enum machine_mode mode1, HOST_WIDE_INT offset1,
5233 enum machine_mode mode2, HOST_WIDE_INT offset2)
5237 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5238 return gen_rtx_PARALLEL
5241 gen_rtx_EXPR_LIST (VOIDmode,
5242 gen_rtx_REG (mode1, FP_RETURN),
5244 gen_rtx_EXPR_LIST (VOIDmode,
5245 gen_rtx_REG (mode2, FP_RETURN + inc),
5246 GEN_INT (offset2))));
5250 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5251 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5252 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5255 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5256 enum machine_mode mode)
5264 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5265 func = fn_decl_or_type;
5269 mode = TYPE_MODE (valtype);
5270 unsigned_p = TYPE_UNSIGNED (valtype);
5272 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5273 return values, promote the mode here too. */
5274 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5276 /* Handle structures whose fields are returned in $f0/$f2. */
5277 switch (mips_fpr_return_fields (valtype, fields))
5280 return mips_return_fpr_single (mode,
5281 TYPE_MODE (TREE_TYPE (fields[0])));
5284 return mips_return_fpr_pair (mode,
5285 TYPE_MODE (TREE_TYPE (fields[0])),
5286 int_byte_position (fields[0]),
5287 TYPE_MODE (TREE_TYPE (fields[1])),
5288 int_byte_position (fields[1]));
5291 /* If a value is passed in the most significant part of a register, see
5292 whether we have to round the mode up to a whole number of words. */
5293 if (mips_return_in_msb (valtype))
5295 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5296 if (size % UNITS_PER_WORD != 0)
5298 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5299 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5303 /* For EABI, the class of return register depends entirely on MODE.
5304 For example, "struct { some_type x; }" and "union { some_type x; }"
5305 are returned in the same way as a bare "some_type" would be.
5306 Other ABIs only use FPRs for scalar, complex or vector types. */
5307 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5308 return gen_rtx_REG (mode, GP_RETURN);
5313 /* Handle long doubles for n32 & n64. */
5315 return mips_return_fpr_pair (mode,
5317 DImode, GET_MODE_SIZE (mode) / 2);
5319 if (mips_return_mode_in_fpr_p (mode))
5321 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5322 return mips_return_fpr_pair (mode,
5323 GET_MODE_INNER (mode), 0,
5324 GET_MODE_INNER (mode),
5325 GET_MODE_SIZE (mode) / 2);
5327 return gen_rtx_REG (mode, FP_RETURN);
5331 return gen_rtx_REG (mode, GP_RETURN);
5334 /* Implement TARGET_FUNCTION_VALUE. */
5337 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5338 bool outgoing ATTRIBUTE_UNUSED)
5340 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5343 /* Implement TARGET_LIBCALL_VALUE. */
5346 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5348 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5351 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5353 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5354 Currently, R2 and F0 are only implemented here (C has no complex type). */
5357 mips_function_value_regno_p (const unsigned int regno)
5359 if (regno == GP_RETURN
5360 || regno == FP_RETURN
5361 || (LONG_DOUBLE_TYPE_SIZE == 128
5362 && FP_RETURN != GP_RETURN
5363 && regno == FP_RETURN + 2))
5369 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5370 all BLKmode objects are returned in memory. Under the n32, n64
5371 and embedded ABIs, small structures are returned in a register.
5372 Objects with varying size must still be returned in memory, of
5376 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5378 return (TARGET_OLDABI
5379 ? TYPE_MODE (type) == BLKmode
5380 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5383 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5386 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5387 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5390 CUMULATIVE_ARGS local_cum;
5391 int gp_saved, fp_saved;
5393 /* The caller has advanced CUM up to, but not beyond, the last named
5394 argument. Advance a local copy of CUM past the last "real" named
5395 argument, to find out how many registers are left over. */
5397 mips_function_arg_advance (&local_cum, mode, type, true);
5399 /* Found out how many registers we need to save. */
5400 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5401 fp_saved = (EABI_FLOAT_VARARGS_P
5402 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5411 ptr = plus_constant (virtual_incoming_args_rtx,
5412 REG_PARM_STACK_SPACE (cfun->decl)
5413 - gp_saved * UNITS_PER_WORD);
5414 mem = gen_frame_mem (BLKmode, ptr);
5415 set_mem_alias_set (mem, get_varargs_alias_set ());
5417 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5422 /* We can't use move_block_from_reg, because it will use
5424 enum machine_mode mode;
5427 /* Set OFF to the offset from virtual_incoming_args_rtx of
5428 the first float register. The FP save area lies below
5429 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5430 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5431 off -= fp_saved * UNITS_PER_FPREG;
5433 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5435 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5436 i += MAX_FPRS_PER_FMT)
5440 ptr = plus_constant (virtual_incoming_args_rtx, off);
5441 mem = gen_frame_mem (mode, ptr);
5442 set_mem_alias_set (mem, get_varargs_alias_set ());
5443 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5444 off += UNITS_PER_HWFPVALUE;
5448 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5449 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5450 + fp_saved * UNITS_PER_FPREG);
5453 /* Implement TARGET_BUILTIN_VA_LIST. */
5456 mips_build_builtin_va_list (void)
5458 if (EABI_FLOAT_VARARGS_P)
5460 /* We keep 3 pointers, and two offsets.
5462 Two pointers are to the overflow area, which starts at the CFA.
5463 One of these is constant, for addressing into the GPR save area
5464 below it. The other is advanced up the stack through the
5467 The third pointer is to the bottom of the GPR save area.
5468 Since the FPR save area is just below it, we can address
5469 FPR slots off this pointer.
5471 We also keep two one-byte offsets, which are to be subtracted
5472 from the constant pointers to yield addresses in the GPR and
5473 FPR save areas. These are downcounted as float or non-float
5474 arguments are used, and when they get to zero, the argument
5475 must be obtained from the overflow region. */
5476 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5479 record = lang_hooks.types.make_type (RECORD_TYPE);
5481 f_ovfl = build_decl (BUILTINS_LOCATION,
5482 FIELD_DECL, get_identifier ("__overflow_argptr"),
5484 f_gtop = build_decl (BUILTINS_LOCATION,
5485 FIELD_DECL, get_identifier ("__gpr_top"),
5487 f_ftop = build_decl (BUILTINS_LOCATION,
5488 FIELD_DECL, get_identifier ("__fpr_top"),
5490 f_goff = build_decl (BUILTINS_LOCATION,
5491 FIELD_DECL, get_identifier ("__gpr_offset"),
5492 unsigned_char_type_node);
5493 f_foff = build_decl (BUILTINS_LOCATION,
5494 FIELD_DECL, get_identifier ("__fpr_offset"),
5495 unsigned_char_type_node);
5496 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5497 warn on every user file. */
5498 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5499 array = build_array_type (unsigned_char_type_node,
5500 build_index_type (index));
5501 f_res = build_decl (BUILTINS_LOCATION,
5502 FIELD_DECL, get_identifier ("__reserved"), array);
5504 DECL_FIELD_CONTEXT (f_ovfl) = record;
5505 DECL_FIELD_CONTEXT (f_gtop) = record;
5506 DECL_FIELD_CONTEXT (f_ftop) = record;
5507 DECL_FIELD_CONTEXT (f_goff) = record;
5508 DECL_FIELD_CONTEXT (f_foff) = record;
5509 DECL_FIELD_CONTEXT (f_res) = record;
5511 TYPE_FIELDS (record) = f_ovfl;
5512 DECL_CHAIN (f_ovfl) = f_gtop;
5513 DECL_CHAIN (f_gtop) = f_ftop;
5514 DECL_CHAIN (f_ftop) = f_goff;
5515 DECL_CHAIN (f_goff) = f_foff;
5516 DECL_CHAIN (f_foff) = f_res;
5518 layout_type (record);
5521 else if (TARGET_IRIX6)
5522 /* On IRIX 6, this type is 'char *'. */
5523 return build_pointer_type (char_type_node);
5525 /* Otherwise, we use 'void *'. */
5526 return ptr_type_node;
5529 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5532 mips_va_start (tree valist, rtx nextarg)
5534 if (EABI_FLOAT_VARARGS_P)
5536 const CUMULATIVE_ARGS *cum;
5537 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5538 tree ovfl, gtop, ftop, goff, foff;
5540 int gpr_save_area_size;
5541 int fpr_save_area_size;
5544 cum = &crtl->args.info;
5546 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5548 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5550 f_ovfl = TYPE_FIELDS (va_list_type_node);
5551 f_gtop = DECL_CHAIN (f_ovfl);
5552 f_ftop = DECL_CHAIN (f_gtop);
5553 f_goff = DECL_CHAIN (f_ftop);
5554 f_foff = DECL_CHAIN (f_goff);
5556 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5558 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5560 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5562 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5564 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5567 /* Emit code to initialize OVFL, which points to the next varargs
5568 stack argument. CUM->STACK_WORDS gives the number of stack
5569 words used by named arguments. */
5570 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5571 if (cum->stack_words > 0)
5572 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t,
5573 size_int (cum->stack_words * UNITS_PER_WORD));
5574 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5575 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5577 /* Emit code to initialize GTOP, the top of the GPR save area. */
5578 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5579 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5580 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5582 /* Emit code to initialize FTOP, the top of the FPR save area.
5583 This address is gpr_save_area_bytes below GTOP, rounded
5584 down to the next fp-aligned boundary. */
5585 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5586 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5587 fpr_offset &= -UNITS_PER_FPVALUE;
5589 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t,
5590 size_int (-fpr_offset));
5591 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5592 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5594 /* Emit code to initialize GOFF, the offset from GTOP of the
5595 next GPR argument. */
5596 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5597 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5598 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5600 /* Likewise emit code to initialize FOFF, the offset from FTOP
5601 of the next FPR argument. */
5602 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5603 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5604 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5608 nextarg = plus_constant (nextarg, -cfun->machine->varargs_size);
5609 std_expand_builtin_va_start (valist, nextarg);
5613 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5616 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5622 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5624 type = build_pointer_type (type);
5626 if (!EABI_FLOAT_VARARGS_P)
5627 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5630 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5631 tree ovfl, top, off, align;
5632 HOST_WIDE_INT size, rsize, osize;
5635 f_ovfl = TYPE_FIELDS (va_list_type_node);
5636 f_gtop = DECL_CHAIN (f_ovfl);
5637 f_ftop = DECL_CHAIN (f_gtop);
5638 f_goff = DECL_CHAIN (f_ftop);
5639 f_foff = DECL_CHAIN (f_goff);
5643 TOP be the top of the GPR or FPR save area;
5644 OFF be the offset from TOP of the next register;
5645 ADDR_RTX be the address of the argument;
5646 SIZE be the number of bytes in the argument type;
5647 RSIZE be the number of bytes used to store the argument
5648 when it's in the register save area; and
5649 OSIZE be the number of bytes used to store it when it's
5650 in the stack overflow area.
5652 The code we want is:
5654 1: off &= -rsize; // round down
5657 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5662 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5663 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5667 [1] and [9] can sometimes be optimized away. */
5669 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5671 size = int_size_in_bytes (type);
5673 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5674 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5676 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5677 unshare_expr (valist), f_ftop, NULL_TREE);
5678 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5679 unshare_expr (valist), f_foff, NULL_TREE);
5681 /* When va_start saves FPR arguments to the stack, each slot
5682 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5683 argument's precision. */
5684 rsize = UNITS_PER_HWFPVALUE;
5686 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5687 (= PARM_BOUNDARY bits). This can be different from RSIZE
5690 (1) On 32-bit targets when TYPE is a structure such as:
5692 struct s { float f; };
5694 Such structures are passed in paired FPRs, so RSIZE
5695 will be 8 bytes. However, the structure only takes
5696 up 4 bytes of memory, so OSIZE will only be 4.
5698 (2) In combinations such as -mgp64 -msingle-float
5699 -fshort-double. Doubles passed in registers will then take
5700 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5701 stack take up UNITS_PER_WORD bytes. */
5702 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
5706 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
5707 unshare_expr (valist), f_gtop, NULL_TREE);
5708 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
5709 unshare_expr (valist), f_goff, NULL_TREE);
5710 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5711 if (rsize > UNITS_PER_WORD)
5713 /* [1] Emit code for: off &= -rsize. */
5714 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
5715 build_int_cst (TREE_TYPE (off), -rsize));
5716 gimplify_assign (unshare_expr (off), t, pre_p);
5721 /* [2] Emit code to branch if off == 0. */
5722 t = build2 (NE_EXPR, boolean_type_node, off,
5723 build_int_cst (TREE_TYPE (off), 0));
5724 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
5726 /* [5] Emit code for: off -= rsize. We do this as a form of
5727 post-decrement not available to C. */
5728 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
5729 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
5731 /* [4] Emit code for:
5732 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5733 t = fold_convert (sizetype, t);
5734 t = fold_build1 (NEGATE_EXPR, sizetype, t);
5735 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t);
5736 if (BYTES_BIG_ENDIAN && rsize > size)
5738 u = size_int (rsize - size);
5739 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5741 COND_EXPR_THEN (addr) = t;
5743 if (osize > UNITS_PER_WORD)
5745 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5746 u = size_int (osize - 1);
5747 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl),
5748 unshare_expr (ovfl), u);
5749 t = fold_convert (sizetype, t);
5750 u = size_int (-osize);
5751 t = build2 (BIT_AND_EXPR, sizetype, t, u);
5752 t = fold_convert (TREE_TYPE (ovfl), t);
5753 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
5754 unshare_expr (ovfl), t);
5759 /* [10, 11] Emit code for:
5760 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5762 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
5763 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
5764 if (BYTES_BIG_ENDIAN && osize > size)
5766 u = size_int (osize - size);
5767 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u);
5770 /* String [9] and [10, 11] together. */
5772 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
5773 COND_EXPR_ELSE (addr) = t;
5775 addr = fold_convert (build_pointer_type (type), addr);
5776 addr = build_va_arg_indirect_ref (addr);
5780 addr = build_va_arg_indirect_ref (addr);
5785 /* Start a definition of function NAME. MIPS16_P indicates whether the
5786 function contains MIPS16 code. */
5789 mips_start_function_definition (const char *name, bool mips16_p)
5792 fprintf (asm_out_file, "\t.set\tmips16\n");
5794 fprintf (asm_out_file, "\t.set\tnomips16\n");
5796 if (!flag_inhibit_size_directive)
5798 fputs ("\t.ent\t", asm_out_file);
5799 assemble_name (asm_out_file, name);
5800 fputs ("\n", asm_out_file);
5803 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
5805 /* Start the definition proper. */
5806 assemble_name (asm_out_file, name);
5807 fputs (":\n", asm_out_file);
5810 /* End a function definition started by mips_start_function_definition. */
5813 mips_end_function_definition (const char *name)
5815 if (!flag_inhibit_size_directive)
5817 fputs ("\t.end\t", asm_out_file);
5818 assemble_name (asm_out_file, name);
5819 fputs ("\n", asm_out_file);
5823 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5826 mips_ok_for_lazy_binding_p (rtx x)
5828 return (TARGET_USE_GOT
5829 && GET_CODE (x) == SYMBOL_REF
5830 && !SYMBOL_REF_BIND_NOW_P (x)
5831 && !mips_symbol_binds_local_p (x));
5834 /* Load function address ADDR into register DEST. TYPE is as for
5835 mips_expand_call. Return true if we used an explicit lazy-binding
5839 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
5841 /* If we're generating PIC, and this call is to a global function,
5842 try to allow its address to be resolved lazily. This isn't
5843 possible for sibcalls when $gp is call-saved because the value
5844 of $gp on entry to the stub would be our caller's gp, not ours. */
5845 if (TARGET_EXPLICIT_RELOCS
5846 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
5847 && mips_ok_for_lazy_binding_p (addr))
5849 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
5850 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
5855 mips_emit_move (dest, addr);
5860 /* Each locally-defined hard-float MIPS16 function has a local symbol
5861 associated with it. This hash table maps the function symbol (FUNC)
5862 to the local symbol (LOCAL). */
5863 struct GTY(()) mips16_local_alias {
5867 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
5869 /* Hash table callbacks for mips16_local_aliases. */
5872 mips16_local_aliases_hash (const void *entry)
5874 const struct mips16_local_alias *alias;
5876 alias = (const struct mips16_local_alias *) entry;
5877 return htab_hash_string (XSTR (alias->func, 0));
5881 mips16_local_aliases_eq (const void *entry1, const void *entry2)
5883 const struct mips16_local_alias *alias1, *alias2;
5885 alias1 = (const struct mips16_local_alias *) entry1;
5886 alias2 = (const struct mips16_local_alias *) entry2;
5887 return rtx_equal_p (alias1->func, alias2->func);
5890 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5891 Return a local alias for it, creating a new one if necessary. */
5894 mips16_local_alias (rtx func)
5896 struct mips16_local_alias *alias, tmp_alias;
5899 /* Create the hash table if this is the first call. */
5900 if (mips16_local_aliases == NULL)
5901 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
5902 mips16_local_aliases_eq, NULL);
5904 /* Look up the function symbol, creating a new entry if need be. */
5905 tmp_alias.func = func;
5906 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
5907 gcc_assert (slot != NULL);
5909 alias = (struct mips16_local_alias *) *slot;
5912 const char *func_name, *local_name;
5915 /* Create a new SYMBOL_REF for the local symbol. The choice of
5916 __fn_local_* is based on the __fn_stub_* names that we've
5917 traditionally used for the non-MIPS16 stub. */
5918 func_name = targetm.strip_name_encoding (XSTR (func, 0));
5919 local_name = ACONCAT (("__fn_local_", func_name, NULL));
5920 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
5921 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
5923 /* Create a new structure to represent the mapping. */
5924 alias = ggc_alloc_mips16_local_alias ();
5926 alias->local = local;
5929 return alias->local;
5932 /* A chained list of functions for which mips16_build_call_stub has already
5933 generated a stub. NAME is the name of the function and FP_RET_P is true
5934 if the function returns a value in floating-point registers. */
5935 struct mips16_stub {
5936 struct mips16_stub *next;
5940 static struct mips16_stub *mips16_stubs;
5942 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5945 mips16_stub_function (const char *name)
5949 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
5950 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
5954 /* Return the two-character string that identifies floating-point
5955 return mode MODE in the name of a MIPS16 function stub. */
5958 mips16_call_stub_mode_suffix (enum machine_mode mode)
5962 else if (mode == DFmode)
5964 else if (mode == SCmode)
5966 else if (mode == DCmode)
5968 else if (mode == V2SFmode)
5974 /* Write instructions to move a 32-bit value between general register
5975 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5976 from GPREG to FPREG and 'f' to move in the opposite direction. */
5979 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5981 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5982 reg_names[gpreg], reg_names[fpreg]);
5985 /* Likewise for 64-bit values. */
5988 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
5991 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
5992 reg_names[gpreg], reg_names[fpreg]);
5993 else if (TARGET_FLOAT64)
5995 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
5996 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
5997 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
5998 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6002 /* Move the least-significant word. */
6003 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6004 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6005 /* ...then the most significant word. */
6006 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6007 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6011 /* Write out code to move floating-point arguments into or out of
6012 general registers. FP_CODE is the code describing which arguments
6013 are present (see the comment above the definition of CUMULATIVE_ARGS
6014 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6017 mips_output_args_xfer (int fp_code, char direction)
6019 unsigned int gparg, fparg, f;
6020 CUMULATIVE_ARGS cum;
6022 /* This code only works for o32 and o64. */
6023 gcc_assert (TARGET_OLDABI);
6025 mips_init_cumulative_args (&cum, NULL);
6027 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6029 enum machine_mode mode;
6030 struct mips_arg_info info;
6034 else if ((f & 3) == 2)
6039 mips_get_arg_info (&info, &cum, mode, NULL, true);
6040 gparg = mips_arg_regno (&info, false);
6041 fparg = mips_arg_regno (&info, true);
6044 mips_output_32bit_xfer (direction, gparg, fparg);
6046 mips_output_64bit_xfer (direction, gparg, fparg);
6048 mips_function_arg_advance (&cum, mode, NULL, true);
6052 /* Write a MIPS16 stub for the current function. This stub is used
6053 for functions which take arguments in the floating-point registers.
6054 It is normal-mode code that moves the floating-point arguments
6055 into the general registers and then jumps to the MIPS16 code. */
6058 mips16_build_function_stub (void)
6060 const char *fnname, *alias_name, *separator;
6061 char *secname, *stubname;
6066 /* Create the name of the stub, and its unique section. */
6067 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6068 alias = mips16_local_alias (symbol);
6070 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6071 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6072 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6073 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6075 /* Build a decl for the stub. */
6076 stubdecl = build_decl (BUILTINS_LOCATION,
6077 FUNCTION_DECL, get_identifier (stubname),
6078 build_function_type_list (void_type_node, NULL_TREE));
6079 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6080 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6081 RESULT_DECL, NULL_TREE, void_type_node);
6083 /* Output a comment. */
6084 fprintf (asm_out_file, "\t# Stub function for %s (",
6085 current_function_name ());
6087 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6089 fprintf (asm_out_file, "%s%s", separator,
6090 (f & 3) == 1 ? "float" : "double");
6093 fprintf (asm_out_file, ")\n");
6095 /* Start the function definition. */
6096 assemble_start_function (stubdecl, stubname);
6097 mips_start_function_definition (stubname, false);
6099 /* If generating pic2 code, either set up the global pointer or
6101 if (TARGET_ABICALLS_PIC2)
6103 if (TARGET_ABSOLUTE_ABICALLS)
6104 fprintf (asm_out_file, "\t.option\tpic0\n");
6107 output_asm_insn ("%(.cpload\t%^%)", NULL);
6108 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6109 target function is. Use a local GOT access when loading the
6110 symbol, to cut down on the number of unnecessary GOT entries
6111 for stubs that aren't needed. */
6112 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6117 /* Load the address of the MIPS16 function into $25. Do this first so
6118 that targets with coprocessor interlocks can use an MFC1 to fill the
6120 output_asm_insn ("la\t%^,%0", &symbol);
6122 /* Move the arguments from floating-point registers to general registers. */
6123 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6125 /* Jump to the MIPS16 function. */
6126 output_asm_insn ("jr\t%^", NULL);
6128 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6129 fprintf (asm_out_file, "\t.option\tpic2\n");
6131 mips_end_function_definition (stubname);
6133 /* If the linker needs to create a dynamic symbol for the target
6134 function, it will associate the symbol with the stub (which,
6135 unlike the target function, follows the proper calling conventions).
6136 It is therefore useful to have a local alias for the target function,
6137 so that it can still be identified as MIPS16 code. As an optimization,
6138 this symbol can also be used for indirect MIPS16 references from
6139 within this file. */
6140 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6142 switch_to_section (function_section (current_function_decl));
6145 /* The current function is a MIPS16 function that returns a value in an FPR.
6146 Copy the return value from its soft-float to its hard-float location.
6147 libgcc2 has special non-MIPS16 helper functions for each case. */
6150 mips16_copy_fpr_return_value (void)
6152 rtx fn, insn, retval;
6154 enum machine_mode return_mode;
6157 return_type = DECL_RESULT (current_function_decl);
6158 return_mode = DECL_MODE (return_type);
6160 name = ACONCAT (("__mips16_ret_",
6161 mips16_call_stub_mode_suffix (return_mode),
6163 fn = mips16_stub_function (name);
6165 /* The function takes arguments in $2 (and possibly $3), so calls
6166 to it cannot be lazily bound. */
6167 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6169 /* Model the call as something that takes the GPR return value as
6170 argument and returns an "updated" value. */
6171 retval = gen_rtx_REG (return_mode, GP_RETURN);
6172 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6173 const0_rtx, NULL_RTX, false);
6174 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6177 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6178 RETVAL is the location of the return value, or null if this is
6179 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6180 arguments and FP_CODE is the code built by mips_function_arg;
6181 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6183 There are three alternatives:
6185 - If a stub was needed, emit the call and return the call insn itself.
6187 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6188 to the new target and return null.
6190 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6193 A stub is needed for calls to functions that, in normal mode,
6194 receive arguments in FPRs or return values in FPRs. The stub
6195 copies the arguments from their soft-float positions to their
6196 hard-float positions, calls the real function, then copies the
6197 return value from its hard-float position to its soft-float
6200 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6201 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6202 automatically redirects the JAL to the stub, otherwise the JAL
6203 continues to call FN directly. */
6206 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6210 struct mips16_stub *l;
6213 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6214 we were invoked with the -msoft-float option. */
6215 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6218 /* Figure out whether the value might come back in a floating-point
6220 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6222 /* We don't need to do anything if there were no floating-point
6223 arguments and the value will not be returned in a floating-point
6225 if (fp_code == 0 && !fp_ret_p)
6228 /* We don't need to do anything if this is a call to a special
6229 MIPS16 support function. */
6231 if (mips16_stub_function_p (fn))
6234 /* This code will only work for o32 and o64 abis. The other ABI's
6235 require more sophisticated support. */
6236 gcc_assert (TARGET_OLDABI);
6238 /* If we're calling via a function pointer, use one of the magic
6239 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6240 Each stub expects the function address to arrive in register $2. */
6241 if (GET_CODE (fn) != SYMBOL_REF
6242 || !call_insn_operand (fn, VOIDmode))
6245 rtx stub_fn, insn, addr;
6248 /* If this is a locally-defined and locally-binding function,
6249 avoid the stub by calling the local alias directly. */
6250 if (mips16_local_function_p (fn))
6252 *fn_ptr = mips16_local_alias (fn);
6256 /* Create a SYMBOL_REF for the libgcc.a function. */
6258 sprintf (buf, "__mips16_call_stub_%s_%d",
6259 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6262 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6263 stub_fn = mips16_stub_function (buf);
6265 /* The function uses $2 as an argument, so calls to it
6266 cannot be lazily bound. */
6267 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6269 /* Load the target function into $2. */
6270 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6271 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6273 /* Emit the call. */
6274 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6275 args_size, NULL_RTX, lazy_p);
6277 /* Tell GCC that this call does indeed use the value of $2. */
6278 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6280 /* If we are handling a floating-point return value, we need to
6281 save $18 in the function prologue. Putting a note on the
6282 call will mean that df_regs_ever_live_p ($18) will be true if the
6283 call is not eliminated, and we can check that in the prologue
6286 CALL_INSN_FUNCTION_USAGE (insn) =
6287 gen_rtx_EXPR_LIST (VOIDmode,
6288 gen_rtx_CLOBBER (VOIDmode,
6289 gen_rtx_REG (word_mode, 18)),
6290 CALL_INSN_FUNCTION_USAGE (insn));
6295 /* We know the function we are going to call. If we have already
6296 built a stub, we don't need to do anything further. */
6297 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6298 for (l = mips16_stubs; l != NULL; l = l->next)
6299 if (strcmp (l->name, fnname) == 0)
6304 const char *separator;
6305 char *secname, *stubname;
6306 tree stubid, stubdecl;
6309 /* If the function does not return in FPRs, the special stub
6313 If the function does return in FPRs, the stub section is named
6314 .mips16.call.fp.FNNAME
6316 Build a decl for the stub. */
6317 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6319 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6321 stubid = get_identifier (stubname);
6322 stubdecl = build_decl (BUILTINS_LOCATION,
6323 FUNCTION_DECL, stubid,
6324 build_function_type_list (void_type_node,
6326 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6327 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6328 RESULT_DECL, NULL_TREE,
6331 /* Output a comment. */
6332 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6334 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6338 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6340 fprintf (asm_out_file, "%s%s", separator,
6341 (f & 3) == 1 ? "float" : "double");
6344 fprintf (asm_out_file, ")\n");
6346 /* Start the function definition. */
6347 assemble_start_function (stubdecl, stubname);
6348 mips_start_function_definition (stubname, false);
6352 /* Load the address of the MIPS16 function into $25. Do this
6353 first so that targets with coprocessor interlocks can use
6354 an MFC1 to fill the delay slot. */
6355 if (TARGET_EXPLICIT_RELOCS)
6357 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6358 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6361 output_asm_insn ("la\t%^,%0", &fn);
6364 /* Move the arguments from general registers to floating-point
6366 mips_output_args_xfer (fp_code, 't');
6370 /* Jump to the previously-loaded address. */
6371 output_asm_insn ("jr\t%^", NULL);
6375 /* Save the return address in $18 and call the non-MIPS16 function.
6376 The stub's caller knows that $18 might be clobbered, even though
6377 $18 is usually a call-saved register. */
6378 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6379 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6380 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6382 /* Move the result from floating-point registers to
6383 general registers. */
6384 switch (GET_MODE (retval))
6387 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6389 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6391 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6392 TARGET_LITTLE_ENDIAN
6393 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6395 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6397 /* On 64-bit targets, complex floats are returned in
6398 a single GPR, such that "sd" on a suitably-aligned
6399 target would store the value correctly. */
6400 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6401 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6402 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6403 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6404 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6405 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6406 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6407 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6408 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6409 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6410 reg_names[GP_RETURN],
6411 reg_names[GP_RETURN],
6412 reg_names[GP_RETURN + 1]);
6417 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6421 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6422 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6426 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6432 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6435 #ifdef ASM_DECLARE_FUNCTION_SIZE
6436 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6439 mips_end_function_definition (stubname);
6441 /* Record this stub. */
6442 l = XNEW (struct mips16_stub);
6443 l->name = xstrdup (fnname);
6444 l->fp_ret_p = fp_ret_p;
6445 l->next = mips16_stubs;
6449 /* If we expect a floating-point return value, but we've built a
6450 stub which does not expect one, then we're in trouble. We can't
6451 use the existing stub, because it won't handle the floating-point
6452 value. We can't build a new stub, because the linker won't know
6453 which stub to use for the various calls in this object file.
6454 Fortunately, this case is illegal, since it means that a function
6455 was declared in two different ways in a single compilation. */
6456 if (fp_ret_p && !l->fp_ret_p)
6457 error ("cannot handle inconsistent calls to %qs", fnname);
6459 if (retval == NULL_RTX)
6460 insn = gen_call_internal_direct (fn, args_size);
6462 insn = gen_call_value_internal_direct (retval, fn, args_size);
6463 insn = mips_emit_call_insn (insn, fn, fn, false);
6465 /* If we are calling a stub which handles a floating-point return
6466 value, we need to arrange to save $18 in the prologue. We do this
6467 by marking the function call as using the register. The prologue
6468 will later see that it is used, and emit code to save it. */
6470 CALL_INSN_FUNCTION_USAGE (insn) =
6471 gen_rtx_EXPR_LIST (VOIDmode,
6472 gen_rtx_CLOBBER (VOIDmode,
6473 gen_rtx_REG (word_mode, 18)),
6474 CALL_INSN_FUNCTION_USAGE (insn));
6479 /* Expand a call of type TYPE. RESULT is where the result will go (null
6480 for "call"s and "sibcall"s), ADDR is the address of the function,
6481 ARGS_SIZE is the size of the arguments and AUX is the value passed
6482 to us by mips_function_arg. LAZY_P is true if this call already
6483 involves a lazily-bound function address (such as when calling
6484 functions through a MIPS16 hard-float stub).
6486 Return the call itself. */
6489 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6490 rtx args_size, rtx aux, bool lazy_p)
6492 rtx orig_addr, pattern, insn;
6495 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6496 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6499 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6504 if (!call_insn_operand (addr, VOIDmode))
6506 if (type == MIPS_CALL_EPILOGUE)
6507 addr = MIPS_EPILOGUE_TEMP (Pmode);
6509 addr = gen_reg_rtx (Pmode);
6510 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6515 rtx (*fn) (rtx, rtx);
6517 if (type == MIPS_CALL_SIBCALL)
6518 fn = gen_sibcall_internal;
6520 fn = gen_call_internal;
6522 pattern = fn (addr, args_size);
6524 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6526 /* Handle return values created by mips_return_fpr_pair. */
6527 rtx (*fn) (rtx, rtx, rtx, rtx);
6530 if (type == MIPS_CALL_SIBCALL)
6531 fn = gen_sibcall_value_multiple_internal;
6533 fn = gen_call_value_multiple_internal;
6535 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6536 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6537 pattern = fn (reg1, addr, args_size, reg2);
6541 rtx (*fn) (rtx, rtx, rtx);
6543 if (type == MIPS_CALL_SIBCALL)
6544 fn = gen_sibcall_value_internal;
6546 fn = gen_call_value_internal;
6548 /* Handle return values created by mips_return_fpr_single. */
6549 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6550 result = XEXP (XVECEXP (result, 0, 0), 0);
6551 pattern = fn (result, addr, args_size);
6554 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6557 /* Split call instruction INSN into a $gp-clobbering call and
6558 (where necessary) an instruction to restore $gp from its save slot.
6559 CALL_PATTERN is the pattern of the new call. */
6562 mips_split_call (rtx insn, rtx call_pattern)
6564 emit_call_insn (call_pattern);
6565 if (!find_reg_note (insn, REG_NORETURN, 0))
6566 /* Pick a temporary register that is suitable for both MIPS16 and
6567 non-MIPS16 code. $4 and $5 are used for returning complex double
6568 values in soft-float code, so $6 is the first suitable candidate. */
6569 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6572 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6575 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6577 if (!TARGET_SIBCALLS)
6580 /* Interrupt handlers need special epilogue code and therefore can't
6582 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6585 /* We can't do a sibcall if the called function is a MIPS16 function
6586 because there is no direct "jx" instruction equivalent to "jalx" to
6587 switch the ISA mode. We only care about cases where the sibling
6588 and normal calls would both be direct. */
6590 && mips_use_mips16_mode_p (decl)
6591 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6594 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6595 functions could be MIPS16 ones unless an attribute explicitly tells
6597 if (TARGET_INTERLINK_MIPS16
6599 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6600 && !mips_nomips16_decl_p (decl)
6601 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6608 /* Emit code to move general operand SRC into condition-code
6609 register DEST given that SCRATCH is a scratch TFmode FPR.
6616 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6619 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6623 /* Change the source to SFmode. */
6625 src = adjust_address (src, SFmode, 0);
6626 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6627 src = gen_rtx_REG (SFmode, true_regnum (src));
6629 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6630 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6632 mips_emit_move (copy_rtx (fp1), src);
6633 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6634 emit_insn (gen_slt_sf (dest, fp2, fp1));
6637 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6638 Assume that the areas do not overlap. */
6641 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
6643 HOST_WIDE_INT offset, delta;
6644 unsigned HOST_WIDE_INT bits;
6646 enum machine_mode mode;
6649 /* Work out how many bits to move at a time. If both operands have
6650 half-word alignment, it is usually better to move in half words.
6651 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6652 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6653 Otherwise move word-sized chunks. */
6654 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
6655 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
6656 bits = BITS_PER_WORD / 2;
6658 bits = BITS_PER_WORD;
6660 mode = mode_for_size (bits, MODE_INT, 0);
6661 delta = bits / BITS_PER_UNIT;
6663 /* Allocate a buffer for the temporary registers. */
6664 regs = XALLOCAVEC (rtx, length / delta);
6666 /* Load as many BITS-sized chunks as possible. Use a normal load if
6667 the source has enough alignment, otherwise use left/right pairs. */
6668 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6670 regs[i] = gen_reg_rtx (mode);
6671 if (MEM_ALIGN (src) >= bits)
6672 mips_emit_move (regs[i], adjust_address (src, mode, offset));
6675 rtx part = adjust_address (src, BLKmode, offset);
6676 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0))
6681 /* Copy the chunks to the destination. */
6682 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
6683 if (MEM_ALIGN (dest) >= bits)
6684 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
6687 rtx part = adjust_address (dest, BLKmode, offset);
6688 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
6692 /* Mop up any left-over bytes. */
6693 if (offset < length)
6695 src = adjust_address (src, BLKmode, offset);
6696 dest = adjust_address (dest, BLKmode, offset);
6697 move_by_pieces (dest, src, length - offset,
6698 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
6702 /* Helper function for doing a loop-based block operation on memory
6703 reference MEM. Each iteration of the loop will operate on LENGTH
6706 Create a new base register for use within the loop and point it to
6707 the start of MEM. Create a new memory reference that uses this
6708 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6711 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
6712 rtx *loop_reg, rtx *loop_mem)
6714 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
6716 /* Although the new mem does not refer to a known location,
6717 it does keep up to LENGTH bytes of alignment. */
6718 *loop_mem = change_address (mem, BLKmode, *loop_reg);
6719 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
6722 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6723 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6724 the memory regions do not overlap. */
6727 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
6728 HOST_WIDE_INT bytes_per_iter)
6730 rtx label, src_reg, dest_reg, final_src, test;
6731 HOST_WIDE_INT leftover;
6733 leftover = length % bytes_per_iter;
6736 /* Create registers and memory references for use within the loop. */
6737 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
6738 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
6740 /* Calculate the value that SRC_REG should have after the last iteration
6742 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
6745 /* Emit the start of the loop. */
6746 label = gen_label_rtx ();
6749 /* Emit the loop body. */
6750 mips_block_move_straight (dest, src, bytes_per_iter);
6752 /* Move on to the next block. */
6753 mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter));
6754 mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter));
6756 /* Emit the loop condition. */
6757 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
6758 if (Pmode == DImode)
6759 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
6761 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
6763 /* Mop up any left-over bytes. */
6765 mips_block_move_straight (dest, src, leftover);
6768 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6769 memory reference SRC to memory reference DEST. */
6772 mips_expand_block_move (rtx dest, rtx src, rtx length)
6774 if (CONST_INT_P (length))
6776 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
6778 mips_block_move_straight (dest, src, INTVAL (length));
6783 mips_block_move_loop (dest, src, INTVAL (length),
6784 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
6791 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6794 mips_expand_synci_loop (rtx begin, rtx end)
6796 rtx inc, label, end_label, cmp_result, mask, length;
6798 /* Create end_label. */
6799 end_label = gen_label_rtx ();
6801 /* Check if begin equals end. */
6802 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
6803 emit_jump_insn (gen_condjump (cmp_result, end_label));
6805 /* Load INC with the cache line size (rdhwr INC,$1). */
6806 inc = gen_reg_rtx (Pmode);
6807 emit_insn (Pmode == SImode
6808 ? gen_rdhwr_synci_step_si (inc)
6809 : gen_rdhwr_synci_step_di (inc));
6811 /* Check if inc is 0. */
6812 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
6813 emit_jump_insn (gen_condjump (cmp_result, end_label));
6815 /* Calculate mask. */
6816 mask = mips_force_unary (Pmode, NEG, inc);
6818 /* Mask out begin by mask. */
6819 begin = mips_force_binary (Pmode, AND, begin, mask);
6821 /* Calculate length. */
6822 length = mips_force_binary (Pmode, MINUS, end, begin);
6824 /* Loop back to here. */
6825 label = gen_label_rtx ();
6828 emit_insn (gen_synci (begin));
6830 /* Update length. */
6831 mips_emit_binary (MINUS, length, length, inc);
6834 mips_emit_binary (PLUS, begin, begin, inc);
6836 /* Check if length is greater than 0. */
6837 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
6838 emit_jump_insn (gen_condjump (cmp_result, label));
6840 emit_label (end_label);
6843 /* Expand a QI or HI mode atomic memory operation.
6845 GENERATOR contains a pointer to the gen_* function that generates
6846 the SI mode underlying atomic operation using masks that we
6849 RESULT is the return register for the operation. Its value is NULL
6852 MEM is the location of the atomic access.
6854 OLDVAL is the first operand for the operation.
6856 NEWVAL is the optional second operand for the operation. Its value
6857 is NULL if unused. */
6860 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
6861 rtx result, rtx mem, rtx oldval, rtx newval)
6863 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
6864 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
6866 enum machine_mode mode;
6868 mode = GET_MODE (mem);
6870 /* Compute the address of the containing SImode value. */
6871 orig_addr = force_reg (Pmode, XEXP (mem, 0));
6872 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
6873 force_reg (Pmode, GEN_INT (-4)));
6875 /* Create a memory reference for it. */
6876 memsi = gen_rtx_MEM (SImode, memsi_addr);
6877 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
6878 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
6880 /* Work out the byte offset of the QImode or HImode value,
6881 counting from the least significant byte. */
6882 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
6883 if (TARGET_BIG_ENDIAN)
6884 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
6886 /* Multiply by eight to convert the shift value from bytes to bits. */
6887 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
6889 /* Make the final shift an SImode value, so that it can be used in
6890 SImode operations. */
6891 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
6893 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6894 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
6895 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
6896 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
6898 /* Compute the equivalent exclusive mask. */
6899 inverted_mask = gen_reg_rtx (SImode);
6900 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
6901 gen_rtx_NOT (SImode, mask)));
6903 /* Shift the old value into place. */
6904 if (oldval != const0_rtx)
6906 oldval = convert_modes (SImode, mode, oldval, true);
6907 oldval = force_reg (SImode, oldval);
6908 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
6911 /* Do the same for the new value. */
6912 if (newval && newval != const0_rtx)
6914 newval = convert_modes (SImode, mode, newval, true);
6915 newval = force_reg (SImode, newval);
6916 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
6919 /* Do the SImode atomic access. */
6921 res = gen_reg_rtx (SImode);
6923 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
6925 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
6927 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
6933 /* Shift and convert the result. */
6934 mips_emit_binary (AND, res, res, mask);
6935 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
6936 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
6940 /* Return true if it is possible to use left/right accesses for a
6941 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6942 returning true, update *OP, *LEFT and *RIGHT as follows:
6944 *OP is a BLKmode reference to the whole field.
6946 *LEFT is a QImode reference to the first byte if big endian or
6947 the last byte if little endian. This address can be used in the
6948 left-side instructions (LWL, SWL, LDL, SDL).
6950 *RIGHT is a QImode reference to the opposite end of the field and
6951 can be used in the patterning right-side instruction. */
6954 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
6955 rtx *left, rtx *right)
6959 /* Check that the operand really is a MEM. Not all the extv and
6960 extzv predicates are checked. */
6964 /* Check that the size is valid. */
6965 if (width != 32 && (!TARGET_64BIT || width != 64))
6968 /* We can only access byte-aligned values. Since we are always passed
6969 a reference to the first byte of the field, it is not necessary to
6970 do anything with BITPOS after this check. */
6971 if (bitpos % BITS_PER_UNIT != 0)
6974 /* Reject aligned bitfields: we want to use a normal load or store
6975 instead of a left/right pair. */
6976 if (MEM_ALIGN (*op) >= width)
6979 /* Adjust *OP to refer to the whole field. This also has the effect
6980 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6981 *op = adjust_address (*op, BLKmode, 0);
6982 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
6984 /* Get references to both ends of the field. We deliberately don't
6985 use the original QImode *OP for FIRST since the new BLKmode one
6986 might have a simpler address. */
6987 first = adjust_address (*op, QImode, 0);
6988 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
6990 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6991 correspond to the MSB and RIGHT to the LSB. */
6992 if (TARGET_BIG_ENDIAN)
6993 *left = first, *right = last;
6995 *left = last, *right = first;
7000 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7001 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7002 the operation is the equivalent of:
7004 (set DEST (*_extract SRC WIDTH BITPOS))
7006 Return true on success. */
7009 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7010 HOST_WIDE_INT bitpos)
7012 rtx left, right, temp;
7014 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7015 be a paradoxical word_mode subreg. This is the only case in which
7016 we allow the destination to be larger than the source. */
7017 if (GET_CODE (dest) == SUBREG
7018 && GET_MODE (dest) == DImode
7019 && GET_MODE (SUBREG_REG (dest)) == SImode)
7020 dest = SUBREG_REG (dest);
7022 /* After the above adjustment, the destination must be the same
7023 width as the source. */
7024 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7027 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7030 temp = gen_reg_rtx (GET_MODE (dest));
7031 if (GET_MODE (dest) == DImode)
7033 emit_insn (gen_mov_ldl (temp, src, left));
7034 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7038 emit_insn (gen_mov_lwl (temp, src, left));
7039 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7044 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7045 BITPOS and SRC are the operands passed to the expander; the operation
7046 is the equivalent of:
7048 (set (zero_extract DEST WIDTH BITPOS) SRC)
7050 Return true on success. */
7053 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7054 HOST_WIDE_INT bitpos)
7057 enum machine_mode mode;
7059 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7062 mode = mode_for_size (width, MODE_INT, 0);
7063 src = gen_lowpart (mode, src);
7066 emit_insn (gen_mov_sdl (dest, src, left));
7067 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7071 emit_insn (gen_mov_swl (dest, src, left));
7072 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7077 /* Return true if X is a MEM with the same size as MODE. */
7080 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7087 size = MEM_SIZE (x);
7088 return size && INTVAL (size) == GET_MODE_SIZE (mode);
7091 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7092 source of an "ext" instruction or the destination of an "ins"
7093 instruction. OP must be a register operand and the following
7094 conditions must hold:
7096 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7097 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7098 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7100 Also reject lengths equal to a word as they are better handled
7101 by the move patterns. */
7104 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7106 if (!ISA_HAS_EXT_INS
7107 || !register_operand (op, VOIDmode)
7108 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7111 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7114 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7120 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7121 operation if MAXLEN is the maxium length of consecutive bits that
7122 can make up MASK. MODE is the mode of the operation. See
7123 mask_low_and_shift_len for the actual definition. */
7126 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7128 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7131 /* Return true iff OP1 and OP2 are valid operands together for the
7132 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7133 see the table in the comment before the pattern. */
7136 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7138 return (memory_operand (op1, mode)
7139 ? and_load_operand (op2, mode)
7140 : and_reg_operand (op2, mode));
7143 /* The canonical form of a mask-low-and-shift-left operation is
7144 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7145 cleared. Thus we need to shift MASK to the right before checking if it
7146 is a valid mask value. MODE is the mode of the operation. If true
7147 return the length of the mask, otherwise return -1. */
7150 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7152 HOST_WIDE_INT shval;
7154 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7155 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7158 /* Return true if -msplit-addresses is selected and should be honored.
7160 -msplit-addresses is a half-way house between explicit relocations
7161 and the traditional assembler macros. It can split absolute 32-bit
7162 symbolic constants into a high/lo_sum pair but uses macros for other
7165 Like explicit relocation support for REL targets, it relies
7166 on GNU extensions in the assembler and the linker.
7168 Although this code should work for -O0, it has traditionally
7169 been treated as an optimization. */
7172 mips_split_addresses_p (void)
7174 return (TARGET_SPLIT_ADDRESSES
7178 && !ABI_HAS_64BIT_SYMBOLS);
7181 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7184 mips_init_relocs (void)
7186 memset (mips_split_p, '\0', sizeof (mips_split_p));
7187 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7188 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7189 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7191 if (ABI_HAS_64BIT_SYMBOLS)
7193 if (TARGET_EXPLICIT_RELOCS)
7195 mips_split_p[SYMBOL_64_HIGH] = true;
7196 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7197 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7199 mips_split_p[SYMBOL_64_MID] = true;
7200 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7201 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7203 mips_split_p[SYMBOL_64_LOW] = true;
7204 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7205 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7207 mips_split_p[SYMBOL_ABSOLUTE] = true;
7208 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7213 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16)
7215 mips_split_p[SYMBOL_ABSOLUTE] = true;
7216 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7217 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7219 mips_lo_relocs[SYMBOL_32_HIGH] = "%hi(";
7225 /* The high part is provided by a pseudo copy of $gp. */
7226 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7227 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7229 else if (TARGET_EXPLICIT_RELOCS)
7230 /* Small data constants are kept whole until after reload,
7231 then lowered by mips_rewrite_small_data. */
7232 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7234 if (TARGET_EXPLICIT_RELOCS)
7236 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7239 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7240 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7244 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7245 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7248 /* Expose the use of $28 as soon as possible. */
7249 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7253 /* The HIGH and LO_SUM are matched by special .md patterns. */
7254 mips_split_p[SYMBOL_GOT_DISP] = true;
7256 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7257 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7258 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7260 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7261 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7262 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7267 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7269 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7270 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7272 /* Expose the use of $28 as soon as possible. */
7273 mips_split_p[SYMBOL_GOT_DISP] = true;
7279 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7280 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7281 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7284 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7285 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7287 mips_split_p[SYMBOL_DTPREL] = true;
7288 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7289 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7291 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7293 mips_split_p[SYMBOL_TPREL] = true;
7294 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7295 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7297 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7300 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7301 in context CONTEXT. RELOCS is the array of relocations to use. */
7304 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7305 const char **relocs)
7307 enum mips_symbol_type symbol_type;
7310 symbol_type = mips_classify_symbolic_expression (op, context);
7311 gcc_assert (relocs[symbol_type]);
7313 fputs (relocs[symbol_type], file);
7314 output_addr_const (file, mips_strip_unspec_address (op));
7315 for (p = relocs[symbol_type]; *p != 0; p++)
7320 /* Start a new block with the given asm switch enabled. If we need
7321 to print a directive, emit PREFIX before it and SUFFIX after it. */
7324 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7325 const char *prefix, const char *suffix)
7327 if (asm_switch->nesting_level == 0)
7328 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7329 asm_switch->nesting_level++;
7332 /* Likewise, but end a block. */
7335 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7336 const char *prefix, const char *suffix)
7338 gcc_assert (asm_switch->nesting_level);
7339 asm_switch->nesting_level--;
7340 if (asm_switch->nesting_level == 0)
7341 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7344 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7345 that either print a complete line or print nothing. */
7348 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7350 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7354 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7356 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7359 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7360 The punctuation characters are:
7362 '(' Start a nested ".set noreorder" block.
7363 ')' End a nested ".set noreorder" block.
7364 '[' Start a nested ".set noat" block.
7365 ']' End a nested ".set noat" block.
7366 '<' Start a nested ".set nomacro" block.
7367 '>' End a nested ".set nomacro" block.
7368 '*' Behave like %(%< if generating a delayed-branch sequence.
7369 '#' Print a nop if in a ".set noreorder" block.
7370 '/' Like '#', but do nothing within a delayed-branch sequence.
7371 '?' Print "l" if mips_branch_likely is true
7372 '~' Print a nop if mips_branch_likely is true
7373 '.' Print the name of the register with a hard-wired zero (zero or $0).
7374 '@' Print the name of the assembler temporary register (at or $1).
7375 '^' Print the name of the pic call-through register (t9 or $25).
7376 '+' Print the name of the gp register (usually gp or $28).
7377 '$' Print the name of the stack pointer register (sp or $29).
7379 See also mips_init_print_operand_pucnt. */
7382 mips_print_operand_punctuation (FILE *file, int ch)
7387 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7391 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7395 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7399 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7403 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7407 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7411 if (final_sequence != 0)
7413 mips_print_operand_punctuation (file, '(');
7414 mips_print_operand_punctuation (file, '<');
7419 if (mips_noreorder.nesting_level > 0)
7420 fputs ("\n\tnop", file);
7424 /* Print an extra newline so that the delayed insn is separated
7425 from the following ones. This looks neater and is consistent
7426 with non-nop delayed sequences. */
7427 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7428 fputs ("\n\tnop\n", file);
7432 if (mips_branch_likely)
7437 if (mips_branch_likely)
7438 fputs ("\n\tnop", file);
7442 fputs (reg_names[GP_REG_FIRST + 0], file);
7446 fputs (reg_names[AT_REGNUM], file);
7450 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7454 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7458 fputs (reg_names[STACK_POINTER_REGNUM], file);
7467 /* Initialize mips_print_operand_punct. */
7470 mips_init_print_operand_punct (void)
7474 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7475 mips_print_operand_punct[(unsigned char) *p] = true;
7478 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7479 associated with condition CODE. Print the condition part of the
7483 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7497 /* Conveniently, the MIPS names for these conditions are the same
7498 as their RTL equivalents. */
7499 fputs (GET_RTX_NAME (code), file);
7503 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7508 /* Likewise floating-point branches. */
7511 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7516 fputs ("c1f", file);
7520 fputs ("c1t", file);
7524 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7529 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7532 mips_print_operand_punct_valid_p (unsigned char code)
7534 return mips_print_operand_punct[code];
7537 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7539 'X' Print CONST_INT OP in hexadecimal format.
7540 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7541 'd' Print CONST_INT OP in decimal.
7542 'm' Print one less than CONST_INT OP in decimal.
7543 'h' Print the high-part relocation associated with OP, after stripping
7545 'R' Print the low-part relocation associated with OP.
7546 'C' Print the integer branch condition for comparison OP.
7547 'N' Print the inverse of the integer branch condition for comparison OP.
7548 'F' Print the FPU branch condition for comparison OP.
7549 'W' Print the inverse of the FPU branch condition for comparison OP.
7550 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7551 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7552 't' Like 'T', but with the EQ/NE cases reversed
7553 'Y' Print mips_fp_conditions[INTVAL (OP)]
7554 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7555 'q' Print a DSP accumulator register.
7556 'D' Print the second part of a double-word register or memory operand.
7557 'L' Print the low-order register in a double-word register operand.
7558 'M' Print high-order register in a double-word register operand.
7559 'z' Print $0 if OP is zero, otherwise print OP normally. */
7562 mips_print_operand (FILE *file, rtx op, int letter)
7566 if (mips_print_operand_punct_valid_p (letter))
7568 mips_print_operand_punctuation (file, letter);
7573 code = GET_CODE (op);
7578 if (CONST_INT_P (op))
7579 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
7581 output_operand_lossage ("invalid use of '%%%c'", letter);
7585 if (CONST_INT_P (op))
7586 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
7588 output_operand_lossage ("invalid use of '%%%c'", letter);
7592 if (CONST_INT_P (op))
7593 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
7595 output_operand_lossage ("invalid use of '%%%c'", letter);
7599 if (CONST_INT_P (op))
7600 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
7602 output_operand_lossage ("invalid use of '%%%c'", letter);
7608 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
7612 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
7616 mips_print_int_branch_condition (file, code, letter);
7620 mips_print_int_branch_condition (file, reverse_condition (code), letter);
7624 mips_print_float_branch_condition (file, code, letter);
7628 mips_print_float_branch_condition (file, reverse_condition (code),
7635 int truth = (code == NE) == (letter == 'T');
7636 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
7641 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
7642 fputs (mips_fp_conditions[UINTVAL (op)], file);
7644 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7651 mips_print_operand (file, op, 0);
7657 if (code == REG && MD_REG_P (REGNO (op)))
7658 fprintf (file, "$ac0");
7659 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
7660 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
7662 output_operand_lossage ("invalid use of '%%%c'", letter);
7670 unsigned int regno = REGNO (op);
7671 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
7672 || (letter == 'L' && TARGET_BIG_ENDIAN)
7675 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
7676 output_operand_lossage ("invalid use of '%%%c'", letter);
7677 /* We need to print $0 .. $31 for COP0 registers. */
7678 if (COP0_REG_P (regno))
7679 fprintf (file, "$%s", ®_names[regno][4]);
7681 fprintf (file, "%s", reg_names[regno]);
7687 output_address (plus_constant (XEXP (op, 0), 4));
7688 else if (letter && letter != 'z')
7689 output_operand_lossage ("invalid use of '%%%c'", letter);
7691 output_address (XEXP (op, 0));
7695 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
7696 fputs (reg_names[GP_REG_FIRST], file);
7697 else if (letter && letter != 'z')
7698 output_operand_lossage ("invalid use of '%%%c'", letter);
7699 else if (CONST_GP_P (op))
7700 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
7702 output_addr_const (file, mips_strip_unspec_address (op));
7708 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7711 mips_print_operand_address (FILE *file, rtx x)
7713 struct mips_address_info addr;
7715 if (mips_classify_address (&addr, x, word_mode, true))
7719 mips_print_operand (file, addr.offset, 0);
7720 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7723 case ADDRESS_LO_SUM:
7724 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
7726 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
7729 case ADDRESS_CONST_INT:
7730 output_addr_const (file, x);
7731 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
7734 case ADDRESS_SYMBOLIC:
7735 output_addr_const (file, mips_strip_unspec_address (x));
7741 /* Implement TARGET_ENCODE_SECTION_INFO. */
7744 mips_encode_section_info (tree decl, rtx rtl, int first)
7746 default_encode_section_info (decl, rtl, first);
7748 if (TREE_CODE (decl) == FUNCTION_DECL)
7750 rtx symbol = XEXP (rtl, 0);
7751 tree type = TREE_TYPE (decl);
7753 /* Encode whether the symbol is short or long. */
7754 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
7755 || mips_far_type_p (type))
7756 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
7760 /* Implement TARGET_SELECT_RTX_SECTION. */
7763 mips_select_rtx_section (enum machine_mode mode, rtx x,
7764 unsigned HOST_WIDE_INT align)
7766 /* ??? Consider using mergeable small data sections. */
7767 if (mips_rtx_constant_in_small_data_p (mode))
7768 return get_named_section (NULL, ".sdata", 0);
7770 return default_elf_select_rtx_section (mode, x, align);
7773 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7775 The complication here is that, with the combination TARGET_ABICALLS
7776 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7777 absolute addresses, and should therefore not be included in the
7778 read-only part of a DSO. Handle such cases by selecting a normal
7779 data section instead of a read-only one. The logic apes that in
7780 default_function_rodata_section. */
7783 mips_function_rodata_section (tree decl)
7785 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
7786 return default_function_rodata_section (decl);
7788 if (decl && DECL_SECTION_NAME (decl))
7790 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7791 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
7793 char *rname = ASTRDUP (name);
7795 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
7797 else if (flag_function_sections
7798 && flag_data_sections
7799 && strncmp (name, ".text.", 6) == 0)
7801 char *rname = ASTRDUP (name);
7802 memcpy (rname + 1, "data", 4);
7803 return get_section (rname, SECTION_WRITE, decl);
7806 return data_section;
7809 /* Implement TARGET_IN_SMALL_DATA_P. */
7812 mips_in_small_data_p (const_tree decl)
7814 unsigned HOST_WIDE_INT size;
7816 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7819 /* We don't yet generate small-data references for -mabicalls
7820 or VxWorks RTP code. See the related -G handling in
7821 mips_option_override. */
7822 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
7825 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7829 /* Reject anything that isn't in a known small-data section. */
7830 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7831 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7834 /* If a symbol is defined externally, the assembler will use the
7835 usual -G rules when deciding how to implement macros. */
7836 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
7839 else if (TARGET_EMBEDDED_DATA)
7841 /* Don't put constants into the small data section: we want them
7842 to be in ROM rather than RAM. */
7843 if (TREE_CODE (decl) != VAR_DECL)
7846 if (TREE_READONLY (decl)
7847 && !TREE_SIDE_EFFECTS (decl)
7848 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7852 /* Enforce -mlocal-sdata. */
7853 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
7856 /* Enforce -mextern-sdata. */
7857 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
7859 if (DECL_EXTERNAL (decl))
7861 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
7865 /* We have traditionally not treated zero-sized objects as small data,
7866 so this is now effectively part of the ABI. */
7867 size = int_size_in_bytes (TREE_TYPE (decl));
7868 return size > 0 && size <= mips_small_data_threshold;
7871 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7872 anchors for small data: the GP register acts as an anchor in that
7873 case. We also don't want to use them for PC-relative accesses,
7874 where the PC acts as an anchor. */
7877 mips_use_anchors_for_symbol_p (const_rtx symbol)
7879 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
7881 case SYMBOL_PC_RELATIVE:
7882 case SYMBOL_GP_RELATIVE:
7886 return default_use_anchors_for_symbol_p (symbol);
7890 /* The MIPS debug format wants all automatic variables and arguments
7891 to be in terms of the virtual frame pointer (stack pointer before
7892 any adjustment in the function), while the MIPS 3.0 linker wants
7893 the frame pointer to be the stack pointer after the initial
7894 adjustment. So, we do the adjustment here. The arg pointer (which
7895 is eliminated) points to the virtual frame pointer, while the frame
7896 pointer (which may be eliminated) points to the stack pointer after
7897 the initial adjustments. */
7900 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
7902 rtx offset2 = const0_rtx;
7903 rtx reg = eliminate_constant_term (addr, &offset2);
7906 offset = INTVAL (offset2);
7908 if (reg == stack_pointer_rtx
7909 || reg == frame_pointer_rtx
7910 || reg == hard_frame_pointer_rtx)
7912 offset -= cfun->machine->frame.total_size;
7913 if (reg == hard_frame_pointer_rtx)
7914 offset += cfun->machine->frame.hard_frame_pointer_offset;
7917 /* sdbout_parms does not want this to crash for unrecognized cases. */
7919 else if (reg != arg_pointer_rtx)
7920 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7927 /* Implement ASM_OUTPUT_EXTERNAL. */
7930 mips_output_external (FILE *file, tree decl, const char *name)
7932 default_elf_asm_output_external (file, decl, name);
7934 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7935 set in order to avoid putting out names that are never really
7937 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
7939 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
7941 /* When using assembler macros, emit .extern directives for
7942 all small-data externs so that the assembler knows how
7945 In most cases it would be safe (though pointless) to emit
7946 .externs for other symbols too. One exception is when an
7947 object is within the -G limit but declared by the user to
7948 be in a section other than .sbss or .sdata. */
7949 fputs ("\t.extern\t", file);
7950 assemble_name (file, name);
7951 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
7952 int_size_in_bytes (TREE_TYPE (decl)));
7957 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7960 mips_output_filename (FILE *stream, const char *name)
7962 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7964 if (write_symbols == DWARF2_DEBUG)
7966 else if (mips_output_filename_first_time)
7968 mips_output_filename_first_time = 0;
7969 num_source_filenames += 1;
7970 current_function_file = name;
7971 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7972 output_quoted_string (stream, name);
7973 putc ('\n', stream);
7975 /* If we are emitting stabs, let dbxout.c handle this (except for
7976 the mips_output_filename_first_time case). */
7977 else if (write_symbols == DBX_DEBUG)
7979 else if (name != current_function_file
7980 && strcmp (name, current_function_file) != 0)
7982 num_source_filenames += 1;
7983 current_function_file = name;
7984 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7985 output_quoted_string (stream, name);
7986 putc ('\n', stream);
7990 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7992 static void ATTRIBUTE_UNUSED
7993 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
7998 fputs ("\t.dtprelword\t", file);
8002 fputs ("\t.dtpreldword\t", file);
8008 output_addr_const (file, x);
8009 fputs ("+0x8000", file);
8012 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8015 mips_dwarf_register_span (rtx reg)
8018 enum machine_mode mode;
8020 /* By default, GCC maps increasing register numbers to increasing
8021 memory locations, but paired FPRs are always little-endian,
8022 regardless of the prevailing endianness. */
8023 mode = GET_MODE (reg);
8024 if (FP_REG_P (REGNO (reg))
8025 && TARGET_BIG_ENDIAN
8026 && MAX_FPRS_PER_FMT > 1
8027 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8029 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8030 high = mips_subword (reg, true);
8031 low = mips_subword (reg, false);
8032 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8038 /* Implement ASM_OUTPUT_ASCII. */
8041 mips_output_ascii (FILE *stream, const char *string, size_t len)
8047 fprintf (stream, "\t.ascii\t\"");
8048 for (i = 0; i < len; i++)
8052 c = (unsigned char) string[i];
8055 if (c == '\\' || c == '\"')
8057 putc ('\\', stream);
8065 fprintf (stream, "\\%03o", c);
8069 if (cur_pos > 72 && i+1 < len)
8072 fprintf (stream, "\"\n\t.ascii\t\"");
8075 fprintf (stream, "\"\n");
8078 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8079 macros, mark the symbol as written so that mips_asm_output_external
8080 won't emit an .extern for it. STREAM is the output file, NAME is the
8081 name of the symbol, INIT_STRING is the string that should be written
8082 before the symbol and FINAL_STRING is the string that should be
8083 written after it. FINAL_STRING is a printf format that consumes the
8084 remaining arguments. */
8087 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8088 const char *final_string, ...)
8092 fputs (init_string, stream);
8093 assemble_name (stream, name);
8094 va_start (ap, final_string);
8095 vfprintf (stream, final_string, ap);
8098 if (!TARGET_EXPLICIT_RELOCS)
8100 tree name_tree = get_identifier (name);
8101 TREE_ASM_WRITTEN (name_tree) = 1;
8105 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8106 NAME is the name of the object and ALIGN is the required alignment
8107 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8108 alignment argument. */
8111 mips_declare_common_object (FILE *stream, const char *name,
8112 const char *init_string,
8113 unsigned HOST_WIDE_INT size,
8114 unsigned int align, bool takes_alignment_p)
8116 if (!takes_alignment_p)
8118 size += (align / BITS_PER_UNIT) - 1;
8119 size -= size % (align / BITS_PER_UNIT);
8120 mips_declare_object (stream, name, init_string,
8121 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8124 mips_declare_object (stream, name, init_string,
8125 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8126 size, align / BITS_PER_UNIT);
8129 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8130 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8133 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8134 unsigned HOST_WIDE_INT size,
8137 /* If the target wants uninitialized const declarations in
8138 .rdata then don't put them in .comm. */
8139 if (TARGET_EMBEDDED_DATA
8140 && TARGET_UNINIT_CONST_IN_RODATA
8141 && TREE_CODE (decl) == VAR_DECL
8142 && TREE_READONLY (decl)
8143 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8145 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8146 targetm.asm_out.globalize_label (stream, name);
8148 switch_to_section (readonly_data_section);
8149 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8150 mips_declare_object (stream, name, "",
8151 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8155 mips_declare_common_object (stream, name, "\n\t.comm\t",
8159 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8160 extern int size_directive_output;
8162 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8163 definitions except that it uses mips_declare_object to emit the label. */
8166 mips_declare_object_name (FILE *stream, const char *name,
8167 tree decl ATTRIBUTE_UNUSED)
8169 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8170 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8173 size_directive_output = 0;
8174 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8178 size_directive_output = 1;
8179 size = int_size_in_bytes (TREE_TYPE (decl));
8180 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8183 mips_declare_object (stream, name, "", ":\n");
8186 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8189 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8193 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8194 if (!flag_inhibit_size_directive
8195 && DECL_SIZE (decl) != 0
8198 && DECL_INITIAL (decl) == error_mark_node
8199 && !size_directive_output)
8203 size_directive_output = 1;
8204 size = int_size_in_bytes (TREE_TYPE (decl));
8205 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8210 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8211 with the current ABI. */
8214 mips_mdebug_abi_name (void)
8227 return TARGET_64BIT ? "eabi64" : "eabi32";
8233 /* Implement TARGET_ASM_FILE_START. */
8236 mips_file_start (void)
8238 default_file_start ();
8240 /* Generate a special section to describe the ABI switches used to
8241 produce the resultant binary. This is unnecessary on IRIX and
8242 causes unwanted warnings from the native linker. */
8245 /* Record the ABI itself. Modern versions of binutils encode
8246 this information in the ELF header flags, but GDB needs the
8247 information in order to correctly debug binaries produced by
8248 older binutils. See the function mips_gdbarch_init in
8250 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8251 mips_mdebug_abi_name ());
8253 /* There is no ELF header flag to distinguish long32 forms of the
8254 EABI from long64 forms. Emit a special section to help tools
8255 such as GDB. Do the same for o64, which is sometimes used with
8257 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8258 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8259 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8261 #ifdef HAVE_AS_GNU_ATTRIBUTE
8265 /* No floating-point operations, -mno-float. */
8266 if (TARGET_NO_FLOAT)
8268 /* Soft-float code, -msoft-float. */
8269 else if (!TARGET_HARD_FLOAT_ABI)
8271 /* Single-float code, -msingle-float. */
8272 else if (!TARGET_DOUBLE_FLOAT)
8274 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8275 else if (!TARGET_64BIT && TARGET_FLOAT64)
8277 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8281 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8286 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8287 if (TARGET_ABICALLS)
8289 fprintf (asm_out_file, "\t.abicalls\n");
8290 if (TARGET_ABICALLS_PIC0)
8291 fprintf (asm_out_file, "\t.option\tpic0\n");
8294 if (flag_verbose_asm)
8295 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8297 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8300 /* Make the last instruction frame-related and note that it performs
8301 the operation described by FRAME_PATTERN. */
8304 mips_set_frame_expr (rtx frame_pattern)
8308 insn = get_last_insn ();
8309 RTX_FRAME_RELATED_P (insn) = 1;
8310 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8315 /* Return a frame-related rtx that stores REG at MEM.
8316 REG must be a single register. */
8319 mips_frame_set (rtx mem, rtx reg)
8323 /* If we're saving the return address register and the DWARF return
8324 address column differs from the hard register number, adjust the
8325 note reg to refer to the former. */
8326 if (REGNO (reg) == RETURN_ADDR_REGNUM
8327 && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM)
8328 reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN);
8330 set = gen_rtx_SET (VOIDmode, mem, reg);
8331 RTX_FRAME_RELATED_P (set) = 1;
8336 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8337 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8338 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8339 static const unsigned char mips16e_s2_s8_regs[] = {
8340 30, 23, 22, 21, 20, 19, 18
8342 static const unsigned char mips16e_a0_a3_regs[] = {
8346 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8347 ordered from the uppermost in memory to the lowest in memory. */
8348 static const unsigned char mips16e_save_restore_regs[] = {
8349 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8352 /* Return the index of the lowest X in the range [0, SIZE) for which
8353 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8356 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8361 for (i = 0; i < size; i++)
8362 if (BITSET_P (mask, regs[i]))
8368 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8369 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8370 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8371 is true for all indexes (X, SIZE). */
8374 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8375 unsigned int size, unsigned int *num_regs_ptr)
8379 i = mips16e_find_first_register (*mask_ptr, regs, size);
8380 for (i++; i < size; i++)
8381 if (!BITSET_P (*mask_ptr, regs[i]))
8384 *mask_ptr |= 1 << regs[i];
8388 /* Return a simplified form of X using the register values in REG_VALUES.
8389 REG_VALUES[R] is the last value assigned to hard register R, or null
8390 if R has not been modified.
8392 This function is rather limited, but is good enough for our purposes. */
8395 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8397 x = avoid_constant_pool_reference (x);
8401 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8402 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8403 x0, GET_MODE (XEXP (x, 0)));
8406 if (ARITHMETIC_P (x))
8408 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8409 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8410 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8414 && reg_values[REGNO (x)]
8415 && !rtx_unstable_p (reg_values[REGNO (x)]))
8416 return reg_values[REGNO (x)];
8421 /* Return true if (set DEST SRC) stores an argument register into its
8422 caller-allocated save slot, storing the number of that argument
8423 register in *REGNO_PTR if so. REG_VALUES is as for
8424 mips16e_collect_propagate_value. */
8427 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8428 unsigned int *regno_ptr)
8430 unsigned int argno, regno;
8431 HOST_WIDE_INT offset, required_offset;
8434 /* Check that this is a word-mode store. */
8435 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8438 /* Check that the register being saved is an unmodified argument
8440 regno = REGNO (src);
8441 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8443 argno = regno - GP_ARG_FIRST;
8445 /* Check whether the address is an appropriate stack-pointer or
8446 frame-pointer access. */
8447 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8448 mips_split_plus (addr, &base, &offset);
8449 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8450 if (base == hard_frame_pointer_rtx)
8451 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8452 else if (base != stack_pointer_rtx)
8454 if (offset != required_offset)
8461 /* A subroutine of mips_expand_prologue, called only when generating
8462 MIPS16e SAVE instructions. Search the start of the function for any
8463 instructions that save argument registers into their caller-allocated
8464 save slots. Delete such instructions and return a value N such that
8465 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8466 instructions redundant. */
8469 mips16e_collect_argument_saves (void)
8471 rtx reg_values[FIRST_PSEUDO_REGISTER];
8472 rtx insn, next, set, dest, src;
8473 unsigned int nargs, regno;
8475 push_topmost_sequence ();
8477 memset (reg_values, 0, sizeof (reg_values));
8478 for (insn = get_insns (); insn; insn = next)
8480 next = NEXT_INSN (insn);
8481 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
8487 set = PATTERN (insn);
8488 if (GET_CODE (set) != SET)
8491 dest = SET_DEST (set);
8492 src = SET_SRC (set);
8493 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
8495 if (!BITSET_P (cfun->machine->frame.mask, regno))
8498 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
8501 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
8502 reg_values[REGNO (dest)]
8503 = mips16e_collect_propagate_value (src, reg_values);
8507 pop_topmost_sequence ();
8512 /* Return a move between register REGNO and memory location SP + OFFSET.
8513 Make the move a load if RESTORE_P, otherwise make it a frame-related
8517 mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset,
8522 mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset));
8523 reg = gen_rtx_REG (SImode, regno);
8525 ? gen_rtx_SET (VOIDmode, reg, mem)
8526 : mips_frame_set (mem, reg));
8529 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8530 The instruction must:
8532 - Allocate or deallocate SIZE bytes in total; SIZE is known
8535 - Save or restore as many registers in *MASK_PTR as possible.
8536 The instruction saves the first registers at the top of the
8537 allocated area, with the other registers below it.
8539 - Save NARGS argument registers above the allocated area.
8541 (NARGS is always zero if RESTORE_P.)
8543 The SAVE and RESTORE instructions cannot save and restore all general
8544 registers, so there may be some registers left over for the caller to
8545 handle. Destructively modify *MASK_PTR so that it contains the registers
8546 that still need to be saved or restored. The caller can save these
8547 registers in the memory immediately below *OFFSET_PTR, which is a
8548 byte offset from the bottom of the allocated stack area. */
8551 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
8552 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
8556 HOST_WIDE_INT offset, top_offset;
8557 unsigned int i, regno;
8560 gcc_assert (cfun->machine->frame.num_fp == 0);
8562 /* Calculate the number of elements in the PARALLEL. We need one element
8563 for the stack adjustment, one for each argument register save, and one
8564 for each additional register move. */
8566 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8567 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
8570 /* Create the final PARALLEL. */
8571 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
8574 /* Add the stack pointer adjustment. */
8575 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8576 plus_constant (stack_pointer_rtx,
8577 restore_p ? size : -size));
8578 RTX_FRAME_RELATED_P (set) = 1;
8579 XVECEXP (pattern, 0, n++) = set;
8581 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8582 top_offset = restore_p ? size : 0;
8584 /* Save the arguments. */
8585 for (i = 0; i < nargs; i++)
8587 offset = top_offset + i * UNITS_PER_WORD;
8588 set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i);
8589 XVECEXP (pattern, 0, n++) = set;
8592 /* Then fill in the other register moves. */
8593 offset = top_offset;
8594 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
8596 regno = mips16e_save_restore_regs[i];
8597 if (BITSET_P (*mask_ptr, regno))
8599 offset -= UNITS_PER_WORD;
8600 set = mips16e_save_restore_reg (restore_p, offset, regno);
8601 XVECEXP (pattern, 0, n++) = set;
8602 *mask_ptr &= ~(1 << regno);
8606 /* Tell the caller what offset it should use for the remaining registers. */
8607 *offset_ptr = size + (offset - top_offset);
8609 gcc_assert (n == XVECLEN (pattern, 0));
8614 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8615 pointer. Return true if PATTERN matches the kind of instruction
8616 generated by mips16e_build_save_restore. If INFO is nonnull,
8617 initialize it when returning true. */
8620 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
8621 struct mips16e_save_restore_info *info)
8623 unsigned int i, nargs, mask, extra;
8624 HOST_WIDE_INT top_offset, save_offset, offset;
8625 rtx set, reg, mem, base;
8628 if (!GENERATE_MIPS16E_SAVE_RESTORE)
8631 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8632 top_offset = adjust > 0 ? adjust : 0;
8634 /* Interpret all other members of the PARALLEL. */
8635 save_offset = top_offset - UNITS_PER_WORD;
8639 for (n = 1; n < XVECLEN (pattern, 0); n++)
8641 /* Check that we have a SET. */
8642 set = XVECEXP (pattern, 0, n);
8643 if (GET_CODE (set) != SET)
8646 /* Check that the SET is a load (if restoring) or a store
8648 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
8652 /* Check that the address is the sum of the stack pointer and a
8653 possibly-zero constant offset. */
8654 mips_split_plus (XEXP (mem, 0), &base, &offset);
8655 if (base != stack_pointer_rtx)
8658 /* Check that SET's other operand is a register. */
8659 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
8663 /* Check for argument saves. */
8664 if (offset == top_offset + nargs * UNITS_PER_WORD
8665 && REGNO (reg) == GP_ARG_FIRST + nargs)
8667 else if (offset == save_offset)
8669 while (mips16e_save_restore_regs[i++] != REGNO (reg))
8670 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
8673 mask |= 1 << REGNO (reg);
8674 save_offset -= UNITS_PER_WORD;
8680 /* Check that the restrictions on register ranges are met. */
8682 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
8683 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
8684 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
8685 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
8689 /* Make sure that the topmost argument register is not saved twice.
8690 The checks above ensure that the same is then true for the other
8691 argument registers. */
8692 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
8695 /* Pass back information, if requested. */
8698 info->nargs = nargs;
8700 info->size = (adjust > 0 ? adjust : -adjust);
8706 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8707 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8708 the null terminator. */
8711 mips16e_add_register_range (char *s, unsigned int min_reg,
8712 unsigned int max_reg)
8714 if (min_reg != max_reg)
8715 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
8717 s += sprintf (s, ",%s", reg_names[min_reg]);
8721 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8722 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8725 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
8727 static char buffer[300];
8729 struct mips16e_save_restore_info info;
8730 unsigned int i, end;
8733 /* Parse the pattern. */
8734 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
8737 /* Add the mnemonic. */
8738 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
8741 /* Save the arguments. */
8743 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
8744 reg_names[GP_ARG_FIRST + info.nargs - 1]);
8745 else if (info.nargs == 1)
8746 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
8748 /* Emit the amount of stack space to allocate or deallocate. */
8749 s += sprintf (s, "%d", (int) info.size);
8751 /* Save or restore $16. */
8752 if (BITSET_P (info.mask, 16))
8753 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
8755 /* Save or restore $17. */
8756 if (BITSET_P (info.mask, 17))
8757 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
8759 /* Save or restore registers in the range $s2...$s8, which
8760 mips16e_s2_s8_regs lists in decreasing order. Note that this
8761 is a software register range; the hardware registers are not
8762 numbered consecutively. */
8763 end = ARRAY_SIZE (mips16e_s2_s8_regs);
8764 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
8766 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
8767 mips16e_s2_s8_regs[i]);
8769 /* Save or restore registers in the range $a0...$a3. */
8770 end = ARRAY_SIZE (mips16e_a0_a3_regs);
8771 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
8773 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
8774 mips16e_a0_a3_regs[end - 1]);
8776 /* Save or restore $31. */
8777 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
8778 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
8783 /* Return true if the current function returns its value in a floating-point
8784 register in MIPS16 mode. */
8787 mips16_cfun_returns_in_fpr_p (void)
8789 tree return_type = DECL_RESULT (current_function_decl);
8790 return (TARGET_MIPS16
8791 && TARGET_HARD_FLOAT_ABI
8792 && !aggregate_value_p (return_type, current_function_decl)
8793 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
8796 /* Return true if predicate PRED is true for at least one instruction.
8797 Cache the result in *CACHE, and assume that the result is true
8798 if *CACHE is already true. */
8801 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
8807 push_topmost_sequence ();
8808 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8809 if (USEFUL_INSN_P (insn) && pred (insn))
8814 pop_topmost_sequence ();
8819 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8820 See mips_cfun_has_inflexible_gp_ref_p for details. */
8823 mips_insn_has_inflexible_gp_ref_p (rtx insn)
8825 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8826 indicate that the target could be a traditional MIPS
8827 lazily-binding stub. */
8828 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
8831 /* Return true if the current function refers to the global pointer
8832 in a way that forces $28 to be valid. This means that we can't
8833 change the choice of global pointer, even for NewABI code.
8835 One example of this (and one which needs several checks) is that
8836 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8837 (This restriction does not apply to PLTs.) */
8840 mips_cfun_has_inflexible_gp_ref_p (void)
8842 /* If the function has a nonlocal goto, $28 must hold the correct
8843 global pointer for the target function. That is, the target
8844 of the goto implicitly uses $28. */
8845 if (crtl->has_nonlocal_goto)
8848 if (TARGET_ABICALLS_PIC2)
8850 /* Symbolic accesses implicitly use the global pointer unless
8851 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8852 might go to traditional MIPS lazy-binding stubs. */
8853 if (!TARGET_EXPLICIT_RELOCS)
8856 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8857 can be lazily-bound. */
8861 /* MIPS16 functions that return in FPRs need to call an
8862 external libgcc routine. This call is only made explict
8863 during mips_expand_epilogue, and it too might be lazily bound. */
8864 if (mips16_cfun_returns_in_fpr_p ())
8868 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
8869 mips_insn_has_inflexible_gp_ref_p);
8872 /* Return true if INSN refers to the global pointer in a "flexible" way.
8873 See mips_cfun_has_flexible_gp_ref_p for details. */
8876 mips_insn_has_flexible_gp_ref_p (rtx insn)
8878 return (get_attr_got (insn) != GOT_UNSET
8879 || mips_small_data_pattern_p (PATTERN (insn))
8880 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
8883 /* Return true if the current function references the global pointer,
8884 but if those references do not inherently require the global pointer
8885 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8888 mips_cfun_has_flexible_gp_ref_p (void)
8890 /* Reload can sometimes introduce constant pool references
8891 into a function that otherwise didn't need them. For example,
8892 suppose we have an instruction like:
8894 (set (reg:DF R1) (float:DF (reg:SI R2)))
8896 If R2 turns out to be a constant such as 1, the instruction may
8897 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8898 the option of using this constant if R2 doesn't get allocated
8901 In cases like these, reload will have added the constant to the
8902 pool but no instruction will yet refer to it. */
8903 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
8906 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
8907 mips_insn_has_flexible_gp_ref_p);
8910 /* Return the register that should be used as the global pointer
8911 within this function. Return INVALID_REGNUM if the function
8912 doesn't need a global pointer. */
8915 mips_global_pointer (void)
8919 /* $gp is always available unless we're using a GOT. */
8920 if (!TARGET_USE_GOT)
8921 return GLOBAL_POINTER_REGNUM;
8923 /* If there are inflexible references to $gp, we must use the
8924 standard register. */
8925 if (mips_cfun_has_inflexible_gp_ref_p ())
8926 return GLOBAL_POINTER_REGNUM;
8928 /* If there are no current references to $gp, then the only uses
8929 we can introduce later are those involved in long branches. */
8930 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
8931 return INVALID_REGNUM;
8933 /* If the global pointer is call-saved, try to use a call-clobbered
8935 if (TARGET_CALL_SAVED_GP && current_function_is_leaf)
8936 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
8937 if (!df_regs_ever_live_p (regno)
8938 && call_really_used_regs[regno]
8939 && !fixed_regs[regno]
8940 && regno != PIC_FUNCTION_ADDR_REGNUM)
8943 return GLOBAL_POINTER_REGNUM;
8946 /* Return true if the current function's prologue must load the global
8947 pointer value into pic_offset_table_rtx and store the same value in
8948 the function's cprestore slot (if any).
8950 One problem we have to deal with is that, when emitting GOT-based
8951 position independent code, long-branch sequences will need to load
8952 the address of the branch target from the GOT. We don't know until
8953 the very end of compilation whether (and where) the function needs
8954 long branches, so we must ensure that _any_ branch can access the
8955 global pointer in some form. However, we do not want to pessimize
8956 the usual case in which all branches are short.
8958 We handle this as follows:
8960 (1) During reload, we set cfun->machine->global_pointer to
8961 INVALID_REGNUM if we _know_ that the current function
8962 doesn't need a global pointer. This is only valid if
8963 long branches don't need the GOT.
8965 Otherwise, we assume that we might need a global pointer
8966 and pick an appropriate register.
8968 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8969 we ensure that the global pointer is available at every
8970 block boundary bar entry and exit. We do this in one of two ways:
8972 - If the function has a cprestore slot, we ensure that this
8973 slot is valid at every branch. However, as explained in
8974 point (6) below, there is no guarantee that pic_offset_table_rtx
8975 itself is valid if new uses of the global pointer are introduced
8976 after the first post-epilogue split.
8978 We guarantee that the cprestore slot is valid by loading it
8979 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8980 this register live at every block boundary bar function entry
8981 and exit. It is then invalid to move the load (and thus the
8982 preceding store) across a block boundary.
8984 - If the function has no cprestore slot, we guarantee that
8985 pic_offset_table_rtx itself is valid at every branch.
8987 See mips_eh_uses for the handling of the register liveness.
8989 (3) During prologue and epilogue generation, we emit "ghost"
8990 placeholder instructions to manipulate the global pointer.
8992 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8993 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8994 that the function needs a global pointer. (There is no need to set
8995 them earlier than this, and doing it as late as possible leads to
8996 fewer false positives.)
8998 (5) If cfun->machine->must_initialize_gp_p is true during a
8999 split_insns pass, we split the ghost instructions into real
9000 instructions. These split instructions can then be optimized in
9001 the usual way. Otherwise, we keep the ghost instructions intact,
9002 and optimize for the case where they aren't needed. We still
9003 have the option of splitting them later, if we need to introduce
9004 new uses of the global pointer.
9006 For example, the scheduler ignores a ghost instruction that
9007 stores $28 to the stack, but it handles the split form of
9008 the ghost instruction as an ordinary store.
9010 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9011 is true during the first post-epilogue split_insns pass, we split
9012 calls and restore_gp patterns into instructions that explicitly
9013 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9014 we split these patterns into instructions that _don't_ load from
9017 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9018 time of the split, then any instructions that exist at that time
9019 can make free use of pic_offset_table_rtx. However, if we want
9020 to introduce new uses of the global pointer after the split,
9021 we must explicitly load the value from the cprestore slot, since
9022 pic_offset_table_rtx itself might not be valid at a given point
9025 The idea is that we want to be able to delete redundant
9026 loads from the cprestore slot in the usual case where no
9027 long branches are needed.
9029 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9030 of md_reorg, we decide whether the global pointer is needed for
9031 long branches. If so, we set cfun->machine->must_initialize_gp_p
9032 to true and split the ghost instructions into real instructions
9035 Note that the ghost instructions must have a zero length for three reasons:
9037 - Giving the length of the underlying $gp sequence might cause
9038 us to use long branches in cases where they aren't really needed.
9040 - They would perturb things like alignment calculations.
9042 - More importantly, the hazard detection in md_reorg relies on
9043 empty instructions having a zero length.
9045 If we find a long branch and split the ghost instructions at the
9046 end of md_reorg, the split could introduce more long branches.
9047 That isn't a problem though, because we still do the split before
9048 the final shorten_branches pass.
9050 This is extremely ugly, but it seems like the best compromise between
9051 correctness and efficiency. */
9054 mips_must_initialize_gp_p (void)
9056 return cfun->machine->must_initialize_gp_p;
9059 /* Return true if REGNO is a register that is ordinarily call-clobbered
9060 but must nevertheless be preserved by an interrupt handler. */
9063 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9065 if (MD_REG_P (regno))
9068 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9071 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9073 /* $0 is hard-wired. */
9074 if (regno == GP_REG_FIRST)
9077 /* The interrupt handler can treat kernel registers as
9078 scratch registers. */
9079 if (KERNEL_REG_P (regno))
9082 /* The function will return the stack pointer to its original value
9084 if (regno == STACK_POINTER_REGNUM)
9087 /* Otherwise, return true for registers that aren't ordinarily
9089 return call_really_used_regs[regno];
9095 /* Return true if the current function should treat register REGNO
9099 mips_cfun_call_saved_reg_p (unsigned int regno)
9101 /* If the user makes an ordinarily-call-saved register global,
9102 that register is no longer call-saved. */
9103 if (global_regs[regno])
9106 /* Interrupt handlers need to save extra registers. */
9107 if (cfun->machine->interrupt_handler_p
9108 && mips_interrupt_extra_call_saved_reg_p (regno))
9111 /* call_insns preserve $28 unless they explicitly say otherwise,
9112 so call_really_used_regs[] treats $28 as call-saved. However,
9113 we want the ABI property rather than the default call_insn
9115 return (regno == GLOBAL_POINTER_REGNUM
9116 ? TARGET_CALL_SAVED_GP
9117 : !call_really_used_regs[regno]);
9120 /* Return true if the function body might clobber register REGNO.
9121 We know that REGNO is call-saved. */
9124 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9126 /* Some functions should be treated as clobbering all call-saved
9128 if (crtl->saves_all_registers)
9131 /* DF handles cases where a register is explicitly referenced in
9132 the rtl. Incoming values are passed in call-clobbered registers,
9133 so we can assume that any live call-saved register is set within
9135 if (df_regs_ever_live_p (regno))
9138 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9139 These clobbers are not explicit in the rtl. */
9140 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9143 /* If we're using a call-saved global pointer, the function's
9144 prologue will need to set it up. */
9145 if (cfun->machine->global_pointer == regno)
9148 /* The function's prologue will need to set the frame pointer if
9149 frame_pointer_needed. */
9150 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9153 /* If a MIPS16 function returns a value in FPRs, its epilogue
9154 will need to call an external libgcc routine. This yet-to-be
9155 generated call_insn will clobber $31. */
9156 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9159 /* If REGNO is ordinarily call-clobbered, we must assume that any
9160 called function could modify it. */
9161 if (cfun->machine->interrupt_handler_p
9162 && !current_function_is_leaf
9163 && mips_interrupt_extra_call_saved_reg_p (regno))
9169 /* Return true if the current function must save register REGNO. */
9172 mips_save_reg_p (unsigned int regno)
9174 if (mips_cfun_call_saved_reg_p (regno))
9176 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9179 /* Save both registers in an FPR pair if either one is used. This is
9180 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9181 register to be used without the even register. */
9182 if (FP_REG_P (regno)
9183 && MAX_FPRS_PER_FMT == 2
9184 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9188 /* We need to save the incoming return address if __builtin_eh_return
9189 is being used to set a different return address. */
9190 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9196 /* Populate the current function's mips_frame_info structure.
9198 MIPS stack frames look like:
9200 +-------------------------------+
9202 | incoming stack arguments |
9204 +-------------------------------+
9206 | caller-allocated save area |
9207 A | for register arguments |
9209 +-------------------------------+ <-- incoming stack pointer
9211 | callee-allocated save area |
9212 B | for arguments that are |
9213 | split between registers and |
9216 +-------------------------------+ <-- arg_pointer_rtx
9218 C | callee-allocated save area |
9219 | for register varargs |
9221 +-------------------------------+ <-- frame_pointer_rtx
9222 | | + cop0_sp_offset
9223 | COP0 reg save area | + UNITS_PER_WORD
9225 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9226 | | + UNITS_PER_WORD
9227 | accumulator save area |
9229 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9230 | | + UNITS_PER_HWFPVALUE
9233 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9234 | | + UNITS_PER_WORD
9237 +-------------------------------+ <-- frame_pointer_rtx with
9238 | | \ -fstack-protector
9239 | local variables | | var_size
9241 +-------------------------------+
9243 | $gp save area | | cprestore_size
9245 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9247 | outgoing stack arguments | |
9249 +-------------------------------+ | args_size
9251 | caller-allocated save area | |
9252 | for register arguments | |
9254 +-------------------------------+ <-- stack_pointer_rtx
9255 frame_pointer_rtx without
9257 hard_frame_pointer_rtx for
9260 At least two of A, B and C will be empty.
9262 Dynamic stack allocations such as alloca insert data at point P.
9263 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9264 hard_frame_pointer_rtx unchanged. */
9267 mips_compute_frame_info (void)
9269 struct mips_frame_info *frame;
9270 HOST_WIDE_INT offset, size;
9271 unsigned int regno, i;
9273 /* Set this function's interrupt properties. */
9274 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9277 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9278 else if (TARGET_HARD_FLOAT)
9279 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9280 else if (TARGET_MIPS16)
9281 error ("interrupt handlers cannot be MIPS16 functions");
9284 cfun->machine->interrupt_handler_p = true;
9285 cfun->machine->use_shadow_register_set_p =
9286 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9287 cfun->machine->keep_interrupts_masked_p =
9288 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9289 cfun->machine->use_debug_exception_return_p =
9290 mips_use_debug_exception_return_p (TREE_TYPE
9291 (current_function_decl));
9295 frame = &cfun->machine->frame;
9296 memset (frame, 0, sizeof (*frame));
9297 size = get_frame_size ();
9299 cfun->machine->global_pointer = mips_global_pointer ();
9301 /* The first two blocks contain the outgoing argument area and the $gp save
9302 slot. This area isn't needed in leaf functions, but if the
9303 target-independent frame size is nonzero, we have already committed to
9304 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9305 if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf)
9307 /* The MIPS 3.0 linker does not like functions that dynamically
9308 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9309 looks like we are trying to create a second frame pointer to the
9310 function, so allocate some stack space to make it happy. */
9311 if (cfun->calls_alloca)
9312 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9314 frame->args_size = 0;
9315 frame->cprestore_size = 0;
9319 frame->args_size = crtl->outgoing_args_size;
9320 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9322 offset = frame->args_size + frame->cprestore_size;
9324 /* Move above the local variables. */
9325 frame->var_size = MIPS_STACK_ALIGN (size);
9326 offset += frame->var_size;
9328 /* Find out which GPRs we need to save. */
9329 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9330 if (mips_save_reg_p (regno))
9333 frame->mask |= 1 << (regno - GP_REG_FIRST);
9336 /* If this function calls eh_return, we must also save and restore the
9337 EH data registers. */
9338 if (crtl->calls_eh_return)
9339 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9342 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9345 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9346 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9347 save all later registers too. */
9348 if (GENERATE_MIPS16E_SAVE_RESTORE)
9350 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9351 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9352 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9353 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9356 /* Move above the GPR save area. */
9357 if (frame->num_gp > 0)
9359 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9360 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9363 /* Find out which FPRs we need to save. This loop must iterate over
9364 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9365 if (TARGET_HARD_FLOAT)
9366 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9367 if (mips_save_reg_p (regno))
9369 frame->num_fp += MAX_FPRS_PER_FMT;
9370 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9373 /* Move above the FPR save area. */
9374 if (frame->num_fp > 0)
9376 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9377 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9380 /* Add in space for the interrupt context information. */
9381 if (cfun->machine->interrupt_handler_p)
9384 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9387 frame->acc_mask |= (1 << 0);
9390 /* Check accumulators 1, 2, 3. */
9391 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9392 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9395 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9398 /* All interrupt context functions need space to preserve STATUS. */
9399 frame->num_cop0_regs++;
9401 /* If we don't keep interrupts masked, we need to save EPC. */
9402 if (!cfun->machine->keep_interrupts_masked_p)
9403 frame->num_cop0_regs++;
9406 /* Move above the accumulator save area. */
9407 if (frame->num_acc > 0)
9409 /* Each accumulator needs 2 words. */
9410 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9411 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9414 /* Move above the COP0 register save area. */
9415 if (frame->num_cop0_regs > 0)
9417 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9418 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9421 /* Move above the callee-allocated varargs save area. */
9422 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9423 frame->arg_pointer_offset = offset;
9425 /* Move above the callee-allocated area for pretend stack arguments. */
9426 offset += crtl->args.pretend_args_size;
9427 frame->total_size = offset;
9429 /* Work out the offsets of the save areas from the top of the frame. */
9430 if (frame->gp_sp_offset > 0)
9431 frame->gp_save_offset = frame->gp_sp_offset - offset;
9432 if (frame->fp_sp_offset > 0)
9433 frame->fp_save_offset = frame->fp_sp_offset - offset;
9434 if (frame->acc_sp_offset > 0)
9435 frame->acc_save_offset = frame->acc_sp_offset - offset;
9436 if (frame->num_cop0_regs > 0)
9437 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9439 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9440 arguments. This tends to increase the chances of using unextended
9441 instructions for local variables and incoming arguments. */
9443 frame->hard_frame_pointer_offset = frame->args_size;
9446 /* Return the style of GP load sequence that is being used for the
9447 current function. */
9449 enum mips_loadgp_style
9450 mips_current_loadgp_style (void)
9452 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9458 if (TARGET_ABSOLUTE_ABICALLS)
9459 return LOADGP_ABSOLUTE;
9461 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9464 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9467 mips_frame_pointer_required (void)
9469 /* If the function contains dynamic stack allocations, we need to
9470 use the frame pointer to access the static parts of the frame. */
9471 if (cfun->calls_alloca)
9474 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9475 reload may be unable to compute the address of a local variable,
9476 since there is no way to add a large constant to the stack pointer
9477 without using a second temporary register. */
9480 mips_compute_frame_info ();
9481 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
9488 /* Make sure that we're not trying to eliminate to the wrong hard frame
9492 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
9494 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
9497 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9498 or argument pointer. TO is either the stack pointer or hard frame
9502 mips_initial_elimination_offset (int from, int to)
9504 HOST_WIDE_INT offset;
9506 mips_compute_frame_info ();
9508 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9511 case FRAME_POINTER_REGNUM:
9512 if (FRAME_GROWS_DOWNWARD)
9513 offset = (cfun->machine->frame.args_size
9514 + cfun->machine->frame.cprestore_size
9515 + cfun->machine->frame.var_size);
9520 case ARG_POINTER_REGNUM:
9521 offset = cfun->machine->frame.arg_pointer_offset;
9528 if (to == HARD_FRAME_POINTER_REGNUM)
9529 offset -= cfun->machine->frame.hard_frame_pointer_offset;
9534 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9537 mips_extra_live_on_entry (bitmap regs)
9541 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9542 the global pointer. */
9543 if (!TARGET_ABSOLUTE_ABICALLS)
9544 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
9546 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9547 the global pointer. */
9549 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
9551 /* See the comment above load_call<mode> for details. */
9552 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
9556 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9560 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
9565 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
9568 /* Emit code to change the current function's return address to
9569 ADDRESS. SCRATCH is available as a scratch register, if needed.
9570 ADDRESS and SCRATCH are both word-mode GPRs. */
9573 mips_set_return_address (rtx address, rtx scratch)
9577 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
9578 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
9579 cfun->machine->frame.gp_sp_offset);
9580 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
9583 /* Return true if the current function has a cprestore slot. */
9586 mips_cfun_has_cprestore_slot_p (void)
9588 return (cfun->machine->global_pointer != INVALID_REGNUM
9589 && cfun->machine->frame.cprestore_size > 0);
9592 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9593 cprestore slot. LOAD_P is true if the caller wants to load from
9594 the cprestore slot; it is false if the caller wants to store to
9598 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
9601 const struct mips_frame_info *frame;
9603 frame = &cfun->machine->frame;
9604 /* .cprestore always uses the stack pointer instead of the frame pointer.
9605 We have a free choice for direct stores for non-MIPS16 functions,
9606 and for MIPS16 functions whose cprestore slot is in range of the
9607 stack pointer. Using the stack pointer would sometimes give more
9608 (early) scheduling freedom, but using the frame pointer would
9609 sometimes give more (late) scheduling freedom. It's hard to
9610 predict which applies to a given function, so let's keep things
9613 Loads must always use the frame pointer in functions that call
9614 alloca, and there's little benefit to using the stack pointer
9616 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
9618 *base = hard_frame_pointer_rtx;
9619 *offset = frame->args_size - frame->hard_frame_pointer_offset;
9623 *base = stack_pointer_rtx;
9624 *offset = frame->args_size;
9628 /* Return true if X is the load or store address of the cprestore slot;
9629 LOAD_P says which. */
9632 mips_cprestore_address_p (rtx x, bool load_p)
9634 rtx given_base, required_base;
9635 HOST_WIDE_INT given_offset, required_offset;
9637 mips_split_plus (x, &given_base, &given_offset);
9638 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
9639 return given_base == required_base && given_offset == required_offset;
9642 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9643 going to load from it, false if we are going to store to it.
9644 Use TEMP as a temporary register if need be. */
9647 mips_cprestore_slot (rtx temp, bool load_p)
9650 HOST_WIDE_INT offset;
9652 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
9653 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
9656 /* Emit instructions to save global pointer value GP into cprestore
9657 slot MEM. OFFSET is the offset that MEM applies to the base register.
9659 MEM may not be a legitimate address. If it isn't, TEMP is a
9660 temporary register that can be used, otherwise it is a SCRATCH. */
9663 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
9665 if (TARGET_CPRESTORE_DIRECTIVE)
9667 gcc_assert (gp == pic_offset_table_rtx);
9668 emit_insn (gen_cprestore (mem, offset));
9671 mips_emit_move (mips_cprestore_slot (temp, false), gp);
9674 /* Restore $gp from its save slot, using TEMP as a temporary base register
9675 if need be. This function is for o32 and o64 abicalls only.
9677 See mips_must_initialize_gp_p for details about how we manage the
9681 mips_restore_gp_from_cprestore_slot (rtx temp)
9683 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
9685 if (!cfun->machine->must_restore_gp_when_clobbered_p)
9687 emit_note (NOTE_INSN_DELETED);
9693 mips_emit_move (temp, mips_cprestore_slot (temp, true));
9694 mips_emit_move (pic_offset_table_rtx, temp);
9697 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
9698 if (!TARGET_EXPLICIT_RELOCS)
9699 emit_insn (gen_blockage ());
9702 /* A function to save or store a register. The first argument is the
9703 register and the second is the stack slot. */
9704 typedef void (*mips_save_restore_fn) (rtx, rtx);
9706 /* Use FN to save or restore register REGNO. MODE is the register's
9707 mode and OFFSET is the offset of its save slot from the current
9711 mips_save_restore_reg (enum machine_mode mode, int regno,
9712 HOST_WIDE_INT offset, mips_save_restore_fn fn)
9716 mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset));
9717 fn (gen_rtx_REG (mode, regno), mem);
9720 /* Call FN for each accumlator that is saved by the current function.
9721 SP_OFFSET is the offset of the current stack pointer from the start
9725 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
9727 HOST_WIDE_INT offset;
9730 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
9731 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
9733 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
9734 offset -= UNITS_PER_WORD;
9735 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
9736 offset -= UNITS_PER_WORD;
9739 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
9740 if (BITSET_P (cfun->machine->frame.acc_mask,
9741 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
9743 mips_save_restore_reg (word_mode, regno, offset, fn);
9744 offset -= UNITS_PER_WORD;
9748 /* Call FN for each register that is saved by the current function.
9749 SP_OFFSET is the offset of the current stack pointer from the start
9753 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
9754 mips_save_restore_fn fn)
9756 enum machine_mode fpr_mode;
9757 HOST_WIDE_INT offset;
9760 /* Save registers starting from high to low. The debuggers prefer at least
9761 the return register be stored at func+4, and also it allows us not to
9762 need a nop in the epilogue if at least one register is reloaded in
9763 addition to return address. */
9764 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
9765 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
9766 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
9768 /* Record the ra offset for use by mips_function_profiler. */
9769 if (regno == RETURN_ADDR_REGNUM)
9770 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
9771 mips_save_restore_reg (word_mode, regno, offset, fn);
9772 offset -= UNITS_PER_WORD;
9775 /* This loop must iterate over the same space as its companion in
9776 mips_compute_frame_info. */
9777 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
9778 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
9779 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
9780 regno >= FP_REG_FIRST;
9781 regno -= MAX_FPRS_PER_FMT)
9782 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
9784 mips_save_restore_reg (fpr_mode, regno, offset, fn);
9785 offset -= GET_MODE_SIZE (fpr_mode);
9789 /* Return true if a move between register REGNO and its save slot (MEM)
9790 can be done in a single move. LOAD_P is true if we are loading
9791 from the slot, false if we are storing to it. */
9794 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
9796 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9797 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
9800 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
9801 GET_MODE (mem), mem, load_p) == NO_REGS;
9804 /* Emit a move from SRC to DEST, given that one of them is a register
9805 save slot and that the other is a register. TEMP is a temporary
9806 GPR of the same mode that is available if need be. */
9809 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
9816 regno = REGNO (src);
9821 regno = REGNO (dest);
9825 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
9827 /* We don't yet know whether we'll need this instruction or not.
9828 Postpone the decision by emitting a ghost move. This move
9829 is specifically not frame-related; only the split version is. */
9831 emit_insn (gen_move_gpdi (dest, src));
9833 emit_insn (gen_move_gpsi (dest, src));
9837 if (regno == HI_REGNUM)
9841 mips_emit_move (temp, src);
9843 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
9844 temp, gen_rtx_REG (DImode, LO_REGNUM)));
9846 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
9847 temp, gen_rtx_REG (SImode, LO_REGNUM)));
9852 emit_insn (gen_mfhidi_ti (temp,
9853 gen_rtx_REG (TImode, MD_REG_FIRST)));
9855 emit_insn (gen_mfhisi_di (temp,
9856 gen_rtx_REG (DImode, MD_REG_FIRST)));
9857 mips_emit_move (dest, temp);
9860 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
9861 mips_emit_move (dest, src);
9864 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
9865 mips_emit_move (temp, src);
9866 mips_emit_move (dest, temp);
9869 mips_set_frame_expr (mips_frame_set (dest, src));
9872 /* If we're generating n32 or n64 abicalls, and the current function
9873 does not use $28 as its global pointer, emit a cplocal directive.
9874 Use pic_offset_table_rtx as the argument to the directive. */
9877 mips_output_cplocal (void)
9879 if (!TARGET_EXPLICIT_RELOCS
9880 && mips_must_initialize_gp_p ()
9881 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
9882 output_asm_insn (".cplocal %+", 0);
9885 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9888 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9892 #ifdef SDB_DEBUGGING_INFO
9893 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
9894 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
9897 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9898 floating-point arguments. */
9900 && TARGET_HARD_FLOAT_ABI
9901 && crtl->args.info.fp_code != 0)
9902 mips16_build_function_stub ();
9904 /* Get the function name the same way that toplev.c does before calling
9905 assemble_start_function. This is needed so that the name used here
9906 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9907 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9908 mips_start_function_definition (fnname, TARGET_MIPS16);
9910 /* Output MIPS-specific frame information. */
9911 if (!flag_inhibit_size_directive)
9913 const struct mips_frame_info *frame;
9915 frame = &cfun->machine->frame;
9917 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9919 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
9920 "# vars= " HOST_WIDE_INT_PRINT_DEC
9922 ", args= " HOST_WIDE_INT_PRINT_DEC
9923 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
9924 reg_names[frame_pointer_needed
9925 ? HARD_FRAME_POINTER_REGNUM
9926 : STACK_POINTER_REGNUM],
9927 (frame_pointer_needed
9928 ? frame->total_size - frame->hard_frame_pointer_offset
9929 : frame->total_size),
9930 reg_names[RETURN_ADDR_REGNUM],
9932 frame->num_gp, frame->num_fp,
9934 frame->cprestore_size);
9936 /* .mask MASK, OFFSET. */
9937 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9938 frame->mask, frame->gp_save_offset);
9940 /* .fmask MASK, OFFSET. */
9941 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
9942 frame->fmask, frame->fp_save_offset);
9945 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9946 Also emit the ".set noreorder; .set nomacro" sequence for functions
9948 if (mips_must_initialize_gp_p ()
9949 && mips_current_loadgp_style () == LOADGP_OLDABI)
9953 /* This is a fixed-form sequence. The position of the
9954 first two instructions is important because of the
9955 way _gp_disp is defined. */
9956 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9957 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9958 output_asm_insn ("sll\t$2,16", 0);
9959 output_asm_insn ("addu\t$2,$3", 0);
9963 /* .cpload must be in a .set noreorder but not a
9964 .set nomacro block. */
9965 mips_push_asm_switch (&mips_noreorder);
9966 output_asm_insn (".cpload\t%^", 0);
9967 if (!cfun->machine->all_noreorder_p)
9968 mips_pop_asm_switch (&mips_noreorder);
9970 mips_push_asm_switch (&mips_nomacro);
9973 else if (cfun->machine->all_noreorder_p)
9975 mips_push_asm_switch (&mips_noreorder);
9976 mips_push_asm_switch (&mips_nomacro);
9979 /* Tell the assembler which register we're using as the global
9980 pointer. This is needed for thunks, since they can use either
9981 explicit relocs or assembler macros. */
9982 mips_output_cplocal ();
9985 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9988 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9989 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
9993 /* Reinstate the normal $gp. */
9994 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
9995 mips_output_cplocal ();
9997 if (cfun->machine->all_noreorder_p)
9999 mips_pop_asm_switch (&mips_nomacro);
10000 mips_pop_asm_switch (&mips_noreorder);
10003 /* Get the function name the same way that toplev.c does before calling
10004 assemble_start_function. This is needed so that the name used here
10005 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10006 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10007 mips_end_function_definition (fnname);
10010 /* Save register REG to MEM. Make the instruction frame-related. */
10013 mips_save_reg (rtx reg, rtx mem)
10015 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10019 if (mips_split_64bit_move_p (mem, reg))
10020 mips_split_doubleword_move (mem, reg);
10022 mips_emit_move (mem, reg);
10024 x1 = mips_frame_set (mips_subword (mem, false),
10025 mips_subword (reg, false));
10026 x2 = mips_frame_set (mips_subword (mem, true),
10027 mips_subword (reg, true));
10028 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10031 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10034 /* The __gnu_local_gp symbol. */
10036 static GTY(()) rtx mips_gnu_local_gp;
10038 /* If we're generating n32 or n64 abicalls, emit instructions
10039 to set up the global pointer. */
10042 mips_emit_loadgp (void)
10044 rtx addr, offset, incoming_address, base, index, pic_reg;
10046 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10047 switch (mips_current_loadgp_style ())
10049 case LOADGP_ABSOLUTE:
10050 if (mips_gnu_local_gp == NULL)
10052 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10053 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10055 emit_insn (Pmode == SImode
10056 ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp)
10057 : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp));
10060 case LOADGP_OLDABI:
10061 /* Added by mips_output_function_prologue. */
10064 case LOADGP_NEWABI:
10065 addr = XEXP (DECL_RTL (current_function_decl), 0);
10066 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10067 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10068 emit_insn (Pmode == SImode
10069 ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address)
10070 : gen_loadgp_newabi_di (pic_reg, offset, incoming_address));
10074 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10075 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10076 emit_insn (Pmode == SImode
10077 ? gen_loadgp_rtp_si (pic_reg, base, index)
10078 : gen_loadgp_rtp_di (pic_reg, base, index));
10086 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg));
10088 /* Emit a blockage if there are implicit uses of the GP register.
10089 This includes profiled functions, because FUNCTION_PROFILE uses
10091 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10092 emit_insn (gen_loadgp_blockage ());
10095 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10098 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10100 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10103 /* Expand the "prologue" pattern. */
10106 mips_expand_prologue (void)
10108 const struct mips_frame_info *frame;
10109 HOST_WIDE_INT size;
10110 unsigned int nargs;
10113 if (cfun->machine->global_pointer != INVALID_REGNUM)
10115 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10116 or implicitly. If so, we can commit to using a global pointer
10117 straight away, otherwise we need to defer the decision. */
10118 if (mips_cfun_has_inflexible_gp_ref_p ()
10119 || mips_cfun_has_flexible_gp_ref_p ())
10121 cfun->machine->must_initialize_gp_p = true;
10122 cfun->machine->must_restore_gp_when_clobbered_p = true;
10125 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10128 frame = &cfun->machine->frame;
10129 size = frame->total_size;
10131 if (flag_stack_usage)
10132 current_function_static_stack_size = size;
10134 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10135 bytes beforehand; this is enough to cover the register save area
10136 without going out of range. */
10137 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10138 || frame->num_cop0_regs > 0)
10140 HOST_WIDE_INT step1;
10142 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10143 if (GENERATE_MIPS16E_SAVE_RESTORE)
10145 HOST_WIDE_INT offset;
10146 unsigned int mask, regno;
10148 /* Try to merge argument stores into the save instruction. */
10149 nargs = mips16e_collect_argument_saves ();
10151 /* Build the save instruction. */
10152 mask = frame->mask;
10153 insn = mips16e_build_save_restore (false, &mask, &offset,
10155 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10158 /* Check if we need to save other registers. */
10159 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10160 if (BITSET_P (mask, regno - GP_REG_FIRST))
10162 offset -= UNITS_PER_WORD;
10163 mips_save_restore_reg (word_mode, regno,
10164 offset, mips_save_reg);
10169 if (cfun->machine->interrupt_handler_p)
10171 HOST_WIDE_INT offset;
10174 /* If this interrupt is using a shadow register set, we need to
10175 get the stack pointer from the previous register set. */
10176 if (cfun->machine->use_shadow_register_set_p)
10177 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10178 stack_pointer_rtx));
10180 if (!cfun->machine->keep_interrupts_masked_p)
10182 /* Move from COP0 Cause to K0. */
10183 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10184 gen_rtx_REG (SImode,
10185 COP0_CAUSE_REG_NUM)));
10186 /* Move from COP0 EPC to K1. */
10187 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10188 gen_rtx_REG (SImode,
10189 COP0_EPC_REG_NUM)));
10192 /* Allocate the first part of the frame. */
10193 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10195 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10198 /* Start at the uppermost location for saving. */
10199 offset = frame->cop0_sp_offset - size;
10200 if (!cfun->machine->keep_interrupts_masked_p)
10202 /* Push EPC into its stack slot. */
10203 mem = gen_frame_mem (word_mode,
10204 plus_constant (stack_pointer_rtx,
10206 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10207 offset -= UNITS_PER_WORD;
10210 /* Move from COP0 Status to K1. */
10211 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10212 gen_rtx_REG (SImode,
10213 COP0_STATUS_REG_NUM)));
10215 /* Right justify the RIPL in k0. */
10216 if (!cfun->machine->keep_interrupts_masked_p)
10217 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10218 gen_rtx_REG (SImode, K0_REG_NUM),
10219 GEN_INT (CAUSE_IPL)));
10221 /* Push Status into its stack slot. */
10222 mem = gen_frame_mem (word_mode,
10223 plus_constant (stack_pointer_rtx, offset));
10224 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10225 offset -= UNITS_PER_WORD;
10227 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10228 if (!cfun->machine->keep_interrupts_masked_p)
10229 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10232 gen_rtx_REG (SImode, K0_REG_NUM)));
10234 if (!cfun->machine->keep_interrupts_masked_p)
10235 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10236 IE is already the correct value, so we don't have to do
10237 anything explicit. */
10238 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10241 gen_rtx_REG (SImode, GP_REG_FIRST)));
10243 /* Disable interrupts by clearing the KSU, ERL, EXL,
10245 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10248 gen_rtx_REG (SImode, GP_REG_FIRST)));
10252 insn = gen_add3_insn (stack_pointer_rtx,
10255 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10258 mips_for_each_saved_acc (size, mips_save_reg);
10259 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10263 /* Allocate the rest of the frame. */
10266 if (SMALL_OPERAND (-size))
10267 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10269 GEN_INT (-size)))) = 1;
10272 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10275 /* There are no instructions to add or subtract registers
10276 from the stack pointer, so use the frame pointer as a
10277 temporary. We should always be using a frame pointer
10278 in this case anyway. */
10279 gcc_assert (frame_pointer_needed);
10280 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10281 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10282 hard_frame_pointer_rtx,
10283 MIPS_PROLOGUE_TEMP (Pmode)));
10284 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10287 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10289 MIPS_PROLOGUE_TEMP (Pmode)));
10291 /* Describe the combined effect of the previous instructions. */
10292 mips_set_frame_expr
10293 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10294 plus_constant (stack_pointer_rtx, -size)));
10298 /* Set up the frame pointer, if we're using one. */
10299 if (frame_pointer_needed)
10301 HOST_WIDE_INT offset;
10303 offset = frame->hard_frame_pointer_offset;
10306 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10307 RTX_FRAME_RELATED_P (insn) = 1;
10309 else if (SMALL_OPERAND (offset))
10311 insn = gen_add3_insn (hard_frame_pointer_rtx,
10312 stack_pointer_rtx, GEN_INT (offset));
10313 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10317 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10318 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10319 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10320 hard_frame_pointer_rtx,
10321 MIPS_PROLOGUE_TEMP (Pmode)));
10322 mips_set_frame_expr
10323 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10324 plus_constant (stack_pointer_rtx, offset)));
10328 mips_emit_loadgp ();
10330 /* Initialize the $gp save slot. */
10331 if (mips_cfun_has_cprestore_slot_p ())
10333 rtx base, mem, gp, temp;
10334 HOST_WIDE_INT offset;
10336 mips_get_cprestore_base_and_offset (&base, &offset, false);
10337 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10338 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10339 temp = (SMALL_OPERAND (offset)
10340 ? gen_rtx_SCRATCH (Pmode)
10341 : MIPS_PROLOGUE_TEMP (Pmode));
10342 emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp));
10344 mips_get_cprestore_base_and_offset (&base, &offset, true);
10345 mem = gen_frame_mem (Pmode, plus_constant (base, offset));
10346 emit_insn (gen_use_cprestore (mem));
10349 /* We need to search back to the last use of K0 or K1. */
10350 if (cfun->machine->interrupt_handler_p)
10352 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10354 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10356 /* Emit a move from K1 to COP0 Status after insn. */
10357 gcc_assert (insn != NULL_RTX);
10358 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10359 gen_rtx_REG (SImode, K1_REG_NUM)),
10363 /* If we are profiling, make sure no instructions are scheduled before
10364 the call to mcount. */
10366 emit_insn (gen_blockage ());
10369 /* Emit instructions to restore register REG from slot MEM. */
10372 mips_restore_reg (rtx reg, rtx mem)
10374 /* There's no MIPS16 instruction to load $31 directly. Load into
10375 $7 instead and adjust the return insn appropriately. */
10376 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10377 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10379 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10382 /* Emit any instructions needed before a return. */
10385 mips_expand_before_return (void)
10387 /* When using a call-clobbered gp, we start out with unified call
10388 insns that include instructions to restore the gp. We then split
10389 these unified calls after reload. These split calls explicitly
10390 clobber gp, so there is no need to define
10391 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10393 For consistency, we should also insert an explicit clobber of $28
10394 before return insns, so that the post-reload optimizers know that
10395 the register is not live on exit. */
10396 if (TARGET_CALL_CLOBBERED_GP)
10397 emit_clobber (pic_offset_table_rtx);
10400 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10404 mips_expand_epilogue (bool sibcall_p)
10406 const struct mips_frame_info *frame;
10407 HOST_WIDE_INT step1, step2;
10408 rtx base, target, insn;
10410 if (!sibcall_p && mips_can_use_return_insn ())
10412 emit_jump_insn (gen_return ());
10416 /* In MIPS16 mode, if the return value should go into a floating-point
10417 register, we need to call a helper routine to copy it over. */
10418 if (mips16_cfun_returns_in_fpr_p ())
10419 mips16_copy_fpr_return_value ();
10421 /* Split the frame into two. STEP1 is the amount of stack we should
10422 deallocate before restoring the registers. STEP2 is the amount we
10423 should deallocate afterwards.
10425 Start off by assuming that no registers need to be restored. */
10426 frame = &cfun->machine->frame;
10427 step1 = frame->total_size;
10430 /* Work out which register holds the frame address. */
10431 if (!frame_pointer_needed)
10432 base = stack_pointer_rtx;
10435 base = hard_frame_pointer_rtx;
10436 step1 -= frame->hard_frame_pointer_offset;
10439 /* If we need to restore registers, deallocate as much stack as
10440 possible in the second step without going out of range. */
10441 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
10442 || frame->num_cop0_regs > 0)
10444 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
10448 /* Set TARGET to BASE + STEP1. */
10454 /* Get an rtx for STEP1 that we can add to BASE. */
10455 adjust = GEN_INT (step1);
10456 if (!SMALL_OPERAND (step1))
10458 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
10459 adjust = MIPS_EPILOGUE_TEMP (Pmode);
10462 /* Normal mode code can copy the result straight into $sp. */
10463 if (!TARGET_MIPS16)
10464 target = stack_pointer_rtx;
10466 emit_insn (gen_add3_insn (target, base, adjust));
10469 /* Copy TARGET into the stack pointer. */
10470 if (target != stack_pointer_rtx)
10471 mips_emit_move (stack_pointer_rtx, target);
10473 /* If we're using addressing macros, $gp is implicitly used by all
10474 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10476 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
10477 emit_insn (gen_blockage ());
10479 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
10481 unsigned int regno, mask;
10482 HOST_WIDE_INT offset;
10485 /* Generate the restore instruction. */
10486 mask = frame->mask;
10487 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
10489 /* Restore any other registers manually. */
10490 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10491 if (BITSET_P (mask, regno - GP_REG_FIRST))
10493 offset -= UNITS_PER_WORD;
10494 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
10497 /* Restore the remaining registers and deallocate the final bit
10499 emit_insn (restore);
10503 /* Restore the registers. */
10504 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
10505 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
10508 if (cfun->machine->interrupt_handler_p)
10510 HOST_WIDE_INT offset;
10513 offset = frame->cop0_sp_offset - (frame->total_size - step2);
10514 if (!cfun->machine->keep_interrupts_masked_p)
10516 /* Restore the original EPC. */
10517 mem = gen_frame_mem (word_mode,
10518 plus_constant (stack_pointer_rtx, offset));
10519 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10520 offset -= UNITS_PER_WORD;
10522 /* Move to COP0 EPC. */
10523 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
10524 gen_rtx_REG (SImode, K0_REG_NUM)));
10527 /* Restore the original Status. */
10528 mem = gen_frame_mem (word_mode,
10529 plus_constant (stack_pointer_rtx, offset));
10530 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
10531 offset -= UNITS_PER_WORD;
10533 /* If we don't use shoadow register set, we need to update SP. */
10534 if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
10535 emit_insn (gen_add3_insn (stack_pointer_rtx,
10539 /* Move to COP0 Status. */
10540 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10541 gen_rtx_REG (SImode, K0_REG_NUM)));
10545 /* Deallocate the final bit of the frame. */
10547 emit_insn (gen_add3_insn (stack_pointer_rtx,
10553 /* Add in the __builtin_eh_return stack adjustment. We need to
10554 use a temporary in MIPS16 code. */
10555 if (crtl->calls_eh_return)
10559 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
10560 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
10561 MIPS_EPILOGUE_TEMP (Pmode),
10562 EH_RETURN_STACKADJ_RTX));
10563 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
10566 emit_insn (gen_add3_insn (stack_pointer_rtx,
10568 EH_RETURN_STACKADJ_RTX));
10573 mips_expand_before_return ();
10574 if (cfun->machine->interrupt_handler_p)
10576 /* Interrupt handlers generate eret or deret. */
10577 if (cfun->machine->use_debug_exception_return_p)
10578 emit_jump_insn (gen_mips_deret ());
10580 emit_jump_insn (gen_mips_eret ());
10584 unsigned int regno;
10586 /* When generating MIPS16 code, the normal
10587 mips_for_each_saved_gpr_and_fpr path will restore the return
10588 address into $7 rather than $31. */
10590 && !GENERATE_MIPS16E_SAVE_RESTORE
10591 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
10592 regno = GP_REG_FIRST + 7;
10594 regno = RETURN_ADDR_REGNUM;
10595 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
10599 /* Search from the beginning to the first use of K0 or K1. */
10600 if (cfun->machine->interrupt_handler_p
10601 && !cfun->machine->keep_interrupts_masked_p)
10603 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
10605 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
10607 gcc_assert (insn != NULL_RTX);
10608 /* Insert disable interrupts before the first use of K0 or K1. */
10609 emit_insn_before (gen_mips_di (), insn);
10610 emit_insn_before (gen_mips_ehb (), insn);
10614 /* Return nonzero if this function is known to have a null epilogue.
10615 This allows the optimizer to omit jumps to jumps if no stack
10619 mips_can_use_return_insn (void)
10621 /* Interrupt handlers need to go through the epilogue. */
10622 if (cfun->machine->interrupt_handler_p)
10625 if (!reload_completed)
10631 /* In MIPS16 mode, a function that returns a floating-point value
10632 needs to arrange to copy the return value into the floating-point
10634 if (mips16_cfun_returns_in_fpr_p ())
10637 return cfun->machine->frame.total_size == 0;
10640 /* Return true if register REGNO can store a value of mode MODE.
10641 The result of this function is cached in mips_hard_regno_mode_ok. */
10644 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
10647 enum mode_class mclass;
10649 if (mode == CCV2mode)
10650 return (ISA_HAS_8CC
10651 && ST_REG_P (regno)
10652 && (regno - ST_REG_FIRST) % 2 == 0);
10654 if (mode == CCV4mode)
10655 return (ISA_HAS_8CC
10656 && ST_REG_P (regno)
10657 && (regno - ST_REG_FIRST) % 4 == 0);
10659 if (mode == CCmode)
10662 return regno == FPSW_REGNUM;
10664 return (ST_REG_P (regno)
10665 || GP_REG_P (regno)
10666 || FP_REG_P (regno));
10669 size = GET_MODE_SIZE (mode);
10670 mclass = GET_MODE_CLASS (mode);
10672 if (GP_REG_P (regno))
10673 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
10675 if (FP_REG_P (regno)
10676 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
10677 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
10679 /* Allow TFmode for CCmode reloads. */
10680 if (mode == TFmode && ISA_HAS_8CC)
10683 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10684 if (TARGET_LOONGSON_VECTORS
10685 && (mode == V2SImode
10686 || mode == V4HImode
10687 || mode == V8QImode
10688 || mode == DImode))
10691 if (mclass == MODE_FLOAT
10692 || mclass == MODE_COMPLEX_FLOAT
10693 || mclass == MODE_VECTOR_FLOAT)
10694 return size <= UNITS_PER_FPVALUE;
10696 /* Allow integer modes that fit into a single register. We need
10697 to put integers into FPRs when using instructions like CVT
10698 and TRUNC. There's no point allowing sizes smaller than a word,
10699 because the FPU has no appropriate load/store instructions. */
10700 if (mclass == MODE_INT)
10701 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
10704 if (ACC_REG_P (regno)
10705 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
10707 if (MD_REG_P (regno))
10709 /* After a multiplication or division, clobbering HI makes
10710 the value of LO unpredictable, and vice versa. This means
10711 that, for all interesting cases, HI and LO are effectively
10714 We model this by requiring that any value that uses HI
10716 if (size <= UNITS_PER_WORD * 2)
10717 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
10721 /* DSP accumulators do not have the same restrictions as
10722 HI and LO, so we can treat them as normal doubleword
10724 if (size <= UNITS_PER_WORD)
10727 if (size <= UNITS_PER_WORD * 2
10728 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
10733 if (ALL_COP_REG_P (regno))
10734 return mclass == MODE_INT && size <= UNITS_PER_WORD;
10736 if (regno == GOT_VERSION_REGNUM)
10737 return mode == SImode;
10742 /* Implement HARD_REGNO_NREGS. */
10745 mips_hard_regno_nregs (int regno, enum machine_mode mode)
10747 if (ST_REG_P (regno))
10748 /* The size of FP status registers is always 4, because they only hold
10749 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10750 return (GET_MODE_SIZE (mode) + 3) / 4;
10752 if (FP_REG_P (regno))
10753 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
10755 /* All other registers are word-sized. */
10756 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
10759 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10760 in mips_hard_regno_nregs. */
10763 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
10769 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
10770 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
10772 size = MIN (size, 4);
10773 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
10775 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
10777 size = MIN (size, UNITS_PER_FPREG);
10778 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
10780 if (!hard_reg_set_empty_p (left))
10781 size = MIN (size, UNITS_PER_WORD);
10782 return (GET_MODE_SIZE (mode) + size - 1) / size;
10785 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10788 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED,
10789 enum machine_mode to ATTRIBUTE_UNUSED,
10790 enum reg_class rclass)
10792 /* There are several problems with changing the modes of values in
10793 floating-point registers:
10795 - When a multi-word value is stored in paired floating-point
10796 registers, the first register always holds the low word. We
10797 therefore can't allow FPRs to change between single-word and
10798 multi-word modes on big-endian targets.
10800 - GCC assumes that each word of a multiword register can be
10801 accessed individually using SUBREGs. This is not true for
10802 floating-point registers if they are bigger than a word.
10804 - Loading a 32-bit value into a 64-bit floating-point register
10805 will not sign-extend the value, despite what LOAD_EXTEND_OP
10806 says. We can't allow FPRs to change from SImode to a wider
10807 mode on 64-bit targets.
10809 - If the FPU has already interpreted a value in one format, we
10810 must not ask it to treat the value as having a different
10813 We therefore disallow all mode changes involving FPRs. */
10814 return reg_classes_intersect_p (FP_REGS, rclass);
10817 /* Implement target hook small_register_classes_for_mode_p. */
10820 mips_small_register_classes_for_mode_p (enum machine_mode mode
10823 return TARGET_MIPS16;
10826 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10829 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
10834 return TARGET_HARD_FLOAT;
10837 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
10840 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
10847 /* Implement MODES_TIEABLE_P. */
10850 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10852 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10853 prefer to put one of them in FPRs. */
10854 return (mode1 == mode2
10855 || (!mips_mode_ok_for_mov_fmt_p (mode1)
10856 && !mips_mode_ok_for_mov_fmt_p (mode2)));
10859 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
10862 mips_preferred_reload_class (rtx x, reg_class_t rclass)
10864 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
10867 if (reg_class_subset_p (FP_REGS, rclass)
10868 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
10871 if (reg_class_subset_p (GR_REGS, rclass))
10874 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
10880 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10881 Return a "canonical" class to represent it in later calculations. */
10884 mips_canonicalize_move_class (reg_class_t rclass)
10886 /* All moves involving accumulator registers have the same cost. */
10887 if (reg_class_subset_p (rclass, ACC_REGS))
10890 /* Likewise promote subclasses of general registers to the most
10891 interesting containing class. */
10892 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
10894 else if (reg_class_subset_p (rclass, GENERAL_REGS))
10895 rclass = GENERAL_REGS;
10900 /* Return the cost of moving a value of mode MODE from a register of
10901 class FROM to a GPR. Return 0 for classes that are unions of other
10902 classes handled by this function. */
10905 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
10911 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10915 /* MFLO and MFHI. */
10923 /* LUI followed by MOVF. */
10929 /* This choice of value is historical. */
10937 /* Return the cost of moving a value of mode MODE from a GPR to a
10938 register of class TO. Return 0 for classes that are unions of
10939 other classes handled by this function. */
10942 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
10947 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10951 /* MTLO and MTHI. */
10959 /* A secondary reload through an FPR scratch. */
10960 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
10961 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
10966 /* This choice of value is historical. */
10974 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10975 maximum of the move costs for subclasses; regclass will work out
10976 the maximum for us. */
10979 mips_register_move_cost (enum machine_mode mode,
10980 reg_class_t from, reg_class_t to)
10985 from = mips_canonicalize_move_class (from);
10986 to = mips_canonicalize_move_class (to);
10988 /* Handle moves that can be done without using general-purpose registers. */
10989 if (from == FP_REGS)
10991 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
10995 /* The sequence generated by mips_expand_fcc_reload. */
10999 /* Handle cases in which only one class deviates from the ideal. */
11000 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11002 return mips_move_from_gpr_cost (mode, to);
11004 return mips_move_to_gpr_cost (mode, from);
11006 /* Handles cases that require a GPR temporary. */
11007 cost1 = mips_move_to_gpr_cost (mode, from);
11010 cost2 = mips_move_from_gpr_cost (mode, to);
11012 return cost1 + cost2;
11018 /* Implement TARGET_MEMORY_MOVE_COST. */
11021 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11023 return (mips_cost->memory_latency
11024 + memory_move_secondary_cost (mode, rclass, in));
11027 /* Return the register class required for a secondary register when
11028 copying between one of the registers in RCLASS and value X, which
11029 has mode MODE. X is the source of the move if IN_P, otherwise it
11030 is the destination. Return NO_REGS if no secondary register is
11034 mips_secondary_reload_class (enum reg_class rclass,
11035 enum machine_mode mode, rtx x, bool in_p)
11039 /* If X is a constant that cannot be loaded into $25, it must be loaded
11040 into some other GPR. No other register class allows a direct move. */
11041 if (mips_dangerous_for_la25_p (x))
11042 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11044 regno = true_regnum (x);
11047 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11048 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11054 /* Copying from accumulator registers to anywhere other than a general
11055 register requires a temporary general register. */
11056 if (reg_class_subset_p (rclass, ACC_REGS))
11057 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11058 if (ACC_REG_P (regno))
11059 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11061 /* We can only copy a value to a condition code register from a
11062 floating-point register, and even then we require a scratch
11063 floating-point register. We can only copy a value out of a
11064 condition-code register into a general register. */
11065 if (reg_class_subset_p (rclass, ST_REGS))
11069 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11071 if (ST_REG_P (regno))
11075 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11078 if (reg_class_subset_p (rclass, FP_REGS))
11081 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11082 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11083 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11086 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11087 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11090 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11091 /* We can force the constant to memory and use lwc1
11092 and ldc1. As above, we will use pairs of lwc1s if
11093 ldc1 is not supported. */
11096 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11097 /* In this case we can use mov.fmt. */
11100 /* Otherwise, we need to reload through an integer register. */
11103 if (FP_REG_P (regno))
11104 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11109 /* Implement TARGET_MODE_REP_EXTENDED. */
11112 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11114 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11115 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11116 return SIGN_EXTEND;
11121 /* Implement TARGET_VALID_POINTER_MODE. */
11124 mips_valid_pointer_mode (enum machine_mode mode)
11126 return mode == SImode || (TARGET_64BIT && mode == DImode);
11129 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11132 mips_vector_mode_supported_p (enum machine_mode mode)
11137 return TARGET_PAIRED_SINGLE_FLOAT;
11152 return TARGET_LOONGSON_VECTORS;
11159 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11162 mips_scalar_mode_supported_p (enum machine_mode mode)
11164 if (ALL_FIXED_POINT_MODE_P (mode)
11165 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11168 return default_scalar_mode_supported_p (mode);
11171 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11173 static enum machine_mode
11174 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11176 if (TARGET_PAIRED_SINGLE_FLOAT
11182 /* Implement TARGET_INIT_LIBFUNCS. */
11185 mips_init_libfuncs (void)
11187 if (TARGET_FIX_VR4120)
11189 /* Register the special divsi3 and modsi3 functions needed to work
11190 around VR4120 division errata. */
11191 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11192 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11195 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11197 /* Register the MIPS16 -mhard-float stubs. */
11198 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11199 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11200 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11201 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11203 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11204 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11205 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11206 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11207 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11208 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11209 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11211 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11212 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11213 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11215 if (TARGET_DOUBLE_FLOAT)
11217 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11218 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11219 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11220 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11222 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11223 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11224 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11225 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11226 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11227 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11228 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11230 set_conv_libfunc (sext_optab, DFmode, SFmode,
11231 "__mips16_extendsfdf2");
11232 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11233 "__mips16_truncdfsf2");
11234 set_conv_libfunc (sfix_optab, SImode, DFmode,
11235 "__mips16_fix_truncdfsi");
11236 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11237 "__mips16_floatsidf");
11238 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11239 "__mips16_floatunsidf");
11243 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11244 on an external non-MIPS16 routine to implement __sync_synchronize. */
11246 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11249 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11252 mips_process_load_label (rtx target)
11254 rtx base, gp, intop;
11255 HOST_WIDE_INT offset;
11257 mips_multi_start ();
11261 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11262 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11266 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11267 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11271 gp = pic_offset_table_rtx;
11272 if (mips_cfun_has_cprestore_slot_p ())
11274 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11275 mips_get_cprestore_base_and_offset (&base, &offset, true);
11276 if (!SMALL_OPERAND (offset))
11278 intop = GEN_INT (CONST_HIGH_PART (offset));
11279 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11280 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11283 offset = CONST_LOW_PART (offset);
11285 intop = GEN_INT (offset);
11286 if (ISA_HAS_LOAD_DELAY)
11287 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11289 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11291 if (ISA_HAS_LOAD_DELAY)
11292 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11294 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11295 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11300 /* Return the number of instructions needed to load a label into $AT. */
11302 static unsigned int
11303 mips_load_label_num_insns (void)
11305 if (cfun->machine->load_label_num_insns == 0)
11307 mips_process_load_label (pc_rtx);
11308 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11310 return cfun->machine->load_label_num_insns;
11313 /* Emit an asm sequence to start a noat block and load the address
11314 of a label into $1. */
11317 mips_output_load_label (rtx target)
11319 mips_push_asm_switch (&mips_noat);
11320 if (TARGET_EXPLICIT_RELOCS)
11322 mips_process_load_label (target);
11323 mips_multi_write ();
11327 if (Pmode == DImode)
11328 output_asm_insn ("dla\t%@,%0", &target);
11330 output_asm_insn ("la\t%@,%0", &target);
11334 /* Return the length of INSN. LENGTH is the initial length computed by
11335 attributes in the machine-description file. */
11338 mips_adjust_insn_length (rtx insn, int length)
11340 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11341 of a PIC long-branch sequence. Substitute the correct value. */
11342 if (length == MAX_PIC_BRANCH_LENGTH
11343 && INSN_CODE (insn) >= 0
11344 && get_attr_type (insn) == TYPE_BRANCH)
11346 /* Add the branch-over instruction and its delay slot, if this
11347 is a conditional branch. */
11348 length = simplejump_p (insn) ? 0 : 8;
11350 /* Load the label into $AT and jump to it. Ignore the delay
11351 slot of the jump. */
11352 length += 4 * mips_load_label_num_insns() + 4;
11355 /* A unconditional jump has an unfilled delay slot if it is not part
11356 of a sequence. A conditional jump normally has a delay slot, but
11357 does not on MIPS16. */
11358 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11361 /* See how many nops might be needed to avoid hardware hazards. */
11362 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11363 switch (get_attr_hazard (insn))
11377 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11378 the .md file length attributes are 4-based for both modes.
11379 Adjust the MIPS16 ones here. */
11386 /* Return the assembly code for INSN, which has the operands given by
11387 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11388 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11389 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11390 version of BRANCH_IF_TRUE. */
11393 mips_output_conditional_branch (rtx insn, rtx *operands,
11394 const char *branch_if_true,
11395 const char *branch_if_false)
11397 unsigned int length;
11398 rtx taken, not_taken;
11400 gcc_assert (LABEL_P (operands[0]));
11402 length = get_attr_length (insn);
11405 /* Just a simple conditional branch. */
11406 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
11407 return branch_if_true;
11410 /* Generate a reversed branch around a direct jump. This fallback does
11411 not use branch-likely instructions. */
11412 mips_branch_likely = false;
11413 not_taken = gen_label_rtx ();
11414 taken = operands[0];
11416 /* Generate the reversed branch to NOT_TAKEN. */
11417 operands[0] = not_taken;
11418 output_asm_insn (branch_if_false, operands);
11420 /* If INSN has a delay slot, we must provide delay slots for both the
11421 branch to NOT_TAKEN and the conditional jump. We must also ensure
11422 that INSN's delay slot is executed in the appropriate cases. */
11423 if (final_sequence)
11425 /* This first delay slot will always be executed, so use INSN's
11426 delay slot if is not annulled. */
11427 if (!INSN_ANNULLED_BRANCH_P (insn))
11429 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11430 asm_out_file, optimize, 1, NULL);
11431 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11434 output_asm_insn ("nop", 0);
11435 fprintf (asm_out_file, "\n");
11438 /* Output the unconditional branch to TAKEN. */
11439 if (TARGET_ABSOLUTE_JUMPS)
11440 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
11443 mips_output_load_label (taken);
11444 output_asm_insn ("jr\t%@%]%/", 0);
11447 /* Now deal with its delay slot; see above. */
11448 if (final_sequence)
11450 /* This delay slot will only be executed if the branch is taken.
11451 Use INSN's delay slot if is annulled. */
11452 if (INSN_ANNULLED_BRANCH_P (insn))
11454 final_scan_insn (XVECEXP (final_sequence, 0, 1),
11455 asm_out_file, optimize, 1, NULL);
11456 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
11459 output_asm_insn ("nop", 0);
11460 fprintf (asm_out_file, "\n");
11463 /* Output NOT_TAKEN. */
11464 targetm.asm_out.internal_label (asm_out_file, "L",
11465 CODE_LABEL_NUMBER (not_taken));
11469 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11470 if some ordering condition is true. The condition is given by
11471 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11472 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11473 its second is always zero. */
11476 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
11478 const char *branch[2];
11480 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11481 Make BRANCH[0] branch on the inverse condition. */
11482 switch (GET_CODE (operands[1]))
11484 /* These cases are equivalent to comparisons against zero. */
11486 inverted_p = !inverted_p;
11487 /* Fall through. */
11489 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
11490 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
11493 /* These cases are always true or always false. */
11495 inverted_p = !inverted_p;
11496 /* Fall through. */
11498 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
11499 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
11503 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
11504 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
11507 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
11510 /* Start a block of code that needs access to the LL, SC and SYNC
11514 mips_start_ll_sc_sync_block (void)
11516 if (!ISA_HAS_LL_SC)
11518 output_asm_insn (".set\tpush", 0);
11519 output_asm_insn (".set\tmips2", 0);
11523 /* End a block started by mips_start_ll_sc_sync_block. */
11526 mips_end_ll_sc_sync_block (void)
11528 if (!ISA_HAS_LL_SC)
11529 output_asm_insn (".set\tpop", 0);
11532 /* Output and/or return the asm template for a sync instruction. */
11535 mips_output_sync (void)
11537 mips_start_ll_sc_sync_block ();
11538 output_asm_insn ("sync", 0);
11539 mips_end_ll_sc_sync_block ();
11543 /* Return the asm template associated with sync_insn1 value TYPE.
11544 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11546 static const char *
11547 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
11551 case SYNC_INSN1_MOVE:
11552 return "move\t%0,%z2";
11553 case SYNC_INSN1_LI:
11554 return "li\t%0,%2";
11555 case SYNC_INSN1_ADDU:
11556 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11557 case SYNC_INSN1_ADDIU:
11558 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11559 case SYNC_INSN1_SUBU:
11560 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11561 case SYNC_INSN1_AND:
11562 return "and\t%0,%1,%z2";
11563 case SYNC_INSN1_ANDI:
11564 return "andi\t%0,%1,%2";
11565 case SYNC_INSN1_OR:
11566 return "or\t%0,%1,%z2";
11567 case SYNC_INSN1_ORI:
11568 return "ori\t%0,%1,%2";
11569 case SYNC_INSN1_XOR:
11570 return "xor\t%0,%1,%z2";
11571 case SYNC_INSN1_XORI:
11572 return "xori\t%0,%1,%2";
11574 gcc_unreachable ();
11577 /* Return the asm template associated with sync_insn2 value TYPE. */
11579 static const char *
11580 mips_sync_insn2_template (enum attr_sync_insn2 type)
11584 case SYNC_INSN2_NOP:
11585 gcc_unreachable ();
11586 case SYNC_INSN2_AND:
11587 return "and\t%0,%1,%z2";
11588 case SYNC_INSN2_XOR:
11589 return "xor\t%0,%1,%z2";
11590 case SYNC_INSN2_NOT:
11591 return "nor\t%0,%1,%.";
11593 gcc_unreachable ();
11596 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11597 the value of the one of the sync_* attributes. Return the operand
11598 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11599 have the associated attribute. */
11602 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
11605 default_value = operands[index - 1];
11606 return default_value;
11609 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11610 sequence for it. */
11613 mips_process_sync_loop (rtx insn, rtx *operands)
11615 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
11616 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3;
11617 unsigned int tmp3_insn;
11618 enum attr_sync_insn1 insn1;
11619 enum attr_sync_insn2 insn2;
11622 /* Read an operand from the sync_WHAT attribute and store it in
11623 variable WHAT. DEFAULT is the default value if no attribute
11625 #define READ_OPERAND(WHAT, DEFAULT) \
11626 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11629 /* Read the memory. */
11630 READ_OPERAND (mem, 0);
11632 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
11634 /* Read the other attributes. */
11635 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
11636 READ_OPERAND (oldval, at);
11637 READ_OPERAND (newval, at);
11638 READ_OPERAND (inclusive_mask, 0);
11639 READ_OPERAND (exclusive_mask, 0);
11640 READ_OPERAND (required_oldval, 0);
11641 READ_OPERAND (insn1_op2, 0);
11642 insn1 = get_attr_sync_insn1 (insn);
11643 insn2 = get_attr_sync_insn2 (insn);
11645 mips_multi_start ();
11647 /* Output the release side of the memory barrier. */
11648 if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES)
11650 if (required_oldval == 0 && TARGET_OCTEON)
11652 /* Octeon doesn't reorder reads, so a full barrier can be
11653 created by using SYNCW to order writes combined with the
11654 write from the following SC. When the SC successfully
11655 completes, we know that all preceding writes are also
11656 committed to the coherent memory system. It is possible
11657 for a single SYNCW to fail, but a pair of them will never
11658 fail, so we use two. */
11659 mips_multi_add_insn ("syncw", NULL);
11660 mips_multi_add_insn ("syncw", NULL);
11663 mips_multi_add_insn ("sync", NULL);
11666 /* Output the branch-back label. */
11667 mips_multi_add_label ("1:");
11669 /* OLDVAL = *MEM. */
11670 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
11671 oldval, mem, NULL);
11673 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11674 if (required_oldval)
11676 if (inclusive_mask == 0)
11680 gcc_assert (oldval != at);
11681 mips_multi_add_insn ("and\t%0,%1,%2",
11682 at, oldval, inclusive_mask, NULL);
11685 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
11688 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11689 if (exclusive_mask == 0)
11693 gcc_assert (oldval != at);
11694 mips_multi_add_insn ("and\t%0,%1,%z2",
11695 at, oldval, exclusive_mask, NULL);
11699 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11701 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11702 at least one instruction in that case. */
11703 if (insn1 == SYNC_INSN1_MOVE
11704 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
11708 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
11709 newval, oldval, insn1_op2, NULL);
11713 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11714 if (insn2 == SYNC_INSN2_NOP)
11718 mips_multi_add_insn (mips_sync_insn2_template (insn2),
11719 newval, tmp2, inclusive_mask, NULL);
11722 tmp3_insn = mips_multi_last_index ();
11724 /* $AT = $TMP1 | $TMP3. */
11725 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
11727 mips_multi_set_operand (tmp3_insn, 0, at);
11732 gcc_assert (tmp1 != tmp3);
11733 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
11736 /* if (!commit (*MEM = $AT)) goto 1.
11738 This will sometimes be a delayed branch; see the write code below
11740 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
11741 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
11743 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11744 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
11746 mips_multi_copy_insn (tmp3_insn);
11747 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
11750 mips_multi_add_insn ("nop", NULL);
11752 /* Output the acquire side of the memory barrier. */
11753 if (TARGET_SYNC_AFTER_SC)
11754 mips_multi_add_insn ("sync", NULL);
11756 /* Output the exit label, if needed. */
11757 if (required_oldval)
11758 mips_multi_add_label ("2:");
11760 #undef READ_OPERAND
11763 /* Output and/or return the asm template for sync loop INSN, which has
11764 the operands given by OPERANDS. */
11767 mips_output_sync_loop (rtx insn, rtx *operands)
11769 mips_process_sync_loop (insn, operands);
11771 /* Use branch-likely instructions to work around the LL/SC R10000
11773 mips_branch_likely = TARGET_FIX_R10000;
11775 mips_push_asm_switch (&mips_noreorder);
11776 mips_push_asm_switch (&mips_nomacro);
11777 mips_push_asm_switch (&mips_noat);
11778 mips_start_ll_sc_sync_block ();
11780 mips_multi_write ();
11782 mips_end_ll_sc_sync_block ();
11783 mips_pop_asm_switch (&mips_noat);
11784 mips_pop_asm_switch (&mips_nomacro);
11785 mips_pop_asm_switch (&mips_noreorder);
11790 /* Return the number of individual instructions in sync loop INSN,
11791 which has the operands given by OPERANDS. */
11794 mips_sync_loop_insns (rtx insn, rtx *operands)
11796 mips_process_sync_loop (insn, operands);
11797 return mips_multi_num_insns;
11800 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11801 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11803 When working around R4000 and R4400 errata, we need to make sure that
11804 the division is not immediately followed by a shift[1][2]. We also
11805 need to stop the division from being put into a branch delay slot[3].
11806 The easiest way to avoid both problems is to add a nop after the
11807 division. When a divide-by-zero check is needed, this nop can be
11808 used to fill the branch delay slot.
11810 [1] If a double-word or a variable shift executes immediately
11811 after starting an integer division, the shift may give an
11812 incorrect result. See quotations of errata #16 and #28 from
11813 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11814 in mips.md for details.
11816 [2] A similar bug to [1] exists for all revisions of the
11817 R4000 and the R4400 when run in an MC configuration.
11818 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11820 "19. In this following sequence:
11822 ddiv (or ddivu or div or divu)
11823 dsll32 (or dsrl32, dsra32)
11825 if an MPT stall occurs, while the divide is slipping the cpu
11826 pipeline, then the following double shift would end up with an
11829 Workaround: The compiler needs to avoid generating any
11830 sequence with divide followed by extended double shift."
11832 This erratum is also present in "MIPS R4400MC Errata, Processor
11833 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11834 & 3.0" as errata #10 and #4, respectively.
11836 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11837 (also valid for MIPS R4000MC processors):
11839 "52. R4000SC: This bug does not apply for the R4000PC.
11841 There are two flavors of this bug:
11843 1) If the instruction just after divide takes an RF exception
11844 (tlb-refill, tlb-invalid) and gets an instruction cache
11845 miss (both primary and secondary) and the line which is
11846 currently in secondary cache at this index had the first
11847 data word, where the bits 5..2 are set, then R4000 would
11848 get a wrong result for the div.
11853 ------------------- # end-of page. -tlb-refill
11858 ------------------- # end-of page. -tlb-invalid
11861 2) If the divide is in the taken branch delay slot, where the
11862 target takes RF exception and gets an I-cache miss for the
11863 exception vector or where I-cache miss occurs for the
11864 target address, under the above mentioned scenarios, the
11865 div would get wrong results.
11868 j r2 # to next page mapped or unmapped
11869 div r8,r9 # this bug would be there as long
11870 # as there is an ICache miss and
11871 nop # the "data pattern" is present
11874 beq r0, r0, NextPage # to Next page
11878 This bug is present for div, divu, ddiv, and ddivu
11881 Workaround: For item 1), OS could make sure that the next page
11882 after the divide instruction is also mapped. For item 2), the
11883 compiler could make sure that the divide instruction is not in
11884 the branch delay slot."
11886 These processors have PRId values of 0x00004220 and 0x00004300 for
11887 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11890 mips_output_division (const char *division, rtx *operands)
11895 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
11897 output_asm_insn (s, operands);
11900 if (TARGET_CHECK_ZERO_DIV)
11904 output_asm_insn (s, operands);
11905 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
11907 else if (GENERATE_DIVIDE_TRAPS)
11909 /* Avoid long replay penalty on load miss by putting the trap before
11912 output_asm_insn ("teq\t%2,%.,7", operands);
11915 output_asm_insn (s, operands);
11916 s = "teq\t%2,%.,7";
11921 output_asm_insn ("%(bne\t%2,%.,1f", operands);
11922 output_asm_insn (s, operands);
11923 s = "break\t7%)\n1:";
11929 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11930 instruction and if OUT_INSN assigns to the accumulator operand. */
11933 mips_linked_madd_p (rtx out_insn, rtx in_insn)
11937 x = single_set (in_insn);
11943 if (GET_CODE (x) == PLUS
11944 && GET_CODE (XEXP (x, 0)) == MULT
11945 && reg_set_p (XEXP (x, 1), out_insn))
11948 if (GET_CODE (x) == MINUS
11949 && GET_CODE (XEXP (x, 1)) == MULT
11950 && reg_set_p (XEXP (x, 0), out_insn))
11956 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11957 data rather than the address. We need this because the cprestore
11958 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11959 which causes the default routine to abort. We just return false
11963 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
11965 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
11968 return !store_data_bypass_p (out_insn, in_insn);
11972 /* Variables and flags used in scheduler hooks when tuning for
11976 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11979 /* If true, then next ALU1/2 instruction will go to ALU1. */
11982 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11985 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11986 int alu1_core_unit_code;
11987 int alu2_core_unit_code;
11988 int falu1_core_unit_code;
11989 int falu2_core_unit_code;
11991 /* True if current cycle has a multi instruction.
11992 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11993 bool cycle_has_multi_p;
11995 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11996 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11998 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11999 instruction to go ALU1. */
12000 rtx alu1_turn_enabled_insn;
12001 rtx alu2_turn_enabled_insn;
12002 rtx falu1_turn_enabled_insn;
12003 rtx falu2_turn_enabled_insn;
12006 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12007 dependencies have no cost, except on the 20Kc where output-dependence
12008 is treated like input-dependence. */
12011 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12012 rtx dep ATTRIBUTE_UNUSED, int cost)
12014 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12017 if (REG_NOTE_KIND (link) != 0)
12022 /* Return the number of instructions that can be issued per cycle. */
12025 mips_issue_rate (void)
12029 case PROCESSOR_74KC:
12030 case PROCESSOR_74KF2_1:
12031 case PROCESSOR_74KF1_1:
12032 case PROCESSOR_74KF3_2:
12033 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12034 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12035 but in reality only a maximum of 3 insns can be issued as
12036 floating-point loads and stores also require a slot in the
12038 case PROCESSOR_R10000:
12039 /* All R10K Processors are quad-issue (being the first MIPS
12040 processors to support this feature). */
12043 case PROCESSOR_20KC:
12044 case PROCESSOR_R4130:
12045 case PROCESSOR_R5400:
12046 case PROCESSOR_R5500:
12047 case PROCESSOR_R7000:
12048 case PROCESSOR_R9000:
12049 case PROCESSOR_OCTEON:
12052 case PROCESSOR_SB1:
12053 case PROCESSOR_SB1A:
12054 /* This is actually 4, but we get better performance if we claim 3.
12055 This is partly because of unwanted speculative code motion with the
12056 larger number, and partly because in most common cases we can't
12057 reach the theoretical max of 4. */
12060 case PROCESSOR_LOONGSON_2E:
12061 case PROCESSOR_LOONGSON_2F:
12062 case PROCESSOR_LOONGSON_3A:
12070 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12073 mips_ls2_init_dfa_post_cycle_insn (void)
12076 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12077 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12081 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12082 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12086 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12087 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12091 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12092 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12095 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12096 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12097 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12098 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12101 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12102 Init data used in mips_dfa_post_advance_cycle. */
12105 mips_init_dfa_post_cycle_insn (void)
12107 if (TUNE_LOONGSON_2EF)
12108 mips_ls2_init_dfa_post_cycle_insn ();
12111 /* Initialize STATE when scheduling for Loongson 2E/2F.
12112 Support round-robin dispatch scheme by enabling only one of
12113 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12117 mips_ls2_dfa_post_advance_cycle (state_t state)
12119 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12121 /* Though there are no non-pipelined ALU1 insns,
12122 we can get an instruction of type 'multi' before reload. */
12123 gcc_assert (mips_ls2.cycle_has_multi_p);
12124 mips_ls2.alu1_turn_p = false;
12127 mips_ls2.cycle_has_multi_p = false;
12129 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12130 /* We have a non-pipelined alu instruction in the core,
12131 adjust round-robin counter. */
12132 mips_ls2.alu1_turn_p = true;
12134 if (mips_ls2.alu1_turn_p)
12136 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12137 gcc_unreachable ();
12141 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12142 gcc_unreachable ();
12145 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12147 /* There are no non-pipelined FALU1 insns. */
12148 gcc_unreachable ();
12149 mips_ls2.falu1_turn_p = false;
12152 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12153 /* We have a non-pipelined falu instruction in the core,
12154 adjust round-robin counter. */
12155 mips_ls2.falu1_turn_p = true;
12157 if (mips_ls2.falu1_turn_p)
12159 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12160 gcc_unreachable ();
12164 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12165 gcc_unreachable ();
12169 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12170 This hook is being called at the start of each cycle. */
12173 mips_dfa_post_advance_cycle (void)
12175 if (TUNE_LOONGSON_2EF)
12176 mips_ls2_dfa_post_advance_cycle (curr_state);
12179 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12180 be as wide as the scheduling freedom in the DFA. */
12183 mips_multipass_dfa_lookahead (void)
12185 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12189 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12198 /* Remove the instruction at index LOWER from ready queue READY and
12199 reinsert it in front of the instruction at index HIGHER. LOWER must
12203 mips_promote_ready (rtx *ready, int lower, int higher)
12208 new_head = ready[lower];
12209 for (i = lower; i < higher; i++)
12210 ready[i] = ready[i + 1];
12211 ready[i] = new_head;
12214 /* If the priority of the instruction at POS2 in the ready queue READY
12215 is within LIMIT units of that of the instruction at POS1, swap the
12216 instructions if POS2 is not already less than POS1. */
12219 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12222 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12226 temp = ready[pos1];
12227 ready[pos1] = ready[pos2];
12228 ready[pos2] = temp;
12232 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12233 that may clobber hi or lo. */
12234 static rtx mips_macc_chains_last_hilo;
12236 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12237 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12240 mips_macc_chains_record (rtx insn)
12242 if (get_attr_may_clobber_hilo (insn))
12243 mips_macc_chains_last_hilo = insn;
12246 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12247 has NREADY elements, looking for a multiply-add or multiply-subtract
12248 instruction that is cumulative with mips_macc_chains_last_hilo.
12249 If there is one, promote it ahead of anything else that might
12250 clobber hi or lo. */
12253 mips_macc_chains_reorder (rtx *ready, int nready)
12257 if (mips_macc_chains_last_hilo != 0)
12258 for (i = nready - 1; i >= 0; i--)
12259 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12261 for (j = nready - 1; j > i; j--)
12262 if (recog_memoized (ready[j]) >= 0
12263 && get_attr_may_clobber_hilo (ready[j]))
12265 mips_promote_ready (ready, i, j);
12272 /* The last instruction to be scheduled. */
12273 static rtx vr4130_last_insn;
12275 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12276 points to an rtx that is initially an instruction. Nullify the rtx
12277 if the instruction uses the value of register X. */
12280 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12285 insn_ptr = (rtx *) data;
12288 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12292 /* Return true if there is true register dependence between vr4130_last_insn
12296 vr4130_true_reg_dependence_p (rtx insn)
12298 note_stores (PATTERN (vr4130_last_insn),
12299 vr4130_true_reg_dependence_p_1, &insn);
12303 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12304 the ready queue and that INSN2 is the instruction after it, return
12305 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12306 in which INSN1 and INSN2 can probably issue in parallel, but for
12307 which (INSN2, INSN1) should be less sensitive to instruction
12308 alignment than (INSN1, INSN2). See 4130.md for more details. */
12311 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12313 sd_iterator_def sd_it;
12316 /* Check for the following case:
12318 1) there is some other instruction X with an anti dependence on INSN1;
12319 2) X has a higher priority than INSN2; and
12320 3) X is an arithmetic instruction (and thus has no unit restrictions).
12322 If INSN1 is the last instruction blocking X, it would better to
12323 choose (INSN1, X) over (INSN2, INSN1). */
12324 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12325 if (DEP_TYPE (dep) == REG_DEP_ANTI
12326 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12327 && recog_memoized (DEP_CON (dep)) >= 0
12328 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12331 if (vr4130_last_insn != 0
12332 && recog_memoized (insn1) >= 0
12333 && recog_memoized (insn2) >= 0)
12335 /* See whether INSN1 and INSN2 use different execution units,
12336 or if they are both ALU-type instructions. If so, they can
12337 probably execute in parallel. */
12338 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12339 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12340 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12342 /* If only one of the instructions has a dependence on
12343 vr4130_last_insn, prefer to schedule the other one first. */
12344 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12345 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12346 if (dep1_p != dep2_p)
12349 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12350 is not an ALU-type instruction and if INSN1 uses the same
12351 execution unit. (Note that if this condition holds, we already
12352 know that INSN2 uses a different execution unit.) */
12353 if (class1 != VR4130_CLASS_ALU
12354 && recog_memoized (vr4130_last_insn) >= 0
12355 && class1 == get_attr_vr4130_class (vr4130_last_insn))
12362 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12363 queue with at least two instructions. Swap the first two if
12364 vr4130_swap_insns_p says that it could be worthwhile. */
12367 vr4130_reorder (rtx *ready, int nready)
12369 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
12370 mips_promote_ready (ready, nready - 2, nready - 1);
12373 /* Record whether last 74k AGEN instruction was a load or store. */
12374 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
12376 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12377 resets to TYPE_UNKNOWN state. */
12380 mips_74k_agen_init (rtx insn)
12382 if (!insn || CALL_P (insn) || JUMP_P (insn))
12383 mips_last_74k_agen_insn = TYPE_UNKNOWN;
12386 enum attr_type type = get_attr_type (insn);
12387 if (type == TYPE_LOAD || type == TYPE_STORE)
12388 mips_last_74k_agen_insn = type;
12392 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12393 loads to be grouped together, and multiple stores to be grouped
12394 together. Swap things around in the ready queue to make this happen. */
12397 mips_74k_agen_reorder (rtx *ready, int nready)
12400 int store_pos, load_pos;
12405 for (i = nready - 1; i >= 0; i--)
12407 rtx insn = ready[i];
12408 if (USEFUL_INSN_P (insn))
12409 switch (get_attr_type (insn))
12412 if (store_pos == -1)
12417 if (load_pos == -1)
12426 if (load_pos == -1 || store_pos == -1)
12429 switch (mips_last_74k_agen_insn)
12432 /* Prefer to schedule loads since they have a higher latency. */
12434 /* Swap loads to the front of the queue. */
12435 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
12438 /* Swap stores to the front of the queue. */
12439 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
12446 /* Implement TARGET_SCHED_INIT. */
12449 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12450 int max_ready ATTRIBUTE_UNUSED)
12452 mips_macc_chains_last_hilo = 0;
12453 vr4130_last_insn = 0;
12454 mips_74k_agen_init (NULL_RTX);
12456 /* When scheduling for Loongson2, branch instructions go to ALU1,
12457 therefore basic block is most likely to start with round-robin counter
12458 pointed to ALU2. */
12459 mips_ls2.alu1_turn_p = false;
12460 mips_ls2.falu1_turn_p = true;
12463 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12466 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12467 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12469 if (!reload_completed
12470 && TUNE_MACC_CHAINS
12472 mips_macc_chains_reorder (ready, *nreadyp);
12474 if (reload_completed
12476 && !TARGET_VR4130_ALIGN
12478 vr4130_reorder (ready, *nreadyp);
12481 mips_74k_agen_reorder (ready, *nreadyp);
12484 /* Implement TARGET_SCHED_REORDER. */
12487 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12488 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12490 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12491 return mips_issue_rate ();
12494 /* Implement TARGET_SCHED_REORDER2. */
12497 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12498 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
12500 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
12501 return cached_can_issue_more;
12504 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12507 mips_ls2_variable_issue (rtx insn)
12509 if (mips_ls2.alu1_turn_p)
12511 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
12512 mips_ls2.alu1_turn_p = false;
12516 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
12517 mips_ls2.alu1_turn_p = true;
12520 if (mips_ls2.falu1_turn_p)
12522 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
12523 mips_ls2.falu1_turn_p = false;
12527 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
12528 mips_ls2.falu1_turn_p = true;
12531 if (recog_memoized (insn) >= 0)
12532 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
12535 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12538 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
12539 rtx insn, int more)
12541 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12542 if (USEFUL_INSN_P (insn))
12544 if (get_attr_type (insn) != TYPE_GHOST)
12546 if (!reload_completed && TUNE_MACC_CHAINS)
12547 mips_macc_chains_record (insn);
12548 vr4130_last_insn = insn;
12550 mips_74k_agen_init (insn);
12551 else if (TUNE_LOONGSON_2EF)
12552 mips_ls2_variable_issue (insn);
12555 /* Instructions of type 'multi' should all be split before
12556 the second scheduling pass. */
12557 gcc_assert (!reload_completed
12558 || recog_memoized (insn) < 0
12559 || get_attr_type (insn) != TYPE_MULTI);
12561 cached_can_issue_more = more;
12565 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12566 return the first operand of the associated PREF or PREFX insn. */
12569 mips_prefetch_cookie (rtx write, rtx locality)
12571 /* store_streamed / load_streamed. */
12572 if (INTVAL (locality) <= 0)
12573 return GEN_INT (INTVAL (write) + 4);
12575 /* store / load. */
12576 if (INTVAL (locality) <= 2)
12579 /* store_retained / load_retained. */
12580 return GEN_INT (INTVAL (write) + 6);
12583 /* Flags that indicate when a built-in function is available.
12585 BUILTIN_AVAIL_NON_MIPS16
12586 The function is available on the current target, but only
12587 in non-MIPS16 mode. */
12588 #define BUILTIN_AVAIL_NON_MIPS16 1
12590 /* Declare an availability predicate for built-in functions that
12591 require non-MIPS16 mode and also require COND to be true.
12592 NAME is the main part of the predicate's name. */
12593 #define AVAIL_NON_MIPS16(NAME, COND) \
12594 static unsigned int \
12595 mips_builtin_avail_##NAME (void) \
12597 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12600 /* This structure describes a single built-in function. */
12601 struct mips_builtin_description {
12602 /* The code of the main .md file instruction. See mips_builtin_type
12603 for more information. */
12604 enum insn_code icode;
12606 /* The floating-point comparison code to use with ICODE, if any. */
12607 enum mips_fp_condition cond;
12609 /* The name of the built-in function. */
12612 /* Specifies how the function should be expanded. */
12613 enum mips_builtin_type builtin_type;
12615 /* The function's prototype. */
12616 enum mips_function_type function_type;
12618 /* Whether the function is available. */
12619 unsigned int (*avail) (void);
12622 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
12623 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
12624 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
12625 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
12626 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
12627 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
12628 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
12629 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
12630 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
12632 /* Construct a mips_builtin_description from the given arguments.
12634 INSN is the name of the associated instruction pattern, without the
12635 leading CODE_FOR_mips_.
12637 CODE is the floating-point condition code associated with the
12638 function. It can be 'f' if the field is not applicable.
12640 NAME is the name of the function itself, without the leading
12643 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12645 AVAIL is the name of the availability predicate, without the leading
12646 mips_builtin_avail_. */
12647 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12648 FUNCTION_TYPE, AVAIL) \
12649 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12650 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12651 mips_builtin_avail_ ## AVAIL }
12653 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12654 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12655 are as for MIPS_BUILTIN. */
12656 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12657 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12659 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12660 are subject to mips_builtin_avail_<AVAIL>. */
12661 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12662 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12663 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12664 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12665 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12667 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12668 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12669 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12670 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12671 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12672 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12674 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12675 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12677 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12678 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12680 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12681 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12684 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12685 are subject to mips_builtin_avail_mips3d. */
12686 #define CMP_4S_BUILTINS(INSN, COND) \
12687 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12688 MIPS_BUILTIN_CMP_ANY, \
12689 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12690 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12691 MIPS_BUILTIN_CMP_ALL, \
12692 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12694 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12695 instruction requires mips_builtin_avail_<AVAIL>. */
12696 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12697 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12698 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12700 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12701 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12704 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12705 #define CMP_BUILTINS(COND) \
12706 MOVTF_BUILTINS (c, COND, paired_single), \
12707 MOVTF_BUILTINS (cabs, COND, mips3d), \
12708 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12709 CMP_PS_BUILTINS (c, COND, paired_single), \
12710 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12711 CMP_4S_BUILTINS (c, COND), \
12712 CMP_4S_BUILTINS (cabs, COND)
12714 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12715 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12716 and AVAIL are as for MIPS_BUILTIN. */
12717 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12718 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12719 FUNCTION_TYPE, AVAIL)
12721 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12722 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12723 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12724 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12725 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12727 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12728 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12729 builtin_description field. */
12730 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12731 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12732 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12733 FUNCTION_TYPE, mips_builtin_avail_loongson }
12735 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12736 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12737 builtin_description field. */
12738 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12739 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12741 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12742 We use functions of this form when the same insn can be usefully applied
12743 to more than one datatype. */
12744 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12745 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12747 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12748 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12749 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12750 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12751 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12752 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12753 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12754 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12756 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12757 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12758 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12759 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12760 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12761 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12762 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12763 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12764 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12765 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12766 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12767 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12768 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12769 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12770 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12771 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12772 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12773 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12774 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12775 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12776 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12777 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12778 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12779 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12780 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12781 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12782 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12783 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12784 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12785 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12786 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12787 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12788 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12789 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12790 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12791 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12793 static const struct mips_builtin_description mips_builtins[] = {
12794 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12795 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12796 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12797 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
12798 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
12799 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
12800 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
12801 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
12803 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
12804 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12805 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12806 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12807 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
12809 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
12810 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
12811 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12812 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12813 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12814 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12816 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
12817 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
12818 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
12819 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
12820 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
12821 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
12823 MIPS_FP_CONDITIONS (CMP_BUILTINS),
12825 /* Built-in functions for the SB-1 processor. */
12826 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
12828 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12829 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12830 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12831 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12832 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12833 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12834 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12835 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12836 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12837 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12838 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12839 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
12840 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
12841 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
12842 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
12843 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
12844 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
12845 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12846 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12847 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
12848 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
12849 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
12850 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
12851 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12852 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12853 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12854 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12855 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
12856 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
12857 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
12858 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
12859 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12860 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12861 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12862 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
12863 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
12864 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12865 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
12866 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
12867 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12868 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
12869 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12870 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12871 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
12872 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
12873 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
12874 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
12875 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
12876 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12877 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12878 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
12879 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12880 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12881 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
12882 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12883 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12884 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
12885 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
12886 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12887 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
12888 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
12889 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
12890 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
12891 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12892 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
12893 BPOSGE_BUILTIN (32, dsp),
12895 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12896 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
12897 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12898 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12899 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12900 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12901 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12902 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12903 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12904 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12905 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
12906 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12907 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12908 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12909 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12910 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12911 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
12912 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12913 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
12914 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
12915 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12916 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
12917 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
12918 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12919 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12920 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12921 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
12922 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12923 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12924 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12925 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12926 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12927 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
12928 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12929 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
12931 /* Built-in functions for the DSP ASE (32-bit only). */
12932 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12933 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12934 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12935 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
12936 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12937 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12938 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12939 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12940 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12941 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12942 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12943 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12944 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
12945 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12946 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12947 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
12948 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
12949 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12950 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
12951 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
12952 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
12953 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12954 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12955 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
12956 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
12957 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
12958 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
12960 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12961 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12962 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12963 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12964 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12965 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12966 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12967 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12968 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12969 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
12971 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12972 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
12973 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
12974 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
12975 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12976 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12977 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12978 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
12979 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
12980 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
12981 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
12982 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
12983 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12984 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12985 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12986 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12987 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
12988 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12989 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12990 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12991 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
12992 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
12993 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
12994 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
12995 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12996 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
12997 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
12998 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
12999 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13000 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13001 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13002 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13003 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13004 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13005 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13006 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13007 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13008 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13009 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13010 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13011 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13012 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13013 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13014 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13015 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13016 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13017 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13018 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13019 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13020 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13021 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13022 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13023 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13024 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13025 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13026 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13027 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13028 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13029 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13030 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13031 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13032 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13033 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI),
13034 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI),
13035 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13036 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13037 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13038 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13039 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13040 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13041 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13042 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13043 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13044 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13045 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13046 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13047 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13048 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13049 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13050 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13051 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13052 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13053 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13054 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13055 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13056 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13057 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13058 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13059 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13060 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13061 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13062 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13063 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13064 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13065 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13066 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13067 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13068 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13069 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13070 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13072 /* Sundry other built-in functions. */
13073 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13076 /* Index I is the function declaration for mips_builtins[I], or null if the
13077 function isn't defined on this target. */
13078 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13080 /* MODE is a vector mode whose elements have type TYPE. Return the type
13081 of the vector itself. */
13084 mips_builtin_vector_type (tree type, enum machine_mode mode)
13086 static tree types[2 * (int) MAX_MACHINE_MODE];
13089 mode_index = (int) mode;
13091 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13092 mode_index += MAX_MACHINE_MODE;
13094 if (types[mode_index] == NULL_TREE)
13095 types[mode_index] = build_vector_type_for_mode (type, mode);
13096 return types[mode_index];
13099 /* Return a type for 'const volatile void *'. */
13102 mips_build_cvpointer_type (void)
13106 if (cache == NULL_TREE)
13107 cache = build_pointer_type (build_qualified_type
13109 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13113 /* Source-level argument types. */
13114 #define MIPS_ATYPE_VOID void_type_node
13115 #define MIPS_ATYPE_INT integer_type_node
13116 #define MIPS_ATYPE_POINTER ptr_type_node
13117 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13119 /* Standard mode-based argument types. */
13120 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13121 #define MIPS_ATYPE_SI intSI_type_node
13122 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13123 #define MIPS_ATYPE_DI intDI_type_node
13124 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13125 #define MIPS_ATYPE_SF float_type_node
13126 #define MIPS_ATYPE_DF double_type_node
13128 /* Vector argument types. */
13129 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13130 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13131 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13132 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13133 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13134 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13135 #define MIPS_ATYPE_UV2SI \
13136 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13137 #define MIPS_ATYPE_UV4HI \
13138 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13139 #define MIPS_ATYPE_UV8QI \
13140 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13142 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13143 their associated MIPS_ATYPEs. */
13144 #define MIPS_FTYPE_ATYPES1(A, B) \
13145 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13147 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13148 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13150 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13151 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13153 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13154 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13157 /* Return the function type associated with function prototype TYPE. */
13160 mips_build_function_type (enum mips_function_type type)
13162 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13164 if (types[(int) type] == NULL_TREE)
13167 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13168 case MIPS_FTYPE_NAME##NUM ARGS: \
13169 types[(int) type] \
13170 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13173 #include "config/mips/mips-ftypes.def"
13174 #undef DEF_MIPS_FTYPE
13176 gcc_unreachable ();
13179 return types[(int) type];
13182 /* Implement TARGET_INIT_BUILTINS. */
13185 mips_init_builtins (void)
13187 const struct mips_builtin_description *d;
13190 /* Iterate through all of the bdesc arrays, initializing all of the
13191 builtin functions. */
13192 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13194 d = &mips_builtins[i];
13196 mips_builtin_decls[i]
13197 = add_builtin_function (d->name,
13198 mips_build_function_type (d->function_type),
13199 i, BUILT_IN_MD, NULL, NULL);
13203 /* Implement TARGET_BUILTIN_DECL. */
13206 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13208 if (code >= ARRAY_SIZE (mips_builtins))
13209 return error_mark_node;
13210 return mips_builtin_decls[code];
13213 /* Take argument ARGNO from EXP's argument list and convert it into
13214 an expand operand. Store the operand in *OP. */
13217 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13218 unsigned int argno)
13223 arg = CALL_EXPR_ARG (exp, argno);
13224 value = expand_normal (arg);
13225 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13228 /* Expand instruction ICODE as part of a built-in function sequence.
13229 Use the first NOPS elements of OPS as the instruction's operands.
13230 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13231 instruction has no target.
13233 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13236 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13237 struct expand_operand *ops, bool has_target_p)
13239 if (!maybe_expand_insn (icode, nops, ops))
13241 error ("invalid argument to built-in function");
13242 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13244 return has_target_p ? ops[0].value : const0_rtx;
13247 /* Expand a floating-point comparison for built-in function call EXP.
13248 The first NARGS arguments are the values to be compared. ICODE is
13249 the .md pattern that does the comparison and COND is the condition
13250 that is being tested. Return an rtx for the result. */
13253 mips_expand_builtin_compare_1 (enum insn_code icode,
13254 enum mips_fp_condition cond,
13255 tree exp, int nargs)
13257 struct expand_operand ops[MAX_RECOG_OPERANDS];
13260 /* The instruction should have a target operand, an operand for each
13261 argument, and an operand for COND. */
13262 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13265 create_output_operand (&ops[opno++], NULL_RTX,
13266 insn_data[(int) icode].operand[0].mode);
13267 for (argno = 0; argno < nargs; argno++)
13268 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13269 create_integer_operand (&ops[opno++], (int) cond);
13270 return mips_expand_builtin_insn (icode, opno, ops, true);
13273 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13274 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13275 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13276 suggests a good place to put the result. */
13279 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13282 struct expand_operand ops[MAX_RECOG_OPERANDS];
13285 /* Map any target to operand 0. */
13288 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13290 /* Map the arguments to the other operands. */
13291 gcc_assert (opno + call_expr_nargs (exp)
13292 == insn_data[icode].n_generator_args);
13293 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13294 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13296 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13299 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13300 function; TYPE says which. EXP is the CALL_EXPR that calls the
13301 function, ICODE is the instruction that should be used to compare
13302 the first two arguments, and COND is the condition it should test.
13303 TARGET, if nonnull, suggests a good place to put the result. */
13306 mips_expand_builtin_movtf (enum mips_builtin_type type,
13307 enum insn_code icode, enum mips_fp_condition cond,
13308 rtx target, tree exp)
13310 struct expand_operand ops[4];
13313 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13314 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13315 if (type == MIPS_BUILTIN_MOVT)
13317 mips_prepare_builtin_arg (&ops[2], exp, 2);
13318 mips_prepare_builtin_arg (&ops[1], exp, 3);
13322 mips_prepare_builtin_arg (&ops[1], exp, 2);
13323 mips_prepare_builtin_arg (&ops[2], exp, 3);
13325 create_fixed_operand (&ops[3], cmp_result);
13326 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13330 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13331 into TARGET otherwise. Return TARGET. */
13334 mips_builtin_branch_and_move (rtx condition, rtx target,
13335 rtx value_if_true, rtx value_if_false)
13337 rtx true_label, done_label;
13339 true_label = gen_label_rtx ();
13340 done_label = gen_label_rtx ();
13342 /* First assume that CONDITION is false. */
13343 mips_emit_move (target, value_if_false);
13345 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13346 emit_jump_insn (gen_condjump (condition, true_label));
13347 emit_jump_insn (gen_jump (done_label));
13350 /* Fix TARGET if CONDITION is true. */
13351 emit_label (true_label);
13352 mips_emit_move (target, value_if_true);
13354 emit_label (done_label);
13358 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13359 the CALL_EXPR that calls the function, ICODE is the code of the
13360 comparison instruction, and COND is the condition it should test.
13361 TARGET, if nonnull, suggests a good place to put the boolean result. */
13364 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
13365 enum insn_code icode, enum mips_fp_condition cond,
13366 rtx target, tree exp)
13368 rtx offset, condition, cmp_result;
13370 if (target == 0 || GET_MODE (target) != SImode)
13371 target = gen_reg_rtx (SImode);
13372 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
13373 call_expr_nargs (exp));
13375 /* If the comparison sets more than one register, we define the result
13376 to be 0 if all registers are false and -1 if all registers are true.
13377 The value of the complete result is indeterminate otherwise. */
13378 switch (builtin_type)
13380 case MIPS_BUILTIN_CMP_ALL:
13381 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
13382 return mips_builtin_branch_and_move (condition, target,
13383 const0_rtx, const1_rtx);
13385 case MIPS_BUILTIN_CMP_UPPER:
13386 case MIPS_BUILTIN_CMP_LOWER:
13387 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
13388 condition = gen_single_cc (cmp_result, offset);
13389 return mips_builtin_branch_and_move (condition, target,
13390 const1_rtx, const0_rtx);
13393 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
13394 return mips_builtin_branch_and_move (condition, target,
13395 const1_rtx, const0_rtx);
13399 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13400 if nonnull, suggests a good place to put the boolean result. */
13403 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
13405 rtx condition, cmp_result;
13408 if (target == 0 || GET_MODE (target) != SImode)
13409 target = gen_reg_rtx (SImode);
13411 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
13413 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
13418 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
13419 return mips_builtin_branch_and_move (condition, target,
13420 const1_rtx, const0_rtx);
13423 /* Implement TARGET_EXPAND_BUILTIN. */
13426 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13427 enum machine_mode mode, int ignore)
13430 unsigned int fcode, avail;
13431 const struct mips_builtin_description *d;
13433 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13434 fcode = DECL_FUNCTION_CODE (fndecl);
13435 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
13436 d = &mips_builtins[fcode];
13437 avail = d->avail ();
13438 gcc_assert (avail != 0);
13441 error ("built-in function %qE not supported for MIPS16",
13442 DECL_NAME (fndecl));
13443 return ignore ? const0_rtx : CONST0_RTX (mode);
13445 switch (d->builtin_type)
13447 case MIPS_BUILTIN_DIRECT:
13448 return mips_expand_builtin_direct (d->icode, target, exp, true);
13450 case MIPS_BUILTIN_DIRECT_NO_TARGET:
13451 return mips_expand_builtin_direct (d->icode, target, exp, false);
13453 case MIPS_BUILTIN_MOVT:
13454 case MIPS_BUILTIN_MOVF:
13455 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
13456 d->cond, target, exp);
13458 case MIPS_BUILTIN_CMP_ANY:
13459 case MIPS_BUILTIN_CMP_ALL:
13460 case MIPS_BUILTIN_CMP_UPPER:
13461 case MIPS_BUILTIN_CMP_LOWER:
13462 case MIPS_BUILTIN_CMP_SINGLE:
13463 return mips_expand_builtin_compare (d->builtin_type, d->icode,
13464 d->cond, target, exp);
13466 case MIPS_BUILTIN_BPOSGE32:
13467 return mips_expand_builtin_bposge (d->builtin_type, target);
13469 gcc_unreachable ();
13472 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13473 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13474 struct mips16_constant {
13475 struct mips16_constant *next;
13478 enum machine_mode mode;
13481 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13482 first constant, HIGHEST_ADDRESS is the highest address that the first
13483 byte of the pool can have, and INSN_ADDRESS is the current instruction
13485 struct mips16_constant_pool {
13486 struct mips16_constant *first;
13487 int highest_address;
13491 /* Add constant VALUE to POOL and return its label. MODE is the
13492 value's mode (used for CONST_INTs, etc.). */
13495 mips16_add_constant (struct mips16_constant_pool *pool,
13496 rtx value, enum machine_mode mode)
13498 struct mips16_constant **p, *c;
13499 bool first_of_size_p;
13501 /* See whether the constant is already in the pool. If so, return the
13502 existing label, otherwise leave P pointing to the place where the
13503 constant should be added.
13505 Keep the pool sorted in increasing order of mode size so that we can
13506 reduce the number of alignments needed. */
13507 first_of_size_p = true;
13508 for (p = &pool->first; *p != 0; p = &(*p)->next)
13510 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
13511 return (*p)->label;
13512 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
13514 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
13515 first_of_size_p = false;
13518 /* In the worst case, the constant needed by the earliest instruction
13519 will end up at the end of the pool. The entire pool must then be
13520 accessible from that instruction.
13522 When adding the first constant, set the pool's highest address to
13523 the address of the first out-of-range byte. Adjust this address
13524 downwards each time a new constant is added. */
13525 if (pool->first == 0)
13526 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13527 of the instruction with the lowest two bits clear. The base PC
13528 value for LDPC has the lowest three bits clear. Assume the worst
13529 case here; namely that the PC-relative instruction occupies the
13530 last 2 bytes in an aligned word. */
13531 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
13532 pool->highest_address -= GET_MODE_SIZE (mode);
13533 if (first_of_size_p)
13534 /* Take into account the worst possible padding due to alignment. */
13535 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
13537 /* Create a new entry. */
13538 c = XNEW (struct mips16_constant);
13541 c->label = gen_label_rtx ();
13548 /* Output constant VALUE after instruction INSN and return the last
13549 instruction emitted. MODE is the mode of the constant. */
13552 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
13554 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
13556 rtx size = GEN_INT (GET_MODE_SIZE (mode));
13557 return emit_insn_after (gen_consttable_int (value, size), insn);
13560 if (SCALAR_FLOAT_MODE_P (mode))
13561 return emit_insn_after (gen_consttable_float (value), insn);
13563 if (VECTOR_MODE_P (mode))
13567 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
13568 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
13569 CONST_VECTOR_ELT (value, i), insn);
13573 gcc_unreachable ();
13576 /* Dump out the constants in CONSTANTS after INSN. */
13579 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
13581 struct mips16_constant *c, *next;
13585 for (c = constants; c != NULL; c = next)
13587 /* If necessary, increase the alignment of PC. */
13588 if (align < GET_MODE_SIZE (c->mode))
13590 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
13591 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
13593 align = GET_MODE_SIZE (c->mode);
13595 insn = emit_label_after (c->label, insn);
13596 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
13602 emit_barrier_after (insn);
13605 /* Return the length of instruction INSN. */
13608 mips16_insn_length (rtx insn)
13612 rtx body = PATTERN (insn);
13613 if (GET_CODE (body) == ADDR_VEC)
13614 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
13615 if (GET_CODE (body) == ADDR_DIFF_VEC)
13616 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
13618 return get_attr_length (insn);
13621 /* If *X is a symbolic constant that refers to the constant pool, add
13622 the constant to POOL and rewrite *X to use the constant's label. */
13625 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
13627 rtx base, offset, label;
13629 split_const (*x, &base, &offset);
13630 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
13632 label = mips16_add_constant (pool, get_pool_constant (base),
13633 get_pool_mode (base));
13634 base = gen_rtx_LABEL_REF (Pmode, label);
13635 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
13639 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13640 INSN is the instruction we're rewriting and POOL points to the current
13642 struct mips16_rewrite_pool_refs_info {
13644 struct mips16_constant_pool *pool;
13647 /* Rewrite *X so that constant pool references refer to the constant's
13648 label instead. DATA points to a mips16_rewrite_pool_refs_info
13652 mips16_rewrite_pool_refs (rtx *x, void *data)
13654 struct mips16_rewrite_pool_refs_info *info =
13655 (struct mips16_rewrite_pool_refs_info *) data;
13657 if (force_to_mem_operand (*x, Pmode))
13659 rtx mem = force_const_mem (GET_MODE (*x), *x);
13660 validate_change (info->insn, x, mem, false);
13665 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
13669 if (TARGET_MIPS16_TEXT_LOADS)
13670 mips16_rewrite_pool_constant (info->pool, x);
13672 return GET_CODE (*x) == CONST ? -1 : 0;
13675 /* Return whether CFG is used in mips_reorg. */
13678 mips_cfg_in_reorg (void)
13680 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
13681 || TARGET_RELAX_PIC_CALLS);
13684 /* Build MIPS16 constant pools. */
13687 mips16_lay_out_constants (void)
13689 struct mips16_constant_pool pool;
13690 struct mips16_rewrite_pool_refs_info info;
13693 if (!TARGET_MIPS16_PCREL_LOADS)
13696 if (mips_cfg_in_reorg ())
13697 split_all_insns ();
13699 split_all_insns_noflow ();
13701 memset (&pool, 0, sizeof (pool));
13702 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13704 /* Rewrite constant pool references in INSN. */
13705 if (USEFUL_INSN_P (insn))
13709 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
13712 pool.insn_address += mips16_insn_length (insn);
13714 if (pool.first != NULL)
13716 /* If there are no natural barriers between the first user of
13717 the pool and the highest acceptable address, we'll need to
13718 create a new instruction to jump around the constant pool.
13719 In the worst case, this instruction will be 4 bytes long.
13721 If it's too late to do this transformation after INSN,
13722 do it immediately before INSN. */
13723 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
13727 label = gen_label_rtx ();
13729 jump = emit_jump_insn_before (gen_jump (label), insn);
13730 JUMP_LABEL (jump) = label;
13731 LABEL_NUSES (label) = 1;
13732 barrier = emit_barrier_after (jump);
13734 emit_label_after (label, barrier);
13735 pool.insn_address += 4;
13738 /* See whether the constant pool is now out of range of the first
13739 user. If so, output the constants after the previous barrier.
13740 Note that any instructions between BARRIER and INSN (inclusive)
13741 will use negative offsets to refer to the pool. */
13742 if (pool.insn_address > pool.highest_address)
13744 mips16_emit_constants (pool.first, barrier);
13748 else if (BARRIER_P (insn))
13752 mips16_emit_constants (pool.first, get_last_insn ());
13755 /* Return true if it is worth r10k_simplify_address's while replacing
13756 an address with X. We are looking for constants, and for addresses
13757 at a known offset from the incoming stack pointer. */
13760 r10k_simplified_address_p (rtx x)
13762 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
13764 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
13767 /* X is an expression that appears in INSN. Try to use the UD chains
13768 to simplify it, returning the simplified form on success and the
13769 original form otherwise. Replace the incoming value of $sp with
13770 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13773 r10k_simplify_address (rtx x, rtx insn)
13775 rtx newx, op0, op1, set, def_insn, note;
13777 struct df_link *defs;
13782 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13783 if (op0 != XEXP (x, 0))
13784 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
13785 op0, GET_MODE (XEXP (x, 0)));
13787 else if (BINARY_P (x))
13789 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13790 op1 = r10k_simplify_address (XEXP (x, 1), insn);
13791 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
13792 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
13794 else if (GET_CODE (x) == LO_SUM)
13796 /* LO_SUMs can be offset from HIGHs, if we know they won't
13797 overflow. See mips_classify_address for the rationale behind
13799 op0 = r10k_simplify_address (XEXP (x, 0), insn);
13800 if (GET_CODE (op0) == HIGH)
13801 newx = XEXP (x, 1);
13803 else if (REG_P (x))
13805 /* Uses are recorded by regno_reg_rtx, not X itself. */
13806 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
13808 defs = DF_REF_CHAIN (use);
13810 /* Require a single definition. */
13811 if (defs && defs->next == NULL)
13814 if (DF_REF_IS_ARTIFICIAL (def))
13816 /* Replace the incoming value of $sp with
13817 virtual_incoming_args_rtx. */
13818 if (x == stack_pointer_rtx
13819 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
13820 newx = virtual_incoming_args_rtx;
13822 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
13825 /* Make sure that DEF_INSN is a single set of REG. */
13826 def_insn = DF_REF_INSN (def);
13827 if (NONJUMP_INSN_P (def_insn))
13829 set = single_set (def_insn);
13830 if (set && rtx_equal_p (SET_DEST (set), x))
13832 /* Prefer to use notes, since the def-use chains
13833 are often shorter. */
13834 note = find_reg_equal_equiv_note (def_insn);
13836 newx = XEXP (note, 0);
13838 newx = SET_SRC (set);
13839 newx = r10k_simplify_address (newx, def_insn);
13845 if (newx && r10k_simplified_address_p (newx))
13850 /* Return true if ADDRESS is known to be an uncached address
13851 on R10K systems. */
13854 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
13856 unsigned HOST_WIDE_INT upper;
13858 /* Check for KSEG1. */
13859 if (address + 0x60000000 < 0x20000000)
13862 /* Check for uncached XKPHYS addresses. */
13863 if (Pmode == DImode)
13865 upper = (address >> 40) & 0xf9ffff;
13866 if (upper == 0x900000 || upper == 0xb80000)
13872 /* Return true if we can prove that an access to address X in instruction
13873 INSN would be safe from R10K speculation. This X is a general
13874 expression; it might not be a legitimate address. */
13877 r10k_safe_address_p (rtx x, rtx insn)
13880 HOST_WIDE_INT offset_val;
13882 x = r10k_simplify_address (x, insn);
13884 /* Check for references to the stack frame. It doesn't really matter
13885 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13886 allows us to assume that accesses to any part of the eventual frame
13887 is safe from speculation at any point in the function. */
13888 mips_split_plus (x, &base, &offset_val);
13889 if (base == virtual_incoming_args_rtx
13890 && offset_val >= -cfun->machine->frame.total_size
13891 && offset_val < cfun->machine->frame.args_size)
13894 /* Check for uncached addresses. */
13895 if (CONST_INT_P (x))
13896 return r10k_uncached_address_p (INTVAL (x));
13898 /* Check for accesses to a static object. */
13899 split_const (x, &base, &offset);
13900 return offset_within_block_p (base, INTVAL (offset));
13903 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13904 an in-range access to an automatic variable, or to an object with
13905 a link-time-constant address. */
13908 r10k_safe_mem_expr_p (tree expr, rtx offset)
13910 if (expr == NULL_TREE
13911 || offset == NULL_RTX
13912 || !CONST_INT_P (offset)
13913 || INTVAL (offset) < 0
13914 || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr)))
13917 while (TREE_CODE (expr) == COMPONENT_REF)
13919 expr = TREE_OPERAND (expr, 0);
13920 if (expr == NULL_TREE)
13924 return DECL_P (expr);
13927 /* A for_each_rtx callback for which DATA points to the instruction
13928 containing *X. Stop the search if we find a MEM that is not safe
13929 from R10K speculation. */
13932 r10k_needs_protection_p_1 (rtx *loc, void *data)
13940 if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
13943 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
13949 /* A note_stores callback for which DATA points to an instruction pointer.
13950 If *DATA is nonnull, make it null if it X contains a MEM that is not
13951 safe from R10K speculation. */
13954 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13959 insn_ptr = (rtx *) data;
13960 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
13961 *insn_ptr = NULL_RTX;
13964 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13965 Return nonzero if the call is not to a declared function. */
13968 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
13977 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
13983 /* Return true if instruction INSN needs to be protected by an R10K
13987 r10k_needs_protection_p (rtx insn)
13990 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
13992 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
13994 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
13995 return insn == NULL_RTX;
13998 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14001 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14002 edge is unconditional. */
14005 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14010 FOR_EACH_EDGE (e, ei, bb->preds)
14011 if (!single_succ_p (e->src)
14012 || !TEST_BIT (protected_bbs, e->src->index)
14013 || (e->flags & EDGE_COMPLEX) != 0)
14018 /* Implement -mr10k-cache-barrier= for the current function. */
14021 r10k_insert_cache_barriers (void)
14023 int *rev_post_order;
14026 sbitmap protected_bbs;
14027 rtx insn, end, unprotected_region;
14031 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14035 /* Calculate dominators. */
14036 calculate_dominance_info (CDI_DOMINATORS);
14038 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14039 X is protected by a cache barrier. */
14040 protected_bbs = sbitmap_alloc (last_basic_block);
14041 sbitmap_zero (protected_bbs);
14043 /* Iterate over the basic blocks in reverse post-order. */
14044 rev_post_order = XNEWVEC (int, last_basic_block);
14045 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14046 for (i = 0; i < n; i++)
14048 bb = BASIC_BLOCK (rev_post_order[i]);
14050 /* If this block is only reached by unconditional edges, and if the
14051 source of every edge is protected, the beginning of the block is
14053 if (r10k_protected_bb_p (bb, protected_bbs))
14054 unprotected_region = NULL_RTX;
14056 unprotected_region = pc_rtx;
14057 end = NEXT_INSN (BB_END (bb));
14059 /* UNPROTECTED_REGION is:
14061 - null if we are processing a protected region,
14062 - pc_rtx if we are processing an unprotected region but have
14063 not yet found the first instruction in it
14064 - the first instruction in an unprotected region otherwise. */
14065 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14067 if (unprotected_region && USEFUL_INSN_P (insn))
14069 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14070 /* This CACHE instruction protects the following code. */
14071 unprotected_region = NULL_RTX;
14074 /* See if INSN is the first instruction in this
14075 unprotected region. */
14076 if (unprotected_region == pc_rtx)
14077 unprotected_region = insn;
14079 /* See if INSN needs to be protected. If so,
14080 we must insert a cache barrier somewhere between
14081 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14082 clear which position is better performance-wise,
14083 but as a tie-breaker, we assume that it is better
14084 to allow delay slots to be back-filled where
14085 possible, and that it is better not to insert
14086 barriers in the middle of already-scheduled code.
14087 We therefore insert the barrier at the beginning
14089 if (r10k_needs_protection_p (insn))
14091 emit_insn_before (gen_r10k_cache_barrier (),
14092 unprotected_region);
14093 unprotected_region = NULL_RTX;
14099 /* The called function is not required to protect the exit path.
14100 The code that follows a call is therefore unprotected. */
14101 unprotected_region = pc_rtx;
14104 /* Record whether the end of this block is protected. */
14105 if (unprotected_region == NULL_RTX)
14106 SET_BIT (protected_bbs, bb->index);
14108 XDELETEVEC (rev_post_order);
14110 sbitmap_free (protected_bbs);
14112 free_dominance_info (CDI_DOMINATORS);
14115 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14116 otherwise. If INSN has two call rtx, then store the second one in
14120 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14125 if (!CALL_P (insn))
14128 x = PATTERN (insn);
14129 if (GET_CODE (x) == PARALLEL)
14131 /* Calls returning complex values have two CALL rtx. Look for the second
14132 one here, and return it via the SECOND_CALL arg. */
14133 x2 = XVECEXP (x, 0, 1);
14134 if (GET_CODE (x2) == SET)
14136 if (GET_CODE (x2) == CALL)
14139 x = XVECEXP (x, 0, 0);
14141 if (GET_CODE (x) == SET)
14143 gcc_assert (GET_CODE (x) == CALL);
14148 /* REG is set in DEF. See if the definition is one of the ways we load a
14149 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14150 it is return the symbol reference of the function, otherwise return
14154 mips_pic_call_symbol_from_set (df_ref def, rtx reg)
14158 if (DF_REF_IS_ARTIFICIAL (def))
14161 def_insn = DF_REF_INSN (def);
14162 set = single_set (def_insn);
14163 if (set && rtx_equal_p (SET_DEST (set), reg))
14165 rtx note, src, symbol;
14167 /* First, look at REG_EQUAL/EQUIV notes. */
14168 note = find_reg_equal_equiv_note (def_insn);
14169 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14170 return XEXP (note, 0);
14172 /* For %call16 references we don't have REG_EQUAL. */
14173 src = SET_SRC (set);
14174 symbol = mips_strip_unspec_call (src);
14177 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14181 /* Follow simple register copies. */
14183 return mips_find_pic_call_symbol (def_insn, src);
14189 /* Find the definition of the use of REG in INSN. See if the definition is
14190 one of the ways we load a register with a symbol address for a
14191 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14192 the function, otherwise return NULL_RTX. */
14195 mips_find_pic_call_symbol (rtx insn, rtx reg)
14198 struct df_link *defs;
14201 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14204 defs = DF_REF_CHAIN (use);
14207 symbol = mips_pic_call_symbol_from_set (defs->ref, reg);
14211 /* If we have more than one definition, they need to be identical. */
14212 for (defs = defs->next; defs; defs = defs->next)
14216 other = mips_pic_call_symbol_from_set (defs->ref, reg);
14217 if (!rtx_equal_p (symbol, other))
14224 /* Replace the args_size operand of the call expression CALL with the
14225 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14228 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14232 args_size = XEXP (call, 1);
14233 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14234 gen_rtvec (2, args_size, symbol),
14238 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14239 if instead of the arg_size argument it contains the call attributes. If
14240 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14241 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14245 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14247 rtx args_size, symbol;
14249 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14252 args_size = operands[args_size_opno];
14253 if (GET_CODE (args_size) != UNSPEC)
14255 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14257 symbol = XVECEXP (args_size, 0, 1);
14258 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14260 operands[args_size_opno] = symbol;
14264 /* Use DF to annotate PIC indirect calls with the function symbol they
14268 mips_annotate_pic_calls (void)
14274 FOR_BB_INSNS (bb, insn)
14276 rtx call, reg, symbol, second_call;
14279 call = mips_call_expr_from_insn (insn, &second_call);
14282 gcc_assert (MEM_P (XEXP (call, 0)));
14283 reg = XEXP (XEXP (call, 0), 0);
14287 symbol = mips_find_pic_call_symbol (insn, reg);
14290 mips_annotate_pic_call_expr (call, symbol);
14292 mips_annotate_pic_call_expr (second_call, symbol);
14297 /* A temporary variable used by for_each_rtx callbacks, etc. */
14298 static rtx mips_sim_insn;
14300 /* A structure representing the state of the processor pipeline.
14301 Used by the mips_sim_* family of functions. */
14303 /* The maximum number of instructions that can be issued in a cycle.
14304 (Caches mips_issue_rate.) */
14305 unsigned int issue_rate;
14307 /* The current simulation time. */
14310 /* How many more instructions can be issued in the current cycle. */
14311 unsigned int insns_left;
14313 /* LAST_SET[X].INSN is the last instruction to set register X.
14314 LAST_SET[X].TIME is the time at which that instruction was issued.
14315 INSN is null if no instruction has yet set register X. */
14319 } last_set[FIRST_PSEUDO_REGISTER];
14321 /* The pipeline's current DFA state. */
14325 /* Reset STATE to the initial simulation state. */
14328 mips_sim_reset (struct mips_sim *state)
14331 state->insns_left = state->issue_rate;
14332 memset (&state->last_set, 0, sizeof (state->last_set));
14333 state_reset (state->dfa_state);
14336 /* Initialize STATE before its first use. DFA_STATE points to an
14337 allocated but uninitialized DFA state. */
14340 mips_sim_init (struct mips_sim *state, state_t dfa_state)
14342 state->issue_rate = mips_issue_rate ();
14343 state->dfa_state = dfa_state;
14344 mips_sim_reset (state);
14347 /* Advance STATE by one clock cycle. */
14350 mips_sim_next_cycle (struct mips_sim *state)
14353 state->insns_left = state->issue_rate;
14354 state_transition (state->dfa_state, 0);
14357 /* Advance simulation state STATE until instruction INSN can read
14361 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
14363 unsigned int regno, end_regno;
14365 end_regno = END_REGNO (reg);
14366 for (regno = REGNO (reg); regno < end_regno; regno++)
14367 if (state->last_set[regno].insn != 0)
14371 t = (state->last_set[regno].time
14372 + insn_latency (state->last_set[regno].insn, insn));
14373 while (state->time < t)
14374 mips_sim_next_cycle (state);
14378 /* A for_each_rtx callback. If *X is a register, advance simulation state
14379 DATA until mips_sim_insn can read the register's value. */
14382 mips_sim_wait_regs_2 (rtx *x, void *data)
14385 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
14389 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14392 mips_sim_wait_regs_1 (rtx *x, void *data)
14394 for_each_rtx (x, mips_sim_wait_regs_2, data);
14397 /* Advance simulation state STATE until all of INSN's register
14398 dependencies are satisfied. */
14401 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
14403 mips_sim_insn = insn;
14404 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
14407 /* Advance simulation state STATE until the units required by
14408 instruction INSN are available. */
14411 mips_sim_wait_units (struct mips_sim *state, rtx insn)
14415 tmp_state = alloca (state_size ());
14416 while (state->insns_left == 0
14417 || (memcpy (tmp_state, state->dfa_state, state_size ()),
14418 state_transition (tmp_state, insn) >= 0))
14419 mips_sim_next_cycle (state);
14422 /* Advance simulation state STATE until INSN is ready to issue. */
14425 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
14427 mips_sim_wait_regs (state, insn);
14428 mips_sim_wait_units (state, insn);
14431 /* mips_sim_insn has just set X. Update the LAST_SET array
14432 in simulation state DATA. */
14435 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
14437 struct mips_sim *state;
14439 state = (struct mips_sim *) data;
14442 unsigned int regno, end_regno;
14444 end_regno = END_REGNO (x);
14445 for (regno = REGNO (x); regno < end_regno; regno++)
14447 state->last_set[regno].insn = mips_sim_insn;
14448 state->last_set[regno].time = state->time;
14453 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14454 can issue immediately (i.e., that mips_sim_wait_insn has already
14458 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
14460 state_transition (state->dfa_state, insn);
14461 state->insns_left--;
14463 mips_sim_insn = insn;
14464 note_stores (PATTERN (insn), mips_sim_record_set, state);
14467 /* Simulate issuing a NOP in state STATE. */
14470 mips_sim_issue_nop (struct mips_sim *state)
14472 if (state->insns_left == 0)
14473 mips_sim_next_cycle (state);
14474 state->insns_left--;
14477 /* Update simulation state STATE so that it's ready to accept the instruction
14478 after INSN. INSN should be part of the main rtl chain, not a member of a
14482 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
14484 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14486 mips_sim_issue_nop (state);
14488 switch (GET_CODE (SEQ_BEGIN (insn)))
14492 /* We can't predict the processor state after a call or label. */
14493 mips_sim_reset (state);
14497 /* The delay slots of branch likely instructions are only executed
14498 when the branch is taken. Therefore, if the caller has simulated
14499 the delay slot instruction, STATE does not really reflect the state
14500 of the pipeline for the instruction after the delay slot. Also,
14501 branch likely instructions tend to incur a penalty when not taken,
14502 so there will probably be an extra delay between the branch and
14503 the instruction after the delay slot. */
14504 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
14505 mips_sim_reset (state);
14513 /* The VR4130 pipeline issues aligned pairs of instructions together,
14514 but it stalls the second instruction if it depends on the first.
14515 In order to cut down the amount of logic required, this dependence
14516 check is not based on a full instruction decode. Instead, any non-SPECIAL
14517 instruction is assumed to modify the register specified by bits 20-16
14518 (which is usually the "rt" field).
14520 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14521 input, so we can end up with a false dependence between the branch
14522 and its delay slot. If this situation occurs in instruction INSN,
14523 try to avoid it by swapping rs and rt. */
14526 vr4130_avoid_branch_rt_conflict (rtx insn)
14530 first = SEQ_BEGIN (insn);
14531 second = SEQ_END (insn);
14533 && NONJUMP_INSN_P (second)
14534 && GET_CODE (PATTERN (first)) == SET
14535 && GET_CODE (SET_DEST (PATTERN (first))) == PC
14536 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
14538 /* Check for the right kind of condition. */
14539 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
14540 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
14541 && REG_P (XEXP (cond, 0))
14542 && REG_P (XEXP (cond, 1))
14543 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
14544 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
14546 /* SECOND mentions the rt register but not the rs register. */
14547 rtx tmp = XEXP (cond, 0);
14548 XEXP (cond, 0) = XEXP (cond, 1);
14549 XEXP (cond, 1) = tmp;
14554 /* Implement -mvr4130-align. Go through each basic block and simulate the
14555 processor pipeline. If we find that a pair of instructions could execute
14556 in parallel, and the first of those instructions is not 8-byte aligned,
14557 insert a nop to make it aligned. */
14560 vr4130_align_insns (void)
14562 struct mips_sim state;
14563 rtx insn, subinsn, last, last2, next;
14568 /* LAST is the last instruction before INSN to have a nonzero length.
14569 LAST2 is the last such instruction before LAST. */
14573 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14576 mips_sim_init (&state, alloca (state_size ()));
14577 for (insn = get_insns (); insn != 0; insn = next)
14579 unsigned int length;
14581 next = NEXT_INSN (insn);
14583 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14584 This isn't really related to the alignment pass, but we do it on
14585 the fly to avoid a separate instruction walk. */
14586 vr4130_avoid_branch_rt_conflict (insn);
14588 if (USEFUL_INSN_P (insn))
14589 FOR_EACH_SUBINSN (subinsn, insn)
14591 mips_sim_wait_insn (&state, subinsn);
14593 /* If we want this instruction to issue in parallel with the
14594 previous one, make sure that the previous instruction is
14595 aligned. There are several reasons why this isn't worthwhile
14596 when the second instruction is a call:
14598 - Calls are less likely to be performance critical,
14599 - There's a good chance that the delay slot can execute
14600 in parallel with the call.
14601 - The return address would then be unaligned.
14603 In general, if we're going to insert a nop between instructions
14604 X and Y, it's better to insert it immediately after X. That
14605 way, if the nop makes Y aligned, it will also align any labels
14606 between X and Y. */
14607 if (state.insns_left != state.issue_rate
14608 && !CALL_P (subinsn))
14610 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
14612 /* SUBINSN is the first instruction in INSN and INSN is
14613 aligned. We want to align the previous instruction
14614 instead, so insert a nop between LAST2 and LAST.
14616 Note that LAST could be either a single instruction
14617 or a branch with a delay slot. In the latter case,
14618 LAST, like INSN, is already aligned, but the delay
14619 slot must have some extra delay that stops it from
14620 issuing at the same time as the branch. We therefore
14621 insert a nop before the branch in order to align its
14623 emit_insn_after (gen_nop (), last2);
14626 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
14628 /* SUBINSN is the delay slot of INSN, but INSN is
14629 currently unaligned. Insert a nop between
14630 LAST and INSN to align it. */
14631 emit_insn_after (gen_nop (), last);
14635 mips_sim_issue_insn (&state, subinsn);
14637 mips_sim_finish_insn (&state, insn);
14639 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14640 length = get_attr_length (insn);
14643 /* If the instruction is an asm statement or multi-instruction
14644 mips.md patern, the length is only an estimate. Insert an
14645 8 byte alignment after it so that the following instructions
14646 can be handled correctly. */
14647 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
14648 && (recog_memoized (insn) < 0 || length >= 8))
14650 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
14651 next = NEXT_INSN (next);
14652 mips_sim_next_cycle (&state);
14655 else if (length & 4)
14656 aligned_p = !aligned_p;
14661 /* See whether INSN is an aligned label. */
14662 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
14668 /* This structure records that the current function has a LO_SUM
14669 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14670 the largest offset applied to BASE by all such LO_SUMs. */
14671 struct mips_lo_sum_offset {
14673 HOST_WIDE_INT offset;
14676 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14679 mips_hash_base (rtx base)
14681 int do_not_record_p;
14683 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
14686 /* Hash-table callbacks for mips_lo_sum_offsets. */
14689 mips_lo_sum_offset_hash (const void *entry)
14691 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
14695 mips_lo_sum_offset_eq (const void *entry, const void *value)
14697 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
14698 (const_rtx) value);
14701 /* Look up symbolic constant X in HTAB, which is a hash table of
14702 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14703 paired with a recorded LO_SUM, otherwise record X in the table. */
14706 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
14710 struct mips_lo_sum_offset *entry;
14712 /* Split X into a base and offset. */
14713 split_const (x, &base, &offset);
14714 if (UNSPEC_ADDRESS_P (base))
14715 base = UNSPEC_ADDRESS (base);
14717 /* Look up the base in the hash table. */
14718 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
14722 entry = (struct mips_lo_sum_offset *) *slot;
14723 if (option == INSERT)
14727 entry = XNEW (struct mips_lo_sum_offset);
14728 entry->base = base;
14729 entry->offset = INTVAL (offset);
14734 if (INTVAL (offset) > entry->offset)
14735 entry->offset = INTVAL (offset);
14738 return INTVAL (offset) <= entry->offset;
14741 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14742 Record every LO_SUM in *LOC. */
14745 mips_record_lo_sum (rtx *loc, void *data)
14747 if (GET_CODE (*loc) == LO_SUM)
14748 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
14752 /* Return true if INSN is a SET of an orphaned high-part relocation.
14753 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14754 LO_SUMs in the current function. */
14757 mips_orphaned_high_part_p (htab_t htab, rtx insn)
14759 enum mips_symbol_type type;
14762 set = single_set (insn);
14765 /* Check for %his. */
14767 if (GET_CODE (x) == HIGH
14768 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
14769 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
14771 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14772 if (GET_CODE (x) == UNSPEC
14773 && XINT (x, 1) == UNSPEC_LOAD_GOT
14774 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
14775 SYMBOL_CONTEXT_LEA, &type)
14776 && type == SYMBOL_GOTOFF_PAGE)
14777 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
14782 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14783 INSN and a previous instruction, avoid it by inserting nops after
14786 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14787 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14788 before using the value of that register. *HILO_DELAY counts the
14789 number of instructions since the last hilo hazard (that is,
14790 the number of instructions since the last MFLO or MFHI).
14792 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14793 for the next instruction.
14795 LO_REG is an rtx for the LO register, used in dependence checking. */
14798 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
14799 rtx *delayed_reg, rtx lo_reg)
14804 pattern = PATTERN (insn);
14806 /* Do not put the whole function in .set noreorder if it contains
14807 an asm statement. We don't know whether there will be hazards
14808 between the asm statement and the gcc-generated code. */
14809 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
14810 cfun->machine->all_noreorder_p = false;
14812 /* Ignore zero-length instructions (barriers and the like). */
14813 ninsns = get_attr_length (insn) / 4;
14817 /* Work out how many nops are needed. Note that we only care about
14818 registers that are explicitly mentioned in the instruction's pattern.
14819 It doesn't matter that calls use the argument registers or that they
14820 clobber hi and lo. */
14821 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
14822 nops = 2 - *hilo_delay;
14823 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
14828 /* Insert the nops between this instruction and the previous one.
14829 Each new nop takes us further from the last hilo hazard. */
14830 *hilo_delay += nops;
14832 emit_insn_after (gen_hazard_nop (), after);
14834 /* Set up the state for the next instruction. */
14835 *hilo_delay += ninsns;
14837 if (INSN_CODE (insn) >= 0)
14838 switch (get_attr_hazard (insn))
14848 set = single_set (insn);
14850 *delayed_reg = SET_DEST (set);
14855 /* Go through the instruction stream and insert nops where necessary.
14856 Also delete any high-part relocations whose partnering low parts
14857 are now all dead. See if the whole function can then be put into
14858 .set noreorder and .set nomacro. */
14861 mips_reorg_process_insns (void)
14863 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
14867 /* Force all instructions to be split into their final form. */
14868 split_all_insns_noflow ();
14870 /* Recalculate instruction lengths without taking nops into account. */
14871 cfun->machine->ignore_hazard_length_p = true;
14872 shorten_branches (get_insns ());
14874 cfun->machine->all_noreorder_p = true;
14876 /* We don't track MIPS16 PC-relative offsets closely enough to make
14877 a good job of "set .noreorder" code in MIPS16 mode. */
14879 cfun->machine->all_noreorder_p = false;
14881 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14882 if (!TARGET_EXPLICIT_RELOCS)
14883 cfun->machine->all_noreorder_p = false;
14885 /* Profiled functions can't be all noreorder because the profiler
14886 support uses assembler macros. */
14888 cfun->machine->all_noreorder_p = false;
14890 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
14891 because we rely on the assembler to work around some errata. */
14892 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
14893 cfun->machine->all_noreorder_p = false;
14895 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14896 MFHI instructions. Note that we avoid using MFLO and MFHI if
14897 the VR4130 MACC and DMACC instructions are available instead;
14898 see the *mfhilo_{si,di}_macc patterns. */
14899 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
14900 cfun->machine->all_noreorder_p = false;
14902 htab = htab_create (37, mips_lo_sum_offset_hash,
14903 mips_lo_sum_offset_eq, free);
14905 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14906 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14907 FOR_EACH_SUBINSN (subinsn, insn)
14908 if (USEFUL_INSN_P (subinsn))
14909 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
14914 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
14916 /* Make a second pass over the instructions. Delete orphaned
14917 high-part relocations or turn them into NOPs. Avoid hazards
14918 by inserting NOPs. */
14919 for (insn = get_insns (); insn != 0; insn = next_insn)
14921 next_insn = NEXT_INSN (insn);
14922 if (USEFUL_INSN_P (insn))
14924 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
14926 /* If we find an orphaned high-part relocation in a delay
14927 slot, it's easier to turn that instruction into a NOP than
14928 to delete it. The delay slot will be a NOP either way. */
14929 FOR_EACH_SUBINSN (subinsn, insn)
14930 if (INSN_P (subinsn))
14932 if (mips_orphaned_high_part_p (htab, subinsn))
14934 PATTERN (subinsn) = gen_nop ();
14935 INSN_CODE (subinsn) = CODE_FOR_nop;
14937 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
14938 &delayed_reg, lo_reg);
14944 /* INSN is a single instruction. Delete it if it's an
14945 orphaned high-part relocation. */
14946 if (mips_orphaned_high_part_p (htab, insn))
14947 delete_insn (insn);
14948 /* Also delete cache barriers if the last instruction
14949 was an annulled branch. INSN will not be speculatively
14951 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
14953 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
14954 delete_insn (insn);
14957 mips_avoid_hazard (last_insn, insn, &hilo_delay,
14958 &delayed_reg, lo_reg);
14965 htab_delete (htab);
14968 /* If we are using a GOT, but have not decided to use a global pointer yet,
14969 see whether we need one to implement long branches. Convert the ghost
14970 global-pointer instructions into real ones if so. */
14973 mips_expand_ghost_gp_insns (void)
14978 /* Quick exit if we already know that we will or won't need a
14980 if (!TARGET_USE_GOT
14981 || cfun->machine->global_pointer == INVALID_REGNUM
14982 || mips_must_initialize_gp_p ())
14985 shorten_branches (get_insns ());
14987 /* Look for a branch that is longer than normal. The normal length for
14988 non-MIPS16 branches is 8, because the length includes the delay slot.
14989 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
14990 but they have no delay slot. */
14991 normal_length = (TARGET_MIPS16 ? 4 : 8);
14992 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14994 && USEFUL_INSN_P (insn)
14995 && get_attr_length (insn) > normal_length)
14998 if (insn == NULL_RTX)
15001 /* We've now established that we need $gp. */
15002 cfun->machine->must_initialize_gp_p = true;
15003 split_all_insns_noflow ();
15008 /* Subroutine of mips_reorg to manage passes that require DF. */
15011 mips_df_reorg (void)
15013 /* Create def-use chains. */
15014 df_set_flags (DF_EQ_NOTES);
15015 df_chain_add_problem (DF_UD_CHAIN);
15018 if (TARGET_RELAX_PIC_CALLS)
15019 mips_annotate_pic_calls ();
15021 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15022 r10k_insert_cache_barriers ();
15024 df_finish_pass (false);
15027 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15032 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15033 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15034 to date if the CFG is available. */
15035 if (mips_cfg_in_reorg ())
15036 compute_bb_for_insn ();
15037 mips16_lay_out_constants ();
15038 if (mips_cfg_in_reorg ())
15041 free_bb_for_insn ();
15044 if (optimize > 0 && flag_delayed_branch)
15045 dbr_schedule (get_insns ());
15046 mips_reorg_process_insns ();
15048 && TARGET_EXPLICIT_RELOCS
15050 && TARGET_VR4130_ALIGN)
15051 vr4130_align_insns ();
15052 if (mips_expand_ghost_gp_insns ())
15053 /* The expansion could invalidate some of the VR4130 alignment
15054 optimizations, but this should be an extremely rare case anyhow. */
15055 mips_reorg_process_insns ();
15058 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15059 in order to avoid duplicating too much logic from elsewhere. */
15062 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15063 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15066 rtx this_rtx, temp1, temp2, insn, fnaddr;
15067 bool use_sibcall_p;
15069 /* Pretend to be a post-reload pass while generating rtl. */
15070 reload_completed = 1;
15072 /* Mark the end of the (empty) prologue. */
15073 emit_note (NOTE_INSN_PROLOGUE_END);
15075 /* Determine if we can use a sibcall to call FUNCTION directly. */
15076 fnaddr = XEXP (DECL_RTL (function), 0);
15077 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15078 && const_call_insn_operand (fnaddr, Pmode));
15080 /* Determine if we need to load FNADDR from the GOT. */
15082 && (mips_got_symbol_type_p
15083 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
15085 /* Pick a global pointer. Use a call-clobbered register if
15086 TARGET_CALL_SAVED_GP. */
15087 cfun->machine->global_pointer
15088 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
15089 cfun->machine->must_initialize_gp_p = true;
15090 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
15092 /* Set up the global pointer for n32 or n64 abicalls. */
15093 mips_emit_loadgp ();
15096 /* We need two temporary registers in some cases. */
15097 temp1 = gen_rtx_REG (Pmode, 2);
15098 temp2 = gen_rtx_REG (Pmode, 3);
15100 /* Find out which register contains the "this" pointer. */
15101 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15102 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
15104 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
15106 /* Add DELTA to THIS_RTX. */
15109 rtx offset = GEN_INT (delta);
15110 if (!SMALL_OPERAND (delta))
15112 mips_emit_move (temp1, offset);
15115 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
15118 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15119 if (vcall_offset != 0)
15123 /* Set TEMP1 to *THIS_RTX. */
15124 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
15126 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15127 addr = mips_add_offset (temp2, temp1, vcall_offset);
15129 /* Load the offset and add it to THIS_RTX. */
15130 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
15131 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
15134 /* Jump to the target function. Use a sibcall if direct jumps are
15135 allowed, otherwise load the address into a register first. */
15138 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
15139 SIBLING_CALL_P (insn) = 1;
15143 /* This is messy. GAS treats "la $25,foo" as part of a call
15144 sequence and may allow a global "foo" to be lazily bound.
15145 The general move patterns therefore reject this combination.
15147 In this context, lazy binding would actually be OK
15148 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15149 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15150 We must therefore load the address via a temporary
15151 register if mips_dangerous_for_la25_p.
15153 If we jump to the temporary register rather than $25,
15154 the assembler can use the move insn to fill the jump's
15157 We can use the same technique for MIPS16 code, where $25
15158 is not a valid JR register. */
15159 if (TARGET_USE_PIC_FN_ADDR_REG
15161 && !mips_dangerous_for_la25_p (fnaddr))
15162 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
15163 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
15165 if (TARGET_USE_PIC_FN_ADDR_REG
15166 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
15167 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
15168 emit_jump_insn (gen_indirect_jump (temp1));
15171 /* Run just enough of rest_of_compilation. This sequence was
15172 "borrowed" from alpha.c. */
15173 insn = get_insns ();
15174 insn_locators_alloc ();
15175 split_all_insns_noflow ();
15176 mips16_lay_out_constants ();
15177 shorten_branches (insn);
15178 final_start_function (insn, file, 1);
15179 final (insn, file, 1);
15180 final_end_function ();
15182 /* Clean up the vars set above. Note that final_end_function resets
15183 the global pointer for us. */
15184 reload_completed = 0;
15187 /* The last argument passed to mips_set_mips16_mode, or negative if the
15188 function hasn't been called yet.
15190 There are two copies of this information. One is saved and restored
15191 by the PCH process while the other is specific to this compiler
15192 invocation. The information calculated by mips_set_mips16_mode
15193 is invalid unless the two variables are the same. */
15194 static int was_mips16_p = -1;
15195 static GTY(()) int was_mips16_pch_p = -1;
15197 /* Set up the target-dependent global state so that it matches the
15198 current function's ISA mode. */
15201 mips_set_mips16_mode (int mips16_p)
15203 if (mips16_p == was_mips16_p
15204 && mips16_p == was_mips16_pch_p)
15207 /* Restore base settings of various flags. */
15208 target_flags = mips_base_target_flags;
15209 flag_schedule_insns = mips_base_schedule_insns;
15210 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
15211 flag_move_loop_invariants = mips_base_move_loop_invariants;
15212 align_loops = mips_base_align_loops;
15213 align_jumps = mips_base_align_jumps;
15214 align_functions = mips_base_align_functions;
15218 /* Switch to MIPS16 mode. */
15219 target_flags |= MASK_MIPS16;
15221 /* Don't run the scheduler before reload, since it tends to
15222 increase register pressure. */
15223 flag_schedule_insns = 0;
15225 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15226 the whole function to be in a single section. */
15227 flag_reorder_blocks_and_partition = 0;
15229 /* Don't move loop invariants, because it tends to increase
15230 register pressure. It also introduces an extra move in cases
15231 where the constant is the first operand in a two-operand binary
15232 instruction, or when it forms a register argument to a functon
15234 flag_move_loop_invariants = 0;
15236 target_flags |= MASK_EXPLICIT_RELOCS;
15238 /* Experiments suggest we get the best overall section-anchor
15239 results from using the range of an unextended LW or SW. Code
15240 that makes heavy use of byte or short accesses can do better
15241 with ranges of 0...31 and 0...63 respectively, but most code is
15242 sensitive to the range of LW and SW instead. */
15243 targetm.min_anchor_offset = 0;
15244 targetm.max_anchor_offset = 127;
15246 targetm.const_anchor = 0;
15248 /* MIPS16 has no BAL instruction. */
15249 target_flags &= ~MASK_RELAX_PIC_CALLS;
15251 if (flag_pic && !TARGET_OLDABI)
15252 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15255 sorry ("MIPS16 -mxgot code");
15257 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
15258 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15262 /* Switch to normal (non-MIPS16) mode. */
15263 target_flags &= ~MASK_MIPS16;
15265 /* Provide default values for align_* for 64-bit targets. */
15268 if (align_loops == 0)
15270 if (align_jumps == 0)
15272 if (align_functions == 0)
15273 align_functions = 8;
15276 targetm.min_anchor_offset = -32768;
15277 targetm.max_anchor_offset = 32767;
15279 targetm.const_anchor = 0x8000;
15282 /* (Re)initialize MIPS target internals for new ISA. */
15283 mips_init_relocs ();
15287 if (!mips16_globals)
15288 mips16_globals = save_target_globals ();
15290 restore_target_globals (mips16_globals);
15293 restore_target_globals (&default_target_globals);
15295 was_mips16_p = mips16_p;
15296 was_mips16_pch_p = mips16_p;
15299 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15300 function should use the MIPS16 ISA and switch modes accordingly. */
15303 mips_set_current_function (tree fndecl)
15305 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
15308 /* Allocate a chunk of memory for per-function machine-dependent data. */
15310 static struct machine_function *
15311 mips_init_machine_status (void)
15313 return ggc_alloc_cleared_machine_function ();
15316 /* Return the processor associated with the given ISA level, or null
15317 if the ISA isn't valid. */
15319 static const struct mips_cpu_info *
15320 mips_cpu_info_from_isa (int isa)
15324 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15325 if (mips_cpu_info_table[i].isa == isa)
15326 return mips_cpu_info_table + i;
15331 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15332 with a final "000" replaced by "k". Ignore case.
15334 Note: this function is shared between GCC and GAS. */
15337 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
15339 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
15340 given++, canonical++;
15342 return ((*given == 0 && *canonical == 0)
15343 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
15346 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15347 CPU name. We've traditionally allowed a lot of variation here.
15349 Note: this function is shared between GCC and GAS. */
15352 mips_matching_cpu_name_p (const char *canonical, const char *given)
15354 /* First see if the name matches exactly, or with a final "000"
15355 turned into "k". */
15356 if (mips_strict_matching_cpu_name_p (canonical, given))
15359 /* If not, try comparing based on numerical designation alone.
15360 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15361 if (TOLOWER (*given) == 'r')
15363 if (!ISDIGIT (*given))
15366 /* Skip over some well-known prefixes in the canonical name,
15367 hoping to find a number there too. */
15368 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
15370 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
15372 else if (TOLOWER (canonical[0]) == 'r')
15375 return mips_strict_matching_cpu_name_p (canonical, given);
15378 /* Return the mips_cpu_info entry for the processor or ISA given
15379 by CPU_STRING. Return null if the string isn't recognized.
15381 A similar function exists in GAS. */
15383 static const struct mips_cpu_info *
15384 mips_parse_cpu (const char *cpu_string)
15389 /* In the past, we allowed upper-case CPU names, but it doesn't
15390 work well with the multilib machinery. */
15391 for (s = cpu_string; *s != 0; s++)
15394 warning (0, "CPU names must be lower case");
15398 /* 'from-abi' selects the most compatible architecture for the given
15399 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15400 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15402 if (strcasecmp (cpu_string, "from-abi") == 0)
15403 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
15404 : ABI_NEEDS_64BIT_REGS ? 3
15405 : (TARGET_64BIT ? 3 : 1));
15407 /* 'default' has traditionally been a no-op. Probably not very useful. */
15408 if (strcasecmp (cpu_string, "default") == 0)
15411 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
15412 if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
15413 return mips_cpu_info_table + i;
15418 /* Set up globals to generate code for the ISA or processor
15419 described by INFO. */
15422 mips_set_architecture (const struct mips_cpu_info *info)
15426 mips_arch_info = info;
15427 mips_arch = info->cpu;
15428 mips_isa = info->isa;
15432 /* Likewise for tuning. */
15435 mips_set_tune (const struct mips_cpu_info *info)
15439 mips_tune_info = info;
15440 mips_tune = info->cpu;
15444 /* Implement TARGET_HANDLE_OPTION. */
15447 mips_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
15448 const struct cl_decoded_option *decoded,
15449 location_t loc ATTRIBUTE_UNUSED)
15451 size_t code = decoded->opt_index;
15452 const char *arg = decoded->arg;
15454 gcc_assert (opts == &global_options);
15455 gcc_assert (opts_set == &global_options_set);
15460 if (strcmp (arg, "32") == 0)
15462 else if (strcmp (arg, "o64") == 0)
15463 mips_abi = ABI_O64;
15464 else if (strcmp (arg, "n32") == 0)
15465 mips_abi = ABI_N32;
15466 else if (strcmp (arg, "64") == 0)
15468 else if (strcmp (arg, "eabi") == 0)
15469 mips_abi = ABI_EABI;
15476 return mips_parse_cpu (arg) != 0;
15479 mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
15480 return mips_isa_option_info != 0;
15482 case OPT_mno_flush_func:
15483 mips_cache_flush_func = NULL;
15486 case OPT_mcode_readable_:
15487 if (strcmp (arg, "yes") == 0)
15488 mips_code_readable = CODE_READABLE_YES;
15489 else if (strcmp (arg, "pcrel") == 0)
15490 mips_code_readable = CODE_READABLE_PCREL;
15491 else if (strcmp (arg, "no") == 0)
15492 mips_code_readable = CODE_READABLE_NO;
15497 case OPT_mr10k_cache_barrier_:
15498 if (strcmp (arg, "load-store") == 0)
15499 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE;
15500 else if (strcmp (arg, "store") == 0)
15501 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE;
15502 else if (strcmp (arg, "none") == 0)
15503 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15513 /* Implement TARGET_OPTION_OVERRIDE. */
15516 mips_option_override (void)
15518 int i, start, regno, mode;
15520 /* Process flags as though we were generating non-MIPS16 code. */
15521 mips_base_mips16 = TARGET_MIPS16;
15522 target_flags &= ~MASK_MIPS16;
15524 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15525 SUBTARGET_OVERRIDE_OPTIONS;
15528 /* -mno-float overrides -mhard-float and -msoft-float. */
15529 if (TARGET_NO_FLOAT)
15531 target_flags |= MASK_SOFT_FLOAT_ABI;
15532 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
15535 if (TARGET_FLIP_MIPS16)
15536 TARGET_INTERLINK_MIPS16 = 1;
15538 /* Set the small data limit. */
15539 mips_small_data_threshold = (global_options_set.x_g_switch_value
15541 : MIPS_DEFAULT_GVALUE);
15543 /* The following code determines the architecture and register size.
15544 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15545 The GAS and GCC code should be kept in sync as much as possible. */
15547 if (mips_arch_string != 0)
15548 mips_set_architecture (mips_parse_cpu (mips_arch_string));
15550 if (mips_isa_option_info != 0)
15552 if (mips_arch_info == 0)
15553 mips_set_architecture (mips_isa_option_info);
15554 else if (mips_arch_info->isa != mips_isa_option_info->isa)
15555 error ("%<-%s%> conflicts with the other architecture options, "
15556 "which specify a %s processor",
15557 mips_isa_option_info->name,
15558 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
15561 if (mips_arch_info == 0)
15563 #ifdef MIPS_CPU_STRING_DEFAULT
15564 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
15566 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
15570 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
15571 error ("%<-march=%s%> is not compatible with the selected ABI",
15572 mips_arch_info->name);
15574 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15575 if (mips_tune_string != 0)
15576 mips_set_tune (mips_parse_cpu (mips_tune_string));
15578 if (mips_tune_info == 0)
15579 mips_set_tune (mips_arch_info);
15581 if ((target_flags_explicit & MASK_64BIT) != 0)
15583 /* The user specified the size of the integer registers. Make sure
15584 it agrees with the ABI and ISA. */
15585 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
15586 error ("%<-mgp64%> used with a 32-bit processor");
15587 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
15588 error ("%<-mgp32%> used with a 64-bit ABI");
15589 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
15590 error ("%<-mgp64%> used with a 32-bit ABI");
15594 /* Infer the integer register size from the ABI and processor.
15595 Restrict ourselves to 32-bit registers if that's all the
15596 processor has, or if the ABI cannot handle 64-bit registers. */
15597 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
15598 target_flags &= ~MASK_64BIT;
15600 target_flags |= MASK_64BIT;
15603 if ((target_flags_explicit & MASK_FLOAT64) != 0)
15605 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
15606 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15607 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
15608 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15609 else if (!TARGET_64BIT && TARGET_FLOAT64)
15611 if (!ISA_HAS_MXHC1)
15612 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15613 " the target supports the mfhc1 and mthc1 instructions");
15614 else if (mips_abi != ABI_32)
15615 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15621 /* -msingle-float selects 32-bit float registers. Otherwise the
15622 float registers should be the same size as the integer ones. */
15623 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
15624 target_flags |= MASK_FLOAT64;
15626 target_flags &= ~MASK_FLOAT64;
15629 /* End of code shared with GAS. */
15631 /* If no -mlong* option was given, infer it from the other options. */
15632 if ((target_flags_explicit & MASK_LONG64) == 0)
15634 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
15635 target_flags |= MASK_LONG64;
15637 target_flags &= ~MASK_LONG64;
15640 if (!TARGET_OLDABI)
15641 flag_pcc_struct_return = 0;
15643 /* Decide which rtx_costs structure to use. */
15645 mips_cost = &mips_rtx_cost_optimize_size;
15647 mips_cost = &mips_rtx_cost_data[mips_tune];
15649 /* If the user hasn't specified a branch cost, use the processor's
15651 if (mips_branch_cost == 0)
15652 mips_branch_cost = mips_cost->branch_cost;
15654 /* If neither -mbranch-likely nor -mno-branch-likely was given
15655 on the command line, set MASK_BRANCHLIKELY based on the target
15656 architecture and tuning flags. Annulled delay slots are a
15657 size win, so we only consider the processor-specific tuning
15658 for !optimize_size. */
15659 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
15661 if (ISA_HAS_BRANCHLIKELY
15663 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
15664 target_flags |= MASK_BRANCHLIKELY;
15666 target_flags &= ~MASK_BRANCHLIKELY;
15668 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
15669 warning (0, "the %qs architecture does not support branch-likely"
15670 " instructions", mips_arch_info->name);
15672 /* The effect of -mabicalls isn't defined for the EABI. */
15673 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
15675 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15676 target_flags &= ~MASK_ABICALLS;
15679 if (TARGET_ABICALLS_PIC2)
15680 /* We need to set flag_pic for executables as well as DSOs
15681 because we may reference symbols that are not defined in
15682 the final executable. (MIPS does not use things like
15683 copy relocs, for example.)
15685 There is a body of code that uses __PIC__ to distinguish
15686 between -mabicalls and -mno-abicalls code. The non-__PIC__
15687 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15688 long as any indirect jumps use $25. */
15691 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15692 faster code, but at the expense of more nops. Enable it at -O3 and
15694 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
15695 target_flags |= MASK_VR4130_ALIGN;
15697 /* Prefer a call to memcpy over inline code when optimizing for size,
15698 though see MOVE_RATIO in mips.h. */
15699 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
15700 target_flags |= MASK_MEMCPY;
15702 /* If we have a nonzero small-data limit, check that the -mgpopt
15703 setting is consistent with the other target flags. */
15704 if (mips_small_data_threshold > 0)
15708 if (!TARGET_EXPLICIT_RELOCS)
15709 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15711 TARGET_LOCAL_SDATA = false;
15712 TARGET_EXTERN_SDATA = false;
15716 if (TARGET_VXWORKS_RTP)
15717 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15719 if (TARGET_ABICALLS)
15720 warning (0, "cannot use small-data accesses for %qs",
15725 #ifdef MIPS_TFMODE_FORMAT
15726 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
15729 /* Make sure that the user didn't turn off paired single support when
15730 MIPS-3D support is requested. */
15732 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
15733 && !TARGET_PAIRED_SINGLE_FLOAT)
15734 error ("%<-mips3d%> requires %<-mpaired-single%>");
15736 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15738 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
15740 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15741 and TARGET_HARD_FLOAT_ABI are both true. */
15742 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
15743 error ("%qs must be used with %qs",
15744 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
15745 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
15747 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15749 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
15750 warning (0, "the %qs architecture does not support paired-single"
15751 " instructions", mips_arch_info->name);
15753 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
15754 && !TARGET_CACHE_BUILTIN)
15756 error ("%qs requires a target that provides the %qs instruction",
15757 "-mr10k-cache-barrier", "cache");
15758 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
15761 /* If TARGET_DSPR2, enable MASK_DSP. */
15763 target_flags |= MASK_DSP;
15765 /* .eh_frame addresses should be the same width as a C pointer.
15766 Most MIPS ABIs support only one pointer size, so the assembler
15767 will usually know exactly how big an .eh_frame address is.
15769 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15770 originally defined to use 64-bit pointers (i.e. it is LP64), and
15771 this is still the default mode. However, we also support an n32-like
15772 ILP32 mode, which is selected by -mlong32. The problem is that the
15773 assembler has traditionally not had an -mlong option, so it has
15774 traditionally not known whether we're using the ILP32 or LP64 form.
15776 As it happens, gas versions up to and including 2.19 use _32-bit_
15777 addresses for EABI64 .cfi_* directives. This is wrong for the
15778 default LP64 mode, so we can't use the directives by default.
15779 Moreover, since gas's current behavior is at odds with gcc's
15780 default behavior, it seems unwise to rely on future versions
15781 of gas behaving the same way. We therefore avoid using .cfi
15782 directives for -mlong32 as well. */
15783 if (mips_abi == ABI_EABI && TARGET_64BIT)
15784 flag_dwarf2_cfi_asm = 0;
15786 /* .cfi_* directives generate a read-only section, so fall back on
15787 manual .eh_frame creation if we need the section to be writable. */
15788 if (TARGET_WRITABLE_EH_FRAME)
15789 flag_dwarf2_cfi_asm = 0;
15791 mips_init_print_operand_punct ();
15793 /* Set up array to map GCC register number to debug register number.
15794 Ignore the special purpose register numbers. */
15796 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
15798 mips_dbx_regno[i] = INVALID_REGNUM;
15799 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
15800 mips_dwarf_regno[i] = i;
15802 mips_dwarf_regno[i] = INVALID_REGNUM;
15805 start = GP_DBX_FIRST - GP_REG_FIRST;
15806 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
15807 mips_dbx_regno[i] = i + start;
15809 start = FP_DBX_FIRST - FP_REG_FIRST;
15810 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
15811 mips_dbx_regno[i] = i + start;
15813 /* Accumulator debug registers use big-endian ordering. */
15814 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
15815 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
15816 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
15817 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
15818 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
15820 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
15821 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
15824 /* Set up mips_hard_regno_mode_ok. */
15825 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
15826 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
15827 mips_hard_regno_mode_ok[mode][regno]
15828 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
15830 /* Function to allocate machine-dependent function status. */
15831 init_machine_status = &mips_init_machine_status;
15833 /* Default to working around R4000 errata only if the processor
15834 was selected explicitly. */
15835 if ((target_flags_explicit & MASK_FIX_R4000) == 0
15836 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
15837 target_flags |= MASK_FIX_R4000;
15839 /* Default to working around R4400 errata only if the processor
15840 was selected explicitly. */
15841 if ((target_flags_explicit & MASK_FIX_R4400) == 0
15842 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
15843 target_flags |= MASK_FIX_R4400;
15845 /* Default to working around R10000 errata only if the processor
15846 was selected explicitly. */
15847 if ((target_flags_explicit & MASK_FIX_R10000) == 0
15848 && mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
15849 target_flags |= MASK_FIX_R10000;
15851 /* Make sure that branch-likely instructions available when using
15852 -mfix-r10000. The instructions are not available if either:
15854 1. -mno-branch-likely was passed.
15855 2. The selected ISA does not support branch-likely and
15856 the command line does not include -mbranch-likely. */
15857 if (TARGET_FIX_R10000
15858 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
15859 ? !ISA_HAS_BRANCHLIKELY
15860 : !TARGET_BRANCHLIKELY))
15861 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15863 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
15865 warning (0, "the %qs architecture does not support the synci "
15866 "instruction", mips_arch_info->name);
15867 target_flags &= ~MASK_SYNCI;
15870 /* Only optimize PIC indirect calls if they are actually required. */
15871 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
15872 target_flags &= ~MASK_RELAX_PIC_CALLS;
15874 /* Save base state of options. */
15875 mips_base_target_flags = target_flags;
15876 mips_base_schedule_insns = flag_schedule_insns;
15877 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
15878 mips_base_move_loop_invariants = flag_move_loop_invariants;
15879 mips_base_align_loops = align_loops;
15880 mips_base_align_jumps = align_jumps;
15881 mips_base_align_functions = align_functions;
15883 /* Now select the ISA mode.
15885 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15886 MIPS16 mode afterwards if need be. */
15887 mips_set_mips16_mode (false);
15890 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
15891 static const struct default_options mips_option_optimization_table[] =
15893 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
15894 { OPT_LEVELS_NONE, 0, NULL, 0 }
15897 /* Swap the register information for registers I and I + 1, which
15898 currently have the wrong endianness. Note that the registers'
15899 fixedness and call-clobberedness might have been set on the
15903 mips_swap_registers (unsigned int i)
15908 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15909 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15911 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
15912 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
15913 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
15914 SWAP_STRING (reg_names[i], reg_names[i + 1]);
15920 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15923 mips_conditional_register_usage (void)
15928 /* These DSP control register fields are global. */
15929 global_regs[CCDSP_PO_REGNUM] = 1;
15930 global_regs[CCDSP_SC_REGNUM] = 1;
15936 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
15937 fixed_regs[regno] = call_used_regs[regno] = 1;
15939 if (!TARGET_HARD_FLOAT)
15943 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
15944 fixed_regs[regno] = call_used_regs[regno] = 1;
15945 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15946 fixed_regs[regno] = call_used_regs[regno] = 1;
15948 else if (! ISA_HAS_8CC)
15952 /* We only have a single condition-code register. We implement
15953 this by fixing all the condition-code registers and generating
15954 RTL that refers directly to ST_REG_FIRST. */
15955 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
15956 fixed_regs[regno] = call_used_regs[regno] = 1;
15958 /* In MIPS16 mode, we permit the $t temporary registers to be used
15959 for reload. We prohibit the unused $s registers, since they
15960 are call-saved, and saving them via a MIPS16 register would
15961 probably waste more time than just reloading the value. */
15964 fixed_regs[18] = call_used_regs[18] = 1;
15965 fixed_regs[19] = call_used_regs[19] = 1;
15966 fixed_regs[20] = call_used_regs[20] = 1;
15967 fixed_regs[21] = call_used_regs[21] = 1;
15968 fixed_regs[22] = call_used_regs[22] = 1;
15969 fixed_regs[23] = call_used_regs[23] = 1;
15970 fixed_regs[26] = call_used_regs[26] = 1;
15971 fixed_regs[27] = call_used_regs[27] = 1;
15972 fixed_regs[30] = call_used_regs[30] = 1;
15974 /* $f20-$f23 are call-clobbered for n64. */
15975 if (mips_abi == ABI_64)
15978 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
15979 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15981 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15983 if (mips_abi == ABI_N32)
15986 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
15987 call_really_used_regs[regno] = call_used_regs[regno] = 1;
15989 /* Make sure that double-register accumulator values are correctly
15990 ordered for the current endianness. */
15991 if (TARGET_LITTLE_ENDIAN)
15993 unsigned int regno;
15995 mips_swap_registers (MD_REG_FIRST);
15996 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
15997 mips_swap_registers (regno);
16001 /* Initialize vector TARGET to VALS. */
16004 mips_expand_vector_init (rtx target, rtx vals)
16006 enum machine_mode mode;
16007 enum machine_mode inner;
16008 unsigned int i, n_elts;
16011 mode = GET_MODE (target);
16012 inner = GET_MODE_INNER (mode);
16013 n_elts = GET_MODE_NUNITS (mode);
16015 gcc_assert (VECTOR_MODE_P (mode));
16017 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
16018 for (i = 0; i < n_elts; i++)
16019 emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)),
16020 XVECEXP (vals, 0, i));
16022 emit_move_insn (target, mem);
16025 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16026 other registers for instructions for which it is possible. This
16027 encourages the compiler to use CMP in cases where an XOR would
16028 require some register shuffling. */
16031 mips_order_regs_for_local_alloc (void)
16035 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16036 reg_alloc_order[i] = i;
16040 /* It really doesn't matter where we put register 0, since it is
16041 a fixed register anyhow. */
16042 reg_alloc_order[0] = 24;
16043 reg_alloc_order[24] = 0;
16047 /* Implement EH_USES. */
16050 mips_eh_uses (unsigned int regno)
16052 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16054 /* We need to force certain registers to be live in order to handle
16055 PIC long branches correctly. See mips_must_initialize_gp_p for
16057 if (mips_cfun_has_cprestore_slot_p ())
16059 if (regno == CPRESTORE_SLOT_REGNUM)
16064 if (cfun->machine->global_pointer == regno)
16072 /* Implement EPILOGUE_USES. */
16075 mips_epilogue_uses (unsigned int regno)
16077 /* Say that the epilogue uses the return address register. Note that
16078 in the case of sibcalls, the values "used by the epilogue" are
16079 considered live at the start of the called function. */
16080 if (regno == RETURN_ADDR_REGNUM)
16083 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16084 See the comment above load_call<mode> for details. */
16085 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16088 /* An interrupt handler must preserve some registers that are
16089 ordinarily call-clobbered. */
16090 if (cfun->machine->interrupt_handler_p
16091 && mips_interrupt_extra_call_saved_reg_p (regno))
16097 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16100 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16102 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16105 /* Return true if INSN needs to be wrapped in ".set noat".
16106 INSN has NOPERANDS operands, stored in OPVEC. */
16109 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16113 if (recog_memoized (insn) >= 0)
16114 for (i = 0; i < noperands; i++)
16115 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16120 /* Implement FINAL_PRESCAN_INSN. */
16123 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16125 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16126 mips_push_asm_switch (&mips_noat);
16129 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16132 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16133 rtx *opvec, int noperands)
16135 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16136 mips_pop_asm_switch (&mips_noat);
16139 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16140 EXT_CODE is the code of the extension used. Return NULL if widening
16141 multiplication shouldn't be used. */
16144 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16148 signed_p = ext_code == SIGN_EXTEND;
16151 /* Don't use widening multiplication with MULT when we have DMUL. Even
16152 with the extension of its input operands DMUL is faster. Note that
16153 the extension is not needed for signed multiplication. In order to
16154 ensure that we always remove the redundant sign-extension in this
16155 case we still expand mulsidi3 for DMUL. */
16157 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16158 if (TARGET_FIX_R4000)
16160 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16164 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16165 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16166 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16170 /* Return the size in bytes of the trampoline code, padded to
16171 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16172 function address immediately follow. */
16175 mips_trampoline_code_size (void)
16177 if (TARGET_USE_PIC_FN_ADDR_REG)
16179 else if (ptr_mode == DImode)
16181 else if (ISA_HAS_LOAD_DELAY)
16187 /* Implement TARGET_TRAMPOLINE_INIT. */
16190 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
16192 rtx addr, end_addr, high, low, opcode, mem;
16195 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
16197 /* Work out the offsets of the pointers from the start of the
16198 trampoline code. */
16199 end_addr_offset = mips_trampoline_code_size ();
16200 static_chain_offset = end_addr_offset;
16201 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
16203 /* Get pointers to the beginning and end of the code block. */
16204 addr = force_reg (Pmode, XEXP (m_tramp, 0));
16205 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
16207 #define OP(X) gen_int_mode (X, SImode)
16209 /* Build up the code in TRAMPOLINE. */
16211 if (TARGET_USE_PIC_FN_ADDR_REG)
16213 /* $25 contains the address of the trampoline. Emit code of the form:
16215 l[wd] $1, target_function_offset($25)
16216 l[wd] $static_chain, static_chain_offset($25)
16219 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
16220 target_function_offset,
16221 PIC_FUNCTION_ADDR_REGNUM));
16222 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16223 static_chain_offset,
16224 PIC_FUNCTION_ADDR_REGNUM));
16225 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
16226 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
16228 else if (ptr_mode == DImode)
16230 /* It's too cumbersome to create the full 64-bit address, so let's
16236 1: l[wd] $25, target_function_offset - 12($31)
16237 l[wd] $static_chain, static_chain_offset - 12($31)
16241 where 12 is the offset of "1:" from the start of the code block. */
16242 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
16243 trampoline[i++] = OP (MIPS_BAL (1));
16244 trampoline[i++] = OP (MIPS_NOP);
16245 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16246 target_function_offset - 12,
16247 RETURN_ADDR_REGNUM));
16248 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16249 static_chain_offset - 12,
16250 RETURN_ADDR_REGNUM));
16251 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16252 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
16256 /* If the target has load delays, emit:
16258 lui $1, %hi(end_addr)
16259 lw $25, %lo(end_addr + ...)($1)
16260 lw $static_chain, %lo(end_addr + ...)($1)
16266 lui $1, %hi(end_addr)
16267 lw $25, %lo(end_addr + ...)($1)
16269 lw $static_chain, %lo(end_addr + ...)($1). */
16271 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16272 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16273 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
16274 NULL, false, OPTAB_WIDEN);
16275 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
16276 NULL, false, OPTAB_WIDEN);
16277 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
16279 /* Emit the LUI. */
16280 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
16281 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
16282 NULL, false, OPTAB_WIDEN);
16284 /* Emit the load of the target function. */
16285 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
16286 target_function_offset - end_addr_offset,
16288 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16289 NULL, false, OPTAB_WIDEN);
16291 /* Emit the JR here, if we can. */
16292 if (!ISA_HAS_LOAD_DELAY)
16293 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16295 /* Emit the load of the static chain register. */
16296 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
16297 static_chain_offset - end_addr_offset,
16299 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
16300 NULL, false, OPTAB_WIDEN);
16302 /* Emit the JR, if we couldn't above. */
16303 if (ISA_HAS_LOAD_DELAY)
16305 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
16306 trampoline[i++] = OP (MIPS_NOP);
16312 /* Copy the trampoline code. Leave any padding uninitialized. */
16313 for (j = 0; j < i; j++)
16315 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
16316 mips_emit_move (mem, trampoline[j]);
16319 /* Set up the static chain pointer field. */
16320 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
16321 mips_emit_move (mem, chain_value);
16323 /* Set up the target function field. */
16324 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
16325 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
16327 /* Flush the code part of the trampoline. */
16328 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
16329 emit_insn (gen_clear_cache (addr, end_addr));
16332 /* Implement FUNCTION_PROFILER. */
16334 void mips_function_profiler (FILE *file)
16337 sorry ("mips16 function profiling");
16338 if (TARGET_LONG_CALLS)
16340 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16341 if (Pmode == DImode)
16342 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
16344 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
16346 mips_push_asm_switch (&mips_noat);
16347 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
16348 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
16349 /* _mcount treats $2 as the static chain register. */
16350 if (cfun->static_chain_decl != NULL)
16351 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
16352 reg_names[STATIC_CHAIN_REGNUM]);
16353 if (TARGET_MCOUNT_RA_ADDRESS)
16355 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16356 ra save location. */
16357 if (cfun->machine->frame.ra_fp_offset == 0)
16358 /* ra not saved, pass zero. */
16359 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
16361 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
16362 Pmode == DImode ? "dla" : "la", reg_names[12],
16363 cfun->machine->frame.ra_fp_offset,
16364 reg_names[STACK_POINTER_REGNUM]);
16366 if (!TARGET_NEWABI)
16368 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16369 TARGET_64BIT ? "dsubu" : "subu",
16370 reg_names[STACK_POINTER_REGNUM],
16371 reg_names[STACK_POINTER_REGNUM],
16372 Pmode == DImode ? 16 : 8);
16374 if (TARGET_LONG_CALLS)
16375 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
16377 fprintf (file, "\tjal\t_mcount\n");
16378 mips_pop_asm_switch (&mips_noat);
16379 /* _mcount treats $2 as the static chain register. */
16380 if (cfun->static_chain_decl != NULL)
16381 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
16385 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16386 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16387 when TARGET_LOONGSON_VECTORS is true. */
16389 static unsigned HOST_WIDE_INT
16390 mips_shift_truncation_mask (enum machine_mode mode)
16392 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
16395 return GET_MODE_BITSIZE (mode) - 1;
16399 /* Initialize the GCC target structure. */
16400 #undef TARGET_ASM_ALIGNED_HI_OP
16401 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16402 #undef TARGET_ASM_ALIGNED_SI_OP
16403 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16404 #undef TARGET_ASM_ALIGNED_DI_OP
16405 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16407 #undef TARGET_OPTION_OVERRIDE
16408 #define TARGET_OPTION_OVERRIDE mips_option_override
16409 #undef TARGET_OPTION_OPTIMIZATION_TABLE
16410 #define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
16412 #undef TARGET_LEGITIMIZE_ADDRESS
16413 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16415 #undef TARGET_ASM_FUNCTION_PROLOGUE
16416 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16417 #undef TARGET_ASM_FUNCTION_EPILOGUE
16418 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16419 #undef TARGET_ASM_SELECT_RTX_SECTION
16420 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16421 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16422 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16424 #undef TARGET_SCHED_INIT
16425 #define TARGET_SCHED_INIT mips_sched_init
16426 #undef TARGET_SCHED_REORDER
16427 #define TARGET_SCHED_REORDER mips_sched_reorder
16428 #undef TARGET_SCHED_REORDER2
16429 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16430 #undef TARGET_SCHED_VARIABLE_ISSUE
16431 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16432 #undef TARGET_SCHED_ADJUST_COST
16433 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16434 #undef TARGET_SCHED_ISSUE_RATE
16435 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16436 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16437 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16438 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16439 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16440 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16441 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16442 mips_multipass_dfa_lookahead
16443 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16444 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16445 mips_small_register_classes_for_mode_p
16447 #undef TARGET_DEFAULT_TARGET_FLAGS
16448 #define TARGET_DEFAULT_TARGET_FLAGS \
16450 | TARGET_CPU_DEFAULT \
16451 | TARGET_ENDIAN_DEFAULT \
16452 | TARGET_FP_EXCEPTIONS_DEFAULT \
16453 | MASK_CHECK_ZERO_DIV \
16455 #undef TARGET_HANDLE_OPTION
16456 #define TARGET_HANDLE_OPTION mips_handle_option
16458 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16459 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16461 #undef TARGET_INSERT_ATTRIBUTES
16462 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16463 #undef TARGET_MERGE_DECL_ATTRIBUTES
16464 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16465 #undef TARGET_SET_CURRENT_FUNCTION
16466 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16468 #undef TARGET_VALID_POINTER_MODE
16469 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16470 #undef TARGET_REGISTER_MOVE_COST
16471 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16472 #undef TARGET_MEMORY_MOVE_COST
16473 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16474 #undef TARGET_RTX_COSTS
16475 #define TARGET_RTX_COSTS mips_rtx_costs
16476 #undef TARGET_ADDRESS_COST
16477 #define TARGET_ADDRESS_COST mips_address_cost
16479 #undef TARGET_IN_SMALL_DATA_P
16480 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16482 #undef TARGET_MACHINE_DEPENDENT_REORG
16483 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16485 #undef TARGET_PREFERRED_RELOAD_CLASS
16486 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
16488 #undef TARGET_ASM_FILE_START
16489 #define TARGET_ASM_FILE_START mips_file_start
16490 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16491 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16493 #undef TARGET_INIT_LIBFUNCS
16494 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16496 #undef TARGET_BUILD_BUILTIN_VA_LIST
16497 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16498 #undef TARGET_EXPAND_BUILTIN_VA_START
16499 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16500 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16501 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16503 #undef TARGET_PROMOTE_FUNCTION_MODE
16504 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16505 #undef TARGET_PROMOTE_PROTOTYPES
16506 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16508 #undef TARGET_FUNCTION_VALUE
16509 #define TARGET_FUNCTION_VALUE mips_function_value
16510 #undef TARGET_LIBCALL_VALUE
16511 #define TARGET_LIBCALL_VALUE mips_libcall_value
16512 #undef TARGET_FUNCTION_VALUE_REGNO_P
16513 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
16514 #undef TARGET_RETURN_IN_MEMORY
16515 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16516 #undef TARGET_RETURN_IN_MSB
16517 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16519 #undef TARGET_ASM_OUTPUT_MI_THUNK
16520 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16521 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16522 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16524 #undef TARGET_PRINT_OPERAND
16525 #define TARGET_PRINT_OPERAND mips_print_operand
16526 #undef TARGET_PRINT_OPERAND_ADDRESS
16527 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16528 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16529 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16531 #undef TARGET_SETUP_INCOMING_VARARGS
16532 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16533 #undef TARGET_STRICT_ARGUMENT_NAMING
16534 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16535 #undef TARGET_MUST_PASS_IN_STACK
16536 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16537 #undef TARGET_PASS_BY_REFERENCE
16538 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16539 #undef TARGET_CALLEE_COPIES
16540 #define TARGET_CALLEE_COPIES mips_callee_copies
16541 #undef TARGET_ARG_PARTIAL_BYTES
16542 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16543 #undef TARGET_FUNCTION_ARG
16544 #define TARGET_FUNCTION_ARG mips_function_arg
16545 #undef TARGET_FUNCTION_ARG_ADVANCE
16546 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16547 #undef TARGET_FUNCTION_ARG_BOUNDARY
16548 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16550 #undef TARGET_MODE_REP_EXTENDED
16551 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16553 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16554 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16556 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16557 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16559 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16560 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16562 #undef TARGET_INIT_BUILTINS
16563 #define TARGET_INIT_BUILTINS mips_init_builtins
16564 #undef TARGET_BUILTIN_DECL
16565 #define TARGET_BUILTIN_DECL mips_builtin_decl
16566 #undef TARGET_EXPAND_BUILTIN
16567 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16569 #undef TARGET_HAVE_TLS
16570 #define TARGET_HAVE_TLS HAVE_AS_TLS
16572 #undef TARGET_CANNOT_FORCE_CONST_MEM
16573 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16575 #undef TARGET_ENCODE_SECTION_INFO
16576 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16578 #undef TARGET_ATTRIBUTE_TABLE
16579 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16580 /* All our function attributes are related to how out-of-line copies should
16581 be compiled or called. They don't in themselves prevent inlining. */
16582 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16583 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16585 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16586 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16588 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16589 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16590 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16591 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16593 #undef TARGET_COMP_TYPE_ATTRIBUTES
16594 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16596 #ifdef HAVE_AS_DTPRELWORD
16597 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16598 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16600 #undef TARGET_DWARF_REGISTER_SPAN
16601 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16603 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16604 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16606 #undef TARGET_LEGITIMATE_ADDRESS_P
16607 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16609 #undef TARGET_FRAME_POINTER_REQUIRED
16610 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16612 #undef TARGET_CAN_ELIMINATE
16613 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16615 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16616 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16618 #undef TARGET_TRAMPOLINE_INIT
16619 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16621 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16622 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16624 #undef TARGET_SHIFT_TRUNCATION_MASK
16625 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16627 struct gcc_target targetm = TARGET_INITIALIZER;
16629 #include "gt-mips.h"