1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
58 #define STAB_CODE_TYPE enum __stab_debug_code
60 #define STAB_CODE_TYPE int
63 extern tree lookup_name PARAMS ((tree));
65 /* Enumeration for all of the relational tests, so that we can build
66 arrays indexed by the test type, and not worry about the order
86 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
87 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
89 static int m16_check_op PARAMS ((rtx, int, int, int));
90 static void block_move_loop PARAMS ((rtx, rtx,
94 static void block_move_call PARAMS ((rtx, rtx, rtx));
95 static void mips_arg_info PARAMS ((const CUMULATIVE_ARGS *,
98 struct mips_arg_info *));
99 static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT));
100 static void mips_annotate_frame_insn PARAMS ((rtx, rtx));
101 static rtx mips_frame_set PARAMS ((enum machine_mode,
103 static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
105 static void save_restore_insns PARAMS ((int, rtx, long));
106 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
107 static void mips16_fp_args PARAMS ((FILE *, int, int));
108 static void build_mips16_function_stub PARAMS ((FILE *));
109 static void mips16_optimize_gp PARAMS ((rtx));
110 static rtx add_constant PARAMS ((struct constant **,
113 static void dump_constants PARAMS ((struct constant *,
115 static rtx mips_find_symbol PARAMS ((rtx));
116 static void abort_with_insn PARAMS ((rtx, const char *))
118 static int symbolic_expression_p PARAMS ((rtx));
119 static bool mips_assemble_integer PARAMS ((rtx, unsigned int, int));
120 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
121 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
122 static void mips_set_architecture PARAMS ((const struct mips_cpu_info *));
123 static void mips_set_tune PARAMS ((const struct mips_cpu_info *));
124 static bool mips_strict_matching_cpu_name_p PARAMS ((const char *,
126 static bool mips_matching_cpu_name_p PARAMS ((const char *,
128 static const struct mips_cpu_info *mips_parse_cpu PARAMS ((const char *,
130 static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
131 static void copy_file_data PARAMS ((FILE *, FILE *));
133 static void iris6_asm_named_section_1 PARAMS ((const char *,
136 static void iris6_asm_named_section PARAMS ((const char *,
138 static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
139 static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
140 static int iris6_section_align_1 PARAMS ((void **, void *));
142 static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
143 static int mips_issue_rate PARAMS ((void));
145 static struct machine_function * mips_init_machine_status PARAMS ((void));
146 static void mips_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
148 static void mips_unique_section PARAMS ((tree, int))
150 static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
151 unsigned HOST_WIDE_INT));
152 static void mips_encode_section_info PARAMS ((tree, int));
154 /* Structure to be filled in by compute_frame_size with register
155 save masks, and offsets for the current function. */
157 struct mips_frame_info GTY(())
159 long total_size; /* # bytes that the entire frame takes up */
160 long var_size; /* # bytes that variables take up */
161 long args_size; /* # bytes that outgoing arguments take up */
162 long extra_size; /* # bytes of extra gunk */
163 int gp_reg_size; /* # bytes needed to store gp regs */
164 int fp_reg_size; /* # bytes needed to store fp regs */
165 long mask; /* mask of saved gp registers */
166 long fmask; /* mask of saved fp registers */
167 long gp_save_offset; /* offset from vfp to store gp registers */
168 long fp_save_offset; /* offset from vfp to store fp registers */
169 long gp_sp_offset; /* offset from new sp to store gp registers */
170 long fp_sp_offset; /* offset from new sp to store fp registers */
171 int initialized; /* != 0 if frame size already calculated */
172 int num_gp; /* number of gp registers saved */
173 int num_fp; /* number of fp registers saved */
176 struct machine_function GTY(()) {
177 /* Pseudo-reg holding the address of the current function when
178 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS,
179 used by mips_finalize_pic if it was created. */
180 rtx embedded_pic_fnaddr_rtx;
182 /* Pseudo-reg holding the value of $28 in a mips16 function which
183 refers to GP relative global variables. */
184 rtx mips16_gp_pseudo_rtx;
186 /* Current frame information, calculated by compute_frame_size. */
187 struct mips_frame_info frame;
189 /* Length of instructions in function; mips16 only. */
193 /* Information about a single argument. */
196 /* True if the argument is a record or union type. */
199 /* True if the argument is passed in a floating-point register, or
200 would have been if we hadn't run out of registers. */
203 /* The argument's size, in bytes. */
204 unsigned int num_bytes;
206 /* The number of words passed in registers, rounded up. */
207 unsigned int reg_words;
209 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
210 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
212 unsigned int reg_offset;
214 /* The number of words that must be passed on the stack, rounded up. */
215 unsigned int stack_words;
217 /* The offset from the start of the stack overflow area of the argument's
218 first stack word. Only meaningful when STACK_WORDS is non-zero. */
219 unsigned int stack_offset;
222 /* Global variables for machine-dependent things. */
224 /* Threshold for data being put into the small data/bss area, instead
225 of the normal data area (references to the small data/bss area take
226 1 instruction, and use the global pointer, references to the normal
227 data area takes 2 instructions). */
228 int mips_section_threshold = -1;
230 /* Count the number of .file directives, so that .loc is up to date. */
231 int num_source_filenames = 0;
233 /* Count the number of sdb related labels are generated (to find block
234 start and end boundaries). */
235 int sdb_label_count = 0;
237 /* Next label # for each statement for Silicon Graphics IRIS systems. */
240 /* Non-zero if inside of a function, because the stupid MIPS asm can't
241 handle .files inside of functions. */
242 int inside_function = 0;
244 /* Files to separate the text and the data output, so that all of the data
245 can be emitted before the text, which will mean that the assembler will
246 generate smaller code, based on the global pointer. */
247 FILE *asm_out_data_file;
248 FILE *asm_out_text_file;
250 /* Linked list of all externals that are to be emitted when optimizing
251 for the global pointer if they haven't been declared by the end of
252 the program with an appropriate .comm or initialization. */
256 struct extern_list *next; /* next external */
257 const char *name; /* name of the external */
258 int size; /* size in bytes */
261 /* Name of the file containing the current function. */
262 const char *current_function_file = "";
264 /* Warning given that Mips ECOFF can't support changing files
265 within a function. */
266 int file_in_function_warning = FALSE;
268 /* Whether to suppress issuing .loc's because the user attempted
269 to change the filename within a function. */
270 int ignore_line_number = FALSE;
272 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
278 /* The next branch instruction is a branch likely, not branch normal. */
279 int mips_branch_likely;
281 /* Count of delay slots and how many are filled. */
282 int dslots_load_total;
283 int dslots_load_filled;
284 int dslots_jump_total;
285 int dslots_jump_filled;
287 /* # of nops needed by previous insn */
288 int dslots_number_nops;
290 /* Number of 1/2/3 word references to data items (ie, not jal's). */
293 /* registers to check for load delay */
294 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
296 /* Cached operands, and operator to compare for use in set/branch/trap
297 on condition codes. */
300 /* what type of branch to use */
301 enum cmp_type branch_type;
303 /* The target cpu for code generation. */
304 enum processor_type mips_arch;
305 const struct mips_cpu_info *mips_arch_info;
307 /* The target cpu for optimization and scheduling. */
308 enum processor_type mips_tune;
309 const struct mips_cpu_info *mips_tune_info;
311 /* which instruction set architecture to use. */
314 /* which abi to use. */
317 /* Strings to hold which cpu and instruction set architecture to use. */
318 const char *mips_arch_string; /* for -march=<xxx> */
319 const char *mips_tune_string; /* for -mtune=<xxx> */
320 const char *mips_isa_string; /* for -mips{1,2,3,4} */
321 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
323 /* Whether we are generating mips16 code. This is a synonym for
324 TARGET_MIPS16, and exists for use as an attribute. */
327 /* This variable is set by -mno-mips16. We only care whether
328 -mno-mips16 appears or not, and using a string in this fashion is
329 just a way to avoid using up another bit in target_flags. */
330 const char *mips_no_mips16_string;
332 /* Whether we are generating mips16 hard float code. In mips16 mode
333 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
334 -msoft-float was not specified by the user, which means that we
335 should arrange to call mips32 hard floating point code. */
336 int mips16_hard_float;
338 /* This variable is set by -mentry. We only care whether -mentry
339 appears or not, and using a string in this fashion is just a way to
340 avoid using up another bit in target_flags. */
341 const char *mips_entry_string;
343 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
345 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
348 /* If TRUE, we split addresses into their high and low parts in the RTL. */
349 int mips_split_addresses;
351 /* Generating calls to position independent functions? */
352 enum mips_abicalls_type mips_abicalls;
354 /* High and low marks for floating point values which we will accept
355 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
356 initialized in override_options. */
357 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
359 /* Mode used for saving/restoring general purpose registers. */
360 static enum machine_mode gpr_mode;
362 /* Array giving truth value on whether or not a given hard register
363 can support a given mode. */
364 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
366 /* The length of all strings seen when compiling for the mips16. This
367 is used to tell how many strings are in the constant pool, so that
368 we can see if we may have an overflow. This is reset each time the
369 constant pool is output. */
370 int mips_string_length;
372 /* In mips16 mode, we build a list of all the string constants we see
373 in a particular function. */
375 struct string_constant
377 struct string_constant *next;
381 static struct string_constant *string_constants;
383 /* List of all MIPS punctuation characters used by print_operand. */
384 char mips_print_operand_punct[256];
386 /* Map GCC register number to debugger register number. */
387 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
389 /* Buffer to use to enclose a load/store operation with %{ %} to
390 turn on .set volatile. */
391 static char volatile_buffer[60];
393 /* Hardware names for the registers. If -mrnames is used, this
394 will be overwritten with mips_sw_reg_names. */
396 char mips_reg_names[][8] =
398 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
399 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
400 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
401 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
402 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
403 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
404 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
405 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
406 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
407 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
408 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
409 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
410 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
411 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
412 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
413 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
414 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
415 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
416 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
417 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
418 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
419 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
422 /* Mips software names for the registers, used to overwrite the
423 mips_reg_names array. */
425 char mips_sw_reg_names[][8] =
427 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
428 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
429 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
430 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
431 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
432 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
433 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
434 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
435 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
436 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
437 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
438 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
439 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
440 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
441 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
442 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
443 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
444 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
445 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
446 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
447 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
448 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
451 /* Map hard register number to register class */
452 const enum reg_class mips_regno_to_class[] =
454 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
455 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
456 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
457 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
458 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
459 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
460 T_REG, GR_REGS, GR_REGS, GR_REGS,
461 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
462 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
463 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
464 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
465 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
466 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
467 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
468 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
469 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
470 HI_REG, LO_REG, HILO_REG, ST_REGS,
471 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
472 ST_REGS, ST_REGS, ST_REGS, GR_REGS,
473 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
474 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
475 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
476 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
477 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
478 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
479 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
480 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
481 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
482 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
483 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
484 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
485 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
486 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
487 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
488 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
489 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
490 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
491 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
492 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
493 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
494 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
495 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
496 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
497 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
500 /* Map register constraint character to register class. */
501 enum reg_class mips_char_to_class[256] =
503 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
504 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
505 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
506 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
507 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
508 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
509 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
510 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
511 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
512 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
513 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
514 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
515 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
516 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
517 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
518 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
519 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
520 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
521 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
522 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
523 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
524 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
525 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
526 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
527 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
528 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
529 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
530 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
531 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
532 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
533 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
534 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
535 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
536 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
537 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
538 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
539 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
540 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
541 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
542 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
543 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
544 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
545 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
546 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
547 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
548 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
549 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
550 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
551 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
552 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
553 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
554 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
555 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
556 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
557 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
558 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
559 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
560 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
561 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
562 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
563 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
564 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
565 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
566 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
569 /* A table describing all the processors gcc knows about. Names are
570 matched in the order listed. The first mention of an ISA level is
571 taken as the canonical name for that ISA.
573 To ease comparison, please keep this table in the same order as
574 gas's mips_cpu_info_table[]. */
575 const struct mips_cpu_info mips_cpu_info_table[] = {
576 /* Entries for generic ISAs */
577 { "mips1", PROCESSOR_R3000, 1 },
578 { "mips2", PROCESSOR_R6000, 2 },
579 { "mips3", PROCESSOR_R4000, 3 },
580 { "mips4", PROCESSOR_R8000, 4 },
581 { "mips32", PROCESSOR_R4KC, 32 },
582 { "mips64", PROCESSOR_R5KC, 64 },
585 { "r3000", PROCESSOR_R3000, 1 },
586 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
587 { "r3900", PROCESSOR_R3900, 1 },
590 { "r6000", PROCESSOR_R6000, 2 },
593 { "r4000", PROCESSOR_R4000, 3 },
594 { "vr4100", PROCESSOR_R4100, 3 },
595 { "vr4300", PROCESSOR_R4300, 3 },
596 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
597 { "r4600", PROCESSOR_R4600, 3 },
598 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
599 { "r4650", PROCESSOR_R4650, 3 },
602 { "r8000", PROCESSOR_R8000, 4 },
603 { "vr5000", PROCESSOR_R5000, 4 },
606 { "4kc", PROCESSOR_R4KC, 32 },
607 { "4kp", PROCESSOR_R4KC, 32 }, /* = 4kc */
610 { "5kc", PROCESSOR_R5KC, 64 },
611 { "20kc", PROCESSOR_R20KC, 64 },
613 /* Broadcom SB-1 CPU core */
614 { "sb1", PROCESSOR_SB1, 64 },
620 /* Initialize the GCC target structure. */
621 #undef TARGET_ASM_ALIGNED_HI_OP
622 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
623 #undef TARGET_ASM_ALIGNED_SI_OP
624 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
625 #undef TARGET_ASM_INTEGER
626 #define TARGET_ASM_INTEGER mips_assemble_integer
628 #if TARGET_IRIX5 && !TARGET_IRIX6
629 #undef TARGET_ASM_UNALIGNED_HI_OP
630 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"
631 #undef TARGET_ASM_UNALIGNED_SI_OP
632 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"
633 #undef TARGET_ASM_UNALIGNED_DI_OP
634 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.dword\t"
637 #undef TARGET_ASM_FUNCTION_PROLOGUE
638 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
639 #undef TARGET_ASM_FUNCTION_EPILOGUE
640 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
641 #undef TARGET_ASM_SELECT_RTX_SECTION
642 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
644 #undef TARGET_SCHED_ADJUST_COST
645 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
646 #undef TARGET_SCHED_ISSUE_RATE
647 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
649 #undef TARGET_ENCODE_SECTION_INFO
650 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
652 struct gcc_target targetm = TARGET_INITIALIZER;
654 /* Return truth value of whether OP can be used as an operands
655 where a register or 16 bit unsigned integer is needed. */
658 uns_arith_operand (op, mode)
660 enum machine_mode mode;
662 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
665 return register_operand (op, mode);
668 /* Return truth value of whether OP can be used as an operands
669 where a 16 bit integer is needed */
672 arith_operand (op, mode)
674 enum machine_mode mode;
676 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
679 /* On the mips16, a GP relative value is a signed 16 bit offset. */
680 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
683 return register_operand (op, mode);
686 /* Return truth value of whether OP can be used as an operand in a two
687 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
690 arith32_operand (op, mode)
692 enum machine_mode mode;
694 if (GET_CODE (op) == CONST_INT)
697 return register_operand (op, mode);
700 /* Return truth value of whether OP is an integer which fits in 16 bits. */
705 enum machine_mode mode ATTRIBUTE_UNUSED;
707 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
710 /* Return truth value of whether OP is a 32 bit integer which is too big to
711 be loaded with one instruction. */
716 enum machine_mode mode ATTRIBUTE_UNUSED;
720 if (GET_CODE (op) != CONST_INT)
725 /* ior reg,$r0,value */
726 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
729 /* subu reg,$r0,value */
730 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
733 /* lui reg,value>>16 */
734 if ((value & 0x0000ffff) == 0)
740 /* Return truth value of whether OP is a register or the constant 0.
741 In mips16 mode, we only accept a register, since the mips16 does
745 reg_or_0_operand (op, mode)
747 enum machine_mode mode;
749 switch (GET_CODE (op))
754 return INTVAL (op) == 0;
759 return op == CONST0_RTX (mode);
763 return register_operand (op, mode);
772 /* Return truth value of whether OP is a register or the constant 0,
773 even in mips16 mode. */
776 true_reg_or_0_operand (op, mode)
778 enum machine_mode mode;
780 switch (GET_CODE (op))
783 return INTVAL (op) == 0;
786 return op == CONST0_RTX (mode);
790 return register_operand (op, mode);
799 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
802 mips_const_double_ok (op, mode)
804 enum machine_mode mode;
808 if (GET_CODE (op) != CONST_DOUBLE)
811 if (mode == VOIDmode)
814 if (mode != SFmode && mode != DFmode)
817 if (op == CONST0_RTX (mode))
820 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
821 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
824 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
826 if (REAL_VALUE_ISNAN (d))
829 if (REAL_VALUE_NEGATIVE (d))
830 d = REAL_VALUE_NEGATE (d);
834 if (REAL_VALUES_LESS (d, dfhigh)
835 && REAL_VALUES_LESS (dflow, d))
840 if (REAL_VALUES_LESS (d, sfhigh)
841 && REAL_VALUES_LESS (sflow, d))
848 /* Accept the floating point constant 1 in the appropriate mode. */
851 const_float_1_operand (op, mode)
853 enum machine_mode mode;
856 static REAL_VALUE_TYPE onedf;
857 static REAL_VALUE_TYPE onesf;
858 static int one_initialized;
860 if (GET_CODE (op) != CONST_DOUBLE
861 || mode != GET_MODE (op)
862 || (mode != DFmode && mode != SFmode))
865 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
867 /* We only initialize these values if we need them, since we will
868 never get called unless mips_isa >= 4. */
869 if (! one_initialized)
871 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
872 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
877 return REAL_VALUES_EQUAL (d, onedf);
879 return REAL_VALUES_EQUAL (d, onesf);
882 /* Return true if a memory load or store of REG plus OFFSET in MODE
883 can be represented in a single word on the mips16. */
886 mips16_simple_memory_operand (reg, offset, mode)
889 enum machine_mode mode;
896 /* We can't tell, because we don't know how the value will
897 eventually be accessed. Returning 0 here does no great
898 harm; it just prevents some possible instruction scheduling. */
902 size = GET_MODE_SIZE (mode);
904 if (INTVAL (offset) % size != 0)
906 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
910 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
915 /* Return truth value if a memory operand fits in a single instruction
916 (ie, register + small offset). */
919 simple_memory_operand (op, mode)
921 enum machine_mode mode;
923 rtx addr, plus0, plus1;
925 /* Eliminate non-memory operations */
926 if (GET_CODE (op) != MEM)
929 /* dword operations really put out 2 instructions, so eliminate them. */
930 /* ??? This isn't strictly correct. It is OK to accept multiword modes
931 here, since the length attributes are being set correctly, but only
932 if the address is offsettable. LO_SUM is not offsettable. */
933 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
936 /* Decode the address now. */
938 switch (GET_CODE (addr))
947 return SMALL_INT (addr);
950 plus0 = XEXP (addr, 0);
951 plus1 = XEXP (addr, 1);
952 if (GET_CODE (plus0) == REG
953 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
955 || mips16_simple_memory_operand (plus0, plus1, mode)))
958 else if (GET_CODE (plus1) == REG
959 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
961 || mips16_simple_memory_operand (plus1, plus0, mode)))
968 /* We used to allow small symbol refs here (ie, stuff in .sdata
969 or .sbss), but this causes some bugs in G++. Also, it won't
970 interfere if the MIPS linker rewrites the store instruction
971 because the function is PIC. */
973 case LABEL_REF: /* never gp relative */
977 /* If -G 0, we can never have a GP relative memory operation.
978 Also, save some time if not optimizing. */
983 rtx offset = const0_rtx;
984 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
985 if (GET_CODE (op) != SYMBOL_REF)
988 /* let's be paranoid.... */
989 if (! SMALL_INT (offset))
996 return SYMBOL_REF_FLAG (addr);
999 /* This SYMBOL_REF case is for the mips16. If the above case is
1000 reenabled, this one should be merged in. */
1002 /* References to the constant pool on the mips16 use a small
1003 offset if the function is small. The only time we care about
1004 getting this right is during delayed branch scheduling, so
1005 don't need to check until then. The machine_dependent_reorg
1006 function will set the total length of the instructions used
1007 in the function (cfun->machine->insns_len). If that is small
1008 enough, we know for sure that this is a small offset. It
1009 would be better if we could take into account the location of
1010 the instruction within the function, but we can't, because we
1011 don't know where we are. */
1013 && CONSTANT_POOL_ADDRESS_P (addr)
1014 && cfun->machine->insns_len > 0)
1018 size = cfun->machine->insns_len + get_pool_size ();
1019 if (GET_MODE_SIZE (mode) == 4)
1020 return size < 4 * 0x100;
1021 else if (GET_MODE_SIZE (mode) == 8)
1022 return size < 8 * 0x20;
1036 /* Return nonzero for a memory address that can be used to load or store
1040 double_memory_operand (op, mode)
1042 enum machine_mode mode;
1044 if (GET_CODE (op) != MEM
1045 || ! memory_operand (op, mode))
1047 /* During reload, we accept a pseudo register if it has an
1048 appropriate memory address. If we don't do this, we will
1049 wind up reloading into a register, and then reloading that
1050 register from memory, when we could just reload directly from
1052 if (reload_in_progress
1053 && GET_CODE (op) == REG
1054 && REGNO (op) >= FIRST_PSEUDO_REGISTER
1055 && reg_renumber[REGNO (op)] < 0
1056 && reg_equiv_mem[REGNO (op)] != 0
1057 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
1060 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
1061 the same test performed for 'm' in find_reloads. */
1063 if (reload_in_progress
1065 && (GET_CODE (op) == MEM
1066 || (GET_CODE (op) == REG
1067 && REGNO (op) >= FIRST_PSEUDO_REGISTER
1068 && reg_renumber[REGNO (op)] < 0)))
1071 if (reload_in_progress
1073 && GET_CODE (op) == MEM)
1077 addr = XEXP (op, 0);
1079 /* During reload on the mips16, we accept a large offset
1080 from the frame pointer or the stack pointer. This large
1081 address will get reloaded anyhow. */
1082 if (GET_CODE (addr) == PLUS
1083 && GET_CODE (XEXP (addr, 0)) == REG
1084 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1085 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
1086 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
1087 && ! SMALL_INT (XEXP (addr, 1)))
1088 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
1089 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
1092 /* Similarly, we accept a case where the memory address is
1093 itself on the stack, and will be reloaded. */
1094 if (GET_CODE (addr) == MEM)
1098 maddr = XEXP (addr, 0);
1099 if (GET_CODE (maddr) == PLUS
1100 && GET_CODE (XEXP (maddr, 0)) == REG
1101 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1102 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
1103 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
1104 && ! SMALL_INT (XEXP (maddr, 1)))
1105 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
1106 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
1110 /* We also accept the same case when we have a 16 bit signed
1111 offset mixed in as well. The large address will get
1112 reloaded, and the 16 bit offset will be OK. */
1113 if (GET_CODE (addr) == PLUS
1114 && GET_CODE (XEXP (addr, 0)) == MEM
1115 && GET_CODE (XEXP (addr, 1)) == CONST_INT
1116 && SMALL_INT (XEXP (addr, 1)))
1118 addr = XEXP (XEXP (addr, 0), 0);
1119 if (GET_CODE (addr) == PLUS
1120 && GET_CODE (XEXP (addr, 0)) == REG
1121 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
1122 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
1123 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
1124 && ! SMALL_INT (XEXP (addr, 1)))
1125 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
1126 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
1136 /* In this case we can use an instruction like sd. */
1140 /* Make sure that 4 added to the address is a valid memory address.
1141 This essentially just checks for overflow in an added constant. */
1143 if (CONSTANT_ADDRESS_P (XEXP (op, 0)))
1146 op = adjust_address_nv (op, GET_MODE_CLASS (mode) == MODE_INT
1147 ? SImode : SFmode, 4);
1148 return memory_address_p (GET_MODE (op), XEXP (op, 0));
1151 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1154 equality_op (op, mode)
1156 enum machine_mode mode;
1158 if (mode != GET_MODE (op))
1161 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1164 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1169 enum machine_mode mode;
1171 if (mode != GET_MODE (op))
1174 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1177 /* Return nonzero if the code is a relational operation suitable for a
1178 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
1179 We need this in the insn that expands `trap_if' in order to prevent
1180 combine from erroneously altering the condition. */
1183 trap_cmp_op (op, mode)
1185 enum machine_mode mode;
1187 if (mode != GET_MODE (op))
1190 switch (GET_CODE (op))
1205 /* Return nonzero if the operand is either the PC or a label_ref. */
1208 pc_or_label_operand (op, mode)
1210 enum machine_mode mode ATTRIBUTE_UNUSED;
1215 if (GET_CODE (op) == LABEL_REF)
1221 /* Test for a valid operand for a call instruction.
1222 Don't allow the arg pointer register or virtual regs
1223 since they may change into reg + const, which the patterns
1224 can't handle yet. */
1227 call_insn_operand (op, mode)
1229 enum machine_mode mode ATTRIBUTE_UNUSED;
1231 return (CONSTANT_ADDRESS_P (op)
1232 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1233 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1234 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1237 /* Return nonzero if OPERAND is valid as a source operand for a move
1241 move_operand (op, mode)
1243 enum machine_mode mode;
1245 /* Accept any general operand after reload has started; doing so
1246 avoids losing if reload does an in-place replacement of a register
1247 with a SYMBOL_REF or CONST. */
1248 return (general_operand (op, mode)
1249 && (! (mips_split_addresses && mips_check_split (op, mode))
1250 || reload_in_progress || reload_completed)
1252 && GET_CODE (op) == SYMBOL_REF
1253 && ! mips16_constant (op, mode, 1, 0)));
1256 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1257 This accepts not only general_operand, but also sign extended
1258 move_operands. Note that we need to accept sign extended constants
1259 in case a sign extended register which is used in an expression,
1260 and is equivalent to a constant, is spilled. We need to accept
1261 sign-extended memory in order to reload registers from stack slots,
1262 and so that we generate efficient code for extendsidi2. */
1265 movdi_operand (op, mode)
1267 enum machine_mode mode;
1271 && GET_CODE (op) == SIGN_EXTEND
1272 && GET_MODE (op) == DImode
1273 && move_operand (XEXP (op, 0), SImode))
1276 return (general_operand (op, mode)
1278 && GET_CODE (op) == SYMBOL_REF
1279 && ! mips16_constant (op, mode, 1, 0)));
1282 /* Like register_operand, but when in 64 bit mode also accept a sign
1283 extend of a 32 bit register, since the value is known to be already
1287 se_register_operand (op, mode)
1289 enum machine_mode mode;
1293 && GET_CODE (op) == SIGN_EXTEND
1294 && GET_MODE (op) == DImode
1295 && GET_MODE (XEXP (op, 0)) == SImode
1296 && register_operand (XEXP (op, 0), SImode))
1299 return register_operand (op, mode);
1302 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1303 extend of a 32 bit register, since the value is known to be already
1307 se_reg_or_0_operand (op, mode)
1309 enum machine_mode mode;
1313 && GET_CODE (op) == SIGN_EXTEND
1314 && GET_MODE (op) == DImode
1315 && GET_MODE (XEXP (op, 0)) == SImode
1316 && register_operand (XEXP (op, 0), SImode))
1319 return reg_or_0_operand (op, mode);
1322 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1323 extend of a 32 bit register, since the value is known to be already
1327 se_uns_arith_operand (op, mode)
1329 enum machine_mode mode;
1333 && GET_CODE (op) == SIGN_EXTEND
1334 && GET_MODE (op) == DImode
1335 && GET_MODE (XEXP (op, 0)) == SImode
1336 && register_operand (XEXP (op, 0), SImode))
1339 return uns_arith_operand (op, mode);
1342 /* Like arith_operand, but when in 64 bit mode also accept a sign
1343 extend of a 32 bit register, since the value is known to be already
1347 se_arith_operand (op, mode)
1349 enum machine_mode mode;
1353 && GET_CODE (op) == SIGN_EXTEND
1354 && GET_MODE (op) == DImode
1355 && GET_MODE (XEXP (op, 0)) == SImode
1356 && register_operand (XEXP (op, 0), SImode))
1359 return arith_operand (op, mode);
1362 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1363 extend of a 32 bit register, since the value is known to be already
1367 se_nonmemory_operand (op, mode)
1369 enum machine_mode mode;
1373 && GET_CODE (op) == SIGN_EXTEND
1374 && GET_MODE (op) == DImode
1375 && GET_MODE (XEXP (op, 0)) == SImode
1376 && register_operand (XEXP (op, 0), SImode))
1379 return nonmemory_operand (op, mode);
1382 /* Accept any operand that can appear in a mips16 constant table
1383 instruction. We can't use any of the standard operand functions
1384 because for these instructions we accept values that are not
1385 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1388 consttable_operand (op, mode)
1390 enum machine_mode mode ATTRIBUTE_UNUSED;
1392 return CONSTANT_P (op);
1395 /* Coprocessor operand; return true if rtx is a REG and refers to a
1399 coprocessor_operand (op, mode)
1401 enum machine_mode mode ATTRIBUTE_UNUSED;
1403 return (GET_CODE (op) == REG
1404 && COP0_REG_FIRST <= REGNO (op)
1405 && REGNO (op) <= COP3_REG_LAST);
1409 coprocessor2_operand (op, mode)
1411 enum machine_mode mode ATTRIBUTE_UNUSED;
1413 return (GET_CODE (op) == REG
1414 && COP2_REG_FIRST <= REGNO (op)
1415 && REGNO (op) <= COP2_REG_LAST);
1418 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1419 possibly with an offset. */
1422 symbolic_operand (op, mode)
1424 enum machine_mode mode;
1426 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1428 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1430 if (GET_CODE (op) == CONST
1431 && GET_CODE (XEXP (op,0)) == PLUS
1432 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1433 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1438 /* Return nonzero if we split the address into high and low parts. */
1440 /* ??? We should also handle reg+array somewhere. We get four
1441 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1442 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1443 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1444 out of the address, then we have 4 instructions to combine. Perhaps
1445 add a 3->2 define_split for combine. */
1447 /* ??? We could also split a CONST_INT here if it is a large_int().
1448 However, it doesn't seem to be very useful to have %hi(constant).
1449 We would be better off by doing the masking ourselves and then putting
1450 the explicit high part of the constant in the RTL. This will give better
1451 optimization. Also, %hi(constant) needs assembler changes to work.
1452 There is already a define_split that does this. */
1455 mips_check_split (address, mode)
1457 enum machine_mode mode;
1459 /* ??? This is the same check used in simple_memory_operand.
1460 We use it here because LO_SUM is not offsettable. */
1461 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1464 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1465 || (GET_CODE (address) == CONST
1466 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1467 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1468 || GET_CODE (address) == LABEL_REF)
1474 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1477 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1479 enum machine_mode mode;
1483 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1484 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1487 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1488 returns a nonzero value if XINSN is a legitimate address for a
1489 memory operand of the indicated MODE. STRICT is non-zero if this
1490 function is called during reload. */
1493 mips_legitimate_address_p (mode, xinsn, strict)
1494 enum machine_mode mode;
1498 if (TARGET_DEBUG_B_MODE)
1500 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1501 strict ? "" : "not ");
1502 GO_DEBUG_RTX (xinsn);
1505 /* Check for constant before stripping off SUBREG, so that we don't
1506 accept (subreg (const_int)) which will fail to reload. */
1507 if (CONSTANT_ADDRESS_P (xinsn)
1508 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1509 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1512 while (GET_CODE (xinsn) == SUBREG)
1513 xinsn = SUBREG_REG (xinsn);
1515 /* The mips16 can only use the stack pointer as a base register when
1516 loading SImode or DImode values. */
1517 if (GET_CODE (xinsn) == REG
1518 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1521 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1523 register rtx xlow0 = XEXP (xinsn, 0);
1524 register rtx xlow1 = XEXP (xinsn, 1);
1526 while (GET_CODE (xlow0) == SUBREG)
1527 xlow0 = SUBREG_REG (xlow0);
1528 if (GET_CODE (xlow0) == REG
1529 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1530 && mips_check_split (xlow1, mode))
1534 if (GET_CODE (xinsn) == PLUS)
1536 register rtx xplus0 = XEXP (xinsn, 0);
1537 register rtx xplus1 = XEXP (xinsn, 1);
1538 register enum rtx_code code0;
1539 register enum rtx_code code1;
1541 while (GET_CODE (xplus0) == SUBREG)
1542 xplus0 = SUBREG_REG (xplus0);
1543 code0 = GET_CODE (xplus0);
1545 while (GET_CODE (xplus1) == SUBREG)
1546 xplus1 = SUBREG_REG (xplus1);
1547 code1 = GET_CODE (xplus1);
1549 /* The mips16 can only use the stack pointer as a base register
1550 when loading SImode or DImode values. */
1552 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1554 if (code1 == CONST_INT && SMALL_INT (xplus1))
1557 /* On the mips16, we represent GP relative offsets in RTL.
1558 These are 16 bit signed values, and can serve as register
1561 && mips16_gp_offset_p (xplus1))
1564 /* For some code sequences, you actually get better code by
1565 pretending that the MIPS supports an address mode of a
1566 constant address + a register, even though the real
1567 machine doesn't support it. This is because the
1568 assembler can use $r1 to load just the high 16 bits, add
1569 in the register, and fold the low 16 bits into the memory
1570 reference, whereas the compiler generates a 4 instruction
1571 sequence. On the other hand, CSE is not as effective.
1572 It would be a win to generate the lui directly, but the
1573 MIPS assembler does not have syntax to generate the
1574 appropriate relocation. */
1576 /* Also accept CONST_INT addresses here, so no else. */
1577 /* Reject combining an embedded PIC text segment reference
1578 with a register. That requires an additional
1580 /* ??? Reject combining an address with a register for the MIPS
1581 64 bit ABI, because the SGI assembler can not handle this. */
1582 if (!TARGET_DEBUG_A_MODE
1583 && (mips_abi == ABI_32
1584 || mips_abi == ABI_O64
1585 || mips_abi == ABI_EABI)
1586 && CONSTANT_ADDRESS_P (xplus1)
1587 && ! mips_split_addresses
1588 && (!TARGET_EMBEDDED_PIC
1590 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1591 /* When assembling for machines with 64 bit registers,
1592 the assembler will sign-extend the constant "foo"
1593 in "la x, foo(x)" yielding the wrong result for:
1594 (set (blah:DI) (plus x y)). */
1596 || (code1 == CONST_INT
1597 && trunc_int_for_mode (INTVAL (xplus1),
1598 SImode) == INTVAL (xplus1)))
1604 if (TARGET_DEBUG_B_MODE)
1605 GO_PRINTF ("Not a legitimate address\n");
1607 /* The address was not legitimate. */
1612 /* We need a lot of little routines to check constant values on the
1613 mips16. These are used to figure out how long the instruction will
1614 be. It would be much better to do this using constraints, but
1615 there aren't nearly enough letters available. */
1618 m16_check_op (op, low, high, mask)
1624 return (GET_CODE (op) == CONST_INT
1625 && INTVAL (op) >= low
1626 && INTVAL (op) <= high
1627 && (INTVAL (op) & mask) == 0);
1631 m16_uimm3_b (op, mode)
1633 enum machine_mode mode ATTRIBUTE_UNUSED;
1635 return m16_check_op (op, 0x1, 0x8, 0);
1639 m16_simm4_1 (op, mode)
1641 enum machine_mode mode ATTRIBUTE_UNUSED;
1643 return m16_check_op (op, - 0x8, 0x7, 0);
1647 m16_nsimm4_1 (op, mode)
1649 enum machine_mode mode ATTRIBUTE_UNUSED;
1651 return m16_check_op (op, - 0x7, 0x8, 0);
1655 m16_simm5_1 (op, mode)
1657 enum machine_mode mode ATTRIBUTE_UNUSED;
1659 return m16_check_op (op, - 0x10, 0xf, 0);
1663 m16_nsimm5_1 (op, mode)
1665 enum machine_mode mode ATTRIBUTE_UNUSED;
1667 return m16_check_op (op, - 0xf, 0x10, 0);
1671 m16_uimm5_4 (op, mode)
1673 enum machine_mode mode ATTRIBUTE_UNUSED;
1675 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1679 m16_nuimm5_4 (op, mode)
1681 enum machine_mode mode ATTRIBUTE_UNUSED;
1683 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1687 m16_simm8_1 (op, mode)
1689 enum machine_mode mode ATTRIBUTE_UNUSED;
1691 return m16_check_op (op, - 0x80, 0x7f, 0);
1695 m16_nsimm8_1 (op, mode)
1697 enum machine_mode mode ATTRIBUTE_UNUSED;
1699 return m16_check_op (op, - 0x7f, 0x80, 0);
1703 m16_uimm8_1 (op, mode)
1705 enum machine_mode mode ATTRIBUTE_UNUSED;
1707 return m16_check_op (op, 0x0, 0xff, 0);
1711 m16_nuimm8_1 (op, mode)
1713 enum machine_mode mode ATTRIBUTE_UNUSED;
1715 return m16_check_op (op, - 0xff, 0x0, 0);
1719 m16_uimm8_m1_1 (op, mode)
1721 enum machine_mode mode ATTRIBUTE_UNUSED;
1723 return m16_check_op (op, - 0x1, 0xfe, 0);
1727 m16_uimm8_4 (op, mode)
1729 enum machine_mode mode ATTRIBUTE_UNUSED;
1731 return m16_check_op (op, 0x0, 0xff << 2, 3);
1735 m16_nuimm8_4 (op, mode)
1737 enum machine_mode mode ATTRIBUTE_UNUSED;
1739 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1743 m16_simm8_8 (op, mode)
1745 enum machine_mode mode ATTRIBUTE_UNUSED;
1747 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1751 m16_nsimm8_8 (op, mode)
1753 enum machine_mode mode ATTRIBUTE_UNUSED;
1755 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1758 /* References to the string table on the mips16 only use a small
1759 offset if the function is small. See the comment in the SYMBOL_REF
1760 case in simple_memory_operand. We can't check for LABEL_REF here,
1761 because the offset is always large if the label is before the
1762 referencing instruction. */
1765 m16_usym8_4 (op, mode)
1767 enum machine_mode mode ATTRIBUTE_UNUSED;
1769 if (GET_CODE (op) == SYMBOL_REF
1770 && SYMBOL_REF_FLAG (op)
1771 && cfun->machine->insns_len > 0
1772 && XSTR (op, 0)[0] == '*'
1773 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1774 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1775 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
1778 struct string_constant *l;
1780 /* Make sure this symbol is on thelist of string constants to be
1781 output for this function. It is possible that it has already
1782 been output, in which case this requires a large offset. */
1783 for (l = string_constants; l != NULL; l = l->next)
1784 if (strcmp (l->label, XSTR (op, 0)) == 0)
1792 m16_usym5_4 (op, mode)
1794 enum machine_mode mode ATTRIBUTE_UNUSED;
1796 if (GET_CODE (op) == SYMBOL_REF
1797 && SYMBOL_REF_FLAG (op)
1798 && cfun->machine->insns_len > 0
1799 && XSTR (op, 0)[0] == '*'
1800 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1801 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1802 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
1805 struct string_constant *l;
1807 /* Make sure this symbol is on thelist of string constants to be
1808 output for this function. It is possible that it has already
1809 been output, in which case this requires a large offset. */
1810 for (l = string_constants; l != NULL; l = l->next)
1811 if (strcmp (l->label, XSTR (op, 0)) == 0)
1818 /* Returns an operand string for the given instruction's delay slot,
1819 after updating filled delay slot statistics.
1821 We assume that operands[0] is the target register that is set.
1823 In order to check the next insn, most of this functionality is moved
1824 to FINAL_PRESCAN_INSN, and we just set the global variables that
1827 /* ??? This function no longer does anything useful, because final_prescan_insn
1828 now will never emit a nop. */
1831 mips_fill_delay_slot (ret, type, operands, cur_insn)
1832 const char *ret; /* normal string to return */
1833 enum delay_type type; /* type of delay */
1834 rtx operands[]; /* operands to use */
1835 rtx cur_insn; /* current insn */
1837 register rtx set_reg;
1838 register enum machine_mode mode;
1839 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1840 register int num_nops;
1842 if (type == DELAY_LOAD || type == DELAY_FCMP)
1845 else if (type == DELAY_HILO)
1851 /* Make sure that we don't put nop's after labels. */
1852 next_insn = NEXT_INSN (cur_insn);
1853 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1854 next_insn = NEXT_INSN (next_insn);
1856 dslots_load_total += num_nops;
1857 if (TARGET_DEBUG_F_MODE
1859 || type == DELAY_NONE
1863 || GET_CODE (next_insn) == CODE_LABEL
1864 || (set_reg = operands[0]) == 0)
1866 dslots_number_nops = 0;
1874 set_reg = operands[0];
1878 while (GET_CODE (set_reg) == SUBREG)
1879 set_reg = SUBREG_REG (set_reg);
1881 mode = GET_MODE (set_reg);
1882 dslots_number_nops = num_nops;
1883 mips_load_reg = set_reg;
1884 if (GET_MODE_SIZE (mode)
1885 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1886 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1890 if (type == DELAY_HILO)
1892 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1893 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1905 /* Determine whether a memory reference takes one (based off of the GP
1906 pointer), two (normal), or three (label + reg) instructions, and bump the
1907 appropriate counter for -mstats. */
1910 mips_count_memory_refs (op, num)
1916 rtx addr, plus0, plus1;
1917 enum rtx_code code0, code1;
1920 if (TARGET_DEBUG_B_MODE)
1922 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1926 /* Skip MEM if passed, otherwise handle movsi of address. */
1927 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1929 /* Loop, going through the address RTL. */
1933 switch (GET_CODE (addr))
1941 plus0 = XEXP (addr, 0);
1942 plus1 = XEXP (addr, 1);
1943 code0 = GET_CODE (plus0);
1944 code1 = GET_CODE (plus1);
1954 if (code0 == CONST_INT)
1969 if (code1 == CONST_INT)
1976 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1983 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1993 n_words = 2; /* always 2 words */
1997 addr = XEXP (addr, 0);
2002 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
2014 n_words += additional;
2018 num_refs[n_words-1] += num;
2022 /* Return a pseudo that points to the address of the current function.
2023 The first time it is called for a function, an initializer for the
2024 pseudo is emitted in the beginning of the function. */
2027 embedded_pic_fnaddr_reg ()
2029 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2033 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2035 /* Output code at function start to initialize the pseudo-reg. */
2036 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2037 inline functions, because it is called after RTL for the function
2038 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2039 does not get copied, and ends up not matching the rest of the RTL.
2040 This solution works, but means that we get unnecessary code to
2041 initialize this value every time a function is inlined into another
2044 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2045 XEXP (DECL_RTL (current_function_decl), 0)));
2048 push_topmost_sequence ();
2049 emit_insn_after (seq, get_insns ());
2050 pop_topmost_sequence ();
2053 return cfun->machine->embedded_pic_fnaddr_rtx;
2056 /* Return RTL for the offset from the current function to the argument.
2057 X is the symbol whose offset from the current function we want. */
2060 embedded_pic_offset (x)
2063 /* Make sure it is emitted. */
2064 embedded_pic_fnaddr_reg ();
2067 gen_rtx_CONST (Pmode,
2068 gen_rtx_MINUS (Pmode, x,
2069 XEXP (DECL_RTL (current_function_decl), 0)));
2072 /* Return the appropriate instructions to move one operand to another. */
2075 mips_move_1word (operands, insn, unsignedp)
2080 const char *ret = 0;
2081 rtx op0 = operands[0];
2082 rtx op1 = operands[1];
2083 enum rtx_code code0 = GET_CODE (op0);
2084 enum rtx_code code1 = GET_CODE (op1);
2085 enum machine_mode mode = GET_MODE (op0);
2086 int subreg_offset0 = 0;
2087 int subreg_offset1 = 0;
2088 enum delay_type delay = DELAY_NONE;
2090 while (code0 == SUBREG)
2092 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2093 GET_MODE (SUBREG_REG (op0)),
2096 op0 = SUBREG_REG (op0);
2097 code0 = GET_CODE (op0);
2100 while (code1 == SUBREG)
2102 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2103 GET_MODE (SUBREG_REG (op1)),
2106 op1 = SUBREG_REG (op1);
2107 code1 = GET_CODE (op1);
2110 /* For our purposes, a condition code mode is the same as SImode. */
2116 int regno0 = REGNO (op0) + subreg_offset0;
2120 int regno1 = REGNO (op1) + subreg_offset1;
2122 /* Just in case, don't do anything for assigning a register
2123 to itself, unless we are filling a delay slot. */
2124 if (regno0 == regno1 && set_nomacro == 0)
2127 else if (GP_REG_P (regno0))
2129 if (GP_REG_P (regno1))
2130 ret = "move\t%0,%1";
2132 else if (MD_REG_P (regno1))
2135 if (regno1 != HILO_REGNUM)
2141 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
2142 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
2147 if (FP_REG_P (regno1))
2148 ret = "mfc1\t%0,%1";
2149 else if (ALL_COP_REG_P (regno1))
2151 static char retval[] = "mfc_\t%0,%1";
2153 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2156 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
2157 ret = "cfc1\t%0,$31";
2161 else if (FP_REG_P (regno0))
2163 if (GP_REG_P (regno1))
2166 ret = "mtc1\t%1,%0";
2169 if (FP_REG_P (regno1))
2170 ret = "mov.s\t%0,%1";
2173 else if (MD_REG_P (regno0))
2175 if (GP_REG_P (regno1))
2178 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
2183 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
2185 if (GP_REG_P (regno1))
2188 ret = "ctc1\t%0,$31";
2191 else if (ALL_COP_REG_P (regno0))
2193 if (GP_REG_P (regno1))
2195 static char retval[] = "mtc_\t%1,%0";
2196 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2199 abort_with_insn (insn,
2200 "mtc0 not supported; it disturbs virtual address translation");
2208 else if (code1 == MEM)
2213 mips_count_memory_refs (op1, 1);
2215 if (GP_REG_P (regno0))
2217 /* For loads, use the mode of the memory item, instead of the
2218 target, so zero/sign extend can use this code as well. */
2219 switch (GET_MODE (op1))
2228 ret = ((unsignedp && TARGET_64BIT)
2233 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
2236 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
2241 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
2244 else if (ALL_COP_REG_P (regno0))
2246 static char retval[] = "lwc_\t%0,%1";
2247 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2250 abort_with_insn (insn,
2251 "loads from memory to COP0 are illegal");
2257 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2259 size_t i = strlen (ret);
2260 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2263 sprintf (volatile_buffer, "%%{%s%%}", ret);
2264 ret = volatile_buffer;
2268 else if (code1 == CONST_INT
2269 || (code1 == CONST_DOUBLE
2270 && GET_MODE (op1) == VOIDmode))
2272 if (code1 == CONST_DOUBLE)
2274 /* This can happen when storing constants into long long
2275 bitfields. Just store the least significant word of
2277 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2280 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2282 if (GP_REG_P (regno0))
2283 ret = "move\t%0,%z1";
2285 else if (FP_REG_P (regno0))
2288 ret = "mtc1\t%z1,%0";
2291 else if (MD_REG_P (regno0))
2298 else if (GP_REG_P (regno0))
2300 /* Don't use X format, because that will give out of
2301 range numbers for 64 bit host and 32 bit target. */
2302 if (! TARGET_MIPS16)
2303 ret = "li\t%0,%1\t\t\t# %X1";
2306 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2308 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2309 ret = "li\t%0,%n1\n\tneg\t%0";
2314 else if (code1 == CONST_DOUBLE && mode == SFmode)
2316 if (op1 == CONST0_RTX (SFmode))
2318 if (GP_REG_P (regno0))
2319 ret = "move\t%0,%.";
2321 else if (FP_REG_P (regno0))
2324 ret = "mtc1\t%.,%0";
2331 ret = "li.s\t%0,%1";
2335 else if (code1 == LABEL_REF)
2338 mips_count_memory_refs (op1, 1);
2343 else if (code1 == SYMBOL_REF || code1 == CONST)
2347 && GET_CODE (XEXP (op1, 0)) == REG
2348 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2350 /* This case arises on the mips16; see
2351 mips16_gp_pseudo_reg. */
2352 ret = "move\t%0,%+";
2354 else if (TARGET_MIPS16
2355 && code1 == SYMBOL_REF
2356 && SYMBOL_REF_FLAG (op1)
2357 && (XSTR (op1, 0)[0] != '*'
2358 || strncmp (XSTR (op1, 0) + 1,
2360 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2362 /* This can occur when reloading the address of a GP
2363 relative symbol on the mips16. */
2364 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2369 mips_count_memory_refs (op1, 1);
2375 else if (code1 == PLUS)
2377 rtx add_op0 = XEXP (op1, 0);
2378 rtx add_op1 = XEXP (op1, 1);
2380 if (GET_CODE (XEXP (op1, 1)) == REG
2381 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2382 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2384 operands[2] = add_op0;
2385 operands[3] = add_op1;
2386 ret = "add%:\t%0,%2,%3";
2389 else if (code1 == HIGH)
2391 operands[1] = XEXP (op1, 0);
2392 ret = "lui\t%0,%%hi(%1)";
2396 else if (code0 == MEM)
2399 mips_count_memory_refs (op0, 1);
2403 int regno1 = REGNO (op1) + subreg_offset1;
2405 if (GP_REG_P (regno1))
2409 case SFmode: ret = "sw\t%1,%0"; break;
2410 case SImode: ret = "sw\t%1,%0"; break;
2411 case HImode: ret = "sh\t%1,%0"; break;
2412 case QImode: ret = "sb\t%1,%0"; break;
2417 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2419 else if (ALL_COP_REG_P (regno1))
2421 static char retval[] = "swc_\t%1,%0";
2423 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2428 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2432 case SFmode: ret = "sw\t%z1,%0"; break;
2433 case SImode: ret = "sw\t%z1,%0"; break;
2434 case HImode: ret = "sh\t%z1,%0"; break;
2435 case QImode: ret = "sb\t%z1,%0"; break;
2440 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2444 case SFmode: ret = "sw\t%.,%0"; break;
2445 case SImode: ret = "sw\t%.,%0"; break;
2446 case HImode: ret = "sh\t%.,%0"; break;
2447 case QImode: ret = "sb\t%.,%0"; break;
2452 if (ret != 0 && MEM_VOLATILE_P (op0))
2454 size_t i = strlen (ret);
2456 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2459 sprintf (volatile_buffer, "%%{%s%%}", ret);
2460 ret = volatile_buffer;
2466 abort_with_insn (insn, "bad move");
2470 if (delay != DELAY_NONE)
2471 return mips_fill_delay_slot (ret, delay, operands, insn);
2476 /* Return instructions to restore the global pointer from the stack,
2477 assuming TARGET_ABICALLS. Used by exception_receiver to set up
2478 the GP for exception handlers.
2480 OPERANDS is an array of operands whose contents are undefined
2481 on entry. INSN is the exception_handler instruction. */
2484 mips_restore_gp (operands, insn)
2485 rtx *operands, insn;
2489 operands[0] = pic_offset_table_rtx;
2490 if (frame_pointer_needed)
2491 loc = hard_frame_pointer_rtx;
2493 loc = stack_pointer_rtx;
2494 loc = plus_constant (loc, cfun->machine->frame.args_size);
2495 operands[1] = gen_rtx_MEM (Pmode, loc);
2497 return mips_move_1word (operands, insn, 0);
2500 /* Return an instruction to sign-extend SImode value SRC and store it
2501 in DImode value DEST. INSN is the original extendsidi2-type insn. */
2504 mips_sign_extend (insn, dest, src)
2505 rtx insn, dest, src;
2507 rtx operands[MAX_RECOG_OPERANDS];
2509 if ((register_operand (src, SImode) && FP_REG_P (true_regnum (src)))
2510 || memory_operand (src, SImode))
2512 /* If the source is a floating-point register, we need to use a
2513 32-bit move, since the float register is not kept sign-extended.
2514 If the source is in memory, we need a 32-bit load. */
2515 operands[0] = gen_lowpart_SUBREG (SImode, dest);
2517 return mips_move_1word (operands, insn, false);
2523 return mips_move_2words (operands, insn);
2527 /* Return the appropriate instructions to move 2 words */
2530 mips_move_2words (operands, insn)
2534 const char *ret = 0;
2535 rtx op0 = operands[0];
2536 rtx op1 = operands[1];
2537 enum rtx_code code0 = GET_CODE (operands[0]);
2538 enum rtx_code code1 = GET_CODE (operands[1]);
2539 int subreg_offset0 = 0;
2540 int subreg_offset1 = 0;
2541 enum delay_type delay = DELAY_NONE;
2543 if (code1 == SIGN_EXTEND)
2544 return mips_sign_extend (insn, op0, XEXP (op1, 0));
2546 while (code0 == SUBREG)
2548 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2549 GET_MODE (SUBREG_REG (op0)),
2552 op0 = SUBREG_REG (op0);
2553 code0 = GET_CODE (op0);
2556 while (code1 == SUBREG)
2558 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2559 GET_MODE (SUBREG_REG (op1)),
2562 op1 = SUBREG_REG (op1);
2563 code1 = GET_CODE (op1);
2568 int regno0 = REGNO (op0) + subreg_offset0;
2572 int regno1 = REGNO (op1) + subreg_offset1;
2574 /* Just in case, don't do anything for assigning a register
2575 to itself, unless we are filling a delay slot. */
2576 if (regno0 == regno1 && set_nomacro == 0)
2579 else if (FP_REG_P (regno0))
2581 if (FP_REG_P (regno1))
2582 ret = "mov.d\t%0,%1";
2590 abort_with_insn (insn, "bad move");
2592 #ifdef TARGET_FP_CALL_32
2593 if (FP_CALL_GP_REG_P (regno1))
2594 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2597 ret = "dmtc1\t%1,%0";
2600 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2604 else if (FP_REG_P (regno1))
2610 abort_with_insn (insn, "bad move");
2612 #ifdef TARGET_FP_CALL_32
2613 if (FP_CALL_GP_REG_P (regno0))
2614 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2617 ret = "dmfc1\t%0,%1";
2620 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2623 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2628 if (regno0 != HILO_REGNUM)
2630 else if (regno1 == 0)
2631 ret = "mtlo\t%.\n\tmthi\t%.";
2634 ret = "mthi\t%M1\n\tmtlo\t%L1";
2637 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2642 if (regno1 != HILO_REGNUM)
2646 ret = "mfhi\t%M0\n\tmflo\t%L0";
2648 else if (GP_REG_P (regno0) && ALL_COP_REG_P (regno1)
2651 static char retval[] = "dmfc_\t%0,%1";
2654 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2657 else if (ALL_COP_REG_P (regno0) && GP_REG_P (regno1)
2660 static char retval[] = "dmtc_\t%1,%0";
2661 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2664 abort_with_insn (insn,
2665 "dmtc0 not supported; it disturbs virtual address translation");
2670 else if (TARGET_64BIT)
2671 ret = "move\t%0,%1";
2673 else if (regno0 != (regno1+1))
2674 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2677 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2680 else if (code1 == CONST_DOUBLE)
2682 /* Move zero from $0 unless !TARGET_64BIT and recipient
2683 is 64-bit fp reg, in which case generate a constant. */
2684 if (op1 != CONST0_RTX (GET_MODE (op1))
2685 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2687 if (GET_MODE (op1) == DFmode)
2691 #ifdef TARGET_FP_CALL_32
2692 if (FP_CALL_GP_REG_P (regno0))
2694 if (TARGET_FLOAT64 && !TARGET_64BIT)
2696 split_double (op1, operands + 2, operands + 3);
2697 ret = "li\t%0,%2\n\tli\t%D0,%3";
2700 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2704 /* GNU as emits 64-bit code for li.d if the ISA is 3
2705 or higher. For !TARGET_64BIT && gp registers we
2706 need to avoid this by using two li instructions
2708 if (ISA_HAS_64BIT_REGS
2710 && ! FP_REG_P (regno0))
2712 split_double (op1, operands + 2, operands + 3);
2713 ret = "li\t%0,%2\n\tli\t%D0,%3";
2716 ret = "li.d\t%0,%1";
2719 else if (TARGET_64BIT)
2721 if (! TARGET_MIPS16)
2727 split_double (op1, operands + 2, operands + 3);
2728 ret = "li\t%0,%2\n\tli\t%D0,%3";
2734 if (GP_REG_P (regno0))
2736 #ifdef TARGET_FP_CALL_32
2737 && ! FP_CALL_GP_REG_P (regno0)
2740 : "move\t%0,%.\n\tmove\t%D0,%.");
2742 else if (FP_REG_P (regno0))
2747 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2752 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2754 if (GP_REG_P (regno0))
2757 : "move\t%0,%.\n\tmove\t%D0,%.");
2759 else if (FP_REG_P (regno0))
2766 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2768 else if (MD_REG_P (regno0))
2771 ret = (regno0 == HILO_REGNUM
2772 ? "mtlo\t%.\n\tmthi\t%."
2777 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2778 && GP_REG_P (regno0))
2784 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2786 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2787 ret = "li\t%0,%n1\n\tneg\t%0";
2789 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2790 ret = "li\t%0,%1\t\t# %X1";
2791 else if (HOST_BITS_PER_WIDE_INT < 64)
2792 /* We can't use 'X' for negative numbers, because then we won't
2793 get the right value for the upper 32 bits. */
2794 ret = (INTVAL (op1) < 0
2795 ? "dli\t%0,%1\t\t\t# %X1"
2796 : "dli\t%0,%X1\t\t# %1");
2798 /* We must use 'X', because otherwise LONG_MIN will print as
2799 a number that the assembler won't accept. */
2800 ret = "dli\t%0,%X1\t\t# %1";
2802 else if (HOST_BITS_PER_WIDE_INT < 64)
2804 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2807 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2808 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2809 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2811 operands[2] = GEN_INT (1);
2812 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2816 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2820 /* We use multiple shifts here, to avoid warnings about out
2821 of range shifts on 32 bit hosts. */
2822 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2824 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2827 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2828 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2829 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2831 operands[2] = GEN_INT (1);
2832 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2836 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2840 else if (code1 == MEM)
2845 mips_count_memory_refs (op1, 2);
2847 if (FP_REG_P (regno0))
2850 else if (ALL_COP_REG_P (regno0) && TARGET_64BIT)
2852 static char retval[] = "ldc_\t%0,%1";
2853 char cop = COPNUM_AS_CHAR_FROM_REGNUM (regno0);
2856 abort_with_insn (insn,
2857 "loads from memory to COP0 are illegal");
2863 else if (TARGET_64BIT)
2866 #ifdef TARGET_FP_CALL_32
2867 if (FP_CALL_GP_REG_P (regno0))
2868 ret = (double_memory_operand (op1, GET_MODE (op1))
2869 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2870 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2876 else if (double_memory_operand (op1, GET_MODE (op1)))
2877 ret = (reg_mentioned_p (op0, op1)
2878 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2879 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2881 if (ret != 0 && MEM_VOLATILE_P (op1))
2883 size_t i = strlen (ret);
2885 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2888 sprintf (volatile_buffer, "%%{%s%%}", ret);
2889 ret = volatile_buffer;
2893 else if (code1 == LABEL_REF)
2896 mips_count_memory_refs (op1, 2);
2898 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2899 /* We deliberately remove the 'a' from '%1', so that we don't
2900 have to add SIGN_EXTEND support to print_operand_address.
2901 print_operand will just call print_operand_address in this
2902 case, so there is no problem. */
2905 ret = "dla\t%0,%a1";
2907 else if (code1 == SYMBOL_REF || code1 == CONST)
2911 && GET_CODE (XEXP (op1, 0)) == REG
2912 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2914 /* This case arises on the mips16; see
2915 mips16_gp_pseudo_reg. */
2916 ret = "move\t%0,%+";
2918 else if (TARGET_MIPS16
2919 && code1 == SYMBOL_REF
2920 && SYMBOL_REF_FLAG (op1)
2921 && (XSTR (op1, 0)[0] != '*'
2922 || strncmp (XSTR (op1, 0) + 1,
2924 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2926 /* This can occur when reloading the address of a GP
2927 relative symbol on the mips16. */
2928 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2933 mips_count_memory_refs (op1, 2);
2935 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2936 /* We deliberately remove the 'a' from '%1', so that we don't
2937 have to add SIGN_EXTEND support to print_operand_address.
2938 print_operand will just call print_operand_address in this
2939 case, so there is no problem. */
2942 ret = "dla\t%0,%a1";
2947 else if (code0 == MEM)
2951 int regno1 = REGNO (op1) + subreg_offset1;
2953 if (FP_REG_P (regno1))
2956 else if (ALL_COP_REG_P (regno1) && TARGET_64BIT)
2958 static char retval[] = "sdc_\t%1,%0";
2960 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (regno1);
2963 else if (TARGET_64BIT)
2966 #ifdef TARGET_FP_CALL_32
2967 if (FP_CALL_GP_REG_P (regno1))
2968 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2974 else if (double_memory_operand (op0, GET_MODE (op0)))
2975 ret = "sw\t%1,%0\n\tsw\t%D1,%D0";
2978 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2979 || (code1 == CONST_DOUBLE
2980 && op1 == CONST0_RTX (GET_MODE (op1))))
2982 || double_memory_operand (op0, GET_MODE (op0))))
2987 ret = "sw\t%.,%0\n\tsw\t%.,%D0";
2991 mips_count_memory_refs (op0, 2);
2993 if (ret != 0 && MEM_VOLATILE_P (op0))
2995 size_t i = strlen (ret);
2997 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
3000 sprintf (volatile_buffer, "%%{%s%%}", ret);
3001 ret = volatile_buffer;
3007 abort_with_insn (insn, "bad move");
3011 if (delay != DELAY_NONE)
3012 return mips_fill_delay_slot (ret, delay, operands, insn);
3017 /* Provide the costs of an addressing mode that contains ADDR.
3018 If ADDR is not a valid address, its cost is irrelevant. */
3021 mips_address_cost (addr)
3024 switch (GET_CODE (addr))
3034 rtx offset = const0_rtx;
3035 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
3036 if (GET_CODE (addr) == LABEL_REF)
3039 if (GET_CODE (addr) != SYMBOL_REF)
3042 if (! SMALL_INT (offset))
3046 /* ... fall through ... */
3049 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
3053 register rtx plus0 = XEXP (addr, 0);
3054 register rtx plus1 = XEXP (addr, 1);
3056 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
3057 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
3059 if (GET_CODE (plus0) != REG)
3062 switch (GET_CODE (plus1))
3065 return SMALL_INT (plus1) ? 1 : 2;
3072 return mips_address_cost (plus1) + 1;
3086 /* Return nonzero if X is an address which needs a temporary register when
3087 reloaded while generating PIC code. */
3090 pic_address_needs_scratch (x)
3093 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3094 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3095 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3096 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3097 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3103 /* Make normal rtx_code into something we can index from an array */
3105 static enum internal_test
3106 map_test_to_internal_test (test_code)
3107 enum rtx_code test_code;
3109 enum internal_test test = ITEST_MAX;
3113 case EQ: test = ITEST_EQ; break;
3114 case NE: test = ITEST_NE; break;
3115 case GT: test = ITEST_GT; break;
3116 case GE: test = ITEST_GE; break;
3117 case LT: test = ITEST_LT; break;
3118 case LE: test = ITEST_LE; break;
3119 case GTU: test = ITEST_GTU; break;
3120 case GEU: test = ITEST_GEU; break;
3121 case LTU: test = ITEST_LTU; break;
3122 case LEU: test = ITEST_LEU; break;
3130 /* Generate the code to compare two integer values. The return value is:
3131 (reg:SI xx) The pseudo register the comparison is in
3132 0 No register, generate a simple branch.
3134 ??? This is called with result nonzero by the Scond patterns in
3135 mips.md. These patterns are called with a target in the mode of
3136 the Scond instruction pattern. Since this must be a constant, we
3137 must use SImode. This means that if RESULT is non-zero, it will
3138 always be an SImode register, even if TARGET_64BIT is true. We
3139 cope with this by calling convert_move rather than emit_move_insn.
3140 This will sometimes lead to an unnecessary extension of the result;
3152 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
3153 enum rtx_code test_code; /* relational test (EQ, etc) */
3154 rtx result; /* result to store comp. or 0 if branch */
3155 rtx cmp0; /* first operand to compare */
3156 rtx cmp1; /* second operand to compare */
3157 int *p_invert; /* NULL or ptr to hold whether branch needs */
3158 /* to reverse its test */
3162 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
3163 int const_low; /* low bound of constant we can accept */
3164 int const_high; /* high bound of constant we can accept */
3165 int const_add; /* constant to add (convert LE -> LT) */
3166 int reverse_regs; /* reverse registers in test */
3167 int invert_const; /* != 0 if invert value if cmp1 is constant */
3168 int invert_reg; /* != 0 if invert value if cmp1 is register */
3169 int unsignedp; /* != 0 for unsigned comparisons. */
3172 static const struct cmp_info info[ (int)ITEST_MAX ] = {
3174 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
3175 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
3176 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
3177 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
3178 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
3179 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
3180 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
3181 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
3182 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
3183 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
3186 enum internal_test test;
3187 enum machine_mode mode;
3188 const struct cmp_info *p_info;
3195 test = map_test_to_internal_test (test_code);
3196 if (test == ITEST_MAX)
3199 p_info = &info[(int) test];
3200 eqne_p = (p_info->test_code == XOR);
3202 mode = GET_MODE (cmp0);
3203 if (mode == VOIDmode)
3204 mode = GET_MODE (cmp1);
3206 /* Eliminate simple branches */
3207 branch_p = (result == 0);
3210 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
3212 /* Comparisons against zero are simple branches */
3213 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
3214 && (! TARGET_MIPS16 || eqne_p))
3217 /* Test for beq/bne. */
3218 if (eqne_p && ! TARGET_MIPS16)
3222 /* allocate a pseudo to calculate the value in. */
3223 result = gen_reg_rtx (mode);
3226 /* Make sure we can handle any constants given to us. */
3227 if (GET_CODE (cmp0) == CONST_INT)
3228 cmp0 = force_reg (mode, cmp0);
3230 if (GET_CODE (cmp1) == CONST_INT)
3232 HOST_WIDE_INT value = INTVAL (cmp1);
3234 if (value < p_info->const_low
3235 || value > p_info->const_high
3236 /* ??? Why? And why wasn't the similar code below modified too? */
3238 && HOST_BITS_PER_WIDE_INT < 64
3239 && p_info->const_add != 0
3240 && ((p_info->unsignedp
3241 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
3242 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
3243 : (value + p_info->const_add) > INTVAL (cmp1))
3244 != (p_info->const_add > 0))))
3245 cmp1 = force_reg (mode, cmp1);
3248 /* See if we need to invert the result. */
3249 invert = (GET_CODE (cmp1) == CONST_INT
3250 ? p_info->invert_const : p_info->invert_reg);
3252 if (p_invert != (int *)0)
3258 /* Comparison to constants, may involve adding 1 to change a LT into LE.
3259 Comparison between two registers, may involve switching operands. */
3260 if (GET_CODE (cmp1) == CONST_INT)
3262 if (p_info->const_add != 0)
3264 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
3266 /* If modification of cmp1 caused overflow,
3267 we would get the wrong answer if we follow the usual path;
3268 thus, x > 0xffffffffU would turn into x > 0U. */
3269 if ((p_info->unsignedp
3270 ? (unsigned HOST_WIDE_INT) new >
3271 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
3272 : new > INTVAL (cmp1))
3273 != (p_info->const_add > 0))
3275 /* This test is always true, but if INVERT is true then
3276 the result of the test needs to be inverted so 0 should
3277 be returned instead. */
3278 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
3282 cmp1 = GEN_INT (new);
3286 else if (p_info->reverse_regs)
3293 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
3297 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
3298 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
3301 if (test == ITEST_NE)
3303 if (! TARGET_MIPS16)
3305 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
3306 if (p_invert != NULL)
3312 reg2 = invert ? gen_reg_rtx (mode) : result;
3313 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3318 else if (test == ITEST_EQ)
3320 reg2 = invert ? gen_reg_rtx (mode) : result;
3321 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3329 if (! TARGET_MIPS16)
3333 /* The value is in $24. Copy it to another register, so
3334 that reload doesn't think it needs to store the $24 and
3335 the input to the XOR in the same location. */
3336 reg2 = gen_reg_rtx (mode);
3337 emit_move_insn (reg2, reg);
3339 one = force_reg (mode, const1_rtx);
3341 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3347 /* Emit the common code for doing conditional branches.
3348 operand[0] is the label to jump to.
3349 The comparison operands are saved away by cmp{si,di,sf,df}. */
3352 gen_conditional_branch (operands, test_code)
3354 enum rtx_code test_code;
3356 enum cmp_type type = branch_type;
3357 rtx cmp0 = branch_cmp[0];
3358 rtx cmp1 = branch_cmp[1];
3359 enum machine_mode mode;
3368 mode = type == CMP_SI ? SImode : DImode;
3370 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3378 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3379 /* We don't want to build a comparison against a non-zero
3381 cmp1 = force_reg (mode, cmp1);
3388 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3390 reg = gen_reg_rtx (CCmode);
3392 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3393 0 in the instruction built below. The MIPS FPU handles
3394 inequality testing by testing for equality and looking for a
3396 emit_insn (gen_rtx_SET (VOIDmode, reg,
3397 gen_rtx (test_code == NE ? EQ : test_code,
3398 CCmode, cmp0, cmp1)));
3400 test_code = test_code == NE ? EQ : NE;
3408 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3411 /* Generate the branch. */
3413 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3422 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3423 gen_rtx_IF_THEN_ELSE (VOIDmode,
3424 gen_rtx (test_code, mode,
3429 /* Emit the common code for conditional moves. OPERANDS is the array
3430 of operands passed to the conditional move defined_expand. */
3433 gen_conditional_move (operands)
3436 rtx op0 = branch_cmp[0];
3437 rtx op1 = branch_cmp[1];
3438 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3439 enum rtx_code cmp_code = GET_CODE (operands[1]);
3440 enum rtx_code move_code = NE;
3441 enum machine_mode op_mode = GET_MODE (operands[0]);
3442 enum machine_mode cmp_mode;
3445 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3464 op0 = force_reg (mode, branch_cmp[1]);
3465 op1 = branch_cmp[0];
3469 op0 = force_reg (mode, branch_cmp[1]);
3470 op1 = branch_cmp[0];
3481 op0 = force_reg (mode, branch_cmp[1]);
3482 op1 = branch_cmp[0];
3486 op0 = force_reg (mode, branch_cmp[1]);
3487 op1 = branch_cmp[0];
3494 else if (cmp_code == NE)
3495 cmp_code = EQ, move_code = EQ;
3497 if (mode == SImode || mode == DImode)
3499 else if (mode == SFmode || mode == DFmode)
3504 cmp_reg = gen_reg_rtx (cmp_mode);
3505 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3506 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3508 emit_insn (gen_rtx_SET (op_mode, operands[0],
3509 gen_rtx_IF_THEN_ELSE (op_mode,
3510 gen_rtx (move_code, VOIDmode,
3512 CONST0_RTX (SImode)),
3513 operands[2], operands[3])));
3516 /* Emit the common code for conditional moves. OPERANDS is the array
3517 of operands passed to the conditional move defined_expand. */
3520 mips_gen_conditional_trap (operands)
3524 enum rtx_code cmp_code = GET_CODE (operands[0]);
3525 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3527 /* MIPS conditional trap machine instructions don't have GT or LE
3528 flavors, so we must invert the comparison and convert to LT and
3529 GE, respectively. */
3532 case GT: cmp_code = LT; break;
3533 case LE: cmp_code = GE; break;
3534 case GTU: cmp_code = LTU; break;
3535 case LEU: cmp_code = GEU; break;
3538 if (cmp_code == GET_CODE (operands[0]))
3540 op0 = force_reg (mode, branch_cmp[0]);
3541 op1 = branch_cmp[1];
3545 op0 = force_reg (mode, branch_cmp[1]);
3546 op1 = branch_cmp[0];
3548 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3549 op1 = force_reg (mode, op1);
3551 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3552 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3556 /* Emit code to change the current function's return address to
3557 ADDRESS. SCRATCH is available as a scratch register, if needed.
3558 ADDRESS and SCRATCH are both word-mode GPRs. */
3561 mips_set_return_address (address, scratch)
3562 rtx address, scratch;
3564 HOST_WIDE_INT gp_offset;
3566 compute_frame_size (get_frame_size ());
3567 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3569 gp_offset = cfun->machine->frame.gp_sp_offset;
3571 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3572 if (gp_offset < 32768)
3573 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3576 emit_move_insn (scratch, GEN_INT (gp_offset));
3577 if (Pmode == DImode)
3578 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3580 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3583 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3586 /* Write a loop to move a constant number of bytes.
3587 Generate load/stores as follows:
3593 temp<last> = src[MAX_MOVE_REGS-1];
3597 dest[MAX_MOVE_REGS-1] = temp<last>;
3598 src += MAX_MOVE_REGS;
3599 dest += MAX_MOVE_REGS;
3600 } while (src != final);
3602 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3603 registers are needed.
3605 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3606 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3607 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3609 #define MAX_MOVE_REGS 4
3610 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3613 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3614 rtx dest_reg; /* register holding destination address */
3615 rtx src_reg; /* register holding source address */
3616 unsigned int bytes; /* # bytes to move */
3617 int align; /* alignment */
3618 rtx orig_dest; /* original dest */
3619 rtx orig_src; /* original source for making a reg note */
3621 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3622 rtx src_mem = replace_equiv_address (orig_src, src_reg);
3623 rtx align_rtx = GEN_INT (align);
3629 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3632 leftover = bytes % MAX_MOVE_BYTES;
3635 label = gen_label_rtx ();
3636 final_src = gen_reg_rtx (Pmode);
3637 bytes_rtx = GEN_INT (bytes);
3641 if (Pmode == DImode)
3643 emit_insn (gen_movdi (final_src, bytes_rtx));
3644 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3648 emit_insn (gen_movsi (final_src, bytes_rtx));
3649 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3654 if (Pmode == DImode)
3655 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3657 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3662 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3663 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3665 if (Pmode == DImode)
3667 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3668 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3669 emit_insn (gen_cmpdi (src_reg, final_src));
3673 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3674 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3675 emit_insn (gen_cmpsi (src_reg, final_src));
3678 emit_jump_insn (gen_bne (label));
3681 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3685 /* Use a library function to move some bytes. */
3688 block_move_call (dest_reg, src_reg, bytes_rtx)
3693 /* We want to pass the size as Pmode, which will normally be SImode
3694 but will be DImode if we are using 64 bit longs and pointers. */
3695 if (GET_MODE (bytes_rtx) != VOIDmode
3696 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3697 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3699 #ifdef TARGET_MEM_FUNCTIONS
3700 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3701 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3702 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3703 TREE_UNSIGNED (sizetype)),
3704 TYPE_MODE (sizetype));
3706 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3707 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3708 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3709 TREE_UNSIGNED (integer_type_node)),
3710 TYPE_MODE (integer_type_node));
3714 /* Expand string/block move operations.
3716 operands[0] is the pointer to the destination.
3717 operands[1] is the pointer to the source.
3718 operands[2] is the number of bytes to move.
3719 operands[3] is the alignment. */
3722 expand_block_move (operands)
3725 rtx bytes_rtx = operands[2];
3726 rtx align_rtx = operands[3];
3727 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3728 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3729 unsigned int align = INTVAL (align_rtx);
3730 rtx orig_src = operands[1];
3731 rtx orig_dest = operands[0];
3735 if (constp && bytes == 0)
3738 if (align > (unsigned) UNITS_PER_WORD)
3739 align = UNITS_PER_WORD;
3741 /* Move the address into scratch registers. */
3742 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3743 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3746 block_move_call (dest_reg, src_reg, bytes_rtx);
3748 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3749 && align == (unsigned) UNITS_PER_WORD)
3750 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3752 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3753 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3755 replace_equiv_address (orig_src,
3757 bytes_rtx, align_rtx));
3759 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3760 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3762 else if (constp && optimize)
3764 /* If the alignment is not word aligned, generate a test at
3765 runtime, to see whether things wound up aligned, and we
3766 can use the faster lw/sw instead ulw/usw. */
3768 rtx temp = gen_reg_rtx (Pmode);
3769 rtx aligned_label = gen_label_rtx ();
3770 rtx join_label = gen_label_rtx ();
3771 int leftover = bytes % MAX_MOVE_BYTES;
3775 if (Pmode == DImode)
3777 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3778 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3779 emit_insn (gen_cmpdi (temp, const0_rtx));
3783 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3784 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3785 emit_insn (gen_cmpsi (temp, const0_rtx));
3788 emit_jump_insn (gen_beq (aligned_label));
3790 /* Unaligned loop. */
3791 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3792 emit_jump_insn (gen_jump (join_label));
3796 emit_label (aligned_label);
3797 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3799 emit_label (join_label);
3801 /* Bytes at the end of the loop. */
3803 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3805 replace_equiv_address (orig_src,
3812 block_move_call (dest_reg, src_reg, bytes_rtx);
3815 /* Emit load/stores for a small constant block_move.
3817 operands[0] is the memory address of the destination.
3818 operands[1] is the memory address of the source.
3819 operands[2] is the number of bytes to move.
3820 operands[3] is the alignment.
3821 operands[4] is a temp register.
3822 operands[5] is a temp register.
3824 operands[3+num_regs] is the last temp register.
3826 The block move type can be one of the following:
3827 BLOCK_MOVE_NORMAL Do all of the block move.
3828 BLOCK_MOVE_NOT_LAST Do all but the last store.
3829 BLOCK_MOVE_LAST Do just the last store. */
3832 output_block_move (insn, operands, num_regs, move_type)
3836 enum block_move_type move_type;
3838 rtx dest_reg = XEXP (operands[0], 0);
3839 rtx src_reg = XEXP (operands[1], 0);
3840 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3841 int align = INTVAL (operands[3]);
3844 int use_lwl_lwr = 0;
3845 int last_operand = num_regs + 4;
3851 const char *load; /* load insn without nop */
3852 const char *load_nop; /* load insn with trailing nop */
3853 const char *store; /* store insn */
3854 const char *final; /* if last_store used: NULL or swr */
3855 const char *last_store; /* last store instruction */
3856 int offset; /* current offset */
3857 enum machine_mode mode; /* mode to use on (MEM) */
3860 /* ??? Detect a bug in GCC, where it can give us a register
3861 the same as one of the addressing registers and reduce
3862 the number of registers available. */
3863 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3864 if (! reg_mentioned_p (operands[i], operands[0])
3865 && ! reg_mentioned_p (operands[i], operands[1]))
3866 xoperands[safe_regs++] = operands[i];
3868 if (safe_regs < last_operand)
3870 xoperands[0] = operands[0];
3871 xoperands[1] = operands[1];
3872 xoperands[2] = operands[2];
3873 xoperands[3] = operands[3];
3874 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3877 /* If we are given global or static addresses, and we would be
3878 emitting a few instructions, try to save time by using a
3879 temporary register for the pointer. */
3880 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3881 an ldl/ldr instruction pair. We play it safe, and always move
3882 constant addresses into registers when generating N32/N64 code, just
3883 in case we might emit an unaligned load instruction. */
3884 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3885 || mips_abi == ABI_MEABI
3886 || mips_abi == ABI_N32
3887 || mips_abi == ABI_64))
3889 if (CONSTANT_P (src_reg))
3892 mips_count_memory_refs (operands[1], 1);
3894 src_reg = operands[3 + num_regs--];
3895 if (move_type != BLOCK_MOVE_LAST)
3897 xoperands[1] = operands[1];
3898 xoperands[0] = src_reg;
3899 if (Pmode == DImode)
3900 output_asm_insn ("dla\t%0,%1", xoperands);
3902 output_asm_insn ("la\t%0,%1", xoperands);
3906 if (CONSTANT_P (dest_reg))
3909 mips_count_memory_refs (operands[0], 1);
3911 dest_reg = operands[3 + num_regs--];
3912 if (move_type != BLOCK_MOVE_LAST)
3914 xoperands[1] = operands[0];
3915 xoperands[0] = dest_reg;
3916 if (Pmode == DImode)
3917 output_asm_insn ("dla\t%0,%1", xoperands);
3919 output_asm_insn ("la\t%0,%1", xoperands);
3924 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3925 are not offsettable, however, offsettable_address_p says they are
3926 offsettable. I think this is a bug in offsettable_address_p.
3927 For expediency, we fix this by just loading the address into a register
3928 if we happen to get one. */
3930 if (GET_CODE (src_reg) == LO_SUM)
3932 src_reg = operands[3 + num_regs--];
3933 if (move_type != BLOCK_MOVE_LAST)
3935 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3936 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3937 xoperands[0] = src_reg;
3938 if (Pmode == DImode)
3939 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3941 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3945 if (GET_CODE (dest_reg) == LO_SUM)
3947 dest_reg = operands[3 + num_regs--];
3948 if (move_type != BLOCK_MOVE_LAST)
3950 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3951 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3952 xoperands[0] = dest_reg;
3953 if (Pmode == DImode)
3954 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3956 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3960 if (num_regs > (int) ARRAY_SIZE (load_store))
3961 num_regs = ARRAY_SIZE (load_store);
3963 else if (num_regs < 1)
3964 abort_with_insn (insn,
3965 "cannot do block move, not enough scratch registers");
3969 load_store[num].offset = offset;
3971 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3973 load_store[num].load = "ld\t%0,%1";
3974 load_store[num].load_nop = "ld\t%0,%1%#";
3975 load_store[num].store = "sd\t%0,%1";
3976 load_store[num].last_store = "sd\t%0,%1";
3977 load_store[num].final = 0;
3978 load_store[num].mode = DImode;
3983 /* ??? Fails because of a MIPS assembler bug? */
3984 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3986 if (BYTES_BIG_ENDIAN)
3988 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3989 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3990 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3991 load_store[num].last_store = "sdr\t%0,%2";
3992 load_store[num].final = "sdl\t%0,%1";
3996 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3997 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3998 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3999 load_store[num].last_store = "sdr\t%0,%1";
4000 load_store[num].final = "sdl\t%0,%2";
4003 load_store[num].mode = DImode;
4009 else if (bytes >= 4 && align >= 4)
4011 load_store[num].load = "lw\t%0,%1";
4012 load_store[num].load_nop = "lw\t%0,%1%#";
4013 load_store[num].store = "sw\t%0,%1";
4014 load_store[num].last_store = "sw\t%0,%1";
4015 load_store[num].final = 0;
4016 load_store[num].mode = SImode;
4021 else if (bytes >= 4 && ! TARGET_MIPS16)
4023 if (BYTES_BIG_ENDIAN)
4025 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
4026 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
4027 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
4028 load_store[num].last_store = "swr\t%0,%2";
4029 load_store[num].final = "swl\t%0,%1";
4033 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
4034 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
4035 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
4036 load_store[num].last_store = "swr\t%0,%1";
4037 load_store[num].final = "swl\t%0,%2";
4040 load_store[num].mode = SImode;
4046 else if (bytes >= 2 && align >= 2)
4048 load_store[num].load = "lh\t%0,%1";
4049 load_store[num].load_nop = "lh\t%0,%1%#";
4050 load_store[num].store = "sh\t%0,%1";
4051 load_store[num].last_store = "sh\t%0,%1";
4052 load_store[num].final = 0;
4053 load_store[num].mode = HImode;
4059 load_store[num].load = "lb\t%0,%1";
4060 load_store[num].load_nop = "lb\t%0,%1%#";
4061 load_store[num].store = "sb\t%0,%1";
4062 load_store[num].last_store = "sb\t%0,%1";
4063 load_store[num].final = 0;
4064 load_store[num].mode = QImode;
4069 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4071 dslots_load_total++;
4072 dslots_load_filled++;
4074 if (CONSTANT_P (src_reg))
4075 mips_count_memory_refs (src_reg, 1);
4077 if (CONSTANT_P (dest_reg))
4078 mips_count_memory_refs (dest_reg, 1);
4081 /* Emit load/stores now if we have run out of registers or are
4082 at the end of the move. */
4084 if (++num == num_regs || bytes == 0)
4086 /* If only load/store, we need a NOP after the load. */
4089 load_store[0].load = load_store[0].load_nop;
4090 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
4091 dslots_load_filled--;
4094 if (move_type != BLOCK_MOVE_LAST)
4096 for (i = 0; i < num; i++)
4100 if (!operands[i + 4])
4103 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
4104 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
4105 REGNO (operands[i + 4]));
4107 offset = load_store[i].offset;
4108 xoperands[0] = operands[i + 4];
4109 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4110 plus_constant (src_reg, offset));
4115 = GET_MODE_SIZE (load_store[i].mode) - 1;
4117 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4118 plus_constant (src_reg,
4123 output_asm_insn (load_store[i].load, xoperands);
4127 for (i = 0; i < num; i++)
4129 int last_p = (i == num-1 && bytes == 0);
4130 int offset = load_store[i].offset;
4132 xoperands[0] = operands[i + 4];
4133 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
4134 plus_constant (dest_reg, offset));
4139 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
4140 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
4141 plus_constant (dest_reg,
4146 if (move_type == BLOCK_MOVE_NORMAL)
4147 output_asm_insn (load_store[i].store, xoperands);
4149 else if (move_type == BLOCK_MOVE_NOT_LAST)
4152 output_asm_insn (load_store[i].store, xoperands);
4154 else if (load_store[i].final != 0)
4155 output_asm_insn (load_store[i].final, xoperands);
4159 output_asm_insn (load_store[i].last_store, xoperands);
4162 num = 0; /* reset load_store */
4170 /* Argument support functions. */
4172 /* Initialize CUMULATIVE_ARGS for a function. */
4175 init_cumulative_args (cum, fntype, libname)
4176 CUMULATIVE_ARGS *cum; /* argument info to initialize */
4177 tree fntype; /* tree ptr for function decl */
4178 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
4180 static CUMULATIVE_ARGS zero_cum;
4181 tree param, next_param;
4183 if (TARGET_DEBUG_E_MODE)
4186 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
4189 fputc ('\n', stderr);
4193 tree ret_type = TREE_TYPE (fntype);
4194 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
4195 tree_code_name[(int)TREE_CODE (fntype)],
4196 tree_code_name[(int)TREE_CODE (ret_type)]);
4201 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4203 /* Determine if this function has variable arguments. This is
4204 indicated by the last argument being 'void_type_mode' if there
4205 are no variable arguments. The standard MIPS calling sequence
4206 passes all arguments in the general purpose registers in this case. */
4208 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
4209 param != 0; param = next_param)
4211 next_param = TREE_CHAIN (param);
4212 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
4213 cum->gp_reg_found = 1;
4218 mips_arg_info (cum, mode, type, named, info)
4219 const CUMULATIVE_ARGS *cum;
4220 enum machine_mode mode;
4223 struct mips_arg_info *info;
4226 unsigned int num_words, max_regs;
4228 info->struct_p = (type != 0
4229 && (TREE_CODE (type) == RECORD_TYPE
4230 || TREE_CODE (type) == UNION_TYPE
4231 || TREE_CODE (type) == QUAL_UNION_TYPE));
4233 /* Decide whether this argument should go in a floating-point register,
4234 assuming one is free. Later code checks for availablity. */
4236 info->fpr_p = false;
4237 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4238 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
4244 info->fpr_p = (!cum->gp_reg_found && cum->arg_number < 2);
4252 /* The MIPS eabi says only structures containing doubles get
4253 passed in a fp register, so force a structure containing
4254 a float to be passed in the integer registers. */
4255 info->fpr_p = (named && !(mode == SFmode && info->struct_p));
4259 info->fpr_p = named;
4264 /* Now decide whether the argument must go in an even-numbered register. */
4269 /* Under the O64 ABI, the second float argument goes in $f13 if it
4270 is a double, but $f14 if it is a single. Otherwise, on a
4271 32-bit double-float machine, each FP argument must start in a
4272 new register pair. */
4273 even_reg_p = ((mips_abi == ABI_O64 && mode == SFmode) || FP_INC > 1);
4275 else if (!TARGET_64BIT)
4277 if (GET_MODE_CLASS (mode) == MODE_INT
4278 || GET_MODE_CLASS (mode) == MODE_FLOAT)
4279 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
4281 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
4285 /* Set REG_OFFSET to the register count we're interested in.
4286 The EABI allocates the floating-point registers separately,
4287 but the other ABIs allocate them like integer registers. */
4288 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
4293 info->reg_offset += info->reg_offset & 1;
4295 /* The alignment applied to registers is also applied to stack arguments. */
4296 info->stack_offset = cum->stack_words;
4298 info->stack_offset += info->stack_offset & 1;
4300 if (mode == BLKmode)
4301 info->num_bytes = int_size_in_bytes (type);
4303 info->num_bytes = GET_MODE_SIZE (mode);
4305 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4306 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
4308 /* Partition the argument between registers and stack. */
4309 info->reg_words = MIN (num_words, max_regs);
4310 info->stack_words = num_words - info->reg_words;
4314 /* Advance the argument to the next argument position. */
4317 function_arg_advance (cum, mode, type, named)
4318 CUMULATIVE_ARGS *cum; /* current arg information */
4319 enum machine_mode mode; /* current arg mode */
4320 tree type; /* type of the argument or 0 if lib support */
4321 int named; /* whether or not the argument was named */
4323 struct mips_arg_info info;
4325 mips_arg_info (cum, mode, type, named, &info);
4327 /* The following is a hack in order to pass 1 byte structures
4328 the same way that the MIPS compiler does (namely by passing
4329 the structure in the high byte or half word of the register).
4330 This also makes varargs work. If we have such a structure,
4331 we save the adjustment RTL, and the call define expands will
4332 emit them. For the VOIDmode argument (argument after the
4333 last real argument), pass back a parallel vector holding each
4334 of the adjustments. */
4336 /* ??? This scheme requires everything smaller than the word size to
4337 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4338 that would mean every int needs to be shifted left, which is very
4339 inefficient. Let's not carry this compatibility to the 64 bit
4340 calling convention for now. */
4343 && info.reg_words == 1
4344 && info.num_bytes < UNITS_PER_WORD
4346 && mips_abi != ABI_EABI
4347 && mips_abi != ABI_MEABI)
4349 rtx amount = GEN_INT (BITS_PER_WORD - info.num_bytes * BITS_PER_UNIT);
4350 rtx reg = gen_rtx_REG (word_mode, GP_ARG_FIRST + info.reg_offset);
4353 cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashldi3 (reg, reg, amount));
4355 cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashlsi3 (reg, reg, amount));
4359 cum->gp_reg_found = true;
4361 /* See the comment above the cumulative args structure in mips.h
4362 for an explanation of what this code does. It assumes the O32
4363 ABI, which passes at most 2 arguments in float registers. */
4364 if (cum->arg_number < 2 && info.fpr_p)
4365 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
4367 if (mips_abi != ABI_EABI || !info.fpr_p)
4368 cum->num_gprs = info.reg_offset + info.reg_words;
4369 else if (info.reg_words > 0)
4370 cum->num_fprs += FP_INC;
4372 if (info.stack_words > 0)
4373 cum->stack_words = info.stack_offset + info.stack_words;
4378 /* Return an RTL expression containing the register for the given mode,
4379 or 0 if the argument is to be passed on the stack. */
4382 function_arg (cum, mode, type, named)
4383 const CUMULATIVE_ARGS *cum; /* current arg information */
4384 enum machine_mode mode; /* current arg mode */
4385 tree type; /* type of the argument or 0 if lib support */
4386 int named; /* != 0 for normal args, == 0 for ... args */
4388 struct mips_arg_info info;
4390 /* We will be called with a mode of VOIDmode after the last argument
4391 has been seen. Whatever we return will be passed to the call
4392 insn. If we need any shifts for small structures, return them in
4393 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4394 mode. Otherwise, if we need a mips16 fp_code, return a REG
4395 with the code stored as the mode. */
4396 if (mode == VOIDmode)
4398 if (cum->num_adjusts > 0)
4399 return gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code,
4400 gen_rtvec_v (cum->num_adjusts,
4401 (rtx *) cum->adjust));
4403 else if (TARGET_MIPS16 && cum->fp_code != 0)
4404 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
4410 mips_arg_info (cum, mode, type, named, &info);
4412 /* Return straight away if the whole argument is passed on the stack. */
4413 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
4417 && TREE_CODE (type) == RECORD_TYPE
4418 && (mips_abi == ABI_N32 || mips_abi == ABI_64)
4419 && TYPE_SIZE_UNIT (type)
4420 && host_integerp (TYPE_SIZE_UNIT (type), 1)
4424 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4425 structure contains a double in its entirety, then that 64 bit
4426 chunk is passed in a floating point register. */
4429 /* First check to see if there is any such field. */
4430 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4431 if (TREE_CODE (field) == FIELD_DECL
4432 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4433 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4434 && host_integerp (bit_position (field), 0)
4435 && int_bit_position (field) % BITS_PER_WORD == 0)
4440 /* Now handle the special case by returning a PARALLEL
4441 indicating where each 64 bit chunk goes. INFO.REG_WORDS
4442 chunks are passed in registers. */
4444 HOST_WIDE_INT bitpos;
4447 /* assign_parms checks the mode of ENTRY_PARM, so we must
4448 use the actual mode here. */
4449 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
4452 field = TYPE_FIELDS (type);
4453 for (i = 0; i < info.reg_words; i++)
4457 for (; field; field = TREE_CHAIN (field))
4458 if (TREE_CODE (field) == FIELD_DECL
4459 && int_bit_position (field) >= bitpos)
4463 && int_bit_position (field) == bitpos
4464 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4465 && !TARGET_SOFT_FLOAT
4466 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4467 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
4469 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
4472 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4473 GEN_INT (bitpos / BITS_PER_UNIT));
4475 bitpos += BITS_PER_WORD;
4481 if (mips_abi == ABI_MEABI && info.fpr_p && !cum->prototype)
4483 /* To make K&R varargs work we need to pass floating
4484 point arguments in both integer and FP registers. */
4485 return gen_rtx_PARALLEL
4488 gen_rtx_EXPR_LIST (VOIDmode,
4493 gen_rtx_EXPR_LIST (VOIDmode,
4501 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
4503 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
4507 function_arg_partial_nregs (cum, mode, type, named)
4508 const CUMULATIVE_ARGS *cum; /* current arg information */
4509 enum machine_mode mode; /* current arg mode */
4510 tree type; /* type of the argument or 0 if lib support */
4511 int named; /* != 0 for normal args, == 0 for ... args */
4513 struct mips_arg_info info;
4515 mips_arg_info (cum, mode, type, named, &info);
4516 return info.stack_words > 0 ? info.reg_words : 0;
4520 mips_setup_incoming_varargs (cum, mode, type, no_rtl)
4521 const CUMULATIVE_ARGS *cum;
4522 enum machine_mode mode;
4526 CUMULATIVE_ARGS local_cum;
4527 int gp_saved, fp_saved;
4529 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4532 /* The caller has advanced CUM up to, but not beyond, the last named
4533 argument. Advance a local copy of CUM past the last "real" named
4534 argument, to find out how many registers are left over. */
4537 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
4539 /* Found out how many registers we need to save. */
4540 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
4541 fp_saved = (EABI_FLOAT_VARARGS_P
4542 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
4551 ptr = virtual_incoming_args_rtx;
4552 if (mips_abi == ABI_EABI)
4553 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
4554 mem = gen_rtx_MEM (BLKmode, ptr);
4556 /* va_arg is an array access in this case, which causes
4557 it to get MEM_IN_STRUCT_P set. We must set it here
4558 so that the insn scheduler won't assume that these
4559 stores can't possibly overlap with the va_arg loads. */
4560 if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)
4561 MEM_SET_IN_STRUCT_P (mem, 1);
4563 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, mem,
4564 gp_saved, gp_saved * UNITS_PER_WORD);
4568 /* We can't use move_block_from_reg, because it will use
4570 enum machine_mode mode;
4573 /* Set OFF to the offset from virtual_incoming_args_rtx of
4574 the first float register. The FP save area lies below
4575 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
4576 off = -gp_saved * UNITS_PER_WORD;
4577 off &= ~(UNITS_PER_FPVALUE - 1);
4578 off -= fp_saved * UNITS_PER_FPREG;
4580 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
4582 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
4584 rtx ptr = plus_constant (virtual_incoming_args_rtx, off);
4585 emit_move_insn (gen_rtx_MEM (mode, ptr),
4586 gen_rtx_REG (mode, FP_ARG_FIRST + i));
4587 off += UNITS_PER_FPVALUE;
4591 return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
4594 /* Create the va_list data type.
4595 We keep 3 pointers, and two offsets.
4596 Two pointers are to the overflow area, which starts at the CFA.
4597 One of these is constant, for addressing into the GPR save area below it.
4598 The other is advanced up the stack through the overflow region.
4599 The third pointer is to the GPR save area. Since the FPR save area
4600 is just below it, we can address FPR slots off this pointer.
4601 We also keep two one-byte offsets, which are to be subtracted from the
4602 constant pointers to yield addresses in the GPR and FPR save areas.
4603 These are downcounted as float or non-float arguments are used,
4604 and when they get to zero, the argument must be obtained from the
4606 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
4607 pointer is enough. It's started at the GPR save area, and is
4609 Note that the GPR save area is not constant size, due to optimization
4610 in the prologue. Hence, we can't use a design with two pointers
4611 and two offsets, although we could have designed this with two pointers
4612 and three offsets. */
4616 mips_build_va_list ()
4618 if (EABI_FLOAT_VARARGS_P)
4620 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4622 record = make_node (RECORD_TYPE);
4624 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4626 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4628 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4630 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4631 unsigned_char_type_node);
4632 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4633 unsigned_char_type_node);
4636 DECL_FIELD_CONTEXT (f_ovfl) = record;
4637 DECL_FIELD_CONTEXT (f_gtop) = record;
4638 DECL_FIELD_CONTEXT (f_ftop) = record;
4639 DECL_FIELD_CONTEXT (f_goff) = record;
4640 DECL_FIELD_CONTEXT (f_foff) = record;
4642 TYPE_FIELDS (record) = f_ovfl;
4643 TREE_CHAIN (f_ovfl) = f_gtop;
4644 TREE_CHAIN (f_gtop) = f_ftop;
4645 TREE_CHAIN (f_ftop) = f_goff;
4646 TREE_CHAIN (f_goff) = f_foff;
4648 layout_type (record);
4652 return ptr_type_node;
4655 /* Implement va_start. stdarg_p is always 1. */
4658 mips_va_start (valist, nextarg)
4662 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4664 if (mips_abi == ABI_EABI)
4666 int gpr_save_area_size;
4669 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4671 if (EABI_FLOAT_VARARGS_P)
4673 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4674 tree ovfl, gtop, ftop, goff, foff;
4677 int fpr_save_area_size;
4679 f_ovfl = TYPE_FIELDS (va_list_type_node);
4680 f_gtop = TREE_CHAIN (f_ovfl);
4681 f_ftop = TREE_CHAIN (f_gtop);
4682 f_goff = TREE_CHAIN (f_ftop);
4683 f_foff = TREE_CHAIN (f_goff);
4685 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4686 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4687 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4688 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4689 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4691 /* Emit code to initialize OVFL, which points to the next varargs
4692 stack argument. CUM->STACK_WORDS gives the number of stack
4693 words used by named arguments. */
4694 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4695 if (cum->stack_words > 0)
4696 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4697 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4698 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4699 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4701 /* Emit code to initialize GTOP, the top of the GPR save area. */
4702 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4703 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4704 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4706 /* Emit code to initialize FTOP, the top of the FPR save area.
4707 This address is gpr_save_area_bytes below GTOP, rounded
4708 down to the next fp-aligned boundary. */
4709 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4710 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4711 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4713 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4714 build_int_2 (-fpr_offset, -1));
4715 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4716 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4718 /* Emit code to initialize GOFF, the offset from GTOP of the
4719 next GPR argument. */
4720 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4721 build_int_2 (gpr_save_area_size, 0));
4722 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4724 /* Likewise emit code to initialize FOFF, the offset from FTOP
4725 of the next FPR argument. */
4727 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4728 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4729 build_int_2 (fpr_save_area_size, 0));
4730 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4734 /* Everything is in the GPR save area, or in the overflow
4735 area which is contiguous with it. */
4736 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4737 std_expand_builtin_va_start (valist, nextarg);
4741 std_expand_builtin_va_start (valist, nextarg);
4744 /* Implement va_arg. */
4747 mips_va_arg (valist, type)
4750 HOST_WIDE_INT size, rsize;
4754 size = int_size_in_bytes (type);
4755 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4757 if (mips_abi == ABI_EABI)
4763 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4767 size = POINTER_SIZE / BITS_PER_UNIT;
4768 rsize = UNITS_PER_WORD;
4771 addr_rtx = gen_reg_rtx (Pmode);
4773 if (!EABI_FLOAT_VARARGS_P)
4775 /* Case of all args in a merged stack. No need to check bounds,
4776 just advance valist along the stack. */
4781 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4783 /* Align the pointer using: ap = (ap + align - 1) & -align,
4784 where align is 2 * UNITS_PER_WORD. */
4785 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4786 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4787 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4788 build_int_2 (-2 * UNITS_PER_WORD, -1));
4789 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4790 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4793 /* Emit code to set addr_rtx to the valist, and postincrement
4794 the valist by the size of the argument, rounded up to the
4796 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4798 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4800 emit_move_insn (addr_rtx, r);
4802 /* Flush the POSTINCREMENT. */
4807 /* Not a simple merged stack. */
4809 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4810 tree ovfl, top, off;
4811 rtx lab_over = NULL_RTX, lab_false;
4812 HOST_WIDE_INT osize;
4814 f_ovfl = TYPE_FIELDS (va_list_type_node);
4815 f_gtop = TREE_CHAIN (f_ovfl);
4816 f_ftop = TREE_CHAIN (f_gtop);
4817 f_goff = TREE_CHAIN (f_ftop);
4818 f_foff = TREE_CHAIN (f_goff);
4820 /* We maintain separate pointers and offsets for floating-point
4821 and integer arguments, but we need similar code in both cases.
4824 TOP be the top of the register save area;
4825 OFF be the offset from TOP of the next register;
4826 ADDR_RTX be the address of the argument; and
4827 RSIZE be the number of bytes used to store the argument
4828 when it's in the register save area
4829 OSIZE be the number of bytes used to store it when it's
4830 in the stack overflow area
4831 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4833 The code we want is:
4835 1: off &= -rsize; // round down
4838 4: addr_rtx = top - off;
4843 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4844 10: addr_rtx = ovfl + PADDING;
4848 [1] and [9] can sometimes be optimized away. */
4850 lab_false = gen_label_rtx ();
4851 lab_over = gen_label_rtx ();
4853 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4855 if (TREE_CODE (type) == REAL_TYPE)
4857 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4858 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4860 /* When floating-point registers are saved to the stack,
4861 each one will take up UNITS_PER_FPVALUE bytes, regardless
4862 of the float's precision. */
4863 rsize = UNITS_PER_FPVALUE;
4867 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4868 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4869 if (rsize > UNITS_PER_WORD)
4871 /* [1] Emit code for: off &= -rsize. */
4872 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4873 build_int_2 (-rsize, -1));
4874 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4875 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4878 /* Every overflow argument must take up at least UNITS_PER_WORD
4879 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4880 than that, such as in the combination -mgp64 -msingle-float
4881 -fshort-double. Doubles passed in registers will then take
4882 up UNITS_PER_FPVALUE bytes, but those passed on the stack
4883 take up UNITS_PER_WORD bytes. */
4884 osize = MAX (rsize, UNITS_PER_WORD);
4886 /* [2] Emit code to branch if off == 0. */
4887 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4889 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4892 /* [4] Emit code for: addr_rtx = top - off. */
4893 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4894 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4896 emit_move_insn (addr_rtx, r);
4898 /* [5] Emit code for: off -= rsize. */
4899 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4900 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4901 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4903 /* [7] Emit code to jump over the else clause, then the label
4906 emit_jump (lab_over);
4908 emit_label (lab_false);
4910 if (osize > UNITS_PER_WORD)
4912 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4913 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4914 build_int_2 (osize - 1, 0));
4915 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4916 build_int_2 (-osize, -1));
4917 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4918 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4921 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4922 post-increment ovfl by osize. On big-endian machines,
4923 the argument has OSIZE - RSIZE bytes of leading padding. */
4924 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4926 if (BYTES_BIG_ENDIAN && osize > rsize)
4927 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4928 build_int_2 (osize - rsize, 0));
4929 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4931 emit_move_insn (addr_rtx, r);
4934 emit_label (lab_over);
4938 addr_rtx = force_reg (Pmode, addr_rtx);
4939 r = gen_rtx_MEM (Pmode, addr_rtx);
4940 set_mem_alias_set (r, get_varargs_alias_set ());
4941 emit_move_insn (addr_rtx, r);
4945 if (BYTES_BIG_ENDIAN && rsize != size)
4946 addr_rtx = plus_constant (addr_rtx, rsize - size);
4955 /* ??? The original va-mips.h did always align, despite the fact
4956 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4957 increment mechanism. */
4961 else if (TYPE_ALIGN (type) > 32)
4966 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4967 build_int_2 (align - 1, 0));
4968 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4969 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4970 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4972 /* Everything past the alignment is standard. */
4973 return std_expand_builtin_va_arg (valist, type);
4977 /* Abort after printing out a specific insn. */
4980 abort_with_insn (insn, reason)
4989 /* Set up globals to generate code for the ISA or processor
4990 described by INFO. */
4993 mips_set_architecture (info)
4994 const struct mips_cpu_info *info;
4998 mips_arch_info = info;
4999 mips_arch = info->cpu;
5000 mips_isa = info->isa;
5005 /* Likewise for tuning. */
5008 mips_set_tune (info)
5009 const struct mips_cpu_info *info;
5013 mips_tune_info = info;
5014 mips_tune = info->cpu;
5019 /* Set up the threshold for data to go into the small data area, instead
5020 of the normal data area, and detect any conflicts in the switches. */
5025 int i, start, regno;
5026 enum machine_mode mode;
5028 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
5030 if (mips_section_threshold <= 0)
5031 target_flags &= ~MASK_GPOPT;
5033 target_flags |= MASK_GPOPT;
5035 /* If both single-float and soft-float are set, then clear the one that
5036 was set by TARGET_DEFAULT, leaving the one that was set by the
5037 user. We assume here that the specs prevent both being set by the
5039 #ifdef TARGET_DEFAULT
5040 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
5041 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
5044 /* Interpret -mabi. */
5045 mips_abi = MIPS_ABI_DEFAULT;
5046 if (mips_abi_string != 0)
5048 if (strcmp (mips_abi_string, "32") == 0)
5050 else if (strcmp (mips_abi_string, "o64") == 0)
5052 else if (strcmp (mips_abi_string, "n32") == 0)
5054 else if (strcmp (mips_abi_string, "64") == 0)
5056 else if (strcmp (mips_abi_string, "eabi") == 0)
5057 mips_abi = ABI_EABI;
5058 else if (strcmp (mips_abi_string, "meabi") == 0)
5059 mips_abi = ABI_MEABI;
5061 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
5064 /* The following code determines the architecture and register size.
5065 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
5066 The GAS and GCC code should be kept in sync as much as possible. */
5068 if (mips_arch_string != 0)
5069 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
5071 if (mips_tune_string != 0)
5072 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
5074 if (mips_isa_string != 0)
5076 /* Handle -mipsN. */
5077 int level = atoi (mips_isa_string);
5080 /* -mips16 specifies an ASE rather than a processor, so don't
5081 change mips_arch here. -mno-mips16 overrides -mips16. */
5082 if (mips_no_mips16_string == NULL)
5083 target_flags |= MASK_MIPS16;
5085 else if (mips_arch_info != 0)
5087 /* -march takes precedence over -mipsN, since it is more descriptive.
5088 There's no harm in specifying both as long as the ISA levels
5090 if (mips_isa != level)
5091 error ("-mips%d conflicts with the other architecture options, which specify a MIPS%d processor",
5096 mips_set_architecture (mips_cpu_info_from_isa (level));
5097 if (mips_arch_info == 0)
5098 error ("bad value (%s) for -mips switch", mips_isa_string);
5102 if (mips_arch_info == 0)
5104 #ifdef MIPS_CPU_STRING_DEFAULT
5105 mips_set_architecture (mips_parse_cpu ("default CPU",
5106 MIPS_CPU_STRING_DEFAULT));
5108 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
5112 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
5113 error ("-march=%s is not compatible with the selected ABI",
5114 mips_arch_info->name);
5116 /* Optimize for mips_arch, unless -mtune selects a different processor. */
5117 if (mips_tune_info == 0)
5118 mips_set_tune (mips_arch_info);
5120 if ((target_flags_explicit & MASK_64BIT) != 0)
5122 /* The user specified the size of the integer registers. Make sure
5123 it agrees with the ABI and ISA. */
5124 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
5125 error ("-mgp64 used with a 32-bit processor");
5126 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
5127 error ("-mgp32 used with a 64-bit ABI");
5128 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
5129 error ("-mgp64 used with a 32-bit ABI");
5133 /* Infer the integer register size from the ABI and processor.
5134 Restrict ourselves to 32-bit registers if that's all the
5135 processor has, or if the ABI cannot handle 64-bit registers. */
5136 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
5137 target_flags &= ~MASK_64BIT;
5139 target_flags |= MASK_64BIT;
5142 if ((target_flags_explicit & MASK_FLOAT64) != 0)
5144 /* Really, -mfp32 and -mfp64 are ornamental options. There's
5145 only one right answer here. */
5146 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
5147 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
5148 else if (!TARGET_64BIT && TARGET_FLOAT64)
5149 error ("unsupported combination: %s", "-mgp32 -mfp64");
5150 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
5151 error ("unsupported combination: %s", "-mfp64 -msingle-float");
5155 /* -msingle-float selects 32-bit float registers. Otherwise the
5156 float registers should be the same size as the integer ones. */
5157 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
5158 target_flags |= MASK_FLOAT64;
5160 target_flags &= ~MASK_FLOAT64;
5163 /* End of code shared with GAS. */
5165 if ((target_flags_explicit & MASK_LONG64) == 0)
5167 /* If no type size setting options (-mlong64,-mint64,-mlong32)
5168 were used, then set the type sizes. In the EABI in 64 bit mode,
5169 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
5171 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
5172 target_flags |= MASK_LONG64;
5174 target_flags &= ~MASK_LONG64;
5177 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
5178 flag_pcc_struct_return = 0;
5180 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
5181 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
5182 /* ??? -non_shared turns off pic code generation, but this is not
5184 if (TARGET_ABICALLS)
5186 mips_abicalls = MIPS_ABICALLS_YES;
5188 if (mips_section_threshold > 0)
5189 warning ("-G is incompatible with PIC code which is the default");
5192 mips_abicalls = MIPS_ABICALLS_NO;
5194 /* -membedded-pic is a form of PIC code suitable for embedded
5195 systems. All calls are made using PC relative addressing, and
5196 all data is addressed using the $gp register. This requires gas,
5197 which does most of the work, and GNU ld, which automatically
5198 expands PC relative calls which are out of range into a longer
5199 instruction sequence. All gcc really does differently is
5200 generate a different sequence for a switch. */
5201 if (TARGET_EMBEDDED_PIC)
5204 if (TARGET_ABICALLS)
5205 warning ("-membedded-pic and -mabicalls are incompatible");
5208 warning ("-G and -membedded-pic are incompatible");
5210 /* Setting mips_section_threshold is not required, because gas
5211 will force everything to be GP addressable anyhow, but
5212 setting it will cause gcc to make better estimates of the
5213 number of instructions required to access a particular data
5215 mips_section_threshold = 0x7fffffff;
5218 /* This optimization requires a linker that can support a R_MIPS_LO16
5219 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5220 GNU ld has this support, but not all other MIPS linkers do, so we enable
5221 this optimization only if the user requests it, or if GNU ld is the
5222 standard linker for this configuration. */
5223 /* ??? This does not work when target addresses are DImode.
5224 This is because we are missing DImode high/lo_sum patterns. */
5225 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5227 mips_split_addresses = 1;
5229 mips_split_addresses = 0;
5231 /* -mrnames says to use the MIPS software convention for register
5232 names instead of the hardware names (ie, $a0 instead of $4).
5233 We do this by switching the names in mips_reg_names, which the
5234 reg_names points into via the REGISTER_NAMES macro. */
5236 if (TARGET_NAME_REGS)
5237 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5239 /* When compiling for the mips16, we can not use floating point. We
5240 record the original hard float value in mips16_hard_float. */
5243 if (TARGET_SOFT_FLOAT)
5244 mips16_hard_float = 0;
5246 mips16_hard_float = 1;
5247 target_flags |= MASK_SOFT_FLOAT;
5249 /* Don't run the scheduler before reload, since it tends to
5250 increase register pressure. */
5251 flag_schedule_insns = 0;
5254 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5255 to avoid using up another bit in target_flags. */
5256 if (mips_entry_string != NULL)
5258 if (*mips_entry_string != '\0')
5259 error ("invalid option `entry%s'", mips_entry_string);
5261 if (! TARGET_MIPS16)
5262 warning ("-mentry is only meaningful with -mips-16");
5267 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5268 attributes can access it. */
5274 /* Initialize the high and low values for legitimate floating point
5275 constants. Rather than trying to get the accuracy down to the
5276 last bit, just use approximate ranges. */
5277 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5278 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5279 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5280 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5282 mips_print_operand_punct['?'] = 1;
5283 mips_print_operand_punct['#'] = 1;
5284 mips_print_operand_punct['&'] = 1;
5285 mips_print_operand_punct['!'] = 1;
5286 mips_print_operand_punct['*'] = 1;
5287 mips_print_operand_punct['@'] = 1;
5288 mips_print_operand_punct['.'] = 1;
5289 mips_print_operand_punct['('] = 1;
5290 mips_print_operand_punct[')'] = 1;
5291 mips_print_operand_punct['['] = 1;
5292 mips_print_operand_punct[']'] = 1;
5293 mips_print_operand_punct['<'] = 1;
5294 mips_print_operand_punct['>'] = 1;
5295 mips_print_operand_punct['{'] = 1;
5296 mips_print_operand_punct['}'] = 1;
5297 mips_print_operand_punct['^'] = 1;
5298 mips_print_operand_punct['$'] = 1;
5299 mips_print_operand_punct['+'] = 1;
5300 mips_print_operand_punct['~'] = 1;
5302 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5303 mips_char_to_class['e'] = M16_NA_REGS;
5304 mips_char_to_class['t'] = T_REG;
5305 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5306 mips_char_to_class['h'] = HI_REG;
5307 mips_char_to_class['l'] = LO_REG;
5308 mips_char_to_class['a'] = HILO_REG;
5309 mips_char_to_class['x'] = MD_REGS;
5310 mips_char_to_class['b'] = ALL_REGS;
5311 mips_char_to_class['y'] = GR_REGS;
5312 mips_char_to_class['z'] = ST_REGS;
5313 mips_char_to_class['B'] = COP0_REGS;
5314 mips_char_to_class['C'] = COP2_REGS;
5315 mips_char_to_class['D'] = COP3_REGS;
5317 /* Set up array to map GCC register number to debug register number.
5318 Ignore the special purpose register numbers. */
5320 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5321 mips_dbx_regno[i] = -1;
5323 start = GP_DBX_FIRST - GP_REG_FIRST;
5324 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5325 mips_dbx_regno[i] = i + start;
5327 start = FP_DBX_FIRST - FP_REG_FIRST;
5328 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5329 mips_dbx_regno[i] = i + start;
5331 /* Set up array giving whether a given register can hold a given mode.
5332 At present, restrict ints from being in FP registers, because reload
5333 is a little enthusiastic about storing extra values in FP registers,
5334 and this is not good for things like OS kernels. Also, due to the
5335 mandatory delay, it is as fast to load from cached memory as to move
5336 from the FP register. */
5338 for (mode = VOIDmode;
5339 mode != MAX_MACHINE_MODE;
5340 mode = (enum machine_mode) ((int)mode + 1))
5342 register int size = GET_MODE_SIZE (mode);
5343 register enum mode_class class = GET_MODE_CLASS (mode);
5345 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5352 temp = (regno == FPSW_REGNUM);
5354 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5355 || FP_REG_P (regno));
5358 else if (GP_REG_P (regno))
5359 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5361 else if (FP_REG_P (regno))
5362 temp = (((regno % FP_INC) == 0
5363 /* I think this change is OK regardless of abi, but
5364 I'm being cautions untill I can test this more.
5365 HARD_REGNO_MODE_OK is about whether or not you
5366 can move to and from a register without changing
5367 the value, not about whether math works on the
5369 || (mips_abi == ABI_MEABI && size <= 4))
5370 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
5371 && size <= UNITS_PER_FPVALUE)
5372 /* Allow integer modes that fit into a single
5373 register. We need to put integers into FPRs
5374 when using instructions like cvt and trunc. */
5375 || (class == MODE_INT && size <= UNITS_PER_FPREG)));
5377 else if (MD_REG_P (regno))
5378 temp = (class == MODE_INT
5379 && (size <= UNITS_PER_WORD
5380 || (regno == MD_REG_FIRST
5381 && size == 2 * UNITS_PER_WORD)));
5383 else if (ALL_COP_REG_P (regno))
5384 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5388 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5392 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5393 initialized yet, so we can't use that here. */
5394 gpr_mode = TARGET_64BIT ? DImode : SImode;
5396 /* Provide default values for align_* for 64-bit targets. */
5397 if (TARGET_64BIT && !TARGET_MIPS16)
5399 if (align_loops == 0)
5401 if (align_jumps == 0)
5403 if (align_functions == 0)
5404 align_functions = 8;
5407 /* Function to allocate machine-dependent function status. */
5408 init_machine_status = &mips_init_machine_status;
5411 /* Implement CONDITIONAL_REGISTER_USAGE. */
5414 mips_conditional_register_usage ()
5416 if (!TARGET_HARD_FLOAT)
5420 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5421 fixed_regs[regno] = call_used_regs[regno] = 1;
5422 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5423 fixed_regs[regno] = call_used_regs[regno] = 1;
5425 else if (! ISA_HAS_8CC)
5429 /* We only have a single condition code register. We
5430 implement this by hiding all the condition code registers,
5431 and generating RTL that refers directly to ST_REG_FIRST. */
5432 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5433 fixed_regs[regno] = call_used_regs[regno] = 1;
5435 /* In mips16 mode, we permit the $t temporary registers to be used
5436 for reload. We prohibit the unused $s registers, since they
5437 are caller saved, and saving them via a mips16 register would
5438 probably waste more time than just reloading the value. */
5441 fixed_regs[18] = call_used_regs[18] = 1;
5442 fixed_regs[19] = call_used_regs[19] = 1;
5443 fixed_regs[20] = call_used_regs[20] = 1;
5444 fixed_regs[21] = call_used_regs[21] = 1;
5445 fixed_regs[22] = call_used_regs[22] = 1;
5446 fixed_regs[23] = call_used_regs[23] = 1;
5447 fixed_regs[26] = call_used_regs[26] = 1;
5448 fixed_regs[27] = call_used_regs[27] = 1;
5449 fixed_regs[30] = call_used_regs[30] = 1;
5451 /* fp20-23 are now caller saved. */
5452 if (mips_abi == ABI_64)
5455 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5456 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5458 /* odd registers from fp21 to fp31 are now caller saved. */
5459 if (mips_abi == ABI_N32 || mips_abi == ABI_MEABI)
5462 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5463 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5467 /* Allocate a chunk of memory for per-function machine-dependent data. */
5468 static struct machine_function *
5469 mips_init_machine_status ()
5471 return ((struct machine_function *)
5472 ggc_alloc_cleared (sizeof (struct machine_function)));
5475 /* On the mips16, we want to allocate $24 (T_REG) before other
5476 registers for instructions for which it is possible. This helps
5477 avoid shuffling registers around in order to set up for an xor,
5478 encouraging the compiler to use a cmp instead. */
5481 mips_order_regs_for_local_alloc ()
5485 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5486 reg_alloc_order[i] = i;
5490 /* It really doesn't matter where we put register 0, since it is
5491 a fixed register anyhow. */
5492 reg_alloc_order[0] = 24;
5493 reg_alloc_order[24] = 0;
5498 /* The MIPS debug format wants all automatic variables and arguments
5499 to be in terms of the virtual frame pointer (stack pointer before
5500 any adjustment in the function), while the MIPS 3.0 linker wants
5501 the frame pointer to be the stack pointer after the initial
5502 adjustment. So, we do the adjustment here. The arg pointer (which
5503 is eliminated) points to the virtual frame pointer, while the frame
5504 pointer (which may be eliminated) points to the stack pointer after
5505 the initial adjustments. */
5508 mips_debugger_offset (addr, offset)
5510 HOST_WIDE_INT offset;
5512 rtx offset2 = const0_rtx;
5513 rtx reg = eliminate_constant_term (addr, &offset2);
5516 offset = INTVAL (offset2);
5518 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5519 || reg == hard_frame_pointer_rtx)
5521 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5522 ? compute_frame_size (get_frame_size ())
5523 : cfun->machine->frame.total_size;
5525 /* MIPS16 frame is smaller */
5526 if (frame_pointer_needed && TARGET_MIPS16)
5527 frame_size -= current_function_outgoing_args_size;
5529 offset = offset - frame_size;
5532 /* sdbout_parms does not want this to crash for unrecognized cases. */
5534 else if (reg != arg_pointer_rtx)
5535 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
5541 /* A C compound statement to output to stdio stream STREAM the
5542 assembler syntax for an instruction operand X. X is an RTL
5545 CODE is a value that can be used to specify one of several ways
5546 of printing the operand. It is used when identical operands
5547 must be printed differently depending on the context. CODE
5548 comes from the `%' specification that was used to request
5549 printing of the operand. If the specification was just `%DIGIT'
5550 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5551 is the ASCII code for LTR.
5553 If X is a register, this macro should print the register's name.
5554 The names can be found in an array `reg_names' whose type is
5555 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5557 When the machine description has a specification `%PUNCT' (a `%'
5558 followed by a punctuation character), this macro is called with
5559 a null pointer for X and the punctuation character for CODE.
5561 The MIPS specific codes are:
5563 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5564 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5565 'd' output integer constant in decimal,
5566 'z' if the operand is 0, use $0 instead of normal operand.
5567 'D' print second part of double-word register or memory operand.
5568 'L' print low-order register of double-word register operand.
5569 'M' print high-order register of double-word register operand.
5570 'C' print part of opcode for a branch condition.
5571 'F' print part of opcode for a floating-point branch condition.
5572 'N' print part of opcode for a branch condition, inverted.
5573 'W' print part of opcode for a floating-point branch condition, inverted.
5574 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5575 'B' print 'z' for EQ, 'n' for NE
5576 'b' print 'n' for EQ, 'z' for NE
5577 'T' print 'f' for EQ, 't' for NE
5578 't' print 't' for EQ, 'f' for NE
5579 'Z' print register and a comma, but print nothing for $fcc0
5580 '(' Turn on .set noreorder
5581 ')' Turn on .set reorder
5582 '[' Turn on .set noat
5584 '<' Turn on .set nomacro
5585 '>' Turn on .set macro
5586 '{' Turn on .set volatile (not GAS)
5587 '}' Turn on .set novolatile (not GAS)
5588 '&' Turn on .set noreorder if filling delay slots
5589 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5590 '!' Turn on .set nomacro if filling delay slots
5591 '#' Print nop if in a .set noreorder section.
5592 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5593 '@' Print the name of the assembler temporary register (at or $1).
5594 '.' Print the name of the register with a hard-wired zero (zero or $0).
5595 '^' Print the name of the pic call-through register (t9 or $25).
5596 '$' Print the name of the stack pointer register (sp or $29).
5597 '+' Print the name of the gp register (gp or $28).
5598 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5601 print_operand (file, op, letter)
5602 FILE *file; /* file to write to */
5603 rtx op; /* operand to print */
5604 int letter; /* %<letter> or 0 */
5606 register enum rtx_code code;
5608 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5613 if (mips_branch_likely)
5618 fputs (reg_names [GP_REG_FIRST + 1], file);
5622 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5626 fputs (reg_names [GP_REG_FIRST + 0], file);
5630 fputs (reg_names[STACK_POINTER_REGNUM], file);
5634 fputs (reg_names[GP_REG_FIRST + 28], file);
5638 if (final_sequence != 0 && set_noreorder++ == 0)
5639 fputs (".set\tnoreorder\n\t", file);
5643 if (final_sequence != 0)
5645 if (set_noreorder++ == 0)
5646 fputs (".set\tnoreorder\n\t", file);
5648 if (set_nomacro++ == 0)
5649 fputs (".set\tnomacro\n\t", file);
5654 if (final_sequence != 0 && set_nomacro++ == 0)
5655 fputs ("\n\t.set\tnomacro", file);
5659 if (set_noreorder != 0)
5660 fputs ("\n\tnop", file);
5661 else if (TARGET_STATS)
5662 fputs ("\n\t#nop", file);
5667 if (set_noreorder++ == 0)
5668 fputs (".set\tnoreorder\n\t", file);
5672 if (set_noreorder == 0)
5673 error ("internal error: %%) found without a %%( in assembler pattern");
5675 else if (--set_noreorder == 0)
5676 fputs ("\n\t.set\treorder", file);
5681 if (set_noat++ == 0)
5682 fputs (".set\tnoat\n\t", file);
5687 error ("internal error: %%] found without a %%[ in assembler pattern");
5688 else if (--set_noat == 0)
5689 fputs ("\n\t.set\tat", file);
5694 if (set_nomacro++ == 0)
5695 fputs (".set\tnomacro\n\t", file);
5699 if (set_nomacro == 0)
5700 error ("internal error: %%> found without a %%< in assembler pattern");
5701 else if (--set_nomacro == 0)
5702 fputs ("\n\t.set\tmacro", file);
5707 if (set_volatile++ == 0)
5708 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5712 if (set_volatile == 0)
5713 error ("internal error: %%} found without a %%{ in assembler pattern");
5714 else if (--set_volatile == 0)
5715 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5721 if (align_labels_log > 0)
5722 ASM_OUTPUT_ALIGN (file, align_labels_log);
5727 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5736 error ("PRINT_OPERAND null pointer");
5740 code = GET_CODE (op);
5742 if (code == SIGN_EXTEND)
5743 op = XEXP (op, 0), code = GET_CODE (op);
5748 case EQ: fputs ("eq", file); break;
5749 case NE: fputs ("ne", file); break;
5750 case GT: fputs ("gt", file); break;
5751 case GE: fputs ("ge", file); break;
5752 case LT: fputs ("lt", file); break;
5753 case LE: fputs ("le", file); break;
5754 case GTU: fputs ("gtu", file); break;
5755 case GEU: fputs ("geu", file); break;
5756 case LTU: fputs ("ltu", file); break;
5757 case LEU: fputs ("leu", file); break;
5759 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5762 else if (letter == 'N')
5765 case EQ: fputs ("ne", file); break;
5766 case NE: fputs ("eq", file); break;
5767 case GT: fputs ("le", file); break;
5768 case GE: fputs ("lt", file); break;
5769 case LT: fputs ("ge", file); break;
5770 case LE: fputs ("gt", file); break;
5771 case GTU: fputs ("leu", file); break;
5772 case GEU: fputs ("ltu", file); break;
5773 case LTU: fputs ("geu", file); break;
5774 case LEU: fputs ("gtu", file); break;
5776 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5779 else if (letter == 'F')
5782 case EQ: fputs ("c1f", file); break;
5783 case NE: fputs ("c1t", file); break;
5785 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5788 else if (letter == 'W')
5791 case EQ: fputs ("c1t", file); break;
5792 case NE: fputs ("c1f", file); break;
5794 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5797 else if (letter == 'S')
5801 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5802 assemble_name (file, buffer);
5805 else if (letter == 'Z')
5807 register int regnum;
5812 regnum = REGNO (op);
5813 if (! ST_REG_P (regnum))
5816 if (regnum != ST_REG_FIRST)
5817 fprintf (file, "%s,", reg_names[regnum]);
5820 else if (code == REG || code == SUBREG)
5822 register int regnum;
5825 regnum = REGNO (op);
5827 regnum = true_regnum (op);
5829 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5830 || (letter == 'L' && WORDS_BIG_ENDIAN)
5834 fprintf (file, "%s", reg_names[regnum]);
5837 else if (code == MEM)
5840 output_address (plus_constant (XEXP (op, 0), 4));
5842 output_address (XEXP (op, 0));
5845 else if (code == CONST_DOUBLE
5846 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5851 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5852 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5856 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5857 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5859 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5860 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5862 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5863 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5865 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5866 fputs (reg_names[GP_REG_FIRST], file);
5868 else if (letter == 'd' || letter == 'x' || letter == 'X')
5869 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5871 else if (letter == 'B')
5872 fputs (code == EQ ? "z" : "n", file);
5873 else if (letter == 'b')
5874 fputs (code == EQ ? "n" : "z", file);
5875 else if (letter == 'T')
5876 fputs (code == EQ ? "f" : "t", file);
5877 else if (letter == 't')
5878 fputs (code == EQ ? "t" : "f", file);
5880 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5882 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5883 print_operand (file, XEXP (op, 0), letter);
5886 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5888 fputs ("%gprel(", file);
5889 mips16_output_gp_offset (file, op);
5894 output_addr_const (file, op);
5897 /* A C compound statement to output to stdio stream STREAM the
5898 assembler syntax for an instruction operand that is a memory
5899 reference whose address is ADDR. ADDR is an RTL expression. */
5902 print_operand_address (file, addr)
5907 error ("PRINT_OPERAND_ADDRESS, null pointer");
5910 switch (GET_CODE (addr))
5913 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5914 abort_with_insn (addr, "arg pointer not eliminated");
5916 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5921 register rtx arg0 = XEXP (addr, 0);
5922 register rtx arg1 = XEXP (addr, 1);
5924 if (! mips_split_addresses)
5925 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM");
5927 if (GET_CODE (arg0) != REG)
5928 abort_with_insn (addr,
5929 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG");
5931 fprintf (file, "%%lo(");
5932 print_operand_address (file, arg1);
5933 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5939 register rtx reg = 0;
5940 register rtx offset = 0;
5941 register rtx arg0 = XEXP (addr, 0);
5942 register rtx arg1 = XEXP (addr, 1);
5944 if (GET_CODE (arg0) == REG)
5948 if (GET_CODE (offset) == REG)
5949 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5952 else if (GET_CODE (arg1) == REG)
5953 reg = arg1, offset = arg0;
5954 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5956 output_addr_const (file, addr);
5960 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5962 if (! CONSTANT_P (offset))
5963 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5965 if (REGNO (reg) == ARG_POINTER_REGNUM)
5966 abort_with_insn (addr, "arg pointer not eliminated");
5969 && GET_CODE (offset) == CONST
5970 && mips16_gp_offset_p (offset))
5972 fputs ("%gprel(", file);
5973 mips16_output_gp_offset (file, offset);
5977 output_addr_const (file, offset);
5978 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5986 output_addr_const (file, addr);
5990 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5995 /* Target hook for assembling integer objects. It appears that the Irix
5996 6 assembler can't handle 64-bit decimal integers, so avoid printing
5997 such an integer here. */
6000 mips_assemble_integer (x, size, aligned_p)
6005 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
6007 fputs ("\t.dword\t", asm_out_file);
6008 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
6009 output_addr_const (asm_out_file, x);
6011 print_operand (asm_out_file, x, 'X');
6012 fputc ('\n', asm_out_file);
6015 return default_assemble_integer (x, size, aligned_p);
6018 /* If optimizing for the global pointer, keep track of all of the externs, so
6019 that at the end of the file, we can emit the appropriate .extern
6020 declaration for them, before writing out the text section. We assume all
6021 names passed to us are in the permanent obstack, so they will be valid at
6022 the end of the compilation.
6024 If we have -G 0, or the extern size is unknown, or the object is in a user
6025 specified section that is not .sbss/.sdata, don't bother emitting the
6026 .externs. In the case of user specified sections this behaviour is
6027 required as otherwise GAS will think the object lives in .sbss/.sdata. */
6030 mips_output_external (file, decl, name)
6031 FILE *file ATTRIBUTE_UNUSED;
6035 register struct extern_list *p;
6040 && TREE_CODE (decl) != FUNCTION_DECL
6041 && !DECL_COMDAT (decl)
6042 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
6043 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
6044 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
6045 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
6047 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
6048 p->next = extern_head;
6054 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6055 if (TREE_CODE (decl) == FUNCTION_DECL
6056 /* ??? Don't include alloca, since gcc will always expand it
6057 inline. If we don't do this, the C++ library fails to build. */
6058 && strcmp (name, "alloca")
6059 /* ??? Don't include __builtin_next_arg, because then gcc will not
6060 bootstrap under Irix 5.1. */
6061 && strcmp (name, "__builtin_next_arg"))
6063 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
6064 p->next = extern_head;
6074 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6076 mips_output_external_libcall (file, name)
6077 FILE *file ATTRIBUTE_UNUSED;
6080 register struct extern_list *p;
6082 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
6083 p->next = extern_head;
6092 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
6093 for .file's that start within a function. If we are smuggling stabs, try to
6094 put out a MIPS ECOFF file and a stab. */
6097 mips_output_filename (stream, name)
6101 static int first_time = 1;
6102 char ltext_label_name[100];
6104 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
6106 if (write_symbols == DWARF2_DEBUG)
6108 else if (first_time)
6112 current_function_file = name;
6113 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
6114 /* This tells mips-tfile that stabs will follow. */
6115 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
6116 fprintf (stream, "\t#@stabs\n");
6119 else if (write_symbols == DBX_DEBUG)
6121 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
6122 fprintf (stream, "%s", ASM_STABS_OP);
6123 output_quoted_string (stream, name);
6124 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
6127 else if (name != current_function_file
6128 && strcmp (name, current_function_file) != 0)
6130 if (inside_function && !TARGET_GAS)
6132 if (!file_in_function_warning)
6134 file_in_function_warning = 1;
6135 ignore_line_number = 1;
6136 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
6142 current_function_file = name;
6143 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
6148 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
6149 as well as a .loc, since it is possible that MIPS ECOFF might not be
6150 able to represent the location for inlines that come from a different
6154 mips_output_lineno (stream, line)
6158 if (write_symbols == DBX_DEBUG)
6161 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
6162 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
6163 LOCAL_LABEL_PREFIX, sym_lineno);
6167 fprintf (stream, "\n\t%s.loc\t%d %d\n",
6168 (ignore_line_number) ? "#" : "",
6169 num_source_filenames, line);
6171 LABEL_AFTER_LOC (stream);
6175 /* Output an ASCII string, in a space-saving way. */
6178 mips_output_ascii (stream, string_param, len)
6180 const char *string_param;
6185 register const unsigned char *string =
6186 (const unsigned char *)string_param;
6188 fprintf (stream, "\t.ascii\t\"");
6189 for (i = 0; i < len; i++)
6191 register int c = string[i];
6197 putc ('\\', stream);
6202 case TARGET_NEWLINE:
6203 fputs ("\\n", stream);
6205 && (((c = string[i+1]) >= '\040' && c <= '~')
6206 || c == TARGET_TAB))
6207 cur_pos = 32767; /* break right here */
6213 fputs ("\\t", stream);
6218 fputs ("\\f", stream);
6223 fputs ("\\b", stream);
6228 fputs ("\\r", stream);
6233 if (c >= ' ' && c < 0177)
6240 fprintf (stream, "\\%03o", c);
6245 if (cur_pos > 72 && i+1 < len)
6248 fprintf (stream, "\"\n\t.ascii\t\"");
6251 fprintf (stream, "\"\n");
6254 /* If defined, a C statement to be executed just prior to the output of
6255 assembler code for INSN, to modify the extracted operands so they will be
6258 Here the argument OPVEC is the vector containing the operands extracted
6259 from INSN, and NOPERANDS is the number of elements of the vector which
6260 contain meaningful data for this insn. The contents of this vector are
6261 what will be used to convert the insn template into assembler code, so you
6262 can change the assembler output by changing the contents of the vector.
6264 We use it to check if the current insn needs a nop in front of it because
6265 of load delays, and also to update the delay slot statistics. */
6267 /* ??? There is no real need for this function, because it never actually
6268 emits a NOP anymore. */
6271 final_prescan_insn (insn, opvec, noperands)
6273 rtx opvec[] ATTRIBUTE_UNUSED;
6274 int noperands ATTRIBUTE_UNUSED;
6276 if (dslots_number_nops > 0)
6278 rtx pattern = PATTERN (insn);
6279 int length = get_attr_length (insn);
6281 /* Do we need to emit a NOP? */
6283 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
6284 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
6285 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
6286 || (mips_load_reg4 != 0
6287 && reg_mentioned_p (mips_load_reg4, pattern)))
6288 fputs ("\t#nop\n", asm_out_file);
6291 dslots_load_filled++;
6293 while (--dslots_number_nops > 0)
6294 fputs ("\t#nop\n", asm_out_file);
6303 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6304 dslots_jump_total++;
6307 /* Output at beginning of assembler file.
6309 If we are optimizing to use the global pointer, create a temporary file to
6310 hold all of the text stuff, and write it out to the end. This is needed
6311 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6312 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6313 processed, it generates a two instruction sequence. */
6316 mips_asm_file_start (stream)
6319 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6321 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6322 inside of a .set noreorder section jumps to a label outside of the .set
6323 noreorder section. Revision 2.20 just set nobopt silently rather than
6326 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6327 fprintf (stream, "\t.set\tnobopt\n");
6331 #if defined(OBJECT_FORMAT_ELF) && !(TARGET_IRIX5 || TARGET_IRIX6)
6332 /* Generate a special section to describe the ABI switches used to
6333 produce the resultant binary. This used to be done by the assembler
6334 setting bits in the ELF header's flags field, but we have run out of
6335 bits. GDB needs this information in order to be able to correctly
6336 debug these binaries. See the function mips_gdbarch_init() in
6337 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
6338 causes unnecessary IRIX 6 ld warnings. */
6339 const char * abi_string = NULL;
6343 case ABI_32: abi_string = "abi32"; break;
6344 case ABI_N32: abi_string = "abiN32"; break;
6345 case ABI_64: abi_string = "abi64"; break;
6346 case ABI_O64: abi_string = "abiO64"; break;
6347 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
6348 case ABI_MEABI:abi_string = TARGET_64BIT ? "meabi64" : "meabi32"; break;
6352 /* Note - we use fprintf directly rather than called named_section()
6353 because in this way we can avoid creating an allocated section. We
6354 do not want this section to take up any space in the running
6356 fprintf (stream, "\t.section .mdebug.%s\n", abi_string);
6358 /* Restore the default section. */
6359 fprintf (stream, "\t.previous\n");
6365 /* Generate the pseudo ops that System V.4 wants. */
6366 #ifndef ABICALLS_ASM_OP
6367 #define ABICALLS_ASM_OP "\t.abicalls"
6369 if (TARGET_ABICALLS)
6370 /* ??? but do not want this (or want pic0) if -non-shared? */
6371 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6374 fprintf (stream, "\t.set\tmips16\n");
6376 /* This code exists so that we can put all externs before all symbol
6377 references. This is necessary for the MIPS assembler's global pointer
6378 optimizations to work. */
6379 if (TARGET_FILE_SWITCHING)
6381 asm_out_data_file = stream;
6382 asm_out_text_file = tmpfile ();
6385 asm_out_data_file = asm_out_text_file = stream;
6387 if (flag_verbose_asm)
6388 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6390 mips_section_threshold, mips_arch_info->name, mips_isa);
6393 /* If we are optimizing the global pointer, emit the text section now and any
6394 small externs which did not have .comm, etc that are needed. Also, give a
6395 warning if the data area is more than 32K and -pic because 3 instructions
6396 are needed to reference the data pointers. */
6399 mips_asm_file_end (file)
6403 struct extern_list *p;
6409 for (p = extern_head; p != 0; p = p->next)
6411 name_tree = get_identifier (p->name);
6413 /* Positively ensure only one .extern for any given symbol. */
6414 if (! TREE_ASM_WRITTEN (name_tree))
6416 TREE_ASM_WRITTEN (name_tree) = 1;
6417 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6419 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6423 fputs ("\t.extern\t", file);
6424 assemble_name (file, p->name);
6425 fprintf (file, ", %d\n", p->size);
6431 if (TARGET_FILE_SWITCHING)
6433 fprintf (file, "\n\t.text\n");
6434 copy_file_data (file, asm_out_text_file);
6439 copy_file_data (to, from)
6446 fatal_io_error ("can't rewind temp file");
6448 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6449 if (fwrite (buffer, 1, len, to) != len)
6450 fatal_io_error ("can't write to output file");
6453 fatal_io_error ("can't read from temp file");
6456 fatal_io_error ("can't close temp file");
6459 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6460 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6463 mips_declare_object (stream, name, init_string, final_string, size)
6466 const char *init_string;
6467 const char *final_string;
6470 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6471 assemble_name (stream, name);
6472 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6476 tree name_tree = get_identifier (name);
6477 TREE_ASM_WRITTEN (name_tree) = 1;
6481 /* Return the bytes needed to compute the frame pointer from the current
6484 Mips stack frames look like:
6486 Before call After call
6487 +-----------------------+ +-----------------------+
6490 | caller's temps. | | caller's temps. |
6492 +-----------------------+ +-----------------------+
6494 | arguments on stack. | | arguments on stack. |
6496 +-----------------------+ +-----------------------+
6497 | 4 words to save | | 4 words to save |
6498 | arguments passed | | arguments passed |
6499 | in registers, even | | in registers, even |
6500 SP->| if not passed. | VFP->| if not passed. |
6501 +-----------------------+ +-----------------------+
6503 | fp register save |
6505 +-----------------------+
6507 | gp register save |
6509 +-----------------------+
6513 +-----------------------+
6515 | alloca allocations |
6517 +-----------------------+
6519 | GP save for V.4 abi |
6521 +-----------------------+
6523 | arguments on stack |
6525 +-----------------------+
6527 | arguments passed |
6528 | in registers, even |
6529 low SP->| if not passed. |
6530 memory +-----------------------+
6535 compute_frame_size (size)
6536 HOST_WIDE_INT size; /* # of var. bytes allocated */
6539 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6540 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6541 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6542 HOST_WIDE_INT extra_size; /* # extra bytes */
6543 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6544 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6545 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6546 long mask; /* mask of saved gp registers */
6547 long fmask; /* mask of saved fp registers */
6554 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6555 var_size = MIPS_STACK_ALIGN (size);
6556 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6558 /* The MIPS 3.0 linker does not like functions that dynamically
6559 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6560 looks like we are trying to create a second frame pointer to the
6561 function, so allocate some stack space to make it happy. */
6563 if (args_size == 0 && current_function_calls_alloca)
6564 args_size = 4 * UNITS_PER_WORD;
6566 total_size = var_size + args_size + extra_size;
6567 return_type = DECL_RESULT (current_function_decl);
6569 /* Calculate space needed for gp registers. */
6570 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6572 /* $18 is a special case on the mips16. It may be used to call
6573 a function which returns a floating point value, but it is
6574 marked in call_used_regs. $31 is also a special case. When
6575 not using -mentry, it will be used to copy a return value
6576 into the floating point registers if the return value is
6578 if (MUST_SAVE_REGISTER (regno)
6580 && regno == GP_REG_FIRST + 18
6581 && regs_ever_live[regno])
6583 && regno == GP_REG_FIRST + 31
6584 && mips16_hard_float
6586 && ! aggregate_value_p (return_type)
6587 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6588 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE))
6590 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6591 mask |= 1L << (regno - GP_REG_FIRST);
6593 /* The entry and exit pseudo instructions can not save $17
6594 without also saving $16. */
6596 && regno == GP_REG_FIRST + 17
6597 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6599 gp_reg_size += UNITS_PER_WORD;
6605 /* We need to restore these for the handler. */
6606 if (current_function_calls_eh_return)
6611 regno = EH_RETURN_DATA_REGNO (i);
6612 if (regno == INVALID_REGNUM)
6614 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6615 mask |= 1L << (regno - GP_REG_FIRST);
6619 /* This loop must iterate over the same space as its companion in
6620 save_restore_insns. */
6621 for (regno = (FP_REG_LAST - FP_INC + 1);
6622 regno >= FP_REG_FIRST;
6625 if (regs_ever_live[regno] && !call_used_regs[regno])
6627 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6628 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6632 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6633 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6635 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6636 for leaf routines (total_size == extra_size) to save the gp reg.
6637 The gp reg is callee saved in the 64 bit ABI, so all routines must
6638 save the gp reg. This is not a leaf routine if -p, because of the
6640 if (total_size == extra_size
6641 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6642 && ! current_function_profile)
6643 total_size = extra_size = 0;
6644 else if (TARGET_ABICALLS)
6646 /* Add the context-pointer to the saved registers. */
6647 gp_reg_size += UNITS_PER_WORD;
6648 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6649 total_size -= gp_reg_rounded;
6650 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6651 total_size += gp_reg_rounded;
6654 /* Add in space reserved on the stack by the callee for storing arguments
6655 passed in registers. */
6656 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6657 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6659 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6660 if (mips_entry && total_size > 0 && total_size < 32)
6663 /* Save other computed information. */
6664 cfun->machine->frame.total_size = total_size;
6665 cfun->machine->frame.var_size = var_size;
6666 cfun->machine->frame.args_size = args_size;
6667 cfun->machine->frame.extra_size = extra_size;
6668 cfun->machine->frame.gp_reg_size = gp_reg_size;
6669 cfun->machine->frame.fp_reg_size = fp_reg_size;
6670 cfun->machine->frame.mask = mask;
6671 cfun->machine->frame.fmask = fmask;
6672 cfun->machine->frame.initialized = reload_completed;
6673 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6674 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6678 unsigned long offset;
6680 /* When using mips_entry, the registers are always saved at the
6681 top of the stack. */
6683 offset = (args_size + extra_size + var_size
6684 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6686 offset = total_size - GET_MODE_SIZE (gpr_mode);
6688 cfun->machine->frame.gp_sp_offset = offset;
6689 cfun->machine->frame.gp_save_offset = offset - total_size;
6693 cfun->machine->frame.gp_sp_offset = 0;
6694 cfun->machine->frame.gp_save_offset = 0;
6699 unsigned long offset = (args_size + extra_size + var_size
6700 + gp_reg_rounded + fp_reg_size
6701 - FP_INC * UNITS_PER_FPREG);
6702 cfun->machine->frame.fp_sp_offset = offset;
6703 cfun->machine->frame.fp_save_offset = offset - total_size;
6707 cfun->machine->frame.fp_sp_offset = 0;
6708 cfun->machine->frame.fp_save_offset = 0;
6711 /* Ok, we're done. */
6715 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6716 pointer, argument pointer, or return address pointer. TO is either
6717 the stack pointer or hard frame pointer. */
6720 mips_initial_elimination_offset (from, to)
6725 /* Set OFFSET to the offset from the stack pointer. */
6728 case FRAME_POINTER_REGNUM:
6732 case ARG_POINTER_REGNUM:
6733 compute_frame_size (get_frame_size ());
6734 offset = cfun->machine->frame.total_size;
6735 if (mips_abi == ABI_N32 || mips_abi == ABI_64 || mips_abi == ABI_MEABI)
6736 offset -= current_function_pretend_args_size;
6739 case RETURN_ADDRESS_POINTER_REGNUM:
6740 compute_frame_size (get_frame_size ());
6741 offset = cfun->machine->frame.gp_sp_offset;
6742 if (BYTES_BIG_ENDIAN)
6743 offset += UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT);
6750 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6751 offset -= current_function_outgoing_args_size;
6756 /* Common code to emit the insns (or to write the instructions to a file)
6757 to save/restore registers.
6759 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6760 is not modified within save_restore_insns. */
6762 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6764 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6765 and return an rtl expression for the register.
6767 This function is a subroutine of save_restore_insns. It is used when
6768 OFFSET is too large to add in a single instruction. */
6771 mips_add_large_offset_to_sp (offset)
6772 HOST_WIDE_INT offset;
6774 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6775 rtx offset_rtx = GEN_INT (offset);
6777 emit_move_insn (reg, offset_rtx);
6778 if (Pmode == DImode)
6779 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
6781 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
6785 /* Make INSN frame related and note that it performs the frame-related
6786 operation DWARF_PATTERN. */
6789 mips_annotate_frame_insn (insn, dwarf_pattern)
6790 rtx insn, dwarf_pattern;
6792 RTX_FRAME_RELATED_P (insn) = 1;
6793 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6798 /* Return a frame-related rtx that stores register REGNO at (SP + OFFSET).
6799 The expression should only be used to store single registers. */
6802 mips_frame_set (mode, regno, offset)
6803 enum machine_mode mode;
6807 rtx address = plus_constant (stack_pointer_rtx, offset);
6808 rtx set = gen_rtx_SET (mode,
6809 gen_rtx_MEM (mode, address),
6810 gen_rtx_REG (mode, regno));
6811 RTX_FRAME_RELATED_P (set) = 1;
6816 /* Emit a move instruction that stores REG in MEM. Make the instruction
6817 frame related and note that it stores REG at (SP + OFFSET). This
6818 function may be asked to store an FPR pair. */
6821 mips_emit_frame_related_store (mem, reg, offset)
6824 HOST_WIDE_INT offset;
6828 if (GET_MODE (reg) == DFmode && ! TARGET_FLOAT64)
6830 /* Two registers are being stored, so the frame-related expression
6831 must be a PARALLEL rtx with one SET for each register. The
6832 higher numbered register is stored in the lower address on
6833 big-endian targets. */
6834 int regno1 = TARGET_BIG_ENDIAN ? REGNO (reg) + 1 : REGNO (reg);
6835 int regno2 = TARGET_BIG_ENDIAN ? REGNO (reg) : REGNO (reg) + 1;
6836 rtx set1 = mips_frame_set (SFmode, regno1, offset);
6837 rtx set2 = mips_frame_set (SFmode, regno2, offset + UNITS_PER_FPREG);
6838 dwarf_expr = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set1, set2));
6841 dwarf_expr = mips_frame_set (GET_MODE (reg), REGNO (reg), offset);
6843 mips_annotate_frame_insn (emit_move_insn (mem, reg), dwarf_expr);
6847 save_restore_insns (store_p, large_reg, large_offset)
6848 int store_p; /* true if this is prologue */
6849 rtx large_reg; /* register holding large offset constant or NULL */
6850 long large_offset; /* large constant offset value */
6852 long mask = cfun->machine->frame.mask;
6853 long fmask = cfun->machine->frame.fmask;
6854 long real_mask = mask;
6857 HOST_WIDE_INT base_offset;
6858 HOST_WIDE_INT gp_offset;
6859 HOST_WIDE_INT fp_offset;
6860 HOST_WIDE_INT end_offset;
6863 if (frame_pointer_needed
6864 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6867 /* Do not restore GP under certain conditions. */
6870 && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6871 mask &= ~(1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST));
6873 if (mask == 0 && fmask == 0)
6876 /* Save registers starting from high to low. The debuggers prefer at least
6877 the return register be stored at func+4, and also it allows us not to
6878 need a nop in the epilog if at least one register is reloaded in
6879 addition to return address. */
6881 /* Save GP registers if needed. */
6884 /* Pick which pointer to use as a base register. For small frames, just
6885 use the stack pointer. Otherwise, use a temporary register. Save 2
6886 cycles if the save area is near the end of a large frame, by reusing
6887 the constant created in the prologue/epilogue to adjust the stack
6890 gp_offset = cfun->machine->frame.gp_sp_offset;
6892 = gp_offset - (cfun->machine->frame.gp_reg_size
6893 - GET_MODE_SIZE (gpr_mode));
6895 if (gp_offset < 0 || end_offset < 0)
6897 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
6898 (long) gp_offset, (long) end_offset);
6900 /* If we see a large frame in mips16 mode, we save the registers
6901 before adjusting the stack pointer, and load them afterward. */
6902 else if (TARGET_MIPS16 && large_offset > 32767)
6903 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6905 else if (gp_offset < 32768)
6906 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6908 else if (large_reg != 0
6909 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6910 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6912 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6913 base_offset = large_offset;
6914 if (Pmode == DImode)
6915 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6916 stack_pointer_rtx));
6918 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6919 stack_pointer_rtx));
6923 base_offset = gp_offset;
6924 base_reg_rtx = mips_add_large_offset_to_sp (base_offset);
6927 /* When we restore the registers in MIPS16 mode, then if we are
6928 using a frame pointer, and this is not a large frame, the
6929 current stack pointer will be offset by
6930 current_function_outgoing_args_size. Doing it this way lets
6931 us avoid offsetting the frame pointer before copying it into
6932 the stack pointer; there is no instruction to set the stack
6933 pointer to the sum of a register and a constant. */
6936 && frame_pointer_needed
6937 && large_offset <= 32767)
6938 base_offset += current_function_outgoing_args_size;
6940 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6942 if (BITSET_P (mask, regno - GP_REG_FIRST))
6946 = gen_rtx (MEM, gpr_mode,
6947 gen_rtx (PLUS, Pmode, base_reg_rtx,
6948 GEN_INT (gp_offset - base_offset)));
6950 if (! current_function_calls_eh_return)
6951 RTX_UNCHANGING_P (mem_rtx) = 1;
6953 /* The mips16 does not have an instruction to load
6954 $31, so we load $7 instead, and work things out
6955 in mips_expand_epilogue. */
6956 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6957 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6958 /* The mips16 sometimes needs to save $18. */
6959 else if (TARGET_MIPS16
6960 && regno != GP_REG_FIRST + 31
6961 && ! M16_REG_P (regno))
6964 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6967 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6968 emit_move_insn (reg_rtx,
6969 gen_rtx (REG, gpr_mode, regno));
6973 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6976 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
6979 emit_move_insn (reg_rtx, mem_rtx);
6981 && regno != GP_REG_FIRST + 31
6982 && ! M16_REG_P (regno))
6983 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6987 /* If the restore is being supressed, still take into account
6988 the offset at which it is stored. */
6989 if (BITSET_P (real_mask, regno - GP_REG_FIRST))
6990 gp_offset -= GET_MODE_SIZE (gpr_mode);
6994 base_reg_rtx = 0, base_offset = 0;
6996 /* Save floating point registers if needed. */
6999 /* Pick which pointer to use as a base register. */
7000 fp_offset = cfun->machine->frame.fp_sp_offset;
7001 end_offset = fp_offset - (cfun->machine->frame.fp_reg_size
7002 - UNITS_PER_FPVALUE);
7004 if (fp_offset < 0 || end_offset < 0)
7006 ("fp_offset (%ld) or end_offset (%ld) is less than zero",
7007 (long) fp_offset, (long) end_offset);
7009 else if (fp_offset < 32768)
7010 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
7012 else if (base_reg_rtx != 0
7013 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
7014 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
7015 ; /* already set up for gp registers above */
7017 else if (large_reg != 0
7018 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
7019 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
7021 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
7022 base_offset = large_offset;
7023 if (Pmode == DImode)
7024 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
7025 stack_pointer_rtx));
7027 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
7028 stack_pointer_rtx));
7032 base_offset = fp_offset;
7033 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset);
7036 /* This loop must iterate over the same space as its companion in
7037 compute_frame_size. */
7038 for (regno = (FP_REG_LAST - FP_INC + 1);
7039 regno >= FP_REG_FIRST;
7041 if (BITSET_P (fmask, regno - FP_REG_FIRST))
7043 enum machine_mode sz = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
7044 rtx reg_rtx = gen_rtx (REG, sz, regno);
7045 rtx mem_rtx = gen_rtx (MEM, sz,
7046 gen_rtx (PLUS, Pmode, base_reg_rtx,
7049 if (! current_function_calls_eh_return)
7050 RTX_UNCHANGING_P (mem_rtx) = 1;
7053 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
7055 emit_move_insn (reg_rtx, mem_rtx);
7057 fp_offset -= UNITS_PER_FPVALUE;
7062 /* Set up the stack and frame (if desired) for the function. */
7065 mips_output_function_prologue (file, size)
7067 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7069 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7072 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7074 /* ??? When is this really needed? At least the GNU assembler does not
7075 need the source filename more than once in the file, beyond what is
7076 emitted by the debug information. */
7078 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
7080 #ifdef SDB_DEBUGGING_INFO
7081 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
7082 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
7085 /* In mips16 mode, we may need to generate a 32 bit to handle
7086 floating point arguments. The linker will arrange for any 32 bit
7087 functions to call this stub, which will then jump to the 16 bit
7089 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
7090 && current_function_args_info.fp_code != 0)
7091 build_mips16_function_stub (file);
7093 inside_function = 1;
7095 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7096 /* Get the function name the same way that toplev.c does before calling
7097 assemble_start_function. This is needed so that the name used here
7098 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7099 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7101 if (!flag_inhibit_size_directive)
7103 fputs ("\t.ent\t", file);
7104 assemble_name (file, fnname);
7108 assemble_name (file, fnname);
7109 fputs (":\n", file);
7112 if (!flag_inhibit_size_directive)
7114 /* .frame FRAMEREG, FRAMESIZE, RETREG */
7116 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7117 (reg_names[(frame_pointer_needed)
7118 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
7119 ((frame_pointer_needed && TARGET_MIPS16)
7120 ? ((long) tsize - current_function_outgoing_args_size)
7122 reg_names[GP_REG_FIRST + 31],
7123 cfun->machine->frame.var_size,
7124 cfun->machine->frame.num_gp,
7125 cfun->machine->frame.num_fp,
7126 current_function_outgoing_args_size,
7127 cfun->machine->frame.extra_size);
7129 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
7130 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
7131 cfun->machine->frame.mask,
7132 cfun->machine->frame.gp_save_offset,
7133 cfun->machine->frame.fmask,
7134 cfun->machine->frame.fp_save_offset);
7137 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
7138 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
7141 if (mips_entry && ! mips_can_use_return_insn ())
7143 int save16 = BITSET_P (cfun->machine->frame.mask, 16);
7144 int save17 = BITSET_P (cfun->machine->frame.mask, 17);
7145 int save31 = BITSET_P (cfun->machine->frame.mask, 31);
7149 /* Look through the initial insns to see if any of them store
7150 the function parameters into the incoming parameter storage
7151 area. If they do, we delete the insn, and save the register
7152 using the entry pseudo-instruction instead. We don't try to
7153 look past a label, jump, or call. */
7154 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
7156 rtx note, set, src, dest, base, offset;
7159 if (GET_CODE (insn) == CODE_LABEL
7160 || GET_CODE (insn) == JUMP_INSN
7161 || GET_CODE (insn) == CALL_INSN)
7163 if (GET_CODE (insn) != INSN)
7165 set = PATTERN (insn);
7166 if (GET_CODE (set) != SET)
7169 /* An insn storing a function parameter will still have a
7170 REG_EQUIV note on it mentioning the argument pointer. */
7171 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
7172 if (note == NULL_RTX)
7174 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
7177 src = SET_SRC (set);
7178 if (GET_CODE (src) != REG
7179 || REGNO (src) < GP_REG_FIRST + 4
7180 || REGNO (src) > GP_REG_FIRST + 7)
7183 dest = SET_DEST (set);
7184 if (GET_CODE (dest) != MEM)
7186 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
7188 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
7189 && REGNO (src) < GP_REG_FIRST + 7)
7193 offset = const0_rtx;
7194 base = eliminate_constant_term (XEXP (dest, 0), &offset);
7195 if (GET_CODE (base) != REG
7196 || GET_CODE (offset) != CONST_INT)
7198 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
7199 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
7201 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
7204 + (REGNO (src) - 4) * UNITS_PER_WORD
7205 - current_function_outgoing_args_size)))
7210 /* This insn stores a parameter onto the stack, in the same
7211 location where the entry pseudo-instruction will put it.
7212 Delete the insn, and arrange to tell the entry
7213 instruction to save the register. */
7214 PUT_CODE (insn, NOTE);
7215 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7216 NOTE_SOURCE_FILE (insn) = 0;
7218 hireg = (REGNO (src)
7219 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
7221 if (hireg > savearg)
7225 /* If this is a varargs function, we need to save all the
7226 registers onto the stack anyhow. */
7227 if (current_function_stdarg)
7228 savearg = GP_REG_FIRST + 7;
7230 fprintf (file, "\tentry\t");
7233 if (savearg == GP_REG_FIRST + 4)
7234 fprintf (file, "%s", reg_names[savearg]);
7236 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
7237 reg_names[savearg]);
7239 if (save16 || save17)
7242 fprintf (file, ",");
7243 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
7245 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
7249 if (savearg > 0 || save16 || save17)
7250 fprintf (file, ",");
7251 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
7253 fprintf (file, "\n");
7256 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
7258 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7260 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7261 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7264 fprintf (file, "\t%s\t%s,%s,%ld\n",
7265 (Pmode == DImode ? "dsubu" : "subu"),
7266 sp_str, sp_str, (long) tsize);
7267 fprintf (file, "\t.cprestore %ld\n", cfun->machine->frame.args_size);
7270 if (dwarf2out_do_frame ())
7271 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7275 /* Expand the prologue into a bunch of separate insns. */
7278 mips_expand_prologue ()
7281 HOST_WIDE_INT tsize;
7283 int last_arg_is_vararg_marker = 0;
7284 tree fndecl = current_function_decl;
7285 tree fntype = TREE_TYPE (fndecl);
7286 tree fnargs = DECL_ARGUMENTS (fndecl);
7291 CUMULATIVE_ARGS args_so_far;
7292 rtx reg_18_save = NULL_RTX;
7293 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7294 && (! mips_entry || mips_can_use_return_insn ());
7296 /* If struct value address is treated as the first argument, make it so. */
7297 if (aggregate_value_p (DECL_RESULT (fndecl))
7298 && ! current_function_returns_pcc_struct
7299 && struct_value_incoming_rtx == 0)
7301 tree type = build_pointer_type (fntype);
7302 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7304 DECL_ARG_TYPE (function_result_decl) = type;
7305 TREE_CHAIN (function_result_decl) = fnargs;
7306 fnargs = function_result_decl;
7309 /* For arguments passed in registers, find the register number
7310 of the first argument in the variable part of the argument list,
7311 otherwise GP_ARG_LAST+1. Note also if the last argument is
7312 the varargs special argument, and treat it as part of the
7315 This is only needed if store_args_on_stack is true. */
7317 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7318 regno = GP_ARG_FIRST;
7320 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7322 tree passed_type = DECL_ARG_TYPE (cur_arg);
7323 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7326 if (TREE_ADDRESSABLE (passed_type))
7328 passed_type = build_pointer_type (passed_type);
7329 passed_mode = Pmode;
7332 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7334 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7335 next_arg = TREE_CHAIN (cur_arg);
7337 if (entry_parm && store_args_on_stack)
7340 && DECL_NAME (cur_arg)
7341 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7342 "__builtin_va_alist"))
7343 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7346 last_arg_is_vararg_marker = 1;
7347 if (GET_CODE (entry_parm) == REG)
7348 regno = REGNO (entry_parm);
7350 regno = GP_ARG_LAST + 1;
7357 if (GET_CODE (entry_parm) != REG)
7360 /* passed in a register, so will get homed automatically */
7361 if (GET_MODE (entry_parm) == BLKmode)
7362 words = (int_size_in_bytes (passed_type) + 3) / 4;
7364 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7366 regno = REGNO (entry_parm) + words - 1;
7371 regno = GP_ARG_LAST+1;
7376 /* In order to pass small structures by value in registers compatibly with
7377 the MIPS compiler, we need to shift the value into the high part of the
7378 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7379 adjustments to be made as the next_arg_reg variable, so we split up the
7380 insns, and emit them separately. */
7382 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7383 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7385 rtvec adjust = XVEC (next_arg_reg, 0);
7386 int num = GET_NUM_ELEM (adjust);
7388 for (i = 0; i < num; i++)
7392 pattern = RTVEC_ELT (adjust, i);
7393 if (GET_CODE (pattern) != SET
7394 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7395 abort_with_insn (pattern, "insn is not a shift");
7396 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7398 insn = emit_insn (pattern);
7400 /* Global life information isn't valid at this point, so we
7401 can't check whether these shifts are actually used. Mark
7402 them MAYBE_DEAD so that flow2 will remove them, and not
7403 complain about dead code in the prologue. */
7404 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7409 tsize = compute_frame_size (get_frame_size ());
7411 /* If this function is a varargs function, store any registers that
7412 would normally hold arguments ($4 - $7) on the stack. */
7413 if (store_args_on_stack
7414 && ((TYPE_ARG_TYPES (fntype) != 0
7415 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7417 || last_arg_is_vararg_marker))
7419 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7420 rtx ptr = stack_pointer_rtx;
7422 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7423 if (TARGET_ABICALLS)
7426 for (; regno <= GP_ARG_LAST; regno++)
7429 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7430 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7431 gen_rtx (REG, gpr_mode, regno));
7433 offset += GET_MODE_SIZE (gpr_mode);
7437 /* If we are using the entry pseudo instruction, it will
7438 automatically subtract 32 from the stack pointer, so we don't
7439 need to. The entry pseudo instruction is emitted by
7440 function_prologue. */
7441 if (mips_entry && ! mips_can_use_return_insn ())
7443 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7447 /* If we are using a frame pointer with a small stack frame,
7448 we need to initialize it here since it won't be done
7450 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7452 rtx incr = GEN_INT (current_function_outgoing_args_size);
7453 if (Pmode == DImode)
7454 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7458 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7462 else if (Pmode == DImode)
7463 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7464 stack_pointer_rtx));
7466 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7467 stack_pointer_rtx));
7469 RTX_FRAME_RELATED_P (insn) = 1;
7472 /* We may need to save $18, if it is used to call a function
7473 which may return a floating point value. Set up a sequence
7474 of instructions to do so. Later on we emit them at the right
7476 if (TARGET_MIPS16 && BITSET_P (cfun->machine->frame.mask, 18))
7478 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7479 long gp_offset, base_offset;
7481 gp_offset = cfun->machine->frame.gp_sp_offset;
7482 if (BITSET_P (cfun->machine->frame.mask, 16))
7483 gp_offset -= UNITS_PER_WORD;
7484 if (BITSET_P (cfun->machine->frame.mask, 17))
7485 gp_offset -= UNITS_PER_WORD;
7486 if (BITSET_P (cfun->machine->frame.mask, 31))
7487 gp_offset -= UNITS_PER_WORD;
7489 base_offset = tsize;
7493 emit_move_insn (reg_rtx,
7494 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7495 emit_move_insn (gen_rtx (MEM, gpr_mode,
7496 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7500 reg_18_save = get_insns ();
7509 if (reg_18_save != NULL_RTX)
7510 emit_insn (reg_18_save);
7516 rtx tsize_rtx = GEN_INT (tsize);
7518 /* If we are doing svr4-abi, sp move is done by
7519 function_prologue. In mips16 mode with a large frame, we
7520 save the registers before adjusting the stack. */
7521 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7522 && (!TARGET_MIPS16 || tsize <= 32767))
7524 rtx adjustment_rtx, insn, dwarf_pattern;
7528 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7529 emit_move_insn (adjustment_rtx, tsize_rtx);
7532 adjustment_rtx = tsize_rtx;
7534 if (Pmode == DImode)
7535 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7538 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7541 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
7542 plus_constant (stack_pointer_rtx,
7545 mips_annotate_frame_insn (insn, dwarf_pattern);
7549 save_restore_insns (1, tmp_rtx, tsize);
7550 else if (reg_18_save != NULL_RTX)
7551 emit_insn (reg_18_save);
7553 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7559 if (!frame_pointer_needed)
7562 reg_rtx = gen_rtx (REG, Pmode, 3);
7563 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7564 emit_move_insn (reg_rtx, tsize_rtx);
7565 if (Pmode == DImode)
7566 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7567 hard_frame_pointer_rtx,
7570 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7571 hard_frame_pointer_rtx,
7573 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7576 if (frame_pointer_needed)
7580 /* On the mips16, we encourage the use of unextended
7581 instructions when using the frame pointer by pointing the
7582 frame pointer ahead of the argument space allocated on
7584 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7588 /* In this case, we have already copied the stack
7589 pointer into the frame pointer, above. We need only
7590 adjust for the outgoing argument size. */
7591 if (current_function_outgoing_args_size != 0)
7593 rtx incr = GEN_INT (current_function_outgoing_args_size);
7594 if (Pmode == DImode)
7595 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7596 hard_frame_pointer_rtx,
7599 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7600 hard_frame_pointer_rtx,
7604 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7606 rtx incr = GEN_INT (current_function_outgoing_args_size);
7607 if (Pmode == DImode)
7608 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7612 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7616 else if (Pmode == DImode)
7617 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7618 stack_pointer_rtx));
7620 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7621 stack_pointer_rtx));
7624 RTX_FRAME_RELATED_P (insn) = 1;
7627 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7628 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7629 gen_rtx_REG (DImode, 25)));
7632 /* If we are profiling, make sure no instructions are scheduled before
7633 the call to mcount. */
7635 if (current_function_profile)
7636 emit_insn (gen_blockage ());
7639 /* Do any necessary cleanup after a function to restore stack, frame,
7642 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7643 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7646 mips_output_function_epilogue (file, size)
7647 FILE *file ATTRIBUTE_UNUSED;
7648 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7650 const char *fnname = ""; /* FIXME: Correct initialisation? */
7652 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7653 /* Get the function name the same way that toplev.c does before calling
7654 assemble_start_function. This is needed so that the name used here
7655 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7656 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7658 if (!flag_inhibit_size_directive)
7660 fputs ("\t.end\t", file);
7661 assemble_name (file, fnname);
7668 int num_gp_regs = cfun->machine->frame.gp_reg_size / 4;
7669 int num_fp_regs = cfun->machine->frame.fp_reg_size / 8;
7670 int num_regs = num_gp_regs + num_fp_regs;
7671 const char *name = fnname;
7676 dslots_load_total += num_regs;
7679 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7680 name, frame_pointer_needed ? 'y' : 'n',
7681 (cfun->machine->frame.mask & RA_MASK) != 0 ? 'n' : 'y',
7682 current_function_calls_alloca ? 'y' : 'n',
7683 current_function_calls_setjmp ? 'y' : 'n',
7684 cfun->machine->frame.total_size,
7685 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7686 dslots_load_total, dslots_load_filled,
7687 dslots_jump_total, dslots_jump_filled,
7688 num_refs[0], num_refs[1], num_refs[2]);
7690 fputc ('\n', stderr);
7693 /* Reset state info for each function. */
7694 inside_function = 0;
7695 ignore_line_number = 0;
7696 dslots_load_total = 0;
7697 dslots_jump_total = 0;
7698 dslots_load_filled = 0;
7699 dslots_jump_filled = 0;
7706 while (string_constants != NULL)
7708 struct string_constant *next;
7710 next = string_constants->next;
7711 free (string_constants);
7712 string_constants = next;
7715 /* Restore the output file if optimizing the GP (optimizing the GP causes
7716 the text to be diverted to a tempfile, so that data decls come before
7717 references to the data). */
7718 if (TARGET_FILE_SWITCHING)
7720 asm_out_file = asm_out_data_file;
7725 /* Expand the epilogue into a bunch of separate insns. */
7728 mips_expand_epilogue ()
7730 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
7731 rtx tsize_rtx = GEN_INT (tsize);
7732 rtx tmp_rtx = (rtx)0;
7734 if (mips_can_use_return_insn ())
7736 emit_jump_insn (gen_return ());
7740 if (mips_entry && ! mips_can_use_return_insn ())
7743 if (tsize > 32767 && ! TARGET_MIPS16)
7745 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7746 emit_move_insn (tmp_rtx, tsize_rtx);
7747 tsize_rtx = tmp_rtx;
7752 long orig_tsize = tsize;
7754 if (frame_pointer_needed)
7756 emit_insn (gen_blockage ());
7758 /* On the mips16, the frame pointer is offset from the stack
7759 pointer by current_function_outgoing_args_size. We
7760 account for that by changing tsize. Note that this can
7761 actually make tsize negative. */
7764 tsize -= current_function_outgoing_args_size;
7766 /* If we have a large frame, it's easier to add to $6
7767 than to $sp, since the mips16 has no instruction to
7768 add a register to $sp. */
7769 if (orig_tsize > 32767)
7771 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7773 emit_move_insn (g6_rtx, GEN_INT (tsize));
7774 if (Pmode == DImode)
7775 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7776 hard_frame_pointer_rtx,
7779 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7780 hard_frame_pointer_rtx,
7785 if (tsize && tsize != orig_tsize)
7786 tsize_rtx = GEN_INT (tsize);
7789 if (Pmode == DImode)
7790 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7792 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7795 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7796 are going to restore it, then we must emit a blockage insn to
7797 prevent the scheduler from moving the restore out of the epilogue. */
7798 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7799 && (cfun->machine->frame.mask
7800 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7801 emit_insn (gen_blockage ());
7803 save_restore_insns (0, tmp_rtx, orig_tsize);
7805 /* In mips16 mode with a large frame, we adjust the stack
7806 pointer before restoring the registers. In this case, we
7807 should always be using a frame pointer, so everything should
7808 have been handled above. */
7809 if (tsize > 32767 && TARGET_MIPS16)
7812 if (current_function_calls_eh_return)
7814 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7815 if (Pmode == DImode)
7816 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7818 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7822 emit_insn (gen_blockage ());
7824 if (tsize != 0 || current_function_calls_eh_return)
7828 if (Pmode == DImode)
7829 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7832 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7837 /* We need to work around not being able to add a register
7838 to the stack pointer directly. Use register $6 as an
7839 intermediate step. */
7841 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7843 if (Pmode == DImode)
7845 emit_insn (gen_movdi (g6_rtx, stack_pointer_rtx));
7846 emit_insn (gen_adddi3 (g6_rtx, g6_rtx, tsize_rtx));
7847 emit_insn (gen_movdi (stack_pointer_rtx, g6_rtx));
7851 emit_insn (gen_movsi (g6_rtx, stack_pointer_rtx));
7852 emit_insn (gen_addsi3 (g6_rtx, g6_rtx, tsize_rtx));
7853 emit_insn (gen_movsi (stack_pointer_rtx, g6_rtx));
7860 /* The mips16 loads the return address into $7, not $31. */
7861 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
7862 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7863 GP_REG_FIRST + 7)));
7865 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7866 GP_REG_FIRST + 31)));
7869 /* Return nonzero if this function is known to have a null epilogue.
7870 This allows the optimizer to omit jumps to jumps if no stack
7874 mips_can_use_return_insn ()
7878 if (! reload_completed)
7881 if (regs_ever_live[31] || current_function_profile)
7884 return_type = DECL_RESULT (current_function_decl);
7886 /* In mips16 mode, a function which returns a floating point value
7887 needs to arrange to copy the return value into the floating point
7890 && mips16_hard_float
7891 && ! aggregate_value_p (return_type)
7892 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
7893 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
7896 if (cfun->machine->frame.initialized)
7897 return cfun->machine->frame.total_size == 0;
7899 return compute_frame_size (get_frame_size ()) == 0;
7902 /* Returns non-zero if X contains a SYMBOL_REF. */
7905 symbolic_expression_p (x)
7908 if (GET_CODE (x) == SYMBOL_REF)
7911 if (GET_CODE (x) == CONST)
7912 return symbolic_expression_p (XEXP (x, 0));
7914 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7915 return symbolic_expression_p (XEXP (x, 0));
7917 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7918 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7919 return (symbolic_expression_p (XEXP (x, 0))
7920 || symbolic_expression_p (XEXP (x, 1)));
7925 /* Choose the section to use for the constant rtx expression X that has
7929 mips_select_rtx_section (mode, x, align)
7930 enum machine_mode mode;
7932 unsigned HOST_WIDE_INT align;
7936 /* In mips16 mode, the constant table always goes in the same section
7937 as the function, so that constants can be loaded using PC relative
7939 function_section (current_function_decl);
7941 else if (TARGET_EMBEDDED_DATA)
7943 /* For embedded applications, always put constants in read-only data,
7944 in order to reduce RAM usage. */
7945 mergeable_constant_section (mode, align, 0);
7949 /* For hosted applications, always put constants in small data if
7950 possible, as this gives the best performance. */
7951 /* ??? Consider using mergable small data sections. */
7953 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7954 && mips_section_threshold > 0)
7955 SMALL_DATA_SECTION ();
7956 else if (flag_pic && symbolic_expression_p (x))
7958 if (targetm.have_named_sections)
7959 named_section (NULL_TREE, ".data.rel.ro", 3);
7964 mergeable_constant_section (mode, align, 0);
7968 /* Choose the section to use for DECL. RELOC is true if its value contains
7969 any relocatable expression.
7971 Some of the logic used here needs to be replicated in
7972 mips_encode_section_info so that references to these symbols are
7973 done correctly. Specifically, at least all symbols assigned here
7974 to rom (.text and/or .rodata) must not be referenced via
7975 mips_encode_section_info with %gprel, as the rom might be too far
7978 If you need to make a change here, you probably should check
7979 mips_encode_section_info to see if it needs a similar change.
7981 ??? This would be fixed by implementing targetm.is_small_data_p. */
7984 mips_select_section (decl, reloc, align)
7987 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7989 int size = int_size_in_bytes (TREE_TYPE (decl));
7991 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7992 && TREE_CODE (decl) == STRING_CST
7993 && !flag_writable_strings)
7994 /* For embedded position independent code, put constant strings in the
7995 text section, because the data section is limited to 64K in size.
7996 For mips16 code, put strings in the text section so that a PC
7997 relative load instruction can be used to get their address. */
7999 else if (TARGET_EMBEDDED_DATA)
8001 /* For embedded applications, always put an object in read-only data
8002 if possible, in order to reduce RAM usage. */
8004 if (((TREE_CODE (decl) == VAR_DECL
8005 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
8006 && DECL_INITIAL (decl)
8007 && (DECL_INITIAL (decl) == error_mark_node
8008 || TREE_CONSTANT (DECL_INITIAL (decl))))
8009 /* Deal with calls from output_constant_def_contents. */
8010 || (TREE_CODE (decl) != VAR_DECL
8011 && (TREE_CODE (decl) != STRING_CST
8012 || !flag_writable_strings)))
8013 && ! (flag_pic && reloc))
8014 readonly_data_section ();
8015 else if (size > 0 && size <= mips_section_threshold)
8016 SMALL_DATA_SECTION ();
8022 /* For hosted applications, always put an object in small data if
8023 possible, as this gives the best performance. */
8025 if (size > 0 && size <= mips_section_threshold)
8026 SMALL_DATA_SECTION ();
8027 else if (((TREE_CODE (decl) == VAR_DECL
8028 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
8029 && DECL_INITIAL (decl)
8030 && (DECL_INITIAL (decl) == error_mark_node
8031 || TREE_CONSTANT (DECL_INITIAL (decl))))
8032 /* Deal with calls from output_constant_def_contents. */
8033 || (TREE_CODE (decl) != VAR_DECL
8034 && (TREE_CODE (decl) != STRING_CST
8035 || !flag_writable_strings)))
8036 && ! (flag_pic && reloc))
8037 readonly_data_section ();
8043 /* When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
8046 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
8047 symbols which are not in the .text section.
8049 When generating mips16 code, SYMBOL_REF_FLAG is set for string
8050 constants which are put in the .text section. We also record the
8051 total length of all such strings; this total is used to decide
8052 whether we need to split the constant table, and need not be
8055 When not mips16 code nor embedded PIC, if a symbol is in a
8056 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
8057 splitting the reference so that gas can generate a gp relative
8060 When TARGET_EMBEDDED_DATA is set, we assume that all const
8061 variables will be stored in ROM, which is too far from %gp to use
8062 %gprel addressing. Note that (1) we include "extern const"
8063 variables in this, which mips_select_section doesn't, and (2) we
8064 can't always tell if they're really const (they might be const C++
8065 objects with non-const constructors), so we err on the side of
8066 caution and won't use %gprel anyway (otherwise we'd have to defer
8067 this decision to the linker/loader). The handling of extern consts
8068 is why the DECL_INITIAL macros differ from mips_select_section. */
8071 mips_encode_section_info (decl, first)
8077 if (first && TREE_CODE (decl) == STRING_CST
8078 && ! flag_writable_strings
8079 /* If this string is from a function, and the function will
8080 go in a gnu linkonce section, then we can't directly
8081 access the string. This gets an assembler error
8082 "unsupported PC relative reference to different section".
8083 If we modify SELECT_SECTION to put it in function_section
8084 instead of text_section, it still fails because
8085 DECL_SECTION_NAME isn't set until assemble_start_function.
8086 If we fix that, it still fails because strings are shared
8087 among multiple functions, and we have cross section
8088 references again. We force it to work by putting string
8089 addresses in the constant pool and indirecting. */
8090 && (! current_function_decl
8091 || ! DECL_ONE_ONLY (current_function_decl)))
8093 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl), 0)) = 1;
8094 mips_string_length += TREE_STRING_LENGTH (decl);
8098 if (TARGET_EMBEDDED_DATA
8099 && (TREE_CODE (decl) == VAR_DECL
8100 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl))
8101 && (!DECL_INITIAL (decl)
8102 || TREE_CONSTANT (DECL_INITIAL (decl))))
8104 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 0;
8107 else if (TARGET_EMBEDDED_PIC)
8109 if (TREE_CODE (decl) == VAR_DECL)
8110 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8111 else if (TREE_CODE (decl) == FUNCTION_DECL)
8112 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 0;
8113 else if (TREE_CODE (decl) == STRING_CST
8114 && ! flag_writable_strings)
8115 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl), 0)) = 0;
8117 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (decl), 0)) = 1;
8120 else if (TREE_CODE (decl) == VAR_DECL
8121 && DECL_SECTION_NAME (decl) != NULL_TREE
8122 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
8124 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (decl)),
8127 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8130 /* We can not perform GP optimizations on variables which are in
8131 specific sections, except for .sdata and .sbss which are
8133 else if (TARGET_GP_OPT && TREE_CODE (decl) == VAR_DECL
8134 && DECL_SECTION_NAME (decl) == NULL_TREE
8135 && ! (TARGET_MIPS16 && TREE_PUBLIC (decl)
8136 && (DECL_COMMON (decl)
8137 || DECL_ONE_ONLY (decl)
8138 || DECL_WEAK (decl))))
8140 int size = int_size_in_bytes (TREE_TYPE (decl));
8142 if (size > 0 && size <= mips_section_threshold)
8143 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
8148 /* Return register to use for a function return value with VALTYPE for
8149 function FUNC. MODE is used instead of VALTYPE for LIBCALLs. */
8152 mips_function_value (valtype, func, mode)
8154 tree func ATTRIBUTE_UNUSED;
8155 enum machine_mode mode;
8157 int reg = GP_RETURN;
8158 enum mode_class mclass;
8163 mode = TYPE_MODE (valtype);
8164 unsignedp = TREE_UNSIGNED (valtype);
8166 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
8167 the mode just as PROMOTE_MODE does. */
8168 mode = promote_mode (valtype, mode, &unsignedp, 1);
8170 mclass = GET_MODE_CLASS (mode);
8172 if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
8175 else if (mclass == MODE_COMPLEX_FLOAT
8176 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE * 2)
8178 enum machine_mode cmode = GET_MODE_INNER (mode);
8180 return gen_rtx_PARALLEL
8183 gen_rtx_EXPR_LIST (VOIDmode,
8184 gen_rtx_REG (cmode, FP_RETURN),
8186 gen_rtx_EXPR_LIST (VOIDmode,
8187 gen_rtx_REG (cmode, FP_RETURN + FP_INC),
8188 GEN_INT (GET_MODE_SIZE (cmode)))));
8191 else if (valtype && TREE_CODE (valtype) == RECORD_TYPE
8192 && mips_abi != ABI_32
8193 && mips_abi != ABI_O64
8194 && mips_abi != ABI_EABI)
8196 /* A struct with only one or two floating point fields is returned in
8197 the floating point registers. */
8198 tree field, fields[2];
8201 for (i = 0, field = TYPE_FIELDS (valtype); field;
8202 field = TREE_CHAIN (field))
8204 if (TREE_CODE (field) != FIELD_DECL)
8207 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
8210 fields[i++] = field;
8213 /* Must check i, so that we reject structures with no elements. */
8218 /* The structure has DImode, but we don't allow DImode values
8219 in FP registers, so we use a PARALLEL even though it isn't
8220 strictly necessary. */
8221 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
8223 return gen_rtx_PARALLEL
8226 gen_rtx_EXPR_LIST (VOIDmode,
8227 gen_rtx_REG (field_mode,
8234 enum machine_mode first_mode
8235 = TYPE_MODE (TREE_TYPE (fields[0]));
8236 enum machine_mode second_mode
8237 = TYPE_MODE (TREE_TYPE (fields[1]));
8238 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
8239 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
8241 return gen_rtx_PARALLEL
8244 gen_rtx_EXPR_LIST (VOIDmode,
8245 gen_rtx_REG (first_mode,
8247 GEN_INT (first_offset)),
8248 gen_rtx_EXPR_LIST (VOIDmode,
8249 gen_rtx_REG (second_mode,
8251 GEN_INT (second_offset))));
8256 return gen_rtx_REG (mode, reg);
8259 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
8260 nonzero when an argument must be passed by reference. */
8263 function_arg_pass_by_reference (cum, mode, type, named)
8264 const CUMULATIVE_ARGS *cum;
8265 enum machine_mode mode;
8267 int named ATTRIBUTE_UNUSED;
8271 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
8274 /* We must pass by reference if we would be both passing in registers
8275 and the stack. This is because any subsequent partial arg would be
8276 handled incorrectly in this case.
8278 ??? This is really a kludge. We should either fix GCC so that such
8279 a situation causes an abort and then do something in the MIPS port
8280 to prevent it, or add code to function.c to properly handle the case. */
8281 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
8282 here hopefully is not relevant to mips_va_arg. */
8283 if (cum && MUST_PASS_IN_STACK (mode, type)
8284 && mips_abi != ABI_MEABI
8285 && FUNCTION_ARG (*cum, mode, type, named) != 0)
8288 /* Otherwise, we only do this if EABI is selected. */
8289 if (mips_abi != ABI_EABI)
8292 /* ??? How should SCmode be handled? */
8293 if (type == NULL_TREE || mode == DImode || mode == DFmode)
8296 size = int_size_in_bytes (type);
8297 return size == -1 || size > UNITS_PER_WORD;
8300 /* This function returns the register class required for a secondary
8301 register when copying between one of the registers in CLASS, and X,
8302 using MODE. If IN_P is nonzero, the copy is going from X to the
8303 register, otherwise the register is the source. A return value of
8304 NO_REGS means that no secondary register is required. */
8307 mips_secondary_reload_class (class, mode, x, in_p)
8308 enum reg_class class;
8309 enum machine_mode mode;
8313 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
8317 if (GET_CODE (x) == SIGN_EXTEND)
8323 /* We may be called with reg_renumber NULL from regclass.
8324 ??? This is probably a bug. */
8326 regno = true_regnum (x);
8329 while (GET_CODE (x) == SUBREG)
8331 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
8332 GET_MODE (SUBREG_REG (x)),
8338 if (GET_CODE (x) == REG)
8339 regno = REGNO (x) + off;
8342 /* 64-bit floating-point registers don't store 32-bit values
8343 in sign-extended form. The only way we can reload
8344 (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
8345 an integer register using a 32-bit move. */
8346 if (FP_REG_P (regno))
8347 return (class == GR_REGS ? NO_REGS : GR_REGS);
8349 /* For the same reason, we can only reload (sign_extend:DI FOO) into
8350 a floating-point register when FOO is an integer register. */
8351 if (class == FP_REGS)
8352 return (GP_REG_P (regno) ? NO_REGS : GR_REGS);
8355 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
8356 regno = true_regnum (x);
8358 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
8360 /* We always require a general register when copying anything to
8361 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
8362 to a general register, or when copying from register 0. */
8363 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
8366 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8367 ? NO_REGS : gr_regs);
8368 else if (regno == HILO_REGNUM)
8371 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
8372 ? NO_REGS : gr_regs);
8374 /* Copying from HI or LO to anywhere other than a general register
8375 requires a general register. */
8376 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8378 if (TARGET_MIPS16 && in_p)
8380 /* We can't really copy to HI or LO at all in mips16 mode. */
8383 return gp_reg_p ? NO_REGS : gr_regs;
8385 if (MD_REG_P (regno))
8387 if (TARGET_MIPS16 && ! in_p)
8389 /* We can't really copy to HI or LO at all in mips16 mode. */
8392 return class == gr_regs ? NO_REGS : gr_regs;
8395 /* We can only copy a value to a condition code register from a
8396 floating point register, and even then we require a scratch
8397 floating point register. We can only copy a value out of a
8398 condition code register into a general register. */
8399 if (class == ST_REGS)
8403 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8405 if (ST_REG_P (regno))
8409 return class == GR_REGS ? NO_REGS : GR_REGS;
8412 if (class == FP_REGS)
8414 if (GET_CODE (x) == MEM)
8416 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
8419 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
8421 /* We can use the l.s and l.d macros to load floating-point
8422 constants. ??? For l.s, we could probably get better
8423 code by returning GR_REGS here. */
8426 else if (GP_REG_P (regno) || x == CONST0_RTX (mode))
8428 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
8431 else if (FP_REG_P (regno))
8433 /* In this case we can use mov.s or mov.d. */
8438 /* Otherwise, we need to reload through an integer register. */
8443 /* In mips16 mode, going between memory and anything but M16_REGS
8444 requires an M16_REG. */
8447 if (class != M16_REGS && class != M16_NA_REGS)
8455 /* The stack pointer isn't a valid operand to an add instruction,
8456 so we need to load it into M16_REGS first. This can happen as
8457 a result of register elimination and form_sum converting
8458 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8459 need an extra register if the dest is the same as the other
8460 register. In that case, we can't fix the problem by loading SP
8461 into the dest first. */
8462 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8463 && GET_CODE (XEXP (x, 1)) == REG
8464 && (XEXP (x, 0) == stack_pointer_rtx
8465 || XEXP (x, 1) == stack_pointer_rtx))
8466 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8468 if (class == M16_REGS || class == M16_NA_REGS)
8477 /* This function returns the maximum number of consecutive registers
8478 needed to represent mode MODE in registers of class CLASS. */
8481 mips_class_max_nregs (class, mode)
8482 enum reg_class class;
8483 enum machine_mode mode;
8485 if (class == FP_REGS)
8488 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8491 /* For each mips16 function which refers to GP relative symbols, we
8492 use a pseudo register, initialized at the start of the function, to
8493 hold the $gp value. */
8496 mips16_gp_pseudo_reg ()
8498 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
8503 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8504 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
8506 /* We want to initialize this to a value which gcc will believe
8508 const_gp = gen_rtx (CONST, Pmode,
8509 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8512 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
8514 insn = get_insns ();
8517 push_topmost_sequence ();
8518 /* We need to emit the initialization after the FUNCTION_BEG
8519 note, so that it will be integrated. */
8520 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8521 if (GET_CODE (scan) == NOTE
8522 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8524 if (scan == NULL_RTX)
8525 scan = get_insns ();
8526 insn = emit_insn_after (insn, scan);
8527 pop_topmost_sequence ();
8530 return cfun->machine->mips16_gp_pseudo_rtx;
8533 /* Return an RTX which represents the signed 16 bit offset from the
8534 $gp register for the given symbol. This is only used on the
8538 mips16_gp_offset (sym)
8543 if (GET_CODE (sym) != SYMBOL_REF
8544 || ! SYMBOL_REF_FLAG (sym))
8547 /* We use a special identifier to represent the value of the gp
8549 gp = get_identifier ("__mips16_gp_value");
8551 return gen_rtx (CONST, Pmode,
8552 gen_rtx (MINUS, Pmode, sym,
8553 gen_rtx (SYMBOL_REF, Pmode,
8554 IDENTIFIER_POINTER (gp))));
8557 /* Return nonzero if the given RTX represents a signed 16 bit offset
8558 from the $gp register. */
8561 mips16_gp_offset_p (x)
8564 if (GET_CODE (x) == CONST)
8567 /* It's OK to add a small integer value to a gp offset. */
8568 if (GET_CODE (x) == PLUS)
8570 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8571 && SMALL_INT (XEXP (x, 1)))
8572 return mips16_gp_offset_p (XEXP (x, 0));
8573 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8574 && SMALL_INT (XEXP (x, 0)))
8575 return mips16_gp_offset_p (XEXP (x, 1));
8579 /* Make sure it is in the form SYM - __mips16_gp_value. */
8580 return (GET_CODE (x) == MINUS
8581 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8582 && SYMBOL_REF_FLAG (XEXP (x, 0))
8583 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8584 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8587 /* Output a GP offset. We don't want to print the subtraction of
8588 __mips16_gp_value; it is implicitly represented by the %gprel which
8589 should have been printed by the caller. */
8592 mips16_output_gp_offset (file, x)
8596 if (GET_CODE (x) == CONST)
8599 if (GET_CODE (x) == PLUS)
8601 mips16_output_gp_offset (file, XEXP (x, 0));
8603 mips16_output_gp_offset (file, XEXP (x, 1));
8607 if (GET_CODE (x) == MINUS
8608 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8609 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8611 mips16_output_gp_offset (file, XEXP (x, 0));
8615 output_addr_const (file, x);
8618 /* Return nonzero if a constant should not be output until after the
8619 function. This is true of most string constants, so that we can
8620 use a more efficient PC relative reference. However, a static
8621 inline function may never call assemble_function_end to write out
8622 the constant pool, so don't try to postpone the constant in that
8625 ??? It's really a bug that a static inline function can put stuff
8626 in the constant pool even if the function itself is not output.
8628 We record which string constants we've seen, so that we know which
8629 ones might use the more efficient reference. */
8632 mips16_constant_after_function_p (x)
8635 if (TREE_CODE (x) == STRING_CST
8636 && ! flag_writable_strings
8637 && current_function_decl != 0
8638 && ! DECL_DEFER_OUTPUT (current_function_decl)
8639 && ! (DECL_INLINE (current_function_decl)
8640 && ((! TREE_PUBLIC (current_function_decl)
8641 && ! TREE_ADDRESSABLE (current_function_decl)
8642 && ! flag_keep_inline_functions)
8643 || DECL_EXTERNAL (current_function_decl))))
8645 struct string_constant *n;
8647 n = (struct string_constant *) xmalloc (sizeof *n);
8648 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8649 n->next = string_constants;
8650 string_constants = n;
8658 /* Validate a constant for the mips16. This rejects general symbolic
8659 addresses, which must be loaded from memory. If ADDR is nonzero,
8660 this should reject anything which is not a legal address. If
8661 ADDEND is nonzero, this is being added to something else. */
8664 mips16_constant (x, mode, addr, addend)
8666 enum machine_mode mode;
8670 while (GET_CODE (x) == CONST)
8673 switch (GET_CODE (x))
8679 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8680 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8683 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8685 if (CONSTANT_POOL_ADDRESS_P (x))
8688 /* If we aren't looking for a memory address, we can accept a GP
8689 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8690 knows how to handle this. We can always accept a string
8691 constant, which is the other case in which SYMBOL_REF_FLAG
8695 && SYMBOL_REF_FLAG (x)
8696 && mode == (enum machine_mode) Pmode)
8699 /* We can accept a string constant, which will have
8700 SYMBOL_REF_FLAG set but must be recognized by name to
8701 distinguish from a GP accessible symbol. The name of a
8702 string constant will have been generated by
8703 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8704 if (SYMBOL_REF_FLAG (x))
8706 const char *name = XSTR (x, 0);
8708 return (name[0] == '*'
8709 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8710 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8716 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8721 if (addr && ! addend)
8723 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8726 /* We need to treat $gp as a legitimate constant, because
8727 mips16_gp_pseudo_reg assumes that. */
8728 return REGNO (x) == GP_REG_FIRST + 28;
8732 /* Write out code to move floating point arguments in or out of
8733 general registers. Output the instructions to FILE. FP_CODE is
8734 the code describing which arguments are present (see the comment at
8735 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8736 we are copying from the floating point registers. */
8739 mips16_fp_args (file, fp_code, from_fp_p)
8748 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8749 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8756 gparg = GP_ARG_FIRST;
8757 fparg = FP_ARG_FIRST;
8758 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8762 if ((fparg & 1) != 0)
8764 fprintf (file, "\t%s\t%s,%s\n", s,
8765 reg_names[gparg], reg_names[fparg]);
8767 else if ((f & 3) == 2)
8770 fprintf (file, "\td%s\t%s,%s\n", s,
8771 reg_names[gparg], reg_names[fparg]);
8774 if ((fparg & 1) != 0)
8776 if (TARGET_BIG_ENDIAN)
8777 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8778 reg_names[gparg], reg_names[fparg + 1], s,
8779 reg_names[gparg + 1], reg_names[fparg]);
8781 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8782 reg_names[gparg], reg_names[fparg], s,
8783 reg_names[gparg + 1], reg_names[fparg + 1]);
8796 /* Build a mips16 function stub. This is used for functions which
8797 take aruments in the floating point registers. It is 32 bit code
8798 that moves the floating point args into the general registers, and
8799 then jumps to the 16 bit code. */
8802 build_mips16_function_stub (file)
8806 char *secname, *stubname;
8807 tree stubid, stubdecl;
8811 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8812 secname = (char *) alloca (strlen (fnname) + 20);
8813 sprintf (secname, ".mips16.fn.%s", fnname);
8814 stubname = (char *) alloca (strlen (fnname) + 20);
8815 sprintf (stubname, "__fn_stub_%s", fnname);
8816 stubid = get_identifier (stubname);
8817 stubdecl = build_decl (FUNCTION_DECL, stubid,
8818 build_function_type (void_type_node, NULL_TREE));
8819 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8821 fprintf (file, "\t# Stub function for %s (", current_function_name);
8823 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8825 fprintf (file, "%s%s",
8826 need_comma ? ", " : "",
8827 (f & 3) == 1 ? "float" : "double");
8830 fprintf (file, ")\n");
8832 fprintf (file, "\t.set\tnomips16\n");
8833 function_section (stubdecl);
8834 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8836 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8837 within a .ent, and we can not emit another .ent. */
8838 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8839 fputs ("\t.ent\t", file);
8840 assemble_name (file, stubname);
8844 assemble_name (file, stubname);
8845 fputs (":\n", file);
8847 /* We don't want the assembler to insert any nops here. */
8848 fprintf (file, "\t.set\tnoreorder\n");
8850 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8852 fprintf (asm_out_file, "\t.set\tnoat\n");
8853 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8854 assemble_name (file, fnname);
8855 fprintf (file, "\n");
8856 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8857 fprintf (asm_out_file, "\t.set\tat\n");
8859 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8860 with one of the mfc1 instructions, because the result is not
8861 available for one instruction, so if the very first instruction
8862 in the function refers to the register, it will see the wrong
8864 fprintf (file, "\tnop\n");
8866 fprintf (file, "\t.set\treorder\n");
8868 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8869 fputs ("\t.end\t", file);
8870 assemble_name (file, stubname);
8874 fprintf (file, "\t.set\tmips16\n");
8876 function_section (current_function_decl);
8879 /* We keep a list of functions for which we have already built stubs
8880 in build_mips16_call_stub. */
8884 struct mips16_stub *next;
8889 static struct mips16_stub *mips16_stubs;
8891 /* Build a call stub for a mips16 call. A stub is needed if we are
8892 passing any floating point values which should go into the floating
8893 point registers. If we are, and the call turns out to be to a 32
8894 bit function, the stub will be used to move the values into the
8895 floating point registers before calling the 32 bit function. The
8896 linker will magically adjust the function call to either the 16 bit
8897 function or the 32 bit stub, depending upon where the function call
8898 is actually defined.
8900 Similarly, we need a stub if the return value might come back in a
8901 floating point register.
8903 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8904 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8905 is the code built by function_arg. This function returns a nonzero
8906 value if it builds the call instruction itself. */
8909 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8918 char *secname, *stubname;
8919 struct mips16_stub *l;
8920 tree stubid, stubdecl;
8924 /* We don't need to do anything if we aren't in mips16 mode, or if
8925 we were invoked with the -msoft-float option. */
8926 if (! TARGET_MIPS16 || ! mips16_hard_float)
8929 /* Figure out whether the value might come back in a floating point
8931 fpret = (retval != 0
8932 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8933 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
8935 /* We don't need to do anything if there were no floating point
8936 arguments and the value will not be returned in a floating point
8938 if (fp_code == 0 && ! fpret)
8941 if (GET_CODE (fnmem) != MEM)
8943 fn = XEXP (fnmem, 0);
8945 /* We don't need to do anything if this is a call to a special
8946 mips16 support function. */
8947 if (GET_CODE (fn) == SYMBOL_REF
8948 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8951 /* This code will only work for o32 and o64 abis. The other ABI's
8952 require more sophisticated support. */
8953 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8956 /* We can only handle SFmode and DFmode floating point return
8958 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8961 /* If we're calling via a function pointer, then we must always call
8962 via a stub. There are magic stubs provided in libgcc.a for each
8963 of the required cases. Each of them expects the function address
8964 to arrive in register $2. */
8966 if (GET_CODE (fn) != SYMBOL_REF)
8970 rtx stub_fn, stub_mem, insn;
8972 /* ??? If this code is modified to support other ABI's, we need
8973 to handle PARALLEL return values here. */
8975 sprintf (buf, "__mips16_call_stub_%s%d",
8977 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8980 id = get_identifier (buf);
8981 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8982 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8984 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8986 if (retval == NULL_RTX)
8987 insn = gen_call_internal0 (stub_mem, arg_size,
8988 gen_rtx (REG, SImode,
8989 GP_REG_FIRST + 31));
8991 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8992 gen_rtx (REG, SImode,
8993 GP_REG_FIRST + 31));
8994 insn = emit_call_insn (insn);
8996 /* Put the register usage information on the CALL. */
8997 if (GET_CODE (insn) != CALL_INSN)
8999 CALL_INSN_FUNCTION_USAGE (insn) =
9000 gen_rtx (EXPR_LIST, VOIDmode,
9001 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
9002 CALL_INSN_FUNCTION_USAGE (insn));
9004 /* If we are handling a floating point return value, we need to
9005 save $18 in the function prologue. Putting a note on the
9006 call will mean that regs_ever_live[$18] will be true if the
9007 call is not eliminated, and we can check that in the prologue
9010 CALL_INSN_FUNCTION_USAGE (insn) =
9011 gen_rtx (EXPR_LIST, VOIDmode,
9012 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9013 CALL_INSN_FUNCTION_USAGE (insn));
9015 /* Return 1 to tell the caller that we've generated the call
9020 /* We know the function we are going to call. If we have already
9021 built a stub, we don't need to do anything further. */
9023 fnname = XSTR (fn, 0);
9024 for (l = mips16_stubs; l != NULL; l = l->next)
9025 if (strcmp (l->name, fnname) == 0)
9030 /* Build a special purpose stub. When the linker sees a
9031 function call in mips16 code, it will check where the target
9032 is defined. If the target is a 32 bit call, the linker will
9033 search for the section defined here. It can tell which
9034 symbol this section is associated with by looking at the
9035 relocation information (the name is unreliable, since this
9036 might be a static function). If such a section is found, the
9037 linker will redirect the call to the start of the magic
9040 If the function does not return a floating point value, the
9041 special stub section is named
9044 If the function does return a floating point value, the stub
9046 .mips16.call.fp.FNNAME
9049 secname = (char *) alloca (strlen (fnname) + 40);
9050 sprintf (secname, ".mips16.call.%s%s",
9053 stubname = (char *) alloca (strlen (fnname) + 20);
9054 sprintf (stubname, "__call_stub_%s%s",
9057 stubid = get_identifier (stubname);
9058 stubdecl = build_decl (FUNCTION_DECL, stubid,
9059 build_function_type (void_type_node, NULL_TREE));
9060 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
9062 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
9064 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
9068 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
9070 fprintf (asm_out_file, "%s%s",
9071 need_comma ? ", " : "",
9072 (f & 3) == 1 ? "float" : "double");
9075 fprintf (asm_out_file, ")\n");
9077 fprintf (asm_out_file, "\t.set\tnomips16\n");
9078 assemble_start_function (stubdecl, stubname);
9080 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9081 fputs ("\t.ent\t", asm_out_file);
9082 assemble_name (asm_out_file, stubname);
9083 fputs ("\n", asm_out_file);
9085 assemble_name (asm_out_file, stubname);
9086 fputs (":\n", asm_out_file);
9089 /* We build the stub code by hand. That's the only way we can
9090 do it, since we can't generate 32 bit code during a 16 bit
9093 /* We don't want the assembler to insert any nops here. */
9094 fprintf (asm_out_file, "\t.set\tnoreorder\n");
9096 mips16_fp_args (asm_out_file, fp_code, 0);
9100 fprintf (asm_out_file, "\t.set\tnoat\n");
9101 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
9103 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
9104 fprintf (asm_out_file, "\t.set\tat\n");
9105 /* Unfortunately, we can't fill the jump delay slot. We
9106 can't fill with one of the mtc1 instructions, because the
9107 result is not available for one instruction, so if the
9108 very first instruction in the function refers to the
9109 register, it will see the wrong value. */
9110 fprintf (asm_out_file, "\tnop\n");
9114 fprintf (asm_out_file, "\tmove\t%s,%s\n",
9115 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
9116 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
9117 /* As above, we can't fill the delay slot. */
9118 fprintf (asm_out_file, "\tnop\n");
9119 if (GET_MODE (retval) == SFmode)
9120 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9121 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
9124 if (TARGET_BIG_ENDIAN)
9126 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9127 reg_names[GP_REG_FIRST + 2],
9128 reg_names[FP_REG_FIRST + 1]);
9129 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9130 reg_names[GP_REG_FIRST + 3],
9131 reg_names[FP_REG_FIRST + 0]);
9135 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9136 reg_names[GP_REG_FIRST + 2],
9137 reg_names[FP_REG_FIRST + 0]);
9138 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
9139 reg_names[GP_REG_FIRST + 3],
9140 reg_names[FP_REG_FIRST + 1]);
9143 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
9144 /* As above, we can't fill the delay slot. */
9145 fprintf (asm_out_file, "\tnop\n");
9148 fprintf (asm_out_file, "\t.set\treorder\n");
9150 #ifdef ASM_DECLARE_FUNCTION_SIZE
9151 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
9154 #ifndef FUNCTION_NAME_ALREADY_DECLARED
9155 fputs ("\t.end\t", asm_out_file);
9156 assemble_name (asm_out_file, stubname);
9157 fputs ("\n", asm_out_file);
9160 fprintf (asm_out_file, "\t.set\tmips16\n");
9162 /* Record this stub. */
9163 l = (struct mips16_stub *) xmalloc (sizeof *l);
9164 l->name = xstrdup (fnname);
9166 l->next = mips16_stubs;
9170 /* If we expect a floating point return value, but we've built a
9171 stub which does not expect one, then we're in trouble. We can't
9172 use the existing stub, because it won't handle the floating point
9173 value. We can't build a new stub, because the linker won't know
9174 which stub to use for the various calls in this object file.
9175 Fortunately, this case is illegal, since it means that a function
9176 was declared in two different ways in a single compilation. */
9177 if (fpret && ! l->fpret)
9178 error ("can not handle inconsistent calls to `%s'", fnname);
9180 /* If we are calling a stub which handles a floating point return
9181 value, we need to arrange to save $18 in the prologue. We do
9182 this by marking the function call as using the register. The
9183 prologue will later see that it is used, and emit code to save
9190 if (retval == NULL_RTX)
9191 insn = gen_call_internal0 (fnmem, arg_size,
9192 gen_rtx (REG, SImode,
9193 GP_REG_FIRST + 31));
9195 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
9196 gen_rtx (REG, SImode,
9197 GP_REG_FIRST + 31));
9198 insn = emit_call_insn (insn);
9200 if (GET_CODE (insn) != CALL_INSN)
9203 CALL_INSN_FUNCTION_USAGE (insn) =
9204 gen_rtx (EXPR_LIST, VOIDmode,
9205 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
9206 CALL_INSN_FUNCTION_USAGE (insn));
9208 /* Return 1 to tell the caller that we've generated the call
9213 /* Return 0 to let the caller generate the call insn. */
9217 /* This function looks through the code for a function, and tries to
9218 optimize the usage of the $gp register. We arrange to copy $gp
9219 into a pseudo-register, and then let gcc's normal reload handling
9220 deal with the pseudo-register. Unfortunately, if reload choose to
9221 put the pseudo-register into a call-clobbered register, it will
9222 emit saves and restores for that register around any function
9223 calls. We don't need the saves, and it's faster to copy $gp than
9224 to do an actual restore. ??? This still means that we waste a
9227 This is an optimization, and the code which gcc has actually
9228 generated is correct, so we do not need to catch all cases. */
9231 mips16_optimize_gp (first)
9234 rtx gpcopy, slot, insn;
9236 /* Look through the instructions. Set GPCOPY to the register which
9237 holds a copy of $gp. Set SLOT to the stack slot where it is
9238 saved. If we find an instruction which sets GPCOPY to anything
9239 other than $gp or SLOT, then we can't use it. If we find an
9240 instruction which sets SLOT to anything other than GPCOPY, we
9245 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9249 if (! INSN_P (insn))
9252 set = PATTERN (insn);
9254 /* We know that all references to memory will be inside a SET,
9255 because there is no other way to access memory on the mips16.
9256 We don't have to worry about a PARALLEL here, because the
9257 mips.md file will never generate them for memory references. */
9258 if (GET_CODE (set) != SET)
9261 if (gpcopy == NULL_RTX
9262 && GET_CODE (SET_SRC (set)) == CONST
9263 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
9264 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
9265 && GET_CODE (SET_DEST (set)) == REG
9266 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9267 gpcopy = SET_DEST (set);
9268 else if (slot == NULL_RTX
9269 && gpcopy != NULL_RTX
9270 && GET_CODE (SET_DEST (set)) == MEM
9271 && GET_CODE (SET_SRC (set)) == REG
9272 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
9273 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
9277 offset = const0_rtx;
9278 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
9279 if (GET_CODE (base) == REG
9280 && (REGNO (base) == STACK_POINTER_REGNUM
9281 || REGNO (base) == FRAME_POINTER_REGNUM))
9282 slot = SET_DEST (set);
9284 else if (gpcopy != NULL_RTX
9285 && (GET_CODE (SET_DEST (set)) == REG
9286 || GET_CODE (SET_DEST (set)) == SUBREG)
9287 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
9288 && (GET_CODE (SET_DEST (set)) != REG
9289 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
9290 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
9291 || ((GET_CODE (SET_SRC (set)) != CONST
9292 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
9293 || (REGNO (XEXP (SET_SRC (set), 0))
9294 != GP_REG_FIRST + 28))
9295 && ! rtx_equal_p (SET_SRC (set), slot))))
9297 else if (slot != NULL_RTX
9298 && GET_CODE (SET_DEST (set)) == MEM
9299 && rtx_equal_p (SET_DEST (set), slot)
9300 && (GET_CODE (SET_SRC (set)) != REG
9301 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
9305 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
9306 different optimization. Any time we find a copy of $28 into a
9307 register, followed by an add of a symbol_ref to that register, we
9308 convert it to load the value from the constant table instead.
9309 The copy and add will take six bytes, just as the load and
9310 constant table entry will take six bytes. However, it is
9311 possible that the constant table entry will be shared.
9313 This could be a peephole optimization, but I don't know if the
9314 peephole code can call force_const_mem.
9316 Using the same register for the copy of $28 and the add of the
9317 symbol_ref is actually pretty likely, since the add instruction
9318 requires the destination and the first addend to be the same
9321 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
9325 /* This optimization is only reasonable if the constant table
9326 entries are only 4 bytes. */
9327 if (Pmode != SImode)
9330 for (insn = first; insn != NULL_RTX; insn = next)
9337 next = NEXT_INSN (next);
9339 while (next != NULL_RTX
9340 && (GET_CODE (next) == NOTE
9341 || (GET_CODE (next) == INSN
9342 && (GET_CODE (PATTERN (next)) == USE
9343 || GET_CODE (PATTERN (next)) == CLOBBER))));
9345 if (next == NULL_RTX)
9348 if (! INSN_P (insn))
9351 if (! INSN_P (next))
9354 set1 = PATTERN (insn);
9355 if (GET_CODE (set1) != SET)
9357 set2 = PATTERN (next);
9358 if (GET_CODE (set2) != SET)
9361 if (GET_CODE (SET_DEST (set1)) == REG
9362 && GET_CODE (SET_SRC (set1)) == CONST
9363 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
9364 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
9365 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
9366 && GET_CODE (SET_SRC (set2)) == PLUS
9367 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
9368 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
9369 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
9373 /* We've found a case we can change to load from the
9376 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
9377 if (GET_CODE (sym) != SYMBOL_REF)
9379 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
9380 force_const_mem (Pmode, sym)),
9383 PUT_CODE (insn, NOTE);
9384 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9385 NOTE_SOURCE_FILE (insn) = 0;
9387 PUT_CODE (next, NOTE);
9388 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
9389 NOTE_SOURCE_FILE (next) = 0;
9396 /* We can safely remove all assignments to SLOT from GPCOPY, and
9397 replace all assignments from SLOT to GPCOPY with assignments from
9400 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
9404 if (! INSN_P (insn))
9407 set = PATTERN (insn);
9408 if (GET_CODE (set) != SET
9409 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
9412 if (GET_CODE (SET_DEST (set)) == MEM
9413 && rtx_equal_p (SET_DEST (set), slot)
9414 && GET_CODE (SET_SRC (set)) == REG
9415 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
9417 PUT_CODE (insn, NOTE);
9418 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9419 NOTE_SOURCE_FILE (insn) = 0;
9421 else if (GET_CODE (SET_DEST (set)) == REG
9422 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9423 && GET_CODE (SET_SRC (set)) == MEM
9424 && rtx_equal_p (SET_SRC (set), slot))
9426 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9427 gen_rtx (CONST, Pmode,
9428 gen_rtx (REG, Pmode,
9429 GP_REG_FIRST + 28))),
9431 PUT_CODE (insn, NOTE);
9432 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9433 NOTE_SOURCE_FILE (insn) = 0;
9438 /* We keep a list of constants we which we have to add to internal
9439 constant tables in the middle of large functions. */
9443 struct constant *next;
9446 enum machine_mode mode;
9449 /* Add a constant to the list in *PCONSTANTS. */
9452 add_constant (pconstants, val, mode)
9453 struct constant **pconstants;
9455 enum machine_mode mode;
9459 for (c = *pconstants; c != NULL; c = c->next)
9460 if (mode == c->mode && rtx_equal_p (val, c->value))
9463 c = (struct constant *) xmalloc (sizeof *c);
9466 c->label = gen_label_rtx ();
9467 c->next = *pconstants;
9472 /* Dump out the constants in CONSTANTS after INSN. */
9475 dump_constants (constants, insn)
9476 struct constant *constants;
9487 struct constant *next;
9489 switch (GET_MODE_SIZE (c->mode))
9496 insn = emit_insn_after (gen_align_2 (), insn);
9501 insn = emit_insn_after (gen_align_4 (), insn);
9506 insn = emit_insn_after (gen_align_8 (), insn);
9511 insn = emit_label_after (c->label, insn);
9516 r = gen_consttable_qi (c->value);
9519 r = gen_consttable_hi (c->value);
9522 r = gen_consttable_si (c->value);
9525 r = gen_consttable_sf (c->value);
9528 r = gen_consttable_di (c->value);
9531 r = gen_consttable_df (c->value);
9537 insn = emit_insn_after (r, insn);
9544 emit_barrier_after (insn);
9547 /* Find the symbol in an address expression. */
9550 mips_find_symbol (addr)
9553 if (GET_CODE (addr) == MEM)
9554 addr = XEXP (addr, 0);
9555 while (GET_CODE (addr) == CONST)
9556 addr = XEXP (addr, 0);
9557 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9559 if (GET_CODE (addr) == PLUS)
9563 l1 = mips_find_symbol (XEXP (addr, 0));
9564 l2 = mips_find_symbol (XEXP (addr, 1));
9565 if (l1 != NULL_RTX && l2 == NULL_RTX)
9567 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9573 /* Exported to toplev.c.
9575 Do a final pass over the function, just before delayed branch
9579 machine_dependent_reorg (first)
9582 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9584 struct constant *constants;
9586 if (! TARGET_MIPS16)
9589 /* If $gp is used, try to remove stores, and replace loads with
9592 mips16_optimize_gp (first);
9594 /* Scan the function looking for PC relative loads which may be out
9595 of range. All such loads will either be from the constant table,
9596 or be getting the address of a constant string. If the size of
9597 the function plus the size of the constant table is less than
9598 0x8000, then all loads are in range. */
9601 for (insn = first; insn; insn = NEXT_INSN (insn))
9603 insns_len += get_attr_length (insn);
9605 /* ??? We put switch tables in .text, but we don't define
9606 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9607 compute their lengths correctly. */
9608 if (GET_CODE (insn) == JUMP_INSN)
9612 body = PATTERN (insn);
9613 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9614 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9615 * GET_MODE_SIZE (GET_MODE (body)));
9616 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9620 /* Store the original value of insns_len in cfun->machine, so
9621 that simple_memory_operand can look at it. */
9622 cfun->machine->insns_len = insns_len;
9624 pool_size = get_pool_size ();
9625 if (insns_len + pool_size + mips_string_length < 0x8000)
9628 /* Loop over the insns and figure out what the maximum internal pool
9630 max_internal_pool_size = 0;
9631 for (insn = first; insn; insn = NEXT_INSN (insn))
9633 if (GET_CODE (insn) == INSN
9634 && GET_CODE (PATTERN (insn)) == SET)
9638 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9639 if (src == NULL_RTX)
9641 if (CONSTANT_POOL_ADDRESS_P (src))
9642 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9643 else if (SYMBOL_REF_FLAG (src))
9644 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9650 first_constant_ref = -1;
9652 for (insn = first; insn; insn = NEXT_INSN (insn))
9654 if (GET_CODE (insn) == INSN
9655 && GET_CODE (PATTERN (insn)) == SET)
9658 enum machine_mode mode = VOIDmode;
9661 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9662 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9664 /* ??? This is very conservative, which means that we
9665 will generate too many copies of the constant table.
9666 The only solution would seem to be some form of
9668 if (((insns_len - addr)
9669 + max_internal_pool_size
9670 + get_pool_offset (src))
9673 val = get_pool_constant (src);
9674 mode = get_pool_mode (src);
9676 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9678 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9680 /* Including all of mips_string_length is conservative,
9681 and so is including all of max_internal_pool_size. */
9682 if (((insns_len - addr)
9683 + max_internal_pool_size
9685 + mips_string_length)
9691 max_internal_pool_size -= Pmode;
9694 if (val != NULL_RTX)
9698 /* This PC relative load is out of range. ??? In the
9699 case of a string constant, we are only guessing that
9700 it is range, since we don't know the offset of a
9701 particular string constant. */
9703 lab = add_constant (&constants, val, mode);
9704 newsrc = gen_rtx (MEM, mode,
9705 gen_rtx (LABEL_REF, VOIDmode, lab));
9706 RTX_UNCHANGING_P (newsrc) = 1;
9707 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9708 SET_DEST (PATTERN (insn)),
9710 INSN_CODE (insn) = -1;
9712 if (first_constant_ref < 0)
9713 first_constant_ref = addr;
9717 addr += get_attr_length (insn);
9719 /* ??? We put switch tables in .text, but we don't define
9720 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9721 compute their lengths correctly. */
9722 if (GET_CODE (insn) == JUMP_INSN)
9726 body = PATTERN (insn);
9727 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9728 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9729 * GET_MODE_SIZE (GET_MODE (body)));
9730 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9733 if (GET_CODE (insn) == BARRIER)
9735 /* Output any constants we have accumulated. Note that we
9736 don't need to change ADDR, since its only use is
9737 subtraction from INSNS_LEN, and both would be changed by
9739 ??? If the instructions up to the next barrier reuse a
9740 constant, it would often be better to continue
9742 if (constants != NULL)
9743 dump_constants (constants, insn);
9745 first_constant_ref = -1;
9748 if (constants != NULL
9749 && (NEXT_INSN (insn) == NULL
9750 || (first_constant_ref >= 0
9751 && (((addr - first_constant_ref)
9752 + 2 /* for alignment */
9753 + 2 /* for a short jump insn */
9757 /* If we haven't had a barrier within 0x8000 bytes of a
9758 constant reference or we are at the end of the function,
9759 emit a barrier now. */
9761 rtx label, jump, barrier;
9763 label = gen_label_rtx ();
9764 jump = emit_jump_insn_after (gen_jump (label), insn);
9765 JUMP_LABEL (jump) = label;
9766 LABEL_NUSES (label) = 1;
9767 barrier = emit_barrier_after (jump);
9768 emit_label_after (label, barrier);
9769 first_constant_ref = -1;
9773 /* ??? If we output all references to a constant in internal
9774 constants table, we don't need to output the constant in the real
9775 constant table, but we have no way to prevent that. */
9778 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9780 extend_operator (x, mode)
9782 enum machine_mode mode ATTRIBUTE_UNUSED;
9784 enum rtx_code code = GET_CODE (x);
9785 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9788 /* Accept any operator that can be used to shift the high half of the
9789 input value to the lower half, suitable for truncation. The
9790 remainder (the lower half of the input, and the upper half of the
9791 output) will be discarded. */
9793 highpart_shift_operator (x, mode)
9795 enum machine_mode mode ATTRIBUTE_UNUSED;
9797 enum rtx_code code = GET_CODE (x);
9798 return (code == LSHIFTRT
9804 /* Return a number assessing the cost of moving a register in class
9805 FROM to class TO. The classes are expressed using the enumeration
9806 values such as `GENERAL_REGS'. A value of 2 is the default; other
9807 values are interpreted relative to that.
9809 It is not required that the cost always equal 2 when FROM is the
9810 same as TO; on some machines it is expensive to move between
9811 registers if they are not general registers.
9813 If reload sees an insn consisting of a single `set' between two
9814 hard registers, and if `REGISTER_MOVE_COST' applied to their
9815 classes returns a value of 2, reload does not check to ensure that
9816 the constraints of the insn are met. Setting a cost of other than
9817 2 will allow reload to verify that the constraints are met. You
9818 should do this if the `movM' pattern's constraints do not allow
9821 ??? We make make the cost of moving from HI/LO/HILO/MD into general
9822 registers the same as for one of moving general registers to
9823 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
9824 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
9825 isn't clear if it is wise. And it might not work in all cases. We
9826 could solve the DImode LO reg problem by using a multiply, just
9827 like reload_{in,out}si. We could solve the SImode/HImode HI reg
9828 problem by using divide instructions. divu puts the remainder in
9829 the HI reg, so doing a divide by -1 will move the value in the HI
9830 reg for all values except -1. We could handle that case by using a
9831 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
9832 a compare/branch to test the input value to see which instruction
9833 we need to use. This gets pretty messy, but it is feasible. */
9836 mips_register_move_cost (mode, to, from)
9837 enum machine_mode mode ATTRIBUTE_UNUSED;
9838 enum reg_class to, from;
9840 if (from == M16_REGS && GR_REG_CLASS_P (to))
9842 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
9844 else if (GR_REG_CLASS_P (from))
9848 else if (to == M16_NA_REGS)
9850 else if (GR_REG_CLASS_P (to))
9857 else if (to == FP_REGS)
9859 else if (to == HI_REG || to == LO_REG || to == MD_REGS
9867 else if (COP_REG_CLASS_P (to))
9871 } /* GR_REG_CLASS_P (from) */
9872 else if (from == FP_REGS)
9874 if (GR_REG_CLASS_P (to))
9876 else if (to == FP_REGS)
9878 else if (to == ST_REGS)
9880 } /* from == FP_REGS */
9881 else if (from == HI_REG || from == LO_REG || from == MD_REGS
9882 || from == HILO_REG)
9884 if (GR_REG_CLASS_P (to))
9891 } /* from == HI_REG, etc. */
9892 else if (from == ST_REGS && GR_REG_CLASS_P (to))
9894 else if (COP_REG_CLASS_P (from))
9897 } /* COP_REG_CLASS_P (from) */
9904 /* Return the length of INSN. LENGTH is the initial length computed by
9905 attributes in the machine-description file. */
9908 mips_adjust_insn_length (insn, length)
9912 /* A unconditional jump has an unfilled delay slot if it is not part
9913 of a sequence. A conditional jump normally has a delay slot, but
9914 does not on MIPS16. */
9915 if (simplejump_p (insn)
9916 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9917 || GET_CODE (insn) == CALL_INSN)))
9920 /* All MIPS16 instructions are a measly two bytes. */
9927 /* Output assembly instructions to peform a conditional branch.
9929 INSN is the branch instruction. OPERANDS[0] is the condition.
9930 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9931 of the first operand to the condition. If TWO_OPERANDS_P is
9932 non-zero the comparison takes two operands; OPERANDS[3] will be the
9935 If INVERTED_P is non-zero we are to branch if the condition does
9936 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9938 LENGTH is the length (in bytes) of the sequence we are to generate.
9939 That tells us whether to generate a simple conditional branch, or a
9940 reversed conditional branch around a `jr' instruction. */
9942 mips_output_conditional_branch (insn,
9955 static char buffer[200];
9956 /* The kind of comparison we are doing. */
9957 enum rtx_code code = GET_CODE (operands[0]);
9958 /* Non-zero if the opcode for the comparison needs a `z' indicating
9959 that it is a comparision against zero. */
9961 /* A string to use in the assembly output to represent the first
9963 const char *op1 = "%z2";
9964 /* A string to use in the assembly output to represent the second
9965 operand. Use the hard-wired zero register if there's no second
9967 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9968 /* The operand-printing string for the comparison. */
9969 const char *const comp = (float_p ? "%F0" : "%C0");
9970 /* The operand-printing string for the inverted comparison. */
9971 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9973 /* The MIPS processors (for levels of the ISA at least two), have
9974 "likely" variants of each branch instruction. These instructions
9975 annul the instruction in the delay slot if the branch is not
9977 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9979 if (!two_operands_p)
9981 /* To compute whether than A > B, for example, we normally
9982 subtract B from A and then look at the sign bit. But, if we
9983 are doing an unsigned comparison, and B is zero, we don't
9984 have to do the subtraction. Instead, we can just check to
9985 see if A is non-zero. Thus, we change the CODE here to
9986 reflect the simpler comparison operation. */
9998 /* A condition which will always be true. */
10004 /* A condition which will always be false. */
10010 /* Not a special case. */
10015 /* Relative comparisons are always done against zero. But
10016 equality comparisons are done between two operands, and therefore
10017 do not require a `z' in the assembly language output. */
10018 need_z_p = (!float_p && code != EQ && code != NE);
10019 /* For comparisons against zero, the zero is not provided
10024 /* Begin by terminating the buffer. That way we can always use
10025 strcat to add to it. */
10032 /* Just a simple conditional branch. */
10034 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
10035 inverted_p ? inverted_comp : comp);
10037 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
10038 inverted_p ? inverted_comp : comp,
10039 need_z_p ? "z" : "",
10047 /* Generate a reversed conditional branch around ` j'
10062 rtx target = gen_label_rtx ();
10064 output_asm_insn ("%(%<", 0);
10065 orig_target = operands[1];
10066 operands[1] = target;
10067 /* Generate the reversed comparison. This takes four
10070 sprintf (buffer, "%%*b%s\t%%Z2%%1",
10071 inverted_p ? comp : inverted_comp);
10073 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
10074 inverted_p ? comp : inverted_comp,
10075 need_z_p ? "z" : "",
10078 output_asm_insn (buffer, operands);
10079 operands[1] = orig_target;
10081 output_asm_insn ("nop\n\tj\t%1", operands);
10084 output_asm_insn ("nop", 0);
10087 /* Output delay slot instruction. */
10088 rtx insn = final_sequence;
10089 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
10091 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
10093 output_asm_insn ("%>%)", 0);
10094 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
10095 CODE_LABEL_NUMBER (target));
10099 /* We do not currently use this code. It handles jumps to
10100 arbitrary locations, using `jr', even across a 256MB boundary.
10101 We could add a -mhuge switch, and then use this code instead of
10102 the `j' alternative above when -mhuge was used. */
10107 /* Generate a reversed conditional branch around a `jr'
10121 Not pretty, but allows a conditional branch anywhere in the
10122 32-bit address space. If the original branch is annulled,
10123 then the instruction in the delay slot should be executed
10124 only if the branch is taken. The la instruction is really
10125 a macro which will usually take eight bytes, but sometimes
10126 takes only four, if the instruction to which we're jumping
10127 gets its own entry in the global pointer table, which will
10128 happen if its a case label. The assembler will then
10129 generate only a four-byte sequence, rather than eight, and
10130 there seems to be no way to tell it not to. Thus, we can't
10131 just use a `.+x' addressing form; we don't know what value
10134 So, we resort to using the explicit relocation syntax
10135 available in the assembler and do:
10137 lw $at,%got_page(target)($gp)
10138 daddiu $at,$at,%got_ofst(target)
10140 That way, this always takes up eight bytes, and we can use
10141 the `.+x' form. Of course, these explicit machinations
10142 with relocation will not work with old assemblers. Then
10143 again, neither do out-of-range branches, so we haven't lost
10146 /* The target of the reversed branch. */
10147 const char *const target
10148 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
10149 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
10150 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
10153 strcpy (buffer, "%(%<%[");
10154 c = strchr (buffer, '\0');
10155 /* Generate the reversed comparision. This takes four
10158 sprintf (c, "%%*b%s\t%%Z2%s",
10159 inverted_p ? comp : inverted_comp,
10162 sprintf (c, "%%*b%s%s\t%s%s,%s",
10163 inverted_p ? comp : inverted_comp,
10164 need_z_p ? "z" : "",
10168 c = strchr (buffer, '\0');
10169 /* Generate the load-address, and jump. This takes twelve
10170 bytes, for a total of 16. */
10172 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
10179 /* The delay slot was unfilled. Since we're inside
10180 .noreorder, the assembler will not fill in the NOP for
10181 us, so we must do it ourselves. */
10182 strcat (buffer, "\n\tnop");
10183 strcat (buffer, "%]%>%)");
10196 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
10197 with a final "000" replaced by "k". Ignore case.
10199 Note: this function is shared between GCC and GAS. */
10202 mips_strict_matching_cpu_name_p (canonical, given)
10203 const char *canonical, *given;
10205 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
10206 given++, canonical++;
10208 return ((*given == 0 && *canonical == 0)
10209 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
10213 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
10214 CPU name. We've traditionally allowed a lot of variation here.
10216 Note: this function is shared between GCC and GAS. */
10219 mips_matching_cpu_name_p (canonical, given)
10220 const char *canonical, *given;
10222 /* First see if the name matches exactly, or with a final "000"
10223 turned into "k". */
10224 if (mips_strict_matching_cpu_name_p (canonical, given))
10227 /* If not, try comparing based on numerical designation alone.
10228 See if GIVEN is an unadorned number, or 'r' followed by a number. */
10229 if (TOLOWER (*given) == 'r')
10231 if (!ISDIGIT (*given))
10234 /* Skip over some well-known prefixes in the canonical name,
10235 hoping to find a number there too. */
10236 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
10238 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
10240 else if (TOLOWER (canonical[0]) == 'r')
10243 return mips_strict_matching_cpu_name_p (canonical, given);
10247 /* Parse an option that takes the name of a processor as its argument.
10248 OPTION is the name of the option and CPU_STRING is the argument.
10249 Return the corresponding processor enumeration if the CPU_STRING is
10250 recognized, otherwise report an error and return null.
10252 A similar function exists in GAS. */
10254 static const struct mips_cpu_info *
10255 mips_parse_cpu (option, cpu_string)
10256 const char *option, *cpu_string;
10258 const struct mips_cpu_info *p;
10261 /* In the past, we allowed upper-case CPU names, but it doesn't
10262 work well with the multilib machinery. */
10263 for (s = cpu_string; *s != 0; s++)
10266 warning ("the cpu name must be lower case");
10270 /* 'from-abi' selects the most compatible architecture for the given
10271 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
10272 EABIs, we have to decide whether we're using the 32-bit or 64-bit
10273 version. Look first at the -mgp options, if given, otherwise base
10274 the choice on MASK_64BIT in TARGET_DEFAULT. */
10275 if (strcasecmp (cpu_string, "from-abi") == 0)
10276 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
10277 : ABI_NEEDS_64BIT_REGS ? 3
10278 : (TARGET_64BIT ? 3 : 1));
10280 /* 'default' has traditionally been a no-op. Probably not very useful. */
10281 if (strcasecmp (cpu_string, "default") == 0)
10284 for (p = mips_cpu_info_table; p->name != 0; p++)
10285 if (mips_matching_cpu_name_p (p->name, cpu_string))
10288 error ("bad value (%s) for %s", cpu_string, option);
10293 /* Return the processor associated with the given ISA level, or null
10294 if the ISA isn't valid. */
10296 static const struct mips_cpu_info *
10297 mips_cpu_info_from_isa (isa)
10300 const struct mips_cpu_info *p;
10302 for (p = mips_cpu_info_table; p->name != 0; p++)
10309 /* Adjust the cost of INSN based on the relationship between INSN that
10310 is dependent on DEP_INSN through the dependence LINK. The default
10311 is to make no adjustment to COST.
10313 On the MIPS, ignore the cost of anti- and output-dependencies. */
10315 mips_adjust_cost (insn, link, dep, cost)
10316 rtx insn ATTRIBUTE_UNUSED;
10318 rtx dep ATTRIBUTE_UNUSED;
10321 if (REG_NOTE_KIND (link) != 0)
10322 return 0; /* Anti or output dependence. */
10326 /* ??? This could be replaced with the default elf version if
10327 TARGET_IS_SMALL_DATA_P is set properly. */
10330 mips_unique_section (decl, reloc)
10334 int len, size, sec;
10335 const char *name, *prefix;
10337 static const char *const prefixes[4][2] = {
10338 { ".text.", ".gnu.linkonce.t." },
10339 { ".rodata.", ".gnu.linkonce.r." },
10340 { ".data.", ".gnu.linkonce.d." },
10341 { ".sdata.", ".gnu.linkonce.s." }
10344 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10345 name = (* targetm.strip_name_encoding) (name);
10346 size = int_size_in_bytes (TREE_TYPE (decl));
10348 /* Determine the base section we are interested in:
10349 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
10350 if (TREE_CODE (decl) == FUNCTION_DECL)
10352 else if (DECL_INITIAL (decl) == 0
10353 || DECL_INITIAL (decl) == error_mark_node)
10355 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
10356 && TREE_CODE (decl) == STRING_CST
10357 && !flag_writable_strings)
10359 /* For embedded position independent code, put constant
10360 strings in the text section, because the data section
10361 is limited to 64K in size. For mips16 code, put
10362 strings in the text section so that a PC relative load
10363 instruction can be used to get their address. */
10366 else if (TARGET_EMBEDDED_DATA)
10368 /* For embedded applications, always put an object in
10369 read-only data if possible, in order to reduce RAM
10372 if (decl_readonly_section (decl, reloc))
10374 else if (size > 0 && size <= mips_section_threshold)
10381 /* For hosted applications, always put an object in
10382 small data if possible, as this gives the best
10385 if (size > 0 && size <= mips_section_threshold)
10387 else if (decl_readonly_section (decl, reloc))
10393 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
10394 len = strlen (name) + strlen (prefix);
10395 string = alloca (len + 1);
10396 sprintf (string, "%s%s", prefix, name);
10398 DECL_SECTION_NAME (decl) = build_string (len, string);
10402 mips_hard_regno_nregs (regno, mode)
10404 enum machine_mode mode;
10406 if (! FP_REG_P (regno))
10407 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
10409 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
10413 mips_return_in_memory (type)
10416 /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
10417 returned in memory. Under the new (N32 and 64-bit MIPS ABIs) small
10418 structures are returned in a register. Objects with varying size
10419 must still be returned in memory, of course. */
10421 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
10422 return (TYPE_MODE (type) == BLKmode);
10424 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
10425 || (int_size_in_bytes (type) == -1));
10433 case PROCESSOR_R3000:
10445 mips_emit_prefetch (operands)
10448 /* For the mips32/64 architectures the hint fields are arranged
10449 by operation (load/store) and locality (normal/streamed/retained).
10450 Irritatingly, numbers 2 and 3 are reserved leaving no simple
10451 algorithm for figuring the hint. */
10453 int write = INTVAL (operands[1]);
10454 int locality = INTVAL (operands[2]);
10456 static const char * const alt[2][4] = {
10471 return alt[write][locality];
10476 #ifdef TARGET_IRIX6
10477 /* Output assembly to switch to section NAME with attribute FLAGS. */
10480 iris6_asm_named_section_1 (name, flags, align)
10482 unsigned int flags;
10483 unsigned int align;
10485 unsigned int sh_type, sh_flags, sh_entsize;
10488 if (!(flags & SECTION_DEBUG))
10489 sh_flags |= 2; /* SHF_ALLOC */
10490 if (flags & SECTION_WRITE)
10491 sh_flags |= 1; /* SHF_WRITE */
10492 if (flags & SECTION_CODE)
10493 sh_flags |= 4; /* SHF_EXECINSTR */
10494 if (flags & SECTION_SMALL)
10495 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
10496 if (strcmp (name, ".debug_frame") == 0)
10497 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
10498 if (flags & SECTION_DEBUG)
10499 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
10500 else if (flags & SECTION_BSS)
10501 sh_type = 8; /* SHT_NOBITS */
10503 sh_type = 1; /* SHT_PROGBITS */
10505 if (flags & SECTION_CODE)
10510 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
10511 name, sh_type, sh_flags, sh_entsize, align);
10515 iris6_asm_named_section (name, flags)
10517 unsigned int flags;
10519 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
10520 asm_out_file = asm_out_text_file;
10521 iris6_asm_named_section_1 (name, flags, 0);
10524 /* In addition to emitting a .align directive, record the maximum
10525 alignment requested for the current section. */
10527 struct iris_section_align_entry
10531 unsigned int flags;
10534 static htab_t iris_section_align_htab;
10535 static FILE *iris_orig_asm_out_file;
10538 iris_section_align_entry_eq (p1, p2)
10542 const struct iris_section_align_entry *old = p1;
10543 const char *new = p2;
10545 return strcmp (old->name, new) == 0;
10549 iris_section_align_entry_hash (p)
10552 const struct iris_section_align_entry *old = p;
10553 return htab_hash_string (old->name);
10557 iris6_asm_output_align (file, log)
10561 const char *section = current_section_name ();
10562 struct iris_section_align_entry **slot, *entry;
10567 slot = (struct iris_section_align_entry **)
10568 htab_find_slot_with_hash (iris_section_align_htab, section,
10569 htab_hash_string (section), INSERT);
10573 entry = (struct iris_section_align_entry *)
10574 xmalloc (sizeof (struct iris_section_align_entry));
10576 entry->name = section;
10578 entry->flags = current_section_flags ();
10580 else if (entry->log < log)
10583 fprintf (file, "\t.align\t%u\n", log);
10586 /* The Iris assembler does not record alignment from .align directives,
10587 but takes it from the first .section directive seen. Play yet more
10588 file switching games so that we can emit a .section directive at the
10589 beginning of the file with the proper alignment attached. */
10592 iris6_asm_file_start (stream)
10595 mips_asm_file_start (stream);
10597 iris_orig_asm_out_file = asm_out_file;
10598 stream = tmpfile ();
10599 asm_out_file = stream;
10600 asm_out_data_file = stream;
10601 if (! TARGET_FILE_SWITCHING)
10602 asm_out_text_file = stream;
10604 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
10605 iris_section_align_entry_eq, NULL);
10609 iris6_section_align_1 (slot, data)
10611 void *data ATTRIBUTE_UNUSED;
10613 const struct iris_section_align_entry *entry
10614 = *(const struct iris_section_align_entry **) slot;
10616 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10621 iris6_asm_file_end (stream)
10624 /* Emit section directives with the proper alignment at the top of the
10625 real output file. */
10626 asm_out_file = iris_orig_asm_out_file;
10627 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10629 /* Copy the data emitted to the temp file to the real output file. */
10630 copy_file_data (asm_out_file, stream);
10632 mips_asm_file_end (stream);
10634 #endif /* TARGET_IRIX6 */
10636 #include "gt-mips.h"