1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
56 /* Enumeration for all of the relational tests, so that we can build
57 arrays indexed by the test type, and not worry about the order
74 /* Return true if it is likely that the given mode will be accessed
75 using only a single instruction. */
76 #define SINGLE_WORD_MODE_P(MODE) \
77 ((MODE) != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
79 /* True if the given SYMBOL_REF is for an internally-generated symbol. */
80 #define INTERNAL_SYMBOL_P(SYM) \
81 (XSTR (SYM, 0)[0] == '*' && XSTR (SYM, 0)[1] == LOCAL_LABEL_PREFIX[0])
83 /* The maximum distance between the top of the stack frame and the
84 value $sp has when we save & restore registers.
86 Use a maximum gap of 0x100 in the mips16 case. We can then use
87 unextended instructions to save and restore registers, and to
88 allocate and deallocate the top part of the frame.
90 The value in the !mips16 case must be a SMALL_OPERAND and must
91 preserve the maximum stack alignment. It could really be 0x7ff0,
92 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
93 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
94 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
96 /* Classifies a non-literal integer constant.
99 Not one of the constants below.
102 The global pointer, treated as a constant when TARGET_MIPS16.
103 The rtx has the form:
108 A signed 16-bit relocation against either a symbol
109 or a symbol plus an offset. The relocation has the form:
111 (unspec [(SYMBOL) ...] RELOC)
113 Any offset is added outside the unspec, such as:
115 (plus (unspec [(SYMBOL) ...] RELOC) (const_int OFFSET))
117 In either case, the whole expression is wrapped in a (const ...).
120 A reference to a symbol, possibly with an offset. */
121 enum mips_constant_type {
129 /* Classifies a SYMBOL_REF or LABEL_REF.
132 Used when none of the below apply.
135 The symbol refers to something in a small data section.
138 The symbol refers to something in the mips16 constant pool.
141 The symbol refers to local data that will be found using
142 the global offset table.
145 Likewise non-local data. */
146 enum mips_symbol_type {
149 SYMBOL_CONSTANT_POOL,
155 /* Classifies an address.
158 The address should be rejected as invalid.
161 A natural register + offset address. The register satisfies
162 mips_valid_base_register_p and the offset is a const_arith_operand.
165 A LO_SUM rtx. The first operand is a valid base register and
166 the second operand is a symbolic address.
169 A signed 16-bit constant address.
172 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
173 enum mips_address_type {
181 /* A function to save or store a register. The first argument is the
182 register and the second is the stack slot. */
183 typedef void (*mips_save_restore_fn) (rtx, rtx);
186 struct mips_arg_info;
187 struct mips_constant_info;
188 struct mips_address_info;
189 struct mips_integer_op;
191 static bool mips_reloc_offset_ok_p (int, HOST_WIDE_INT);
192 static enum mips_constant_type
193 mips_classify_constant (struct mips_constant_info *, rtx);
194 static enum mips_symbol_type mips_classify_symbol (rtx);
195 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
196 static bool mips_symbolic_address_p (rtx, HOST_WIDE_INT,
197 enum machine_mode, int);
198 static enum mips_address_type
199 mips_classify_address (struct mips_address_info *, rtx,
200 enum machine_mode, int, int);
201 static bool mips_splittable_symbol_p (enum mips_symbol_type, HOST_WIDE_INT);
202 static int mips_symbol_insns (enum mips_symbol_type);
203 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
204 static rtx mips_reloc (rtx, int);
205 static rtx mips_lui_reloc (rtx, int);
206 static rtx mips_force_temporary (rtx, rtx);
207 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
208 static rtx mips_load_got (rtx, rtx, int);
209 static rtx mips_load_got16 (rtx, int);
210 static rtx mips_load_got32 (rtx, rtx, int, int);
211 static rtx mips_emit_high (rtx, rtx);
212 static bool mips_legitimize_symbol (rtx, rtx *, int);
213 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
214 static unsigned int mips_build_lower (struct mips_integer_op *,
215 unsigned HOST_WIDE_INT);
216 static unsigned int mips_build_integer (struct mips_integer_op *,
217 unsigned HOST_WIDE_INT);
218 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
219 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
220 static int m16_check_op (rtx, int, int, int);
221 static bool mips_rtx_costs (rtx, int, int, int *);
222 static int mips_address_cost (rtx);
223 static enum internal_test map_test_to_internal_test (enum rtx_code);
224 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
226 static bool mips_function_ok_for_sibcall (tree, tree);
227 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
228 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
229 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
230 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
231 tree, int, struct mips_arg_info *);
232 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
233 static void mips_set_architecture (const struct mips_cpu_info *);
234 static void mips_set_tune (const struct mips_cpu_info *);
235 static struct machine_function *mips_init_machine_status (void);
236 static const char *mips_reloc_string (int);
237 static bool mips_assemble_integer (rtx, unsigned int, int);
238 static void mips_file_start (void);
239 static void mips_file_end (void);
240 static unsigned int mips_global_pointer (void);
241 static bool mips_save_reg_p (unsigned int);
242 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
243 mips_save_restore_fn);
244 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
245 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
246 static void mips_set_frame_expr (rtx);
247 static rtx mips_frame_set (rtx, rtx);
248 static void mips_save_reg (rtx, rtx);
249 static void mips_gp_insn (rtx, rtx);
250 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
251 static void mips_restore_reg (rtx, rtx);
252 static int symbolic_expression_p (rtx);
253 static void mips_select_rtx_section (enum machine_mode, rtx,
254 unsigned HOST_WIDE_INT);
255 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
257 static bool mips_in_small_data_p (tree);
258 static void mips_encode_section_info (tree, rtx, int);
259 static rtx mips_sdata_pointer (void);
260 static void mips16_fp_args (FILE *, int, int);
261 static void build_mips16_function_stub (FILE *);
262 static void mips16_optimize_gp (void);
263 static rtx add_constant (struct constant **, rtx, enum machine_mode);
264 static void dump_constants (struct constant *, rtx);
265 static rtx mips_find_symbol (rtx);
266 static void mips16_lay_out_constants (void);
267 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
268 static void mips_avoid_hazards (void);
269 static void mips_reorg (void);
270 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
271 static bool mips_matching_cpu_name_p (const char *, const char *);
272 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
273 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
274 static int mips_adjust_cost (rtx, rtx, rtx, int);
275 static int mips_issue_rate (void);
276 static int mips_use_dfa_pipeline_interface (void);
277 static void mips_init_libfuncs (void);
278 static tree mips_build_builtin_va_list (void);
281 static void irix_asm_named_section_1 (const char *, unsigned int,
283 static void irix_asm_named_section (const char *, unsigned int);
284 static int irix_section_align_entry_eq (const void *, const void *);
285 static hashval_t irix_section_align_entry_hash (const void *);
286 static void irix_file_start (void);
287 static int irix_section_align_1 (void **, void *);
288 static void copy_file_data (FILE *, FILE *);
289 static void irix_file_end (void);
290 static unsigned int irix_section_type_flags (tree, const char *, int);
293 /* Structure to be filled in by compute_frame_size with register
294 save masks, and offsets for the current function. */
296 struct mips_frame_info GTY(())
298 long total_size; /* # bytes that the entire frame takes up */
299 long var_size; /* # bytes that variables take up */
300 long args_size; /* # bytes that outgoing arguments take up */
301 long cprestore_size; /* # bytes that the .cprestore slot takes up */
302 int gp_reg_size; /* # bytes needed to store gp regs */
303 int fp_reg_size; /* # bytes needed to store fp regs */
304 long mask; /* mask of saved gp registers */
305 long fmask; /* mask of saved fp registers */
306 long gp_save_offset; /* offset from vfp to store gp registers */
307 long fp_save_offset; /* offset from vfp to store fp registers */
308 long gp_sp_offset; /* offset from new sp to store gp registers */
309 long fp_sp_offset; /* offset from new sp to store fp registers */
310 int initialized; /* != 0 if frame size already calculated */
311 int num_gp; /* number of gp registers saved */
312 int num_fp; /* number of fp registers saved */
315 struct machine_function GTY(()) {
316 /* Pseudo-reg holding the address of the current function when
317 generating embedded PIC code. */
318 rtx embedded_pic_fnaddr_rtx;
320 /* Pseudo-reg holding the value of $28 in a mips16 function which
321 refers to GP relative global variables. */
322 rtx mips16_gp_pseudo_rtx;
324 /* Current frame information, calculated by compute_frame_size. */
325 struct mips_frame_info frame;
327 /* Length of instructions in function; mips16 only. */
330 /* The register to use as the global pointer within this function. */
331 unsigned int global_pointer;
333 /* True if mips_adjust_insn_length should ignore an instruction's
335 bool ignore_hazard_length_p;
337 /* True if the whole function is suitable for .set noreorder and
339 bool all_noreorder_p;
342 /* Information about a single argument. */
345 /* True if the argument is passed in a floating-point register, or
346 would have been if we hadn't run out of registers. */
349 /* The argument's size, in bytes. */
350 unsigned int num_bytes;
352 /* The number of words passed in registers, rounded up. */
353 unsigned int reg_words;
355 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
356 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
358 unsigned int reg_offset;
360 /* The number of words that must be passed on the stack, rounded up. */
361 unsigned int stack_words;
363 /* The offset from the start of the stack overflow area of the argument's
364 first stack word. Only meaningful when STACK_WORDS is nonzero. */
365 unsigned int stack_offset;
369 /* Struct for recording constants. The meaning of the fields depends
370 on a mips_constant_type:
377 SYMBOL is the referenced symbol and OFFSET is the constant offset.
380 SYMBOL and OFFSET are the same as for CONSTANT_SYMBOLIC. RELOC is
381 the relocation number. */
382 struct mips_constant_info
386 HOST_WIDE_INT offset;
390 /* Information about an address described by mips_address_type.
397 REG is the base register and OFFSET is the constant offset.
400 REG is the register that contains the high part of the address,
401 OFFSET is the symbolic address being referenced, and C contains
402 the individual components of the symbolic address.
405 C contains the symbol and offset. */
406 struct mips_address_info
410 struct mips_constant_info c;
414 /* One stage in a constant building sequence. These sequences have
418 A = A CODE[1] VALUE[1]
419 A = A CODE[2] VALUE[2]
422 where A is an accumulator, each CODE[i] is a binary rtl operation
423 and each VALUE[i] is a constant integer. */
424 struct mips_integer_op {
426 unsigned HOST_WIDE_INT value;
430 /* The largest number of operations needed to load an integer constant.
431 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
432 When the lowest bit is clear, we can try, but reject a sequence with
433 an extra SLL at the end. */
434 #define MIPS_MAX_INTEGER_OPS 7
437 /* Global variables for machine-dependent things. */
439 /* Threshold for data being put into the small data/bss area, instead
440 of the normal data area. */
441 int mips_section_threshold = -1;
443 /* Count the number of .file directives, so that .loc is up to date. */
444 int num_source_filenames = 0;
446 /* Count the number of sdb related labels are generated (to find block
447 start and end boundaries). */
448 int sdb_label_count = 0;
450 /* Next label # for each statement for Silicon Graphics IRIS systems. */
453 /* Linked list of all externals that are to be emitted when optimizing
454 for the global pointer if they haven't been declared by the end of
455 the program with an appropriate .comm or initialization. */
457 struct extern_list GTY (())
459 struct extern_list *next; /* next external */
460 const char *name; /* name of the external */
461 int size; /* size in bytes */
464 static GTY (()) struct extern_list *extern_head = 0;
466 /* Name of the file containing the current function. */
467 const char *current_function_file = "";
469 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
475 /* The next branch instruction is a branch likely, not branch normal. */
476 int mips_branch_likely;
478 /* Cached operands, and operator to compare for use in set/branch/trap
479 on condition codes. */
482 /* what type of branch to use */
483 enum cmp_type branch_type;
485 /* The target cpu for code generation. */
486 enum processor_type mips_arch;
487 const struct mips_cpu_info *mips_arch_info;
489 /* The target cpu for optimization and scheduling. */
490 enum processor_type mips_tune;
491 const struct mips_cpu_info *mips_tune_info;
493 /* Which instruction set architecture to use. */
496 /* Which ABI to use. */
499 /* Strings to hold which cpu and instruction set architecture to use. */
500 const char *mips_arch_string; /* for -march=<xxx> */
501 const char *mips_tune_string; /* for -mtune=<xxx> */
502 const char *mips_isa_string; /* for -mips{1,2,3,4} */
503 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
505 /* Whether we are generating mips16 hard float code. In mips16 mode
506 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
507 -msoft-float was not specified by the user, which means that we
508 should arrange to call mips32 hard floating point code. */
509 int mips16_hard_float;
511 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
513 /* If TRUE, we split addresses into their high and low parts in the RTL. */
514 int mips_split_addresses;
516 /* Mode used for saving/restoring general purpose registers. */
517 static enum machine_mode gpr_mode;
519 /* Array giving truth value on whether or not a given hard register
520 can support a given mode. */
521 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
523 /* The length of all strings seen when compiling for the mips16. This
524 is used to tell how many strings are in the constant pool, so that
525 we can see if we may have an overflow. This is reset each time the
526 constant pool is output. */
527 int mips_string_length;
529 /* When generating mips16 code, a list of all strings that are to be
530 output after the current function. */
532 static GTY(()) rtx mips16_strings;
534 /* In mips16 mode, we build a list of all the string constants we see
535 in a particular function. */
537 struct string_constant
539 struct string_constant *next;
543 static struct string_constant *string_constants;
545 /* List of all MIPS punctuation characters used by print_operand. */
546 char mips_print_operand_punct[256];
548 /* Map GCC register number to debugger register number. */
549 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
551 /* An alias set for the GOT. */
552 static int mips_got_alias_set;
554 /* A copy of the original flag_delayed_branch: see override_options. */
555 static int mips_flag_delayed_branch;
557 static GTY (()) int mips_output_filename_first_time = 1;
559 /* Hardware names for the registers. If -mrnames is used, this
560 will be overwritten with mips_sw_reg_names. */
562 char mips_reg_names[][8] =
564 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
565 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
566 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
567 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
568 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
569 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
570 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
571 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
572 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
573 "$fcc5","$fcc6","$fcc7","", "", "", "", "",
574 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
575 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
576 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
577 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
578 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
579 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
580 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
581 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
582 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
583 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
584 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
585 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
588 /* Mips software names for the registers, used to overwrite the
589 mips_reg_names array. */
591 char mips_sw_reg_names[][8] =
593 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
594 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
595 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
596 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
597 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
598 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
599 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
600 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
601 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
602 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
603 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
604 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
605 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",
606 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",
607 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",
608 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",
609 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",
610 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",
611 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",
612 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",
613 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",
614 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"
617 /* Map hard register number to register class */
618 const enum reg_class mips_regno_to_class[] =
620 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
621 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
622 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
623 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
624 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
625 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
626 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
627 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
628 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
629 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
630 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
631 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
634 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
635 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
636 HI_REG, LO_REG, NO_REGS, ST_REGS,
637 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
638 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
639 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
640 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
641 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
642 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
643 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
646 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
647 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
648 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
649 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
650 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
651 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
654 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
655 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
656 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
657 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
658 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
659 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
661 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
662 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
663 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
666 /* Map register constraint character to register class. */
667 enum reg_class mips_char_to_class[256];
669 /* A table describing all the processors gcc knows about. Names are
670 matched in the order listed. The first mention of an ISA level is
671 taken as the canonical name for that ISA.
673 To ease comparison, please keep this table in the same order as
674 gas's mips_cpu_info_table[]. */
675 const struct mips_cpu_info mips_cpu_info_table[] = {
676 /* Entries for generic ISAs */
677 { "mips1", PROCESSOR_R3000, 1 },
678 { "mips2", PROCESSOR_R6000, 2 },
679 { "mips3", PROCESSOR_R4000, 3 },
680 { "mips4", PROCESSOR_R8000, 4 },
681 { "mips32", PROCESSOR_4KC, 32 },
682 { "mips32r2", PROCESSOR_M4K, 33 },
683 { "mips64", PROCESSOR_5KC, 64 },
686 { "r3000", PROCESSOR_R3000, 1 },
687 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
688 { "r3900", PROCESSOR_R3900, 1 },
691 { "r6000", PROCESSOR_R6000, 2 },
694 { "r4000", PROCESSOR_R4000, 3 },
695 { "vr4100", PROCESSOR_R4100, 3 },
696 { "vr4111", PROCESSOR_R4111, 3 },
697 { "vr4120", PROCESSOR_R4120, 3 },
698 { "vr4300", PROCESSOR_R4300, 3 },
699 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
700 { "r4600", PROCESSOR_R4600, 3 },
701 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
702 { "r4650", PROCESSOR_R4650, 3 },
705 { "r8000", PROCESSOR_R8000, 4 },
706 { "vr5000", PROCESSOR_R5000, 4 },
707 { "vr5400", PROCESSOR_R5400, 4 },
708 { "vr5500", PROCESSOR_R5500, 4 },
709 { "rm7000", PROCESSOR_R7000, 4 },
710 { "rm9000", PROCESSOR_R9000, 4 },
713 { "4kc", PROCESSOR_4KC, 32 },
714 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
716 /* MIPS32 Release 2 */
717 { "m4k", PROCESSOR_M4K, 33 },
720 { "5kc", PROCESSOR_5KC, 64 },
721 { "20kc", PROCESSOR_20KC, 64 },
722 { "sb1", PROCESSOR_SB1, 64 },
723 { "sr71000", PROCESSOR_SR71000, 64 },
729 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
730 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
731 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
734 /* Initialize the GCC target structure. */
735 #undef TARGET_ASM_ALIGNED_HI_OP
736 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
737 #undef TARGET_ASM_ALIGNED_SI_OP
738 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
739 #undef TARGET_ASM_INTEGER
740 #define TARGET_ASM_INTEGER mips_assemble_integer
742 #undef TARGET_ASM_FUNCTION_PROLOGUE
743 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
744 #undef TARGET_ASM_FUNCTION_EPILOGUE
745 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
746 #undef TARGET_ASM_SELECT_RTX_SECTION
747 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
749 #undef TARGET_SCHED_ADJUST_COST
750 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
751 #undef TARGET_SCHED_ISSUE_RATE
752 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
753 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
754 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
756 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
757 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
759 #undef TARGET_VALID_POINTER_MODE
760 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
761 #undef TARGET_RTX_COSTS
762 #define TARGET_RTX_COSTS mips_rtx_costs
763 #undef TARGET_ADDRESS_COST
764 #define TARGET_ADDRESS_COST mips_address_cost
765 #undef TARGET_DELEGITIMIZE_ADDRESS
766 #define TARGET_DELEGITIMIZE_ADDRESS mips_delegitimize_address
768 #undef TARGET_ENCODE_SECTION_INFO
769 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
770 #undef TARGET_IN_SMALL_DATA_P
771 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
773 #undef TARGET_MACHINE_DEPENDENT_REORG
774 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
776 #undef TARGET_ASM_FILE_START
777 #undef TARGET_ASM_FILE_END
779 #define TARGET_ASM_FILE_START irix_file_start
780 #define TARGET_ASM_FILE_END irix_file_end
782 #define TARGET_ASM_FILE_START mips_file_start
783 #define TARGET_ASM_FILE_END mips_file_end
785 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
786 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
789 #undef TARGET_SECTION_TYPE_FLAGS
790 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
793 #undef TARGET_INIT_LIBFUNCS
794 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
796 #undef TARGET_BUILD_BUILTIN_VA_LIST
797 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
799 struct gcc_target targetm = TARGET_INITIALIZER;
801 /* Return true if RELOC is a valid relocation number and OFFSET can be
802 added to the relocation symbol.
804 Note that OFFSET might not refer to part of the object. For example,
805 in an expression like x[i - 0x12345], we might try to take the address
809 mips_reloc_offset_ok_p (int reloc, HOST_WIDE_INT offset)
814 /* The linker should provide enough page entries to cope with
815 16-bit offsets from a valid segment address. */
816 return SMALL_OPERAND (offset);
824 case RELOC_LOADGP_HI:
825 case RELOC_LOADGP_LO:
826 /* These relocations should be applied to bare symbols only. */
835 /* If X is one of the constants described by mips_constant_type,
836 store its components in INFO and return its type. */
838 static enum mips_constant_type
839 mips_classify_constant (struct mips_constant_info *info, rtx x)
841 enum mips_constant_type type;
843 type = CONSTANT_SYMBOLIC;
846 if (GET_CODE (x) == CONST)
850 if (x == pic_offset_table_rtx)
853 while (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
855 info->offset += INTVAL (XEXP (x, 1));
859 if (TARGET_EXPLICIT_RELOCS
860 && GET_CODE (x) == UNSPEC
861 && mips_reloc_offset_ok_p (XINT (x, 1), info->offset))
863 info->reloc = XINT (x, 1);
864 x = XVECEXP (x, 0, 0);
865 type = CONSTANT_RELOC;
869 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
874 return CONSTANT_NONE;
878 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
880 static enum mips_symbol_type
881 mips_classify_symbol (rtx x)
883 if (GET_CODE (x) == LABEL_REF)
884 return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
886 if (GET_CODE (x) != SYMBOL_REF)
889 if (CONSTANT_POOL_ADDRESS_P (x))
892 return SYMBOL_CONSTANT_POOL;
895 return SYMBOL_GOT_LOCAL;
897 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
898 return SYMBOL_SMALL_DATA;
900 return SYMBOL_GENERAL;
903 if (INTERNAL_SYMBOL_P (x))
905 /* The symbol is a local label. For TARGET_MIPS16, SYMBOL_REF_FLAG
906 will be set if the symbol refers to a string in the current
907 function's constant pool. */
908 if (TARGET_MIPS16 && SYMBOL_REF_FLAG (x))
909 return SYMBOL_CONSTANT_POOL;
912 return SYMBOL_GOT_LOCAL;
915 if (SYMBOL_REF_SMALL_P (x))
916 return SYMBOL_SMALL_DATA;
919 return (SYMBOL_REF_FLAG (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL);
921 return SYMBOL_GENERAL;
925 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
928 mips_reg_mode_ok_for_base_p (rtx reg, enum machine_mode mode, int strict)
931 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
932 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
936 /* Return true if X is a valid base register for the given mode.
937 Allow only hard registers if STRICT. */
940 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
942 if (!strict && GET_CODE (x) == SUBREG)
945 return (GET_CODE (x) == REG
946 && mips_reg_mode_ok_for_base_p (x, mode, strict));
950 /* Return true if SYMBOL + OFFSET should be considered a legitimate
951 address. LEA_P is true and MODE is word_mode if the address
952 will be used in an LA or DLA macro. Otherwise MODE is the
953 mode of the value being accessed.
955 Some guiding principles:
957 - Allow a nonzero offset when it takes no additional instructions.
958 Ask for other offsets to be added separately.
960 - Only allow multi-instruction load or store macros when MODE is
961 word-sized or smaller. For other modes (including BLKmode)
962 it is better to move the address into a register first. */
965 mips_symbolic_address_p (rtx symbol, HOST_WIDE_INT offset,
966 enum machine_mode mode, int lea_p)
968 if (TARGET_EXPLICIT_RELOCS)
971 switch (mips_classify_symbol (symbol))
974 /* General symbols aren't valid addresses in mips16 code:
975 they have to go into the constant pool. */
976 return (!TARGET_MIPS16
977 && !mips_split_addresses
978 && SINGLE_WORD_MODE_P (mode));
980 case SYMBOL_SMALL_DATA:
981 /* Small data references are normally OK for any address.
982 But for mips16 code, we need to use a pseudo register
983 instead of $gp as the base register. */
984 return !TARGET_MIPS16;
986 case SYMBOL_CONSTANT_POOL:
987 /* PC-relative addressing is only available for lw, sw, ld and sd.
988 There's also a PC-relative add instruction. */
989 return lea_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
991 case SYMBOL_GOT_GLOBAL:
992 /* The address of the symbol is stored in the GOT. We can load
993 it using an LA or DLA instruction, but any offset is added
995 return lea_p && offset == 0;
997 case SYMBOL_GOT_LOCAL:
998 /* The symbol is part of a block of local memory. We fetch the
999 address of the local memory from the GOT and then add the
1000 offset for this symbol. This addition can take the form of an
1001 offset(base) address, so the symbol is a legitimate address. */
1002 return SINGLE_WORD_MODE_P (mode);
1008 /* If X is a valid address, describe it in INFO and return its type.
1009 STRICT says to only allow hard registers. MODE and LEA_P are
1010 the same as for mips_symbolic_address_p. */
1012 static enum mips_address_type
1013 mips_classify_address (struct mips_address_info *info, rtx x,
1014 enum machine_mode mode, int strict, int lea_p)
1016 switch (GET_CODE (x))
1020 if (mips_valid_base_register_p (x, mode, strict))
1023 info->offset = const0_rtx;
1026 return ADDRESS_INVALID;
1029 if (mips_valid_base_register_p (XEXP (x, 0), mode, strict)
1030 && const_arith_operand (XEXP (x, 1), VOIDmode))
1032 info->reg = XEXP (x, 0);
1033 info->offset = XEXP (x, 1);
1036 return ADDRESS_INVALID;
1039 if (SINGLE_WORD_MODE_P (mode)
1040 && mips_valid_base_register_p (XEXP (x, 0), mode, strict)
1041 && (mips_classify_constant (&info->c, XEXP (x, 1))
1042 == CONSTANT_SYMBOLIC)
1043 && mips_splittable_symbol_p (mips_classify_symbol (info->c.symbol),
1046 info->reg = XEXP (x, 0);
1047 info->offset = XEXP (x, 1);
1048 return ADDRESS_LO_SUM;
1050 return ADDRESS_INVALID;
1053 /* Small-integer addresses don't occur very often, but they
1054 are legitimate if $0 is a valid base register. */
1055 if (!TARGET_MIPS16 && SMALL_INT (x))
1056 return ADDRESS_CONST_INT;
1057 return ADDRESS_INVALID;
1062 if (mips_classify_constant (&info->c, x) == CONSTANT_SYMBOLIC
1063 && mips_symbolic_address_p (info->c.symbol, info->c.offset,
1065 return ADDRESS_SYMBOLIC;
1066 return ADDRESS_INVALID;
1069 return ADDRESS_INVALID;
1073 /* Return true if symbols of the given type can be split into a
1074 high part and a LO_SUM. In the case of small data symbols,
1075 the high part will be $gp. */
1078 mips_splittable_symbol_p (enum mips_symbol_type type, HOST_WIDE_INT offset)
1082 case SYMBOL_GENERAL:
1083 return TARGET_EXPLICIT_RELOCS || mips_split_addresses;
1085 case SYMBOL_GOT_LOCAL:
1086 return TARGET_EXPLICIT_RELOCS && SMALL_OPERAND (offset);
1088 case SYMBOL_SMALL_DATA:
1089 return ((TARGET_EXPLICIT_RELOCS || TARGET_MIPS16)
1091 || (offset > 0 && offset <= mips_section_threshold)));
1099 /* Return the number of instructions needed to load a symbol of the
1100 given type into a register. If valid in an address, the same number
1101 of instructions are needed for loads and stores. Treat extended
1102 mips16 instructions as two instructions. */
1105 mips_symbol_insns (enum mips_symbol_type type)
1109 case SYMBOL_GENERAL:
1110 /* When using 64-bit symbols, we need 5 preparatory instructions,
1113 lui $at,%highest(symbol)
1114 daddiu $at,$at,%higher(symbol)
1116 daddiu $at,$at,%hi(symbol)
1119 The final address is then $at + %lo(symbol). With 32-bit
1120 symbols we just need a preparatory lui. */
1121 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1123 case SYMBOL_SMALL_DATA:
1126 case SYMBOL_CONSTANT_POOL:
1127 /* This case is for mips16 only. Assume we'll need an
1128 extended instruction. */
1131 case SYMBOL_GOT_GLOBAL:
1132 /* When using a small GOT, we just fetch the address using
1133 a gp-relative load. For a big GOT, we need a sequence
1136 lui $at,%got_hi(symbol)
1139 and the final address is $at + %got_lo(symbol). */
1140 return (TARGET_XGOT ? 3 : 1);
1142 case SYMBOL_GOT_LOCAL:
1143 /* For o32 and o64, the sequence is:
1148 and the final address is $at + %lo(symbol). A load/add
1149 sequence is also needed for n32 and n64. Some versions
1150 of GAS insert a nop in the n32/n64 sequences too so, for
1151 simplicity, use the worst case of 3 instructions. */
1158 /* Return true if a value at OFFSET bytes from BASE can be accessed
1159 using an unextended mips16 instruction. MODE is the mode of the
1162 Usually the offset in an unextended instruction is a 5-bit field.
1163 The offset is unsigned and shifted left once for HIs, twice
1164 for SIs, and so on. An exception is SImode accesses off the
1165 stack pointer, which have an 8-bit immediate field. */
1168 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1171 && GET_CODE (offset) == CONST_INT
1172 && INTVAL (offset) >= 0
1173 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1175 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1176 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1177 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1183 /* Return the number of instructions needed to load or store a value
1184 of mode MODE at X. Return 0 if X isn't valid for MODE.
1186 For mips16 code, count extended instructions as two instructions. */
1189 mips_address_insns (rtx x, enum machine_mode mode)
1191 struct mips_address_info addr;
1194 /* Each word of a multi-word value will be accessed individually. */
1195 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1196 switch (mips_classify_address (&addr, x, mode, 0, 0))
1198 case ADDRESS_INVALID:
1203 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1207 case ADDRESS_LO_SUM:
1208 return (TARGET_MIPS16 ? factor * 2 : factor);
1210 case ADDRESS_CONST_INT:
1213 case ADDRESS_SYMBOLIC:
1214 return factor * mips_symbol_insns (mips_classify_symbol (addr.c.symbol));
1220 /* Likewise for constant X. */
1223 mips_const_insns (rtx x)
1225 struct mips_constant_info c;
1226 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1228 switch (GET_CODE (x))
1230 case CONSTANT_P_RTX:
1236 /* Unsigned 8-bit constants can be loaded using an unextended
1237 LI instruction. Unsigned 16-bit constants can be loaded
1238 using an extended LI. Negative constants must be loaded
1239 using LI and then negated. */
1240 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1241 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1242 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1243 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1246 return mips_build_integer (codes, INTVAL (x));
1249 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1252 switch (mips_classify_constant (&c, x))
1258 case CONSTANT_RELOC:
1261 case CONSTANT_SYMBOLIC:
1262 return mips_symbol_insns (mips_classify_symbol (c.symbol));
1269 /* Return the number of instructions needed for memory reference X.
1270 Count extended mips16 instructions as two instructions. */
1273 mips_fetch_insns (rtx x)
1275 if (GET_CODE (x) != MEM)
1278 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1282 /* Return true if OP is a symbolic constant that refers to a
1283 global PIC symbol. */
1286 mips_global_pic_constant_p (rtx op)
1288 struct mips_constant_info c;
1290 return (mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC
1291 && mips_classify_symbol (c.symbol) == SYMBOL_GOT_GLOBAL);
1295 /* Return truth value of whether OP can be used as an operands
1296 where a register or 16 bit unsigned integer is needed. */
1299 uns_arith_operand (rtx op, enum machine_mode mode)
1301 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1304 return register_operand (op, mode);
1308 /* True if OP can be treated as a signed 16-bit constant. */
1311 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1313 struct mips_constant_info c;
1315 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1316 || mips_classify_constant (&c, op) == CONSTANT_RELOC);
1320 /* Return true if OP is a register operand or a signed 16-bit constant. */
1323 arith_operand (rtx op, enum machine_mode mode)
1325 return const_arith_operand (op, mode) || register_operand (op, mode);
1328 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1331 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1333 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1336 /* Return truth value of whether OP is a register or the constant 0.
1337 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1341 reg_or_0_operand (rtx op, enum machine_mode mode)
1343 switch (GET_CODE (op))
1348 return INTVAL (op) == 0;
1353 return op == CONST0_RTX (mode);
1356 return register_operand (op, mode);
1360 /* Accept a register or the floating point constant 1 in the appropriate mode. */
1363 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1367 switch (GET_CODE (op))
1370 if (mode != GET_MODE (op)
1371 || (mode != DFmode && mode != SFmode))
1374 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1375 return REAL_VALUES_EQUAL (d, dconst1);
1378 return register_operand (op, mode);
1382 /* Accept the floating point constant 1 in the appropriate mode. */
1385 const_float_1_operand (rtx op, enum machine_mode mode)
1389 if (GET_CODE (op) != CONST_DOUBLE
1390 || mode != GET_MODE (op)
1391 || (mode != DFmode && mode != SFmode))
1394 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1396 return REAL_VALUES_EQUAL (d, dconst1);
1399 /* Return true if OP is either the HI or LO register. */
1402 hilo_operand (rtx op, enum machine_mode mode)
1404 return ((mode == VOIDmode || mode == GET_MODE (op))
1405 && REG_P (op) && MD_REG_P (REGNO (op)));
1408 /* Return true if OP is an extension operator. */
1411 extend_operator (rtx op, enum machine_mode mode)
1413 return ((mode == VOIDmode || mode == GET_MODE (op))
1414 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1417 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1420 equality_op (rtx op, enum machine_mode mode)
1422 if (mode != GET_MODE (op))
1425 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1428 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1431 cmp_op (rtx op, enum machine_mode mode)
1433 if (mode != GET_MODE (op))
1436 return GET_RTX_CLASS (GET_CODE (op)) == '<';
1439 /* Return nonzero if the code is a relational operation suitable for a
1440 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1441 We need this in the insn that expands `trap_if' in order to prevent
1442 combine from erroneously altering the condition. */
1445 trap_cmp_op (rtx op, enum machine_mode mode)
1447 if (mode != GET_MODE (op))
1450 switch (GET_CODE (op))
1465 /* Return nonzero if the operand is either the PC or a label_ref. */
1468 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1473 if (GET_CODE (op) == LABEL_REF)
1479 /* Test for a valid call address. */
1482 call_insn_operand (rtx op, enum machine_mode mode)
1484 struct mips_constant_info c;
1486 if (mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC)
1487 switch (mips_classify_symbol (c.symbol))
1489 case SYMBOL_GENERAL:
1490 /* If -mlong-calls, force all calls to use register addressing. */
1491 return !TARGET_LONG_CALLS;
1493 case SYMBOL_GOT_GLOBAL:
1494 /* Without explicit relocs, there is no special syntax for
1495 loading the address of a call destination into a register.
1496 Using "la $25,foo; jal $25" would prevent the lazy binding
1497 of "foo", so keep the address of global symbols with the
1499 return c.offset == 0 && !TARGET_EXPLICIT_RELOCS;
1504 return register_operand (op, mode);
1508 /* Return nonzero if OP is valid as a source operand for a move
1512 move_operand (rtx op, enum machine_mode mode)
1514 struct mips_constant_info c;
1516 if (GET_CODE (op) == HIGH && TARGET_ABICALLS)
1518 if (GET_CODE (op) == CONST_INT && !TARGET_MIPS16)
1519 return (SMALL_INT (op) || SMALL_INT_UNSIGNED (op) || LUI_INT (op));
1520 if (mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC)
1521 return mips_symbolic_address_p (c.symbol, c.offset, word_mode, 1);
1522 return general_operand (op, mode);
1526 /* Accept any operand that can appear in a mips16 constant table
1527 instruction. We can't use any of the standard operand functions
1528 because for these instructions we accept values that are not
1529 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1532 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1534 return CONSTANT_P (op);
1537 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1538 possibly with an offset. */
1541 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1543 struct mips_constant_info c;
1545 return mips_classify_constant (&c, op) == CONSTANT_SYMBOLIC;
1549 /* Return true if OP is a memory reference that uses the stack pointer
1550 as a base register. */
1553 stack_operand (rtx op, enum machine_mode mode)
1555 struct mips_address_info addr;
1557 return ((mode == VOIDmode || mode == GET_MODE (op))
1558 && GET_CODE (op) == MEM
1559 && mips_classify_address (&addr, XEXP (op, 0),
1560 GET_MODE (op), false, true) == ADDRESS_REG
1561 && addr.reg == stack_pointer_rtx);
1565 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1566 returns a nonzero value if X is a legitimate address for a memory
1567 operand of the indicated MODE. STRICT is nonzero if this function
1568 is called during reload. */
1571 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1573 struct mips_address_info addr;
1575 return mips_classify_address (&addr, x, mode, strict, 0) != ADDRESS_INVALID;
1579 /* Return an rtx that represents the effect of applying relocation
1580 RELOC to symbolic address ADDR. */
1583 mips_reloc (rtx addr, int reloc)
1585 struct mips_constant_info c;
1588 if (mips_classify_constant (&c, addr) != CONSTANT_SYMBOLIC)
1591 x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, c.symbol), reloc);
1592 return plus_constant (gen_rtx_CONST (VOIDmode, x), c.offset);
1596 /* Likewise, but shift the result left 16 bits. The expression can be
1597 used as the right hand side of an LUISI or LUIDI pattern. */
1600 mips_lui_reloc (rtx addr, int reloc)
1602 return gen_rtx_UNSPEC (Pmode,
1603 gen_rtvec (1, mips_reloc (addr, reloc)),
1607 /* Copy VALUE to a register and return that register. Use DEST as the
1608 register if non-null, otherwise create a new one.
1610 VALUE must be valid on the right hand side of a simple SET pattern.
1611 The operation happens in Pmode. */
1614 mips_force_temporary (rtx dest, rtx value)
1617 return force_reg (Pmode, value);
1620 if (!rtx_equal_p (dest, value))
1621 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (dest), value));
1627 /* Return a legitimate address for REG + OFFSET. This function will
1628 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1631 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1633 if (!SMALL_OPERAND (offset))
1634 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1635 GEN_INT (CONST_HIGH_PART (offset)),
1636 reg, NULL, 0, OPTAB_WIDEN);
1638 return plus_constant (reg, CONST_LOW_PART (offset));
1642 /* Return the GOT entry whose address is given by %RELOC(ADDR)(BASE).
1643 BASE is a base register (such as $gp), ADDR is addresses being
1644 sought and RELOC is the relocation that should be used. */
1647 mips_load_got (rtx base, rtx addr, int reloc)
1651 mem = gen_rtx_MEM (ptr_mode,
1652 gen_rtx_PLUS (Pmode, base, mips_reloc (addr, reloc)));
1653 set_mem_alias_set (mem, mips_got_alias_set);
1655 /* GOT references can't trap. */
1656 MEM_NOTRAP_P (mem) = 1;
1658 /* If we allow a function's address to be lazily bound, its entry
1659 may change after the first call. Other entries are constant. */
1660 if (reloc != RELOC_CALL16 && reloc != RELOC_CALL_LO)
1661 RTX_UNCHANGING_P (mem) = 1;
1667 /* Obtain the address of ADDR from the GOT using relocation RELOC.
1668 The returned address may be used on the right hand side of a SET. */
1671 mips_load_got16 (rtx addr, int reloc)
1673 return mips_load_got (pic_offset_table_rtx, addr, reloc);
1677 /* Like mips_load_got16, but for 32-bit offsets. HIGH_RELOC is the
1678 relocation that gives the high 16 bits of the offset and LOW_RELOC is
1679 the relocation that gives the low 16 bits. TEMP is a Pmode register
1680 to use a temporary, or null if new registers can be created at will. */
1683 mips_load_got32 (rtx temp, rtx addr, int high_reloc, int low_reloc)
1687 x = mips_force_temporary (temp, mips_lui_reloc (addr, high_reloc));
1688 x = mips_force_temporary (temp,
1689 gen_rtx_PLUS (Pmode, pic_offset_table_rtx, x));
1690 return mips_load_got (x, addr, low_reloc);
1694 /* Copy the high part of ADDR into a register and return the register.
1695 Use DEST as the register if non-null. */
1698 mips_emit_high (rtx dest, rtx addr)
1702 high = gen_rtx_HIGH (Pmode, addr);
1703 if (TARGET_ABICALLS)
1705 x = mips_load_got16 (copy_rtx (addr), RELOC_GOT_PAGE);
1706 x = mips_force_temporary (dest, x);
1707 set_unique_reg_note (get_last_insn (), REG_EQUAL, high);
1710 x = mips_force_temporary (dest, high);
1716 /* See if *XLOC is a symbolic constant that can be reduced in some way.
1717 If it is, set *XLOC to the reduced expression and return true.
1718 The new expression will be both a legitimate address and a legitimate
1719 source operand for a mips.md SET pattern. If OFFSETABLE_P, the
1720 address will be offsetable.
1722 DEST is a register to use a temporary, or null if new registers
1723 can be created at will. */
1726 mips_legitimize_symbol (rtx dest, rtx *xloc, int offsetable_p)
1728 struct mips_constant_info c;
1729 enum mips_symbol_type symbol_type;
1732 if (mips_classify_constant (&c, *xloc) != CONSTANT_SYMBOLIC)
1735 symbol_type = mips_classify_symbol (c.symbol);
1737 /* If a non-offsetable address is OK, try splitting it into a
1738 high part and a LO_SUM. */
1739 if (!offsetable_p && mips_splittable_symbol_p (symbol_type, c.offset))
1741 if (symbol_type == SYMBOL_SMALL_DATA)
1742 x = mips_sdata_pointer ();
1744 x = mips_emit_high (dest, *xloc);
1747 *xloc = gen_rtx_LO_SUM (Pmode, x, copy_rtx (*xloc));
1752 /* If the offset is nonzero, move the symbol into a register (always valid)
1753 and add the constant in afterwards. This requires an extra temporary if
1754 the offset isn't a signed 16-bit number.
1756 For mips16, it's better to force the constant into memory instead. */
1759 && (SMALL_OPERAND (c.offset) || dest == 0))
1761 x = (dest == 0 ? gen_reg_rtx (Pmode) : dest);
1762 emit_move_insn (copy_rtx (x), c.symbol);
1763 *xloc = mips_add_offset (x, c.offset);
1771 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1772 be legitimized in a way that the generic machinery might not expect,
1773 put the new address in *XLOC and return true. MODE is the mode of
1774 the memory being accessed. */
1777 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1779 if (mips_legitimize_symbol (0, xloc, !SINGLE_WORD_MODE_P (mode)))
1782 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1784 /* Handle REG + CONSTANT using mips_add_offset. */
1787 reg = XEXP (*xloc, 0);
1788 if (!mips_valid_base_register_p (reg, mode, 0))
1789 reg = copy_to_mode_reg (Pmode, reg);
1790 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1798 /* Subroutine of mips_build_integer (with the same interface).
1799 Assume that the final action in the sequence should be a left shift. */
1802 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1804 unsigned int i, shift;
1806 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1807 since signed numbers are easier to load than unsigned ones. */
1809 while ((value & 1) == 0)
1810 value /= 2, shift++;
1812 i = mips_build_integer (codes, value);
1813 codes[i].code = ASHIFT;
1814 codes[i].value = shift;
1819 /* As for mips_build_shift, but assume that the final action will be
1820 an IOR or PLUS operation. */
1823 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1825 unsigned HOST_WIDE_INT high;
1828 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1829 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1831 /* The constant is too complex to load with a simple lui/ori pair
1832 so our goal is to clear as many trailing zeros as possible.
1833 In this case, we know bit 16 is set and that the low 16 bits
1834 form a negative number. If we subtract that number from VALUE,
1835 we will clear at least the lowest 17 bits, maybe more. */
1836 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1837 codes[i].code = PLUS;
1838 codes[i].value = CONST_LOW_PART (value);
1842 i = mips_build_integer (codes, high);
1843 codes[i].code = IOR;
1844 codes[i].value = value & 0xffff;
1850 /* Fill CODES with a sequence of rtl operations to load VALUE.
1851 Return the number of operations needed. */
1854 mips_build_integer (struct mips_integer_op *codes,
1855 unsigned HOST_WIDE_INT value)
1857 if (SMALL_OPERAND (value)
1858 || SMALL_OPERAND_UNSIGNED (value)
1859 || LUI_OPERAND (value))
1861 /* The value can be loaded with a single instruction. */
1862 codes[0].code = NIL;
1863 codes[0].value = value;
1866 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1868 /* Either the constant is a simple LUI/ORI combination or its
1869 lowest bit is set. We don't want to shift in this case. */
1870 return mips_build_lower (codes, value);
1872 else if ((value & 0xffff) == 0)
1874 /* The constant will need at least three actions. The lowest
1875 16 bits are clear, so the final action will be a shift. */
1876 return mips_build_shift (codes, value);
1880 /* The final action could be a shift, add or inclusive OR.
1881 Rather than use a complex condition to select the best
1882 approach, try both mips_build_shift and mips_build_lower
1883 and pick the one that gives the shortest sequence.
1884 Note that this case is only used once per constant. */
1885 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1886 unsigned int cost, alt_cost;
1888 cost = mips_build_shift (codes, value);
1889 alt_cost = mips_build_lower (alt_codes, value);
1890 if (alt_cost < cost)
1892 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1900 /* Move VALUE into register DEST. */
1903 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1905 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1906 enum machine_mode mode;
1907 unsigned int i, cost;
1910 mode = GET_MODE (dest);
1911 cost = mips_build_integer (codes, value);
1913 /* Apply each binary operation to X. Invariant: X is a legitimate
1914 source operand for a SET pattern. */
1915 x = GEN_INT (codes[0].value);
1916 for (i = 1; i < cost; i++)
1919 emit_move_insn (dest, x), x = dest;
1921 x = force_reg (mode, x);
1922 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1925 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1929 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1930 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1934 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1938 temp = no_new_pseudos ? dest : 0;
1940 /* If generating PIC, the high part of an address is loaded from the GOT. */
1941 if (GET_CODE (src) == HIGH)
1943 mips_emit_high (dest, XEXP (src, 0));
1947 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1949 mips_move_integer (dest, INTVAL (src));
1953 /* Fetch global symbols from the GOT. */
1954 if (TARGET_EXPLICIT_RELOCS
1955 && GET_CODE (src) == SYMBOL_REF
1956 && mips_classify_symbol (src) == SYMBOL_GOT_GLOBAL)
1959 src = mips_load_got32 (temp, src, RELOC_GOT_HI, RELOC_GOT_LO);
1961 src = mips_load_got16 (src, RELOC_GOT_DISP);
1962 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
1966 /* Try handling the source operand as a symbolic address. */
1967 if (mips_legitimize_symbol (temp, &src, false))
1969 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
1973 src = force_const_mem (mode, src);
1975 /* When using explicit relocs, constant pool references are sometimes
1976 not legitimate addresses. mips_legitimize_symbol must be able to
1977 deal with all such cases. */
1978 if (GET_CODE (src) == MEM && !memory_operand (src, VOIDmode))
1980 src = copy_rtx (src);
1981 if (!mips_legitimize_symbol (temp, &XEXP (src, 0), false))
1984 emit_move_insn (dest, src);
1988 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1989 sequence that is valid. */
1992 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
1994 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1996 emit_move_insn (dest, force_reg (mode, src));
2000 /* The source of an SImode move must be a move_operand. Likewise
2001 DImode moves on 64-bit targets. We need to deal with constants
2002 that would be legitimate immediate_operands but not legitimate
2004 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
2006 && !move_operand (src, mode))
2008 mips_legitimize_const_move (mode, dest, src);
2009 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2016 /* Convert GOT and GP-relative accesses back into their original form.
2017 Used by both TARGET_DELEGITIMIZE_ADDRESS and FIND_BASE_TERM. */
2020 mips_delegitimize_address (rtx x)
2022 struct mips_constant_info c;
2024 if (GET_CODE (x) == MEM
2025 && GET_CODE (XEXP (x, 0)) == PLUS
2026 && mips_classify_constant (&c, XEXP (XEXP (x, 0), 1)) == CONSTANT_RELOC
2027 && mips_classify_symbol (c.symbol) == SYMBOL_GOT_GLOBAL)
2030 if (GET_CODE (x) == LO_SUM
2031 && XEXP (x, 0) == (TARGET_MIPS16
2032 ? cfun->machine->mips16_gp_pseudo_rtx
2033 : pic_offset_table_rtx))
2039 /* We need a lot of little routines to check constant values on the
2040 mips16. These are used to figure out how long the instruction will
2041 be. It would be much better to do this using constraints, but
2042 there aren't nearly enough letters available. */
2045 m16_check_op (rtx op, int low, int high, int mask)
2047 return (GET_CODE (op) == CONST_INT
2048 && INTVAL (op) >= low
2049 && INTVAL (op) <= high
2050 && (INTVAL (op) & mask) == 0);
2054 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2056 return m16_check_op (op, 0x1, 0x8, 0);
2060 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2062 return m16_check_op (op, - 0x8, 0x7, 0);
2066 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2068 return m16_check_op (op, - 0x7, 0x8, 0);
2072 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2074 return m16_check_op (op, - 0x10, 0xf, 0);
2078 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2080 return m16_check_op (op, - 0xf, 0x10, 0);
2084 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2086 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2090 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2092 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2096 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2098 return m16_check_op (op, - 0x80, 0x7f, 0);
2102 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2104 return m16_check_op (op, - 0x7f, 0x80, 0);
2108 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2110 return m16_check_op (op, 0x0, 0xff, 0);
2114 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2116 return m16_check_op (op, - 0xff, 0x0, 0);
2120 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2122 return m16_check_op (op, - 0x1, 0xfe, 0);
2126 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2128 return m16_check_op (op, 0x0, 0xff << 2, 3);
2132 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2134 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2138 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2140 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2144 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2146 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2149 /* References to the string table on the mips16 only use a small
2150 offset if the function is small. We can't check for LABEL_REF here,
2151 because the offset is always large if the label is before the
2152 referencing instruction. */
2155 m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2157 if (GET_CODE (op) == SYMBOL_REF
2158 && SYMBOL_REF_FLAG (op)
2159 && cfun->machine->insns_len > 0
2160 && INTERNAL_SYMBOL_P (op)
2161 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2164 struct string_constant *l;
2166 /* Make sure this symbol is on thelist of string constants to be
2167 output for this function. It is possible that it has already
2168 been output, in which case this requires a large offset. */
2169 for (l = string_constants; l != NULL; l = l->next)
2170 if (strcmp (l->label, XSTR (op, 0)) == 0)
2178 m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2180 if (GET_CODE (op) == SYMBOL_REF
2181 && SYMBOL_REF_FLAG (op)
2182 && cfun->machine->insns_len > 0
2183 && INTERNAL_SYMBOL_P (op)
2184 && (cfun->machine->insns_len + get_pool_size () + mips_string_length
2187 struct string_constant *l;
2189 /* Make sure this symbol is on thelist of string constants to be
2190 output for this function. It is possible that it has already
2191 been output, in which case this requires a large offset. */
2192 for (l = string_constants; l != NULL; l = l->next)
2193 if (strcmp (l->label, XSTR (op, 0)) == 0)
2201 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2203 enum machine_mode mode = GET_MODE (x);
2210 /* Always return 0, since we don't have different sized
2211 instructions, hence different costs according to Richard
2217 /* A number between 1 and 8 inclusive is efficient for a shift.
2218 Otherwise, we will need an extended instruction. */
2219 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2220 || (outer_code) == LSHIFTRT)
2222 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2225 *total = COSTS_N_INSNS (1);
2229 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2230 if ((outer_code) == XOR
2231 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2237 /* We may be able to use slt or sltu for a comparison with a
2238 signed 16 bit value. (The boundary conditions aren't quite
2239 right, but this is just a heuristic anyhow.) */
2240 if (((outer_code) == LT || (outer_code) == LE
2241 || (outer_code) == GE || (outer_code) == GT
2242 || (outer_code) == LTU || (outer_code) == LEU
2243 || (outer_code) == GEU || (outer_code) == GTU)
2244 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2250 /* Equality comparisons with 0 are cheap. */
2251 if (((outer_code) == EQ || (outer_code) == NE)
2258 /* Otherwise fall through to the handling below. */
2264 if (((outer_code) == PLUS || (outer_code) == MINUS)
2265 && const_arith_operand (x, VOIDmode))
2272 int n = mips_const_insns (x);
2273 return (n == 0 ? CONSTANT_POOL_COST : COSTS_N_INSNS (n));
2278 /* If the address is legitimate, return the number of
2279 instructions it needs, otherwise use the default handling. */
2280 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2283 *total = COSTS_N_INSNS (1 + n);
2290 *total = COSTS_N_INSNS (6);
2294 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2300 if (mode == DImode && !TARGET_64BIT)
2302 *total = COSTS_N_INSNS (2);
2310 if (mode == DImode && !TARGET_64BIT)
2312 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2319 if (mode == SFmode || mode == DFmode)
2320 *total = COSTS_N_INSNS (1);
2322 *total = COSTS_N_INSNS (4);
2326 *total = COSTS_N_INSNS (1);
2331 if (mode == SFmode || mode == DFmode)
2333 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2334 *total = COSTS_N_INSNS (2);
2335 else if (TUNE_MIPS6000)
2336 *total = COSTS_N_INSNS (3);
2338 *total = COSTS_N_INSNS (6);
2341 if (mode == DImode && !TARGET_64BIT)
2343 *total = COSTS_N_INSNS (4);
2349 if (mode == DImode && !TARGET_64BIT)
2362 *total = COSTS_N_INSNS (4);
2363 else if (TUNE_MIPS6000
2366 *total = COSTS_N_INSNS (5);
2368 *total = COSTS_N_INSNS (7);
2377 *total = COSTS_N_INSNS (5);
2378 else if (TUNE_MIPS6000
2381 *total = COSTS_N_INSNS (6);
2383 *total = COSTS_N_INSNS (8);
2388 *total = COSTS_N_INSNS (12);
2389 else if (TUNE_MIPS3900)
2390 *total = COSTS_N_INSNS (2);
2391 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2392 *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
2393 else if (TUNE_MIPS7000)
2394 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2395 else if (TUNE_MIPS9000)
2396 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2397 else if (TUNE_MIPS6000)
2398 *total = COSTS_N_INSNS (17);
2399 else if (TUNE_MIPS5000)
2400 *total = COSTS_N_INSNS (5);
2402 *total = COSTS_N_INSNS (10);
2411 *total = COSTS_N_INSNS (12);
2412 else if (TUNE_MIPS6000)
2413 *total = COSTS_N_INSNS (15);
2414 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2415 *total = COSTS_N_INSNS (30);
2417 *total = COSTS_N_INSNS (23);
2425 *total = COSTS_N_INSNS (19);
2426 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2427 *total = COSTS_N_INSNS (59);
2428 else if (TUNE_MIPS6000)
2429 *total = COSTS_N_INSNS (16);
2431 *total = COSTS_N_INSNS (36);
2440 *total = COSTS_N_INSNS (35);
2441 else if (TUNE_MIPS6000)
2442 *total = COSTS_N_INSNS (38);
2443 else if (TUNE_MIPS5000)
2444 *total = COSTS_N_INSNS (36);
2445 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2446 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2448 *total = COSTS_N_INSNS (69);
2452 /* A sign extend from SImode to DImode in 64 bit mode is often
2453 zero instructions, because the result can often be used
2454 directly by another instruction; we'll call it one. */
2455 if (TARGET_64BIT && mode == DImode
2456 && GET_MODE (XEXP (x, 0)) == SImode)
2457 *total = COSTS_N_INSNS (1);
2459 *total = COSTS_N_INSNS (2);
2463 if (TARGET_64BIT && mode == DImode
2464 && GET_MODE (XEXP (x, 0)) == SImode)
2465 *total = COSTS_N_INSNS (2);
2467 *total = COSTS_N_INSNS (1);
2475 /* Provide the costs of an addressing mode that contains ADDR.
2476 If ADDR is not a valid address, its cost is irrelevant. */
2479 mips_address_cost (rtx addr)
2481 return mips_address_insns (addr, SImode);
2484 /* Return a pseudo that points to the address of the current function.
2485 The first time it is called for a function, an initializer for the
2486 pseudo is emitted in the beginning of the function. */
2489 embedded_pic_fnaddr_reg (void)
2491 if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
2495 cfun->machine->embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
2497 /* Output code at function start to initialize the pseudo-reg. */
2498 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
2499 inline functions, because it is called after RTL for the function
2500 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
2501 does not get copied, and ends up not matching the rest of the RTL.
2502 This solution works, but means that we get unnecessary code to
2503 initialize this value every time a function is inlined into another
2506 emit_insn (gen_get_fnaddr (cfun->machine->embedded_pic_fnaddr_rtx,
2507 XEXP (DECL_RTL (current_function_decl), 0)));
2510 push_topmost_sequence ();
2511 emit_insn_after (seq, get_insns ());
2512 pop_topmost_sequence ();
2515 return cfun->machine->embedded_pic_fnaddr_rtx;
2518 /* Return RTL for the offset from the current function to the argument.
2519 X is the symbol whose offset from the current function we want. */
2522 embedded_pic_offset (rtx x)
2524 /* Make sure it is emitted. */
2525 embedded_pic_fnaddr_reg ();
2528 gen_rtx_CONST (Pmode,
2529 gen_rtx_MINUS (Pmode, x,
2530 XEXP (DECL_RTL (current_function_decl), 0)));
2533 /* Return one word of double-word value OP, taking into account the fixed
2534 endianness of certain registers. HIGH_P is true to select the high part,
2535 false to select the low part. */
2538 mips_subword (rtx op, int high_p)
2541 enum machine_mode mode;
2543 mode = GET_MODE (op);
2544 if (mode == VOIDmode)
2547 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2548 byte = UNITS_PER_WORD;
2552 if (GET_CODE (op) == REG)
2554 if (FP_REG_P (REGNO (op)))
2555 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2556 if (REGNO (op) == HI_REGNUM)
2557 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2560 if (GET_CODE (op) == MEM)
2561 return adjust_address (op, word_mode, byte);
2563 return simplify_gen_subreg (word_mode, op, mode, byte);
2567 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2570 mips_split_64bit_move_p (rtx dest, rtx src)
2575 /* FP->FP moves can be done in a single instruction. */
2576 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2579 /* Check for floating-point loads and stores. They can be done using
2580 ldc1 and sdc1 on MIPS II and above. */
2583 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2585 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2592 /* Split a 64-bit move from SRC to DEST assuming that
2593 mips_split_64bit_move_p holds.
2595 Moves into and out of FPRs cause some difficulty here. Such moves
2596 will always be DFmode, since paired FPRs are not allowed to store
2597 DImode values. The most natural representation would be two separate
2598 32-bit moves, such as:
2600 (set (reg:SI $f0) (mem:SI ...))
2601 (set (reg:SI $f1) (mem:SI ...))
2603 However, the second insn is invalid because odd-numbered FPRs are
2604 not allowed to store independent values. Use the patterns load_df_low,
2605 load_df_high and store_df_high instead. */
2608 mips_split_64bit_move (rtx dest, rtx src)
2610 if (FP_REG_RTX_P (dest))
2612 /* Loading an FPR from memory or from GPRs. */
2613 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2614 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2617 else if (FP_REG_RTX_P (src))
2619 /* Storing an FPR into memory or GPRs. */
2620 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2621 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2625 /* The operation can be split into two normal moves. Decide in
2626 which order to do them. */
2629 low_dest = mips_subword (dest, 0);
2630 if (GET_CODE (low_dest) == REG
2631 && reg_overlap_mentioned_p (low_dest, src))
2633 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2634 emit_move_insn (low_dest, mips_subword (src, 0));
2638 emit_move_insn (low_dest, mips_subword (src, 0));
2639 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2644 /* Return the appropriate instructions to move SRC into DEST. Assume
2645 that SRC is operand 1 and DEST is operand 0. */
2648 mips_output_move (rtx dest, rtx src)
2650 enum rtx_code dest_code, src_code;
2651 struct mips_constant_info c;
2654 dest_code = GET_CODE (dest);
2655 src_code = GET_CODE (src);
2656 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2658 if (dbl_p && mips_split_64bit_move_p (dest, src))
2661 if ((src_code == REG && GP_REG_P (REGNO (src)))
2662 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2664 if (dest_code == REG)
2666 if (GP_REG_P (REGNO (dest)))
2667 return "move\t%0,%z1";
2669 if (MD_REG_P (REGNO (dest)))
2672 if (FP_REG_P (REGNO (dest)))
2673 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2675 if (ALL_COP_REG_P (REGNO (dest)))
2677 static char retval[] = "dmtc_\t%z1,%0";
2679 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2680 return (dbl_p ? retval : retval + 1);
2683 if (dest_code == MEM)
2684 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2686 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2688 if (src_code == REG)
2690 if (MD_REG_P (REGNO (src)))
2693 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2694 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2696 if (FP_REG_P (REGNO (src)))
2697 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2699 if (ALL_COP_REG_P (REGNO (src)))
2701 static char retval[] = "dmfc_\t%0,%1";
2703 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2704 return (dbl_p ? retval : retval + 1);
2708 if (src_code == MEM)
2709 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2711 if (src_code == CONST_INT)
2713 /* Don't use the X format, because that will give out of
2714 range numbers for 64 bit hosts and 32 bit targets. */
2716 return "li\t%0,%1\t\t\t# %X1";
2718 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2721 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2722 return "li\t%0,%n1\n\tneg\t%0";
2725 if (src_code == HIGH)
2726 return "lui\t%0,%h1";
2728 switch (mips_classify_constant (&c, src))
2734 return "move\t%0,%1";
2736 case CONSTANT_RELOC:
2739 case CONSTANT_SYMBOLIC:
2740 return (dbl_p ? "dla\t%0,%a1" : "la\t%0,%a1");
2743 if (src_code == REG && FP_REG_P (REGNO (src)))
2745 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2746 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2748 if (dest_code == MEM)
2749 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2751 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2753 if (src_code == MEM)
2754 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2756 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2758 static char retval[] = "l_c_\t%0,%1";
2760 retval[1] = (dbl_p ? 'd' : 'w');
2761 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2764 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2766 static char retval[] = "s_c_\t%1,%0";
2768 retval[1] = (dbl_p ? 'd' : 'w');
2769 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2775 /* Return an rtx for the gp save slot. Valid only when using o32 or
2779 mips_gp_save_slot (void)
2783 if (!TARGET_ABICALLS || TARGET_NEWABI)
2786 if (frame_pointer_needed)
2787 loc = hard_frame_pointer_rtx;
2789 loc = stack_pointer_rtx;
2790 loc = plus_constant (loc, current_function_outgoing_args_size);
2791 loc = gen_rtx_MEM (Pmode, loc);
2792 RTX_UNCHANGING_P (loc) = 1;
2796 /* Make normal rtx_code into something we can index from an array */
2798 static enum internal_test
2799 map_test_to_internal_test (enum rtx_code test_code)
2801 enum internal_test test = ITEST_MAX;
2805 case EQ: test = ITEST_EQ; break;
2806 case NE: test = ITEST_NE; break;
2807 case GT: test = ITEST_GT; break;
2808 case GE: test = ITEST_GE; break;
2809 case LT: test = ITEST_LT; break;
2810 case LE: test = ITEST_LE; break;
2811 case GTU: test = ITEST_GTU; break;
2812 case GEU: test = ITEST_GEU; break;
2813 case LTU: test = ITEST_LTU; break;
2814 case LEU: test = ITEST_LEU; break;
2822 /* Generate the code to compare two integer values. The return value is:
2823 (reg:SI xx) The pseudo register the comparison is in
2824 0 No register, generate a simple branch.
2826 ??? This is called with result nonzero by the Scond patterns in
2827 mips.md. These patterns are called with a target in the mode of
2828 the Scond instruction pattern. Since this must be a constant, we
2829 must use SImode. This means that if RESULT is nonzero, it will
2830 always be an SImode register, even if TARGET_64BIT is true. We
2831 cope with this by calling convert_move rather than emit_move_insn.
2832 This will sometimes lead to an unnecessary extension of the result;
2841 TEST_CODE is the rtx code for the comparison.
2842 CMP0 and CMP1 are the two operands to compare.
2843 RESULT is the register in which the result should be stored (null for
2845 For branches, P_INVERT points to an integer that is nonzero on return
2846 if the branch should be inverted. */
2849 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2850 rtx cmp1, int *p_invert)
2854 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2855 int const_low; /* low bound of constant we can accept */
2856 int const_high; /* high bound of constant we can accept */
2857 int const_add; /* constant to add (convert LE -> LT) */
2858 int reverse_regs; /* reverse registers in test */
2859 int invert_const; /* != 0 if invert value if cmp1 is constant */
2860 int invert_reg; /* != 0 if invert value if cmp1 is register */
2861 int unsignedp; /* != 0 for unsigned comparisons. */
2864 static const struct cmp_info info[ (int)ITEST_MAX ] = {
2866 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2867 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2868 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2869 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2870 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2871 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2872 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2873 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2874 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2875 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2878 enum internal_test test;
2879 enum machine_mode mode;
2880 const struct cmp_info *p_info;
2887 test = map_test_to_internal_test (test_code);
2888 if (test == ITEST_MAX)
2891 p_info = &info[(int) test];
2892 eqne_p = (p_info->test_code == XOR);
2894 mode = GET_MODE (cmp0);
2895 if (mode == VOIDmode)
2896 mode = GET_MODE (cmp1);
2898 /* Eliminate simple branches */
2899 branch_p = (result == 0);
2902 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2904 /* Comparisons against zero are simple branches */
2905 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2906 && (! TARGET_MIPS16 || eqne_p))
2909 /* Test for beq/bne. */
2910 if (eqne_p && ! TARGET_MIPS16)
2914 /* allocate a pseudo to calculate the value in. */
2915 result = gen_reg_rtx (mode);
2918 /* Make sure we can handle any constants given to us. */
2919 if (GET_CODE (cmp0) == CONST_INT)
2920 cmp0 = force_reg (mode, cmp0);
2922 if (GET_CODE (cmp1) == CONST_INT)
2924 HOST_WIDE_INT value = INTVAL (cmp1);
2926 if (value < p_info->const_low
2927 || value > p_info->const_high
2928 /* ??? Why? And why wasn't the similar code below modified too? */
2930 && HOST_BITS_PER_WIDE_INT < 64
2931 && p_info->const_add != 0
2932 && ((p_info->unsignedp
2933 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2934 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2935 : (value + p_info->const_add) > INTVAL (cmp1))
2936 != (p_info->const_add > 0))))
2937 cmp1 = force_reg (mode, cmp1);
2940 /* See if we need to invert the result. */
2941 invert = (GET_CODE (cmp1) == CONST_INT
2942 ? p_info->invert_const : p_info->invert_reg);
2944 if (p_invert != (int *)0)
2950 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2951 Comparison between two registers, may involve switching operands. */
2952 if (GET_CODE (cmp1) == CONST_INT)
2954 if (p_info->const_add != 0)
2956 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2958 /* If modification of cmp1 caused overflow,
2959 we would get the wrong answer if we follow the usual path;
2960 thus, x > 0xffffffffU would turn into x > 0U. */
2961 if ((p_info->unsignedp
2962 ? (unsigned HOST_WIDE_INT) new >
2963 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2964 : new > INTVAL (cmp1))
2965 != (p_info->const_add > 0))
2967 /* This test is always true, but if INVERT is true then
2968 the result of the test needs to be inverted so 0 should
2969 be returned instead. */
2970 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2974 cmp1 = GEN_INT (new);
2978 else if (p_info->reverse_regs)
2985 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2989 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2990 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2993 if (test == ITEST_NE)
2995 if (! TARGET_MIPS16)
2997 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2998 if (p_invert != NULL)
3004 reg2 = invert ? gen_reg_rtx (mode) : result;
3005 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3010 else if (test == ITEST_EQ)
3012 reg2 = invert ? gen_reg_rtx (mode) : result;
3013 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3021 if (! TARGET_MIPS16)
3025 /* The value is in $24. Copy it to another register, so
3026 that reload doesn't think it needs to store the $24 and
3027 the input to the XOR in the same location. */
3028 reg2 = gen_reg_rtx (mode);
3029 emit_move_insn (reg2, reg);
3031 one = force_reg (mode, const1_rtx);
3033 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3039 /* Work out how to check a floating-point condition. We need a
3040 separate comparison instruction (C.cond.fmt), followed by a
3041 branch or conditional move. Given that IN_CODE is the
3042 required condition, set *CMP_CODE to the C.cond.fmt code
3043 and *action_code to the branch or move code. */
3046 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
3047 enum rtx_code *action_code)
3056 *cmp_code = reverse_condition_maybe_unordered (in_code);
3061 *cmp_code = in_code;
3067 /* Emit the common code for doing conditional branches.
3068 operand[0] is the label to jump to.
3069 The comparison operands are saved away by cmp{si,di,sf,df}. */
3072 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
3074 enum cmp_type type = branch_type;
3075 rtx cmp0 = branch_cmp[0];
3076 rtx cmp1 = branch_cmp[1];
3077 enum machine_mode mode;
3078 enum rtx_code cmp_code;
3087 mode = type == CMP_SI ? SImode : DImode;
3089 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3097 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3098 /* We don't want to build a comparison against a nonzero
3100 cmp1 = force_reg (mode, cmp1);
3107 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3109 reg = gen_reg_rtx (CCmode);
3111 get_float_compare_codes (test_code, &cmp_code, &test_code);
3112 emit_insn (gen_rtx_SET (VOIDmode, reg,
3113 gen_rtx (cmp_code, CCmode, cmp0, cmp1)));
3122 fatal_insn ("bad test", gen_rtx (test_code, VOIDmode, cmp0, cmp1));
3125 /* Generate the branch. */
3127 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3136 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3137 gen_rtx_IF_THEN_ELSE (VOIDmode,
3138 gen_rtx (test_code, mode,
3143 /* Emit the common code for conditional moves. OPERANDS is the array
3144 of operands passed to the conditional move define_expand. */
3147 gen_conditional_move (rtx *operands)
3149 rtx op0 = branch_cmp[0];
3150 rtx op1 = branch_cmp[1];
3151 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3152 enum rtx_code cmp_code = GET_CODE (operands[1]);
3153 enum rtx_code move_code = NE;
3154 enum machine_mode op_mode = GET_MODE (operands[0]);
3155 enum machine_mode cmp_mode;
3158 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3177 op0 = force_reg (mode, branch_cmp[1]);
3178 op1 = branch_cmp[0];
3182 op0 = force_reg (mode, branch_cmp[1]);
3183 op1 = branch_cmp[0];
3194 op0 = force_reg (mode, branch_cmp[1]);
3195 op1 = branch_cmp[0];
3199 op0 = force_reg (mode, branch_cmp[1]);
3200 op1 = branch_cmp[0];
3208 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3210 if (mode == SImode || mode == DImode)
3212 else if (mode == SFmode || mode == DFmode)
3217 cmp_reg = gen_reg_rtx (cmp_mode);
3218 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3219 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3221 emit_insn (gen_rtx_SET (op_mode, operands[0],
3222 gen_rtx_IF_THEN_ELSE (op_mode,
3223 gen_rtx (move_code, VOIDmode,
3225 CONST0_RTX (SImode)),
3226 operands[2], operands[3])));
3229 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3230 the conditional_trap expander. */
3233 mips_gen_conditional_trap (rtx *operands)
3236 enum rtx_code cmp_code = GET_CODE (operands[0]);
3237 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3239 /* MIPS conditional trap machine instructions don't have GT or LE
3240 flavors, so we must invert the comparison and convert to LT and
3241 GE, respectively. */
3244 case GT: cmp_code = LT; break;
3245 case LE: cmp_code = GE; break;
3246 case GTU: cmp_code = LTU; break;
3247 case LEU: cmp_code = GEU; break;
3250 if (cmp_code == GET_CODE (operands[0]))
3252 op0 = force_reg (mode, branch_cmp[0]);
3253 op1 = branch_cmp[1];
3257 op0 = force_reg (mode, branch_cmp[1]);
3258 op1 = branch_cmp[0];
3260 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3261 op1 = force_reg (mode, op1);
3263 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3264 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3268 /* Expand a call or call_value instruction. RESULT is where the
3269 result will go (null for calls), ADDR is the address of the
3270 function, ARGS_SIZE is the size of the arguments and AUX is
3271 the value passed to us by mips_function_arg. SIBCALL_P is true
3272 if we are expanding a sibling call, false if we're expanding
3276 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3278 if (!call_insn_operand (addr, VOIDmode))
3280 /* When generating PIC, try to allow global functions to be
3282 if (TARGET_EXPLICIT_RELOCS
3283 && GET_CODE (addr) == SYMBOL_REF
3284 && mips_classify_symbol (addr) == SYMBOL_GOT_GLOBAL)
3287 addr = mips_load_got32 (0, addr, RELOC_CALL_HI, RELOC_CALL_LO);
3289 addr = mips_load_got16 (addr, RELOC_CALL16);
3291 addr = force_reg (Pmode, addr);
3295 && mips16_hard_float
3296 && build_mips16_call_stub (result, addr, args_size,
3297 aux == 0 ? 0 : (int) GET_MODE (aux)))
3298 /* Nothing more to do */;
3299 else if (result == 0)
3300 emit_call_insn (sibcall_p
3301 ? gen_sibcall_internal (addr, args_size)
3302 : gen_call_internal (addr, args_size));
3303 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3307 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3308 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3311 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3312 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3315 emit_call_insn (sibcall_p
3316 ? gen_sibcall_value_internal (result, addr, args_size)
3317 : gen_call_value_internal (result, addr, args_size));
3321 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3324 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3325 tree exp ATTRIBUTE_UNUSED)
3327 return TARGET_SIBCALLS;
3330 /* Return true if operand OP is a condition code register.
3331 Only for use during or after reload. */
3334 fcc_register_operand (rtx op, enum machine_mode mode)
3336 return ((mode == VOIDmode || mode == GET_MODE (op))
3337 && (reload_in_progress || reload_completed)
3338 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3339 && ST_REG_P (true_regnum (op)));
3342 /* Emit code to move general operand SRC into condition-code
3343 register DEST. SCRATCH is a scratch TFmode float register.
3350 where FP1 and FP2 are single-precision float registers
3351 taken from SCRATCH. */
3354 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3358 /* Change the source to SFmode. */
3359 if (GET_CODE (src) == MEM)
3360 src = adjust_address (src, SFmode, 0);
3361 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3362 src = gen_rtx_REG (SFmode, true_regnum (src));
3364 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3365 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3367 emit_move_insn (copy_rtx (fp1), src);
3368 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3369 emit_insn (gen_slt_sf (dest, fp2, fp1));
3372 /* Emit code to change the current function's return address to
3373 ADDRESS. SCRATCH is available as a scratch register, if needed.
3374 ADDRESS and SCRATCH are both word-mode GPRs. */
3377 mips_set_return_address (rtx address, rtx scratch)
3379 HOST_WIDE_INT gp_offset;
3381 compute_frame_size (get_frame_size ());
3382 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3384 gp_offset = cfun->machine->frame.gp_sp_offset;
3386 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3387 if (gp_offset < 32768)
3388 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3391 emit_move_insn (scratch, GEN_INT (gp_offset));
3392 if (Pmode == DImode)
3393 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3395 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3398 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3401 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3402 Assume that the areas do not overlap. */
3405 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3407 HOST_WIDE_INT offset, delta;
3408 unsigned HOST_WIDE_INT bits;
3410 enum machine_mode mode;
3413 /* Work out how many bits to move at a time. If both operands have
3414 half-word alignment, it is usually better to move in half words.
3415 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3416 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3417 Otherwise move word-sized chunks. */
3418 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3419 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3420 bits = BITS_PER_WORD / 2;
3422 bits = BITS_PER_WORD;
3424 mode = mode_for_size (bits, MODE_INT, 0);
3425 delta = bits / BITS_PER_UNIT;
3427 /* Allocate a buffer for the temporary registers. */
3428 regs = alloca (sizeof (rtx) * length / delta);
3430 /* Load as many BITS-sized chunks as possible. Use a normal load if
3431 the source has enough alignment, otherwise use left/right pairs. */
3432 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3436 regs[i] = gen_reg_rtx (mode);
3437 part = adjust_address (src, mode, offset);
3438 if (MEM_ALIGN (part) >= bits)
3439 emit_move_insn (regs[i], part);
3440 else if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3444 /* Copy the chunks to the destination. */
3445 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3449 part = adjust_address (dest, mode, offset);
3450 if (MEM_ALIGN (part) >= bits)
3451 emit_move_insn (part, regs[i]);
3452 else if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3456 /* Mop up any left-over bytes. */
3457 if (offset < length)
3459 src = adjust_address (src, mode, offset);
3460 dest = adjust_address (dest, mode, offset);
3461 move_by_pieces (dest, src, length - offset,
3462 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3466 #define MAX_MOVE_REGS 4
3467 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3470 /* Helper function for doing a loop-based block operation on memory
3471 reference MEM. Each iteration of the loop will operate on LENGTH
3474 Create a new base register for use within the loop and point it to
3475 the start of MEM. Create a new memory reference that uses this
3476 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3479 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3480 rtx *loop_reg, rtx *loop_mem)
3482 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3484 /* Although the new mem does not refer to a known location,
3485 it does keep up to LENGTH bytes of alignment. */
3486 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3487 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3491 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3492 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3493 memory regions do not overlap. */
3496 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3498 rtx label, src_reg, dest_reg, final_src;
3499 HOST_WIDE_INT leftover;
3501 leftover = length % MAX_MOVE_BYTES;
3504 /* Create registers and memory references for use within the loop. */
3505 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3506 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3508 /* Calculate the value that SRC_REG should have after the last iteration
3510 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3513 /* Emit the start of the loop. */
3514 label = gen_label_rtx ();
3517 /* Emit the loop body. */
3518 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3520 /* Move on to the next block. */
3521 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3522 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3524 /* Emit the loop condition. */
3525 if (Pmode == DImode)
3526 emit_insn (gen_cmpdi (src_reg, final_src));
3528 emit_insn (gen_cmpsi (src_reg, final_src));
3529 emit_jump_insn (gen_bne (label));
3531 /* Mop up any left-over bytes. */
3533 mips_block_move_straight (dest, src, leftover);
3536 /* Expand a movstrsi instruction. */
3539 mips_expand_block_move (rtx dest, rtx src, rtx length)
3541 if (GET_CODE (length) == CONST_INT)
3543 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3545 mips_block_move_straight (dest, src, INTVAL (length));
3550 mips_block_move_loop (dest, src, INTVAL (length));
3557 /* Argument support functions. */
3559 /* Initialize CUMULATIVE_ARGS for a function. */
3562 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3563 rtx libname ATTRIBUTE_UNUSED)
3565 static CUMULATIVE_ARGS zero_cum;
3566 tree param, next_param;
3568 if (TARGET_DEBUG_E_MODE)
3571 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3574 fputc ('\n', stderr);
3578 tree ret_type = TREE_TYPE (fntype);
3579 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3580 tree_code_name[(int)TREE_CODE (fntype)],
3581 tree_code_name[(int)TREE_CODE (ret_type)]);
3586 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3588 /* Determine if this function has variable arguments. This is
3589 indicated by the last argument being 'void_type_mode' if there
3590 are no variable arguments. The standard MIPS calling sequence
3591 passes all arguments in the general purpose registers in this case. */
3593 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3594 param != 0; param = next_param)
3596 next_param = TREE_CHAIN (param);
3597 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3598 cum->gp_reg_found = 1;
3603 /* Fill INFO with information about a single argument. CUM is the
3604 cumulative state for earlier arguments. MODE is the mode of this
3605 argument and TYPE is its type (if known). NAMED is true if this
3606 is a named (fixed) argument rather than a variable one. */
3609 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3610 tree type, int named, struct mips_arg_info *info)
3613 unsigned int num_words, max_regs;
3615 /* Decide whether this argument should go in a floating-point register,
3616 assuming one is free. Later code checks for availability. */
3618 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3619 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3626 info->fpr_p = (!cum->gp_reg_found
3627 && cum->arg_number < 2
3628 && (type == 0 || FLOAT_TYPE_P (type)));
3633 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3637 /* Now decide whether the argument must go in an even-numbered register. */
3642 /* Under the O64 ABI, the second float argument goes in $f13 if it
3643 is a double, but $f14 if it is a single. Otherwise, on a
3644 32-bit double-float machine, each FP argument must start in a
3645 new register pair. */
3646 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3647 || (mips_abi == ABI_O64 && mode == SFmode)
3650 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3652 if (GET_MODE_CLASS (mode) == MODE_INT
3653 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3654 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3656 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3660 if (mips_abi != ABI_EABI && MUST_PASS_IN_STACK (mode, type))
3661 /* This argument must be passed on the stack. Eat up all the
3662 remaining registers. */
3663 info->reg_offset = MAX_ARGS_IN_REGISTERS;
3666 /* Set REG_OFFSET to the register count we're interested in.
3667 The EABI allocates the floating-point registers separately,
3668 but the other ABIs allocate them like integer registers. */
3669 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3674 info->reg_offset += info->reg_offset & 1;
3677 /* The alignment applied to registers is also applied to stack arguments. */
3678 info->stack_offset = cum->stack_words;
3680 info->stack_offset += info->stack_offset & 1;
3682 if (mode == BLKmode)
3683 info->num_bytes = int_size_in_bytes (type);
3685 info->num_bytes = GET_MODE_SIZE (mode);
3687 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3688 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3690 /* Partition the argument between registers and stack. */
3691 info->reg_words = MIN (num_words, max_regs);
3692 info->stack_words = num_words - info->reg_words;
3696 /* Implement FUNCTION_ARG_ADVANCE. */
3699 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3700 tree type, int named)
3702 struct mips_arg_info info;
3704 mips_arg_info (cum, mode, type, named, &info);
3707 cum->gp_reg_found = true;
3709 /* See the comment above the cumulative args structure in mips.h
3710 for an explanation of what this code does. It assumes the O32
3711 ABI, which passes at most 2 arguments in float registers. */
3712 if (cum->arg_number < 2 && info.fpr_p)
3713 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3715 if (mips_abi != ABI_EABI || !info.fpr_p)
3716 cum->num_gprs = info.reg_offset + info.reg_words;
3717 else if (info.reg_words > 0)
3718 cum->num_fprs += FP_INC;
3720 if (info.stack_words > 0)
3721 cum->stack_words = info.stack_offset + info.stack_words;
3726 /* Implement FUNCTION_ARG. */
3729 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3730 tree type, int named)
3732 struct mips_arg_info info;
3734 /* We will be called with a mode of VOIDmode after the last argument
3735 has been seen. Whatever we return will be passed to the call
3736 insn. If we need a mips16 fp_code, return a REG with the code
3737 stored as the mode. */
3738 if (mode == VOIDmode)
3740 if (TARGET_MIPS16 && cum->fp_code != 0)
3741 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3747 mips_arg_info (cum, mode, type, named, &info);
3749 /* Return straight away if the whole argument is passed on the stack. */
3750 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3754 && TREE_CODE (type) == RECORD_TYPE
3755 && (mips_abi == ABI_N32 || mips_abi == ABI_64)
3756 && TYPE_SIZE_UNIT (type)
3757 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3760 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3761 structure contains a double in its entirety, then that 64 bit
3762 chunk is passed in a floating point register. */
3765 /* First check to see if there is any such field. */
3766 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3767 if (TREE_CODE (field) == FIELD_DECL
3768 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3769 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3770 && host_integerp (bit_position (field), 0)
3771 && int_bit_position (field) % BITS_PER_WORD == 0)
3776 /* Now handle the special case by returning a PARALLEL
3777 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3778 chunks are passed in registers. */
3780 HOST_WIDE_INT bitpos;
3783 /* assign_parms checks the mode of ENTRY_PARM, so we must
3784 use the actual mode here. */
3785 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3788 field = TYPE_FIELDS (type);
3789 for (i = 0; i < info.reg_words; i++)
3793 for (; field; field = TREE_CHAIN (field))
3794 if (TREE_CODE (field) == FIELD_DECL
3795 && int_bit_position (field) >= bitpos)
3799 && int_bit_position (field) == bitpos
3800 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3801 && !TARGET_SOFT_FLOAT
3802 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3803 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3805 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3808 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3809 GEN_INT (bitpos / BITS_PER_UNIT));
3811 bitpos += BITS_PER_WORD;
3818 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3820 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3824 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3827 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3828 enum machine_mode mode, tree type, int named)
3830 struct mips_arg_info info;
3832 mips_arg_info (cum, mode, type, named, &info);
3833 return info.stack_words > 0 ? info.reg_words : 0;
3837 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3838 upward rather than downward. In other words, return true if the
3839 first byte of the stack slot has useful data, false if the last
3843 mips_pad_arg_upward (enum machine_mode mode, tree type)
3845 /* On little-endian targets, the first byte of every stack argument
3846 is passed in the first byte of the stack slot. */
3847 if (!BYTES_BIG_ENDIAN)
3850 /* Otherwise, integral types are padded downward: the last byte of a
3851 stack argument is passed in the last byte of the stack slot. */
3853 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3854 : GET_MODE_CLASS (mode) == MODE_INT)
3857 /* Big-endian o64 pads floating-point arguments downward. */
3858 if (mips_abi == ABI_O64)
3859 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3862 /* Other types are padded upward for o32, o64, n32 and n64. */
3863 if (mips_abi != ABI_EABI)
3866 /* Arguments smaller than a stack slot are padded downward. */
3867 if (mode != BLKmode)
3868 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3870 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3874 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3875 if the least significant byte of the register has useful data. Return
3876 the opposite if the most significant byte does. */
3879 mips_pad_reg_upward (enum machine_mode mode, tree type)
3881 /* No shifting is required for floating-point arguments. */
3882 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3883 return !BYTES_BIG_ENDIAN;
3885 /* Otherwise, apply the same padding to register arguments as we do
3886 to stack arguments. */
3887 return mips_pad_arg_upward (mode, type);
3891 mips_setup_incoming_varargs (const CUMULATIVE_ARGS *cum,
3892 enum machine_mode mode, tree type, int no_rtl)
3894 CUMULATIVE_ARGS local_cum;
3895 int gp_saved, fp_saved;
3897 /* The caller has advanced CUM up to, but not beyond, the last named
3898 argument. Advance a local copy of CUM past the last "real" named
3899 argument, to find out how many registers are left over. */
3902 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3904 /* Found out how many registers we need to save. */
3905 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3906 fp_saved = (EABI_FLOAT_VARARGS_P
3907 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3916 ptr = virtual_incoming_args_rtx;
3921 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3925 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3928 mem = gen_rtx_MEM (BLKmode, ptr);
3929 set_mem_alias_set (mem, get_varargs_alias_set ());
3931 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3936 /* We can't use move_block_from_reg, because it will use
3938 enum machine_mode mode;
3941 /* Set OFF to the offset from virtual_incoming_args_rtx of
3942 the first float register. The FP save area lies below
3943 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3944 off = -gp_saved * UNITS_PER_WORD;
3945 off &= ~(UNITS_PER_FPVALUE - 1);
3946 off -= fp_saved * UNITS_PER_FPREG;
3948 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3950 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3954 ptr = plus_constant (virtual_incoming_args_rtx, off);
3955 mem = gen_rtx_MEM (mode, ptr);
3956 set_mem_alias_set (mem, get_varargs_alias_set ());
3957 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3958 off += UNITS_PER_HWFPVALUE;
3962 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3963 /* No need for pretend arguments: the register parameter area was
3964 allocated by the caller. */
3966 return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3969 /* Create the va_list data type.
3970 We keep 3 pointers, and two offsets.
3971 Two pointers are to the overflow area, which starts at the CFA.
3972 One of these is constant, for addressing into the GPR save area below it.
3973 The other is advanced up the stack through the overflow region.
3974 The third pointer is to the GPR save area. Since the FPR save area
3975 is just below it, we can address FPR slots off this pointer.
3976 We also keep two one-byte offsets, which are to be subtracted from the
3977 constant pointers to yield addresses in the GPR and FPR save areas.
3978 These are downcounted as float or non-float arguments are used,
3979 and when they get to zero, the argument must be obtained from the
3981 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3982 pointer is enough. It's started at the GPR save area, and is
3984 Note that the GPR save area is not constant size, due to optimization
3985 in the prologue. Hence, we can't use a design with two pointers
3986 and two offsets, although we could have designed this with two pointers
3987 and three offsets. */
3990 mips_build_builtin_va_list (void)
3992 if (EABI_FLOAT_VARARGS_P)
3994 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3997 record = make_node (RECORD_TYPE);
3999 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4001 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4003 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4005 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4006 unsigned_char_type_node);
4007 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4008 unsigned_char_type_node);
4009 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
4010 warn on every user file. */
4011 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
4012 array = build_array_type (unsigned_char_type_node,
4013 build_index_type (index));
4014 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
4016 DECL_FIELD_CONTEXT (f_ovfl) = record;
4017 DECL_FIELD_CONTEXT (f_gtop) = record;
4018 DECL_FIELD_CONTEXT (f_ftop) = record;
4019 DECL_FIELD_CONTEXT (f_goff) = record;
4020 DECL_FIELD_CONTEXT (f_foff) = record;
4021 DECL_FIELD_CONTEXT (f_res) = record;
4023 TYPE_FIELDS (record) = f_ovfl;
4024 TREE_CHAIN (f_ovfl) = f_gtop;
4025 TREE_CHAIN (f_gtop) = f_ftop;
4026 TREE_CHAIN (f_ftop) = f_goff;
4027 TREE_CHAIN (f_goff) = f_foff;
4028 TREE_CHAIN (f_foff) = f_res;
4030 layout_type (record);
4033 else if (TARGET_IRIX && !TARGET_IRIX5)
4034 /* On IRIX 6, this type is 'char *'. */
4035 return build_pointer_type (char_type_node);
4037 /* Otherwise, we use 'void *'. */
4038 return ptr_type_node;
4041 /* Implement va_start. */
4044 mips_va_start (tree valist, rtx nextarg)
4046 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
4048 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
4049 since the stack is aligned for a pair of argument-passing slots,
4050 and the beginning of a variable argument list may be an odd slot,
4051 we have to decrease its alignment. */
4052 if (cfun && cfun->emit->regno_pointer_align)
4053 while (((current_function_pretend_args_size * BITS_PER_UNIT)
4054 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
4055 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
4057 if (mips_abi == ABI_EABI)
4059 int gpr_save_area_size;
4062 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
4064 if (EABI_FLOAT_VARARGS_P)
4066 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4067 tree ovfl, gtop, ftop, goff, foff;
4070 int fpr_save_area_size;
4072 f_ovfl = TYPE_FIELDS (va_list_type_node);
4073 f_gtop = TREE_CHAIN (f_ovfl);
4074 f_ftop = TREE_CHAIN (f_gtop);
4075 f_goff = TREE_CHAIN (f_ftop);
4076 f_foff = TREE_CHAIN (f_goff);
4078 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4079 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4080 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4081 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4082 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4084 /* Emit code to initialize OVFL, which points to the next varargs
4085 stack argument. CUM->STACK_WORDS gives the number of stack
4086 words used by named arguments. */
4087 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4088 if (cum->stack_words > 0)
4089 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4090 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
4091 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4092 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4094 /* Emit code to initialize GTOP, the top of the GPR save area. */
4095 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4096 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4097 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4099 /* Emit code to initialize FTOP, the top of the FPR save area.
4100 This address is gpr_save_area_bytes below GTOP, rounded
4101 down to the next fp-aligned boundary. */
4102 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4103 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4104 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4106 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4107 build_int_2 (-fpr_offset, -1));
4108 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4109 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4111 /* Emit code to initialize GOFF, the offset from GTOP of the
4112 next GPR argument. */
4113 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4114 build_int_2 (gpr_save_area_size, 0));
4115 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4117 /* Likewise emit code to initialize FOFF, the offset from FTOP
4118 of the next FPR argument. */
4120 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4121 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4122 build_int_2 (fpr_save_area_size, 0));
4123 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4127 /* Everything is in the GPR save area, or in the overflow
4128 area which is contiguous with it. */
4129 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4130 std_expand_builtin_va_start (valist, nextarg);
4134 std_expand_builtin_va_start (valist, nextarg);
4137 /* Implement va_arg. */
4140 mips_va_arg (tree valist, tree type)
4142 HOST_WIDE_INT size, rsize;
4146 size = int_size_in_bytes (type);
4147 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4149 if (mips_abi == ABI_EABI)
4155 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4159 size = POINTER_SIZE / BITS_PER_UNIT;
4160 rsize = UNITS_PER_WORD;
4163 addr_rtx = gen_reg_rtx (Pmode);
4165 if (!EABI_FLOAT_VARARGS_P)
4167 /* Case of all args in a merged stack. No need to check bounds,
4168 just advance valist along the stack. */
4173 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4175 /* Align the pointer using: ap = (ap + align - 1) & -align,
4176 where align is 2 * UNITS_PER_WORD. */
4177 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4178 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
4179 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4180 build_int_2 (-2 * UNITS_PER_WORD, -1));
4181 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4182 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4185 /* Emit code to set addr_rtx to the valist, and postincrement
4186 the valist by the size of the argument, rounded up to the
4188 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4190 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4192 emit_move_insn (addr_rtx, r);
4194 /* Flush the POSTINCREMENT. */
4199 /* Not a simple merged stack. */
4201 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4202 tree ovfl, top, off;
4203 rtx lab_over = NULL_RTX, lab_false;
4204 HOST_WIDE_INT osize;
4206 f_ovfl = TYPE_FIELDS (va_list_type_node);
4207 f_gtop = TREE_CHAIN (f_ovfl);
4208 f_ftop = TREE_CHAIN (f_gtop);
4209 f_goff = TREE_CHAIN (f_ftop);
4210 f_foff = TREE_CHAIN (f_goff);
4212 /* We maintain separate pointers and offsets for floating-point
4213 and integer arguments, but we need similar code in both cases.
4216 TOP be the top of the register save area;
4217 OFF be the offset from TOP of the next register;
4218 ADDR_RTX be the address of the argument;
4219 RSIZE be the number of bytes used to store the argument
4220 when it's in the register save area;
4221 OSIZE be the number of bytes used to store it when it's
4222 in the stack overflow area; and
4223 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4225 The code we want is:
4227 1: off &= -rsize; // round down
4230 4: addr_rtx = top - off;
4235 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4236 10: addr_rtx = ovfl + PADDING;
4240 [1] and [9] can sometimes be optimized away. */
4242 lab_false = gen_label_rtx ();
4243 lab_over = gen_label_rtx ();
4245 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4246 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4247 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4249 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4250 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4252 /* When floating-point registers are saved to the stack,
4253 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4254 of the float's precision. */
4255 rsize = UNITS_PER_HWFPVALUE;
4259 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4260 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4261 if (rsize > UNITS_PER_WORD)
4263 /* [1] Emit code for: off &= -rsize. */
4264 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4265 build_int_2 (-rsize, -1));
4266 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4267 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4270 /* Every overflow argument must take up at least UNITS_PER_WORD
4271 bytes (= PARM_BOUNDARY bits). RSIZE can sometimes be smaller
4272 than that, such as in the combination -mgp64 -msingle-float
4273 -fshort-double. Doubles passed in registers will then take
4274 up UNITS_PER_HWFPVALUE bytes, but those passed on the stack
4275 take up UNITS_PER_WORD bytes. */
4276 osize = MAX (rsize, UNITS_PER_WORD);
4278 /* [2] Emit code to branch if off == 0. */
4279 r = expand_expr (off, NULL_RTX, TYPE_MODE (TREE_TYPE (off)),
4281 emit_cmp_and_jump_insns (r, const0_rtx, EQ, const1_rtx, GET_MODE (r),
4284 /* [4] Emit code for: addr_rtx = top - off. */
4285 t = build (MINUS_EXPR, TREE_TYPE (top), top, off);
4286 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4288 emit_move_insn (addr_rtx, r);
4290 /* [5] Emit code for: off -= rsize. */
4291 t = build (MINUS_EXPR, TREE_TYPE (off), off, build_int_2 (rsize, 0));
4292 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4293 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4295 /* [7] Emit code to jump over the else clause, then the label
4298 emit_jump (lab_over);
4300 emit_label (lab_false);
4302 if (osize > UNITS_PER_WORD)
4304 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4305 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl,
4306 build_int_2 (osize - 1, 0));
4307 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t,
4308 build_int_2 (-osize, -1));
4309 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4310 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4313 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4314 post-increment ovfl by osize. On big-endian machines,
4315 the argument has OSIZE - RSIZE bytes of leading padding. */
4316 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl,
4318 if (BYTES_BIG_ENDIAN && osize > rsize)
4319 t = build (PLUS_EXPR, TREE_TYPE (t), t,
4320 build_int_2 (osize - rsize, 0));
4321 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4323 emit_move_insn (addr_rtx, r);
4326 emit_label (lab_over);
4328 if (BYTES_BIG_ENDIAN && rsize != size)
4329 addr_rtx = plus_constant (addr_rtx, rsize - size);
4332 addr_rtx = force_reg (Pmode, addr_rtx);
4333 r = gen_rtx_MEM (Pmode, addr_rtx);
4334 set_mem_alias_set (r, get_varargs_alias_set ());
4335 emit_move_insn (addr_rtx, r);
4343 HOST_WIDE_INT min_offset;
4345 /* ??? The original va-mips.h did always align, despite the fact
4346 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4347 increment mechanism. */
4349 if ((mips_abi == ABI_N32 || mips_abi == ABI_64)
4350 && TYPE_ALIGN (type) > 64)
4352 else if (TARGET_64BIT)
4354 else if (TYPE_ALIGN (type) > 32)
4359 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4360 build_int_2 (align - 1, 0));
4361 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4363 /* If arguments of type TYPE must be passed on the stack,
4364 set MIN_OFFSET to the offset of the first stack parameter. */
4365 if (!MUST_PASS_IN_STACK (TYPE_MODE (type), type))
4367 else if (TARGET_NEWABI)
4368 min_offset = current_function_pretend_args_size;
4370 min_offset = REG_PARM_STACK_SPACE (current_function_decl);
4372 /* Make sure the new address is at least MIN_OFFSET bytes from
4373 the incoming argument pointer. */
4375 t = build (MAX_EXPR, TREE_TYPE (valist), t,
4376 make_tree (TREE_TYPE (valist),
4377 plus_constant (virtual_incoming_args_rtx,
4380 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4381 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4383 /* Everything past the alignment is standard. */
4384 return std_expand_builtin_va_arg (valist, type);
4388 /* Return true if it is possible to use left/right accesses for a
4389 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4390 returning true, update *OP, *LEFT and *RIGHT as follows:
4392 *OP is a BLKmode reference to the whole field.
4394 *LEFT is a QImode reference to the first byte if big endian or
4395 the last byte if little endian. This address can be used in the
4396 left-side instructions (lwl, swl, ldl, sdl).
4398 *RIGHT is a QImode reference to the opposite end of the field and
4399 can be used in the parterning right-side instruction. */
4402 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4403 rtx *left, rtx *right)
4407 /* Check that the operand really is a MEM. Not all the extv and
4408 extzv predicates are checked. */
4409 if (GET_CODE (*op) != MEM)
4412 /* Check that the size is valid. */
4413 if (width != 32 && (!TARGET_64BIT || width != 64))
4416 /* We can only access byte-aligned values. Since we are always passed
4417 a reference to the first byte of the field, it is not necessary to
4418 do anything with BITPOS after this check. */
4419 if (bitpos % BITS_PER_UNIT != 0)
4422 /* Reject aligned bitfields: we want to use a normal load or store
4423 instead of a left/right pair. */
4424 if (MEM_ALIGN (*op) >= width)
4427 /* Adjust *OP to refer to the whole field. This also has the effect
4428 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4429 *op = adjust_address (*op, BLKmode, 0);
4430 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4432 /* Get references to both ends of the field. We deliberately don't
4433 use the original QImode *OP for FIRST since the new BLKmode one
4434 might have a simpler address. */
4435 first = adjust_address (*op, QImode, 0);
4436 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4438 /* Allocate to LEFT and RIGHT according to endiannes. LEFT should
4439 be the upper word and RIGHT the lower word. */
4440 if (TARGET_BIG_ENDIAN)
4441 *left = first, *right = last;
4443 *left = last, *right = first;
4449 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4450 Return true on success. We only handle cases where zero_extract is
4451 equivalent to sign_extract. */
4454 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4458 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4459 paradoxical word_mode subreg. This is the only case in which
4460 we allow the destination to be larger than the source. */
4461 if (GET_CODE (dest) == SUBREG
4462 && GET_MODE (dest) == DImode
4463 && SUBREG_BYTE (dest) == 0
4464 && GET_MODE (SUBREG_REG (dest)) == SImode)
4465 dest = SUBREG_REG (dest);
4467 /* After the above adjustment, the destination must be the same
4468 width as the source. */
4469 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4472 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4475 if (GET_MODE (dest) == DImode)
4477 emit_insn (gen_mov_ldl (dest, src, left));
4478 emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
4479 right, copy_rtx (dest)));
4483 emit_insn (gen_mov_lwl (dest, src, left));
4484 emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
4485 right, copy_rtx (dest)));
4491 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4495 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4499 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4502 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4504 if (GET_MODE (src) == DImode)
4506 emit_insn (gen_mov_sdl (dest, src, left));
4507 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4511 emit_insn (gen_mov_swl (dest, src, left));
4512 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4517 /* Set up globals to generate code for the ISA or processor
4518 described by INFO. */
4521 mips_set_architecture (const struct mips_cpu_info *info)
4525 mips_arch_info = info;
4526 mips_arch = info->cpu;
4527 mips_isa = info->isa;
4532 /* Likewise for tuning. */
4535 mips_set_tune (const struct mips_cpu_info *info)
4539 mips_tune_info = info;
4540 mips_tune = info->cpu;
4545 /* Set up the threshold for data to go into the small data area, instead
4546 of the normal data area, and detect any conflicts in the switches. */
4549 override_options (void)
4551 int i, start, regno;
4552 enum machine_mode mode;
4554 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4556 /* Interpret -mabi. */
4557 mips_abi = MIPS_ABI_DEFAULT;
4558 if (mips_abi_string != 0)
4560 if (strcmp (mips_abi_string, "32") == 0)
4562 else if (strcmp (mips_abi_string, "o64") == 0)
4564 else if (strcmp (mips_abi_string, "n32") == 0)
4566 else if (strcmp (mips_abi_string, "64") == 0)
4568 else if (strcmp (mips_abi_string, "eabi") == 0)
4569 mips_abi = ABI_EABI;
4571 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4574 /* The following code determines the architecture and register size.
4575 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4576 The GAS and GCC code should be kept in sync as much as possible. */
4578 if (mips_arch_string != 0)
4579 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4581 if (mips_isa_string != 0)
4583 /* Handle -mipsN. */
4584 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4585 const struct mips_cpu_info *isa_info;
4587 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4588 free (whole_isa_str);
4590 /* -march takes precedence over -mipsN, since it is more descriptive.
4591 There's no harm in specifying both as long as the ISA levels
4593 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4594 error ("-mips%s conflicts with the other architecture options, "
4595 "which specify a MIPS%d processor",
4596 mips_isa_string, mips_isa);
4598 /* Set architecture based on the given option. */
4599 mips_set_architecture (isa_info);
4602 if (mips_arch_info == 0)
4604 #ifdef MIPS_CPU_STRING_DEFAULT
4605 mips_set_architecture (mips_parse_cpu ("default CPU",
4606 MIPS_CPU_STRING_DEFAULT));
4608 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4612 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4613 error ("-march=%s is not compatible with the selected ABI",
4614 mips_arch_info->name);
4616 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4617 if (mips_tune_string != 0)
4618 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4620 if (mips_tune_info == 0)
4621 mips_set_tune (mips_arch_info);
4623 if ((target_flags_explicit & MASK_64BIT) != 0)
4625 /* The user specified the size of the integer registers. Make sure
4626 it agrees with the ABI and ISA. */
4627 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4628 error ("-mgp64 used with a 32-bit processor");
4629 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4630 error ("-mgp32 used with a 64-bit ABI");
4631 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4632 error ("-mgp64 used with a 32-bit ABI");
4636 /* Infer the integer register size from the ABI and processor.
4637 Restrict ourselves to 32-bit registers if that's all the
4638 processor has, or if the ABI cannot handle 64-bit registers. */
4639 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4640 target_flags &= ~MASK_64BIT;
4642 target_flags |= MASK_64BIT;
4645 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4647 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4648 only one right answer here. */
4649 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4650 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4651 else if (!TARGET_64BIT && TARGET_FLOAT64)
4652 error ("unsupported combination: %s", "-mgp32 -mfp64");
4653 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4654 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4658 /* -msingle-float selects 32-bit float registers. Otherwise the
4659 float registers should be the same size as the integer ones. */
4660 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4661 target_flags |= MASK_FLOAT64;
4663 target_flags &= ~MASK_FLOAT64;
4666 /* End of code shared with GAS. */
4668 if ((target_flags_explicit & MASK_LONG64) == 0)
4670 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4671 were used, then set the type sizes. In the EABI in 64 bit mode,
4672 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4674 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4675 target_flags |= MASK_LONG64;
4677 target_flags &= ~MASK_LONG64;
4680 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4681 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4683 /* For some configurations, it is useful to have -march control
4684 the default setting of MASK_SOFT_FLOAT. */
4685 switch ((int) mips_arch)
4687 case PROCESSOR_R4100:
4688 case PROCESSOR_R4120:
4689 target_flags |= MASK_SOFT_FLOAT;
4693 target_flags &= ~MASK_SOFT_FLOAT;
4698 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4699 flag_pcc_struct_return = 0;
4701 #if defined(USE_COLLECT2)
4702 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4703 always defined when GNU as is not in use, but collect2 is only used
4704 for the O32 ABI, so override the toplev.c and target-def.h defaults
4705 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4706 TARGET_HAVE_CTORS_DTORS.
4708 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4709 sections, constructor/destructor handling depends on the ABI in use.
4711 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4712 defaults for the N32/N64 ABIs. */
4713 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4715 flag_gnu_linker = 1;
4717 targetm.have_ctors_dtors = true;
4718 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4719 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4723 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4725 if (TARGET_SGI_O32_AS)
4727 /* They don't recognize `.[248]byte'. */
4728 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4729 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4730 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4731 contrary to the documentation, so disable it. */
4732 targetm.asm_out.unaligned_op.di = NULL;
4734 /* They cannot handle named sections. */
4735 targetm.have_named_sections = false;
4736 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4738 targetm.terminate_dw2_eh_frame_info = true;
4739 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4741 /* They cannot handle debug information. */
4742 if (write_symbols != NO_DEBUG)
4744 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4745 so -mabi=32 isn't usually specified. */
4747 warning ("-g is only supported using GNU as,");
4749 warning ("-g is only supported using GNU as with -mabi=32,");
4750 warning ("-g option disabled");
4751 write_symbols = NO_DEBUG;
4755 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4757 /* If neither -mbranch-likely nor -mno-branch-likely was given
4758 on the command line, set MASK_BRANCHLIKELY based on the target
4761 By default, we enable use of Branch Likely instructions on
4762 all architectures which support them except for MIPS32 and MIPS64
4763 (i.e., the generic MIPS32 and MIPS64 ISAs, and processors which
4766 The MIPS32 and MIPS64 architecture specifications say "Software
4767 is strongly encouraged to avoid use of Branch Likely
4768 instructions, as they will be removed from a future revision
4769 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4770 issue those instructions unless instructed to do so by
4772 if (ISA_HAS_BRANCHLIKELY && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64))
4773 target_flags |= MASK_BRANCHLIKELY;
4775 target_flags &= ~MASK_BRANCHLIKELY;
4777 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4778 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4780 /* The effect of -mabicalls isn't defined for the EABI. */
4781 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4783 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4784 target_flags &= ~MASK_ABICALLS;
4787 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4788 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4789 /* ??? -non_shared turns off pic code generation, but this is not
4791 if (TARGET_ABICALLS)
4794 if (mips_section_threshold > 0)
4795 warning ("-G is incompatible with PIC code which is the default");
4798 /* The MIPS and SGI o32 assemblers expect small-data variables to
4799 be declared before they are used. Although we once had code to
4800 do this, it was very invasive and fragile. It no longer seems
4801 worth the effort. */
4802 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4803 mips_section_threshold = 0;
4805 /* We switch to small data sections using ".section", which the native
4806 o32 irix assemblers don't understand. Disable -G accordingly.
4807 We must do this regardless of command-line options since otherwise
4808 the compiler would abort. */
4809 if (!targetm.have_named_sections)
4810 mips_section_threshold = 0;
4812 /* -membedded-pic is a form of PIC code suitable for embedded
4813 systems. All calls are made using PC relative addressing, and
4814 all data is addressed using the $gp register. This requires gas,
4815 which does most of the work, and GNU ld, which automatically
4816 expands PC relative calls which are out of range into a longer
4817 instruction sequence. All gcc really does differently is
4818 generate a different sequence for a switch. */
4819 if (TARGET_EMBEDDED_PIC)
4822 if (TARGET_ABICALLS)
4823 warning ("-membedded-pic and -mabicalls are incompatible");
4826 warning ("-G and -membedded-pic are incompatible");
4828 /* Setting mips_section_threshold is not required, because gas
4829 will force everything to be GP addressable anyhow, but
4830 setting it will cause gcc to make better estimates of the
4831 number of instructions required to access a particular data
4833 mips_section_threshold = 0x7fffffff;
4836 /* mips_split_addresses is a half-way house between explicit
4837 relocations and the traditional assembler macros. It can
4838 split absolute 32-bit symbolic constants into a high/lo_sum
4839 pair but uses macros for other sorts of access.
4841 Like explicit relocation support for REL targets, it relies
4842 on GNU extensions in the assembler and the linker.
4844 Although this code should work for -O0, it has traditionally
4845 been treated as an optimization. */
4846 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4847 && optimize && !flag_pic
4848 && !ABI_HAS_64BIT_SYMBOLS)
4849 mips_split_addresses = 1;
4851 mips_split_addresses = 0;
4853 /* -mexplicit-relocs doesn't yet support non-PIC n64. We don't know
4854 how to generate %highest/%higher/%hi/%lo sequences. */
4855 if (mips_abi == ABI_64 && !TARGET_ABICALLS)
4857 if ((target_flags_explicit & target_flags & MASK_EXPLICIT_RELOCS) != 0)
4858 sorry ("non-PIC n64 with explicit relocations");
4859 target_flags &= ~MASK_EXPLICIT_RELOCS;
4862 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4863 the user has said otherwise, assume that they are not available
4864 with assemblers other than gas. */
4865 if (!TARGET_NEWABI && !TARGET_GAS
4866 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4867 target_flags &= ~MASK_EXPLICIT_RELOCS;
4869 /* -mrnames says to use the MIPS software convention for register
4870 names instead of the hardware names (ie, $a0 instead of $4).
4871 We do this by switching the names in mips_reg_names, which the
4872 reg_names points into via the REGISTER_NAMES macro. */
4874 if (TARGET_NAME_REGS)
4875 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
4877 /* When compiling for the mips16, we can not use floating point. We
4878 record the original hard float value in mips16_hard_float. */
4881 if (TARGET_SOFT_FLOAT)
4882 mips16_hard_float = 0;
4884 mips16_hard_float = 1;
4885 target_flags |= MASK_SOFT_FLOAT;
4887 /* Don't run the scheduler before reload, since it tends to
4888 increase register pressure. */
4889 flag_schedule_insns = 0;
4891 /* Silently disable -mexplicit-relocs since it doesn't apply
4892 to mips16 code. Even so, it would overly pedantic to warn
4893 about "-mips16 -mexplicit-relocs", especially given that
4894 we use a %gprel() operator. */
4895 target_flags &= ~MASK_EXPLICIT_RELOCS;
4898 /* When using explicit relocs, we call dbr_schedule from within
4900 if (TARGET_EXPLICIT_RELOCS)
4902 mips_flag_delayed_branch = flag_delayed_branch;
4903 flag_delayed_branch = 0;
4906 #ifdef MIPS_TFMODE_FORMAT
4907 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4910 mips_print_operand_punct['?'] = 1;
4911 mips_print_operand_punct['#'] = 1;
4912 mips_print_operand_punct['/'] = 1;
4913 mips_print_operand_punct['&'] = 1;
4914 mips_print_operand_punct['!'] = 1;
4915 mips_print_operand_punct['*'] = 1;
4916 mips_print_operand_punct['@'] = 1;
4917 mips_print_operand_punct['.'] = 1;
4918 mips_print_operand_punct['('] = 1;
4919 mips_print_operand_punct[')'] = 1;
4920 mips_print_operand_punct['['] = 1;
4921 mips_print_operand_punct[']'] = 1;
4922 mips_print_operand_punct['<'] = 1;
4923 mips_print_operand_punct['>'] = 1;
4924 mips_print_operand_punct['{'] = 1;
4925 mips_print_operand_punct['}'] = 1;
4926 mips_print_operand_punct['^'] = 1;
4927 mips_print_operand_punct['$'] = 1;
4928 mips_print_operand_punct['+'] = 1;
4929 mips_print_operand_punct['~'] = 1;
4931 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4932 mips_char_to_class['e'] = M16_NA_REGS;
4933 mips_char_to_class['t'] = T_REG;
4934 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4935 mips_char_to_class['h'] = HI_REG;
4936 mips_char_to_class['l'] = LO_REG;
4937 mips_char_to_class['x'] = MD_REGS;
4938 mips_char_to_class['b'] = ALL_REGS;
4939 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4940 TARGET_MIPS16 ? M16_NA_REGS :
4942 mips_char_to_class['e'] = LEA_REGS;
4943 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4944 mips_char_to_class['y'] = GR_REGS;
4945 mips_char_to_class['z'] = ST_REGS;
4946 mips_char_to_class['B'] = COP0_REGS;
4947 mips_char_to_class['C'] = COP2_REGS;
4948 mips_char_to_class['D'] = COP3_REGS;
4950 /* Set up array to map GCC register number to debug register number.
4951 Ignore the special purpose register numbers. */
4953 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4954 mips_dbx_regno[i] = -1;
4956 start = GP_DBX_FIRST - GP_REG_FIRST;
4957 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4958 mips_dbx_regno[i] = i + start;
4960 start = FP_DBX_FIRST - FP_REG_FIRST;
4961 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4962 mips_dbx_regno[i] = i + start;
4964 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4965 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4967 /* Set up array giving whether a given register can hold a given mode. */
4969 for (mode = VOIDmode;
4970 mode != MAX_MACHINE_MODE;
4971 mode = (enum machine_mode) ((int)mode + 1))
4973 register int size = GET_MODE_SIZE (mode);
4974 register enum mode_class class = GET_MODE_CLASS (mode);
4976 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4983 temp = (regno == FPSW_REGNUM);
4985 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4986 || FP_REG_P (regno));
4989 else if (GP_REG_P (regno))
4990 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4992 else if (FP_REG_P (regno))
4993 temp = ((regno % FP_INC) == 0)
4994 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
4995 && size <= UNITS_PER_FPVALUE)
4996 /* Allow integer modes that fit into a single
4997 register. We need to put integers into FPRs
4998 when using instructions like cvt and trunc. */
4999 || (class == MODE_INT && size <= UNITS_PER_FPREG)
5000 /* Allow TFmode for CCmode reloads. */
5001 || (ISA_HAS_8CC && mode == TFmode));
5003 else if (MD_REG_P (regno))
5004 temp = (class == MODE_INT
5005 && (size <= UNITS_PER_WORD
5006 || (regno == MD_REG_FIRST
5007 && size == 2 * UNITS_PER_WORD)));
5009 else if (ALL_COP_REG_P (regno))
5010 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
5014 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5018 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5019 initialized yet, so we can't use that here. */
5020 gpr_mode = TARGET_64BIT ? DImode : SImode;
5022 /* Provide default values for align_* for 64-bit targets. */
5023 if (TARGET_64BIT && !TARGET_MIPS16)
5025 if (align_loops == 0)
5027 if (align_jumps == 0)
5029 if (align_functions == 0)
5030 align_functions = 8;
5033 /* Function to allocate machine-dependent function status. */
5034 init_machine_status = &mips_init_machine_status;
5036 /* Create a unique alias set for GOT references. */
5037 mips_got_alias_set = new_alias_set ();
5040 /* Implement CONDITIONAL_REGISTER_USAGE. */
5043 mips_conditional_register_usage (void)
5045 if (!TARGET_HARD_FLOAT)
5049 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
5050 fixed_regs[regno] = call_used_regs[regno] = 1;
5051 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5052 fixed_regs[regno] = call_used_regs[regno] = 1;
5054 else if (! ISA_HAS_8CC)
5058 /* We only have a single condition code register. We
5059 implement this by hiding all the condition code registers,
5060 and generating RTL that refers directly to ST_REG_FIRST. */
5061 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
5062 fixed_regs[regno] = call_used_regs[regno] = 1;
5064 /* In mips16 mode, we permit the $t temporary registers to be used
5065 for reload. We prohibit the unused $s registers, since they
5066 are caller saved, and saving them via a mips16 register would
5067 probably waste more time than just reloading the value. */
5070 fixed_regs[18] = call_used_regs[18] = 1;
5071 fixed_regs[19] = call_used_regs[19] = 1;
5072 fixed_regs[20] = call_used_regs[20] = 1;
5073 fixed_regs[21] = call_used_regs[21] = 1;
5074 fixed_regs[22] = call_used_regs[22] = 1;
5075 fixed_regs[23] = call_used_regs[23] = 1;
5076 fixed_regs[26] = call_used_regs[26] = 1;
5077 fixed_regs[27] = call_used_regs[27] = 1;
5078 fixed_regs[30] = call_used_regs[30] = 1;
5080 /* fp20-23 are now caller saved. */
5081 if (mips_abi == ABI_64)
5084 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
5085 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5087 /* odd registers from fp21 to fp31 are now caller saved. */
5088 if (mips_abi == ABI_N32)
5091 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5092 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5096 /* Allocate a chunk of memory for per-function machine-dependent data. */
5097 static struct machine_function *
5098 mips_init_machine_status (void)
5100 return ((struct machine_function *)
5101 ggc_alloc_cleared (sizeof (struct machine_function)));
5104 /* On the mips16, we want to allocate $24 (T_REG) before other
5105 registers for instructions for which it is possible. This helps
5106 avoid shuffling registers around in order to set up for an xor,
5107 encouraging the compiler to use a cmp instead. */
5110 mips_order_regs_for_local_alloc (void)
5114 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5115 reg_alloc_order[i] = i;
5119 /* It really doesn't matter where we put register 0, since it is
5120 a fixed register anyhow. */
5121 reg_alloc_order[0] = 24;
5122 reg_alloc_order[24] = 0;
5127 /* The MIPS debug format wants all automatic variables and arguments
5128 to be in terms of the virtual frame pointer (stack pointer before
5129 any adjustment in the function), while the MIPS 3.0 linker wants
5130 the frame pointer to be the stack pointer after the initial
5131 adjustment. So, we do the adjustment here. The arg pointer (which
5132 is eliminated) points to the virtual frame pointer, while the frame
5133 pointer (which may be eliminated) points to the stack pointer after
5134 the initial adjustments. */
5137 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5139 rtx offset2 = const0_rtx;
5140 rtx reg = eliminate_constant_term (addr, &offset2);
5143 offset = INTVAL (offset2);
5145 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5146 || reg == hard_frame_pointer_rtx)
5148 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5149 ? compute_frame_size (get_frame_size ())
5150 : cfun->machine->frame.total_size;
5152 /* MIPS16 frame is smaller */
5153 if (frame_pointer_needed && TARGET_MIPS16)
5154 frame_size -= cfun->machine->frame.args_size;
5156 offset = offset - frame_size;
5159 /* sdbout_parms does not want this to crash for unrecognized cases. */
5161 else if (reg != arg_pointer_rtx)
5162 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5169 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5171 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5172 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5173 'h' OP is HIGH, prints %hi(X),
5174 'd' output integer constant in decimal,
5175 'z' if the operand is 0, use $0 instead of normal operand.
5176 'D' print second part of double-word register or memory operand.
5177 'L' print low-order register of double-word register operand.
5178 'M' print high-order register of double-word register operand.
5179 'C' print part of opcode for a branch condition.
5180 'F' print part of opcode for a floating-point branch condition.
5181 'N' print part of opcode for a branch condition, inverted.
5182 'W' print part of opcode for a floating-point branch condition, inverted.
5183 'S' OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5184 'B' print 'z' for EQ, 'n' for NE
5185 'b' print 'n' for EQ, 'z' for NE
5186 'T' print 'f' for EQ, 't' for NE
5187 't' print 't' for EQ, 'f' for NE
5188 'Z' print register and a comma, but print nothing for $fcc0
5189 'R' print the reloc associated with LO_SUM
5191 The punctuation characters are:
5193 '(' Turn on .set noreorder
5194 ')' Turn on .set reorder
5195 '[' Turn on .set noat
5197 '<' Turn on .set nomacro
5198 '>' Turn on .set macro
5199 '{' Turn on .set volatile (not GAS)
5200 '}' Turn on .set novolatile (not GAS)
5201 '&' Turn on .set noreorder if filling delay slots
5202 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5203 '!' Turn on .set nomacro if filling delay slots
5204 '#' Print nop if in a .set noreorder section.
5205 '/' Like '#', but does nothing within a delayed branch sequence
5206 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5207 '@' Print the name of the assembler temporary register (at or $1).
5208 '.' Print the name of the register with a hard-wired zero (zero or $0).
5209 '^' Print the name of the pic call-through register (t9 or $25).
5210 '$' Print the name of the stack pointer register (sp or $29).
5211 '+' Print the name of the gp register (usually gp or $28).
5212 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5215 print_operand (FILE *file, rtx op, int letter)
5217 register enum rtx_code code;
5218 struct mips_constant_info c;
5221 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5226 if (mips_branch_likely)
5231 fputs (reg_names [GP_REG_FIRST + 1], file);
5235 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5239 fputs (reg_names [GP_REG_FIRST + 0], file);
5243 fputs (reg_names[STACK_POINTER_REGNUM], file);
5247 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5251 if (final_sequence != 0 && set_noreorder++ == 0)
5252 fputs (".set\tnoreorder\n\t", file);
5256 if (final_sequence != 0)
5258 if (set_noreorder++ == 0)
5259 fputs (".set\tnoreorder\n\t", file);
5261 if (set_nomacro++ == 0)
5262 fputs (".set\tnomacro\n\t", file);
5267 if (final_sequence != 0 && set_nomacro++ == 0)
5268 fputs ("\n\t.set\tnomacro", file);
5272 if (set_noreorder != 0)
5273 fputs ("\n\tnop", file);
5277 /* Print an extra newline so that the delayed insn is separated
5278 from the following ones. This looks neater and is consistent
5279 with non-nop delayed sequences. */
5280 if (set_noreorder != 0 && final_sequence == 0)
5281 fputs ("\n\tnop\n", file);
5285 if (set_noreorder++ == 0)
5286 fputs (".set\tnoreorder\n\t", file);
5290 if (set_noreorder == 0)
5291 error ("internal error: %%) found without a %%( in assembler pattern");
5293 else if (--set_noreorder == 0)
5294 fputs ("\n\t.set\treorder", file);
5299 if (set_noat++ == 0)
5300 fputs (".set\tnoat\n\t", file);
5305 error ("internal error: %%] found without a %%[ in assembler pattern");
5306 else if (--set_noat == 0)
5307 fputs ("\n\t.set\tat", file);
5312 if (set_nomacro++ == 0)
5313 fputs (".set\tnomacro\n\t", file);
5317 if (set_nomacro == 0)
5318 error ("internal error: %%> found without a %%< in assembler pattern");
5319 else if (--set_nomacro == 0)
5320 fputs ("\n\t.set\tmacro", file);
5325 if (set_volatile++ == 0)
5326 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5330 if (set_volatile == 0)
5331 error ("internal error: %%} found without a %%{ in assembler pattern");
5332 else if (--set_volatile == 0)
5333 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5339 if (align_labels_log > 0)
5340 ASM_OUTPUT_ALIGN (file, align_labels_log);
5345 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5354 error ("PRINT_OPERAND null pointer");
5358 code = GET_CODE (op);
5362 if (GET_CODE (op) != HIGH)
5364 fputs ("%hi(", file);
5365 output_addr_const (file, XEXP (op, 0));
5369 else if (letter == 'C')
5372 case EQ: fputs ("eq", file); break;
5373 case NE: fputs ("ne", file); break;
5374 case GT: fputs ("gt", file); break;
5375 case GE: fputs ("ge", file); break;
5376 case LT: fputs ("lt", file); break;
5377 case LE: fputs ("le", file); break;
5378 case GTU: fputs ("gtu", file); break;
5379 case GEU: fputs ("geu", file); break;
5380 case LTU: fputs ("ltu", file); break;
5381 case LEU: fputs ("leu", file); break;
5383 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5386 else if (letter == 'N')
5389 case EQ: fputs ("ne", file); break;
5390 case NE: fputs ("eq", file); break;
5391 case GT: fputs ("le", file); break;
5392 case GE: fputs ("lt", file); break;
5393 case LT: fputs ("ge", file); break;
5394 case LE: fputs ("gt", file); break;
5395 case GTU: fputs ("leu", file); break;
5396 case GEU: fputs ("ltu", file); break;
5397 case LTU: fputs ("geu", file); break;
5398 case LEU: fputs ("gtu", file); break;
5400 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5403 else if (letter == 'F')
5406 case EQ: fputs ("c1f", file); break;
5407 case NE: fputs ("c1t", file); break;
5409 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5412 else if (letter == 'W')
5415 case EQ: fputs ("c1t", file); break;
5416 case NE: fputs ("c1f", file); break;
5418 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5421 else if (letter == 'S')
5425 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5426 assemble_name (file, buffer);
5429 else if (letter == 'Z')
5431 register int regnum;
5436 regnum = REGNO (op);
5437 if (! ST_REG_P (regnum))
5440 if (regnum != ST_REG_FIRST)
5441 fprintf (file, "%s,", reg_names[regnum]);
5444 else if (code == REG || code == SUBREG)
5446 register int regnum;
5449 regnum = REGNO (op);
5451 regnum = true_regnum (op);
5453 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5454 || (letter == 'L' && WORDS_BIG_ENDIAN)
5458 fprintf (file, "%s", reg_names[regnum]);
5461 else if (code == MEM)
5464 output_address (plus_constant (XEXP (op, 0), 4));
5466 output_address (XEXP (op, 0));
5469 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5470 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5472 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5473 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5475 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5476 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5478 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5479 fputs (reg_names[GP_REG_FIRST], file);
5481 else if (letter == 'd' || letter == 'x' || letter == 'X')
5482 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5484 else if (letter == 'B')
5485 fputs (code == EQ ? "z" : "n", file);
5486 else if (letter == 'b')
5487 fputs (code == EQ ? "n" : "z", file);
5488 else if (letter == 'T')
5489 fputs (code == EQ ? "f" : "t", file);
5490 else if (letter == 't')
5491 fputs (code == EQ ? "t" : "f", file);
5494 switch (mips_classify_constant (&c, op))
5496 case CONSTANT_SYMBOLIC:
5499 if (mips_classify_symbol (c.symbol) == SYMBOL_SMALL_DATA)
5500 fputs (TARGET_MIPS16 ? "%gprel(" : "%gp_rel(", file);
5501 else if (TARGET_ABICALLS && TARGET_NEWABI)
5502 fputs ("%got_ofst(", file);
5504 fputs ("%lo(", file);
5505 output_addr_const (file, op);
5509 /* ... fall through ... */
5512 output_addr_const (file, op);
5516 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5519 case CONSTANT_RELOC:
5520 reloc = mips_reloc_string (c.reloc);
5521 fputs (reloc, file);
5522 output_addr_const (file, plus_constant (c.symbol, c.offset));
5524 if (*reloc++ == '(')
5529 /* Return the assembly operator used for the given type of relocation. */
5532 mips_reloc_string (int reloc)
5536 case RELOC_GOT_HI: return "%got_hi(";
5537 case RELOC_GOT_LO: return "%got_lo(";
5538 case RELOC_GOT_PAGE: return (TARGET_NEWABI ? "%got_page(" : "%got(");
5539 case RELOC_GOT_DISP: return (TARGET_NEWABI ? "%got_disp(" : "%got(");
5540 case RELOC_CALL16: return "%call16(";
5541 case RELOC_CALL_HI: return "%call_hi(";
5542 case RELOC_CALL_LO: return "%call_lo(";
5543 case RELOC_LOADGP_HI: return "%hi(%neg(%gp_rel(";
5544 case RELOC_LOADGP_LO: return "%lo(%neg(%gp_rel(";
5549 /* Output address operand X to FILE. */
5552 print_operand_address (FILE *file, rtx x)
5554 struct mips_address_info addr;
5556 switch (mips_classify_address (&addr, x, word_mode, 1, 1))
5558 case ADDRESS_INVALID:
5562 print_operand (file, addr.offset, 0);
5563 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5566 case ADDRESS_LO_SUM:
5567 print_operand (file, addr.offset, 'R');
5568 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5571 case ADDRESS_CONST_INT:
5572 case ADDRESS_SYMBOLIC:
5573 output_addr_const (file, x);
5579 /* Target hook for assembling integer objects. It appears that the Irix
5580 6 assembler can't handle 64-bit decimal integers, so avoid printing
5581 such an integer here. */
5584 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5586 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5588 fputs ("\t.dword\t", asm_out_file);
5589 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5590 output_addr_const (asm_out_file, x);
5592 print_operand (asm_out_file, x, 'X');
5593 fputc ('\n', asm_out_file);
5596 return default_assemble_integer (x, size, aligned_p);
5599 /* When using assembler macros, keep track of all of small-data externs
5600 so that mips_file_end can emit the appropriate declarations for them.
5602 In most cases it would be safe (though pointless) to emit .externs
5603 for other symbols too. One exception is when an object is within
5604 the -G limit but declared by the user to be in a section other
5605 than .sbss or .sdata. */
5608 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5610 register struct extern_list *p;
5612 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5614 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5615 p->next = extern_head;
5617 p->size = int_size_in_bytes (TREE_TYPE (decl));
5621 if (TARGET_IRIX && mips_abi == ABI_32
5622 && TREE_CODE (decl) == FUNCTION_DECL
5623 /* ??? Don't include alloca, since gcc will always expand it
5624 inline. If we don't do this, the C++ library fails to build. */
5625 && strcmp (name, "alloca")
5626 /* ??? Don't include __builtin_next_arg, because then gcc will not
5627 bootstrap under Irix 5.1. */
5628 && strcmp (name, "__builtin_next_arg"))
5630 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5631 p->next = extern_head;
5642 irix_output_external_libcall (rtx fun)
5644 register struct extern_list *p;
5646 if (mips_abi == ABI_32)
5648 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5649 p->next = extern_head;
5650 p->name = XSTR (fun, 0);
5657 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5658 put out a MIPS ECOFF file and a stab. */
5661 mips_output_filename (FILE *stream, const char *name)
5663 char ltext_label_name[100];
5665 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5667 if (write_symbols == DWARF2_DEBUG)
5669 else if (mips_output_filename_first_time)
5671 mips_output_filename_first_time = 0;
5673 current_function_file = name;
5674 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5675 /* This tells mips-tfile that stabs will follow. */
5676 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5677 fprintf (stream, "\t#@stabs\n");
5680 else if (write_symbols == DBX_DEBUG)
5682 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5683 fprintf (stream, "%s", ASM_STABS_OP);
5684 output_quoted_string (stream, name);
5685 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5688 else if (name != current_function_file
5689 && strcmp (name, current_function_file) != 0)
5692 current_function_file = name;
5693 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5697 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5698 as well as a .loc, since it is possible that MIPS ECOFF might not be
5699 able to represent the location for inlines that come from a different
5703 mips_output_lineno (FILE *stream, int line)
5705 if (write_symbols == DBX_DEBUG)
5708 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5709 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5710 LOCAL_LABEL_PREFIX, sym_lineno);
5714 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5715 LABEL_AFTER_LOC (stream);
5719 /* Output an ASCII string, in a space-saving way. */
5722 mips_output_ascii (FILE *stream, const char *string_param, size_t len)
5726 register const unsigned char *string =
5727 (const unsigned char *)string_param;
5729 fprintf (stream, "\t.ascii\t\"");
5730 for (i = 0; i < len; i++)
5732 register int c = string[i];
5738 putc ('\\', stream);
5743 case TARGET_NEWLINE:
5744 fputs ("\\n", stream);
5746 && (((c = string[i+1]) >= '\040' && c <= '~')
5747 || c == TARGET_TAB))
5748 cur_pos = 32767; /* break right here */
5754 fputs ("\\t", stream);
5759 fputs ("\\f", stream);
5764 fputs ("\\b", stream);
5769 fputs ("\\r", stream);
5774 if (c >= ' ' && c < 0177)
5781 fprintf (stream, "\\%03o", c);
5786 if (cur_pos > 72 && i+1 < len)
5789 fprintf (stream, "\"\n\t.ascii\t\"");
5792 fprintf (stream, "\"\n");
5795 /* Implement TARGET_ASM_FILE_START. */
5798 mips_file_start (void)
5800 default_file_start ();
5802 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5803 inside of a .set noreorder section jumps to a label outside of the .set
5804 noreorder section. Revision 2.20 just set nobopt silently rather than
5807 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5808 fprintf (asm_out_file, "\t.set\tnobopt\n");
5812 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5813 /* Generate a special section to describe the ABI switches used to
5814 produce the resultant binary. This used to be done by the assembler
5815 setting bits in the ELF header's flags field, but we have run out of
5816 bits. GDB needs this information in order to be able to correctly
5817 debug these binaries. See the function mips_gdbarch_init() in
5818 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5819 causes unnecessary IRIX 6 ld warnings. */
5820 const char * abi_string = NULL;
5824 case ABI_32: abi_string = "abi32"; break;
5825 case ABI_N32: abi_string = "abiN32"; break;
5826 case ABI_64: abi_string = "abi64"; break;
5827 case ABI_O64: abi_string = "abiO64"; break;
5828 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5832 /* Note - we use fprintf directly rather than called named_section()
5833 because in this way we can avoid creating an allocated section. We
5834 do not want this section to take up any space in the running
5836 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5838 /* Restore the default section. */
5839 fprintf (asm_out_file, "\t.previous\n");
5843 /* Generate the pseudo ops that System V.4 wants. */
5844 #ifndef ABICALLS_ASM_OP
5845 #define ABICALLS_ASM_OP "\t.abicalls"
5847 if (TARGET_ABICALLS)
5848 /* ??? but do not want this (or want pic0) if -non-shared? */
5849 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5852 fprintf (asm_out_file, "\t.set\tmips16\n");
5854 if (flag_verbose_asm)
5855 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5857 mips_section_threshold, mips_arch_info->name, mips_isa);
5860 #ifdef BSS_SECTION_ASM_OP
5861 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5862 in the use of sbss. */
5865 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5866 unsigned HOST_WIDE_INT size, int align)
5868 extern tree last_assemble_variable_decl;
5870 if (mips_in_small_data_p (decl))
5871 named_section (0, ".sbss", 0);
5874 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5875 last_assemble_variable_decl = decl;
5876 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5877 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5881 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5882 .externs for any small-data variables that turned out to be external. */
5885 mips_file_end (void)
5888 struct extern_list *p;
5892 fputs ("\n", asm_out_file);
5894 for (p = extern_head; p != 0; p = p->next)
5896 name_tree = get_identifier (p->name);
5898 /* Positively ensure only one .extern for any given symbol. */
5899 if (! TREE_ASM_WRITTEN (name_tree))
5901 TREE_ASM_WRITTEN (name_tree) = 1;
5902 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5903 `.global name .text' directive for every used but
5904 undefined function. If we don't, the linker may perform
5905 an optimization (skipping over the insns that set $gp)
5906 when it is unsafe. */
5907 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5909 fputs ("\t.globl ", asm_out_file);
5910 assemble_name (asm_out_file, p->name);
5911 fputs (" .text\n", asm_out_file);
5915 fputs ("\t.extern\t", asm_out_file);
5916 assemble_name (asm_out_file, p->name);
5917 fprintf (asm_out_file, ", %d\n", p->size);
5924 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5925 macros, mark the symbol as written so that mips_file_end won't emit an
5929 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5930 const char *final_string, int size)
5932 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5933 assemble_name (stream, name);
5934 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5936 if (!TARGET_EXPLICIT_RELOCS)
5938 tree name_tree = get_identifier (name);
5939 TREE_ASM_WRITTEN (name_tree) = 1;
5943 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5944 extern int size_directive_output;
5946 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5947 definitions except that it uses mips_declare_object() to emit the label. */
5950 mips_declare_object_name (FILE *stream, const char *name,
5951 tree decl ATTRIBUTE_UNUSED)
5953 if (!TARGET_SGI_O32_AS)
5955 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5956 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5959 size_directive_output = 0;
5960 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5964 size_directive_output = 1;
5965 size = int_size_in_bytes (TREE_TYPE (decl));
5966 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5970 mips_declare_object (stream, name, "", ":\n", 0);
5973 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5976 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5980 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5981 if (!TARGET_SGI_O32_AS
5982 && !flag_inhibit_size_directive
5983 && DECL_SIZE (decl) != 0
5984 && !at_end && top_level
5985 && DECL_INITIAL (decl) == error_mark_node
5986 && !size_directive_output)
5990 size_directive_output = 1;
5991 size = int_size_in_bytes (TREE_TYPE (decl));
5992 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5997 /* Return the register that should be used as the global pointer
5998 within this function. Return 0 if the function doesn't need
5999 a global pointer. */
6002 mips_global_pointer (void)
6006 /* $gp is always available in non-abicalls code. */
6007 if (!TARGET_ABICALLS)
6008 return GLOBAL_POINTER_REGNUM;
6010 /* We must always provide $gp when it is used implicitly. */
6011 if (!TARGET_EXPLICIT_RELOCS)
6012 return GLOBAL_POINTER_REGNUM;
6014 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6016 if (current_function_profile)
6017 return GLOBAL_POINTER_REGNUM;
6019 /* If the gp is never referenced, there's no need to initialize it.
6020 Note that reload can sometimes introduce constant pool references
6021 into a function that otherwise didn't need them. For example,
6022 suppose we have an instruction like:
6024 (set (reg:DF R1) (float:DF (reg:SI R2)))
6026 If R2 turns out to be constant such as 1, the instruction may have a
6027 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6028 using this constant if R2 doesn't get allocated to a register.
6030 In cases like these, reload will have added the constant to the pool
6031 but no instruction will yet refer to it. */
6032 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6033 && !current_function_uses_const_pool)
6036 /* We need a global pointer, but perhaps we can use a call-clobbered
6037 register instead of $gp. */
6038 if (TARGET_NEWABI && current_function_is_leaf)
6039 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6040 if (!regs_ever_live[regno]
6041 && call_used_regs[regno]
6042 && !fixed_regs[regno])
6045 return GLOBAL_POINTER_REGNUM;
6049 /* Return true if the current function must save REGNO. */
6052 mips_save_reg_p (unsigned int regno)
6054 /* We only need to save $gp for NewABI PIC. */
6055 if (regno == GLOBAL_POINTER_REGNUM)
6056 return (TARGET_ABICALLS && TARGET_NEWABI
6057 && cfun->machine->global_pointer == regno);
6059 /* Check call-saved registers. */
6060 if (regs_ever_live[regno] && !call_used_regs[regno])
6063 /* We need to save the old frame pointer before setting up a new one. */
6064 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6067 /* We need to save the incoming return address if it is ever clobbered
6068 within the function. */
6069 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6076 return_type = DECL_RESULT (current_function_decl);
6078 /* $18 is a special case in mips16 code. It may be used to call
6079 a function which returns a floating point value, but it is
6080 marked in call_used_regs. */
6081 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6084 /* $31 is also a special case. It will be used to copy a return
6085 value into the floating point registers if the return value is
6087 if (regno == GP_REG_FIRST + 31
6088 && mips16_hard_float
6089 && !aggregate_value_p (return_type, current_function_decl)
6090 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6091 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6099 /* Return the bytes needed to compute the frame pointer from the current
6100 stack pointer. SIZE is the size (in bytes) of the local variables.
6102 Mips stack frames look like:
6104 Before call After call
6105 +-----------------------+ +-----------------------+
6108 | caller's temps. | | caller's temps. |
6110 +-----------------------+ +-----------------------+
6112 | arguments on stack. | | arguments on stack. |
6114 +-----------------------+ +-----------------------+
6115 | 4 words to save | | 4 words to save |
6116 | arguments passed | | arguments passed |
6117 | in registers, even | | in registers, even |
6118 SP->| if not passed. | VFP->| if not passed. |
6119 +-----------------------+ +-----------------------+
6121 | fp register save |
6123 +-----------------------+
6125 | gp register save |
6127 +-----------------------+
6131 +-----------------------+
6133 | alloca allocations |
6135 +-----------------------+
6137 | GP save for V.4 abi |
6139 +-----------------------+
6141 | arguments on stack |
6143 +-----------------------+
6145 | arguments passed |
6146 | in registers, even |
6147 low SP->| if not passed. |
6148 memory +-----------------------+
6153 compute_frame_size (HOST_WIDE_INT size)
6156 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6157 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6158 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6159 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6160 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6161 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6162 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6163 long mask; /* mask of saved gp registers */
6164 long fmask; /* mask of saved fp registers */
6166 cfun->machine->global_pointer = mips_global_pointer ();
6172 var_size = MIPS_STACK_ALIGN (size);
6173 args_size = current_function_outgoing_args_size;
6174 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6176 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6177 functions. If the function has local variables, we're committed
6178 to allocating it anyway. Otherwise reclaim it here. */
6179 if (var_size == 0 && current_function_is_leaf)
6180 cprestore_size = args_size = 0;
6182 /* The MIPS 3.0 linker does not like functions that dynamically
6183 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6184 looks like we are trying to create a second frame pointer to the
6185 function, so allocate some stack space to make it happy. */
6187 if (args_size == 0 && current_function_calls_alloca)
6188 args_size = 4 * UNITS_PER_WORD;
6190 total_size = var_size + args_size + cprestore_size;
6192 /* Calculate space needed for gp registers. */
6193 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6194 if (mips_save_reg_p (regno))
6196 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6197 mask |= 1L << (regno - GP_REG_FIRST);
6200 /* We need to restore these for the handler. */
6201 if (current_function_calls_eh_return)
6206 regno = EH_RETURN_DATA_REGNO (i);
6207 if (regno == INVALID_REGNUM)
6209 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6210 mask |= 1L << (regno - GP_REG_FIRST);
6214 /* This loop must iterate over the same space as its companion in
6215 save_restore_insns. */
6216 for (regno = (FP_REG_LAST - FP_INC + 1);
6217 regno >= FP_REG_FIRST;
6220 if (mips_save_reg_p (regno))
6222 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6223 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6227 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6228 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6230 /* Add in space reserved on the stack by the callee for storing arguments
6231 passed in registers. */
6232 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6233 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6235 /* Save other computed information. */
6236 cfun->machine->frame.total_size = total_size;
6237 cfun->machine->frame.var_size = var_size;
6238 cfun->machine->frame.args_size = args_size;
6239 cfun->machine->frame.cprestore_size = cprestore_size;
6240 cfun->machine->frame.gp_reg_size = gp_reg_size;
6241 cfun->machine->frame.fp_reg_size = fp_reg_size;
6242 cfun->machine->frame.mask = mask;
6243 cfun->machine->frame.fmask = fmask;
6244 cfun->machine->frame.initialized = reload_completed;
6245 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6246 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6250 unsigned long offset;
6252 offset = (args_size + cprestore_size + var_size
6253 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6254 cfun->machine->frame.gp_sp_offset = offset;
6255 cfun->machine->frame.gp_save_offset = offset - total_size;
6259 cfun->machine->frame.gp_sp_offset = 0;
6260 cfun->machine->frame.gp_save_offset = 0;
6265 unsigned long offset = (args_size + cprestore_size + var_size
6266 + gp_reg_rounded + fp_reg_size
6267 - FP_INC * UNITS_PER_FPREG);
6268 cfun->machine->frame.fp_sp_offset = offset;
6269 cfun->machine->frame.fp_save_offset = offset - total_size;
6273 cfun->machine->frame.fp_sp_offset = 0;
6274 cfun->machine->frame.fp_save_offset = 0;
6277 /* Ok, we're done. */
6281 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6282 pointer or argument pointer. TO is either the stack pointer or
6283 hard frame pointer. */
6286 mips_initial_elimination_offset (int from, int to)
6290 compute_frame_size (get_frame_size ());
6292 /* Set OFFSET to the offset from the stack pointer. */
6295 case FRAME_POINTER_REGNUM:
6299 case ARG_POINTER_REGNUM:
6300 offset = cfun->machine->frame.total_size;
6301 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
6302 offset -= current_function_pretend_args_size;
6309 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6310 offset -= cfun->machine->frame.args_size;
6315 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6316 back to a previous frame. */
6318 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6323 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6326 /* Use FN to save or restore register REGNO. MODE is the register's
6327 mode and OFFSET is the offset of its save slot from the current
6331 mips_save_restore_reg (enum machine_mode mode, int regno,
6332 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6336 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6337 if (!current_function_calls_eh_return)
6338 RTX_UNCHANGING_P (mem) = 1;
6340 fn (gen_rtx_REG (mode, regno), mem);
6344 /* Call FN for each register that is saved by the current function.
6345 SP_OFFSET is the offset of the current stack pointer from the start
6349 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6351 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6353 enum machine_mode fpr_mode;
6354 HOST_WIDE_INT offset;
6357 /* Save registers starting from high to low. The debuggers prefer at least
6358 the return register be stored at func+4, and also it allows us not to
6359 need a nop in the epilog if at least one register is reloaded in
6360 addition to return address. */
6361 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6362 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6363 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6365 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6366 offset -= GET_MODE_SIZE (gpr_mode);
6369 /* This loop must iterate over the same space as its companion in
6370 compute_frame_size. */
6371 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6372 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6373 for (regno = (FP_REG_LAST - FP_INC + 1);
6374 regno >= FP_REG_FIRST;
6376 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6378 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6379 offset -= GET_MODE_SIZE (fpr_mode);
6384 /* Set up the stack and frame (if desired) for the function. */
6387 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6390 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6392 /* ??? When is this really needed? At least the GNU assembler does not
6393 need the source filename more than once in the file, beyond what is
6394 emitted by the debug information. */
6396 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6398 #ifdef SDB_DEBUGGING_INFO
6399 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6400 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6403 /* In mips16 mode, we may need to generate a 32 bit to handle
6404 floating point arguments. The linker will arrange for any 32 bit
6405 functions to call this stub, which will then jump to the 16 bit
6407 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6408 && current_function_args_info.fp_code != 0)
6409 build_mips16_function_stub (file);
6411 if (!FUNCTION_NAME_ALREADY_DECLARED)
6413 /* Get the function name the same way that toplev.c does before calling
6414 assemble_start_function. This is needed so that the name used here
6415 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6416 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6418 if (!flag_inhibit_size_directive)
6420 fputs ("\t.ent\t", file);
6421 assemble_name (file, fnname);
6425 assemble_name (file, fnname);
6426 fputs (":\n", file);
6429 if (!flag_inhibit_size_directive)
6431 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6433 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %ld, gp= %ld\n",
6434 (reg_names[(frame_pointer_needed)
6435 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6436 ((frame_pointer_needed && TARGET_MIPS16)
6437 ? ((long) tsize - cfun->machine->frame.args_size)
6439 reg_names[GP_REG_FIRST + 31],
6440 cfun->machine->frame.var_size,
6441 cfun->machine->frame.num_gp,
6442 cfun->machine->frame.num_fp,
6443 cfun->machine->frame.args_size,
6444 cfun->machine->frame.cprestore_size);
6446 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6447 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6448 cfun->machine->frame.mask,
6449 cfun->machine->frame.gp_save_offset,
6450 cfun->machine->frame.fmask,
6451 cfun->machine->frame.fp_save_offset);
6454 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6455 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6458 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6460 /* Handle the initialization of $gp for SVR4 PIC. */
6461 if (!cfun->machine->all_noreorder_p)
6462 output_asm_insn ("%(.cpload\t%^%)", 0);
6464 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6466 else if (cfun->machine->all_noreorder_p)
6467 output_asm_insn ("%(%<", 0);
6470 /* Make the last instruction frame related and note that it performs
6471 the operation described by FRAME_PATTERN. */
6474 mips_set_frame_expr (rtx frame_pattern)
6478 insn = get_last_insn ();
6479 RTX_FRAME_RELATED_P (insn) = 1;
6480 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6486 /* Return a frame-related rtx that stores REG at MEM.
6487 REG must be a single register. */
6490 mips_frame_set (rtx mem, rtx reg)
6492 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6493 RTX_FRAME_RELATED_P (set) = 1;
6498 /* Save register REG to MEM. Make the instruction frame-related. */
6501 mips_save_reg (rtx reg, rtx mem)
6503 if (GET_MODE (reg) == DFmode && mips_split_64bit_move_p (mem, reg))
6507 mips_split_64bit_move (mem, reg);
6508 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6509 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6510 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6515 && REGNO (reg) != GP_REG_FIRST + 31
6516 && !M16_REG_P (REGNO (reg)))
6518 /* Save a non-mips16 register by moving it through a temporary.
6519 We don't need to do this for $31 since there's a special
6520 instruction for it. */
6521 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6522 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6525 emit_move_insn (mem, reg);
6527 mips_set_frame_expr (mips_frame_set (mem, reg));
6532 /* Emit an instruction to move SRC into DEST. When generating
6533 explicit reloc code, mark the instruction as potentially dead. */
6536 mips_gp_insn (rtx dest, rtx src)
6540 insn = emit_insn (gen_rtx_SET (VOIDmode, dest, src));
6541 if (TARGET_EXPLICIT_RELOCS)
6543 /* compute_frame_size assumes that any function which uses the
6544 constant pool will need a gp. However, all constant
6545 pool references could be eliminated, in which case
6546 it is OK for flow to delete the gp load as well. */
6547 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx,
6552 /* Expand the prologue into a bunch of separate insns. */
6555 mips_expand_prologue (void)
6559 if (cfun->machine->global_pointer > 0)
6560 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6562 size = compute_frame_size (get_frame_size ());
6564 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6565 bytes beforehand; this is enough to cover the register save area
6566 without going out of range. */
6567 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6569 HOST_WIDE_INT step1;
6571 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6572 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6574 GEN_INT (-step1)))) = 1;
6576 mips_for_each_saved_reg (size, mips_save_reg);
6579 /* Allocate the rest of the frame. */
6582 if (SMALL_OPERAND (-size))
6583 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6585 GEN_INT (-size)))) = 1;
6588 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6591 /* There are no instructions to add or subtract registers
6592 from the stack pointer, so use the frame pointer as a
6593 temporary. We should always be using a frame pointer
6594 in this case anyway. */
6595 if (!frame_pointer_needed)
6598 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6599 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6600 hard_frame_pointer_rtx,
6601 MIPS_PROLOGUE_TEMP (Pmode)));
6602 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6605 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6607 MIPS_PROLOGUE_TEMP (Pmode)));
6609 /* Describe the combined effect of the previous instructions. */
6611 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6612 plus_constant (stack_pointer_rtx, -size)));
6616 /* Set up the frame pointer, if we're using one. In mips16 code,
6617 we point the frame pointer ahead of the outgoing argument area.
6618 This should allow more variables & incoming arguments to be
6619 acceesed with unextended instructions. */
6620 if (frame_pointer_needed)
6622 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6624 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6626 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6631 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6632 stack_pointer_rtx)) = 1;
6635 /* If generating o32/o64 abicalls, save $gp on the stack. */
6636 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6637 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6639 /* If generating n32/n64 abicalls, emit the instructions to load $gp. */
6640 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6642 rtx fnsymbol, fnaddr;
6644 fnsymbol = XEXP (DECL_RTL (current_function_decl), 0);
6645 fnaddr = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6647 mips_gp_insn (MIPS_PROLOGUE_TEMP (Pmode),
6648 mips_lui_reloc (fnsymbol, RELOC_LOADGP_HI));
6649 mips_gp_insn (MIPS_PROLOGUE_TEMP (Pmode),
6650 gen_rtx_PLUS (Pmode, MIPS_PROLOGUE_TEMP (Pmode), fnaddr));
6651 mips_gp_insn (pic_offset_table_rtx,
6652 gen_rtx_PLUS (Pmode, MIPS_PROLOGUE_TEMP (Pmode),
6653 mips_reloc (fnsymbol, RELOC_LOADGP_LO)));
6655 if (!TARGET_EXPLICIT_RELOCS)
6656 emit_insn (gen_loadgp_blockage ());
6659 /* If we are profiling, make sure no instructions are scheduled before
6660 the call to mcount. */
6662 if (current_function_profile)
6663 emit_insn (gen_blockage ());
6666 /* Do any necessary cleanup after a function to restore stack, frame,
6669 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6670 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6673 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6674 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6678 if (cfun->machine->all_noreorder_p)
6680 /* Avoid using %>%) since it adds excess whitespace. */
6681 output_asm_insn (".set\tmacro", 0);
6682 output_asm_insn (".set\treorder", 0);
6683 set_noreorder = set_nomacro = 0;
6686 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6690 /* Get the function name the same way that toplev.c does before calling
6691 assemble_start_function. This is needed so that the name used here
6692 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6693 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6694 fputs ("\t.end\t", file);
6695 assemble_name (file, fnname);
6699 while (string_constants != NULL)
6701 struct string_constant *next;
6703 next = string_constants->next;
6704 free (string_constants);
6705 string_constants = next;
6708 /* If any following function uses the same strings as this one, force
6709 them to refer those strings indirectly. Nearby functions could
6710 refer them using pc-relative addressing, but it isn't safe in
6711 general. For instance, some functions may be placed in sections
6712 other than .text, and we don't know whether they be close enough
6713 to this one. In large files, even other .text functions can be
6715 for (string = mips16_strings; string != 0; string = XEXP (string, 1))
6716 SYMBOL_REF_FLAG (XEXP (string, 0)) = 0;
6717 free_EXPR_LIST_list (&mips16_strings);
6719 /* Reinstate the normal $gp. */
6720 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6723 /* Emit instructions to restore register REG from slot MEM. */
6726 mips_restore_reg (rtx reg, rtx mem)
6728 /* There's no mips16 instruction to load $31 directly. Load into
6729 $7 instead and adjust the return insn appropriately. */
6730 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6731 reg = gen_rtx_REG (GET_MODE (reg), 7);
6733 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6735 /* Can't restore directly; move through a temporary. */
6736 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6737 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6740 emit_move_insn (reg, mem);
6744 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6745 if this epilogue precedes a sibling call, false if it is for a normal
6746 "epilogue" pattern. */
6749 mips_expand_epilogue (int sibcall_p)
6751 HOST_WIDE_INT step1, step2;
6754 if (!sibcall_p && mips_can_use_return_insn ())
6756 emit_jump_insn (gen_return ());
6760 /* Split the frame into two. STEP1 is the amount of stack we should
6761 deallocate before restoring the registers. STEP2 is the amount we
6762 should deallocate afterwards.
6764 Start off by assuming that no registers need to be restored. */
6765 step1 = cfun->machine->frame.total_size;
6768 /* Work out which register holds the frame address. Account for the
6769 frame pointer offset used by mips16 code. */
6770 if (!frame_pointer_needed)
6771 base = stack_pointer_rtx;
6774 base = hard_frame_pointer_rtx;
6776 step1 -= cfun->machine->frame.args_size;
6779 /* If we need to restore registers, deallocate as much stack as
6780 possible in the second step without going out of range. */
6781 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6783 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6787 /* Set TARGET to BASE + STEP1. */
6793 /* Get an rtx for STEP1 that we can add to BASE. */
6794 adjust = GEN_INT (step1);
6795 if (!SMALL_OPERAND (step1))
6797 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6798 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6801 /* Normal mode code can copy the result straight into $sp. */
6803 target = stack_pointer_rtx;
6805 emit_insn (gen_add3_insn (target, base, adjust));
6808 /* Copy TARGET into the stack pointer. */
6809 if (target != stack_pointer_rtx)
6810 emit_move_insn (stack_pointer_rtx, target);
6812 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6813 implicitly used by all SYMBOL_REFs. We must emit a blockage
6814 insn before restoring it. */
6815 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6816 emit_insn (gen_blockage ());
6818 /* Restore the registers. */
6819 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6822 /* Deallocate the final bit of the frame. */
6824 emit_insn (gen_add3_insn (stack_pointer_rtx,
6828 /* Add in the __builtin_eh_return stack adjustment. We need to
6829 use a temporary in mips16 code. */
6830 if (current_function_calls_eh_return)
6834 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6835 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6836 MIPS_EPILOGUE_TEMP (Pmode),
6837 EH_RETURN_STACKADJ_RTX));
6838 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6841 emit_insn (gen_add3_insn (stack_pointer_rtx,
6843 EH_RETURN_STACKADJ_RTX));
6848 /* The mips16 loads the return address into $7, not $31. */
6849 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6850 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6851 GP_REG_FIRST + 7)));
6853 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6854 GP_REG_FIRST + 31)));
6858 /* Return nonzero if this function is known to have a null epilogue.
6859 This allows the optimizer to omit jumps to jumps if no stack
6863 mips_can_use_return_insn (void)
6867 if (! reload_completed)
6870 if (regs_ever_live[31] || current_function_profile)
6873 return_type = DECL_RESULT (current_function_decl);
6875 /* In mips16 mode, a function which returns a floating point value
6876 needs to arrange to copy the return value into the floating point
6879 && mips16_hard_float
6880 && ! aggregate_value_p (return_type, current_function_decl)
6881 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6882 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6885 if (cfun->machine->frame.initialized)
6886 return cfun->machine->frame.total_size == 0;
6888 return compute_frame_size (get_frame_size ()) == 0;
6891 /* Returns nonzero if X contains a SYMBOL_REF. */
6894 symbolic_expression_p (rtx x)
6896 if (GET_CODE (x) == SYMBOL_REF)
6899 if (GET_CODE (x) == CONST)
6900 return symbolic_expression_p (XEXP (x, 0));
6902 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
6903 return symbolic_expression_p (XEXP (x, 0));
6905 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
6906 || GET_RTX_CLASS (GET_CODE (x)) == '2')
6907 return (symbolic_expression_p (XEXP (x, 0))
6908 || symbolic_expression_p (XEXP (x, 1)));
6913 /* Choose the section to use for the constant rtx expression X that has
6917 mips_select_rtx_section (enum machine_mode mode, rtx x,
6918 unsigned HOST_WIDE_INT align)
6922 /* In mips16 mode, the constant table always goes in the same section
6923 as the function, so that constants can be loaded using PC relative
6925 function_section (current_function_decl);
6927 else if (TARGET_EMBEDDED_DATA)
6929 /* For embedded applications, always put constants in read-only data,
6930 in order to reduce RAM usage. */
6931 mergeable_constant_section (mode, align, 0);
6935 /* For hosted applications, always put constants in small data if
6936 possible, as this gives the best performance. */
6937 /* ??? Consider using mergeable small data sections. */
6939 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
6940 && mips_section_threshold > 0)
6941 named_section (0, ".sdata", 0);
6942 else if (flag_pic && symbolic_expression_p (x))
6944 if (targetm.have_named_sections)
6945 named_section (0, ".data.rel.ro", 3);
6950 mergeable_constant_section (mode, align, 0);
6954 /* Choose the section to use for DECL. RELOC is true if its value contains
6955 any relocatable expression. */
6958 mips_select_section (tree decl, int reloc,
6959 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
6961 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
6962 && TREE_CODE (decl) == STRING_CST
6963 && !flag_writable_strings)
6964 /* For embedded position independent code, put constant strings in the
6965 text section, because the data section is limited to 64K in size.
6966 For mips16 code, put strings in the text section so that a PC
6967 relative load instruction can be used to get their address. */
6969 else if (targetm.have_named_sections)
6970 default_elf_select_section (decl, reloc, align);
6972 /* The native irix o32 assembler doesn't support named sections. */
6973 default_select_section (decl, reloc, align);
6977 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
6978 access DECL using %gp_rel(...)($gp). */
6981 mips_in_small_data_p (tree decl)
6985 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6988 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6992 /* Reject anything that isn't in a known small-data section. */
6993 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6994 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6997 /* If a symbol is defined externally, the assembler will use the
6998 usual -G rules when deciding how to implement macros. */
6999 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7002 else if (TARGET_EMBEDDED_DATA)
7004 /* Don't put constants into the small data section: we want them
7005 to be in ROM rather than RAM. */
7006 if (TREE_CODE (decl) != VAR_DECL)
7009 if (TREE_READONLY (decl)
7010 && !TREE_SIDE_EFFECTS (decl)
7011 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7015 size = int_size_in_bytes (TREE_TYPE (decl));
7016 return (size > 0 && size <= mips_section_threshold);
7020 /* When generating embedded PIC code, SYMBOL_REF_FLAG is set for
7021 symbols which are not in the .text section.
7023 When generating mips16 code, SYMBOL_REF_FLAG is set for string
7024 constants which are put in the .text section. We also record the
7025 total length of all such strings; this total is used to decide
7026 whether we need to split the constant table, and need not be
7029 When generating -mabicalls code, SYMBOL_REF_FLAG is set if we
7030 should treat the symbol as SYMBOL_GOT_LOCAL. */
7033 mips_encode_section_info (tree decl, rtx rtl, int first)
7037 if (GET_CODE (rtl) != MEM)
7040 symbol = XEXP (rtl, 0);
7042 if (GET_CODE (symbol) != SYMBOL_REF)
7047 if (first && TREE_CODE (decl) == STRING_CST
7048 && ! flag_writable_strings
7049 /* If this string is from a function, and the function will
7050 go in a gnu linkonce section, then we can't directly
7051 access the string. This gets an assembler error
7052 "unsupported PC relative reference to different section".
7053 If we modify SELECT_SECTION to put it in function_section
7054 instead of text_section, it still fails because
7055 DECL_SECTION_NAME isn't set until assemble_start_function.
7056 If we fix that, it still fails because strings are shared
7057 among multiple functions, and we have cross section
7058 references again. We force it to work by putting string
7059 addresses in the constant pool and indirecting. */
7060 && (! current_function_decl
7061 || ! DECL_ONE_ONLY (current_function_decl)))
7063 mips16_strings = alloc_EXPR_LIST (0, symbol, mips16_strings);
7064 SYMBOL_REF_FLAG (symbol) = 1;
7065 mips_string_length += TREE_STRING_LENGTH (decl);
7069 if (TARGET_EMBEDDED_PIC)
7071 if (TREE_CODE (decl) == VAR_DECL)
7072 SYMBOL_REF_FLAG (symbol) = 1;
7073 else if (TREE_CODE (decl) == FUNCTION_DECL)
7074 SYMBOL_REF_FLAG (symbol) = 0;
7075 else if (TREE_CODE (decl) == STRING_CST
7076 && ! flag_writable_strings)
7077 SYMBOL_REF_FLAG (symbol) = 0;
7079 SYMBOL_REF_FLAG (symbol) = 1;
7082 else if (TARGET_ABICALLS)
7084 /* Mark the symbol if we should treat it as SYMBOL_GOT_LOCAL.
7085 There are three cases to consider:
7087 - o32 PIC (either with or without explicit relocs)
7088 - n32/n64 PIC without explicit relocs
7089 - n32/n64 PIC with explicit relocs
7091 In the first case, both local and global accesses will use an
7092 R_MIPS_GOT16 relocation. We must correctly predict which of
7093 the two semantics (local or global) the assembler and linker
7094 will apply. The choice doesn't depend on the symbol's
7095 visibility, so we deliberately ignore decl_visibility and
7098 In the second case, the assembler will not use R_MIPS_GOT16
7099 relocations, but it chooses between local and global accesses
7100 in the same way as for o32 PIC.
7102 In the third case we have more freedom since both forms of
7103 access will work for any kind of symbol. However, there seems
7104 little point in doing things differently. */
7105 if (DECL_P (decl) && TREE_PUBLIC (decl))
7106 SYMBOL_REF_FLAG (symbol) = 0;
7108 SYMBOL_REF_FLAG (symbol) = 1;
7111 default_encode_section_info (decl, rtl, first);
7114 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7115 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7116 VALTYPE is null and MODE is the mode of the return value. */
7119 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7120 enum machine_mode mode)
7122 int reg = GP_RETURN;
7123 enum mode_class mclass;
7128 mode = TYPE_MODE (valtype);
7129 unsignedp = TREE_UNSIGNED (valtype);
7131 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote
7132 the mode just as PROMOTE_MODE does. */
7133 mode = promote_mode (valtype, mode, &unsignedp, 1);
7135 mclass = GET_MODE_CLASS (mode);
7137 if (mclass == MODE_FLOAT && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7140 else if (mclass == MODE_FLOAT && mode == TFmode)
7141 /* long doubles are really split between f0 and f2, not f1. Eek.
7142 Use DImode for each component, since GCC wants integer modes
7144 return gen_rtx_PARALLEL
7147 gen_rtx_EXPR_LIST (VOIDmode,
7148 gen_rtx_REG (DImode, FP_RETURN),
7150 gen_rtx_EXPR_LIST (VOIDmode,
7151 gen_rtx_REG (DImode, FP_RETURN + 2),
7152 GEN_INT (GET_MODE_SIZE (mode) / 2))));
7155 else if (mclass == MODE_COMPLEX_FLOAT
7156 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7158 enum machine_mode cmode = GET_MODE_INNER (mode);
7160 return gen_rtx_PARALLEL
7163 gen_rtx_EXPR_LIST (VOIDmode,
7164 gen_rtx_REG (cmode, FP_RETURN),
7166 gen_rtx_EXPR_LIST (VOIDmode,
7167 gen_rtx_REG (cmode, FP_RETURN + FP_INC),
7168 GEN_INT (GET_MODE_SIZE (cmode)))));
7171 else if (valtype && TREE_CODE (valtype) == RECORD_TYPE
7172 && mips_abi != ABI_32
7173 && mips_abi != ABI_O64
7174 && mips_abi != ABI_EABI)
7176 /* A struct with only one or two floating point fields is returned in
7177 the floating point registers. */
7178 tree field, fields[2];
7181 for (i = 0, field = TYPE_FIELDS (valtype); field;
7182 field = TREE_CHAIN (field))
7184 if (TREE_CODE (field) != FIELD_DECL)
7187 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7190 fields[i++] = field;
7193 /* Must check i, so that we reject structures with no elements. */
7198 /* The structure has DImode, but we don't allow DImode values
7199 in FP registers, so we use a PARALLEL even though it isn't
7200 strictly necessary. */
7201 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7203 return gen_rtx_PARALLEL
7206 gen_rtx_EXPR_LIST (VOIDmode,
7207 gen_rtx_REG (field_mode,
7214 enum machine_mode first_mode
7215 = TYPE_MODE (TREE_TYPE (fields[0]));
7216 enum machine_mode second_mode
7217 = TYPE_MODE (TREE_TYPE (fields[1]));
7218 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7219 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
7221 return gen_rtx_PARALLEL
7224 gen_rtx_EXPR_LIST (VOIDmode,
7225 gen_rtx_REG (first_mode,
7227 GEN_INT (first_offset)),
7228 gen_rtx_EXPR_LIST (VOIDmode,
7229 gen_rtx_REG (second_mode,
7231 GEN_INT (second_offset))));
7236 return gen_rtx_REG (mode, reg);
7239 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7240 nonzero when an argument must be passed by reference. */
7243 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7244 enum machine_mode mode, tree type,
7245 int named ATTRIBUTE_UNUSED)
7249 /* The EABI is the only one to pass args by reference. */
7250 if (mips_abi != ABI_EABI)
7253 /* ??? How should SCmode be handled? */
7254 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7257 size = int_size_in_bytes (type);
7258 return size == -1 || size > UNITS_PER_WORD;
7261 /* Return the class of registers for which a mode change from FROM to TO
7264 In little-endian mode, the hi-lo registers are numbered backwards,
7265 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7268 Similarly, when using paired floating-point registers, the first
7269 register holds the low word, regardless of endianness. So in big
7270 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7273 Also, loading a 32-bit value into a 64-bit floating-point register
7274 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7275 We can't allow 64-bit float registers to change from a 32-bit
7276 mode to a 64-bit mode. */
7279 mips_cannot_change_mode_class (enum machine_mode from,
7280 enum machine_mode to, enum reg_class class)
7282 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7284 if (TARGET_BIG_ENDIAN)
7285 return reg_classes_intersect_p (FP_REGS, class);
7287 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7288 return reg_classes_intersect_p (HI_REG, class);
7293 /* This function returns the register class required for a secondary
7294 register when copying between one of the registers in CLASS, and X,
7295 using MODE. If IN_P is nonzero, the copy is going from X to the
7296 register, otherwise the register is the source. A return value of
7297 NO_REGS means that no secondary register is required. */
7300 mips_secondary_reload_class (enum reg_class class,
7301 enum machine_mode mode, rtx x, int in_p)
7303 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7307 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7308 regno = true_regnum (x);
7310 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7312 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25)
7313 && DANGEROUS_FOR_LA25_P (x))
7316 /* Copying from HI or LO to anywhere other than a general register
7317 requires a general register. */
7318 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7320 if (TARGET_MIPS16 && in_p)
7322 /* We can't really copy to HI or LO at all in mips16 mode. */
7325 return gp_reg_p ? NO_REGS : gr_regs;
7327 if (MD_REG_P (regno))
7329 if (TARGET_MIPS16 && ! in_p)
7331 /* We can't really copy to HI or LO at all in mips16 mode. */
7334 return class == gr_regs ? NO_REGS : gr_regs;
7337 /* We can only copy a value to a condition code register from a
7338 floating point register, and even then we require a scratch
7339 floating point register. We can only copy a value out of a
7340 condition code register into a general register. */
7341 if (class == ST_REGS)
7345 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
7347 if (ST_REG_P (regno))
7351 return class == GR_REGS ? NO_REGS : GR_REGS;
7354 if (class == FP_REGS)
7356 if (GET_CODE (x) == MEM)
7358 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7361 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7363 /* We can use the l.s and l.d macros to load floating-point
7364 constants. ??? For l.s, we could probably get better
7365 code by returning GR_REGS here. */
7368 else if (GP_REG_P (regno) || x == CONST0_RTX (mode))
7370 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7373 else if (FP_REG_P (regno))
7375 /* In this case we can use mov.s or mov.d. */
7380 /* Otherwise, we need to reload through an integer register. */
7385 /* In mips16 mode, going between memory and anything but M16_REGS
7386 requires an M16_REG. */
7389 if (class != M16_REGS && class != M16_NA_REGS)
7397 if (class == M16_REGS || class == M16_NA_REGS)
7406 /* Implement CLASS_MAX_NREGS.
7408 Usually all registers are word-sized. The only supported exception
7409 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7410 registers. A word-based calculation is correct even in that case,
7411 since -msingle-float disallows multi-FPR values. */
7414 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7415 enum machine_mode mode)
7417 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7421 mips_valid_pointer_mode (enum machine_mode mode)
7423 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7427 /* If we can access small data directly (using gp-relative relocation
7428 operators) return the small data pointer, otherwise return null.
7430 For each mips16 function which refers to GP relative symbols, we
7431 use a pseudo register, initialized at the start of the function, to
7432 hold the $gp value. */
7435 mips_sdata_pointer (void)
7437 if (TARGET_EXPLICIT_RELOCS)
7438 return pic_offset_table_rtx;
7440 if (!TARGET_MIPS16 || no_new_pseudos)
7443 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7448 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7449 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7451 /* We want to initialize this to a value which gcc will believe
7453 const_gp = gen_rtx_CONST (Pmode, pic_offset_table_rtx);
7455 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7457 insn = get_insns ();
7460 push_topmost_sequence ();
7461 /* We need to emit the initialization after the FUNCTION_BEG
7462 note, so that it will be integrated. */
7463 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7464 if (GET_CODE (scan) == NOTE
7465 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7467 if (scan == NULL_RTX)
7468 scan = get_insns ();
7469 insn = emit_insn_after (insn, scan);
7470 pop_topmost_sequence ();
7473 return cfun->machine->mips16_gp_pseudo_rtx;
7476 /* Write out code to move floating point arguments in or out of
7477 general registers. Output the instructions to FILE. FP_CODE is
7478 the code describing which arguments are present (see the comment at
7479 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7480 we are copying from the floating point registers. */
7483 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7489 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7490 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
7497 gparg = GP_ARG_FIRST;
7498 fparg = FP_ARG_FIRST;
7499 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7503 if ((fparg & 1) != 0)
7505 fprintf (file, "\t%s\t%s,%s\n", s,
7506 reg_names[gparg], reg_names[fparg]);
7508 else if ((f & 3) == 2)
7511 fprintf (file, "\td%s\t%s,%s\n", s,
7512 reg_names[gparg], reg_names[fparg]);
7515 if ((fparg & 1) != 0)
7517 if (TARGET_BIG_ENDIAN)
7518 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7519 reg_names[gparg], reg_names[fparg + 1], s,
7520 reg_names[gparg + 1], reg_names[fparg]);
7522 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7523 reg_names[gparg], reg_names[fparg], s,
7524 reg_names[gparg + 1], reg_names[fparg + 1]);
7537 /* Build a mips16 function stub. This is used for functions which
7538 take arguments in the floating point registers. It is 32 bit code
7539 that moves the floating point args into the general registers, and
7540 then jumps to the 16 bit code. */
7543 build_mips16_function_stub (FILE *file)
7546 char *secname, *stubname;
7547 tree stubid, stubdecl;
7551 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7552 secname = (char *) alloca (strlen (fnname) + 20);
7553 sprintf (secname, ".mips16.fn.%s", fnname);
7554 stubname = (char *) alloca (strlen (fnname) + 20);
7555 sprintf (stubname, "__fn_stub_%s", fnname);
7556 stubid = get_identifier (stubname);
7557 stubdecl = build_decl (FUNCTION_DECL, stubid,
7558 build_function_type (void_type_node, NULL_TREE));
7559 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7561 fprintf (file, "\t# Stub function for %s (", current_function_name);
7563 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7565 fprintf (file, "%s%s",
7566 need_comma ? ", " : "",
7567 (f & 3) == 1 ? "float" : "double");
7570 fprintf (file, ")\n");
7572 fprintf (file, "\t.set\tnomips16\n");
7573 function_section (stubdecl);
7574 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7576 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7577 within a .ent, and we can not emit another .ent. */
7578 if (!FUNCTION_NAME_ALREADY_DECLARED)
7580 fputs ("\t.ent\t", file);
7581 assemble_name (file, stubname);
7585 assemble_name (file, stubname);
7586 fputs (":\n", file);
7588 /* We don't want the assembler to insert any nops here. */
7589 fprintf (file, "\t.set\tnoreorder\n");
7591 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7593 fprintf (asm_out_file, "\t.set\tnoat\n");
7594 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7595 assemble_name (file, fnname);
7596 fprintf (file, "\n");
7597 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7598 fprintf (asm_out_file, "\t.set\tat\n");
7600 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7601 with one of the mfc1 instructions, because the result is not
7602 available for one instruction, so if the very first instruction
7603 in the function refers to the register, it will see the wrong
7605 fprintf (file, "\tnop\n");
7607 fprintf (file, "\t.set\treorder\n");
7609 if (!FUNCTION_NAME_ALREADY_DECLARED)
7611 fputs ("\t.end\t", file);
7612 assemble_name (file, stubname);
7616 fprintf (file, "\t.set\tmips16\n");
7618 function_section (current_function_decl);
7621 /* We keep a list of functions for which we have already built stubs
7622 in build_mips16_call_stub. */
7626 struct mips16_stub *next;
7631 static struct mips16_stub *mips16_stubs;
7633 /* Build a call stub for a mips16 call. A stub is needed if we are
7634 passing any floating point values which should go into the floating
7635 point registers. If we are, and the call turns out to be to a 32
7636 bit function, the stub will be used to move the values into the
7637 floating point registers before calling the 32 bit function. The
7638 linker will magically adjust the function call to either the 16 bit
7639 function or the 32 bit stub, depending upon where the function call
7640 is actually defined.
7642 Similarly, we need a stub if the return value might come back in a
7643 floating point register.
7645 RETVAL is the location of the return value, or null if this is
7646 a call rather than a call_value. FN is the address of the
7647 function and ARG_SIZE is the size of the arguments. FP_CODE
7648 is the code built by function_arg. This function returns a nonzero
7649 value if it builds the call instruction itself. */
7652 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7656 char *secname, *stubname;
7657 struct mips16_stub *l;
7658 tree stubid, stubdecl;
7662 /* We don't need to do anything if we aren't in mips16 mode, or if
7663 we were invoked with the -msoft-float option. */
7664 if (! TARGET_MIPS16 || ! mips16_hard_float)
7667 /* Figure out whether the value might come back in a floating point
7669 fpret = (retval != 0
7670 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7671 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7673 /* We don't need to do anything if there were no floating point
7674 arguments and the value will not be returned in a floating point
7676 if (fp_code == 0 && ! fpret)
7679 /* We don't need to do anything if this is a call to a special
7680 mips16 support function. */
7681 if (GET_CODE (fn) == SYMBOL_REF
7682 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7685 /* This code will only work for o32 and o64 abis. The other ABI's
7686 require more sophisticated support. */
7687 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
7690 /* We can only handle SFmode and DFmode floating point return
7692 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7695 /* If we're calling via a function pointer, then we must always call
7696 via a stub. There are magic stubs provided in libgcc.a for each
7697 of the required cases. Each of them expects the function address
7698 to arrive in register $2. */
7700 if (GET_CODE (fn) != SYMBOL_REF)
7706 /* ??? If this code is modified to support other ABI's, we need
7707 to handle PARALLEL return values here. */
7709 sprintf (buf, "__mips16_call_stub_%s%d",
7711 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7714 id = get_identifier (buf);
7715 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
7717 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
7719 if (retval == NULL_RTX)
7720 insn = gen_call_internal (stub_fn, arg_size);
7722 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7723 insn = emit_call_insn (insn);
7725 /* Put the register usage information on the CALL. */
7726 if (GET_CODE (insn) != CALL_INSN)
7728 CALL_INSN_FUNCTION_USAGE (insn) =
7729 gen_rtx (EXPR_LIST, VOIDmode,
7730 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
7731 CALL_INSN_FUNCTION_USAGE (insn));
7733 /* If we are handling a floating point return value, we need to
7734 save $18 in the function prologue. Putting a note on the
7735 call will mean that regs_ever_live[$18] will be true if the
7736 call is not eliminated, and we can check that in the prologue
7739 CALL_INSN_FUNCTION_USAGE (insn) =
7740 gen_rtx (EXPR_LIST, VOIDmode,
7741 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7742 CALL_INSN_FUNCTION_USAGE (insn));
7744 /* Return 1 to tell the caller that we've generated the call
7749 /* We know the function we are going to call. If we have already
7750 built a stub, we don't need to do anything further. */
7752 fnname = XSTR (fn, 0);
7753 for (l = mips16_stubs; l != NULL; l = l->next)
7754 if (strcmp (l->name, fnname) == 0)
7759 /* Build a special purpose stub. When the linker sees a
7760 function call in mips16 code, it will check where the target
7761 is defined. If the target is a 32 bit call, the linker will
7762 search for the section defined here. It can tell which
7763 symbol this section is associated with by looking at the
7764 relocation information (the name is unreliable, since this
7765 might be a static function). If such a section is found, the
7766 linker will redirect the call to the start of the magic
7769 If the function does not return a floating point value, the
7770 special stub section is named
7773 If the function does return a floating point value, the stub
7775 .mips16.call.fp.FNNAME
7778 secname = (char *) alloca (strlen (fnname) + 40);
7779 sprintf (secname, ".mips16.call.%s%s",
7782 stubname = (char *) alloca (strlen (fnname) + 20);
7783 sprintf (stubname, "__call_stub_%s%s",
7786 stubid = get_identifier (stubname);
7787 stubdecl = build_decl (FUNCTION_DECL, stubid,
7788 build_function_type (void_type_node, NULL_TREE));
7789 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7791 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7793 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7797 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7799 fprintf (asm_out_file, "%s%s",
7800 need_comma ? ", " : "",
7801 (f & 3) == 1 ? "float" : "double");
7804 fprintf (asm_out_file, ")\n");
7806 fprintf (asm_out_file, "\t.set\tnomips16\n");
7807 assemble_start_function (stubdecl, stubname);
7809 if (!FUNCTION_NAME_ALREADY_DECLARED)
7811 fputs ("\t.ent\t", asm_out_file);
7812 assemble_name (asm_out_file, stubname);
7813 fputs ("\n", asm_out_file);
7815 assemble_name (asm_out_file, stubname);
7816 fputs (":\n", asm_out_file);
7819 /* We build the stub code by hand. That's the only way we can
7820 do it, since we can't generate 32 bit code during a 16 bit
7823 /* We don't want the assembler to insert any nops here. */
7824 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7826 mips16_fp_args (asm_out_file, fp_code, 0);
7830 fprintf (asm_out_file, "\t.set\tnoat\n");
7831 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7833 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7834 fprintf (asm_out_file, "\t.set\tat\n");
7835 /* Unfortunately, we can't fill the jump delay slot. We
7836 can't fill with one of the mtc1 instructions, because the
7837 result is not available for one instruction, so if the
7838 very first instruction in the function refers to the
7839 register, it will see the wrong value. */
7840 fprintf (asm_out_file, "\tnop\n");
7844 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7845 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7846 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7847 /* As above, we can't fill the delay slot. */
7848 fprintf (asm_out_file, "\tnop\n");
7849 if (GET_MODE (retval) == SFmode)
7850 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7851 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7854 if (TARGET_BIG_ENDIAN)
7856 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7857 reg_names[GP_REG_FIRST + 2],
7858 reg_names[FP_REG_FIRST + 1]);
7859 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7860 reg_names[GP_REG_FIRST + 3],
7861 reg_names[FP_REG_FIRST + 0]);
7865 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7866 reg_names[GP_REG_FIRST + 2],
7867 reg_names[FP_REG_FIRST + 0]);
7868 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7869 reg_names[GP_REG_FIRST + 3],
7870 reg_names[FP_REG_FIRST + 1]);
7873 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7874 /* As above, we can't fill the delay slot. */
7875 fprintf (asm_out_file, "\tnop\n");
7878 fprintf (asm_out_file, "\t.set\treorder\n");
7880 #ifdef ASM_DECLARE_FUNCTION_SIZE
7881 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7884 if (!FUNCTION_NAME_ALREADY_DECLARED)
7886 fputs ("\t.end\t", asm_out_file);
7887 assemble_name (asm_out_file, stubname);
7888 fputs ("\n", asm_out_file);
7891 fprintf (asm_out_file, "\t.set\tmips16\n");
7893 /* Record this stub. */
7894 l = (struct mips16_stub *) xmalloc (sizeof *l);
7895 l->name = xstrdup (fnname);
7897 l->next = mips16_stubs;
7901 /* If we expect a floating point return value, but we've built a
7902 stub which does not expect one, then we're in trouble. We can't
7903 use the existing stub, because it won't handle the floating point
7904 value. We can't build a new stub, because the linker won't know
7905 which stub to use for the various calls in this object file.
7906 Fortunately, this case is illegal, since it means that a function
7907 was declared in two different ways in a single compilation. */
7908 if (fpret && ! l->fpret)
7909 error ("can not handle inconsistent calls to `%s'", fnname);
7911 /* If we are calling a stub which handles a floating point return
7912 value, we need to arrange to save $18 in the prologue. We do
7913 this by marking the function call as using the register. The
7914 prologue will later see that it is used, and emit code to save
7921 if (retval == NULL_RTX)
7922 insn = gen_call_internal (fn, arg_size);
7924 insn = gen_call_value_internal (retval, fn, arg_size);
7925 insn = emit_call_insn (insn);
7927 if (GET_CODE (insn) != CALL_INSN)
7930 CALL_INSN_FUNCTION_USAGE (insn) =
7931 gen_rtx (EXPR_LIST, VOIDmode,
7932 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7933 CALL_INSN_FUNCTION_USAGE (insn));
7935 /* Return 1 to tell the caller that we've generated the call
7940 /* Return 0 to let the caller generate the call insn. */
7944 /* This function looks through the code for a function, and tries to
7945 optimize the usage of the $gp register. We arrange to copy $gp
7946 into a pseudo-register, and then let gcc's normal reload handling
7947 deal with the pseudo-register. Unfortunately, if reload choose to
7948 put the pseudo-register into a call-clobbered register, it will
7949 emit saves and restores for that register around any function
7950 calls. We don't need the saves, and it's faster to copy $gp than
7951 to do an actual restore. ??? This still means that we waste a
7954 This is an optimization, and the code which gcc has actually
7955 generated is correct, so we do not need to catch all cases. */
7958 mips16_optimize_gp (void)
7960 rtx gpcopy, slot, insn;
7962 /* Look through the instructions. Set GPCOPY to the register which
7963 holds a copy of $gp. Set SLOT to the stack slot where it is
7964 saved. If we find an instruction which sets GPCOPY to anything
7965 other than $gp or SLOT, then we can't use it. If we find an
7966 instruction which sets SLOT to anything other than GPCOPY, we
7971 for (insn = get_insns (); insn != NULL_RTX; insn = next_active_insn (insn))
7975 if (! INSN_P (insn))
7978 set = PATTERN (insn);
7980 /* We know that all references to memory will be inside a SET,
7981 because there is no other way to access memory on the mips16.
7982 We don't have to worry about a PARALLEL here, because the
7983 mips.md file will never generate them for memory references. */
7984 if (GET_CODE (set) != SET)
7987 if (gpcopy == NULL_RTX
7988 && GET_CODE (SET_SRC (set)) == CONST
7989 && XEXP (SET_SRC (set), 0) == pic_offset_table_rtx
7990 && GET_CODE (SET_DEST (set)) == REG)
7991 gpcopy = SET_DEST (set);
7992 else if (slot == NULL_RTX
7993 && gpcopy != NULL_RTX
7994 && GET_CODE (SET_DEST (set)) == MEM
7995 && GET_CODE (SET_SRC (set)) == REG
7996 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8000 offset = const0_rtx;
8001 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8002 if (GET_CODE (base) == REG
8003 && (REGNO (base) == STACK_POINTER_REGNUM
8004 || REGNO (base) == FRAME_POINTER_REGNUM))
8005 slot = SET_DEST (set);
8007 else if (gpcopy != NULL_RTX
8008 && (GET_CODE (SET_DEST (set)) == REG
8009 || GET_CODE (SET_DEST (set)) == SUBREG)
8010 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8011 && (GET_CODE (SET_DEST (set)) != REG
8012 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8013 || ((GET_CODE (SET_SRC (set)) != CONST
8014 || XEXP (SET_SRC (set), 0) != pic_offset_table_rtx)
8015 && ! rtx_equal_p (SET_SRC (set), slot))))
8017 else if (slot != NULL_RTX
8018 && GET_CODE (SET_DEST (set)) == MEM
8019 && rtx_equal_p (SET_DEST (set), slot)
8020 && (GET_CODE (SET_SRC (set)) != REG
8021 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8025 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8026 different optimization. Any time we find a copy of $28 into a
8027 register, followed by an add of a symbol_ref to that register, we
8028 convert it to load the value from the constant table instead.
8029 The copy and add will take six bytes, just as the load and
8030 constant table entry will take six bytes. However, it is
8031 possible that the constant table entry will be shared.
8033 This could be a peephole optimization, but I don't know if the
8034 peephole code can call force_const_mem.
8036 Using the same register for the copy of $28 and the add of the
8037 symbol_ref is actually pretty likely, since the add instruction
8038 requires the destination and the first addend to be the same
8041 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8044 /* Used below in #if 0 area. */
8047 /* This optimization is only reasonable if the constant table
8048 entries are only 4 bytes. */
8049 if (Pmode != SImode)
8053 /* ??? FIXME. Rewrite for new UNSPEC_RELOC stuff. */
8054 for (insn = get_insns (); insn != NULL_RTX; insn = next)
8061 next = NEXT_INSN (next);
8063 while (next != NULL_RTX
8064 && (GET_CODE (next) == NOTE
8065 || (GET_CODE (next) == INSN
8066 && (GET_CODE (PATTERN (next)) == USE
8067 || GET_CODE (PATTERN (next)) == CLOBBER))));
8069 if (next == NULL_RTX)
8072 if (! INSN_P (insn))
8075 if (! INSN_P (next))
8078 set1 = PATTERN (insn);
8079 if (GET_CODE (set1) != SET)
8081 set2 = PATTERN (next);
8082 if (GET_CODE (set2) != SET)
8085 if (GET_CODE (SET_DEST (set1)) == REG
8086 && GET_CODE (SET_SRC (set1)) == CONST
8087 && XEXP (SET_SRC (set1), 0) == pic_offset_table_rtx
8088 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8089 && GET_CODE (SET_SRC (set2)) == PLUS
8090 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8091 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8092 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8096 /* We've found a case we can change to load from the
8099 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8100 if (GET_CODE (sym) != SYMBOL_REF)
8102 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8103 force_const_mem (Pmode, sym)),
8106 PUT_CODE (insn, NOTE);
8107 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8108 NOTE_SOURCE_FILE (insn) = 0;
8110 PUT_CODE (next, NOTE);
8111 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8112 NOTE_SOURCE_FILE (next) = 0;
8119 /* We can safely remove all assignments to SLOT from GPCOPY, and
8120 replace all assignments from SLOT to GPCOPY with assignments from
8123 for (insn = get_insns (); insn != NULL_RTX; insn = next_active_insn (insn))
8127 if (! INSN_P (insn))
8130 set = PATTERN (insn);
8131 if (GET_CODE (set) != SET)
8134 if (GET_CODE (SET_DEST (set)) == MEM
8135 && rtx_equal_p (SET_DEST (set), slot)
8136 && GET_CODE (SET_SRC (set)) == REG
8137 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8139 PUT_CODE (insn, NOTE);
8140 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8141 NOTE_SOURCE_FILE (insn) = 0;
8143 else if (GET_CODE (SET_DEST (set)) == REG
8144 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8145 && GET_CODE (SET_SRC (set)) == MEM
8146 && rtx_equal_p (SET_SRC (set), slot))
8148 enum machine_mode mode;
8151 mode = GET_MODE (SET_DEST (set));
8152 src = gen_rtx_CONST (mode, pic_offset_table_rtx);
8153 emit_insn_after (gen_rtx_SET (VOIDmode, SET_DEST (set), src), insn);
8154 PUT_CODE (insn, NOTE);
8155 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8156 NOTE_SOURCE_FILE (insn) = 0;
8161 /* We keep a list of constants we which we have to add to internal
8162 constant tables in the middle of large functions. */
8166 struct constant *next;
8169 enum machine_mode mode;
8172 /* Add a constant to the list in *PCONSTANTS. */
8175 add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
8179 for (c = *pconstants; c != NULL; c = c->next)
8180 if (mode == c->mode && rtx_equal_p (val, c->value))
8183 c = (struct constant *) xmalloc (sizeof *c);
8186 c->label = gen_label_rtx ();
8187 c->next = *pconstants;
8192 /* Dump out the constants in CONSTANTS after INSN. */
8195 dump_constants (struct constant *constants, rtx insn)
8205 struct constant *next;
8207 switch (GET_MODE_SIZE (c->mode))
8214 insn = emit_insn_after (gen_align_2 (), insn);
8219 insn = emit_insn_after (gen_align_4 (), insn);
8224 insn = emit_insn_after (gen_align_8 (), insn);
8229 insn = emit_label_after (c->label, insn);
8234 r = gen_consttable_qi (c->value);
8237 r = gen_consttable_hi (c->value);
8240 r = gen_consttable_si (c->value);
8243 r = gen_consttable_sf (c->value);
8246 r = gen_consttable_di (c->value);
8249 r = gen_consttable_df (c->value);
8255 insn = emit_insn_after (r, insn);
8262 emit_barrier_after (insn);
8265 /* Find the symbol in an address expression. */
8268 mips_find_symbol (rtx addr)
8270 if (GET_CODE (addr) == MEM)
8271 addr = XEXP (addr, 0);
8272 while (GET_CODE (addr) == CONST)
8273 addr = XEXP (addr, 0);
8274 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8276 if (GET_CODE (addr) == PLUS)
8280 l1 = mips_find_symbol (XEXP (addr, 0));
8281 l2 = mips_find_symbol (XEXP (addr, 1));
8282 if (l1 != NULL_RTX && l2 == NULL_RTX)
8284 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8290 /* In mips16 mode, we need to look through the function to check for
8291 PC relative loads that are out of range. */
8294 mips16_lay_out_constants (void)
8296 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
8298 struct constant *constants;
8300 first = get_insns ();
8302 /* Scan the function looking for PC relative loads which may be out
8303 of range. All such loads will either be from the constant table,
8304 or be getting the address of a constant string. If the size of
8305 the function plus the size of the constant table is less than
8306 0x8000, then all loads are in range. */
8309 for (insn = first; insn; insn = NEXT_INSN (insn))
8311 insns_len += get_attr_length (insn);
8313 /* ??? We put switch tables in .text, but we don't define
8314 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8315 compute their lengths correctly. */
8316 if (GET_CODE (insn) == JUMP_INSN)
8320 body = PATTERN (insn);
8321 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8322 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8323 * GET_MODE_SIZE (GET_MODE (body)));
8324 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8328 /* Store the original value of insns_len in cfun->machine, so
8329 that simple_memory_operand can look at it. */
8330 cfun->machine->insns_len = insns_len;
8332 pool_size = get_pool_size ();
8333 if (insns_len + pool_size + mips_string_length < 0x8000)
8336 /* Loop over the insns and figure out what the maximum internal pool
8338 max_internal_pool_size = 0;
8339 for (insn = first; insn; insn = NEXT_INSN (insn))
8341 if (GET_CODE (insn) == INSN
8342 && GET_CODE (PATTERN (insn)) == SET)
8346 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8347 if (src == NULL_RTX)
8349 if (CONSTANT_POOL_ADDRESS_P (src))
8350 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8351 else if (SYMBOL_REF_FLAG (src))
8352 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8358 first_constant_ref = -1;
8360 for (insn = first; insn; insn = NEXT_INSN (insn))
8362 if (GET_CODE (insn) == INSN
8363 && GET_CODE (PATTERN (insn)) == SET)
8366 enum machine_mode mode = VOIDmode;
8369 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8370 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8372 /* ??? This is very conservative, which means that we
8373 will generate too many copies of the constant table.
8374 The only solution would seem to be some form of
8376 if (((insns_len - addr)
8377 + max_internal_pool_size
8378 + get_pool_offset (src))
8381 val = get_pool_constant (src);
8382 mode = get_pool_mode (src);
8384 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8386 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8388 /* Including all of mips_string_length is conservative,
8389 and so is including all of max_internal_pool_size. */
8390 if (((insns_len - addr)
8391 + max_internal_pool_size
8393 + mips_string_length)
8399 max_internal_pool_size -= Pmode;
8402 if (val != NULL_RTX)
8406 /* This PC relative load is out of range. ??? In the
8407 case of a string constant, we are only guessing that
8408 it is range, since we don't know the offset of a
8409 particular string constant. */
8411 lab = add_constant (&constants, val, mode);
8412 newsrc = gen_rtx (MEM, mode,
8413 gen_rtx (LABEL_REF, VOIDmode, lab));
8414 RTX_UNCHANGING_P (newsrc) = 1;
8415 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8416 SET_DEST (PATTERN (insn)),
8418 INSN_CODE (insn) = -1;
8420 if (first_constant_ref < 0)
8421 first_constant_ref = addr;
8425 addr += get_attr_length (insn);
8427 /* ??? We put switch tables in .text, but we don't define
8428 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8429 compute their lengths correctly. */
8430 if (GET_CODE (insn) == JUMP_INSN)
8434 body = PATTERN (insn);
8435 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8436 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8437 * GET_MODE_SIZE (GET_MODE (body)));
8438 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8441 if (GET_CODE (insn) == BARRIER)
8443 /* Output any constants we have accumulated. Note that we
8444 don't need to change ADDR, since its only use is
8445 subtraction from INSNS_LEN, and both would be changed by
8447 ??? If the instructions up to the next barrier reuse a
8448 constant, it would often be better to continue
8450 if (constants != NULL)
8451 dump_constants (constants, insn);
8453 first_constant_ref = -1;
8456 if (constants != NULL
8457 && (NEXT_INSN (insn) == NULL
8458 || (first_constant_ref >= 0
8459 && (((addr - first_constant_ref)
8460 + 2 /* for alignment */
8461 + 2 /* for a short jump insn */
8465 /* If we haven't had a barrier within 0x8000 bytes of a
8466 constant reference or we are at the end of the function,
8467 emit a barrier now. */
8469 rtx label, jump, barrier;
8471 label = gen_label_rtx ();
8472 jump = emit_jump_insn_after (gen_jump (label), insn);
8473 JUMP_LABEL (jump) = label;
8474 LABEL_NUSES (label) = 1;
8475 barrier = emit_barrier_after (jump);
8476 emit_label_after (label, barrier);
8477 first_constant_ref = -1;
8481 /* ??? If we output all references to a constant in internal
8482 constants table, we don't need to output the constant in the real
8483 constant table, but we have no way to prevent that. */
8487 /* Subroutine of mips_reorg. If there is a hazard between INSN
8488 and a previous instruction, avoid it by inserting nops after
8491 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8492 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8493 before using the value of that register. *HILO_DELAY counts the
8494 number of instructions since the last hilo hazard (that is,
8495 the number of instructions since the last mflo or mfhi).
8497 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8498 for the next instruction.
8500 LO_REG is an rtx for the LO register, used in dependence checking. */
8503 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8504 rtx *delayed_reg, rtx lo_reg)
8512 pattern = PATTERN (insn);
8514 /* Do not put the whole function in .set noreorder if it contains
8515 an asm statement. We don't know whether there will be hazards
8516 between the asm statement and the gcc-generated code. */
8517 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8518 cfun->machine->all_noreorder_p = false;
8520 /* Ignore zero-length instructions (barriers and the like). */
8521 ninsns = get_attr_length (insn) / 4;
8525 /* Work out how many nops are needed. Note that we only care about
8526 registers that are explicitly mentioned in the instruction's pattern.
8527 It doesn't matter that calls use the argument registers or that they
8528 clobber hi and lo. */
8529 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8530 nops = 2 - *hilo_delay;
8531 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8536 /* Insert the nops between this instruction and the previous one.
8537 Each new nop takes us further from the last hilo hazard. */
8538 *hilo_delay += nops;
8540 emit_insn_after (gen_hazard_nop (), after);
8542 /* Set up the state for the next instruction. */
8543 *hilo_delay += ninsns;
8545 if (INSN_CODE (insn) >= 0)
8546 switch (get_attr_hazard (insn))
8556 set = single_set (insn);
8559 *delayed_reg = SET_DEST (set);
8565 /* Go through the instruction stream and insert nops where necessary.
8566 See if the whole function can then be put into .set noreorder &
8570 mips_avoid_hazards (void)
8572 rtx insn, last_insn, lo_reg, delayed_reg;
8575 /* Recalculate instruction lengths without taking nops into account. */
8576 cfun->machine->ignore_hazard_length_p = true;
8577 shorten_branches (get_insns ());
8579 /* The profiler code uses assembler macros. */
8580 cfun->machine->all_noreorder_p = !current_function_profile;
8585 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8587 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8590 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8591 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8592 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8593 &hilo_delay, &delayed_reg, lo_reg);
8595 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8596 &delayed_reg, lo_reg);
8603 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8611 mips16_optimize_gp ();
8612 mips16_lay_out_constants ();
8614 else if (TARGET_EXPLICIT_RELOCS)
8616 if (mips_flag_delayed_branch)
8617 dbr_schedule (get_insns (), rtl_dump_file);
8618 mips_avoid_hazards ();
8622 /* We need to use a special set of functions to handle hard floating
8623 point code in mips16 mode. Also, allow for --enable-gofast. */
8625 #include "config/gofast.h"
8628 mips_init_libfuncs (void)
8630 if (TARGET_MIPS16 && mips16_hard_float)
8632 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8633 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8634 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8635 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8637 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8638 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8639 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8640 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8641 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8642 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8644 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fixsfsi");
8645 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8647 if (TARGET_DOUBLE_FLOAT)
8649 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8650 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8651 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8652 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8654 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8655 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8656 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8657 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8658 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8659 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8661 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8662 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8664 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fixdfsi");
8665 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8669 gofast_maybe_init_libfuncs ();
8672 /* Return a number assessing the cost of moving a register in class
8673 FROM to class TO. The classes are expressed using the enumeration
8674 values such as `GENERAL_REGS'. A value of 2 is the default; other
8675 values are interpreted relative to that.
8677 It is not required that the cost always equal 2 when FROM is the
8678 same as TO; on some machines it is expensive to move between
8679 registers if they are not general registers.
8681 If reload sees an insn consisting of a single `set' between two
8682 hard registers, and if `REGISTER_MOVE_COST' applied to their
8683 classes returns a value of 2, reload does not check to ensure that
8684 the constraints of the insn are met. Setting a cost of other than
8685 2 will allow reload to verify that the constraints are met. You
8686 should do this if the `movM' pattern's constraints do not allow
8689 ??? We make the cost of moving from HI/LO into general
8690 registers the same as for one of moving general registers to
8691 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8692 pseudo to HI/LO. This might hurt optimizations though, it
8693 isn't clear if it is wise. And it might not work in all cases. We
8694 could solve the DImode LO reg problem by using a multiply, just
8695 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8696 problem by using divide instructions. divu puts the remainder in
8697 the HI reg, so doing a divide by -1 will move the value in the HI
8698 reg for all values except -1. We could handle that case by using a
8699 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8700 a compare/branch to test the input value to see which instruction
8701 we need to use. This gets pretty messy, but it is feasible. */
8704 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8705 enum reg_class to, enum reg_class from)
8707 if (from == M16_REGS && GR_REG_CLASS_P (to))
8709 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8711 else if (GR_REG_CLASS_P (from))
8715 else if (to == M16_NA_REGS)
8717 else if (GR_REG_CLASS_P (to))
8724 else if (to == FP_REGS)
8726 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8733 else if (COP_REG_CLASS_P (to))
8737 } /* GR_REG_CLASS_P (from) */
8738 else if (from == FP_REGS)
8740 if (GR_REG_CLASS_P (to))
8742 else if (to == FP_REGS)
8744 else if (to == ST_REGS)
8746 } /* from == FP_REGS */
8747 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8749 if (GR_REG_CLASS_P (to))
8756 } /* from == HI_REG, etc. */
8757 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8759 else if (COP_REG_CLASS_P (from))
8762 } /* COP_REG_CLASS_P (from) */
8769 /* Return the length of INSN. LENGTH is the initial length computed by
8770 attributes in the machine-description file. */
8773 mips_adjust_insn_length (rtx insn, int length)
8775 /* A unconditional jump has an unfilled delay slot if it is not part
8776 of a sequence. A conditional jump normally has a delay slot, but
8777 does not on MIPS16. */
8778 if (simplejump_p (insn)
8779 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8780 || GET_CODE (insn) == CALL_INSN)))
8783 /* See how many nops might be needed to avoid hardware hazards. */
8784 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8785 switch (get_attr_hazard (insn))
8799 /* All MIPS16 instructions are a measly two bytes. */
8807 /* Return an asm sequence to start a noat block and load the address
8808 of a label into $1. */
8811 mips_output_load_label (void)
8813 if (TARGET_EXPLICIT_RELOCS)
8817 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8820 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8823 if (ISA_HAS_LOAD_DELAY)
8824 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8825 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8829 if (Pmode == DImode)
8830 return "%[dla\t%@,%0";
8832 return "%[la\t%@,%0";
8837 /* Output assembly instructions to peform a conditional branch.
8839 INSN is the branch instruction. OPERANDS[0] is the condition.
8840 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8841 of the first operand to the condition. If TWO_OPERANDS_P is
8842 nonzero the comparison takes two operands; OPERANDS[3] will be the
8845 If INVERTED_P is nonzero we are to branch if the condition does
8846 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8848 LENGTH is the length (in bytes) of the sequence we are to generate.
8849 That tells us whether to generate a simple conditional branch, or a
8850 reversed conditional branch around a `jr' instruction. */
8852 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8853 int float_p, int inverted_p, int length)
8855 static char buffer[200];
8856 /* The kind of comparison we are doing. */
8857 enum rtx_code code = GET_CODE (operands[0]);
8858 /* Nonzero if the opcode for the comparison needs a `z' indicating
8859 that it is a comparison against zero. */
8861 /* A string to use in the assembly output to represent the first
8863 const char *op1 = "%z2";
8864 /* A string to use in the assembly output to represent the second
8865 operand. Use the hard-wired zero register if there's no second
8867 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
8868 /* The operand-printing string for the comparison. */
8869 const char *const comp = (float_p ? "%F0" : "%C0");
8870 /* The operand-printing string for the inverted comparison. */
8871 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
8873 /* The MIPS processors (for levels of the ISA at least two), have
8874 "likely" variants of each branch instruction. These instructions
8875 annul the instruction in the delay slot if the branch is not
8877 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8879 if (!two_operands_p)
8881 /* To compute whether than A > B, for example, we normally
8882 subtract B from A and then look at the sign bit. But, if we
8883 are doing an unsigned comparison, and B is zero, we don't
8884 have to do the subtraction. Instead, we can just check to
8885 see if A is nonzero. Thus, we change the CODE here to
8886 reflect the simpler comparison operation. */
8898 /* A condition which will always be true. */
8904 /* A condition which will always be false. */
8910 /* Not a special case. */
8915 /* Relative comparisons are always done against zero. But
8916 equality comparisons are done between two operands, and therefore
8917 do not require a `z' in the assembly language output. */
8918 need_z_p = (!float_p && code != EQ && code != NE);
8919 /* For comparisons against zero, the zero is not provided
8924 /* Begin by terminating the buffer. That way we can always use
8925 strcat to add to it. */
8932 /* Just a simple conditional branch. */
8934 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
8935 inverted_p ? inverted_comp : comp);
8937 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
8938 inverted_p ? inverted_comp : comp,
8939 need_z_p ? "z" : "",
8949 /* Generate a reversed conditional branch around ` j'
8962 If the original branch was a likely branch, the delay slot
8963 must be executed only if the branch is taken, so generate:
8975 When generating non-embedded PIC, instead of:
8988 rtx target = gen_label_rtx ();
8990 orig_target = operands[1];
8991 operands[1] = target;
8992 /* Generate the reversed comparison. This takes four
8995 sprintf (buffer, "%%*b%s\t%%Z2%%1",
8996 inverted_p ? comp : inverted_comp);
8998 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
8999 inverted_p ? comp : inverted_comp,
9000 need_z_p ? "z" : "",
9003 output_asm_insn (buffer, operands);
9005 if (length != 16 && length != 28 && ! mips_branch_likely)
9007 /* Output delay slot instruction. */
9008 rtx insn = final_sequence;
9009 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9011 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9014 output_asm_insn ("%#", 0);
9017 output_asm_insn ("j\t%0", &orig_target);
9020 output_asm_insn (mips_output_load_label (), &orig_target);
9021 output_asm_insn ("jr\t%@%]", 0);
9024 if (length != 16 && length != 28 && mips_branch_likely)
9026 /* Output delay slot instruction. */
9027 rtx insn = final_sequence;
9028 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9030 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9033 output_asm_insn ("%#", 0);
9035 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9036 CODE_LABEL_NUMBER (target));
9049 /* Used to output div or ddiv instruction DIVISION, which has the
9050 operands given by OPERANDS. If we need a divide-by-zero check,
9051 output the instruction and return an asm string that traps if
9052 operand 2 is zero. Otherwise just return DIVISION itself. */
9055 mips_output_division (const char *division, rtx *operands)
9057 if (TARGET_CHECK_ZERO_DIV)
9059 output_asm_insn (division, operands);
9062 return "bnez\t%2,1f\n\tbreak\t7\n1:";
9064 return "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
9069 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9070 with a final "000" replaced by "k". Ignore case.
9072 Note: this function is shared between GCC and GAS. */
9075 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9077 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9078 given++, canonical++;
9080 return ((*given == 0 && *canonical == 0)
9081 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9085 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9086 CPU name. We've traditionally allowed a lot of variation here.
9088 Note: this function is shared between GCC and GAS. */
9091 mips_matching_cpu_name_p (const char *canonical, const char *given)
9093 /* First see if the name matches exactly, or with a final "000"
9095 if (mips_strict_matching_cpu_name_p (canonical, given))
9098 /* If not, try comparing based on numerical designation alone.
9099 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9100 if (TOLOWER (*given) == 'r')
9102 if (!ISDIGIT (*given))
9105 /* Skip over some well-known prefixes in the canonical name,
9106 hoping to find a number there too. */
9107 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9109 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9111 else if (TOLOWER (canonical[0]) == 'r')
9114 return mips_strict_matching_cpu_name_p (canonical, given);
9118 /* Parse an option that takes the name of a processor as its argument.
9119 OPTION is the name of the option and CPU_STRING is the argument.
9120 Return the corresponding processor enumeration if the CPU_STRING is
9121 recognized, otherwise report an error and return null.
9123 A similar function exists in GAS. */
9125 static const struct mips_cpu_info *
9126 mips_parse_cpu (const char *option, const char *cpu_string)
9128 const struct mips_cpu_info *p;
9131 /* In the past, we allowed upper-case CPU names, but it doesn't
9132 work well with the multilib machinery. */
9133 for (s = cpu_string; *s != 0; s++)
9136 warning ("the cpu name must be lower case");
9140 /* 'from-abi' selects the most compatible architecture for the given
9141 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9142 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9143 version. Look first at the -mgp options, if given, otherwise base
9144 the choice on MASK_64BIT in TARGET_DEFAULT. */
9145 if (strcasecmp (cpu_string, "from-abi") == 0)
9146 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9147 : ABI_NEEDS_64BIT_REGS ? 3
9148 : (TARGET_64BIT ? 3 : 1));
9150 /* 'default' has traditionally been a no-op. Probably not very useful. */
9151 if (strcasecmp (cpu_string, "default") == 0)
9154 for (p = mips_cpu_info_table; p->name != 0; p++)
9155 if (mips_matching_cpu_name_p (p->name, cpu_string))
9158 error ("bad value (%s) for %s", cpu_string, option);
9163 /* Return the processor associated with the given ISA level, or null
9164 if the ISA isn't valid. */
9166 static const struct mips_cpu_info *
9167 mips_cpu_info_from_isa (int isa)
9169 const struct mips_cpu_info *p;
9171 for (p = mips_cpu_info_table; p->name != 0; p++)
9178 /* Adjust the cost of INSN based on the relationship between INSN that
9179 is dependent on DEP_INSN through the dependence LINK. The default
9180 is to make no adjustment to COST.
9182 On the MIPS, ignore the cost of anti- and output-dependencies. */
9184 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9185 rtx dep ATTRIBUTE_UNUSED, int cost)
9187 if (REG_NOTE_KIND (link) != 0)
9188 return 0; /* Anti or output dependence. */
9192 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9193 by UNITS_PER_FPREG. All other registers are word sized. */
9196 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9198 if (! FP_REG_P (regno))
9199 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9201 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9204 /* Implement RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9205 all BLKmode objects are returned in memory. Under the new (N32 and
9206 64-bit MIPS ABIs) small structures are returned in a register.
9207 Objects with varying size must still be returned in memory, of
9211 mips_return_in_memory (tree type)
9213 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
9214 return (TYPE_MODE (type) == BLKmode);
9216 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9217 || (int_size_in_bytes (type) == -1));
9221 mips_issue_rate (void)
9225 case PROCESSOR_R5400:
9226 case PROCESSOR_R5500:
9227 case PROCESSOR_R7000:
9228 case PROCESSOR_R9000:
9239 /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
9240 processors that have a DFA pipeline description. */
9243 mips_use_dfa_pipeline_interface (void)
9247 case PROCESSOR_R5400:
9248 case PROCESSOR_R5500:
9249 case PROCESSOR_R7000:
9250 case PROCESSOR_R9000:
9251 case PROCESSOR_SR71000:
9261 mips_emit_prefetch (rtx *operands)
9263 int write = INTVAL (operands[1]);
9264 int locality = INTVAL (operands[2]);
9265 int indexed = GET_CODE (operands[3]) == REG;
9270 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9271 else if (locality <= 2)
9272 code = (write ? 1 : 0); /* store / load. */
9274 code = (write ? 7 : 6); /* store_retained / load_retained. */
9276 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9277 output_asm_insn (buffer, operands);
9284 /* Output assembly to switch to section NAME with attribute FLAGS. */
9287 irix_asm_named_section_1 (const char *name, unsigned int flags,
9290 unsigned int sh_type, sh_flags, sh_entsize;
9293 if (!(flags & SECTION_DEBUG))
9294 sh_flags |= 2; /* SHF_ALLOC */
9295 if (flags & SECTION_WRITE)
9296 sh_flags |= 1; /* SHF_WRITE */
9297 if (flags & SECTION_CODE)
9298 sh_flags |= 4; /* SHF_EXECINSTR */
9299 if (flags & SECTION_SMALL)
9300 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9301 if (strcmp (name, ".debug_frame") == 0)
9302 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9303 if (flags & SECTION_DEBUG)
9304 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9305 else if (flags & SECTION_BSS)
9306 sh_type = 8; /* SHT_NOBITS */
9308 sh_type = 1; /* SHT_PROGBITS */
9310 if (flags & SECTION_CODE)
9315 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9316 name, sh_type, sh_flags, sh_entsize, align);
9320 irix_asm_named_section (const char *name, unsigned int flags)
9322 if (TARGET_SGI_O32_AS)
9323 default_no_named_section (name, flags);
9324 else if (mips_abi == ABI_32 && TARGET_GAS)
9325 default_elf_asm_named_section (name, flags);
9327 irix_asm_named_section_1 (name, flags, 0);
9330 /* In addition to emitting a .align directive, record the maximum
9331 alignment requested for the current section. */
9333 struct GTY (()) irix_section_align_entry
9340 static htab_t irix_section_align_htab;
9341 static FILE *irix_orig_asm_out_file;
9344 irix_section_align_entry_eq (const void *p1, const void *p2)
9346 const struct irix_section_align_entry *old = p1;
9347 const char *new = p2;
9349 return strcmp (old->name, new) == 0;
9353 irix_section_align_entry_hash (const void *p)
9355 const struct irix_section_align_entry *old = p;
9356 return htab_hash_string (old->name);
9360 irix_asm_output_align (FILE *file, unsigned int log)
9362 const char *section = current_section_name ();
9363 struct irix_section_align_entry **slot, *entry;
9365 if (mips_abi != ABI_32)
9370 slot = (struct irix_section_align_entry **)
9371 htab_find_slot_with_hash (irix_section_align_htab, section,
9372 htab_hash_string (section), INSERT);
9376 entry = (struct irix_section_align_entry *)
9377 xmalloc (sizeof (struct irix_section_align_entry));
9379 entry->name = section;
9381 entry->flags = current_section_flags ();
9383 else if (entry->log < log)
9387 fprintf (file, "\t.align\t%u\n", log);
9390 /* The IRIX assembler does not record alignment from .align directives,
9391 but takes it from the first .section directive seen. Play file
9392 switching games so that we can emit a .section directive at the
9393 beginning of the file with the proper alignment attached. */
9396 irix_file_start (void)
9400 if (mips_abi == ABI_32)
9403 irix_orig_asm_out_file = asm_out_file;
9404 asm_out_file = tmpfile ();
9406 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9407 irix_section_align_entry_eq, NULL);
9411 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9413 const struct irix_section_align_entry *entry
9414 = *(const struct irix_section_align_entry **) slot;
9416 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9421 copy_file_data (FILE *to, FILE *from)
9427 fatal_error ("can't rewind temp file: %m");
9429 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9430 if (fwrite (buffer, 1, len, to) != len)
9431 fatal_error ("can't write to output file: %m");
9434 fatal_error ("can't read from temp file: %m");
9437 fatal_error ("can't close temp file: %m");
9441 irix_file_end (void)
9443 if (mips_abi != ABI_32)
9445 /* Emit section directives with the proper alignment at the top of the
9446 real output file. */
9447 FILE *temp = asm_out_file;
9448 asm_out_file = irix_orig_asm_out_file;
9449 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9451 /* Copy the data emitted to the temp file to the real output file. */
9452 copy_file_data (asm_out_file, temp);
9459 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9460 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9464 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9468 flags = default_section_type_flags (decl, section, relocs_p);
9470 if (strcmp (section, ".sdata") == 0
9471 || strcmp (section, ".sbss") == 0
9472 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9473 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9474 flags |= SECTION_SMALL;
9479 #endif /* TARGET_IRIX */
9481 #include "gt-mips.h"