1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
26 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
27 calling convention in 64 bit mode. It doesn't work though, and should
28 be replaced with something better designed. */
35 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "insn-attr.h"
55 #include "target-def.h"
58 #define STAB_CODE_TYPE enum __stab_debug_code
60 #define STAB_CODE_TYPE int
63 extern tree lookup_name PARAMS ((tree));
65 /* Enumeration for all of the relational tests, so that we can build
66 arrays indexed by the test type, and not worry about the order
85 static enum internal_test map_test_to_internal_test PARAMS ((enum rtx_code));
86 static int mips16_simple_memory_operand PARAMS ((rtx, rtx,
88 static int m16_check_op PARAMS ((rtx, int, int, int));
89 static void block_move_loop PARAMS ((rtx, rtx,
93 static void block_move_call PARAMS ((rtx, rtx, rtx));
94 static rtx mips_add_large_offset_to_sp PARAMS ((HOST_WIDE_INT,
96 static void mips_annotate_frame_insn PARAMS ((rtx, rtx));
97 static void mips_emit_frame_related_store PARAMS ((rtx, rtx,
99 static void save_restore_insns PARAMS ((int, rtx,
101 static void mips16_output_gp_offset PARAMS ((FILE *, rtx));
102 static void mips16_fp_args PARAMS ((FILE *, int, int));
103 static void build_mips16_function_stub PARAMS ((FILE *));
104 static void mips16_optimize_gp PARAMS ((rtx));
105 static rtx add_constant PARAMS ((struct constant **,
108 static void dump_constants PARAMS ((struct constant *,
110 static rtx mips_find_symbol PARAMS ((rtx));
111 static void abort_with_insn PARAMS ((rtx, const char *))
113 static int symbolic_expression_p PARAMS ((rtx));
114 static void mips_add_gc_roots PARAMS ((void));
115 static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
116 static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
117 static enum processor_type mips_parse_cpu PARAMS ((const char *));
118 static void copy_file_data PARAMS ((FILE *, FILE *));
120 static void iris6_asm_named_section_1 PARAMS ((const char *,
123 static void iris6_asm_named_section PARAMS ((const char *,
125 static int iris_section_align_entry_eq PARAMS ((const PTR, const PTR));
126 static hashval_t iris_section_align_entry_hash PARAMS ((const PTR));
127 static int iris6_section_align_1 PARAMS ((void **, void *));
129 static int mips_adjust_cost PARAMS ((rtx, rtx, rtx, int));
131 /* Global variables for machine-dependent things. */
133 /* Threshold for data being put into the small data/bss area, instead
134 of the normal data area (references to the small data/bss area take
135 1 instruction, and use the global pointer, references to the normal
136 data area takes 2 instructions). */
137 int mips_section_threshold = -1;
139 /* Count the number of .file directives, so that .loc is up to date. */
140 int num_source_filenames = 0;
142 /* Count the number of sdb related labels are generated (to find block
143 start and end boundaries). */
144 int sdb_label_count = 0;
146 /* Next label # for each statement for Silicon Graphics IRIS systems. */
149 /* Non-zero if inside of a function, because the stupid MIPS asm can't
150 handle .files inside of functions. */
151 int inside_function = 0;
153 /* Files to separate the text and the data output, so that all of the data
154 can be emitted before the text, which will mean that the assembler will
155 generate smaller code, based on the global pointer. */
156 FILE *asm_out_data_file;
157 FILE *asm_out_text_file;
159 /* Linked list of all externals that are to be emitted when optimizing
160 for the global pointer if they haven't been declared by the end of
161 the program with an appropriate .comm or initialization. */
165 struct extern_list *next; /* next external */
166 const char *name; /* name of the external */
167 int size; /* size in bytes */
170 /* Name of the file containing the current function. */
171 const char *current_function_file = "";
173 /* Warning given that Mips ECOFF can't support changing files
174 within a function. */
175 int file_in_function_warning = FALSE;
177 /* Whether to suppress issuing .loc's because the user attempted
178 to change the filename within a function. */
179 int ignore_line_number = FALSE;
181 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
187 /* The next branch instruction is a branch likely, not branch normal. */
188 int mips_branch_likely;
190 /* Count of delay slots and how many are filled. */
191 int dslots_load_total;
192 int dslots_load_filled;
193 int dslots_jump_total;
194 int dslots_jump_filled;
196 /* # of nops needed by previous insn */
197 int dslots_number_nops;
199 /* Number of 1/2/3 word references to data items (ie, not jal's). */
202 /* registers to check for load delay */
203 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
205 /* Cached operands, and operator to compare for use in set/branch/trap
206 on condition codes. */
209 /* what type of branch to use */
210 enum cmp_type branch_type;
212 /* Number of previously seen half-pic pointers and references. */
213 static int prev_half_pic_ptrs = 0;
214 static int prev_half_pic_refs = 0;
216 /* The target cpu for code generation. */
217 enum processor_type mips_arch;
219 /* The target cpu for optimization and scheduling. */
220 enum processor_type mips_tune;
222 /* which instruction set architecture to use. */
225 #ifdef MIPS_ABI_DEFAULT
226 /* Which ABI to use. This is defined to a constant in mips.h if the target
227 doesn't support multiple ABIs. */
231 /* Strings to hold which cpu and instruction set architecture to use. */
232 const char *mips_cpu_string; /* for -mcpu=<xxx> */
233 const char *mips_arch_string; /* for -march=<xxx> */
234 const char *mips_tune_string; /* for -mtune=<xxx> */
235 const char *mips_isa_string; /* for -mips{1,2,3,4} */
236 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
238 /* Whether we are generating mips16 code. This is a synonym for
239 TARGET_MIPS16, and exists for use as an attribute. */
242 /* This variable is set by -mno-mips16. We only care whether
243 -mno-mips16 appears or not, and using a string in this fashion is
244 just a way to avoid using up another bit in target_flags. */
245 const char *mips_no_mips16_string;
247 /* This is only used to determine if an type size setting option was
248 explicitly specified (-mlong64, -mint64, -mlong32). The specs
249 set this option if such an option is used. */
250 const char *mips_explicit_type_size_string;
252 /* Whether we are generating mips16 hard float code. In mips16 mode
253 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
254 -msoft-float was not specified by the user, which means that we
255 should arrange to call mips32 hard floating point code. */
256 int mips16_hard_float;
258 /* This variable is set by -mentry. We only care whether -mentry
259 appears or not, and using a string in this fashion is just a way to
260 avoid using up another bit in target_flags. */
261 const char *mips_entry_string;
263 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
266 /* If TRUE, we split addresses into their high and low parts in the RTL. */
267 int mips_split_addresses;
269 /* Generating calls to position independent functions? */
270 enum mips_abicalls_type mips_abicalls;
272 /* High and low marks for floating point values which we will accept
273 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
274 initialized in override_options. */
275 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
277 /* Mode used for saving/restoring general purpose registers. */
278 static enum machine_mode gpr_mode;
280 /* Array giving truth value on whether or not a given hard register
281 can support a given mode. */
282 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
284 /* Current frame information calculated by compute_frame_size. */
285 struct mips_frame_info current_frame_info;
287 /* Zero structure to initialize current_frame_info. */
288 struct mips_frame_info zero_frame_info;
290 /* Pseudo-reg holding the address of the current function when
291 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
292 by mips_finalize_pic if it was created. */
293 rtx embedded_pic_fnaddr_rtx;
295 /* The length of all strings seen when compiling for the mips16. This
296 is used to tell how many strings are in the constant pool, so that
297 we can see if we may have an overflow. This is reset each time the
298 constant pool is output. */
299 int mips_string_length;
301 /* Pseudo-reg holding the value of $28 in a mips16 function which
302 refers to GP relative global variables. */
303 rtx mips16_gp_pseudo_rtx;
305 /* In mips16 mode, we build a list of all the string constants we see
306 in a particular function. */
308 struct string_constant
310 struct string_constant *next;
314 static struct string_constant *string_constants;
316 /* List of all MIPS punctuation characters used by print_operand. */
317 char mips_print_operand_punct[256];
319 /* Map GCC register number to debugger register number. */
320 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
322 /* Buffer to use to enclose a load/store operation with %{ %} to
323 turn on .set volatile. */
324 static char volatile_buffer[60];
326 /* Hardware names for the registers. If -mrnames is used, this
327 will be overwritten with mips_sw_reg_names. */
329 char mips_reg_names[][8] =
331 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
332 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
333 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
334 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
335 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
336 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
337 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
338 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
339 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
340 "$fcc5","$fcc6","$fcc7","$rap"
343 /* Mips software names for the registers, used to overwrite the
344 mips_reg_names array. */
346 char mips_sw_reg_names[][8] =
348 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
349 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
350 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
351 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
352 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
353 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
354 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
355 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
356 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
357 "$fcc5","$fcc6","$fcc7","$rap"
360 /* Map hard register number to register class */
361 enum reg_class mips_regno_to_class[] =
363 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
364 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
365 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
366 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
367 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
368 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
369 T_REG, GR_REGS, GR_REGS, GR_REGS,
370 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
371 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
372 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
373 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
374 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
375 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
376 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
377 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
378 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
379 HI_REG, LO_REG, HILO_REG, ST_REGS,
380 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
381 ST_REGS, ST_REGS, ST_REGS, GR_REGS
384 /* Map register constraint character to register class. */
385 enum reg_class mips_char_to_class[256] =
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
426 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
427 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
428 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
430 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
431 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
432 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
433 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
434 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
435 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
436 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
437 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
438 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
439 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
440 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
441 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
442 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
443 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
444 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
445 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
446 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
447 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
448 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
449 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
450 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
453 /* Initialize the GCC target structure. */
454 #undef TARGET_ASM_FUNCTION_PROLOGUE
455 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
456 #undef TARGET_ASM_FUNCTION_EPILOGUE
457 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
459 #undef TARGET_SCHED_ADJUST_COST
460 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
462 struct gcc_target targetm = TARGET_INITIALIZER;
464 /* Return truth value of whether OP can be used as an operands
465 where a register or 16 bit unsigned integer is needed. */
468 uns_arith_operand (op, mode)
470 enum machine_mode mode;
472 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
475 return register_operand (op, mode);
478 /* Return truth value of whether OP can be used as an operands
479 where a 16 bit integer is needed */
482 arith_operand (op, mode)
484 enum machine_mode mode;
486 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
489 /* On the mips16, a GP relative value is a signed 16 bit offset. */
490 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
493 return register_operand (op, mode);
496 /* Return truth value of whether OP can be used as an operand in a two
497 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
500 arith32_operand (op, mode)
502 enum machine_mode mode;
504 if (GET_CODE (op) == CONST_INT)
507 return register_operand (op, mode);
510 /* Return truth value of whether OP is a integer which fits in 16 bits */
515 enum machine_mode mode ATTRIBUTE_UNUSED;
517 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
520 /* Return truth value of whether OP is a 32 bit integer which is too big to
521 be loaded with one instruction. */
526 enum machine_mode mode ATTRIBUTE_UNUSED;
530 if (GET_CODE (op) != CONST_INT)
535 /* ior reg,$r0,value */
536 if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
539 /* subu reg,$r0,value */
540 if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
543 /* lui reg,value>>16 */
544 if ((value & 0x0000ffff) == 0)
550 /* Return truth value of whether OP is a register or the constant 0.
551 In mips16 mode, we only accept a register, since the mips16 does
555 reg_or_0_operand (op, mode)
557 enum machine_mode mode;
559 switch (GET_CODE (op))
564 return INTVAL (op) == 0;
569 return op == CONST0_RTX (mode);
573 return register_operand (op, mode);
582 /* Return truth value of whether OP is a register or the constant 0,
583 even in mips16 mode. */
586 true_reg_or_0_operand (op, mode)
588 enum machine_mode mode;
590 switch (GET_CODE (op))
593 return INTVAL (op) == 0;
596 return op == CONST0_RTX (mode);
600 return register_operand (op, mode);
609 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
612 mips_const_double_ok (op, mode)
614 enum machine_mode mode;
618 if (GET_CODE (op) != CONST_DOUBLE)
621 if (mode == VOIDmode)
624 if (mode != SFmode && mode != DFmode)
627 if (op == CONST0_RTX (mode))
630 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
631 if (mips_abi != ABI_32 && mips_abi != ABI_O64 && mips_abi != ABI_EABI)
634 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
636 if (REAL_VALUE_ISNAN (d))
639 if (REAL_VALUE_NEGATIVE (d))
640 d = REAL_VALUE_NEGATE (d);
644 if (REAL_VALUES_LESS (d, dfhigh)
645 && REAL_VALUES_LESS (dflow, d))
650 if (REAL_VALUES_LESS (d, sfhigh)
651 && REAL_VALUES_LESS (sflow, d))
658 /* Accept the floating point constant 1 in the appropriate mode. */
661 const_float_1_operand (op, mode)
663 enum machine_mode mode;
666 static REAL_VALUE_TYPE onedf;
667 static REAL_VALUE_TYPE onesf;
668 static int one_initialized;
670 if (GET_CODE (op) != CONST_DOUBLE
671 || mode != GET_MODE (op)
672 || (mode != DFmode && mode != SFmode))
675 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
677 /* We only initialize these values if we need them, since we will
678 never get called unless mips_isa >= 4. */
679 if (! one_initialized)
681 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
682 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
687 return REAL_VALUES_EQUAL (d, onedf);
689 return REAL_VALUES_EQUAL (d, onesf);
692 /* Return true if a memory load or store of REG plus OFFSET in MODE
693 can be represented in a single word on the mips16. */
696 mips16_simple_memory_operand (reg, offset, mode)
699 enum machine_mode mode;
706 /* We can't tell, because we don't know how the value will
707 eventually be accessed. Returning 0 here does no great
708 harm; it just prevents some possible instruction scheduling. */
712 size = GET_MODE_SIZE (mode);
714 if (INTVAL (offset) % size != 0)
716 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
720 if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))
725 /* Return truth value if a memory operand fits in a single instruction
726 (ie, register + small offset). */
729 simple_memory_operand (op, mode)
731 enum machine_mode mode;
733 rtx addr, plus0, plus1;
735 /* Eliminate non-memory operations */
736 if (GET_CODE (op) != MEM)
739 /* dword operations really put out 2 instructions, so eliminate them. */
740 /* ??? This isn't strictly correct. It is OK to accept multiword modes
741 here, since the length attributes are being set correctly, but only
742 if the address is offsettable. LO_SUM is not offsettable. */
743 if (GET_MODE_SIZE (GET_MODE (op)) > (unsigned) UNITS_PER_WORD)
746 /* Decode the address now. */
748 switch (GET_CODE (addr))
757 return SMALL_INT (addr);
760 plus0 = XEXP (addr, 0);
761 plus1 = XEXP (addr, 1);
762 if (GET_CODE (plus0) == REG
763 && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
765 || mips16_simple_memory_operand (plus0, plus1, mode)))
768 else if (GET_CODE (plus1) == REG
769 && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
771 || mips16_simple_memory_operand (plus1, plus0, mode)))
778 /* We used to allow small symbol refs here (ie, stuff in .sdata
779 or .sbss), but this causes some bugs in G++. Also, it won't
780 interfere if the MIPS linker rewrites the store instruction
781 because the function is PIC. */
783 case LABEL_REF: /* never gp relative */
787 /* If -G 0, we can never have a GP relative memory operation.
788 Also, save some time if not optimizing. */
793 rtx offset = const0_rtx;
794 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
795 if (GET_CODE (op) != SYMBOL_REF)
798 /* let's be paranoid.... */
799 if (! SMALL_INT (offset))
806 return SYMBOL_REF_FLAG (addr);
809 /* This SYMBOL_REF case is for the mips16. If the above case is
810 reenabled, this one should be merged in. */
812 /* References to the constant pool on the mips16 use a small
813 offset if the function is small. The only time we care about
814 getting this right is during delayed branch scheduling, so
815 don't need to check until then. The machine_dependent_reorg
816 function will set the total length of the instructions used
817 in the function in current_frame_info. If that is small
818 enough, we know for sure that this is a small offset. It
819 would be better if we could take into account the location of
820 the instruction within the function, but we can't, because we
821 don't know where we are. */
823 && CONSTANT_POOL_ADDRESS_P (addr)
824 && current_frame_info.insns_len > 0)
828 size = current_frame_info.insns_len + get_pool_size ();
829 if (GET_MODE_SIZE (mode) == 4)
830 return size < 4 * 0x100;
831 else if (GET_MODE_SIZE (mode) == 8)
832 return size < 8 * 0x20;
846 /* Return nonzero for a memory address that can be used to load or store
850 double_memory_operand (op, mode)
852 enum machine_mode mode;
854 if (GET_CODE (op) != MEM
855 || ! memory_operand (op, mode))
857 /* During reload, we accept a pseudo register if it has an
858 appropriate memory address. If we don't do this, we will
859 wind up reloading into a register, and then reloading that
860 register from memory, when we could just reload directly from
862 if (reload_in_progress
863 && GET_CODE (op) == REG
864 && REGNO (op) >= FIRST_PSEUDO_REGISTER
865 && reg_renumber[REGNO (op)] < 0
866 && reg_equiv_mem[REGNO (op)] != 0
867 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
870 /* All reloaded addresses are valid in TARGET_64BIT mode. This is
871 the same test performed for 'm' in find_reloads. */
873 if (reload_in_progress
875 && (GET_CODE (op) == MEM
876 || (GET_CODE (op) == REG
877 && REGNO (op) >= FIRST_PSEUDO_REGISTER
878 && reg_renumber[REGNO (op)] < 0)))
881 if (reload_in_progress
883 && GET_CODE (op) == MEM)
889 /* During reload on the mips16, we accept a large offset
890 from the frame pointer or the stack pointer. This large
891 address will get reloaded anyhow. */
892 if (GET_CODE (addr) == PLUS
893 && GET_CODE (XEXP (addr, 0)) == REG
894 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
895 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
896 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
897 && ! SMALL_INT (XEXP (addr, 1)))
898 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
899 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
902 /* Similarly, we accept a case where the memory address is
903 itself on the stack, and will be reloaded. */
904 if (GET_CODE (addr) == MEM)
908 maddr = XEXP (addr, 0);
909 if (GET_CODE (maddr) == PLUS
910 && GET_CODE (XEXP (maddr, 0)) == REG
911 && (REGNO (XEXP (maddr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
912 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
913 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
914 && ! SMALL_INT (XEXP (maddr, 1)))
915 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
916 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
920 /* We also accept the same case when we have a 16 bit signed
921 offset mixed in as well. The large address will get
922 reloaded, and the 16 bit offset will be OK. */
923 if (GET_CODE (addr) == PLUS
924 && GET_CODE (XEXP (addr, 0)) == MEM
925 && GET_CODE (XEXP (addr, 1)) == CONST_INT
926 && SMALL_INT (XEXP (addr, 1)))
928 addr = XEXP (XEXP (addr, 0), 0);
929 if (GET_CODE (addr) == PLUS
930 && GET_CODE (XEXP (addr, 0)) == REG
931 && (REGNO (XEXP (addr, 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
932 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
933 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
934 && ! SMALL_INT (XEXP (addr, 1)))
935 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
936 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
946 /* In this case we can use an instruction like sd. */
950 /* Make sure that 4 added to the address is a valid memory address.
951 This essentially just checks for overflow in an added constant. */
953 if (CONSTANT_ADDRESS_P (XEXP (op, 0)))
956 op = adjust_address_nv (op, GET_MODE_CLASS (mode) == MODE_INT
957 ? SImode : SFmode, 4);
958 return memory_address_p (GET_MODE (op), XEXP (op, 0));
961 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
964 equality_op (op, mode)
966 enum machine_mode mode;
968 if (mode != GET_MODE (op))
971 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
974 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
979 enum machine_mode mode;
981 if (mode != GET_MODE (op))
984 return GET_RTX_CLASS (GET_CODE (op)) == '<';
987 /* Return nonzero if the code is a relational operation suitable for a
988 conditional trap instructuion (only EQ, NE, LT, LTU, GE, GEU).
989 We need this in the insn that expands `trap_if' in order to prevent
990 combine from erroneously altering the condition. */
993 trap_cmp_op (op, mode)
995 enum machine_mode mode;
997 if (mode != GET_MODE (op))
1000 switch (GET_CODE (op))
1015 /* Return nonzero if the operand is either the PC or a label_ref. */
1018 pc_or_label_operand (op, mode)
1020 enum machine_mode mode ATTRIBUTE_UNUSED;
1025 if (GET_CODE (op) == LABEL_REF)
1031 /* Test for a valid operand for a call instruction.
1032 Don't allow the arg pointer register or virtual regs
1033 since they may change into reg + const, which the patterns
1034 can't handle yet. */
1037 call_insn_operand (op, mode)
1039 enum machine_mode mode ATTRIBUTE_UNUSED;
1041 return (CONSTANT_ADDRESS_P (op)
1042 || (GET_CODE (op) == REG && op != arg_pointer_rtx
1043 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
1044 && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
1047 /* Return nonzero if OPERAND is valid as a source operand for a move
1051 move_operand (op, mode)
1053 enum machine_mode mode;
1055 /* Accept any general operand after reload has started; doing so
1056 avoids losing if reload does an in-place replacement of a register
1057 with a SYMBOL_REF or CONST. */
1058 return (general_operand (op, mode)
1059 && (! (mips_split_addresses && mips_check_split (op, mode))
1060 || reload_in_progress || reload_completed)
1062 && GET_CODE (op) == SYMBOL_REF
1063 && ! mips16_constant (op, mode, 1, 0)));
1066 /* Return nonzero if OPERAND is valid as a source operand for movdi.
1067 This accepts not only general_operand, but also sign extended
1068 constants and registers. We need to accept sign extended constants
1069 in case a sign extended register which is used in an expression,
1070 and is equivalent to a constant, is spilled. */
1073 movdi_operand (op, mode)
1075 enum machine_mode mode;
1079 && GET_CODE (op) == SIGN_EXTEND
1080 && GET_MODE (op) == DImode
1081 && (GET_MODE (XEXP (op, 0)) == SImode
1082 || (GET_CODE (XEXP (op, 0)) == CONST_INT
1083 && GET_MODE (XEXP (op, 0)) == VOIDmode))
1084 && (register_operand (XEXP (op, 0), SImode)
1085 || immediate_operand (XEXP (op, 0), SImode)))
1088 return (general_operand (op, mode)
1090 && GET_CODE (op) == SYMBOL_REF
1091 && ! mips16_constant (op, mode, 1, 0)));
1094 /* Like register_operand, but when in 64 bit mode also accept a sign
1095 extend of a 32 bit register, since the value is known to be already
1099 se_register_operand (op, mode)
1101 enum machine_mode mode;
1105 && GET_CODE (op) == SIGN_EXTEND
1106 && GET_MODE (op) == DImode
1107 && GET_MODE (XEXP (op, 0)) == SImode
1108 && register_operand (XEXP (op, 0), SImode))
1111 return register_operand (op, mode);
1114 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1115 extend of a 32 bit register, since the value is known to be already
1119 se_reg_or_0_operand (op, mode)
1121 enum machine_mode mode;
1125 && GET_CODE (op) == SIGN_EXTEND
1126 && GET_MODE (op) == DImode
1127 && GET_MODE (XEXP (op, 0)) == SImode
1128 && register_operand (XEXP (op, 0), SImode))
1131 return reg_or_0_operand (op, mode);
1134 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1135 extend of a 32 bit register, since the value is known to be already
1139 se_uns_arith_operand (op, mode)
1141 enum machine_mode mode;
1145 && GET_CODE (op) == SIGN_EXTEND
1146 && GET_MODE (op) == DImode
1147 && GET_MODE (XEXP (op, 0)) == SImode
1148 && register_operand (XEXP (op, 0), SImode))
1151 return uns_arith_operand (op, mode);
1154 /* Like arith_operand, but when in 64 bit mode also accept a sign
1155 extend of a 32 bit register, since the value is known to be already
1159 se_arith_operand (op, mode)
1161 enum machine_mode mode;
1165 && GET_CODE (op) == SIGN_EXTEND
1166 && GET_MODE (op) == DImode
1167 && GET_MODE (XEXP (op, 0)) == SImode
1168 && register_operand (XEXP (op, 0), SImode))
1171 return arith_operand (op, mode);
1174 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1175 extend of a 32 bit register, since the value is known to be already
1179 se_nonmemory_operand (op, mode)
1181 enum machine_mode mode;
1185 && GET_CODE (op) == SIGN_EXTEND
1186 && GET_MODE (op) == DImode
1187 && GET_MODE (XEXP (op, 0)) == SImode
1188 && register_operand (XEXP (op, 0), SImode))
1191 return nonmemory_operand (op, mode);
1194 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1195 sign extend of a 32 bit register, since the value is known to be
1196 already sign extended. */
1199 se_nonimmediate_operand (op, mode)
1201 enum machine_mode mode;
1205 && GET_CODE (op) == SIGN_EXTEND
1206 && GET_MODE (op) == DImode
1207 && GET_MODE (XEXP (op, 0)) == SImode
1208 && register_operand (XEXP (op, 0), SImode))
1211 return nonimmediate_operand (op, mode);
1214 /* Accept any operand that can appear in a mips16 constant table
1215 instruction. We can't use any of the standard operand functions
1216 because for these instructions we accept values that are not
1217 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1220 consttable_operand (op, mode)
1222 enum machine_mode mode ATTRIBUTE_UNUSED;
1224 return CONSTANT_P (op);
1227 /* Return nonzero if we split the address into high and low parts. */
1229 /* ??? We should also handle reg+array somewhere. We get four
1230 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1231 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1232 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1233 out of the address, then we have 4 instructions to combine. Perhaps
1234 add a 3->2 define_split for combine. */
1236 /* ??? We could also split a CONST_INT here if it is a large_int().
1237 However, it doesn't seem to be very useful to have %hi(constant).
1238 We would be better off by doing the masking ourselves and then putting
1239 the explicit high part of the constant in the RTL. This will give better
1240 optimization. Also, %hi(constant) needs assembler changes to work.
1241 There is already a define_split that does this. */
1244 mips_check_split (address, mode)
1246 enum machine_mode mode;
1248 /* ??? This is the same check used in simple_memory_operand.
1249 We use it here because LO_SUM is not offsettable. */
1250 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
1253 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1254 || (GET_CODE (address) == CONST
1255 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1256 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1257 || GET_CODE (address) == LABEL_REF)
1263 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1266 mips_reg_mode_ok_for_base_p (reg, mode, strict)
1268 enum machine_mode mode;
1272 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
1273 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
1276 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1277 returns a nonzero value if XINSN is a legitimate address for a
1278 memory operand of the indicated MODE. STRICT is non-zero if this
1279 function is called during reload. */
1282 mips_legitimate_address_p (mode, xinsn, strict)
1283 enum machine_mode mode;
1287 if (TARGET_DEBUG_B_MODE)
1289 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n",
1290 strict ? "" : "not ");
1291 GO_DEBUG_RTX (xinsn);
1294 /* Check for constant before stripping off SUBREG, so that we don't
1295 accept (subreg (const_int)) which will fail to reload. */
1296 if (CONSTANT_ADDRESS_P (xinsn)
1297 && ! (mips_split_addresses && mips_check_split (xinsn, mode))
1298 && (! TARGET_MIPS16 || mips16_constant (xinsn, mode, 1, 0)))
1301 while (GET_CODE (xinsn) == SUBREG)
1302 xinsn = SUBREG_REG (xinsn);
1304 /* The mips16 can only use the stack pointer as a base register when
1305 loading SImode or DImode values. */
1306 if (GET_CODE (xinsn) == REG
1307 && mips_reg_mode_ok_for_base_p (xinsn, mode, strict))
1310 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses)
1312 register rtx xlow0 = XEXP (xinsn, 0);
1313 register rtx xlow1 = XEXP (xinsn, 1);
1315 while (GET_CODE (xlow0) == SUBREG)
1316 xlow0 = SUBREG_REG (xlow0);
1317 if (GET_CODE (xlow0) == REG
1318 && mips_reg_mode_ok_for_base_p (xlow0, mode, strict)
1319 && mips_check_split (xlow1, mode))
1323 if (GET_CODE (xinsn) == PLUS)
1325 register rtx xplus0 = XEXP (xinsn, 0);
1326 register rtx xplus1 = XEXP (xinsn, 1);
1327 register enum rtx_code code0;
1328 register enum rtx_code code1;
1330 while (GET_CODE (xplus0) == SUBREG)
1331 xplus0 = SUBREG_REG (xplus0);
1332 code0 = GET_CODE (xplus0);
1334 while (GET_CODE (xplus1) == SUBREG)
1335 xplus1 = SUBREG_REG (xplus1);
1336 code1 = GET_CODE (xplus1);
1338 /* The mips16 can only use the stack pointer as a base register
1339 when loading SImode or DImode values. */
1341 && mips_reg_mode_ok_for_base_p (xplus0, mode, strict))
1343 if (code1 == CONST_INT && SMALL_INT (xplus1))
1346 /* On the mips16, we represent GP relative offsets in RTL.
1347 These are 16 bit signed values, and can serve as register
1350 && mips16_gp_offset_p (xplus1))
1353 /* For some code sequences, you actually get better code by
1354 pretending that the MIPS supports an address mode of a
1355 constant address + a register, even though the real
1356 machine doesn't support it. This is because the
1357 assembler can use $r1 to load just the high 16 bits, add
1358 in the register, and fold the low 16 bits into the memory
1359 reference, whereas the compiler generates a 4 instruction
1360 sequence. On the other hand, CSE is not as effective.
1361 It would be a win to generate the lui directly, but the
1362 MIPS assembler does not have syntax to generate the
1363 appropriate relocation. */
1365 /* Also accept CONST_INT addresses here, so no else. */
1366 /* Reject combining an embedded PIC text segment reference
1367 with a register. That requires an additional
1369 /* ??? Reject combining an address with a register for the MIPS
1370 64 bit ABI, because the SGI assembler can not handle this. */
1371 if (!TARGET_DEBUG_A_MODE
1372 && (mips_abi == ABI_32
1373 || mips_abi == ABI_O64
1374 || mips_abi == ABI_EABI)
1375 && CONSTANT_ADDRESS_P (xplus1)
1376 && ! mips_split_addresses
1377 && (!TARGET_EMBEDDED_PIC
1379 || GET_CODE (XEXP (xplus1, 0)) != MINUS)
1380 /* When assembling for machines with 64 bit registers,
1381 the assembler will sign-extend the constant "foo"
1382 in "la x, foo(x)" yielding the wrong result for:
1383 (set (blah:DI) (plus x y)). */
1385 || (code1 == CONST_INT
1386 && trunc_int_for_mode (INTVAL (xplus1),
1387 SImode) == INTVAL (xplus1)))
1393 if (TARGET_DEBUG_B_MODE)
1394 GO_PRINTF ("Not a legitimate address\n");
1396 /* The address was not legitimate. */
1401 /* We need a lot of little routines to check constant values on the
1402 mips16. These are used to figure out how long the instruction will
1403 be. It would be much better to do this using constraints, but
1404 there aren't nearly enough letters available. */
1407 m16_check_op (op, low, high, mask)
1413 return (GET_CODE (op) == CONST_INT
1414 && INTVAL (op) >= low
1415 && INTVAL (op) <= high
1416 && (INTVAL (op) & mask) == 0);
1420 m16_uimm3_b (op, mode)
1422 enum machine_mode mode ATTRIBUTE_UNUSED;
1424 return m16_check_op (op, 0x1, 0x8, 0);
1428 m16_simm4_1 (op, mode)
1430 enum machine_mode mode ATTRIBUTE_UNUSED;
1432 return m16_check_op (op, - 0x8, 0x7, 0);
1436 m16_nsimm4_1 (op, mode)
1438 enum machine_mode mode ATTRIBUTE_UNUSED;
1440 return m16_check_op (op, - 0x7, 0x8, 0);
1444 m16_simm5_1 (op, mode)
1446 enum machine_mode mode ATTRIBUTE_UNUSED;
1448 return m16_check_op (op, - 0x10, 0xf, 0);
1452 m16_nsimm5_1 (op, mode)
1454 enum machine_mode mode ATTRIBUTE_UNUSED;
1456 return m16_check_op (op, - 0xf, 0x10, 0);
1460 m16_uimm5_4 (op, mode)
1462 enum machine_mode mode ATTRIBUTE_UNUSED;
1464 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1468 m16_nuimm5_4 (op, mode)
1470 enum machine_mode mode ATTRIBUTE_UNUSED;
1472 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1476 m16_simm8_1 (op, mode)
1478 enum machine_mode mode ATTRIBUTE_UNUSED;
1480 return m16_check_op (op, - 0x80, 0x7f, 0);
1484 m16_nsimm8_1 (op, mode)
1486 enum machine_mode mode ATTRIBUTE_UNUSED;
1488 return m16_check_op (op, - 0x7f, 0x80, 0);
1492 m16_uimm8_1 (op, mode)
1494 enum machine_mode mode ATTRIBUTE_UNUSED;
1496 return m16_check_op (op, 0x0, 0xff, 0);
1500 m16_nuimm8_1 (op, mode)
1502 enum machine_mode mode ATTRIBUTE_UNUSED;
1504 return m16_check_op (op, - 0xff, 0x0, 0);
1508 m16_uimm8_m1_1 (op, mode)
1510 enum machine_mode mode ATTRIBUTE_UNUSED;
1512 return m16_check_op (op, - 0x1, 0xfe, 0);
1516 m16_uimm8_4 (op, mode)
1518 enum machine_mode mode ATTRIBUTE_UNUSED;
1520 return m16_check_op (op, 0x0, 0xff << 2, 3);
1524 m16_nuimm8_4 (op, mode)
1526 enum machine_mode mode ATTRIBUTE_UNUSED;
1528 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1532 m16_simm8_8 (op, mode)
1534 enum machine_mode mode ATTRIBUTE_UNUSED;
1536 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1540 m16_nsimm8_8 (op, mode)
1542 enum machine_mode mode ATTRIBUTE_UNUSED;
1544 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1547 /* References to the string table on the mips16 only use a small
1548 offset if the function is small. See the comment in the SYMBOL_REF
1549 case in simple_memory_operand. We can't check for LABEL_REF here,
1550 because the offset is always large if the label is before the
1551 referencing instruction. */
1554 m16_usym8_4 (op, mode)
1556 enum machine_mode mode ATTRIBUTE_UNUSED;
1558 if (GET_CODE (op) == SYMBOL_REF
1559 && SYMBOL_REF_FLAG (op)
1560 && current_frame_info.insns_len > 0
1561 && XSTR (op, 0)[0] == '*'
1562 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1563 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1564 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1567 struct string_constant *l;
1569 /* Make sure this symbol is on thelist of string constants to be
1570 output for this function. It is possible that it has already
1571 been output, in which case this requires a large offset. */
1572 for (l = string_constants; l != NULL; l = l->next)
1573 if (strcmp (l->label, XSTR (op, 0)) == 0)
1581 m16_usym5_4 (op, mode)
1583 enum machine_mode mode ATTRIBUTE_UNUSED;
1585 if (GET_CODE (op) == SYMBOL_REF
1586 && SYMBOL_REF_FLAG (op)
1587 && current_frame_info.insns_len > 0
1588 && XSTR (op, 0)[0] == '*'
1589 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1590 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1591 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1594 struct string_constant *l;
1596 /* Make sure this symbol is on thelist of string constants to be
1597 output for this function. It is possible that it has already
1598 been output, in which case this requires a large offset. */
1599 for (l = string_constants; l != NULL; l = l->next)
1600 if (strcmp (l->label, XSTR (op, 0)) == 0)
1607 /* Returns an operand string for the given instruction's delay slot,
1608 after updating filled delay slot statistics.
1610 We assume that operands[0] is the target register that is set.
1612 In order to check the next insn, most of this functionality is moved
1613 to FINAL_PRESCAN_INSN, and we just set the global variables that
1616 /* ??? This function no longer does anything useful, because final_prescan_insn
1617 now will never emit a nop. */
1620 mips_fill_delay_slot (ret, type, operands, cur_insn)
1621 const char *ret; /* normal string to return */
1622 enum delay_type type; /* type of delay */
1623 rtx operands[]; /* operands to use */
1624 rtx cur_insn; /* current insn */
1626 register rtx set_reg;
1627 register enum machine_mode mode;
1628 register rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
1629 register int num_nops;
1631 if (type == DELAY_LOAD || type == DELAY_FCMP)
1634 else if (type == DELAY_HILO)
1640 /* Make sure that we don't put nop's after labels. */
1641 next_insn = NEXT_INSN (cur_insn);
1642 while (next_insn != 0 && GET_CODE (next_insn) == NOTE)
1643 next_insn = NEXT_INSN (next_insn);
1645 dslots_load_total += num_nops;
1646 if (TARGET_DEBUG_F_MODE
1648 || type == DELAY_NONE
1652 || GET_CODE (next_insn) == CODE_LABEL
1653 || (set_reg = operands[0]) == 0)
1655 dslots_number_nops = 0;
1663 set_reg = operands[0];
1667 while (GET_CODE (set_reg) == SUBREG)
1668 set_reg = SUBREG_REG (set_reg);
1670 mode = GET_MODE (set_reg);
1671 dslots_number_nops = num_nops;
1672 mips_load_reg = set_reg;
1673 if (GET_MODE_SIZE (mode)
1674 > (unsigned) (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1675 mips_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
1679 if (type == DELAY_HILO)
1681 mips_load_reg3 = gen_rtx_REG (SImode, MD_REG_FIRST);
1682 mips_load_reg4 = gen_rtx_REG (SImode, MD_REG_FIRST+1);
1694 /* Determine whether a memory reference takes one (based off of the GP
1695 pointer), two (normal), or three (label + reg) instructions, and bump the
1696 appropriate counter for -mstats. */
1699 mips_count_memory_refs (op, num)
1705 rtx addr, plus0, plus1;
1706 enum rtx_code code0, code1;
1709 if (TARGET_DEBUG_B_MODE)
1711 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1715 /* Skip MEM if passed, otherwise handle movsi of address. */
1716 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1718 /* Loop, going through the address RTL. */
1722 switch (GET_CODE (addr))
1730 plus0 = XEXP (addr, 0);
1731 plus1 = XEXP (addr, 1);
1732 code0 = GET_CODE (plus0);
1733 code1 = GET_CODE (plus1);
1743 if (code0 == CONST_INT)
1758 if (code1 == CONST_INT)
1765 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1772 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1782 n_words = 2; /* always 2 words */
1786 addr = XEXP (addr, 0);
1791 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1803 n_words += additional;
1807 num_refs[n_words-1] += num;
1811 /* Return RTL for the offset from the current function to the argument.
1813 ??? Which argument is this? */
1816 embedded_pic_offset (x)
1819 if (embedded_pic_fnaddr_rtx == NULL)
1823 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1825 /* Output code at function start to initialize the pseudo-reg. */
1826 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1827 inline functions, because it is called after RTL for the function
1828 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1829 does not get copied, and ends up not matching the rest of the RTL.
1830 This solution works, but means that we get unnecessary code to
1831 initialize this value every time a function is inlined into another
1834 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1835 XEXP (DECL_RTL (current_function_decl), 0)));
1836 seq = gen_sequence ();
1838 push_topmost_sequence ();
1839 emit_insn_after (seq, get_insns ());
1840 pop_topmost_sequence ();
1844 gen_rtx_CONST (Pmode,
1845 gen_rtx_MINUS (Pmode, x,
1846 XEXP (DECL_RTL (current_function_decl), 0)));
1849 /* Return the appropriate instructions to move one operand to another. */
1852 mips_move_1word (operands, insn, unsignedp)
1857 const char *ret = 0;
1858 rtx op0 = operands[0];
1859 rtx op1 = operands[1];
1860 enum rtx_code code0 = GET_CODE (op0);
1861 enum rtx_code code1 = GET_CODE (op1);
1862 enum machine_mode mode = GET_MODE (op0);
1863 int subreg_offset0 = 0;
1864 int subreg_offset1 = 0;
1865 enum delay_type delay = DELAY_NONE;
1867 while (code0 == SUBREG)
1869 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
1870 GET_MODE (SUBREG_REG (op0)),
1873 op0 = SUBREG_REG (op0);
1874 code0 = GET_CODE (op0);
1877 while (code1 == SUBREG)
1879 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
1880 GET_MODE (SUBREG_REG (op1)),
1883 op1 = SUBREG_REG (op1);
1884 code1 = GET_CODE (op1);
1887 /* For our purposes, a condition code mode is the same as SImode. */
1893 int regno0 = REGNO (op0) + subreg_offset0;
1897 int regno1 = REGNO (op1) + subreg_offset1;
1899 /* Just in case, don't do anything for assigning a register
1900 to itself, unless we are filling a delay slot. */
1901 if (regno0 == regno1 && set_nomacro == 0)
1904 else if (GP_REG_P (regno0))
1906 if (GP_REG_P (regno1))
1907 ret = "move\t%0,%1";
1909 else if (MD_REG_P (regno1))
1912 if (regno1 != HILO_REGNUM)
1918 else if (ST_REG_P (regno1) && ISA_HAS_8CC)
1919 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1924 if (FP_REG_P (regno1))
1925 ret = "mfc1\t%0,%1";
1927 else if (regno1 == FPSW_REGNUM && ! ISA_HAS_8CC)
1928 ret = "cfc1\t%0,$31";
1932 else if (FP_REG_P (regno0))
1934 if (GP_REG_P (regno1))
1937 ret = "mtc1\t%1,%0";
1940 if (FP_REG_P (regno1))
1941 ret = "mov.s\t%0,%1";
1944 else if (MD_REG_P (regno0))
1946 if (GP_REG_P (regno1))
1949 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1954 else if (regno0 == FPSW_REGNUM && ! ISA_HAS_8CC)
1956 if (GP_REG_P (regno1))
1959 ret = "ctc1\t%0,$31";
1964 else if (code1 == MEM)
1969 mips_count_memory_refs (op1, 1);
1971 if (GP_REG_P (regno0))
1973 /* For loads, use the mode of the memory item, instead of the
1974 target, so zero/sign extend can use this code as well. */
1975 switch (GET_MODE (op1))
1984 ret = ((unsignedp && TARGET_64BIT)
1989 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1992 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1997 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
2000 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2002 size_t i = strlen (ret);
2003 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2006 sprintf (volatile_buffer, "%%{%s%%}", ret);
2007 ret = volatile_buffer;
2011 else if (code1 == CONST_INT
2012 || (code1 == CONST_DOUBLE
2013 && GET_MODE (op1) == VOIDmode))
2015 if (code1 == CONST_DOUBLE)
2017 /* This can happen when storing constants into long long
2018 bitfields. Just store the least significant word of
2020 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
2023 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
2025 if (GP_REG_P (regno0))
2026 ret = "move\t%0,%z1";
2028 else if (FP_REG_P (regno0))
2031 ret = "mtc1\t%z1,%0";
2034 else if (MD_REG_P (regno0))
2041 else if (GP_REG_P (regno0))
2043 /* Don't use X format, because that will give out of
2044 range numbers for 64 bit host and 32 bit target. */
2045 if (! TARGET_MIPS16)
2046 ret = "li\t%0,%1\t\t\t# %X1";
2049 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2051 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2052 ret = "li\t%0,%n1\n\tneg\t%0";
2057 else if (code1 == CONST_DOUBLE && mode == SFmode)
2059 if (op1 == CONST0_RTX (SFmode))
2061 if (GP_REG_P (regno0))
2062 ret = "move\t%0,%.";
2064 else if (FP_REG_P (regno0))
2067 ret = "mtc1\t%.,%0";
2074 ret = "li.s\t%0,%1";
2078 else if (code1 == LABEL_REF)
2081 mips_count_memory_refs (op1, 1);
2086 else if (code1 == SYMBOL_REF || code1 == CONST)
2088 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
2090 rtx offset = const0_rtx;
2092 if (GET_CODE (op1) == CONST)
2093 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
2095 if (GET_CODE (op1) == SYMBOL_REF)
2097 operands[2] = HALF_PIC_PTR (op1);
2100 mips_count_memory_refs (operands[2], 1);
2102 if (INTVAL (offset) == 0)
2105 ret = (unsignedp && TARGET_64BIT
2111 dslots_load_total++;
2112 operands[3] = offset;
2113 if (unsignedp && TARGET_64BIT)
2114 ret = (SMALL_INT (offset)
2115 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
2116 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2118 ret = (SMALL_INT (offset)
2119 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
2120 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
2124 else if (TARGET_MIPS16
2126 && GET_CODE (XEXP (op1, 0)) == REG
2127 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2129 /* This case arises on the mips16; see
2130 mips16_gp_pseudo_reg. */
2131 ret = "move\t%0,%+";
2133 else if (TARGET_MIPS16
2134 && code1 == SYMBOL_REF
2135 && SYMBOL_REF_FLAG (op1)
2136 && (XSTR (op1, 0)[0] != '*'
2137 || strncmp (XSTR (op1, 0) + 1,
2139 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2141 /* This can occur when reloading the address of a GP
2142 relative symbol on the mips16. */
2143 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2148 mips_count_memory_refs (op1, 1);
2154 else if (code1 == PLUS)
2156 rtx add_op0 = XEXP (op1, 0);
2157 rtx add_op1 = XEXP (op1, 1);
2159 if (GET_CODE (XEXP (op1, 1)) == REG
2160 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
2161 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
2163 operands[2] = add_op0;
2164 operands[3] = add_op1;
2165 ret = "add%:\t%0,%2,%3";
2168 else if (code1 == HIGH)
2170 operands[1] = XEXP (op1, 0);
2171 ret = "lui\t%0,%%hi(%1)";
2175 else if (code0 == MEM)
2178 mips_count_memory_refs (op0, 1);
2182 int regno1 = REGNO (op1) + subreg_offset1;
2184 if (GP_REG_P (regno1))
2188 case SFmode: ret = "sw\t%1,%0"; break;
2189 case SImode: ret = "sw\t%1,%0"; break;
2190 case HImode: ret = "sh\t%1,%0"; break;
2191 case QImode: ret = "sb\t%1,%0"; break;
2196 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
2200 else if (code1 == CONST_INT && INTVAL (op1) == 0)
2204 case SFmode: ret = "sw\t%z1,%0"; break;
2205 case SImode: ret = "sw\t%z1,%0"; break;
2206 case HImode: ret = "sh\t%z1,%0"; break;
2207 case QImode: ret = "sb\t%z1,%0"; break;
2212 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
2216 case SFmode: ret = "sw\t%.,%0"; break;
2217 case SImode: ret = "sw\t%.,%0"; break;
2218 case HImode: ret = "sh\t%.,%0"; break;
2219 case QImode: ret = "sb\t%.,%0"; break;
2224 if (ret != 0 && MEM_VOLATILE_P (op0))
2226 size_t i = strlen (ret);
2228 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2231 sprintf (volatile_buffer, "%%{%s%%}", ret);
2232 ret = volatile_buffer;
2238 abort_with_insn (insn, "Bad move");
2242 if (delay != DELAY_NONE)
2243 return mips_fill_delay_slot (ret, delay, operands, insn);
2249 /* Return the appropriate instructions to move 2 words */
2252 mips_move_2words (operands, insn)
2256 const char *ret = 0;
2257 rtx op0 = operands[0];
2258 rtx op1 = operands[1];
2259 enum rtx_code code0 = GET_CODE (operands[0]);
2260 enum rtx_code code1 = GET_CODE (operands[1]);
2261 int subreg_offset0 = 0;
2262 int subreg_offset1 = 0;
2263 enum delay_type delay = DELAY_NONE;
2265 while (code0 == SUBREG)
2267 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
2268 GET_MODE (SUBREG_REG (op0)),
2271 op0 = SUBREG_REG (op0);
2272 code0 = GET_CODE (op0);
2275 if (code1 == SIGN_EXTEND)
2277 op1 = XEXP (op1, 0);
2278 code1 = GET_CODE (op1);
2281 while (code1 == SUBREG)
2283 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
2284 GET_MODE (SUBREG_REG (op1)),
2287 op1 = SUBREG_REG (op1);
2288 code1 = GET_CODE (op1);
2292 if (GET_CODE (operands[1]) == SIGN_EXTEND
2294 && code1 != CONST_INT
2295 /* The following three can happen as the result of a questionable
2297 && code1 != LABEL_REF
2298 && code1 != SYMBOL_REF
2304 int regno0 = REGNO (op0) + subreg_offset0;
2308 int regno1 = REGNO (op1) + subreg_offset1;
2310 /* Just in case, don't do anything for assigning a register
2311 to itself, unless we are filling a delay slot. */
2312 if (regno0 == regno1 && set_nomacro == 0)
2315 else if (FP_REG_P (regno0))
2317 if (FP_REG_P (regno1))
2318 ret = "mov.d\t%0,%1";
2326 abort_with_insn (insn, "Bad move");
2328 #ifdef TARGET_FP_CALL_32
2329 if (FP_CALL_GP_REG_P (regno1))
2330 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2333 ret = "dmtc1\t%1,%0";
2336 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2340 else if (FP_REG_P (regno1))
2346 abort_with_insn (insn, "Bad move");
2348 #ifdef TARGET_FP_CALL_32
2349 if (FP_CALL_GP_REG_P (regno0))
2350 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2353 ret = "dmfc1\t%0,%1";
2356 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2359 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2364 if (regno0 != HILO_REGNUM)
2366 else if (regno1 == 0)
2367 ret = "mtlo\t%.\n\tmthi\t%.";
2370 ret = "mthi\t%M1\n\tmtlo\t%L1";
2373 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2378 if (regno1 != HILO_REGNUM)
2382 ret = "mfhi\t%M0\n\tmflo\t%L0";
2385 else if (TARGET_64BIT)
2386 ret = "move\t%0,%1";
2388 else if (regno0 != (regno1+1))
2389 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2392 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2395 else if (code1 == CONST_DOUBLE)
2397 /* Move zero from $0 unless !TARGET_64BIT and recipient
2398 is 64-bit fp reg, in which case generate a constant. */
2399 if (op1 != CONST0_RTX (GET_MODE (op1))
2400 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2402 if (GET_MODE (op1) == DFmode)
2406 #ifdef TARGET_FP_CALL_32
2407 if (FP_CALL_GP_REG_P (regno0))
2409 if (TARGET_FLOAT64 && !TARGET_64BIT)
2411 split_double (op1, operands + 2, operands + 3);
2412 ret = "li\t%0,%2\n\tli\t%D0,%3";
2415 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2419 /* GNU as emits 64-bit code for li.d if the ISA is 3
2420 or higher. For !TARGET_64BIT && gp registers we
2421 need to avoid this by using two li instructions
2423 if (ISA_HAS_64BIT_REGS
2425 && ! FP_REG_P (regno0))
2427 split_double (op1, operands + 2, operands + 3);
2428 ret = "li\t%0,%2\n\tli\t%D0,%3";
2431 ret = "li.d\t%0,%1";
2434 else if (TARGET_64BIT)
2436 if (! TARGET_MIPS16)
2442 split_double (op1, operands + 2, operands + 3);
2443 ret = "li\t%0,%2\n\tli\t%D0,%3";
2449 if (GP_REG_P (regno0))
2451 #ifdef TARGET_FP_CALL_32
2452 && ! FP_CALL_GP_REG_P (regno0)
2455 : "move\t%0,%.\n\tmove\t%D0,%.");
2457 else if (FP_REG_P (regno0))
2462 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2467 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2469 if (GP_REG_P (regno0))
2472 : "move\t%0,%.\n\tmove\t%D0,%.");
2474 else if (FP_REG_P (regno0))
2481 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
2483 else if (MD_REG_P (regno0))
2486 ret = (regno0 == HILO_REGNUM
2487 ? "mtlo\t%.\n\tmthi\t%."
2492 else if (code1 == CONST_INT && GET_MODE (op0) == DImode
2493 && GP_REG_P (regno0))
2499 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2501 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2502 ret = "li\t%0,%n1\n\tneg\t%0";
2504 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2505 ret = "li\t%0,%1\t\t# %X1";
2506 else if (HOST_BITS_PER_WIDE_INT < 64)
2507 /* We can't use 'X' for negative numbers, because then we won't
2508 get the right value for the upper 32 bits. */
2509 ret = (INTVAL (op1) < 0
2510 ? "dli\t%0,%1\t\t\t# %X1"
2511 : "dli\t%0,%X1\t\t# %1");
2513 /* We must use 'X', because otherwise LONG_MIN will print as
2514 a number that the assembler won't accept. */
2515 ret = "dli\t%0,%X1\t\t# %1";
2517 else if (HOST_BITS_PER_WIDE_INT < 64)
2519 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2522 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2523 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2524 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2526 operands[2] = GEN_INT (1);
2527 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2531 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2535 /* We use multiple shifts here, to avoid warnings about out
2536 of range shifts on 32 bit hosts. */
2537 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2539 = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2540 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2544 else if (code1 == MEM)
2549 mips_count_memory_refs (op1, 2);
2551 if (FP_REG_P (regno0))
2554 else if (TARGET_64BIT)
2557 #ifdef TARGET_FP_CALL_32
2558 if (FP_CALL_GP_REG_P (regno0))
2559 ret = (double_memory_operand (op1, GET_MODE (op1))
2560 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
2561 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32");
2567 else if (double_memory_operand (op1, GET_MODE (op1)))
2568 ret = (reg_mentioned_p (op0, op1)
2569 ? "lw\t%D0,%D1\n\tlw\t%0,%1"
2570 : "lw\t%0,%1\n\tlw\t%D0,%D1");
2572 if (ret != 0 && MEM_VOLATILE_P (op1))
2574 size_t i = strlen (ret);
2576 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2579 sprintf (volatile_buffer, "%%{%s%%}", ret);
2580 ret = volatile_buffer;
2584 else if (code1 == LABEL_REF)
2587 mips_count_memory_refs (op1, 2);
2589 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2590 /* We deliberately remove the 'a' from '%1', so that we don't
2591 have to add SIGN_EXTEND support to print_operand_address.
2592 print_operand will just call print_operand_address in this
2593 case, so there is no problem. */
2596 ret = "dla\t%0,%a1";
2598 else if (code1 == SYMBOL_REF || code1 == CONST)
2602 && GET_CODE (XEXP (op1, 0)) == REG
2603 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2605 /* This case arises on the mips16; see
2606 mips16_gp_pseudo_reg. */
2607 ret = "move\t%0,%+";
2609 else if (TARGET_MIPS16
2610 && code1 == SYMBOL_REF
2611 && SYMBOL_REF_FLAG (op1)
2612 && (XSTR (op1, 0)[0] != '*'
2613 || strncmp (XSTR (op1, 0) + 1,
2615 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2617 /* This can occur when reloading the address of a GP
2618 relative symbol on the mips16. */
2619 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2624 mips_count_memory_refs (op1, 2);
2626 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2627 /* We deliberately remove the 'a' from '%1', so that we don't
2628 have to add SIGN_EXTEND support to print_operand_address.
2629 print_operand will just call print_operand_address in this
2630 case, so there is no problem. */
2633 ret = "dla\t%0,%a1";
2638 else if (code0 == MEM)
2642 int regno1 = REGNO (op1) + subreg_offset1;
2644 if (FP_REG_P (regno1))
2647 else if (TARGET_64BIT)
2650 #ifdef TARGET_FP_CALL_32
2651 if (FP_CALL_GP_REG_P (regno1))
2652 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2658 else if (double_memory_operand (op0, GET_MODE (op0)))
2659 ret = "sw\t%1,%0\n\tsw\t%D1,%D0";
2662 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2663 || (code1 == CONST_DOUBLE
2664 && op1 == CONST0_RTX (GET_MODE (op1))))
2666 || double_memory_operand (op0, GET_MODE (op0))))
2671 ret = "sw\t%.,%0\n\tsw\t%.,%D0";
2675 mips_count_memory_refs (op0, 2);
2677 if (ret != 0 && MEM_VOLATILE_P (op0))
2679 size_t i = strlen (ret);
2681 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2684 sprintf (volatile_buffer, "%%{%s%%}", ret);
2685 ret = volatile_buffer;
2691 abort_with_insn (insn, "Bad move");
2695 if (delay != DELAY_NONE)
2696 return mips_fill_delay_slot (ret, delay, operands, insn);
2701 /* Provide the costs of an addressing mode that contains ADDR.
2702 If ADDR is not a valid address, its cost is irrelevant. */
2705 mips_address_cost (addr)
2708 switch (GET_CODE (addr))
2718 rtx offset = const0_rtx;
2719 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2720 if (GET_CODE (addr) == LABEL_REF)
2723 if (GET_CODE (addr) != SYMBOL_REF)
2726 if (! SMALL_INT (offset))
2730 /* ... fall through ... */
2733 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2737 register rtx plus0 = XEXP (addr, 0);
2738 register rtx plus1 = XEXP (addr, 1);
2740 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2741 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
2743 if (GET_CODE (plus0) != REG)
2746 switch (GET_CODE (plus1))
2749 return SMALL_INT (plus1) ? 1 : 2;
2756 return mips_address_cost (plus1) + 1;
2770 /* Return nonzero if X is an address which needs a temporary register when
2771 reloaded while generating PIC code. */
2774 pic_address_needs_scratch (x)
2777 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2778 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2779 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2780 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2781 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2787 /* Make normal rtx_code into something we can index from an array */
2789 static enum internal_test
2790 map_test_to_internal_test (test_code)
2791 enum rtx_code test_code;
2793 enum internal_test test = ITEST_MAX;
2797 case EQ: test = ITEST_EQ; break;
2798 case NE: test = ITEST_NE; break;
2799 case GT: test = ITEST_GT; break;
2800 case GE: test = ITEST_GE; break;
2801 case LT: test = ITEST_LT; break;
2802 case LE: test = ITEST_LE; break;
2803 case GTU: test = ITEST_GTU; break;
2804 case GEU: test = ITEST_GEU; break;
2805 case LTU: test = ITEST_LTU; break;
2806 case LEU: test = ITEST_LEU; break;
2814 /* Generate the code to compare two integer values. The return value is:
2815 (reg:SI xx) The pseudo register the comparison is in
2816 0 No register, generate a simple branch.
2818 ??? This is called with result nonzero by the Scond patterns in
2819 mips.md. These patterns are called with a target in the mode of
2820 the Scond instruction pattern. Since this must be a constant, we
2821 must use SImode. This means that if RESULT is non-zero, it will
2822 always be an SImode register, even if TARGET_64BIT is true. We
2823 cope with this by calling convert_move rather than emit_move_insn.
2824 This will sometimes lead to an unnecessary extension of the result;
2836 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2837 enum rtx_code test_code; /* relational test (EQ, etc) */
2838 rtx result; /* result to store comp. or 0 if branch */
2839 rtx cmp0; /* first operand to compare */
2840 rtx cmp1; /* second operand to compare */
2841 int *p_invert; /* NULL or ptr to hold whether branch needs */
2842 /* to reverse its test */
2846 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2847 int const_low; /* low bound of constant we can accept */
2848 int const_high; /* high bound of constant we can accept */
2849 int const_add; /* constant to add (convert LE -> LT) */
2850 int reverse_regs; /* reverse registers in test */
2851 int invert_const; /* != 0 if invert value if cmp1 is constant */
2852 int invert_reg; /* != 0 if invert value if cmp1 is register */
2853 int unsignedp; /* != 0 for unsigned comparisons. */
2856 static struct cmp_info info[ (int)ITEST_MAX ] = {
2858 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2859 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2860 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2861 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2862 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2863 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2864 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2865 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2866 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2867 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2870 enum internal_test test;
2871 enum machine_mode mode;
2872 struct cmp_info *p_info;
2879 test = map_test_to_internal_test (test_code);
2880 if (test == ITEST_MAX)
2883 p_info = &info[(int) test];
2884 eqne_p = (p_info->test_code == XOR);
2886 mode = GET_MODE (cmp0);
2887 if (mode == VOIDmode)
2888 mode = GET_MODE (cmp1);
2890 /* Eliminate simple branches */
2891 branch_p = (result == 0);
2894 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2896 /* Comparisons against zero are simple branches */
2897 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2898 && (! TARGET_MIPS16 || eqne_p))
2901 /* Test for beq/bne. */
2902 if (eqne_p && ! TARGET_MIPS16)
2906 /* allocate a pseudo to calculate the value in. */
2907 result = gen_reg_rtx (mode);
2910 /* Make sure we can handle any constants given to us. */
2911 if (GET_CODE (cmp0) == CONST_INT)
2912 cmp0 = force_reg (mode, cmp0);
2914 if (GET_CODE (cmp1) == CONST_INT)
2916 HOST_WIDE_INT value = INTVAL (cmp1);
2918 if (value < p_info->const_low
2919 || value > p_info->const_high
2920 /* ??? Why? And why wasn't the similar code below modified too? */
2922 && HOST_BITS_PER_WIDE_INT < 64
2923 && p_info->const_add != 0
2924 && ((p_info->unsignedp
2925 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2926 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2927 : (value + p_info->const_add) > INTVAL (cmp1))
2928 != (p_info->const_add > 0))))
2929 cmp1 = force_reg (mode, cmp1);
2932 /* See if we need to invert the result. */
2933 invert = (GET_CODE (cmp1) == CONST_INT
2934 ? p_info->invert_const : p_info->invert_reg);
2936 if (p_invert != (int *)0)
2942 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2943 Comparison between two registers, may involve switching operands. */
2944 if (GET_CODE (cmp1) == CONST_INT)
2946 if (p_info->const_add != 0)
2948 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2950 /* If modification of cmp1 caused overflow,
2951 we would get the wrong answer if we follow the usual path;
2952 thus, x > 0xffffffffU would turn into x > 0U. */
2953 if ((p_info->unsignedp
2954 ? (unsigned HOST_WIDE_INT) new >
2955 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2956 : new > INTVAL (cmp1))
2957 != (p_info->const_add > 0))
2959 /* This test is always true, but if INVERT is true then
2960 the result of the test needs to be inverted so 0 should
2961 be returned instead. */
2962 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2966 cmp1 = GEN_INT (new);
2970 else if (p_info->reverse_regs)
2977 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2981 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2982 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2985 if (test == ITEST_NE)
2987 if (! TARGET_MIPS16)
2989 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2990 if (p_invert != NULL)
2996 reg2 = invert ? gen_reg_rtx (mode) : result;
2997 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
3002 else if (test == ITEST_EQ)
3004 reg2 = invert ? gen_reg_rtx (mode) : result;
3005 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
3013 if (! TARGET_MIPS16)
3017 /* The value is in $24. Copy it to another register, so
3018 that reload doesn't think it needs to store the $24 and
3019 the input to the XOR in the same location. */
3020 reg2 = gen_reg_rtx (mode);
3021 emit_move_insn (reg2, reg);
3023 one = force_reg (mode, const1_rtx);
3025 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
3031 /* Emit the common code for doing conditional branches.
3032 operand[0] is the label to jump to.
3033 The comparison operands are saved away by cmp{si,di,sf,df}. */
3036 gen_conditional_branch (operands, test_code)
3038 enum rtx_code test_code;
3040 enum cmp_type type = branch_type;
3041 rtx cmp0 = branch_cmp[0];
3042 rtx cmp1 = branch_cmp[1];
3043 enum machine_mode mode;
3052 mode = type == CMP_SI ? SImode : DImode;
3054 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
3062 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
3063 /* We don't want to build a comparison against a non-zero
3065 cmp1 = force_reg (mode, cmp1);
3072 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
3074 reg = gen_reg_rtx (CCmode);
3076 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
3077 0 in the instruction built below. The MIPS FPU handles
3078 inequality testing by testing for equality and looking for a
3080 emit_insn (gen_rtx_SET (VOIDmode, reg,
3081 gen_rtx (test_code == NE ? EQ : test_code,
3082 CCmode, cmp0, cmp1)));
3084 test_code = test_code == NE ? EQ : NE;
3092 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
3095 /* Generate the branch. */
3097 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3106 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3107 gen_rtx_IF_THEN_ELSE (VOIDmode,
3108 gen_rtx (test_code, mode,
3113 /* Emit the common code for conditional moves. OPERANDS is the array
3114 of operands passed to the conditional move defined_expand. */
3117 gen_conditional_move (operands)
3120 rtx op0 = branch_cmp[0];
3121 rtx op1 = branch_cmp[1];
3122 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3123 enum rtx_code cmp_code = GET_CODE (operands[1]);
3124 enum rtx_code move_code = NE;
3125 enum machine_mode op_mode = GET_MODE (operands[0]);
3126 enum machine_mode cmp_mode;
3129 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3148 op0 = force_reg (mode, branch_cmp[1]);
3149 op1 = branch_cmp[0];
3153 op0 = force_reg (mode, branch_cmp[1]);
3154 op1 = branch_cmp[0];
3165 op0 = force_reg (mode, branch_cmp[1]);
3166 op1 = branch_cmp[0];
3170 op0 = force_reg (mode, branch_cmp[1]);
3171 op1 = branch_cmp[0];
3178 else if (cmp_code == NE)
3179 cmp_code = EQ, move_code = EQ;
3181 if (mode == SImode || mode == DImode)
3183 else if (mode == SFmode || mode == DFmode)
3188 cmp_reg = gen_reg_rtx (cmp_mode);
3189 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3190 gen_rtx (cmp_code, cmp_mode, op0, op1)));
3192 emit_insn (gen_rtx_SET (op_mode, operands[0],
3193 gen_rtx_IF_THEN_ELSE (op_mode,
3194 gen_rtx (move_code, VOIDmode,
3196 CONST0_RTX (SImode)),
3197 operands[2], operands[3])));
3200 /* Emit the common code for conditional moves. OPERANDS is the array
3201 of operands passed to the conditional move defined_expand. */
3204 mips_gen_conditional_trap (operands)
3208 enum rtx_code cmp_code = GET_CODE (operands[0]);
3209 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3211 /* MIPS conditional trap machine instructions don't have GT or LE
3212 flavors, so we must invert the comparison and convert to LT and
3213 GE, respectively. */
3216 case GT: cmp_code = LT; break;
3217 case LE: cmp_code = GE; break;
3218 case GTU: cmp_code = LTU; break;
3219 case LEU: cmp_code = GEU; break;
3222 if (cmp_code == GET_CODE (operands[0]))
3224 op0 = force_reg (mode, branch_cmp[0]);
3225 op1 = branch_cmp[1];
3229 op0 = force_reg (mode, branch_cmp[1]);
3230 op1 = branch_cmp[0];
3232 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3233 op1 = force_reg (mode, op1);
3235 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3236 gen_rtx (cmp_code, GET_MODE (operands[0]), op0, op1),
3240 /* Write a loop to move a constant number of bytes.
3241 Generate load/stores as follows:
3247 temp<last> = src[MAX_MOVE_REGS-1];
3251 dest[MAX_MOVE_REGS-1] = temp<last>;
3252 src += MAX_MOVE_REGS;
3253 dest += MAX_MOVE_REGS;
3254 } while (src != final);
3256 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
3257 registers are needed.
3259 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
3260 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
3261 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
3263 #define MAX_MOVE_REGS 4
3264 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3267 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
3268 rtx dest_reg; /* register holding destination address */
3269 rtx src_reg; /* register holding source address */
3270 unsigned int bytes; /* # bytes to move */
3271 int align; /* alignment */
3272 rtx orig_dest; /* original dest */
3273 rtx orig_src; /* original source for making a reg note */
3275 rtx dest_mem = replace_equiv_address (orig_dest, dest_reg);
3276 rtx src_mem = replace_equiv_address (orig_src, src_reg);
3277 rtx align_rtx = GEN_INT (align);
3283 if (bytes < (unsigned)2 * MAX_MOVE_BYTES)
3286 leftover = bytes % MAX_MOVE_BYTES;
3289 label = gen_label_rtx ();
3290 final_src = gen_reg_rtx (Pmode);
3291 bytes_rtx = GEN_INT (bytes);
3295 if (Pmode == DImode)
3297 emit_insn (gen_movdi (final_src, bytes_rtx));
3298 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3302 emit_insn (gen_movsi (final_src, bytes_rtx));
3303 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3308 if (Pmode == DImode)
3309 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3311 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3316 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3317 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3319 if (Pmode == DImode)
3321 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3322 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3323 emit_insn (gen_cmpdi (src_reg, final_src));
3327 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3328 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3329 emit_insn (gen_cmpsi (src_reg, final_src));
3332 emit_jump_insn (gen_bne (label));
3335 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, GEN_INT (leftover),
3339 /* Use a library function to move some bytes. */
3342 block_move_call (dest_reg, src_reg, bytes_rtx)
3347 /* We want to pass the size as Pmode, which will normally be SImode
3348 but will be DImode if we are using 64 bit longs and pointers. */
3349 if (GET_MODE (bytes_rtx) != VOIDmode
3350 && GET_MODE (bytes_rtx) != (unsigned) Pmode)
3351 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
3353 #ifdef TARGET_MEM_FUNCTIONS
3354 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "memcpy"), 0,
3355 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
3356 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3357 TREE_UNSIGNED (sizetype)),
3358 TYPE_MODE (sizetype));
3360 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "bcopy"), 0,
3361 VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
3362 convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
3363 TREE_UNSIGNED (integer_type_node)),
3364 TYPE_MODE (integer_type_node));
3368 /* Expand string/block move operations.
3370 operands[0] is the pointer to the destination.
3371 operands[1] is the pointer to the source.
3372 operands[2] is the number of bytes to move.
3373 operands[3] is the alignment. */
3376 expand_block_move (operands)
3379 rtx bytes_rtx = operands[2];
3380 rtx align_rtx = operands[3];
3381 int constp = GET_CODE (bytes_rtx) == CONST_INT;
3382 unsigned HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
3383 unsigned int align = INTVAL (align_rtx);
3384 rtx orig_src = operands[1];
3385 rtx orig_dest = operands[0];
3389 if (constp && bytes == 0)
3392 if (align > (unsigned) UNITS_PER_WORD)
3393 align = UNITS_PER_WORD;
3395 /* Move the address into scratch registers. */
3396 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3397 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3400 block_move_call (dest_reg, src_reg, bytes_rtx);
3402 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES
3403 && align == (unsigned) UNITS_PER_WORD)
3404 move_by_pieces (orig_dest, orig_src, bytes, align * BITS_PER_WORD);
3406 else if (constp && bytes <= (unsigned)2 * MAX_MOVE_BYTES)
3407 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3409 replace_equiv_address (orig_src,
3411 bytes_rtx, align_rtx));
3413 else if (constp && align >= (unsigned) UNITS_PER_WORD && optimize)
3414 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3416 else if (constp && optimize)
3418 /* If the alignment is not word aligned, generate a test at
3419 runtime, to see whether things wound up aligned, and we
3420 can use the faster lw/sw instead ulw/usw. */
3422 rtx temp = gen_reg_rtx (Pmode);
3423 rtx aligned_label = gen_label_rtx ();
3424 rtx join_label = gen_label_rtx ();
3425 int leftover = bytes % MAX_MOVE_BYTES;
3429 if (Pmode == DImode)
3431 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3432 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3433 emit_insn (gen_cmpdi (temp, const0_rtx));
3437 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3438 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD - 1)));
3439 emit_insn (gen_cmpsi (temp, const0_rtx));
3442 emit_jump_insn (gen_beq (aligned_label));
3444 /* Unaligned loop. */
3445 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3446 emit_jump_insn (gen_jump (join_label));
3450 emit_label (aligned_label);
3451 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3453 emit_label (join_label);
3455 /* Bytes at the end of the loop. */
3457 emit_insn (gen_movstrsi_internal (replace_equiv_address (orig_dest,
3459 replace_equiv_address (orig_src,
3466 block_move_call (dest_reg, src_reg, bytes_rtx);
3469 /* Emit load/stores for a small constant block_move.
3471 operands[0] is the memory address of the destination.
3472 operands[1] is the memory address of the source.
3473 operands[2] is the number of bytes to move.
3474 operands[3] is the alignment.
3475 operands[4] is a temp register.
3476 operands[5] is a temp register.
3478 operands[3+num_regs] is the last temp register.
3480 The block move type can be one of the following:
3481 BLOCK_MOVE_NORMAL Do all of the block move.
3482 BLOCK_MOVE_NOT_LAST Do all but the last store.
3483 BLOCK_MOVE_LAST Do just the last store. */
3486 output_block_move (insn, operands, num_regs, move_type)
3490 enum block_move_type move_type;
3492 rtx dest_reg = XEXP (operands[0], 0);
3493 rtx src_reg = XEXP (operands[1], 0);
3494 HOST_WIDE_INT bytes = INTVAL (operands[2]);
3495 int align = INTVAL (operands[3]);
3498 int use_lwl_lwr = 0;
3499 int last_operand = num_regs + 4;
3505 const char *load; /* load insn without nop */
3506 const char *load_nop; /* load insn with trailing nop */
3507 const char *store; /* store insn */
3508 const char *final; /* if last_store used: NULL or swr */
3509 const char *last_store; /* last store instruction */
3510 int offset; /* current offset */
3511 enum machine_mode mode; /* mode to use on (MEM) */
3514 /* ??? Detect a bug in GCC, where it can give us a register
3515 the same as one of the addressing registers and reduce
3516 the number of registers available. */
3517 for (i = 4; i < last_operand && safe_regs < (int) ARRAY_SIZE (xoperands); i++)
3518 if (! reg_mentioned_p (operands[i], operands[0])
3519 && ! reg_mentioned_p (operands[i], operands[1]))
3520 xoperands[safe_regs++] = operands[i];
3522 if (safe_regs < last_operand)
3524 xoperands[0] = operands[0];
3525 xoperands[1] = operands[1];
3526 xoperands[2] = operands[2];
3527 xoperands[3] = operands[3];
3528 return output_block_move (insn, xoperands, safe_regs - 4, move_type);
3531 /* If we are given global or static addresses, and we would be
3532 emitting a few instructions, try to save time by using a
3533 temporary register for the pointer. */
3534 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3535 an ldl/ldr instruction pair. We play it safe, and always move
3536 constant addresses into registers when generating N32/N64 code, just
3537 in case we might emit an unaligned load instruction. */
3538 if (num_regs > 2 && (bytes > 2 * align || move_type != BLOCK_MOVE_NORMAL
3539 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3541 if (CONSTANT_P (src_reg))
3544 mips_count_memory_refs (operands[1], 1);
3546 src_reg = operands[3 + num_regs--];
3547 if (move_type != BLOCK_MOVE_LAST)
3549 xoperands[1] = operands[1];
3550 xoperands[0] = src_reg;
3551 if (Pmode == DImode)
3552 output_asm_insn ("dla\t%0,%1", xoperands);
3554 output_asm_insn ("la\t%0,%1", xoperands);
3558 if (CONSTANT_P (dest_reg))
3561 mips_count_memory_refs (operands[0], 1);
3563 dest_reg = operands[3 + num_regs--];
3564 if (move_type != BLOCK_MOVE_LAST)
3566 xoperands[1] = operands[0];
3567 xoperands[0] = dest_reg;
3568 if (Pmode == DImode)
3569 output_asm_insn ("dla\t%0,%1", xoperands);
3571 output_asm_insn ("la\t%0,%1", xoperands);
3576 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3577 are not offsettable, however, offsettable_address_p says they are
3578 offsettable. I think this is a bug in offsettable_address_p.
3579 For expediency, we fix this by just loading the address into a register
3580 if we happen to get one. */
3582 if (GET_CODE (src_reg) == LO_SUM)
3584 src_reg = operands[3 + num_regs--];
3585 if (move_type != BLOCK_MOVE_LAST)
3587 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3588 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3589 xoperands[0] = src_reg;
3590 if (Pmode == DImode)
3591 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3593 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3597 if (GET_CODE (dest_reg) == LO_SUM)
3599 dest_reg = operands[3 + num_regs--];
3600 if (move_type != BLOCK_MOVE_LAST)
3602 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3603 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3604 xoperands[0] = dest_reg;
3605 if (Pmode == DImode)
3606 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3608 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3612 if (num_regs > (int) ARRAY_SIZE (load_store))
3613 num_regs = ARRAY_SIZE (load_store);
3615 else if (num_regs < 1)
3616 abort_with_insn (insn,
3617 "Cannot do block move, not enough scratch registers");
3621 load_store[num].offset = offset;
3623 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3625 load_store[num].load = "ld\t%0,%1";
3626 load_store[num].load_nop = "ld\t%0,%1%#";
3627 load_store[num].store = "sd\t%0,%1";
3628 load_store[num].last_store = "sd\t%0,%1";
3629 load_store[num].final = 0;
3630 load_store[num].mode = DImode;
3635 /* ??? Fails because of a MIPS assembler bug? */
3636 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3638 if (BYTES_BIG_ENDIAN)
3640 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3641 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3642 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3643 load_store[num].last_store = "sdr\t%0,%2";
3644 load_store[num].final = "sdl\t%0,%1";
3648 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3649 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3650 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3651 load_store[num].last_store = "sdr\t%0,%1";
3652 load_store[num].final = "sdl\t%0,%2";
3655 load_store[num].mode = DImode;
3661 else if (bytes >= 4 && align >= 4)
3663 load_store[num].load = "lw\t%0,%1";
3664 load_store[num].load_nop = "lw\t%0,%1%#";
3665 load_store[num].store = "sw\t%0,%1";
3666 load_store[num].last_store = "sw\t%0,%1";
3667 load_store[num].final = 0;
3668 load_store[num].mode = SImode;
3673 else if (bytes >= 4 && ! TARGET_MIPS16)
3675 if (BYTES_BIG_ENDIAN)
3677 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3678 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3679 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3680 load_store[num].last_store = "swr\t%0,%2";
3681 load_store[num].final = "swl\t%0,%1";
3685 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3686 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3687 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3688 load_store[num].last_store = "swr\t%0,%1";
3689 load_store[num].final = "swl\t%0,%2";
3692 load_store[num].mode = SImode;
3698 else if (bytes >= 2 && align >= 2)
3700 load_store[num].load = "lh\t%0,%1";
3701 load_store[num].load_nop = "lh\t%0,%1%#";
3702 load_store[num].store = "sh\t%0,%1";
3703 load_store[num].last_store = "sh\t%0,%1";
3704 load_store[num].final = 0;
3705 load_store[num].mode = HImode;
3711 load_store[num].load = "lb\t%0,%1";
3712 load_store[num].load_nop = "lb\t%0,%1%#";
3713 load_store[num].store = "sb\t%0,%1";
3714 load_store[num].last_store = "sb\t%0,%1";
3715 load_store[num].final = 0;
3716 load_store[num].mode = QImode;
3721 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3723 dslots_load_total++;
3724 dslots_load_filled++;
3726 if (CONSTANT_P (src_reg))
3727 mips_count_memory_refs (src_reg, 1);
3729 if (CONSTANT_P (dest_reg))
3730 mips_count_memory_refs (dest_reg, 1);
3733 /* Emit load/stores now if we have run out of registers or are
3734 at the end of the move. */
3736 if (++num == num_regs || bytes == 0)
3738 /* If only load/store, we need a NOP after the load. */
3741 load_store[0].load = load_store[0].load_nop;
3742 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3743 dslots_load_filled--;
3746 if (move_type != BLOCK_MOVE_LAST)
3748 for (i = 0; i < num; i++)
3752 if (!operands[i + 4])
3755 if (GET_MODE (operands[i + 4]) != load_store[i].mode)
3756 operands[i + 4] = gen_rtx_REG (load_store[i].mode,
3757 REGNO (operands[i + 4]));
3759 offset = load_store[i].offset;
3760 xoperands[0] = operands[i + 4];
3761 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3762 plus_constant (src_reg, offset));
3767 = GET_MODE_SIZE (load_store[i].mode) - 1;
3769 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3770 plus_constant (src_reg,
3775 output_asm_insn (load_store[i].load, xoperands);
3779 for (i = 0; i < num; i++)
3781 int last_p = (i == num-1 && bytes == 0);
3782 int offset = load_store[i].offset;
3784 xoperands[0] = operands[i + 4];
3785 xoperands[1] = gen_rtx_MEM (load_store[i].mode,
3786 plus_constant (dest_reg, offset));
3791 int extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3792 xoperands[2] = gen_rtx_MEM (load_store[i].mode,
3793 plus_constant (dest_reg,
3798 if (move_type == BLOCK_MOVE_NORMAL)
3799 output_asm_insn (load_store[i].store, xoperands);
3801 else if (move_type == BLOCK_MOVE_NOT_LAST)
3804 output_asm_insn (load_store[i].store, xoperands);
3806 else if (load_store[i].final != 0)
3807 output_asm_insn (load_store[i].final, xoperands);
3811 output_asm_insn (load_store[i].last_store, xoperands);
3814 num = 0; /* reset load_store */
3822 /* Argument support functions. */
3824 /* Initialize CUMULATIVE_ARGS for a function. */
3827 init_cumulative_args (cum, fntype, libname)
3828 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3829 tree fntype; /* tree ptr for function decl */
3830 rtx libname ATTRIBUTE_UNUSED; /* SYMBOL_REF of library name or 0 */
3832 static CUMULATIVE_ARGS zero_cum;
3833 tree param, next_param;
3835 if (TARGET_DEBUG_E_MODE)
3838 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3841 fputc ('\n', stderr);
3845 tree ret_type = TREE_TYPE (fntype);
3846 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3847 tree_code_name[(int)TREE_CODE (fntype)],
3848 tree_code_name[(int)TREE_CODE (ret_type)]);
3854 /* Determine if this function has variable arguments. This is
3855 indicated by the last argument being 'void_type_mode' if there
3856 are no variable arguments. The standard MIPS calling sequence
3857 passes all arguments in the general purpose registers in this case. */
3859 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3860 param != 0; param = next_param)
3862 next_param = TREE_CHAIN (param);
3863 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3864 cum->gp_reg_found = 1;
3868 /* Advance the argument to the next argument position. */
3871 function_arg_advance (cum, mode, type, named)
3872 CUMULATIVE_ARGS *cum; /* current arg information */
3873 enum machine_mode mode; /* current arg mode */
3874 tree type; /* type of the argument or 0 if lib support */
3875 int named; /* whether or not the argument was named */
3877 if (TARGET_DEBUG_E_MODE)
3880 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3881 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3882 GET_MODE_NAME (mode));
3883 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3884 fprintf (stderr, ", %d )\n\n", named);
3894 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3895 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3898 cum->gp_reg_found = 1;
3899 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3904 cum->gp_reg_found = 1;
3905 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3910 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3911 cum->fp_arg_words++;
3914 if (! cum->gp_reg_found && cum->arg_number <= 2)
3915 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3919 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3920 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3922 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3923 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3924 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3928 cum->gp_reg_found = 1;
3929 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3935 cum->gp_reg_found = 1;
3941 /* Return an RTL expression containing the register for the given mode,
3942 or 0 if the argument is to be passed on the stack. */
3945 function_arg (cum, mode, type, named)
3946 CUMULATIVE_ARGS *cum; /* current arg information */
3947 enum machine_mode mode; /* current arg mode */
3948 tree type; /* type of the argument or 0 if lib support */
3949 int named; /* != 0 for normal args, == 0 for ... args */
3954 unsigned int *arg_words = &cum->arg_words;
3955 int struct_p = (type != 0
3956 && (TREE_CODE (type) == RECORD_TYPE
3957 || TREE_CODE (type) == UNION_TYPE
3958 || TREE_CODE (type) == QUAL_UNION_TYPE));
3960 if (TARGET_DEBUG_E_MODE)
3963 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
3964 cum->gp_reg_found, cum->arg_number, cum->arg_words,
3965 GET_MODE_NAME (mode));
3966 fprintf (stderr, HOST_PTR_PRINTF, (const PTR) type);
3967 fprintf (stderr, ", %d ) = ", named);
3971 cum->last_arg_fp = 0;
3975 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
3977 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3978 regbase = GP_ARG_FIRST;
3981 regbase = FP_ARG_FIRST;
3983 /* If the first arg was a float in a floating point register,
3984 then set bias to align this float arg properly. */
3985 if (cum->arg_words == 1)
3989 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3992 cum->fp_arg_words += cum->fp_arg_words & 1;
3993 cum->last_arg_fp = 1;
3994 arg_words = &cum->fp_arg_words;
3995 regbase = FP_ARG_FIRST;
3998 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
4004 if (mips_abi == ABI_EABI
4005 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4006 cum->fp_arg_words += cum->fp_arg_words & 1;
4008 cum->arg_words += cum->arg_words & 1;
4011 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
4012 regbase = ((cum->gp_reg_found
4013 || TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT
4014 || cum->arg_number >= 2)
4015 ? GP_ARG_FIRST : FP_ARG_FIRST);
4016 else if (mips_abi == ABI_EABI
4017 && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
4019 cum->last_arg_fp = 1;
4020 arg_words = &cum->fp_arg_words;
4021 regbase = FP_ARG_FIRST;
4024 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
4025 ? GP_ARG_FIRST : FP_ARG_FIRST);
4029 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4030 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4033 /* Drops through. */
4035 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD
4036 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4037 cum->arg_words += (cum->arg_words & 1);
4038 regbase = GP_ARG_FIRST;
4045 regbase = GP_ARG_FIRST;
4050 cum->arg_words += (cum->arg_words & 1);
4051 regbase = GP_ARG_FIRST;
4054 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
4056 if (TARGET_DEBUG_E_MODE)
4057 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
4066 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
4067 || mips_abi == ABI_EABI || mips_abi == ABI_O64 || ! named
4068 || ! TYPE_SIZE_UNIT (type)
4069 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
4070 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4073 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
4074 structure contains a double in its entirety, then that 64 bit
4075 chunk is passed in a floating point register. */
4078 /* First check to see if there is any such field. */
4079 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4080 if (TREE_CODE (field) == FIELD_DECL
4081 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4082 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
4083 && host_integerp (bit_position (field), 0)
4084 && int_bit_position (field) % BITS_PER_WORD == 0)
4087 /* If the whole struct fits a DFmode register,
4088 we don't need the PARALLEL. */
4089 if (! field || mode == DFmode)
4090 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
4093 /* Now handle the special case by returning a PARALLEL
4094 indicating where each 64 bit chunk goes. */
4095 unsigned int chunks;
4096 HOST_WIDE_INT bitpos;
4100 /* ??? If this is a packed structure, then the last hunk won't
4104 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
4105 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
4106 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
4108 /* assign_parms checks the mode of ENTRY_PARM, so we must
4109 use the actual mode here. */
4110 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
4113 regno = regbase + *arg_words + bias;
4114 field = TYPE_FIELDS (type);
4115 for (i = 0; i < chunks; i++)
4119 for (; field; field = TREE_CHAIN (field))
4120 if (TREE_CODE (field) == FIELD_DECL
4121 && int_bit_position (field) >= bitpos)
4125 && int_bit_position (field) == bitpos
4126 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
4127 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
4128 reg = gen_rtx_REG (DFmode,
4129 regno + FP_ARG_FIRST - GP_ARG_FIRST);
4131 reg = gen_rtx_REG (word_mode, regno);
4134 = gen_rtx_EXPR_LIST (VOIDmode, reg,
4135 GEN_INT (bitpos / BITS_PER_UNIT));
4143 if (TARGET_DEBUG_E_MODE)
4144 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
4145 struct_p ? ", [struct]" : "");
4147 /* The following is a hack in order to pass 1 byte structures
4148 the same way that the MIPS compiler does (namely by passing
4149 the structure in the high byte or half word of the register).
4150 This also makes varargs work. If we have such a structure,
4151 we save the adjustment RTL, and the call define expands will
4152 emit them. For the VOIDmode argument (argument after the
4153 last real argument), pass back a parallel vector holding each
4154 of the adjustments. */
4156 /* ??? function_arg can be called more than once for each argument.
4157 As a result, we compute more adjustments than we need here.
4158 See the CUMULATIVE_ARGS definition in mips.h. */
4160 /* ??? This scheme requires everything smaller than the word size to
4161 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
4162 that would mean every int needs to be shifted left, which is very
4163 inefficient. Let's not carry this compatibility to the 64 bit
4164 calling convention for now. */
4166 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
4167 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4169 rtx amount = GEN_INT (BITS_PER_WORD
4170 - int_size_in_bytes (type) * BITS_PER_UNIT);
4171 rtx reg = gen_rtx_REG (word_mode, regbase + *arg_words + bias);
4174 cum->adjust[cum->num_adjusts++] = gen_ashldi3 (reg, reg, amount);
4176 cum->adjust[cum->num_adjusts++] = gen_ashlsi3 (reg, reg, amount);
4180 /* We will be called with a mode of VOIDmode after the last argument
4181 has been seen. Whatever we return will be passed to the call
4182 insn. If we need any shifts for small structures, return them in
4183 a PARALLEL; in that case, stuff the mips16 fp_code in as the
4184 mode. Otherwise, if we have need a mips16 fp_code, return a REG
4185 with the code stored as the mode. */
4186 if (mode == VOIDmode)
4188 if (cum->num_adjusts > 0)
4189 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
4190 gen_rtvec_v (cum->num_adjusts, cum->adjust));
4191 else if (TARGET_MIPS16 && cum->fp_code != 0)
4192 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
4199 function_arg_partial_nregs (cum, mode, type, named)
4200 CUMULATIVE_ARGS *cum; /* current arg information */
4201 enum machine_mode mode; /* current arg mode */
4202 tree type; /* type of the argument or 0 if lib support */
4203 int named ATTRIBUTE_UNUSED;/* != 0 for normal args, == 0 for ... args */
4205 if ((mode == BLKmode
4206 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
4207 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
4208 && cum->arg_words < (unsigned) MAX_ARGS_IN_REGISTERS
4209 && mips_abi != ABI_EABI)
4212 if (mode == BLKmode)
4213 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
4216 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4218 if (words + cum->arg_words <= (unsigned) MAX_ARGS_IN_REGISTERS)
4219 return 0; /* structure fits in registers */
4221 if (TARGET_DEBUG_E_MODE)
4222 fprintf (stderr, "function_arg_partial_nregs = %d\n",
4223 MAX_ARGS_IN_REGISTERS - cum->arg_words);
4225 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
4228 else if (mode == DImode
4229 && cum->arg_words == MAX_ARGS_IN_REGISTERS - (unsigned)1
4230 && ! TARGET_64BIT && mips_abi != ABI_EABI)
4232 if (TARGET_DEBUG_E_MODE)
4233 fprintf (stderr, "function_arg_partial_nregs = 1\n");
4241 /* Create the va_list data type.
4242 We keep 3 pointers, and two offsets.
4243 Two pointers are to the overflow area, which starts at the CFA.
4244 One of these is constant, for addressing into the GPR save area below it.
4245 The other is advanced up the stack through the overflow region.
4246 The third pointer is to the GPR save area. Since the FPR save area
4247 is just below it, we can address FPR slots off this pointer.
4248 We also keep two one-byte offsets, which are to be subtracted from the
4249 constant pointers to yield addresses in the GPR and FPR save areas.
4250 These are downcounted as float or non-float arguments are used,
4251 and when they get to zero, the argument must be obtained from the
4253 If TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT, then no FPR save area exists,
4254 and a single pointer is enough. It's started at the GPR save area,
4255 and is advanced, period.
4256 Note that the GPR save area is not constant size, due to optimization
4257 in the prologue. Hence, we can't use a design with two pointers
4258 and two offsets, although we could have designed this with two pointers
4259 and three offsets. */
4263 mips_build_va_list ()
4265 if (mips_abi == ABI_EABI && !TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4267 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, record;
4269 record = make_node (RECORD_TYPE);
4271 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
4273 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
4275 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
4277 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
4278 unsigned_char_type_node);
4279 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
4280 unsigned_char_type_node);
4283 DECL_FIELD_CONTEXT (f_ovfl) = record;
4284 DECL_FIELD_CONTEXT (f_gtop) = record;
4285 DECL_FIELD_CONTEXT (f_ftop) = record;
4286 DECL_FIELD_CONTEXT (f_goff) = record;
4287 DECL_FIELD_CONTEXT (f_foff) = record;
4289 TYPE_FIELDS (record) = f_ovfl;
4290 TREE_CHAIN (f_ovfl) = f_gtop;
4291 TREE_CHAIN (f_gtop) = f_ftop;
4292 TREE_CHAIN (f_ftop) = f_goff;
4293 TREE_CHAIN (f_goff) = f_foff;
4295 layout_type (record);
4299 return ptr_type_node;
4302 /* Implement va_start. stdarg_p is 0 if implementing
4303 __builtin_varargs_va_start, 1 if implementing __builtin_stdarg_va_start.
4304 Note that this routine isn't called when compiling e.g. "_vfprintf_r".
4305 (It doesn't have "...", so it inherits the pointers of its caller.) */
4308 mips_va_start (stdarg_p, valist, nextarg)
4316 /* Find out how many non-float named formals */
4317 int_arg_words = current_function_args_info.arg_words;
4319 if (mips_abi == ABI_EABI)
4321 int gpr_save_area_size;
4322 /* Note UNITS_PER_WORD is 4 bytes or 8, depending on TARGET_64BIT. */
4323 if (int_arg_words < 8 )
4324 /* Adjust for the prologue's economy measure */
4325 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
4327 gpr_save_area_size = 0;
4329 if (!TARGET_SOFT_FLOAT && !TARGET_SINGLE_FLOAT)
4331 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4332 tree ovfl, gtop, ftop, goff, foff;
4334 int float_formals, fpr_offset, size_excess, floats_passed_in_regs;
4335 int fpr_save_offset;
4337 float_formals = current_function_args_info.fp_arg_words;
4338 /* If mips2, the number of formals is half the reported # of words */
4341 floats_passed_in_regs = (TARGET_64BIT ? 8 : 4);
4343 f_ovfl = TYPE_FIELDS (va_list_type_node);
4344 f_gtop = TREE_CHAIN (f_ovfl);
4345 f_ftop = TREE_CHAIN (f_gtop);
4346 f_goff = TREE_CHAIN (f_ftop);
4347 f_foff = TREE_CHAIN (f_goff);
4349 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4350 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4351 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4352 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4353 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4355 /* Emit code setting a pointer into the overflow (shared-stack) area.
4356 If there were more than 8 non-float formals, or more than 8
4357 float formals, then this pointer isn't to the base of the area.
4358 In that case, it must point to where the first vararg is. */
4360 if (float_formals > floats_passed_in_regs)
4361 size_excess += (float_formals-floats_passed_in_regs) * 8;
4362 if (int_arg_words > 8)
4363 size_excess += (int_arg_words-8) * UNITS_PER_WORD;
4365 /* FIXME: for mips2, the above size_excess can be wrong. Because the
4366 overflow stack holds mixed size items, there can be alignments,
4367 so that an 8 byte double following a 4 byte int will be on an
4368 8 byte boundary. This means that the above calculation should
4369 take into account the exact sequence of floats and non-floats
4370 which make up the excess. That calculation should be rolled
4371 into the code which sets the current_function_args_info struct.
4372 The above then reduces to a fetch from that struct. */
4375 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
4377 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
4378 build_int_2 (size_excess, 0));
4379 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4380 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4382 /* Emit code setting a ptr to the base of the overflow area. */
4383 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
4384 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
4385 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4387 /* Emit code setting a pointer to the GPR save area.
4388 More precisely, a pointer to off-the-end of the FPR save area.
4389 If mips4, this is gpr_save_area_size below the overflow area.
4390 If mips2, also round down to an 8-byte boundary, since the FPR
4391 save area is 8-byte aligned, and GPR is 4-byte-aligned.
4392 Therefore there can be a 4-byte gap between the save areas. */
4393 gprv = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4394 fpr_save_offset = gpr_save_area_size;
4397 if (fpr_save_offset & 7)
4398 fpr_save_offset += 4;
4400 if (fpr_save_offset)
4401 gprv = build (PLUS_EXPR, TREE_TYPE (ftop), gprv,
4402 build_int_2 (-fpr_save_offset,-1));
4403 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, gprv);
4404 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4406 /* Emit code initting an offset to the size of the GPR save area */
4407 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4408 build_int_2 (gpr_save_area_size,0));
4409 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4411 /* Emit code initting an offset from ftop to the first float
4412 vararg. This varies in size, since any float
4413 varargs are put in the FPR save area after the formals.
4414 Note it's 8 bytes/formal regardless of TARGET_64BIT.
4415 However, mips2 stores 4 GPRs, mips4 stores 8 GPRs.
4416 If there are 8 or more float formals, init to zero.
4417 (In fact, the formals aren't stored in the bottom of the
4418 FPR save area: they are elsewhere, and the size of the FPR
4419 save area is economized by the prologue. But this code doesn't
4420 care. This design is unaffected by that fact.) */
4421 if (float_formals >= floats_passed_in_regs)
4424 fpr_offset = (floats_passed_in_regs - float_formals) * 8;
4425 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4426 build_int_2 (fpr_offset,0));
4427 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4431 /* TARGET_SOFT_FLOAT or TARGET_SINGLE_FLOAT */
4433 /* Everything is in the GPR save area, or in the overflow
4434 area which is contiguous with it. */
4436 int offset = -gpr_save_area_size;
4437 if (gpr_save_area_size == 0)
4438 offset = (stdarg_p ? 0 : -UNITS_PER_WORD);
4439 nextarg = plus_constant (nextarg, offset);
4440 std_expand_builtin_va_start (1, valist, nextarg);
4452 /* ??? This had been conditional on
4453 _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
4454 and both iris5.h and iris6.h define _MIPS_SIM. */
4455 if (mips_abi == ABI_N32 || mips_abi == ABI_64)
4456 ofs = (int_arg_words >= 8 ? -UNITS_PER_WORD : 0);
4458 ofs = -UNITS_PER_WORD;
4461 nextarg = plus_constant (nextarg, ofs);
4462 std_expand_builtin_va_start (1, valist, nextarg);
4466 /* Implement va_arg. */
4469 mips_va_arg (valist, type)
4472 HOST_WIDE_INT size, rsize;
4476 size = int_size_in_bytes (type);
4477 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4479 if (mips_abi == ABI_EABI)
4482 rtx r, lab_over = NULL_RTX, lab_false;
4483 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4484 tree ovfl, gtop, ftop, goff, foff;
4487 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4490 size = POINTER_SIZE / BITS_PER_UNIT;
4491 rsize = UNITS_PER_WORD;
4494 addr_rtx = gen_reg_rtx (Pmode);
4496 if (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4498 /* Case of all args in a merged stack. No need to check bounds,
4499 just advance valist along the stack. */
4504 && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
4506 t = build (PLUS_EXPR, TREE_TYPE (gpr), gpr,
4507 build_int_2 (2*UNITS_PER_WORD - 1, 0));
4508 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
4509 build_int_2 (-2*UNITS_PER_WORD, -1));
4510 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
4511 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4514 t = build (POSTINCREMENT_EXPR, TREE_TYPE (gpr), gpr,
4516 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4518 emit_move_insn (addr_rtx, r);
4520 /* flush the POSTINCREMENT */
4525 r = gen_rtx_MEM (Pmode, addr_rtx);
4526 set_mem_alias_set (r, get_varargs_alias_set ());
4527 emit_move_insn (addr_rtx, r);
4531 if (BYTES_BIG_ENDIAN && rsize != size)
4532 addr_rtx = plus_constant (addr_rtx, rsize - size);
4537 /* Not a simple merged stack. Need ptrs and indexes left by va_start. */
4539 f_ovfl = TYPE_FIELDS (va_list_type_node);
4540 f_gtop = TREE_CHAIN (f_ovfl);
4541 f_ftop = TREE_CHAIN (f_gtop);
4542 f_goff = TREE_CHAIN (f_ftop);
4543 f_foff = TREE_CHAIN (f_goff);
4545 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
4546 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop);
4547 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
4548 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff);
4549 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
4551 lab_false = gen_label_rtx ();
4552 lab_over = gen_label_rtx ();
4554 if (TREE_CODE (type) == REAL_TYPE)
4557 /* Emit code to branch if foff == 0. */
4558 r = expand_expr (foff, NULL_RTX, TYPE_MODE (TREE_TYPE (foff)),
4560 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4561 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4563 /* Emit code for addr_rtx = ftop - foff */
4564 t = build (MINUS_EXPR, TREE_TYPE (ftop), ftop, foff );
4565 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4567 emit_move_insn (addr_rtx, r);
4569 /* Emit code for foff-=8.
4570 Advances the offset up FPR save area by one double */
4571 t = build (MINUS_EXPR, TREE_TYPE (foff), foff, build_int_2 (8, 0));
4572 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff, t);
4573 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4576 emit_jump (lab_over);
4578 emit_label (lab_false);
4582 /* For mips2, the overflow area contains mixed size items.
4583 If a 4-byte int is followed by an 8-byte float, then
4584 natural alignment causes a 4 byte gap.
4585 So, dynamically adjust ovfl up to a multiple of 8. */
4586 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), ovfl,
4587 build_int_2 (7, 0));
4588 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, t);
4589 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4590 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4593 /* Emit code for addr_rtx = the ovfl pointer into overflow area.
4594 Regardless of mips2, postincrement the ovfl pointer by 8. */
4595 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4597 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4599 emit_move_insn (addr_rtx, r);
4602 emit_label (lab_over);
4611 && TREE_CODE (type) == INTEGER_TYPE
4612 && TYPE_PRECISION (type) == 64)
4614 /* In mips2, int takes 32 bits of the GPR save area, but
4615 longlong takes an aligned 64 bits. So, emit code
4616 to zero the low order bits of goff, thus aligning
4617 the later calculation of (gtop-goff) upwards. */
4618 t = build (BIT_AND_EXPR, TREE_TYPE (goff), goff,
4619 build_int_2 (-8, -1));
4620 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4621 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4624 /* Emit code to branch if goff == 0. */
4625 r = expand_expr (goff, NULL_RTX, TYPE_MODE (TREE_TYPE (goff)),
4627 emit_cmp_and_jump_insns (r, const0_rtx, EQ,
4628 const1_rtx, GET_MODE (r), 1, 1, lab_false);
4630 /* Emit code for addr_rtx = gtop - goff. */
4631 t = build (MINUS_EXPR, TREE_TYPE (gtop), gtop, goff);
4632 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4634 emit_move_insn (addr_rtx, r);
4636 /* Note that mips2 int is 32 bit, but mips2 longlong is 64. */
4637 if (! TARGET_64BIT && TYPE_PRECISION (type) == 64)
4640 step_size = UNITS_PER_WORD;
4642 /* Emit code for goff = goff - step_size.
4643 Advances the offset up GPR save area over the item. */
4644 t = build (MINUS_EXPR, TREE_TYPE (goff), goff,
4645 build_int_2 (step_size, 0));
4646 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff, t);
4647 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4650 emit_jump (lab_over);
4652 emit_label (lab_false);
4654 /* Emit code for addr_rtx -> overflow area, postinc by step_size */
4655 t = build (POSTINCREMENT_EXPR, TREE_TYPE(ovfl), ovfl,
4656 size_int (step_size));
4657 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4659 emit_move_insn (addr_rtx, r);
4662 emit_label (lab_over);
4666 r = gen_rtx_MEM (Pmode, addr_rtx);
4667 set_mem_alias_set (r, get_varargs_alias_set ());
4668 emit_move_insn (addr_rtx, r);
4672 if (BYTES_BIG_ENDIAN && rsize != size)
4673 addr_rtx = plus_constant (addr_rtx, rsize - size);
4683 /* ??? The original va-mips.h did always align, despite the fact
4684 that alignments <= UNITS_PER_WORD are preserved by the va_arg
4685 increment mechanism. */
4689 else if (TYPE_ALIGN (type) > 32)
4694 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4695 build_int_2 (align - 1, 0));
4696 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1));
4697 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4698 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4700 /* Everything past the alignment is standard. */
4701 return std_expand_builtin_va_arg (valist, type);
4705 /* Abort after printing out a specific insn. */
4708 abort_with_insn (insn, reason)
4717 /* Set up the threshold for data to go into the small data area, instead
4718 of the normal data area, and detect any conflicts in the switches. */
4723 register int i, start;
4725 register enum machine_mode mode;
4726 register enum processor_type mips_cpu;
4728 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4730 if (mips_section_threshold <= 0)
4731 target_flags &= ~MASK_GPOPT;
4733 target_flags |= MASK_GPOPT;
4735 /* If both single-float and soft-float are set, then clear the one that
4736 was set by TARGET_DEFAULT, leaving the one that was set by the
4737 user. We assume here that the specs prevent both being set by the
4739 #ifdef TARGET_DEFAULT
4740 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
4741 target_flags &= ~((TARGET_DEFAULT) & (MASK_SOFT_FLOAT | MASK_SINGLE_FLOAT));
4744 /* Get the architectural level. */
4745 if (mips_isa_string == 0)
4746 mips_isa = MIPS_ISA_DEFAULT;
4748 else if (ISDIGIT (*mips_isa_string))
4750 mips_isa = atoi (mips_isa_string);
4753 /* -mno-mips16 overrides -mips16. */
4754 if (mips_no_mips16_string == NULL)
4756 target_flags |= MASK_MIPS16;
4760 mips_isa = MIPS_ISA_DEFAULT;
4764 mips_isa = MIPS_ISA_DEFAULT;
4767 else if (mips_isa < 1 || mips_isa > 4)
4769 error ("-mips%d not supported", mips_isa);
4776 error ("bad value (%s) for -mips switch", mips_isa_string);
4780 #ifdef MIPS_ABI_DEFAULT
4781 /* Get the ABI to use. */
4782 if (mips_abi_string == (char *) 0)
4783 mips_abi = MIPS_ABI_DEFAULT;
4784 else if (! strcmp (mips_abi_string, "32"))
4786 else if (! strcmp (mips_abi_string, "o64"))
4788 else if (! strcmp (mips_abi_string, "n32"))
4790 else if (! strcmp (mips_abi_string, "64"))
4792 else if (! strcmp (mips_abi_string, "eabi"))
4793 mips_abi = ABI_EABI;
4795 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4797 /* A specified ISA defaults the ABI if it was not specified. */
4798 if (mips_abi_string == 0 && mips_isa_string
4799 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4801 if (! ISA_HAS_64BIT_REGS)
4807 /* A specified ABI defaults the ISA if it was not specified. */
4808 else if (mips_isa_string == 0 && mips_abi_string
4809 && mips_abi != ABI_EABI && mips_abi != ABI_O64)
4811 if (mips_abi == ABI_32)
4813 else if (mips_abi == ABI_N32)
4819 /* If both ABI and ISA were specified, check for conflicts. */
4820 else if (mips_isa_string && mips_abi_string)
4822 if ((! ISA_HAS_64BIT_REGS && (mips_abi == ABI_N32 || mips_abi == ABI_64
4823 || mips_abi == ABI_O64))
4824 || (ISA_HAS_64BIT_REGS && mips_abi == ABI_32))
4825 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4828 /* Override TARGET_DEFAULT if necessary. */
4829 if (mips_abi == ABI_32)
4830 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4832 /* If no type size setting options (-mlong64,-mint64,-mlong32) were used
4833 then set the type sizes. In the EABI in 64 bit mode, longs and
4834 pointers are 64 bits. Likewise for the SGI Irix6 N64 ABI. */
4835 if (mips_explicit_type_size_string == NULL
4836 && ((mips_abi == ABI_EABI && TARGET_64BIT)
4837 || mips_abi == ABI_64))
4838 target_flags |= MASK_LONG64;
4840 /* ??? This doesn't work yet, so don't let people try to use it. */
4841 if (mips_abi == ABI_32)
4842 error ("The -mabi=32 support does not work yet.");
4845 if (mips_abi_string)
4846 error ("This target does not support the -mabi switch.");
4849 #ifdef MIPS_CPU_STRING_DEFAULT
4850 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4851 greater than that supported by the default processor, then the user gets
4852 an error. Normally, the compiler will just default to the base level cpu
4853 for the indicated isa. */
4854 if (mips_arch_string == 0)
4855 mips_arch_string = MIPS_CPU_STRING_DEFAULT;
4856 if (mips_tune_string == 0)
4857 mips_tune_string = MIPS_CPU_STRING_DEFAULT;
4860 /* Identify the processor type. */
4862 if (mips_cpu_string != 0)
4864 mips_cpu = mips_parse_cpu (mips_cpu_string);
4865 if (mips_cpu == PROCESSOR_DEFAULT)
4867 error ("bad value (%s) for -mcpu= switch", mips_arch_string);
4868 mips_cpu_string = "default";
4870 mips_arch = mips_cpu;
4871 mips_tune = mips_cpu;
4874 if (mips_arch_string == 0
4875 || ! strcmp (mips_arch_string, "default")
4876 || ! strcmp (mips_arch_string, "DEFAULT"))
4881 mips_arch_string = "3000";
4882 mips_arch = PROCESSOR_R3000;
4885 mips_arch_string = "6000";
4886 mips_arch = PROCESSOR_R6000;
4889 mips_arch_string = "4000";
4890 mips_arch = PROCESSOR_R4000;
4893 mips_arch_string = "8000";
4894 mips_arch = PROCESSOR_R8000;
4900 mips_arch = mips_parse_cpu (mips_arch_string);
4901 if (mips_arch == PROCESSOR_DEFAULT)
4903 error ("bad value (%s) for -march= switch", mips_arch_string);
4904 mips_arch_string = "default";
4907 if (mips_tune_string == 0
4908 || ! strcmp (mips_tune_string, "default")
4909 || ! strcmp (mips_tune_string, "DEFAULT"))
4911 if (mips_arch != PROCESSOR_DEFAULT)
4912 mips_tune = mips_arch;
4917 mips_tune_string = "3000";
4918 mips_tune = PROCESSOR_R3000;
4921 mips_tune_string = "6000";
4922 mips_tune = PROCESSOR_R6000;
4925 mips_tune_string = "4000";
4926 mips_tune = PROCESSOR_R4000;
4929 mips_tune_string = "8000";
4930 mips_tune = PROCESSOR_R8000;
4937 mips_tune = mips_parse_cpu (mips_tune_string);
4938 if (mips_tune == PROCESSOR_DEFAULT)
4940 error ("bad value (%s) for -mtune= switch", mips_tune_string);
4941 mips_tune_string = "default";
4945 /* Handle processor configuration based on architecture. */
4946 if (TARGET_MIPS4100 || TARGET_MIPS3900)
4947 target_flags |= MASK_SOFT_FLOAT;
4950 if ((mips_arch == PROCESSOR_R3000 && (mips_isa != 1))
4951 || (mips_arch == PROCESSOR_R6000 && mips_isa != 1 && mips_isa != 2)
4952 || ((mips_arch == PROCESSOR_R4000
4953 || mips_arch == PROCESSOR_R4100
4954 || mips_arch == PROCESSOR_R4300
4955 || mips_arch == PROCESSOR_R4600
4956 || mips_arch == PROCESSOR_R4650)
4957 && mips_isa != 1 && mips_isa != 2 && mips_isa != 3))
4958 error ("-march=%s does not support -mips%d", mips_arch_string, mips_isa);
4960 /* make sure sizes of ints/longs/etc. are ok */
4961 if (! ISA_HAS_64BIT_REGS)
4965 error ("-mips%d does not support 64 bit fp registers", mips_isa);
4966 target_flags &= ~ MASK_FLOAT64;
4969 else if (TARGET_64BIT)
4971 error ("-mips%d does not support 64 bit gp registers", mips_isa);
4972 target_flags &= ~MASK_64BIT;
4976 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
4977 flag_pcc_struct_return = 0;
4979 /* Tell halfpic.c that we have half-pic code if we do. */
4980 if (TARGET_HALF_PIC)
4983 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4984 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4985 /* ??? -non_shared turns off pic code generation, but this is not
4987 if (TARGET_ABICALLS)
4989 mips_abicalls = MIPS_ABICALLS_YES;
4991 if (mips_section_threshold > 0)
4992 warning ("-G is incompatible with PIC code which is the default");
4995 mips_abicalls = MIPS_ABICALLS_NO;
4997 /* -membedded-pic is a form of PIC code suitable for embedded
4998 systems. All calls are made using PC relative addressing, and
4999 all data is addressed using the $gp register. This requires gas,
5000 which does most of the work, and GNU ld, which automatically
5001 expands PC relative calls which are out of range into a longer
5002 instruction sequence. All gcc really does differently is
5003 generate a different sequence for a switch. */
5004 if (TARGET_EMBEDDED_PIC)
5007 if (TARGET_ABICALLS)
5008 warning ("-membedded-pic and -mabicalls are incompatible");
5011 warning ("-G and -membedded-pic are incompatible");
5013 /* Setting mips_section_threshold is not required, because gas
5014 will force everything to be GP addressable anyhow, but
5015 setting it will cause gcc to make better estimates of the
5016 number of instructions required to access a particular data
5018 mips_section_threshold = 0x7fffffff;
5021 /* This optimization requires a linker that can support a R_MIPS_LO16
5022 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
5023 GNU ld has this support, but not all other MIPS linkers do, so we enable
5024 this optimization only if the user requests it, or if GNU ld is the
5025 standard linker for this configuration. */
5026 /* ??? This does not work when target addresses are DImode.
5027 This is because we are missing DImode high/lo_sum patterns. */
5028 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
5030 mips_split_addresses = 1;
5032 mips_split_addresses = 0;
5034 /* -mrnames says to use the MIPS software convention for register
5035 names instead of the hardware names (ie, $a0 instead of $4).
5036 We do this by switching the names in mips_reg_names, which the
5037 reg_names points into via the REGISTER_NAMES macro. */
5039 if (TARGET_NAME_REGS)
5040 memcpy (mips_reg_names, mips_sw_reg_names, sizeof (mips_reg_names));
5042 /* When compiling for the mips16, we can not use floating point. We
5043 record the original hard float value in mips16_hard_float. */
5046 if (TARGET_SOFT_FLOAT)
5047 mips16_hard_float = 0;
5049 mips16_hard_float = 1;
5050 target_flags |= MASK_SOFT_FLOAT;
5052 /* Don't run the scheduler before reload, since it tends to
5053 increase register pressure. */
5054 flag_schedule_insns = 0;
5057 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
5058 to avoid using up another bit in target_flags. */
5059 if (mips_entry_string != NULL)
5061 if (*mips_entry_string != '\0')
5062 error ("Invalid option `entry%s'", mips_entry_string);
5064 if (! TARGET_MIPS16)
5065 warning ("-mentry is only meaningful with -mips-16");
5070 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
5071 attributes can access it. */
5077 /* Initialize the high and low values for legitimate floating point
5078 constants. Rather than trying to get the accuracy down to the
5079 last bit, just use approximate ranges. */
5080 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
5081 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
5082 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
5083 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
5085 mips_print_operand_punct['?'] = 1;
5086 mips_print_operand_punct['#'] = 1;
5087 mips_print_operand_punct['&'] = 1;
5088 mips_print_operand_punct['!'] = 1;
5089 mips_print_operand_punct['*'] = 1;
5090 mips_print_operand_punct['@'] = 1;
5091 mips_print_operand_punct['.'] = 1;
5092 mips_print_operand_punct['('] = 1;
5093 mips_print_operand_punct[')'] = 1;
5094 mips_print_operand_punct['['] = 1;
5095 mips_print_operand_punct[']'] = 1;
5096 mips_print_operand_punct['<'] = 1;
5097 mips_print_operand_punct['>'] = 1;
5098 mips_print_operand_punct['{'] = 1;
5099 mips_print_operand_punct['}'] = 1;
5100 mips_print_operand_punct['^'] = 1;
5101 mips_print_operand_punct['$'] = 1;
5102 mips_print_operand_punct['+'] = 1;
5103 mips_print_operand_punct['~'] = 1;
5105 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
5106 mips_char_to_class['e'] = M16_NA_REGS;
5107 mips_char_to_class['t'] = T_REG;
5108 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
5109 mips_char_to_class['h'] = HI_REG;
5110 mips_char_to_class['l'] = LO_REG;
5111 mips_char_to_class['a'] = HILO_REG;
5112 mips_char_to_class['x'] = MD_REGS;
5113 mips_char_to_class['b'] = ALL_REGS;
5114 mips_char_to_class['y'] = GR_REGS;
5115 mips_char_to_class['z'] = ST_REGS;
5117 /* Set up array to map GCC register number to debug register number.
5118 Ignore the special purpose register numbers. */
5120 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5121 mips_dbx_regno[i] = -1;
5123 start = GP_DBX_FIRST - GP_REG_FIRST;
5124 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
5125 mips_dbx_regno[i] = i + start;
5127 start = FP_DBX_FIRST - FP_REG_FIRST;
5128 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
5129 mips_dbx_regno[i] = i + start;
5131 /* Set up array giving whether a given register can hold a given mode.
5132 At present, restrict ints from being in FP registers, because reload
5133 is a little enthusiastic about storing extra values in FP registers,
5134 and this is not good for things like OS kernels. Also, due to the
5135 mandatory delay, it is as fast to load from cached memory as to move
5136 from the FP register. */
5138 for (mode = VOIDmode;
5139 mode != MAX_MACHINE_MODE;
5140 mode = (enum machine_mode) ((int)mode + 1))
5142 register int size = GET_MODE_SIZE (mode);
5143 register enum mode_class class = GET_MODE_CLASS (mode);
5145 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
5152 temp = (regno == FPSW_REGNUM);
5154 temp = (ST_REG_P (regno) || GP_REG_P (regno)
5155 || FP_REG_P (regno));
5158 else if (GP_REG_P (regno))
5159 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
5161 else if (FP_REG_P (regno))
5162 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
5163 && (class == MODE_FLOAT
5164 || class == MODE_COMPLEX_FLOAT
5165 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
5166 && (! TARGET_SINGLE_FLOAT || size <= 4));
5168 else if (MD_REG_P (regno))
5169 temp = (class == MODE_INT
5170 && (size <= UNITS_PER_WORD
5171 || (regno == MD_REG_FIRST
5172 && size == 2 * UNITS_PER_WORD)));
5177 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
5181 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
5182 initialized yet, so we can't use that here. */
5183 gpr_mode = TARGET_64BIT ? DImode : SImode;
5185 /* Provide default values for align_* for 64-bit targets. */
5186 if (TARGET_64BIT && !TARGET_MIPS16)
5188 if (align_loops == 0)
5190 if (align_jumps == 0)
5192 if (align_functions == 0)
5193 align_functions = 8;
5196 /* Register global variables with the garbage collector. */
5197 mips_add_gc_roots ();
5200 /* On the mips16, we want to allocate $24 (T_REG) before other
5201 registers for instructions for which it is possible. This helps
5202 avoid shuffling registers around in order to set up for an xor,
5203 encouraging the compiler to use a cmp instead. */
5206 mips_order_regs_for_local_alloc ()
5210 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5211 reg_alloc_order[i] = i;
5215 /* It really doesn't matter where we put register 0, since it is
5216 a fixed register anyhow. */
5217 reg_alloc_order[0] = 24;
5218 reg_alloc_order[24] = 0;
5223 /* The MIPS debug format wants all automatic variables and arguments
5224 to be in terms of the virtual frame pointer (stack pointer before
5225 any adjustment in the function), while the MIPS 3.0 linker wants
5226 the frame pointer to be the stack pointer after the initial
5227 adjustment. So, we do the adjustment here. The arg pointer (which
5228 is eliminated) points to the virtual frame pointer, while the frame
5229 pointer (which may be eliminated) points to the stack pointer after
5230 the initial adjustments. */
5233 mips_debugger_offset (addr, offset)
5235 HOST_WIDE_INT offset;
5237 rtx offset2 = const0_rtx;
5238 rtx reg = eliminate_constant_term (addr, &offset2);
5241 offset = INTVAL (offset2);
5243 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5244 || reg == hard_frame_pointer_rtx)
5246 HOST_WIDE_INT frame_size = (!current_frame_info.initialized)
5247 ? compute_frame_size (get_frame_size ())
5248 : current_frame_info.total_size;
5250 /* MIPS16 frame is smaller */
5251 if (frame_pointer_needed && TARGET_MIPS16)
5252 frame_size -= current_function_outgoing_args_size;
5254 offset = offset - frame_size;
5257 /* sdbout_parms does not want this to crash for unrecognized cases. */
5259 else if (reg != arg_pointer_rtx)
5260 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
5266 /* A C compound statement to output to stdio stream STREAM the
5267 assembler syntax for an instruction operand X. X is an RTL
5270 CODE is a value that can be used to specify one of several ways
5271 of printing the operand. It is used when identical operands
5272 must be printed differently depending on the context. CODE
5273 comes from the `%' specification that was used to request
5274 printing of the operand. If the specification was just `%DIGIT'
5275 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
5276 is the ASCII code for LTR.
5278 If X is a register, this macro should print the register's name.
5279 The names can be found in an array `reg_names' whose type is
5280 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
5282 When the machine description has a specification `%PUNCT' (a `%'
5283 followed by a punctuation character), this macro is called with
5284 a null pointer for X and the punctuation character for CODE.
5286 The MIPS specific codes are:
5288 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5289 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5290 'd' output integer constant in decimal,
5291 'z' if the operand is 0, use $0 instead of normal operand.
5292 'D' print second part of double-word register or memory operand.
5293 'L' print low-order register of double-word register operand.
5294 'M' print high-order register of double-word register operand.
5295 'C' print part of opcode for a branch condition.
5296 'F' print part of opcode for a floating-point branch condition.
5297 'N' print part of opcode for a branch condition, inverted.
5298 'W' print part of opcode for a floating-point branch condition, inverted.
5299 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
5300 'B' print 'z' for EQ, 'n' for NE
5301 'b' print 'n' for EQ, 'z' for NE
5302 'T' print 'f' for EQ, 't' for NE
5303 't' print 't' for EQ, 'f' for NE
5304 'Z' print register and a comma, but print nothing for $fcc0
5305 '(' Turn on .set noreorder
5306 ')' Turn on .set reorder
5307 '[' Turn on .set noat
5309 '<' Turn on .set nomacro
5310 '>' Turn on .set macro
5311 '{' Turn on .set volatile (not GAS)
5312 '}' Turn on .set novolatile (not GAS)
5313 '&' Turn on .set noreorder if filling delay slots
5314 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5315 '!' Turn on .set nomacro if filling delay slots
5316 '#' Print nop if in a .set noreorder section.
5317 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5318 '@' Print the name of the assembler temporary register (at or $1).
5319 '.' Print the name of the register with a hard-wired zero (zero or $0).
5320 '^' Print the name of the pic call-through register (t9 or $25).
5321 '$' Print the name of the stack pointer register (sp or $29).
5322 '+' Print the name of the gp register (gp or $28).
5323 '~' Output an branch alignment to LABEL_ALIGN(NULL). */
5326 print_operand (file, op, letter)
5327 FILE *file; /* file to write to */
5328 rtx op; /* operand to print */
5329 int letter; /* %<letter> or 0 */
5331 register enum rtx_code code;
5333 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5338 if (mips_branch_likely)
5343 fputs (reg_names [GP_REG_FIRST + 1], file);
5347 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5351 fputs (reg_names [GP_REG_FIRST + 0], file);
5355 fputs (reg_names[STACK_POINTER_REGNUM], file);
5359 fputs (reg_names[GP_REG_FIRST + 28], file);
5363 if (final_sequence != 0 && set_noreorder++ == 0)
5364 fputs (".set\tnoreorder\n\t", file);
5368 if (final_sequence != 0)
5370 if (set_noreorder++ == 0)
5371 fputs (".set\tnoreorder\n\t", file);
5373 if (set_nomacro++ == 0)
5374 fputs (".set\tnomacro\n\t", file);
5379 if (final_sequence != 0 && set_nomacro++ == 0)
5380 fputs ("\n\t.set\tnomacro", file);
5384 if (set_noreorder != 0)
5385 fputs ("\n\tnop", file);
5386 else if (TARGET_STATS)
5387 fputs ("\n\t#nop", file);
5392 if (set_noreorder++ == 0)
5393 fputs (".set\tnoreorder\n\t", file);
5397 if (set_noreorder == 0)
5398 error ("internal error: %%) found without a %%( in assembler pattern");
5400 else if (--set_noreorder == 0)
5401 fputs ("\n\t.set\treorder", file);
5406 if (set_noat++ == 0)
5407 fputs (".set\tnoat\n\t", file);
5412 error ("internal error: %%] found without a %%[ in assembler pattern");
5413 else if (--set_noat == 0)
5414 fputs ("\n\t.set\tat", file);
5419 if (set_nomacro++ == 0)
5420 fputs (".set\tnomacro\n\t", file);
5424 if (set_nomacro == 0)
5425 error ("internal error: %%> found without a %%< in assembler pattern");
5426 else if (--set_nomacro == 0)
5427 fputs ("\n\t.set\tmacro", file);
5432 if (set_volatile++ == 0)
5433 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5437 if (set_volatile == 0)
5438 error ("internal error: %%} found without a %%{ in assembler pattern");
5439 else if (--set_volatile == 0)
5440 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5446 if (align_labels_log > 0)
5447 ASM_OUTPUT_ALIGN (file, align_labels_log);
5452 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
5461 error ("PRINT_OPERAND null pointer");
5465 code = GET_CODE (op);
5467 if (code == SIGN_EXTEND)
5468 op = XEXP (op, 0), code = GET_CODE (op);
5473 case EQ: fputs ("eq", file); break;
5474 case NE: fputs ("ne", file); break;
5475 case GT: fputs ("gt", file); break;
5476 case GE: fputs ("ge", file); break;
5477 case LT: fputs ("lt", file); break;
5478 case LE: fputs ("le", file); break;
5479 case GTU: fputs ("gtu", file); break;
5480 case GEU: fputs ("geu", file); break;
5481 case LTU: fputs ("ltu", file); break;
5482 case LEU: fputs ("leu", file); break;
5484 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
5487 else if (letter == 'N')
5490 case EQ: fputs ("ne", file); break;
5491 case NE: fputs ("eq", file); break;
5492 case GT: fputs ("le", file); break;
5493 case GE: fputs ("lt", file); break;
5494 case LT: fputs ("ge", file); break;
5495 case LE: fputs ("gt", file); break;
5496 case GTU: fputs ("leu", file); break;
5497 case GEU: fputs ("ltu", file); break;
5498 case LTU: fputs ("geu", file); break;
5499 case LEU: fputs ("gtu", file); break;
5501 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
5504 else if (letter == 'F')
5507 case EQ: fputs ("c1f", file); break;
5508 case NE: fputs ("c1t", file); break;
5510 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
5513 else if (letter == 'W')
5516 case EQ: fputs ("c1t", file); break;
5517 case NE: fputs ("c1f", file); break;
5519 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
5522 else if (letter == 'S')
5526 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
5527 assemble_name (file, buffer);
5530 else if (letter == 'Z')
5532 register int regnum;
5537 regnum = REGNO (op);
5538 if (! ST_REG_P (regnum))
5541 if (regnum != ST_REG_FIRST)
5542 fprintf (file, "%s,", reg_names[regnum]);
5545 else if (code == REG || code == SUBREG)
5547 register int regnum;
5550 regnum = REGNO (op);
5552 regnum = true_regnum (op);
5554 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5555 || (letter == 'L' && WORDS_BIG_ENDIAN)
5559 fprintf (file, "%s", reg_names[regnum]);
5562 else if (code == MEM)
5565 output_address (plus_constant (XEXP (op, 0), 4));
5567 output_address (XEXP (op, 0));
5570 else if (code == CONST_DOUBLE
5571 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
5576 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
5577 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
5581 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5582 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5584 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5585 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5587 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5588 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5590 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
5591 fputs (reg_names[GP_REG_FIRST], file);
5593 else if (letter == 'd' || letter == 'x' || letter == 'X')
5594 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5596 else if (letter == 'B')
5597 fputs (code == EQ ? "z" : "n", file);
5598 else if (letter == 'b')
5599 fputs (code == EQ ? "n" : "z", file);
5600 else if (letter == 'T')
5601 fputs (code == EQ ? "f" : "t", file);
5602 else if (letter == 't')
5603 fputs (code == EQ ? "t" : "f", file);
5605 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
5607 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
5608 print_operand (file, XEXP (op, 0), letter);
5611 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
5613 fputs ("%gprel(", file);
5614 mips16_output_gp_offset (file, op);
5619 output_addr_const (file, op);
5622 /* A C compound statement to output to stdio stream STREAM the
5623 assembler syntax for an instruction operand that is a memory
5624 reference whose address is ADDR. ADDR is an RTL expression.
5626 On some machines, the syntax for a symbolic address depends on
5627 the section that the address refers to. On these machines,
5628 define the macro `ENCODE_SECTION_INFO' to store the information
5629 into the `symbol_ref', and then check for it here. */
5632 print_operand_address (file, addr)
5637 error ("PRINT_OPERAND_ADDRESS, null pointer");
5640 switch (GET_CODE (addr))
5643 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
5644 abort_with_insn (addr, "Arg pointer not eliminated.");
5646 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
5651 register rtx arg0 = XEXP (addr, 0);
5652 register rtx arg1 = XEXP (addr, 1);
5654 if (! mips_split_addresses)
5655 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
5657 if (GET_CODE (arg0) != REG)
5658 abort_with_insn (addr,
5659 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
5661 fprintf (file, "%%lo(");
5662 print_operand_address (file, arg1);
5663 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
5669 register rtx reg = 0;
5670 register rtx offset = 0;
5671 register rtx arg0 = XEXP (addr, 0);
5672 register rtx arg1 = XEXP (addr, 1);
5674 if (GET_CODE (arg0) == REG)
5678 if (GET_CODE (offset) == REG)
5679 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
5682 else if (GET_CODE (arg1) == REG)
5683 reg = arg1, offset = arg0;
5684 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
5686 output_addr_const (file, addr);
5690 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
5692 if (! CONSTANT_P (offset))
5693 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
5695 if (REGNO (reg) == ARG_POINTER_REGNUM)
5696 abort_with_insn (addr, "Arg pointer not eliminated.");
5699 && GET_CODE (offset) == CONST
5700 && mips16_gp_offset_p (offset))
5702 fputs ("%gprel(", file);
5703 mips16_output_gp_offset (file, offset);
5707 output_addr_const (file, offset);
5708 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
5716 output_addr_const (file, addr);
5720 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
5726 /* If optimizing for the global pointer, keep track of all of the externs, so
5727 that at the end of the file, we can emit the appropriate .extern
5728 declaration for them, before writing out the text section. We assume all
5729 names passed to us are in the permanent obstack, so they will be valid at
5730 the end of the compilation.
5732 If we have -G 0, or the extern size is unknown, or the object is in a user
5733 specified section that is not .sbss/.sdata, don't bother emitting the
5734 .externs. In the case of user specified sections this behaviour is
5735 required as otherwise GAS will think the object lives in .sbss/.sdata. */
5738 mips_output_external (file, decl, name)
5739 FILE *file ATTRIBUTE_UNUSED;
5743 register struct extern_list *p;
5748 && TREE_CODE (decl) != FUNCTION_DECL
5749 && (len = int_size_in_bytes (TREE_TYPE (decl))) > 0
5750 && ((section_name = DECL_SECTION_NAME (decl)) == NULL
5751 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5752 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5754 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5755 p->next = extern_head;
5761 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5762 if (TREE_CODE (decl) == FUNCTION_DECL
5763 /* ??? Don't include alloca, since gcc will always expand it
5764 inline. If we don't do this, the C++ library fails to build. */
5765 && strcmp (name, "alloca")
5766 /* ??? Don't include __builtin_next_arg, because then gcc will not
5767 bootstrap under Irix 5.1. */
5768 && strcmp (name, "__builtin_next_arg"))
5770 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5771 p->next = extern_head;
5781 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5783 mips_output_external_libcall (file, name)
5787 register struct extern_list *p;
5789 p = (struct extern_list *) permalloc (sizeof (struct extern_list));
5790 p->next = extern_head;
5799 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5800 for .file's that start within a function. If we are smuggling stabs, try to
5801 put out a MIPS ECOFF file and a stab. */
5804 mips_output_filename (stream, name)
5808 static int first_time = 1;
5809 char ltext_label_name[100];
5815 current_function_file = name;
5816 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5817 /* This tells mips-tfile that stabs will follow. */
5818 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5819 fprintf (stream, "\t#@stabs\n");
5822 else if (write_symbols == DBX_DEBUG)
5824 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5825 fprintf (stream, "%s", ASM_STABS_OP);
5826 output_quoted_string (stream, name);
5827 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5830 else if (name != current_function_file
5831 && strcmp (name, current_function_file) != 0)
5833 if (inside_function && !TARGET_GAS)
5835 if (!file_in_function_warning)
5837 file_in_function_warning = 1;
5838 ignore_line_number = 1;
5839 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5845 current_function_file = name;
5846 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5851 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5852 as well as a .loc, since it is possible that MIPS ECOFF might not be
5853 able to represent the location for inlines that come from a different
5857 mips_output_lineno (stream, line)
5861 if (write_symbols == DBX_DEBUG)
5864 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5865 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5866 LOCAL_LABEL_PREFIX, sym_lineno);
5871 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5872 (ignore_line_number) ? "#" : "",
5873 num_source_filenames, line);
5875 LABEL_AFTER_LOC (stream);
5879 /* Output an ASCII string, in a space-saving way. */
5882 mips_output_ascii (stream, string_param, len)
5884 const char *string_param;
5889 register const unsigned char *string =
5890 (const unsigned char *)string_param;
5892 fprintf (stream, "\t.ascii\t\"");
5893 for (i = 0; i < len; i++)
5895 register int c = string[i];
5901 putc ('\\', stream);
5906 case TARGET_NEWLINE:
5907 fputs ("\\n", stream);
5909 && (((c = string[i+1]) >= '\040' && c <= '~')
5910 || c == TARGET_TAB))
5911 cur_pos = 32767; /* break right here */
5917 fputs ("\\t", stream);
5922 fputs ("\\f", stream);
5927 fputs ("\\b", stream);
5932 fputs ("\\r", stream);
5937 if (c >= ' ' && c < 0177)
5944 fprintf (stream, "\\%03o", c);
5949 if (cur_pos > 72 && i+1 < len)
5952 fprintf (stream, "\"\n\t.ascii\t\"");
5955 fprintf (stream, "\"\n");
5958 /* If defined, a C statement to be executed just prior to the output of
5959 assembler code for INSN, to modify the extracted operands so they will be
5962 Here the argument OPVEC is the vector containing the operands extracted
5963 from INSN, and NOPERANDS is the number of elements of the vector which
5964 contain meaningful data for this insn. The contents of this vector are
5965 what will be used to convert the insn template into assembler code, so you
5966 can change the assembler output by changing the contents of the vector.
5968 We use it to check if the current insn needs a nop in front of it because
5969 of load delays, and also to update the delay slot statistics. */
5971 /* ??? There is no real need for this function, because it never actually
5972 emits a NOP anymore. */
5975 final_prescan_insn (insn, opvec, noperands)
5977 rtx opvec[] ATTRIBUTE_UNUSED;
5978 int noperands ATTRIBUTE_UNUSED;
5980 if (dslots_number_nops > 0)
5982 rtx pattern = PATTERN (insn);
5983 int length = get_attr_length (insn);
5985 /* Do we need to emit a NOP? */
5987 || (mips_load_reg != 0 && reg_mentioned_p (mips_load_reg, pattern))
5988 || (mips_load_reg2 != 0 && reg_mentioned_p (mips_load_reg2, pattern))
5989 || (mips_load_reg3 != 0 && reg_mentioned_p (mips_load_reg3, pattern))
5990 || (mips_load_reg4 != 0
5991 && reg_mentioned_p (mips_load_reg4, pattern)))
5992 fputs ("\t#nop\n", asm_out_file);
5995 dslots_load_filled++;
5997 while (--dslots_number_nops > 0)
5998 fputs ("\t#nop\n", asm_out_file);
6007 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
6008 dslots_jump_total++;
6011 /* Output at beginning of assembler file.
6013 If we are optimizing to use the global pointer, create a temporary file to
6014 hold all of the text stuff, and write it out to the end. This is needed
6015 because the MIPS assembler is evidently one pass, and if it hasn't seen the
6016 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
6017 processed, it generates a two instruction sequence. */
6020 mips_asm_file_start (stream)
6023 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
6025 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
6026 inside of a .set noreorder section jumps to a label outside of the .set
6027 noreorder section. Revision 2.20 just set nobopt silently rather than
6030 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
6031 fprintf (stream, "\t.set\tnobopt\n");
6033 /* Generate the pseudo ops that System V.4 wants. */
6034 #ifndef ABICALLS_ASM_OP
6035 #define ABICALLS_ASM_OP "\t.abicalls"
6037 if (TARGET_ABICALLS)
6038 /* ??? but do not want this (or want pic0) if -non-shared? */
6039 fprintf (stream, "%s\n", ABICALLS_ASM_OP);
6042 fprintf (stream, "\t.set\tmips16\n");
6044 /* This code exists so that we can put all externs before all symbol
6045 references. This is necessary for the MIPS assembler's global pointer
6046 optimizations to work. */
6047 if (TARGET_FILE_SWITCHING)
6049 asm_out_data_file = stream;
6050 asm_out_text_file = tmpfile ();
6053 asm_out_data_file = asm_out_text_file = stream;
6055 if (flag_verbose_asm)
6056 fprintf (stream, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
6058 mips_section_threshold, mips_arch_string, mips_isa);
6061 /* If we are optimizing the global pointer, emit the text section now and any
6062 small externs which did not have .comm, etc that are needed. Also, give a
6063 warning if the data area is more than 32K and -pic because 3 instructions
6064 are needed to reference the data pointers. */
6067 mips_asm_file_end (file)
6071 struct extern_list *p;
6075 HALF_PIC_FINISH (file);
6082 for (p = extern_head; p != 0; p = p->next)
6084 name_tree = get_identifier (p->name);
6086 /* Positively ensure only one .extern for any given symbol. */
6087 if (! TREE_ASM_WRITTEN (name_tree))
6089 TREE_ASM_WRITTEN (name_tree) = 1;
6090 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
6092 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
6096 fputs ("\t.extern\t", file);
6097 assemble_name (file, p->name);
6098 fprintf (file, ", %d\n", p->size);
6104 if (TARGET_FILE_SWITCHING)
6106 fprintf (file, "\n\t.text\n");
6107 copy_file_data (file, asm_out_text_file);
6112 copy_file_data (to, from)
6120 fatal_io_error ("can't rewind temp file");
6122 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
6123 if (fwrite (buffer, 1, len, to) != len)
6124 fatal_io_error ("can't write to output file");
6127 fatal_io_error ("can't read from temp file");
6130 fatal_io_error ("can't close temp file");
6133 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
6134 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
6137 mips_declare_object (stream, name, init_string, final_string, size)
6140 const char *init_string;
6141 const char *final_string;
6144 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
6145 assemble_name (stream, name);
6146 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
6150 tree name_tree = get_identifier (name);
6151 TREE_ASM_WRITTEN (name_tree) = 1;
6155 /* Output a double precision value to the assembler. If both the
6156 host and target are IEEE, emit the values in hex. */
6159 mips_output_double (stream, value)
6161 REAL_VALUE_TYPE value;
6163 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
6165 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
6167 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
6168 value_long[0], value, value_long[1]);
6170 fprintf (stream, "\t.double\t%.20g\n", value);
6174 /* Output a single precision value to the assembler. If both the
6175 host and target are IEEE, emit the values in hex. */
6178 mips_output_float (stream, value)
6180 REAL_VALUE_TYPE value;
6182 #ifdef REAL_VALUE_TO_TARGET_SINGLE
6184 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
6186 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
6188 fprintf (stream, "\t.float\t%.12g\n", value);
6192 /* Return the bytes needed to compute the frame pointer from the current
6195 Mips stack frames look like:
6197 Before call After call
6198 +-----------------------+ +-----------------------+
6201 | caller's temps. | | caller's temps. |
6203 +-----------------------+ +-----------------------+
6205 | arguments on stack. | | arguments on stack. |
6207 +-----------------------+ +-----------------------+
6208 | 4 words to save | | 4 words to save |
6209 | arguments passed | | arguments passed |
6210 | in registers, even | | in registers, even |
6211 SP->| if not passed. | VFP->| if not passed. |
6212 +-----------------------+ +-----------------------+
6214 | fp register save |
6216 +-----------------------+
6218 | gp register save |
6220 +-----------------------+
6224 +-----------------------+
6226 | alloca allocations |
6228 +-----------------------+
6230 | GP save for V.4 abi |
6232 +-----------------------+
6234 | arguments on stack |
6236 +-----------------------+
6238 | arguments passed |
6239 | in registers, even |
6240 low SP->| if not passed. |
6241 memory +-----------------------+
6246 compute_frame_size (size)
6247 HOST_WIDE_INT size; /* # of var. bytes allocated */
6250 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6251 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6252 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6253 HOST_WIDE_INT extra_size; /* # extra bytes */
6254 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6255 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6256 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6257 long mask; /* mask of saved gp registers */
6258 long fmask; /* mask of saved fp registers */
6259 int fp_inc; /* 1 or 2 depending on the size of fp regs */
6260 long fp_bits; /* bitmask to use for each fp register */
6266 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
6267 var_size = MIPS_STACK_ALIGN (size);
6268 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
6270 /* The MIPS 3.0 linker does not like functions that dynamically
6271 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6272 looks like we are trying to create a second frame pointer to the
6273 function, so allocate some stack space to make it happy. */
6275 if (args_size == 0 && current_function_calls_alloca)
6276 args_size = 4 * UNITS_PER_WORD;
6278 total_size = var_size + args_size + extra_size;
6280 /* Calculate space needed for gp registers. */
6281 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6283 /* $18 is a special case on the mips16. It may be used to call
6284 a function which returns a floating point value, but it is
6285 marked in call_used_regs. $31 is also a special case. When
6286 not using -mentry, it will be used to copy a return value
6287 into the floating point registers if the return value is
6289 if (MUST_SAVE_REGISTER (regno)
6291 && regno == GP_REG_FIRST + 18
6292 && regs_ever_live[regno])
6294 && regno == GP_REG_FIRST + 31
6295 && mips16_hard_float
6297 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6298 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6300 && (! TARGET_SINGLE_FLOAT
6301 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6304 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6305 mask |= 1L << (regno - GP_REG_FIRST);
6307 /* The entry and exit pseudo instructions can not save $17
6308 without also saving $16. */
6310 && regno == GP_REG_FIRST + 17
6311 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
6313 gp_reg_size += UNITS_PER_WORD;
6319 /* We need to restore these for the handler. */
6320 if (current_function_calls_eh_return)
6325 regno = EH_RETURN_DATA_REGNO (i);
6326 if (regno == INVALID_REGNUM)
6328 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6329 mask |= 1L << (regno - GP_REG_FIRST);
6333 /* Calculate space needed for fp registers. */
6334 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
6345 /* This loop must iterate over the same space as its companion in
6346 save_restore_regs. */
6347 for (regno = (FP_REG_LAST - fp_inc + 1);
6348 regno >= FP_REG_FIRST;
6351 if (regs_ever_live[regno] && !call_used_regs[regno])
6353 fp_reg_size += fp_inc * UNITS_PER_FPREG;
6354 fmask |= fp_bits << (regno - FP_REG_FIRST);
6358 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6359 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6361 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
6362 for leaf routines (total_size == extra_size) to save the gp reg.
6363 The gp reg is callee saved in the 64 bit ABI, so all routines must
6364 save the gp reg. This is not a leaf routine if -p, because of the
6366 if (total_size == extra_size
6367 && (mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI)
6369 total_size = extra_size = 0;
6370 else if (TARGET_ABICALLS)
6372 /* Add the context-pointer to the saved registers. */
6373 gp_reg_size += UNITS_PER_WORD;
6374 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
6375 total_size -= gp_reg_rounded;
6376 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6377 total_size += gp_reg_rounded;
6380 /* Add in space reserved on the stack by the callee for storing arguments
6381 passed in registers. */
6382 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
6383 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6385 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
6386 if (mips_entry && total_size > 0 && total_size < 32)
6389 /* Save other computed information. */
6390 current_frame_info.total_size = total_size;
6391 current_frame_info.var_size = var_size;
6392 current_frame_info.args_size = args_size;
6393 current_frame_info.extra_size = extra_size;
6394 current_frame_info.gp_reg_size = gp_reg_size;
6395 current_frame_info.fp_reg_size = fp_reg_size;
6396 current_frame_info.mask = mask;
6397 current_frame_info.fmask = fmask;
6398 current_frame_info.initialized = reload_completed;
6399 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
6400 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
6404 unsigned long offset;
6406 /* When using mips_entry, the registers are always saved at the
6407 top of the stack. */
6409 offset = (args_size + extra_size + var_size
6410 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6412 offset = total_size - GET_MODE_SIZE (gpr_mode);
6414 current_frame_info.gp_sp_offset = offset;
6415 current_frame_info.gp_save_offset = offset - total_size;
6419 current_frame_info.gp_sp_offset = 0;
6420 current_frame_info.gp_save_offset = 0;
6425 unsigned long offset = (args_size + extra_size + var_size
6426 + gp_reg_rounded + fp_reg_size
6427 - fp_inc * UNITS_PER_FPREG);
6428 current_frame_info.fp_sp_offset = offset;
6429 current_frame_info.fp_save_offset = offset - total_size;
6433 current_frame_info.fp_sp_offset = 0;
6434 current_frame_info.fp_save_offset = 0;
6437 /* Ok, we're done. */
6441 /* Common code to emit the insns (or to write the instructions to a file)
6442 to save/restore registers.
6444 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
6445 is not modified within save_restore_insns. */
6447 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
6449 /* Emit instructions to load the value (SP + OFFSET) into MIPS_TEMP2_REGNUM
6450 and return an rtl expression for the register. Write the assembly
6451 instructions directly to FILE if it is not null, otherwise emit them as
6454 This function is a subroutine of save_restore_insns. It is used when
6455 OFFSET is too large to add in a single instruction. */
6458 mips_add_large_offset_to_sp (offset, file)
6459 HOST_WIDE_INT offset;
6462 rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6465 rtx offset_rtx = GEN_INT (offset);
6467 emit_move_insn (reg, offset_rtx);
6468 if (Pmode == DImode)
6469 emit_insn (gen_adddi3 (reg, reg, stack_pointer_rtx));
6471 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
6475 fprintf (file, "\tli\t%s,0x%.08lx\t# ",
6476 reg_names[MIPS_TEMP2_REGNUM], (long) offset);
6477 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
6478 fprintf (file, "\n\t%s\t%s,%s,%s\n",
6479 Pmode == DImode ? "daddu" : "addu",
6480 reg_names[MIPS_TEMP2_REGNUM],
6481 reg_names[MIPS_TEMP2_REGNUM],
6482 reg_names[STACK_POINTER_REGNUM]);
6487 /* Make INSN frame related and note that it performs the frame-related
6488 operation DWARF_PATTERN. */
6491 mips_annotate_frame_insn (insn, dwarf_pattern)
6492 rtx insn, dwarf_pattern;
6494 RTX_FRAME_RELATED_P (insn) = 1;
6495 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6500 /* Emit a move instruction that stores REG in MEM. Make the instruction
6501 frame related and note that it stores REG at (SP + OFFSET). */
6504 mips_emit_frame_related_store (mem, reg, offset)
6507 HOST_WIDE_INT offset;
6509 rtx dwarf_address = plus_constant (stack_pointer_rtx, offset);
6510 rtx dwarf_mem = gen_rtx_MEM (GET_MODE (reg), dwarf_address);
6512 mips_annotate_frame_insn (emit_move_insn (mem, reg),
6513 gen_rtx_SET (GET_MODE (reg), dwarf_mem, reg));
6517 save_restore_insns (store_p, large_reg, large_offset, file)
6518 int store_p; /* true if this is prologue */
6519 rtx large_reg; /* register holding large offset constant or NULL */
6520 long large_offset; /* large constant offset value */
6521 FILE *file; /* file to write instructions instead of making RTL */
6523 long mask = current_frame_info.mask;
6524 long fmask = current_frame_info.fmask;
6527 HOST_WIDE_INT base_offset;
6528 HOST_WIDE_INT gp_offset;
6529 HOST_WIDE_INT fp_offset;
6530 HOST_WIDE_INT end_offset;
6533 if (frame_pointer_needed
6534 && ! BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
6537 if (mask == 0 && fmask == 0)
6540 /* Save registers starting from high to low. The debuggers prefer at least
6541 the return register be stored at func+4, and also it allows us not to
6542 need a nop in the epilog if at least one register is reloaded in
6543 addition to return address. */
6545 /* Save GP registers if needed. */
6548 /* Pick which pointer to use as a base register. For small frames, just
6549 use the stack pointer. Otherwise, use a temporary register. Save 2
6550 cycles if the save area is near the end of a large frame, by reusing
6551 the constant created in the prologue/epilogue to adjust the stack
6554 gp_offset = current_frame_info.gp_sp_offset;
6556 = gp_offset - (current_frame_info.gp_reg_size
6557 - GET_MODE_SIZE (gpr_mode));
6559 if (gp_offset < 0 || end_offset < 0)
6561 ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
6562 (long) gp_offset, (long) end_offset);
6564 /* If we see a large frame in mips16 mode, we save the registers
6565 before adjusting the stack pointer, and load them afterward. */
6566 else if (TARGET_MIPS16 && large_offset > 32767)
6567 base_reg_rtx = stack_pointer_rtx, base_offset = large_offset;
6569 else if (gp_offset < 32768)
6570 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6572 else if (large_reg != 0
6573 && (unsigned HOST_WIDE_INT) (large_offset - gp_offset) < 32768
6574 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6576 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6577 base_offset = large_offset;
6580 if (Pmode == DImode)
6581 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6582 stack_pointer_rtx));
6584 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6585 stack_pointer_rtx));
6588 fprintf (file, "\t%s\t%s,%s,%s\n",
6589 Pmode == DImode ? "daddu" : "addu",
6590 reg_names[MIPS_TEMP2_REGNUM],
6591 reg_names[REGNO (large_reg)],
6592 reg_names[STACK_POINTER_REGNUM]);
6596 base_offset = gp_offset;
6597 base_reg_rtx = mips_add_large_offset_to_sp (base_offset, file);
6600 /* When we restore the registers in MIPS16 mode, then if we are
6601 using a frame pointer, and this is not a large frame, the
6602 current stack pointer will be offset by
6603 current_function_outgoing_args_size. Doing it this way lets
6604 us avoid offsetting the frame pointer before copying it into
6605 the stack pointer; there is no instruction to set the stack
6606 pointer to the sum of a register and a constant. */
6609 && frame_pointer_needed
6610 && large_offset <= 32767)
6611 base_offset += current_function_outgoing_args_size;
6613 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6614 if (BITSET_P (mask, regno - GP_REG_FIRST))
6620 = gen_rtx (MEM, gpr_mode,
6621 gen_rtx (PLUS, Pmode, base_reg_rtx,
6622 GEN_INT (gp_offset - base_offset)));
6624 if (! current_function_calls_eh_return)
6625 RTX_UNCHANGING_P (mem_rtx) = 1;
6627 /* The mips16 does not have an instruction to load
6628 $31, so we load $7 instead, and work things out
6630 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
6631 reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 7);
6632 /* The mips16 sometimes needs to save $18. */
6633 else if (TARGET_MIPS16
6634 && regno != GP_REG_FIRST + 31
6635 && ! M16_REG_P (regno))
6638 reg_rtx = gen_rtx (REG, gpr_mode, 6);
6641 reg_rtx = gen_rtx (REG, gpr_mode, 3);
6642 emit_move_insn (reg_rtx,
6643 gen_rtx (REG, gpr_mode, regno));
6647 reg_rtx = gen_rtx (REG, gpr_mode, regno);
6650 mips_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
6651 else if (!TARGET_ABICALLS
6652 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6653 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6655 emit_move_insn (reg_rtx, mem_rtx);
6657 && regno != GP_REG_FIRST + 31
6658 && ! M16_REG_P (regno))
6659 emit_move_insn (gen_rtx (REG, gpr_mode, regno),
6665 if (store_p || !TARGET_ABICALLS
6666 || (mips_abi != ABI_32 && mips_abi != ABI_O64)
6667 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6671 /* The mips16 does not have an instruction to
6672 load $31, so we load $7 instead, and work
6673 things out in the caller. */
6674 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
6675 r = GP_REG_FIRST + 7;
6676 /* The mips16 sometimes needs to save $18. */
6678 && regno != GP_REG_FIRST + 31
6679 && ! M16_REG_P (regno))
6682 r = GP_REG_FIRST + 6;
6685 r = GP_REG_FIRST + 3;
6686 fprintf (file, "\tmove\t%s,%s\n",
6687 reg_names[r], reg_names[regno]);
6690 fprintf (file, "\t%s\t%s,",
6692 ? (store_p) ? "sd" : "ld"
6693 : (store_p) ? "sw" : "lw"),
6695 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6696 gp_offset - base_offset);
6697 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6700 && regno != GP_REG_FIRST + 31
6701 && ! M16_REG_P (regno))
6702 fprintf (file, "\tmove\t%s,%s\n",
6703 reg_names[regno], reg_names[r]);
6707 gp_offset -= GET_MODE_SIZE (gpr_mode);
6711 base_reg_rtx = 0, base_offset = 0;
6713 /* Save floating point registers if needed. */
6716 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
6717 int fp_size = fp_inc * UNITS_PER_FPREG;
6719 /* Pick which pointer to use as a base register. */
6720 fp_offset = current_frame_info.fp_sp_offset;
6721 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
6723 if (fp_offset < 0 || end_offset < 0)
6725 ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
6726 (long) fp_offset, (long) end_offset);
6728 else if (fp_offset < 32768)
6729 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
6731 else if (base_reg_rtx != 0
6732 && (unsigned HOST_WIDE_INT) (base_offset - fp_offset) < 32768
6733 && (unsigned HOST_WIDE_INT) (base_offset - end_offset) < 32768)
6734 ; /* already set up for gp registers above */
6736 else if (large_reg != 0
6737 && (unsigned HOST_WIDE_INT) (large_offset - fp_offset) < 32768
6738 && (unsigned HOST_WIDE_INT) (large_offset - end_offset) < 32768)
6740 base_reg_rtx = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
6741 base_offset = large_offset;
6744 if (Pmode == DImode)
6745 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg,
6746 stack_pointer_rtx));
6748 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg,
6749 stack_pointer_rtx));
6753 fprintf (file, "\t%s\t%s,%s,%s\n",
6754 Pmode == DImode ? "daddu" : "addu",
6755 reg_names[MIPS_TEMP2_REGNUM],
6756 reg_names[REGNO (large_reg)],
6757 reg_names[STACK_POINTER_REGNUM]);
6761 base_offset = fp_offset;
6762 base_reg_rtx = mips_add_large_offset_to_sp (fp_offset, file);
6765 /* This loop must iterate over the same space as its companion in
6766 compute_frame_size. */
6767 for (regno = (FP_REG_LAST - fp_inc + 1);
6768 regno >= FP_REG_FIRST;
6770 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6774 enum machine_mode sz
6775 = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6776 rtx reg_rtx = gen_rtx (REG, sz, regno);
6777 rtx mem_rtx = gen_rtx (MEM, sz,
6778 gen_rtx (PLUS, Pmode, base_reg_rtx,
6781 if (! current_function_calls_eh_return)
6782 RTX_UNCHANGING_P (mem_rtx) = 1;
6785 mips_emit_frame_related_store (mem_rtx, reg_rtx, fp_offset);
6787 emit_move_insn (reg_rtx, mem_rtx);
6791 fprintf (file, "\t%s\t%s,",
6792 (TARGET_SINGLE_FLOAT
6793 ? (store_p ? "s.s" : "l.s")
6794 : (store_p ? "s.d" : "l.d")),
6796 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
6797 fp_offset - base_offset);
6798 fprintf (file, "(%s)\n", reg_names[REGNO(base_reg_rtx)]);
6801 fp_offset -= fp_size;
6806 /* Set up the stack and frame (if desired) for the function. */
6809 mips_output_function_prologue (file, size)
6811 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
6813 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6816 long tsize = current_frame_info.total_size;
6818 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6820 #ifdef SDB_DEBUGGING_INFO
6821 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6822 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6825 /* In mips16 mode, we may need to generate a 32 bit to handle
6826 floating point arguments. The linker will arrange for any 32 bit
6827 functions to call this stub, which will then jump to the 16 bit
6829 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6830 && current_function_args_info.fp_code != 0)
6831 build_mips16_function_stub (file);
6833 inside_function = 1;
6835 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6836 /* Get the function name the same way that toplev.c does before calling
6837 assemble_start_function. This is needed so that the name used here
6838 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6839 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6841 if (!flag_inhibit_size_directive)
6843 fputs ("\t.ent\t", file);
6844 assemble_name (file, fnname);
6848 assemble_name (file, fnname);
6849 fputs (":\n", file);
6852 if (!flag_inhibit_size_directive)
6854 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6856 "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6857 (reg_names[(frame_pointer_needed)
6858 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6859 ((frame_pointer_needed && TARGET_MIPS16)
6860 ? (tsize - current_function_outgoing_args_size)
6862 reg_names[31 + GP_REG_FIRST],
6863 current_frame_info.var_size,
6864 current_frame_info.num_gp,
6865 current_frame_info.num_fp,
6866 current_function_outgoing_args_size,
6867 current_frame_info.extra_size);
6869 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6870 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6871 current_frame_info.mask,
6872 current_frame_info.gp_save_offset,
6873 current_frame_info.fmask,
6874 current_frame_info.fp_save_offset);
6877 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6878 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6881 if (mips_entry && ! mips_can_use_return_insn ())
6883 int save16 = BITSET_P (current_frame_info.mask, 16);
6884 int save17 = BITSET_P (current_frame_info.mask, 17);
6885 int save31 = BITSET_P (current_frame_info.mask, 31);
6889 /* Look through the initial insns to see if any of them store
6890 the function parameters into the incoming parameter storage
6891 area. If they do, we delete the insn, and save the register
6892 using the entry pseudo-instruction instead. We don't try to
6893 look past a label, jump, or call. */
6894 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6896 rtx note, set, src, dest, base, offset;
6899 if (GET_CODE (insn) == CODE_LABEL
6900 || GET_CODE (insn) == JUMP_INSN
6901 || GET_CODE (insn) == CALL_INSN)
6903 if (GET_CODE (insn) != INSN)
6905 set = PATTERN (insn);
6906 if (GET_CODE (set) != SET)
6909 /* An insn storing a function parameter will still have a
6910 REG_EQUIV note on it mentioning the argument pointer. */
6911 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6912 if (note == NULL_RTX)
6914 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6917 src = SET_SRC (set);
6918 if (GET_CODE (src) != REG
6919 || REGNO (src) < GP_REG_FIRST + 4
6920 || REGNO (src) > GP_REG_FIRST + 7)
6923 dest = SET_DEST (set);
6924 if (GET_CODE (dest) != MEM)
6926 if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned) UNITS_PER_WORD)
6928 else if (GET_MODE_SIZE (GET_MODE (dest)) == (unsigned)2 * UNITS_PER_WORD
6929 && REGNO (src) < GP_REG_FIRST + 7)
6933 offset = const0_rtx;
6934 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6935 if (GET_CODE (base) != REG
6936 || GET_CODE (offset) != CONST_INT)
6938 if (REGNO (base) == (unsigned) STACK_POINTER_REGNUM
6939 && (unsigned HOST_WIDE_INT) INTVAL (offset)
6940 == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6942 else if (REGNO (base) == (unsigned) HARD_FRAME_POINTER_REGNUM
6943 && ((unsigned HOST_WIDE_INT) INTVAL (offset)
6945 + (REGNO (src) - 4) * UNITS_PER_WORD
6946 - current_function_outgoing_args_size)))
6951 /* This insn stores a parameter onto the stack, in the same
6952 location where the entry pseudo-instruction will put it.
6953 Delete the insn, and arrange to tell the entry
6954 instruction to save the register. */
6955 PUT_CODE (insn, NOTE);
6956 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6957 NOTE_SOURCE_FILE (insn) = 0;
6959 hireg = (REGNO (src)
6960 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6962 if (hireg > savearg)
6966 /* If this is a varargs function, we need to save all the
6967 registers onto the stack anyhow. */
6968 if (current_function_stdarg || current_function_varargs)
6969 savearg = GP_REG_FIRST + 7;
6971 fprintf (file, "\tentry\t");
6974 if (savearg == GP_REG_FIRST + 4)
6975 fprintf (file, "%s", reg_names[savearg]);
6977 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6978 reg_names[savearg]);
6980 if (save16 || save17)
6983 fprintf (file, ",");
6984 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6986 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6990 if (savearg > 0 || save16 || save17)
6991 fprintf (file, ",");
6992 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6994 fprintf (file, "\n");
6997 if (TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64))
6999 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
7001 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
7002 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
7005 fprintf (file, "\t%s\t%s,%s,%ld\n",
7006 (Pmode == DImode ? "dsubu" : "subu"),
7007 sp_str, sp_str, tsize);
7008 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
7011 if (dwarf2out_do_frame ())
7012 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
7016 /* Expand the prologue into a bunch of separate insns. */
7019 mips_expand_prologue ()
7022 HOST_WIDE_INT tsize;
7024 int last_arg_is_vararg_marker = 0;
7025 tree fndecl = current_function_decl;
7026 tree fntype = TREE_TYPE (fndecl);
7027 tree fnargs = DECL_ARGUMENTS (fndecl);
7032 CUMULATIVE_ARGS args_so_far;
7033 rtx reg_18_save = NULL_RTX;
7034 int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
7035 && (! mips_entry || mips_can_use_return_insn ());
7037 /* If struct value address is treated as the first argument, make it so. */
7038 if (aggregate_value_p (DECL_RESULT (fndecl))
7039 && ! current_function_returns_pcc_struct
7040 && struct_value_incoming_rtx == 0)
7042 tree type = build_pointer_type (fntype);
7043 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
7045 DECL_ARG_TYPE (function_result_decl) = type;
7046 TREE_CHAIN (function_result_decl) = fnargs;
7047 fnargs = function_result_decl;
7050 /* For arguments passed in registers, find the register number
7051 of the first argument in the variable part of the argument list,
7052 otherwise GP_ARG_LAST+1. Note also if the last argument is
7053 the varargs special argument, and treat it as part of the
7056 This is only needed if store_args_on_stack is true. */
7058 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0);
7059 regno = GP_ARG_FIRST;
7061 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
7063 tree passed_type = DECL_ARG_TYPE (cur_arg);
7064 enum machine_mode passed_mode = TYPE_MODE (passed_type);
7067 if (TREE_ADDRESSABLE (passed_type))
7069 passed_type = build_pointer_type (passed_type);
7070 passed_mode = Pmode;
7073 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
7075 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
7076 next_arg = TREE_CHAIN (cur_arg);
7078 if (entry_parm && store_args_on_stack)
7081 && DECL_NAME (cur_arg)
7082 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7083 "__builtin_va_alist"))
7084 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
7087 last_arg_is_vararg_marker = 1;
7094 if (GET_CODE (entry_parm) != REG)
7097 /* passed in a register, so will get homed automatically */
7098 if (GET_MODE (entry_parm) == BLKmode)
7099 words = (int_size_in_bytes (passed_type) + 3) / 4;
7101 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
7103 regno = REGNO (entry_parm) + words - 1;
7108 regno = GP_ARG_LAST+1;
7113 /* In order to pass small structures by value in registers compatibly with
7114 the MIPS compiler, we need to shift the value into the high part of the
7115 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
7116 adjustments to be made as the next_arg_reg variable, so we split up the
7117 insns, and emit them separately. */
7119 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
7120 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
7122 rtvec adjust = XVEC (next_arg_reg, 0);
7123 int num = GET_NUM_ELEM (adjust);
7125 for (i = 0; i < num; i++)
7129 pattern = RTVEC_ELT (adjust, i);
7130 if (GET_CODE (pattern) != SET
7131 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
7132 abort_with_insn (pattern, "Insn is not a shift");
7133 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
7135 insn = emit_insn (pattern);
7137 /* Global life information isn't valid at this point, so we
7138 can't check whether these shifts are actually used. Mark
7139 them MAYBE_DEAD so that flow2 will remove them, and not
7140 complain about dead code in the prologue. */
7141 REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
7146 tsize = compute_frame_size (get_frame_size ());
7148 /* If this function is a varargs function, store any registers that
7149 would normally hold arguments ($4 - $7) on the stack. */
7150 if (store_args_on_stack
7151 && ((TYPE_ARG_TYPES (fntype) != 0
7152 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
7154 || last_arg_is_vararg_marker))
7156 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
7157 rtx ptr = stack_pointer_rtx;
7159 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
7160 if (TARGET_ABICALLS)
7163 for (; regno <= GP_ARG_LAST; regno++)
7166 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
7167 emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
7168 gen_rtx (REG, gpr_mode, regno));
7170 offset += GET_MODE_SIZE (gpr_mode);
7174 /* If we are using the entry pseudo instruction, it will
7175 automatically subtract 32 from the stack pointer, so we don't
7176 need to. The entry pseudo instruction is emitted by
7177 function_prologue. */
7178 if (mips_entry && ! mips_can_use_return_insn ())
7180 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
7184 /* If we are using a frame pointer with a small stack frame,
7185 we need to initialize it here since it won't be done
7187 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7189 rtx incr = GEN_INT (current_function_outgoing_args_size);
7190 if (Pmode == DImode)
7191 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7195 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7199 else if (Pmode == DImode)
7200 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7201 stack_pointer_rtx));
7203 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7204 stack_pointer_rtx));
7206 RTX_FRAME_RELATED_P (insn) = 1;
7209 /* We may need to save $18, if it is used to call a function
7210 which may return a floating point value. Set up a sequence
7211 of instructions to do so. Later on we emit them at the right
7213 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
7215 rtx reg_rtx = gen_rtx (REG, gpr_mode, GP_REG_FIRST + 3);
7216 long gp_offset, base_offset;
7218 gp_offset = current_frame_info.gp_sp_offset;
7219 if (BITSET_P (current_frame_info.mask, 16))
7220 gp_offset -= UNITS_PER_WORD;
7221 if (BITSET_P (current_frame_info.mask, 17))
7222 gp_offset -= UNITS_PER_WORD;
7223 if (BITSET_P (current_frame_info.mask, 31))
7224 gp_offset -= UNITS_PER_WORD;
7226 base_offset = tsize;
7230 emit_move_insn (reg_rtx,
7231 gen_rtx (REG, gpr_mode, GP_REG_FIRST + 18));
7232 emit_move_insn (gen_rtx (MEM, gpr_mode,
7233 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
7237 reg_18_save = gen_sequence ();
7246 if (reg_18_save != NULL_RTX)
7247 emit_insn (reg_18_save);
7253 rtx tsize_rtx = GEN_INT (tsize);
7255 /* If we are doing svr4-abi, sp move is done by
7256 function_prologue. In mips16 mode with a large frame, we
7257 save the registers before adjusting the stack. */
7258 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7259 && (!TARGET_MIPS16 || tsize <= 32767))
7261 rtx adjustment_rtx, insn, dwarf_pattern;
7265 adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
7266 emit_move_insn (adjustment_rtx, tsize_rtx);
7269 adjustment_rtx = tsize_rtx;
7271 if (Pmode == DImode)
7272 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7275 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
7278 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
7279 plus_constant (stack_pointer_rtx,
7282 mips_annotate_frame_insn (insn, dwarf_pattern);
7286 save_restore_insns (1, tmp_rtx, tsize, (FILE *)0);
7287 else if (reg_18_save != NULL_RTX)
7288 emit_insn (reg_18_save);
7290 if ((!TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7296 if (!frame_pointer_needed)
7299 reg_rtx = gen_rtx (REG, Pmode, 3);
7300 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
7301 emit_move_insn (reg_rtx, tsize_rtx);
7302 if (Pmode == DImode)
7303 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
7304 hard_frame_pointer_rtx,
7307 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
7308 hard_frame_pointer_rtx,
7310 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
7313 if (frame_pointer_needed)
7317 /* On the mips16, we encourage the use of unextended
7318 instructions when using the frame pointer by pointing the
7319 frame pointer ahead of the argument space allocated on
7321 if ((! TARGET_ABICALLS || (mips_abi != ABI_32 && mips_abi != ABI_O64))
7325 /* In this case, we have already copied the stack
7326 pointer into the frame pointer, above. We need only
7327 adjust for the outgoing argument size. */
7328 if (current_function_outgoing_args_size != 0)
7330 rtx incr = GEN_INT (current_function_outgoing_args_size);
7331 if (Pmode == DImode)
7332 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7333 hard_frame_pointer_rtx,
7336 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7337 hard_frame_pointer_rtx,
7341 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
7343 rtx incr = GEN_INT (current_function_outgoing_args_size);
7344 if (Pmode == DImode)
7345 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7349 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7353 else if (Pmode == DImode)
7354 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx,
7355 stack_pointer_rtx));
7357 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
7358 stack_pointer_rtx));
7361 RTX_FRAME_RELATED_P (insn) = 1;
7364 if (TARGET_ABICALLS && (mips_abi != ABI_32 && mips_abi != ABI_O64))
7365 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
7366 gen_rtx_REG (DImode, 25)));
7369 /* If we are profiling, make sure no instructions are scheduled before
7370 the call to mcount. */
7372 if (profile_flag || profile_block_flag)
7373 emit_insn (gen_blockage ());
7376 /* Do any necessary cleanup after a function to restore stack, frame,
7379 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
7380 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
7383 mips_output_function_epilogue (file, size)
7384 FILE *file ATTRIBUTE_UNUSED;
7385 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
7387 const char *fnname = ""; /* FIXME: Correct initialisation? */
7389 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7390 /* Get the function name the same way that toplev.c does before calling
7391 assemble_start_function. This is needed so that the name used here
7392 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
7393 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7395 if (!flag_inhibit_size_directive)
7397 fputs ("\t.end\t", file);
7398 assemble_name (file, fnname);
7405 int num_gp_regs = current_frame_info.gp_reg_size / 4;
7406 int num_fp_regs = current_frame_info.fp_reg_size / 8;
7407 int num_regs = num_gp_regs + num_fp_regs;
7408 const char *name = fnname;
7413 dslots_load_total += num_regs;
7416 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3d reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
7417 name, frame_pointer_needed ? 'y' : 'n',
7418 (current_frame_info.mask & RA_MASK) != 0 ? 'n' : 'y',
7419 current_function_calls_alloca ? 'y' : 'n',
7420 current_function_calls_setjmp ? 'y' : 'n',
7421 current_frame_info.total_size,
7422 current_function_outgoing_args_size, num_gp_regs, num_fp_regs,
7423 dslots_load_total, dslots_load_filled,
7424 dslots_jump_total, dslots_jump_filled,
7425 num_refs[0], num_refs[1], num_refs[2]);
7427 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
7430 " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
7431 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
7434 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
7437 " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
7438 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
7441 fputc ('\n', stderr);
7444 /* Reset state info for each function. */
7445 inside_function = 0;
7446 ignore_line_number = 0;
7447 dslots_load_total = 0;
7448 dslots_jump_total = 0;
7449 dslots_load_filled = 0;
7450 dslots_jump_filled = 0;
7456 current_frame_info = zero_frame_info;
7458 while (string_constants != NULL)
7460 struct string_constant *next;
7462 next = string_constants->next;
7463 free (string_constants);
7464 string_constants = next;
7467 /* Restore the output file if optimizing the GP (optimizing the GP causes
7468 the text to be diverted to a tempfile, so that data decls come before
7469 references to the data). */
7470 if (TARGET_FILE_SWITCHING)
7472 asm_out_file = asm_out_data_file;
7477 /* Expand the epilogue into a bunch of separate insns. */
7480 mips_expand_epilogue ()
7482 HOST_WIDE_INT tsize = current_frame_info.total_size;
7483 rtx tsize_rtx = GEN_INT (tsize);
7484 rtx tmp_rtx = (rtx)0;
7486 if (mips_can_use_return_insn ())
7488 emit_insn (gen_return ());
7492 if (mips_entry && ! mips_can_use_return_insn ())
7495 if (tsize > 32767 && ! TARGET_MIPS16)
7497 tmp_rtx = gen_rtx_REG (Pmode, MIPS_TEMP1_REGNUM);
7498 emit_move_insn (tmp_rtx, tsize_rtx);
7499 tsize_rtx = tmp_rtx;
7504 long orig_tsize = tsize;
7506 if (frame_pointer_needed)
7508 emit_insn (gen_blockage ());
7510 /* On the mips16, the frame pointer is offset from the stack
7511 pointer by current_function_outgoing_args_size. We
7512 account for that by changing tsize. Note that this can
7513 actually make tsize negative. */
7516 tsize -= current_function_outgoing_args_size;
7518 /* If we have a large frame, it's easier to add to $17
7519 than to $sp, since the mips16 has no instruction to
7520 add a register to $sp. */
7521 if (orig_tsize > 32767)
7523 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
7525 emit_move_insn (g6_rtx, GEN_INT (tsize));
7526 if (Pmode == DImode)
7527 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7528 hard_frame_pointer_rtx,
7531 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
7532 hard_frame_pointer_rtx,
7537 if (tsize && tsize != orig_tsize)
7538 tsize_rtx = GEN_INT (tsize);
7541 if (Pmode == DImode)
7542 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
7544 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
7547 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
7548 are going to restore it, then we must emit a blockage insn to
7549 prevent the scheduler from moving the restore out of the epilogue. */
7550 else if (TARGET_ABICALLS && mips_abi != ABI_32 && mips_abi != ABI_O64
7551 && (current_frame_info.mask
7552 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
7553 emit_insn (gen_blockage ());
7555 save_restore_insns (0, tmp_rtx, orig_tsize, (FILE *)0);
7557 /* In mips16 mode with a large frame, we adjust the stack
7558 pointer before restoring the registers. In this case, we
7559 should always be using a frame pointer, so everything should
7560 have been handled above. */
7561 if (tsize > 32767 && TARGET_MIPS16)
7564 if (current_function_calls_eh_return)
7566 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
7567 if (Pmode == DImode)
7568 emit_insn (gen_adddi3 (eh_ofs, eh_ofs, tsize_rtx));
7570 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
7574 emit_insn (gen_blockage ());
7576 if (tsize != 0 || current_function_calls_eh_return)
7578 if (Pmode == DImode)
7579 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7582 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7587 /* The mips16 loads the return address into $7, not $31. */
7588 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
7589 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7590 GP_REG_FIRST + 7)));
7592 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
7593 GP_REG_FIRST + 31)));
7596 /* Return nonzero if this function is known to have a null epilogue.
7597 This allows the optimizer to omit jumps to jumps if no stack
7601 mips_can_use_return_insn ()
7603 if (! reload_completed)
7606 if (regs_ever_live[31] || profile_flag)
7609 /* In mips16 mode, a function which returns a floating point value
7610 needs to arrange to copy the return value into the floating point
7613 && mips16_hard_float
7614 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
7615 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
7617 && (! TARGET_SINGLE_FLOAT
7618 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
7622 if (current_frame_info.initialized)
7623 return current_frame_info.total_size == 0;
7625 return compute_frame_size (get_frame_size ()) == 0;
7628 /* Returns non-zero if X contains a SYMBOL_REF. */
7631 symbolic_expression_p (x)
7634 if (GET_CODE (x) == SYMBOL_REF)
7637 if (GET_CODE (x) == CONST)
7638 return symbolic_expression_p (XEXP (x, 0));
7640 if (GET_RTX_CLASS (GET_CODE (x)) == '1')
7641 return symbolic_expression_p (XEXP (x, 0));
7643 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
7644 || GET_RTX_CLASS (GET_CODE (x)) == '2')
7645 return (symbolic_expression_p (XEXP (x, 0))
7646 || symbolic_expression_p (XEXP (x, 1)));
7651 /* Choose the section to use for the constant rtx expression X that has
7655 mips_select_rtx_section (mode, x)
7656 enum machine_mode mode;
7657 rtx x ATTRIBUTE_UNUSED;
7661 /* In mips16 mode, the constant table always goes in the same section
7662 as the function, so that constants can be loaded using PC relative
7664 function_section (current_function_decl);
7666 else if (TARGET_EMBEDDED_DATA)
7668 /* For embedded applications, always put constants in read-only data,
7669 in order to reduce RAM usage. */
7670 READONLY_DATA_SECTION ();
7674 /* For hosted applications, always put constants in small data if
7675 possible, as this gives the best performance. */
7677 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7678 && mips_section_threshold > 0)
7679 SMALL_DATA_SECTION ();
7680 else if (flag_pic && symbolic_expression_p (x))
7681 /* Any expression involving a SYMBOL_REF might need a run-time
7682 relocation. (The symbol might be defined in a shared
7683 library loaded at an unexpected base address.) So, we must
7684 put such expressions in the data segment (which is
7685 writable), rather than the text segment (which is
7689 READONLY_DATA_SECTION ();
7693 /* Choose the section to use for DECL. RELOC is true if its value contains
7694 any relocatable expression.
7696 Some of the logic used here needs to be replicated in
7697 ENCODE_SECTION_INFO in mips.h so that references to these symbols
7698 are done correctly. Specifically, at least all symbols assigned
7699 here to rom (.text and/or .rodata) must not be referenced via
7700 ENCODE_SECTION_INFO with %gprel, as the rom might be too far away.
7702 If you need to make a change here, you probably should check
7703 ENCODE_SECTION_INFO to see if it needs a similar change. */
7706 mips_select_section (decl, reloc)
7710 int size = int_size_in_bytes (TREE_TYPE (decl));
7712 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
7713 && TREE_CODE (decl) == STRING_CST
7714 && !flag_writable_strings)
7715 /* For embedded position independent code, put constant strings in the
7716 text section, because the data section is limited to 64K in size.
7717 For mips16 code, put strings in the text section so that a PC
7718 relative load instruction can be used to get their address. */
7720 else if (TARGET_EMBEDDED_DATA)
7722 /* For embedded applications, always put an object in read-only data
7723 if possible, in order to reduce RAM usage. */
7725 if (((TREE_CODE (decl) == VAR_DECL
7726 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7727 && DECL_INITIAL (decl)
7728 && (DECL_INITIAL (decl) == error_mark_node
7729 || TREE_CONSTANT (DECL_INITIAL (decl))))
7730 /* Deal with calls from output_constant_def_contents. */
7731 || (TREE_CODE (decl) != VAR_DECL
7732 && (TREE_CODE (decl) != STRING_CST
7733 || !flag_writable_strings)))
7734 && ! (flag_pic && reloc))
7735 READONLY_DATA_SECTION ();
7736 else if (size > 0 && size <= mips_section_threshold)
7737 SMALL_DATA_SECTION ();
7743 /* For hosted applications, always put an object in small data if
7744 possible, as this gives the best performance. */
7746 if (size > 0 && size <= mips_section_threshold)
7747 SMALL_DATA_SECTION ();
7748 else if (((TREE_CODE (decl) == VAR_DECL
7749 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
7750 && DECL_INITIAL (decl)
7751 && (DECL_INITIAL (decl) == error_mark_node
7752 || TREE_CONSTANT (DECL_INITIAL (decl))))
7753 /* Deal with calls from output_constant_def_contents. */
7754 || (TREE_CODE (decl) != VAR_DECL
7755 && (TREE_CODE (decl) != STRING_CST
7756 || !flag_writable_strings)))
7757 && ! (flag_pic && reloc))
7758 READONLY_DATA_SECTION ();
7764 #ifdef MIPS_ABI_DEFAULT
7766 /* Support functions for the 64 bit ABI. */
7768 /* Return register to use for a function return value with VALTYPE for function
7772 mips_function_value (valtype, func)
7774 tree func ATTRIBUTE_UNUSED;
7776 int reg = GP_RETURN;
7777 enum machine_mode mode = TYPE_MODE (valtype);
7778 enum mode_class mclass = GET_MODE_CLASS (mode);
7779 int unsignedp = TREE_UNSIGNED (valtype);
7781 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
7782 just as PROMOTE_MODE does. */
7783 mode = promote_mode (valtype, mode, &unsignedp, 1);
7785 if (mclass == MODE_FLOAT)
7787 if (TARGET_SINGLE_FLOAT
7788 && (mclass == MODE_FLOAT
7789 ? GET_MODE_SIZE (mode) > 4 : GET_MODE_SIZE (mode) / 2 > 4))
7795 else if (mclass == MODE_COMPLEX_FLOAT)
7799 else if (mode == SCmode)
7801 /* When FP registers are 32 bits, we can't directly reference
7802 the odd numbered ones, so let's make a pair of evens. */
7804 enum machine_mode cmode = TYPE_MODE (TREE_TYPE (valtype));
7806 return gen_rtx_PARALLEL
7809 gen_rtx_EXPR_LIST (VOIDmode,
7813 gen_rtx_EXPR_LIST (VOIDmode,
7822 else if (TREE_CODE (valtype) == RECORD_TYPE
7823 && mips_abi != ABI_32
7824 && mips_abi != ABI_O64
7825 && mips_abi != ABI_EABI)
7827 /* A struct with only one or two floating point fields is returned in
7828 the floating point registers. */
7829 tree field, fields[2];
7832 for (i = 0, field = TYPE_FIELDS (valtype); field;
7833 field = TREE_CHAIN (field))
7835 if (TREE_CODE (field) != FIELD_DECL)
7838 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
7841 fields[i++] = field;
7844 /* Must check i, so that we reject structures with no elements. */
7849 /* The structure has DImode, but we don't allow DImode values
7850 in FP registers, so we use a PARALLEL even though it isn't
7851 strictly necessary. */
7852 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7854 return gen_rtx_PARALLEL
7857 gen_rtx_EXPR_LIST (VOIDmode,
7858 gen_rtx_REG (field_mode,
7865 enum machine_mode first_mode
7866 = TYPE_MODE (TREE_TYPE (fields[0]));
7867 enum machine_mode second_mode
7868 = TYPE_MODE (TREE_TYPE (fields[1]));
7869 HOST_WIDE_INT first_offset = int_byte_position (fields[0]);
7870 HOST_WIDE_INT second_offset = int_byte_position (fields[1]);
7872 return gen_rtx_PARALLEL
7875 gen_rtx_EXPR_LIST (VOIDmode,
7876 gen_rtx_REG (first_mode,
7878 GEN_INT (first_offset)),
7879 gen_rtx_EXPR_LIST (VOIDmode,
7880 gen_rtx_REG (second_mode,
7882 GEN_INT (second_offset))));
7887 return gen_rtx_REG (mode, reg);
7891 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7892 nonzero when an argument must be passed by reference. */
7895 function_arg_pass_by_reference (cum, mode, type, named)
7896 CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
7897 enum machine_mode mode;
7899 int named ATTRIBUTE_UNUSED;
7903 /* We must pass by reference if we would be both passing in registers
7904 and the stack. This is because any subsequent partial arg would be
7905 handled incorrectly in this case.
7907 ??? This is really a kludge. We should either fix GCC so that such
7908 a situation causes an abort and then do something in the MIPS port
7909 to prevent it, or add code to function.c to properly handle the case. */
7910 /* ??? cum can be NULL when called from mips_va_arg. The problem handled
7911 here hopefully is not relevant to mips_va_arg. */
7912 if (cum && MUST_PASS_IN_STACK (mode, type))
7914 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
7915 get double copies of any offsets generated for small structs
7916 passed in registers. */
7917 CUMULATIVE_ARGS temp;
7919 if (FUNCTION_ARG (temp, mode, type, named) != 0)
7923 /* Otherwise, we only do this if EABI is selected. */
7924 if (mips_abi != ABI_EABI)
7927 /* ??? How should SCmode be handled? */
7928 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7931 size = int_size_in_bytes (type);
7932 return size == -1 || size > UNITS_PER_WORD;
7935 /* This function returns the register class required for a secondary
7936 register when copying between one of the registers in CLASS, and X,
7937 using MODE. If IN_P is nonzero, the copy is going from X to the
7938 register, otherwise the register is the source. A return value of
7939 NO_REGS means that no secondary register is required. */
7942 mips_secondary_reload_class (class, mode, x, in_p)
7943 enum reg_class class;
7944 enum machine_mode mode;
7948 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7952 if (GET_CODE (x) == SIGN_EXTEND)
7958 /* We may be called with reg_renumber NULL from regclass.
7959 ??? This is probably a bug. */
7961 regno = true_regnum (x);
7964 while (GET_CODE (x) == SUBREG)
7966 off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
7967 GET_MODE (SUBREG_REG (x)),
7973 if (GET_CODE (x) == REG)
7974 regno = REGNO (x) + off;
7978 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7979 regno = true_regnum (x);
7981 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7983 /* We always require a general register when copying anything to
7984 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7985 to a general register, or when copying from register 0. */
7986 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7989 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7990 ? NO_REGS : gr_regs);
7991 else if (regno == HILO_REGNUM)
7994 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7995 ? NO_REGS : gr_regs);
7997 /* Copying from HI or LO to anywhere other than a general register
7998 requires a general register. */
7999 if (class == HI_REG || class == LO_REG || class == MD_REGS)
8001 if (TARGET_MIPS16 && in_p)
8003 /* We can't really copy to HI or LO at all in mips16 mode. */
8006 return gp_reg_p ? NO_REGS : gr_regs;
8008 if (MD_REG_P (regno))
8010 if (TARGET_MIPS16 && ! in_p)
8012 /* We can't really copy to HI or LO at all in mips16 mode. */
8015 return class == gr_regs ? NO_REGS : gr_regs;
8018 /* We can only copy a value to a condition code register from a
8019 floating point register, and even then we require a scratch
8020 floating point register. We can only copy a value out of a
8021 condition code register into a general register. */
8022 if (class == ST_REGS)
8026 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
8028 if (ST_REG_P (regno))
8032 return class == GR_REGS ? NO_REGS : GR_REGS;
8035 /* In mips16 mode, going between memory and anything but M16_REGS
8036 requires an M16_REG. */
8039 if (class != M16_REGS && class != M16_NA_REGS)
8047 /* The stack pointer isn't a valid operand to an add instruction,
8048 so we need to load it into M16_REGS first. This can happen as
8049 a result of register elimination and form_sum converting
8050 (plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
8051 need an extra register if the dest is the same as the other
8052 register. In that case, we can't fix the problem by loading SP
8053 into the dest first. */
8054 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
8055 && GET_CODE (XEXP (x, 1)) == REG
8056 && (XEXP (x, 0) == stack_pointer_rtx
8057 || XEXP (x, 1) == stack_pointer_rtx))
8058 return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
8060 if (class == M16_REGS || class == M16_NA_REGS)
8069 /* For each mips16 function which refers to GP relative symbols, we
8070 use a pseudo register, initialized at the start of the function, to
8071 hold the $gp value. */
8074 mips16_gp_pseudo_reg ()
8076 if (mips16_gp_pseudo_rtx == NULL_RTX)
8081 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
8082 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
8084 /* We want to initialize this to a value which gcc will believe
8086 const_gp = gen_rtx (CONST, Pmode,
8087 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
8090 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
8091 insn = gen_sequence ();
8094 push_topmost_sequence ();
8095 /* We need to emit the initialization after the FUNCTION_BEG
8096 note, so that it will be integrated. */
8097 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
8098 if (GET_CODE (scan) == NOTE
8099 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
8101 if (scan == NULL_RTX)
8102 scan = get_insns ();
8103 insn = emit_insn_after (insn, scan);
8104 pop_topmost_sequence ();
8107 return mips16_gp_pseudo_rtx;
8110 /* Return an RTX which represents the signed 16 bit offset from the
8111 $gp register for the given symbol. This is only used on the
8115 mips16_gp_offset (sym)
8120 if (GET_CODE (sym) != SYMBOL_REF
8121 || ! SYMBOL_REF_FLAG (sym))
8124 /* We use a special identifier to represent the value of the gp
8126 gp = get_identifier ("__mips16_gp_value");
8128 return gen_rtx (CONST, Pmode,
8129 gen_rtx (MINUS, Pmode, sym,
8130 gen_rtx (SYMBOL_REF, Pmode,
8131 IDENTIFIER_POINTER (gp))));
8134 /* Return nonzero if the given RTX represents a signed 16 bit offset
8135 from the $gp register. */
8138 mips16_gp_offset_p (x)
8141 if (GET_CODE (x) == CONST)
8144 /* It's OK to add a small integer value to a gp offset. */
8145 if (GET_CODE (x) == PLUS)
8147 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8148 && SMALL_INT (XEXP (x, 1)))
8149 return mips16_gp_offset_p (XEXP (x, 0));
8150 if (GET_CODE (XEXP (x, 0)) == CONST_INT
8151 && SMALL_INT (XEXP (x, 0)))
8152 return mips16_gp_offset_p (XEXP (x, 1));
8156 /* Make sure it is in the form SYM - __mips16_gp_value. */
8157 return (GET_CODE (x) == MINUS
8158 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
8159 && SYMBOL_REF_FLAG (XEXP (x, 0))
8160 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8161 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
8164 /* Output a GP offset. We don't want to print the subtraction of
8165 __mips16_gp_value; it is implicitly represented by the %gprel which
8166 should have been printed by the caller. */
8169 mips16_output_gp_offset (file, x)
8173 if (GET_CODE (x) == CONST)
8176 if (GET_CODE (x) == PLUS)
8178 mips16_output_gp_offset (file, XEXP (x, 0));
8180 mips16_output_gp_offset (file, XEXP (x, 1));
8184 if (GET_CODE (x) == MINUS
8185 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
8186 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
8188 mips16_output_gp_offset (file, XEXP (x, 0));
8192 output_addr_const (file, x);
8195 /* Return nonzero if a constant should not be output until after the
8196 function. This is true of most string constants, so that we can
8197 use a more efficient PC relative reference. However, a static
8198 inline function may never call assemble_function_end to write out
8199 the constant pool, so don't try to postpone the constant in that
8202 ??? It's really a bug that a static inline function can put stuff
8203 in the constant pool even if the function itself is not output.
8205 We record which string constants we've seen, so that we know which
8206 ones might use the more efficient reference. */
8209 mips16_constant_after_function_p (x)
8212 if (TREE_CODE (x) == STRING_CST
8213 && ! flag_writable_strings
8214 && current_function_decl != 0
8215 && ! DECL_DEFER_OUTPUT (current_function_decl)
8216 && ! (DECL_INLINE (current_function_decl)
8217 && ((! TREE_PUBLIC (current_function_decl)
8218 && ! TREE_ADDRESSABLE (current_function_decl)
8219 && ! flag_keep_inline_functions)
8220 || DECL_EXTERNAL (current_function_decl))))
8222 struct string_constant *n;
8224 n = (struct string_constant *) xmalloc (sizeof *n);
8225 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
8226 n->next = string_constants;
8227 string_constants = n;
8235 /* Validate a constant for the mips16. This rejects general symbolic
8236 addresses, which must be loaded from memory. If ADDR is nonzero,
8237 this should reject anything which is not a legal address. If
8238 ADDEND is nonzero, this is being added to something else. */
8241 mips16_constant (x, mode, addr, addend)
8243 enum machine_mode mode;
8247 while (GET_CODE (x) == CONST)
8250 switch (GET_CODE (x))
8256 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
8257 && mips16_constant (XEXP (x, 1), mode, addr, 1));
8260 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8262 if (CONSTANT_POOL_ADDRESS_P (x))
8265 /* If we aren't looking for a memory address, we can accept a GP
8266 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
8267 knows how to handle this. We can always accept a string
8268 constant, which is the other case in which SYMBOL_REF_FLAG
8272 && SYMBOL_REF_FLAG (x)
8273 && mode == (enum machine_mode) Pmode)
8276 /* We can accept a string constant, which will have
8277 SYMBOL_REF_FLAG set but must be recognized by name to
8278 distinguish from a GP accessible symbol. The name of a
8279 string constant will have been generated by
8280 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
8281 if (SYMBOL_REF_FLAG (x))
8283 const char *name = XSTR (x, 0);
8285 return (name[0] == '*'
8286 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
8287 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
8293 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
8298 if (addr && ! addend)
8300 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
8303 /* We need to treat $gp as a legitimate constant, because
8304 mips16_gp_pseudo_reg assumes that. */
8305 return REGNO (x) == GP_REG_FIRST + 28;
8309 /* Write out code to move floating point arguments in or out of
8310 general registers. Output the instructions to FILE. FP_CODE is
8311 the code describing which arguments are present (see the comment at
8312 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
8313 we are copying from the floating point registers. */
8316 mips16_fp_args (file, fp_code, from_fp_p)
8325 /* This code only works for the original 32 bit ABI and the O64 ABI. */
8326 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8333 gparg = GP_ARG_FIRST;
8334 fparg = FP_ARG_FIRST;
8335 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8339 if ((fparg & 1) != 0)
8341 fprintf (file, "\t%s\t%s,%s\n", s,
8342 reg_names[gparg], reg_names[fparg]);
8344 else if ((f & 3) == 2)
8347 fprintf (file, "\td%s\t%s,%s\n", s,
8348 reg_names[gparg], reg_names[fparg]);
8351 if ((fparg & 1) != 0)
8353 if (TARGET_BIG_ENDIAN)
8354 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8355 reg_names[gparg], reg_names[fparg + 1], s,
8356 reg_names[gparg + 1], reg_names[fparg]);
8358 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
8359 reg_names[gparg], reg_names[fparg], s,
8360 reg_names[gparg + 1], reg_names[fparg + 1]);
8373 /* Build a mips16 function stub. This is used for functions which
8374 take aruments in the floating point registers. It is 32 bit code
8375 that moves the floating point args into the general registers, and
8376 then jumps to the 16 bit code. */
8379 build_mips16_function_stub (file)
8383 char *secname, *stubname;
8384 tree stubid, stubdecl;
8388 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
8389 secname = (char *) alloca (strlen (fnname) + 20);
8390 sprintf (secname, ".mips16.fn.%s", fnname);
8391 stubname = (char *) alloca (strlen (fnname) + 20);
8392 sprintf (stubname, "__fn_stub_%s", fnname);
8393 stubid = get_identifier (stubname);
8394 stubdecl = build_decl (FUNCTION_DECL, stubid,
8395 build_function_type (void_type_node, NULL_TREE));
8396 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8398 fprintf (file, "\t# Stub function for %s (", current_function_name);
8400 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
8402 fprintf (file, "%s%s",
8403 need_comma ? ", " : "",
8404 (f & 3) == 1 ? "float" : "double");
8407 fprintf (file, ")\n");
8409 fprintf (file, "\t.set\tnomips16\n");
8410 function_section (stubdecl);
8411 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
8413 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
8414 within a .ent, and we can not emit another .ent. */
8415 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8416 fputs ("\t.ent\t", file);
8417 assemble_name (file, stubname);
8421 assemble_name (file, stubname);
8422 fputs (":\n", file);
8424 /* We don't want the assembler to insert any nops here. */
8425 fprintf (file, "\t.set\tnoreorder\n");
8427 mips16_fp_args (file, current_function_args_info.fp_code, 1);
8429 fprintf (asm_out_file, "\t.set\tnoat\n");
8430 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
8431 assemble_name (file, fnname);
8432 fprintf (file, "\n");
8433 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8434 fprintf (asm_out_file, "\t.set\tat\n");
8436 /* Unfortunately, we can't fill the jump delay slot. We can't fill
8437 with one of the mfc1 instructions, because the result is not
8438 available for one instruction, so if the very first instruction
8439 in the function refers to the register, it will see the wrong
8441 fprintf (file, "\tnop\n");
8443 fprintf (file, "\t.set\treorder\n");
8445 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8446 fputs ("\t.end\t", file);
8447 assemble_name (file, stubname);
8451 fprintf (file, "\t.set\tmips16\n");
8453 function_section (current_function_decl);
8456 /* We keep a list of functions for which we have already built stubs
8457 in build_mips16_call_stub. */
8461 struct mips16_stub *next;
8466 static struct mips16_stub *mips16_stubs;
8468 /* Build a call stub for a mips16 call. A stub is needed if we are
8469 passing any floating point values which should go into the floating
8470 point registers. If we are, and the call turns out to be to a 32
8471 bit function, the stub will be used to move the values into the
8472 floating point registers before calling the 32 bit function. The
8473 linker will magically adjust the function call to either the 16 bit
8474 function or the 32 bit stub, depending upon where the function call
8475 is actually defined.
8477 Similarly, we need a stub if the return value might come back in a
8478 floating point register.
8480 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
8481 (RETVAL is NULL if this is call rather than call_value). FP_CODE
8482 is the code built by function_arg. This function returns a nonzero
8483 value if it builds the call instruction itself. */
8486 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
8495 char *secname, *stubname;
8496 struct mips16_stub *l;
8497 tree stubid, stubdecl;
8501 /* We don't need to do anything if we aren't in mips16 mode, or if
8502 we were invoked with the -msoft-float option. */
8503 if (! TARGET_MIPS16 || ! mips16_hard_float)
8506 /* Figure out whether the value might come back in a floating point
8508 fpret = (retval != 0
8509 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
8510 && (! TARGET_SINGLE_FLOAT
8511 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
8513 /* We don't need to do anything if there were no floating point
8514 arguments and the value will not be returned in a floating point
8516 if (fp_code == 0 && ! fpret)
8519 if (GET_CODE (fnmem) != MEM)
8521 fn = XEXP (fnmem, 0);
8523 /* We don't need to do anything if this is a call to a special
8524 mips16 support function. */
8525 if (GET_CODE (fn) == SYMBOL_REF
8526 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
8529 /* This code will only work for o32 and o64 abis. The other ABI's
8530 require more sophisticated support. */
8531 if (mips_abi != ABI_32 && mips_abi != ABI_O64)
8534 /* We can only handle SFmode and DFmode floating point return
8536 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
8539 /* If we're calling via a function pointer, then we must always call
8540 via a stub. There are magic stubs provided in libgcc.a for each
8541 of the required cases. Each of them expects the function address
8542 to arrive in register $2. */
8544 if (GET_CODE (fn) != SYMBOL_REF)
8548 rtx stub_fn, stub_mem, insn;
8550 /* ??? If this code is modified to support other ABI's, we need
8551 to handle PARALLEL return values here. */
8553 sprintf (buf, "__mips16_call_stub_%s%d",
8555 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
8558 id = get_identifier (buf);
8559 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
8560 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
8562 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
8564 if (retval == NULL_RTX)
8565 insn = gen_call_internal0 (stub_mem, arg_size,
8566 gen_rtx (REG, SImode,
8567 GP_REG_FIRST + 31));
8569 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
8570 gen_rtx (REG, SImode,
8571 GP_REG_FIRST + 31));
8572 insn = emit_call_insn (insn);
8574 /* Put the register usage information on the CALL. */
8575 if (GET_CODE (insn) != CALL_INSN)
8577 CALL_INSN_FUNCTION_USAGE (insn) =
8578 gen_rtx (EXPR_LIST, VOIDmode,
8579 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
8580 CALL_INSN_FUNCTION_USAGE (insn));
8582 /* If we are handling a floating point return value, we need to
8583 save $18 in the function prologue. Putting a note on the
8584 call will mean that regs_ever_live[$18] will be true if the
8585 call is not eliminated, and we can check that in the prologue
8588 CALL_INSN_FUNCTION_USAGE (insn) =
8589 gen_rtx (EXPR_LIST, VOIDmode,
8590 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8591 CALL_INSN_FUNCTION_USAGE (insn));
8593 /* Return 1 to tell the caller that we've generated the call
8598 /* We know the function we are going to call. If we have already
8599 built a stub, we don't need to do anything further. */
8601 fnname = XSTR (fn, 0);
8602 for (l = mips16_stubs; l != NULL; l = l->next)
8603 if (strcmp (l->name, fnname) == 0)
8608 /* Build a special purpose stub. When the linker sees a
8609 function call in mips16 code, it will check where the target
8610 is defined. If the target is a 32 bit call, the linker will
8611 search for the section defined here. It can tell which
8612 symbol this section is associated with by looking at the
8613 relocation information (the name is unreliable, since this
8614 might be a static function). If such a section is found, the
8615 linker will redirect the call to the start of the magic
8618 If the function does not return a floating point value, the
8619 special stub section is named
8622 If the function does return a floating point value, the stub
8624 .mips16.call.fp.FNNAME
8627 secname = (char *) alloca (strlen (fnname) + 40);
8628 sprintf (secname, ".mips16.call.%s%s",
8631 stubname = (char *) alloca (strlen (fnname) + 20);
8632 sprintf (stubname, "__call_stub_%s%s",
8635 stubid = get_identifier (stubname);
8636 stubdecl = build_decl (FUNCTION_DECL, stubid,
8637 build_function_type (void_type_node, NULL_TREE));
8638 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
8640 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
8642 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
8646 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
8648 fprintf (asm_out_file, "%s%s",
8649 need_comma ? ", " : "",
8650 (f & 3) == 1 ? "float" : "double");
8653 fprintf (asm_out_file, ")\n");
8655 fprintf (asm_out_file, "\t.set\tnomips16\n");
8656 assemble_start_function (stubdecl, stubname);
8658 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8659 fputs ("\t.ent\t", asm_out_file);
8660 assemble_name (asm_out_file, stubname);
8661 fputs ("\n", asm_out_file);
8663 assemble_name (asm_out_file, stubname);
8664 fputs (":\n", asm_out_file);
8667 /* We build the stub code by hand. That's the only way we can
8668 do it, since we can't generate 32 bit code during a 16 bit
8671 /* We don't want the assembler to insert any nops here. */
8672 fprintf (asm_out_file, "\t.set\tnoreorder\n");
8674 mips16_fp_args (asm_out_file, fp_code, 0);
8678 fprintf (asm_out_file, "\t.set\tnoat\n");
8679 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
8681 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
8682 fprintf (asm_out_file, "\t.set\tat\n");
8683 /* Unfortunately, we can't fill the jump delay slot. We
8684 can't fill with one of the mtc1 instructions, because the
8685 result is not available for one instruction, so if the
8686 very first instruction in the function refers to the
8687 register, it will see the wrong value. */
8688 fprintf (asm_out_file, "\tnop\n");
8692 fprintf (asm_out_file, "\tmove\t%s,%s\n",
8693 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
8694 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
8695 /* As above, we can't fill the delay slot. */
8696 fprintf (asm_out_file, "\tnop\n");
8697 if (GET_MODE (retval) == SFmode)
8698 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8699 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
8702 if (TARGET_BIG_ENDIAN)
8704 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8705 reg_names[GP_REG_FIRST + 2],
8706 reg_names[FP_REG_FIRST + 1]);
8707 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8708 reg_names[GP_REG_FIRST + 3],
8709 reg_names[FP_REG_FIRST + 0]);
8713 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8714 reg_names[GP_REG_FIRST + 2],
8715 reg_names[FP_REG_FIRST + 0]);
8716 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
8717 reg_names[GP_REG_FIRST + 3],
8718 reg_names[FP_REG_FIRST + 1]);
8721 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
8722 /* As above, we can't fill the delay slot. */
8723 fprintf (asm_out_file, "\tnop\n");
8726 fprintf (asm_out_file, "\t.set\treorder\n");
8728 #ifdef ASM_DECLARE_FUNCTION_SIZE
8729 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8732 #ifndef FUNCTION_NAME_ALREADY_DECLARED
8733 fputs ("\t.end\t", asm_out_file);
8734 assemble_name (asm_out_file, stubname);
8735 fputs ("\n", asm_out_file);
8738 fprintf (asm_out_file, "\t.set\tmips16\n");
8740 /* Record this stub. */
8741 l = (struct mips16_stub *) xmalloc (sizeof *l);
8742 l->name = xstrdup (fnname);
8744 l->next = mips16_stubs;
8748 /* If we expect a floating point return value, but we've built a
8749 stub which does not expect one, then we're in trouble. We can't
8750 use the existing stub, because it won't handle the floating point
8751 value. We can't build a new stub, because the linker won't know
8752 which stub to use for the various calls in this object file.
8753 Fortunately, this case is illegal, since it means that a function
8754 was declared in two different ways in a single compilation. */
8755 if (fpret && ! l->fpret)
8756 error ("can not handle inconsistent calls to `%s'", fnname);
8758 /* If we are calling a stub which handles a floating point return
8759 value, we need to arrange to save $18 in the prologue. We do
8760 this by marking the function call as using the register. The
8761 prologue will later see that it is used, and emit code to save
8768 if (retval == NULL_RTX)
8769 insn = gen_call_internal0 (fnmem, arg_size,
8770 gen_rtx (REG, SImode,
8771 GP_REG_FIRST + 31));
8773 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
8774 gen_rtx (REG, SImode,
8775 GP_REG_FIRST + 31));
8776 insn = emit_call_insn (insn);
8778 if (GET_CODE (insn) != CALL_INSN)
8781 CALL_INSN_FUNCTION_USAGE (insn) =
8782 gen_rtx (EXPR_LIST, VOIDmode,
8783 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
8784 CALL_INSN_FUNCTION_USAGE (insn));
8786 /* Return 1 to tell the caller that we've generated the call
8791 /* Return 0 to let the caller generate the call insn. */
8795 /* This function looks through the code for a function, and tries to
8796 optimize the usage of the $gp register. We arrange to copy $gp
8797 into a pseudo-register, and then let gcc's normal reload handling
8798 deal with the pseudo-register. Unfortunately, if reload choose to
8799 put the pseudo-register into a call-clobbered register, it will
8800 emit saves and restores for that register around any function
8801 calls. We don't need the saves, and it's faster to copy $gp than
8802 to do an actual restore. ??? This still means that we waste a
8805 This is an optimization, and the code which gcc has actually
8806 generated is correct, so we do not need to catch all cases. */
8809 mips16_optimize_gp (first)
8812 rtx gpcopy, slot, insn;
8814 /* Look through the instructions. Set GPCOPY to the register which
8815 holds a copy of $gp. Set SLOT to the stack slot where it is
8816 saved. If we find an instruction which sets GPCOPY to anything
8817 other than $gp or SLOT, then we can't use it. If we find an
8818 instruction which sets SLOT to anything other than GPCOPY, we
8823 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8827 if (! INSN_P (insn))
8830 set = PATTERN (insn);
8832 /* We know that all references to memory will be inside a SET,
8833 because there is no other way to access memory on the mips16.
8834 We don't have to worry about a PARALLEL here, because the
8835 mips.md file will never generate them for memory references. */
8836 if (GET_CODE (set) != SET)
8839 if (gpcopy == NULL_RTX
8840 && GET_CODE (SET_SRC (set)) == CONST
8841 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
8842 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
8843 && GET_CODE (SET_DEST (set)) == REG
8844 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8845 gpcopy = SET_DEST (set);
8846 else if (slot == NULL_RTX
8847 && gpcopy != NULL_RTX
8848 && GET_CODE (SET_DEST (set)) == MEM
8849 && GET_CODE (SET_SRC (set)) == REG
8850 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
8851 && GET_MODE (SET_DEST (set)) == (unsigned) Pmode)
8855 offset = const0_rtx;
8856 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
8857 if (GET_CODE (base) == REG
8858 && (REGNO (base) == STACK_POINTER_REGNUM
8859 || REGNO (base) == FRAME_POINTER_REGNUM))
8860 slot = SET_DEST (set);
8862 else if (gpcopy != NULL_RTX
8863 && (GET_CODE (SET_DEST (set)) == REG
8864 || GET_CODE (SET_DEST (set)) == SUBREG)
8865 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
8866 && (GET_CODE (SET_DEST (set)) != REG
8867 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
8868 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode
8869 || ((GET_CODE (SET_SRC (set)) != CONST
8870 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
8871 || (REGNO (XEXP (SET_SRC (set), 0))
8872 != GP_REG_FIRST + 28))
8873 && ! rtx_equal_p (SET_SRC (set), slot))))
8875 else if (slot != NULL_RTX
8876 && GET_CODE (SET_DEST (set)) == MEM
8877 && rtx_equal_p (SET_DEST (set), slot)
8878 && (GET_CODE (SET_SRC (set)) != REG
8879 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
8883 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
8884 different optimization. Any time we find a copy of $28 into a
8885 register, followed by an add of a symbol_ref to that register, we
8886 convert it to load the value from the constant table instead.
8887 The copy and add will take six bytes, just as the load and
8888 constant table entry will take six bytes. However, it is
8889 possible that the constant table entry will be shared.
8891 This could be a peephole optimization, but I don't know if the
8892 peephole code can call force_const_mem.
8894 Using the same register for the copy of $28 and the add of the
8895 symbol_ref is actually pretty likely, since the add instruction
8896 requires the destination and the first addend to be the same
8899 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8903 /* This optimization is only reasonable if the constant table
8904 entries are only 4 bytes. */
8905 if (Pmode != SImode)
8908 for (insn = first; insn != NULL_RTX; insn = next)
8915 next = NEXT_INSN (next);
8917 while (next != NULL_RTX
8918 && (GET_CODE (next) == NOTE
8919 || (GET_CODE (next) == INSN
8920 && (GET_CODE (PATTERN (next)) == USE
8921 || GET_CODE (PATTERN (next)) == CLOBBER))));
8923 if (next == NULL_RTX)
8926 if (! INSN_P (insn))
8929 if (! INSN_P (next))
8932 set1 = PATTERN (insn);
8933 if (GET_CODE (set1) != SET)
8935 set2 = PATTERN (next);
8936 if (GET_CODE (set2) != SET)
8939 if (GET_CODE (SET_DEST (set1)) == REG
8940 && GET_CODE (SET_SRC (set1)) == CONST
8941 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8942 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8943 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8944 && GET_CODE (SET_SRC (set2)) == PLUS
8945 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8946 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8947 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8951 /* We've found a case we can change to load from the
8954 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8955 if (GET_CODE (sym) != SYMBOL_REF)
8957 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8958 force_const_mem (Pmode, sym)),
8961 PUT_CODE (insn, NOTE);
8962 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8963 NOTE_SOURCE_FILE (insn) = 0;
8965 PUT_CODE (next, NOTE);
8966 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8967 NOTE_SOURCE_FILE (next) = 0;
8974 /* We can safely remove all assignments to SLOT from GPCOPY, and
8975 replace all assignments from SLOT to GPCOPY with assignments from
8978 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8982 if (! INSN_P (insn))
8985 set = PATTERN (insn);
8986 if (GET_CODE (set) != SET
8987 || GET_MODE (SET_DEST (set)) != (unsigned) Pmode)
8990 if (GET_CODE (SET_DEST (set)) == MEM
8991 && rtx_equal_p (SET_DEST (set), slot)
8992 && GET_CODE (SET_SRC (set)) == REG
8993 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8995 PUT_CODE (insn, NOTE);
8996 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8997 NOTE_SOURCE_FILE (insn) = 0;
8999 else if (GET_CODE (SET_DEST (set)) == REG
9000 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
9001 && GET_CODE (SET_SRC (set)) == MEM
9002 && rtx_equal_p (SET_SRC (set), slot))
9004 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
9005 gen_rtx (CONST, Pmode,
9006 gen_rtx (REG, Pmode,
9007 GP_REG_FIRST + 28))),
9009 PUT_CODE (insn, NOTE);
9010 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9011 NOTE_SOURCE_FILE (insn) = 0;
9016 /* We keep a list of constants we which we have to add to internal
9017 constant tables in the middle of large functions. */
9021 struct constant *next;
9024 enum machine_mode mode;
9027 /* Add a constant to the list in *PCONSTANTS. */
9030 add_constant (pconstants, val, mode)
9031 struct constant **pconstants;
9033 enum machine_mode mode;
9037 for (c = *pconstants; c != NULL; c = c->next)
9038 if (mode == c->mode && rtx_equal_p (val, c->value))
9041 c = (struct constant *) xmalloc (sizeof *c);
9044 c->label = gen_label_rtx ();
9045 c->next = *pconstants;
9050 /* Dump out the constants in CONSTANTS after INSN. */
9053 dump_constants (constants, insn)
9054 struct constant *constants;
9065 struct constant *next;
9067 switch (GET_MODE_SIZE (c->mode))
9074 insn = emit_insn_after (gen_align_2 (), insn);
9079 insn = emit_insn_after (gen_align_4 (), insn);
9084 insn = emit_insn_after (gen_align_8 (), insn);
9089 insn = emit_label_after (c->label, insn);
9094 r = gen_consttable_qi (c->value);
9097 r = gen_consttable_hi (c->value);
9100 r = gen_consttable_si (c->value);
9103 r = gen_consttable_sf (c->value);
9106 r = gen_consttable_di (c->value);
9109 r = gen_consttable_df (c->value);
9115 insn = emit_insn_after (r, insn);
9122 emit_barrier_after (insn);
9125 /* Find the symbol in an address expression. */
9128 mips_find_symbol (addr)
9131 if (GET_CODE (addr) == MEM)
9132 addr = XEXP (addr, 0);
9133 while (GET_CODE (addr) == CONST)
9134 addr = XEXP (addr, 0);
9135 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
9137 if (GET_CODE (addr) == PLUS)
9141 l1 = mips_find_symbol (XEXP (addr, 0));
9142 l2 = mips_find_symbol (XEXP (addr, 1));
9143 if (l1 != NULL_RTX && l2 == NULL_RTX)
9145 else if (l1 == NULL_RTX && l2 != NULL_RTX)
9151 /* Exported to toplev.c.
9153 Do a final pass over the function, just before delayed branch
9157 machine_dependent_reorg (first)
9160 int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
9162 struct constant *constants;
9164 if (! TARGET_MIPS16)
9167 /* If $gp is used, try to remove stores, and replace loads with
9170 mips16_optimize_gp (first);
9172 /* Scan the function looking for PC relative loads which may be out
9173 of range. All such loads will either be from the constant table,
9174 or be getting the address of a constant string. If the size of
9175 the function plus the size of the constant table is less than
9176 0x8000, then all loads are in range. */
9179 for (insn = first; insn; insn = NEXT_INSN (insn))
9181 insns_len += get_attr_length (insn);
9183 /* ??? We put switch tables in .text, but we don't define
9184 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9185 compute their lengths correctly. */
9186 if (GET_CODE (insn) == JUMP_INSN)
9190 body = PATTERN (insn);
9191 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9192 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9193 * GET_MODE_SIZE (GET_MODE (body)));
9194 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
9198 /* Store the original value of insns_len in current_frame_info, so
9199 that simple_memory_operand can look at it. */
9200 current_frame_info.insns_len = insns_len;
9202 pool_size = get_pool_size ();
9203 if (insns_len + pool_size + mips_string_length < 0x8000)
9206 /* Loop over the insns and figure out what the maximum internal pool
9208 max_internal_pool_size = 0;
9209 for (insn = first; insn; insn = NEXT_INSN (insn))
9211 if (GET_CODE (insn) == INSN
9212 && GET_CODE (PATTERN (insn)) == SET)
9216 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9217 if (src == NULL_RTX)
9219 if (CONSTANT_POOL_ADDRESS_P (src))
9220 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
9221 else if (SYMBOL_REF_FLAG (src))
9222 max_internal_pool_size += GET_MODE_SIZE (Pmode);
9228 first_constant_ref = -1;
9230 for (insn = first; insn; insn = NEXT_INSN (insn))
9232 if (GET_CODE (insn) == INSN
9233 && GET_CODE (PATTERN (insn)) == SET)
9236 enum machine_mode mode = VOIDmode;
9239 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
9240 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
9242 /* ??? This is very conservative, which means that we
9243 will generate too many copies of the constant table.
9244 The only solution would seem to be some form of
9246 if (((insns_len - addr)
9247 + max_internal_pool_size
9248 + get_pool_offset (src))
9251 val = get_pool_constant (src);
9252 mode = get_pool_mode (src);
9254 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
9256 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
9258 /* Including all of mips_string_length is conservative,
9259 and so is including all of max_internal_pool_size. */
9260 if (((insns_len - addr)
9261 + max_internal_pool_size
9263 + mips_string_length)
9269 max_internal_pool_size -= Pmode;
9272 if (val != NULL_RTX)
9276 /* This PC relative load is out of range. ??? In the
9277 case of a string constant, we are only guessing that
9278 it is range, since we don't know the offset of a
9279 particular string constant. */
9281 lab = add_constant (&constants, val, mode);
9282 newsrc = gen_rtx (MEM, mode,
9283 gen_rtx (LABEL_REF, VOIDmode, lab));
9284 RTX_UNCHANGING_P (newsrc) = 1;
9285 PATTERN (insn) = gen_rtx (SET, VOIDmode,
9286 SET_DEST (PATTERN (insn)),
9288 INSN_CODE (insn) = -1;
9290 if (first_constant_ref < 0)
9291 first_constant_ref = addr;
9295 addr += get_attr_length (insn);
9297 /* ??? We put switch tables in .text, but we don't define
9298 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
9299 compute their lengths correctly. */
9300 if (GET_CODE (insn) == JUMP_INSN)
9304 body = PATTERN (insn);
9305 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
9306 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
9307 * GET_MODE_SIZE (GET_MODE (body)));
9308 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
9311 if (GET_CODE (insn) == BARRIER)
9313 /* Output any constants we have accumulated. Note that we
9314 don't need to change ADDR, since its only use is
9315 subtraction from INSNS_LEN, and both would be changed by
9317 ??? If the instructions up to the next barrier reuse a
9318 constant, it would often be better to continue
9320 if (constants != NULL)
9321 dump_constants (constants, insn);
9323 first_constant_ref = -1;
9326 if (constants != NULL
9327 && (NEXT_INSN (insn) == NULL
9328 || (first_constant_ref >= 0
9329 && (((addr - first_constant_ref)
9330 + 2 /* for alignment */
9331 + 2 /* for a short jump insn */
9335 /* If we haven't had a barrier within 0x8000 bytes of a
9336 constant reference or we are at the end of the function,
9337 emit a barrier now. */
9339 rtx label, jump, barrier;
9341 label = gen_label_rtx ();
9342 jump = emit_jump_insn_after (gen_jump (label), insn);
9343 JUMP_LABEL (jump) = label;
9344 LABEL_NUSES (label) = 1;
9345 barrier = emit_barrier_after (jump);
9346 emit_label_after (label, barrier);
9347 first_constant_ref = -1;
9351 /* ??? If we output all references to a constant in internal
9352 constants table, we don't need to output the constant in the real
9353 constant table, but we have no way to prevent that. */
9356 /* Return nonzero if X is a SIGN or ZERO extend operator. */
9358 extend_operator (x, mode)
9360 enum machine_mode mode ATTRIBUTE_UNUSED;
9362 enum rtx_code code = GET_CODE (x);
9363 return code == SIGN_EXTEND || code == ZERO_EXTEND;
9366 /* Accept any operator that can be used to shift the high half of the
9367 input value to the lower half, suitable for truncation. The
9368 remainder (the lower half of the input, and the upper half of the
9369 output) will be discarded. */
9371 highpart_shift_operator (x, mode)
9373 enum machine_mode mode ATTRIBUTE_UNUSED;
9375 enum rtx_code code = GET_CODE (x);
9376 return (code == LSHIFTRT
9382 /* Return the length of INSN. LENGTH is the initial length computed by
9383 attributes in the machine-description file. */
9386 mips_adjust_insn_length (insn, length)
9390 /* A unconditional jump has an unfilled delay slot if it is not part
9391 of a sequence. A conditional jump normally has a delay slot, but
9392 does not on MIPS16. */
9393 if (simplejump_p (insn)
9394 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
9395 || GET_CODE (insn) == CALL_INSN)))
9398 /* All MIPS16 instructions are a measly two bytes. */
9405 /* Output assembly instructions to peform a conditional branch.
9407 INSN is the branch instruction. OPERANDS[0] is the condition.
9408 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9409 of the first operand to the condition. If TWO_OPERANDS_P is
9410 non-zero the comparison takes two operands; OPERANDS[3] will be the
9413 If INVERTED_P is non-zero we are to branch if the condition does
9414 not hold. If FLOAT_P is non-zero this is a floating-point comparison.
9416 LENGTH is the length (in bytes) of the sequence we are to generate.
9417 That tells us whether to generate a simple conditional branch, or a
9418 reversed conditional branch around a `jr' instruction. */
9420 mips_output_conditional_branch (insn,
9433 static char buffer[200];
9434 /* The kind of comparison we are doing. */
9435 enum rtx_code code = GET_CODE (operands[0]);
9436 /* Non-zero if the opcode for the comparison needs a `z' indicating
9437 that it is a comparision against zero. */
9439 /* A string to use in the assembly output to represent the first
9441 const char *op1 = "%z2";
9442 /* A string to use in the assembly output to represent the second
9443 operand. Use the hard-wired zero register if there's no second
9445 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9446 /* The operand-printing string for the comparison. */
9447 const char *comp = (float_p ? "%F0" : "%C0");
9448 /* The operand-printing string for the inverted comparison. */
9449 const char *inverted_comp = (float_p ? "%W0" : "%N0");
9451 /* The MIPS processors (for levels of the ISA at least two), have
9452 "likely" variants of each branch instruction. These instructions
9453 annul the instruction in the delay slot if the branch is not
9455 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9457 if (!two_operands_p)
9459 /* To compute whether than A > B, for example, we normally
9460 subtract B from A and then look at the sign bit. But, if we
9461 are doing an unsigned comparison, and B is zero, we don't
9462 have to do the subtraction. Instead, we can just check to
9463 see if A is non-zero. Thus, we change the CODE here to
9464 reflect the simpler comparison operation. */
9476 /* A condition which will always be true. */
9482 /* A condition which will always be false. */
9488 /* Not a special case. */
9493 /* Relative comparisons are always done against zero. But
9494 equality comparisons are done between two operands, and therefore
9495 do not require a `z' in the assembly language output. */
9496 need_z_p = (!float_p && code != EQ && code != NE);
9497 /* For comparisons against zero, the zero is not provided
9502 /* Begin by terminating the buffer. That way we can always use
9503 strcat to add to it. */
9510 /* Just a simple conditional branch. */
9512 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1",
9513 inverted_p ? inverted_comp : comp);
9515 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1",
9516 inverted_p ? inverted_comp : comp,
9517 need_z_p ? "z" : "",
9525 /* Generate a reversed conditional branch around ` j'
9537 Because we have to jump four bytes *past* the following
9538 instruction if this branch was annulled, we can't just use
9539 a label, as in the picture above; there's no way to put the
9540 label after the next instruction, as the assembler does not
9541 accept `.L+4' as the target of a branch. (We can't just
9542 wait until the next instruction is output; it might be a
9543 macro and take up more than four bytes. Once again, we see
9544 why we want to eliminate macros.)
9546 If the branch is annulled, we jump four more bytes that we
9547 would otherwise; that way we skip the annulled instruction
9548 in the delay slot. */
9551 = ((mips_branch_likely || length == 16) ? ".+16" : ".+12");
9554 strcpy (buffer, "%(%<");
9555 c = strchr (buffer, '\0');
9556 /* Generate the reversed comparision. This takes four
9559 sprintf (c, "%%*b%s\t%%Z2%s",
9560 inverted_p ? comp : inverted_comp,
9563 sprintf (c, "%%*b%s%s\t%s%s,%s",
9564 inverted_p ? comp : inverted_comp,
9565 need_z_p ? "z" : "",
9569 strcat (c, "\n\tnop\n\tj\t%1");
9571 /* The delay slot was unfilled. Since we're inside
9572 .noreorder, the assembler will not fill in the NOP for
9573 us, so we must do it ourselves. */
9574 strcat (buffer, "\n\tnop");
9575 strcat (buffer, "%>%)");
9579 /* We do not currently use this code. It handles jumps to
9580 arbitrary locations, using `jr', even across a 256MB boundary.
9581 We could add a -mhuge switch, and then use this code instead of
9582 the `j' alternative above when -mhuge was used. */
9587 /* Generate a reversed conditional branch around a `jr'
9601 Not pretty, but allows a conditional branch anywhere in the
9602 32-bit address space. If the original branch is annulled,
9603 then the instruction in the delay slot should be executed
9604 only if the branch is taken. The la instruction is really
9605 a macro which will usually take eight bytes, but sometimes
9606 takes only four, if the instruction to which we're jumping
9607 gets its own entry in the global pointer table, which will
9608 happen if its a case label. The assembler will then
9609 generate only a four-byte sequence, rather than eight, and
9610 there seems to be no way to tell it not to. Thus, we can't
9611 just use a `.+x' addressing form; we don't know what value
9614 So, we resort to using the explicit relocation syntax
9615 available in the assembler and do:
9617 lw $at,%got_page(target)($gp)
9618 daddiu $at,$at,%got_ofst(target)
9620 That way, this always takes up eight bytes, and we can use
9621 the `.+x' form. Of course, these explicit machinations
9622 with relocation will not work with old assemblers. Then
9623 again, neither do out-of-range branches, so we haven't lost
9626 /* The target of the reversed branch. */
9628 = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
9629 const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
9630 const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
9633 strcpy (buffer, "%(%<%[");
9634 c = strchr (buffer, '\0');
9635 /* Generate the reversed comparision. This takes four
9638 sprintf (c, "%%*b%s\t%%Z2%s",
9639 inverted_p ? comp : inverted_comp,
9642 sprintf (c, "%%*b%s%s\t%s%s,%s",
9643 inverted_p ? comp : inverted_comp,
9644 need_z_p ? "z" : "",
9648 c = strchr (buffer, '\0');
9649 /* Generate the load-address, and jump. This takes twelve
9650 bytes, for a total of 16. */
9652 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
9659 /* The delay slot was unfilled. Since we're inside
9660 .noreorder, the assembler will not fill in the NOP for
9661 us, so we must do it ourselves. */
9662 strcat (buffer, "\n\tnop");
9663 strcat (buffer, "%]%>%)");
9676 /* Called to register all of our global variables with the garbage
9680 mips_add_gc_roots ()
9682 ggc_add_rtx_root (&mips_load_reg, 1);
9683 ggc_add_rtx_root (&mips_load_reg2, 1);
9684 ggc_add_rtx_root (&mips_load_reg3, 1);
9685 ggc_add_rtx_root (&mips_load_reg4, 1);
9686 ggc_add_rtx_root (branch_cmp, sizeof (branch_cmp) / sizeof (rtx));
9687 ggc_add_rtx_root (&embedded_pic_fnaddr_rtx, 1);
9688 ggc_add_rtx_root (&mips16_gp_pseudo_rtx, 1);
9691 static enum processor_type
9692 mips_parse_cpu (cpu_string)
9693 const char *cpu_string;
9695 const char *p = cpu_string;
9697 enum processor_type cpu;
9699 /* We need to cope with the various "vr" prefixes for the NEC 4300
9700 and 4100 processors. */
9701 if (*p == 'v' || *p == 'V')
9704 if (*p == 'r' || *p == 'R')
9707 /* Since there is no difference between a R2000 and R3000 in
9708 terms of the scheduler, we collapse them into just an R3000. */
9710 cpu = PROCESSOR_DEFAULT;
9714 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
9715 cpu = PROCESSOR_R3000;
9719 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
9720 cpu = PROCESSOR_R3000;
9721 else if (!strcmp (p, "3900"))
9722 cpu = PROCESSOR_R3900;
9726 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
9727 cpu = PROCESSOR_R4000;
9728 /* The vr4100 is a non-FP ISA III processor with some extra
9730 else if (!strcmp (p, "4100"))
9731 cpu = PROCESSOR_R4100;
9732 /* The vr4300 is a standard ISA III processor, but with a different
9734 else if (!strcmp (p, "4300"))
9735 cpu = PROCESSOR_R4300;
9736 /* The r4400 is exactly the same as the r4000 from the compiler's
9738 else if (!strcmp (p, "4400"))
9739 cpu = PROCESSOR_R4000;
9740 else if (!strcmp (p, "4600"))
9741 cpu = PROCESSOR_R4600;
9742 else if (!strcmp (p, "4650"))
9743 cpu = PROCESSOR_R4650;
9747 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
9748 cpu = PROCESSOR_R5000;
9752 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
9753 cpu = PROCESSOR_R6000;
9757 if (!strcmp (p, "8000"))
9758 cpu = PROCESSOR_R8000;
9762 if (!strcmp (p, "orion"))
9763 cpu = PROCESSOR_R4600;
9768 && cpu != PROCESSOR_R4300
9769 && cpu != PROCESSOR_R4100
9770 && cpu != PROCESSOR_R5000)
9771 cpu = PROCESSOR_DEFAULT;
9776 /* Adjust the cost of INSN based on the relationship between INSN that
9777 is dependent on DEP_INSN through the dependence LINK. The default
9778 is to make no adjustment to COST.
9780 On the MIPS, ignore the cost of anti- and output-dependencies. */
9782 mips_adjust_cost (insn, link, dep, cost)
9783 rtx insn ATTRIBUTE_UNUSED;
9785 rtx dep ATTRIBUTE_UNUSED;
9788 if (REG_NOTE_KIND (link) != 0)
9789 return 0; /* Anti or output dependence. */
9793 /* Cover function for UNIQUE_SECTION. */
9796 mips_unique_section (decl, reloc)
9801 const char *name, *prefix;
9803 static const char *prefixes[4][2] = {
9804 { ".text.", ".gnu.linkonce.t." },
9805 { ".rodata.", ".gnu.linkonce.r." },
9806 { ".data.", ".gnu.linkonce.d." },
9807 { ".sdata.", ".gnu.linkonce.s." }
9810 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9811 size = int_size_in_bytes (TREE_TYPE (decl));
9813 /* Determine the base section we are interested in:
9814 0=text, 1=rodata, 2=data, 3=sdata, [4=bss]. */
9815 if (TREE_CODE (decl) == FUNCTION_DECL)
9817 else if (DECL_INITIAL (decl) == 0
9818 || DECL_INITIAL (decl) == error_mark_node)
9820 else if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
9821 && TREE_CODE (decl) == STRING_CST
9822 && !flag_writable_strings)
9824 /* For embedded position independent code, put constant
9825 strings in the text section, because the data section
9826 is limited to 64K in size. For mips16 code, put
9827 strings in the text section so that a PC relative load
9828 instruction can be used to get their address. */
9831 else if (TARGET_EMBEDDED_DATA)
9833 /* For embedded applications, always put an object in
9834 read-only data if possible, in order to reduce RAM
9837 if (DECL_READONLY_SECTION (decl, reloc))
9839 else if (size > 0 && size <= mips_section_threshold)
9846 /* For hosted applications, always put an object in
9847 small data if possible, as this gives the best
9850 if (size > 0 && size <= mips_section_threshold)
9852 else if (DECL_READONLY_SECTION (decl, reloc))
9858 prefix = prefixes[sec][DECL_ONE_ONLY (decl)];
9859 len = strlen (name) + strlen (prefix);
9860 string = alloca (len + 1);
9861 sprintf (string, "%s%s", prefix, name);
9863 DECL_SECTION_NAME (decl) = build_string (len, string);
9868 /* Output assembly to switch to section NAME with attribute FLAGS. */
9871 iris6_asm_named_section_1 (name, flags, align)
9876 unsigned int sh_type, sh_flags, sh_entsize;
9879 if (!(flags & SECTION_DEBUG))
9880 sh_flags |= 2; /* SHF_ALLOC */
9881 if (flags & SECTION_WRITE)
9882 sh_flags |= 1; /* SHF_WRITE */
9883 if (flags & SECTION_CODE)
9884 sh_flags |= 4; /* SHF_EXECINSTR */
9885 if (flags & SECTION_SMALL)
9886 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9887 if (strcmp (name, ".debug_frame") == 0)
9888 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9890 if (flags & SECTION_DEBUG)
9891 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9892 else if (flags & SECTION_BSS)
9893 sh_type = 8; /* SHT_NOBITS */
9895 sh_type = 1; /* SHT_PROGBITS */
9897 if (flags & SECTION_CODE)
9902 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9903 name, sh_type, sh_flags, sh_entsize, align);
9907 iris6_asm_named_section (name, flags)
9911 if (TARGET_FILE_SWITCHING && (flags & SECTION_CODE))
9912 asm_out_file = asm_out_text_file;
9913 iris6_asm_named_section_1 (name, flags, 0);
9916 /* In addition to emitting a .align directive, record the maximum
9917 alignment requested for the current section. */
9919 struct iris_section_align_entry
9926 static htab_t iris_section_align_htab;
9927 static FILE *iris_orig_asm_out_file;
9930 iris_section_align_entry_eq (p1, p2)
9934 const struct iris_section_align_entry *old = p1;
9935 const char *new = p2;
9937 return strcmp (old->name, new) == 0;
9941 iris_section_align_entry_hash (p)
9944 const struct iris_section_align_entry *old = p;
9945 return htab_hash_string (old->name);
9949 iris6_asm_output_align (file, log)
9953 const char *section = current_section_name ();
9954 struct iris_section_align_entry **slot, *entry;
9959 slot = (struct iris_section_align_entry **)
9960 htab_find_slot_with_hash (iris_section_align_htab, section,
9961 htab_hash_string (section), INSERT);
9965 entry = (struct iris_section_align_entry *)
9966 xmalloc (sizeof (struct iris_section_align_entry));
9968 entry->name = section;
9970 entry->flags = current_section_flags ();
9972 else if (entry->log < log)
9975 fprintf (file, "\t.align\t%u\n", log);
9978 /* The Iris assembler does not record alignment from .align directives,
9979 but takes it from the first .section directive seen. Play yet more
9980 file switching games so that we can emit a .section directive at the
9981 beginning of the file with the proper alignment attached. */
9984 iris6_asm_file_start (stream)
9987 mips_asm_file_start (stream);
9989 iris_orig_asm_out_file = asm_out_file;
9990 stream = tmpfile ();
9991 asm_out_file = stream;
9992 asm_out_data_file = stream;
9993 if (! TARGET_FILE_SWITCHING)
9994 asm_out_text_file = stream;
9996 iris_section_align_htab = htab_create (31, iris_section_align_entry_hash,
9997 iris_section_align_entry_eq, NULL);
10001 iris6_section_align_1 (slot, data)
10003 void *data ATTRIBUTE_UNUSED;
10005 const struct iris_section_align_entry *entry
10006 = *(const struct iris_section_align_entry **) slot;
10008 iris6_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
10013 iris6_asm_file_end (stream)
10016 /* Emit section directives with the proper alignment at the top of the
10017 real output file. */
10018 asm_out_file = iris_orig_asm_out_file;
10019 htab_traverse (iris_section_align_htab, iris6_section_align_1, NULL);
10021 /* Copy the data emitted to the temp file to the real output file. */
10022 copy_file_data (asm_out_file, stream);
10024 mips_asm_file_end (stream);
10026 #endif /* TARGET_IRIX6 */