1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
61 #define UNSPEC_ADDRESS_P(X) \
62 (GET_CODE (X) == UNSPEC \
63 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
64 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
66 /* Extract the symbol or label from UNSPEC wrapper X. */
67 #define UNSPEC_ADDRESS(X) \
70 /* Extract the symbol type from UNSPEC wrapper X. */
71 #define UNSPEC_ADDRESS_TYPE(X) \
72 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
74 /* The maximum distance between the top of the stack frame and the
75 value $sp has when we save & restore registers.
77 Use a maximum gap of 0x100 in the mips16 case. We can then use
78 unextended instructions to save and restore registers, and to
79 allocate and deallocate the top part of the frame.
81 The value in the !mips16 case must be a SMALL_OPERAND and must
82 preserve the maximum stack alignment. */
83 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7ff0)
85 /* True if INSN is a mips.md pattern or asm statement. */
86 #define USEFUL_INSN_P(INSN) \
88 && GET_CODE (PATTERN (INSN)) != USE \
89 && GET_CODE (PATTERN (INSN)) != CLOBBER \
90 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
91 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
93 /* If INSN is a delayed branch sequence, return the first instruction
94 in the sequence, otherwise return INSN itself. */
95 #define SEQ_BEGIN(INSN) \
96 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
97 ? XVECEXP (PATTERN (INSN), 0, 0) \
100 /* Likewise for the last instruction in a delayed branch sequence. */
101 #define SEQ_END(INSN) \
102 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
103 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
106 /* Execute the following loop body with SUBINSN set to each instruction
107 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
108 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
109 for ((SUBINSN) = SEQ_BEGIN (INSN); \
110 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
111 (SUBINSN) = NEXT_INSN (SUBINSN))
113 /* Classifies an address.
116 A natural register + offset address. The register satisfies
117 mips_valid_base_register_p and the offset is a const_arith_operand.
120 A LO_SUM rtx. The first operand is a valid base register and
121 the second operand is a symbolic address.
124 A signed 16-bit constant address.
127 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
128 enum mips_address_type {
135 /* Classifies the prototype of a builtin function. */
136 enum mips_function_type
138 MIPS_V2SF_FTYPE_V2SF,
139 MIPS_V2SF_FTYPE_V2SF_V2SF,
140 MIPS_V2SF_FTYPE_V2SF_V2SF_INT,
141 MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF,
142 MIPS_V2SF_FTYPE_SF_SF,
143 MIPS_INT_FTYPE_V2SF_V2SF,
144 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF,
145 MIPS_INT_FTYPE_SF_SF,
146 MIPS_INT_FTYPE_DF_DF,
157 /* Specifies how a builtin function should be converted into rtl. */
158 enum mips_builtin_type
160 /* The builtin corresponds directly to an .md pattern. The return
161 value is mapped to operand 0 and the arguments are mapped to
162 operands 1 and above. */
165 /* The builtin corresponds to a comparison instruction followed by
166 a mips_cond_move_tf_ps pattern. The first two arguments are the
167 values to compare and the second two arguments are the vector
168 operands for the movt.ps or movf.ps instruction (in assembly order). */
172 /* The builtin corresponds to a V2SF comparison instruction. Operand 0
173 of this instruction is the result of the comparison, which has mode
174 CCV2 or CCV4. The function arguments are mapped to operands 1 and
175 above. The function's return value is an SImode boolean that is
176 true under the following conditions:
178 MIPS_BUILTIN_CMP_ANY: one of the registers is true
179 MIPS_BUILTIN_CMP_ALL: all of the registers are true
180 MIPS_BUILTIN_CMP_LOWER: the first register is true
181 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
182 MIPS_BUILTIN_CMP_ANY,
183 MIPS_BUILTIN_CMP_ALL,
184 MIPS_BUILTIN_CMP_UPPER,
185 MIPS_BUILTIN_CMP_LOWER,
187 /* As above, but the instruction only sets a single $fcc register. */
188 MIPS_BUILTIN_CMP_SINGLE
191 /* Invokes MACRO (COND) for each c.cond.fmt condition. */
192 #define MIPS_FP_CONDITIONS(MACRO) \
210 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
211 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
212 enum mips_fp_condition {
213 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
216 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
217 #define STRINGIFY(X) #X
218 static const char *const mips_fp_conditions[] = {
219 MIPS_FP_CONDITIONS (STRINGIFY)
222 /* A function to save or store a register. The first argument is the
223 register and the second is the stack slot. */
224 typedef void (*mips_save_restore_fn) (rtx, rtx);
226 struct mips16_constant;
227 struct mips_arg_info;
228 struct mips_address_info;
229 struct mips_integer_op;
232 static enum mips_symbol_type mips_classify_symbol (rtx);
233 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
234 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
235 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
236 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
237 static bool mips_classify_address (struct mips_address_info *, rtx,
238 enum machine_mode, int);
239 static int mips_symbol_insns (enum mips_symbol_type);
240 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
241 static rtx mips_force_temporary (rtx, rtx);
242 static rtx mips_split_symbol (rtx, rtx);
243 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
244 static rtx mips_add_offset (rtx, rtx, HOST_WIDE_INT);
245 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
246 static unsigned int mips_build_lower (struct mips_integer_op *,
247 unsigned HOST_WIDE_INT);
248 static unsigned int mips_build_integer (struct mips_integer_op *,
249 unsigned HOST_WIDE_INT);
250 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
251 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
252 static int m16_check_op (rtx, int, int, int);
253 static bool mips_rtx_costs (rtx, int, int, int *);
254 static int mips_address_cost (rtx);
255 static void mips_emit_compare (enum rtx_code *, rtx *, rtx *, bool);
256 static void mips_load_call_address (rtx, rtx, int);
257 static bool mips_function_ok_for_sibcall (tree, tree);
258 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
259 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
260 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
261 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
262 tree, int, struct mips_arg_info *);
263 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
264 static void mips_set_architecture (const struct mips_cpu_info *);
265 static void mips_set_tune (const struct mips_cpu_info *);
266 static struct machine_function *mips_init_machine_status (void);
267 static void print_operand_reloc (FILE *, rtx, const char **);
269 static void irix_output_external_libcall (rtx);
271 static void mips_file_start (void);
272 static void mips_file_end (void);
273 static bool mips_rewrite_small_data_p (rtx);
274 static int mips_small_data_pattern_1 (rtx *, void *);
275 static int mips_rewrite_small_data_1 (rtx *, void *);
276 static bool mips_function_has_gp_insn (void);
277 static unsigned int mips_global_pointer (void);
278 static bool mips_save_reg_p (unsigned int);
279 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
280 mips_save_restore_fn);
281 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
282 static void mips_output_cplocal (void);
283 static void mips_emit_loadgp (void);
284 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
285 static void mips_set_frame_expr (rtx);
286 static rtx mips_frame_set (rtx, rtx);
287 static void mips_save_reg (rtx, rtx);
288 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
289 static void mips_restore_reg (rtx, rtx);
290 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
291 HOST_WIDE_INT, tree);
292 static int symbolic_expression_p (rtx);
293 static void mips_select_rtx_section (enum machine_mode, rtx,
294 unsigned HOST_WIDE_INT);
295 static void mips_function_rodata_section (tree);
296 static bool mips_in_small_data_p (tree);
297 static int mips_fpr_return_fields (tree, tree *);
298 static bool mips_return_in_msb (tree);
299 static rtx mips_return_fpr_pair (enum machine_mode mode,
300 enum machine_mode mode1, HOST_WIDE_INT,
301 enum machine_mode mode2, HOST_WIDE_INT);
302 static rtx mips16_gp_pseudo_reg (void);
303 static void mips16_fp_args (FILE *, int, int);
304 static void build_mips16_function_stub (FILE *);
305 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
306 static void dump_constants (struct mips16_constant *, rtx);
307 static int mips16_insn_length (rtx);
308 static int mips16_rewrite_pool_refs (rtx *, void *);
309 static void mips16_lay_out_constants (void);
310 static void mips_sim_reset (struct mips_sim *);
311 static void mips_sim_init (struct mips_sim *, state_t);
312 static void mips_sim_next_cycle (struct mips_sim *);
313 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
314 static int mips_sim_wait_regs_2 (rtx *, void *);
315 static void mips_sim_wait_regs_1 (rtx *, void *);
316 static void mips_sim_wait_regs (struct mips_sim *, rtx);
317 static void mips_sim_wait_units (struct mips_sim *, rtx);
318 static void mips_sim_wait_insn (struct mips_sim *, rtx);
319 static void mips_sim_record_set (rtx, rtx, void *);
320 static void mips_sim_issue_insn (struct mips_sim *, rtx);
321 static void mips_sim_issue_nop (struct mips_sim *);
322 static void mips_sim_finish_insn (struct mips_sim *, rtx);
323 static void vr4130_avoid_branch_rt_conflict (rtx);
324 static void vr4130_align_insns (void);
325 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
326 static void mips_avoid_hazards (void);
327 static void mips_reorg (void);
328 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
329 static bool mips_matching_cpu_name_p (const char *, const char *);
330 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
331 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
332 static bool mips_return_in_memory (tree, tree);
333 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
334 static void mips_macc_chains_record (rtx);
335 static void mips_macc_chains_reorder (rtx *, int);
336 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
337 static bool vr4130_true_reg_dependence_p (rtx);
338 static bool vr4130_swap_insns_p (rtx, rtx);
339 static void vr4130_reorder (rtx *, int);
340 static void mips_promote_ready (rtx *, int, int);
341 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
342 static int mips_variable_issue (FILE *, int, rtx, int);
343 static int mips_adjust_cost (rtx, rtx, rtx, int);
344 static int mips_issue_rate (void);
345 static int mips_multipass_dfa_lookahead (void);
346 static void mips_init_libfuncs (void);
347 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
349 static tree mips_build_builtin_va_list (void);
350 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
351 static bool mips_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode mode,
353 static bool mips_callee_copies (CUMULATIVE_ARGS *, enum machine_mode mode,
355 static bool mips_valid_pointer_mode (enum machine_mode);
356 static bool mips_scalar_mode_supported_p (enum machine_mode);
357 static bool mips_vector_mode_supported_p (enum machine_mode);
358 static rtx mips_prepare_builtin_arg (enum insn_code, unsigned int, tree *);
359 static rtx mips_prepare_builtin_target (enum insn_code, unsigned int, rtx);
360 static rtx mips_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
361 static void mips_init_builtins (void);
362 static rtx mips_expand_builtin_direct (enum insn_code, rtx, tree);
363 static rtx mips_expand_builtin_movtf (enum mips_builtin_type,
364 enum insn_code, enum mips_fp_condition,
366 static rtx mips_expand_builtin_compare (enum mips_builtin_type,
367 enum insn_code, enum mips_fp_condition,
370 /* Structure to be filled in by compute_frame_size with register
371 save masks, and offsets for the current function. */
373 struct mips_frame_info GTY(())
375 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
376 HOST_WIDE_INT var_size; /* # bytes that variables take up */
377 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
378 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
379 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
380 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
381 unsigned int mask; /* mask of saved gp registers */
382 unsigned int fmask; /* mask of saved fp registers */
383 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
384 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
385 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
386 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
387 bool initialized; /* true if frame size already calculated */
388 int num_gp; /* number of gp registers saved */
389 int num_fp; /* number of fp registers saved */
392 struct machine_function GTY(()) {
393 /* Pseudo-reg holding the value of $28 in a mips16 function which
394 refers to GP relative global variables. */
395 rtx mips16_gp_pseudo_rtx;
397 /* Current frame information, calculated by compute_frame_size. */
398 struct mips_frame_info frame;
400 /* The register to use as the global pointer within this function. */
401 unsigned int global_pointer;
403 /* True if mips_adjust_insn_length should ignore an instruction's
405 bool ignore_hazard_length_p;
407 /* True if the whole function is suitable for .set noreorder and
409 bool all_noreorder_p;
411 /* True if the function is known to have an instruction that needs $gp. */
415 /* Information about a single argument. */
418 /* True if the argument is passed in a floating-point register, or
419 would have been if we hadn't run out of registers. */
422 /* The number of words passed in registers, rounded up. */
423 unsigned int reg_words;
425 /* For EABI, the offset of the first register from GP_ARG_FIRST or
426 FP_ARG_FIRST. For other ABIs, the offset of the first register from
427 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
428 comment for details).
430 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
432 unsigned int reg_offset;
434 /* The number of words that must be passed on the stack, rounded up. */
435 unsigned int stack_words;
437 /* The offset from the start of the stack overflow area of the argument's
438 first stack word. Only meaningful when STACK_WORDS is nonzero. */
439 unsigned int stack_offset;
443 /* Information about an address described by mips_address_type.
449 REG is the base register and OFFSET is the constant offset.
452 REG is the register that contains the high part of the address,
453 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
454 is the type of OFFSET's symbol.
457 SYMBOL_TYPE is the type of symbol being referenced. */
459 struct mips_address_info
461 enum mips_address_type type;
464 enum mips_symbol_type symbol_type;
468 /* One stage in a constant building sequence. These sequences have
472 A = A CODE[1] VALUE[1]
473 A = A CODE[2] VALUE[2]
476 where A is an accumulator, each CODE[i] is a binary rtl operation
477 and each VALUE[i] is a constant integer. */
478 struct mips_integer_op {
480 unsigned HOST_WIDE_INT value;
484 /* The largest number of operations needed to load an integer constant.
485 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
486 When the lowest bit is clear, we can try, but reject a sequence with
487 an extra SLL at the end. */
488 #define MIPS_MAX_INTEGER_OPS 7
491 /* Global variables for machine-dependent things. */
493 /* Threshold for data being put into the small data/bss area, instead
494 of the normal data area. */
495 int mips_section_threshold = -1;
497 /* Count the number of .file directives, so that .loc is up to date. */
498 int num_source_filenames = 0;
500 /* Count the number of sdb related labels are generated (to find block
501 start and end boundaries). */
502 int sdb_label_count = 0;
504 /* Next label # for each statement for Silicon Graphics IRIS systems. */
507 /* Linked list of all externals that are to be emitted when optimizing
508 for the global pointer if they haven't been declared by the end of
509 the program with an appropriate .comm or initialization. */
511 struct extern_list GTY (())
513 struct extern_list *next; /* next external */
514 const char *name; /* name of the external */
515 int size; /* size in bytes */
518 static GTY (()) struct extern_list *extern_head = 0;
520 /* Name of the file containing the current function. */
521 const char *current_function_file = "";
523 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
529 /* The next branch instruction is a branch likely, not branch normal. */
530 int mips_branch_likely;
532 /* The operands passed to the last cmpMM expander. */
535 /* The target cpu for code generation. */
536 enum processor_type mips_arch;
537 const struct mips_cpu_info *mips_arch_info;
539 /* The target cpu for optimization and scheduling. */
540 enum processor_type mips_tune;
541 const struct mips_cpu_info *mips_tune_info;
543 /* Which instruction set architecture to use. */
546 /* Which ABI to use. */
549 /* Strings to hold which cpu and instruction set architecture to use. */
550 const char *mips_arch_string; /* for -march=<xxx> */
551 const char *mips_tune_string; /* for -mtune=<xxx> */
552 const char *mips_isa_string; /* for -mips{1,2,3,4} */
553 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
555 /* Whether we are generating mips16 hard float code. In mips16 mode
556 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
557 -msoft-float was not specified by the user, which means that we
558 should arrange to call mips32 hard floating point code. */
559 int mips16_hard_float;
561 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
563 /* If TRUE, we split addresses into their high and low parts in the RTL. */
564 int mips_split_addresses;
566 /* Mode used for saving/restoring general purpose registers. */
567 static enum machine_mode gpr_mode;
569 /* Array giving truth value on whether or not a given hard register
570 can support a given mode. */
571 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
573 /* List of all MIPS punctuation characters used by print_operand. */
574 char mips_print_operand_punct[256];
576 /* Map GCC register number to debugger register number. */
577 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
579 /* A copy of the original flag_delayed_branch: see override_options. */
580 static int mips_flag_delayed_branch;
582 static GTY (()) int mips_output_filename_first_time = 1;
584 /* mips_split_p[X] is true if symbols of type X can be split by
585 mips_split_symbol(). */
586 static bool mips_split_p[NUM_SYMBOL_TYPES];
588 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
589 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
590 if they are matched by a special .md file pattern. */
591 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
593 /* Likewise for HIGHs. */
594 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
596 /* Map hard register number to register class */
597 const enum reg_class mips_regno_to_class[] =
599 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
600 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
601 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
602 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
603 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
604 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
605 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
606 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
607 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
608 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
609 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
610 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
611 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
612 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
613 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
614 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
615 HI_REG, LO_REG, NO_REGS, ST_REGS,
616 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
617 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
618 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
619 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
620 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
621 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
622 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
623 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
624 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
625 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
626 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
627 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
628 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
629 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
630 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
631 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
632 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
633 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
634 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
635 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
636 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
637 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
638 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
639 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
640 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
641 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
642 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
645 /* Map register constraint character to register class. */
646 enum reg_class mips_char_to_class[256];
648 /* A table describing all the processors gcc knows about. Names are
649 matched in the order listed. The first mention of an ISA level is
650 taken as the canonical name for that ISA.
652 To ease comparison, please keep this table in the same order as
653 gas's mips_cpu_info_table[]. */
654 const struct mips_cpu_info mips_cpu_info_table[] = {
655 /* Entries for generic ISAs */
656 { "mips1", PROCESSOR_R3000, 1 },
657 { "mips2", PROCESSOR_R6000, 2 },
658 { "mips3", PROCESSOR_R4000, 3 },
659 { "mips4", PROCESSOR_R8000, 4 },
660 { "mips32", PROCESSOR_4KC, 32 },
661 { "mips32r2", PROCESSOR_M4K, 33 },
662 { "mips64", PROCESSOR_5KC, 64 },
665 { "r3000", PROCESSOR_R3000, 1 },
666 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
667 { "r3900", PROCESSOR_R3900, 1 },
670 { "r6000", PROCESSOR_R6000, 2 },
673 { "r4000", PROCESSOR_R4000, 3 },
674 { "vr4100", PROCESSOR_R4100, 3 },
675 { "vr4111", PROCESSOR_R4111, 3 },
676 { "vr4120", PROCESSOR_R4120, 3 },
677 { "vr4130", PROCESSOR_R4130, 3 },
678 { "vr4300", PROCESSOR_R4300, 3 },
679 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
680 { "r4600", PROCESSOR_R4600, 3 },
681 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
682 { "r4650", PROCESSOR_R4650, 3 },
685 { "r8000", PROCESSOR_R8000, 4 },
686 { "vr5000", PROCESSOR_R5000, 4 },
687 { "vr5400", PROCESSOR_R5400, 4 },
688 { "vr5500", PROCESSOR_R5500, 4 },
689 { "rm7000", PROCESSOR_R7000, 4 },
690 { "rm9000", PROCESSOR_R9000, 4 },
693 { "4kc", PROCESSOR_4KC, 32 },
694 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
696 /* MIPS32 Release 2 */
697 { "m4k", PROCESSOR_M4K, 33 },
700 { "5kc", PROCESSOR_5KC, 64 },
701 { "20kc", PROCESSOR_20KC, 64 },
702 { "sb1", PROCESSOR_SB1, 64 },
703 { "sr71000", PROCESSOR_SR71000, 64 },
709 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
710 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
711 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
714 /* Initialize the GCC target structure. */
715 #undef TARGET_ASM_ALIGNED_HI_OP
716 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
717 #undef TARGET_ASM_ALIGNED_SI_OP
718 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
719 #undef TARGET_ASM_ALIGNED_DI_OP
720 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
722 #undef TARGET_ASM_FUNCTION_PROLOGUE
723 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
724 #undef TARGET_ASM_FUNCTION_EPILOGUE
725 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
726 #undef TARGET_ASM_SELECT_RTX_SECTION
727 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
728 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
729 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
731 #undef TARGET_SCHED_REORDER
732 #define TARGET_SCHED_REORDER mips_sched_reorder
733 #undef TARGET_SCHED_VARIABLE_ISSUE
734 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
735 #undef TARGET_SCHED_ADJUST_COST
736 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
737 #undef TARGET_SCHED_ISSUE_RATE
738 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
739 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
740 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
741 mips_multipass_dfa_lookahead
743 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
744 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
746 #undef TARGET_VALID_POINTER_MODE
747 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
748 #undef TARGET_RTX_COSTS
749 #define TARGET_RTX_COSTS mips_rtx_costs
750 #undef TARGET_ADDRESS_COST
751 #define TARGET_ADDRESS_COST mips_address_cost
753 #undef TARGET_IN_SMALL_DATA_P
754 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
756 #undef TARGET_MACHINE_DEPENDENT_REORG
757 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
759 #undef TARGET_ASM_FILE_START
760 #undef TARGET_ASM_FILE_END
761 #define TARGET_ASM_FILE_START mips_file_start
762 #define TARGET_ASM_FILE_END mips_file_end
763 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
764 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
766 #undef TARGET_INIT_LIBFUNCS
767 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
769 #undef TARGET_BUILD_BUILTIN_VA_LIST
770 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
771 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
772 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
774 #undef TARGET_PROMOTE_FUNCTION_ARGS
775 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
776 #undef TARGET_PROMOTE_FUNCTION_RETURN
777 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
778 #undef TARGET_PROMOTE_PROTOTYPES
779 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
781 #undef TARGET_RETURN_IN_MEMORY
782 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
783 #undef TARGET_RETURN_IN_MSB
784 #define TARGET_RETURN_IN_MSB mips_return_in_msb
786 #undef TARGET_ASM_OUTPUT_MI_THUNK
787 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
788 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
789 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
791 #undef TARGET_SETUP_INCOMING_VARARGS
792 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
793 #undef TARGET_STRICT_ARGUMENT_NAMING
794 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
795 #undef TARGET_MUST_PASS_IN_STACK
796 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
797 #undef TARGET_PASS_BY_REFERENCE
798 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
799 #undef TARGET_CALLEE_COPIES
800 #define TARGET_CALLEE_COPIES mips_callee_copies
802 #undef TARGET_VECTOR_MODE_SUPPORTED_P
803 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
805 #undef TARGET_SCALAR_MODE_SUPPORTED_P
806 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
808 #undef TARGET_INIT_BUILTINS
809 #define TARGET_INIT_BUILTINS mips_init_builtins
810 #undef TARGET_EXPAND_BUILTIN
811 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
813 struct gcc_target targetm = TARGET_INITIALIZER;
815 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
817 static enum mips_symbol_type
818 mips_classify_symbol (rtx x)
820 if (GET_CODE (x) == LABEL_REF)
823 return SYMBOL_CONSTANT_POOL;
825 return SYMBOL_GOT_LOCAL;
826 return SYMBOL_GENERAL;
829 gcc_assert (GET_CODE (x) == SYMBOL_REF);
831 if (CONSTANT_POOL_ADDRESS_P (x))
834 return SYMBOL_CONSTANT_POOL;
837 return SYMBOL_GOT_LOCAL;
839 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
840 return SYMBOL_SMALL_DATA;
842 return SYMBOL_GENERAL;
845 if (SYMBOL_REF_SMALL_P (x))
846 return SYMBOL_SMALL_DATA;
850 if (SYMBOL_REF_DECL (x) == 0)
851 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
853 /* There are three cases to consider:
855 - o32 PIC (either with or without explicit relocs)
856 - n32/n64 PIC without explicit relocs
857 - n32/n64 PIC with explicit relocs
859 In the first case, both local and global accesses will use an
860 R_MIPS_GOT16 relocation. We must correctly predict which of
861 the two semantics (local or global) the assembler and linker
862 will apply. The choice doesn't depend on the symbol's
863 visibility, so we deliberately ignore decl_visibility and
866 In the second case, the assembler will not use R_MIPS_GOT16
867 relocations, but it chooses between local and global accesses
868 in the same way as for o32 PIC.
870 In the third case we have more freedom since both forms of
871 access will work for any kind of symbol. However, there seems
872 little point in doing things differently. */
873 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
874 return SYMBOL_GOT_GLOBAL;
876 return SYMBOL_GOT_LOCAL;
879 return SYMBOL_GENERAL;
883 /* Split X into a base and a constant offset, storing them in *BASE
884 and *OFFSET respectively. */
887 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
891 if (GET_CODE (x) == CONST)
894 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
896 *offset += INTVAL (XEXP (x, 1));
903 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
904 to the same object as SYMBOL. */
907 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
909 if (GET_CODE (symbol) != SYMBOL_REF)
912 if (CONSTANT_POOL_ADDRESS_P (symbol)
914 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
917 if (SYMBOL_REF_DECL (symbol) != 0
919 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
926 /* Return true if X is a symbolic constant that can be calculated in
927 the same way as a bare symbol. If it is, store the type of the
928 symbol in *SYMBOL_TYPE. */
931 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
933 HOST_WIDE_INT offset;
935 mips_split_const (x, &x, &offset);
936 if (UNSPEC_ADDRESS_P (x))
937 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
938 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
939 *symbol_type = mips_classify_symbol (x);
946 /* Check whether a nonzero offset is valid for the underlying
948 switch (*symbol_type)
954 /* If the target has 64-bit pointers and the object file only
955 supports 32-bit symbols, the values of those symbols will be
956 sign-extended. In this case we can't allow an arbitrary offset
957 in case the 32-bit value X + OFFSET has a different sign from X. */
958 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
959 return mips_offset_within_object_p (x, offset);
961 /* In other cases the relocations can handle any offset. */
964 case SYMBOL_CONSTANT_POOL:
965 /* Allow constant pool references to be converted to LABEL+CONSTANT.
966 In this case, we no longer have access to the underlying constant,
967 but the original symbol-based access was known to be valid. */
968 if (GET_CODE (x) == LABEL_REF)
973 case SYMBOL_SMALL_DATA:
974 /* Make sure that the offset refers to something within the
975 underlying object. This should guarantee that the final
976 PC- or GP-relative offset is within the 16-bit limit. */
977 return mips_offset_within_object_p (x, offset);
979 case SYMBOL_GOT_LOCAL:
980 case SYMBOL_GOTOFF_PAGE:
981 /* The linker should provide enough local GOT entries for a
982 16-bit offset. Larger offsets may lead to GOT overflow. */
983 return SMALL_OPERAND (offset);
985 case SYMBOL_GOT_GLOBAL:
986 case SYMBOL_GOTOFF_GLOBAL:
987 case SYMBOL_GOTOFF_CALL:
988 case SYMBOL_GOTOFF_LOADGP:
995 /* Return true if X is a symbolic constant whose value is not split
996 into separate relocations. */
999 mips_atomic_symbolic_constant_p (rtx x)
1001 enum mips_symbol_type type;
1002 return mips_symbolic_constant_p (x, &type) && !mips_split_p[type];
1006 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
1009 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
1011 if (regno >= FIRST_PSEUDO_REGISTER)
1015 regno = reg_renumber[regno];
1018 /* These fake registers will be eliminated to either the stack or
1019 hard frame pointer, both of which are usually valid base registers.
1020 Reload deals with the cases where the eliminated form isn't valid. */
1021 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
1024 /* In mips16 mode, the stack pointer can only address word and doubleword
1025 values, nothing smaller. There are two problems here:
1027 (a) Instantiating virtual registers can introduce new uses of the
1028 stack pointer. If these virtual registers are valid addresses,
1029 the stack pointer should be too.
1031 (b) Most uses of the stack pointer are not made explicit until
1032 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
1033 We don't know until that stage whether we'll be eliminating to the
1034 stack pointer (which needs the restriction) or the hard frame
1035 pointer (which doesn't).
1037 All in all, it seems more consistent to only enforce this restriction
1038 during and after reload. */
1039 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
1040 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1042 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
1046 /* Return true if X is a valid base register for the given mode.
1047 Allow only hard registers if STRICT. */
1050 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
1052 if (!strict && GET_CODE (x) == SUBREG)
1056 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
1060 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
1061 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
1064 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
1065 enum machine_mode mode)
1067 switch (symbol_type)
1069 case SYMBOL_GENERAL:
1070 return !TARGET_MIPS16;
1072 case SYMBOL_SMALL_DATA:
1075 case SYMBOL_CONSTANT_POOL:
1076 /* PC-relative addressing is only available for lw and ld. */
1077 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1079 case SYMBOL_GOT_LOCAL:
1082 case SYMBOL_GOT_GLOBAL:
1083 /* The address will have to be loaded from the GOT first. */
1086 case SYMBOL_GOTOFF_PAGE:
1087 case SYMBOL_GOTOFF_GLOBAL:
1088 case SYMBOL_GOTOFF_CALL:
1089 case SYMBOL_GOTOFF_LOADGP:
1090 case SYMBOL_64_HIGH:
1099 /* Return true if X is a valid address for machine mode MODE. If it is,
1100 fill in INFO appropriately. STRICT is true if we should only accept
1101 hard base registers. */
1104 mips_classify_address (struct mips_address_info *info, rtx x,
1105 enum machine_mode mode, int strict)
1107 switch (GET_CODE (x))
1111 info->type = ADDRESS_REG;
1113 info->offset = const0_rtx;
1114 return mips_valid_base_register_p (info->reg, mode, strict);
1117 info->type = ADDRESS_REG;
1118 info->reg = XEXP (x, 0);
1119 info->offset = XEXP (x, 1);
1120 return (mips_valid_base_register_p (info->reg, mode, strict)
1121 && const_arith_operand (info->offset, VOIDmode));
1124 info->type = ADDRESS_LO_SUM;
1125 info->reg = XEXP (x, 0);
1126 info->offset = XEXP (x, 1);
1127 return (mips_valid_base_register_p (info->reg, mode, strict)
1128 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1129 && mips_symbolic_address_p (info->symbol_type, mode)
1130 && mips_lo_relocs[info->symbol_type] != 0);
1133 /* Small-integer addresses don't occur very often, but they
1134 are legitimate if $0 is a valid base register. */
1135 info->type = ADDRESS_CONST_INT;
1136 return !TARGET_MIPS16 && SMALL_INT (x);
1141 info->type = ADDRESS_SYMBOLIC;
1142 return (mips_symbolic_constant_p (x, &info->symbol_type)
1143 && mips_symbolic_address_p (info->symbol_type, mode)
1144 && !mips_split_p[info->symbol_type]);
1151 /* Return the number of instructions needed to load a symbol of the
1152 given type into a register. If valid in an address, the same number
1153 of instructions are needed for loads and stores. Treat extended
1154 mips16 instructions as two instructions. */
1157 mips_symbol_insns (enum mips_symbol_type type)
1161 case SYMBOL_GENERAL:
1162 /* In mips16 code, general symbols must be fetched from the
1167 /* When using 64-bit symbols, we need 5 preparatory instructions,
1170 lui $at,%highest(symbol)
1171 daddiu $at,$at,%higher(symbol)
1173 daddiu $at,$at,%hi(symbol)
1176 The final address is then $at + %lo(symbol). With 32-bit
1177 symbols we just need a preparatory lui. */
1178 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1180 case SYMBOL_SMALL_DATA:
1183 case SYMBOL_CONSTANT_POOL:
1184 /* This case is for mips16 only. Assume we'll need an
1185 extended instruction. */
1188 case SYMBOL_GOT_LOCAL:
1189 case SYMBOL_GOT_GLOBAL:
1190 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1191 the local/global classification is accurate. See override_options
1194 The worst cases are:
1196 (1) For local symbols when generating o32 or o64 code. The assembler
1202 ...and the final address will be $at + %lo(symbol).
1204 (2) For global symbols when -mxgot. The assembler will use:
1206 lui $at,%got_hi(symbol)
1209 ...and the final address will be $at + %got_lo(symbol). */
1212 case SYMBOL_GOTOFF_PAGE:
1213 case SYMBOL_GOTOFF_GLOBAL:
1214 case SYMBOL_GOTOFF_CALL:
1215 case SYMBOL_GOTOFF_LOADGP:
1216 case SYMBOL_64_HIGH:
1219 /* Check whether the offset is a 16- or 32-bit value. */
1220 return mips_split_p[type] ? 2 : 1;
1225 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
1228 mips_stack_address_p (rtx x, enum machine_mode mode)
1230 struct mips_address_info addr;
1232 return (mips_classify_address (&addr, x, mode, false)
1233 && addr.type == ADDRESS_REG
1234 && addr.reg == stack_pointer_rtx);
1237 /* Return true if a value at OFFSET bytes from BASE can be accessed
1238 using an unextended mips16 instruction. MODE is the mode of the
1241 Usually the offset in an unextended instruction is a 5-bit field.
1242 The offset is unsigned and shifted left once for HIs, twice
1243 for SIs, and so on. An exception is SImode accesses off the
1244 stack pointer, which have an 8-bit immediate field. */
1247 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1250 && GET_CODE (offset) == CONST_INT
1251 && INTVAL (offset) >= 0
1252 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1254 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1255 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1256 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1262 /* Return the number of instructions needed to load or store a value
1263 of mode MODE at X. Return 0 if X isn't valid for MODE.
1265 For mips16 code, count extended instructions as two instructions. */
1268 mips_address_insns (rtx x, enum machine_mode mode)
1270 struct mips_address_info addr;
1273 if (mode == BLKmode)
1274 /* BLKmode is used for single unaligned loads and stores. */
1277 /* Each word of a multi-word value will be accessed individually. */
1278 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1280 if (mips_classify_address (&addr, x, mode, false))
1285 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1289 case ADDRESS_LO_SUM:
1290 return (TARGET_MIPS16 ? factor * 2 : factor);
1292 case ADDRESS_CONST_INT:
1295 case ADDRESS_SYMBOLIC:
1296 return factor * mips_symbol_insns (addr.symbol_type);
1302 /* Likewise for constant X. */
1305 mips_const_insns (rtx x)
1307 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1308 enum mips_symbol_type symbol_type;
1309 HOST_WIDE_INT offset;
1311 switch (GET_CODE (x))
1315 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1316 || !mips_split_p[symbol_type])
1323 /* Unsigned 8-bit constants can be loaded using an unextended
1324 LI instruction. Unsigned 16-bit constants can be loaded
1325 using an extended LI. Negative constants must be loaded
1326 using LI and then negated. */
1327 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1328 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1329 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1330 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1333 return mips_build_integer (codes, INTVAL (x));
1337 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1343 /* See if we can refer to X directly. */
1344 if (mips_symbolic_constant_p (x, &symbol_type))
1345 return mips_symbol_insns (symbol_type);
1347 /* Otherwise try splitting the constant into a base and offset.
1348 16-bit offsets can be added using an extra addiu. Larger offsets
1349 must be calculated separately and then added to the base. */
1350 mips_split_const (x, &x, &offset);
1353 int n = mips_const_insns (x);
1356 if (SMALL_OPERAND (offset))
1359 return n + 1 + mips_build_integer (codes, offset);
1366 return mips_symbol_insns (mips_classify_symbol (x));
1374 /* Return the number of instructions needed for memory reference X.
1375 Count extended mips16 instructions as two instructions. */
1378 mips_fetch_insns (rtx x)
1380 gcc_assert (MEM_P (x));
1381 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1385 /* Return the number of instructions needed for an integer division. */
1388 mips_idiv_insns (void)
1393 if (TARGET_CHECK_ZERO_DIV)
1395 if (GENERATE_DIVIDE_TRAPS)
1401 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1406 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1407 returns a nonzero value if X is a legitimate address for a memory
1408 operand of the indicated MODE. STRICT is nonzero if this function
1409 is called during reload. */
1412 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1414 struct mips_address_info addr;
1416 return mips_classify_address (&addr, x, mode, strict);
1420 /* Copy VALUE to a register and return that register. If new psuedos
1421 are allowed, copy it into a new register, otherwise use DEST. */
1424 mips_force_temporary (rtx dest, rtx value)
1426 if (!no_new_pseudos)
1427 return force_reg (Pmode, value);
1430 emit_move_insn (copy_rtx (dest), value);
1436 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1437 and is used to load the high part into a register. */
1440 mips_split_symbol (rtx temp, rtx addr)
1445 high = mips16_gp_pseudo_reg ();
1447 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1448 return gen_rtx_LO_SUM (Pmode, high, addr);
1452 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1453 type SYMBOL_TYPE. */
1456 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1459 HOST_WIDE_INT offset;
1461 mips_split_const (address, &base, &offset);
1462 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1463 UNSPEC_ADDRESS_FIRST + symbol_type);
1464 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1468 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1469 high part to BASE and return the result. Just return BASE otherwise.
1470 TEMP is available as a temporary register if needed.
1472 The returned expression can be used as the first operand to a LO_SUM. */
1475 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1476 enum mips_symbol_type symbol_type)
1478 if (mips_split_p[symbol_type])
1480 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1481 addr = mips_force_temporary (temp, addr);
1482 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1488 /* Return a legitimate address for REG + OFFSET. TEMP is as for
1489 mips_force_temporary; it is only needed when OFFSET is not a
1493 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
1495 if (!SMALL_OPERAND (offset))
1500 /* Load the full offset into a register so that we can use
1501 an unextended instruction for the address itself. */
1502 high = GEN_INT (offset);
1507 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. */
1508 high = GEN_INT (CONST_HIGH_PART (offset));
1509 offset = CONST_LOW_PART (offset);
1511 high = mips_force_temporary (temp, high);
1512 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
1514 return plus_constant (reg, offset);
1518 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1519 be legitimized in a way that the generic machinery might not expect,
1520 put the new address in *XLOC and return true. MODE is the mode of
1521 the memory being accessed. */
1524 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1526 enum mips_symbol_type symbol_type;
1528 /* See if the address can split into a high part and a LO_SUM. */
1529 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1530 && mips_symbolic_address_p (symbol_type, mode)
1531 && mips_split_p[symbol_type])
1533 *xloc = mips_split_symbol (0, *xloc);
1537 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1539 /* Handle REG + CONSTANT using mips_add_offset. */
1542 reg = XEXP (*xloc, 0);
1543 if (!mips_valid_base_register_p (reg, mode, 0))
1544 reg = copy_to_mode_reg (Pmode, reg);
1545 *xloc = mips_add_offset (0, reg, INTVAL (XEXP (*xloc, 1)));
1553 /* Subroutine of mips_build_integer (with the same interface).
1554 Assume that the final action in the sequence should be a left shift. */
1557 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1559 unsigned int i, shift;
1561 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1562 since signed numbers are easier to load than unsigned ones. */
1564 while ((value & 1) == 0)
1565 value /= 2, shift++;
1567 i = mips_build_integer (codes, value);
1568 codes[i].code = ASHIFT;
1569 codes[i].value = shift;
1574 /* As for mips_build_shift, but assume that the final action will be
1575 an IOR or PLUS operation. */
1578 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1580 unsigned HOST_WIDE_INT high;
1583 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1584 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1586 /* The constant is too complex to load with a simple lui/ori pair
1587 so our goal is to clear as many trailing zeros as possible.
1588 In this case, we know bit 16 is set and that the low 16 bits
1589 form a negative number. If we subtract that number from VALUE,
1590 we will clear at least the lowest 17 bits, maybe more. */
1591 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1592 codes[i].code = PLUS;
1593 codes[i].value = CONST_LOW_PART (value);
1597 i = mips_build_integer (codes, high);
1598 codes[i].code = IOR;
1599 codes[i].value = value & 0xffff;
1605 /* Fill CODES with a sequence of rtl operations to load VALUE.
1606 Return the number of operations needed. */
1609 mips_build_integer (struct mips_integer_op *codes,
1610 unsigned HOST_WIDE_INT value)
1612 if (SMALL_OPERAND (value)
1613 || SMALL_OPERAND_UNSIGNED (value)
1614 || LUI_OPERAND (value))
1616 /* The value can be loaded with a single instruction. */
1617 codes[0].code = UNKNOWN;
1618 codes[0].value = value;
1621 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1623 /* Either the constant is a simple LUI/ORI combination or its
1624 lowest bit is set. We don't want to shift in this case. */
1625 return mips_build_lower (codes, value);
1627 else if ((value & 0xffff) == 0)
1629 /* The constant will need at least three actions. The lowest
1630 16 bits are clear, so the final action will be a shift. */
1631 return mips_build_shift (codes, value);
1635 /* The final action could be a shift, add or inclusive OR.
1636 Rather than use a complex condition to select the best
1637 approach, try both mips_build_shift and mips_build_lower
1638 and pick the one that gives the shortest sequence.
1639 Note that this case is only used once per constant. */
1640 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1641 unsigned int cost, alt_cost;
1643 cost = mips_build_shift (codes, value);
1644 alt_cost = mips_build_lower (alt_codes, value);
1645 if (alt_cost < cost)
1647 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1655 /* Move VALUE into register DEST. */
1658 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1660 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1661 enum machine_mode mode;
1662 unsigned int i, cost;
1665 mode = GET_MODE (dest);
1666 cost = mips_build_integer (codes, value);
1668 /* Apply each binary operation to X. Invariant: X is a legitimate
1669 source operand for a SET pattern. */
1670 x = GEN_INT (codes[0].value);
1671 for (i = 1; i < cost; i++)
1674 emit_move_insn (dest, x), x = dest;
1676 x = force_reg (mode, x);
1677 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1680 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1684 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1685 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1689 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1692 HOST_WIDE_INT offset;
1693 enum mips_symbol_type symbol_type;
1695 /* Split moves of big integers into smaller pieces. In mips16 code,
1696 it's better to force the constant into memory instead. */
1697 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1699 mips_move_integer (dest, INTVAL (src));
1703 /* See if the symbol can be split. For mips16, this is often worse than
1704 forcing it in the constant pool since it needs the single-register form
1705 of addiu or daddiu. */
1707 && mips_symbolic_constant_p (src, &symbol_type)
1708 && mips_split_p[symbol_type])
1710 emit_move_insn (dest, mips_split_symbol (dest, src));
1714 /* If we have (const (plus symbol offset)), load the symbol first
1715 and then add in the offset. This is usually better than forcing
1716 the constant into memory, at least in non-mips16 code. */
1717 mips_split_const (src, &base, &offset);
1720 && (!no_new_pseudos || SMALL_OPERAND (offset)))
1722 base = mips_force_temporary (dest, base);
1723 emit_move_insn (dest, mips_add_offset (0, base, offset));
1727 src = force_const_mem (mode, src);
1729 /* When using explicit relocs, constant pool references are sometimes
1730 not legitimate addresses. */
1731 if (!memory_operand (src, VOIDmode))
1732 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1733 emit_move_insn (dest, src);
1737 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1738 sequence that is valid. */
1741 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
1743 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1745 emit_move_insn (dest, force_reg (mode, src));
1749 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
1750 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1751 && REG_P (src) && MD_REG_P (REGNO (src))
1752 && REG_P (dest) && GP_REG_P (REGNO (dest)))
1754 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
1755 if (GET_MODE_SIZE (mode) <= 4)
1756 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
1757 gen_rtx_REG (SImode, REGNO (src)),
1758 gen_rtx_REG (SImode, other_regno)));
1760 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
1761 gen_rtx_REG (DImode, REGNO (src)),
1762 gen_rtx_REG (DImode, other_regno)));
1766 /* We need to deal with constants that would be legitimate
1767 immediate_operands but not legitimate move_operands. */
1768 if (CONSTANT_P (src) && !move_operand (src, mode))
1770 mips_legitimize_const_move (mode, dest, src);
1771 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
1777 /* We need a lot of little routines to check constant values on the
1778 mips16. These are used to figure out how long the instruction will
1779 be. It would be much better to do this using constraints, but
1780 there aren't nearly enough letters available. */
1783 m16_check_op (rtx op, int low, int high, int mask)
1785 return (GET_CODE (op) == CONST_INT
1786 && INTVAL (op) >= low
1787 && INTVAL (op) <= high
1788 && (INTVAL (op) & mask) == 0);
1792 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1794 return m16_check_op (op, 0x1, 0x8, 0);
1798 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1800 return m16_check_op (op, - 0x8, 0x7, 0);
1804 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1806 return m16_check_op (op, - 0x7, 0x8, 0);
1810 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1812 return m16_check_op (op, - 0x10, 0xf, 0);
1816 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1818 return m16_check_op (op, - 0xf, 0x10, 0);
1822 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1824 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1828 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1830 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1834 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1836 return m16_check_op (op, - 0x80, 0x7f, 0);
1840 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1842 return m16_check_op (op, - 0x7f, 0x80, 0);
1846 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1848 return m16_check_op (op, 0x0, 0xff, 0);
1852 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1854 return m16_check_op (op, - 0xff, 0x0, 0);
1858 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1860 return m16_check_op (op, - 0x1, 0xfe, 0);
1864 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1866 return m16_check_op (op, 0x0, 0xff << 2, 3);
1870 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1872 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1876 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1878 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1882 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1884 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1888 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
1890 enum machine_mode mode = GET_MODE (x);
1897 /* Always return 0, since we don't have different sized
1898 instructions, hence different costs according to Richard
1904 /* A number between 1 and 8 inclusive is efficient for a shift.
1905 Otherwise, we will need an extended instruction. */
1906 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
1907 || (outer_code) == LSHIFTRT)
1909 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
1912 *total = COSTS_N_INSNS (1);
1916 /* We can use cmpi for an xor with an unsigned 16 bit value. */
1917 if ((outer_code) == XOR
1918 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
1924 /* We may be able to use slt or sltu for a comparison with a
1925 signed 16 bit value. (The boundary conditions aren't quite
1926 right, but this is just a heuristic anyhow.) */
1927 if (((outer_code) == LT || (outer_code) == LE
1928 || (outer_code) == GE || (outer_code) == GT
1929 || (outer_code) == LTU || (outer_code) == LEU
1930 || (outer_code) == GEU || (outer_code) == GTU)
1931 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
1937 /* Equality comparisons with 0 are cheap. */
1938 if (((outer_code) == EQ || (outer_code) == NE)
1945 /* Constants in the range 0...255 can be loaded with an unextended
1946 instruction. They are therefore as cheap as a register move.
1948 Given the choice between "li R1,0...255" and "move R1,R2"
1949 (where R2 is a known constant), it is usually better to use "li",
1950 since we do not want to unnecessarily extend the lifetime of R2. */
1951 if (outer_code == SET
1953 && INTVAL (x) < 256)
1959 /* Otherwise fall through to the handling below. */
1965 if (LEGITIMATE_CONSTANT_P (x))
1967 *total = COSTS_N_INSNS (1);
1972 /* The value will need to be fetched from the constant pool. */
1973 *total = CONSTANT_POOL_COST;
1979 /* If the address is legitimate, return the number of
1980 instructions it needs, otherwise use the default handling. */
1981 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
1984 *total = COSTS_N_INSNS (1 + n);
1991 *total = COSTS_N_INSNS (6);
1995 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2001 if (mode == DImode && !TARGET_64BIT)
2003 *total = COSTS_N_INSNS (2);
2011 if (mode == DImode && !TARGET_64BIT)
2013 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2020 if (mode == SFmode || mode == DFmode)
2021 *total = COSTS_N_INSNS (1);
2023 *total = COSTS_N_INSNS (4);
2027 *total = COSTS_N_INSNS (1);
2032 if (mode == SFmode || mode == DFmode)
2034 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2035 *total = COSTS_N_INSNS (2);
2036 else if (TUNE_MIPS6000)
2037 *total = COSTS_N_INSNS (3);
2039 *total = COSTS_N_INSNS (4);
2041 *total = COSTS_N_INSNS (6);
2044 if (mode == DImode && !TARGET_64BIT)
2046 *total = COSTS_N_INSNS (4);
2052 if (mode == DImode && !TARGET_64BIT)
2066 *total = COSTS_N_INSNS (4);
2067 else if (TUNE_MIPS6000
2070 *total = COSTS_N_INSNS (5);
2072 *total = COSTS_N_INSNS (7);
2079 *total = COSTS_N_INSNS (4);
2080 else if (TUNE_MIPS3000
2083 *total = COSTS_N_INSNS (5);
2084 else if (TUNE_MIPS6000
2087 *total = COSTS_N_INSNS (6);
2089 *total = COSTS_N_INSNS (8);
2094 *total = COSTS_N_INSNS (12);
2095 else if (TUNE_MIPS3900)
2096 *total = COSTS_N_INSNS (2);
2097 else if (TUNE_MIPS4130)
2098 *total = COSTS_N_INSNS (mode == DImode ? 6 : 4);
2099 else if (TUNE_MIPS5400 || TUNE_SB1)
2100 *total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
2101 else if (TUNE_MIPS5500 || TUNE_MIPS7000)
2102 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2103 else if (TUNE_MIPS9000)
2104 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2105 else if (TUNE_MIPS6000)
2106 *total = COSTS_N_INSNS (17);
2107 else if (TUNE_MIPS5000)
2108 *total = COSTS_N_INSNS (5);
2110 *total = COSTS_N_INSNS (10);
2119 *total = COSTS_N_INSNS (12);
2120 else if (TUNE_MIPS6000)
2121 *total = COSTS_N_INSNS (15);
2123 *total = COSTS_N_INSNS (24);
2124 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2125 *total = COSTS_N_INSNS (30);
2127 *total = COSTS_N_INSNS (23);
2135 *total = COSTS_N_INSNS (19);
2136 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2137 *total = COSTS_N_INSNS (59);
2138 else if (TUNE_MIPS6000)
2139 *total = COSTS_N_INSNS (16);
2141 *total = COSTS_N_INSNS (32);
2143 *total = COSTS_N_INSNS (36);
2152 *total = COSTS_N_INSNS (35);
2153 else if (TUNE_MIPS6000)
2154 *total = COSTS_N_INSNS (38);
2155 else if (TUNE_MIPS5000)
2156 *total = COSTS_N_INSNS (36);
2158 *total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
2159 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2160 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2162 *total = COSTS_N_INSNS (69);
2166 /* A sign extend from SImode to DImode in 64 bit mode is often
2167 zero instructions, because the result can often be used
2168 directly by another instruction; we'll call it one. */
2169 if (TARGET_64BIT && mode == DImode
2170 && GET_MODE (XEXP (x, 0)) == SImode)
2171 *total = COSTS_N_INSNS (1);
2173 *total = COSTS_N_INSNS (2);
2177 if (TARGET_64BIT && mode == DImode
2178 && GET_MODE (XEXP (x, 0)) == SImode)
2179 *total = COSTS_N_INSNS (2);
2181 *total = COSTS_N_INSNS (1);
2189 /* Provide the costs of an addressing mode that contains ADDR.
2190 If ADDR is not a valid address, its cost is irrelevant. */
2193 mips_address_cost (rtx addr)
2195 return mips_address_insns (addr, SImode);
2198 /* Return one word of double-word value OP, taking into account the fixed
2199 endianness of certain registers. HIGH_P is true to select the high part,
2200 false to select the low part. */
2203 mips_subword (rtx op, int high_p)
2206 enum machine_mode mode;
2208 mode = GET_MODE (op);
2209 if (mode == VOIDmode)
2212 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2213 byte = UNITS_PER_WORD;
2219 if (FP_REG_P (REGNO (op)))
2220 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2221 if (REGNO (op) == HI_REGNUM)
2222 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2226 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2228 return simplify_gen_subreg (word_mode, op, mode, byte);
2232 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2235 mips_split_64bit_move_p (rtx dest, rtx src)
2240 /* FP->FP moves can be done in a single instruction. */
2241 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2244 /* Check for floating-point loads and stores. They can be done using
2245 ldc1 and sdc1 on MIPS II and above. */
2248 if (FP_REG_RTX_P (dest) && MEM_P (src))
2250 if (FP_REG_RTX_P (src) && MEM_P (dest))
2257 /* Split a 64-bit move from SRC to DEST assuming that
2258 mips_split_64bit_move_p holds.
2260 Moves into and out of FPRs cause some difficulty here. Such moves
2261 will always be DFmode, since paired FPRs are not allowed to store
2262 DImode values. The most natural representation would be two separate
2263 32-bit moves, such as:
2265 (set (reg:SI $f0) (mem:SI ...))
2266 (set (reg:SI $f1) (mem:SI ...))
2268 However, the second insn is invalid because odd-numbered FPRs are
2269 not allowed to store independent values. Use the patterns load_df_low,
2270 load_df_high and store_df_high instead. */
2273 mips_split_64bit_move (rtx dest, rtx src)
2275 if (FP_REG_RTX_P (dest))
2277 /* Loading an FPR from memory or from GPRs. */
2278 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2279 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2282 else if (FP_REG_RTX_P (src))
2284 /* Storing an FPR into memory or GPRs. */
2285 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2286 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2290 /* The operation can be split into two normal moves. Decide in
2291 which order to do them. */
2294 low_dest = mips_subword (dest, 0);
2295 if (REG_P (low_dest)
2296 && reg_overlap_mentioned_p (low_dest, src))
2298 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2299 emit_move_insn (low_dest, mips_subword (src, 0));
2303 emit_move_insn (low_dest, mips_subword (src, 0));
2304 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2309 /* Return the appropriate instructions to move SRC into DEST. Assume
2310 that SRC is operand 1 and DEST is operand 0. */
2313 mips_output_move (rtx dest, rtx src)
2315 enum rtx_code dest_code, src_code;
2318 dest_code = GET_CODE (dest);
2319 src_code = GET_CODE (src);
2320 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2322 if (dbl_p && mips_split_64bit_move_p (dest, src))
2325 if ((src_code == REG && GP_REG_P (REGNO (src)))
2326 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2328 if (dest_code == REG)
2330 if (GP_REG_P (REGNO (dest)))
2331 return "move\t%0,%z1";
2333 if (MD_REG_P (REGNO (dest)))
2336 if (FP_REG_P (REGNO (dest)))
2337 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2339 if (ALL_COP_REG_P (REGNO (dest)))
2341 static char retval[] = "dmtc_\t%z1,%0";
2343 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2344 return (dbl_p ? retval : retval + 1);
2347 if (dest_code == MEM)
2348 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2350 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2352 if (src_code == REG)
2354 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2355 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2357 if (FP_REG_P (REGNO (src)))
2358 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2360 if (ALL_COP_REG_P (REGNO (src)))
2362 static char retval[] = "dmfc_\t%0,%1";
2364 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2365 return (dbl_p ? retval : retval + 1);
2369 if (src_code == MEM)
2370 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2372 if (src_code == CONST_INT)
2374 /* Don't use the X format, because that will give out of
2375 range numbers for 64 bit hosts and 32 bit targets. */
2377 return "li\t%0,%1\t\t\t# %X1";
2379 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2382 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2386 if (src_code == HIGH)
2387 return "lui\t%0,%h1";
2389 if (CONST_GP_P (src))
2390 return "move\t%0,%1";
2392 if (symbolic_operand (src, VOIDmode))
2393 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2395 if (src_code == REG && FP_REG_P (REGNO (src)))
2397 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2399 if (GET_MODE (dest) == V2SFmode)
2400 return "mov.ps\t%0,%1";
2402 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2405 if (dest_code == MEM)
2406 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2408 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2410 if (src_code == MEM)
2411 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2413 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2415 static char retval[] = "l_c_\t%0,%1";
2417 retval[1] = (dbl_p ? 'd' : 'w');
2418 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2421 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2423 static char retval[] = "s_c_\t%1,%0";
2425 retval[1] = (dbl_p ? 'd' : 'w');
2426 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2432 /* Restore $gp from its save slot. Valid only when using o32 or
2436 mips_restore_gp (void)
2440 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI);
2442 address = mips_add_offset (pic_offset_table_rtx,
2443 frame_pointer_needed
2444 ? hard_frame_pointer_rtx
2445 : stack_pointer_rtx,
2446 current_function_outgoing_args_size);
2447 slot = gen_rtx_MEM (Pmode, address);
2449 emit_move_insn (pic_offset_table_rtx, slot);
2450 if (!TARGET_EXPLICIT_RELOCS)
2451 emit_insn (gen_blockage ());
2454 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2457 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2459 emit_insn (gen_rtx_SET (VOIDmode, target,
2460 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2463 /* Return true if CMP1 is a suitable second operand for relational
2464 operator CODE. See also the *sCC patterns in mips.md. */
2467 mips_relational_operand_ok_p (enum rtx_code code, rtx cmp1)
2473 return reg_or_0_operand (cmp1, VOIDmode);
2477 return !TARGET_MIPS16 && cmp1 == const1_rtx;
2481 return arith_operand (cmp1, VOIDmode);
2484 return sle_operand (cmp1, VOIDmode);
2487 return sleu_operand (cmp1, VOIDmode);
2494 /* Compare CMP0 and CMP1 using relational operator CODE and store the
2495 result in TARGET. CMP0 and TARGET are register_operands that have
2496 the same integer mode. If INVERT_PTR is nonnull, it's OK to set
2497 TARGET to the inverse of the result and flip *INVERT_PTR instead. */
2500 mips_emit_int_relational (enum rtx_code code, bool *invert_ptr,
2501 rtx target, rtx cmp0, rtx cmp1)
2503 /* First see if there is a MIPS instruction that can do this operation
2504 with CMP1 in its current form. If not, try doing the same for the
2505 inverse operation. If that also fails, force CMP1 into a register
2507 if (mips_relational_operand_ok_p (code, cmp1))
2508 mips_emit_binary (code, target, cmp0, cmp1);
2511 enum rtx_code inv_code = reverse_condition (code);
2512 if (!mips_relational_operand_ok_p (inv_code, cmp1))
2514 cmp1 = force_reg (GET_MODE (cmp0), cmp1);
2515 mips_emit_int_relational (code, invert_ptr, target, cmp0, cmp1);
2517 else if (invert_ptr == 0)
2519 rtx inv_target = gen_reg_rtx (GET_MODE (target));
2520 mips_emit_binary (inv_code, inv_target, cmp0, cmp1);
2521 mips_emit_binary (XOR, target, inv_target, const1_rtx);
2525 *invert_ptr = !*invert_ptr;
2526 mips_emit_binary (inv_code, target, cmp0, cmp1);
2531 /* Return a register that is zero iff CMP0 and CMP1 are equal.
2532 The register will have the same mode as CMP0. */
2535 mips_zero_if_equal (rtx cmp0, rtx cmp1)
2537 if (cmp1 == const0_rtx)
2540 if (uns_arith_operand (cmp1, VOIDmode))
2541 return expand_binop (GET_MODE (cmp0), xor_optab,
2542 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2544 return expand_binop (GET_MODE (cmp0), sub_optab,
2545 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
2548 /* Convert a comparison into something that can be used in a branch or
2549 conditional move. cmp_operands[0] and cmp_operands[1] are the values
2550 being compared and *CODE is the code used to compare them.
2552 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
2553 If NEED_EQ_NE_P, then only EQ/NE comparisons against zero are possible,
2554 otherwise any standard branch condition can be used. The standard branch
2557 - EQ/NE between two registers.
2558 - any comparison between a register and zero. */
2561 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
2563 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT)
2565 if (!need_eq_ne_p && cmp_operands[1] == const0_rtx)
2567 *op0 = cmp_operands[0];
2568 *op1 = cmp_operands[1];
2570 else if (*code == EQ || *code == NE)
2574 *op0 = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2579 *op0 = cmp_operands[0];
2580 *op1 = force_reg (GET_MODE (*op0), cmp_operands[1]);
2585 /* The comparison needs a separate scc instruction. Store the
2586 result of the scc in *OP0 and compare it against zero. */
2587 bool invert = false;
2588 *op0 = gen_reg_rtx (GET_MODE (cmp_operands[0]));
2590 mips_emit_int_relational (*code, &invert, *op0,
2591 cmp_operands[0], cmp_operands[1]);
2592 *code = (invert ? EQ : NE);
2597 enum rtx_code cmp_code;
2599 /* Floating-point tests use a separate c.cond.fmt comparison to
2600 set a condition code register. The branch or conditional move
2601 will then compare that register against zero.
2603 Set CMP_CODE to the code of the comparison instruction and
2604 *CODE to the code that the branch or move should use. */
2612 cmp_code = reverse_condition_maybe_unordered (*code);
2622 ? gen_reg_rtx (CCmode)
2623 : gen_rtx_REG (CCmode, FPSW_REGNUM));
2625 mips_emit_binary (cmp_code, *op0, cmp_operands[0], cmp_operands[1]);
2629 /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE.
2630 Store the result in TARGET and return true if successful.
2632 On 64-bit targets, TARGET may be wider than cmp_operands[0]. */
2635 mips_emit_scc (enum rtx_code code, rtx target)
2637 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT)
2640 target = gen_lowpart (GET_MODE (cmp_operands[0]), target);
2641 if (code == EQ || code == NE)
2643 rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]);
2644 mips_emit_binary (code, target, zie, const0_rtx);
2647 mips_emit_int_relational (code, 0, target,
2648 cmp_operands[0], cmp_operands[1]);
2652 /* Emit the common code for doing conditional branches.
2653 operand[0] is the label to jump to.
2654 The comparison operands are saved away by cmp{si,di,sf,df}. */
2657 gen_conditional_branch (rtx *operands, enum rtx_code code)
2659 rtx op0, op1, target;
2661 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
2662 target = gen_rtx_IF_THEN_ELSE (VOIDmode,
2663 gen_rtx_fmt_ee (code, GET_MODE (op0),
2665 gen_rtx_LABEL_REF (VOIDmode, operands[0]),
2667 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, target));
2670 /* Emit the common code for conditional moves. OPERANDS is the array
2671 of operands passed to the conditional move define_expand. */
2674 gen_conditional_move (rtx *operands)
2679 code = GET_CODE (operands[1]);
2680 mips_emit_compare (&code, &op0, &op1, true);
2681 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2682 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2683 gen_rtx_fmt_ee (code,
2686 operands[2], operands[3])));
2689 /* Emit a conditional trap. OPERANDS is the array of operands passed to
2690 the conditional_trap expander. */
2693 mips_gen_conditional_trap (rtx *operands)
2696 enum rtx_code cmp_code = GET_CODE (operands[0]);
2697 enum machine_mode mode = GET_MODE (cmp_operands[0]);
2699 /* MIPS conditional trap machine instructions don't have GT or LE
2700 flavors, so we must invert the comparison and convert to LT and
2701 GE, respectively. */
2704 case GT: cmp_code = LT; break;
2705 case LE: cmp_code = GE; break;
2706 case GTU: cmp_code = LTU; break;
2707 case LEU: cmp_code = GEU; break;
2710 if (cmp_code == GET_CODE (operands[0]))
2712 op0 = cmp_operands[0];
2713 op1 = cmp_operands[1];
2717 op0 = cmp_operands[1];
2718 op1 = cmp_operands[0];
2720 op0 = force_reg (mode, op0);
2721 if (!arith_operand (op1, mode))
2722 op1 = force_reg (mode, op1);
2724 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
2725 gen_rtx_fmt_ee (cmp_code, mode, op0, op1),
2729 /* Load function address ADDR into register DEST. SIBCALL_P is true
2730 if the address is needed for a sibling call. */
2733 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
2735 /* If we're generating PIC, and this call is to a global function,
2736 try to allow its address to be resolved lazily. This isn't
2737 possible for NewABI sibcalls since the value of $gp on entry
2738 to the stub would be our caller's gp, not ours. */
2739 if (TARGET_EXPLICIT_RELOCS
2740 && !(sibcall_p && TARGET_NEWABI)
2741 && global_got_operand (addr, VOIDmode))
2743 rtx high, lo_sum_symbol;
2745 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
2746 addr, SYMBOL_GOTOFF_CALL);
2747 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
2748 if (Pmode == SImode)
2749 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
2751 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
2754 emit_move_insn (dest, addr);
2758 /* Expand a call or call_value instruction. RESULT is where the
2759 result will go (null for calls), ADDR is the address of the
2760 function, ARGS_SIZE is the size of the arguments and AUX is
2761 the value passed to us by mips_function_arg. SIBCALL_P is true
2762 if we are expanding a sibling call, false if we're expanding
2766 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
2768 rtx orig_addr, pattern, insn;
2771 if (!call_insn_operand (addr, VOIDmode))
2773 addr = gen_reg_rtx (Pmode);
2774 mips_load_call_address (addr, orig_addr, sibcall_p);
2778 && mips16_hard_float
2779 && build_mips16_call_stub (result, addr, args_size,
2780 aux == 0 ? 0 : (int) GET_MODE (aux)))
2784 pattern = (sibcall_p
2785 ? gen_sibcall_internal (addr, args_size)
2786 : gen_call_internal (addr, args_size));
2787 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
2791 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
2792 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
2795 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
2796 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
2799 pattern = (sibcall_p
2800 ? gen_sibcall_value_internal (result, addr, args_size)
2801 : gen_call_value_internal (result, addr, args_size));
2803 insn = emit_call_insn (pattern);
2805 /* Lazy-binding stubs require $gp to be valid on entry. */
2806 if (global_got_operand (orig_addr, VOIDmode))
2807 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2811 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
2814 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
2815 tree exp ATTRIBUTE_UNUSED)
2817 return TARGET_SIBCALLS;
2820 /* Emit code to move general operand SRC into condition-code
2821 register DEST. SCRATCH is a scratch TFmode float register.
2828 where FP1 and FP2 are single-precision float registers
2829 taken from SCRATCH. */
2832 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
2836 /* Change the source to SFmode. */
2838 src = adjust_address (src, SFmode, 0);
2839 else if (REG_P (src) || GET_CODE (src) == SUBREG)
2840 src = gen_rtx_REG (SFmode, true_regnum (src));
2842 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
2843 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
2845 emit_move_insn (copy_rtx (fp1), src);
2846 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
2847 emit_insn (gen_slt_sf (dest, fp2, fp1));
2850 /* Emit code to change the current function's return address to
2851 ADDRESS. SCRATCH is available as a scratch register, if needed.
2852 ADDRESS and SCRATCH are both word-mode GPRs. */
2855 mips_set_return_address (rtx address, rtx scratch)
2859 compute_frame_size (get_frame_size ());
2860 gcc_assert ((cfun->machine->frame.mask >> 31) & 1);
2861 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
2862 cfun->machine->frame.gp_sp_offset);
2864 emit_move_insn (gen_rtx_MEM (GET_MODE (address), slot_address), address);
2867 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
2868 Assume that the areas do not overlap. */
2871 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
2873 HOST_WIDE_INT offset, delta;
2874 unsigned HOST_WIDE_INT bits;
2876 enum machine_mode mode;
2879 /* Work out how many bits to move at a time. If both operands have
2880 half-word alignment, it is usually better to move in half words.
2881 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
2882 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
2883 Otherwise move word-sized chunks. */
2884 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
2885 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
2886 bits = BITS_PER_WORD / 2;
2888 bits = BITS_PER_WORD;
2890 mode = mode_for_size (bits, MODE_INT, 0);
2891 delta = bits / BITS_PER_UNIT;
2893 /* Allocate a buffer for the temporary registers. */
2894 regs = alloca (sizeof (rtx) * length / delta);
2896 /* Load as many BITS-sized chunks as possible. Use a normal load if
2897 the source has enough alignment, otherwise use left/right pairs. */
2898 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
2900 regs[i] = gen_reg_rtx (mode);
2901 if (MEM_ALIGN (src) >= bits)
2902 emit_move_insn (regs[i], adjust_address (src, mode, offset));
2905 rtx part = adjust_address (src, BLKmode, offset);
2906 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
2911 /* Copy the chunks to the destination. */
2912 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
2913 if (MEM_ALIGN (dest) >= bits)
2914 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
2917 rtx part = adjust_address (dest, BLKmode, offset);
2918 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
2922 /* Mop up any left-over bytes. */
2923 if (offset < length)
2925 src = adjust_address (src, BLKmode, offset);
2926 dest = adjust_address (dest, BLKmode, offset);
2927 move_by_pieces (dest, src, length - offset,
2928 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
2932 #define MAX_MOVE_REGS 4
2933 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2936 /* Helper function for doing a loop-based block operation on memory
2937 reference MEM. Each iteration of the loop will operate on LENGTH
2940 Create a new base register for use within the loop and point it to
2941 the start of MEM. Create a new memory reference that uses this
2942 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
2945 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
2946 rtx *loop_reg, rtx *loop_mem)
2948 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
2950 /* Although the new mem does not refer to a known location,
2951 it does keep up to LENGTH bytes of alignment. */
2952 *loop_mem = change_address (mem, BLKmode, *loop_reg);
2953 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
2957 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
2958 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
2959 memory regions do not overlap. */
2962 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
2964 rtx label, src_reg, dest_reg, final_src;
2965 HOST_WIDE_INT leftover;
2967 leftover = length % MAX_MOVE_BYTES;
2970 /* Create registers and memory references for use within the loop. */
2971 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
2972 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
2974 /* Calculate the value that SRC_REG should have after the last iteration
2976 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
2979 /* Emit the start of the loop. */
2980 label = gen_label_rtx ();
2983 /* Emit the loop body. */
2984 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
2986 /* Move on to the next block. */
2987 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
2988 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
2990 /* Emit the loop condition. */
2991 if (Pmode == DImode)
2992 emit_insn (gen_cmpdi (src_reg, final_src));
2994 emit_insn (gen_cmpsi (src_reg, final_src));
2995 emit_jump_insn (gen_bne (label));
2997 /* Mop up any left-over bytes. */
2999 mips_block_move_straight (dest, src, leftover);
3002 /* Expand a movmemsi instruction. */
3005 mips_expand_block_move (rtx dest, rtx src, rtx length)
3007 if (GET_CODE (length) == CONST_INT)
3009 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3011 mips_block_move_straight (dest, src, INTVAL (length));
3016 mips_block_move_loop (dest, src, INTVAL (length));
3023 /* Argument support functions. */
3025 /* Initialize CUMULATIVE_ARGS for a function. */
3028 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3029 rtx libname ATTRIBUTE_UNUSED)
3031 static CUMULATIVE_ARGS zero_cum;
3032 tree param, next_param;
3035 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3037 /* Determine if this function has variable arguments. This is
3038 indicated by the last argument being 'void_type_mode' if there
3039 are no variable arguments. The standard MIPS calling sequence
3040 passes all arguments in the general purpose registers in this case. */
3042 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3043 param != 0; param = next_param)
3045 next_param = TREE_CHAIN (param);
3046 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3047 cum->gp_reg_found = 1;
3052 /* Fill INFO with information about a single argument. CUM is the
3053 cumulative state for earlier arguments. MODE is the mode of this
3054 argument and TYPE is its type (if known). NAMED is true if this
3055 is a named (fixed) argument rather than a variable one. */
3058 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3059 tree type, int named, struct mips_arg_info *info)
3061 bool doubleword_aligned_p;
3062 unsigned int num_bytes, num_words, max_regs;
3064 /* Work out the size of the argument. */
3065 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
3066 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3068 /* Decide whether it should go in a floating-point register, assuming
3069 one is free. Later code checks for availability.
3071 The checks against UNITS_PER_FPVALUE handle the soft-float and
3072 single-float cases. */
3076 /* The EABI conventions have traditionally been defined in terms
3077 of TYPE_MODE, regardless of the actual type. */
3078 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
3079 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3080 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3085 /* Only leading floating-point scalars are passed in
3086 floating-point registers. We also handle vector floats the same
3087 say, which is OK because they are not covered by the standard ABI. */
3088 info->fpr_p = (!cum->gp_reg_found
3089 && cum->arg_number < 2
3090 && (type == 0 || SCALAR_FLOAT_TYPE_P (type)
3091 || VECTOR_FLOAT_TYPE_P (type))
3092 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3093 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3094 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3099 /* Scalar and complex floating-point types are passed in
3100 floating-point registers. */
3101 info->fpr_p = (named
3102 && (type == 0 || FLOAT_TYPE_P (type))
3103 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3104 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3105 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3106 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
3108 /* ??? According to the ABI documentation, the real and imaginary
3109 parts of complex floats should be passed in individual registers.
3110 The real and imaginary parts of stack arguments are supposed
3111 to be contiguous and there should be an extra word of padding
3114 This has two problems. First, it makes it impossible to use a
3115 single "void *" va_list type, since register and stack arguments
3116 are passed differently. (At the time of writing, MIPSpro cannot
3117 handle complex float varargs correctly.) Second, it's unclear
3118 what should happen when there is only one register free.
3120 For now, we assume that named complex floats should go into FPRs
3121 if there are two FPRs free, otherwise they should be passed in the
3122 same way as a struct containing two floats. */
3124 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
3125 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
3127 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
3128 info->fpr_p = false;
3138 /* See whether the argument has doubleword alignment. */
3139 doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD;
3141 /* Set REG_OFFSET to the register count we're interested in.
3142 The EABI allocates the floating-point registers separately,
3143 but the other ABIs allocate them like integer registers. */
3144 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3148 /* Advance to an even register if the argument is doubleword-aligned. */
3149 if (doubleword_aligned_p)
3150 info->reg_offset += info->reg_offset & 1;
3152 /* Work out the offset of a stack argument. */
3153 info->stack_offset = cum->stack_words;
3154 if (doubleword_aligned_p)
3155 info->stack_offset += info->stack_offset & 1;
3157 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3159 /* Partition the argument between registers and stack. */
3160 info->reg_words = MIN (num_words, max_regs);
3161 info->stack_words = num_words - info->reg_words;
3165 /* Implement FUNCTION_ARG_ADVANCE. */
3168 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3169 tree type, int named)
3171 struct mips_arg_info info;
3173 mips_arg_info (cum, mode, type, named, &info);
3176 cum->gp_reg_found = true;
3178 /* See the comment above the cumulative args structure in mips.h
3179 for an explanation of what this code does. It assumes the O32
3180 ABI, which passes at most 2 arguments in float registers. */
3181 if (cum->arg_number < 2 && info.fpr_p)
3182 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3184 if (mips_abi != ABI_EABI || !info.fpr_p)
3185 cum->num_gprs = info.reg_offset + info.reg_words;
3186 else if (info.reg_words > 0)
3187 cum->num_fprs += FP_INC;
3189 if (info.stack_words > 0)
3190 cum->stack_words = info.stack_offset + info.stack_words;
3195 /* Implement FUNCTION_ARG. */
3198 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3199 tree type, int named)
3201 struct mips_arg_info info;
3203 /* We will be called with a mode of VOIDmode after the last argument
3204 has been seen. Whatever we return will be passed to the call
3205 insn. If we need a mips16 fp_code, return a REG with the code
3206 stored as the mode. */
3207 if (mode == VOIDmode)
3209 if (TARGET_MIPS16 && cum->fp_code != 0)
3210 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3216 mips_arg_info (cum, mode, type, named, &info);
3218 /* Return straight away if the whole argument is passed on the stack. */
3219 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3223 && TREE_CODE (type) == RECORD_TYPE
3225 && TYPE_SIZE_UNIT (type)
3226 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3229 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3230 structure contains a double in its entirety, then that 64 bit
3231 chunk is passed in a floating point register. */
3234 /* First check to see if there is any such field. */
3235 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3236 if (TREE_CODE (field) == FIELD_DECL
3237 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3238 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3239 && host_integerp (bit_position (field), 0)
3240 && int_bit_position (field) % BITS_PER_WORD == 0)
3245 /* Now handle the special case by returning a PARALLEL
3246 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3247 chunks are passed in registers. */
3249 HOST_WIDE_INT bitpos;
3252 /* assign_parms checks the mode of ENTRY_PARM, so we must
3253 use the actual mode here. */
3254 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3257 field = TYPE_FIELDS (type);
3258 for (i = 0; i < info.reg_words; i++)
3262 for (; field; field = TREE_CHAIN (field))
3263 if (TREE_CODE (field) == FIELD_DECL
3264 && int_bit_position (field) >= bitpos)
3268 && int_bit_position (field) == bitpos
3269 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3270 && !TARGET_SOFT_FLOAT
3271 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3272 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3274 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3277 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3278 GEN_INT (bitpos / BITS_PER_UNIT));
3280 bitpos += BITS_PER_WORD;
3286 /* Handle the n32/n64 conventions for passing complex floating-point
3287 arguments in FPR pairs. The real part goes in the lower register
3288 and the imaginary part goes in the upper register. */
3291 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
3294 enum machine_mode inner;
3297 inner = GET_MODE_INNER (mode);
3298 reg = FP_ARG_FIRST + info.reg_offset;
3299 real = gen_rtx_EXPR_LIST (VOIDmode,
3300 gen_rtx_REG (inner, reg),
3302 imag = gen_rtx_EXPR_LIST (VOIDmode,
3303 gen_rtx_REG (inner, reg + info.reg_words / 2),
3304 GEN_INT (GET_MODE_SIZE (inner)));
3305 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
3309 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3310 else if (info.reg_offset == 1)
3311 /* This code handles the special o32 case in which the second word
3312 of the argument structure is passed in floating-point registers. */
3313 return gen_rtx_REG (mode, FP_ARG_FIRST + FP_INC);
3315 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3319 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3322 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3323 enum machine_mode mode, tree type, int named)
3325 struct mips_arg_info info;
3327 mips_arg_info (cum, mode, type, named, &info);
3328 return info.stack_words > 0 ? info.reg_words : 0;
3332 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
3333 PARM_BOUNDARY bits of alignment, but will be given anything up
3334 to STACK_BOUNDARY bits if the type requires it. */
3337 function_arg_boundary (enum machine_mode mode, tree type)
3339 unsigned int alignment;
3341 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
3342 if (alignment < PARM_BOUNDARY)
3343 alignment = PARM_BOUNDARY;
3344 if (alignment > STACK_BOUNDARY)
3345 alignment = STACK_BOUNDARY;
3349 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3350 upward rather than downward. In other words, return true if the
3351 first byte of the stack slot has useful data, false if the last
3355 mips_pad_arg_upward (enum machine_mode mode, tree type)
3357 /* On little-endian targets, the first byte of every stack argument
3358 is passed in the first byte of the stack slot. */
3359 if (!BYTES_BIG_ENDIAN)
3362 /* Otherwise, integral types are padded downward: the last byte of a
3363 stack argument is passed in the last byte of the stack slot. */
3365 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3366 : GET_MODE_CLASS (mode) == MODE_INT)
3369 /* Big-endian o64 pads floating-point arguments downward. */
3370 if (mips_abi == ABI_O64)
3371 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3374 /* Other types are padded upward for o32, o64, n32 and n64. */
3375 if (mips_abi != ABI_EABI)
3378 /* Arguments smaller than a stack slot are padded downward. */
3379 if (mode != BLKmode)
3380 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3382 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3386 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3387 if the least significant byte of the register has useful data. Return
3388 the opposite if the most significant byte does. */
3391 mips_pad_reg_upward (enum machine_mode mode, tree type)
3393 /* No shifting is required for floating-point arguments. */
3394 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3395 return !BYTES_BIG_ENDIAN;
3397 /* Otherwise, apply the same padding to register arguments as we do
3398 to stack arguments. */
3399 return mips_pad_arg_upward (mode, type);
3403 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3404 tree type, int *pretend_size, int no_rtl)
3406 CUMULATIVE_ARGS local_cum;
3407 int gp_saved, fp_saved;
3409 /* The caller has advanced CUM up to, but not beyond, the last named
3410 argument. Advance a local copy of CUM past the last "real" named
3411 argument, to find out how many registers are left over. */
3414 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3416 /* Found out how many registers we need to save. */
3417 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3418 fp_saved = (EABI_FLOAT_VARARGS_P
3419 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3428 ptr = virtual_incoming_args_rtx;
3433 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3437 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3440 mem = gen_rtx_MEM (BLKmode, ptr);
3441 set_mem_alias_set (mem, get_varargs_alias_set ());
3443 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3448 /* We can't use move_block_from_reg, because it will use
3450 enum machine_mode mode;
3453 /* Set OFF to the offset from virtual_incoming_args_rtx of
3454 the first float register. The FP save area lies below
3455 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3456 off = -gp_saved * UNITS_PER_WORD;
3457 off &= ~(UNITS_PER_FPVALUE - 1);
3458 off -= fp_saved * UNITS_PER_FPREG;
3460 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3462 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3466 ptr = plus_constant (virtual_incoming_args_rtx, off);
3467 mem = gen_rtx_MEM (mode, ptr);
3468 set_mem_alias_set (mem, get_varargs_alias_set ());
3469 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3470 off += UNITS_PER_HWFPVALUE;
3476 /* No need for pretend arguments: the register parameter area was
3477 allocated by the caller. */
3481 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3484 /* Create the va_list data type.
3485 We keep 3 pointers, and two offsets.
3486 Two pointers are to the overflow area, which starts at the CFA.
3487 One of these is constant, for addressing into the GPR save area below it.
3488 The other is advanced up the stack through the overflow region.
3489 The third pointer is to the GPR save area. Since the FPR save area
3490 is just below it, we can address FPR slots off this pointer.
3491 We also keep two one-byte offsets, which are to be subtracted from the
3492 constant pointers to yield addresses in the GPR and FPR save areas.
3493 These are downcounted as float or non-float arguments are used,
3494 and when they get to zero, the argument must be obtained from the
3496 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3497 pointer is enough. It's started at the GPR save area, and is
3499 Note that the GPR save area is not constant size, due to optimization
3500 in the prologue. Hence, we can't use a design with two pointers
3501 and two offsets, although we could have designed this with two pointers
3502 and three offsets. */
3505 mips_build_builtin_va_list (void)
3507 if (EABI_FLOAT_VARARGS_P)
3509 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3512 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3514 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3516 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3518 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3520 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3521 unsigned_char_type_node);
3522 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3523 unsigned_char_type_node);
3524 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3525 warn on every user file. */
3526 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
3527 array = build_array_type (unsigned_char_type_node,
3528 build_index_type (index));
3529 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3531 DECL_FIELD_CONTEXT (f_ovfl) = record;
3532 DECL_FIELD_CONTEXT (f_gtop) = record;
3533 DECL_FIELD_CONTEXT (f_ftop) = record;
3534 DECL_FIELD_CONTEXT (f_goff) = record;
3535 DECL_FIELD_CONTEXT (f_foff) = record;
3536 DECL_FIELD_CONTEXT (f_res) = record;
3538 TYPE_FIELDS (record) = f_ovfl;
3539 TREE_CHAIN (f_ovfl) = f_gtop;
3540 TREE_CHAIN (f_gtop) = f_ftop;
3541 TREE_CHAIN (f_ftop) = f_goff;
3542 TREE_CHAIN (f_goff) = f_foff;
3543 TREE_CHAIN (f_foff) = f_res;
3545 layout_type (record);
3548 else if (TARGET_IRIX && TARGET_IRIX6)
3549 /* On IRIX 6, this type is 'char *'. */
3550 return build_pointer_type (char_type_node);
3552 /* Otherwise, we use 'void *'. */
3553 return ptr_type_node;
3556 /* Implement va_start. */
3559 mips_va_start (tree valist, rtx nextarg)
3561 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
3563 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
3564 since the stack is aligned for a pair of argument-passing slots,
3565 and the beginning of a variable argument list may be an odd slot,
3566 we have to decrease its alignment. */
3567 if (cfun && cfun->emit->regno_pointer_align)
3568 while (((current_function_pretend_args_size * BITS_PER_UNIT)
3569 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
3570 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
3572 if (mips_abi == ABI_EABI)
3574 int gpr_save_area_size;
3577 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
3579 if (EABI_FLOAT_VARARGS_P)
3581 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3582 tree ovfl, gtop, ftop, goff, foff;
3585 int fpr_save_area_size;
3587 f_ovfl = TYPE_FIELDS (va_list_type_node);
3588 f_gtop = TREE_CHAIN (f_ovfl);
3589 f_ftop = TREE_CHAIN (f_gtop);
3590 f_goff = TREE_CHAIN (f_ftop);
3591 f_foff = TREE_CHAIN (f_goff);
3593 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3595 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3597 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3599 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3601 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3604 /* Emit code to initialize OVFL, which points to the next varargs
3605 stack argument. CUM->STACK_WORDS gives the number of stack
3606 words used by named arguments. */
3607 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
3608 if (cum->stack_words > 0)
3609 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
3610 build_int_cst (NULL_TREE,
3611 cum->stack_words * UNITS_PER_WORD));
3612 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
3613 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3615 /* Emit code to initialize GTOP, the top of the GPR save area. */
3616 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
3617 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
3618 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3620 /* Emit code to initialize FTOP, the top of the FPR save area.
3621 This address is gpr_save_area_bytes below GTOP, rounded
3622 down to the next fp-aligned boundary. */
3623 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
3624 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
3625 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
3627 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
3628 build_int_cst (NULL_TREE, -fpr_offset));
3629 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
3630 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3632 /* Emit code to initialize GOFF, the offset from GTOP of the
3633 next GPR argument. */
3634 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
3635 build_int_cst (NULL_TREE, gpr_save_area_size));
3636 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3638 /* Likewise emit code to initialize FOFF, the offset from FTOP
3639 of the next FPR argument. */
3641 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
3642 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
3643 build_int_cst (NULL_TREE, fpr_save_area_size));
3644 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3648 /* Everything is in the GPR save area, or in the overflow
3649 area which is contiguous with it. */
3650 nextarg = plus_constant (nextarg, -gpr_save_area_size);
3651 std_expand_builtin_va_start (valist, nextarg);
3655 std_expand_builtin_va_start (valist, nextarg);
3658 /* Implement va_arg. */
3661 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
3663 HOST_WIDE_INT size, rsize;
3667 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
3670 type = build_pointer_type (type);
3672 size = int_size_in_bytes (type);
3673 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
3675 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
3676 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
3679 /* Not a simple merged stack. */
3681 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3682 tree ovfl, top, off, align;
3683 HOST_WIDE_INT osize;
3686 f_ovfl = TYPE_FIELDS (va_list_type_node);
3687 f_gtop = TREE_CHAIN (f_ovfl);
3688 f_ftop = TREE_CHAIN (f_gtop);
3689 f_goff = TREE_CHAIN (f_ftop);
3690 f_foff = TREE_CHAIN (f_goff);
3692 /* We maintain separate pointers and offsets for floating-point
3693 and integer arguments, but we need similar code in both cases.
3696 TOP be the top of the register save area;
3697 OFF be the offset from TOP of the next register;
3698 ADDR_RTX be the address of the argument;
3699 RSIZE be the number of bytes used to store the argument
3700 when it's in the register save area;
3701 OSIZE be the number of bytes used to store it when it's
3702 in the stack overflow area; and
3703 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
3705 The code we want is:
3707 1: off &= -rsize; // round down
3710 4: addr_rtx = top - off;
3715 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
3716 10: addr_rtx = ovfl + PADDING;
3720 [1] and [9] can sometimes be optimized away. */
3722 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3725 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
3726 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
3728 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3730 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3733 /* When floating-point registers are saved to the stack,
3734 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
3735 of the float's precision. */
3736 rsize = UNITS_PER_HWFPVALUE;
3738 /* Overflow arguments are padded to UNITS_PER_WORD bytes
3739 (= PARM_BOUNDARY bits). This can be different from RSIZE
3742 (1) On 32-bit targets when TYPE is a structure such as:
3744 struct s { float f; };
3746 Such structures are passed in paired FPRs, so RSIZE
3747 will be 8 bytes. However, the structure only takes
3748 up 4 bytes of memory, so OSIZE will only be 4.
3750 (2) In combinations such as -mgp64 -msingle-float
3751 -fshort-double. Doubles passed in registers
3752 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
3753 but those passed on the stack take up
3754 UNITS_PER_WORD bytes. */
3755 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
3759 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3761 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3763 if (rsize > UNITS_PER_WORD)
3765 /* [1] Emit code for: off &= -rsize. */
3766 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
3767 build_int_cst (NULL_TREE, -rsize));
3768 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
3769 gimplify_and_add (t, pre_p);
3774 /* [2] Emit code to branch if off == 0. */
3775 t = lang_hooks.truthvalue_conversion (off);
3776 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
3778 /* [5] Emit code for: off -= rsize. We do this as a form of
3779 post-increment not available to C. Also widen for the
3780 coming pointer arithmetic. */
3781 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
3782 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
3783 t = fold_convert (sizetype, t);
3784 t = fold_convert (TREE_TYPE (top), t);
3786 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
3787 the argument has RSIZE - SIZE bytes of leading padding. */
3788 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
3789 if (BYTES_BIG_ENDIAN && rsize > size)
3791 u = fold_convert (TREE_TYPE (t), build_int_cst (NULL_TREE,
3793 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
3795 COND_EXPR_THEN (addr) = t;
3797 if (osize > UNITS_PER_WORD)
3799 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
3800 u = fold_convert (TREE_TYPE (ovfl),
3801 build_int_cst (NULL_TREE, osize - 1));
3802 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
3803 u = fold_convert (TREE_TYPE (ovfl),
3804 build_int_cst (NULL_TREE, -osize));
3805 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
3806 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
3811 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
3812 post-increment ovfl by osize. On big-endian machines,
3813 the argument has OSIZE - SIZE bytes of leading padding. */
3814 u = fold_convert (TREE_TYPE (ovfl),
3815 build_int_cst (NULL_TREE, osize));
3816 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
3817 if (BYTES_BIG_ENDIAN && osize > size)
3819 u = fold_convert (TREE_TYPE (t),
3820 build_int_cst (NULL_TREE, osize - size));
3821 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
3824 /* String [9] and [10,11] together. */
3826 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
3827 COND_EXPR_ELSE (addr) = t;
3829 addr = fold_convert (build_pointer_type (type), addr);
3830 addr = build_fold_indirect_ref (addr);
3834 addr = build_fold_indirect_ref (addr);
3839 /* Return true if it is possible to use left/right accesses for a
3840 bitfield of WIDTH bits starting BITPOS bits into *OP. When
3841 returning true, update *OP, *LEFT and *RIGHT as follows:
3843 *OP is a BLKmode reference to the whole field.
3845 *LEFT is a QImode reference to the first byte if big endian or
3846 the last byte if little endian. This address can be used in the
3847 left-side instructions (lwl, swl, ldl, sdl).
3849 *RIGHT is a QImode reference to the opposite end of the field and
3850 can be used in the parterning right-side instruction. */
3853 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
3854 rtx *left, rtx *right)
3858 /* Check that the operand really is a MEM. Not all the extv and
3859 extzv predicates are checked. */
3863 /* Check that the size is valid. */
3864 if (width != 32 && (!TARGET_64BIT || width != 64))
3867 /* We can only access byte-aligned values. Since we are always passed
3868 a reference to the first byte of the field, it is not necessary to
3869 do anything with BITPOS after this check. */
3870 if (bitpos % BITS_PER_UNIT != 0)
3873 /* Reject aligned bitfields: we want to use a normal load or store
3874 instead of a left/right pair. */
3875 if (MEM_ALIGN (*op) >= width)
3878 /* Adjust *OP to refer to the whole field. This also has the effect
3879 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
3880 *op = adjust_address (*op, BLKmode, 0);
3881 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
3883 /* Get references to both ends of the field. We deliberately don't
3884 use the original QImode *OP for FIRST since the new BLKmode one
3885 might have a simpler address. */
3886 first = adjust_address (*op, QImode, 0);
3887 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
3889 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
3890 be the upper word and RIGHT the lower word. */
3891 if (TARGET_BIG_ENDIAN)
3892 *left = first, *right = last;
3894 *left = last, *right = first;
3900 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
3901 Return true on success. We only handle cases where zero_extract is
3902 equivalent to sign_extract. */
3905 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
3907 rtx left, right, temp;
3909 /* If TARGET_64BIT, the destination of a 32-bit load will be a
3910 paradoxical word_mode subreg. This is the only case in which
3911 we allow the destination to be larger than the source. */
3912 if (GET_CODE (dest) == SUBREG
3913 && GET_MODE (dest) == DImode
3914 && SUBREG_BYTE (dest) == 0
3915 && GET_MODE (SUBREG_REG (dest)) == SImode)
3916 dest = SUBREG_REG (dest);
3918 /* After the above adjustment, the destination must be the same
3919 width as the source. */
3920 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
3923 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
3926 temp = gen_reg_rtx (GET_MODE (dest));
3927 if (GET_MODE (dest) == DImode)
3929 emit_insn (gen_mov_ldl (temp, src, left));
3930 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
3934 emit_insn (gen_mov_lwl (temp, src, left));
3935 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
3941 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
3945 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
3949 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
3952 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
3954 if (GET_MODE (src) == DImode)
3956 emit_insn (gen_mov_sdl (dest, src, left));
3957 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
3961 emit_insn (gen_mov_swl (dest, src, left));
3962 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
3967 /* Set up globals to generate code for the ISA or processor
3968 described by INFO. */
3971 mips_set_architecture (const struct mips_cpu_info *info)
3975 mips_arch_info = info;
3976 mips_arch = info->cpu;
3977 mips_isa = info->isa;
3982 /* Likewise for tuning. */
3985 mips_set_tune (const struct mips_cpu_info *info)
3989 mips_tune_info = info;
3990 mips_tune = info->cpu;
3995 /* Set up the threshold for data to go into the small data area, instead
3996 of the normal data area, and detect any conflicts in the switches. */
3999 override_options (void)
4001 int i, start, regno;
4002 enum machine_mode mode;
4004 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4006 /* Interpret -mabi. */
4007 mips_abi = MIPS_ABI_DEFAULT;
4008 if (mips_abi_string != 0)
4010 if (strcmp (mips_abi_string, "32") == 0)
4012 else if (strcmp (mips_abi_string, "o64") == 0)
4014 else if (strcmp (mips_abi_string, "n32") == 0)
4016 else if (strcmp (mips_abi_string, "64") == 0)
4018 else if (strcmp (mips_abi_string, "eabi") == 0)
4019 mips_abi = ABI_EABI;
4021 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4024 /* The following code determines the architecture and register size.
4025 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4026 The GAS and GCC code should be kept in sync as much as possible. */
4028 if (mips_arch_string != 0)
4029 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4031 if (mips_isa_string != 0)
4033 /* Handle -mipsN. */
4034 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4035 const struct mips_cpu_info *isa_info;
4037 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4038 free (whole_isa_str);
4040 /* -march takes precedence over -mipsN, since it is more descriptive.
4041 There's no harm in specifying both as long as the ISA levels
4043 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4044 error ("-mips%s conflicts with the other architecture options, "
4045 "which specify a MIPS%d processor",
4046 mips_isa_string, mips_isa);
4048 /* Set architecture based on the given option. */
4049 mips_set_architecture (isa_info);
4052 if (mips_arch_info == 0)
4054 #ifdef MIPS_CPU_STRING_DEFAULT
4055 mips_set_architecture (mips_parse_cpu ("default CPU",
4056 MIPS_CPU_STRING_DEFAULT));
4058 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4062 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4063 error ("-march=%s is not compatible with the selected ABI",
4064 mips_arch_info->name);
4066 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4067 if (mips_tune_string != 0)
4068 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4070 if (mips_tune_info == 0)
4071 mips_set_tune (mips_arch_info);
4073 if ((target_flags_explicit & MASK_64BIT) != 0)
4075 /* The user specified the size of the integer registers. Make sure
4076 it agrees with the ABI and ISA. */
4077 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4078 error ("-mgp64 used with a 32-bit processor");
4079 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4080 error ("-mgp32 used with a 64-bit ABI");
4081 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4082 error ("-mgp64 used with a 32-bit ABI");
4086 /* Infer the integer register size from the ABI and processor.
4087 Restrict ourselves to 32-bit registers if that's all the
4088 processor has, or if the ABI cannot handle 64-bit registers. */
4089 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4090 target_flags &= ~MASK_64BIT;
4092 target_flags |= MASK_64BIT;
4095 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4097 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4098 only one right answer here. */
4099 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4100 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4101 else if (!TARGET_64BIT && TARGET_FLOAT64)
4102 error ("unsupported combination: %s", "-mgp32 -mfp64");
4103 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4104 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4108 /* -msingle-float selects 32-bit float registers. Otherwise the
4109 float registers should be the same size as the integer ones. */
4110 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4111 target_flags |= MASK_FLOAT64;
4113 target_flags &= ~MASK_FLOAT64;
4116 /* End of code shared with GAS. */
4118 if ((target_flags_explicit & MASK_LONG64) == 0)
4120 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4121 were used, then set the type sizes. In the EABI in 64 bit mode,
4122 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4124 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4125 target_flags |= MASK_LONG64;
4127 target_flags &= ~MASK_LONG64;
4130 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4131 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4133 /* For some configurations, it is useful to have -march control
4134 the default setting of MASK_SOFT_FLOAT. */
4135 switch ((int) mips_arch)
4137 case PROCESSOR_R4100:
4138 case PROCESSOR_R4111:
4139 case PROCESSOR_R4120:
4140 case PROCESSOR_R4130:
4141 target_flags |= MASK_SOFT_FLOAT;
4145 target_flags &= ~MASK_SOFT_FLOAT;
4151 flag_pcc_struct_return = 0;
4153 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4155 /* If neither -mbranch-likely nor -mno-branch-likely was given
4156 on the command line, set MASK_BRANCHLIKELY based on the target
4159 By default, we enable use of Branch Likely instructions on
4160 all architectures which support them with the following
4161 exceptions: when creating MIPS32 or MIPS64 code, and when
4162 tuning for architectures where their use tends to hurt
4165 The MIPS32 and MIPS64 architecture specifications say "Software
4166 is strongly encouraged to avoid use of Branch Likely
4167 instructions, as they will be removed from a future revision
4168 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4169 issue those instructions unless instructed to do so by
4171 if (ISA_HAS_BRANCHLIKELY
4172 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4173 && !(TUNE_MIPS5500 || TUNE_SB1))
4174 target_flags |= MASK_BRANCHLIKELY;
4176 target_flags &= ~MASK_BRANCHLIKELY;
4178 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4179 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4181 /* The effect of -mabicalls isn't defined for the EABI. */
4182 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4184 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4185 target_flags &= ~MASK_ABICALLS;
4188 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4189 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4190 /* ??? -non_shared turns off pic code generation, but this is not
4192 if (TARGET_ABICALLS)
4195 if (mips_section_threshold > 0)
4196 warning ("-G is incompatible with PIC code which is the default");
4199 /* mips_split_addresses is a half-way house between explicit
4200 relocations and the traditional assembler macros. It can
4201 split absolute 32-bit symbolic constants into a high/lo_sum
4202 pair but uses macros for other sorts of access.
4204 Like explicit relocation support for REL targets, it relies
4205 on GNU extensions in the assembler and the linker.
4207 Although this code should work for -O0, it has traditionally
4208 been treated as an optimization. */
4209 if (!TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4210 && optimize && !flag_pic
4211 && !ABI_HAS_64BIT_SYMBOLS)
4212 mips_split_addresses = 1;
4214 mips_split_addresses = 0;
4216 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4217 faster code, but at the expense of more nops. Enable it at -O3 and
4219 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4220 target_flags |= MASK_VR4130_ALIGN;
4222 /* When compiling for the mips16, we cannot use floating point. We
4223 record the original hard float value in mips16_hard_float. */
4226 if (TARGET_SOFT_FLOAT)
4227 mips16_hard_float = 0;
4229 mips16_hard_float = 1;
4230 target_flags |= MASK_SOFT_FLOAT;
4232 /* Don't run the scheduler before reload, since it tends to
4233 increase register pressure. */
4234 flag_schedule_insns = 0;
4236 /* Don't do hot/cold partitioning. The constant layout code expects
4237 the whole function to be in a single section. */
4238 flag_reorder_blocks_and_partition = 0;
4240 /* Silently disable -mexplicit-relocs since it doesn't apply
4241 to mips16 code. Even so, it would overly pedantic to warn
4242 about "-mips16 -mexplicit-relocs", especially given that
4243 we use a %gprel() operator. */
4244 target_flags &= ~MASK_EXPLICIT_RELOCS;
4247 /* When using explicit relocs, we call dbr_schedule from within
4249 if (TARGET_EXPLICIT_RELOCS)
4251 mips_flag_delayed_branch = flag_delayed_branch;
4252 flag_delayed_branch = 0;
4255 #ifdef MIPS_TFMODE_FORMAT
4256 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4259 /* Make sure that the user didn't turn off paired single support when
4260 MIPS-3D support is requested. */
4261 if (TARGET_MIPS3D && (target_flags_explicit & MASK_PAIRED_SINGLE)
4262 && !TARGET_PAIRED_SINGLE_FLOAT)
4263 error ("-mips3d requires -mpaired-single");
4265 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE. */
4267 target_flags |= MASK_PAIRED_SINGLE;
4269 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
4270 and TARGET_HARD_FLOAT are both true. */
4271 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT))
4272 error ("-mips3d/-mpaired-single must be used with -mfp64 -mhard-float");
4274 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
4276 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_MIPS64)
4277 error ("-mips3d/-mpaired-single must be used with -mips64");
4279 mips_print_operand_punct['?'] = 1;
4280 mips_print_operand_punct['#'] = 1;
4281 mips_print_operand_punct['/'] = 1;
4282 mips_print_operand_punct['&'] = 1;
4283 mips_print_operand_punct['!'] = 1;
4284 mips_print_operand_punct['*'] = 1;
4285 mips_print_operand_punct['@'] = 1;
4286 mips_print_operand_punct['.'] = 1;
4287 mips_print_operand_punct['('] = 1;
4288 mips_print_operand_punct[')'] = 1;
4289 mips_print_operand_punct['['] = 1;
4290 mips_print_operand_punct[']'] = 1;
4291 mips_print_operand_punct['<'] = 1;
4292 mips_print_operand_punct['>'] = 1;
4293 mips_print_operand_punct['{'] = 1;
4294 mips_print_operand_punct['}'] = 1;
4295 mips_print_operand_punct['^'] = 1;
4296 mips_print_operand_punct['$'] = 1;
4297 mips_print_operand_punct['+'] = 1;
4298 mips_print_operand_punct['~'] = 1;
4300 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4301 mips_char_to_class['t'] = T_REG;
4302 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4303 mips_char_to_class['h'] = HI_REG;
4304 mips_char_to_class['l'] = LO_REG;
4305 mips_char_to_class['x'] = MD_REGS;
4306 mips_char_to_class['b'] = ALL_REGS;
4307 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4308 TARGET_MIPS16 ? M16_NA_REGS :
4310 mips_char_to_class['e'] = LEA_REGS;
4311 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4312 mips_char_to_class['y'] = GR_REGS;
4313 mips_char_to_class['z'] = ST_REGS;
4314 mips_char_to_class['B'] = COP0_REGS;
4315 mips_char_to_class['C'] = COP2_REGS;
4316 mips_char_to_class['D'] = COP3_REGS;
4318 /* Set up array to map GCC register number to debug register number.
4319 Ignore the special purpose register numbers. */
4321 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4322 mips_dbx_regno[i] = -1;
4324 start = GP_DBX_FIRST - GP_REG_FIRST;
4325 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4326 mips_dbx_regno[i] = i + start;
4328 start = FP_DBX_FIRST - FP_REG_FIRST;
4329 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4330 mips_dbx_regno[i] = i + start;
4332 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4333 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4335 /* Set up array giving whether a given register can hold a given mode. */
4337 for (mode = VOIDmode;
4338 mode != MAX_MACHINE_MODE;
4339 mode = (enum machine_mode) ((int)mode + 1))
4341 register int size = GET_MODE_SIZE (mode);
4342 register enum mode_class class = GET_MODE_CLASS (mode);
4344 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4348 if (mode == CCV2mode)
4351 && (regno - ST_REG_FIRST) % 2 == 0);
4353 else if (mode == CCV4mode)
4356 && (regno - ST_REG_FIRST) % 4 == 0);
4358 else if (mode == CCmode)
4361 temp = (regno == FPSW_REGNUM);
4363 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4364 || FP_REG_P (regno));
4367 else if (GP_REG_P (regno))
4368 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4370 else if (FP_REG_P (regno))
4371 temp = ((regno % FP_INC) == 0)
4372 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT
4373 || class == MODE_VECTOR_FLOAT)
4374 && size <= UNITS_PER_FPVALUE)
4375 /* Allow integer modes that fit into a single
4376 register. We need to put integers into FPRs
4377 when using instructions like cvt and trunc. */
4378 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4379 /* Allow TFmode for CCmode reloads. */
4380 || (ISA_HAS_8CC && mode == TFmode));
4382 else if (MD_REG_P (regno))
4383 temp = (INTEGRAL_MODE_P (mode)
4384 && (size <= UNITS_PER_WORD
4385 || (regno == MD_REG_FIRST
4386 && size == 2 * UNITS_PER_WORD)));
4388 else if (ALL_COP_REG_P (regno))
4389 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4393 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4397 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4398 initialized yet, so we can't use that here. */
4399 gpr_mode = TARGET_64BIT ? DImode : SImode;
4401 /* Provide default values for align_* for 64-bit targets. */
4402 if (TARGET_64BIT && !TARGET_MIPS16)
4404 if (align_loops == 0)
4406 if (align_jumps == 0)
4408 if (align_functions == 0)
4409 align_functions = 8;
4412 /* Function to allocate machine-dependent function status. */
4413 init_machine_status = &mips_init_machine_status;
4415 if (ABI_HAS_64BIT_SYMBOLS)
4417 if (TARGET_EXPLICIT_RELOCS)
4419 mips_split_p[SYMBOL_64_HIGH] = true;
4420 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4421 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4423 mips_split_p[SYMBOL_64_MID] = true;
4424 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4425 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4427 mips_split_p[SYMBOL_64_LOW] = true;
4428 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4429 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4431 mips_split_p[SYMBOL_GENERAL] = true;
4432 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4437 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4439 mips_split_p[SYMBOL_GENERAL] = true;
4440 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4441 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4447 /* The high part is provided by a pseudo copy of $gp. */
4448 mips_split_p[SYMBOL_SMALL_DATA] = true;
4449 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4452 if (TARGET_EXPLICIT_RELOCS)
4454 /* Small data constants are kept whole until after reload,
4455 then lowered by mips_rewrite_small_data. */
4456 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
4458 mips_split_p[SYMBOL_GOT_LOCAL] = true;
4461 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
4462 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
4466 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
4467 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
4472 /* The HIGH and LO_SUM are matched by special .md patterns. */
4473 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
4475 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
4476 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
4477 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
4479 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
4480 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
4481 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
4486 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
4488 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
4489 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
4495 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
4496 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
4497 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
4500 /* Default to working around R4000 errata only if the processor
4501 was selected explicitly. */
4502 if ((target_flags_explicit & MASK_FIX_R4000) == 0
4503 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
4504 target_flags |= MASK_FIX_R4000;
4506 /* Default to working around R4400 errata only if the processor
4507 was selected explicitly. */
4508 if ((target_flags_explicit & MASK_FIX_R4400) == 0
4509 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
4510 target_flags |= MASK_FIX_R4400;
4513 /* Implement CONDITIONAL_REGISTER_USAGE. */
4516 mips_conditional_register_usage (void)
4518 if (!TARGET_HARD_FLOAT)
4522 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4523 fixed_regs[regno] = call_used_regs[regno] = 1;
4524 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4525 fixed_regs[regno] = call_used_regs[regno] = 1;
4527 else if (! ISA_HAS_8CC)
4531 /* We only have a single condition code register. We
4532 implement this by hiding all the condition code registers,
4533 and generating RTL that refers directly to ST_REG_FIRST. */
4534 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4535 fixed_regs[regno] = call_used_regs[regno] = 1;
4537 /* In mips16 mode, we permit the $t temporary registers to be used
4538 for reload. We prohibit the unused $s registers, since they
4539 are caller saved, and saving them via a mips16 register would
4540 probably waste more time than just reloading the value. */
4543 fixed_regs[18] = call_used_regs[18] = 1;
4544 fixed_regs[19] = call_used_regs[19] = 1;
4545 fixed_regs[20] = call_used_regs[20] = 1;
4546 fixed_regs[21] = call_used_regs[21] = 1;
4547 fixed_regs[22] = call_used_regs[22] = 1;
4548 fixed_regs[23] = call_used_regs[23] = 1;
4549 fixed_regs[26] = call_used_regs[26] = 1;
4550 fixed_regs[27] = call_used_regs[27] = 1;
4551 fixed_regs[30] = call_used_regs[30] = 1;
4553 /* fp20-23 are now caller saved. */
4554 if (mips_abi == ABI_64)
4557 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
4558 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4560 /* Odd registers from fp21 to fp31 are now caller saved. */
4561 if (mips_abi == ABI_N32)
4564 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
4565 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4569 /* Allocate a chunk of memory for per-function machine-dependent data. */
4570 static struct machine_function *
4571 mips_init_machine_status (void)
4573 return ((struct machine_function *)
4574 ggc_alloc_cleared (sizeof (struct machine_function)));
4577 /* On the mips16, we want to allocate $24 (T_REG) before other
4578 registers for instructions for which it is possible. This helps
4579 avoid shuffling registers around in order to set up for an xor,
4580 encouraging the compiler to use a cmp instead. */
4583 mips_order_regs_for_local_alloc (void)
4587 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4588 reg_alloc_order[i] = i;
4592 /* It really doesn't matter where we put register 0, since it is
4593 a fixed register anyhow. */
4594 reg_alloc_order[0] = 24;
4595 reg_alloc_order[24] = 0;
4600 /* The MIPS debug format wants all automatic variables and arguments
4601 to be in terms of the virtual frame pointer (stack pointer before
4602 any adjustment in the function), while the MIPS 3.0 linker wants
4603 the frame pointer to be the stack pointer after the initial
4604 adjustment. So, we do the adjustment here. The arg pointer (which
4605 is eliminated) points to the virtual frame pointer, while the frame
4606 pointer (which may be eliminated) points to the stack pointer after
4607 the initial adjustments. */
4610 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
4612 rtx offset2 = const0_rtx;
4613 rtx reg = eliminate_constant_term (addr, &offset2);
4616 offset = INTVAL (offset2);
4618 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4619 || reg == hard_frame_pointer_rtx)
4621 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
4622 ? compute_frame_size (get_frame_size ())
4623 : cfun->machine->frame.total_size;
4625 /* MIPS16 frame is smaller */
4626 if (frame_pointer_needed && TARGET_MIPS16)
4627 frame_size -= cfun->machine->frame.args_size;
4629 offset = offset - frame_size;
4632 /* sdbout_parms does not want this to crash for unrecognized cases. */
4634 else if (reg != arg_pointer_rtx)
4635 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
4642 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
4644 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4645 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4646 'h' OP is HIGH, prints %hi(X),
4647 'd' output integer constant in decimal,
4648 'z' if the operand is 0, use $0 instead of normal operand.
4649 'D' print second part of double-word register or memory operand.
4650 'L' print low-order register of double-word register operand.
4651 'M' print high-order register of double-word register operand.
4652 'C' print part of opcode for a branch condition.
4653 'F' print part of opcode for a floating-point branch condition.
4654 'N' print part of opcode for a branch condition, inverted.
4655 'W' print part of opcode for a floating-point branch condition, inverted.
4656 'T' print 'f' for (eq:CC ...), 't' for (ne:CC ...),
4657 'z' for (eq:?I ...), 'n' for (ne:?I ...).
4658 't' like 'T', but with the EQ/NE cases reversed
4659 'Y' for a CONST_INT X, print mips_fp_conditions[X]
4660 'Z' print the operand and a comma for ISA_HAS_8CC, otherwise print nothing
4661 'R' print the reloc associated with LO_SUM
4663 The punctuation characters are:
4665 '(' Turn on .set noreorder
4666 ')' Turn on .set reorder
4667 '[' Turn on .set noat
4669 '<' Turn on .set nomacro
4670 '>' Turn on .set macro
4671 '{' Turn on .set volatile (not GAS)
4672 '}' Turn on .set novolatile (not GAS)
4673 '&' Turn on .set noreorder if filling delay slots
4674 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4675 '!' Turn on .set nomacro if filling delay slots
4676 '#' Print nop if in a .set noreorder section.
4677 '/' Like '#', but does nothing within a delayed branch sequence
4678 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4679 '@' Print the name of the assembler temporary register (at or $1).
4680 '.' Print the name of the register with a hard-wired zero (zero or $0).
4681 '^' Print the name of the pic call-through register (t9 or $25).
4682 '$' Print the name of the stack pointer register (sp or $29).
4683 '+' Print the name of the gp register (usually gp or $28).
4684 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
4687 print_operand (FILE *file, rtx op, int letter)
4689 register enum rtx_code code;
4691 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4696 if (mips_branch_likely)
4701 fputs (reg_names [GP_REG_FIRST + 1], file);
4705 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4709 fputs (reg_names [GP_REG_FIRST + 0], file);
4713 fputs (reg_names[STACK_POINTER_REGNUM], file);
4717 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
4721 if (final_sequence != 0 && set_noreorder++ == 0)
4722 fputs (".set\tnoreorder\n\t", file);
4726 if (final_sequence != 0)
4728 if (set_noreorder++ == 0)
4729 fputs (".set\tnoreorder\n\t", file);
4731 if (set_nomacro++ == 0)
4732 fputs (".set\tnomacro\n\t", file);
4737 if (final_sequence != 0 && set_nomacro++ == 0)
4738 fputs ("\n\t.set\tnomacro", file);
4742 if (set_noreorder != 0)
4743 fputs ("\n\tnop", file);
4747 /* Print an extra newline so that the delayed insn is separated
4748 from the following ones. This looks neater and is consistent
4749 with non-nop delayed sequences. */
4750 if (set_noreorder != 0 && final_sequence == 0)
4751 fputs ("\n\tnop\n", file);
4755 if (set_noreorder++ == 0)
4756 fputs (".set\tnoreorder\n\t", file);
4760 if (set_noreorder == 0)
4761 error ("internal error: %%) found without a %%( in assembler pattern");
4763 else if (--set_noreorder == 0)
4764 fputs ("\n\t.set\treorder", file);
4769 if (set_noat++ == 0)
4770 fputs (".set\tnoat\n\t", file);
4775 error ("internal error: %%] found without a %%[ in assembler pattern");
4776 else if (--set_noat == 0)
4777 fputs ("\n\t.set\tat", file);
4782 if (set_nomacro++ == 0)
4783 fputs (".set\tnomacro\n\t", file);
4787 if (set_nomacro == 0)
4788 error ("internal error: %%> found without a %%< in assembler pattern");
4789 else if (--set_nomacro == 0)
4790 fputs ("\n\t.set\tmacro", file);
4795 if (set_volatile++ == 0)
4796 fputs ("#.set\tvolatile\n\t", file);
4800 if (set_volatile == 0)
4801 error ("internal error: %%} found without a %%{ in assembler pattern");
4802 else if (--set_volatile == 0)
4803 fputs ("\n\t#.set\tnovolatile", file);
4809 if (align_labels_log > 0)
4810 ASM_OUTPUT_ALIGN (file, align_labels_log);
4815 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
4824 error ("PRINT_OPERAND null pointer");
4828 code = GET_CODE (op);
4833 case EQ: fputs ("eq", file); break;
4834 case NE: fputs ("ne", file); break;
4835 case GT: fputs ("gt", file); break;
4836 case GE: fputs ("ge", file); break;
4837 case LT: fputs ("lt", file); break;
4838 case LE: fputs ("le", file); break;
4839 case GTU: fputs ("gtu", file); break;
4840 case GEU: fputs ("geu", file); break;
4841 case LTU: fputs ("ltu", file); break;
4842 case LEU: fputs ("leu", file); break;
4844 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
4847 else if (letter == 'N')
4850 case EQ: fputs ("ne", file); break;
4851 case NE: fputs ("eq", file); break;
4852 case GT: fputs ("le", file); break;
4853 case GE: fputs ("lt", file); break;
4854 case LT: fputs ("ge", file); break;
4855 case LE: fputs ("gt", file); break;
4856 case GTU: fputs ("leu", file); break;
4857 case GEU: fputs ("ltu", file); break;
4858 case LTU: fputs ("geu", file); break;
4859 case LEU: fputs ("gtu", file); break;
4861 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
4864 else if (letter == 'F')
4867 case EQ: fputs ("c1f", file); break;
4868 case NE: fputs ("c1t", file); break;
4870 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
4873 else if (letter == 'W')
4876 case EQ: fputs ("c1t", file); break;
4877 case NE: fputs ("c1f", file); break;
4879 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
4882 else if (letter == 'h')
4884 if (GET_CODE (op) == HIGH)
4887 print_operand_reloc (file, op, mips_hi_relocs);
4890 else if (letter == 'R')
4891 print_operand_reloc (file, op, mips_lo_relocs);
4893 else if (letter == 'Y')
4895 if (GET_CODE (op) == CONST_INT
4896 && ((unsigned HOST_WIDE_INT) INTVAL (op)
4897 < ARRAY_SIZE (mips_fp_conditions)))
4898 fputs (mips_fp_conditions[INTVAL (op)], file);
4900 output_operand_lossage ("invalid %%Y value");
4903 else if (letter == 'Z')
4907 print_operand (file, op, 0);
4912 else if (code == REG || code == SUBREG)
4914 register int regnum;
4917 regnum = REGNO (op);
4919 regnum = true_regnum (op);
4921 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
4922 || (letter == 'L' && WORDS_BIG_ENDIAN)
4926 fprintf (file, "%s", reg_names[regnum]);
4929 else if (code == MEM)
4932 output_address (plus_constant (XEXP (op, 0), 4));
4934 output_address (XEXP (op, 0));
4937 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
4938 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
4940 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
4941 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
4943 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
4944 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
4946 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
4947 fputs (reg_names[GP_REG_FIRST], file);
4949 else if (letter == 'd' || letter == 'x' || letter == 'X')
4950 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
4952 else if (letter == 'T' || letter == 't')
4954 int truth = (code == NE) == (letter == 'T');
4955 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
4958 else if (CONST_GP_P (op))
4959 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
4962 output_addr_const (file, op);
4966 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
4967 RELOCS is the array of relocations to use. */
4970 print_operand_reloc (FILE *file, rtx op, const char **relocs)
4972 enum mips_symbol_type symbol_type;
4975 HOST_WIDE_INT offset;
4977 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
4978 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
4980 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
4981 mips_split_const (op, &base, &offset);
4982 if (UNSPEC_ADDRESS_P (base))
4983 op = plus_constant (UNSPEC_ADDRESS (base), offset);
4985 fputs (relocs[symbol_type], file);
4986 output_addr_const (file, op);
4987 for (p = relocs[symbol_type]; *p != 0; p++)
4992 /* Output address operand X to FILE. */
4995 print_operand_address (FILE *file, rtx x)
4997 struct mips_address_info addr;
4999 if (mips_classify_address (&addr, x, word_mode, true))
5003 print_operand (file, addr.offset, 0);
5004 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5007 case ADDRESS_LO_SUM:
5008 print_operand (file, addr.offset, 'R');
5009 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5012 case ADDRESS_CONST_INT:
5013 output_addr_const (file, x);
5014 fprintf (file, "(%s)", reg_names[0]);
5017 case ADDRESS_SYMBOLIC:
5018 output_addr_const (file, x);
5024 /* When using assembler macros, keep track of all of small-data externs
5025 so that mips_file_end can emit the appropriate declarations for them.
5027 In most cases it would be safe (though pointless) to emit .externs
5028 for other symbols too. One exception is when an object is within
5029 the -G limit but declared by the user to be in a section other
5030 than .sbss or .sdata. */
5033 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5035 register struct extern_list *p;
5037 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5039 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5040 p->next = extern_head;
5042 p->size = int_size_in_bytes (TREE_TYPE (decl));
5046 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5048 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5049 p->next = extern_head;
5060 irix_output_external_libcall (rtx fun)
5062 register struct extern_list *p;
5064 if (mips_abi == ABI_32)
5066 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5067 p->next = extern_head;
5068 p->name = XSTR (fun, 0);
5075 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5076 put out a MIPS ECOFF file and a stab. */
5079 mips_output_filename (FILE *stream, const char *name)
5082 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5084 if (write_symbols == DWARF2_DEBUG)
5086 else if (mips_output_filename_first_time)
5088 mips_output_filename_first_time = 0;
5089 num_source_filenames += 1;
5090 current_function_file = name;
5091 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5092 output_quoted_string (stream, name);
5093 putc ('\n', stream);
5096 /* If we are emitting stabs, let dbxout.c handle this (except for
5097 the mips_output_filename_first_time case). */
5098 else if (write_symbols == DBX_DEBUG)
5101 else if (name != current_function_file
5102 && strcmp (name, current_function_file) != 0)
5104 num_source_filenames += 1;
5105 current_function_file = name;
5106 fprintf (stream, "\t.file\t%d ", num_source_filenames);
5107 output_quoted_string (stream, name);
5108 putc ('\n', stream);
5112 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5113 that should be written before the opening quote, such as "\t.ascii\t"
5114 for real string data or "\t# " for a comment. */
5117 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5122 register const unsigned char *string =
5123 (const unsigned char *)string_param;
5125 fprintf (stream, "%s\"", prefix);
5126 for (i = 0; i < len; i++)
5128 register int c = string[i];
5134 putc ('\\', stream);
5139 case TARGET_NEWLINE:
5140 fputs ("\\n", stream);
5142 && (((c = string[i+1]) >= '\040' && c <= '~')
5143 || c == TARGET_TAB))
5144 cur_pos = 32767; /* break right here */
5150 fputs ("\\t", stream);
5155 fputs ("\\f", stream);
5160 fputs ("\\b", stream);
5165 fputs ("\\r", stream);
5170 if (c >= ' ' && c < 0177)
5177 fprintf (stream, "\\%03o", c);
5182 if (cur_pos > 72 && i+1 < len)
5185 fprintf (stream, "\"\n%s\"", prefix);
5188 fprintf (stream, "\"\n");
5191 /* Implement TARGET_ASM_FILE_START. */
5194 mips_file_start (void)
5196 default_file_start ();
5200 /* Generate a special section to describe the ABI switches used to
5201 produce the resultant binary. This used to be done by the assembler
5202 setting bits in the ELF header's flags field, but we have run out of
5203 bits. GDB needs this information in order to be able to correctly
5204 debug these binaries. See the function mips_gdbarch_init() in
5205 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5206 causes unnecessary IRIX 6 ld warnings. */
5207 const char * abi_string = NULL;
5211 case ABI_32: abi_string = "abi32"; break;
5212 case ABI_N32: abi_string = "abiN32"; break;
5213 case ABI_64: abi_string = "abi64"; break;
5214 case ABI_O64: abi_string = "abiO64"; break;
5215 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5219 /* Note - we use fprintf directly rather than called named_section()
5220 because in this way we can avoid creating an allocated section. We
5221 do not want this section to take up any space in the running
5223 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5225 /* There is no ELF header flag to distinguish long32 forms of the
5226 EABI from long64 forms. Emit a special section to help tools
5228 if (mips_abi == ABI_EABI)
5229 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5230 TARGET_LONG64 ? 64 : 32);
5232 /* Restore the default section. */
5233 fprintf (asm_out_file, "\t.previous\n");
5236 /* Generate the pseudo ops that System V.4 wants. */
5237 if (TARGET_ABICALLS)
5238 /* ??? but do not want this (or want pic0) if -non-shared? */
5239 fprintf (asm_out_file, "\t.abicalls\n");
5242 fprintf (asm_out_file, "\t.set\tmips16\n");
5244 if (flag_verbose_asm)
5245 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5247 mips_section_threshold, mips_arch_info->name, mips_isa);
5250 #ifdef BSS_SECTION_ASM_OP
5251 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5252 in the use of sbss. */
5255 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5256 unsigned HOST_WIDE_INT size, int align)
5258 extern tree last_assemble_variable_decl;
5260 if (mips_in_small_data_p (decl))
5261 named_section (0, ".sbss", 0);
5264 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5265 last_assemble_variable_decl = decl;
5266 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5267 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5271 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5272 .externs for any small-data variables that turned out to be external. */
5275 mips_file_end (void)
5278 struct extern_list *p;
5282 fputs ("\n", asm_out_file);
5284 for (p = extern_head; p != 0; p = p->next)
5286 name_tree = get_identifier (p->name);
5288 /* Positively ensure only one .extern for any given symbol. */
5289 if (!TREE_ASM_WRITTEN (name_tree)
5290 && TREE_SYMBOL_REFERENCED (name_tree))
5292 TREE_ASM_WRITTEN (name_tree) = 1;
5293 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5294 `.global name .text' directive for every used but
5295 undefined function. If we don't, the linker may perform
5296 an optimization (skipping over the insns that set $gp)
5297 when it is unsafe. */
5298 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5300 fputs ("\t.globl ", asm_out_file);
5301 assemble_name (asm_out_file, p->name);
5302 fputs (" .text\n", asm_out_file);
5306 fputs ("\t.extern\t", asm_out_file);
5307 assemble_name (asm_out_file, p->name);
5308 fprintf (asm_out_file, ", %d\n", p->size);
5315 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
5316 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
5319 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5320 unsigned HOST_WIDE_INT size,
5323 /* If the target wants uninitialized const declarations in
5324 .rdata then don't put them in .comm. */
5325 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5326 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5327 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5329 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5330 targetm.asm_out.globalize_label (stream, name);
5332 readonly_data_section ();
5333 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5334 mips_declare_object (stream, name, "",
5335 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5339 mips_declare_common_object (stream, name, "\n\t.comm\t",
5343 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5344 NAME is the name of the object and ALIGN is the required alignment
5345 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5346 alignment argument. */
5349 mips_declare_common_object (FILE *stream, const char *name,
5350 const char *init_string,
5351 unsigned HOST_WIDE_INT size,
5352 unsigned int align, bool takes_alignment_p)
5354 if (!takes_alignment_p)
5356 size += (align / BITS_PER_UNIT) - 1;
5357 size -= size % (align / BITS_PER_UNIT);
5358 mips_declare_object (stream, name, init_string,
5359 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5362 mips_declare_object (stream, name, init_string,
5363 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5364 size, align / BITS_PER_UNIT);
5367 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5368 macros, mark the symbol as written so that mips_file_end won't emit an
5369 .extern for it. STREAM is the output file, NAME is the name of the
5370 symbol, INIT_STRING is the string that should be written before the
5371 symbol and FINAL_STRING is the string that should be written after it.
5372 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5375 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5376 const char *final_string, ...)
5380 fputs (init_string, stream);
5381 assemble_name (stream, name);
5382 va_start (ap, final_string);
5383 vfprintf (stream, final_string, ap);
5386 if (!TARGET_EXPLICIT_RELOCS)
5388 tree name_tree = get_identifier (name);
5389 TREE_ASM_WRITTEN (name_tree) = 1;
5393 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5394 extern int size_directive_output;
5396 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5397 definitions except that it uses mips_declare_object() to emit the label. */
5400 mips_declare_object_name (FILE *stream, const char *name,
5401 tree decl ATTRIBUTE_UNUSED)
5403 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5404 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5407 size_directive_output = 0;
5408 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5412 size_directive_output = 1;
5413 size = int_size_in_bytes (TREE_TYPE (decl));
5414 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5417 mips_declare_object (stream, name, "", ":\n", 0);
5420 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5423 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5427 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5428 if (!flag_inhibit_size_directive
5429 && DECL_SIZE (decl) != 0
5430 && !at_end && top_level
5431 && DECL_INITIAL (decl) == error_mark_node
5432 && !size_directive_output)
5436 size_directive_output = 1;
5437 size = int_size_in_bytes (TREE_TYPE (decl));
5438 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5443 /* Return true if X is a small data address that can be rewritten
5447 mips_rewrite_small_data_p (rtx x)
5449 enum mips_symbol_type symbol_type;
5451 return (TARGET_EXPLICIT_RELOCS
5452 && mips_symbolic_constant_p (x, &symbol_type)
5453 && symbol_type == SYMBOL_SMALL_DATA);
5457 /* A for_each_rtx callback for mips_small_data_pattern_p. */
5460 mips_small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5462 if (GET_CODE (*loc) == LO_SUM)
5465 return mips_rewrite_small_data_p (*loc);
5468 /* Return true if OP refers to small data symbols directly, not through
5472 mips_small_data_pattern_p (rtx op)
5474 return for_each_rtx (&op, mips_small_data_pattern_1, 0);
5477 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
5480 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5482 if (mips_rewrite_small_data_p (*loc))
5483 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
5485 if (GET_CODE (*loc) == LO_SUM)
5491 /* If possible, rewrite OP so that it refers to small data using
5492 explicit relocations. */
5495 mips_rewrite_small_data (rtx op)
5497 op = copy_insn (op);
5498 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
5502 /* Return true if the current function has an insn that implicitly
5506 mips_function_has_gp_insn (void)
5508 /* Don't bother rechecking if we found one last time. */
5509 if (!cfun->machine->has_gp_insn_p)
5513 push_topmost_sequence ();
5514 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
5516 && GET_CODE (PATTERN (insn)) != USE
5517 && GET_CODE (PATTERN (insn)) != CLOBBER
5518 && (get_attr_got (insn) != GOT_UNSET
5519 || small_data_pattern (PATTERN (insn), VOIDmode)))
5521 pop_topmost_sequence ();
5523 cfun->machine->has_gp_insn_p = (insn != 0);
5525 return cfun->machine->has_gp_insn_p;
5529 /* Return the register that should be used as the global pointer
5530 within this function. Return 0 if the function doesn't need
5531 a global pointer. */
5534 mips_global_pointer (void)
5538 /* $gp is always available in non-abicalls code. */
5539 if (!TARGET_ABICALLS)
5540 return GLOBAL_POINTER_REGNUM;
5542 /* We must always provide $gp when it is used implicitly. */
5543 if (!TARGET_EXPLICIT_RELOCS)
5544 return GLOBAL_POINTER_REGNUM;
5546 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
5548 if (current_function_profile)
5549 return GLOBAL_POINTER_REGNUM;
5551 /* If the function has a nonlocal goto, $gp must hold the correct
5552 global pointer for the target function. */
5553 if (current_function_has_nonlocal_goto)
5554 return GLOBAL_POINTER_REGNUM;
5556 /* If the gp is never referenced, there's no need to initialize it.
5557 Note that reload can sometimes introduce constant pool references
5558 into a function that otherwise didn't need them. For example,
5559 suppose we have an instruction like:
5561 (set (reg:DF R1) (float:DF (reg:SI R2)))
5563 If R2 turns out to be constant such as 1, the instruction may have a
5564 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
5565 using this constant if R2 doesn't get allocated to a register.
5567 In cases like these, reload will have added the constant to the pool
5568 but no instruction will yet refer to it. */
5569 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
5570 && !current_function_uses_const_pool
5571 && !mips_function_has_gp_insn ())
5574 /* We need a global pointer, but perhaps we can use a call-clobbered
5575 register instead of $gp. */
5576 if (TARGET_NEWABI && current_function_is_leaf)
5577 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5578 if (!regs_ever_live[regno]
5579 && call_used_regs[regno]
5580 && !fixed_regs[regno]
5581 && regno != PIC_FUNCTION_ADDR_REGNUM)
5584 return GLOBAL_POINTER_REGNUM;
5588 /* Return true if the current function must save REGNO. */
5591 mips_save_reg_p (unsigned int regno)
5593 /* We only need to save $gp for NewABI PIC. */
5594 if (regno == GLOBAL_POINTER_REGNUM)
5595 return (TARGET_ABICALLS && TARGET_NEWABI
5596 && cfun->machine->global_pointer == regno);
5598 /* Check call-saved registers. */
5599 if (regs_ever_live[regno] && !call_used_regs[regno])
5602 /* We need to save the old frame pointer before setting up a new one. */
5603 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
5606 /* We need to save the incoming return address if it is ever clobbered
5607 within the function. */
5608 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
5615 return_type = DECL_RESULT (current_function_decl);
5617 /* $18 is a special case in mips16 code. It may be used to call
5618 a function which returns a floating point value, but it is
5619 marked in call_used_regs. */
5620 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
5623 /* $31 is also a special case. It will be used to copy a return
5624 value into the floating point registers if the return value is
5626 if (regno == GP_REG_FIRST + 31
5627 && mips16_hard_float
5628 && !aggregate_value_p (return_type, current_function_decl)
5629 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
5630 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
5638 /* Return the bytes needed to compute the frame pointer from the current
5639 stack pointer. SIZE is the size (in bytes) of the local variables.
5641 Mips stack frames look like:
5643 Before call After call
5644 +-----------------------+ +-----------------------+
5647 | caller's temps. | | caller's temps. |
5649 +-----------------------+ +-----------------------+
5651 | arguments on stack. | | arguments on stack. |
5653 +-----------------------+ +-----------------------+
5654 | 4 words to save | | 4 words to save |
5655 | arguments passed | | arguments passed |
5656 | in registers, even | | in registers, even |
5657 SP->| if not passed. | VFP->| if not passed. |
5658 +-----------------------+ +-----------------------+
5660 | fp register save |
5662 +-----------------------+
5664 | gp register save |
5666 +-----------------------+
5670 +-----------------------+
5672 | alloca allocations |
5674 +-----------------------+
5676 | GP save for V.4 abi |
5678 +-----------------------+
5680 | arguments on stack |
5682 +-----------------------+
5684 | arguments passed |
5685 | in registers, even |
5686 low SP->| if not passed. |
5687 memory +-----------------------+
5692 compute_frame_size (HOST_WIDE_INT size)
5695 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
5696 HOST_WIDE_INT var_size; /* # bytes that variables take up */
5697 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
5698 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
5699 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
5700 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
5701 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
5702 unsigned int mask; /* mask of saved gp registers */
5703 unsigned int fmask; /* mask of saved fp registers */
5705 cfun->machine->global_pointer = mips_global_pointer ();
5711 var_size = MIPS_STACK_ALIGN (size);
5712 args_size = current_function_outgoing_args_size;
5713 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
5715 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
5716 functions. If the function has local variables, we're committed
5717 to allocating it anyway. Otherwise reclaim it here. */
5718 if (var_size == 0 && current_function_is_leaf)
5719 cprestore_size = args_size = 0;
5721 /* The MIPS 3.0 linker does not like functions that dynamically
5722 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5723 looks like we are trying to create a second frame pointer to the
5724 function, so allocate some stack space to make it happy. */
5726 if (args_size == 0 && current_function_calls_alloca)
5727 args_size = 4 * UNITS_PER_WORD;
5729 total_size = var_size + args_size + cprestore_size;
5731 /* Calculate space needed for gp registers. */
5732 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5733 if (mips_save_reg_p (regno))
5735 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5736 mask |= 1 << (regno - GP_REG_FIRST);
5739 /* We need to restore these for the handler. */
5740 if (current_function_calls_eh_return)
5745 regno = EH_RETURN_DATA_REGNO (i);
5746 if (regno == INVALID_REGNUM)
5748 gp_reg_size += GET_MODE_SIZE (gpr_mode);
5749 mask |= 1 << (regno - GP_REG_FIRST);
5753 /* This loop must iterate over the same space as its companion in
5754 save_restore_insns. */
5755 for (regno = (FP_REG_LAST - FP_INC + 1);
5756 regno >= FP_REG_FIRST;
5759 if (mips_save_reg_p (regno))
5761 fp_reg_size += FP_INC * UNITS_PER_FPREG;
5762 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
5766 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5767 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
5769 /* Add in space reserved on the stack by the callee for storing arguments
5770 passed in registers. */
5772 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5774 /* Save other computed information. */
5775 cfun->machine->frame.total_size = total_size;
5776 cfun->machine->frame.var_size = var_size;
5777 cfun->machine->frame.args_size = args_size;
5778 cfun->machine->frame.cprestore_size = cprestore_size;
5779 cfun->machine->frame.gp_reg_size = gp_reg_size;
5780 cfun->machine->frame.fp_reg_size = fp_reg_size;
5781 cfun->machine->frame.mask = mask;
5782 cfun->machine->frame.fmask = fmask;
5783 cfun->machine->frame.initialized = reload_completed;
5784 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
5785 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
5789 HOST_WIDE_INT offset;
5791 offset = (args_size + cprestore_size + var_size
5792 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
5793 cfun->machine->frame.gp_sp_offset = offset;
5794 cfun->machine->frame.gp_save_offset = offset - total_size;
5798 cfun->machine->frame.gp_sp_offset = 0;
5799 cfun->machine->frame.gp_save_offset = 0;
5804 HOST_WIDE_INT offset;
5806 offset = (args_size + cprestore_size + var_size
5807 + gp_reg_rounded + fp_reg_size
5808 - FP_INC * UNITS_PER_FPREG);
5809 cfun->machine->frame.fp_sp_offset = offset;
5810 cfun->machine->frame.fp_save_offset = offset - total_size;
5814 cfun->machine->frame.fp_sp_offset = 0;
5815 cfun->machine->frame.fp_save_offset = 0;
5818 /* Ok, we're done. */
5822 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
5823 pointer or argument pointer. TO is either the stack pointer or
5824 hard frame pointer. */
5827 mips_initial_elimination_offset (int from, int to)
5829 HOST_WIDE_INT offset;
5831 compute_frame_size (get_frame_size ());
5833 /* Set OFFSET to the offset from the stack pointer. */
5836 case FRAME_POINTER_REGNUM:
5840 case ARG_POINTER_REGNUM:
5841 offset = cfun->machine->frame.total_size;
5843 offset -= current_function_pretend_args_size;
5850 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
5851 offset -= cfun->machine->frame.args_size;
5856 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
5857 back to a previous frame. */
5859 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
5864 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
5867 /* Use FN to save or restore register REGNO. MODE is the register's
5868 mode and OFFSET is the offset of its save slot from the current
5872 mips_save_restore_reg (enum machine_mode mode, int regno,
5873 HOST_WIDE_INT offset, mips_save_restore_fn fn)
5877 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
5879 fn (gen_rtx_REG (mode, regno), mem);
5883 /* Call FN for each register that is saved by the current function.
5884 SP_OFFSET is the offset of the current stack pointer from the start
5888 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
5890 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
5892 enum machine_mode fpr_mode;
5893 HOST_WIDE_INT offset;
5896 /* Save registers starting from high to low. The debuggers prefer at least
5897 the return register be stored at func+4, and also it allows us not to
5898 need a nop in the epilog if at least one register is reloaded in
5899 addition to return address. */
5900 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
5901 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
5902 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
5904 mips_save_restore_reg (gpr_mode, regno, offset, fn);
5905 offset -= GET_MODE_SIZE (gpr_mode);
5908 /* This loop must iterate over the same space as its companion in
5909 compute_frame_size. */
5910 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
5911 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
5912 for (regno = (FP_REG_LAST - FP_INC + 1);
5913 regno >= FP_REG_FIRST;
5915 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
5917 mips_save_restore_reg (fpr_mode, regno, offset, fn);
5918 offset -= GET_MODE_SIZE (fpr_mode);
5923 /* If we're generating n32 or n64 abicalls, and the current function
5924 does not use $28 as its global pointer, emit a cplocal directive.
5925 Use pic_offset_table_rtx as the argument to the directive. */
5928 mips_output_cplocal (void)
5930 if (!TARGET_EXPLICIT_RELOCS
5931 && cfun->machine->global_pointer > 0
5932 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
5933 output_asm_insn (".cplocal %+", 0);
5936 /* If we're generating n32 or n64 abicalls, emit instructions
5937 to set up the global pointer. */
5940 mips_emit_loadgp (void)
5942 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
5944 rtx addr, offset, incoming_address;
5946 addr = XEXP (DECL_RTL (current_function_decl), 0);
5947 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
5948 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5949 emit_insn (gen_loadgp (offset, incoming_address));
5950 if (!TARGET_EXPLICIT_RELOCS)
5951 emit_insn (gen_loadgp_blockage ());
5955 /* Set up the stack and frame (if desired) for the function. */
5958 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
5961 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
5963 #ifdef SDB_DEBUGGING_INFO
5964 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
5965 SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
5968 /* In mips16 mode, we may need to generate a 32 bit to handle
5969 floating point arguments. The linker will arrange for any 32 bit
5970 functions to call this stub, which will then jump to the 16 bit
5972 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
5973 && current_function_args_info.fp_code != 0)
5974 build_mips16_function_stub (file);
5976 if (!FUNCTION_NAME_ALREADY_DECLARED)
5978 /* Get the function name the same way that toplev.c does before calling
5979 assemble_start_function. This is needed so that the name used here
5980 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5981 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
5983 if (!flag_inhibit_size_directive)
5985 fputs ("\t.ent\t", file);
5986 assemble_name (file, fnname);
5990 assemble_name (file, fnname);
5991 fputs (":\n", file);
5994 /* Stop mips_file_end from treating this function as external. */
5995 if (TARGET_IRIX && mips_abi == ABI_32)
5996 TREE_ASM_WRITTEN (DECL_NAME (cfun->decl)) = 1;
5998 if (!flag_inhibit_size_directive)
6000 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6002 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6003 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6004 ", args= " HOST_WIDE_INT_PRINT_DEC
6005 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6006 (reg_names[(frame_pointer_needed)
6007 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6008 ((frame_pointer_needed && TARGET_MIPS16)
6009 ? tsize - cfun->machine->frame.args_size
6011 reg_names[GP_REG_FIRST + 31],
6012 cfun->machine->frame.var_size,
6013 cfun->machine->frame.num_gp,
6014 cfun->machine->frame.num_fp,
6015 cfun->machine->frame.args_size,
6016 cfun->machine->frame.cprestore_size);
6018 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6019 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6020 cfun->machine->frame.mask,
6021 cfun->machine->frame.gp_save_offset);
6022 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6023 cfun->machine->frame.fmask,
6024 cfun->machine->frame.fp_save_offset);
6027 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6028 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6031 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6033 /* Handle the initialization of $gp for SVR4 PIC. */
6034 if (!cfun->machine->all_noreorder_p)
6035 output_asm_insn ("%(.cpload\t%^%)", 0);
6037 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6039 else if (cfun->machine->all_noreorder_p)
6040 output_asm_insn ("%(%<", 0);
6042 /* Tell the assembler which register we're using as the global
6043 pointer. This is needed for thunks, since they can use either
6044 explicit relocs or assembler macros. */
6045 mips_output_cplocal ();
6048 /* Make the last instruction frame related and note that it performs
6049 the operation described by FRAME_PATTERN. */
6052 mips_set_frame_expr (rtx frame_pattern)
6056 insn = get_last_insn ();
6057 RTX_FRAME_RELATED_P (insn) = 1;
6058 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6064 /* Return a frame-related rtx that stores REG at MEM.
6065 REG must be a single register. */
6068 mips_frame_set (rtx mem, rtx reg)
6070 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6071 RTX_FRAME_RELATED_P (set) = 1;
6076 /* Save register REG to MEM. Make the instruction frame-related. */
6079 mips_save_reg (rtx reg, rtx mem)
6081 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6085 if (mips_split_64bit_move_p (mem, reg))
6086 mips_split_64bit_move (mem, reg);
6088 emit_move_insn (mem, reg);
6090 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6091 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6092 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6097 && REGNO (reg) != GP_REG_FIRST + 31
6098 && !M16_REG_P (REGNO (reg)))
6100 /* Save a non-mips16 register by moving it through a temporary.
6101 We don't need to do this for $31 since there's a special
6102 instruction for it. */
6103 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6104 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6107 emit_move_insn (mem, reg);
6109 mips_set_frame_expr (mips_frame_set (mem, reg));
6114 /* Expand the prologue into a bunch of separate insns. */
6117 mips_expand_prologue (void)
6121 if (cfun->machine->global_pointer > 0)
6122 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6124 size = compute_frame_size (get_frame_size ());
6126 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6127 bytes beforehand; this is enough to cover the register save area
6128 without going out of range. */
6129 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6131 HOST_WIDE_INT step1;
6133 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6134 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6136 GEN_INT (-step1)))) = 1;
6138 mips_for_each_saved_reg (size, mips_save_reg);
6141 /* Allocate the rest of the frame. */
6144 if (SMALL_OPERAND (-size))
6145 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6147 GEN_INT (-size)))) = 1;
6150 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6153 /* There are no instructions to add or subtract registers
6154 from the stack pointer, so use the frame pointer as a
6155 temporary. We should always be using a frame pointer
6156 in this case anyway. */
6157 gcc_assert (frame_pointer_needed);
6158 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6159 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6160 hard_frame_pointer_rtx,
6161 MIPS_PROLOGUE_TEMP (Pmode)));
6162 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6165 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6167 MIPS_PROLOGUE_TEMP (Pmode)));
6169 /* Describe the combined effect of the previous instructions. */
6171 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6172 plus_constant (stack_pointer_rtx, -size)));
6176 /* Set up the frame pointer, if we're using one. In mips16 code,
6177 we point the frame pointer ahead of the outgoing argument area.
6178 This should allow more variables & incoming arguments to be
6179 accessed with unextended instructions. */
6180 if (frame_pointer_needed)
6182 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6184 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6186 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6191 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6192 stack_pointer_rtx)) = 1;
6195 /* If generating o32/o64 abicalls, save $gp on the stack. */
6196 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6197 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6199 mips_emit_loadgp ();
6201 /* If we are profiling, make sure no instructions are scheduled before
6202 the call to mcount. */
6204 if (current_function_profile)
6205 emit_insn (gen_blockage ());
6208 /* Do any necessary cleanup after a function to restore stack, frame,
6211 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6214 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6215 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6217 /* Reinstate the normal $gp. */
6218 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6219 mips_output_cplocal ();
6221 if (cfun->machine->all_noreorder_p)
6223 /* Avoid using %>%) since it adds excess whitespace. */
6224 output_asm_insn (".set\tmacro", 0);
6225 output_asm_insn (".set\treorder", 0);
6226 set_noreorder = set_nomacro = 0;
6229 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6233 /* Get the function name the same way that toplev.c does before calling
6234 assemble_start_function. This is needed so that the name used here
6235 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6236 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6237 fputs ("\t.end\t", file);
6238 assemble_name (file, fnname);
6243 /* Emit instructions to restore register REG from slot MEM. */
6246 mips_restore_reg (rtx reg, rtx mem)
6248 /* There's no mips16 instruction to load $31 directly. Load into
6249 $7 instead and adjust the return insn appropriately. */
6250 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6251 reg = gen_rtx_REG (GET_MODE (reg), 7);
6253 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6255 /* Can't restore directly; move through a temporary. */
6256 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6257 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6260 emit_move_insn (reg, mem);
6264 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6265 if this epilogue precedes a sibling call, false if it is for a normal
6266 "epilogue" pattern. */
6269 mips_expand_epilogue (int sibcall_p)
6271 HOST_WIDE_INT step1, step2;
6274 if (!sibcall_p && mips_can_use_return_insn ())
6276 emit_jump_insn (gen_return ());
6280 /* Split the frame into two. STEP1 is the amount of stack we should
6281 deallocate before restoring the registers. STEP2 is the amount we
6282 should deallocate afterwards.
6284 Start off by assuming that no registers need to be restored. */
6285 step1 = cfun->machine->frame.total_size;
6288 /* Work out which register holds the frame address. Account for the
6289 frame pointer offset used by mips16 code. */
6290 if (!frame_pointer_needed)
6291 base = stack_pointer_rtx;
6294 base = hard_frame_pointer_rtx;
6296 step1 -= cfun->machine->frame.args_size;
6299 /* If we need to restore registers, deallocate as much stack as
6300 possible in the second step without going out of range. */
6301 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6303 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6307 /* Set TARGET to BASE + STEP1. */
6313 /* Get an rtx for STEP1 that we can add to BASE. */
6314 adjust = GEN_INT (step1);
6315 if (!SMALL_OPERAND (step1))
6317 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6318 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6321 /* Normal mode code can copy the result straight into $sp. */
6323 target = stack_pointer_rtx;
6325 emit_insn (gen_add3_insn (target, base, adjust));
6328 /* Copy TARGET into the stack pointer. */
6329 if (target != stack_pointer_rtx)
6330 emit_move_insn (stack_pointer_rtx, target);
6332 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6333 implicitly used by all SYMBOL_REFs. We must emit a blockage
6334 insn before restoring it. */
6335 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6336 emit_insn (gen_blockage ());
6338 /* Restore the registers. */
6339 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6342 /* Deallocate the final bit of the frame. */
6344 emit_insn (gen_add3_insn (stack_pointer_rtx,
6348 /* Add in the __builtin_eh_return stack adjustment. We need to
6349 use a temporary in mips16 code. */
6350 if (current_function_calls_eh_return)
6354 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6355 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6356 MIPS_EPILOGUE_TEMP (Pmode),
6357 EH_RETURN_STACKADJ_RTX));
6358 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6361 emit_insn (gen_add3_insn (stack_pointer_rtx,
6363 EH_RETURN_STACKADJ_RTX));
6368 /* The mips16 loads the return address into $7, not $31. */
6369 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6370 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6371 GP_REG_FIRST + 7)));
6373 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6374 GP_REG_FIRST + 31)));
6378 /* Return nonzero if this function is known to have a null epilogue.
6379 This allows the optimizer to omit jumps to jumps if no stack
6383 mips_can_use_return_insn (void)
6387 if (! reload_completed)
6390 if (regs_ever_live[31] || current_function_profile)
6393 return_type = DECL_RESULT (current_function_decl);
6395 /* In mips16 mode, a function which returns a floating point value
6396 needs to arrange to copy the return value into the floating point
6399 && mips16_hard_float
6400 && ! aggregate_value_p (return_type, current_function_decl)
6401 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6402 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6405 if (cfun->machine->frame.initialized)
6406 return cfun->machine->frame.total_size == 0;
6408 return compute_frame_size (get_frame_size ()) == 0;
6411 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6412 in order to avoid duplicating too much logic from elsewhere. */
6415 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6416 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6419 rtx this, temp1, temp2, insn, fnaddr;
6421 /* Pretend to be a post-reload pass while generating rtl. */
6423 reload_completed = 1;
6424 reset_block_changes ();
6426 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6427 for TARGET_NEWABI since the latter is a call-saved register. */
6428 if (TARGET_ABICALLS)
6429 cfun->machine->global_pointer
6430 = REGNO (pic_offset_table_rtx)
6431 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6433 /* Set up the global pointer for n32 or n64 abicalls. */
6434 mips_emit_loadgp ();
6436 /* We need two temporary registers in some cases. */
6437 temp1 = gen_rtx_REG (Pmode, 2);
6438 temp2 = gen_rtx_REG (Pmode, 3);
6440 /* Find out which register contains the "this" pointer. */
6441 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6442 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6444 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6446 /* Add DELTA to THIS. */
6449 rtx offset = GEN_INT (delta);
6450 if (!SMALL_OPERAND (delta))
6452 emit_move_insn (temp1, offset);
6455 emit_insn (gen_add3_insn (this, this, offset));
6458 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6459 if (vcall_offset != 0)
6463 /* Set TEMP1 to *THIS. */
6464 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
6466 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
6467 addr = mips_add_offset (temp2, temp1, vcall_offset);
6469 /* Load the offset and add it to THIS. */
6470 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
6471 emit_insn (gen_add3_insn (this, this, temp1));
6474 /* Jump to the target function. Use a sibcall if direct jumps are
6475 allowed, otherwise load the address into a register first. */
6476 fnaddr = XEXP (DECL_RTL (function), 0);
6477 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
6479 /* This is messy. gas treats "la $25,foo" as part of a call
6480 sequence and may allow a global "foo" to be lazily bound.
6481 The general move patterns therefore reject this combination.
6483 In this context, lazy binding would actually be OK for o32 and o64,
6484 but it's still wrong for n32 and n64; see mips_load_call_address.
6485 We must therefore load the address via a temporary register if
6486 mips_dangerous_for_la25_p.
6488 If we jump to the temporary register rather than $25, the assembler
6489 can use the move insn to fill the jump's delay slot. */
6490 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
6491 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6492 mips_load_call_address (temp1, fnaddr, true);
6494 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
6495 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
6496 emit_jump_insn (gen_indirect_jump (temp1));
6500 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
6501 SIBLING_CALL_P (insn) = 1;
6504 /* Run just enough of rest_of_compilation. This sequence was
6505 "borrowed" from alpha.c. */
6506 insn = get_insns ();
6507 insn_locators_initialize ();
6508 split_all_insns_noflow ();
6510 mips16_lay_out_constants ();
6511 shorten_branches (insn);
6512 final_start_function (insn, file, 1);
6513 final (insn, file, 1, 0);
6514 final_end_function ();
6516 /* Clean up the vars set above. Note that final_end_function resets
6517 the global pointer for us. */
6518 reload_completed = 0;
6522 /* Returns nonzero if X contains a SYMBOL_REF. */
6525 symbolic_expression_p (rtx x)
6527 if (GET_CODE (x) == SYMBOL_REF)
6530 if (GET_CODE (x) == CONST)
6531 return symbolic_expression_p (XEXP (x, 0));
6534 return symbolic_expression_p (XEXP (x, 0));
6536 if (ARITHMETIC_P (x))
6537 return (symbolic_expression_p (XEXP (x, 0))
6538 || symbolic_expression_p (XEXP (x, 1)));
6543 /* Choose the section to use for the constant rtx expression X that has
6547 mips_select_rtx_section (enum machine_mode mode, rtx x,
6548 unsigned HOST_WIDE_INT align)
6552 /* In mips16 mode, the constant table always goes in the same section
6553 as the function, so that constants can be loaded using PC relative
6555 function_section (current_function_decl);
6557 else if (TARGET_EMBEDDED_DATA)
6559 /* For embedded applications, always put constants in read-only data,
6560 in order to reduce RAM usage. */
6561 mergeable_constant_section (mode, align, 0);
6565 /* For hosted applications, always put constants in small data if
6566 possible, as this gives the best performance. */
6567 /* ??? Consider using mergeable small data sections. */
6569 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
6570 && mips_section_threshold > 0)
6571 named_section (0, ".sdata", 0);
6572 else if (flag_pic && symbolic_expression_p (x))
6573 named_section (0, ".data.rel.ro", 3);
6575 mergeable_constant_section (mode, align, 0);
6579 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
6581 The complication here is that, with the combination TARGET_ABICALLS
6582 && !TARGET_GPWORD, jump tables will use absolute addresses, and should
6583 therefore not be included in the read-only part of a DSO. Handle such
6584 cases by selecting a normal data section instead of a read-only one.
6585 The logic apes that in default_function_rodata_section. */
6588 mips_function_rodata_section (tree decl)
6590 if (!TARGET_ABICALLS || TARGET_GPWORD)
6591 default_function_rodata_section (decl);
6592 else if (decl && DECL_SECTION_NAME (decl))
6594 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6595 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
6597 char *rname = ASTRDUP (name);
6599 named_section_real (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
6601 else if (flag_function_sections && flag_data_sections
6602 && strncmp (name, ".text.", 6) == 0)
6604 char *rname = ASTRDUP (name);
6605 memcpy (rname + 1, "data", 4);
6606 named_section_flags (rname, SECTION_WRITE);
6615 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
6616 access DECL using %gp_rel(...)($gp). */
6619 mips_in_small_data_p (tree decl)
6623 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
6626 /* We don't yet generate small-data references for -mabicalls. See related
6627 -G handling in override_options. */
6628 if (TARGET_ABICALLS)
6631 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
6635 /* Reject anything that isn't in a known small-data section. */
6636 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
6637 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
6640 /* If a symbol is defined externally, the assembler will use the
6641 usual -G rules when deciding how to implement macros. */
6642 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
6645 else if (TARGET_EMBEDDED_DATA)
6647 /* Don't put constants into the small data section: we want them
6648 to be in ROM rather than RAM. */
6649 if (TREE_CODE (decl) != VAR_DECL)
6652 if (TREE_READONLY (decl)
6653 && !TREE_SIDE_EFFECTS (decl)
6654 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
6658 size = int_size_in_bytes (TREE_TYPE (decl));
6659 return (size > 0 && size <= mips_section_threshold);
6662 /* See whether VALTYPE is a record whose fields should be returned in
6663 floating-point registers. If so, return the number of fields and
6664 list them in FIELDS (which should have two elements). Return 0
6667 For n32 & n64, a structure with one or two fields is returned in
6668 floating-point registers as long as every field has a floating-point
6672 mips_fpr_return_fields (tree valtype, tree *fields)
6680 if (TREE_CODE (valtype) != RECORD_TYPE)
6684 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
6686 if (TREE_CODE (field) != FIELD_DECL)
6689 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
6695 fields[i++] = field;
6701 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
6702 a value in the most significant part of $2/$3 if:
6704 - the target is big-endian;
6706 - the value has a structure or union type (we generalize this to
6707 cover aggregates from other languages too); and
6709 - the structure is not returned in floating-point registers. */
6712 mips_return_in_msb (tree valtype)
6716 return (TARGET_NEWABI
6717 && TARGET_BIG_ENDIAN
6718 && AGGREGATE_TYPE_P (valtype)
6719 && mips_fpr_return_fields (valtype, fields) == 0);
6723 /* Return a composite value in a pair of floating-point registers.
6724 MODE1 and OFFSET1 are the mode and byte offset for the first value,
6725 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
6728 For n32 & n64, $f0 always holds the first value and $f2 the second.
6729 Otherwise the values are packed together as closely as possible. */
6732 mips_return_fpr_pair (enum machine_mode mode,
6733 enum machine_mode mode1, HOST_WIDE_INT offset1,
6734 enum machine_mode mode2, HOST_WIDE_INT offset2)
6738 inc = (TARGET_NEWABI ? 2 : FP_INC);
6739 return gen_rtx_PARALLEL
6742 gen_rtx_EXPR_LIST (VOIDmode,
6743 gen_rtx_REG (mode1, FP_RETURN),
6745 gen_rtx_EXPR_LIST (VOIDmode,
6746 gen_rtx_REG (mode2, FP_RETURN + inc),
6747 GEN_INT (offset2))));
6752 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
6753 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
6754 VALTYPE is null and MODE is the mode of the return value. */
6757 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
6758 enum machine_mode mode)
6765 mode = TYPE_MODE (valtype);
6766 unsignedp = TYPE_UNSIGNED (valtype);
6768 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
6769 true, we must promote the mode just as PROMOTE_MODE does. */
6770 mode = promote_mode (valtype, mode, &unsignedp, 1);
6772 /* Handle structures whose fields are returned in $f0/$f2. */
6773 switch (mips_fpr_return_fields (valtype, fields))
6776 return gen_rtx_REG (mode, FP_RETURN);
6779 return mips_return_fpr_pair (mode,
6780 TYPE_MODE (TREE_TYPE (fields[0])),
6781 int_byte_position (fields[0]),
6782 TYPE_MODE (TREE_TYPE (fields[1])),
6783 int_byte_position (fields[1]));
6786 /* If a value is passed in the most significant part of a register, see
6787 whether we have to round the mode up to a whole number of words. */
6788 if (mips_return_in_msb (valtype))
6790 HOST_WIDE_INT size = int_size_in_bytes (valtype);
6791 if (size % UNITS_PER_WORD != 0)
6793 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
6794 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
6798 /* For EABI, the class of return register depends entirely on MODE.
6799 For example, "struct { some_type x; }" and "union { some_type x; }"
6800 are returned in the same way as a bare "some_type" would be.
6801 Other ABIs only use FPRs for scalar, complex or vector types. */
6802 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
6803 return gen_rtx_REG (mode, GP_RETURN);
6806 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
6807 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
6808 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
6809 return gen_rtx_REG (mode, FP_RETURN);
6811 /* Handle long doubles for n32 & n64. */
6813 return mips_return_fpr_pair (mode,
6815 DImode, GET_MODE_SIZE (mode) / 2);
6817 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6818 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
6819 return mips_return_fpr_pair (mode,
6820 GET_MODE_INNER (mode), 0,
6821 GET_MODE_INNER (mode),
6822 GET_MODE_SIZE (mode) / 2);
6824 return gen_rtx_REG (mode, GP_RETURN);
6827 /* Return nonzero when an argument must be passed by reference. */
6830 mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6831 enum machine_mode mode, tree type,
6832 bool named ATTRIBUTE_UNUSED)
6834 if (mips_abi == ABI_EABI)
6838 /* ??? How should SCmode be handled? */
6839 if (type == NULL_TREE || mode == DImode || mode == DFmode)
6842 size = int_size_in_bytes (type);
6843 return size == -1 || size > UNITS_PER_WORD;
6847 /* If we have a variable-sized parameter, we have no choice. */
6848 return targetm.calls.must_pass_in_stack (mode, type);
6853 mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6854 enum machine_mode mode ATTRIBUTE_UNUSED,
6855 tree type ATTRIBUTE_UNUSED, bool named)
6857 return mips_abi == ABI_EABI && named;
6860 /* Return true if registers of class CLASS cannot change from mode FROM
6864 mips_cannot_change_mode_class (enum machine_mode from,
6865 enum machine_mode to, enum reg_class class)
6867 if (MIN (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) <= UNITS_PER_WORD
6868 && MAX (GET_MODE_SIZE (from), GET_MODE_SIZE (to)) > UNITS_PER_WORD)
6870 if (TARGET_BIG_ENDIAN)
6872 /* When a multi-word value is stored in paired floating-point
6873 registers, the first register always holds the low word.
6874 We therefore can't allow FPRs to change between single-word
6875 and multi-word modes. */
6876 if (FP_INC > 1 && reg_classes_intersect_p (FP_REGS, class))
6881 /* LO_REGNO == HI_REGNO + 1, so if a multi-word value is stored
6882 in LO and HI, the high word always comes first. We therefore
6883 can't allow values stored in HI to change between single-word
6884 and multi-word modes. */
6885 if (reg_classes_intersect_p (HI_REG, class))
6889 /* Loading a 32-bit value into a 64-bit floating-point register
6890 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
6891 We can't allow 64-bit float registers to change from SImode to
6895 && GET_MODE_SIZE (to) >= UNITS_PER_WORD
6896 && reg_classes_intersect_p (FP_REGS, class))
6901 /* Return true if X should not be moved directly into register $25.
6902 We need this because many versions of GAS will treat "la $25,foo" as
6903 part of a call sequence and so allow a global "foo" to be lazily bound. */
6906 mips_dangerous_for_la25_p (rtx x)
6908 HOST_WIDE_INT offset;
6910 if (TARGET_EXPLICIT_RELOCS)
6913 mips_split_const (x, &x, &offset);
6914 return global_got_operand (x, VOIDmode);
6917 /* Implement PREFERRED_RELOAD_CLASS. */
6920 mips_preferred_reload_class (rtx x, enum reg_class class)
6922 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
6925 if (TARGET_HARD_FLOAT
6926 && FLOAT_MODE_P (GET_MODE (x))
6927 && reg_class_subset_p (FP_REGS, class))
6930 if (reg_class_subset_p (GR_REGS, class))
6933 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
6939 /* This function returns the register class required for a secondary
6940 register when copying between one of the registers in CLASS, and X,
6941 using MODE. If IN_P is nonzero, the copy is going from X to the
6942 register, otherwise the register is the source. A return value of
6943 NO_REGS means that no secondary register is required. */
6946 mips_secondary_reload_class (enum reg_class class,
6947 enum machine_mode mode, rtx x, int in_p)
6949 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
6953 if (REG_P (x)|| GET_CODE (x) == SUBREG)
6954 regno = true_regnum (x);
6956 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
6958 if (mips_dangerous_for_la25_p (x))
6961 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
6965 /* Copying from HI or LO to anywhere other than a general register
6966 requires a general register. */
6967 if (class == HI_REG || class == LO_REG || class == MD_REGS)
6969 if (TARGET_MIPS16 && in_p)
6971 /* We can't really copy to HI or LO at all in mips16 mode. */
6974 return gp_reg_p ? NO_REGS : gr_regs;
6976 if (MD_REG_P (regno))
6978 if (TARGET_MIPS16 && ! in_p)
6980 /* We can't really copy to HI or LO at all in mips16 mode. */
6983 return class == gr_regs ? NO_REGS : gr_regs;
6986 /* We can only copy a value to a condition code register from a
6987 floating point register, and even then we require a scratch
6988 floating point register. We can only copy a value out of a
6989 condition code register into a general register. */
6990 if (class == ST_REGS)
6994 return gp_reg_p ? NO_REGS : gr_regs;
6996 if (ST_REG_P (regno))
7000 return class == gr_regs ? NO_REGS : gr_regs;
7003 if (class == FP_REGS)
7007 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7010 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7012 /* We can use the l.s and l.d macros to load floating-point
7013 constants. ??? For l.s, we could probably get better
7014 code by returning GR_REGS here. */
7017 else if (gp_reg_p || x == CONST0_RTX (mode))
7019 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7022 else if (FP_REG_P (regno))
7024 /* In this case we can use mov.s or mov.d. */
7029 /* Otherwise, we need to reload through an integer register. */
7034 /* In mips16 mode, going between memory and anything but M16_REGS
7035 requires an M16_REG. */
7038 if (class != M16_REGS && class != M16_NA_REGS)
7046 if (class == M16_REGS || class == M16_NA_REGS)
7055 /* Implement CLASS_MAX_NREGS.
7057 Usually all registers are word-sized. The only supported exception
7058 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7059 registers. A word-based calculation is correct even in that case,
7060 since -msingle-float disallows multi-FPR values.
7062 The FP status registers are an exception to this rule. They are always
7063 4 bytes wide as they only hold condition code modes, and CCmode is always
7064 considered to be 4 bytes wide. */
7067 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7068 enum machine_mode mode)
7070 if (class == ST_REGS)
7071 return (GET_MODE_SIZE (mode) + 3) / 4;
7073 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7077 mips_valid_pointer_mode (enum machine_mode mode)
7079 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7082 /* Define this so that we can deal with a testcase like:
7084 char foo __attribute__ ((mode (SI)));
7086 then compiled with -mabi=64 and -mint64. We have no
7087 32-bit type at that point and so the default case
7091 mips_scalar_mode_supported_p (enum machine_mode mode)
7101 /* Handled via optabs.c. */
7103 return TARGET_64BIT;
7109 /* LONG_DOUBLE_TYPE_SIZE is 128 for TARGET_NEWABI only. */
7111 return TARGET_NEWABI;
7119 /* Target hook for vector_mode_supported_p. */
7121 mips_vector_mode_supported_p (enum machine_mode mode)
7123 if (mode == V2SFmode && TARGET_PAIRED_SINGLE_FLOAT)
7129 /* If we can access small data directly (using gp-relative relocation
7130 operators) return the small data pointer, otherwise return null.
7132 For each mips16 function which refers to GP relative symbols, we
7133 use a pseudo register, initialized at the start of the function, to
7134 hold the $gp value. */
7137 mips16_gp_pseudo_reg (void)
7139 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7144 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7146 /* We want to initialize this to a value which gcc will believe
7149 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7150 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7151 gen_rtx_CONST (Pmode, unspec));
7152 insn = get_insns ();
7155 push_topmost_sequence ();
7156 /* We need to emit the initialization after the FUNCTION_BEG
7157 note, so that it will be integrated. */
7158 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7160 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7162 if (scan == NULL_RTX)
7163 scan = get_insns ();
7164 insn = emit_insn_after (insn, scan);
7165 pop_topmost_sequence ();
7168 return cfun->machine->mips16_gp_pseudo_rtx;
7171 /* Write out code to move floating point arguments in or out of
7172 general registers. Output the instructions to FILE. FP_CODE is
7173 the code describing which arguments are present (see the comment at
7174 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7175 we are copying from the floating point registers. */
7178 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7184 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7185 gcc_assert (TARGET_OLDABI);
7191 gparg = GP_ARG_FIRST;
7192 fparg = FP_ARG_FIRST;
7193 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7197 if ((fparg & 1) != 0)
7199 fprintf (file, "\t%s\t%s,%s\n", s,
7200 reg_names[gparg], reg_names[fparg]);
7202 else if ((f & 3) == 2)
7205 fprintf (file, "\td%s\t%s,%s\n", s,
7206 reg_names[gparg], reg_names[fparg]);
7209 if ((fparg & 1) != 0)
7211 if (TARGET_BIG_ENDIAN)
7212 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7213 reg_names[gparg], reg_names[fparg + 1], s,
7214 reg_names[gparg + 1], reg_names[fparg]);
7216 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7217 reg_names[gparg], reg_names[fparg], s,
7218 reg_names[gparg + 1], reg_names[fparg + 1]);
7231 /* Build a mips16 function stub. This is used for functions which
7232 take arguments in the floating point registers. It is 32 bit code
7233 that moves the floating point args into the general registers, and
7234 then jumps to the 16 bit code. */
7237 build_mips16_function_stub (FILE *file)
7240 char *secname, *stubname;
7241 tree stubid, stubdecl;
7245 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7246 secname = (char *) alloca (strlen (fnname) + 20);
7247 sprintf (secname, ".mips16.fn.%s", fnname);
7248 stubname = (char *) alloca (strlen (fnname) + 20);
7249 sprintf (stubname, "__fn_stub_%s", fnname);
7250 stubid = get_identifier (stubname);
7251 stubdecl = build_decl (FUNCTION_DECL, stubid,
7252 build_function_type (void_type_node, NULL_TREE));
7253 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7255 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7257 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7259 fprintf (file, "%s%s",
7260 need_comma ? ", " : "",
7261 (f & 3) == 1 ? "float" : "double");
7264 fprintf (file, ")\n");
7266 fprintf (file, "\t.set\tnomips16\n");
7267 function_section (stubdecl);
7268 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7270 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7271 within a .ent, and we cannot emit another .ent. */
7272 if (!FUNCTION_NAME_ALREADY_DECLARED)
7274 fputs ("\t.ent\t", file);
7275 assemble_name (file, stubname);
7279 assemble_name (file, stubname);
7280 fputs (":\n", file);
7282 /* We don't want the assembler to insert any nops here. */
7283 fprintf (file, "\t.set\tnoreorder\n");
7285 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7287 fprintf (asm_out_file, "\t.set\tnoat\n");
7288 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7289 assemble_name (file, fnname);
7290 fprintf (file, "\n");
7291 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7292 fprintf (asm_out_file, "\t.set\tat\n");
7294 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7295 with one of the mfc1 instructions, because the result is not
7296 available for one instruction, so if the very first instruction
7297 in the function refers to the register, it will see the wrong
7299 fprintf (file, "\tnop\n");
7301 fprintf (file, "\t.set\treorder\n");
7303 if (!FUNCTION_NAME_ALREADY_DECLARED)
7305 fputs ("\t.end\t", file);
7306 assemble_name (file, stubname);
7310 fprintf (file, "\t.set\tmips16\n");
7312 function_section (current_function_decl);
7315 /* We keep a list of functions for which we have already built stubs
7316 in build_mips16_call_stub. */
7320 struct mips16_stub *next;
7325 static struct mips16_stub *mips16_stubs;
7327 /* Build a call stub for a mips16 call. A stub is needed if we are
7328 passing any floating point values which should go into the floating
7329 point registers. If we are, and the call turns out to be to a 32
7330 bit function, the stub will be used to move the values into the
7331 floating point registers before calling the 32 bit function. The
7332 linker will magically adjust the function call to either the 16 bit
7333 function or the 32 bit stub, depending upon where the function call
7334 is actually defined.
7336 Similarly, we need a stub if the return value might come back in a
7337 floating point register.
7339 RETVAL is the location of the return value, or null if this is
7340 a call rather than a call_value. FN is the address of the
7341 function and ARG_SIZE is the size of the arguments. FP_CODE
7342 is the code built by function_arg. This function returns a nonzero
7343 value if it builds the call instruction itself. */
7346 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7350 char *secname, *stubname;
7351 struct mips16_stub *l;
7352 tree stubid, stubdecl;
7356 /* We don't need to do anything if we aren't in mips16 mode, or if
7357 we were invoked with the -msoft-float option. */
7358 if (! TARGET_MIPS16 || ! mips16_hard_float)
7361 /* Figure out whether the value might come back in a floating point
7363 fpret = (retval != 0
7364 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7365 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7367 /* We don't need to do anything if there were no floating point
7368 arguments and the value will not be returned in a floating point
7370 if (fp_code == 0 && ! fpret)
7373 /* We don't need to do anything if this is a call to a special
7374 mips16 support function. */
7375 if (GET_CODE (fn) == SYMBOL_REF
7376 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7379 /* This code will only work for o32 and o64 abis. The other ABI's
7380 require more sophisticated support. */
7381 gcc_assert (TARGET_OLDABI);
7383 /* We can only handle SFmode and DFmode floating point return
7386 gcc_assert (GET_MODE (retval) == SFmode || GET_MODE (retval) == DFmode);
7388 /* If we're calling via a function pointer, then we must always call
7389 via a stub. There are magic stubs provided in libgcc.a for each
7390 of the required cases. Each of them expects the function address
7391 to arrive in register $2. */
7393 if (GET_CODE (fn) != SYMBOL_REF)
7399 /* ??? If this code is modified to support other ABI's, we need
7400 to handle PARALLEL return values here. */
7402 sprintf (buf, "__mips16_call_stub_%s%d",
7404 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7407 id = get_identifier (buf);
7408 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7410 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7412 if (retval == NULL_RTX)
7413 insn = gen_call_internal (stub_fn, arg_size);
7415 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7416 insn = emit_call_insn (insn);
7418 /* Put the register usage information on the CALL. */
7419 CALL_INSN_FUNCTION_USAGE (insn) =
7420 gen_rtx_EXPR_LIST (VOIDmode,
7421 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7422 CALL_INSN_FUNCTION_USAGE (insn));
7424 /* If we are handling a floating point return value, we need to
7425 save $18 in the function prologue. Putting a note on the
7426 call will mean that regs_ever_live[$18] will be true if the
7427 call is not eliminated, and we can check that in the prologue
7430 CALL_INSN_FUNCTION_USAGE (insn) =
7431 gen_rtx_EXPR_LIST (VOIDmode,
7432 gen_rtx_USE (VOIDmode,
7433 gen_rtx_REG (word_mode, 18)),
7434 CALL_INSN_FUNCTION_USAGE (insn));
7436 /* Return 1 to tell the caller that we've generated the call
7441 /* We know the function we are going to call. If we have already
7442 built a stub, we don't need to do anything further. */
7444 fnname = XSTR (fn, 0);
7445 for (l = mips16_stubs; l != NULL; l = l->next)
7446 if (strcmp (l->name, fnname) == 0)
7451 /* Build a special purpose stub. When the linker sees a
7452 function call in mips16 code, it will check where the target
7453 is defined. If the target is a 32 bit call, the linker will
7454 search for the section defined here. It can tell which
7455 symbol this section is associated with by looking at the
7456 relocation information (the name is unreliable, since this
7457 might be a static function). If such a section is found, the
7458 linker will redirect the call to the start of the magic
7461 If the function does not return a floating point value, the
7462 special stub section is named
7465 If the function does return a floating point value, the stub
7467 .mips16.call.fp.FNNAME
7470 secname = (char *) alloca (strlen (fnname) + 40);
7471 sprintf (secname, ".mips16.call.%s%s",
7474 stubname = (char *) alloca (strlen (fnname) + 20);
7475 sprintf (stubname, "__call_stub_%s%s",
7478 stubid = get_identifier (stubname);
7479 stubdecl = build_decl (FUNCTION_DECL, stubid,
7480 build_function_type (void_type_node, NULL_TREE));
7481 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7483 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7485 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7489 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7491 fprintf (asm_out_file, "%s%s",
7492 need_comma ? ", " : "",
7493 (f & 3) == 1 ? "float" : "double");
7496 fprintf (asm_out_file, ")\n");
7498 fprintf (asm_out_file, "\t.set\tnomips16\n");
7499 assemble_start_function (stubdecl, stubname);
7501 if (!FUNCTION_NAME_ALREADY_DECLARED)
7503 fputs ("\t.ent\t", asm_out_file);
7504 assemble_name (asm_out_file, stubname);
7505 fputs ("\n", asm_out_file);
7507 assemble_name (asm_out_file, stubname);
7508 fputs (":\n", asm_out_file);
7511 /* We build the stub code by hand. That's the only way we can
7512 do it, since we can't generate 32 bit code during a 16 bit
7515 /* We don't want the assembler to insert any nops here. */
7516 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7518 mips16_fp_args (asm_out_file, fp_code, 0);
7522 fprintf (asm_out_file, "\t.set\tnoat\n");
7523 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7525 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7526 fprintf (asm_out_file, "\t.set\tat\n");
7527 /* Unfortunately, we can't fill the jump delay slot. We
7528 can't fill with one of the mtc1 instructions, because the
7529 result is not available for one instruction, so if the
7530 very first instruction in the function refers to the
7531 register, it will see the wrong value. */
7532 fprintf (asm_out_file, "\tnop\n");
7536 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7537 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7538 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7539 /* As above, we can't fill the delay slot. */
7540 fprintf (asm_out_file, "\tnop\n");
7541 if (GET_MODE (retval) == SFmode)
7542 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7543 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7546 if (TARGET_BIG_ENDIAN)
7548 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7549 reg_names[GP_REG_FIRST + 2],
7550 reg_names[FP_REG_FIRST + 1]);
7551 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7552 reg_names[GP_REG_FIRST + 3],
7553 reg_names[FP_REG_FIRST + 0]);
7557 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7558 reg_names[GP_REG_FIRST + 2],
7559 reg_names[FP_REG_FIRST + 0]);
7560 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7561 reg_names[GP_REG_FIRST + 3],
7562 reg_names[FP_REG_FIRST + 1]);
7565 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7566 /* As above, we can't fill the delay slot. */
7567 fprintf (asm_out_file, "\tnop\n");
7570 fprintf (asm_out_file, "\t.set\treorder\n");
7572 #ifdef ASM_DECLARE_FUNCTION_SIZE
7573 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7576 if (!FUNCTION_NAME_ALREADY_DECLARED)
7578 fputs ("\t.end\t", asm_out_file);
7579 assemble_name (asm_out_file, stubname);
7580 fputs ("\n", asm_out_file);
7583 fprintf (asm_out_file, "\t.set\tmips16\n");
7585 /* Record this stub. */
7586 l = (struct mips16_stub *) xmalloc (sizeof *l);
7587 l->name = xstrdup (fnname);
7589 l->next = mips16_stubs;
7593 /* If we expect a floating point return value, but we've built a
7594 stub which does not expect one, then we're in trouble. We can't
7595 use the existing stub, because it won't handle the floating point
7596 value. We can't build a new stub, because the linker won't know
7597 which stub to use for the various calls in this object file.
7598 Fortunately, this case is illegal, since it means that a function
7599 was declared in two different ways in a single compilation. */
7600 if (fpret && ! l->fpret)
7601 error ("cannot handle inconsistent calls to %qs", fnname);
7603 /* If we are calling a stub which handles a floating point return
7604 value, we need to arrange to save $18 in the prologue. We do
7605 this by marking the function call as using the register. The
7606 prologue will later see that it is used, and emit code to save
7613 if (retval == NULL_RTX)
7614 insn = gen_call_internal (fn, arg_size);
7616 insn = gen_call_value_internal (retval, fn, arg_size);
7617 insn = emit_call_insn (insn);
7619 CALL_INSN_FUNCTION_USAGE (insn) =
7620 gen_rtx_EXPR_LIST (VOIDmode,
7621 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
7622 CALL_INSN_FUNCTION_USAGE (insn));
7624 /* Return 1 to tell the caller that we've generated the call
7629 /* Return 0 to let the caller generate the call insn. */
7633 /* An entry in the mips16 constant pool. VALUE is the pool constant,
7634 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
7636 struct mips16_constant {
7637 struct mips16_constant *next;
7640 enum machine_mode mode;
7643 /* Information about an incomplete mips16 constant pool. FIRST is the
7644 first constant, HIGHEST_ADDRESS is the highest address that the first
7645 byte of the pool can have, and INSN_ADDRESS is the current instruction
7648 struct mips16_constant_pool {
7649 struct mips16_constant *first;
7650 int highest_address;
7654 /* Add constant VALUE to POOL and return its label. MODE is the
7655 value's mode (used for CONST_INTs, etc.). */
7658 add_constant (struct mips16_constant_pool *pool,
7659 rtx value, enum machine_mode mode)
7661 struct mips16_constant **p, *c;
7662 bool first_of_size_p;
7664 /* See whether the constant is already in the pool. If so, return the
7665 existing label, otherwise leave P pointing to the place where the
7666 constant should be added.
7668 Keep the pool sorted in increasing order of mode size so that we can
7669 reduce the number of alignments needed. */
7670 first_of_size_p = true;
7671 for (p = &pool->first; *p != 0; p = &(*p)->next)
7673 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
7675 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
7677 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
7678 first_of_size_p = false;
7681 /* In the worst case, the constant needed by the earliest instruction
7682 will end up at the end of the pool. The entire pool must then be
7683 accessible from that instruction.
7685 When adding the first constant, set the pool's highest address to
7686 the address of the first out-of-range byte. Adjust this address
7687 downwards each time a new constant is added. */
7688 if (pool->first == 0)
7689 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
7690 is the address of the instruction with the lowest two bits clear.
7691 The base PC value for ld has the lowest three bits clear. Assume
7692 the worst case here. */
7693 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
7694 pool->highest_address -= GET_MODE_SIZE (mode);
7695 if (first_of_size_p)
7696 /* Take into account the worst possible padding due to alignment. */
7697 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
7699 /* Create a new entry. */
7700 c = (struct mips16_constant *) xmalloc (sizeof *c);
7703 c->label = gen_label_rtx ();
7710 /* Output constant VALUE after instruction INSN and return the last
7711 instruction emitted. MODE is the mode of the constant. */
7714 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
7716 switch (GET_MODE_CLASS (mode))
7720 rtx size = GEN_INT (GET_MODE_SIZE (mode));
7721 return emit_insn_after (gen_consttable_int (value, size), insn);
7725 return emit_insn_after (gen_consttable_float (value), insn);
7727 case MODE_VECTOR_FLOAT:
7728 case MODE_VECTOR_INT:
7731 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
7732 insn = dump_constants_1 (GET_MODE_INNER (mode),
7733 CONST_VECTOR_ELT (value, i), insn);
7743 /* Dump out the constants in CONSTANTS after INSN. */
7746 dump_constants (struct mips16_constant *constants, rtx insn)
7748 struct mips16_constant *c, *next;
7752 for (c = constants; c != NULL; c = next)
7754 /* If necessary, increase the alignment of PC. */
7755 if (align < GET_MODE_SIZE (c->mode))
7757 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
7758 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
7760 align = GET_MODE_SIZE (c->mode);
7762 insn = emit_label_after (c->label, insn);
7763 insn = dump_constants_1 (c->mode, c->value, insn);
7769 emit_barrier_after (insn);
7772 /* Return the length of instruction INSN.
7774 ??? MIPS16 switch tables go in .text, but we don't define
7775 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
7776 compute their lengths correctly. */
7779 mips16_insn_length (rtx insn)
7783 rtx body = PATTERN (insn);
7784 if (GET_CODE (body) == ADDR_VEC)
7785 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
7786 if (GET_CODE (body) == ADDR_DIFF_VEC)
7787 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
7789 return get_attr_length (insn);
7792 /* Rewrite *X so that constant pool references refer to the constant's
7793 label instead. DATA points to the constant pool structure. */
7796 mips16_rewrite_pool_refs (rtx *x, void *data)
7798 struct mips16_constant_pool *pool = data;
7799 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
7800 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
7801 get_pool_constant (*x),
7802 get_pool_mode (*x)));
7806 /* Build MIPS16 constant pools. */
7809 mips16_lay_out_constants (void)
7811 struct mips16_constant_pool pool;
7815 memset (&pool, 0, sizeof (pool));
7816 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7818 /* Rewrite constant pool references in INSN. */
7820 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
7822 pool.insn_address += mips16_insn_length (insn);
7824 if (pool.first != NULL)
7826 /* If there are no natural barriers between the first user of
7827 the pool and the highest acceptable address, we'll need to
7828 create a new instruction to jump around the constant pool.
7829 In the worst case, this instruction will be 4 bytes long.
7831 If it's too late to do this transformation after INSN,
7832 do it immediately before INSN. */
7833 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
7837 label = gen_label_rtx ();
7839 jump = emit_jump_insn_before (gen_jump (label), insn);
7840 JUMP_LABEL (jump) = label;
7841 LABEL_NUSES (label) = 1;
7842 barrier = emit_barrier_after (jump);
7844 emit_label_after (label, barrier);
7845 pool.insn_address += 4;
7848 /* See whether the constant pool is now out of range of the first
7849 user. If so, output the constants after the previous barrier.
7850 Note that any instructions between BARRIER and INSN (inclusive)
7851 will use negative offsets to refer to the pool. */
7852 if (pool.insn_address > pool.highest_address)
7854 dump_constants (pool.first, barrier);
7858 else if (BARRIER_P (insn))
7862 dump_constants (pool.first, get_last_insn ());
7865 /* A temporary variable used by for_each_rtx callbacks, etc. */
7866 static rtx mips_sim_insn;
7868 /* A structure representing the state of the processor pipeline.
7869 Used by the mips_sim_* family of functions. */
7871 /* The maximum number of instructions that can be issued in a cycle.
7872 (Caches mips_issue_rate.) */
7873 unsigned int issue_rate;
7875 /* The current simulation time. */
7878 /* How many more instructions can be issued in the current cycle. */
7879 unsigned int insns_left;
7881 /* LAST_SET[X].INSN is the last instruction to set register X.
7882 LAST_SET[X].TIME is the time at which that instruction was issued.
7883 INSN is null if no instruction has yet set register X. */
7887 } last_set[FIRST_PSEUDO_REGISTER];
7889 /* The pipeline's current DFA state. */
7893 /* Reset STATE to the initial simulation state. */
7896 mips_sim_reset (struct mips_sim *state)
7899 state->insns_left = state->issue_rate;
7900 memset (&state->last_set, 0, sizeof (state->last_set));
7901 state_reset (state->dfa_state);
7904 /* Initialize STATE before its first use. DFA_STATE points to an
7905 allocated but uninitialized DFA state. */
7908 mips_sim_init (struct mips_sim *state, state_t dfa_state)
7910 state->issue_rate = mips_issue_rate ();
7911 state->dfa_state = dfa_state;
7912 mips_sim_reset (state);
7915 /* Advance STATE by one clock cycle. */
7918 mips_sim_next_cycle (struct mips_sim *state)
7921 state->insns_left = state->issue_rate;
7922 state_transition (state->dfa_state, 0);
7925 /* Advance simulation state STATE until instruction INSN can read
7929 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
7933 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
7934 if (state->last_set[REGNO (reg) + i].insn != 0)
7938 t = state->last_set[REGNO (reg) + i].time;
7939 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
7940 while (state->time < t)
7941 mips_sim_next_cycle (state);
7945 /* A for_each_rtx callback. If *X is a register, advance simulation state
7946 DATA until mips_sim_insn can read the register's value. */
7949 mips_sim_wait_regs_2 (rtx *x, void *data)
7952 mips_sim_wait_reg (data, mips_sim_insn, *x);
7956 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
7959 mips_sim_wait_regs_1 (rtx *x, void *data)
7961 for_each_rtx (x, mips_sim_wait_regs_2, data);
7964 /* Advance simulation state STATE until all of INSN's register
7965 dependencies are satisfied. */
7968 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
7970 mips_sim_insn = insn;
7971 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
7974 /* Advance simulation state STATE until the units required by
7975 instruction INSN are available. */
7978 mips_sim_wait_units (struct mips_sim *state, rtx insn)
7982 tmp_state = alloca (state_size ());
7983 while (state->insns_left == 0
7984 || (memcpy (tmp_state, state->dfa_state, state_size ()),
7985 state_transition (tmp_state, insn) >= 0))
7986 mips_sim_next_cycle (state);
7989 /* Advance simulation state STATE until INSN is ready to issue. */
7992 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
7994 mips_sim_wait_regs (state, insn);
7995 mips_sim_wait_units (state, insn);
7998 /* mips_sim_insn has just set X. Update the LAST_SET array
7999 in simulation state DATA. */
8002 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8004 struct mips_sim *state;
8009 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8011 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8012 state->last_set[REGNO (x) + i].time = state->time;
8016 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8017 can issue immediately (i.e., that mips_sim_wait_insn has already
8021 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8023 state_transition (state->dfa_state, insn);
8024 state->insns_left--;
8026 mips_sim_insn = insn;
8027 note_stores (PATTERN (insn), mips_sim_record_set, state);
8030 /* Simulate issuing a NOP in state STATE. */
8033 mips_sim_issue_nop (struct mips_sim *state)
8035 if (state->insns_left == 0)
8036 mips_sim_next_cycle (state);
8037 state->insns_left--;
8040 /* Update simulation state STATE so that it's ready to accept the instruction
8041 after INSN. INSN should be part of the main rtl chain, not a member of a
8045 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8047 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8049 mips_sim_issue_nop (state);
8051 switch (GET_CODE (SEQ_BEGIN (insn)))
8055 /* We can't predict the processor state after a call or label. */
8056 mips_sim_reset (state);
8060 /* The delay slots of branch likely instructions are only executed
8061 when the branch is taken. Therefore, if the caller has simulated
8062 the delay slot instruction, STATE does not really reflect the state
8063 of the pipeline for the instruction after the delay slot. Also,
8064 branch likely instructions tend to incur a penalty when not taken,
8065 so there will probably be an extra delay between the branch and
8066 the instruction after the delay slot. */
8067 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8068 mips_sim_reset (state);
8076 /* The VR4130 pipeline issues aligned pairs of instructions together,
8077 but it stalls the second instruction if it depends on the first.
8078 In order to cut down the amount of logic required, this dependence
8079 check is not based on a full instruction decode. Instead, any non-SPECIAL
8080 instruction is assumed to modify the register specified by bits 20-16
8081 (which is usually the "rt" field).
8083 In beq, beql, bne and bnel instructions, the rt field is actually an
8084 input, so we can end up with a false dependence between the branch
8085 and its delay slot. If this situation occurs in instruction INSN,
8086 try to avoid it by swapping rs and rt. */
8089 vr4130_avoid_branch_rt_conflict (rtx insn)
8093 first = SEQ_BEGIN (insn);
8094 second = SEQ_END (insn);
8096 && NONJUMP_INSN_P (second)
8097 && GET_CODE (PATTERN (first)) == SET
8098 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8099 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8101 /* Check for the right kind of condition. */
8102 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8103 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8104 && REG_P (XEXP (cond, 0))
8105 && REG_P (XEXP (cond, 1))
8106 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8107 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8109 /* SECOND mentions the rt register but not the rs register. */
8110 rtx tmp = XEXP (cond, 0);
8111 XEXP (cond, 0) = XEXP (cond, 1);
8112 XEXP (cond, 1) = tmp;
8117 /* Implement -mvr4130-align. Go through each basic block and simulate the
8118 processor pipeline. If we find that a pair of instructions could execute
8119 in parallel, and the first of those instruction is not 8-byte aligned,
8120 insert a nop to make it aligned. */
8123 vr4130_align_insns (void)
8125 struct mips_sim state;
8126 rtx insn, subinsn, last, last2, next;
8131 /* LAST is the last instruction before INSN to have a nonzero length.
8132 LAST2 is the last such instruction before LAST. */
8136 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8139 mips_sim_init (&state, alloca (state_size ()));
8140 for (insn = get_insns (); insn != 0; insn = next)
8142 unsigned int length;
8144 next = NEXT_INSN (insn);
8146 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8147 This isn't really related to the alignment pass, but we do it on
8148 the fly to avoid a separate instruction walk. */
8149 vr4130_avoid_branch_rt_conflict (insn);
8151 if (USEFUL_INSN_P (insn))
8152 FOR_EACH_SUBINSN (subinsn, insn)
8154 mips_sim_wait_insn (&state, subinsn);
8156 /* If we want this instruction to issue in parallel with the
8157 previous one, make sure that the previous instruction is
8158 aligned. There are several reasons why this isn't worthwhile
8159 when the second instruction is a call:
8161 - Calls are less likely to be performance critical,
8162 - There's a good chance that the delay slot can execute
8163 in parallel with the call.
8164 - The return address would then be unaligned.
8166 In general, if we're going to insert a nop between instructions
8167 X and Y, it's better to insert it immediately after X. That
8168 way, if the nop makes Y aligned, it will also align any labels
8170 if (state.insns_left != state.issue_rate
8171 && !CALL_P (subinsn))
8173 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8175 /* SUBINSN is the first instruction in INSN and INSN is
8176 aligned. We want to align the previous instruction
8177 instead, so insert a nop between LAST2 and LAST.
8179 Note that LAST could be either a single instruction
8180 or a branch with a delay slot. In the latter case,
8181 LAST, like INSN, is already aligned, but the delay
8182 slot must have some extra delay that stops it from
8183 issuing at the same time as the branch. We therefore
8184 insert a nop before the branch in order to align its
8186 emit_insn_after (gen_nop (), last2);
8189 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8191 /* SUBINSN is the delay slot of INSN, but INSN is
8192 currently unaligned. Insert a nop between
8193 LAST and INSN to align it. */
8194 emit_insn_after (gen_nop (), last);
8198 mips_sim_issue_insn (&state, subinsn);
8200 mips_sim_finish_insn (&state, insn);
8202 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8203 length = get_attr_length (insn);
8206 /* If the instruction is an asm statement or multi-instruction
8207 mips.md patern, the length is only an estimate. Insert an
8208 8 byte alignment after it so that the following instructions
8209 can be handled correctly. */
8210 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
8211 && (recog_memoized (insn) < 0 || length >= 8))
8213 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8214 next = NEXT_INSN (next);
8215 mips_sim_next_cycle (&state);
8218 else if (length & 4)
8219 aligned_p = !aligned_p;
8224 /* See whether INSN is an aligned label. */
8225 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8231 /* Subroutine of mips_reorg. If there is a hazard between INSN
8232 and a previous instruction, avoid it by inserting nops after
8235 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8236 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8237 before using the value of that register. *HILO_DELAY counts the
8238 number of instructions since the last hilo hazard (that is,
8239 the number of instructions since the last mflo or mfhi).
8241 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8242 for the next instruction.
8244 LO_REG is an rtx for the LO register, used in dependence checking. */
8247 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8248 rtx *delayed_reg, rtx lo_reg)
8256 pattern = PATTERN (insn);
8258 /* Do not put the whole function in .set noreorder if it contains
8259 an asm statement. We don't know whether there will be hazards
8260 between the asm statement and the gcc-generated code. */
8261 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8262 cfun->machine->all_noreorder_p = false;
8264 /* Ignore zero-length instructions (barriers and the like). */
8265 ninsns = get_attr_length (insn) / 4;
8269 /* Work out how many nops are needed. Note that we only care about
8270 registers that are explicitly mentioned in the instruction's pattern.
8271 It doesn't matter that calls use the argument registers or that they
8272 clobber hi and lo. */
8273 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8274 nops = 2 - *hilo_delay;
8275 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8280 /* Insert the nops between this instruction and the previous one.
8281 Each new nop takes us further from the last hilo hazard. */
8282 *hilo_delay += nops;
8284 emit_insn_after (gen_hazard_nop (), after);
8286 /* Set up the state for the next instruction. */
8287 *hilo_delay += ninsns;
8289 if (INSN_CODE (insn) >= 0)
8290 switch (get_attr_hazard (insn))
8300 set = single_set (insn);
8301 gcc_assert (set != 0);
8302 *delayed_reg = SET_DEST (set);
8308 /* Go through the instruction stream and insert nops where necessary.
8309 See if the whole function can then be put into .set noreorder &
8313 mips_avoid_hazards (void)
8315 rtx insn, last_insn, lo_reg, delayed_reg;
8318 /* Force all instructions to be split into their final form. */
8319 split_all_insns_noflow ();
8321 /* Recalculate instruction lengths without taking nops into account. */
8322 cfun->machine->ignore_hazard_length_p = true;
8323 shorten_branches (get_insns ());
8325 /* The profiler code uses assembler macros. -mfix-vr4120 relies on
8326 assembler nop insertion. */
8327 cfun->machine->all_noreorder_p = (!current_function_profile
8328 && !TARGET_FIX_VR4120);
8333 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8335 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8338 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8339 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8340 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8341 &hilo_delay, &delayed_reg, lo_reg);
8343 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8344 &delayed_reg, lo_reg);
8351 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8357 mips16_lay_out_constants ();
8358 else if (TARGET_EXPLICIT_RELOCS)
8360 if (mips_flag_delayed_branch)
8361 dbr_schedule (get_insns (), dump_file);
8362 mips_avoid_hazards ();
8363 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8364 vr4130_align_insns ();
8368 /* This function does three things:
8370 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8371 - Register the mips16 hardware floating point stubs.
8372 - Register the gofast functions if selected using --enable-gofast. */
8374 #include "config/gofast.h"
8377 mips_init_libfuncs (void)
8379 if (TARGET_FIX_VR4120)
8381 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8382 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8385 if (TARGET_MIPS16 && mips16_hard_float)
8387 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8388 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8389 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8390 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8392 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8393 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8394 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8395 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8396 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8397 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8399 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8400 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8402 if (TARGET_DOUBLE_FLOAT)
8404 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8405 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8406 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8407 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8409 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8410 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8411 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8412 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8413 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8414 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8416 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8417 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8419 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8420 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8424 gofast_maybe_init_libfuncs ();
8427 /* Return a number assessing the cost of moving a register in class
8428 FROM to class TO. The classes are expressed using the enumeration
8429 values such as `GENERAL_REGS'. A value of 2 is the default; other
8430 values are interpreted relative to that.
8432 It is not required that the cost always equal 2 when FROM is the
8433 same as TO; on some machines it is expensive to move between
8434 registers if they are not general registers.
8436 If reload sees an insn consisting of a single `set' between two
8437 hard registers, and if `REGISTER_MOVE_COST' applied to their
8438 classes returns a value of 2, reload does not check to ensure that
8439 the constraints of the insn are met. Setting a cost of other than
8440 2 will allow reload to verify that the constraints are met. You
8441 should do this if the `movM' pattern's constraints do not allow
8444 ??? We make the cost of moving from HI/LO into general
8445 registers the same as for one of moving general registers to
8446 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8447 pseudo to HI/LO. This might hurt optimizations though, it
8448 isn't clear if it is wise. And it might not work in all cases. We
8449 could solve the DImode LO reg problem by using a multiply, just
8450 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8451 problem by using divide instructions. divu puts the remainder in
8452 the HI reg, so doing a divide by -1 will move the value in the HI
8453 reg for all values except -1. We could handle that case by using a
8454 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8455 a compare/branch to test the input value to see which instruction
8456 we need to use. This gets pretty messy, but it is feasible. */
8459 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8460 enum reg_class to, enum reg_class from)
8462 if (from == M16_REGS && GR_REG_CLASS_P (to))
8464 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8466 else if (GR_REG_CLASS_P (from))
8470 else if (to == M16_NA_REGS)
8472 else if (GR_REG_CLASS_P (to))
8479 else if (to == FP_REGS)
8481 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8488 else if (COP_REG_CLASS_P (to))
8492 } /* GR_REG_CLASS_P (from) */
8493 else if (from == FP_REGS)
8495 if (GR_REG_CLASS_P (to))
8497 else if (to == FP_REGS)
8499 else if (to == ST_REGS)
8501 } /* from == FP_REGS */
8502 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8504 if (GR_REG_CLASS_P (to))
8511 } /* from == HI_REG, etc. */
8512 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8514 else if (COP_REG_CLASS_P (from))
8517 } /* COP_REG_CLASS_P (from) */
8524 /* Return the length of INSN. LENGTH is the initial length computed by
8525 attributes in the machine-description file. */
8528 mips_adjust_insn_length (rtx insn, int length)
8530 /* A unconditional jump has an unfilled delay slot if it is not part
8531 of a sequence. A conditional jump normally has a delay slot, but
8532 does not on MIPS16. */
8533 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
8536 /* See how many nops might be needed to avoid hardware hazards. */
8537 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8538 switch (get_attr_hazard (insn))
8552 /* All MIPS16 instructions are a measly two bytes. */
8560 /* Return an asm sequence to start a noat block and load the address
8561 of a label into $1. */
8564 mips_output_load_label (void)
8566 if (TARGET_EXPLICIT_RELOCS)
8570 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
8573 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
8576 if (ISA_HAS_LOAD_DELAY)
8577 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
8578 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
8582 if (Pmode == DImode)
8583 return "%[dla\t%@,%0";
8585 return "%[la\t%@,%0";
8590 /* Output assembly instructions to peform a conditional branch.
8592 INSN is the branch instruction. OPERANDS[0] is the condition.
8593 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
8594 of the first operand to the condition. If TWO_OPERANDS_P is
8595 nonzero the comparison takes two operands; OPERANDS[3] will be the
8598 If INVERTED_P is nonzero we are to branch if the condition does
8599 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
8601 LENGTH is the length (in bytes) of the sequence we are to generate.
8602 That tells us whether to generate a simple conditional branch, or a
8603 reversed conditional branch around a `jr' instruction. */
8605 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
8606 int float_p, int inverted_p, int length)
8608 static char buffer[200];
8609 /* The kind of comparison we are doing. */
8610 enum rtx_code code = GET_CODE (operands[0]);
8611 /* Nonzero if the opcode for the comparison needs a `z' indicating
8612 that it is a comparison against zero. */
8614 /* A string to use in the assembly output to represent the first
8616 const char *op1 = "%z2";
8617 /* A string to use in the assembly output to represent the second
8618 operand. Use the hard-wired zero register if there's no second
8620 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
8621 /* The operand-printing string for the comparison. */
8622 const char *const comp = (float_p ? "%F0" : "%C0");
8623 /* The operand-printing string for the inverted comparison. */
8624 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
8626 /* The MIPS processors (for levels of the ISA at least two), have
8627 "likely" variants of each branch instruction. These instructions
8628 annul the instruction in the delay slot if the branch is not
8630 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
8632 if (!two_operands_p)
8634 /* To compute whether than A > B, for example, we normally
8635 subtract B from A and then look at the sign bit. But, if we
8636 are doing an unsigned comparison, and B is zero, we don't
8637 have to do the subtraction. Instead, we can just check to
8638 see if A is nonzero. Thus, we change the CODE here to
8639 reflect the simpler comparison operation. */
8651 /* A condition which will always be true. */
8657 /* A condition which will always be false. */
8663 /* Not a special case. */
8668 /* Relative comparisons are always done against zero. But
8669 equality comparisons are done between two operands, and therefore
8670 do not require a `z' in the assembly language output. */
8671 need_z_p = (!float_p && code != EQ && code != NE);
8672 /* For comparisons against zero, the zero is not provided
8677 /* Begin by terminating the buffer. That way we can always use
8678 strcat to add to it. */
8685 /* Just a simple conditional branch. */
8687 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
8688 inverted_p ? inverted_comp : comp);
8690 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
8691 inverted_p ? inverted_comp : comp,
8692 need_z_p ? "z" : "",
8702 /* Generate a reversed conditional branch around ` j'
8715 If the original branch was a likely branch, the delay slot
8716 must be executed only if the branch is taken, so generate:
8728 When generating PIC, instead of:
8741 rtx target = gen_label_rtx ();
8743 orig_target = operands[1];
8744 operands[1] = target;
8745 /* Generate the reversed comparison. This takes four
8748 sprintf (buffer, "%%*b%s\t%%Z2%%1",
8749 inverted_p ? comp : inverted_comp);
8751 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
8752 inverted_p ? comp : inverted_comp,
8753 need_z_p ? "z" : "",
8756 output_asm_insn (buffer, operands);
8758 if (length != 16 && length != 28 && ! mips_branch_likely)
8760 /* Output delay slot instruction. */
8761 rtx insn = final_sequence;
8762 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8763 optimize, 0, 1, NULL);
8764 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8767 output_asm_insn ("%#", 0);
8770 output_asm_insn ("j\t%0", &orig_target);
8773 output_asm_insn (mips_output_load_label (), &orig_target);
8774 output_asm_insn ("jr\t%@%]", 0);
8777 if (length != 16 && length != 28 && mips_branch_likely)
8779 /* Output delay slot instruction. */
8780 rtx insn = final_sequence;
8781 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
8782 optimize, 0, 1, NULL);
8783 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
8786 output_asm_insn ("%#", 0);
8788 (*targetm.asm_out.internal_label) (asm_out_file, "L",
8789 CODE_LABEL_NUMBER (target));
8802 /* Used to output div or ddiv instruction DIVISION, which has the operands
8803 given by OPERANDS. Add in a divide-by-zero check if needed.
8805 When working around R4000 and R4400 errata, we need to make sure that
8806 the division is not immediately followed by a shift[1][2]. We also
8807 need to stop the division from being put into a branch delay slot[3].
8808 The easiest way to avoid both problems is to add a nop after the
8809 division. When a divide-by-zero check is needed, this nop can be
8810 used to fill the branch delay slot.
8812 [1] If a double-word or a variable shift executes immediately
8813 after starting an integer division, the shift may give an
8814 incorrect result. See quotations of errata #16 and #28 from
8815 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
8816 in mips.md for details.
8818 [2] A similar bug to [1] exists for all revisions of the
8819 R4000 and the R4400 when run in an MC configuration.
8820 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
8822 "19. In this following sequence:
8824 ddiv (or ddivu or div or divu)
8825 dsll32 (or dsrl32, dsra32)
8827 if an MPT stall occurs, while the divide is slipping the cpu
8828 pipeline, then the following double shift would end up with an
8831 Workaround: The compiler needs to avoid generating any
8832 sequence with divide followed by extended double shift."
8834 This erratum is also present in "MIPS R4400MC Errata, Processor
8835 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
8836 & 3.0" as errata #10 and #4, respectively.
8838 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
8839 (also valid for MIPS R4000MC processors):
8841 "52. R4000SC: This bug does not apply for the R4000PC.
8843 There are two flavors of this bug:
8845 1) If the instruction just after divide takes an RF exception
8846 (tlb-refill, tlb-invalid) and gets an instruction cache
8847 miss (both primary and secondary) and the line which is
8848 currently in secondary cache at this index had the first
8849 data word, where the bits 5..2 are set, then R4000 would
8850 get a wrong result for the div.
8855 ------------------- # end-of page. -tlb-refill
8860 ------------------- # end-of page. -tlb-invalid
8863 2) If the divide is in the taken branch delay slot, where the
8864 target takes RF exception and gets an I-cache miss for the
8865 exception vector or where I-cache miss occurs for the
8866 target address, under the above mentioned scenarios, the
8867 div would get wrong results.
8870 j r2 # to next page mapped or unmapped
8871 div r8,r9 # this bug would be there as long
8872 # as there is an ICache miss and
8873 nop # the "data pattern" is present
8876 beq r0, r0, NextPage # to Next page
8880 This bug is present for div, divu, ddiv, and ddivu
8883 Workaround: For item 1), OS could make sure that the next page
8884 after the divide instruction is also mapped. For item 2), the
8885 compiler could make sure that the divide instruction is not in
8886 the branch delay slot."
8888 These processors have PRId values of 0x00004220 and 0x00004300 for
8889 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
8892 mips_output_division (const char *division, rtx *operands)
8897 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
8899 output_asm_insn (s, operands);
8902 if (TARGET_CHECK_ZERO_DIV)
8906 output_asm_insn (s, operands);
8907 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
8909 else if (GENERATE_DIVIDE_TRAPS)
8911 output_asm_insn (s, operands);
8916 output_asm_insn ("%(bne\t%2,%.,1f", operands);
8917 output_asm_insn (s, operands);
8918 s = "break\t7%)\n1:";
8924 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
8925 with a final "000" replaced by "k". Ignore case.
8927 Note: this function is shared between GCC and GAS. */
8930 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
8932 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
8933 given++, canonical++;
8935 return ((*given == 0 && *canonical == 0)
8936 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
8940 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
8941 CPU name. We've traditionally allowed a lot of variation here.
8943 Note: this function is shared between GCC and GAS. */
8946 mips_matching_cpu_name_p (const char *canonical, const char *given)
8948 /* First see if the name matches exactly, or with a final "000"
8950 if (mips_strict_matching_cpu_name_p (canonical, given))
8953 /* If not, try comparing based on numerical designation alone.
8954 See if GIVEN is an unadorned number, or 'r' followed by a number. */
8955 if (TOLOWER (*given) == 'r')
8957 if (!ISDIGIT (*given))
8960 /* Skip over some well-known prefixes in the canonical name,
8961 hoping to find a number there too. */
8962 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
8964 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
8966 else if (TOLOWER (canonical[0]) == 'r')
8969 return mips_strict_matching_cpu_name_p (canonical, given);
8973 /* Parse an option that takes the name of a processor as its argument.
8974 OPTION is the name of the option and CPU_STRING is the argument.
8975 Return the corresponding processor enumeration if the CPU_STRING is
8976 recognized, otherwise report an error and return null.
8978 A similar function exists in GAS. */
8980 static const struct mips_cpu_info *
8981 mips_parse_cpu (const char *option, const char *cpu_string)
8983 const struct mips_cpu_info *p;
8986 /* In the past, we allowed upper-case CPU names, but it doesn't
8987 work well with the multilib machinery. */
8988 for (s = cpu_string; *s != 0; s++)
8991 warning ("the cpu name must be lower case");
8995 /* 'from-abi' selects the most compatible architecture for the given
8996 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
8997 EABIs, we have to decide whether we're using the 32-bit or 64-bit
8998 version. Look first at the -mgp options, if given, otherwise base
8999 the choice on MASK_64BIT in TARGET_DEFAULT. */
9000 if (strcasecmp (cpu_string, "from-abi") == 0)
9001 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9002 : ABI_NEEDS_64BIT_REGS ? 3
9003 : (TARGET_64BIT ? 3 : 1));
9005 /* 'default' has traditionally been a no-op. Probably not very useful. */
9006 if (strcasecmp (cpu_string, "default") == 0)
9009 for (p = mips_cpu_info_table; p->name != 0; p++)
9010 if (mips_matching_cpu_name_p (p->name, cpu_string))
9013 error ("bad value (%s) for %s", cpu_string, option);
9018 /* Return the processor associated with the given ISA level, or null
9019 if the ISA isn't valid. */
9021 static const struct mips_cpu_info *
9022 mips_cpu_info_from_isa (int isa)
9024 const struct mips_cpu_info *p;
9026 for (p = mips_cpu_info_table; p->name != 0; p++)
9033 /* Implement HARD_REGNO_NREGS. The size of FP registers is controlled
9034 by UNITS_PER_FPREG. The size of FP status registers is always 4, because
9035 they only hold condition code modes, and CCmode is always considered to
9036 be 4 bytes wide. All other registers are word sized. */
9039 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9041 if (ST_REG_P (regno))
9042 return ((GET_MODE_SIZE (mode) + 3) / 4);
9043 else if (! FP_REG_P (regno))
9044 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9046 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9049 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9050 all BLKmode objects are returned in memory. Under the new (N32 and
9051 64-bit MIPS ABIs) small structures are returned in a register.
9052 Objects with varying size must still be returned in memory, of
9056 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9059 return (TYPE_MODE (type) == BLKmode);
9061 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9062 || (int_size_in_bytes (type) == -1));
9066 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9068 return !TARGET_OLDABI;
9071 /* Return true if INSN is a multiply-add or multiply-subtract
9072 instruction and PREV assigns to the accumulator operand. */
9075 mips_linked_madd_p (rtx prev, rtx insn)
9079 x = single_set (insn);
9085 if (GET_CODE (x) == PLUS
9086 && GET_CODE (XEXP (x, 0)) == MULT
9087 && reg_set_p (XEXP (x, 1), prev))
9090 if (GET_CODE (x) == MINUS
9091 && GET_CODE (XEXP (x, 1)) == MULT
9092 && reg_set_p (XEXP (x, 0), prev))
9098 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9099 that may clobber hi or lo. */
9101 static rtx mips_macc_chains_last_hilo;
9103 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9104 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9107 mips_macc_chains_record (rtx insn)
9109 if (get_attr_may_clobber_hilo (insn))
9110 mips_macc_chains_last_hilo = insn;
9113 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9114 has NREADY elements, looking for a multiply-add or multiply-subtract
9115 instruction that is cumulative with mips_macc_chains_last_hilo.
9116 If there is one, promote it ahead of anything else that might
9117 clobber hi or lo. */
9120 mips_macc_chains_reorder (rtx *ready, int nready)
9124 if (mips_macc_chains_last_hilo != 0)
9125 for (i = nready - 1; i >= 0; i--)
9126 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9128 for (j = nready - 1; j > i; j--)
9129 if (recog_memoized (ready[j]) >= 0
9130 && get_attr_may_clobber_hilo (ready[j]))
9132 mips_promote_ready (ready, i, j);
9139 /* The last instruction to be scheduled. */
9141 static rtx vr4130_last_insn;
9143 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9144 points to an rtx that is initially an instruction. Nullify the rtx
9145 if the instruction uses the value of register X. */
9148 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9150 rtx *insn_ptr = data;
9153 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9157 /* Return true if there is true register dependence between vr4130_last_insn
9161 vr4130_true_reg_dependence_p (rtx insn)
9163 note_stores (PATTERN (vr4130_last_insn),
9164 vr4130_true_reg_dependence_p_1, &insn);
9168 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9169 the ready queue and that INSN2 is the instruction after it, return
9170 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9171 in which INSN1 and INSN2 can probably issue in parallel, but for
9172 which (INSN2, INSN1) should be less sensitive to instruction
9173 alignment than (INSN1, INSN2). See 4130.md for more details. */
9176 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9180 /* Check for the following case:
9182 1) there is some other instruction X with an anti dependence on INSN1;
9183 2) X has a higher priority than INSN2; and
9184 3) X is an arithmetic instruction (and thus has no unit restrictions).
9186 If INSN1 is the last instruction blocking X, it would better to
9187 choose (INSN1, X) over (INSN2, INSN1). */
9188 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9189 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9190 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9191 && recog_memoized (XEXP (dep, 0)) >= 0
9192 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9195 if (vr4130_last_insn != 0
9196 && recog_memoized (insn1) >= 0
9197 && recog_memoized (insn2) >= 0)
9199 /* See whether INSN1 and INSN2 use different execution units,
9200 or if they are both ALU-type instructions. If so, they can
9201 probably execute in parallel. */
9202 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9203 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9204 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9206 /* If only one of the instructions has a dependence on
9207 vr4130_last_insn, prefer to schedule the other one first. */
9208 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9209 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9213 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9214 is not an ALU-type instruction and if INSN1 uses the same
9215 execution unit. (Note that if this condition holds, we already
9216 know that INSN2 uses a different execution unit.) */
9217 if (class1 != VR4130_CLASS_ALU
9218 && recog_memoized (vr4130_last_insn) >= 0
9219 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9226 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9227 queue with at least two instructions. Swap the first two if
9228 vr4130_swap_insns_p says that it could be worthwhile. */
9231 vr4130_reorder (rtx *ready, int nready)
9233 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9234 mips_promote_ready (ready, nready - 2, nready - 1);
9237 /* Remove the instruction at index LOWER from ready queue READY and
9238 reinsert it in front of the instruction at index HIGHER. LOWER must
9242 mips_promote_ready (rtx *ready, int lower, int higher)
9247 new_head = ready[lower];
9248 for (i = lower; i < higher; i++)
9249 ready[i] = ready[i + 1];
9250 ready[i] = new_head;
9253 /* Implement TARGET_SCHED_REORDER. */
9256 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9257 rtx *ready, int *nreadyp, int cycle)
9259 if (!reload_completed && TUNE_MACC_CHAINS)
9262 mips_macc_chains_last_hilo = 0;
9264 mips_macc_chains_reorder (ready, *nreadyp);
9266 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9269 vr4130_last_insn = 0;
9271 vr4130_reorder (ready, *nreadyp);
9273 return mips_issue_rate ();
9276 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9279 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9282 switch (GET_CODE (PATTERN (insn)))
9286 /* Don't count USEs and CLOBBERs against the issue rate. */
9291 if (!reload_completed && TUNE_MACC_CHAINS)
9292 mips_macc_chains_record (insn);
9293 vr4130_last_insn = insn;
9299 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9300 dependencies have no cost. */
9303 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9304 rtx dep ATTRIBUTE_UNUSED, int cost)
9306 if (REG_NOTE_KIND (link) != 0)
9311 /* Return the number of instructions that can be issued per cycle. */
9314 mips_issue_rate (void)
9318 case PROCESSOR_R4130:
9319 case PROCESSOR_R5400:
9320 case PROCESSOR_R5500:
9321 case PROCESSOR_R7000:
9322 case PROCESSOR_R9000:
9326 /* This is actually 4, but we get better performance if we claim 3.
9327 This is partly because of unwanted speculative code motion with the
9328 larger number, and partly because in most common cases we can't
9329 reach the theoretical max of 4. */
9337 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9338 be as wide as the scheduling freedom in the DFA. */
9341 mips_multipass_dfa_lookahead (void)
9343 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9344 if (mips_tune == PROCESSOR_SB1)
9350 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
9351 return the first operand of the associated "pref" or "prefx" insn. */
9354 mips_prefetch_cookie (rtx write, rtx locality)
9356 /* store_streamed / load_streamed. */
9357 if (INTVAL (locality) <= 0)
9358 return GEN_INT (INTVAL (write) + 4);
9361 if (INTVAL (locality) <= 2)
9364 /* store_retained / load_retained. */
9365 return GEN_INT (INTVAL (write) + 6);
9368 /* MIPS builtin function support. */
9370 struct builtin_description
9372 /* The code of the main .md file instruction. See mips_builtin_type
9373 for more information. */
9374 enum insn_code icode;
9376 /* The floating-point comparison code to use with ICODE, if any. */
9377 enum mips_fp_condition cond;
9379 /* The name of the builtin function. */
9382 /* Specifies how the function should be expanded. */
9383 enum mips_builtin_type builtin_type;
9385 /* The function's prototype. */
9386 enum mips_function_type function_type;
9388 /* The target flags required for this function. */
9392 /* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_mips_<INSN>.
9393 FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
9394 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
9395 { CODE_FOR_mips_ ## INSN, 0, "__builtin_mips_" #INSN, \
9396 MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, TARGET_FLAGS }
9398 /* Define __builtin_mips_<INSN>_<COND>_{s,d}, both of which require
9400 #define CMP_SCALAR_BUILTINS(INSN, COND, TARGET_FLAGS) \
9401 { CODE_FOR_mips_ ## INSN ## _cond_s, MIPS_FP_COND_ ## COND, \
9402 "__builtin_mips_" #INSN "_" #COND "_s", \
9403 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, TARGET_FLAGS }, \
9404 { CODE_FOR_mips_ ## INSN ## _cond_d, MIPS_FP_COND_ ## COND, \
9405 "__builtin_mips_" #INSN "_" #COND "_d", \
9406 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, TARGET_FLAGS }
9408 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
9409 The lower and upper forms require TARGET_FLAGS while the any and all
9410 forms require MASK_MIPS3D. */
9411 #define CMP_PS_BUILTINS(INSN, COND, TARGET_FLAGS) \
9412 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9413 "__builtin_mips_any_" #INSN "_" #COND "_ps", \
9414 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9415 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9416 "__builtin_mips_all_" #INSN "_" #COND "_ps", \
9417 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, MASK_MIPS3D }, \
9418 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9419 "__builtin_mips_lower_" #INSN "_" #COND "_ps", \
9420 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }, \
9421 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9422 "__builtin_mips_upper_" #INSN "_" #COND "_ps", \
9423 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, TARGET_FLAGS }
9425 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
9426 require MASK_MIPS3D. */
9427 #define CMP_4S_BUILTINS(INSN, COND) \
9428 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9429 "__builtin_mips_any_" #INSN "_" #COND "_4s", \
9430 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9432 { CODE_FOR_mips_ ## INSN ## _cond_4s, MIPS_FP_COND_ ## COND, \
9433 "__builtin_mips_all_" #INSN "_" #COND "_4s", \
9434 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9437 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
9438 instruction requires TARGET_FLAGS. */
9439 #define MOVTF_BUILTINS(INSN, COND, TARGET_FLAGS) \
9440 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9441 "__builtin_mips_movt_" #INSN "_" #COND "_ps", \
9442 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9444 { CODE_FOR_mips_ ## INSN ## _cond_ps, MIPS_FP_COND_ ## COND, \
9445 "__builtin_mips_movf_" #INSN "_" #COND "_ps", \
9446 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
9449 /* Define all the builtins related to c.cond.fmt condition COND. */
9450 #define CMP_BUILTINS(COND) \
9451 MOVTF_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
9452 MOVTF_BUILTINS (cabs, COND, MASK_MIPS3D), \
9453 CMP_SCALAR_BUILTINS (cabs, COND, MASK_MIPS3D), \
9454 CMP_PS_BUILTINS (c, COND, MASK_PAIRED_SINGLE), \
9455 CMP_PS_BUILTINS (cabs, COND, MASK_MIPS3D), \
9456 CMP_4S_BUILTINS (c, COND), \
9457 CMP_4S_BUILTINS (cabs, COND)
9459 /* __builtin_mips_abs_ps() maps to the standard absM2 pattern. */
9460 #define CODE_FOR_mips_abs_ps CODE_FOR_absv2sf2
9462 static const struct builtin_description mips_bdesc[] =
9464 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
9465 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
9466 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
9467 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_PAIRED_SINGLE),
9468 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, MASK_PAIRED_SINGLE),
9469 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
9470 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
9471 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE),
9473 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, MASK_PAIRED_SINGLE),
9474 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9475 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9476 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9477 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9479 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9480 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9481 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9482 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9483 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9484 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9486 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, MASK_MIPS3D),
9487 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, MASK_MIPS3D),
9488 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, MASK_MIPS3D),
9489 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, MASK_MIPS3D),
9490 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, MASK_MIPS3D),
9491 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, MASK_MIPS3D),
9493 MIPS_FP_CONDITIONS (CMP_BUILTINS)
9496 /* Builtin functions for the SB-1 processor. */
9498 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
9500 static const struct builtin_description sb1_bdesc[] =
9502 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, MASK_PAIRED_SINGLE)
9505 /* This helps provide a mapping from builtin function codes to bdesc
9510 /* The builtin function table that this entry describes. */
9511 const struct builtin_description *bdesc;
9513 /* The number of entries in the builtin function table. */
9516 /* The target processor that supports these builtin functions.
9517 PROCESSOR_DEFAULT means we enable them for all processors. */
9518 enum processor_type proc;
9521 static const struct bdesc_map bdesc_arrays[] =
9523 { mips_bdesc, ARRAY_SIZE (mips_bdesc), PROCESSOR_DEFAULT },
9524 { sb1_bdesc, ARRAY_SIZE (sb1_bdesc), PROCESSOR_SB1 }
9527 /* Take the head of argument list *ARGLIST and convert it into a form
9528 suitable for input operand OP of instruction ICODE. Return the value
9529 and point *ARGLIST at the next element of the list. */
9532 mips_prepare_builtin_arg (enum insn_code icode,
9533 unsigned int op, tree *arglist)
9536 enum machine_mode mode;
9538 value = expand_expr (TREE_VALUE (*arglist), NULL_RTX, VOIDmode, 0);
9539 mode = insn_data[icode].operand[op].mode;
9540 if (!insn_data[icode].operand[op].predicate (value, mode))
9541 value = copy_to_mode_reg (mode, value);
9543 *arglist = TREE_CHAIN (*arglist);
9547 /* Return an rtx suitable for output operand OP of instruction ICODE.
9548 If TARGET is non-null, try to use it where possible. */
9551 mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
9553 enum machine_mode mode;
9555 mode = insn_data[icode].operand[op].mode;
9556 if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
9557 target = gen_reg_rtx (mode);
9562 /* Expand builtin functions. This is called from TARGET_EXPAND_BUILTIN. */
9565 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9566 enum machine_mode mode ATTRIBUTE_UNUSED,
9567 int ignore ATTRIBUTE_UNUSED)
9569 enum insn_code icode;
9570 enum mips_builtin_type type;
9571 tree fndecl, arglist;
9573 const struct builtin_description *bdesc;
9574 const struct bdesc_map *m;
9576 fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9577 arglist = TREE_OPERAND (exp, 1);
9578 fcode = DECL_FUNCTION_CODE (fndecl);
9581 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
9583 if (fcode < m->size)
9586 icode = bdesc[fcode].icode;
9587 type = bdesc[fcode].builtin_type;
9597 case MIPS_BUILTIN_DIRECT:
9598 return mips_expand_builtin_direct (icode, target, arglist);
9600 case MIPS_BUILTIN_MOVT:
9601 case MIPS_BUILTIN_MOVF:
9602 return mips_expand_builtin_movtf (type, icode, bdesc[fcode].cond,
9605 case MIPS_BUILTIN_CMP_ANY:
9606 case MIPS_BUILTIN_CMP_ALL:
9607 case MIPS_BUILTIN_CMP_UPPER:
9608 case MIPS_BUILTIN_CMP_LOWER:
9609 case MIPS_BUILTIN_CMP_SINGLE:
9610 return mips_expand_builtin_compare (type, icode, bdesc[fcode].cond,
9618 /* Init builtin functions. This is called from TARGET_INIT_BUILTIN. */
9621 mips_init_builtins (void)
9623 const struct builtin_description *d;
9624 const struct bdesc_map *m;
9625 tree types[(int) MIPS_MAX_FTYPE_MAX];
9626 tree V2SF_type_node;
9627 unsigned int offset;
9629 /* We have only builtins for -mpaired-single and -mips3d. */
9630 if (!TARGET_PAIRED_SINGLE_FLOAT)
9633 V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode);
9635 types[MIPS_V2SF_FTYPE_V2SF]
9636 = build_function_type_list (V2SF_type_node, V2SF_type_node, NULL_TREE);
9638 types[MIPS_V2SF_FTYPE_V2SF_V2SF]
9639 = build_function_type_list (V2SF_type_node,
9640 V2SF_type_node, V2SF_type_node, NULL_TREE);
9642 types[MIPS_V2SF_FTYPE_V2SF_V2SF_INT]
9643 = build_function_type_list (V2SF_type_node,
9644 V2SF_type_node, V2SF_type_node,
9645 integer_type_node, NULL_TREE);
9647 types[MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF]
9648 = build_function_type_list (V2SF_type_node,
9649 V2SF_type_node, V2SF_type_node,
9650 V2SF_type_node, V2SF_type_node, NULL_TREE);
9652 types[MIPS_V2SF_FTYPE_SF_SF]
9653 = build_function_type_list (V2SF_type_node,
9654 float_type_node, float_type_node, NULL_TREE);
9656 types[MIPS_INT_FTYPE_V2SF_V2SF]
9657 = build_function_type_list (integer_type_node,
9658 V2SF_type_node, V2SF_type_node, NULL_TREE);
9660 types[MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF]
9661 = build_function_type_list (integer_type_node,
9662 V2SF_type_node, V2SF_type_node,
9663 V2SF_type_node, V2SF_type_node, NULL_TREE);
9665 types[MIPS_INT_FTYPE_SF_SF]
9666 = build_function_type_list (integer_type_node,
9667 float_type_node, float_type_node, NULL_TREE);
9669 types[MIPS_INT_FTYPE_DF_DF]
9670 = build_function_type_list (integer_type_node,
9671 double_type_node, double_type_node, NULL_TREE);
9673 types[MIPS_SF_FTYPE_V2SF]
9674 = build_function_type_list (float_type_node, V2SF_type_node, NULL_TREE);
9676 types[MIPS_SF_FTYPE_SF]
9677 = build_function_type_list (float_type_node,
9678 float_type_node, NULL_TREE);
9680 types[MIPS_SF_FTYPE_SF_SF]
9681 = build_function_type_list (float_type_node,
9682 float_type_node, float_type_node, NULL_TREE);
9684 types[MIPS_DF_FTYPE_DF]
9685 = build_function_type_list (double_type_node,
9686 double_type_node, NULL_TREE);
9688 types[MIPS_DF_FTYPE_DF_DF]
9689 = build_function_type_list (double_type_node,
9690 double_type_node, double_type_node, NULL_TREE);
9692 /* Iterate through all of the bdesc arrays, initializing all of the
9693 builtin functions. */
9696 for (m = bdesc_arrays; m < &bdesc_arrays[ARRAY_SIZE (bdesc_arrays)]; m++)
9698 if (m->proc == PROCESSOR_DEFAULT || (m->proc == mips_arch))
9699 for (d = m->bdesc; d < &m->bdesc[m->size]; d++)
9700 if ((d->target_flags & target_flags) == d->target_flags)
9701 lang_hooks.builtin_function (d->name, types[d->function_type],
9702 d - m->bdesc + offset,
9703 BUILT_IN_MD, NULL, NULL);
9708 /* Expand a MIPS_BUILTIN_DIRECT function. ICODE is the code of the
9709 .md pattern and ARGLIST is the list of function arguments. TARGET,
9710 if nonnull, suggests a good place to put the result. */
9713 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree arglist)
9715 rtx ops[MAX_RECOG_OPERANDS];
9718 target = mips_prepare_builtin_target (icode, 0, target);
9719 for (i = 1; i < insn_data[icode].n_operands; i++)
9720 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
9722 switch (insn_data[icode].n_operands)
9725 emit_insn (GEN_FCN (icode) (target, ops[1]));
9729 emit_insn (GEN_FCN (icode) (target, ops[1], ops[2]));
9733 emit_insn (GEN_FCN (icode) (target, ops[1], ops[2], ops[3]));
9742 /* Expand a __builtin_mips_movt_*_ps() or __builtin_mips_movf_*_ps()
9743 function (TYPE says which). ARGLIST is the list of arguments to the
9744 function, ICODE is the instruction that should be used to compare
9745 the first two arguments, and COND is the condition it should test.
9746 TARGET, if nonnull, suggests a good place to put the result. */
9749 mips_expand_builtin_movtf (enum mips_builtin_type type,
9750 enum insn_code icode, enum mips_fp_condition cond,
9751 rtx target, tree arglist)
9753 rtx cmp_result, op0, op1;
9755 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
9756 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
9757 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
9758 emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
9760 icode = CODE_FOR_mips_cond_move_tf_ps;
9761 target = mips_prepare_builtin_target (icode, 0, target);
9762 if (type == MIPS_BUILTIN_MOVT)
9764 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
9765 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
9769 op0 = mips_prepare_builtin_arg (icode, 1, &arglist);
9770 op1 = mips_prepare_builtin_arg (icode, 2, &arglist);
9772 emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
9776 /* Expand a comparison builtin of type BUILTIN_TYPE. ICODE is the code
9777 of the comparison instruction and COND is the condition it should test.
9778 ARGLIST is the list of function arguments and TARGET, if nonnull,
9779 suggests a good place to put the boolean result. */
9782 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
9783 enum insn_code icode, enum mips_fp_condition cond,
9784 rtx target, tree arglist)
9786 rtx label1, label2, if_then_else;
9787 rtx pat, cmp_result, ops[MAX_RECOG_OPERANDS];
9788 rtx target_if_equal, target_if_unequal;
9791 if (target == 0 || GET_MODE (target) != SImode)
9792 target = gen_reg_rtx (SImode);
9794 /* Prepare the operands to the comparison. */
9795 cmp_result = mips_prepare_builtin_target (icode, 0, 0);
9796 for (i = 1; i < insn_data[icode].n_operands - 1; i++)
9797 ops[i] = mips_prepare_builtin_arg (icode, i, &arglist);
9799 switch (insn_data[icode].n_operands)
9802 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2], GEN_INT (cond));
9806 pat = GEN_FCN (icode) (cmp_result, ops[1], ops[2],
9807 ops[3], ops[4], GEN_INT (cond));
9814 /* If the comparison sets more than one register, we define the result
9815 to be 0 if all registers are false and -1 if all registers are true.
9816 The value of the complete result is indeterminate otherwise. It is
9817 possible to test individual registers using SUBREGs.
9819 Set up CMP_RESULT, CMP_VALUE, TARGET_IF_EQUAL and TARGET_IF_UNEQUAL so
9820 that the result should be TARGET_IF_EQUAL if (EQ CMP_RESULT CMP_VALUE)
9821 and TARGET_IF_UNEQUAL otherwise. */
9822 if (builtin_type == MIPS_BUILTIN_CMP_ALL)
9825 target_if_equal = const1_rtx;
9826 target_if_unequal = const0_rtx;
9831 target_if_equal = const0_rtx;
9832 target_if_unequal = const1_rtx;
9833 if (builtin_type == MIPS_BUILTIN_CMP_UPPER)
9834 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 4);
9835 else if (builtin_type == MIPS_BUILTIN_CMP_LOWER)
9836 cmp_result = simplify_gen_subreg (CCmode, cmp_result, CCV2mode, 0);
9839 /* First assume that CMP_RESULT == CMP_VALUE. */
9840 emit_move_insn (target, target_if_equal);
9842 /* Branch to LABEL1 if CMP_RESULT != CMP_VALUE. */
9844 label1 = gen_label_rtx ();
9845 label2 = gen_label_rtx ();
9847 = gen_rtx_IF_THEN_ELSE (VOIDmode,
9848 gen_rtx_fmt_ee (NE, GET_MODE (cmp_result),
9849 cmp_result, GEN_INT (cmp_value)),
9850 gen_rtx_LABEL_REF (VOIDmode, label1), pc_rtx);
9851 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, if_then_else));
9852 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
9853 gen_rtx_LABEL_REF (VOIDmode, label2)));
9855 emit_label (label1);
9857 /* Fix TARGET for CMP_RESULT != CMP_VALUE. */
9858 emit_move_insn (target, target_if_unequal);
9859 emit_label (label2);
9864 #include "gt-mips.h"