1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky, lich@inria.inria.fr.
5 Changes by Michael Meissner, meissner@osf.org.
6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 Brendan Eich, brendan@microunity.com.
9 This file is part of GCC.
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
28 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-attr.h"
53 #include "target-def.h"
54 #include "integrate.h"
55 #include "langhooks.h"
56 #include "cfglayout.h"
57 #include "sched-int.h"
58 #include "tree-gimple.h"
60 /* Enumeration for all of the relational tests, so that we can build
61 arrays indexed by the test type, and not worry about the order
78 /* True if X is an unspec wrapper around a SYMBOL_REF or LABEL_REF. */
79 #define UNSPEC_ADDRESS_P(X) \
80 (GET_CODE (X) == UNSPEC \
81 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
82 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
84 /* Extract the symbol or label from UNSPEC wrapper X. */
85 #define UNSPEC_ADDRESS(X) \
88 /* Extract the symbol type from UNSPEC wrapper X. */
89 #define UNSPEC_ADDRESS_TYPE(X) \
90 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
92 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
93 to initialize the mips16 gp pseudo register. */
94 #define CONST_GP_P(X) \
95 (GET_CODE (X) == CONST \
96 && GET_CODE (XEXP (X, 0)) == UNSPEC \
97 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
99 /* The maximum distance between the top of the stack frame and the
100 value $sp has when we save & restore registers.
102 Use a maximum gap of 0x100 in the mips16 case. We can then use
103 unextended instructions to save and restore registers, and to
104 allocate and deallocate the top part of the frame.
106 The value in the !mips16 case must be a SMALL_OPERAND and must
107 preserve the maximum stack alignment. It could really be 0x7ff0,
108 but SGI's assemblers implement daddiu $sp,$sp,-0x7ff0 as a
109 multi-instruction addu sequence. Use 0x7fe0 to work around this. */
110 #define MIPS_MAX_FIRST_STACK_STEP (TARGET_MIPS16 ? 0x100 : 0x7fe0)
112 /* True if INSN is a mips.md pattern or asm statement. */
113 #define USEFUL_INSN_P(INSN) \
115 && GET_CODE (PATTERN (INSN)) != USE \
116 && GET_CODE (PATTERN (INSN)) != CLOBBER \
117 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
118 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
120 /* If INSN is a delayed branch sequence, return the first instruction
121 in the sequence, otherwise return INSN itself. */
122 #define SEQ_BEGIN(INSN) \
123 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
124 ? XVECEXP (PATTERN (INSN), 0, 0) \
127 /* Likewise for the last instruction in a delayed branch sequence. */
128 #define SEQ_END(INSN) \
129 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
130 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
133 /* Execute the following loop body with SUBINSN set to each instruction
134 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
135 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
136 for ((SUBINSN) = SEQ_BEGIN (INSN); \
137 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
138 (SUBINSN) = NEXT_INSN (SUBINSN))
140 /* Classifies an address.
143 A natural register + offset address. The register satisfies
144 mips_valid_base_register_p and the offset is a const_arith_operand.
147 A LO_SUM rtx. The first operand is a valid base register and
148 the second operand is a symbolic address.
151 A signed 16-bit constant address.
154 A constant symbolic address (equivalent to CONSTANT_SYMBOLIC). */
155 enum mips_address_type {
162 /* A function to save or store a register. The first argument is the
163 register and the second is the stack slot. */
164 typedef void (*mips_save_restore_fn) (rtx, rtx);
166 struct mips16_constant;
167 struct mips_arg_info;
168 struct mips_address_info;
169 struct mips_integer_op;
172 static enum mips_symbol_type mips_classify_symbol (rtx);
173 static void mips_split_const (rtx, rtx *, HOST_WIDE_INT *);
174 static bool mips_offset_within_object_p (rtx, HOST_WIDE_INT);
175 static bool mips_symbolic_constant_p (rtx, enum mips_symbol_type *);
176 static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
177 static bool mips_symbolic_address_p (enum mips_symbol_type, enum machine_mode);
178 static bool mips_classify_address (struct mips_address_info *, rtx,
179 enum machine_mode, int);
180 static int mips_symbol_insns (enum mips_symbol_type);
181 static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
182 static rtx mips_force_temporary (rtx, rtx);
183 static rtx mips_split_symbol (rtx, rtx);
184 static rtx mips_unspec_offset_high (rtx, rtx, rtx, enum mips_symbol_type);
185 static rtx mips_add_offset (rtx, HOST_WIDE_INT);
186 static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
187 static unsigned int mips_build_lower (struct mips_integer_op *,
188 unsigned HOST_WIDE_INT);
189 static unsigned int mips_build_integer (struct mips_integer_op *,
190 unsigned HOST_WIDE_INT);
191 static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
192 static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
193 static int m16_check_op (rtx, int, int, int);
194 static bool mips_rtx_costs (rtx, int, int, int *);
195 static int mips_address_cost (rtx);
196 static enum internal_test map_test_to_internal_test (enum rtx_code);
197 static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
199 static void mips_load_call_address (rtx, rtx, int);
200 static bool mips_function_ok_for_sibcall (tree, tree);
201 static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
202 static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
203 static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
204 static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
205 tree, int, struct mips_arg_info *);
206 static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
207 static void mips_set_architecture (const struct mips_cpu_info *);
208 static void mips_set_tune (const struct mips_cpu_info *);
209 static struct machine_function *mips_init_machine_status (void);
210 static void print_operand_reloc (FILE *, rtx, const char **);
211 static bool mips_assemble_integer (rtx, unsigned int, int);
212 static void mips_file_start (void);
213 static void mips_file_end (void);
214 static bool mips_rewrite_small_data_p (rtx);
215 static int small_data_pattern_1 (rtx *, void *);
216 static int mips_rewrite_small_data_1 (rtx *, void *);
217 static bool mips_function_has_gp_insn (void);
218 static unsigned int mips_global_pointer (void);
219 static bool mips_save_reg_p (unsigned int);
220 static void mips_save_restore_reg (enum machine_mode, int, HOST_WIDE_INT,
221 mips_save_restore_fn);
222 static void mips_for_each_saved_reg (HOST_WIDE_INT, mips_save_restore_fn);
223 static void mips_output_cplocal (void);
224 static void mips_emit_loadgp (void);
225 static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
226 static void mips_set_frame_expr (rtx);
227 static rtx mips_frame_set (rtx, rtx);
228 static void mips_save_reg (rtx, rtx);
229 static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
230 static void mips_restore_reg (rtx, rtx);
231 static void mips_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
232 HOST_WIDE_INT, tree);
233 static int symbolic_expression_p (rtx);
234 static void mips_select_rtx_section (enum machine_mode, rtx,
235 unsigned HOST_WIDE_INT);
236 static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
238 static bool mips_in_small_data_p (tree);
239 static int mips_fpr_return_fields (tree, tree *);
240 static bool mips_return_in_msb (tree);
241 static rtx mips_return_fpr_pair (enum machine_mode mode,
242 enum machine_mode mode1, HOST_WIDE_INT,
243 enum machine_mode mode2, HOST_WIDE_INT);
244 static rtx mips16_gp_pseudo_reg (void);
245 static void mips16_fp_args (FILE *, int, int);
246 static void build_mips16_function_stub (FILE *);
247 static rtx dump_constants_1 (enum machine_mode, rtx, rtx);
248 static void dump_constants (struct mips16_constant *, rtx);
249 static int mips16_insn_length (rtx);
250 static int mips16_rewrite_pool_refs (rtx *, void *);
251 static void mips16_lay_out_constants (void);
252 static void mips_sim_reset (struct mips_sim *);
253 static void mips_sim_init (struct mips_sim *, state_t);
254 static void mips_sim_next_cycle (struct mips_sim *);
255 static void mips_sim_wait_reg (struct mips_sim *, rtx, rtx);
256 static int mips_sim_wait_regs_2 (rtx *, void *);
257 static void mips_sim_wait_regs_1 (rtx *, void *);
258 static void mips_sim_wait_regs (struct mips_sim *, rtx);
259 static void mips_sim_wait_units (struct mips_sim *, rtx);
260 static void mips_sim_wait_insn (struct mips_sim *, rtx);
261 static void mips_sim_record_set (rtx, rtx, void *);
262 static void mips_sim_issue_insn (struct mips_sim *, rtx);
263 static void mips_sim_issue_nop (struct mips_sim *);
264 static void mips_sim_finish_insn (struct mips_sim *, rtx);
265 static void vr4130_avoid_branch_rt_conflict (rtx);
266 static void vr4130_align_insns (void);
267 static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
268 static void mips_avoid_hazards (void);
269 static void mips_reorg (void);
270 static bool mips_strict_matching_cpu_name_p (const char *, const char *);
271 static bool mips_matching_cpu_name_p (const char *, const char *);
272 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
273 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
274 static bool mips_return_in_memory (tree, tree);
275 static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
276 static void mips_macc_chains_record (rtx);
277 static void mips_macc_chains_reorder (rtx *, int);
278 static void vr4130_true_reg_dependence_p_1 (rtx, rtx, void *);
279 static bool vr4130_true_reg_dependence_p (rtx);
280 static bool vr4130_swap_insns_p (rtx, rtx);
281 static void vr4130_reorder (rtx *, int);
282 static void mips_promote_ready (rtx *, int, int);
283 static int mips_sched_reorder (FILE *, int, rtx *, int *, int);
284 static int mips_variable_issue (FILE *, int, rtx, int);
285 static int mips_adjust_cost (rtx, rtx, rtx, int);
286 static int mips_issue_rate (void);
287 static int mips_multipass_dfa_lookahead (void);
288 static void mips_init_libfuncs (void);
289 static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
291 static tree mips_build_builtin_va_list (void);
292 static tree mips_gimplify_va_arg_expr (tree, tree, tree *, tree *);
295 static void irix_asm_named_section_1 (const char *, unsigned int,
297 static void irix_asm_named_section (const char *, unsigned int);
298 static int irix_section_align_entry_eq (const void *, const void *);
299 static hashval_t irix_section_align_entry_hash (const void *);
300 static void irix_file_start (void);
301 static int irix_section_align_1 (void **, void *);
302 static void copy_file_data (FILE *, FILE *);
303 static void irix_file_end (void);
304 static unsigned int irix_section_type_flags (tree, const char *, int);
307 /* Structure to be filled in by compute_frame_size with register
308 save masks, and offsets for the current function. */
310 struct mips_frame_info GTY(())
312 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
313 HOST_WIDE_INT var_size; /* # bytes that variables take up */
314 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
315 HOST_WIDE_INT cprestore_size; /* # bytes that the .cprestore slot takes up */
316 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
317 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
318 unsigned int mask; /* mask of saved gp registers */
319 unsigned int fmask; /* mask of saved fp registers */
320 HOST_WIDE_INT gp_save_offset; /* offset from vfp to store gp registers */
321 HOST_WIDE_INT fp_save_offset; /* offset from vfp to store fp registers */
322 HOST_WIDE_INT gp_sp_offset; /* offset from new sp to store gp registers */
323 HOST_WIDE_INT fp_sp_offset; /* offset from new sp to store fp registers */
324 bool initialized; /* true if frame size already calculated */
325 int num_gp; /* number of gp registers saved */
326 int num_fp; /* number of fp registers saved */
329 struct machine_function GTY(()) {
330 /* Pseudo-reg holding the value of $28 in a mips16 function which
331 refers to GP relative global variables. */
332 rtx mips16_gp_pseudo_rtx;
334 /* Current frame information, calculated by compute_frame_size. */
335 struct mips_frame_info frame;
337 /* The register to use as the global pointer within this function. */
338 unsigned int global_pointer;
340 /* True if mips_adjust_insn_length should ignore an instruction's
342 bool ignore_hazard_length_p;
344 /* True if the whole function is suitable for .set noreorder and
346 bool all_noreorder_p;
348 /* True if the function is known to have an instruction that needs $gp. */
352 /* Information about a single argument. */
355 /* True if the argument is passed in a floating-point register, or
356 would have been if we hadn't run out of registers. */
359 /* The argument's size, in bytes. */
360 unsigned int num_bytes;
362 /* The number of words passed in registers, rounded up. */
363 unsigned int reg_words;
365 /* The offset of the first register from GP_ARG_FIRST or FP_ARG_FIRST,
366 or MAX_ARGS_IN_REGISTERS if the argument is passed entirely
368 unsigned int reg_offset;
370 /* The number of words that must be passed on the stack, rounded up. */
371 unsigned int stack_words;
373 /* The offset from the start of the stack overflow area of the argument's
374 first stack word. Only meaningful when STACK_WORDS is nonzero. */
375 unsigned int stack_offset;
379 /* Information about an address described by mips_address_type.
385 REG is the base register and OFFSET is the constant offset.
388 REG is the register that contains the high part of the address,
389 OFFSET is the symbolic address being referenced and SYMBOL_TYPE
390 is the type of OFFSET's symbol.
393 SYMBOL_TYPE is the type of symbol being referenced. */
395 struct mips_address_info
397 enum mips_address_type type;
400 enum mips_symbol_type symbol_type;
404 /* One stage in a constant building sequence. These sequences have
408 A = A CODE[1] VALUE[1]
409 A = A CODE[2] VALUE[2]
412 where A is an accumulator, each CODE[i] is a binary rtl operation
413 and each VALUE[i] is a constant integer. */
414 struct mips_integer_op {
416 unsigned HOST_WIDE_INT value;
420 /* The largest number of operations needed to load an integer constant.
421 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
422 When the lowest bit is clear, we can try, but reject a sequence with
423 an extra SLL at the end. */
424 #define MIPS_MAX_INTEGER_OPS 7
427 /* Global variables for machine-dependent things. */
429 /* Threshold for data being put into the small data/bss area, instead
430 of the normal data area. */
431 int mips_section_threshold = -1;
433 /* Count the number of .file directives, so that .loc is up to date. */
434 int num_source_filenames = 0;
436 /* Count the number of sdb related labels are generated (to find block
437 start and end boundaries). */
438 int sdb_label_count = 0;
440 /* Next label # for each statement for Silicon Graphics IRIS systems. */
443 /* Linked list of all externals that are to be emitted when optimizing
444 for the global pointer if they haven't been declared by the end of
445 the program with an appropriate .comm or initialization. */
447 struct extern_list GTY (())
449 struct extern_list *next; /* next external */
450 const char *name; /* name of the external */
451 int size; /* size in bytes */
454 static GTY (()) struct extern_list *extern_head = 0;
456 /* Name of the file containing the current function. */
457 const char *current_function_file = "";
459 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
465 /* The next branch instruction is a branch likely, not branch normal. */
466 int mips_branch_likely;
468 /* Cached operands, and operator to compare for use in set/branch/trap
469 on condition codes. */
472 /* what type of branch to use */
473 enum cmp_type branch_type;
475 /* The target cpu for code generation. */
476 enum processor_type mips_arch;
477 const struct mips_cpu_info *mips_arch_info;
479 /* The target cpu for optimization and scheduling. */
480 enum processor_type mips_tune;
481 const struct mips_cpu_info *mips_tune_info;
483 /* Which instruction set architecture to use. */
486 /* Which ABI to use. */
489 /* Strings to hold which cpu and instruction set architecture to use. */
490 const char *mips_arch_string; /* for -march=<xxx> */
491 const char *mips_tune_string; /* for -mtune=<xxx> */
492 const char *mips_isa_string; /* for -mips{1,2,3,4} */
493 const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
495 /* Whether we are generating mips16 hard float code. In mips16 mode
496 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
497 -msoft-float was not specified by the user, which means that we
498 should arrange to call mips32 hard floating point code. */
499 int mips16_hard_float;
501 const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
503 /* If TRUE, we split addresses into their high and low parts in the RTL. */
504 int mips_split_addresses;
506 /* Mode used for saving/restoring general purpose registers. */
507 static enum machine_mode gpr_mode;
509 /* Array giving truth value on whether or not a given hard register
510 can support a given mode. */
511 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
513 /* List of all MIPS punctuation characters used by print_operand. */
514 char mips_print_operand_punct[256];
516 /* Map GCC register number to debugger register number. */
517 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
519 /* A copy of the original flag_delayed_branch: see override_options. */
520 static int mips_flag_delayed_branch;
522 static GTY (()) int mips_output_filename_first_time = 1;
524 /* mips_split_p[X] is true if symbols of type X can be split by
525 mips_split_symbol(). */
526 static bool mips_split_p[NUM_SYMBOL_TYPES];
528 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
529 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
530 if they are matched by a special .md file pattern. */
531 static const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
533 /* Likewise for HIGHs. */
534 static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
536 /* Map hard register number to register class */
537 const enum reg_class mips_regno_to_class[] =
539 LEA_REGS, LEA_REGS, M16_NA_REGS, M16_NA_REGS,
540 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
541 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
542 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
543 M16_NA_REGS, M16_NA_REGS, LEA_REGS, LEA_REGS,
544 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
545 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
546 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
547 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
548 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
549 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
550 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
551 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
552 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
553 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
554 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
555 HI_REG, LO_REG, NO_REGS, ST_REGS,
556 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
557 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
558 NO_REGS, ALL_REGS, ALL_REGS, NO_REGS,
559 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
560 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
561 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
562 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
563 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
564 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
565 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
566 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
567 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
568 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
569 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
570 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
571 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
572 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
573 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
574 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
575 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
576 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
577 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
578 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
579 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
580 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
581 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
582 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS
585 /* Map register constraint character to register class. */
586 enum reg_class mips_char_to_class[256];
588 /* A table describing all the processors gcc knows about. Names are
589 matched in the order listed. The first mention of an ISA level is
590 taken as the canonical name for that ISA.
592 To ease comparison, please keep this table in the same order as
593 gas's mips_cpu_info_table[]. */
594 const struct mips_cpu_info mips_cpu_info_table[] = {
595 /* Entries for generic ISAs */
596 { "mips1", PROCESSOR_R3000, 1 },
597 { "mips2", PROCESSOR_R6000, 2 },
598 { "mips3", PROCESSOR_R4000, 3 },
599 { "mips4", PROCESSOR_R8000, 4 },
600 { "mips32", PROCESSOR_4KC, 32 },
601 { "mips32r2", PROCESSOR_M4K, 33 },
602 { "mips64", PROCESSOR_5KC, 64 },
605 { "r3000", PROCESSOR_R3000, 1 },
606 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */
607 { "r3900", PROCESSOR_R3900, 1 },
610 { "r6000", PROCESSOR_R6000, 2 },
613 { "r4000", PROCESSOR_R4000, 3 },
614 { "vr4100", PROCESSOR_R4100, 3 },
615 { "vr4111", PROCESSOR_R4111, 3 },
616 { "vr4120", PROCESSOR_R4120, 3 },
617 { "vr4130", PROCESSOR_R4130, 3 },
618 { "vr4300", PROCESSOR_R4300, 3 },
619 { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */
620 { "r4600", PROCESSOR_R4600, 3 },
621 { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */
622 { "r4650", PROCESSOR_R4650, 3 },
625 { "r8000", PROCESSOR_R8000, 4 },
626 { "vr5000", PROCESSOR_R5000, 4 },
627 { "vr5400", PROCESSOR_R5400, 4 },
628 { "vr5500", PROCESSOR_R5500, 4 },
629 { "rm7000", PROCESSOR_R7000, 4 },
630 { "rm9000", PROCESSOR_R9000, 4 },
633 { "4kc", PROCESSOR_4KC, 32 },
634 { "4kp", PROCESSOR_4KC, 32 }, /* = 4kc */
636 /* MIPS32 Release 2 */
637 { "m4k", PROCESSOR_M4K, 33 },
640 { "5kc", PROCESSOR_5KC, 64 },
641 { "20kc", PROCESSOR_20KC, 64 },
642 { "sb1", PROCESSOR_SB1, 64 },
643 { "sr71000", PROCESSOR_SR71000, 64 },
649 /* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT. */
650 #ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT
651 #define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0
654 /* Initialize the GCC target structure. */
655 #undef TARGET_ASM_ALIGNED_HI_OP
656 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
657 #undef TARGET_ASM_ALIGNED_SI_OP
658 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
659 #undef TARGET_ASM_INTEGER
660 #define TARGET_ASM_INTEGER mips_assemble_integer
662 #undef TARGET_ASM_FUNCTION_PROLOGUE
663 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
664 #undef TARGET_ASM_FUNCTION_EPILOGUE
665 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
666 #undef TARGET_ASM_SELECT_RTX_SECTION
667 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
669 #undef TARGET_SCHED_REORDER
670 #define TARGET_SCHED_REORDER mips_sched_reorder
671 #undef TARGET_SCHED_VARIABLE_ISSUE
672 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
673 #undef TARGET_SCHED_ADJUST_COST
674 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
675 #undef TARGET_SCHED_ISSUE_RATE
676 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
677 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
678 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
679 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
680 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
681 mips_multipass_dfa_lookahead
683 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
684 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
686 #undef TARGET_VALID_POINTER_MODE
687 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
688 #undef TARGET_RTX_COSTS
689 #define TARGET_RTX_COSTS mips_rtx_costs
690 #undef TARGET_ADDRESS_COST
691 #define TARGET_ADDRESS_COST mips_address_cost
693 #undef TARGET_IN_SMALL_DATA_P
694 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
696 #undef TARGET_MACHINE_DEPENDENT_REORG
697 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
699 #undef TARGET_ASM_FILE_START
700 #undef TARGET_ASM_FILE_END
702 #define TARGET_ASM_FILE_START irix_file_start
703 #define TARGET_ASM_FILE_END irix_file_end
705 #define TARGET_ASM_FILE_START mips_file_start
706 #define TARGET_ASM_FILE_END mips_file_end
708 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
709 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
712 #undef TARGET_SECTION_TYPE_FLAGS
713 #define TARGET_SECTION_TYPE_FLAGS irix_section_type_flags
716 #undef TARGET_INIT_LIBFUNCS
717 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
719 #undef TARGET_BUILD_BUILTIN_VA_LIST
720 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
721 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
722 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
724 #undef TARGET_PROMOTE_FUNCTION_ARGS
725 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
726 #undef TARGET_PROMOTE_FUNCTION_RETURN
727 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
728 #undef TARGET_PROMOTE_PROTOTYPES
729 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
731 #undef TARGET_RETURN_IN_MEMORY
732 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
733 #undef TARGET_RETURN_IN_MSB
734 #define TARGET_RETURN_IN_MSB mips_return_in_msb
736 #undef TARGET_ASM_OUTPUT_MI_THUNK
737 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
738 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
739 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
741 #undef TARGET_SETUP_INCOMING_VARARGS
742 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
743 #undef TARGET_STRICT_ARGUMENT_NAMING
744 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
745 #undef TARGET_MUST_PASS_IN_STACK
746 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
748 struct gcc_target targetm = TARGET_INITIALIZER;
750 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF. */
752 static enum mips_symbol_type
753 mips_classify_symbol (rtx x)
755 if (GET_CODE (x) == LABEL_REF)
758 return SYMBOL_CONSTANT_POOL;
760 return SYMBOL_GOT_LOCAL;
761 return SYMBOL_GENERAL;
764 if (GET_CODE (x) != SYMBOL_REF)
767 if (CONSTANT_POOL_ADDRESS_P (x))
770 return SYMBOL_CONSTANT_POOL;
773 return SYMBOL_GOT_LOCAL;
775 if (GET_MODE_SIZE (get_pool_mode (x)) <= mips_section_threshold)
776 return SYMBOL_SMALL_DATA;
778 return SYMBOL_GENERAL;
781 if (SYMBOL_REF_SMALL_P (x))
782 return SYMBOL_SMALL_DATA;
786 if (SYMBOL_REF_DECL (x) == 0)
787 return SYMBOL_REF_LOCAL_P (x) ? SYMBOL_GOT_LOCAL : SYMBOL_GOT_GLOBAL;
789 /* There are three cases to consider:
791 - o32 PIC (either with or without explicit relocs)
792 - n32/n64 PIC without explicit relocs
793 - n32/n64 PIC with explicit relocs
795 In the first case, both local and global accesses will use an
796 R_MIPS_GOT16 relocation. We must correctly predict which of
797 the two semantics (local or global) the assembler and linker
798 will apply. The choice doesn't depend on the symbol's
799 visibility, so we deliberately ignore decl_visibility and
802 In the second case, the assembler will not use R_MIPS_GOT16
803 relocations, but it chooses between local and global accesses
804 in the same way as for o32 PIC.
806 In the third case we have more freedom since both forms of
807 access will work for any kind of symbol. However, there seems
808 little point in doing things differently. */
809 if (DECL_P (SYMBOL_REF_DECL (x)) && TREE_PUBLIC (SYMBOL_REF_DECL (x)))
810 return SYMBOL_GOT_GLOBAL;
812 return SYMBOL_GOT_LOCAL;
815 return SYMBOL_GENERAL;
819 /* Split X into a base and a constant offset, storing them in *BASE
820 and *OFFSET respectively. */
823 mips_split_const (rtx x, rtx *base, HOST_WIDE_INT *offset)
827 if (GET_CODE (x) == CONST)
830 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
832 *offset += INTVAL (XEXP (x, 1));
839 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
840 to the same object as SYMBOL. */
843 mips_offset_within_object_p (rtx symbol, HOST_WIDE_INT offset)
845 if (GET_CODE (symbol) != SYMBOL_REF)
848 if (CONSTANT_POOL_ADDRESS_P (symbol)
850 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol)))
853 if (SYMBOL_REF_DECL (symbol) != 0
855 && offset < int_size_in_bytes (TREE_TYPE (SYMBOL_REF_DECL (symbol))))
862 /* Return true if X is a symbolic constant that can be calculated in
863 the same way as a bare symbol. If it is, store the type of the
864 symbol in *SYMBOL_TYPE. */
867 mips_symbolic_constant_p (rtx x, enum mips_symbol_type *symbol_type)
869 HOST_WIDE_INT offset;
871 mips_split_const (x, &x, &offset);
872 if (UNSPEC_ADDRESS_P (x))
873 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
874 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
875 *symbol_type = mips_classify_symbol (x);
882 /* Check whether a nonzero offset is valid for the underlying
884 switch (*symbol_type)
890 /* If the target has 64-bit pointers and the object file only
891 supports 32-bit symbols, the values of those symbols will be
892 sign-extended. In this case we can't allow an arbitrary offset
893 in case the 32-bit value X + OFFSET has a different sign from X. */
894 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
895 return mips_offset_within_object_p (x, offset);
897 /* In other cases the relocations can handle any offset. */
900 case SYMBOL_CONSTANT_POOL:
901 /* Allow constant pool references to be converted to LABEL+CONSTANT.
902 In this case, we no longer have access to the underlying constant,
903 but the original symbol-based access was known to be valid. */
904 if (GET_CODE (x) == LABEL_REF)
909 case SYMBOL_SMALL_DATA:
910 /* Make sure that the offset refers to something within the
911 underlying object. This should guarantee that the final
912 PC- or GP-relative offset is within the 16-bit limit. */
913 return mips_offset_within_object_p (x, offset);
915 case SYMBOL_GOT_LOCAL:
916 case SYMBOL_GOTOFF_PAGE:
917 /* The linker should provide enough local GOT entries for a
918 16-bit offset. Larger offsets may lead to GOT overflow. */
919 return SMALL_OPERAND (offset);
921 case SYMBOL_GOT_GLOBAL:
922 case SYMBOL_GOTOFF_GLOBAL:
923 case SYMBOL_GOTOFF_CALL:
924 case SYMBOL_GOTOFF_LOADGP:
931 /* This function is used to implement REG_MODE_OK_FOR_BASE_P. */
934 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, int strict)
936 if (regno >= FIRST_PSEUDO_REGISTER)
940 regno = reg_renumber[regno];
943 /* These fake registers will be eliminated to either the stack or
944 hard frame pointer, both of which are usually valid base registers.
945 Reload deals with the cases where the eliminated form isn't valid. */
946 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
949 /* In mips16 mode, the stack pointer can only address word and doubleword
950 values, nothing smaller. There are two problems here:
952 (a) Instantiating virtual registers can introduce new uses of the
953 stack pointer. If these virtual registers are valid addresses,
954 the stack pointer should be too.
956 (b) Most uses of the stack pointer are not made explicit until
957 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
958 We don't know until that stage whether we'll be eliminating to the
959 stack pointer (which needs the restriction) or the hard frame
960 pointer (which doesn't).
962 All in all, it seems more consistent to only enforce this restriction
963 during and after reload. */
964 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
965 return !strict || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
967 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
971 /* Return true if X is a valid base register for the given mode.
972 Allow only hard registers if STRICT. */
975 mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
977 if (!strict && GET_CODE (x) == SUBREG)
980 return (GET_CODE (x) == REG
981 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict));
985 /* Return true if symbols of type SYMBOL_TYPE can directly address a value
986 with mode MODE. This is used for both symbolic and LO_SUM addresses. */
989 mips_symbolic_address_p (enum mips_symbol_type symbol_type,
990 enum machine_mode mode)
995 return !TARGET_MIPS16;
997 case SYMBOL_SMALL_DATA:
1000 case SYMBOL_CONSTANT_POOL:
1001 /* PC-relative addressing is only available for lw and ld. */
1002 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
1004 case SYMBOL_GOT_LOCAL:
1007 case SYMBOL_GOT_GLOBAL:
1008 /* The address will have to be loaded from the GOT first. */
1011 case SYMBOL_GOTOFF_PAGE:
1012 case SYMBOL_GOTOFF_GLOBAL:
1013 case SYMBOL_GOTOFF_CALL:
1014 case SYMBOL_GOTOFF_LOADGP:
1015 case SYMBOL_64_HIGH:
1024 /* Return true if X is a valid address for machine mode MODE. If it is,
1025 fill in INFO appropriately. STRICT is true if we should only accept
1026 hard base registers. */
1029 mips_classify_address (struct mips_address_info *info, rtx x,
1030 enum machine_mode mode, int strict)
1032 switch (GET_CODE (x))
1036 info->type = ADDRESS_REG;
1038 info->offset = const0_rtx;
1039 return mips_valid_base_register_p (info->reg, mode, strict);
1042 info->type = ADDRESS_REG;
1043 info->reg = XEXP (x, 0);
1044 info->offset = XEXP (x, 1);
1045 return (mips_valid_base_register_p (info->reg, mode, strict)
1046 && const_arith_operand (info->offset, VOIDmode));
1049 info->type = ADDRESS_LO_SUM;
1050 info->reg = XEXP (x, 0);
1051 info->offset = XEXP (x, 1);
1052 return (mips_valid_base_register_p (info->reg, mode, strict)
1053 && mips_symbolic_constant_p (info->offset, &info->symbol_type)
1054 && mips_symbolic_address_p (info->symbol_type, mode)
1055 && mips_lo_relocs[info->symbol_type] != 0);
1058 /* Small-integer addresses don't occur very often, but they
1059 are legitimate if $0 is a valid base register. */
1060 info->type = ADDRESS_CONST_INT;
1061 return !TARGET_MIPS16 && SMALL_INT (x);
1066 info->type = ADDRESS_SYMBOLIC;
1067 return (mips_symbolic_constant_p (x, &info->symbol_type)
1068 && mips_symbolic_address_p (info->symbol_type, mode)
1069 && !mips_split_p[info->symbol_type]);
1076 /* Return the number of instructions needed to load a symbol of the
1077 given type into a register. If valid in an address, the same number
1078 of instructions are needed for loads and stores. Treat extended
1079 mips16 instructions as two instructions. */
1082 mips_symbol_insns (enum mips_symbol_type type)
1086 case SYMBOL_GENERAL:
1087 /* In mips16 code, general symbols must be fetched from the
1092 /* When using 64-bit symbols, we need 5 preparatory instructions,
1095 lui $at,%highest(symbol)
1096 daddiu $at,$at,%higher(symbol)
1098 daddiu $at,$at,%hi(symbol)
1101 The final address is then $at + %lo(symbol). With 32-bit
1102 symbols we just need a preparatory lui. */
1103 return (ABI_HAS_64BIT_SYMBOLS ? 6 : 2);
1105 case SYMBOL_SMALL_DATA:
1108 case SYMBOL_CONSTANT_POOL:
1109 /* This case is for mips16 only. Assume we'll need an
1110 extended instruction. */
1113 case SYMBOL_GOT_LOCAL:
1114 case SYMBOL_GOT_GLOBAL:
1115 /* Unless -funit-at-a-time is in effect, we can't be sure whether
1116 the local/global classification is accurate. See override_options
1119 The worst cases are:
1121 (1) For local symbols when generating o32 or o64 code. The assembler
1127 ...and the final address will be $at + %lo(symbol).
1129 (2) For global symbols when -mxgot. The assembler will use:
1131 lui $at,%got_hi(symbol)
1134 ...and the final address will be $at + %got_lo(symbol). */
1137 case SYMBOL_GOTOFF_PAGE:
1138 case SYMBOL_GOTOFF_GLOBAL:
1139 case SYMBOL_GOTOFF_CALL:
1140 case SYMBOL_GOTOFF_LOADGP:
1141 case SYMBOL_64_HIGH:
1144 /* Check whether the offset is a 16- or 32-bit value. */
1145 return mips_split_p[type] ? 2 : 1;
1151 /* Return true if a value at OFFSET bytes from BASE can be accessed
1152 using an unextended mips16 instruction. MODE is the mode of the
1155 Usually the offset in an unextended instruction is a 5-bit field.
1156 The offset is unsigned and shifted left once for HIs, twice
1157 for SIs, and so on. An exception is SImode accesses off the
1158 stack pointer, which have an 8-bit immediate field. */
1161 mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
1164 && GET_CODE (offset) == CONST_INT
1165 && INTVAL (offset) >= 0
1166 && (INTVAL (offset) & (GET_MODE_SIZE (mode) - 1)) == 0)
1168 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
1169 return INTVAL (offset) < 256 * GET_MODE_SIZE (mode);
1170 return INTVAL (offset) < 32 * GET_MODE_SIZE (mode);
1176 /* Return the number of instructions needed to load or store a value
1177 of mode MODE at X. Return 0 if X isn't valid for MODE.
1179 For mips16 code, count extended instructions as two instructions. */
1182 mips_address_insns (rtx x, enum machine_mode mode)
1184 struct mips_address_info addr;
1187 if (mode == BLKmode)
1188 /* BLKmode is used for single unaligned loads and stores. */
1191 /* Each word of a multi-word value will be accessed individually. */
1192 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1194 if (mips_classify_address (&addr, x, mode, false))
1199 && !mips16_unextended_reference_p (mode, addr.reg, addr.offset))
1203 case ADDRESS_LO_SUM:
1204 return (TARGET_MIPS16 ? factor * 2 : factor);
1206 case ADDRESS_CONST_INT:
1209 case ADDRESS_SYMBOLIC:
1210 return factor * mips_symbol_insns (addr.symbol_type);
1216 /* Likewise for constant X. */
1219 mips_const_insns (rtx x)
1221 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1222 enum mips_symbol_type symbol_type;
1223 HOST_WIDE_INT offset;
1225 switch (GET_CODE (x))
1229 || !mips_symbolic_constant_p (XEXP (x, 0), &symbol_type)
1230 || !mips_split_p[symbol_type])
1237 /* Unsigned 8-bit constants can be loaded using an unextended
1238 LI instruction. Unsigned 16-bit constants can be loaded
1239 using an extended LI. Negative constants must be loaded
1240 using LI and then negated. */
1241 return (INTVAL (x) >= 0 && INTVAL (x) < 256 ? 1
1242 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
1243 : INTVAL (x) > -256 && INTVAL (x) < 0 ? 2
1244 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
1247 return mips_build_integer (codes, INTVAL (x));
1250 return (!TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0);
1256 /* See if we can refer to X directly. */
1257 if (mips_symbolic_constant_p (x, &symbol_type))
1258 return mips_symbol_insns (symbol_type);
1260 /* Otherwise try splitting the constant into a base and offset.
1261 16-bit offsets can be added using an extra addiu. Larger offsets
1262 must be calculated separately and then added to the base. */
1263 mips_split_const (x, &x, &offset);
1266 int n = mips_const_insns (x);
1269 if (SMALL_OPERAND (offset))
1272 return n + 1 + mips_build_integer (codes, offset);
1279 return mips_symbol_insns (mips_classify_symbol (x));
1287 /* Return the number of instructions needed for memory reference X.
1288 Count extended mips16 instructions as two instructions. */
1291 mips_fetch_insns (rtx x)
1293 if (GET_CODE (x) != MEM)
1296 return mips_address_insns (XEXP (x, 0), GET_MODE (x));
1300 /* Return the number of instructions needed for an integer division. */
1303 mips_idiv_insns (void)
1308 if (TARGET_CHECK_ZERO_DIV)
1310 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
1316 /* Return truth value of whether OP can be used as an operands
1317 where a register or 16 bit unsigned integer is needed. */
1320 uns_arith_operand (rtx op, enum machine_mode mode)
1322 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
1325 return register_operand (op, mode);
1329 /* True if OP can be treated as a signed 16-bit constant. */
1332 const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1334 return GET_CODE (op) == CONST_INT && SMALL_INT (op);
1338 /* Return true if OP is a register operand or a signed 16-bit constant. */
1341 arith_operand (rtx op, enum machine_mode mode)
1343 return const_arith_operand (op, mode) || register_operand (op, mode);
1346 /* Return truth value of whether OP is an integer which fits in 16 bits. */
1349 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1351 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1354 /* Return truth value of whether OP is a register or the constant 0.
1355 Do not accept 0 in mips16 mode since $0 is not one of the core 8
1359 reg_or_0_operand (rtx op, enum machine_mode mode)
1361 switch (GET_CODE (op))
1366 return INTVAL (op) == 0;
1371 return op == CONST0_RTX (mode);
1374 return register_operand (op, mode);
1378 /* Accept a register or the floating point constant 1 in the
1379 appropriate mode. */
1382 reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
1384 return const_float_1_operand (op, mode) || register_operand (op, mode);
1387 /* Accept the floating point constant 1 in the appropriate mode. */
1390 const_float_1_operand (rtx op, enum machine_mode mode)
1394 if (GET_CODE (op) != CONST_DOUBLE
1395 || mode != GET_MODE (op)
1396 || (mode != DFmode && mode != SFmode))
1399 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
1401 return REAL_VALUES_EQUAL (d, dconst1);
1404 /* Return true if OP is either the HI or LO register. */
1407 hilo_operand (rtx op, enum machine_mode mode)
1409 return ((mode == VOIDmode || mode == GET_MODE (op))
1410 && REG_P (op) && MD_REG_P (REGNO (op)));
1413 /* Return true if OP is an extension operator. */
1416 extend_operator (rtx op, enum machine_mode mode)
1418 return ((mode == VOIDmode || mode == GET_MODE (op))
1419 && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
1422 /* Return true if X is the right hand side of a "macc" or "msac" instruction.
1423 This predicate is intended for use in peephole optimizations. */
1426 macc_msac_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
1428 if (ISA_HAS_MACC && GET_CODE (x) == PLUS && REG_P (XEXP (x, 1)))
1430 else if (ISA_HAS_MSAC && GET_CODE (x) == MINUS && REG_P (XEXP (x, 0)))
1435 return GET_CODE (x) == MULT && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1));
1438 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
1441 equality_op (rtx op, enum machine_mode mode)
1443 if (mode != GET_MODE (op))
1446 return GET_CODE (op) == EQ || GET_CODE (op) == NE;
1449 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
1452 cmp_op (rtx op, enum machine_mode mode)
1454 if (mode != GET_MODE (op))
1457 return COMPARISON_P (op);
1460 /* Return nonzero if the code is a relational operation suitable for a
1461 conditional trap instruction (only EQ, NE, LT, LTU, GE, GEU).
1462 We need this in the insn that expands `trap_if' in order to prevent
1463 combine from erroneously altering the condition. */
1466 trap_cmp_op (rtx op, enum machine_mode mode)
1468 if (mode != GET_MODE (op))
1471 switch (GET_CODE (op))
1486 /* Return nonzero if the operand is either the PC or a label_ref. */
1489 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1494 if (GET_CODE (op) == LABEL_REF)
1500 /* Test for a valid call address. */
1503 call_insn_operand (rtx op, enum machine_mode mode)
1505 enum mips_symbol_type symbol_type;
1507 if (mips_symbolic_constant_p (op, &symbol_type))
1508 switch (symbol_type)
1510 case SYMBOL_GENERAL:
1511 /* If -mlong-calls, force all calls to use register addressing. */
1512 return !TARGET_LONG_CALLS;
1514 case SYMBOL_GOT_GLOBAL:
1515 /* Without explicit relocs, there is no special syntax for
1516 loading the address of a call destination into a register.
1517 Using "la $25,foo; jal $25" would prevent the lazy binding
1518 of "foo", so keep the address of global symbols with the
1520 return !TARGET_EXPLICIT_RELOCS;
1525 return register_operand (op, mode);
1529 /* Return nonzero if OP is valid as a source operand for a move
1533 move_operand (rtx op, enum machine_mode mode)
1535 enum mips_symbol_type symbol_type;
1537 if (!general_operand (op, mode))
1540 switch (GET_CODE (op))
1543 /* When generating mips16 code, LEGITIMATE_CONSTANT_P rejects
1544 CONST_INTs that can't be loaded using simple insns. */
1548 /* When generating 32-bit code, allow DImode move_operands to
1549 match arbitrary constants. We split them after reload. */
1550 if (!TARGET_64BIT && mode == DImode)
1553 /* Otherwise check whether the constant can be loaded in a single
1555 return LUI_INT (op) || SMALL_INT (op) || SMALL_INT_UNSIGNED (op);
1560 if (CONST_GP_P (op))
1563 return (mips_symbolic_constant_p (op, &symbol_type)
1564 && !mips_split_p[symbol_type]);
1572 /* Accept any operand that can appear in a mips16 constant table
1573 instruction. We can't use any of the standard operand functions
1574 because for these instructions we accept values that are not
1575 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1578 consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1580 return CONSTANT_P (op);
1583 /* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1584 possibly with an offset. */
1587 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1589 enum mips_symbol_type symbol_type;
1591 return mips_symbolic_constant_p (op, &symbol_type);
1595 /* Return true if OP is a symbolic constant of type SYMBOL_GENERAL. */
1598 general_symbolic_operand (rtx op, enum machine_mode mode)
1600 enum mips_symbol_type symbol_type;
1602 return ((mode == VOIDmode || mode == GET_MODE (op))
1603 && mips_symbolic_constant_p (op, &symbol_type)
1604 && symbol_type == SYMBOL_GENERAL);
1608 /* Return true if we're generating PIC and OP is a global symbol. */
1611 global_got_operand (rtx op, enum machine_mode mode)
1613 enum mips_symbol_type symbol_type;
1615 return ((mode == VOIDmode || mode == GET_MODE (op))
1616 && mips_symbolic_constant_p (op, &symbol_type)
1617 && symbol_type == SYMBOL_GOT_GLOBAL);
1621 /* Likewise for local symbols. */
1624 local_got_operand (rtx op, enum machine_mode mode)
1626 enum mips_symbol_type symbol_type;
1628 return ((mode == VOIDmode || mode == GET_MODE (op))
1629 && mips_symbolic_constant_p (op, &symbol_type)
1630 && symbol_type == SYMBOL_GOT_LOCAL);
1634 /* Return true if OP is a memory reference that uses the stack pointer
1635 as a base register. */
1638 stack_operand (rtx op, enum machine_mode mode)
1640 struct mips_address_info addr;
1642 return ((mode == VOIDmode || mode == GET_MODE (op))
1643 && GET_CODE (op) == MEM
1644 && mips_classify_address (&addr, XEXP (op, 0), GET_MODE (op), false)
1645 && addr.type == ADDRESS_REG
1646 && addr.reg == stack_pointer_rtx);
1649 /* Helper function for DFA schedulers. Return true if OP is a floating
1653 fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1655 return REG_P (op) && FP_REG_P (REGNO (op));
1658 /* Helper function for DFA schedulers. Return true if OP is a LO reg. */
1661 lo_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1663 return REG_P (op) && REGNO (op) == LO_REGNUM;
1667 /* This function is used to implement GO_IF_LEGITIMATE_ADDRESS. It
1668 returns a nonzero value if X is a legitimate address for a memory
1669 operand of the indicated MODE. STRICT is nonzero if this function
1670 is called during reload. */
1673 mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1675 struct mips_address_info addr;
1677 return mips_classify_address (&addr, x, mode, strict);
1681 /* Copy VALUE to a register and return that register. If new psuedos
1682 are allowed, copy it into a new register, otherwise use DEST. */
1685 mips_force_temporary (rtx dest, rtx value)
1687 if (!no_new_pseudos)
1688 return force_reg (Pmode, value);
1691 emit_move_insn (copy_rtx (dest), value);
1697 /* Return a LO_SUM expression for ADDR. TEMP is as for mips_force_temporary
1698 and is used to load the high part into a register. */
1701 mips_split_symbol (rtx temp, rtx addr)
1706 high = mips16_gp_pseudo_reg ();
1708 high = mips_force_temporary (temp, gen_rtx_HIGH (Pmode, copy_rtx (addr)));
1709 return gen_rtx_LO_SUM (Pmode, high, addr);
1713 /* Return an UNSPEC address with underlying address ADDRESS and symbol
1714 type SYMBOL_TYPE. */
1717 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
1720 HOST_WIDE_INT offset;
1722 mips_split_const (address, &base, &offset);
1723 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
1724 UNSPEC_ADDRESS_FIRST + symbol_type);
1725 return plus_constant (gen_rtx_CONST (Pmode, base), offset);
1729 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
1730 high part to BASE and return the result. Just return BASE otherwise.
1731 TEMP is available as a temporary register if needed.
1733 The returned expression can be used as the first operand to a LO_SUM. */
1736 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
1737 enum mips_symbol_type symbol_type)
1739 if (mips_split_p[symbol_type])
1741 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
1742 addr = mips_force_temporary (temp, addr);
1743 return mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
1749 /* Return a legitimate address for REG + OFFSET. This function will
1750 create a temporary register if OFFSET is not a SMALL_OPERAND. */
1753 mips_add_offset (rtx reg, HOST_WIDE_INT offset)
1755 if (!SMALL_OPERAND (offset))
1756 reg = expand_simple_binop (GET_MODE (reg), PLUS,
1757 GEN_INT (CONST_HIGH_PART (offset)),
1758 reg, NULL, 0, OPTAB_WIDEN);
1760 return plus_constant (reg, CONST_LOW_PART (offset));
1764 /* This function is used to implement LEGITIMIZE_ADDRESS. If *XLOC can
1765 be legitimized in a way that the generic machinery might not expect,
1766 put the new address in *XLOC and return true. MODE is the mode of
1767 the memory being accessed. */
1770 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
1772 enum mips_symbol_type symbol_type;
1774 /* See if the address can split into a high part and a LO_SUM. */
1775 if (mips_symbolic_constant_p (*xloc, &symbol_type)
1776 && mips_symbolic_address_p (symbol_type, mode)
1777 && mips_split_p[symbol_type])
1779 *xloc = mips_split_symbol (0, *xloc);
1783 if (GET_CODE (*xloc) == PLUS && GET_CODE (XEXP (*xloc, 1)) == CONST_INT)
1785 /* Handle REG + CONSTANT using mips_add_offset. */
1788 reg = XEXP (*xloc, 0);
1789 if (!mips_valid_base_register_p (reg, mode, 0))
1790 reg = copy_to_mode_reg (Pmode, reg);
1791 *xloc = mips_add_offset (reg, INTVAL (XEXP (*xloc, 1)));
1799 /* Subroutine of mips_build_integer (with the same interface).
1800 Assume that the final action in the sequence should be a left shift. */
1803 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1805 unsigned int i, shift;
1807 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1808 since signed numbers are easier to load than unsigned ones. */
1810 while ((value & 1) == 0)
1811 value /= 2, shift++;
1813 i = mips_build_integer (codes, value);
1814 codes[i].code = ASHIFT;
1815 codes[i].value = shift;
1820 /* As for mips_build_shift, but assume that the final action will be
1821 an IOR or PLUS operation. */
1824 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1826 unsigned HOST_WIDE_INT high;
1829 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1830 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1832 /* The constant is too complex to load with a simple lui/ori pair
1833 so our goal is to clear as many trailing zeros as possible.
1834 In this case, we know bit 16 is set and that the low 16 bits
1835 form a negative number. If we subtract that number from VALUE,
1836 we will clear at least the lowest 17 bits, maybe more. */
1837 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1838 codes[i].code = PLUS;
1839 codes[i].value = CONST_LOW_PART (value);
1843 i = mips_build_integer (codes, high);
1844 codes[i].code = IOR;
1845 codes[i].value = value & 0xffff;
1851 /* Fill CODES with a sequence of rtl operations to load VALUE.
1852 Return the number of operations needed. */
1855 mips_build_integer (struct mips_integer_op *codes,
1856 unsigned HOST_WIDE_INT value)
1858 if (SMALL_OPERAND (value)
1859 || SMALL_OPERAND_UNSIGNED (value)
1860 || LUI_OPERAND (value))
1862 /* The value can be loaded with a single instruction. */
1863 codes[0].code = NIL;
1864 codes[0].value = value;
1867 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1869 /* Either the constant is a simple LUI/ORI combination or its
1870 lowest bit is set. We don't want to shift in this case. */
1871 return mips_build_lower (codes, value);
1873 else if ((value & 0xffff) == 0)
1875 /* The constant will need at least three actions. The lowest
1876 16 bits are clear, so the final action will be a shift. */
1877 return mips_build_shift (codes, value);
1881 /* The final action could be a shift, add or inclusive OR.
1882 Rather than use a complex condition to select the best
1883 approach, try both mips_build_shift and mips_build_lower
1884 and pick the one that gives the shortest sequence.
1885 Note that this case is only used once per constant. */
1886 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1887 unsigned int cost, alt_cost;
1889 cost = mips_build_shift (codes, value);
1890 alt_cost = mips_build_lower (alt_codes, value);
1891 if (alt_cost < cost)
1893 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1901 /* Move VALUE into register DEST. */
1904 mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
1906 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
1907 enum machine_mode mode;
1908 unsigned int i, cost;
1911 mode = GET_MODE (dest);
1912 cost = mips_build_integer (codes, value);
1914 /* Apply each binary operation to X. Invariant: X is a legitimate
1915 source operand for a SET pattern. */
1916 x = GEN_INT (codes[0].value);
1917 for (i = 1; i < cost; i++)
1920 emit_move_insn (dest, x), x = dest;
1922 x = force_reg (mode, x);
1923 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
1926 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
1930 /* Subroutine of mips_legitimize_move. Move constant SRC into register
1931 DEST given that SRC satisfies immediate_operand but doesn't satisfy
1935 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
1938 HOST_WIDE_INT offset;
1939 enum mips_symbol_type symbol_type;
1941 /* Split moves of big integers into smaller pieces. In mips16 code,
1942 it's better to force the constant into memory instead. */
1943 if (GET_CODE (src) == CONST_INT && !TARGET_MIPS16)
1945 mips_move_integer (dest, INTVAL (src));
1949 /* See if the symbol can be split. For mips16, this is often worse than
1950 forcing it in the constant pool since it needs the single-register form
1951 of addiu or daddiu. */
1953 && mips_symbolic_constant_p (src, &symbol_type)
1954 && mips_split_p[symbol_type])
1956 emit_move_insn (dest, mips_split_symbol (dest, src));
1960 /* If we have (const (plus symbol offset)), load the symbol first
1961 and then add in the offset. This is usually better than forcing
1962 the constant into memory, at least in non-mips16 code. */
1963 mips_split_const (src, &base, &offset);
1966 && (!no_new_pseudos || SMALL_OPERAND (offset)))
1968 base = mips_force_temporary (dest, base);
1969 emit_move_insn (dest, mips_add_offset (base, offset));
1973 src = force_const_mem (mode, src);
1975 /* When using explicit relocs, constant pool references are sometimes
1976 not legitimate addresses. */
1977 if (!memory_operand (src, VOIDmode))
1978 src = replace_equiv_address (src, mips_split_symbol (dest, XEXP (src, 0)));
1979 emit_move_insn (dest, src);
1983 /* If (set DEST SRC) is not a valid instruction, emit an equivalent
1984 sequence that is valid. */
1987 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
1989 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
1991 emit_move_insn (dest, force_reg (mode, src));
1995 /* Check for individual, fully-reloaded mflo and mfhi instructions. */
1996 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
1997 && REG_P (src) && MD_REG_P (REGNO (src))
1998 && REG_P (dest) && GP_REG_P (REGNO (dest)))
2000 int other_regno = REGNO (src) == HI_REGNUM ? LO_REGNUM : HI_REGNUM;
2001 if (GET_MODE_SIZE (mode) <= 4)
2002 emit_insn (gen_mfhilo_si (gen_rtx_REG (SImode, REGNO (dest)),
2003 gen_rtx_REG (SImode, REGNO (src)),
2004 gen_rtx_REG (SImode, other_regno)));
2006 emit_insn (gen_mfhilo_di (gen_rtx_REG (DImode, REGNO (dest)),
2007 gen_rtx_REG (DImode, REGNO (src)),
2008 gen_rtx_REG (DImode, other_regno)));
2012 /* We need to deal with constants that would be legitimate
2013 immediate_operands but not legitimate move_operands. */
2014 if (CONSTANT_P (src) && !move_operand (src, mode))
2016 mips_legitimize_const_move (mode, dest, src);
2017 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
2023 /* We need a lot of little routines to check constant values on the
2024 mips16. These are used to figure out how long the instruction will
2025 be. It would be much better to do this using constraints, but
2026 there aren't nearly enough letters available. */
2029 m16_check_op (rtx op, int low, int high, int mask)
2031 return (GET_CODE (op) == CONST_INT
2032 && INTVAL (op) >= low
2033 && INTVAL (op) <= high
2034 && (INTVAL (op) & mask) == 0);
2038 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2040 return m16_check_op (op, 0x1, 0x8, 0);
2044 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2046 return m16_check_op (op, - 0x8, 0x7, 0);
2050 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2052 return m16_check_op (op, - 0x7, 0x8, 0);
2056 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2058 return m16_check_op (op, - 0x10, 0xf, 0);
2062 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2064 return m16_check_op (op, - 0xf, 0x10, 0);
2068 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2070 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
2074 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2076 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
2080 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2082 return m16_check_op (op, - 0x80, 0x7f, 0);
2086 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2088 return m16_check_op (op, - 0x7f, 0x80, 0);
2092 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2094 return m16_check_op (op, 0x0, 0xff, 0);
2098 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2100 return m16_check_op (op, - 0xff, 0x0, 0);
2104 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2106 return m16_check_op (op, - 0x1, 0xfe, 0);
2110 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2112 return m16_check_op (op, 0x0, 0xff << 2, 3);
2116 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2118 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
2122 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2124 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
2128 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2130 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
2134 mips_rtx_costs (rtx x, int code, int outer_code, int *total)
2136 enum machine_mode mode = GET_MODE (x);
2143 /* Always return 0, since we don't have different sized
2144 instructions, hence different costs according to Richard
2150 /* A number between 1 and 8 inclusive is efficient for a shift.
2151 Otherwise, we will need an extended instruction. */
2152 if ((outer_code) == ASHIFT || (outer_code) == ASHIFTRT
2153 || (outer_code) == LSHIFTRT)
2155 if (INTVAL (x) >= 1 && INTVAL (x) <= 8)
2158 *total = COSTS_N_INSNS (1);
2162 /* We can use cmpi for an xor with an unsigned 16 bit value. */
2163 if ((outer_code) == XOR
2164 && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
2170 /* We may be able to use slt or sltu for a comparison with a
2171 signed 16 bit value. (The boundary conditions aren't quite
2172 right, but this is just a heuristic anyhow.) */
2173 if (((outer_code) == LT || (outer_code) == LE
2174 || (outer_code) == GE || (outer_code) == GT
2175 || (outer_code) == LTU || (outer_code) == LEU
2176 || (outer_code) == GEU || (outer_code) == GTU)
2177 && INTVAL (x) >= -0x8000 && INTVAL (x) < 0x8000)
2183 /* Equality comparisons with 0 are cheap. */
2184 if (((outer_code) == EQ || (outer_code) == NE)
2191 /* Otherwise fall through to the handling below. */
2197 if (LEGITIMATE_CONSTANT_P (x))
2199 *total = COSTS_N_INSNS (1);
2204 /* The value will need to be fetched from the constant pool. */
2205 *total = CONSTANT_POOL_COST;
2211 /* If the address is legitimate, return the number of
2212 instructions it needs, otherwise use the default handling. */
2213 int n = mips_address_insns (XEXP (x, 0), GET_MODE (x));
2216 *total = COSTS_N_INSNS (1 + n);
2223 *total = COSTS_N_INSNS (6);
2227 *total = COSTS_N_INSNS ((mode == DImode && !TARGET_64BIT) ? 2 : 1);
2233 if (mode == DImode && !TARGET_64BIT)
2235 *total = COSTS_N_INSNS (2);
2243 if (mode == DImode && !TARGET_64BIT)
2245 *total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT)
2252 if (mode == SFmode || mode == DFmode)
2253 *total = COSTS_N_INSNS (1);
2255 *total = COSTS_N_INSNS (4);
2259 *total = COSTS_N_INSNS (1);
2264 if (mode == SFmode || mode == DFmode)
2266 if (TUNE_MIPS3000 || TUNE_MIPS3900)
2267 *total = COSTS_N_INSNS (2);
2268 else if (TUNE_MIPS6000)
2269 *total = COSTS_N_INSNS (3);
2271 *total = COSTS_N_INSNS (4);
2273 *total = COSTS_N_INSNS (6);
2276 if (mode == DImode && !TARGET_64BIT)
2278 *total = COSTS_N_INSNS (4);
2284 if (mode == DImode && !TARGET_64BIT)
2298 *total = COSTS_N_INSNS (4);
2299 else if (TUNE_MIPS6000
2302 *total = COSTS_N_INSNS (5);
2304 *total = COSTS_N_INSNS (7);
2311 *total = COSTS_N_INSNS (4);
2312 else if (TUNE_MIPS3000
2315 *total = COSTS_N_INSNS (5);
2316 else if (TUNE_MIPS6000
2319 *total = COSTS_N_INSNS (6);
2321 *total = COSTS_N_INSNS (8);
2326 *total = COSTS_N_INSNS (12);
2327 else if (TUNE_MIPS3900)
2328 *total = COSTS_N_INSNS (2);
2329 else if (TUNE_MIPS4130)
2330 *total = COSTS_N_INSNS (mode == DImode ? 6 : 4);
2331 else if (TUNE_MIPS5400 || TUNE_SB1)
2332 *total = COSTS_N_INSNS (mode == DImode ? 4 : 3);
2333 else if (TUNE_MIPS5500 || TUNE_MIPS7000)
2334 *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
2335 else if (TUNE_MIPS9000)
2336 *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
2337 else if (TUNE_MIPS6000)
2338 *total = COSTS_N_INSNS (17);
2339 else if (TUNE_MIPS5000)
2340 *total = COSTS_N_INSNS (5);
2342 *total = COSTS_N_INSNS (10);
2351 *total = COSTS_N_INSNS (12);
2352 else if (TUNE_MIPS6000)
2353 *total = COSTS_N_INSNS (15);
2355 *total = COSTS_N_INSNS (24);
2356 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2357 *total = COSTS_N_INSNS (30);
2359 *total = COSTS_N_INSNS (23);
2367 *total = COSTS_N_INSNS (19);
2368 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2369 *total = COSTS_N_INSNS (59);
2370 else if (TUNE_MIPS6000)
2371 *total = COSTS_N_INSNS (16);
2373 *total = COSTS_N_INSNS (32);
2375 *total = COSTS_N_INSNS (36);
2384 *total = COSTS_N_INSNS (35);
2385 else if (TUNE_MIPS6000)
2386 *total = COSTS_N_INSNS (38);
2387 else if (TUNE_MIPS5000)
2388 *total = COSTS_N_INSNS (36);
2390 *total = COSTS_N_INSNS ((mode == SImode) ? 36 : 68);
2391 else if (TUNE_MIPS5400 || TUNE_MIPS5500)
2392 *total = COSTS_N_INSNS ((mode == SImode) ? 42 : 74);
2394 *total = COSTS_N_INSNS (69);
2398 /* A sign extend from SImode to DImode in 64 bit mode is often
2399 zero instructions, because the result can often be used
2400 directly by another instruction; we'll call it one. */
2401 if (TARGET_64BIT && mode == DImode
2402 && GET_MODE (XEXP (x, 0)) == SImode)
2403 *total = COSTS_N_INSNS (1);
2405 *total = COSTS_N_INSNS (2);
2409 if (TARGET_64BIT && mode == DImode
2410 && GET_MODE (XEXP (x, 0)) == SImode)
2411 *total = COSTS_N_INSNS (2);
2413 *total = COSTS_N_INSNS (1);
2421 /* Provide the costs of an addressing mode that contains ADDR.
2422 If ADDR is not a valid address, its cost is irrelevant. */
2425 mips_address_cost (rtx addr)
2427 return mips_address_insns (addr, SImode);
2430 /* Return one word of double-word value OP, taking into account the fixed
2431 endianness of certain registers. HIGH_P is true to select the high part,
2432 false to select the low part. */
2435 mips_subword (rtx op, int high_p)
2438 enum machine_mode mode;
2440 mode = GET_MODE (op);
2441 if (mode == VOIDmode)
2444 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
2445 byte = UNITS_PER_WORD;
2449 if (GET_CODE (op) == REG)
2451 if (FP_REG_P (REGNO (op)))
2452 return gen_rtx_REG (word_mode, high_p ? REGNO (op) + 1 : REGNO (op));
2453 if (REGNO (op) == HI_REGNUM)
2454 return gen_rtx_REG (word_mode, high_p ? HI_REGNUM : LO_REGNUM);
2457 if (GET_CODE (op) == MEM)
2458 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
2460 return simplify_gen_subreg (word_mode, op, mode, byte);
2464 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
2467 mips_split_64bit_move_p (rtx dest, rtx src)
2472 /* FP->FP moves can be done in a single instruction. */
2473 if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
2476 /* Check for floating-point loads and stores. They can be done using
2477 ldc1 and sdc1 on MIPS II and above. */
2480 if (FP_REG_RTX_P (dest) && GET_CODE (src) == MEM)
2482 if (FP_REG_RTX_P (src) && GET_CODE (dest) == MEM)
2489 /* Split a 64-bit move from SRC to DEST assuming that
2490 mips_split_64bit_move_p holds.
2492 Moves into and out of FPRs cause some difficulty here. Such moves
2493 will always be DFmode, since paired FPRs are not allowed to store
2494 DImode values. The most natural representation would be two separate
2495 32-bit moves, such as:
2497 (set (reg:SI $f0) (mem:SI ...))
2498 (set (reg:SI $f1) (mem:SI ...))
2500 However, the second insn is invalid because odd-numbered FPRs are
2501 not allowed to store independent values. Use the patterns load_df_low,
2502 load_df_high and store_df_high instead. */
2505 mips_split_64bit_move (rtx dest, rtx src)
2507 if (FP_REG_RTX_P (dest))
2509 /* Loading an FPR from memory or from GPRs. */
2510 emit_insn (gen_load_df_low (copy_rtx (dest), mips_subword (src, 0)));
2511 emit_insn (gen_load_df_high (dest, mips_subword (src, 1),
2514 else if (FP_REG_RTX_P (src))
2516 /* Storing an FPR into memory or GPRs. */
2517 emit_move_insn (mips_subword (dest, 0), mips_subword (src, 0));
2518 emit_insn (gen_store_df_high (mips_subword (dest, 1), src));
2522 /* The operation can be split into two normal moves. Decide in
2523 which order to do them. */
2526 low_dest = mips_subword (dest, 0);
2527 if (GET_CODE (low_dest) == REG
2528 && reg_overlap_mentioned_p (low_dest, src))
2530 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2531 emit_move_insn (low_dest, mips_subword (src, 0));
2535 emit_move_insn (low_dest, mips_subword (src, 0));
2536 emit_move_insn (mips_subword (dest, 1), mips_subword (src, 1));
2541 /* Return the appropriate instructions to move SRC into DEST. Assume
2542 that SRC is operand 1 and DEST is operand 0. */
2545 mips_output_move (rtx dest, rtx src)
2547 enum rtx_code dest_code, src_code;
2550 dest_code = GET_CODE (dest);
2551 src_code = GET_CODE (src);
2552 dbl_p = (GET_MODE_SIZE (GET_MODE (dest)) == 8);
2554 if (dbl_p && mips_split_64bit_move_p (dest, src))
2557 if ((src_code == REG && GP_REG_P (REGNO (src)))
2558 || (!TARGET_MIPS16 && src == CONST0_RTX (GET_MODE (dest))))
2560 if (dest_code == REG)
2562 if (GP_REG_P (REGNO (dest)))
2563 return "move\t%0,%z1";
2565 if (MD_REG_P (REGNO (dest)))
2568 if (FP_REG_P (REGNO (dest)))
2569 return (dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0");
2571 if (ALL_COP_REG_P (REGNO (dest)))
2573 static char retval[] = "dmtc_\t%z1,%0";
2575 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2576 return (dbl_p ? retval : retval + 1);
2579 if (dest_code == MEM)
2580 return (dbl_p ? "sd\t%z1,%0" : "sw\t%z1,%0");
2582 if (dest_code == REG && GP_REG_P (REGNO (dest)))
2584 if (src_code == REG)
2586 if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC)
2587 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
2589 if (FP_REG_P (REGNO (src)))
2590 return (dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1");
2592 if (ALL_COP_REG_P (REGNO (src)))
2594 static char retval[] = "dmfc_\t%0,%1";
2596 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2597 return (dbl_p ? retval : retval + 1);
2601 if (src_code == MEM)
2602 return (dbl_p ? "ld\t%0,%1" : "lw\t%0,%1");
2604 if (src_code == CONST_INT)
2606 /* Don't use the X format, because that will give out of
2607 range numbers for 64 bit hosts and 32 bit targets. */
2609 return "li\t%0,%1\t\t\t# %X1";
2611 if (INTVAL (src) >= 0 && INTVAL (src) <= 0xffff)
2614 if (INTVAL (src) < 0 && INTVAL (src) >= -0xffff)
2615 return "li\t%0,%n1\n\tneg\t%0";
2618 if (src_code == HIGH)
2619 return "lui\t%0,%h1";
2621 if (CONST_GP_P (src))
2622 return "move\t%0,%1";
2624 if (symbolic_operand (src, VOIDmode))
2625 return (dbl_p ? "dla\t%0,%1" : "la\t%0,%1");
2627 if (src_code == REG && FP_REG_P (REGNO (src)))
2629 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2630 return (dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1");
2632 if (dest_code == MEM)
2633 return (dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0");
2635 if (dest_code == REG && FP_REG_P (REGNO (dest)))
2637 if (src_code == MEM)
2638 return (dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1");
2640 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
2642 static char retval[] = "l_c_\t%0,%1";
2644 retval[1] = (dbl_p ? 'd' : 'w');
2645 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
2648 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
2650 static char retval[] = "s_c_\t%1,%0";
2652 retval[1] = (dbl_p ? 'd' : 'w');
2653 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
2659 /* Return an rtx for the gp save slot. Valid only when using o32 or
2663 mips_gp_save_slot (void)
2667 if (!TARGET_ABICALLS || TARGET_NEWABI)
2670 if (frame_pointer_needed)
2671 loc = hard_frame_pointer_rtx;
2673 loc = stack_pointer_rtx;
2674 loc = plus_constant (loc, current_function_outgoing_args_size);
2675 loc = gen_rtx_MEM (Pmode, loc);
2676 RTX_UNCHANGING_P (loc) = 1;
2680 /* Make normal rtx_code into something we can index from an array */
2682 static enum internal_test
2683 map_test_to_internal_test (enum rtx_code test_code)
2685 enum internal_test test = ITEST_MAX;
2689 case EQ: test = ITEST_EQ; break;
2690 case NE: test = ITEST_NE; break;
2691 case GT: test = ITEST_GT; break;
2692 case GE: test = ITEST_GE; break;
2693 case LT: test = ITEST_LT; break;
2694 case LE: test = ITEST_LE; break;
2695 case GTU: test = ITEST_GTU; break;
2696 case GEU: test = ITEST_GEU; break;
2697 case LTU: test = ITEST_LTU; break;
2698 case LEU: test = ITEST_LEU; break;
2706 /* Generate the code to compare two integer values. The return value is:
2707 (reg:SI xx) The pseudo register the comparison is in
2708 0 No register, generate a simple branch.
2710 ??? This is called with result nonzero by the Scond patterns in
2711 mips.md. These patterns are called with a target in the mode of
2712 the Scond instruction pattern. Since this must be a constant, we
2713 must use SImode. This means that if RESULT is nonzero, it will
2714 always be an SImode register, even if TARGET_64BIT is true. We
2715 cope with this by calling convert_move rather than emit_move_insn.
2716 This will sometimes lead to an unnecessary extension of the result;
2725 TEST_CODE is the rtx code for the comparison.
2726 CMP0 and CMP1 are the two operands to compare.
2727 RESULT is the register in which the result should be stored (null for
2729 For branches, P_INVERT points to an integer that is nonzero on return
2730 if the branch should be inverted. */
2733 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
2734 rtx cmp1, int *p_invert)
2738 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2739 int const_low; /* low bound of constant we can accept */
2740 int const_high; /* high bound of constant we can accept */
2741 int const_add; /* constant to add (convert LE -> LT) */
2742 int reverse_regs; /* reverse registers in test */
2743 int invert_const; /* != 0 if invert value if cmp1 is constant */
2744 int invert_reg; /* != 0 if invert value if cmp1 is register */
2745 int unsignedp; /* != 0 for unsigned comparisons. */
2748 static const struct cmp_info info[ (int)ITEST_MAX ] = {
2750 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2751 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2752 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2753 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2754 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2755 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2756 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2757 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2758 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2759 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2762 enum internal_test test;
2763 enum machine_mode mode;
2764 const struct cmp_info *p_info;
2771 test = map_test_to_internal_test (test_code);
2772 if (test == ITEST_MAX)
2775 p_info = &info[(int) test];
2776 eqne_p = (p_info->test_code == XOR);
2778 mode = GET_MODE (cmp0);
2779 if (mode == VOIDmode)
2780 mode = GET_MODE (cmp1);
2782 /* Eliminate simple branches. */
2783 branch_p = (result == 0);
2786 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2788 /* Comparisons against zero are simple branches. */
2789 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2790 && (! TARGET_MIPS16 || eqne_p))
2793 /* Test for beq/bne. */
2794 if (eqne_p && ! TARGET_MIPS16)
2798 /* Allocate a pseudo to calculate the value in. */
2799 result = gen_reg_rtx (mode);
2802 /* Make sure we can handle any constants given to us. */
2803 if (GET_CODE (cmp0) == CONST_INT)
2804 cmp0 = force_reg (mode, cmp0);
2806 if (GET_CODE (cmp1) == CONST_INT)
2808 HOST_WIDE_INT value = INTVAL (cmp1);
2810 if (value < p_info->const_low
2811 || value > p_info->const_high
2812 /* ??? Why? And why wasn't the similar code below modified too? */
2814 && HOST_BITS_PER_WIDE_INT < 64
2815 && p_info->const_add != 0
2816 && ((p_info->unsignedp
2817 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2818 > (unsigned HOST_WIDE_INT) INTVAL (cmp1))
2819 : (value + p_info->const_add) > INTVAL (cmp1))
2820 != (p_info->const_add > 0))))
2821 cmp1 = force_reg (mode, cmp1);
2824 /* See if we need to invert the result. */
2825 invert = (GET_CODE (cmp1) == CONST_INT
2826 ? p_info->invert_const : p_info->invert_reg);
2828 if (p_invert != (int *)0)
2834 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2835 Comparison between two registers, may involve switching operands. */
2836 if (GET_CODE (cmp1) == CONST_INT)
2838 if (p_info->const_add != 0)
2840 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2842 /* If modification of cmp1 caused overflow,
2843 we would get the wrong answer if we follow the usual path;
2844 thus, x > 0xffffffffU would turn into x > 0U. */
2845 if ((p_info->unsignedp
2846 ? (unsigned HOST_WIDE_INT) new >
2847 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
2848 : new > INTVAL (cmp1))
2849 != (p_info->const_add > 0))
2851 /* This test is always true, but if INVERT is true then
2852 the result of the test needs to be inverted so 0 should
2853 be returned instead. */
2854 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2858 cmp1 = GEN_INT (new);
2862 else if (p_info->reverse_regs)
2869 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2873 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2874 convert_move (reg, gen_rtx_fmt_ee (p_info->test_code,
2875 mode, cmp0, cmp1), 0);
2878 if (test == ITEST_NE)
2880 if (! TARGET_MIPS16)
2882 convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
2883 if (p_invert != NULL)
2889 reg2 = invert ? gen_reg_rtx (mode) : result;
2890 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2895 else if (test == ITEST_EQ)
2897 reg2 = invert ? gen_reg_rtx (mode) : result;
2898 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
2906 if (! TARGET_MIPS16)
2910 /* The value is in $24. Copy it to another register, so
2911 that reload doesn't think it needs to store the $24 and
2912 the input to the XOR in the same location. */
2913 reg2 = gen_reg_rtx (mode);
2914 emit_move_insn (reg2, reg);
2916 one = force_reg (mode, const1_rtx);
2918 convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
2924 /* Work out how to check a floating-point condition. We need a
2925 separate comparison instruction (C.cond.fmt), followed by a
2926 branch or conditional move. Given that IN_CODE is the
2927 required condition, set *CMP_CODE to the C.cond.fmt code
2928 and *action_code to the branch or move code. */
2931 get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
2932 enum rtx_code *action_code)
2941 *cmp_code = reverse_condition_maybe_unordered (in_code);
2946 *cmp_code = in_code;
2952 /* Emit the common code for doing conditional branches.
2953 operand[0] is the label to jump to.
2954 The comparison operands are saved away by cmp{si,di,sf,df}. */
2957 gen_conditional_branch (rtx *operands, enum rtx_code test_code)
2959 enum cmp_type type = branch_type;
2960 rtx cmp0 = branch_cmp[0];
2961 rtx cmp1 = branch_cmp[1];
2962 enum machine_mode mode;
2963 enum rtx_code cmp_code;
2972 mode = type == CMP_SI ? SImode : DImode;
2974 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
2982 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2983 /* We don't want to build a comparison against a nonzero
2985 cmp1 = force_reg (mode, cmp1);
2992 reg = gen_rtx_REG (CCmode, FPSW_REGNUM);
2994 reg = gen_reg_rtx (CCmode);
2996 get_float_compare_codes (test_code, &cmp_code, &test_code);
2997 emit_insn (gen_rtx_SET (VOIDmode, reg,
2998 gen_rtx_fmt_ee (cmp_code, CCmode, cmp0, cmp1)));
3007 fatal_insn ("bad test",
3008 gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1));
3011 /* Generate the branch. */
3013 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[0]);
3023 (gen_rtx_SET (VOIDmode, pc_rtx,
3024 gen_rtx_IF_THEN_ELSE (VOIDmode,
3025 gen_rtx_fmt_ee (test_code, mode,
3030 /* Emit the common code for conditional moves. OPERANDS is the array
3031 of operands passed to the conditional move define_expand. */
3034 gen_conditional_move (rtx *operands)
3036 rtx op0 = branch_cmp[0];
3037 rtx op1 = branch_cmp[1];
3038 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3039 enum rtx_code cmp_code = GET_CODE (operands[1]);
3040 enum rtx_code move_code = NE;
3041 enum machine_mode op_mode = GET_MODE (operands[0]);
3042 enum machine_mode cmp_mode;
3045 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
3064 op0 = force_reg (mode, branch_cmp[1]);
3065 op1 = branch_cmp[0];
3069 op0 = force_reg (mode, branch_cmp[1]);
3070 op1 = branch_cmp[0];
3081 op0 = force_reg (mode, branch_cmp[1]);
3082 op1 = branch_cmp[0];
3086 op0 = force_reg (mode, branch_cmp[1]);
3087 op1 = branch_cmp[0];
3095 get_float_compare_codes (cmp_code, &cmp_code, &move_code);
3097 if (mode == SImode || mode == DImode)
3099 else if (mode == SFmode || mode == DFmode)
3104 cmp_reg = gen_reg_rtx (cmp_mode);
3105 emit_insn (gen_rtx_SET (cmp_mode, cmp_reg,
3106 gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
3108 emit_insn (gen_rtx_SET (op_mode, operands[0],
3109 gen_rtx_IF_THEN_ELSE (op_mode,
3110 gen_rtx_fmt_ee (move_code,
3114 operands[2], operands[3])));
3117 /* Emit a conditional trap. OPERANDS is the array of operands passed to
3118 the conditional_trap expander. */
3121 mips_gen_conditional_trap (rtx *operands)
3124 enum rtx_code cmp_code = GET_CODE (operands[0]);
3125 enum machine_mode mode = GET_MODE (branch_cmp[0]);
3127 /* MIPS conditional trap machine instructions don't have GT or LE
3128 flavors, so we must invert the comparison and convert to LT and
3129 GE, respectively. */
3132 case GT: cmp_code = LT; break;
3133 case LE: cmp_code = GE; break;
3134 case GTU: cmp_code = LTU; break;
3135 case LEU: cmp_code = GEU; break;
3138 if (cmp_code == GET_CODE (operands[0]))
3140 op0 = force_reg (mode, branch_cmp[0]);
3141 op1 = branch_cmp[1];
3145 op0 = force_reg (mode, branch_cmp[1]);
3146 op1 = branch_cmp[0];
3148 if (GET_CODE (op1) == CONST_INT && ! SMALL_INT (op1))
3149 op1 = force_reg (mode, op1);
3151 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
3152 gen_rtx_fmt_ee (cmp_code, GET_MODE (operands[0]),
3157 /* Load function address ADDR into register DEST. SIBCALL_P is true
3158 if the address is needed for a sibling call. */
3161 mips_load_call_address (rtx dest, rtx addr, int sibcall_p)
3163 /* If we're generating PIC, and this call is to a global function,
3164 try to allow its address to be resolved lazily. This isn't
3165 possible for NewABI sibcalls since the value of $gp on entry
3166 to the stub would be our caller's gp, not ours. */
3167 if (TARGET_EXPLICIT_RELOCS
3168 && !(sibcall_p && TARGET_NEWABI)
3169 && global_got_operand (addr, VOIDmode))
3171 rtx high, lo_sum_symbol;
3173 high = mips_unspec_offset_high (dest, pic_offset_table_rtx,
3174 addr, SYMBOL_GOTOFF_CALL);
3175 lo_sum_symbol = mips_unspec_address (addr, SYMBOL_GOTOFF_CALL);
3176 if (Pmode == SImode)
3177 emit_insn (gen_load_callsi (dest, high, lo_sum_symbol));
3179 emit_insn (gen_load_calldi (dest, high, lo_sum_symbol));
3182 emit_move_insn (dest, addr);
3186 /* Expand a call or call_value instruction. RESULT is where the
3187 result will go (null for calls), ADDR is the address of the
3188 function, ARGS_SIZE is the size of the arguments and AUX is
3189 the value passed to us by mips_function_arg. SIBCALL_P is true
3190 if we are expanding a sibling call, false if we're expanding
3194 mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
3196 rtx orig_addr, pattern, insn;
3199 if (!call_insn_operand (addr, VOIDmode))
3201 addr = gen_reg_rtx (Pmode);
3202 mips_load_call_address (addr, orig_addr, sibcall_p);
3206 && mips16_hard_float
3207 && build_mips16_call_stub (result, addr, args_size,
3208 aux == 0 ? 0 : (int) GET_MODE (aux)))
3212 pattern = (sibcall_p
3213 ? gen_sibcall_internal (addr, args_size)
3214 : gen_call_internal (addr, args_size));
3215 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
3219 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
3220 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
3223 ? gen_sibcall_value_multiple_internal (reg1, addr, args_size, reg2)
3224 : gen_call_value_multiple_internal (reg1, addr, args_size, reg2));
3227 pattern = (sibcall_p
3228 ? gen_sibcall_value_internal (result, addr, args_size)
3229 : gen_call_value_internal (result, addr, args_size));
3231 insn = emit_call_insn (pattern);
3233 /* Lazy-binding stubs require $gp to be valid on entry. */
3234 if (global_got_operand (orig_addr, VOIDmode))
3235 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
3239 /* We can handle any sibcall when TARGET_SIBCALLS is true. */
3242 mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
3243 tree exp ATTRIBUTE_UNUSED)
3245 return TARGET_SIBCALLS;
3248 /* Return true if operand OP is a condition code register.
3249 Only for use during or after reload. */
3252 fcc_register_operand (rtx op, enum machine_mode mode)
3254 return ((mode == VOIDmode || mode == GET_MODE (op))
3255 && (reload_in_progress || reload_completed)
3256 && (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
3257 && ST_REG_P (true_regnum (op)));
3260 /* Emit code to move general operand SRC into condition-code
3261 register DEST. SCRATCH is a scratch TFmode float register.
3268 where FP1 and FP2 are single-precision float registers
3269 taken from SCRATCH. */
3272 mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
3276 /* Change the source to SFmode. */
3277 if (GET_CODE (src) == MEM)
3278 src = adjust_address (src, SFmode, 0);
3279 else if (GET_CODE (src) == REG || GET_CODE (src) == SUBREG)
3280 src = gen_rtx_REG (SFmode, true_regnum (src));
3282 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
3283 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + FP_INC);
3285 emit_move_insn (copy_rtx (fp1), src);
3286 emit_move_insn (copy_rtx (fp2), CONST0_RTX (SFmode));
3287 emit_insn (gen_slt_sf (dest, fp2, fp1));
3290 /* Emit code to change the current function's return address to
3291 ADDRESS. SCRATCH is available as a scratch register, if needed.
3292 ADDRESS and SCRATCH are both word-mode GPRs. */
3295 mips_set_return_address (rtx address, rtx scratch)
3297 HOST_WIDE_INT gp_offset;
3299 compute_frame_size (get_frame_size ());
3300 if (((cfun->machine->frame.mask >> 31) & 1) == 0)
3302 gp_offset = cfun->machine->frame.gp_sp_offset;
3304 /* Reduce SP + GP_OFSET to a legitimate address and put it in SCRATCH. */
3305 if (gp_offset < 32768)
3306 scratch = plus_constant (stack_pointer_rtx, gp_offset);
3309 emit_move_insn (scratch, GEN_INT (gp_offset));
3310 if (Pmode == DImode)
3311 emit_insn (gen_adddi3 (scratch, scratch, stack_pointer_rtx));
3313 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
3316 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
3319 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
3320 Assume that the areas do not overlap. */
3323 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
3325 HOST_WIDE_INT offset, delta;
3326 unsigned HOST_WIDE_INT bits;
3328 enum machine_mode mode;
3331 /* Work out how many bits to move at a time. If both operands have
3332 half-word alignment, it is usually better to move in half words.
3333 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
3334 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
3335 Otherwise move word-sized chunks. */
3336 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
3337 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
3338 bits = BITS_PER_WORD / 2;
3340 bits = BITS_PER_WORD;
3342 mode = mode_for_size (bits, MODE_INT, 0);
3343 delta = bits / BITS_PER_UNIT;
3345 /* Allocate a buffer for the temporary registers. */
3346 regs = alloca (sizeof (rtx) * length / delta);
3348 /* Load as many BITS-sized chunks as possible. Use a normal load if
3349 the source has enough alignment, otherwise use left/right pairs. */
3350 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3352 regs[i] = gen_reg_rtx (mode);
3353 if (MEM_ALIGN (src) >= bits)
3354 emit_move_insn (regs[i], adjust_address (src, mode, offset));
3357 rtx part = adjust_address (src, BLKmode, offset);
3358 if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
3363 /* Copy the chunks to the destination. */
3364 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
3365 if (MEM_ALIGN (dest) >= bits)
3366 emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
3369 rtx part = adjust_address (dest, BLKmode, offset);
3370 if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
3374 /* Mop up any left-over bytes. */
3375 if (offset < length)
3377 src = adjust_address (src, BLKmode, offset);
3378 dest = adjust_address (dest, BLKmode, offset);
3379 move_by_pieces (dest, src, length - offset,
3380 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
3384 #define MAX_MOVE_REGS 4
3385 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
3388 /* Helper function for doing a loop-based block operation on memory
3389 reference MEM. Each iteration of the loop will operate on LENGTH
3392 Create a new base register for use within the loop and point it to
3393 the start of MEM. Create a new memory reference that uses this
3394 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
3397 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
3398 rtx *loop_reg, rtx *loop_mem)
3400 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
3402 /* Although the new mem does not refer to a known location,
3403 it does keep up to LENGTH bytes of alignment. */
3404 *loop_mem = change_address (mem, BLKmode, *loop_reg);
3405 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
3409 /* Move LENGTH bytes from SRC to DEST using a loop that moves MAX_MOVE_BYTES
3410 per iteration. LENGTH must be at least MAX_MOVE_BYTES. Assume that the
3411 memory regions do not overlap. */
3414 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
3416 rtx label, src_reg, dest_reg, final_src;
3417 HOST_WIDE_INT leftover;
3419 leftover = length % MAX_MOVE_BYTES;
3422 /* Create registers and memory references for use within the loop. */
3423 mips_adjust_block_mem (src, MAX_MOVE_BYTES, &src_reg, &src);
3424 mips_adjust_block_mem (dest, MAX_MOVE_BYTES, &dest_reg, &dest);
3426 /* Calculate the value that SRC_REG should have after the last iteration
3428 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
3431 /* Emit the start of the loop. */
3432 label = gen_label_rtx ();
3435 /* Emit the loop body. */
3436 mips_block_move_straight (dest, src, MAX_MOVE_BYTES);
3438 /* Move on to the next block. */
3439 emit_move_insn (src_reg, plus_constant (src_reg, MAX_MOVE_BYTES));
3440 emit_move_insn (dest_reg, plus_constant (dest_reg, MAX_MOVE_BYTES));
3442 /* Emit the loop condition. */
3443 if (Pmode == DImode)
3444 emit_insn (gen_cmpdi (src_reg, final_src));
3446 emit_insn (gen_cmpsi (src_reg, final_src));
3447 emit_jump_insn (gen_bne (label));
3449 /* Mop up any left-over bytes. */
3451 mips_block_move_straight (dest, src, leftover);
3454 /* Expand a movmemsi instruction. */
3457 mips_expand_block_move (rtx dest, rtx src, rtx length)
3459 if (GET_CODE (length) == CONST_INT)
3461 if (INTVAL (length) <= 2 * MAX_MOVE_BYTES)
3463 mips_block_move_straight (dest, src, INTVAL (length));
3468 mips_block_move_loop (dest, src, INTVAL (length));
3475 /* Argument support functions. */
3477 /* Initialize CUMULATIVE_ARGS for a function. */
3480 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3481 rtx libname ATTRIBUTE_UNUSED)
3483 static CUMULATIVE_ARGS zero_cum;
3484 tree param, next_param;
3487 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3489 /* Determine if this function has variable arguments. This is
3490 indicated by the last argument being 'void_type_mode' if there
3491 are no variable arguments. The standard MIPS calling sequence
3492 passes all arguments in the general purpose registers in this case. */
3494 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
3495 param != 0; param = next_param)
3497 next_param = TREE_CHAIN (param);
3498 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
3499 cum->gp_reg_found = 1;
3504 /* Fill INFO with information about a single argument. CUM is the
3505 cumulative state for earlier arguments. MODE is the mode of this
3506 argument and TYPE is its type (if known). NAMED is true if this
3507 is a named (fixed) argument rather than a variable one. */
3510 mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3511 tree type, int named, struct mips_arg_info *info)
3514 unsigned int num_words, max_regs;
3516 /* Decide whether this argument should go in a floating-point register,
3517 assuming one is free. Later code checks for availability. */
3519 info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
3520 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
3527 info->fpr_p = (!cum->gp_reg_found
3528 && cum->arg_number < 2
3529 && (type == 0 || FLOAT_TYPE_P (type)));
3534 info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
3538 /* Now decide whether the argument must go in an even-numbered register. */
3543 /* Under the O64 ABI, the second float argument goes in $f13 if it
3544 is a double, but $f14 if it is a single. Otherwise, on a
3545 32-bit double-float machine, each FP argument must start in a
3546 new register pair. */
3547 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_HWFPVALUE
3548 || (mips_abi == ABI_O64 && mode == SFmode)
3551 else if (!TARGET_64BIT || LONG_DOUBLE_TYPE_SIZE == 128)
3553 if (GET_MODE_CLASS (mode) == MODE_INT
3554 || GET_MODE_CLASS (mode) == MODE_FLOAT)
3555 even_reg_p = (GET_MODE_SIZE (mode) > UNITS_PER_WORD);
3557 else if (type != NULL_TREE && TYPE_ALIGN (type) > BITS_PER_WORD)
3561 /* Set REG_OFFSET to the register count we're interested in.
3562 The EABI allocates the floating-point registers separately,
3563 but the other ABIs allocate them like integer registers. */
3564 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
3569 info->reg_offset += info->reg_offset & 1;
3571 /* The alignment applied to registers is also applied to stack arguments. */
3572 info->stack_offset = cum->stack_words;
3574 info->stack_offset += info->stack_offset & 1;
3576 if (mode == BLKmode)
3577 info->num_bytes = int_size_in_bytes (type);
3579 info->num_bytes = GET_MODE_SIZE (mode);
3581 num_words = (info->num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3582 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
3584 /* Partition the argument between registers and stack. */
3585 info->reg_words = MIN (num_words, max_regs);
3586 info->stack_words = num_words - info->reg_words;
3590 /* Implement FUNCTION_ARG_ADVANCE. */
3593 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3594 tree type, int named)
3596 struct mips_arg_info info;
3598 mips_arg_info (cum, mode, type, named, &info);
3601 cum->gp_reg_found = true;
3603 /* See the comment above the cumulative args structure in mips.h
3604 for an explanation of what this code does. It assumes the O32
3605 ABI, which passes at most 2 arguments in float registers. */
3606 if (cum->arg_number < 2 && info.fpr_p)
3607 cum->fp_code += (mode == SFmode ? 1 : 2) << ((cum->arg_number - 1) * 2);
3609 if (mips_abi != ABI_EABI || !info.fpr_p)
3610 cum->num_gprs = info.reg_offset + info.reg_words;
3611 else if (info.reg_words > 0)
3612 cum->num_fprs += FP_INC;
3614 if (info.stack_words > 0)
3615 cum->stack_words = info.stack_offset + info.stack_words;
3620 /* Implement FUNCTION_ARG. */
3623 function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
3624 tree type, int named)
3626 struct mips_arg_info info;
3628 /* We will be called with a mode of VOIDmode after the last argument
3629 has been seen. Whatever we return will be passed to the call
3630 insn. If we need a mips16 fp_code, return a REG with the code
3631 stored as the mode. */
3632 if (mode == VOIDmode)
3634 if (TARGET_MIPS16 && cum->fp_code != 0)
3635 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
3641 mips_arg_info (cum, mode, type, named, &info);
3643 /* Return straight away if the whole argument is passed on the stack. */
3644 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
3648 && TREE_CODE (type) == RECORD_TYPE
3650 && TYPE_SIZE_UNIT (type)
3651 && host_integerp (TYPE_SIZE_UNIT (type), 1)
3654 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3655 structure contains a double in its entirety, then that 64 bit
3656 chunk is passed in a floating point register. */
3659 /* First check to see if there is any such field. */
3660 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3661 if (TREE_CODE (field) == FIELD_DECL
3662 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3663 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3664 && host_integerp (bit_position (field), 0)
3665 && int_bit_position (field) % BITS_PER_WORD == 0)
3670 /* Now handle the special case by returning a PARALLEL
3671 indicating where each 64 bit chunk goes. INFO.REG_WORDS
3672 chunks are passed in registers. */
3674 HOST_WIDE_INT bitpos;
3677 /* assign_parms checks the mode of ENTRY_PARM, so we must
3678 use the actual mode here. */
3679 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
3682 field = TYPE_FIELDS (type);
3683 for (i = 0; i < info.reg_words; i++)
3687 for (; field; field = TREE_CHAIN (field))
3688 if (TREE_CODE (field) == FIELD_DECL
3689 && int_bit_position (field) >= bitpos)
3693 && int_bit_position (field) == bitpos
3694 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3695 && !TARGET_SOFT_FLOAT
3696 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3697 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
3699 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
3702 = gen_rtx_EXPR_LIST (VOIDmode, reg,
3703 GEN_INT (bitpos / BITS_PER_UNIT));
3705 bitpos += BITS_PER_WORD;
3712 return gen_rtx_REG (mode, FP_ARG_FIRST + info.reg_offset);
3714 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
3718 /* Implement FUNCTION_ARG_PARTIAL_NREGS. */
3721 function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
3722 enum machine_mode mode, tree type, int named)
3724 struct mips_arg_info info;
3726 mips_arg_info (cum, mode, type, named, &info);
3727 return info.stack_words > 0 ? info.reg_words : 0;
3731 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
3732 upward rather than downward. In other words, return true if the
3733 first byte of the stack slot has useful data, false if the last
3737 mips_pad_arg_upward (enum machine_mode mode, tree type)
3739 /* On little-endian targets, the first byte of every stack argument
3740 is passed in the first byte of the stack slot. */
3741 if (!BYTES_BIG_ENDIAN)
3744 /* Otherwise, integral types are padded downward: the last byte of a
3745 stack argument is passed in the last byte of the stack slot. */
3747 ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
3748 : GET_MODE_CLASS (mode) == MODE_INT)
3751 /* Big-endian o64 pads floating-point arguments downward. */
3752 if (mips_abi == ABI_O64)
3753 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3756 /* Other types are padded upward for o32, o64, n32 and n64. */
3757 if (mips_abi != ABI_EABI)
3760 /* Arguments smaller than a stack slot are padded downward. */
3761 if (mode != BLKmode)
3762 return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
3764 return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
3768 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
3769 if the least significant byte of the register has useful data. Return
3770 the opposite if the most significant byte does. */
3773 mips_pad_reg_upward (enum machine_mode mode, tree type)
3775 /* No shifting is required for floating-point arguments. */
3776 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
3777 return !BYTES_BIG_ENDIAN;
3779 /* Otherwise, apply the same padding to register arguments as we do
3780 to stack arguments. */
3781 return mips_pad_arg_upward (mode, type);
3785 mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3786 tree type, int *pretend_size, int no_rtl)
3788 CUMULATIVE_ARGS local_cum;
3789 int gp_saved, fp_saved;
3791 /* The caller has advanced CUM up to, but not beyond, the last named
3792 argument. Advance a local copy of CUM past the last "real" named
3793 argument, to find out how many registers are left over. */
3796 FUNCTION_ARG_ADVANCE (local_cum, mode, type, 1);
3798 /* Found out how many registers we need to save. */
3799 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
3800 fp_saved = (EABI_FLOAT_VARARGS_P
3801 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
3810 ptr = virtual_incoming_args_rtx;
3815 ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
3819 ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
3822 mem = gen_rtx_MEM (BLKmode, ptr);
3823 set_mem_alias_set (mem, get_varargs_alias_set ());
3825 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
3830 /* We can't use move_block_from_reg, because it will use
3832 enum machine_mode mode;
3835 /* Set OFF to the offset from virtual_incoming_args_rtx of
3836 the first float register. The FP save area lies below
3837 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
3838 off = -gp_saved * UNITS_PER_WORD;
3839 off &= ~(UNITS_PER_FPVALUE - 1);
3840 off -= fp_saved * UNITS_PER_FPREG;
3842 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
3844 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
3848 ptr = plus_constant (virtual_incoming_args_rtx, off);
3849 mem = gen_rtx_MEM (mode, ptr);
3850 set_mem_alias_set (mem, get_varargs_alias_set ());
3851 emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
3852 off += UNITS_PER_HWFPVALUE;
3858 /* No need for pretend arguments: the register parameter area was
3859 allocated by the caller. */
3863 *pretend_size = (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
3866 /* Create the va_list data type.
3867 We keep 3 pointers, and two offsets.
3868 Two pointers are to the overflow area, which starts at the CFA.
3869 One of these is constant, for addressing into the GPR save area below it.
3870 The other is advanced up the stack through the overflow region.
3871 The third pointer is to the GPR save area. Since the FPR save area
3872 is just below it, we can address FPR slots off this pointer.
3873 We also keep two one-byte offsets, which are to be subtracted from the
3874 constant pointers to yield addresses in the GPR and FPR save areas.
3875 These are downcounted as float or non-float arguments are used,
3876 and when they get to zero, the argument must be obtained from the
3878 If !EABI_FLOAT_VARARGS_P, then no FPR save area exists, and a single
3879 pointer is enough. It's started at the GPR save area, and is
3881 Note that the GPR save area is not constant size, due to optimization
3882 in the prologue. Hence, we can't use a design with two pointers
3883 and two offsets, although we could have designed this with two pointers
3884 and three offsets. */
3887 mips_build_builtin_va_list (void)
3889 if (EABI_FLOAT_VARARGS_P)
3891 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
3894 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
3896 f_ovfl = build_decl (FIELD_DECL, get_identifier ("__overflow_argptr"),
3898 f_gtop = build_decl (FIELD_DECL, get_identifier ("__gpr_top"),
3900 f_ftop = build_decl (FIELD_DECL, get_identifier ("__fpr_top"),
3902 f_goff = build_decl (FIELD_DECL, get_identifier ("__gpr_offset"),
3903 unsigned_char_type_node);
3904 f_foff = build_decl (FIELD_DECL, get_identifier ("__fpr_offset"),
3905 unsigned_char_type_node);
3906 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
3907 warn on every user file. */
3908 index = build_int_2 (GET_MODE_SIZE (ptr_mode) - 2 - 1, 0);
3909 array = build_array_type (unsigned_char_type_node,
3910 build_index_type (index));
3911 f_res = build_decl (FIELD_DECL, get_identifier ("__reserved"), array);
3913 DECL_FIELD_CONTEXT (f_ovfl) = record;
3914 DECL_FIELD_CONTEXT (f_gtop) = record;
3915 DECL_FIELD_CONTEXT (f_ftop) = record;
3916 DECL_FIELD_CONTEXT (f_goff) = record;
3917 DECL_FIELD_CONTEXT (f_foff) = record;
3918 DECL_FIELD_CONTEXT (f_res) = record;
3920 TYPE_FIELDS (record) = f_ovfl;
3921 TREE_CHAIN (f_ovfl) = f_gtop;
3922 TREE_CHAIN (f_gtop) = f_ftop;
3923 TREE_CHAIN (f_ftop) = f_goff;
3924 TREE_CHAIN (f_goff) = f_foff;
3925 TREE_CHAIN (f_foff) = f_res;
3927 layout_type (record);
3930 else if (TARGET_IRIX && !TARGET_IRIX5)
3931 /* On IRIX 6, this type is 'char *'. */
3932 return build_pointer_type (char_type_node);
3934 /* Otherwise, we use 'void *'. */
3935 return ptr_type_node;
3938 /* Implement va_start. */
3941 mips_va_start (tree valist, rtx nextarg)
3943 const CUMULATIVE_ARGS *cum = ¤t_function_args_info;
3945 /* ARG_POINTER_REGNUM is initialized to STACK_POINTER_BOUNDARY, but
3946 since the stack is aligned for a pair of argument-passing slots,
3947 and the beginning of a variable argument list may be an odd slot,
3948 we have to decrease its alignment. */
3949 if (cfun && cfun->emit->regno_pointer_align)
3950 while (((current_function_pretend_args_size * BITS_PER_UNIT)
3951 & (REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) - 1)) != 0)
3952 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) /= 2;
3954 if (mips_abi == ABI_EABI)
3956 int gpr_save_area_size;
3959 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
3961 if (EABI_FLOAT_VARARGS_P)
3963 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
3964 tree ovfl, gtop, ftop, goff, foff;
3967 int fpr_save_area_size;
3969 f_ovfl = TYPE_FIELDS (va_list_type_node);
3970 f_gtop = TREE_CHAIN (f_ovfl);
3971 f_ftop = TREE_CHAIN (f_gtop);
3972 f_goff = TREE_CHAIN (f_ftop);
3973 f_foff = TREE_CHAIN (f_goff);
3975 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
3977 gtop = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
3979 ftop = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
3981 goff = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
3983 foff = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
3986 /* Emit code to initialize OVFL, which points to the next varargs
3987 stack argument. CUM->STACK_WORDS gives the number of stack
3988 words used by named arguments. */
3989 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
3990 if (cum->stack_words > 0)
3991 t = build (PLUS_EXPR, TREE_TYPE (ovfl), t,
3992 build_int_2 (cum->stack_words * UNITS_PER_WORD, 0));
3993 t = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
3994 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
3996 /* Emit code to initialize GTOP, the top of the GPR save area. */
3997 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
3998 t = build (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
3999 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4001 /* Emit code to initialize FTOP, the top of the FPR save area.
4002 This address is gpr_save_area_bytes below GTOP, rounded
4003 down to the next fp-aligned boundary. */
4004 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
4005 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
4006 fpr_offset &= ~(UNITS_PER_FPVALUE - 1);
4008 t = build (PLUS_EXPR, TREE_TYPE (ftop), t,
4009 build_int_2 (-fpr_offset, -1));
4010 t = build (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
4011 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4013 /* Emit code to initialize GOFF, the offset from GTOP of the
4014 next GPR argument. */
4015 t = build (MODIFY_EXPR, TREE_TYPE (goff), goff,
4016 build_int_2 (gpr_save_area_size, 0));
4017 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4019 /* Likewise emit code to initialize FOFF, the offset from FTOP
4020 of the next FPR argument. */
4022 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
4023 t = build (MODIFY_EXPR, TREE_TYPE (foff), foff,
4024 build_int_2 (fpr_save_area_size, 0));
4025 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4029 /* Everything is in the GPR save area, or in the overflow
4030 area which is contiguous with it. */
4031 nextarg = plus_constant (nextarg, -gpr_save_area_size);
4032 std_expand_builtin_va_start (valist, nextarg);
4036 std_expand_builtin_va_start (valist, nextarg);
4039 /* Implement va_arg. */
4042 mips_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
4044 HOST_WIDE_INT size, rsize;
4049 = function_arg_pass_by_reference (NULL, TYPE_MODE (type), type, 0);
4052 type = build_pointer_type (type);
4054 size = int_size_in_bytes (type);
4055 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
4057 if (mips_abi != ABI_EABI || !EABI_FLOAT_VARARGS_P)
4058 addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
4061 /* Not a simple merged stack. */
4063 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
4064 tree ovfl, top, off, align;
4065 HOST_WIDE_INT osize;
4068 f_ovfl = TYPE_FIELDS (va_list_type_node);
4069 f_gtop = TREE_CHAIN (f_ovfl);
4070 f_ftop = TREE_CHAIN (f_gtop);
4071 f_goff = TREE_CHAIN (f_ftop);
4072 f_foff = TREE_CHAIN (f_goff);
4074 /* We maintain separate pointers and offsets for floating-point
4075 and integer arguments, but we need similar code in both cases.
4078 TOP be the top of the register save area;
4079 OFF be the offset from TOP of the next register;
4080 ADDR_RTX be the address of the argument;
4081 RSIZE be the number of bytes used to store the argument
4082 when it's in the register save area;
4083 OSIZE be the number of bytes used to store it when it's
4084 in the stack overflow area; and
4085 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
4087 The code we want is:
4089 1: off &= -rsize; // round down
4092 4: addr_rtx = top - off;
4097 9: ovfl += ((intptr_t) ovfl + osize - 1) & -osize;
4098 10: addr_rtx = ovfl + PADDING;
4102 [1] and [9] can sometimes be optimized away. */
4104 ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
4107 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
4108 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
4110 top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
4112 off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
4115 /* When floating-point registers are saved to the stack,
4116 each one will take up UNITS_PER_HWFPVALUE bytes, regardless
4117 of the float's precision. */
4118 rsize = UNITS_PER_HWFPVALUE;
4120 /* Overflow arguments are padded to UNITS_PER_WORD bytes
4121 (= PARM_BOUNDARY bits). This can be different from RSIZE
4124 (1) On 32-bit targets when TYPE is a structure such as:
4126 struct s { float f; };
4128 Such structures are passed in paired FPRs, so RSIZE
4129 will be 8 bytes. However, the structure only takes
4130 up 4 bytes of memory, so OSIZE will only be 4.
4132 (2) In combinations such as -mgp64 -msingle-float
4133 -fshort-double. Doubles passed in registers
4134 will then take up 4 (UNITS_PER_HWFPVALUE) bytes,
4135 but those passed on the stack take up
4136 UNITS_PER_WORD bytes. */
4137 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
4141 top = build (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
4143 off = build (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
4145 if (rsize > UNITS_PER_WORD)
4147 /* [1] Emit code for: off &= -rsize. */
4148 t = build (BIT_AND_EXPR, TREE_TYPE (off), off,
4149 build_int_2 (-rsize, -1));
4150 t = build (MODIFY_EXPR, TREE_TYPE (off), off, t);
4151 gimplify_and_add (t, pre_p);
4156 /* [2] Emit code to branch if off == 0. */
4157 t = lang_hooks.truthvalue_conversion (off);
4158 addr = build (COND_EXPR, ptr_type_node, t, NULL, NULL);
4160 /* [5] Emit code for: off -= rsize. We do this as a form of
4161 post-increment not available to C. Also widen for the
4162 coming pointer arithmetic. */
4163 t = fold_convert (TREE_TYPE (off), build_int_2 (rsize, 0));
4164 t = build (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
4165 t = fold_convert (sizetype, t);
4166 t = fold_convert (TREE_TYPE (top), t);
4168 /* [4] Emit code for: addr_rtx = top - off. On big endian machines,
4169 the argument has RSIZE - SIZE bytes of leading padding. */
4170 t = build (MINUS_EXPR, TREE_TYPE (top), top, t);
4171 if (BYTES_BIG_ENDIAN && rsize > size)
4173 u = fold_convert (TREE_TYPE (t), build_int_2 (rsize - size, 0));
4174 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4176 COND_EXPR_THEN (addr) = t;
4178 if (osize > UNITS_PER_WORD)
4180 /* [9] Emit: ovfl += ((intptr_t) ovfl + osize - 1) & -osize. */
4181 u = fold_convert (TREE_TYPE (ovfl), build_int_2 (osize - 1, 0));
4182 t = build (PLUS_EXPR, TREE_TYPE (ovfl), ovfl, u);
4183 u = fold_convert (TREE_TYPE (ovfl), build_int_2 (-osize, -1));
4184 t = build (BIT_AND_EXPR, TREE_TYPE (ovfl), t, u);
4185 align = build (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
4190 /* [10, 11]. Emit code to store ovfl in addr_rtx, then
4191 post-increment ovfl by osize. On big-endian machines,
4192 the argument has OSIZE - SIZE bytes of leading padding. */
4193 u = fold_convert (TREE_TYPE (ovfl), build_int_2 (osize, 0));
4194 t = build (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
4195 if (BYTES_BIG_ENDIAN && osize > size)
4197 u = fold_convert (TREE_TYPE (t), build_int_2 (osize - size, 0));
4198 t = build (PLUS_EXPR, TREE_TYPE (t), t, u);
4201 /* String [9] and [10,11] together. */
4203 t = build (COMPOUND_EXPR, TREE_TYPE (t), align, t);
4204 COND_EXPR_ELSE (addr) = t;
4206 addr = fold_convert (build_pointer_type (type), addr);
4207 addr = build_fold_indirect_ref (addr);
4211 addr = build_fold_indirect_ref (addr);
4216 /* Return true if it is possible to use left/right accesses for a
4217 bitfield of WIDTH bits starting BITPOS bits into *OP. When
4218 returning true, update *OP, *LEFT and *RIGHT as follows:
4220 *OP is a BLKmode reference to the whole field.
4222 *LEFT is a QImode reference to the first byte if big endian or
4223 the last byte if little endian. This address can be used in the
4224 left-side instructions (lwl, swl, ldl, sdl).
4226 *RIGHT is a QImode reference to the opposite end of the field and
4227 can be used in the parterning right-side instruction. */
4230 mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
4231 rtx *left, rtx *right)
4235 /* Check that the operand really is a MEM. Not all the extv and
4236 extzv predicates are checked. */
4237 if (GET_CODE (*op) != MEM)
4240 /* Check that the size is valid. */
4241 if (width != 32 && (!TARGET_64BIT || width != 64))
4244 /* We can only access byte-aligned values. Since we are always passed
4245 a reference to the first byte of the field, it is not necessary to
4246 do anything with BITPOS after this check. */
4247 if (bitpos % BITS_PER_UNIT != 0)
4250 /* Reject aligned bitfields: we want to use a normal load or store
4251 instead of a left/right pair. */
4252 if (MEM_ALIGN (*op) >= width)
4255 /* Adjust *OP to refer to the whole field. This also has the effect
4256 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
4257 *op = adjust_address (*op, BLKmode, 0);
4258 set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
4260 /* Get references to both ends of the field. We deliberately don't
4261 use the original QImode *OP for FIRST since the new BLKmode one
4262 might have a simpler address. */
4263 first = adjust_address (*op, QImode, 0);
4264 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
4266 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
4267 be the upper word and RIGHT the lower word. */
4268 if (TARGET_BIG_ENDIAN)
4269 *left = first, *right = last;
4271 *left = last, *right = first;
4277 /* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
4278 Return true on success. We only handle cases where zero_extract is
4279 equivalent to sign_extract. */
4282 mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
4284 rtx left, right, temp;
4286 /* If TARGET_64BIT, the destination of a 32-bit load will be a
4287 paradoxical word_mode subreg. This is the only case in which
4288 we allow the destination to be larger than the source. */
4289 if (GET_CODE (dest) == SUBREG
4290 && GET_MODE (dest) == DImode
4291 && SUBREG_BYTE (dest) == 0
4292 && GET_MODE (SUBREG_REG (dest)) == SImode)
4293 dest = SUBREG_REG (dest);
4295 /* After the above adjustment, the destination must be the same
4296 width as the source. */
4297 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
4300 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
4303 temp = gen_reg_rtx (GET_MODE (dest));
4304 if (GET_MODE (dest) == DImode)
4306 emit_insn (gen_mov_ldl (temp, src, left));
4307 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
4311 emit_insn (gen_mov_lwl (temp, src, left));
4312 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
4318 /* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC). Return
4322 mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
4326 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
4329 src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
4331 if (GET_MODE (src) == DImode)
4333 emit_insn (gen_mov_sdl (dest, src, left));
4334 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
4338 emit_insn (gen_mov_swl (dest, src, left));
4339 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
4344 /* Set up globals to generate code for the ISA or processor
4345 described by INFO. */
4348 mips_set_architecture (const struct mips_cpu_info *info)
4352 mips_arch_info = info;
4353 mips_arch = info->cpu;
4354 mips_isa = info->isa;
4359 /* Likewise for tuning. */
4362 mips_set_tune (const struct mips_cpu_info *info)
4366 mips_tune_info = info;
4367 mips_tune = info->cpu;
4372 /* Set up the threshold for data to go into the small data area, instead
4373 of the normal data area, and detect any conflicts in the switches. */
4376 override_options (void)
4378 int i, start, regno;
4379 enum machine_mode mode;
4381 mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
4383 /* Interpret -mabi. */
4384 mips_abi = MIPS_ABI_DEFAULT;
4385 if (mips_abi_string != 0)
4387 if (strcmp (mips_abi_string, "32") == 0)
4389 else if (strcmp (mips_abi_string, "o64") == 0)
4391 else if (strcmp (mips_abi_string, "n32") == 0)
4393 else if (strcmp (mips_abi_string, "64") == 0)
4395 else if (strcmp (mips_abi_string, "eabi") == 0)
4396 mips_abi = ABI_EABI;
4398 fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
4401 /* The following code determines the architecture and register size.
4402 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
4403 The GAS and GCC code should be kept in sync as much as possible. */
4405 if (mips_arch_string != 0)
4406 mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
4408 if (mips_isa_string != 0)
4410 /* Handle -mipsN. */
4411 char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
4412 const struct mips_cpu_info *isa_info;
4414 isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
4415 free (whole_isa_str);
4417 /* -march takes precedence over -mipsN, since it is more descriptive.
4418 There's no harm in specifying both as long as the ISA levels
4420 if (mips_arch_info != 0 && mips_isa != isa_info->isa)
4421 error ("-mips%s conflicts with the other architecture options, "
4422 "which specify a MIPS%d processor",
4423 mips_isa_string, mips_isa);
4425 /* Set architecture based on the given option. */
4426 mips_set_architecture (isa_info);
4429 if (mips_arch_info == 0)
4431 #ifdef MIPS_CPU_STRING_DEFAULT
4432 mips_set_architecture (mips_parse_cpu ("default CPU",
4433 MIPS_CPU_STRING_DEFAULT));
4435 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
4439 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
4440 error ("-march=%s is not compatible with the selected ABI",
4441 mips_arch_info->name);
4443 /* Optimize for mips_arch, unless -mtune selects a different processor. */
4444 if (mips_tune_string != 0)
4445 mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
4447 if (mips_tune_info == 0)
4448 mips_set_tune (mips_arch_info);
4450 if ((target_flags_explicit & MASK_64BIT) != 0)
4452 /* The user specified the size of the integer registers. Make sure
4453 it agrees with the ABI and ISA. */
4454 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
4455 error ("-mgp64 used with a 32-bit processor");
4456 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
4457 error ("-mgp32 used with a 64-bit ABI");
4458 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
4459 error ("-mgp64 used with a 32-bit ABI");
4463 /* Infer the integer register size from the ABI and processor.
4464 Restrict ourselves to 32-bit registers if that's all the
4465 processor has, or if the ABI cannot handle 64-bit registers. */
4466 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
4467 target_flags &= ~MASK_64BIT;
4469 target_flags |= MASK_64BIT;
4472 if ((target_flags_explicit & MASK_FLOAT64) != 0)
4474 /* Really, -mfp32 and -mfp64 are ornamental options. There's
4475 only one right answer here. */
4476 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
4477 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
4478 else if (!TARGET_64BIT && TARGET_FLOAT64)
4479 error ("unsupported combination: %s", "-mgp32 -mfp64");
4480 else if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
4481 error ("unsupported combination: %s", "-mfp64 -msingle-float");
4485 /* -msingle-float selects 32-bit float registers. Otherwise the
4486 float registers should be the same size as the integer ones. */
4487 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
4488 target_flags |= MASK_FLOAT64;
4490 target_flags &= ~MASK_FLOAT64;
4493 /* End of code shared with GAS. */
4495 if ((target_flags_explicit & MASK_LONG64) == 0)
4497 /* If no type size setting options (-mlong64,-mint64,-mlong32)
4498 were used, then set the type sizes. In the EABI in 64 bit mode,
4499 longs and pointers are 64 bits. Likewise for the SGI Irix6 N64
4501 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
4502 target_flags |= MASK_LONG64;
4504 target_flags &= ~MASK_LONG64;
4507 if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
4508 && (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
4510 /* For some configurations, it is useful to have -march control
4511 the default setting of MASK_SOFT_FLOAT. */
4512 switch ((int) mips_arch)
4514 case PROCESSOR_R4100:
4515 case PROCESSOR_R4111:
4516 case PROCESSOR_R4120:
4517 case PROCESSOR_R4130:
4518 target_flags |= MASK_SOFT_FLOAT;
4522 target_flags &= ~MASK_SOFT_FLOAT;
4528 flag_pcc_struct_return = 0;
4530 #if defined(USE_COLLECT2)
4531 /* For IRIX 5 or IRIX 6 with integrated O32 ABI support, USE_COLLECT2 is
4532 always defined when GNU as is not in use, but collect2 is only used
4533 for the O32 ABI, so override the toplev.c and target-def.h defaults
4534 for flag_gnu_linker, TARGET_ASM_{CONSTRUCTOR, DESTRUCTOR} and
4535 TARGET_HAVE_CTORS_DTORS.
4537 Since the IRIX 5 and IRIX 6 O32 assemblers cannot handle named
4538 sections, constructor/destructor handling depends on the ABI in use.
4540 Since USE_COLLECT2 is defined, we only need to restore the non-collect2
4541 defaults for the N32/N64 ABIs. */
4542 if (TARGET_IRIX && !TARGET_SGI_O32_AS)
4544 targetm.have_ctors_dtors = true;
4545 targetm.asm_out.constructor = default_named_section_asm_out_constructor;
4546 targetm.asm_out.destructor = default_named_section_asm_out_destructor;
4550 /* Handle some quirks of the IRIX 5 and IRIX 6 O32 assemblers. */
4552 if (TARGET_SGI_O32_AS)
4554 /* They don't recognize `.[248]byte'. */
4555 targetm.asm_out.unaligned_op.hi = "\t.align 0\n\t.half\t";
4556 targetm.asm_out.unaligned_op.si = "\t.align 0\n\t.word\t";
4557 /* The IRIX 6 O32 assembler gives an error for `align 0; .dword',
4558 contrary to the documentation, so disable it. */
4559 targetm.asm_out.unaligned_op.di = NULL;
4561 /* They cannot handle named sections. */
4562 targetm.have_named_sections = false;
4563 /* Therefore, EH_FRAME_SECTION_NAME isn't defined and we must use
4565 targetm.terminate_dw2_eh_frame_info = true;
4566 targetm.asm_out.eh_frame_section = collect2_eh_frame_section;
4568 /* They cannot handle debug information. */
4569 if (write_symbols != NO_DEBUG)
4571 /* Adapt wording to IRIX version: IRIX 5 only had a single ABI,
4572 so -mabi=32 isn't usually specified. */
4574 inform ("-g is only supported using GNU as,");
4576 inform ("-g is only supported using GNU as with -mabi=32,");
4577 inform ("-g option disabled");
4578 write_symbols = NO_DEBUG;
4582 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
4584 /* If neither -mbranch-likely nor -mno-branch-likely was given
4585 on the command line, set MASK_BRANCHLIKELY based on the target
4588 By default, we enable use of Branch Likely instructions on
4589 all architectures which support them with the following
4590 exceptions: when creating MIPS32 or MIPS64 code, and when
4591 tuning for architectures where their use tends to hurt
4594 The MIPS32 and MIPS64 architecture specifications say "Software
4595 is strongly encouraged to avoid use of Branch Likely
4596 instructions, as they will be removed from a future revision
4597 of the [MIPS32 and MIPS64] architecture." Therefore, we do not
4598 issue those instructions unless instructed to do so by
4600 if (ISA_HAS_BRANCHLIKELY
4601 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
4602 && !(TUNE_MIPS5500 || TUNE_SB1))
4603 target_flags |= MASK_BRANCHLIKELY;
4605 target_flags &= ~MASK_BRANCHLIKELY;
4607 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
4608 warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
4610 /* The effect of -mabicalls isn't defined for the EABI. */
4611 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
4613 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
4614 target_flags &= ~MASK_ABICALLS;
4617 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4618 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4619 /* ??? -non_shared turns off pic code generation, but this is not
4621 if (TARGET_ABICALLS)
4624 if (mips_section_threshold > 0)
4625 warning ("-G is incompatible with PIC code which is the default");
4628 /* The MIPS and SGI o32 assemblers expect small-data variables to
4629 be declared before they are used. Although we once had code to
4630 do this, it was very invasive and fragile. It no longer seems
4631 worth the effort. */
4632 if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
4633 mips_section_threshold = 0;
4635 /* We switch to small data sections using ".section", which the native
4636 o32 irix assemblers don't understand. Disable -G accordingly.
4637 We must do this regardless of command-line options since otherwise
4638 the compiler would abort. */
4639 if (!targetm.have_named_sections)
4640 mips_section_threshold = 0;
4642 /* mips_split_addresses is a half-way house between explicit
4643 relocations and the traditional assembler macros. It can
4644 split absolute 32-bit symbolic constants into a high/lo_sum
4645 pair but uses macros for other sorts of access.
4647 Like explicit relocation support for REL targets, it relies
4648 on GNU extensions in the assembler and the linker.
4650 Although this code should work for -O0, it has traditionally
4651 been treated as an optimization. */
4652 if (TARGET_GAS && !TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES
4653 && optimize && !flag_pic
4654 && !ABI_HAS_64BIT_SYMBOLS)
4655 mips_split_addresses = 1;
4657 mips_split_addresses = 0;
4659 /* Explicit relocations for "old" ABIs are a GNU extension. Unless
4660 the user has said otherwise, assume that they are not available
4661 with assemblers other than gas. */
4662 if (!TARGET_NEWABI && !TARGET_GAS
4663 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4664 target_flags &= ~MASK_EXPLICIT_RELOCS;
4666 /* Make -mabicalls -fno-unit-at-a-time imply -mno-explicit-relocs
4667 unless the user says otherwise.
4669 There are two problems here:
4671 (1) The value of an R_MIPS_GOT16 relocation depends on whether
4672 the symbol is local or global. We therefore need to know
4673 a symbol's binding before referring to it using %got().
4675 (2) R_MIPS_CALL16 can only be applied to global symbols.
4677 When not using -funit-at-a-time, a symbol's binding may change
4678 after it has been used. For example, the C++ front-end will
4679 initially assume that the typeinfo for an incomplete type will be
4680 comdat, on the basis that the type could be completed later in the
4681 file. But if the type never is completed, the typeinfo will become
4683 if (!flag_unit_at_a_time
4685 && (target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
4686 target_flags &= ~MASK_EXPLICIT_RELOCS;
4688 /* -mvr4130-align is a "speed over size" optimization: it usually produces
4689 faster code, but at the expense of more nops. Enable it at -O3 and
4691 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
4692 target_flags |= MASK_VR4130_ALIGN;
4694 /* When compiling for the mips16, we can not use floating point. We
4695 record the original hard float value in mips16_hard_float. */
4698 if (TARGET_SOFT_FLOAT)
4699 mips16_hard_float = 0;
4701 mips16_hard_float = 1;
4702 target_flags |= MASK_SOFT_FLOAT;
4704 /* Don't run the scheduler before reload, since it tends to
4705 increase register pressure. */
4706 flag_schedule_insns = 0;
4708 /* Silently disable -mexplicit-relocs since it doesn't apply
4709 to mips16 code. Even so, it would overly pedantic to warn
4710 about "-mips16 -mexplicit-relocs", especially given that
4711 we use a %gprel() operator. */
4712 target_flags &= ~MASK_EXPLICIT_RELOCS;
4715 /* When using explicit relocs, we call dbr_schedule from within
4717 if (TARGET_EXPLICIT_RELOCS)
4719 mips_flag_delayed_branch = flag_delayed_branch;
4720 flag_delayed_branch = 0;
4723 #ifdef MIPS_TFMODE_FORMAT
4724 REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT;
4727 mips_print_operand_punct['?'] = 1;
4728 mips_print_operand_punct['#'] = 1;
4729 mips_print_operand_punct['/'] = 1;
4730 mips_print_operand_punct['&'] = 1;
4731 mips_print_operand_punct['!'] = 1;
4732 mips_print_operand_punct['*'] = 1;
4733 mips_print_operand_punct['@'] = 1;
4734 mips_print_operand_punct['.'] = 1;
4735 mips_print_operand_punct['('] = 1;
4736 mips_print_operand_punct[')'] = 1;
4737 mips_print_operand_punct['['] = 1;
4738 mips_print_operand_punct[']'] = 1;
4739 mips_print_operand_punct['<'] = 1;
4740 mips_print_operand_punct['>'] = 1;
4741 mips_print_operand_punct['{'] = 1;
4742 mips_print_operand_punct['}'] = 1;
4743 mips_print_operand_punct['^'] = 1;
4744 mips_print_operand_punct['$'] = 1;
4745 mips_print_operand_punct['+'] = 1;
4746 mips_print_operand_punct['~'] = 1;
4748 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4749 mips_char_to_class['t'] = T_REG;
4750 mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
4751 mips_char_to_class['h'] = HI_REG;
4752 mips_char_to_class['l'] = LO_REG;
4753 mips_char_to_class['x'] = MD_REGS;
4754 mips_char_to_class['b'] = ALL_REGS;
4755 mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
4756 TARGET_MIPS16 ? M16_NA_REGS :
4758 mips_char_to_class['e'] = LEA_REGS;
4759 mips_char_to_class['j'] = PIC_FN_ADDR_REG;
4760 mips_char_to_class['y'] = GR_REGS;
4761 mips_char_to_class['z'] = ST_REGS;
4762 mips_char_to_class['B'] = COP0_REGS;
4763 mips_char_to_class['C'] = COP2_REGS;
4764 mips_char_to_class['D'] = COP3_REGS;
4766 /* Set up array to map GCC register number to debug register number.
4767 Ignore the special purpose register numbers. */
4769 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4770 mips_dbx_regno[i] = -1;
4772 start = GP_DBX_FIRST - GP_REG_FIRST;
4773 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4774 mips_dbx_regno[i] = i + start;
4776 start = FP_DBX_FIRST - FP_REG_FIRST;
4777 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4778 mips_dbx_regno[i] = i + start;
4780 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
4781 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
4783 /* Set up array giving whether a given register can hold a given mode. */
4785 for (mode = VOIDmode;
4786 mode != MAX_MACHINE_MODE;
4787 mode = (enum machine_mode) ((int)mode + 1))
4789 register int size = GET_MODE_SIZE (mode);
4790 register enum mode_class class = GET_MODE_CLASS (mode);
4792 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4799 temp = (regno == FPSW_REGNUM);
4801 temp = (ST_REG_P (regno) || GP_REG_P (regno)
4802 || FP_REG_P (regno));
4805 else if (GP_REG_P (regno))
4806 temp = ((regno & 1) == 0 || size <= UNITS_PER_WORD);
4808 else if (FP_REG_P (regno))
4809 temp = ((regno % FP_INC) == 0)
4810 && (((class == MODE_FLOAT || class == MODE_COMPLEX_FLOAT)
4811 && size <= UNITS_PER_FPVALUE)
4812 /* Allow integer modes that fit into a single
4813 register. We need to put integers into FPRs
4814 when using instructions like cvt and trunc. */
4815 || (class == MODE_INT && size <= UNITS_PER_FPREG)
4816 /* Allow TFmode for CCmode reloads. */
4817 || (ISA_HAS_8CC && mode == TFmode));
4819 else if (MD_REG_P (regno))
4820 temp = (INTEGRAL_MODE_P (mode)
4821 && (size <= UNITS_PER_WORD
4822 || (regno == MD_REG_FIRST
4823 && size == 2 * UNITS_PER_WORD)));
4825 else if (ALL_COP_REG_P (regno))
4826 temp = (class == MODE_INT && size <= UNITS_PER_WORD);
4830 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4834 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
4835 initialized yet, so we can't use that here. */
4836 gpr_mode = TARGET_64BIT ? DImode : SImode;
4838 /* Provide default values for align_* for 64-bit targets. */
4839 if (TARGET_64BIT && !TARGET_MIPS16)
4841 if (align_loops == 0)
4843 if (align_jumps == 0)
4845 if (align_functions == 0)
4846 align_functions = 8;
4849 /* Function to allocate machine-dependent function status. */
4850 init_machine_status = &mips_init_machine_status;
4852 if (ABI_HAS_64BIT_SYMBOLS)
4854 if (TARGET_EXPLICIT_RELOCS)
4856 mips_split_p[SYMBOL_64_HIGH] = true;
4857 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
4858 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
4860 mips_split_p[SYMBOL_64_MID] = true;
4861 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
4862 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
4864 mips_split_p[SYMBOL_64_LOW] = true;
4865 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
4866 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
4868 mips_split_p[SYMBOL_GENERAL] = true;
4869 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4874 if (TARGET_EXPLICIT_RELOCS || mips_split_addresses)
4876 mips_split_p[SYMBOL_GENERAL] = true;
4877 mips_hi_relocs[SYMBOL_GENERAL] = "%hi(";
4878 mips_lo_relocs[SYMBOL_GENERAL] = "%lo(";
4884 /* The high part is provided by a pseudo copy of $gp. */
4885 mips_split_p[SYMBOL_SMALL_DATA] = true;
4886 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gprel(";
4889 if (TARGET_EXPLICIT_RELOCS)
4891 /* Small data constants are kept whole until after reload,
4892 then lowered by mips_rewrite_small_data. */
4893 mips_lo_relocs[SYMBOL_SMALL_DATA] = "%gp_rel(";
4895 mips_split_p[SYMBOL_GOT_LOCAL] = true;
4898 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
4899 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%got_ofst(";
4903 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
4904 mips_lo_relocs[SYMBOL_GOT_LOCAL] = "%lo(";
4909 /* The HIGH and LO_SUM are matched by special .md patterns. */
4910 mips_split_p[SYMBOL_GOT_GLOBAL] = true;
4912 mips_split_p[SYMBOL_GOTOFF_GLOBAL] = true;
4913 mips_hi_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_hi(";
4914 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_lo(";
4916 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
4917 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
4918 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
4923 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got_disp(";
4925 mips_lo_relocs[SYMBOL_GOTOFF_GLOBAL] = "%got(";
4926 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
4932 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
4933 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
4934 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
4937 /* Default to working around R4000 errata only if the processor
4938 was selected explicitly. */
4939 if ((target_flags_explicit & MASK_FIX_R4000) == 0
4940 && mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
4941 target_flags |= MASK_FIX_R4000;
4943 /* Default to working around R4400 errata only if the processor
4944 was selected explicitly. */
4945 if ((target_flags_explicit & MASK_FIX_R4400) == 0
4946 && mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
4947 target_flags |= MASK_FIX_R4400;
4950 /* Implement CONDITIONAL_REGISTER_USAGE. */
4953 mips_conditional_register_usage (void)
4955 if (!TARGET_HARD_FLOAT)
4959 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
4960 fixed_regs[regno] = call_used_regs[regno] = 1;
4961 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4962 fixed_regs[regno] = call_used_regs[regno] = 1;
4964 else if (! ISA_HAS_8CC)
4968 /* We only have a single condition code register. We
4969 implement this by hiding all the condition code registers,
4970 and generating RTL that refers directly to ST_REG_FIRST. */
4971 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++)
4972 fixed_regs[regno] = call_used_regs[regno] = 1;
4974 /* In mips16 mode, we permit the $t temporary registers to be used
4975 for reload. We prohibit the unused $s registers, since they
4976 are caller saved, and saving them via a mips16 register would
4977 probably waste more time than just reloading the value. */
4980 fixed_regs[18] = call_used_regs[18] = 1;
4981 fixed_regs[19] = call_used_regs[19] = 1;
4982 fixed_regs[20] = call_used_regs[20] = 1;
4983 fixed_regs[21] = call_used_regs[21] = 1;
4984 fixed_regs[22] = call_used_regs[22] = 1;
4985 fixed_regs[23] = call_used_regs[23] = 1;
4986 fixed_regs[26] = call_used_regs[26] = 1;
4987 fixed_regs[27] = call_used_regs[27] = 1;
4988 fixed_regs[30] = call_used_regs[30] = 1;
4990 /* fp20-23 are now caller saved. */
4991 if (mips_abi == ABI_64)
4994 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
4995 call_really_used_regs[regno] = call_used_regs[regno] = 1;
4997 /* Odd registers from fp21 to fp31 are now caller saved. */
4998 if (mips_abi == ABI_N32)
5001 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
5002 call_really_used_regs[regno] = call_used_regs[regno] = 1;
5006 /* Allocate a chunk of memory for per-function machine-dependent data. */
5007 static struct machine_function *
5008 mips_init_machine_status (void)
5010 return ((struct machine_function *)
5011 ggc_alloc_cleared (sizeof (struct machine_function)));
5014 /* On the mips16, we want to allocate $24 (T_REG) before other
5015 registers for instructions for which it is possible. This helps
5016 avoid shuffling registers around in order to set up for an xor,
5017 encouraging the compiler to use a cmp instead. */
5020 mips_order_regs_for_local_alloc (void)
5024 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
5025 reg_alloc_order[i] = i;
5029 /* It really doesn't matter where we put register 0, since it is
5030 a fixed register anyhow. */
5031 reg_alloc_order[0] = 24;
5032 reg_alloc_order[24] = 0;
5037 /* The MIPS debug format wants all automatic variables and arguments
5038 to be in terms of the virtual frame pointer (stack pointer before
5039 any adjustment in the function), while the MIPS 3.0 linker wants
5040 the frame pointer to be the stack pointer after the initial
5041 adjustment. So, we do the adjustment here. The arg pointer (which
5042 is eliminated) points to the virtual frame pointer, while the frame
5043 pointer (which may be eliminated) points to the stack pointer after
5044 the initial adjustments. */
5047 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
5049 rtx offset2 = const0_rtx;
5050 rtx reg = eliminate_constant_term (addr, &offset2);
5053 offset = INTVAL (offset2);
5055 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
5056 || reg == hard_frame_pointer_rtx)
5058 HOST_WIDE_INT frame_size = (!cfun->machine->frame.initialized)
5059 ? compute_frame_size (get_frame_size ())
5060 : cfun->machine->frame.total_size;
5062 /* MIPS16 frame is smaller */
5063 if (frame_pointer_needed && TARGET_MIPS16)
5064 frame_size -= cfun->machine->frame.args_size;
5066 offset = offset - frame_size;
5069 /* sdbout_parms does not want this to crash for unrecognized cases. */
5071 else if (reg != arg_pointer_rtx)
5072 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
5079 /* Implement the PRINT_OPERAND macro. The MIPS-specific operand codes are:
5081 'X' OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
5082 'x' OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
5083 'h' OP is HIGH, prints %hi(X),
5084 'd' output integer constant in decimal,
5085 'z' if the operand is 0, use $0 instead of normal operand.
5086 'D' print second part of double-word register or memory operand.
5087 'L' print low-order register of double-word register operand.
5088 'M' print high-order register of double-word register operand.
5089 'C' print part of opcode for a branch condition.
5090 'F' print part of opcode for a floating-point branch condition.
5091 'N' print part of opcode for a branch condition, inverted.
5092 'W' print part of opcode for a floating-point branch condition, inverted.
5093 'B' print 'z' for EQ, 'n' for NE
5094 'b' print 'n' for EQ, 'z' for NE
5095 'T' print 'f' for EQ, 't' for NE
5096 't' print 't' for EQ, 'f' for NE
5097 'Z' print register and a comma, but print nothing for $fcc0
5098 'R' print the reloc associated with LO_SUM
5100 The punctuation characters are:
5102 '(' Turn on .set noreorder
5103 ')' Turn on .set reorder
5104 '[' Turn on .set noat
5106 '<' Turn on .set nomacro
5107 '>' Turn on .set macro
5108 '{' Turn on .set volatile (not GAS)
5109 '}' Turn on .set novolatile (not GAS)
5110 '&' Turn on .set noreorder if filling delay slots
5111 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
5112 '!' Turn on .set nomacro if filling delay slots
5113 '#' Print nop if in a .set noreorder section.
5114 '/' Like '#', but does nothing within a delayed branch sequence
5115 '?' Print 'l' if we are to use a branch likely instead of normal branch.
5116 '@' Print the name of the assembler temporary register (at or $1).
5117 '.' Print the name of the register with a hard-wired zero (zero or $0).
5118 '^' Print the name of the pic call-through register (t9 or $25).
5119 '$' Print the name of the stack pointer register (sp or $29).
5120 '+' Print the name of the gp register (usually gp or $28).
5121 '~' Output a branch alignment to LABEL_ALIGN(NULL). */
5124 print_operand (FILE *file, rtx op, int letter)
5126 register enum rtx_code code;
5128 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
5133 if (mips_branch_likely)
5138 fputs (reg_names [GP_REG_FIRST + 1], file);
5142 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
5146 fputs (reg_names [GP_REG_FIRST + 0], file);
5150 fputs (reg_names[STACK_POINTER_REGNUM], file);
5154 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
5158 if (final_sequence != 0 && set_noreorder++ == 0)
5159 fputs (".set\tnoreorder\n\t", file);
5163 if (final_sequence != 0)
5165 if (set_noreorder++ == 0)
5166 fputs (".set\tnoreorder\n\t", file);
5168 if (set_nomacro++ == 0)
5169 fputs (".set\tnomacro\n\t", file);
5174 if (final_sequence != 0 && set_nomacro++ == 0)
5175 fputs ("\n\t.set\tnomacro", file);
5179 if (set_noreorder != 0)
5180 fputs ("\n\tnop", file);
5184 /* Print an extra newline so that the delayed insn is separated
5185 from the following ones. This looks neater and is consistent
5186 with non-nop delayed sequences. */
5187 if (set_noreorder != 0 && final_sequence == 0)
5188 fputs ("\n\tnop\n", file);
5192 if (set_noreorder++ == 0)
5193 fputs (".set\tnoreorder\n\t", file);
5197 if (set_noreorder == 0)
5198 error ("internal error: %%) found without a %%( in assembler pattern");
5200 else if (--set_noreorder == 0)
5201 fputs ("\n\t.set\treorder", file);
5206 if (set_noat++ == 0)
5207 fputs (".set\tnoat\n\t", file);
5212 error ("internal error: %%] found without a %%[ in assembler pattern");
5213 else if (--set_noat == 0)
5214 fputs ("\n\t.set\tat", file);
5219 if (set_nomacro++ == 0)
5220 fputs (".set\tnomacro\n\t", file);
5224 if (set_nomacro == 0)
5225 error ("internal error: %%> found without a %%< in assembler pattern");
5226 else if (--set_nomacro == 0)
5227 fputs ("\n\t.set\tmacro", file);
5232 if (set_volatile++ == 0)
5233 fprintf (file, "%s.set\tvolatile\n\t", TARGET_MIPS_AS ? "" : "#");
5237 if (set_volatile == 0)
5238 error ("internal error: %%} found without a %%{ in assembler pattern");
5239 else if (--set_volatile == 0)
5240 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
5246 if (align_labels_log > 0)
5247 ASM_OUTPUT_ALIGN (file, align_labels_log);
5252 error ("PRINT_OPERAND: unknown punctuation '%c'", letter);
5261 error ("PRINT_OPERAND null pointer");
5265 code = GET_CODE (op);
5270 case EQ: fputs ("eq", file); break;
5271 case NE: fputs ("ne", file); break;
5272 case GT: fputs ("gt", file); break;
5273 case GE: fputs ("ge", file); break;
5274 case LT: fputs ("lt", file); break;
5275 case LE: fputs ("le", file); break;
5276 case GTU: fputs ("gtu", file); break;
5277 case GEU: fputs ("geu", file); break;
5278 case LTU: fputs ("ltu", file); break;
5279 case LEU: fputs ("leu", file); break;
5281 fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
5284 else if (letter == 'N')
5287 case EQ: fputs ("ne", file); break;
5288 case NE: fputs ("eq", file); break;
5289 case GT: fputs ("le", file); break;
5290 case GE: fputs ("lt", file); break;
5291 case LT: fputs ("ge", file); break;
5292 case LE: fputs ("gt", file); break;
5293 case GTU: fputs ("leu", file); break;
5294 case GEU: fputs ("ltu", file); break;
5295 case LTU: fputs ("geu", file); break;
5296 case LEU: fputs ("gtu", file); break;
5298 fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
5301 else if (letter == 'F')
5304 case EQ: fputs ("c1f", file); break;
5305 case NE: fputs ("c1t", file); break;
5307 fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
5310 else if (letter == 'W')
5313 case EQ: fputs ("c1t", file); break;
5314 case NE: fputs ("c1f", file); break;
5316 fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
5319 else if (letter == 'h')
5321 if (GET_CODE (op) == HIGH)
5324 print_operand_reloc (file, op, mips_hi_relocs);
5327 else if (letter == 'R')
5328 print_operand_reloc (file, op, mips_lo_relocs);
5330 else if (letter == 'Z')
5332 register int regnum;
5337 regnum = REGNO (op);
5338 if (! ST_REG_P (regnum))
5341 if (regnum != ST_REG_FIRST)
5342 fprintf (file, "%s,", reg_names[regnum]);
5345 else if (code == REG || code == SUBREG)
5347 register int regnum;
5350 regnum = REGNO (op);
5352 regnum = true_regnum (op);
5354 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
5355 || (letter == 'L' && WORDS_BIG_ENDIAN)
5359 fprintf (file, "%s", reg_names[regnum]);
5362 else if (code == MEM)
5365 output_address (plus_constant (XEXP (op, 0), 4));
5367 output_address (XEXP (op, 0));
5370 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
5371 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
5373 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
5374 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
5376 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
5377 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
5379 else if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
5380 fputs (reg_names[GP_REG_FIRST], file);
5382 else if (letter == 'd' || letter == 'x' || letter == 'X')
5383 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
5385 else if (letter == 'B')
5386 fputs (code == EQ ? "z" : "n", file);
5387 else if (letter == 'b')
5388 fputs (code == EQ ? "n" : "z", file);
5389 else if (letter == 'T')
5390 fputs (code == EQ ? "f" : "t", file);
5391 else if (letter == 't')
5392 fputs (code == EQ ? "t" : "f", file);
5394 else if (CONST_GP_P (op))
5395 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
5398 output_addr_const (file, op);
5402 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM.
5403 RELOCS is the array of relocations to use. */
5406 print_operand_reloc (FILE *file, rtx op, const char **relocs)
5408 enum mips_symbol_type symbol_type;
5411 HOST_WIDE_INT offset;
5413 if (!mips_symbolic_constant_p (op, &symbol_type) || relocs[symbol_type] == 0)
5414 fatal_insn ("PRINT_OPERAND, invalid operand for relocation", op);
5416 /* If OP uses an UNSPEC address, we want to print the inner symbol. */
5417 mips_split_const (op, &base, &offset);
5418 if (UNSPEC_ADDRESS_P (base))
5419 op = plus_constant (UNSPEC_ADDRESS (base), offset);
5421 fputs (relocs[symbol_type], file);
5422 output_addr_const (file, op);
5423 for (p = relocs[symbol_type]; *p != 0; p++)
5428 /* Output address operand X to FILE. */
5431 print_operand_address (FILE *file, rtx x)
5433 struct mips_address_info addr;
5435 if (mips_classify_address (&addr, x, word_mode, true))
5439 print_operand (file, addr.offset, 0);
5440 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5443 case ADDRESS_LO_SUM:
5444 print_operand (file, addr.offset, 'R');
5445 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
5448 case ADDRESS_CONST_INT:
5449 case ADDRESS_SYMBOLIC:
5450 output_addr_const (file, x);
5456 /* Target hook for assembling integer objects. It appears that the Irix
5457 6 assembler can't handle 64-bit decimal integers, so avoid printing
5458 such an integer here. */
5461 mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
5463 if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
5465 fputs ("\t.dword\t", asm_out_file);
5466 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (x) != CONST_INT)
5467 output_addr_const (asm_out_file, x);
5469 print_operand (asm_out_file, x, 'X');
5470 fputc ('\n', asm_out_file);
5473 return default_assemble_integer (x, size, aligned_p);
5476 /* When using assembler macros, keep track of all of small-data externs
5477 so that mips_file_end can emit the appropriate declarations for them.
5479 In most cases it would be safe (though pointless) to emit .externs
5480 for other symbols too. One exception is when an object is within
5481 the -G limit but declared by the user to be in a section other
5482 than .sbss or .sdata. */
5485 mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
5487 register struct extern_list *p;
5489 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
5491 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5492 p->next = extern_head;
5494 p->size = int_size_in_bytes (TREE_TYPE (decl));
5498 if (TARGET_IRIX && mips_abi == ABI_32 && TREE_CODE (decl) == FUNCTION_DECL)
5500 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5501 p->next = extern_head;
5512 irix_output_external_libcall (rtx fun)
5514 register struct extern_list *p;
5516 if (mips_abi == ABI_32)
5518 p = (struct extern_list *) ggc_alloc (sizeof (struct extern_list));
5519 p->next = extern_head;
5520 p->name = XSTR (fun, 0);
5527 /* Emit a new filename to a stream. If we are smuggling stabs, try to
5528 put out a MIPS ECOFF file and a stab. */
5531 mips_output_filename (FILE *stream, const char *name)
5533 char ltext_label_name[100];
5535 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
5537 if (write_symbols == DWARF2_DEBUG)
5539 else if (mips_output_filename_first_time)
5541 mips_output_filename_first_time = 0;
5543 current_function_file = name;
5544 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5545 /* This tells mips-tfile that stabs will follow. */
5546 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5547 fprintf (stream, "\t#@stabs\n");
5550 else if (write_symbols == DBX_DEBUG)
5552 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5553 fprintf (stream, "%s", ASM_STABS_OP);
5554 output_quoted_string (stream, name);
5555 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5558 else if (name != current_function_file
5559 && strcmp (name, current_function_file) != 0)
5562 current_function_file = name;
5563 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5567 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5568 as well as a .loc, since it is possible that MIPS ECOFF might not be
5569 able to represent the location for inlines that come from a different
5573 mips_output_lineno (FILE *stream, int line)
5575 if (write_symbols == DBX_DEBUG)
5578 fprintf (stream, "%sLM%d:\n%s%d,0,%d,%sLM%d\n",
5579 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5580 LOCAL_LABEL_PREFIX, sym_lineno);
5584 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
5585 LABEL_AFTER_LOC (stream);
5589 /* Output an ASCII string, in a space-saving way. PREFIX is the string
5590 that should be written before the opening quote, such as "\t.ascii\t"
5591 for real string data or "\t# " for a comment. */
5594 mips_output_ascii (FILE *stream, const char *string_param, size_t len,
5599 register const unsigned char *string =
5600 (const unsigned char *)string_param;
5602 fprintf (stream, "%s\"", prefix);
5603 for (i = 0; i < len; i++)
5605 register int c = string[i];
5611 putc ('\\', stream);
5616 case TARGET_NEWLINE:
5617 fputs ("\\n", stream);
5619 && (((c = string[i+1]) >= '\040' && c <= '~')
5620 || c == TARGET_TAB))
5621 cur_pos = 32767; /* break right here */
5627 fputs ("\\t", stream);
5632 fputs ("\\f", stream);
5637 fputs ("\\b", stream);
5642 fputs ("\\r", stream);
5647 if (c >= ' ' && c < 0177)
5654 fprintf (stream, "\\%03o", c);
5659 if (cur_pos > 72 && i+1 < len)
5662 fprintf (stream, "\"\n%s\"", prefix);
5665 fprintf (stream, "\"\n");
5668 /* Implement TARGET_ASM_FILE_START. */
5671 mips_file_start (void)
5673 default_file_start ();
5675 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
5676 inside of a .set noreorder section jumps to a label outside of the .set
5677 noreorder section. Revision 2.20 just set nobopt silently rather than
5680 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5681 fprintf (asm_out_file, "\t.set\tnobopt\n");
5685 #if defined(OBJECT_FORMAT_ELF) && !TARGET_IRIX
5686 /* Generate a special section to describe the ABI switches used to
5687 produce the resultant binary. This used to be done by the assembler
5688 setting bits in the ELF header's flags field, but we have run out of
5689 bits. GDB needs this information in order to be able to correctly
5690 debug these binaries. See the function mips_gdbarch_init() in
5691 gdb/mips-tdep.c. This is unnecessary for the IRIX 5/6 ABIs and
5692 causes unnecessary IRIX 6 ld warnings. */
5693 const char * abi_string = NULL;
5697 case ABI_32: abi_string = "abi32"; break;
5698 case ABI_N32: abi_string = "abiN32"; break;
5699 case ABI_64: abi_string = "abi64"; break;
5700 case ABI_O64: abi_string = "abiO64"; break;
5701 case ABI_EABI: abi_string = TARGET_64BIT ? "eabi64" : "eabi32"; break;
5705 /* Note - we use fprintf directly rather than called named_section()
5706 because in this way we can avoid creating an allocated section. We
5707 do not want this section to take up any space in the running
5709 fprintf (asm_out_file, "\t.section .mdebug.%s\n", abi_string);
5711 /* There is no ELF header flag to distinguish long32 forms of the
5712 EABI from long64 forms. Emit a special section to help tools
5714 if (mips_abi == ABI_EABI)
5715 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n",
5716 TARGET_LONG64 ? 64 : 32);
5718 /* Restore the default section. */
5719 fprintf (asm_out_file, "\t.previous\n");
5723 /* Generate the pseudo ops that System V.4 wants. */
5724 #ifndef ABICALLS_ASM_OP
5725 #define ABICALLS_ASM_OP "\t.abicalls"
5727 if (TARGET_ABICALLS)
5728 /* ??? but do not want this (or want pic0) if -non-shared? */
5729 fprintf (asm_out_file, "%s\n", ABICALLS_ASM_OP);
5732 fprintf (asm_out_file, "\t.set\tmips16\n");
5734 if (flag_verbose_asm)
5735 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
5737 mips_section_threshold, mips_arch_info->name, mips_isa);
5740 #ifdef BSS_SECTION_ASM_OP
5741 /* Implement ASM_OUTPUT_ALIGNED_BSS. This differs from the default only
5742 in the use of sbss. */
5745 mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
5746 unsigned HOST_WIDE_INT size, int align)
5748 extern tree last_assemble_variable_decl;
5750 if (mips_in_small_data_p (decl))
5751 named_section (0, ".sbss", 0);
5754 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5755 last_assemble_variable_decl = decl;
5756 ASM_DECLARE_OBJECT_NAME (stream, name, decl);
5757 ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
5761 /* Implement TARGET_ASM_FILE_END. When using assembler macros, emit
5762 .externs for any small-data variables that turned out to be external. */
5765 mips_file_end (void)
5768 struct extern_list *p;
5772 fputs ("\n", asm_out_file);
5774 for (p = extern_head; p != 0; p = p->next)
5776 name_tree = get_identifier (p->name);
5778 /* Positively ensure only one .extern for any given symbol. */
5779 if (!TREE_ASM_WRITTEN (name_tree)
5780 && TREE_SYMBOL_REFERENCED (name_tree))
5782 TREE_ASM_WRITTEN (name_tree) = 1;
5783 /* In IRIX 5 or IRIX 6 for the O32 ABI, we must output a
5784 `.global name .text' directive for every used but
5785 undefined function. If we don't, the linker may perform
5786 an optimization (skipping over the insns that set $gp)
5787 when it is unsafe. */
5788 if (TARGET_IRIX && mips_abi == ABI_32 && p->size == -1)
5790 fputs ("\t.globl ", asm_out_file);
5791 assemble_name (asm_out_file, p->name);
5792 fputs (" .text\n", asm_out_file);
5796 fputs ("\t.extern\t", asm_out_file);
5797 assemble_name (asm_out_file, p->name);
5798 fprintf (asm_out_file, ", %d\n", p->size);
5805 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as
5806 the elfos.h version, but we also need to handle -muninit-const-in-rodata
5807 and the limitations of the SGI o32 assembler. */
5810 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
5811 unsigned HOST_WIDE_INT size,
5814 /* If the target wants uninitialized const declarations in
5815 .rdata then don't put them in .comm. */
5816 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA
5817 && TREE_CODE (decl) == VAR_DECL && TREE_READONLY (decl)
5818 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
5820 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
5821 targetm.asm_out.globalize_label (stream, name);
5823 readonly_data_section ();
5824 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
5825 mips_declare_object (stream, name, "",
5826 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
5830 /* The SGI o32 assembler doesn't accept an alignment. */
5831 mips_declare_common_object (stream, name, "\n\t.comm\t",
5832 size, align, !TARGET_SGI_O32_AS);
5835 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
5836 NAME is the name of the object and ALIGN is the required alignment
5837 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
5838 alignment argument. */
5841 mips_declare_common_object (FILE *stream, const char *name,
5842 const char *init_string,
5843 unsigned HOST_WIDE_INT size,
5844 unsigned int align, bool takes_alignment_p)
5846 if (!takes_alignment_p)
5848 size += (align / BITS_PER_UNIT) - 1;
5849 size -= size % (align / BITS_PER_UNIT);
5850 mips_declare_object (stream, name, init_string,
5851 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
5854 mips_declare_object (stream, name, init_string,
5855 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
5856 size, align / BITS_PER_UNIT);
5859 /* Emit either a label, .comm, or .lcomm directive. When using assembler
5860 macros, mark the symbol as written so that mips_file_end won't emit an
5861 .extern for it. STREAM is the output file, NAME is the name of the
5862 symbol, INIT_STRING is the string that should be written before the
5863 symbol and FINAL_STRING is the string that should be written after it.
5864 FINAL_STRING is a printf() format that consumes the remaining arguments. */
5867 mips_declare_object (FILE *stream, const char *name, const char *init_string,
5868 const char *final_string, ...)
5872 fputs (init_string, stream);
5873 assemble_name (stream, name);
5874 va_start (ap, final_string);
5875 vfprintf (stream, final_string, ap);
5878 if (!TARGET_EXPLICIT_RELOCS)
5880 tree name_tree = get_identifier (name);
5881 TREE_ASM_WRITTEN (name_tree) = 1;
5885 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
5886 extern int size_directive_output;
5888 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
5889 definitions except that it uses mips_declare_object() to emit the label. */
5892 mips_declare_object_name (FILE *stream, const char *name,
5893 tree decl ATTRIBUTE_UNUSED)
5895 if (!TARGET_SGI_O32_AS)
5897 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5898 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
5901 size_directive_output = 0;
5902 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
5906 size_directive_output = 1;
5907 size = int_size_in_bytes (TREE_TYPE (decl));
5908 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5912 mips_declare_object (stream, name, "", ":\n", 0);
5915 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
5918 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
5922 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
5923 if (!TARGET_SGI_O32_AS
5924 && !flag_inhibit_size_directive
5925 && DECL_SIZE (decl) != 0
5926 && !at_end && top_level
5927 && DECL_INITIAL (decl) == error_mark_node
5928 && !size_directive_output)
5932 size_directive_output = 1;
5933 size = int_size_in_bytes (TREE_TYPE (decl));
5934 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
5939 /* Return true if X is a small data address that can be rewritten
5943 mips_rewrite_small_data_p (rtx x)
5945 enum mips_symbol_type symbol_type;
5947 return (TARGET_EXPLICIT_RELOCS
5948 && mips_symbolic_constant_p (x, &symbol_type)
5949 && symbol_type == SYMBOL_SMALL_DATA);
5953 /* A for_each_rtx callback for small_data_pattern. */
5956 small_data_pattern_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5958 if (GET_CODE (*loc) == LO_SUM)
5961 return mips_rewrite_small_data_p (*loc);
5964 /* Return true if OP refers to small data symbols directly, not through
5968 small_data_pattern (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5970 return (GET_CODE (op) != SEQUENCE
5971 && for_each_rtx (&op, small_data_pattern_1, 0));
5974 /* A for_each_rtx callback, used by mips_rewrite_small_data. */
5977 mips_rewrite_small_data_1 (rtx *loc, void *data ATTRIBUTE_UNUSED)
5979 if (mips_rewrite_small_data_p (*loc))
5980 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
5982 if (GET_CODE (*loc) == LO_SUM)
5988 /* If possible, rewrite OP so that it refers to small data using
5989 explicit relocations. */
5992 mips_rewrite_small_data (rtx op)
5994 op = copy_insn (op);
5995 for_each_rtx (&op, mips_rewrite_small_data_1, 0);
5999 /* Return true if the current function has an insn that implicitly
6003 mips_function_has_gp_insn (void)
6005 /* Don't bother rechecking if we found one last time. */
6006 if (!cfun->machine->has_gp_insn_p)
6010 push_topmost_sequence ();
6011 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6013 && GET_CODE (PATTERN (insn)) != USE
6014 && GET_CODE (PATTERN (insn)) != CLOBBER
6015 && (get_attr_got (insn) != GOT_UNSET
6016 || small_data_pattern (PATTERN (insn), VOIDmode)))
6018 pop_topmost_sequence ();
6020 cfun->machine->has_gp_insn_p = (insn != 0);
6022 return cfun->machine->has_gp_insn_p;
6026 /* Return the register that should be used as the global pointer
6027 within this function. Return 0 if the function doesn't need
6028 a global pointer. */
6031 mips_global_pointer (void)
6035 /* $gp is always available in non-abicalls code. */
6036 if (!TARGET_ABICALLS)
6037 return GLOBAL_POINTER_REGNUM;
6039 /* We must always provide $gp when it is used implicitly. */
6040 if (!TARGET_EXPLICIT_RELOCS)
6041 return GLOBAL_POINTER_REGNUM;
6043 /* FUNCTION_PROFILER includes a jal macro, so we need to give it
6045 if (current_function_profile)
6046 return GLOBAL_POINTER_REGNUM;
6048 /* If the function has a nonlocal goto, $gp must hold the correct
6049 global pointer for the target function. */
6050 if (current_function_has_nonlocal_goto)
6051 return GLOBAL_POINTER_REGNUM;
6053 /* If the gp is never referenced, there's no need to initialize it.
6054 Note that reload can sometimes introduce constant pool references
6055 into a function that otherwise didn't need them. For example,
6056 suppose we have an instruction like:
6058 (set (reg:DF R1) (float:DF (reg:SI R2)))
6060 If R2 turns out to be constant such as 1, the instruction may have a
6061 REG_EQUAL note saying that R1 == 1.0. Reload then has the option of
6062 using this constant if R2 doesn't get allocated to a register.
6064 In cases like these, reload will have added the constant to the pool
6065 but no instruction will yet refer to it. */
6066 if (!regs_ever_live[GLOBAL_POINTER_REGNUM]
6067 && !current_function_uses_const_pool
6068 && !mips_function_has_gp_insn ())
6071 /* We need a global pointer, but perhaps we can use a call-clobbered
6072 register instead of $gp. */
6073 if (TARGET_NEWABI && current_function_is_leaf)
6074 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6075 if (!regs_ever_live[regno]
6076 && call_used_regs[regno]
6077 && !fixed_regs[regno]
6078 && regno != PIC_FUNCTION_ADDR_REGNUM)
6081 return GLOBAL_POINTER_REGNUM;
6085 /* Return true if the current function must save REGNO. */
6088 mips_save_reg_p (unsigned int regno)
6090 /* We only need to save $gp for NewABI PIC. */
6091 if (regno == GLOBAL_POINTER_REGNUM)
6092 return (TARGET_ABICALLS && TARGET_NEWABI
6093 && cfun->machine->global_pointer == regno);
6095 /* Check call-saved registers. */
6096 if (regs_ever_live[regno] && !call_used_regs[regno])
6099 /* We need to save the old frame pointer before setting up a new one. */
6100 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
6103 /* We need to save the incoming return address if it is ever clobbered
6104 within the function. */
6105 if (regno == GP_REG_FIRST + 31 && regs_ever_live[regno])
6112 return_type = DECL_RESULT (current_function_decl);
6114 /* $18 is a special case in mips16 code. It may be used to call
6115 a function which returns a floating point value, but it is
6116 marked in call_used_regs. */
6117 if (regno == GP_REG_FIRST + 18 && regs_ever_live[regno])
6120 /* $31 is also a special case. It will be used to copy a return
6121 value into the floating point registers if the return value is
6123 if (regno == GP_REG_FIRST + 31
6124 && mips16_hard_float
6125 && !aggregate_value_p (return_type, current_function_decl)
6126 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6127 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6135 /* Return the bytes needed to compute the frame pointer from the current
6136 stack pointer. SIZE is the size (in bytes) of the local variables.
6138 Mips stack frames look like:
6140 Before call After call
6141 +-----------------------+ +-----------------------+
6144 | caller's temps. | | caller's temps. |
6146 +-----------------------+ +-----------------------+
6148 | arguments on stack. | | arguments on stack. |
6150 +-----------------------+ +-----------------------+
6151 | 4 words to save | | 4 words to save |
6152 | arguments passed | | arguments passed |
6153 | in registers, even | | in registers, even |
6154 SP->| if not passed. | VFP->| if not passed. |
6155 +-----------------------+ +-----------------------+
6157 | fp register save |
6159 +-----------------------+
6161 | gp register save |
6163 +-----------------------+
6167 +-----------------------+
6169 | alloca allocations |
6171 +-----------------------+
6173 | GP save for V.4 abi |
6175 +-----------------------+
6177 | arguments on stack |
6179 +-----------------------+
6181 | arguments passed |
6182 | in registers, even |
6183 low SP->| if not passed. |
6184 memory +-----------------------+
6189 compute_frame_size (HOST_WIDE_INT size)
6192 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up */
6193 HOST_WIDE_INT var_size; /* # bytes that variables take up */
6194 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up */
6195 HOST_WIDE_INT cprestore_size; /* # bytes that the cprestore slot takes up */
6196 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding */
6197 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs */
6198 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs */
6199 unsigned int mask; /* mask of saved gp registers */
6200 unsigned int fmask; /* mask of saved fp registers */
6202 cfun->machine->global_pointer = mips_global_pointer ();
6208 var_size = MIPS_STACK_ALIGN (size);
6209 args_size = current_function_outgoing_args_size;
6210 cprestore_size = MIPS_STACK_ALIGN (STARTING_FRAME_OFFSET) - args_size;
6212 /* The space set aside by STARTING_FRAME_OFFSET isn't needed in leaf
6213 functions. If the function has local variables, we're committed
6214 to allocating it anyway. Otherwise reclaim it here. */
6215 if (var_size == 0 && current_function_is_leaf)
6216 cprestore_size = args_size = 0;
6218 /* The MIPS 3.0 linker does not like functions that dynamically
6219 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
6220 looks like we are trying to create a second frame pointer to the
6221 function, so allocate some stack space to make it happy. */
6223 if (args_size == 0 && current_function_calls_alloca)
6224 args_size = 4 * UNITS_PER_WORD;
6226 total_size = var_size + args_size + cprestore_size;
6228 /* Calculate space needed for gp registers. */
6229 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
6230 if (mips_save_reg_p (regno))
6232 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6233 mask |= 1 << (regno - GP_REG_FIRST);
6236 /* We need to restore these for the handler. */
6237 if (current_function_calls_eh_return)
6242 regno = EH_RETURN_DATA_REGNO (i);
6243 if (regno == INVALID_REGNUM)
6245 gp_reg_size += GET_MODE_SIZE (gpr_mode);
6246 mask |= 1 << (regno - GP_REG_FIRST);
6250 /* This loop must iterate over the same space as its companion in
6251 save_restore_insns. */
6252 for (regno = (FP_REG_LAST - FP_INC + 1);
6253 regno >= FP_REG_FIRST;
6256 if (mips_save_reg_p (regno))
6258 fp_reg_size += FP_INC * UNITS_PER_FPREG;
6259 fmask |= ((1 << FP_INC) - 1) << (regno - FP_REG_FIRST);
6263 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
6264 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
6266 /* Add in space reserved on the stack by the callee for storing arguments
6267 passed in registers. */
6269 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
6271 /* Save other computed information. */
6272 cfun->machine->frame.total_size = total_size;
6273 cfun->machine->frame.var_size = var_size;
6274 cfun->machine->frame.args_size = args_size;
6275 cfun->machine->frame.cprestore_size = cprestore_size;
6276 cfun->machine->frame.gp_reg_size = gp_reg_size;
6277 cfun->machine->frame.fp_reg_size = fp_reg_size;
6278 cfun->machine->frame.mask = mask;
6279 cfun->machine->frame.fmask = fmask;
6280 cfun->machine->frame.initialized = reload_completed;
6281 cfun->machine->frame.num_gp = gp_reg_size / UNITS_PER_WORD;
6282 cfun->machine->frame.num_fp = fp_reg_size / (FP_INC * UNITS_PER_FPREG);
6286 HOST_WIDE_INT offset;
6288 offset = (args_size + cprestore_size + var_size
6289 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
6290 cfun->machine->frame.gp_sp_offset = offset;
6291 cfun->machine->frame.gp_save_offset = offset - total_size;
6295 cfun->machine->frame.gp_sp_offset = 0;
6296 cfun->machine->frame.gp_save_offset = 0;
6301 HOST_WIDE_INT offset;
6303 offset = (args_size + cprestore_size + var_size
6304 + gp_reg_rounded + fp_reg_size
6305 - FP_INC * UNITS_PER_FPREG);
6306 cfun->machine->frame.fp_sp_offset = offset;
6307 cfun->machine->frame.fp_save_offset = offset - total_size;
6311 cfun->machine->frame.fp_sp_offset = 0;
6312 cfun->machine->frame.fp_save_offset = 0;
6315 /* Ok, we're done. */
6319 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
6320 pointer or argument pointer. TO is either the stack pointer or
6321 hard frame pointer. */
6324 mips_initial_elimination_offset (int from, int to)
6326 HOST_WIDE_INT offset;
6328 compute_frame_size (get_frame_size ());
6330 /* Set OFFSET to the offset from the stack pointer. */
6333 case FRAME_POINTER_REGNUM:
6337 case ARG_POINTER_REGNUM:
6338 offset = cfun->machine->frame.total_size;
6340 offset -= current_function_pretend_args_size;
6347 if (TARGET_MIPS16 && to == HARD_FRAME_POINTER_REGNUM)
6348 offset -= cfun->machine->frame.args_size;
6353 /* Implement RETURN_ADDR_RTX. Note, we do not support moving
6354 back to a previous frame. */
6356 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
6361 return get_hard_reg_initial_val (Pmode, GP_REG_FIRST + 31);
6364 /* Use FN to save or restore register REGNO. MODE is the register's
6365 mode and OFFSET is the offset of its save slot from the current
6369 mips_save_restore_reg (enum machine_mode mode, int regno,
6370 HOST_WIDE_INT offset, mips_save_restore_fn fn)
6374 mem = gen_rtx_MEM (mode, plus_constant (stack_pointer_rtx, offset));
6375 if (!current_function_calls_eh_return)
6376 RTX_UNCHANGING_P (mem) = 1;
6378 fn (gen_rtx_REG (mode, regno), mem);
6382 /* Call FN for each register that is saved by the current function.
6383 SP_OFFSET is the offset of the current stack pointer from the start
6387 mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
6389 #define BITSET_P(VALUE, BIT) (((VALUE) & (1L << (BIT))) != 0)
6391 enum machine_mode fpr_mode;
6392 HOST_WIDE_INT offset;
6395 /* Save registers starting from high to low. The debuggers prefer at least
6396 the return register be stored at func+4, and also it allows us not to
6397 need a nop in the epilog if at least one register is reloaded in
6398 addition to return address. */
6399 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
6400 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
6401 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
6403 mips_save_restore_reg (gpr_mode, regno, offset, fn);
6404 offset -= GET_MODE_SIZE (gpr_mode);
6407 /* This loop must iterate over the same space as its companion in
6408 compute_frame_size. */
6409 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
6410 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
6411 for (regno = (FP_REG_LAST - FP_INC + 1);
6412 regno >= FP_REG_FIRST;
6414 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
6416 mips_save_restore_reg (fpr_mode, regno, offset, fn);
6417 offset -= GET_MODE_SIZE (fpr_mode);
6422 /* If we're generating n32 or n64 abicalls, and the current function
6423 does not use $28 as its global pointer, emit a cplocal directive.
6424 Use pic_offset_table_rtx as the argument to the directive. */
6427 mips_output_cplocal (void)
6429 if (!TARGET_EXPLICIT_RELOCS
6430 && cfun->machine->global_pointer > 0
6431 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
6432 output_asm_insn (".cplocal %+", 0);
6435 /* If we're generating n32 or n64 abicalls, emit instructions
6436 to set up the global pointer. */
6439 mips_emit_loadgp (void)
6441 if (TARGET_ABICALLS && TARGET_NEWABI && cfun->machine->global_pointer > 0)
6443 rtx addr, offset, incoming_address;
6445 addr = XEXP (DECL_RTL (current_function_decl), 0);
6446 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
6447 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
6448 emit_insn (gen_loadgp (offset, incoming_address));
6449 if (!TARGET_EXPLICIT_RELOCS)
6450 emit_insn (gen_loadgp_blockage ());
6454 /* Set up the stack and frame (if desired) for the function. */
6457 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6460 HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
6462 /* ??? When is this really needed? At least the GNU assembler does not
6463 need the source filename more than once in the file, beyond what is
6464 emitted by the debug information. */
6466 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6468 #ifdef SDB_DEBUGGING_INFO
6469 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6470 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl), 0);
6473 /* In mips16 mode, we may need to generate a 32 bit to handle
6474 floating point arguments. The linker will arrange for any 32 bit
6475 functions to call this stub, which will then jump to the 16 bit
6477 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6478 && current_function_args_info.fp_code != 0)
6479 build_mips16_function_stub (file);
6481 if (!FUNCTION_NAME_ALREADY_DECLARED)
6483 /* Get the function name the same way that toplev.c does before calling
6484 assemble_start_function. This is needed so that the name used here
6485 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6486 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6488 if (!flag_inhibit_size_directive)
6490 fputs ("\t.ent\t", file);
6491 assemble_name (file, fnname);
6495 assemble_name (file, fnname);
6496 fputs (":\n", file);
6499 if (!flag_inhibit_size_directive)
6501 /* .frame FRAMEREG, FRAMESIZE, RETREG */
6503 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
6504 "# vars= " HOST_WIDE_INT_PRINT_DEC ", regs= %d/%d"
6505 ", args= " HOST_WIDE_INT_PRINT_DEC
6506 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
6507 (reg_names[(frame_pointer_needed)
6508 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM]),
6509 ((frame_pointer_needed && TARGET_MIPS16)
6510 ? tsize - cfun->machine->frame.args_size
6512 reg_names[GP_REG_FIRST + 31],
6513 cfun->machine->frame.var_size,
6514 cfun->machine->frame.num_gp,
6515 cfun->machine->frame.num_fp,
6516 cfun->machine->frame.args_size,
6517 cfun->machine->frame.cprestore_size);
6519 /* .mask MASK, GPOFFSET; .fmask FPOFFSET */
6520 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6521 cfun->machine->frame.mask,
6522 cfun->machine->frame.gp_save_offset);
6523 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
6524 cfun->machine->frame.fmask,
6525 cfun->machine->frame.fp_save_offset);
6528 OLD_SP == *FRAMEREG + FRAMESIZE => can find old_sp from nominated FP reg.
6529 HIGHEST_GP_SAVED == *FRAMEREG + FRAMESIZE + GPOFFSET => can find saved regs. */
6532 if (TARGET_ABICALLS && !TARGET_NEWABI && cfun->machine->global_pointer > 0)
6534 /* Handle the initialization of $gp for SVR4 PIC. */
6535 if (!cfun->machine->all_noreorder_p)
6536 output_asm_insn ("%(.cpload\t%^%)", 0);
6538 output_asm_insn ("%(.cpload\t%^\n\t%<", 0);
6540 else if (cfun->machine->all_noreorder_p)
6541 output_asm_insn ("%(%<", 0);
6543 /* Tell the assembler which register we're using as the global
6544 pointer. This is needed for thunks, since they can use either
6545 explicit relocs or assembler macros. */
6546 mips_output_cplocal ();
6549 /* Make the last instruction frame related and note that it performs
6550 the operation described by FRAME_PATTERN. */
6553 mips_set_frame_expr (rtx frame_pattern)
6557 insn = get_last_insn ();
6558 RTX_FRAME_RELATED_P (insn) = 1;
6559 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
6565 /* Return a frame-related rtx that stores REG at MEM.
6566 REG must be a single register. */
6569 mips_frame_set (rtx mem, rtx reg)
6571 rtx set = gen_rtx_SET (VOIDmode, mem, reg);
6572 RTX_FRAME_RELATED_P (set) = 1;
6577 /* Save register REG to MEM. Make the instruction frame-related. */
6580 mips_save_reg (rtx reg, rtx mem)
6582 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
6586 if (mips_split_64bit_move_p (mem, reg))
6587 mips_split_64bit_move (mem, reg);
6589 emit_move_insn (mem, reg);
6591 x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
6592 x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
6593 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
6598 && REGNO (reg) != GP_REG_FIRST + 31
6599 && !M16_REG_P (REGNO (reg)))
6601 /* Save a non-mips16 register by moving it through a temporary.
6602 We don't need to do this for $31 since there's a special
6603 instruction for it. */
6604 emit_move_insn (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
6605 emit_move_insn (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
6608 emit_move_insn (mem, reg);
6610 mips_set_frame_expr (mips_frame_set (mem, reg));
6615 /* Expand the prologue into a bunch of separate insns. */
6618 mips_expand_prologue (void)
6622 if (cfun->machine->global_pointer > 0)
6623 REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
6625 size = compute_frame_size (get_frame_size ());
6627 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
6628 bytes beforehand; this is enough to cover the register save area
6629 without going out of range. */
6630 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6632 HOST_WIDE_INT step1;
6634 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
6635 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6637 GEN_INT (-step1)))) = 1;
6639 mips_for_each_saved_reg (size, mips_save_reg);
6642 /* Allocate the rest of the frame. */
6645 if (SMALL_OPERAND (-size))
6646 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
6648 GEN_INT (-size)))) = 1;
6651 emit_move_insn (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
6654 /* There are no instructions to add or subtract registers
6655 from the stack pointer, so use the frame pointer as a
6656 temporary. We should always be using a frame pointer
6657 in this case anyway. */
6658 if (!frame_pointer_needed)
6661 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6662 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
6663 hard_frame_pointer_rtx,
6664 MIPS_PROLOGUE_TEMP (Pmode)));
6665 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6668 emit_insn (gen_sub3_insn (stack_pointer_rtx,
6670 MIPS_PROLOGUE_TEMP (Pmode)));
6672 /* Describe the combined effect of the previous instructions. */
6674 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
6675 plus_constant (stack_pointer_rtx, -size)));
6679 /* Set up the frame pointer, if we're using one. In mips16 code,
6680 we point the frame pointer ahead of the outgoing argument area.
6681 This should allow more variables & incoming arguments to be
6682 accessed with unextended instructions. */
6683 if (frame_pointer_needed)
6685 if (TARGET_MIPS16 && cfun->machine->frame.args_size != 0)
6687 rtx offset = GEN_INT (cfun->machine->frame.args_size);
6689 (emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
6694 RTX_FRAME_RELATED_P (emit_move_insn (hard_frame_pointer_rtx,
6695 stack_pointer_rtx)) = 1;
6698 /* If generating o32/o64 abicalls, save $gp on the stack. */
6699 if (TARGET_ABICALLS && !TARGET_NEWABI && !current_function_is_leaf)
6700 emit_insn (gen_cprestore (GEN_INT (current_function_outgoing_args_size)));
6702 mips_emit_loadgp ();
6704 /* If we are profiling, make sure no instructions are scheduled before
6705 the call to mcount. */
6707 if (current_function_profile)
6708 emit_insn (gen_blockage ());
6711 /* Do any necessary cleanup after a function to restore stack, frame,
6714 #define RA_MASK BITMASK_HIGH /* 1 << 31 */
6717 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
6718 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
6720 /* Reinstate the normal $gp. */
6721 REGNO (pic_offset_table_rtx) = GLOBAL_POINTER_REGNUM;
6722 mips_output_cplocal ();
6724 if (cfun->machine->all_noreorder_p)
6726 /* Avoid using %>%) since it adds excess whitespace. */
6727 output_asm_insn (".set\tmacro", 0);
6728 output_asm_insn (".set\treorder", 0);
6729 set_noreorder = set_nomacro = 0;
6732 if (!FUNCTION_NAME_ALREADY_DECLARED && !flag_inhibit_size_directive)
6736 /* Get the function name the same way that toplev.c does before calling
6737 assemble_start_function. This is needed so that the name used here
6738 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6739 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6740 fputs ("\t.end\t", file);
6741 assemble_name (file, fnname);
6746 /* Emit instructions to restore register REG from slot MEM. */
6749 mips_restore_reg (rtx reg, rtx mem)
6751 /* There's no mips16 instruction to load $31 directly. Load into
6752 $7 instead and adjust the return insn appropriately. */
6753 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
6754 reg = gen_rtx_REG (GET_MODE (reg), 7);
6756 if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
6758 /* Can't restore directly; move through a temporary. */
6759 emit_move_insn (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
6760 emit_move_insn (reg, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
6763 emit_move_insn (reg, mem);
6767 /* Expand the epilogue into a bunch of separate insns. SIBCALL_P is true
6768 if this epilogue precedes a sibling call, false if it is for a normal
6769 "epilogue" pattern. */
6772 mips_expand_epilogue (int sibcall_p)
6774 HOST_WIDE_INT step1, step2;
6777 if (!sibcall_p && mips_can_use_return_insn ())
6779 emit_jump_insn (gen_return ());
6783 /* Split the frame into two. STEP1 is the amount of stack we should
6784 deallocate before restoring the registers. STEP2 is the amount we
6785 should deallocate afterwards.
6787 Start off by assuming that no registers need to be restored. */
6788 step1 = cfun->machine->frame.total_size;
6791 /* Work out which register holds the frame address. Account for the
6792 frame pointer offset used by mips16 code. */
6793 if (!frame_pointer_needed)
6794 base = stack_pointer_rtx;
6797 base = hard_frame_pointer_rtx;
6799 step1 -= cfun->machine->frame.args_size;
6802 /* If we need to restore registers, deallocate as much stack as
6803 possible in the second step without going out of range. */
6804 if ((cfun->machine->frame.mask | cfun->machine->frame.fmask) != 0)
6806 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
6810 /* Set TARGET to BASE + STEP1. */
6816 /* Get an rtx for STEP1 that we can add to BASE. */
6817 adjust = GEN_INT (step1);
6818 if (!SMALL_OPERAND (step1))
6820 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), adjust);
6821 adjust = MIPS_EPILOGUE_TEMP (Pmode);
6824 /* Normal mode code can copy the result straight into $sp. */
6826 target = stack_pointer_rtx;
6828 emit_insn (gen_add3_insn (target, base, adjust));
6831 /* Copy TARGET into the stack pointer. */
6832 if (target != stack_pointer_rtx)
6833 emit_move_insn (stack_pointer_rtx, target);
6835 /* If we're using addressing macros for n32/n64 abicalls, $gp is
6836 implicitly used by all SYMBOL_REFs. We must emit a blockage
6837 insn before restoring it. */
6838 if (TARGET_ABICALLS && TARGET_NEWABI && !TARGET_EXPLICIT_RELOCS)
6839 emit_insn (gen_blockage ());
6841 /* Restore the registers. */
6842 mips_for_each_saved_reg (cfun->machine->frame.total_size - step2,
6845 /* Deallocate the final bit of the frame. */
6847 emit_insn (gen_add3_insn (stack_pointer_rtx,
6851 /* Add in the __builtin_eh_return stack adjustment. We need to
6852 use a temporary in mips16 code. */
6853 if (current_function_calls_eh_return)
6857 emit_move_insn (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
6858 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
6859 MIPS_EPILOGUE_TEMP (Pmode),
6860 EH_RETURN_STACKADJ_RTX));
6861 emit_move_insn (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
6864 emit_insn (gen_add3_insn (stack_pointer_rtx,
6866 EH_RETURN_STACKADJ_RTX));
6871 /* The mips16 loads the return address into $7, not $31. */
6872 if (TARGET_MIPS16 && (cfun->machine->frame.mask & RA_MASK) != 0)
6873 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6874 GP_REG_FIRST + 7)));
6876 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
6877 GP_REG_FIRST + 31)));
6881 /* Return nonzero if this function is known to have a null epilogue.
6882 This allows the optimizer to omit jumps to jumps if no stack
6886 mips_can_use_return_insn (void)
6890 if (! reload_completed)
6893 if (regs_ever_live[31] || current_function_profile)
6896 return_type = DECL_RESULT (current_function_decl);
6898 /* In mips16 mode, a function which returns a floating point value
6899 needs to arrange to copy the return value into the floating point
6902 && mips16_hard_float
6903 && ! aggregate_value_p (return_type, current_function_decl)
6904 && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
6905 && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
6908 if (cfun->machine->frame.initialized)
6909 return cfun->machine->frame.total_size == 0;
6911 return compute_frame_size (get_frame_size ()) == 0;
6914 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
6915 in order to avoid duplicating too much logic from elsewhere. */
6918 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
6919 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
6922 rtx this, temp1, temp2, insn, fnaddr;
6924 /* Pretend to be a post-reload pass while generating rtl. */
6926 reload_completed = 1;
6927 reset_block_changes ();
6929 /* Pick a global pointer for -mabicalls. Use $15 rather than $28
6930 for TARGET_NEWABI since the latter is a call-saved register. */
6931 if (TARGET_ABICALLS)
6932 cfun->machine->global_pointer
6933 = REGNO (pic_offset_table_rtx)
6934 = TARGET_NEWABI ? 15 : GLOBAL_POINTER_REGNUM;
6936 /* Set up the global pointer for n32 or n64 abicalls. */
6937 mips_emit_loadgp ();
6939 /* We need two temporary registers in some cases. */
6940 temp1 = gen_rtx_REG (Pmode, 2);
6941 temp2 = gen_rtx_REG (Pmode, 3);
6943 /* Find out which register contains the "this" pointer. */
6944 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
6945 this = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
6947 this = gen_rtx_REG (Pmode, GP_ARG_FIRST);
6949 /* Add DELTA to THIS. */
6952 rtx offset = GEN_INT (delta);
6953 if (!SMALL_OPERAND (delta))
6955 emit_move_insn (temp1, offset);
6958 emit_insn (gen_add3_insn (this, this, offset));
6961 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
6962 if (vcall_offset != 0)
6966 /* Set TEMP1 to *THIS. */
6967 emit_move_insn (temp1, gen_rtx_MEM (Pmode, this));
6969 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
6970 if (SMALL_OPERAND (vcall_offset))
6971 addr = gen_rtx_PLUS (Pmode, temp1, GEN_INT (vcall_offset));
6972 else if (TARGET_MIPS16)
6974 /* Load the full offset into a register so that we can use
6975 an unextended instruction for the load itself. */
6976 emit_move_insn (temp2, GEN_INT (vcall_offset));
6977 emit_insn (gen_add3_insn (temp1, temp1, temp2));
6982 /* Load the high part of the offset into a register and
6983 leave the low part for the address. */
6984 emit_move_insn (temp2, GEN_INT (CONST_HIGH_PART (vcall_offset)));
6985 emit_insn (gen_add3_insn (temp1, temp1, temp2));
6986 addr = gen_rtx_PLUS (Pmode, temp1,
6987 GEN_INT (CONST_LOW_PART (vcall_offset)));
6990 /* Load the offset and add it to THIS. */
6991 emit_move_insn (temp1, gen_rtx_MEM (Pmode, addr));
6992 emit_insn (gen_add3_insn (this, this, temp1));
6995 /* Jump to the target function. Use a sibcall if direct jumps are
6996 allowed, otherwise load the address into a register first. */
6997 fnaddr = XEXP (DECL_RTL (function), 0);
6998 if (TARGET_MIPS16 || TARGET_ABICALLS || TARGET_LONG_CALLS)
7000 /* This is messy. gas treats "la $25,foo" as part of a call
7001 sequence and may allow a global "foo" to be lazily bound.
7002 The general move patterns therefore reject this combination.
7004 In this context, lazy binding would actually be OK for o32 and o64,
7005 but it's still wrong for n32 and n64; see mips_load_call_address.
7006 We must therefore load the address via a temporary register if
7007 mips_dangerous_for_la25_p.
7009 If we jump to the temporary register rather than $25, the assembler
7010 can use the move insn to fill the jump's delay slot. */
7011 if (TARGET_ABICALLS && !mips_dangerous_for_la25_p (fnaddr))
7012 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
7013 mips_load_call_address (temp1, fnaddr, true);
7015 if (TARGET_ABICALLS && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
7016 emit_move_insn (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
7017 emit_jump_insn (gen_indirect_jump (temp1));
7021 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
7022 SIBLING_CALL_P (insn) = 1;
7025 /* Run just enough of rest_of_compilation. This sequence was
7026 "borrowed" from alpha.c. */
7027 insn = get_insns ();
7028 insn_locators_initialize ();
7029 split_all_insns_noflow ();
7031 mips16_lay_out_constants ();
7032 shorten_branches (insn);
7033 final_start_function (insn, file, 1);
7034 final (insn, file, 1, 0);
7035 final_end_function ();
7037 /* Clean up the vars set above. Note that final_end_function resets
7038 the global pointer for us. */
7039 reload_completed = 0;
7043 /* Returns nonzero if X contains a SYMBOL_REF. */
7046 symbolic_expression_p (rtx x)
7048 if (GET_CODE (x) == SYMBOL_REF)
7051 if (GET_CODE (x) == CONST)
7052 return symbolic_expression_p (XEXP (x, 0));
7055 return symbolic_expression_p (XEXP (x, 0));
7057 if (ARITHMETIC_P (x))
7058 return (symbolic_expression_p (XEXP (x, 0))
7059 || symbolic_expression_p (XEXP (x, 1)));
7064 /* Choose the section to use for the constant rtx expression X that has
7068 mips_select_rtx_section (enum machine_mode mode, rtx x,
7069 unsigned HOST_WIDE_INT align)
7073 /* In mips16 mode, the constant table always goes in the same section
7074 as the function, so that constants can be loaded using PC relative
7076 function_section (current_function_decl);
7078 else if (TARGET_EMBEDDED_DATA)
7080 /* For embedded applications, always put constants in read-only data,
7081 in order to reduce RAM usage. */
7082 mergeable_constant_section (mode, align, 0);
7086 /* For hosted applications, always put constants in small data if
7087 possible, as this gives the best performance. */
7088 /* ??? Consider using mergeable small data sections. */
7090 if (GET_MODE_SIZE (mode) <= (unsigned) mips_section_threshold
7091 && mips_section_threshold > 0)
7092 named_section (0, ".sdata", 0);
7093 else if (flag_pic && symbolic_expression_p (x))
7095 if (targetm.have_named_sections)
7096 named_section (0, ".data.rel.ro", 3);
7101 mergeable_constant_section (mode, align, 0);
7105 /* Choose the section to use for DECL. RELOC is true if its value contains
7106 any relocatable expression. */
7109 mips_select_section (tree decl, int reloc,
7110 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
7112 if (targetm.have_named_sections)
7113 default_elf_select_section (decl, reloc, align);
7115 /* The native irix o32 assembler doesn't support named sections. */
7116 default_select_section (decl, reloc, align);
7120 /* Implement TARGET_IN_SMALL_DATA_P. Return true if it would be safe to
7121 access DECL using %gp_rel(...)($gp). */
7124 mips_in_small_data_p (tree decl)
7128 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
7131 /* We don't yet generate small-data references for -mabicalls. See related
7132 -G handling in override_options. */
7133 if (TARGET_ABICALLS)
7136 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
7140 /* Reject anything that isn't in a known small-data section. */
7141 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
7142 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
7145 /* If a symbol is defined externally, the assembler will use the
7146 usual -G rules when deciding how to implement macros. */
7147 if (TARGET_EXPLICIT_RELOCS || !DECL_EXTERNAL (decl))
7150 else if (TARGET_EMBEDDED_DATA)
7152 /* Don't put constants into the small data section: we want them
7153 to be in ROM rather than RAM. */
7154 if (TREE_CODE (decl) != VAR_DECL)
7157 if (TREE_READONLY (decl)
7158 && !TREE_SIDE_EFFECTS (decl)
7159 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
7163 size = int_size_in_bytes (TREE_TYPE (decl));
7164 return (size > 0 && size <= mips_section_threshold);
7167 /* See whether VALTYPE is a record whose fields should be returned in
7168 floating-point registers. If so, return the number of fields and
7169 list them in FIELDS (which should have two elements). Return 0
7172 For n32 & n64, a structure with one or two fields is returned in
7173 floating-point registers as long as every field has a floating-point
7177 mips_fpr_return_fields (tree valtype, tree *fields)
7185 if (TREE_CODE (valtype) != RECORD_TYPE)
7189 for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field))
7191 if (TREE_CODE (field) != FIELD_DECL)
7194 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE)
7200 fields[i++] = field;
7206 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
7207 a value in the most significant part of $2/$3 if:
7209 - the target is big-endian;
7211 - the value has a structure or union type (we generalize this to
7212 cover aggregates from other languages too); and
7214 - the structure is not returned in floating-point registers. */
7217 mips_return_in_msb (tree valtype)
7221 return (TARGET_NEWABI
7222 && TARGET_BIG_ENDIAN
7223 && AGGREGATE_TYPE_P (valtype)
7224 && mips_fpr_return_fields (valtype, fields) == 0);
7228 /* Return a composite value in a pair of floating-point registers.
7229 MODE1 and OFFSET1 are the mode and byte offset for the first value,
7230 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
7233 For n32 & n64, $f0 always holds the first value and $f2 the second.
7234 Otherwise the values are packed together as closely as possible. */
7237 mips_return_fpr_pair (enum machine_mode mode,
7238 enum machine_mode mode1, HOST_WIDE_INT offset1,
7239 enum machine_mode mode2, HOST_WIDE_INT offset2)
7243 inc = (TARGET_NEWABI ? 2 : FP_INC);
7244 return gen_rtx_PARALLEL
7247 gen_rtx_EXPR_LIST (VOIDmode,
7248 gen_rtx_REG (mode1, FP_RETURN),
7250 gen_rtx_EXPR_LIST (VOIDmode,
7251 gen_rtx_REG (mode2, FP_RETURN + inc),
7252 GEN_INT (offset2))));
7257 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
7258 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
7259 VALTYPE is null and MODE is the mode of the return value. */
7262 mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
7263 enum machine_mode mode)
7270 mode = TYPE_MODE (valtype);
7271 unsignedp = TYPE_UNSIGNED (valtype);
7273 /* Since we define TARGET_PROMOTE_FUNCTION_RETURN that returns
7274 true, we must promote the mode just as PROMOTE_MODE does. */
7275 mode = promote_mode (valtype, mode, &unsignedp, 1);
7277 /* Handle structures whose fields are returned in $f0/$f2. */
7278 switch (mips_fpr_return_fields (valtype, fields))
7281 return gen_rtx_REG (mode, FP_RETURN);
7284 return mips_return_fpr_pair (mode,
7285 TYPE_MODE (TREE_TYPE (fields[0])),
7286 int_byte_position (fields[0]),
7287 TYPE_MODE (TREE_TYPE (fields[1])),
7288 int_byte_position (fields[1]));
7291 /* If a value is passed in the most significant part of a register, see
7292 whether we have to round the mode up to a whole number of words. */
7293 if (mips_return_in_msb (valtype))
7295 HOST_WIDE_INT size = int_size_in_bytes (valtype);
7296 if (size % UNITS_PER_WORD != 0)
7298 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
7299 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
7304 if (GET_MODE_CLASS (mode) == MODE_FLOAT
7305 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE)
7306 return gen_rtx_REG (mode, FP_RETURN);
7308 /* Handle long doubles for n32 & n64. */
7310 return mips_return_fpr_pair (mode,
7312 DImode, GET_MODE_SIZE (mode) / 2);
7314 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
7315 && GET_MODE_SIZE (mode) <= UNITS_PER_HWFPVALUE * 2)
7316 return mips_return_fpr_pair (mode,
7317 GET_MODE_INNER (mode), 0,
7318 GET_MODE_INNER (mode),
7319 GET_MODE_SIZE (mode) / 2);
7321 return gen_rtx_REG (mode, GP_RETURN);
7324 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7325 nonzero when an argument must be passed by reference. */
7328 function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
7329 enum machine_mode mode, tree type,
7330 int named ATTRIBUTE_UNUSED)
7332 if (mips_abi == ABI_EABI)
7336 /* ??? How should SCmode be handled? */
7337 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7340 size = int_size_in_bytes (type);
7341 return size == -1 || size > UNITS_PER_WORD;
7345 /* If we have a variable-sized parameter, we have no choice. */
7346 return targetm.calls.must_pass_in_stack (mode, type);
7350 /* Return the class of registers for which a mode change from FROM to TO
7353 In little-endian mode, the hi-lo registers are numbered backwards,
7354 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
7357 Similarly, when using paired floating-point registers, the first
7358 register holds the low word, regardless of endianness. So in big
7359 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
7362 Also, loading a 32-bit value into a 64-bit floating-point register
7363 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
7364 We can't allow 64-bit float registers to change from a 32-bit
7365 mode to a 64-bit mode. */
7368 mips_cannot_change_mode_class (enum machine_mode from,
7369 enum machine_mode to, enum reg_class class)
7371 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
7373 if (TARGET_BIG_ENDIAN)
7374 return reg_classes_intersect_p (FP_REGS, class);
7376 return reg_classes_intersect_p (HI_AND_FP_REGS, class);
7377 return reg_classes_intersect_p (HI_REG, class);
7382 /* Return true if X should not be moved directly into register $25.
7383 We need this because many versions of GAS will treat "la $25,foo" as
7384 part of a call sequence and so allow a global "foo" to be lazily bound. */
7387 mips_dangerous_for_la25_p (rtx x)
7389 HOST_WIDE_INT offset;
7391 if (TARGET_EXPLICIT_RELOCS)
7394 mips_split_const (x, &x, &offset);
7395 return global_got_operand (x, VOIDmode);
7398 /* Implement PREFERRED_RELOAD_CLASS. */
7401 mips_preferred_reload_class (rtx x, enum reg_class class)
7403 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, class))
7406 if (TARGET_HARD_FLOAT
7407 && FLOAT_MODE_P (GET_MODE (x))
7408 && reg_class_subset_p (FP_REGS, class))
7411 if (reg_class_subset_p (GR_REGS, class))
7414 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, class))
7420 /* This function returns the register class required for a secondary
7421 register when copying between one of the registers in CLASS, and X,
7422 using MODE. If IN_P is nonzero, the copy is going from X to the
7423 register, otherwise the register is the source. A return value of
7424 NO_REGS means that no secondary register is required. */
7427 mips_secondary_reload_class (enum reg_class class,
7428 enum machine_mode mode, rtx x, int in_p)
7430 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7434 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7435 regno = true_regnum (x);
7437 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7439 if (mips_dangerous_for_la25_p (x))
7442 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], 25))
7446 /* Copying from HI or LO to anywhere other than a general register
7447 requires a general register. */
7448 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7450 if (TARGET_MIPS16 && in_p)
7452 /* We can't really copy to HI or LO at all in mips16 mode. */
7455 return gp_reg_p ? NO_REGS : gr_regs;
7457 if (MD_REG_P (regno))
7459 if (TARGET_MIPS16 && ! in_p)
7461 /* We can't really copy to HI or LO at all in mips16 mode. */
7464 return class == gr_regs ? NO_REGS : gr_regs;
7467 /* We can only copy a value to a condition code register from a
7468 floating point register, and even then we require a scratch
7469 floating point register. We can only copy a value out of a
7470 condition code register into a general register. */
7471 if (class == ST_REGS)
7475 return gp_reg_p ? NO_REGS : gr_regs;
7477 if (ST_REG_P (regno))
7481 return class == gr_regs ? NO_REGS : gr_regs;
7484 if (class == FP_REGS)
7486 if (GET_CODE (x) == MEM)
7488 /* In this case we can use lwc1, swc1, ldc1 or sdc1. */
7491 else if (CONSTANT_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
7493 /* We can use the l.s and l.d macros to load floating-point
7494 constants. ??? For l.s, we could probably get better
7495 code by returning GR_REGS here. */
7498 else if (gp_reg_p || x == CONST0_RTX (mode))
7500 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
7503 else if (FP_REG_P (regno))
7505 /* In this case we can use mov.s or mov.d. */
7510 /* Otherwise, we need to reload through an integer register. */
7515 /* In mips16 mode, going between memory and anything but M16_REGS
7516 requires an M16_REG. */
7519 if (class != M16_REGS && class != M16_NA_REGS)
7527 if (class == M16_REGS || class == M16_NA_REGS)
7536 /* Implement CLASS_MAX_NREGS.
7538 Usually all registers are word-sized. The only supported exception
7539 is -mgp64 -msingle-float, which has 64-bit words but 32-bit float
7540 registers. A word-based calculation is correct even in that case,
7541 since -msingle-float disallows multi-FPR values. */
7544 mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
7545 enum machine_mode mode)
7547 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
7551 mips_valid_pointer_mode (enum machine_mode mode)
7553 return (mode == SImode || (TARGET_64BIT && mode == DImode));
7557 /* If we can access small data directly (using gp-relative relocation
7558 operators) return the small data pointer, otherwise return null.
7560 For each mips16 function which refers to GP relative symbols, we
7561 use a pseudo register, initialized at the start of the function, to
7562 hold the $gp value. */
7565 mips16_gp_pseudo_reg (void)
7567 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
7572 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7573 RTX_UNCHANGING_P (cfun->machine->mips16_gp_pseudo_rtx) = 1;
7575 /* We want to initialize this to a value which gcc will believe
7578 unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_GP);
7579 emit_move_insn (cfun->machine->mips16_gp_pseudo_rtx,
7580 gen_rtx_CONST (Pmode, unspec));
7581 insn = get_insns ();
7584 push_topmost_sequence ();
7585 /* We need to emit the initialization after the FUNCTION_BEG
7586 note, so that it will be integrated. */
7587 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7588 if (GET_CODE (scan) == NOTE
7589 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7591 if (scan == NULL_RTX)
7592 scan = get_insns ();
7593 insn = emit_insn_after (insn, scan);
7594 pop_topmost_sequence ();
7597 return cfun->machine->mips16_gp_pseudo_rtx;
7600 /* Write out code to move floating point arguments in or out of
7601 general registers. Output the instructions to FILE. FP_CODE is
7602 the code describing which arguments are present (see the comment at
7603 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is nonzero if
7604 we are copying from the floating point registers. */
7607 mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
7613 /* This code only works for the original 32 bit ABI and the O64 ABI. */
7621 gparg = GP_ARG_FIRST;
7622 fparg = FP_ARG_FIRST;
7623 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7627 if ((fparg & 1) != 0)
7629 fprintf (file, "\t%s\t%s,%s\n", s,
7630 reg_names[gparg], reg_names[fparg]);
7632 else if ((f & 3) == 2)
7635 fprintf (file, "\td%s\t%s,%s\n", s,
7636 reg_names[gparg], reg_names[fparg]);
7639 if ((fparg & 1) != 0)
7641 if (TARGET_BIG_ENDIAN)
7642 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7643 reg_names[gparg], reg_names[fparg + 1], s,
7644 reg_names[gparg + 1], reg_names[fparg]);
7646 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7647 reg_names[gparg], reg_names[fparg], s,
7648 reg_names[gparg + 1], reg_names[fparg + 1]);
7661 /* Build a mips16 function stub. This is used for functions which
7662 take arguments in the floating point registers. It is 32 bit code
7663 that moves the floating point args into the general registers, and
7664 then jumps to the 16 bit code. */
7667 build_mips16_function_stub (FILE *file)
7670 char *secname, *stubname;
7671 tree stubid, stubdecl;
7675 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7676 secname = (char *) alloca (strlen (fnname) + 20);
7677 sprintf (secname, ".mips16.fn.%s", fnname);
7678 stubname = (char *) alloca (strlen (fnname) + 20);
7679 sprintf (stubname, "__fn_stub_%s", fnname);
7680 stubid = get_identifier (stubname);
7681 stubdecl = build_decl (FUNCTION_DECL, stubid,
7682 build_function_type (void_type_node, NULL_TREE));
7683 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7685 fprintf (file, "\t# Stub function for %s (", current_function_name ());
7687 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7689 fprintf (file, "%s%s",
7690 need_comma ? ", " : "",
7691 (f & 3) == 1 ? "float" : "double");
7694 fprintf (file, ")\n");
7696 fprintf (file, "\t.set\tnomips16\n");
7697 function_section (stubdecl);
7698 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7700 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7701 within a .ent, and we can not emit another .ent. */
7702 if (!FUNCTION_NAME_ALREADY_DECLARED)
7704 fputs ("\t.ent\t", file);
7705 assemble_name (file, stubname);
7709 assemble_name (file, stubname);
7710 fputs (":\n", file);
7712 /* We don't want the assembler to insert any nops here. */
7713 fprintf (file, "\t.set\tnoreorder\n");
7715 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7717 fprintf (asm_out_file, "\t.set\tnoat\n");
7718 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7719 assemble_name (file, fnname);
7720 fprintf (file, "\n");
7721 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7722 fprintf (asm_out_file, "\t.set\tat\n");
7724 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7725 with one of the mfc1 instructions, because the result is not
7726 available for one instruction, so if the very first instruction
7727 in the function refers to the register, it will see the wrong
7729 fprintf (file, "\tnop\n");
7731 fprintf (file, "\t.set\treorder\n");
7733 if (!FUNCTION_NAME_ALREADY_DECLARED)
7735 fputs ("\t.end\t", file);
7736 assemble_name (file, stubname);
7740 fprintf (file, "\t.set\tmips16\n");
7742 function_section (current_function_decl);
7745 /* We keep a list of functions for which we have already built stubs
7746 in build_mips16_call_stub. */
7750 struct mips16_stub *next;
7755 static struct mips16_stub *mips16_stubs;
7757 /* Build a call stub for a mips16 call. A stub is needed if we are
7758 passing any floating point values which should go into the floating
7759 point registers. If we are, and the call turns out to be to a 32
7760 bit function, the stub will be used to move the values into the
7761 floating point registers before calling the 32 bit function. The
7762 linker will magically adjust the function call to either the 16 bit
7763 function or the 32 bit stub, depending upon where the function call
7764 is actually defined.
7766 Similarly, we need a stub if the return value might come back in a
7767 floating point register.
7769 RETVAL is the location of the return value, or null if this is
7770 a call rather than a call_value. FN is the address of the
7771 function and ARG_SIZE is the size of the arguments. FP_CODE
7772 is the code built by function_arg. This function returns a nonzero
7773 value if it builds the call instruction itself. */
7776 build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
7780 char *secname, *stubname;
7781 struct mips16_stub *l;
7782 tree stubid, stubdecl;
7786 /* We don't need to do anything if we aren't in mips16 mode, or if
7787 we were invoked with the -msoft-float option. */
7788 if (! TARGET_MIPS16 || ! mips16_hard_float)
7791 /* Figure out whether the value might come back in a floating point
7793 fpret = (retval != 0
7794 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7795 && GET_MODE_SIZE (GET_MODE (retval)) <= UNITS_PER_FPVALUE);
7797 /* We don't need to do anything if there were no floating point
7798 arguments and the value will not be returned in a floating point
7800 if (fp_code == 0 && ! fpret)
7803 /* We don't need to do anything if this is a call to a special
7804 mips16 support function. */
7805 if (GET_CODE (fn) == SYMBOL_REF
7806 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7809 /* This code will only work for o32 and o64 abis. The other ABI's
7810 require more sophisticated support. */
7814 /* We can only handle SFmode and DFmode floating point return
7816 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7819 /* If we're calling via a function pointer, then we must always call
7820 via a stub. There are magic stubs provided in libgcc.a for each
7821 of the required cases. Each of them expects the function address
7822 to arrive in register $2. */
7824 if (GET_CODE (fn) != SYMBOL_REF)
7830 /* ??? If this code is modified to support other ABI's, we need
7831 to handle PARALLEL return values here. */
7833 sprintf (buf, "__mips16_call_stub_%s%d",
7835 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7838 id = get_identifier (buf);
7839 stub_fn = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (id));
7841 emit_move_insn (gen_rtx_REG (Pmode, 2), fn);
7843 if (retval == NULL_RTX)
7844 insn = gen_call_internal (stub_fn, arg_size);
7846 insn = gen_call_value_internal (retval, stub_fn, arg_size);
7847 insn = emit_call_insn (insn);
7849 /* Put the register usage information on the CALL. */
7850 if (GET_CODE (insn) != CALL_INSN)
7852 CALL_INSN_FUNCTION_USAGE (insn) =
7853 gen_rtx_EXPR_LIST (VOIDmode,
7854 gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 2)),
7855 CALL_INSN_FUNCTION_USAGE (insn));
7857 /* If we are handling a floating point return value, we need to
7858 save $18 in the function prologue. Putting a note on the
7859 call will mean that regs_ever_live[$18] will be true if the
7860 call is not eliminated, and we can check that in the prologue
7863 CALL_INSN_FUNCTION_USAGE (insn) =
7864 gen_rtx_EXPR_LIST (VOIDmode,
7865 gen_rtx_USE (VOIDmode,
7866 gen_rtx_REG (word_mode, 18)),
7867 CALL_INSN_FUNCTION_USAGE (insn));
7869 /* Return 1 to tell the caller that we've generated the call
7874 /* We know the function we are going to call. If we have already
7875 built a stub, we don't need to do anything further. */
7877 fnname = XSTR (fn, 0);
7878 for (l = mips16_stubs; l != NULL; l = l->next)
7879 if (strcmp (l->name, fnname) == 0)
7884 /* Build a special purpose stub. When the linker sees a
7885 function call in mips16 code, it will check where the target
7886 is defined. If the target is a 32 bit call, the linker will
7887 search for the section defined here. It can tell which
7888 symbol this section is associated with by looking at the
7889 relocation information (the name is unreliable, since this
7890 might be a static function). If such a section is found, the
7891 linker will redirect the call to the start of the magic
7894 If the function does not return a floating point value, the
7895 special stub section is named
7898 If the function does return a floating point value, the stub
7900 .mips16.call.fp.FNNAME
7903 secname = (char *) alloca (strlen (fnname) + 40);
7904 sprintf (secname, ".mips16.call.%s%s",
7907 stubname = (char *) alloca (strlen (fnname) + 20);
7908 sprintf (stubname, "__call_stub_%s%s",
7911 stubid = get_identifier (stubname);
7912 stubdecl = build_decl (FUNCTION_DECL, stubid,
7913 build_function_type (void_type_node, NULL_TREE));
7914 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7916 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7918 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7922 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7924 fprintf (asm_out_file, "%s%s",
7925 need_comma ? ", " : "",
7926 (f & 3) == 1 ? "float" : "double");
7929 fprintf (asm_out_file, ")\n");
7931 fprintf (asm_out_file, "\t.set\tnomips16\n");
7932 assemble_start_function (stubdecl, stubname);
7934 if (!FUNCTION_NAME_ALREADY_DECLARED)
7936 fputs ("\t.ent\t", asm_out_file);
7937 assemble_name (asm_out_file, stubname);
7938 fputs ("\n", asm_out_file);
7940 assemble_name (asm_out_file, stubname);
7941 fputs (":\n", asm_out_file);
7944 /* We build the stub code by hand. That's the only way we can
7945 do it, since we can't generate 32 bit code during a 16 bit
7948 /* We don't want the assembler to insert any nops here. */
7949 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7951 mips16_fp_args (asm_out_file, fp_code, 0);
7955 fprintf (asm_out_file, "\t.set\tnoat\n");
7956 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7958 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7959 fprintf (asm_out_file, "\t.set\tat\n");
7960 /* Unfortunately, we can't fill the jump delay slot. We
7961 can't fill with one of the mtc1 instructions, because the
7962 result is not available for one instruction, so if the
7963 very first instruction in the function refers to the
7964 register, it will see the wrong value. */
7965 fprintf (asm_out_file, "\tnop\n");
7969 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7970 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7971 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7972 /* As above, we can't fill the delay slot. */
7973 fprintf (asm_out_file, "\tnop\n");
7974 if (GET_MODE (retval) == SFmode)
7975 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7976 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7979 if (TARGET_BIG_ENDIAN)
7981 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7982 reg_names[GP_REG_FIRST + 2],
7983 reg_names[FP_REG_FIRST + 1]);
7984 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7985 reg_names[GP_REG_FIRST + 3],
7986 reg_names[FP_REG_FIRST + 0]);
7990 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7991 reg_names[GP_REG_FIRST + 2],
7992 reg_names[FP_REG_FIRST + 0]);
7993 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7994 reg_names[GP_REG_FIRST + 3],
7995 reg_names[FP_REG_FIRST + 1]);
7998 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7999 /* As above, we can't fill the delay slot. */
8000 fprintf (asm_out_file, "\tnop\n");
8003 fprintf (asm_out_file, "\t.set\treorder\n");
8005 #ifdef ASM_DECLARE_FUNCTION_SIZE
8006 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
8009 if (!FUNCTION_NAME_ALREADY_DECLARED)
8011 fputs ("\t.end\t", asm_out_file);
8012 assemble_name (asm_out_file, stubname);
8013 fputs ("\n", asm_out_file);
8016 fprintf (asm_out_file, "\t.set\tmips16\n");
8018 /* Record this stub. */
8019 l = (struct mips16_stub *) xmalloc (sizeof *l);
8020 l->name = xstrdup (fnname);
8022 l->next = mips16_stubs;
8026 /* If we expect a floating point return value, but we've built a
8027 stub which does not expect one, then we're in trouble. We can't
8028 use the existing stub, because it won't handle the floating point
8029 value. We can't build a new stub, because the linker won't know
8030 which stub to use for the various calls in this object file.
8031 Fortunately, this case is illegal, since it means that a function
8032 was declared in two different ways in a single compilation. */
8033 if (fpret && ! l->fpret)
8034 error ("can not handle inconsistent calls to `%s'", fnname);
8036 /* If we are calling a stub which handles a floating point return
8037 value, we need to arrange to save $18 in the prologue. We do
8038 this by marking the function call as using the register. The
8039 prologue will later see that it is used, and emit code to save
8046 if (retval == NULL_RTX)
8047 insn = gen_call_internal (fn, arg_size);
8049 insn = gen_call_value_internal (retval, fn, arg_size);
8050 insn = emit_call_insn (insn);
8052 if (GET_CODE (insn) != CALL_INSN)
8055 CALL_INSN_FUNCTION_USAGE (insn) =
8056 gen_rtx_EXPR_LIST (VOIDmode,
8057 gen_rtx_USE (VOIDmode, gen_rtx_REG (word_mode, 18)),
8058 CALL_INSN_FUNCTION_USAGE (insn));
8060 /* Return 1 to tell the caller that we've generated the call
8065 /* Return 0 to let the caller generate the call insn. */
8069 /* An entry in the mips16 constant pool. VALUE is the pool constant,
8070 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
8072 struct mips16_constant {
8073 struct mips16_constant *next;
8076 enum machine_mode mode;
8079 /* Information about an incomplete mips16 constant pool. FIRST is the
8080 first constant, HIGHEST_ADDRESS is the highest address that the first
8081 byte of the pool can have, and INSN_ADDRESS is the current instruction
8084 struct mips16_constant_pool {
8085 struct mips16_constant *first;
8086 int highest_address;
8090 /* Add constant VALUE to POOL and return its label. MODE is the
8091 value's mode (used for CONST_INTs, etc.). */
8094 add_constant (struct mips16_constant_pool *pool,
8095 rtx value, enum machine_mode mode)
8097 struct mips16_constant **p, *c;
8098 bool first_of_size_p;
8100 /* See whether the constant is already in the pool. If so, return the
8101 existing label, otherwise leave P pointing to the place where the
8102 constant should be added.
8104 Keep the pool sorted in increasing order of mode size so that we can
8105 reduce the number of alignments needed. */
8106 first_of_size_p = true;
8107 for (p = &pool->first; *p != 0; p = &(*p)->next)
8109 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
8111 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
8113 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
8114 first_of_size_p = false;
8117 /* In the worst case, the constant needed by the earliest instruction
8118 will end up at the end of the pool. The entire pool must then be
8119 accessible from that instruction.
8121 When adding the first constant, set the pool's highest address to
8122 the address of the first out-of-range byte. Adjust this address
8123 downwards each time a new constant is added. */
8124 if (pool->first == 0)
8125 /* For pc-relative lw, addiu and daddiu instructions, the base PC value
8126 is the address of the instruction with the lowest two bits clear.
8127 The base PC value for ld has the lowest three bits clear. Assume
8128 the worst case here. */
8129 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
8130 pool->highest_address -= GET_MODE_SIZE (mode);
8131 if (first_of_size_p)
8132 /* Take into account the worst possible padding due to alignment. */
8133 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
8135 /* Create a new entry. */
8136 c = (struct mips16_constant *) xmalloc (sizeof *c);
8139 c->label = gen_label_rtx ();
8146 /* Output constant VALUE after instruction INSN and return the last
8147 instruction emitted. MODE is the mode of the constant. */
8150 dump_constants_1 (enum machine_mode mode, rtx value, rtx insn)
8152 switch (GET_MODE_CLASS (mode))
8156 rtx size = GEN_INT (GET_MODE_SIZE (mode));
8157 return emit_insn_after (gen_consttable_int (value, size), insn);
8161 return emit_insn_after (gen_consttable_float (value), insn);
8163 case MODE_VECTOR_FLOAT:
8164 case MODE_VECTOR_INT:
8167 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
8168 insn = dump_constants_1 (GET_MODE_INNER (mode),
8169 CONST_VECTOR_ELT (value, i), insn);
8179 /* Dump out the constants in CONSTANTS after INSN. */
8182 dump_constants (struct mips16_constant *constants, rtx insn)
8184 struct mips16_constant *c, *next;
8188 for (c = constants; c != NULL; c = next)
8190 /* If necessary, increase the alignment of PC. */
8191 if (align < GET_MODE_SIZE (c->mode))
8193 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
8194 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
8196 align = GET_MODE_SIZE (c->mode);
8198 insn = emit_label_after (c->label, insn);
8199 insn = dump_constants_1 (c->mode, c->value, insn);
8205 emit_barrier_after (insn);
8208 /* Return the length of instruction INSN.
8210 ??? MIPS16 switch tables go in .text, but we don't define
8211 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8212 compute their lengths correctly. */
8215 mips16_insn_length (rtx insn)
8217 if (GET_CODE (insn) == JUMP_INSN)
8219 rtx body = PATTERN (insn);
8220 if (GET_CODE (body) == ADDR_VEC)
8221 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
8222 if (GET_CODE (body) == ADDR_DIFF_VEC)
8223 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
8225 return get_attr_length (insn);
8228 /* Rewrite *X so that constant pool references refer to the constant's
8229 label instead. DATA points to the constant pool structure. */
8232 mips16_rewrite_pool_refs (rtx *x, void *data)
8234 struct mips16_constant_pool *pool = data;
8235 if (GET_CODE (*x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (*x))
8236 *x = gen_rtx_LABEL_REF (Pmode, add_constant (pool,
8237 get_pool_constant (*x),
8238 get_pool_mode (*x)));
8242 /* Build MIPS16 constant pools. */
8245 mips16_lay_out_constants (void)
8247 struct mips16_constant_pool pool;
8251 memset (&pool, 0, sizeof (pool));
8252 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8254 /* Rewrite constant pool references in INSN. */
8256 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &pool);
8258 pool.insn_address += mips16_insn_length (insn);
8260 if (pool.first != NULL)
8262 /* If there are no natural barriers between the first user of
8263 the pool and the highest acceptable address, we'll need to
8264 create a new instruction to jump around the constant pool.
8265 In the worst case, this instruction will be 4 bytes long.
8267 If it's too late to do this transformation after INSN,
8268 do it immediately before INSN. */
8269 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
8273 label = gen_label_rtx ();
8275 jump = emit_jump_insn_before (gen_jump (label), insn);
8276 JUMP_LABEL (jump) = label;
8277 LABEL_NUSES (label) = 1;
8278 barrier = emit_barrier_after (jump);
8280 emit_label_after (label, barrier);
8281 pool.insn_address += 4;
8284 /* See whether the constant pool is now out of range of the first
8285 user. If so, output the constants after the previous barrier.
8286 Note that any instructions between BARRIER and INSN (inclusive)
8287 will use negative offsets to refer to the pool. */
8288 if (pool.insn_address > pool.highest_address)
8290 dump_constants (pool.first, barrier);
8294 else if (BARRIER_P (insn))
8298 dump_constants (pool.first, get_last_insn ());
8301 /* A temporary variable used by for_each_rtx callbacks, etc. */
8302 static rtx mips_sim_insn;
8304 /* A structure representing the state of the processor pipeline.
8305 Used by the mips_sim_* family of functions. */
8307 /* The maximum number of instructions that can be issued in a cycle.
8308 (Caches mips_issue_rate.) */
8309 unsigned int issue_rate;
8311 /* The current simulation time. */
8314 /* How many more instructions can be issued in the current cycle. */
8315 unsigned int insns_left;
8317 /* LAST_SET[X].INSN is the last instruction to set register X.
8318 LAST_SET[X].TIME is the time at which that instruction was issued.
8319 INSN is null if no instruction has yet set register X. */
8323 } last_set[FIRST_PSEUDO_REGISTER];
8325 /* The pipeline's current DFA state. */
8329 /* Reset STATE to the initial simulation state. */
8332 mips_sim_reset (struct mips_sim *state)
8335 state->insns_left = state->issue_rate;
8336 memset (&state->last_set, 0, sizeof (state->last_set));
8337 state_reset (state->dfa_state);
8340 /* Initialize STATE before its first use. DFA_STATE points to an
8341 allocated but uninitialized DFA state. */
8344 mips_sim_init (struct mips_sim *state, state_t dfa_state)
8346 state->issue_rate = mips_issue_rate ();
8347 state->dfa_state = dfa_state;
8348 mips_sim_reset (state);
8351 /* Advance STATE by one clock cycle. */
8354 mips_sim_next_cycle (struct mips_sim *state)
8357 state->insns_left = state->issue_rate;
8358 state_transition (state->dfa_state, 0);
8361 /* Advance simulation state STATE until instruction INSN can read
8365 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
8369 for (i = 0; i < HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)); i++)
8370 if (state->last_set[REGNO (reg) + i].insn != 0)
8374 t = state->last_set[REGNO (reg) + i].time;
8375 t += insn_latency (state->last_set[REGNO (reg) + i].insn, insn);
8376 while (state->time < t)
8377 mips_sim_next_cycle (state);
8381 /* A for_each_rtx callback. If *X is a register, advance simulation state
8382 DATA until mips_sim_insn can read the register's value. */
8385 mips_sim_wait_regs_2 (rtx *x, void *data)
8388 mips_sim_wait_reg (data, mips_sim_insn, *x);
8392 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
8395 mips_sim_wait_regs_1 (rtx *x, void *data)
8397 for_each_rtx (x, mips_sim_wait_regs_2, data);
8400 /* Advance simulation state STATE until all of INSN's register
8401 dependencies are satisfied. */
8404 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
8406 mips_sim_insn = insn;
8407 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
8410 /* Advance simulation state STATE until the units required by
8411 instruction INSN are available. */
8414 mips_sim_wait_units (struct mips_sim *state, rtx insn)
8418 tmp_state = alloca (state_size ());
8419 while (state->insns_left == 0
8420 || (memcpy (tmp_state, state->dfa_state, state_size ()),
8421 state_transition (tmp_state, insn) >= 0))
8422 mips_sim_next_cycle (state);
8425 /* Advance simulation state STATE until INSN is ready to issue. */
8428 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
8430 mips_sim_wait_regs (state, insn);
8431 mips_sim_wait_units (state, insn);
8434 /* mips_sim_insn has just set X. Update the LAST_SET array
8435 in simulation state DATA. */
8438 mips_sim_record_set (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
8440 struct mips_sim *state;
8445 for (i = 0; i < HARD_REGNO_NREGS (REGNO (x), GET_MODE (x)); i++)
8447 state->last_set[REGNO (x) + i].insn = mips_sim_insn;
8448 state->last_set[REGNO (x) + i].time = state->time;
8452 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
8453 can issue immediately (i.e., that mips_sim_wait_insn has already
8457 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
8459 state_transition (state->dfa_state, insn);
8460 state->insns_left--;
8462 mips_sim_insn = insn;
8463 note_stores (PATTERN (insn), mips_sim_record_set, state);
8466 /* Simulate issuing a NOP in state STATE. */
8469 mips_sim_issue_nop (struct mips_sim *state)
8471 if (state->insns_left == 0)
8472 mips_sim_next_cycle (state);
8473 state->insns_left--;
8476 /* Update simulation state STATE so that it's ready to accept the instruction
8477 after INSN. INSN should be part of the main rtl chain, not a member of a
8481 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
8483 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
8485 mips_sim_issue_nop (state);
8487 switch (GET_CODE (SEQ_BEGIN (insn)))
8491 /* We can't predict the processor state after a call or label. */
8492 mips_sim_reset (state);
8496 /* The delay slots of branch likely instructions are only executed
8497 when the branch is taken. Therefore, if the caller has simulated
8498 the delay slot instruction, STATE does not really reflect the state
8499 of the pipeline for the instruction after the delay slot. Also,
8500 branch likely instructions tend to incur a penalty when not taken,
8501 so there will probably be an extra delay between the branch and
8502 the instruction after the delay slot. */
8503 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
8504 mips_sim_reset (state);
8512 /* The VR4130 pipeline issues aligned pairs of instructions together,
8513 but it stalls the second instruction if it depends on the first.
8514 In order to cut down the amount of logic required, this dependence
8515 check is not based on a full instruction decode. Instead, any non-SPECIAL
8516 instruction is assumed to modify the register specified by bits 20-16
8517 (which is usually the "rt" field).
8519 In beq, beql, bne and bnel instructions, the rt field is actually an
8520 input, so we can end up with a false dependence between the branch
8521 and its delay slot. If this situation occurs in instruction INSN,
8522 try to avoid it by swapping rs and rt. */
8525 vr4130_avoid_branch_rt_conflict (rtx insn)
8529 first = SEQ_BEGIN (insn);
8530 second = SEQ_END (insn);
8531 if (GET_CODE (first) == JUMP_INSN
8532 && GET_CODE (second) == INSN
8533 && GET_CODE (PATTERN (first)) == SET
8534 && GET_CODE (SET_DEST (PATTERN (first))) == PC
8535 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
8537 /* Check for the right kind of condition. */
8538 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
8539 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
8540 && REG_P (XEXP (cond, 0))
8541 && REG_P (XEXP (cond, 1))
8542 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
8543 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
8545 /* SECOND mentions the rt register but not the rs register. */
8546 rtx tmp = XEXP (cond, 0);
8547 XEXP (cond, 0) = XEXP (cond, 1);
8548 XEXP (cond, 1) = tmp;
8553 /* Implement -mvr4130-align. Go through each basic block and simulate the
8554 processor pipeline. If we find that a pair of instructions could execute
8555 in parallel, and the first of those instruction is not 8-byte aligned,
8556 insert a nop to make it aligned. */
8559 vr4130_align_insns (void)
8561 struct mips_sim state;
8562 rtx insn, subinsn, last, last2, next;
8567 /* LAST is the last instruction before INSN to have a nonzero length.
8568 LAST2 is the last such instruction before LAST. */
8572 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
8575 mips_sim_init (&state, alloca (state_size ()));
8576 for (insn = get_insns (); insn != 0; insn = next)
8578 unsigned int length;
8580 next = NEXT_INSN (insn);
8582 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
8583 This isn't really related to the alignment pass, but we do it on
8584 the fly to avoid a separate instruction walk. */
8585 vr4130_avoid_branch_rt_conflict (insn);
8587 if (USEFUL_INSN_P (insn))
8588 FOR_EACH_SUBINSN (subinsn, insn)
8590 mips_sim_wait_insn (&state, subinsn);
8592 /* If we want this instruction to issue in parallel with the
8593 previous one, make sure that the previous instruction is
8594 aligned. There are several reasons why this isn't worthwhile
8595 when the second instruction is a call:
8597 - Calls are less likely to be performance critical,
8598 - There's a good chance that the delay slot can execute
8599 in parallel with the call.
8600 - The return address would then be unaligned.
8602 In general, if we're going to insert a nop between instructions
8603 X and Y, it's better to insert it immediately after X. That
8604 way, if the nop makes Y aligned, it will also align any labels
8606 if (state.insns_left != state.issue_rate
8607 && GET_CODE (subinsn) != CALL_INSN)
8609 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
8611 /* SUBINSN is the first instruction in INSN and INSN is
8612 aligned. We want to align the previous instruction
8613 instead, so insert a nop between LAST2 and LAST.
8615 Note that LAST could be either a single instruction
8616 or a branch with a delay slot. In the latter case,
8617 LAST, like INSN, is already aligned, but the delay
8618 slot must have some extra delay that stops it from
8619 issuing at the same time as the branch. We therefore
8620 insert a nop before the branch in order to align its
8622 emit_insn_after (gen_nop (), last2);
8625 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
8627 /* SUBINSN is the delay slot of INSN, but INSN is
8628 currently unaligned. Insert a nop between
8629 LAST and INSN to align it. */
8630 emit_insn_after (gen_nop (), last);
8634 mips_sim_issue_insn (&state, subinsn);
8636 mips_sim_finish_insn (&state, insn);
8638 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
8639 length = get_attr_length (insn);
8642 /* If the instruction is an asm statement or multi-instruction
8643 mips.md patern, the length is only an estimate. Insert an
8644 8 byte alignment after it so that the following instructions
8645 can be handled correctly. */
8646 if (GET_CODE (SEQ_BEGIN (insn)) == INSN
8647 && (recog_memoized (insn) < 0 || length >= 8))
8649 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
8650 next = NEXT_INSN (next);
8651 mips_sim_next_cycle (&state);
8654 else if (length & 4)
8655 aligned_p = !aligned_p;
8660 /* See whether INSN is an aligned label. */
8661 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
8667 /* Subroutine of mips_reorg. If there is a hazard between INSN
8668 and a previous instruction, avoid it by inserting nops after
8671 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
8672 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
8673 before using the value of that register. *HILO_DELAY counts the
8674 number of instructions since the last hilo hazard (that is,
8675 the number of instructions since the last mflo or mfhi).
8677 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
8678 for the next instruction.
8680 LO_REG is an rtx for the LO register, used in dependence checking. */
8683 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
8684 rtx *delayed_reg, rtx lo_reg)
8692 pattern = PATTERN (insn);
8694 /* Do not put the whole function in .set noreorder if it contains
8695 an asm statement. We don't know whether there will be hazards
8696 between the asm statement and the gcc-generated code. */
8697 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
8698 cfun->machine->all_noreorder_p = false;
8700 /* Ignore zero-length instructions (barriers and the like). */
8701 ninsns = get_attr_length (insn) / 4;
8705 /* Work out how many nops are needed. Note that we only care about
8706 registers that are explicitly mentioned in the instruction's pattern.
8707 It doesn't matter that calls use the argument registers or that they
8708 clobber hi and lo. */
8709 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
8710 nops = 2 - *hilo_delay;
8711 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
8716 /* Insert the nops between this instruction and the previous one.
8717 Each new nop takes us further from the last hilo hazard. */
8718 *hilo_delay += nops;
8720 emit_insn_after (gen_hazard_nop (), after);
8722 /* Set up the state for the next instruction. */
8723 *hilo_delay += ninsns;
8725 if (INSN_CODE (insn) >= 0)
8726 switch (get_attr_hazard (insn))
8736 set = single_set (insn);
8739 *delayed_reg = SET_DEST (set);
8745 /* Go through the instruction stream and insert nops where necessary.
8746 See if the whole function can then be put into .set noreorder &
8750 mips_avoid_hazards (void)
8752 rtx insn, last_insn, lo_reg, delayed_reg;
8755 /* Force all instructions to be split into their final form. */
8756 split_all_insns_noflow ();
8758 /* Recalculate instruction lengths without taking nops into account. */
8759 cfun->machine->ignore_hazard_length_p = true;
8760 shorten_branches (get_insns ());
8762 /* The profiler code uses assembler macros. -mfix-vr4120 relies on
8763 assembler nop insertion. */
8764 cfun->machine->all_noreorder_p = (!current_function_profile
8765 && !TARGET_FIX_VR4120);
8770 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
8772 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
8775 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
8776 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8777 mips_avoid_hazard (last_insn, XVECEXP (PATTERN (insn), 0, i),
8778 &hilo_delay, &delayed_reg, lo_reg);
8780 mips_avoid_hazard (last_insn, insn, &hilo_delay,
8781 &delayed_reg, lo_reg);
8788 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
8794 mips16_lay_out_constants ();
8795 else if (TARGET_EXPLICIT_RELOCS)
8797 if (mips_flag_delayed_branch)
8798 dbr_schedule (get_insns (), dump_file);
8799 mips_avoid_hazards ();
8800 if (TUNE_MIPS4130 && TARGET_VR4130_ALIGN)
8801 vr4130_align_insns ();
8805 /* This function does three things:
8807 - Register the special divsi3 and modsi3 functions if -mfix-vr4120.
8808 - Register the mips16 hardware floating point stubs.
8809 - Register the gofast functions if selected using --enable-gofast. */
8811 #include "config/gofast.h"
8814 mips_init_libfuncs (void)
8816 if (TARGET_FIX_VR4120)
8818 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
8819 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
8822 if (TARGET_MIPS16 && mips16_hard_float)
8824 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
8825 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
8826 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
8827 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
8829 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
8830 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
8831 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
8832 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
8833 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
8834 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
8836 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
8837 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
8839 if (TARGET_DOUBLE_FLOAT)
8841 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
8842 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
8843 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
8844 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
8846 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
8847 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
8848 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
8849 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
8850 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
8851 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
8853 set_conv_libfunc (sext_optab, DFmode, SFmode, "__mips16_extendsfdf2");
8854 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__mips16_truncdfsf2");
8856 set_conv_libfunc (sfix_optab, SImode, DFmode, "__mips16_fix_truncdfsi");
8857 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__mips16_floatsidf");
8861 gofast_maybe_init_libfuncs ();
8864 /* Return a number assessing the cost of moving a register in class
8865 FROM to class TO. The classes are expressed using the enumeration
8866 values such as `GENERAL_REGS'. A value of 2 is the default; other
8867 values are interpreted relative to that.
8869 It is not required that the cost always equal 2 when FROM is the
8870 same as TO; on some machines it is expensive to move between
8871 registers if they are not general registers.
8873 If reload sees an insn consisting of a single `set' between two
8874 hard registers, and if `REGISTER_MOVE_COST' applied to their
8875 classes returns a value of 2, reload does not check to ensure that
8876 the constraints of the insn are met. Setting a cost of other than
8877 2 will allow reload to verify that the constraints are met. You
8878 should do this if the `movM' pattern's constraints do not allow
8881 ??? We make the cost of moving from HI/LO into general
8882 registers the same as for one of moving general registers to
8883 HI/LO for TARGET_MIPS16 in order to prevent allocating a
8884 pseudo to HI/LO. This might hurt optimizations though, it
8885 isn't clear if it is wise. And it might not work in all cases. We
8886 could solve the DImode LO reg problem by using a multiply, just
8887 like reload_{in,out}si. We could solve the SImode/HImode HI reg
8888 problem by using divide instructions. divu puts the remainder in
8889 the HI reg, so doing a divide by -1 will move the value in the HI
8890 reg for all values except -1. We could handle that case by using a
8891 signed divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit
8892 a compare/branch to test the input value to see which instruction
8893 we need to use. This gets pretty messy, but it is feasible. */
8896 mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
8897 enum reg_class to, enum reg_class from)
8899 if (from == M16_REGS && GR_REG_CLASS_P (to))
8901 else if (from == M16_NA_REGS && GR_REG_CLASS_P (to))
8903 else if (GR_REG_CLASS_P (from))
8907 else if (to == M16_NA_REGS)
8909 else if (GR_REG_CLASS_P (to))
8916 else if (to == FP_REGS)
8918 else if (to == HI_REG || to == LO_REG || to == MD_REGS)
8925 else if (COP_REG_CLASS_P (to))
8929 } /* GR_REG_CLASS_P (from) */
8930 else if (from == FP_REGS)
8932 if (GR_REG_CLASS_P (to))
8934 else if (to == FP_REGS)
8936 else if (to == ST_REGS)
8938 } /* from == FP_REGS */
8939 else if (from == HI_REG || from == LO_REG || from == MD_REGS)
8941 if (GR_REG_CLASS_P (to))
8948 } /* from == HI_REG, etc. */
8949 else if (from == ST_REGS && GR_REG_CLASS_P (to))
8951 else if (COP_REG_CLASS_P (from))
8954 } /* COP_REG_CLASS_P (from) */
8961 /* Return the length of INSN. LENGTH is the initial length computed by
8962 attributes in the machine-description file. */
8965 mips_adjust_insn_length (rtx insn, int length)
8967 /* A unconditional jump has an unfilled delay slot if it is not part
8968 of a sequence. A conditional jump normally has a delay slot, but
8969 does not on MIPS16. */
8970 if (simplejump_p (insn)
8971 || (!TARGET_MIPS16 && (GET_CODE (insn) == JUMP_INSN
8972 || GET_CODE (insn) == CALL_INSN)))
8975 /* See how many nops might be needed to avoid hardware hazards. */
8976 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
8977 switch (get_attr_hazard (insn))
8991 /* All MIPS16 instructions are a measly two bytes. */
8999 /* Return an asm sequence to start a noat block and load the address
9000 of a label into $1. */
9003 mips_output_load_label (void)
9005 if (TARGET_EXPLICIT_RELOCS)
9009 return "%[lw\t%@,%%got_page(%0)(%+)\n\taddiu\t%@,%@,%%got_ofst(%0)";
9012 return "%[ld\t%@,%%got_page(%0)(%+)\n\tdaddiu\t%@,%@,%%got_ofst(%0)";
9015 if (ISA_HAS_LOAD_DELAY)
9016 return "%[lw\t%@,%%got(%0)(%+)%#\n\taddiu\t%@,%@,%%lo(%0)";
9017 return "%[lw\t%@,%%got(%0)(%+)\n\taddiu\t%@,%@,%%lo(%0)";
9021 if (Pmode == DImode)
9022 return "%[dla\t%@,%0";
9024 return "%[la\t%@,%0";
9029 /* Output assembly instructions to peform a conditional branch.
9031 INSN is the branch instruction. OPERANDS[0] is the condition.
9032 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
9033 of the first operand to the condition. If TWO_OPERANDS_P is
9034 nonzero the comparison takes two operands; OPERANDS[3] will be the
9037 If INVERTED_P is nonzero we are to branch if the condition does
9038 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
9040 LENGTH is the length (in bytes) of the sequence we are to generate.
9041 That tells us whether to generate a simple conditional branch, or a
9042 reversed conditional branch around a `jr' instruction. */
9044 mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
9045 int float_p, int inverted_p, int length)
9047 static char buffer[200];
9048 /* The kind of comparison we are doing. */
9049 enum rtx_code code = GET_CODE (operands[0]);
9050 /* Nonzero if the opcode for the comparison needs a `z' indicating
9051 that it is a comparison against zero. */
9053 /* A string to use in the assembly output to represent the first
9055 const char *op1 = "%z2";
9056 /* A string to use in the assembly output to represent the second
9057 operand. Use the hard-wired zero register if there's no second
9059 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
9060 /* The operand-printing string for the comparison. */
9061 const char *const comp = (float_p ? "%F0" : "%C0");
9062 /* The operand-printing string for the inverted comparison. */
9063 const char *const inverted_comp = (float_p ? "%W0" : "%N0");
9065 /* The MIPS processors (for levels of the ISA at least two), have
9066 "likely" variants of each branch instruction. These instructions
9067 annul the instruction in the delay slot if the branch is not
9069 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
9071 if (!two_operands_p)
9073 /* To compute whether than A > B, for example, we normally
9074 subtract B from A and then look at the sign bit. But, if we
9075 are doing an unsigned comparison, and B is zero, we don't
9076 have to do the subtraction. Instead, we can just check to
9077 see if A is nonzero. Thus, we change the CODE here to
9078 reflect the simpler comparison operation. */
9090 /* A condition which will always be true. */
9096 /* A condition which will always be false. */
9102 /* Not a special case. */
9107 /* Relative comparisons are always done against zero. But
9108 equality comparisons are done between two operands, and therefore
9109 do not require a `z' in the assembly language output. */
9110 need_z_p = (!float_p && code != EQ && code != NE);
9111 /* For comparisons against zero, the zero is not provided
9116 /* Begin by terminating the buffer. That way we can always use
9117 strcat to add to it. */
9124 /* Just a simple conditional branch. */
9126 sprintf (buffer, "%%*b%s%%?\t%%Z2%%1%%/",
9127 inverted_p ? inverted_comp : comp);
9129 sprintf (buffer, "%%*b%s%s%%?\t%s%s,%%1%%/",
9130 inverted_p ? inverted_comp : comp,
9131 need_z_p ? "z" : "",
9141 /* Generate a reversed conditional branch around ` j'
9154 If the original branch was a likely branch, the delay slot
9155 must be executed only if the branch is taken, so generate:
9167 When generating PIC, instead of:
9180 rtx target = gen_label_rtx ();
9182 orig_target = operands[1];
9183 operands[1] = target;
9184 /* Generate the reversed comparison. This takes four
9187 sprintf (buffer, "%%*b%s\t%%Z2%%1",
9188 inverted_p ? comp : inverted_comp);
9190 sprintf (buffer, "%%*b%s%s\t%s%s,%%1",
9191 inverted_p ? comp : inverted_comp,
9192 need_z_p ? "z" : "",
9195 output_asm_insn (buffer, operands);
9197 if (length != 16 && length != 28 && ! mips_branch_likely)
9199 /* Output delay slot instruction. */
9200 rtx insn = final_sequence;
9201 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9202 optimize, 0, 1, NULL);
9203 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9206 output_asm_insn ("%#", 0);
9209 output_asm_insn ("j\t%0", &orig_target);
9212 output_asm_insn (mips_output_load_label (), &orig_target);
9213 output_asm_insn ("jr\t%@%]", 0);
9216 if (length != 16 && length != 28 && mips_branch_likely)
9218 /* Output delay slot instruction. */
9219 rtx insn = final_sequence;
9220 final_scan_insn (XVECEXP (insn, 0, 1), asm_out_file,
9221 optimize, 0, 1, NULL);
9222 INSN_DELETED_P (XVECEXP (insn, 0, 1)) = 1;
9225 output_asm_insn ("%#", 0);
9227 (*targetm.asm_out.internal_label) (asm_out_file, "L",
9228 CODE_LABEL_NUMBER (target));
9241 /* Used to output div or ddiv instruction DIVISION, which has the operands
9242 given by OPERANDS. Add in a divide-by-zero check if needed.
9244 When working around R4000 and R4400 errata, we need to make sure that
9245 the division is not immediately followed by a shift[1][2]. We also
9246 need to stop the division from being put into a branch delay slot[3].
9247 The easiest way to avoid both problems is to add a nop after the
9248 division. When a divide-by-zero check is needed, this nop can be
9249 used to fill the branch delay slot.
9251 [1] If a double-word or a variable shift executes immediately
9252 after starting an integer division, the shift may give an
9253 incorrect result. See quotations of errata #16 and #28 from
9254 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9255 in mips.md for details.
9257 [2] A similar bug to [1] exists for all revisions of the
9258 R4000 and the R4400 when run in an MC configuration.
9259 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
9261 "19. In this following sequence:
9263 ddiv (or ddivu or div or divu)
9264 dsll32 (or dsrl32, dsra32)
9266 if an MPT stall occurs, while the divide is slipping the cpu
9267 pipeline, then the following double shift would end up with an
9270 Workaround: The compiler needs to avoid generating any
9271 sequence with divide followed by extended double shift."
9273 This erratum is also present in "MIPS R4400MC Errata, Processor
9274 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
9275 & 3.0" as errata #10 and #4, respectively.
9277 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
9278 (also valid for MIPS R4000MC processors):
9280 "52. R4000SC: This bug does not apply for the R4000PC.
9282 There are two flavors of this bug:
9284 1) If the instruction just after divide takes an RF exception
9285 (tlb-refill, tlb-invalid) and gets an instruction cache
9286 miss (both primary and secondary) and the line which is
9287 currently in secondary cache at this index had the first
9288 data word, where the bits 5..2 are set, then R4000 would
9289 get a wrong result for the div.
9294 ------------------- # end-of page. -tlb-refill
9299 ------------------- # end-of page. -tlb-invalid
9302 2) If the divide is in the taken branch delay slot, where the
9303 target takes RF exception and gets an I-cache miss for the
9304 exception vector or where I-cache miss occurs for the
9305 target address, under the above mentioned scenarios, the
9306 div would get wrong results.
9309 j r2 # to next page mapped or unmapped
9310 div r8,r9 # this bug would be there as long
9311 # as there is an ICache miss and
9312 nop # the "data pattern" is present
9315 beq r0, r0, NextPage # to Next page
9319 This bug is present for div, divu, ddiv, and ddivu
9322 Workaround: For item 1), OS could make sure that the next page
9323 after the divide instruction is also mapped. For item 2), the
9324 compiler could make sure that the divide instruction is not in
9325 the branch delay slot."
9327 These processors have PRId values of 0x00004220 and 0x00004300 for
9328 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
9331 mips_output_division (const char *division, rtx *operands)
9336 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
9338 output_asm_insn (s, operands);
9341 if (TARGET_CHECK_ZERO_DIV)
9345 output_asm_insn (s, operands);
9346 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
9350 output_asm_insn ("%(bne\t%2,%.,1f", operands);
9351 output_asm_insn (s, operands);
9352 s = "break\t7%)\n1:";
9358 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
9359 with a final "000" replaced by "k". Ignore case.
9361 Note: this function is shared between GCC and GAS. */
9364 mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
9366 while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
9367 given++, canonical++;
9369 return ((*given == 0 && *canonical == 0)
9370 || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
9374 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
9375 CPU name. We've traditionally allowed a lot of variation here.
9377 Note: this function is shared between GCC and GAS. */
9380 mips_matching_cpu_name_p (const char *canonical, const char *given)
9382 /* First see if the name matches exactly, or with a final "000"
9384 if (mips_strict_matching_cpu_name_p (canonical, given))
9387 /* If not, try comparing based on numerical designation alone.
9388 See if GIVEN is an unadorned number, or 'r' followed by a number. */
9389 if (TOLOWER (*given) == 'r')
9391 if (!ISDIGIT (*given))
9394 /* Skip over some well-known prefixes in the canonical name,
9395 hoping to find a number there too. */
9396 if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
9398 else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
9400 else if (TOLOWER (canonical[0]) == 'r')
9403 return mips_strict_matching_cpu_name_p (canonical, given);
9407 /* Parse an option that takes the name of a processor as its argument.
9408 OPTION is the name of the option and CPU_STRING is the argument.
9409 Return the corresponding processor enumeration if the CPU_STRING is
9410 recognized, otherwise report an error and return null.
9412 A similar function exists in GAS. */
9414 static const struct mips_cpu_info *
9415 mips_parse_cpu (const char *option, const char *cpu_string)
9417 const struct mips_cpu_info *p;
9420 /* In the past, we allowed upper-case CPU names, but it doesn't
9421 work well with the multilib machinery. */
9422 for (s = cpu_string; *s != 0; s++)
9425 warning ("the cpu name must be lower case");
9429 /* 'from-abi' selects the most compatible architecture for the given
9430 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
9431 EABIs, we have to decide whether we're using the 32-bit or 64-bit
9432 version. Look first at the -mgp options, if given, otherwise base
9433 the choice on MASK_64BIT in TARGET_DEFAULT. */
9434 if (strcasecmp (cpu_string, "from-abi") == 0)
9435 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
9436 : ABI_NEEDS_64BIT_REGS ? 3
9437 : (TARGET_64BIT ? 3 : 1));
9439 /* 'default' has traditionally been a no-op. Probably not very useful. */
9440 if (strcasecmp (cpu_string, "default") == 0)
9443 for (p = mips_cpu_info_table; p->name != 0; p++)
9444 if (mips_matching_cpu_name_p (p->name, cpu_string))
9447 error ("bad value (%s) for %s", cpu_string, option);
9452 /* Return the processor associated with the given ISA level, or null
9453 if the ISA isn't valid. */
9455 static const struct mips_cpu_info *
9456 mips_cpu_info_from_isa (int isa)
9458 const struct mips_cpu_info *p;
9460 for (p = mips_cpu_info_table; p->name != 0; p++)
9467 /* Implement HARD_REGNO_NREGS. The size of FP registers are controlled
9468 by UNITS_PER_FPREG. All other registers are word sized. */
9471 mips_hard_regno_nregs (int regno, enum machine_mode mode)
9473 if (! FP_REG_P (regno))
9474 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
9476 return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
9479 /* Implement TARGET_RETURN_IN_MEMORY. Under the old (i.e., 32 and O64 ABIs)
9480 all BLKmode objects are returned in memory. Under the new (N32 and
9481 64-bit MIPS ABIs) small structures are returned in a register.
9482 Objects with varying size must still be returned in memory, of
9486 mips_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
9489 return (TYPE_MODE (type) == BLKmode);
9491 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
9492 || (int_size_in_bytes (type) == -1));
9496 mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED)
9498 return !TARGET_OLDABI;
9501 /* Return true if INSN is a multiply-add or multiply-subtract
9502 instruction and PREV assigns to the accumulator operand. */
9505 mips_linked_madd_p (rtx prev, rtx insn)
9509 x = single_set (insn);
9515 if (GET_CODE (x) == PLUS
9516 && GET_CODE (XEXP (x, 0)) == MULT
9517 && reg_set_p (XEXP (x, 1), prev))
9520 if (GET_CODE (x) == MINUS
9521 && GET_CODE (XEXP (x, 1)) == MULT
9522 && reg_set_p (XEXP (x, 0), prev))
9528 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
9529 that may clobber hi or lo. */
9531 static rtx mips_macc_chains_last_hilo;
9533 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
9534 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
9537 mips_macc_chains_record (rtx insn)
9539 if (get_attr_may_clobber_hilo (insn))
9540 mips_macc_chains_last_hilo = insn;
9543 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
9544 has NREADY elements, looking for a multiply-add or multiply-subtract
9545 instruction that is cumulative with mips_macc_chains_last_hilo.
9546 If there is one, promote it ahead of anything else that might
9547 clobber hi or lo. */
9550 mips_macc_chains_reorder (rtx *ready, int nready)
9554 if (mips_macc_chains_last_hilo != 0)
9555 for (i = nready - 1; i >= 0; i--)
9556 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
9558 for (j = nready - 1; j > i; j--)
9559 if (recog_memoized (ready[j]) >= 0
9560 && get_attr_may_clobber_hilo (ready[j]))
9562 mips_promote_ready (ready, i, j);
9569 /* The last instruction to be scheduled. */
9571 static rtx vr4130_last_insn;
9573 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
9574 points to an rtx that is initially an instruction. Nullify the rtx
9575 if the instruction uses the value of register X. */
9578 vr4130_true_reg_dependence_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
9580 rtx *insn_ptr = data;
9583 && reg_referenced_p (x, PATTERN (*insn_ptr)))
9587 /* Return true if there is true register dependence between vr4130_last_insn
9591 vr4130_true_reg_dependence_p (rtx insn)
9593 note_stores (PATTERN (vr4130_last_insn),
9594 vr4130_true_reg_dependence_p_1, &insn);
9598 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
9599 the ready queue and that INSN2 is the instruction after it, return
9600 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
9601 in which INSN1 and INSN2 can probably issue in parallel, but for
9602 which (INSN2, INSN1) should be less sensitive to instruction
9603 alignment than (INSN1, INSN2). See 4130.md for more details. */
9606 vr4130_swap_insns_p (rtx insn1, rtx insn2)
9610 /* Check for the following case:
9612 1) there is some other instruction X with an anti dependence on INSN1;
9613 2) X has a higher priority than INSN2; and
9614 3) X is an arithmetic instruction (and thus has no unit restrictions).
9616 If INSN1 is the last instruction blocking X, it would better to
9617 choose (INSN1, X) over (INSN2, INSN1). */
9618 for (dep = INSN_DEPEND (insn1); dep != 0; dep = XEXP (dep, 1))
9619 if (REG_NOTE_KIND (dep) == REG_DEP_ANTI
9620 && INSN_PRIORITY (XEXP (dep, 0)) > INSN_PRIORITY (insn2)
9621 && recog_memoized (XEXP (dep, 0)) >= 0
9622 && get_attr_vr4130_class (XEXP (dep, 0)) == VR4130_CLASS_ALU)
9625 if (vr4130_last_insn != 0
9626 && recog_memoized (insn1) >= 0
9627 && recog_memoized (insn2) >= 0)
9629 /* See whether INSN1 and INSN2 use different execution units,
9630 or if they are both ALU-type instructions. If so, they can
9631 probably execute in parallel. */
9632 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
9633 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
9634 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
9636 /* If only one of the instructions has a dependence on
9637 vr4130_last_insn, prefer to schedule the other one first. */
9638 bool dep1 = vr4130_true_reg_dependence_p (insn1);
9639 bool dep2 = vr4130_true_reg_dependence_p (insn2);
9643 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
9644 is not an ALU-type instruction and if INSN1 uses the same
9645 execution unit. (Note that if this condition holds, we already
9646 know that INSN2 uses a different execution unit.) */
9647 if (class1 != VR4130_CLASS_ALU
9648 && recog_memoized (vr4130_last_insn) >= 0
9649 && class1 == get_attr_vr4130_class (vr4130_last_insn))
9656 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
9657 queue with at least two instructions. Swap the first two if
9658 vr4130_swap_insns_p says that it could be worthwhile. */
9661 vr4130_reorder (rtx *ready, int nready)
9663 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
9664 mips_promote_ready (ready, nready - 2, nready - 1);
9667 /* Remove the instruction at index LOWER from ready queue READY and
9668 reinsert it in front of the instruction at index HIGHER. LOWER must
9672 mips_promote_ready (rtx *ready, int lower, int higher)
9677 new_head = ready[lower];
9678 for (i = lower; i < higher; i++)
9679 ready[i] = ready[i + 1];
9680 ready[i] = new_head;
9683 /* Implement TARGET_SCHED_REORDER. */
9686 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9687 rtx *ready, int *nreadyp, int cycle)
9689 if (!reload_completed && TUNE_MACC_CHAINS)
9692 mips_macc_chains_last_hilo = 0;
9694 mips_macc_chains_reorder (ready, *nreadyp);
9696 if (reload_completed && TUNE_MIPS4130 && !TARGET_VR4130_ALIGN)
9699 vr4130_last_insn = 0;
9701 vr4130_reorder (ready, *nreadyp);
9703 return mips_issue_rate ();
9706 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9709 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
9712 switch (GET_CODE (PATTERN (insn)))
9716 /* Don't count USEs and CLOBBERs against the issue rate. */
9721 if (!reload_completed && TUNE_MACC_CHAINS)
9722 mips_macc_chains_record (insn);
9723 vr4130_last_insn = insn;
9729 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
9730 dependencies have no cost. */
9733 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
9734 rtx dep ATTRIBUTE_UNUSED, int cost)
9736 if (REG_NOTE_KIND (link) != 0)
9741 /* Return the number of instructions that can be issued per cycle. */
9744 mips_issue_rate (void)
9748 case PROCESSOR_R4130:
9749 case PROCESSOR_R5400:
9750 case PROCESSOR_R5500:
9751 case PROCESSOR_R7000:
9752 case PROCESSOR_R9000:
9756 /* This is actually 4, but we get better performance if we claim 3.
9757 This is partly because of unwanted speculative code motion with the
9758 larger number, and partly because in most common cases we can't
9759 reach the theoretical max of 4. */
9770 /* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
9771 be as wide as the scheduling freedom in the DFA. */
9774 mips_multipass_dfa_lookahead (void)
9776 /* Can schedule up to 4 of the 6 function units in any one cycle. */
9777 if (mips_tune == PROCESSOR_SB1)
9785 mips_emit_prefetch (rtx *operands)
9787 int write = INTVAL (operands[1]);
9788 int locality = INTVAL (operands[2]);
9789 int indexed = GET_CODE (operands[3]) == REG;
9794 code = (write ? 5 : 4); /* store_streamed / load_streamed. */
9795 else if (locality <= 2)
9796 code = (write ? 1 : 0); /* store / load. */
9798 code = (write ? 7 : 6); /* store_retained / load_retained. */
9800 sprintf (buffer, "%s\t%d,%%3(%%0)", indexed ? "prefx" : "pref", code);
9801 output_asm_insn (buffer, operands);
9808 /* Output assembly to switch to section NAME with attribute FLAGS. */
9811 irix_asm_named_section_1 (const char *name, unsigned int flags,
9814 unsigned int sh_type, sh_flags, sh_entsize;
9817 if (!(flags & SECTION_DEBUG))
9818 sh_flags |= 2; /* SHF_ALLOC */
9819 if (flags & SECTION_WRITE)
9820 sh_flags |= 1; /* SHF_WRITE */
9821 if (flags & SECTION_CODE)
9822 sh_flags |= 4; /* SHF_EXECINSTR */
9823 if (flags & SECTION_SMALL)
9824 sh_flags |= 0x10000000; /* SHF_MIPS_GPREL */
9825 if (strcmp (name, ".debug_frame") == 0)
9826 sh_flags |= 0x08000000; /* SHF_MIPS_NOSTRIP */
9827 if (flags & SECTION_DEBUG)
9828 sh_type = 0x7000001e; /* SHT_MIPS_DWARF */
9829 else if (flags & SECTION_BSS)
9830 sh_type = 8; /* SHT_NOBITS */
9832 sh_type = 1; /* SHT_PROGBITS */
9834 if (flags & SECTION_CODE)
9839 fprintf (asm_out_file, "\t.section %s,%#x,%#x,%u,%u\n",
9840 name, sh_type, sh_flags, sh_entsize, align);
9844 irix_asm_named_section (const char *name, unsigned int flags)
9846 if (TARGET_SGI_O32_AS)
9847 default_no_named_section (name, flags);
9848 else if (mips_abi == ABI_32 && TARGET_GAS)
9849 default_elf_asm_named_section (name, flags);
9851 irix_asm_named_section_1 (name, flags, 0);
9854 /* In addition to emitting a .align directive, record the maximum
9855 alignment requested for the current section. */
9857 struct irix_section_align_entry GTY (())
9864 static htab_t irix_section_align_htab;
9865 static FILE *irix_orig_asm_out_file;
9868 irix_section_align_entry_eq (const void *p1, const void *p2)
9870 const struct irix_section_align_entry *old = p1;
9871 const char *new = p2;
9873 return strcmp (old->name, new) == 0;
9877 irix_section_align_entry_hash (const void *p)
9879 const struct irix_section_align_entry *old = p;
9880 return htab_hash_string (old->name);
9884 irix_asm_output_align (FILE *file, unsigned int log)
9886 const char *section = current_section_name ();
9887 struct irix_section_align_entry **slot, *entry;
9889 if (mips_abi != ABI_32)
9894 slot = (struct irix_section_align_entry **)
9895 htab_find_slot_with_hash (irix_section_align_htab, section,
9896 htab_hash_string (section), INSERT);
9900 entry = (struct irix_section_align_entry *)
9901 xmalloc (sizeof (struct irix_section_align_entry));
9903 entry->name = section;
9905 entry->flags = current_section_flags ();
9907 else if (entry->log < log)
9911 fprintf (file, "\t.align\t%u\n", log);
9914 /* The IRIX assembler does not record alignment from .align directives,
9915 but takes it from the first .section directive seen. Play file
9916 switching games so that we can emit a .section directive at the
9917 beginning of the file with the proper alignment attached. */
9920 irix_file_start (void)
9924 if (mips_abi == ABI_32)
9927 irix_orig_asm_out_file = asm_out_file;
9928 asm_out_file = tmpfile ();
9930 irix_section_align_htab = htab_create (31, irix_section_align_entry_hash,
9931 irix_section_align_entry_eq, NULL);
9935 irix_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
9937 const struct irix_section_align_entry *entry
9938 = *(const struct irix_section_align_entry **) slot;
9940 irix_asm_named_section_1 (entry->name, entry->flags, 1 << entry->log);
9945 copy_file_data (FILE *to, FILE *from)
9951 fatal_error ("can't rewind temp file: %m");
9953 while ((len = fread (buffer, 1, sizeof (buffer), from)) > 0)
9954 if (fwrite (buffer, 1, len, to) != len)
9955 fatal_error ("can't write to output file: %m");
9958 fatal_error ("can't read from temp file: %m");
9961 fatal_error ("can't close temp file: %m");
9965 irix_file_end (void)
9967 if (mips_abi != ABI_32)
9969 /* Emit section directives with the proper alignment at the top of the
9970 real output file. */
9971 FILE *temp = asm_out_file;
9972 asm_out_file = irix_orig_asm_out_file;
9973 htab_traverse (irix_section_align_htab, irix_section_align_1, NULL);
9975 /* Copy the data emitted to the temp file to the real output file. */
9976 copy_file_data (asm_out_file, temp);
9983 /* Implement TARGET_SECTION_TYPE_FLAGS. Make sure that .sdata and
9984 .sbss sections get the SECTION_SMALL flag: this isn't set by the
9988 irix_section_type_flags (tree decl, const char *section, int relocs_p)
9992 flags = default_section_type_flags (decl, section, relocs_p);
9994 if (strcmp (section, ".sdata") == 0
9995 || strcmp (section, ".sbss") == 0
9996 || strncmp (section, ".gnu.linkonce.s.", 16) == 0
9997 || strncmp (section, ".gnu.linkonce.sb.", 17) == 0)
9998 flags |= SECTION_SMALL;
10003 #endif /* TARGET_IRIX */
10005 #include "gt-mips.h"