1 ;; Constraint definitions for MIPS.
2 ;; Copyright (C) 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
21 ;; Register constraints
23 (define_register_constraint "d" "BASE_REG_CLASS"
24 "An address register. This is equivalent to @code{r} unless
25 generating MIPS16 code.")
27 (define_register_constraint "t" "T_REG"
30 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
31 "A floating-point register (if available).")
33 (define_register_constraint "h" "TARGET_BIG_ENDIAN ? MD0_REG : MD1_REG"
34 "The @code{hi} register.")
36 (define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
37 "The @code{lo} register.")
39 (define_register_constraint "x" "MD_REGS"
40 "The @code{hi} and @code{lo} registers.")
42 (define_register_constraint "b" "ALL_REGS"
45 (define_register_constraint "c" "TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
46 : TARGET_MIPS16 ? M16_NA_REGS
48 "A register suitable for use in an indirect jump. This will always be
49 @code{$25} for @option{-mabicalls}.")
51 (define_register_constraint "e" "LEA_REGS"
54 (define_register_constraint "j" "PIC_FN_ADDR_REG"
57 (define_register_constraint "v" "V1_REG"
60 (define_register_constraint "y" "GR_REGS"
61 "Equivalent to @code{r}; retained for backwards compatibility.")
63 (define_register_constraint "z" "ST_REGS"
64 "A floating-point condition code register.")
66 (define_register_constraint "A" "DSP_ACC_REGS"
69 (define_register_constraint "a" "ACC_REGS"
72 (define_register_constraint "B" "COP0_REGS"
75 (define_register_constraint "C" "COP2_REGS"
78 (define_register_constraint "D" "COP3_REGS"
81 ;; Registers that can be used as the target of multiply-accumulate
82 ;; instructions. The core MIPS32 ISA provides a hi/lo madd,
83 ;; but the DSPr2 version allows any accumulator target.
84 (define_register_constraint "ka" "TARGET_DSPR2 ? ACC_REGS : MD_REGS")
86 ;; Integer constraints
88 (define_constraint "I"
89 "A signed 16-bit constant (for arithmetic instructions)."
90 (and (match_code "const_int")
91 (match_test "SMALL_OPERAND (ival)")))
93 (define_constraint "J"
95 (and (match_code "const_int")
96 (match_test "ival == 0")))
98 (define_constraint "K"
99 "An unsigned 16-bit constant (for logic instructions)."
100 (and (match_code "const_int")
101 (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
103 (define_constraint "L"
104 "A signed 32-bit constant in which the lower 16 bits are zero.
105 Such constants can be loaded using @code{lui}."
106 (and (match_code "const_int")
107 (match_test "LUI_OPERAND (ival)")))
109 (define_constraint "M"
110 "A constant that cannot be loaded using @code{lui}, @code{addiu}
112 (and (match_code "const_int")
113 (match_test "!SMALL_OPERAND (ival)")
114 (match_test "!SMALL_OPERAND_UNSIGNED (ival)")
115 (match_test "!LUI_OPERAND (ival)")))
117 (define_constraint "N"
118 "A constant in the range -65535 to -1 (inclusive)."
119 (and (match_code "const_int")
120 (match_test "ival >= -0xffff && ival < 0")))
122 (define_constraint "O"
123 "A signed 15-bit constant."
124 (and (match_code "const_int")
125 (match_test "ival >= -0x4000 && ival < 0x4000")))
127 (define_constraint "P"
128 "A constant in the range 1 to 65535 (inclusive)."
129 (and (match_code "const_int")
130 (match_test "ival > 0 && ival < 0x10000")))
132 ;; Floating-point constraints
134 (define_constraint "G"
135 "Floating-point zero."
136 (and (match_code "const_double")
137 (match_test "op == CONST0_RTX (mode)")))
139 ;; General constraints
141 (define_constraint "Q"
143 (match_operand 0 "const_arith_operand"))
145 (define_memory_constraint "R"
146 "An address that can be used in a non-macro load or store."
147 (and (match_code "mem")
148 (match_test "mips_fetch_insns (op) == 1")))
150 (define_constraint "S"
152 A constant call address."
153 (and (match_operand 0 "call_insn_operand")
154 (match_test "CONSTANT_P (op)")))
156 (define_constraint "T"
158 A constant @code{move_operand} that cannot be safely loaded into @code{$25}
160 (and (match_operand 0 "move_operand")
161 (match_test "CONSTANT_P (op)")
162 (match_test "mips_dangerous_for_la25_p (op)")))
164 (define_constraint "U"
166 A constant @code{move_operand} that can be safely loaded into @code{$25}
168 (and (match_operand 0 "move_operand")
169 (match_test "CONSTANT_P (op)")
170 (match_test "!mips_dangerous_for_la25_p (op)")))
172 (define_memory_constraint "W"
174 A memory address based on a member of @code{BASE_REG_CLASS}. This is
175 true for all non-mips16 references (although it can sometimes be implicit
176 if @samp{!TARGET_EXPLICIT_RELOCS}). For MIPS16, it excludes stack and
177 constant-pool references."
178 (and (match_code "mem")
179 (match_operand 0 "memory_operand")
180 (ior (match_test "!TARGET_MIPS16")
181 (and (not (match_operand 0 "stack_operand"))
182 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
184 (define_constraint "YG"
187 (and (match_code "const_vector")
188 (match_test "op == CONST0_RTX (mode)")))
190 (define_constraint "YA"
192 An unsigned 6-bit constant."
193 (and (match_code "const_int")
194 (match_test "UIMM6_OPERAND (ival)")))
196 (define_constraint "YB"
198 A signed 10-bit constant."
199 (and (match_code "const_int")
200 (match_test "IMM10_OPERAND (ival)")))