1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
37 #include "insn-attr.h"
47 #include "target-def.h"
49 /* Maximum size we are allowed to grow the stack in a single operation.
50 If we want more, we must do it in increments of at most this size.
51 If this value is 0, we don't check at all. */
52 const char * mcore_stack_increment_string = 0;
53 int mcore_stack_increment = STACK_UNITS_MAXSTEP;
55 /* For dumping information about frame sizes. */
56 char * mcore_current_function_name = 0;
57 long mcore_current_compilation_timestamp = 0;
59 /* Global variables for machine-dependent things. */
61 /* Saved operands from the last compare to use when we generate an scc
66 /* Provides the class number of the smallest class containing
68 const int regno_reg_class[FIRST_PSEUDO_REGISTER] =
70 GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS,
71 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
72 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
73 LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS,
74 GENERAL_REGS, C_REGS, NO_REGS, NO_REGS,
77 /* Provide reg_class from a letter such as appears in the machine
79 const enum reg_class reg_class_from_letter[] =
81 /* a */ LRW_REGS, /* b */ ONLYR1_REGS, /* c */ C_REGS, /* d */ NO_REGS,
82 /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
83 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ NO_REGS,
84 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
85 /* q */ NO_REGS, /* r */ GENERAL_REGS, /* s */ NO_REGS, /* t */ NO_REGS,
86 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ ALL_REGS,
87 /* y */ NO_REGS, /* z */ NO_REGS
92 int arg_size; /* Stdarg spills (bytes). */
93 int reg_size; /* Non-volatile reg saves (bytes). */
94 int reg_mask; /* Non-volatile reg saves. */
95 int local_size; /* Locals. */
96 int outbound_size; /* Arg overflow on calls out. */
100 /* Describe the steps we'll use to grow it. */
101 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
102 int growth[MAX_STACK_GROWS];
120 static void output_stack_adjust (int, int);
121 static int calc_live_regs (int *);
122 static int const_ok_for_mcore (int);
123 static int try_constant_tricks (long, int *, int *);
124 static const char * output_inline_const (enum machine_mode, rtx *);
125 static void layout_mcore_frame (struct mcore_frame *);
126 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
127 static cond_type is_cond_candidate (rtx);
128 static rtx emit_new_cond_insn (rtx, int);
129 static rtx conditionalize_block (rtx);
130 static void conditionalize_optimization (void);
131 static void mcore_reorg (void);
132 static rtx handle_structs_in_regs (enum machine_mode, tree, int);
133 static void mcore_mark_dllexport (tree);
134 static void mcore_mark_dllimport (tree);
135 static int mcore_dllexport_p (tree);
136 static int mcore_dllimport_p (tree);
137 const struct attribute_spec mcore_attribute_table[];
138 static tree mcore_handle_naked_attribute (tree *, tree, tree, int, bool *);
139 #ifdef OBJECT_FORMAT_ELF
140 static void mcore_asm_named_section (const char *,
143 static void mcore_unique_section (tree, int);
144 static void mcore_encode_section_info (tree, rtx, int);
145 static const char *mcore_strip_name_encoding (const char *);
146 static int mcore_const_costs (rtx, RTX_CODE);
147 static int mcore_and_cost (rtx);
148 static int mcore_ior_cost (rtx);
149 static bool mcore_rtx_costs (rtx, int, int, int *);
150 static void mcore_external_libcall (rtx);
151 static bool mcore_return_in_memory (tree, tree);
154 /* Initialize the GCC target structure. */
155 #undef TARGET_ASM_EXTERNAL_LIBCALL
156 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
158 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
159 #undef TARGET_MERGE_DECL_ATTRIBUTES
160 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
163 #ifdef OBJECT_FORMAT_ELF
164 #undef TARGET_ASM_UNALIGNED_HI_OP
165 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
166 #undef TARGET_ASM_UNALIGNED_SI_OP
167 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
170 #undef TARGET_ATTRIBUTE_TABLE
171 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
172 #undef TARGET_ASM_UNIQUE_SECTION
173 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
174 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
175 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
176 #undef TARGET_ENCODE_SECTION_INFO
177 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
178 #undef TARGET_STRIP_NAME_ENCODING
179 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
180 #undef TARGET_RTX_COSTS
181 #define TARGET_RTX_COSTS mcore_rtx_costs
182 #undef TARGET_ADDRESS_COST
183 #define TARGET_ADDRESS_COST hook_int_rtx_0
184 #undef TARGET_MACHINE_DEPENDENT_REORG
185 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
187 #undef TARGET_PROMOTE_FUNCTION_ARGS
188 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
189 #undef TARGET_PROMOTE_FUNCTION_RETURN
190 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
191 #undef TARGET_PROMOTE_PROTOTYPES
192 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
194 #undef TARGET_RETURN_IN_MEMORY
195 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
196 #undef TARGET_MUST_PASS_IN_STACK
197 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
198 #undef TARGET_PASS_BY_REFERENCE
199 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
201 #undef TARGET_SETUP_INCOMING_VARARGS
202 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
204 struct gcc_target targetm = TARGET_INITIALIZER;
206 /* Adjust the stack and return the number of bytes taken to do it. */
208 output_stack_adjust (int direction, int size)
210 /* If extending stack a lot, we do it incrementally. */
211 if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0)
213 rtx tmp = gen_rtx_REG (SImode, 1);
216 emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment)));
219 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
220 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
221 MEM_VOLATILE_P (memref) = 1;
222 emit_insn (gen_movsi (memref, stack_pointer_rtx));
223 size -= mcore_stack_increment;
225 while (size > mcore_stack_increment);
227 /* SIZE is now the residual for the last adjustment,
228 which doesn't require a probe. */
234 rtx val = GEN_INT (size);
238 rtx nval = gen_rtx_REG (SImode, 1);
239 emit_insn (gen_movsi (nval, val));
244 insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
246 insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
252 /* Work out the registers which need to be saved,
253 both as a mask and a count. */
256 calc_live_regs (int * count)
259 int live_regs_mask = 0;
263 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
265 if (regs_ever_live[reg] && !call_used_regs[reg])
268 live_regs_mask |= (1 << reg);
272 return live_regs_mask;
275 /* Print the operand address in x to the stream. */
278 mcore_print_operand_address (FILE * stream, rtx x)
280 switch (GET_CODE (x))
283 fprintf (stream, "(%s)", reg_names[REGNO (x)]);
288 rtx base = XEXP (x, 0);
289 rtx index = XEXP (x, 1);
291 if (GET_CODE (base) != REG)
293 /* Ensure that BASE is a register (one of them must be). */
299 switch (GET_CODE (index))
302 fprintf (stream, "(%s," HOST_WIDE_INT_PRINT_DEC ")",
303 reg_names[REGNO(base)], INTVAL (index));
316 output_addr_const (stream, x);
321 /* Print operand x (an rtx) in assembler syntax to file stream
322 according to modifier code.
324 'R' print the next register or memory location along, ie the lsw in
326 'O' print a constant without the #
327 'M' print a constant as its negative
328 'P' print log2 of a power of two
329 'Q' print log2 of an inverse of a power of two
330 'U' print register for ldm/stm instruction
331 'X' print byte number for xtrbN instruction. */
334 mcore_print_operand (FILE * stream, rtx x, int code)
340 fprintf (asm_out_file, "32");
342 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1));
345 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x)));
348 fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x)));
351 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
354 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, - INTVAL (x));
357 /* Next location along in memory or register. */
358 switch (GET_CODE (x))
361 fputs (reg_names[REGNO (x) + 1], (stream));
364 mcore_print_operand_address
365 (stream, XEXP (adjust_address (x, SImode, 4), 0));
372 fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)],
373 reg_names[REGNO (x) + 3]);
376 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
379 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, 3 - INTVAL (x) / 8);
383 switch (GET_CODE (x))
386 fputs (reg_names[REGNO (x)], (stream));
389 output_address (XEXP (x, 0));
392 output_addr_const (stream, x);
399 /* What does a constant cost ? */
402 mcore_const_costs (rtx exp, enum rtx_code code)
404 int val = INTVAL (exp);
406 /* Easy constants. */
407 if ( CONST_OK_FOR_I (val)
408 || CONST_OK_FOR_M (val)
409 || CONST_OK_FOR_N (val)
410 || (code == PLUS && CONST_OK_FOR_L (val)))
413 && ( CONST_OK_FOR_M (~val)
414 || CONST_OK_FOR_N (~val)))
416 else if (code == PLUS
417 && ( CONST_OK_FOR_I (-val)
418 || CONST_OK_FOR_M (-val)
419 || CONST_OK_FOR_N (-val)))
425 /* What does an and instruction cost - we do this b/c immediates may
426 have been relaxed. We want to ensure that cse will cse relaxed immeds
427 out. Otherwise we'll get bad code (multiple reloads of the same const). */
430 mcore_and_cost (rtx x)
434 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
437 val = INTVAL (XEXP (x, 1));
439 /* Do it directly. */
440 if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val))
442 /* Takes one instruction to load. */
443 else if (const_ok_for_mcore (val))
445 /* Takes two instructions to load. */
446 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
449 /* Takes a lrw to load. */
453 /* What does an or cost - see and_cost(). */
456 mcore_ior_cost (rtx x)
460 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
463 val = INTVAL (XEXP (x, 1));
465 /* Do it directly with bclri. */
466 if (CONST_OK_FOR_M (val))
468 /* Takes one instruction to load. */
469 else if (const_ok_for_mcore (val))
471 /* Takes two instructions to load. */
472 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
475 /* Takes a lrw to load. */
480 mcore_rtx_costs (rtx x, int code, int outer_code, int * total)
485 *total = mcore_const_costs (x, outer_code);
497 *total = COSTS_N_INSNS (mcore_and_cost (x));
501 *total = COSTS_N_INSNS (mcore_ior_cost (x));
510 *total = COSTS_N_INSNS (100);
518 /* Check to see if a comparison against a constant can be made more efficient
519 by incrementing/decrementing the constant to get one that is more efficient
523 mcore_modify_comparison (enum rtx_code code)
525 rtx op1 = arch_compare_op1;
527 if (GET_CODE (op1) == CONST_INT)
529 int val = INTVAL (op1);
534 if (CONST_OK_FOR_J (val + 1))
536 arch_compare_op1 = GEN_INT (val + 1);
549 /* Prepare the operands for a comparison. */
552 mcore_gen_compare_reg (enum rtx_code code)
554 rtx op0 = arch_compare_op0;
555 rtx op1 = arch_compare_op1;
556 rtx cc_reg = gen_rtx_REG (CCmode, CC_REG);
558 if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
559 op1 = force_reg (SImode, op1);
561 /* cmpnei: 0-31 (K immediate)
562 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
565 case EQ: /* Use inverted condition, cmpne. */
569 case NE: /* Use normal condition, cmpne. */
570 if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
571 op1 = force_reg (SImode, op1);
574 case LE: /* Use inverted condition, reversed cmplt. */
578 case GT: /* Use normal condition, reversed cmplt. */
579 if (GET_CODE (op1) == CONST_INT)
580 op1 = force_reg (SImode, op1);
583 case GE: /* Use inverted condition, cmplt. */
587 case LT: /* Use normal condition, cmplt. */
588 if (GET_CODE (op1) == CONST_INT &&
589 /* covered by btsti x,31. */
591 ! CONST_OK_FOR_J (INTVAL (op1)))
592 op1 = force_reg (SImode, op1);
595 case GTU: /* Use inverted condition, cmple. */
596 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) == 0)
598 /* Unsigned > 0 is the same as != 0, but we need
599 to invert the condition, so we want to set
600 code = EQ. This cannot be done however, as the
601 mcore does not support such a test. Instead we
602 cope with this case in the "bgtu" pattern itself
603 so we should never reach this point. */
611 case LEU: /* Use normal condition, reversed cmphs. */
612 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
613 op1 = force_reg (SImode, op1);
616 case LTU: /* Use inverted condition, cmphs. */
620 case GEU: /* Use normal condition, cmphs. */
621 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
622 op1 = force_reg (SImode, op1);
629 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_fmt_ee (code, CCmode, op0, op1)));
635 mcore_symbolic_address_p (rtx x)
637 switch (GET_CODE (x))
644 return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
645 || GET_CODE (XEXP (x, 0)) == LABEL_REF)
646 && GET_CODE (XEXP (x, 1)) == CONST_INT);
653 mcore_call_address_operand (rtx x, enum machine_mode mode)
655 return register_operand (x, mode) || CONSTANT_P (x);
658 /* Functions to output assembly code for a function call. */
661 mcore_output_call (rtx operands[], int index)
663 static char buffer[20];
664 rtx addr = operands [index];
670 if (mcore_current_function_name == 0)
673 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
677 sprintf (buffer, "jsr\t%%%d", index);
683 if (mcore_current_function_name == 0)
686 if (GET_CODE (addr) != SYMBOL_REF)
689 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, XSTR (addr, 0), 0);
692 sprintf (buffer, "jbsr\t%%%d", index);
698 /* Can we load a constant with a single instruction ? */
701 const_ok_for_mcore (int value)
703 if (value >= 0 && value <= 127)
706 /* Try exact power of two. */
707 if ((value & (value - 1)) == 0)
710 /* Try exact power of two - 1. */
711 if ((value & (value + 1)) == 0)
717 /* Can we load a constant inline with up to 2 instructions ? */
720 mcore_const_ok_for_inline (long value)
724 return try_constant_tricks (value, & x, & y) > 0;
727 /* Are we loading the constant using a not ? */
730 mcore_const_trick_uses_not (long value)
734 return try_constant_tricks (value, & x, & y) == 2;
737 /* Try tricks to load a constant inline and return the trick number if
738 success (0 is non-inlinable).
741 1: single instruction (do the usual thing)
742 2: single insn followed by a 'not'
743 3: single insn followed by a subi
744 4: single insn followed by an addi
745 5: single insn followed by rsubi
746 6: single insn followed by bseti
747 7: single insn followed by bclri
748 8: single insn followed by rotli
749 9: single insn followed by lsli
750 10: single insn followed by ixh
751 11: single insn followed by ixw. */
754 try_constant_tricks (long value, int * x, int * y)
757 unsigned bit, shf, rot;
759 if (const_ok_for_mcore (value))
760 return 1; /* Do the usual thing. */
764 if (const_ok_for_mcore (~value))
770 for (i = 1; i <= 32; i++)
772 if (const_ok_for_mcore (value - i))
780 if (const_ok_for_mcore (value + i))
791 for (i = 0; i <= 31; i++)
793 if (const_ok_for_mcore (i - value))
801 if (const_ok_for_mcore (value & ~bit))
809 if (const_ok_for_mcore (value | bit))
823 for (i = 1; i < 31; i++)
827 /* MCore has rotate left. */
831 rot |= c; /* Simulate rotate. */
833 if (const_ok_for_mcore (rot))
842 shf = 0; /* Can't use logical shift, low order bit is one. */
846 if (shf != 0 && const_ok_for_mcore (shf))
855 if ((value % 3) == 0 && const_ok_for_mcore (value / 3))
862 if ((value % 5) == 0 && const_ok_for_mcore (value / 5))
873 /* Check whether reg is dead at first. This is done by searching ahead
874 for either the next use (i.e., reg is live), a death note, or a set of
875 reg. Don't just use dead_or_set_p() since reload does not always mark
876 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
877 can ignore subregs by extracting the actual register. BRC */
880 mcore_is_dead (rtx first, rtx reg)
884 /* For mcore, subregs can't live independently of their parent regs. */
885 if (GET_CODE (reg) == SUBREG)
886 reg = SUBREG_REG (reg);
888 /* Dies immediately. */
889 if (dead_or_set_p (first, reg))
892 /* Look for conclusive evidence of live/death, otherwise we have
893 to assume that it is live. */
894 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
896 if (GET_CODE (insn) == JUMP_INSN)
897 return 0; /* We lose track, assume it is alive. */
899 else if (GET_CODE(insn) == CALL_INSN)
901 /* Call's might use it for target or register parms. */
902 if (reg_referenced_p (reg, PATTERN (insn))
903 || find_reg_fusage (insn, USE, reg))
905 else if (dead_or_set_p (insn, reg))
908 else if (GET_CODE (insn) == INSN)
910 if (reg_referenced_p (reg, PATTERN (insn)))
912 else if (dead_or_set_p (insn, reg))
917 /* No conclusive evidence either way, we cannot take the chance
918 that control flow hid the use from us -- "I'm not dead yet". */
922 /* Count the number of ones in mask. */
925 mcore_num_ones (int mask)
927 /* A trick to count set bits recently posted on comp.compilers. */
928 mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555);
929 mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333);
930 mask = ((mask >> 4) + mask) & 0x0f0f0f0f;
931 mask = ((mask >> 8) + mask);
933 return (mask + (mask >> 16)) & 0xff;
936 /* Count the number of zeros in mask. */
939 mcore_num_zeros (int mask)
941 return 32 - mcore_num_ones (mask);
944 /* Determine byte being masked. */
947 mcore_byte_offset (unsigned int mask)
949 if (mask == 0x00ffffffL)
951 else if (mask == 0xff00ffffL)
953 else if (mask == 0xffff00ffL)
955 else if (mask == 0xffffff00L)
961 /* Determine halfword being masked. */
964 mcore_halfword_offset (unsigned int mask)
966 if (mask == 0x0000ffffL)
968 else if (mask == 0xffff0000L)
974 /* Output a series of bseti's corresponding to mask. */
977 mcore_output_bseti (rtx dst, int mask)
982 out_operands[0] = dst;
984 for (bit = 0; bit < 32; bit++)
986 if ((mask & 0x1) == 0x1)
988 out_operands[1] = GEN_INT (bit);
990 output_asm_insn ("bseti\t%0,%1", out_operands);
998 /* Output a series of bclri's corresponding to mask. */
1001 mcore_output_bclri (rtx dst, int mask)
1003 rtx out_operands[2];
1006 out_operands[0] = dst;
1008 for (bit = 0; bit < 32; bit++)
1010 if ((mask & 0x1) == 0x0)
1012 out_operands[1] = GEN_INT (bit);
1014 output_asm_insn ("bclri\t%0,%1", out_operands);
1023 /* Output a conditional move of two constants that are +/- 1 within each
1024 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1025 really worth the effort. */
1028 mcore_output_cmov (rtx operands[], int cmp_t, const char * test)
1032 rtx out_operands[4];
1034 out_operands[0] = operands[0];
1036 /* Check to see which constant is loadable. */
1037 if (const_ok_for_mcore (INTVAL (operands[1])))
1039 out_operands[1] = operands[1];
1040 out_operands[2] = operands[2];
1042 else if (const_ok_for_mcore (INTVAL (operands[2])))
1044 out_operands[1] = operands[2];
1045 out_operands[2] = operands[1];
1047 /* Complement test since constants are swapped. */
1048 cmp_t = (cmp_t == 0);
1050 load_value = INTVAL (out_operands[1]);
1051 adjust_value = INTVAL (out_operands[2]);
1053 /* First output the test if folded into the pattern. */
1056 output_asm_insn (test, operands);
1058 /* Load the constant - for now, only support constants that can be
1059 generated with a single instruction. maybe add general inlinable
1060 constants later (this will increase the # of patterns since the
1061 instruction sequence has a different length attribute). */
1062 if (load_value >= 0 && load_value <= 127)
1063 output_asm_insn ("movi\t%0,%1", out_operands);
1064 else if ((load_value & (load_value - 1)) == 0)
1065 output_asm_insn ("bgeni\t%0,%P1", out_operands);
1066 else if ((load_value & (load_value + 1)) == 0)
1067 output_asm_insn ("bmaski\t%0,%N1", out_operands);
1069 /* Output the constant adjustment. */
1070 if (load_value > adjust_value)
1073 output_asm_insn ("decf\t%0", out_operands);
1075 output_asm_insn ("dect\t%0", out_operands);
1080 output_asm_insn ("incf\t%0", out_operands);
1082 output_asm_insn ("inct\t%0", out_operands);
1088 /* Outputs the peephole for moving a constant that gets not'ed followed
1089 by an and (i.e. combine the not and the and into andn). BRC */
1092 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
1095 rtx out_operands[3];
1096 const char * load_op;
1099 if (try_constant_tricks (INTVAL (operands[1]), &x, &y) != 2)
1102 out_operands[0] = operands[0];
1103 out_operands[1] = GEN_INT(x);
1104 out_operands[2] = operands[2];
1106 if (x >= 0 && x <= 127)
1107 load_op = "movi\t%0,%1";
1109 /* Try exact power of two. */
1110 else if ((x & (x - 1)) == 0)
1111 load_op = "bgeni\t%0,%P1";
1113 /* Try exact power of two - 1. */
1114 else if ((x & (x + 1)) == 0)
1115 load_op = "bmaski\t%0,%N1";
1118 load_op = "BADMOVI\t%0,%1";
1120 sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op);
1121 output_asm_insn (buf, out_operands);
1126 /* Output an inline constant. */
1129 output_inline_const (enum machine_mode mode, rtx operands[])
1133 rtx out_operands[3];
1136 const char *dst_fmt;
1139 value = INTVAL (operands[1]);
1141 if ((trick_no = try_constant_tricks (value, &x, &y)) == 0)
1143 /* lrw's are handled separately: Large inlinable constants
1144 never get turned into lrw's. Our caller uses try_constant_tricks
1145 to back off to an lrw rather than calling this routine. */
1152 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1153 out_operands[0] = operands[0];
1154 out_operands[1] = GEN_INT (x);
1157 out_operands[2] = GEN_INT (y);
1159 /* Select dst format based on mode. */
1160 if (mode == DImode && (! TARGET_LITTLE_END))
1165 if (x >= 0 && x <= 127)
1166 sprintf (load_op, "movi\t%s,%%1", dst_fmt);
1168 /* Try exact power of two. */
1169 else if ((x & (x - 1)) == 0)
1170 sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt);
1172 /* Try exact power of two - 1. */
1173 else if ((x & (x + 1)) == 0)
1174 sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt);
1177 sprintf (load_op, "BADMOVI\t%s,%%1", dst_fmt);
1182 strcpy (buf, load_op);
1185 sprintf (buf, "%s\n\tnot\t%s\t// %d 0x%x", load_op, dst_fmt, value, value);
1188 sprintf (buf, "%s\n\taddi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1191 sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1194 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1195 sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1198 sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %d 0x%x", load_op, dst_fmt, value, value);
1201 sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %d 0x%x", load_op, dst_fmt, value, value);
1204 sprintf (buf, "%s\n\trotli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1207 sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %d 0x%x", load_op, dst_fmt, value, value);
1210 sprintf (buf, "%s\n\tixh\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value);
1213 sprintf (buf, "%s\n\tixw\t%s,%s\t// %d 0x%x", load_op, dst_fmt, dst_fmt, value, value);
1219 output_asm_insn (buf, out_operands);
1224 /* Output a move of a word or less value. */
1227 mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1228 enum machine_mode mode ATTRIBUTE_UNUSED)
1230 rtx dst = operands[0];
1231 rtx src = operands[1];
1233 if (GET_CODE (dst) == REG)
1235 if (GET_CODE (src) == REG)
1237 if (REGNO (src) == CC_REG) /* r-c */
1240 return "mov\t%0,%1"; /* r-r*/
1242 else if (GET_CODE (src) == MEM)
1244 if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
1245 return "lrw\t%0,[%1]"; /* a-R */
1247 switch (GET_MODE (src)) /* r-m */
1250 return "ldw\t%0,%1";
1252 return "ld.h\t%0,%1";
1254 return "ld.b\t%0,%1";
1259 else if (GET_CODE (src) == CONST_INT)
1263 if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */
1264 return "movi\t%0,%1";
1265 else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */
1266 return "bgeni\t%0,%P1\t// %1 %x1";
1267 else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */
1268 return "bmaski\t%0,%N1\t// %1 %x1";
1269 else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */
1270 return output_inline_const (SImode, operands); /* 1-2 insns */
1272 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1275 return "lrw\t%0, %1"; /* Into the literal pool. */
1277 else if (GET_CODE (dst) == MEM) /* m-r */
1278 switch (GET_MODE (dst))
1281 return "stw\t%1,%0";
1283 return "st.h\t%1,%0";
1285 return "st.b\t%1,%0";
1293 /* Return a sequence of instructions to perform DI or DF move.
1294 Since the MCORE cannot move a DI or DF in one instruction, we have
1295 to take care when we see overlapping source and dest registers. */
1298 mcore_output_movedouble (rtx operands[], enum machine_mode mode ATTRIBUTE_UNUSED)
1300 rtx dst = operands[0];
1301 rtx src = operands[1];
1303 if (GET_CODE (dst) == REG)
1305 if (GET_CODE (src) == REG)
1307 int dstreg = REGNO (dst);
1308 int srcreg = REGNO (src);
1310 /* Ensure the second source not overwritten. */
1311 if (srcreg + 1 == dstreg)
1312 return "mov %R0,%R1\n\tmov %0,%1";
1314 return "mov %0,%1\n\tmov %R0,%R1";
1316 else if (GET_CODE (src) == MEM)
1318 rtx memexp = memexp = XEXP (src, 0);
1319 int dstreg = REGNO (dst);
1322 if (GET_CODE (memexp) == LABEL_REF)
1323 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1324 else if (GET_CODE (memexp) == REG)
1325 basereg = REGNO (memexp);
1326 else if (GET_CODE (memexp) == PLUS)
1328 if (GET_CODE (XEXP (memexp, 0)) == REG)
1329 basereg = REGNO (XEXP (memexp, 0));
1330 else if (GET_CODE (XEXP (memexp, 1)) == REG)
1331 basereg = REGNO (XEXP (memexp, 1));
1338 /* ??? length attribute is wrong here. */
1339 if (dstreg == basereg)
1341 /* Just load them in reverse order. */
1342 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1344 /* XXX: alternative: move basereg to basereg+1
1345 and then fall through. */
1348 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1350 else if (GET_CODE (src) == CONST_INT)
1352 if (TARGET_LITTLE_END)
1354 if (CONST_OK_FOR_I (INTVAL (src)))
1355 output_asm_insn ("movi %0,%1", operands);
1356 else if (CONST_OK_FOR_M (INTVAL (src)))
1357 output_asm_insn ("bgeni %0,%P1", operands);
1358 else if (INTVAL (src) == -1)
1359 output_asm_insn ("bmaski %0,32", operands);
1360 else if (CONST_OK_FOR_N (INTVAL (src)))
1361 output_asm_insn ("bmaski %0,%N1", operands);
1365 if (INTVAL (src) < 0)
1366 return "bmaski %R0,32";
1368 return "movi %R0,0";
1372 if (CONST_OK_FOR_I (INTVAL (src)))
1373 output_asm_insn ("movi %R0,%1", operands);
1374 else if (CONST_OK_FOR_M (INTVAL (src)))
1375 output_asm_insn ("bgeni %R0,%P1", operands);
1376 else if (INTVAL (src) == -1)
1377 output_asm_insn ("bmaski %R0,32", operands);
1378 else if (CONST_OK_FOR_N (INTVAL (src)))
1379 output_asm_insn ("bmaski %R0,%N1", operands);
1383 if (INTVAL (src) < 0)
1384 return "bmaski %0,32";
1392 else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
1393 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1398 /* Predicates used by the templates. */
1400 /* Nonzero if OP can be source of a simple move operation. */
1403 mcore_general_movsrc_operand (rtx op, enum machine_mode mode)
1405 /* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
1406 if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
1409 return general_operand (op, mode);
1412 /* Nonzero if OP can be destination of a simple move operation. */
1415 mcore_general_movdst_operand (rtx op, enum machine_mode mode)
1417 if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
1420 return general_operand (op, mode);
1423 /* Nonzero if OP is a normal arithmetic register. */
1426 mcore_arith_reg_operand (rtx op, enum machine_mode mode)
1428 if (! register_operand (op, mode))
1431 if (GET_CODE (op) == SUBREG)
1432 op = SUBREG_REG (op);
1434 if (GET_CODE (op) == REG)
1435 return REGNO (op) != CC_REG;
1440 /* Nonzero if OP should be recognized during reload for an ixh/ixw
1441 operand. See the ixh/ixw patterns. */
1444 mcore_reload_operand (rtx op, enum machine_mode mode)
1446 if (mcore_arith_reg_operand (op, mode))
1449 if (! reload_in_progress)
1452 return GET_CODE (op) == MEM;
1455 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1458 mcore_arith_J_operand (rtx op, enum machine_mode mode)
1460 if (register_operand (op, mode))
1463 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
1469 /* Nonzero if OP is a valid source operand for an arithmetic insn. */
1472 mcore_arith_K_operand (rtx op, enum machine_mode mode)
1474 if (register_operand (op, mode))
1477 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
1483 /* Nonzero if OP is a valid source operand for a shift or rotate insn. */
1486 mcore_arith_K_operand_not_0 (rtx op, enum machine_mode mode)
1488 if (register_operand (op, mode))
1491 if ( GET_CODE (op) == CONST_INT
1492 && CONST_OK_FOR_K (INTVAL (op))
1493 && INTVAL (op) != 0)
1500 mcore_arith_K_S_operand (rtx op, enum machine_mode mode)
1502 if (register_operand (op, mode))
1505 if (GET_CODE (op) == CONST_INT)
1507 if (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_M (~INTVAL (op)))
1515 mcore_arith_S_operand (rtx op)
1517 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
1524 mcore_arith_M_operand (rtx op, enum machine_mode mode)
1526 if (register_operand (op, mode))
1529 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
1535 /* Nonzero if OP is a valid source operand for loading. */
1538 mcore_arith_imm_operand (rtx op, enum machine_mode mode)
1540 if (register_operand (op, mode))
1543 if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
1550 mcore_arith_any_imm_operand (rtx op, enum machine_mode mode)
1552 if (register_operand (op, mode))
1555 if (GET_CODE (op) == CONST_INT)
1561 /* Nonzero if OP is a valid source operand for a cmov with two consts +/- 1. */
1564 mcore_arith_O_operand (rtx op, enum machine_mode mode)
1566 if (register_operand (op, mode))
1569 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
1575 /* Nonzero if OP is a valid source operand for a btsti. */
1578 mcore_literal_K_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1580 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
1586 /* Nonzero if OP is a valid source operand for an add/sub insn. */
1589 mcore_addsub_operand (rtx op, enum machine_mode mode)
1591 if (register_operand (op, mode))
1594 if (GET_CODE (op) == CONST_INT)
1598 /* The following is removed because it precludes large constants from being
1599 returned as valid source operands for and add/sub insn. While large
1600 constants may not directly be used in an add/sub, they may if first loaded
1601 into a register. Thus, this predicate should indicate that they are valid,
1602 and the constraint in mcore.md should control whether an additional load to
1603 register is needed. (see mcore.md, addsi). -- DAC 4/2/1998 */
1605 if (CONST_OK_FOR_J(INTVAL(op)) || CONST_OK_FOR_L(INTVAL(op)))
1613 /* Nonzero if OP is a valid source operand for a compare operation. */
1616 mcore_compare_operand (rtx op, enum machine_mode mode)
1618 if (register_operand (op, mode))
1621 if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
1627 /* Expand insert bit field. BRC */
1630 mcore_expand_insv (rtx operands[])
1632 int width = INTVAL (operands[1]);
1633 int posn = INTVAL (operands[2]);
1635 rtx mreg, sreg, ereg;
1637 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1638 for width==1 must be removed. Look around line 368. This is something
1639 we really want the md part to do. */
1640 if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
1642 /* Do directly with bseti or bclri. */
1643 /* RBE: 2/97 consider only low bit of constant. */
1644 if ((INTVAL(operands[3])&1) == 0)
1646 mask = ~(1 << posn);
1647 emit_insn (gen_rtx_SET (SImode, operands[0],
1648 gen_rtx_AND (SImode, operands[0], GEN_INT (mask))));
1653 emit_insn (gen_rtx_SET (SImode, operands[0],
1654 gen_rtx_IOR (SImode, operands[0], GEN_INT (mask))));
1660 /* Look at some bit-field placements that we aren't interested
1661 in handling ourselves, unless specifically directed to do so. */
1662 if (! TARGET_W_FIELD)
1663 return 0; /* Generally, give up about now. */
1665 if (width == 8 && posn % 8 == 0)
1666 /* Byte sized and aligned; let caller break it up. */
1669 if (width == 16 && posn % 16 == 0)
1670 /* Short sized and aligned; let caller break it up. */
1673 /* The general case - we can do this a little bit better than what the
1674 machine independent part tries. This will get rid of all the subregs
1675 that mess up constant folding in combine when working with relaxed
1678 /* If setting the entire field, do it directly. */
1679 if (GET_CODE (operands[3]) == CONST_INT &&
1680 INTVAL (operands[3]) == ((1 << width) - 1))
1682 mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
1683 emit_insn (gen_rtx_SET (SImode, operands[0],
1684 gen_rtx_IOR (SImode, operands[0], mreg)));
1688 /* Generate the clear mask. */
1689 mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn)));
1691 /* Clear the field, to overlay it later with the source. */
1692 emit_insn (gen_rtx_SET (SImode, operands[0],
1693 gen_rtx_AND (SImode, operands[0], mreg)));
1695 /* If the source is constant 0, we've nothing to add back. */
1696 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
1699 /* XXX: Should we worry about more games with constant values?
1700 We've covered the high profile: set/clear single-bit and many-bit
1701 fields. How often do we see "arbitrary bit pattern" constants? */
1702 sreg = copy_to_mode_reg (SImode, operands[3]);
1704 /* Extract src as same width as dst (needed for signed values). We
1705 always have to do this since we widen everything to SImode.
1706 We don't have to mask if we're shifting this up against the
1707 MSB of the register (e.g., the shift will push out any hi-order
1709 if (width + posn != (int) GET_MODE_SIZE (SImode))
1711 ereg = force_reg (SImode, GEN_INT ((1 << width) - 1));
1712 emit_insn (gen_rtx_SET (SImode, sreg,
1713 gen_rtx_AND (SImode, sreg, ereg)));
1716 /* Insert source value in dest. */
1718 emit_insn (gen_rtx_SET (SImode, sreg,
1719 gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn))));
1721 emit_insn (gen_rtx_SET (SImode, operands[0],
1722 gen_rtx_IOR (SImode, operands[0], sreg)));
1727 /* Return 1 if OP is a load multiple operation. It is known to be a
1728 PARALLEL and the first section will be tested. */
1731 mcore_load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1733 int count = XVECLEN (op, 0);
1738 /* Perform a quick check so we don't blow up below. */
1740 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1741 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1742 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1745 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1746 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1748 for (i = 1; i < count; i++)
1750 rtx elt = XVECEXP (op, 0, i);
1752 if (GET_CODE (elt) != SET
1753 || GET_CODE (SET_DEST (elt)) != REG
1754 || GET_MODE (SET_DEST (elt)) != SImode
1755 || REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
1756 || GET_CODE (SET_SRC (elt)) != MEM
1757 || GET_MODE (SET_SRC (elt)) != SImode
1758 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
1759 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
1760 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
1761 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
1768 /* Similar, but tests for store multiple. */
1771 mcore_store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1773 int count = XVECLEN (op, 0);
1778 /* Perform a quick check so we don't blow up below. */
1780 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1781 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1782 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1785 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1786 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1788 for (i = 1; i < count; i++)
1790 rtx elt = XVECEXP (op, 0, i);
1792 if (GET_CODE (elt) != SET
1793 || GET_CODE (SET_SRC (elt)) != REG
1794 || GET_MODE (SET_SRC (elt)) != SImode
1795 || REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
1796 || GET_CODE (SET_DEST (elt)) != MEM
1797 || GET_MODE (SET_DEST (elt)) != SImode
1798 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
1799 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
1800 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
1801 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
1808 /* ??? Block move stuff stolen from m88k. This code has not been
1809 verified for correctness. */
1811 /* Emit code to perform a block move. Choose the best method.
1813 OPERANDS[0] is the destination.
1814 OPERANDS[1] is the source.
1815 OPERANDS[2] is the size.
1816 OPERANDS[3] is the alignment safe to use. */
1818 /* Emit code to perform a block move with an offset sequence of ldw/st
1819 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1820 known constants. DEST and SRC are registers. OFFSET is the known
1821 starting point for the output pattern. */
1823 static const enum machine_mode mode_from_align[] =
1825 VOIDmode, QImode, HImode, VOIDmode, SImode,
1829 block_move_sequence (rtx dst_mem, rtx src_mem, int size, int align)
1832 enum machine_mode mode[2];
1841 x = XEXP (dst_mem, 0);
1844 x = force_reg (Pmode, x);
1845 dst_mem = replace_equiv_address (dst_mem, x);
1848 x = XEXP (src_mem, 0);
1851 x = force_reg (Pmode, x);
1852 src_mem = replace_equiv_address (src_mem, x);
1855 active[0] = active[1] = false;
1866 next_amount = (size >= 4 ? 4 : (size >= 2 ? 2 : 1));
1867 next_amount = MIN (next_amount, align);
1869 amount[next] = next_amount;
1870 mode[next] = mode_from_align[next_amount];
1871 temp[next] = gen_reg_rtx (mode[next]);
1873 x = adjust_address (src_mem, mode[next], offset_ld);
1874 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1876 offset_ld += next_amount;
1877 size -= next_amount;
1878 active[next] = true;
1883 active[phase] = false;
1885 x = adjust_address (dst_mem, mode[phase], offset_st);
1886 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1888 offset_st += amount[phase];
1891 while (active[next]);
1895 mcore_expand_block_move (rtx *operands)
1897 HOST_WIDE_INT align, bytes, max;
1899 if (GET_CODE (operands[2]) != CONST_INT)
1902 bytes = INTVAL (operands[2]);
1903 align = INTVAL (operands[3]);
1932 block_move_sequence (operands[0], operands[1], bytes, align);
1940 /* Code to generate prologue and epilogue sequences. */
1941 static int number_of_regs_before_varargs;
1943 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1944 for a varargs function. */
1945 static int current_function_anonymous_args;
1947 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1948 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1949 #define ADDI_REACH (32) /* Maximum addi operand. */
1952 layout_mcore_frame (struct mcore_frame * infp)
1961 unsigned int growths;
1964 /* Might have to spill bytes to re-assemble a big argument that
1965 was passed partially in registers and partially on the stack. */
1966 nbytes = current_function_pretend_args_size;
1968 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1969 if (current_function_anonymous_args)
1970 nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD;
1972 infp->arg_size = nbytes;
1974 /* How much space to save non-volatile registers we stomp. */
1975 infp->reg_mask = calc_live_regs (& n);
1976 infp->reg_size = n * 4;
1978 /* And the rest of it... locals and space for overflowed outbounds. */
1979 infp->local_size = get_frame_size ();
1980 infp->outbound_size = current_function_outgoing_args_size;
1982 /* Make sure we have a whole number of words for the locals. */
1983 if (infp->local_size % STACK_BYTES)
1984 infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1);
1986 /* Only thing we know we have to pad is the outbound space, since
1987 we've aligned our locals assuming that base of locals is aligned. */
1988 infp->pad_local = 0;
1990 infp->pad_outbound = 0;
1991 if (infp->outbound_size % STACK_BYTES)
1992 infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES);
1994 /* Now we see how we want to stage the prologue so that it does
1995 the most appropriate stack growth and register saves to either:
1997 (2) reduce instruction space, or
1998 (3) reduce stack space. */
1999 for (i = 0; i < ARRAY_SIZE (infp->growth); i++)
2000 infp->growth[i] = 0;
2002 regarg = infp->reg_size + infp->arg_size;
2003 localregarg = infp->local_size + regarg;
2004 localreg = infp->local_size + infp->reg_size;
2005 outbounds = infp->outbound_size + infp->pad_outbound;
2008 /* XXX: Consider one where we consider localregarg + outbound too! */
2010 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
2011 use stw's with offsets and buy the frame in one shot. */
2012 if (localregarg <= ADDI_REACH
2013 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
2015 /* Make sure we'll be aligned. */
2016 if (localregarg % STACK_BYTES)
2017 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
2019 step = localregarg + infp->pad_reg;
2020 infp->reg_offset = infp->local_size;
2022 if (outbounds + step <= ADDI_REACH && !frame_pointer_needed)
2025 infp->reg_offset += outbounds;
2029 infp->arg_offset = step - 4;
2030 infp->growth[growths++] = step;
2031 infp->reg_growth = growths;
2032 infp->local_growth = growths;
2034 /* If we haven't already folded it in. */
2036 infp->growth[growths++] = outbounds;
2041 /* Frame can't be done with a single subi, but can be done with 2
2042 insns. If the 'stm' is getting <= 2 registers, we use stw's and
2043 shift some of the stack purchase into the first subi, so both are
2044 single instructions. */
2045 if (localregarg <= STORE_REACH
2046 && (infp->local_size > ADDI_REACH)
2047 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
2051 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
2052 if (localregarg % STACK_BYTES)
2053 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
2055 all = localregarg + infp->pad_reg + infp->pad_local;
2056 step = ADDI_REACH; /* As much up front as we can. */
2060 /* XXX: Consider whether step will still be aligned; we believe so. */
2061 infp->arg_offset = step - 4;
2062 infp->growth[growths++] = step;
2063 infp->reg_growth = growths;
2064 infp->reg_offset = step - infp->pad_reg - infp->reg_size;
2067 /* Can we fold in any space required for outbounds? */
2068 if (outbounds + all <= ADDI_REACH && !frame_pointer_needed)
2074 /* Get the rest of the locals in place. */
2076 infp->growth[growths++] = step;
2077 infp->local_growth = growths;
2082 /* Finish off if we need to do so. */
2084 infp->growth[growths++] = outbounds;
2089 /* Registers + args is nicely aligned, so we'll buy that in one shot.
2090 Then we buy the rest of the frame in 1 or 2 steps depending on
2091 whether we need a frame pointer. */
2092 if ((regarg % STACK_BYTES) == 0)
2094 infp->growth[growths++] = regarg;
2095 infp->reg_growth = growths;
2096 infp->arg_offset = regarg - 4;
2097 infp->reg_offset = 0;
2099 if (infp->local_size % STACK_BYTES)
2100 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
2102 step = infp->local_size + infp->pad_local;
2104 if (!frame_pointer_needed)
2110 infp->growth[growths++] = step;
2111 infp->local_growth = growths;
2113 /* If there's any left to be done. */
2115 infp->growth[growths++] = outbounds;
2120 /* XXX: optimizations that we'll want to play with....
2121 -- regarg is not aligned, but it's a small number of registers;
2122 use some of localsize so that regarg is aligned and then
2123 save the registers. */
2125 /* Simple encoding; plods down the stack buying the pieces as it goes.
2126 -- does not optimize space consumption.
2127 -- does not attempt to optimize instruction counts.
2128 -- but it is safe for all alignments. */
2129 if (regarg % STACK_BYTES != 0)
2130 infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES);
2132 infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg;
2133 infp->reg_growth = growths;
2134 infp->arg_offset = infp->growth[0] - 4;
2135 infp->reg_offset = 0;
2137 if (frame_pointer_needed)
2139 if (infp->local_size % STACK_BYTES != 0)
2140 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
2142 infp->growth[growths++] = infp->local_size + infp->pad_local;
2143 infp->local_growth = growths;
2145 infp->growth[growths++] = outbounds;
2149 if ((infp->local_size + outbounds) % STACK_BYTES != 0)
2150 infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES);
2152 infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds;
2153 infp->local_growth = growths;
2156 /* Anything else that we've forgotten?, plus a few consistency checks. */
2158 assert (infp->reg_offset >= 0);
2159 assert (growths <= MAX_STACK_GROWS);
2161 for (i = 0; i < growths; i++)
2163 if (infp->growth[i] % STACK_BYTES)
2165 fprintf (stderr,"stack growth of %d is not %d aligned\n",
2166 infp->growth[i], STACK_BYTES);
2172 /* Define the offset between two registers, one to be eliminated, and
2173 the other its replacement, at the start of a routine. */
2176 mcore_initial_elimination_offset (int from, int to)
2180 struct mcore_frame fi;
2182 layout_mcore_frame (& fi);
2185 above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg;
2187 below_frame = fi.outbound_size + fi.pad_outbound;
2189 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
2192 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2193 return above_frame + below_frame;
2195 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2203 /* Keep track of some information about varargs for the prolog. */
2206 mcore_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_far,
2207 enum machine_mode mode, tree type,
2208 int * ptr_pretend_size ATTRIBUTE_UNUSED,
2209 int second_time ATTRIBUTE_UNUSED)
2211 current_function_anonymous_args = 1;
2213 /* We need to know how many argument registers are used before
2214 the varargs start, so that we can push the remaining argument
2215 registers during the prologue. */
2216 number_of_regs_before_varargs = *args_so_far + mcore_num_arg_regs (mode, type);
2218 /* There is a bug somewhere in the arg handling code.
2219 Until I can find it this workaround always pushes the
2220 last named argument onto the stack. */
2221 number_of_regs_before_varargs = *args_so_far;
2223 /* The last named argument may be split between argument registers
2224 and the stack. Allow for this here. */
2225 if (number_of_regs_before_varargs > NPARM_REGS)
2226 number_of_regs_before_varargs = NPARM_REGS;
2230 mcore_expand_prolog (void)
2232 struct mcore_frame fi;
2233 int space_allocated = 0;
2236 /* Find out what we're doing. */
2237 layout_mcore_frame (&fi);
2239 space_allocated = fi.arg_size + fi.reg_size + fi.local_size +
2240 fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg;
2244 /* Emit a symbol for this routine's frame size. */
2247 x = DECL_RTL (current_function_decl);
2249 if (GET_CODE (x) != MEM)
2254 if (GET_CODE (x) != SYMBOL_REF)
2257 if (mcore_current_function_name)
2258 free (mcore_current_function_name);
2260 mcore_current_function_name = xstrdup (XSTR (x, 0));
2262 ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated);
2264 if (current_function_calls_alloca)
2265 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1);
2268 We're looking at how the 8byte alignment affects stack layout
2269 and where we had to pad things. This emits information we can
2270 extract which tells us about frame sizes and the like. */
2271 fprintf (asm_out_file,
2272 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2273 mcore_current_function_name,
2274 fi.arg_size, fi.reg_size, fi.reg_mask,
2275 fi.local_size, fi.outbound_size,
2276 frame_pointer_needed);
2279 if (mcore_naked_function_p ())
2282 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2283 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2285 /* If we have a parameter passed partially in regs and partially in memory,
2286 the registers will have been stored to memory already in function.c. So
2287 we only need to do something here for varargs functions. */
2288 if (fi.arg_size != 0 && current_function_pretend_args_size == 0)
2291 int rn = FIRST_PARM_REG + NPARM_REGS - 1;
2292 int remaining = fi.arg_size;
2294 for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4)
2296 emit_insn (gen_movsi
2297 (gen_rtx_MEM (SImode,
2298 plus_constant (stack_pointer_rtx, offset)),
2299 gen_rtx_REG (SImode, rn)));
2303 /* Do we need another stack adjustment before we do the register saves? */
2304 if (growth < fi.reg_growth)
2305 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2307 if (fi.reg_size != 0)
2310 int offs = fi.reg_offset;
2312 for (i = 15; i >= 0; i--)
2314 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2318 while (fi.reg_mask & (1 << first_reg))
2322 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode, stack_pointer_rtx),
2323 gen_rtx_REG (SImode, first_reg),
2324 GEN_INT (16 - first_reg)));
2326 i -= (15 - first_reg);
2327 offs += (16 - first_reg) * 4;
2329 else if (fi.reg_mask & (1 << i))
2331 emit_insn (gen_movsi
2332 (gen_rtx_MEM (SImode,
2333 plus_constant (stack_pointer_rtx, offs)),
2334 gen_rtx_REG (SImode, i)));
2340 /* Figure the locals + outbounds. */
2341 if (frame_pointer_needed)
2343 /* If we haven't already purchased to 'fp'. */
2344 if (growth < fi.local_growth)
2345 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2347 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2349 /* ... and then go any remaining distance for outbounds, etc. */
2350 if (fi.growth[growth])
2351 output_stack_adjust (-1, fi.growth[growth++]);
2355 if (growth < fi.local_growth)
2356 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2357 if (fi.growth[growth])
2358 output_stack_adjust (-1, fi.growth[growth++]);
2363 mcore_expand_epilog (void)
2365 struct mcore_frame fi;
2368 int growth = MAX_STACK_GROWS - 1 ;
2371 /* Find out what we're doing. */
2372 layout_mcore_frame(&fi);
2374 if (mcore_naked_function_p ())
2377 /* If we had a frame pointer, restore the sp from that. */
2378 if (frame_pointer_needed)
2380 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2381 growth = fi.local_growth - 1;
2385 /* XXX: while loop should accumulate and do a single sell. */
2386 while (growth >= fi.local_growth)
2388 if (fi.growth[growth] != 0)
2389 output_stack_adjust (1, fi.growth[growth]);
2394 /* Make sure we've shrunk stack back to the point where the registers
2395 were laid down. This is typically 0/1 iterations. Then pull the
2396 register save information back off the stack. */
2397 while (growth >= fi.reg_growth)
2398 output_stack_adjust ( 1, fi.growth[growth--]);
2400 offs = fi.reg_offset;
2402 for (i = 15; i >= 0; i--)
2404 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2408 /* Find the starting register. */
2411 while (fi.reg_mask & (1 << first_reg))
2416 emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg),
2417 gen_rtx_MEM (SImode, stack_pointer_rtx),
2418 GEN_INT (16 - first_reg)));
2420 i -= (15 - first_reg);
2421 offs += (16 - first_reg) * 4;
2423 else if (fi.reg_mask & (1 << i))
2425 emit_insn (gen_movsi
2426 (gen_rtx_REG (SImode, i),
2427 gen_rtx_MEM (SImode,
2428 plus_constant (stack_pointer_rtx, offs))));
2433 /* Give back anything else. */
2434 /* XXX: Should accumulate total and then give it back. */
2436 output_stack_adjust ( 1, fi.growth[growth--]);
2439 /* This code is borrowed from the SH port. */
2441 /* The MCORE cannot load a large constant into a register, constants have to
2442 come from a pc relative load. The reference of a pc relative load
2443 instruction must be less than 1k infront of the instruction. This
2444 means that we often have to dump a constant inside a function, and
2445 generate code to branch around it.
2447 It is important to minimize this, since the branches will slow things
2448 down and make things bigger.
2450 Worst case code looks like:
2466 We fix this by performing a scan before scheduling, which notices which
2467 instructions need to have their operands fetched from the constant table
2468 and builds the table.
2472 scan, find an instruction which needs a pcrel move. Look forward, find the
2473 last barrier which is within MAX_COUNT bytes of the requirement.
2474 If there isn't one, make one. Process all the instructions between
2475 the find and the barrier.
2477 In the above example, we can tell that L3 is within 1k of L1, so
2478 the first move can be shrunk from the 2 insn+constant sequence into
2479 just 1 insn, and the constant moved to L3 to make:
2489 Then the second move becomes the target for the shortening process. */
2493 rtx value; /* Value in table. */
2494 rtx label; /* Label of value. */
2497 /* The maximum number of constants that can fit into one pool, since
2498 the pc relative range is 0...1020 bytes and constants are at least 4
2499 bytes long. We subtract 4 from the range to allow for the case where
2500 we need to add a branch/align before the constant pool. */
2502 #define MAX_COUNT 1016
2503 #define MAX_POOL_SIZE (MAX_COUNT/4)
2504 static pool_node pool_vector[MAX_POOL_SIZE];
2505 static int pool_size;
2507 /* Dump out any constants accumulated in the final pass. These
2508 will only be labels. */
2511 mcore_output_jump_label_table (void)
2517 fprintf (asm_out_file, "\t.align 2\n");
2519 for (i = 0; i < pool_size; i++)
2521 pool_node * p = pool_vector + i;
2523 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label));
2525 output_asm_insn (".long %0", &p->value);
2534 /* Check whether insn is a candidate for a conditional. */
2537 is_cond_candidate (rtx insn)
2539 /* The only things we conditionalize are those that can be directly
2540 changed into a conditional. Only bother with SImode items. If
2541 we wanted to be a little more aggressive, we could also do other
2542 modes such as DImode with reg-reg move or load 0. */
2543 if (GET_CODE (insn) == INSN)
2545 rtx pat = PATTERN (insn);
2548 if (GET_CODE (pat) != SET)
2551 dst = XEXP (pat, 0);
2553 if ((GET_CODE (dst) != REG &&
2554 GET_CODE (dst) != SUBREG) ||
2555 GET_MODE (dst) != SImode)
2558 src = XEXP (pat, 1);
2560 if ((GET_CODE (src) == REG ||
2561 (GET_CODE (src) == SUBREG &&
2562 GET_CODE (SUBREG_REG (src)) == REG)) &&
2563 GET_MODE (src) == SImode)
2564 return COND_MOV_INSN;
2565 else if (GET_CODE (src) == CONST_INT &&
2567 return COND_CLR_INSN;
2568 else if (GET_CODE (src) == PLUS &&
2569 (GET_CODE (XEXP (src, 0)) == REG ||
2570 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2571 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2572 GET_MODE (XEXP (src, 0)) == SImode &&
2573 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2574 INTVAL (XEXP (src, 1)) == 1)
2575 return COND_INC_INSN;
2576 else if (((GET_CODE (src) == MINUS &&
2577 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2578 INTVAL( XEXP (src, 1)) == 1) ||
2579 (GET_CODE (src) == PLUS &&
2580 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2581 INTVAL (XEXP (src, 1)) == -1)) &&
2582 (GET_CODE (XEXP (src, 0)) == REG ||
2583 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2584 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2585 GET_MODE (XEXP (src, 0)) == SImode)
2586 return COND_DEC_INSN;
2588 /* Some insns that we don't bother with:
2589 (set (rx:DI) (ry:DI))
2590 (set (rx:DI) (const_int 0))
2594 else if (GET_CODE (insn) == JUMP_INSN &&
2595 GET_CODE (PATTERN (insn)) == SET &&
2596 GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF)
2597 return COND_BRANCH_INSN;
2602 /* Emit a conditional version of insn and replace the old insn with the
2603 new one. Return the new insn if emitted. */
2606 emit_new_cond_insn (rtx insn, int cond)
2612 if ((num = is_cond_candidate (insn)) == COND_NO)
2615 pat = PATTERN (insn);
2617 if (GET_CODE (insn) == INSN)
2619 dst = SET_DEST (pat);
2620 src = SET_SRC (pat);
2624 dst = JUMP_LABEL (insn);
2633 c_insn = gen_movt0 (dst, src, dst);
2635 c_insn = gen_movt0 (dst, dst, src);
2640 c_insn = gen_incscc (dst, dst);
2642 c_insn = gen_incscc_false (dst, dst);
2647 c_insn = gen_decscc (dst, dst);
2649 c_insn = gen_decscc_false (dst, dst);
2652 case COND_BRANCH_INSN:
2654 c_insn = gen_branch_true (dst);
2656 c_insn = gen_branch_false (dst);
2663 /* Only copy the notes if they exist. */
2664 if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7)
2666 /* We really don't need to bother with the notes and links at this
2667 point, but go ahead and save the notes. This will help is_dead()
2668 when applying peepholes (links don't matter since they are not
2669 used any more beyond this point for the mcore). */
2670 REG_NOTES (c_insn) = REG_NOTES (insn);
2673 if (num == COND_BRANCH_INSN)
2675 /* For jumps, we need to be a little bit careful and emit the new jump
2676 before the old one and to update the use count for the target label.
2677 This way, the barrier following the old (uncond) jump will get
2678 deleted, but the label won't. */
2679 c_insn = emit_jump_insn_before (c_insn, insn);
2681 ++ LABEL_NUSES (dst);
2683 JUMP_LABEL (c_insn) = dst;
2686 c_insn = emit_insn_after (c_insn, insn);
2693 /* Attempt to change a basic block into a series of conditional insns. This
2694 works by taking the branch at the end of the 1st block and scanning for the
2695 end of the 2nd block. If all instructions in the 2nd block have cond.
2696 versions and the label at the start of block 3 is the same as the target
2697 from the branch at block 1, then conditionalize all insn in block 2 using
2698 the inverse condition of the branch at block 1. (Note I'm bending the
2699 definition of basic block here.)
2703 bt L2 <-- end of block 1 (delete)
2706 br L3 <-- end of block 2
2708 L2: ... <-- start of block 3 (NUSES==1)
2719 we can delete the L2 label if NUSES==1 and re-apply the optimization
2720 starting at the last instruction of block 2. This may allow an entire
2721 if-then-else statement to be conditionalized. BRC */
2723 conditionalize_block (rtx first)
2727 rtx end_blk_1_br = 0;
2728 rtx end_blk_2_insn = 0;
2729 rtx start_blk_3_lab = 0;
2735 /* Check that the first insn is a candidate conditional jump. This is
2736 the one that we'll eliminate. If not, advance to the next insn to
2738 if (GET_CODE (first) != JUMP_INSN ||
2739 GET_CODE (PATTERN (first)) != SET ||
2740 GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE)
2741 return NEXT_INSN (first);
2743 /* Extract some information we need. */
2744 end_blk_1_br = first;
2745 br_pat = PATTERN (end_blk_1_br);
2747 /* Complement the condition since we use the reverse cond. for the insns. */
2748 cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ);
2750 /* Determine what kind of branch we have. */
2751 if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF)
2753 /* A normal branch, so extract label out of first arm. */
2754 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0));
2758 /* An inverse branch, so extract the label out of the 2nd arm
2759 and complement the condition. */
2761 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0));
2764 /* Scan forward for the start of block 2: it must start with a
2765 label and that label must be the same as the branch target
2766 label from block 1. We don't care about whether block 2 actually
2767 ends with a branch or a label (an uncond. branch is
2768 conditionalizable). */
2769 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
2773 code = GET_CODE (insn);
2775 /* Look for the label at the start of block 3. */
2776 if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num)
2779 /* Skip barriers, notes, and conditionalizable insns. If the
2780 insn is not conditionalizable or makes this optimization fail,
2781 just return the next insn so we can start over from that point. */
2782 if (code != BARRIER && code != NOTE && !is_cond_candidate (insn))
2783 return NEXT_INSN (insn);
2785 /* Remember the last real insn before the label (ie end of block 2). */
2786 if (code == JUMP_INSN || code == INSN)
2789 end_blk_2_insn = insn;
2796 /* It is possible for this optimization to slow performance if the blocks
2797 are long. This really depends upon whether the branch is likely taken
2798 or not. If the branch is taken, we slow performance in many cases. But,
2799 if the branch is not taken, we always help performance (for a single
2800 block, but for a double block (i.e. when the optimization is re-applied)
2801 this is not true since the 'right thing' depends on the overall length of
2802 the collapsed block). As a compromise, don't apply this optimization on
2803 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2804 the best threshold depends on the latencies of the instructions (i.e.,
2805 the branch penalty). */
2806 if (optimize > 1 && blk_size > 2)
2809 /* At this point, we've found the start of block 3 and we know that
2810 it is the destination of the branch from block 1. Also, all
2811 instructions in the block 2 are conditionalizable. So, apply the
2812 conditionalization and delete the branch. */
2813 start_blk_3_lab = insn;
2815 for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab;
2816 insn = NEXT_INSN (insn))
2820 if (INSN_DELETED_P (insn))
2823 /* Try to form a conditional variant of the instruction and emit it. */
2824 if ((newinsn = emit_new_cond_insn (insn, cond)))
2826 if (end_blk_2_insn == insn)
2827 end_blk_2_insn = newinsn;
2833 /* Note whether we will delete the label starting blk 3 when the jump
2834 gets deleted. If so, we want to re-apply this optimization at the
2835 last real instruction right before the label. */
2836 if (LABEL_NUSES (start_blk_3_lab) == 1)
2838 start_blk_3_lab = 0;
2841 /* ??? we probably should redistribute the death notes for this insn, esp.
2842 the death of cc, but it doesn't really matter this late in the game.
2843 The peepholes all use is_dead() which will find the correct death
2844 regardless of whether there is a note. */
2845 delete_insn (end_blk_1_br);
2847 if (! start_blk_3_lab)
2848 return end_blk_2_insn;
2850 /* Return the insn right after the label at the start of block 3. */
2851 return NEXT_INSN (start_blk_3_lab);
2854 /* Apply the conditionalization of blocks optimization. This is the
2855 outer loop that traverses through the insns scanning for a branch
2856 that signifies an opportunity to apply the optimization. Note that
2857 this optimization is applied late. If we could apply it earlier,
2858 say before cse 2, it may expose more optimization opportunities.
2859 but, the pay back probably isn't really worth the effort (we'd have
2860 to update all reg/flow/notes/links/etc to make it work - and stick it
2861 in before cse 2). */
2864 conditionalize_optimization (void)
2868 for (insn = get_insns (); insn; insn = conditionalize_block (insn))
2872 static int saved_warn_return_type = -1;
2873 static int saved_warn_return_type_count = 0;
2875 /* This is to handle loads from the constant pool. */
2880 /* Reset this variable. */
2881 current_function_anonymous_args = 0;
2883 /* Restore the warn_return_type if it has been altered. */
2884 if (saved_warn_return_type != -1)
2886 /* Only restore the value if we have reached another function.
2887 The test of warn_return_type occurs in final_function () in
2888 c-decl.c a long time after the code for the function is generated,
2889 so we need a counter to tell us when we have finished parsing that
2890 function and can restore the flag. */
2891 if (--saved_warn_return_type_count == 0)
2893 warn_return_type = saved_warn_return_type;
2894 saved_warn_return_type = -1;
2901 /* Conditionalize blocks where we can. */
2902 conditionalize_optimization ();
2904 /* Literal pool generation is now pushed off until the assembler. */
2908 /* Return true if X is something that can be moved directly into r15. */
2911 mcore_r15_operand_p (rtx x)
2913 switch (GET_CODE (x))
2916 return mcore_const_ok_for_inline (INTVAL (x));
2928 /* Implement SECONDARY_RELOAD_CLASS. If CLASS contains r15, and we can't
2929 directly move X into it, use r1-r14 as a temporary. */
2932 mcore_secondary_reload_class (enum reg_class class,
2933 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2935 if (TEST_HARD_REG_BIT (reg_class_contents[class], 15)
2936 && !mcore_r15_operand_p (x))
2941 /* Return the reg_class to use when reloading the rtx X into the class
2942 CLASS. If X is too complex to move directly into r15, prefer to
2943 use LRW_REGS instead. */
2946 mcore_reload_class (rtx x, enum reg_class class)
2948 if (reg_class_subset_p (LRW_REGS, class) && !mcore_r15_operand_p (x))
2954 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2955 register. Note that the current version doesn't worry about whether
2956 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2957 in r2 matches an SImode in r2. Might think in the future about whether
2958 we want to be able to say something about modes. */
2961 mcore_is_same_reg (rtx x, rtx y)
2963 /* Strip any and all of the subreg wrappers. */
2964 while (GET_CODE (x) == SUBREG)
2967 while (GET_CODE (y) == SUBREG)
2970 if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
2977 mcore_override_options (void)
2979 if (mcore_stack_increment_string)
2981 mcore_stack_increment = atoi (mcore_stack_increment_string);
2983 if (mcore_stack_increment < 0
2984 || (mcore_stack_increment == 0
2985 && (mcore_stack_increment_string[0] != '0'
2986 || mcore_stack_increment_string[1] != 0)))
2987 error ("invalid option `-mstack-increment=%s'",
2988 mcore_stack_increment_string);
2991 /* Only the m340 supports little endian code. */
2992 if (TARGET_LITTLE_END && ! TARGET_M340)
2993 target_flags |= M340_BIT;
2996 /* Compute the number of word sized registers needed to
2997 hold a function argument of mode MODE and type TYPE. */
3000 mcore_num_arg_regs (enum machine_mode mode, tree type)
3004 if (targetm.calls.must_pass_in_stack (mode, type))
3007 if (type && mode == BLKmode)
3008 size = int_size_in_bytes (type);
3010 size = GET_MODE_SIZE (mode);
3012 return ROUND_ADVANCE (size);
3016 handle_structs_in_regs (enum machine_mode mode, tree type, int reg)
3020 /* The MCore ABI defines that a structure whoes size is not a whole multiple
3021 of bytes is passed packed into registers (or spilled onto the stack if
3022 not enough registers are available) with the last few bytes of the
3023 structure being packed, left-justified, into the last register/stack slot.
3024 GCC handles this correctly if the last word is in a stack slot, but we
3025 have to generate a special, PARALLEL RTX if the last word is in an
3026 argument register. */
3028 && TYPE_MODE (type) == BLKmode
3029 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
3030 && (size = int_size_in_bytes (type)) > UNITS_PER_WORD
3031 && (size % UNITS_PER_WORD != 0)
3032 && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS)))
3034 rtx arg_regs [NPARM_REGS];
3039 for (nregs = 0; size > 0; size -= UNITS_PER_WORD)
3042 gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++),
3043 GEN_INT (nregs * UNITS_PER_WORD));
3047 /* We assume here that NPARM_REGS == 6. The assert checks this. */
3048 assert (ARRAY_SIZE (arg_regs) == 6);
3049 rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2],
3050 arg_regs[3], arg_regs[4], arg_regs[5]);
3052 result = gen_rtx_PARALLEL (mode, rtvec);
3056 return gen_rtx_REG (mode, reg);
3060 mcore_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
3062 enum machine_mode mode;
3065 mode = TYPE_MODE (valtype);
3067 PROMOTE_MODE (mode, unsigned_p, NULL);
3069 return handle_structs_in_regs (mode, valtype, FIRST_RET_REG);
3072 /* Define where to put the arguments to a function.
3073 Value is zero to push the argument on the stack,
3074 or a hard register in which to store the argument.
3076 MODE is the argument's machine mode.
3077 TYPE is the data type of the argument (as a tree).
3078 This is null for libcalls where that information may
3080 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3081 the preceding args and about the function being called.
3082 NAMED is nonzero if this argument is a named parameter
3083 (otherwise it is an extra parameter matching an ellipsis).
3085 On MCore the first args are normally in registers
3086 and the rest are pushed. Any arg that starts within the first
3087 NPARM_REGS words is at least partially passed in a register unless
3088 its data type forbids. */
3091 mcore_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode,
3092 tree type, int named)
3096 if (! named || mode == VOIDmode)
3099 if (targetm.calls.must_pass_in_stack (mode, type))
3102 arg_reg = ROUND_REG (cum, mode);
3104 if (arg_reg < NPARM_REGS)
3105 return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg);
3110 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.
3111 Returns the number of argument registers required to hold *part* of
3112 a parameter of machine mode MODE and type TYPE (which may be NULL if
3113 the type is not known). If the argument fits entirely in the argument
3114 registers, or entirely on the stack, then 0 is returned. CUM is the
3115 number of argument registers already used by earlier parameters to
3119 mcore_function_arg_partial_nregs (CUMULATIVE_ARGS cum, enum machine_mode mode,
3120 tree type, int named)
3122 int reg = ROUND_REG (cum, mode);
3127 if (targetm.calls.must_pass_in_stack (mode, type))
3130 /* REG is not the *hardware* register number of the register that holds
3131 the argument, it is the *argument* register number. So for example,
3132 the first argument to a function goes in argument register 0, which
3133 translates (for the MCore) into hardware register 2. The second
3134 argument goes into argument register 1, which translates into hardware
3135 register 3, and so on. NPARM_REGS is the number of argument registers
3136 supported by the target, not the maximum hardware register number of
3138 if (reg >= NPARM_REGS)
3141 /* If the argument fits entirely in registers, return 0. */
3142 if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS)
3145 /* The argument overflows the number of available argument registers.
3146 Compute how many argument registers have not yet been assigned to
3147 hold an argument. */
3148 reg = NPARM_REGS - reg;
3150 /* Return partially in registers and partially on the stack. */
3154 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
3157 mcore_dllexport_name_p (const char * symbol)
3159 return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.';
3162 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
3165 mcore_dllimport_name_p (const char * symbol)
3167 return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.';
3170 /* Mark a DECL as being dllexport'd. */
3173 mcore_mark_dllexport (tree decl)
3175 const char * oldname;
3180 rtlname = XEXP (DECL_RTL (decl), 0);
3182 if (GET_CODE (rtlname) == SYMBOL_REF)
3183 oldname = XSTR (rtlname, 0);
3184 else if ( GET_CODE (rtlname) == MEM
3185 && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
3186 oldname = XSTR (XEXP (rtlname, 0), 0);
3190 if (mcore_dllexport_name_p (oldname))
3191 return; /* Already done. */
3193 newname = alloca (strlen (oldname) + 4);
3194 sprintf (newname, "@e.%s", oldname);
3196 /* We pass newname through get_identifier to ensure it has a unique
3197 address. RTL processing can sometimes peek inside the symbol ref
3198 and compare the string's addresses to see if two symbols are
3200 /* ??? At least I think that's why we do this. */
3201 idp = get_identifier (newname);
3203 XEXP (DECL_RTL (decl), 0) =
3204 gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
3207 /* Mark a DECL as being dllimport'd. */
3210 mcore_mark_dllimport (tree decl)
3212 const char * oldname;
3218 rtlname = XEXP (DECL_RTL (decl), 0);
3220 if (GET_CODE (rtlname) == SYMBOL_REF)
3221 oldname = XSTR (rtlname, 0);
3222 else if ( GET_CODE (rtlname) == MEM
3223 && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
3224 oldname = XSTR (XEXP (rtlname, 0), 0);
3228 if (mcore_dllexport_name_p (oldname))
3229 abort (); /* This shouldn't happen. */
3230 else if (mcore_dllimport_name_p (oldname))
3231 return; /* Already done. */
3233 /* ??? One can well ask why we're making these checks here,
3234 and that would be a good question. */
3236 /* Imported variables can't be initialized. */
3237 if (TREE_CODE (decl) == VAR_DECL
3238 && !DECL_VIRTUAL_P (decl)
3239 && DECL_INITIAL (decl))
3241 error ("%Jinitialized variable '%D' is marked dllimport", decl, decl);
3245 /* `extern' needn't be specified with dllimport.
3246 Specify `extern' now and hope for the best. Sigh. */
3247 if (TREE_CODE (decl) == VAR_DECL
3248 /* ??? Is this test for vtables needed? */
3249 && !DECL_VIRTUAL_P (decl))
3251 DECL_EXTERNAL (decl) = 1;
3252 TREE_PUBLIC (decl) = 1;
3255 newname = alloca (strlen (oldname) + 11);
3256 sprintf (newname, "@i.__imp_%s", oldname);
3258 /* We pass newname through get_identifier to ensure it has a unique
3259 address. RTL processing can sometimes peek inside the symbol ref
3260 and compare the string's addresses to see if two symbols are
3262 /* ??? At least I think that's why we do this. */
3263 idp = get_identifier (newname);
3265 newrtl = gen_rtx_MEM (Pmode,
3266 gen_rtx_SYMBOL_REF (Pmode,
3267 IDENTIFIER_POINTER (idp)));
3268 XEXP (DECL_RTL (decl), 0) = newrtl;
3272 mcore_dllexport_p (tree decl)
3274 if ( TREE_CODE (decl) != VAR_DECL
3275 && TREE_CODE (decl) != FUNCTION_DECL)
3278 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0;
3282 mcore_dllimport_p (tree decl)
3284 if ( TREE_CODE (decl) != VAR_DECL
3285 && TREE_CODE (decl) != FUNCTION_DECL)
3288 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0;
3291 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3292 install some info in the .drective (PE) or .exports (ELF) sections. */
3295 mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIBUTE_UNUSED)
3297 /* Mark the decl so we can tell from the rtl whether the object is
3298 dllexport'd or dllimport'd. */
3299 if (mcore_dllexport_p (decl))
3300 mcore_mark_dllexport (decl);
3301 else if (mcore_dllimport_p (decl))
3302 mcore_mark_dllimport (decl);
3304 /* It might be that DECL has already been marked as dllimport, but
3305 a subsequent definition nullified that. The attribute is gone
3306 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3307 else if ((TREE_CODE (decl) == FUNCTION_DECL
3308 || TREE_CODE (decl) == VAR_DECL)
3309 && DECL_RTL (decl) != NULL_RTX
3310 && GET_CODE (DECL_RTL (decl)) == MEM
3311 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
3312 && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
3313 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
3315 const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
3316 tree idp = get_identifier (oldname + 9);
3317 rtx newrtl = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
3319 XEXP (DECL_RTL (decl), 0) = newrtl;
3321 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3322 ??? We leave these alone for now. */
3326 /* Undo the effects of the above. */
3329 mcore_strip_name_encoding (const char * str)
3331 return str + (str[0] == '@' ? 3 : 0);
3334 /* MCore specific attribute support.
3335 dllexport - for exporting a function/variable that will live in a dll
3336 dllimport - for importing a function/variable from a dll
3337 naked - do not create a function prologue/epilogue. */
3339 const struct attribute_spec mcore_attribute_table[] =
3341 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3342 { "dllexport", 0, 0, true, false, false, NULL },
3343 { "dllimport", 0, 0, true, false, false, NULL },
3344 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute },
3345 { NULL, 0, 0, false, false, false, NULL }
3348 /* Handle a "naked" attribute; arguments as in
3349 struct attribute_spec.handler. */
3352 mcore_handle_naked_attribute (tree * node, tree name, tree args ATTRIBUTE_UNUSED,
3353 int flags ATTRIBUTE_UNUSED, bool * no_add_attrs)
3355 if (TREE_CODE (*node) == FUNCTION_DECL)
3357 /* PR14310 - don't complain about lack of return statement
3358 in naked functions. The solution here is a gross hack
3359 but this is the only way to solve the problem without
3360 adding a new feature to GCC. I did try submitting a patch
3361 that would add such a new feature, but it was (rightfully)
3362 rejected on the grounds that it was creeping featurism,
3363 so hence this code. */
3364 if (warn_return_type)
3366 saved_warn_return_type = warn_return_type;
3367 warn_return_type = 0;
3368 saved_warn_return_type_count = 2;
3370 else if (saved_warn_return_type_count)
3371 saved_warn_return_type_count = 2;
3375 warning ("`%s' attribute only applies to functions",
3376 IDENTIFIER_POINTER (name));
3377 *no_add_attrs = true;
3383 /* ??? It looks like this is PE specific? Oh well, this is what the
3384 old code did as well. */
3387 mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
3392 const char * prefix;
3394 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3396 /* Strip off any encoding in name. */
3397 name = (* targetm.strip_name_encoding) (name);
3399 /* The object is put in, for example, section .text$foo.
3400 The linker will then ultimately place them in .text
3401 (everything from the $ on is stripped). */
3402 if (TREE_CODE (decl) == FUNCTION_DECL)
3404 /* For compatibility with EPOC, we ignore the fact that the
3405 section might have relocs against it. */
3406 else if (decl_readonly_section (decl, 0))
3411 len = strlen (name) + strlen (prefix);
3412 string = alloca (len + 1);
3414 sprintf (string, "%s%s", prefix, name);
3416 DECL_SECTION_NAME (decl) = build_string (len, string);
3420 mcore_naked_function_p (void)
3422 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE;
3425 #ifdef OBJECT_FORMAT_ELF
3427 mcore_asm_named_section (const char *name,
3428 unsigned int flags ATTRIBUTE_UNUSED,
3429 tree decl ATTRIBUTE_UNUSED)
3431 fprintf (asm_out_file, "\t.section %s\n", name);
3433 #endif /* OBJECT_FORMAT_ELF */
3435 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3438 mcore_external_libcall (rtx fun)
3440 fprintf (asm_out_file, "\t.import\t");
3441 assemble_name (asm_out_file, XSTR (fun, 0));
3442 fprintf (asm_out_file, "\n");
3445 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3448 mcore_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3450 HOST_WIDE_INT size = int_size_in_bytes (type);
3451 return (size == -1 || size > 2 * UNITS_PER_WORD);