1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "target-def.h"
49 /* Maximum size we are allowed to grow the stack in a single operation.
50 If we want more, we must do it in increments of at most this size.
51 If this value is 0, we don't check at all. */
52 int mcore_stack_increment = STACK_UNITS_MAXSTEP;
54 /* For dumping information about frame sizes. */
55 char * mcore_current_function_name = 0;
56 long mcore_current_compilation_timestamp = 0;
58 /* Global variables for machine-dependent things. */
60 /* Saved operands from the last compare to use when we generate an scc
65 /* Provides the class number of the smallest class containing
67 const int regno_reg_class[FIRST_PSEUDO_REGISTER] =
69 GENERAL_REGS, ONLYR1_REGS, LRW_REGS, LRW_REGS,
70 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
71 LRW_REGS, LRW_REGS, LRW_REGS, LRW_REGS,
72 LRW_REGS, LRW_REGS, LRW_REGS, GENERAL_REGS,
73 GENERAL_REGS, C_REGS, NO_REGS, NO_REGS,
76 /* Provide reg_class from a letter such as appears in the machine
78 const enum reg_class reg_class_from_letter[] =
80 /* a */ LRW_REGS, /* b */ ONLYR1_REGS, /* c */ C_REGS, /* d */ NO_REGS,
81 /* e */ NO_REGS, /* f */ NO_REGS, /* g */ NO_REGS, /* h */ NO_REGS,
82 /* i */ NO_REGS, /* j */ NO_REGS, /* k */ NO_REGS, /* l */ NO_REGS,
83 /* m */ NO_REGS, /* n */ NO_REGS, /* o */ NO_REGS, /* p */ NO_REGS,
84 /* q */ NO_REGS, /* r */ GENERAL_REGS, /* s */ NO_REGS, /* t */ NO_REGS,
85 /* u */ NO_REGS, /* v */ NO_REGS, /* w */ NO_REGS, /* x */ ALL_REGS,
86 /* y */ NO_REGS, /* z */ NO_REGS
91 int arg_size; /* Stdarg spills (bytes). */
92 int reg_size; /* Non-volatile reg saves (bytes). */
93 int reg_mask; /* Non-volatile reg saves. */
94 int local_size; /* Locals. */
95 int outbound_size; /* Arg overflow on calls out. */
99 /* Describe the steps we'll use to grow it. */
100 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
101 int growth[MAX_STACK_GROWS];
119 static void output_stack_adjust (int, int);
120 static int calc_live_regs (int *);
121 static int try_constant_tricks (long, HOST_WIDE_INT *, HOST_WIDE_INT *);
122 static const char * output_inline_const (enum machine_mode, rtx *);
123 static void layout_mcore_frame (struct mcore_frame *);
124 static void mcore_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
125 static cond_type is_cond_candidate (rtx);
126 static rtx emit_new_cond_insn (rtx, int);
127 static rtx conditionalize_block (rtx);
128 static void conditionalize_optimization (void);
129 static void mcore_reorg (void);
130 static rtx handle_structs_in_regs (enum machine_mode, const_tree, int);
131 static void mcore_mark_dllexport (tree);
132 static void mcore_mark_dllimport (tree);
133 static int mcore_dllexport_p (tree);
134 static int mcore_dllimport_p (tree);
135 const struct attribute_spec mcore_attribute_table[];
136 static tree mcore_handle_naked_attribute (tree *, tree, tree, int, bool *);
137 #ifdef OBJECT_FORMAT_ELF
138 static void mcore_asm_named_section (const char *,
141 static void mcore_unique_section (tree, int);
142 static void mcore_encode_section_info (tree, rtx, int);
143 static const char *mcore_strip_name_encoding (const char *);
144 static int mcore_const_costs (rtx, RTX_CODE);
145 static int mcore_and_cost (rtx);
146 static int mcore_ior_cost (rtx);
147 static bool mcore_rtx_costs (rtx, int, int, int *, bool);
148 static void mcore_external_libcall (rtx);
149 static bool mcore_return_in_memory (const_tree, const_tree);
150 static int mcore_arg_partial_bytes (CUMULATIVE_ARGS *,
155 /* Initialize the GCC target structure. */
156 #undef TARGET_ASM_EXTERNAL_LIBCALL
157 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
159 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
160 #undef TARGET_MERGE_DECL_ATTRIBUTES
161 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
164 #ifdef OBJECT_FORMAT_ELF
165 #undef TARGET_ASM_UNALIGNED_HI_OP
166 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
167 #undef TARGET_ASM_UNALIGNED_SI_OP
168 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
171 #undef TARGET_ATTRIBUTE_TABLE
172 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
173 #undef TARGET_ASM_UNIQUE_SECTION
174 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
175 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
176 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
177 #undef TARGET_DEFAULT_TARGET_FLAGS
178 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
179 #undef TARGET_ENCODE_SECTION_INFO
180 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
181 #undef TARGET_STRIP_NAME_ENCODING
182 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
183 #undef TARGET_RTX_COSTS
184 #define TARGET_RTX_COSTS mcore_rtx_costs
185 #undef TARGET_ADDRESS_COST
186 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
187 #undef TARGET_MACHINE_DEPENDENT_REORG
188 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
190 #undef TARGET_PROMOTE_FUNCTION_ARGS
191 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
192 #undef TARGET_PROMOTE_FUNCTION_RETURN
193 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
194 #undef TARGET_PROMOTE_PROTOTYPES
195 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
197 #undef TARGET_RETURN_IN_MEMORY
198 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
199 #undef TARGET_MUST_PASS_IN_STACK
200 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
201 #undef TARGET_PASS_BY_REFERENCE
202 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
203 #undef TARGET_ARG_PARTIAL_BYTES
204 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
206 #undef TARGET_SETUP_INCOMING_VARARGS
207 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
209 struct gcc_target targetm = TARGET_INITIALIZER;
211 /* Adjust the stack and return the number of bytes taken to do it. */
213 output_stack_adjust (int direction, int size)
215 /* If extending stack a lot, we do it incrementally. */
216 if (direction < 0 && size > mcore_stack_increment && mcore_stack_increment > 0)
218 rtx tmp = gen_rtx_REG (SImode, 1);
221 emit_insn (gen_movsi (tmp, GEN_INT (mcore_stack_increment)));
224 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
225 memref = gen_rtx_MEM (SImode, stack_pointer_rtx);
226 MEM_VOLATILE_P (memref) = 1;
227 emit_insn (gen_movsi (memref, stack_pointer_rtx));
228 size -= mcore_stack_increment;
230 while (size > mcore_stack_increment);
232 /* SIZE is now the residual for the last adjustment,
233 which doesn't require a probe. */
239 rtx val = GEN_INT (size);
243 rtx nval = gen_rtx_REG (SImode, 1);
244 emit_insn (gen_movsi (nval, val));
249 insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
251 insn = gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, val);
257 /* Work out the registers which need to be saved,
258 both as a mask and a count. */
261 calc_live_regs (int * count)
264 int live_regs_mask = 0;
268 for (reg = 0; reg < FIRST_PSEUDO_REGISTER; reg++)
270 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
273 live_regs_mask |= (1 << reg);
277 return live_regs_mask;
280 /* Print the operand address in x to the stream. */
283 mcore_print_operand_address (FILE * stream, rtx x)
285 switch (GET_CODE (x))
288 fprintf (stream, "(%s)", reg_names[REGNO (x)]);
293 rtx base = XEXP (x, 0);
294 rtx index = XEXP (x, 1);
296 if (GET_CODE (base) != REG)
298 /* Ensure that BASE is a register (one of them must be). */
304 switch (GET_CODE (index))
307 fprintf (stream, "(%s," HOST_WIDE_INT_PRINT_DEC ")",
308 reg_names[REGNO(base)], INTVAL (index));
319 output_addr_const (stream, x);
324 /* Print operand x (an rtx) in assembler syntax to file stream
325 according to modifier code.
327 'R' print the next register or memory location along, i.e. the lsw in
329 'O' print a constant without the #
330 'M' print a constant as its negative
331 'P' print log2 of a power of two
332 'Q' print log2 of an inverse of a power of two
333 'U' print register for ldm/stm instruction
334 'X' print byte number for xtrbN instruction. */
337 mcore_print_operand (FILE * stream, rtx x, int code)
343 fprintf (asm_out_file, "32");
345 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) + 1));
348 fprintf (asm_out_file, "%d", exact_log2 (INTVAL (x) & 0xffffffff));
351 fprintf (asm_out_file, "%d", exact_log2 (~INTVAL (x)));
354 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
357 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, - INTVAL (x));
360 /* Next location along in memory or register. */
361 switch (GET_CODE (x))
364 fputs (reg_names[REGNO (x) + 1], (stream));
367 mcore_print_operand_address
368 (stream, XEXP (adjust_address (x, SImode, 4), 0));
375 fprintf (asm_out_file, "%s-%s", reg_names[REGNO (x)],
376 reg_names[REGNO (x) + 3]);
379 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
382 fprintf (asm_out_file, HOST_WIDE_INT_PRINT_DEC, 3 - INTVAL (x) / 8);
386 switch (GET_CODE (x))
389 fputs (reg_names[REGNO (x)], (stream));
392 output_address (XEXP (x, 0));
395 output_addr_const (stream, x);
402 /* What does a constant cost ? */
405 mcore_const_costs (rtx exp, enum rtx_code code)
407 HOST_WIDE_INT val = INTVAL (exp);
409 /* Easy constants. */
410 if ( CONST_OK_FOR_I (val)
411 || CONST_OK_FOR_M (val)
412 || CONST_OK_FOR_N (val)
413 || (code == PLUS && CONST_OK_FOR_L (val)))
416 && ( CONST_OK_FOR_M (~val)
417 || CONST_OK_FOR_N (~val)))
419 else if (code == PLUS
420 && ( CONST_OK_FOR_I (-val)
421 || CONST_OK_FOR_M (-val)
422 || CONST_OK_FOR_N (-val)))
428 /* What does an and instruction cost - we do this b/c immediates may
429 have been relaxed. We want to ensure that cse will cse relaxed immeds
430 out. Otherwise we'll get bad code (multiple reloads of the same const). */
433 mcore_and_cost (rtx x)
437 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
440 val = INTVAL (XEXP (x, 1));
442 /* Do it directly. */
443 if (CONST_OK_FOR_K (val) || CONST_OK_FOR_M (~val))
445 /* Takes one instruction to load. */
446 else if (const_ok_for_mcore (val))
448 /* Takes two instructions to load. */
449 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
452 /* Takes a lrw to load. */
456 /* What does an or cost - see and_cost(). */
459 mcore_ior_cost (rtx x)
463 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
466 val = INTVAL (XEXP (x, 1));
468 /* Do it directly with bclri. */
469 if (CONST_OK_FOR_M (val))
471 /* Takes one instruction to load. */
472 else if (const_ok_for_mcore (val))
474 /* Takes two instructions to load. */
475 else if (TARGET_HARDLIT && mcore_const_ok_for_inline (val))
478 /* Takes a lrw to load. */
483 mcore_rtx_costs (rtx x, int code, int outer_code, int * total,
484 bool speed ATTRIBUTE_UNUSED)
489 *total = mcore_const_costs (x, outer_code);
501 *total = COSTS_N_INSNS (mcore_and_cost (x));
505 *total = COSTS_N_INSNS (mcore_ior_cost (x));
514 *total = COSTS_N_INSNS (100);
522 /* Check to see if a comparison against a constant can be made more efficient
523 by incrementing/decrementing the constant to get one that is more efficient
527 mcore_modify_comparison (enum rtx_code code)
529 rtx op1 = arch_compare_op1;
531 if (GET_CODE (op1) == CONST_INT)
533 HOST_WIDE_INT val = INTVAL (op1);
538 if (CONST_OK_FOR_J (val + 1))
540 arch_compare_op1 = GEN_INT (val + 1);
553 /* Prepare the operands for a comparison. */
556 mcore_gen_compare_reg (enum rtx_code code)
558 rtx op0 = arch_compare_op0;
559 rtx op1 = arch_compare_op1;
560 rtx cc_reg = gen_rtx_REG (CCmode, CC_REG);
562 if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
563 op1 = force_reg (SImode, op1);
565 /* cmpnei: 0-31 (K immediate)
566 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
569 case EQ: /* Use inverted condition, cmpne. */
573 case NE: /* Use normal condition, cmpne. */
574 if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
575 op1 = force_reg (SImode, op1);
578 case LE: /* Use inverted condition, reversed cmplt. */
582 case GT: /* Use normal condition, reversed cmplt. */
583 if (GET_CODE (op1) == CONST_INT)
584 op1 = force_reg (SImode, op1);
587 case GE: /* Use inverted condition, cmplt. */
591 case LT: /* Use normal condition, cmplt. */
592 if (GET_CODE (op1) == CONST_INT &&
593 /* covered by btsti x,31. */
595 ! CONST_OK_FOR_J (INTVAL (op1)))
596 op1 = force_reg (SImode, op1);
599 case GTU: /* Use inverted condition, cmple. */
600 /* Unsigned > 0 is the same as != 0, but we need to invert the
601 condition, so we want to set code = EQ. This cannot be done
602 however, as the mcore does not support such a test. Instead
603 we cope with this case in the "bgtu" pattern itself so we
604 should never reach this point. */
605 gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
609 case LEU: /* Use normal condition, reversed cmphs. */
610 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
611 op1 = force_reg (SImode, op1);
614 case LTU: /* Use inverted condition, cmphs. */
618 case GEU: /* Use normal condition, cmphs. */
619 if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
620 op1 = force_reg (SImode, op1);
627 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, gen_rtx_fmt_ee (code, CCmode, op0, op1)));
633 mcore_symbolic_address_p (rtx x)
635 switch (GET_CODE (x))
642 return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
643 || GET_CODE (XEXP (x, 0)) == LABEL_REF)
644 && GET_CODE (XEXP (x, 1)) == CONST_INT);
650 /* Functions to output assembly code for a function call. */
653 mcore_output_call (rtx operands[], int index)
655 static char buffer[20];
656 rtx addr = operands [index];
662 gcc_assert (mcore_current_function_name);
664 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
668 sprintf (buffer, "jsr\t%%%d", index);
674 gcc_assert (mcore_current_function_name);
675 gcc_assert (GET_CODE (addr) == SYMBOL_REF);
677 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
681 sprintf (buffer, "jbsr\t%%%d", index);
687 /* Can we load a constant with a single instruction ? */
690 const_ok_for_mcore (HOST_WIDE_INT value)
692 if (value >= 0 && value <= 127)
695 /* Try exact power of two. */
696 if (CONST_OK_FOR_M (value))
699 /* Try exact power of two - 1. */
700 if (CONST_OK_FOR_N (value) && value != -1)
706 /* Can we load a constant inline with up to 2 instructions ? */
709 mcore_const_ok_for_inline (HOST_WIDE_INT value)
713 return try_constant_tricks (value, & x, & y) > 0;
716 /* Are we loading the constant using a not ? */
719 mcore_const_trick_uses_not (HOST_WIDE_INT value)
723 return try_constant_tricks (value, & x, & y) == 2;
726 /* Try tricks to load a constant inline and return the trick number if
727 success (0 is non-inlinable).
730 1: single instruction (do the usual thing)
731 2: single insn followed by a 'not'
732 3: single insn followed by a subi
733 4: single insn followed by an addi
734 5: single insn followed by rsubi
735 6: single insn followed by bseti
736 7: single insn followed by bclri
737 8: single insn followed by rotli
738 9: single insn followed by lsli
739 10: single insn followed by ixh
740 11: single insn followed by ixw. */
743 try_constant_tricks (HOST_WIDE_INT value, HOST_WIDE_INT * x, HOST_WIDE_INT * y)
746 unsigned HOST_WIDE_INT bit, shf, rot;
748 if (const_ok_for_mcore (value))
749 return 1; /* Do the usual thing. */
751 if (! TARGET_HARDLIT)
754 if (const_ok_for_mcore (~value))
760 for (i = 1; i <= 32; i++)
762 if (const_ok_for_mcore (value - i))
770 if (const_ok_for_mcore (value + i))
781 for (i = 0; i <= 31; i++)
783 if (const_ok_for_mcore (i - value))
791 if (const_ok_for_mcore (value & ~bit))
798 if (const_ok_for_mcore (value | bit))
812 for (i = 1; i < 31; i++)
816 /* MCore has rotate left. */
820 rot |= c; /* Simulate rotate. */
822 if (const_ok_for_mcore (rot))
831 shf = 0; /* Can't use logical shift, low order bit is one. */
835 if (shf != 0 && const_ok_for_mcore (shf))
844 if ((value % 3) == 0 && const_ok_for_mcore (value / 3))
851 if ((value % 5) == 0 && const_ok_for_mcore (value / 5))
861 /* Check whether reg is dead at first. This is done by searching ahead
862 for either the next use (i.e., reg is live), a death note, or a set of
863 reg. Don't just use dead_or_set_p() since reload does not always mark
864 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
865 can ignore subregs by extracting the actual register. BRC */
868 mcore_is_dead (rtx first, rtx reg)
872 /* For mcore, subregs can't live independently of their parent regs. */
873 if (GET_CODE (reg) == SUBREG)
874 reg = SUBREG_REG (reg);
876 /* Dies immediately. */
877 if (dead_or_set_p (first, reg))
880 /* Look for conclusive evidence of live/death, otherwise we have
881 to assume that it is live. */
882 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
884 if (GET_CODE (insn) == JUMP_INSN)
885 return 0; /* We lose track, assume it is alive. */
887 else if (GET_CODE(insn) == CALL_INSN)
889 /* Call's might use it for target or register parms. */
890 if (reg_referenced_p (reg, PATTERN (insn))
891 || find_reg_fusage (insn, USE, reg))
893 else if (dead_or_set_p (insn, reg))
896 else if (GET_CODE (insn) == INSN)
898 if (reg_referenced_p (reg, PATTERN (insn)))
900 else if (dead_or_set_p (insn, reg))
905 /* No conclusive evidence either way, we cannot take the chance
906 that control flow hid the use from us -- "I'm not dead yet". */
910 /* Count the number of ones in mask. */
913 mcore_num_ones (HOST_WIDE_INT mask)
915 /* A trick to count set bits recently posted on comp.compilers. */
916 mask = (mask >> 1 & 0x55555555) + (mask & 0x55555555);
917 mask = ((mask >> 2) & 0x33333333) + (mask & 0x33333333);
918 mask = ((mask >> 4) + mask) & 0x0f0f0f0f;
919 mask = ((mask >> 8) + mask);
921 return (mask + (mask >> 16)) & 0xff;
924 /* Count the number of zeros in mask. */
927 mcore_num_zeros (HOST_WIDE_INT mask)
929 return 32 - mcore_num_ones (mask);
932 /* Determine byte being masked. */
935 mcore_byte_offset (unsigned int mask)
937 if (mask == 0x00ffffffL)
939 else if (mask == 0xff00ffffL)
941 else if (mask == 0xffff00ffL)
943 else if (mask == 0xffffff00L)
949 /* Determine halfword being masked. */
952 mcore_halfword_offset (unsigned int mask)
954 if (mask == 0x0000ffffL)
956 else if (mask == 0xffff0000L)
962 /* Output a series of bseti's corresponding to mask. */
965 mcore_output_bseti (rtx dst, int mask)
970 out_operands[0] = dst;
972 for (bit = 0; bit < 32; bit++)
974 if ((mask & 0x1) == 0x1)
976 out_operands[1] = GEN_INT (bit);
978 output_asm_insn ("bseti\t%0,%1", out_operands);
986 /* Output a series of bclri's corresponding to mask. */
989 mcore_output_bclri (rtx dst, int mask)
994 out_operands[0] = dst;
996 for (bit = 0; bit < 32; bit++)
998 if ((mask & 0x1) == 0x0)
1000 out_operands[1] = GEN_INT (bit);
1002 output_asm_insn ("bclri\t%0,%1", out_operands);
1011 /* Output a conditional move of two constants that are +/- 1 within each
1012 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1013 really worth the effort. */
1016 mcore_output_cmov (rtx operands[], int cmp_t, const char * test)
1018 HOST_WIDE_INT load_value;
1019 HOST_WIDE_INT adjust_value;
1020 rtx out_operands[4];
1022 out_operands[0] = operands[0];
1024 /* Check to see which constant is loadable. */
1025 if (const_ok_for_mcore (INTVAL (operands[1])))
1027 out_operands[1] = operands[1];
1028 out_operands[2] = operands[2];
1030 else if (const_ok_for_mcore (INTVAL (operands[2])))
1032 out_operands[1] = operands[2];
1033 out_operands[2] = operands[1];
1035 /* Complement test since constants are swapped. */
1036 cmp_t = (cmp_t == 0);
1038 load_value = INTVAL (out_operands[1]);
1039 adjust_value = INTVAL (out_operands[2]);
1041 /* First output the test if folded into the pattern. */
1044 output_asm_insn (test, operands);
1046 /* Load the constant - for now, only support constants that can be
1047 generated with a single instruction. maybe add general inlinable
1048 constants later (this will increase the # of patterns since the
1049 instruction sequence has a different length attribute). */
1050 if (load_value >= 0 && load_value <= 127)
1051 output_asm_insn ("movi\t%0,%1", out_operands);
1052 else if (CONST_OK_FOR_M (load_value))
1053 output_asm_insn ("bgeni\t%0,%P1", out_operands);
1054 else if (CONST_OK_FOR_N (load_value))
1055 output_asm_insn ("bmaski\t%0,%N1", out_operands);
1057 /* Output the constant adjustment. */
1058 if (load_value > adjust_value)
1061 output_asm_insn ("decf\t%0", out_operands);
1063 output_asm_insn ("dect\t%0", out_operands);
1068 output_asm_insn ("incf\t%0", out_operands);
1070 output_asm_insn ("inct\t%0", out_operands);
1076 /* Outputs the peephole for moving a constant that gets not'ed followed
1077 by an and (i.e. combine the not and the and into andn). BRC */
1080 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
1083 rtx out_operands[3];
1084 const char * load_op;
1088 trick_no = try_constant_tricks (INTVAL (operands[1]), &x, &y);
1089 gcc_assert (trick_no == 2);
1091 out_operands[0] = operands[0];
1092 out_operands[1] = GEN_INT (x);
1093 out_operands[2] = operands[2];
1095 if (x >= 0 && x <= 127)
1096 load_op = "movi\t%0,%1";
1098 /* Try exact power of two. */
1099 else if (CONST_OK_FOR_M (x))
1100 load_op = "bgeni\t%0,%P1";
1102 /* Try exact power of two - 1. */
1103 else if (CONST_OK_FOR_N (x))
1104 load_op = "bmaski\t%0,%N1";
1108 load_op = "BADMOVI-andn\t%0, %1";
1112 sprintf (buf, "%s\n\tandn\t%%2,%%0", load_op);
1113 output_asm_insn (buf, out_operands);
1118 /* Output an inline constant. */
1121 output_inline_const (enum machine_mode mode, rtx operands[])
1123 HOST_WIDE_INT x = 0, y = 0;
1125 rtx out_operands[3];
1128 const char *dst_fmt;
1129 HOST_WIDE_INT value;
1131 value = INTVAL (operands[1]);
1133 trick_no = try_constant_tricks (value, &x, &y);
1134 /* lrw's are handled separately: Large inlinable constants never get
1135 turned into lrw's. Our caller uses try_constant_tricks to back
1136 off to an lrw rather than calling this routine. */
1137 gcc_assert (trick_no != 0);
1142 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1143 out_operands[0] = operands[0];
1144 out_operands[1] = GEN_INT (x);
1147 out_operands[2] = GEN_INT (y);
1149 /* Select dst format based on mode. */
1150 if (mode == DImode && (! TARGET_LITTLE_END))
1155 if (x >= 0 && x <= 127)
1156 sprintf (load_op, "movi\t%s,%%1", dst_fmt);
1158 /* Try exact power of two. */
1159 else if (CONST_OK_FOR_M (x))
1160 sprintf (load_op, "bgeni\t%s,%%P1", dst_fmt);
1162 /* Try exact power of two - 1. */
1163 else if (CONST_OK_FOR_N (x))
1164 sprintf (load_op, "bmaski\t%s,%%N1", dst_fmt);
1168 sprintf (load_op, "BADMOVI-inline_const %s, %%1", dst_fmt);
1175 strcpy (buf, load_op);
1178 sprintf (buf, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1181 sprintf (buf, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1184 sprintf (buf, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1187 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1188 sprintf (buf, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1191 sprintf (buf, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1194 sprintf (buf, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1197 sprintf (buf, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1200 sprintf (buf, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op, dst_fmt, value, value);
1203 sprintf (buf, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op, dst_fmt, dst_fmt, value, value);
1206 sprintf (buf, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op, dst_fmt, dst_fmt, value, value);
1212 output_asm_insn (buf, out_operands);
1217 /* Output a move of a word or less value. */
1220 mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
1221 enum machine_mode mode ATTRIBUTE_UNUSED)
1223 rtx dst = operands[0];
1224 rtx src = operands[1];
1226 if (GET_CODE (dst) == REG)
1228 if (GET_CODE (src) == REG)
1230 if (REGNO (src) == CC_REG) /* r-c */
1233 return "mov\t%0,%1"; /* r-r*/
1235 else if (GET_CODE (src) == MEM)
1237 if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
1238 return "lrw\t%0,[%1]"; /* a-R */
1240 switch (GET_MODE (src)) /* r-m */
1243 return "ldw\t%0,%1";
1245 return "ld.h\t%0,%1";
1247 return "ld.b\t%0,%1";
1252 else if (GET_CODE (src) == CONST_INT)
1256 if (CONST_OK_FOR_I (INTVAL (src))) /* r-I */
1257 return "movi\t%0,%1";
1258 else if (CONST_OK_FOR_M (INTVAL (src))) /* r-M */
1259 return "bgeni\t%0,%P1\t// %1 %x1";
1260 else if (CONST_OK_FOR_N (INTVAL (src))) /* r-N */
1261 return "bmaski\t%0,%N1\t// %1 %x1";
1262 else if (try_constant_tricks (INTVAL (src), &x, &y)) /* R-P */
1263 return output_inline_const (SImode, operands); /* 1-2 insns */
1265 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1268 return "lrw\t%0, %1"; /* Into the literal pool. */
1270 else if (GET_CODE (dst) == MEM) /* m-r */
1271 switch (GET_MODE (dst))
1274 return "stw\t%1,%0";
1276 return "st.h\t%1,%0";
1278 return "st.b\t%1,%0";
1286 /* Return a sequence of instructions to perform DI or DF move.
1287 Since the MCORE cannot move a DI or DF in one instruction, we have
1288 to take care when we see overlapping source and dest registers. */
1291 mcore_output_movedouble (rtx operands[], enum machine_mode mode ATTRIBUTE_UNUSED)
1293 rtx dst = operands[0];
1294 rtx src = operands[1];
1296 if (GET_CODE (dst) == REG)
1298 if (GET_CODE (src) == REG)
1300 int dstreg = REGNO (dst);
1301 int srcreg = REGNO (src);
1303 /* Ensure the second source not overwritten. */
1304 if (srcreg + 1 == dstreg)
1305 return "mov %R0,%R1\n\tmov %0,%1";
1307 return "mov %0,%1\n\tmov %R0,%R1";
1309 else if (GET_CODE (src) == MEM)
1311 rtx memexp = memexp = XEXP (src, 0);
1312 int dstreg = REGNO (dst);
1315 if (GET_CODE (memexp) == LABEL_REF)
1316 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1317 else if (GET_CODE (memexp) == REG)
1318 basereg = REGNO (memexp);
1319 else if (GET_CODE (memexp) == PLUS)
1321 if (GET_CODE (XEXP (memexp, 0)) == REG)
1322 basereg = REGNO (XEXP (memexp, 0));
1323 else if (GET_CODE (XEXP (memexp, 1)) == REG)
1324 basereg = REGNO (XEXP (memexp, 1));
1331 /* ??? length attribute is wrong here. */
1332 if (dstreg == basereg)
1334 /* Just load them in reverse order. */
1335 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1337 /* XXX: alternative: move basereg to basereg+1
1338 and then fall through. */
1341 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1343 else if (GET_CODE (src) == CONST_INT)
1345 if (TARGET_LITTLE_END)
1347 if (CONST_OK_FOR_I (INTVAL (src)))
1348 output_asm_insn ("movi %0,%1", operands);
1349 else if (CONST_OK_FOR_M (INTVAL (src)))
1350 output_asm_insn ("bgeni %0,%P1", operands);
1351 else if (CONST_OK_FOR_N (INTVAL (src)))
1352 output_asm_insn ("bmaski %0,%N1", operands);
1356 if (INTVAL (src) < 0)
1357 return "bmaski %R0,32";
1359 return "movi %R0,0";
1363 if (CONST_OK_FOR_I (INTVAL (src)))
1364 output_asm_insn ("movi %R0,%1", operands);
1365 else if (CONST_OK_FOR_M (INTVAL (src)))
1366 output_asm_insn ("bgeni %R0,%P1", operands);
1367 else if (CONST_OK_FOR_N (INTVAL (src)))
1368 output_asm_insn ("bmaski %R0,%N1", operands);
1372 if (INTVAL (src) < 0)
1373 return "bmaski %0,32";
1381 else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
1382 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1387 /* Predicates used by the templates. */
1390 mcore_arith_S_operand (rtx op)
1392 if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
1398 /* Expand insert bit field. BRC */
1401 mcore_expand_insv (rtx operands[])
1403 int width = INTVAL (operands[1]);
1404 int posn = INTVAL (operands[2]);
1406 rtx mreg, sreg, ereg;
1408 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1409 for width==1 must be removed. Look around line 368. This is something
1410 we really want the md part to do. */
1411 if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
1413 /* Do directly with bseti or bclri. */
1414 /* RBE: 2/97 consider only low bit of constant. */
1415 if ((INTVAL (operands[3]) & 1) == 0)
1417 mask = ~(1 << posn);
1418 emit_insn (gen_rtx_SET (SImode, operands[0],
1419 gen_rtx_AND (SImode, operands[0], GEN_INT (mask))));
1424 emit_insn (gen_rtx_SET (SImode, operands[0],
1425 gen_rtx_IOR (SImode, operands[0], GEN_INT (mask))));
1431 /* Look at some bit-field placements that we aren't interested
1432 in handling ourselves, unless specifically directed to do so. */
1433 if (! TARGET_W_FIELD)
1434 return 0; /* Generally, give up about now. */
1436 if (width == 8 && posn % 8 == 0)
1437 /* Byte sized and aligned; let caller break it up. */
1440 if (width == 16 && posn % 16 == 0)
1441 /* Short sized and aligned; let caller break it up. */
1444 /* The general case - we can do this a little bit better than what the
1445 machine independent part tries. This will get rid of all the subregs
1446 that mess up constant folding in combine when working with relaxed
1449 /* If setting the entire field, do it directly. */
1450 if (GET_CODE (operands[3]) == CONST_INT
1451 && INTVAL (operands[3]) == ((1 << width) - 1))
1453 mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
1454 emit_insn (gen_rtx_SET (SImode, operands[0],
1455 gen_rtx_IOR (SImode, operands[0], mreg)));
1459 /* Generate the clear mask. */
1460 mreg = force_reg (SImode, GEN_INT (~(((1 << width) - 1) << posn)));
1462 /* Clear the field, to overlay it later with the source. */
1463 emit_insn (gen_rtx_SET (SImode, operands[0],
1464 gen_rtx_AND (SImode, operands[0], mreg)));
1466 /* If the source is constant 0, we've nothing to add back. */
1467 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
1470 /* XXX: Should we worry about more games with constant values?
1471 We've covered the high profile: set/clear single-bit and many-bit
1472 fields. How often do we see "arbitrary bit pattern" constants? */
1473 sreg = copy_to_mode_reg (SImode, operands[3]);
1475 /* Extract src as same width as dst (needed for signed values). We
1476 always have to do this since we widen everything to SImode.
1477 We don't have to mask if we're shifting this up against the
1478 MSB of the register (e.g., the shift will push out any hi-order
1480 if (width + posn != (int) GET_MODE_SIZE (SImode))
1482 ereg = force_reg (SImode, GEN_INT ((1 << width) - 1));
1483 emit_insn (gen_rtx_SET (SImode, sreg,
1484 gen_rtx_AND (SImode, sreg, ereg)));
1487 /* Insert source value in dest. */
1489 emit_insn (gen_rtx_SET (SImode, sreg,
1490 gen_rtx_ASHIFT (SImode, sreg, GEN_INT (posn))));
1492 emit_insn (gen_rtx_SET (SImode, operands[0],
1493 gen_rtx_IOR (SImode, operands[0], sreg)));
1498 /* ??? Block move stuff stolen from m88k. This code has not been
1499 verified for correctness. */
1501 /* Emit code to perform a block move. Choose the best method.
1503 OPERANDS[0] is the destination.
1504 OPERANDS[1] is the source.
1505 OPERANDS[2] is the size.
1506 OPERANDS[3] is the alignment safe to use. */
1508 /* Emit code to perform a block move with an offset sequence of ldw/st
1509 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1510 known constants. DEST and SRC are registers. OFFSET is the known
1511 starting point for the output pattern. */
1513 static const enum machine_mode mode_from_align[] =
1515 VOIDmode, QImode, HImode, VOIDmode, SImode,
1519 block_move_sequence (rtx dst_mem, rtx src_mem, int size, int align)
1522 enum machine_mode mode[2];
1531 x = XEXP (dst_mem, 0);
1534 x = force_reg (Pmode, x);
1535 dst_mem = replace_equiv_address (dst_mem, x);
1538 x = XEXP (src_mem, 0);
1541 x = force_reg (Pmode, x);
1542 src_mem = replace_equiv_address (src_mem, x);
1545 active[0] = active[1] = false;
1556 next_amount = (size >= 4 ? 4 : (size >= 2 ? 2 : 1));
1557 next_amount = MIN (next_amount, align);
1559 amount[next] = next_amount;
1560 mode[next] = mode_from_align[next_amount];
1561 temp[next] = gen_reg_rtx (mode[next]);
1563 x = adjust_address (src_mem, mode[next], offset_ld);
1564 emit_insn (gen_rtx_SET (VOIDmode, temp[next], x));
1566 offset_ld += next_amount;
1567 size -= next_amount;
1568 active[next] = true;
1573 active[phase] = false;
1575 x = adjust_address (dst_mem, mode[phase], offset_st);
1576 emit_insn (gen_rtx_SET (VOIDmode, x, temp[phase]));
1578 offset_st += amount[phase];
1581 while (active[next]);
1585 mcore_expand_block_move (rtx *operands)
1587 HOST_WIDE_INT align, bytes, max;
1589 if (GET_CODE (operands[2]) != CONST_INT)
1592 bytes = INTVAL (operands[2]);
1593 align = INTVAL (operands[3]);
1622 block_move_sequence (operands[0], operands[1], bytes, align);
1630 /* Code to generate prologue and epilogue sequences. */
1631 static int number_of_regs_before_varargs;
1633 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1634 for a varargs function. */
1635 static int current_function_anonymous_args;
1637 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1638 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1639 #define ADDI_REACH (32) /* Maximum addi operand. */
1642 layout_mcore_frame (struct mcore_frame * infp)
1651 unsigned int growths;
1654 /* Might have to spill bytes to re-assemble a big argument that
1655 was passed partially in registers and partially on the stack. */
1656 nbytes = crtl->args.pretend_args_size;
1658 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1659 if (current_function_anonymous_args)
1660 nbytes += (NPARM_REGS - number_of_regs_before_varargs) * UNITS_PER_WORD;
1662 infp->arg_size = nbytes;
1664 /* How much space to save non-volatile registers we stomp. */
1665 infp->reg_mask = calc_live_regs (& n);
1666 infp->reg_size = n * 4;
1668 /* And the rest of it... locals and space for overflowed outbounds. */
1669 infp->local_size = get_frame_size ();
1670 infp->outbound_size = crtl->outgoing_args_size;
1672 /* Make sure we have a whole number of words for the locals. */
1673 if (infp->local_size % STACK_BYTES)
1674 infp->local_size = (infp->local_size + STACK_BYTES - 1) & ~ (STACK_BYTES -1);
1676 /* Only thing we know we have to pad is the outbound space, since
1677 we've aligned our locals assuming that base of locals is aligned. */
1678 infp->pad_local = 0;
1680 infp->pad_outbound = 0;
1681 if (infp->outbound_size % STACK_BYTES)
1682 infp->pad_outbound = STACK_BYTES - (infp->outbound_size % STACK_BYTES);
1684 /* Now we see how we want to stage the prologue so that it does
1685 the most appropriate stack growth and register saves to either:
1687 (2) reduce instruction space, or
1688 (3) reduce stack space. */
1689 for (i = 0; i < ARRAY_SIZE (infp->growth); i++)
1690 infp->growth[i] = 0;
1692 regarg = infp->reg_size + infp->arg_size;
1693 localregarg = infp->local_size + regarg;
1694 localreg = infp->local_size + infp->reg_size;
1695 outbounds = infp->outbound_size + infp->pad_outbound;
1698 /* XXX: Consider one where we consider localregarg + outbound too! */
1700 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1701 use stw's with offsets and buy the frame in one shot. */
1702 if (localregarg <= ADDI_REACH
1703 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
1705 /* Make sure we'll be aligned. */
1706 if (localregarg % STACK_BYTES)
1707 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
1709 step = localregarg + infp->pad_reg;
1710 infp->reg_offset = infp->local_size;
1712 if (outbounds + step <= ADDI_REACH && !frame_pointer_needed)
1715 infp->reg_offset += outbounds;
1719 infp->arg_offset = step - 4;
1720 infp->growth[growths++] = step;
1721 infp->reg_growth = growths;
1722 infp->local_growth = growths;
1724 /* If we haven't already folded it in. */
1726 infp->growth[growths++] = outbounds;
1731 /* Frame can't be done with a single subi, but can be done with 2
1732 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1733 shift some of the stack purchase into the first subi, so both are
1734 single instructions. */
1735 if (localregarg <= STORE_REACH
1736 && (infp->local_size > ADDI_REACH)
1737 && (infp->reg_size <= 8 || (infp->reg_mask & 0xc000) != 0xc000))
1741 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1742 if (localregarg % STACK_BYTES)
1743 infp->pad_reg = STACK_BYTES - (localregarg % STACK_BYTES);
1745 all = localregarg + infp->pad_reg + infp->pad_local;
1746 step = ADDI_REACH; /* As much up front as we can. */
1750 /* XXX: Consider whether step will still be aligned; we believe so. */
1751 infp->arg_offset = step - 4;
1752 infp->growth[growths++] = step;
1753 infp->reg_growth = growths;
1754 infp->reg_offset = step - infp->pad_reg - infp->reg_size;
1757 /* Can we fold in any space required for outbounds? */
1758 if (outbounds + all <= ADDI_REACH && !frame_pointer_needed)
1764 /* Get the rest of the locals in place. */
1766 infp->growth[growths++] = step;
1767 infp->local_growth = growths;
1772 /* Finish off if we need to do so. */
1774 infp->growth[growths++] = outbounds;
1779 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1780 Then we buy the rest of the frame in 1 or 2 steps depending on
1781 whether we need a frame pointer. */
1782 if ((regarg % STACK_BYTES) == 0)
1784 infp->growth[growths++] = regarg;
1785 infp->reg_growth = growths;
1786 infp->arg_offset = regarg - 4;
1787 infp->reg_offset = 0;
1789 if (infp->local_size % STACK_BYTES)
1790 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
1792 step = infp->local_size + infp->pad_local;
1794 if (!frame_pointer_needed)
1800 infp->growth[growths++] = step;
1801 infp->local_growth = growths;
1803 /* If there's any left to be done. */
1805 infp->growth[growths++] = outbounds;
1810 /* XXX: optimizations that we'll want to play with....
1811 -- regarg is not aligned, but it's a small number of registers;
1812 use some of localsize so that regarg is aligned and then
1813 save the registers. */
1815 /* Simple encoding; plods down the stack buying the pieces as it goes.
1816 -- does not optimize space consumption.
1817 -- does not attempt to optimize instruction counts.
1818 -- but it is safe for all alignments. */
1819 if (regarg % STACK_BYTES != 0)
1820 infp->pad_reg = STACK_BYTES - (regarg % STACK_BYTES);
1822 infp->growth[growths++] = infp->arg_size + infp->reg_size + infp->pad_reg;
1823 infp->reg_growth = growths;
1824 infp->arg_offset = infp->growth[0] - 4;
1825 infp->reg_offset = 0;
1827 if (frame_pointer_needed)
1829 if (infp->local_size % STACK_BYTES != 0)
1830 infp->pad_local = STACK_BYTES - (infp->local_size % STACK_BYTES);
1832 infp->growth[growths++] = infp->local_size + infp->pad_local;
1833 infp->local_growth = growths;
1835 infp->growth[growths++] = outbounds;
1839 if ((infp->local_size + outbounds) % STACK_BYTES != 0)
1840 infp->pad_local = STACK_BYTES - ((infp->local_size + outbounds) % STACK_BYTES);
1842 infp->growth[growths++] = infp->local_size + infp->pad_local + outbounds;
1843 infp->local_growth = growths;
1846 /* Anything else that we've forgotten?, plus a few consistency checks. */
1848 assert (infp->reg_offset >= 0);
1849 assert (growths <= MAX_STACK_GROWS);
1851 for (i = 0; i < growths; i++)
1852 gcc_assert (!(infp->growth[i] % STACK_BYTES));
1855 /* Define the offset between two registers, one to be eliminated, and
1856 the other its replacement, at the start of a routine. */
1859 mcore_initial_elimination_offset (int from, int to)
1863 struct mcore_frame fi;
1865 layout_mcore_frame (& fi);
1868 above_frame = fi.local_size + fi.pad_local + fi.reg_size + fi.pad_reg;
1870 below_frame = fi.outbound_size + fi.pad_outbound;
1872 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1875 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1876 return above_frame + below_frame;
1878 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1884 /* Keep track of some information about varargs for the prolog. */
1887 mcore_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_far,
1888 enum machine_mode mode, tree type,
1889 int * ptr_pretend_size ATTRIBUTE_UNUSED,
1890 int second_time ATTRIBUTE_UNUSED)
1892 current_function_anonymous_args = 1;
1894 /* We need to know how many argument registers are used before
1895 the varargs start, so that we can push the remaining argument
1896 registers during the prologue. */
1897 number_of_regs_before_varargs = *args_so_far + mcore_num_arg_regs (mode, type);
1899 /* There is a bug somewhere in the arg handling code.
1900 Until I can find it this workaround always pushes the
1901 last named argument onto the stack. */
1902 number_of_regs_before_varargs = *args_so_far;
1904 /* The last named argument may be split between argument registers
1905 and the stack. Allow for this here. */
1906 if (number_of_regs_before_varargs > NPARM_REGS)
1907 number_of_regs_before_varargs = NPARM_REGS;
1911 mcore_expand_prolog (void)
1913 struct mcore_frame fi;
1914 int space_allocated = 0;
1917 /* Find out what we're doing. */
1918 layout_mcore_frame (&fi);
1920 space_allocated = fi.arg_size + fi.reg_size + fi.local_size +
1921 fi.outbound_size + fi.pad_outbound + fi.pad_local + fi.pad_reg;
1925 /* Emit a symbol for this routine's frame size. */
1928 x = DECL_RTL (current_function_decl);
1930 gcc_assert (GET_CODE (x) == MEM);
1934 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1936 if (mcore_current_function_name)
1937 free (mcore_current_function_name);
1939 mcore_current_function_name = xstrdup (XSTR (x, 0));
1941 ASM_OUTPUT_CG_NODE (asm_out_file, mcore_current_function_name, space_allocated);
1943 if (cfun->calls_alloca)
1944 ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name, "alloca", 1);
1947 We're looking at how the 8byte alignment affects stack layout
1948 and where we had to pad things. This emits information we can
1949 extract which tells us about frame sizes and the like. */
1950 fprintf (asm_out_file,
1951 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
1952 mcore_current_function_name,
1953 fi.arg_size, fi.reg_size, fi.reg_mask,
1954 fi.local_size, fi.outbound_size,
1955 frame_pointer_needed);
1958 if (mcore_naked_function_p ())
1961 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
1962 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
1964 /* If we have a parameter passed partially in regs and partially in memory,
1965 the registers will have been stored to memory already in function.c. So
1966 we only need to do something here for varargs functions. */
1967 if (fi.arg_size != 0 && crtl->args.pretend_args_size == 0)
1970 int rn = FIRST_PARM_REG + NPARM_REGS - 1;
1971 int remaining = fi.arg_size;
1973 for (offset = fi.arg_offset; remaining >= 4; offset -= 4, rn--, remaining -= 4)
1975 emit_insn (gen_movsi
1976 (gen_rtx_MEM (SImode,
1977 plus_constant (stack_pointer_rtx, offset)),
1978 gen_rtx_REG (SImode, rn)));
1982 /* Do we need another stack adjustment before we do the register saves? */
1983 if (growth < fi.reg_growth)
1984 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
1986 if (fi.reg_size != 0)
1989 int offs = fi.reg_offset;
1991 for (i = 15; i >= 0; i--)
1993 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
1997 while (fi.reg_mask & (1 << first_reg))
2001 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode, stack_pointer_rtx),
2002 gen_rtx_REG (SImode, first_reg),
2003 GEN_INT (16 - first_reg)));
2005 i -= (15 - first_reg);
2006 offs += (16 - first_reg) * 4;
2008 else if (fi.reg_mask & (1 << i))
2010 emit_insn (gen_movsi
2011 (gen_rtx_MEM (SImode,
2012 plus_constant (stack_pointer_rtx, offs)),
2013 gen_rtx_REG (SImode, i)));
2019 /* Figure the locals + outbounds. */
2020 if (frame_pointer_needed)
2022 /* If we haven't already purchased to 'fp'. */
2023 if (growth < fi.local_growth)
2024 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2026 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
2028 /* ... and then go any remaining distance for outbounds, etc. */
2029 if (fi.growth[growth])
2030 output_stack_adjust (-1, fi.growth[growth++]);
2034 if (growth < fi.local_growth)
2035 output_stack_adjust (-1, fi.growth[growth++]); /* Grows it. */
2036 if (fi.growth[growth])
2037 output_stack_adjust (-1, fi.growth[growth++]);
2042 mcore_expand_epilog (void)
2044 struct mcore_frame fi;
2047 int growth = MAX_STACK_GROWS - 1 ;
2050 /* Find out what we're doing. */
2051 layout_mcore_frame(&fi);
2053 if (mcore_naked_function_p ())
2056 /* If we had a frame pointer, restore the sp from that. */
2057 if (frame_pointer_needed)
2059 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx));
2060 growth = fi.local_growth - 1;
2064 /* XXX: while loop should accumulate and do a single sell. */
2065 while (growth >= fi.local_growth)
2067 if (fi.growth[growth] != 0)
2068 output_stack_adjust (1, fi.growth[growth]);
2073 /* Make sure we've shrunk stack back to the point where the registers
2074 were laid down. This is typically 0/1 iterations. Then pull the
2075 register save information back off the stack. */
2076 while (growth >= fi.reg_growth)
2077 output_stack_adjust ( 1, fi.growth[growth--]);
2079 offs = fi.reg_offset;
2081 for (i = 15; i >= 0; i--)
2083 if (offs == 0 && i == 15 && ((fi.reg_mask & 0xc000) == 0xc000))
2087 /* Find the starting register. */
2090 while (fi.reg_mask & (1 << first_reg))
2095 emit_insn (gen_load_multiple (gen_rtx_REG (SImode, first_reg),
2096 gen_rtx_MEM (SImode, stack_pointer_rtx),
2097 GEN_INT (16 - first_reg)));
2099 i -= (15 - first_reg);
2100 offs += (16 - first_reg) * 4;
2102 else if (fi.reg_mask & (1 << i))
2104 emit_insn (gen_movsi
2105 (gen_rtx_REG (SImode, i),
2106 gen_rtx_MEM (SImode,
2107 plus_constant (stack_pointer_rtx, offs))));
2112 /* Give back anything else. */
2113 /* XXX: Should accumulate total and then give it back. */
2115 output_stack_adjust ( 1, fi.growth[growth--]);
2118 /* This code is borrowed from the SH port. */
2120 /* The MCORE cannot load a large constant into a register, constants have to
2121 come from a pc relative load. The reference of a pc relative load
2122 instruction must be less than 1k in front of the instruction. This
2123 means that we often have to dump a constant inside a function, and
2124 generate code to branch around it.
2126 It is important to minimize this, since the branches will slow things
2127 down and make things bigger.
2129 Worst case code looks like:
2145 We fix this by performing a scan before scheduling, which notices which
2146 instructions need to have their operands fetched from the constant table
2147 and builds the table.
2151 scan, find an instruction which needs a pcrel move. Look forward, find the
2152 last barrier which is within MAX_COUNT bytes of the requirement.
2153 If there isn't one, make one. Process all the instructions between
2154 the find and the barrier.
2156 In the above example, we can tell that L3 is within 1k of L1, so
2157 the first move can be shrunk from the 2 insn+constant sequence into
2158 just 1 insn, and the constant moved to L3 to make:
2168 Then the second move becomes the target for the shortening process. */
2172 rtx value; /* Value in table. */
2173 rtx label; /* Label of value. */
2176 /* The maximum number of constants that can fit into one pool, since
2177 the pc relative range is 0...1020 bytes and constants are at least 4
2178 bytes long. We subtract 4 from the range to allow for the case where
2179 we need to add a branch/align before the constant pool. */
2181 #define MAX_COUNT 1016
2182 #define MAX_POOL_SIZE (MAX_COUNT/4)
2183 static pool_node pool_vector[MAX_POOL_SIZE];
2184 static int pool_size;
2186 /* Dump out any constants accumulated in the final pass. These
2187 will only be labels. */
2190 mcore_output_jump_label_table (void)
2196 fprintf (asm_out_file, "\t.align 2\n");
2198 for (i = 0; i < pool_size; i++)
2200 pool_node * p = pool_vector + i;
2202 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (p->label));
2204 output_asm_insn (".long %0", &p->value);
2213 /* Check whether insn is a candidate for a conditional. */
2216 is_cond_candidate (rtx insn)
2218 /* The only things we conditionalize are those that can be directly
2219 changed into a conditional. Only bother with SImode items. If
2220 we wanted to be a little more aggressive, we could also do other
2221 modes such as DImode with reg-reg move or load 0. */
2222 if (GET_CODE (insn) == INSN)
2224 rtx pat = PATTERN (insn);
2227 if (GET_CODE (pat) != SET)
2230 dst = XEXP (pat, 0);
2232 if ((GET_CODE (dst) != REG &&
2233 GET_CODE (dst) != SUBREG) ||
2234 GET_MODE (dst) != SImode)
2237 src = XEXP (pat, 1);
2239 if ((GET_CODE (src) == REG ||
2240 (GET_CODE (src) == SUBREG &&
2241 GET_CODE (SUBREG_REG (src)) == REG)) &&
2242 GET_MODE (src) == SImode)
2243 return COND_MOV_INSN;
2244 else if (GET_CODE (src) == CONST_INT &&
2246 return COND_CLR_INSN;
2247 else if (GET_CODE (src) == PLUS &&
2248 (GET_CODE (XEXP (src, 0)) == REG ||
2249 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2250 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2251 GET_MODE (XEXP (src, 0)) == SImode &&
2252 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2253 INTVAL (XEXP (src, 1)) == 1)
2254 return COND_INC_INSN;
2255 else if (((GET_CODE (src) == MINUS &&
2256 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2257 INTVAL( XEXP (src, 1)) == 1) ||
2258 (GET_CODE (src) == PLUS &&
2259 GET_CODE (XEXP (src, 1)) == CONST_INT &&
2260 INTVAL (XEXP (src, 1)) == -1)) &&
2261 (GET_CODE (XEXP (src, 0)) == REG ||
2262 (GET_CODE (XEXP (src, 0)) == SUBREG &&
2263 GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
2264 GET_MODE (XEXP (src, 0)) == SImode)
2265 return COND_DEC_INSN;
2267 /* Some insns that we don't bother with:
2268 (set (rx:DI) (ry:DI))
2269 (set (rx:DI) (const_int 0))
2273 else if (GET_CODE (insn) == JUMP_INSN &&
2274 GET_CODE (PATTERN (insn)) == SET &&
2275 GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF)
2276 return COND_BRANCH_INSN;
2281 /* Emit a conditional version of insn and replace the old insn with the
2282 new one. Return the new insn if emitted. */
2285 emit_new_cond_insn (rtx insn, int cond)
2291 if ((num = is_cond_candidate (insn)) == COND_NO)
2294 pat = PATTERN (insn);
2296 if (GET_CODE (insn) == INSN)
2298 dst = SET_DEST (pat);
2299 src = SET_SRC (pat);
2303 dst = JUMP_LABEL (insn);
2312 c_insn = gen_movt0 (dst, src, dst);
2314 c_insn = gen_movt0 (dst, dst, src);
2319 c_insn = gen_incscc (dst, dst);
2321 c_insn = gen_incscc_false (dst, dst);
2326 c_insn = gen_decscc (dst, dst);
2328 c_insn = gen_decscc_false (dst, dst);
2331 case COND_BRANCH_INSN:
2333 c_insn = gen_branch_true (dst);
2335 c_insn = gen_branch_false (dst);
2342 /* Only copy the notes if they exist. */
2343 if (rtx_length [GET_CODE (c_insn)] >= 7 && rtx_length [GET_CODE (insn)] >= 7)
2345 /* We really don't need to bother with the notes and links at this
2346 point, but go ahead and save the notes. This will help is_dead()
2347 when applying peepholes (links don't matter since they are not
2348 used any more beyond this point for the mcore). */
2349 REG_NOTES (c_insn) = REG_NOTES (insn);
2352 if (num == COND_BRANCH_INSN)
2354 /* For jumps, we need to be a little bit careful and emit the new jump
2355 before the old one and to update the use count for the target label.
2356 This way, the barrier following the old (uncond) jump will get
2357 deleted, but the label won't. */
2358 c_insn = emit_jump_insn_before (c_insn, insn);
2360 ++ LABEL_NUSES (dst);
2362 JUMP_LABEL (c_insn) = dst;
2365 c_insn = emit_insn_after (c_insn, insn);
2372 /* Attempt to change a basic block into a series of conditional insns. This
2373 works by taking the branch at the end of the 1st block and scanning for the
2374 end of the 2nd block. If all instructions in the 2nd block have cond.
2375 versions and the label at the start of block 3 is the same as the target
2376 from the branch at block 1, then conditionalize all insn in block 2 using
2377 the inverse condition of the branch at block 1. (Note I'm bending the
2378 definition of basic block here.)
2382 bt L2 <-- end of block 1 (delete)
2385 br L3 <-- end of block 2
2387 L2: ... <-- start of block 3 (NUSES==1)
2398 we can delete the L2 label if NUSES==1 and re-apply the optimization
2399 starting at the last instruction of block 2. This may allow an entire
2400 if-then-else statement to be conditionalized. BRC */
2402 conditionalize_block (rtx first)
2406 rtx end_blk_1_br = 0;
2407 rtx end_blk_2_insn = 0;
2408 rtx start_blk_3_lab = 0;
2414 /* Check that the first insn is a candidate conditional jump. This is
2415 the one that we'll eliminate. If not, advance to the next insn to
2417 if (GET_CODE (first) != JUMP_INSN ||
2418 GET_CODE (PATTERN (first)) != SET ||
2419 GET_CODE (XEXP (PATTERN (first), 1)) != IF_THEN_ELSE)
2420 return NEXT_INSN (first);
2422 /* Extract some information we need. */
2423 end_blk_1_br = first;
2424 br_pat = PATTERN (end_blk_1_br);
2426 /* Complement the condition since we use the reverse cond. for the insns. */
2427 cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ);
2429 /* Determine what kind of branch we have. */
2430 if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF)
2432 /* A normal branch, so extract label out of first arm. */
2433 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0));
2437 /* An inverse branch, so extract the label out of the 2nd arm
2438 and complement the condition. */
2440 br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 2), 0));
2443 /* Scan forward for the start of block 2: it must start with a
2444 label and that label must be the same as the branch target
2445 label from block 1. We don't care about whether block 2 actually
2446 ends with a branch or a label (an uncond. branch is
2447 conditionalizable). */
2448 for (insn = NEXT_INSN (first); insn; insn = NEXT_INSN (insn))
2452 code = GET_CODE (insn);
2454 /* Look for the label at the start of block 3. */
2455 if (code == CODE_LABEL && CODE_LABEL_NUMBER (insn) == br_lab_num)
2458 /* Skip barriers, notes, and conditionalizable insns. If the
2459 insn is not conditionalizable or makes this optimization fail,
2460 just return the next insn so we can start over from that point. */
2461 if (code != BARRIER && code != NOTE && !is_cond_candidate (insn))
2462 return NEXT_INSN (insn);
2464 /* Remember the last real insn before the label (i.e. end of block 2). */
2465 if (code == JUMP_INSN || code == INSN)
2468 end_blk_2_insn = insn;
2475 /* It is possible for this optimization to slow performance if the blocks
2476 are long. This really depends upon whether the branch is likely taken
2477 or not. If the branch is taken, we slow performance in many cases. But,
2478 if the branch is not taken, we always help performance (for a single
2479 block, but for a double block (i.e. when the optimization is re-applied)
2480 this is not true since the 'right thing' depends on the overall length of
2481 the collapsed block). As a compromise, don't apply this optimization on
2482 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2483 the best threshold depends on the latencies of the instructions (i.e.,
2484 the branch penalty). */
2485 if (optimize > 1 && blk_size > 2)
2488 /* At this point, we've found the start of block 3 and we know that
2489 it is the destination of the branch from block 1. Also, all
2490 instructions in the block 2 are conditionalizable. So, apply the
2491 conditionalization and delete the branch. */
2492 start_blk_3_lab = insn;
2494 for (insn = NEXT_INSN (end_blk_1_br); insn != start_blk_3_lab;
2495 insn = NEXT_INSN (insn))
2499 if (INSN_DELETED_P (insn))
2502 /* Try to form a conditional variant of the instruction and emit it. */
2503 if ((newinsn = emit_new_cond_insn (insn, cond)))
2505 if (end_blk_2_insn == insn)
2506 end_blk_2_insn = newinsn;
2512 /* Note whether we will delete the label starting blk 3 when the jump
2513 gets deleted. If so, we want to re-apply this optimization at the
2514 last real instruction right before the label. */
2515 if (LABEL_NUSES (start_blk_3_lab) == 1)
2517 start_blk_3_lab = 0;
2520 /* ??? we probably should redistribute the death notes for this insn, esp.
2521 the death of cc, but it doesn't really matter this late in the game.
2522 The peepholes all use is_dead() which will find the correct death
2523 regardless of whether there is a note. */
2524 delete_insn (end_blk_1_br);
2526 if (! start_blk_3_lab)
2527 return end_blk_2_insn;
2529 /* Return the insn right after the label at the start of block 3. */
2530 return NEXT_INSN (start_blk_3_lab);
2533 /* Apply the conditionalization of blocks optimization. This is the
2534 outer loop that traverses through the insns scanning for a branch
2535 that signifies an opportunity to apply the optimization. Note that
2536 this optimization is applied late. If we could apply it earlier,
2537 say before cse 2, it may expose more optimization opportunities.
2538 but, the pay back probably isn't really worth the effort (we'd have
2539 to update all reg/flow/notes/links/etc to make it work - and stick it
2540 in before cse 2). */
2543 conditionalize_optimization (void)
2547 for (insn = get_insns (); insn; insn = conditionalize_block (insn))
2551 static int saved_warn_return_type = -1;
2552 static int saved_warn_return_type_count = 0;
2554 /* This is to handle loads from the constant pool. */
2559 /* Reset this variable. */
2560 current_function_anonymous_args = 0;
2562 /* Restore the warn_return_type if it has been altered. */
2563 if (saved_warn_return_type != -1)
2565 /* Only restore the value if we have reached another function.
2566 The test of warn_return_type occurs in final_function () in
2567 c-decl.c a long time after the code for the function is generated,
2568 so we need a counter to tell us when we have finished parsing that
2569 function and can restore the flag. */
2570 if (--saved_warn_return_type_count == 0)
2572 warn_return_type = saved_warn_return_type;
2573 saved_warn_return_type = -1;
2580 /* Conditionalize blocks where we can. */
2581 conditionalize_optimization ();
2583 /* Literal pool generation is now pushed off until the assembler. */
2587 /* Return true if X is something that can be moved directly into r15. */
2590 mcore_r15_operand_p (rtx x)
2592 switch (GET_CODE (x))
2595 return mcore_const_ok_for_inline (INTVAL (x));
2607 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2608 directly move X into it, use r1-r14 as a temporary. */
2611 mcore_secondary_reload_class (enum reg_class rclass,
2612 enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2614 if (TEST_HARD_REG_BIT (reg_class_contents[rclass], 15)
2615 && !mcore_r15_operand_p (x))
2620 /* Return the reg_class to use when reloading the rtx X into the class
2621 RCLASS. If X is too complex to move directly into r15, prefer to
2622 use LRW_REGS instead. */
2625 mcore_reload_class (rtx x, enum reg_class rclass)
2627 if (reg_class_subset_p (LRW_REGS, rclass) && !mcore_r15_operand_p (x))
2633 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2634 register. Note that the current version doesn't worry about whether
2635 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2636 in r2 matches an SImode in r2. Might think in the future about whether
2637 we want to be able to say something about modes. */
2640 mcore_is_same_reg (rtx x, rtx y)
2642 /* Strip any and all of the subreg wrappers. */
2643 while (GET_CODE (x) == SUBREG)
2646 while (GET_CODE (y) == SUBREG)
2649 if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
2656 mcore_override_options (void)
2658 /* Only the m340 supports little endian code. */
2659 if (TARGET_LITTLE_END && ! TARGET_M340)
2660 target_flags |= MASK_M340;
2663 /* Compute the number of word sized registers needed to
2664 hold a function argument of mode MODE and type TYPE. */
2667 mcore_num_arg_regs (enum machine_mode mode, const_tree type)
2671 if (targetm.calls.must_pass_in_stack (mode, type))
2674 if (type && mode == BLKmode)
2675 size = int_size_in_bytes (type);
2677 size = GET_MODE_SIZE (mode);
2679 return ROUND_ADVANCE (size);
2683 handle_structs_in_regs (enum machine_mode mode, const_tree type, int reg)
2687 /* The MCore ABI defines that a structure whose size is not a whole multiple
2688 of bytes is passed packed into registers (or spilled onto the stack if
2689 not enough registers are available) with the last few bytes of the
2690 structure being packed, left-justified, into the last register/stack slot.
2691 GCC handles this correctly if the last word is in a stack slot, but we
2692 have to generate a special, PARALLEL RTX if the last word is in an
2693 argument register. */
2695 && TYPE_MODE (type) == BLKmode
2696 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
2697 && (size = int_size_in_bytes (type)) > UNITS_PER_WORD
2698 && (size % UNITS_PER_WORD != 0)
2699 && (reg + mcore_num_arg_regs (mode, type) <= (FIRST_PARM_REG + NPARM_REGS)))
2701 rtx arg_regs [NPARM_REGS];
2706 for (nregs = 0; size > 0; size -= UNITS_PER_WORD)
2709 gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, reg ++),
2710 GEN_INT (nregs * UNITS_PER_WORD));
2714 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2715 assert (ARRAY_SIZE (arg_regs) == 6);
2716 rtvec = gen_rtvec (nregs, arg_regs[0], arg_regs[1], arg_regs[2],
2717 arg_regs[3], arg_regs[4], arg_regs[5]);
2719 result = gen_rtx_PARALLEL (mode, rtvec);
2723 return gen_rtx_REG (mode, reg);
2727 mcore_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
2729 enum machine_mode mode;
2732 mode = TYPE_MODE (valtype);
2734 mode = promote_mode (valtype, mode, &unsigned_p, 1);
2736 return handle_structs_in_regs (mode, valtype, FIRST_RET_REG);
2739 /* Define where to put the arguments to a function.
2740 Value is zero to push the argument on the stack,
2741 or a hard register in which to store the argument.
2743 MODE is the argument's machine mode.
2744 TYPE is the data type of the argument (as a tree).
2745 This is null for libcalls where that information may
2747 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2748 the preceding args and about the function being called.
2749 NAMED is nonzero if this argument is a named parameter
2750 (otherwise it is an extra parameter matching an ellipsis).
2752 On MCore the first args are normally in registers
2753 and the rest are pushed. Any arg that starts within the first
2754 NPARM_REGS words is at least partially passed in a register unless
2755 its data type forbids. */
2758 mcore_function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode,
2759 tree type, int named)
2763 if (! named || mode == VOIDmode)
2766 if (targetm.calls.must_pass_in_stack (mode, type))
2769 arg_reg = ROUND_REG (cum, mode);
2771 if (arg_reg < NPARM_REGS)
2772 return handle_structs_in_regs (mode, type, FIRST_PARM_REG + arg_reg);
2777 /* Returns the number of bytes of argument registers required to hold *part*
2778 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2779 the type is not known). If the argument fits entirely in the argument
2780 registers, or entirely on the stack, then 0 is returned. CUM is the
2781 number of argument registers already used by earlier parameters to
2785 mcore_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2786 tree type, bool named)
2788 int reg = ROUND_REG (*cum, mode);
2793 if (targetm.calls.must_pass_in_stack (mode, type))
2796 /* REG is not the *hardware* register number of the register that holds
2797 the argument, it is the *argument* register number. So for example,
2798 the first argument to a function goes in argument register 0, which
2799 translates (for the MCore) into hardware register 2. The second
2800 argument goes into argument register 1, which translates into hardware
2801 register 3, and so on. NPARM_REGS is the number of argument registers
2802 supported by the target, not the maximum hardware register number of
2804 if (reg >= NPARM_REGS)
2807 /* If the argument fits entirely in registers, return 0. */
2808 if (reg + mcore_num_arg_regs (mode, type) <= NPARM_REGS)
2811 /* The argument overflows the number of available argument registers.
2812 Compute how many argument registers have not yet been assigned to
2813 hold an argument. */
2814 reg = NPARM_REGS - reg;
2816 /* Return partially in registers and partially on the stack. */
2817 return reg * UNITS_PER_WORD;
2820 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2823 mcore_dllexport_name_p (const char * symbol)
2825 return symbol[0] == '@' && symbol[1] == 'e' && symbol[2] == '.';
2828 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2831 mcore_dllimport_name_p (const char * symbol)
2833 return symbol[0] == '@' && symbol[1] == 'i' && symbol[2] == '.';
2836 /* Mark a DECL as being dllexport'd. */
2839 mcore_mark_dllexport (tree decl)
2841 const char * oldname;
2846 rtlname = XEXP (DECL_RTL (decl), 0);
2848 if (GET_CODE (rtlname) == MEM)
2849 rtlname = XEXP (rtlname, 0);
2850 gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
2851 oldname = XSTR (rtlname, 0);
2853 if (mcore_dllexport_name_p (oldname))
2854 return; /* Already done. */
2856 newname = XALLOCAVEC (char, strlen (oldname) + 4);
2857 sprintf (newname, "@e.%s", oldname);
2859 /* We pass newname through get_identifier to ensure it has a unique
2860 address. RTL processing can sometimes peek inside the symbol ref
2861 and compare the string's addresses to see if two symbols are
2863 /* ??? At least I think that's why we do this. */
2864 idp = get_identifier (newname);
2866 XEXP (DECL_RTL (decl), 0) =
2867 gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
2870 /* Mark a DECL as being dllimport'd. */
2873 mcore_mark_dllimport (tree decl)
2875 const char * oldname;
2881 rtlname = XEXP (DECL_RTL (decl), 0);
2883 if (GET_CODE (rtlname) == MEM)
2884 rtlname = XEXP (rtlname, 0);
2885 gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
2886 oldname = XSTR (rtlname, 0);
2888 gcc_assert (!mcore_dllexport_name_p (oldname));
2889 if (mcore_dllimport_name_p (oldname))
2890 return; /* Already done. */
2892 /* ??? One can well ask why we're making these checks here,
2893 and that would be a good question. */
2895 /* Imported variables can't be initialized. */
2896 if (TREE_CODE (decl) == VAR_DECL
2897 && !DECL_VIRTUAL_P (decl)
2898 && DECL_INITIAL (decl))
2900 error ("initialized variable %q+D is marked dllimport", decl);
2904 /* `extern' needn't be specified with dllimport.
2905 Specify `extern' now and hope for the best. Sigh. */
2906 if (TREE_CODE (decl) == VAR_DECL
2907 /* ??? Is this test for vtables needed? */
2908 && !DECL_VIRTUAL_P (decl))
2910 DECL_EXTERNAL (decl) = 1;
2911 TREE_PUBLIC (decl) = 1;
2914 newname = XALLOCAVEC (char, strlen (oldname) + 11);
2915 sprintf (newname, "@i.__imp_%s", oldname);
2917 /* We pass newname through get_identifier to ensure it has a unique
2918 address. RTL processing can sometimes peek inside the symbol ref
2919 and compare the string's addresses to see if two symbols are
2921 /* ??? At least I think that's why we do this. */
2922 idp = get_identifier (newname);
2924 newrtl = gen_rtx_MEM (Pmode,
2925 gen_rtx_SYMBOL_REF (Pmode,
2926 IDENTIFIER_POINTER (idp)));
2927 XEXP (DECL_RTL (decl), 0) = newrtl;
2931 mcore_dllexport_p (tree decl)
2933 if ( TREE_CODE (decl) != VAR_DECL
2934 && TREE_CODE (decl) != FUNCTION_DECL)
2937 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)) != 0;
2941 mcore_dllimport_p (tree decl)
2943 if ( TREE_CODE (decl) != VAR_DECL
2944 && TREE_CODE (decl) != FUNCTION_DECL)
2947 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl)) != 0;
2950 /* We must mark dll symbols specially. Definitions of dllexport'd objects
2951 install some info in the .drective (PE) or .exports (ELF) sections. */
2954 mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIBUTE_UNUSED)
2956 /* Mark the decl so we can tell from the rtl whether the object is
2957 dllexport'd or dllimport'd. */
2958 if (mcore_dllexport_p (decl))
2959 mcore_mark_dllexport (decl);
2960 else if (mcore_dllimport_p (decl))
2961 mcore_mark_dllimport (decl);
2963 /* It might be that DECL has already been marked as dllimport, but
2964 a subsequent definition nullified that. The attribute is gone
2965 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
2966 else if ((TREE_CODE (decl) == FUNCTION_DECL
2967 || TREE_CODE (decl) == VAR_DECL)
2968 && DECL_RTL (decl) != NULL_RTX
2969 && GET_CODE (DECL_RTL (decl)) == MEM
2970 && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
2971 && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
2972 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
2974 const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
2975 tree idp = get_identifier (oldname + 9);
2976 rtx newrtl = gen_rtx_SYMBOL_REF (Pmode, IDENTIFIER_POINTER (idp));
2978 XEXP (DECL_RTL (decl), 0) = newrtl;
2980 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
2981 ??? We leave these alone for now. */
2985 /* Undo the effects of the above. */
2988 mcore_strip_name_encoding (const char * str)
2990 return str + (str[0] == '@' ? 3 : 0);
2993 /* MCore specific attribute support.
2994 dllexport - for exporting a function/variable that will live in a dll
2995 dllimport - for importing a function/variable from a dll
2996 naked - do not create a function prologue/epilogue. */
2998 const struct attribute_spec mcore_attribute_table[] =
3000 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3001 { "dllexport", 0, 0, true, false, false, NULL },
3002 { "dllimport", 0, 0, true, false, false, NULL },
3003 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute },
3004 { NULL, 0, 0, false, false, false, NULL }
3007 /* Handle a "naked" attribute; arguments as in
3008 struct attribute_spec.handler. */
3011 mcore_handle_naked_attribute (tree * node, tree name, tree args ATTRIBUTE_UNUSED,
3012 int flags ATTRIBUTE_UNUSED, bool * no_add_attrs)
3014 if (TREE_CODE (*node) == FUNCTION_DECL)
3016 /* PR14310 - don't complain about lack of return statement
3017 in naked functions. The solution here is a gross hack
3018 but this is the only way to solve the problem without
3019 adding a new feature to GCC. I did try submitting a patch
3020 that would add such a new feature, but it was (rightfully)
3021 rejected on the grounds that it was creeping featurism,
3022 so hence this code. */
3023 if (warn_return_type)
3025 saved_warn_return_type = warn_return_type;
3026 warn_return_type = 0;
3027 saved_warn_return_type_count = 2;
3029 else if (saved_warn_return_type_count)
3030 saved_warn_return_type_count = 2;
3034 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3035 IDENTIFIER_POINTER (name));
3036 *no_add_attrs = true;
3042 /* ??? It looks like this is PE specific? Oh well, this is what the
3043 old code did as well. */
3046 mcore_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
3051 const char * prefix;
3053 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
3055 /* Strip off any encoding in name. */
3056 name = (* targetm.strip_name_encoding) (name);
3058 /* The object is put in, for example, section .text$foo.
3059 The linker will then ultimately place them in .text
3060 (everything from the $ on is stripped). */
3061 if (TREE_CODE (decl) == FUNCTION_DECL)
3063 /* For compatibility with EPOC, we ignore the fact that the
3064 section might have relocs against it. */
3065 else if (decl_readonly_section (decl, 0))
3070 len = strlen (name) + strlen (prefix);
3071 string = XALLOCAVEC (char, len + 1);
3073 sprintf (string, "%s%s", prefix, name);
3075 DECL_SECTION_NAME (decl) = build_string (len, string);
3079 mcore_naked_function_p (void)
3081 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE;
3084 #ifdef OBJECT_FORMAT_ELF
3086 mcore_asm_named_section (const char *name,
3087 unsigned int flags ATTRIBUTE_UNUSED,
3088 tree decl ATTRIBUTE_UNUSED)
3090 fprintf (asm_out_file, "\t.section %s\n", name);
3092 #endif /* OBJECT_FORMAT_ELF */
3094 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3097 mcore_external_libcall (rtx fun)
3099 fprintf (asm_out_file, "\t.import\t");
3100 assemble_name (asm_out_file, XSTR (fun, 0));
3101 fprintf (asm_out_file, "\n");
3104 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3107 mcore_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
3109 const HOST_WIDE_INT size = int_size_in_bytes (type);
3110 return (size == -1 || size > 2 * UNITS_PER_WORD);