1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_5200 flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
50 ;;- 'x' if one of the Sun FPA registers
51 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
53 ;;- Immediate Floating point operator constraints
54 ;;- 'G' a floating point constant that is *NOT* one of the standard
55 ;; 68881 constant values (to force calling output_move_const_double
56 ;; to get it from rom if it is a 68881 constant).
57 ;;- 'H' one of the standard FPA constant values
59 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
62 ;;- Immediate integer operand constraints:
64 ;;- 'J' -32768 .. 32767
65 ;;- 'K' all integers EXCEPT -128 .. 127
67 ;;- 'M' all integers EXCEPT -256 .. 255
73 ;;- "%." size separator ("." or "") move%.l d0,d1
74 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
75 ;;- "%-" push operand "sp@-" move%.l d0,%-
76 ;;- "%+" pop operand "sp@+" move%.l d0,%+
77 ;;- "%@" top of stack "sp@" move%.l d0,%@
78 ;;- "%!" fpcr register
79 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
80 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
83 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
84 ;; operand 1 is the argument for `sin'.
85 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
86 ;; operand 1 is the argument for `cos'.
88 ;;- Information about 68040 port.
90 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
91 ;;- be emulated in software by the OS. It is faster to avoid these
92 ;;- instructions and issue a library call rather than trapping into
93 ;;- the kernel. The affected instructions are fintrz and fscale. The
94 ;;- TARGET_68040 flag turns the use of the opcodes off.
96 ;;- The '040 also implements a set of new floating-point instructions
97 ;;- which specify the rounding precision in the opcode. This finally
98 ;;- permit the 68k series to be truly IEEE compliant, and solves all
99 ;;- issues of excess precision accumulating in the extended registers.
100 ;;- By default, GCC does not use these instructions, since such code will
101 ;;- not run on an '030. To use these instructions, use the -m68040-only
102 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
103 ;;- you can make these instructions the default.
105 ;;- These new instructions aren't directly in the md. They are brought
106 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
109 ;;- Information about 68060 port.
111 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
112 ;;- be emulated in software by the OS. It is faster to avoid these
113 ;;- instructions and issue a library call rather than trapping into
114 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
115 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
116 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
118 ;;- FPA port explanation:
120 ;;- Usage of the Sun FPA and the 68881 together
122 ;;- The current port of gcc to the sun fpa disallows use of the m68881
123 ;;- instructions completely if code is targeted for the fpa. This is
124 ;;- for the following reasons:
126 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
127 ;;- can, the 68881 otherwise, and data registers only if you are
128 ;;- forced to it) is a bitch with the current constraint scheme,
129 ;;- especially since it would have to work for any combination of
132 ;;- 2) There are no instructions to move between the two types of
133 ;;- registers; the stack must be used as an intermediary.
135 ;;- It could indeed be done; I think the best way would be to have
136 ;;- separate patterns for TARGET_FPA (which implies a 68881),
137 ;;- TARGET_68881, and no floating point co-processor. Use
138 ;;- define_expands for all of the named instruction patterns, and
139 ;;- include code in the FPA instruction to deal with the 68881 with
140 ;;- preferences specifically set to favor the fpa. Some of this has
141 ;;- already been done:
143 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
144 ;;- case and a TARGET_68881 case (the exceptions are the patterns
145 ;;- which would need one define_expand and three define_insn's under
146 ;;- it (with a lot of duplicate code between them) to replace the
147 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
148 ;;- first two patterns in the md.
150 ;;- Some would still have to be done:
152 ;;- 1) Add code to the fpa patterns which correspond to 68881
153 ;;- patterns to deal with the 68881 case (including preferences!).
154 ;;- What you might actually do here is combine the fpa and 68881 code
155 ;;- back together into one pattern for those instructions where it's
156 ;;- absolutely necessary and save yourself some duplicate code. I'm
157 ;;- not completely sure as to whether you could get away with doing
158 ;;- this only for the mov* insns, or if you'd have to do it for all
160 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
161 ;;- moving between fpa regs and 68881 regs.
163 ;;- Since the fpa is more powerful than the 68881 and also has more
164 ;;- registers, and since I think the resultant md would be medium ugly
165 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
166 ;;- to do this change.
168 ;;- Another reason why someone *might* want to do the change is to
169 ;;- control which register classes are accessed in a slightly cleaner
170 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
171 ;;- the internals manual.
173 ;;- Yet another reason why someone might want to do this change is to
174 ;;- allow use of some of the 68881 insns which have no equivalent on
175 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
177 ;;- If this is ever done, don't forget to change sun3.h so that
178 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
180 ;;- Condition code hack
182 ;;- When a floating point compare is done in the fpa, the resulting
183 ;;- condition codes are left in the fpastatus register. The values in
184 ;;- this register must be moved into the 68000 cc register before any
185 ;;- jump is executed. Once this has been done, regular jump
186 ;;- instructions are fine (ie. floating point jumps are not necessary.
187 ;;- They are only done if the cc is in the 68881).
189 ;;- The instructions that move the fpastatus register to the 68000
190 ;;- register clobber a data register (the move cannot be done direct).
191 ;;- These instructions might be bundled either with the compare
192 ;;- instruction, or the branch instruction. If we were using both the
193 ;;- fpa and the 68881 together, we would wish to only mark the
194 ;;- register clobbered if we were doing the compare in the fpa, but I
195 ;;- think that that decision (whether to clobber the register or not)
196 ;;- must be done before register allocation (makes sense) and hence we
197 ;;- can't know if the floating point compare will be done in the fpa
198 ;;- or the fp. So whenever we are asked for code that uses the fpa,
199 ;;- we will mark a data register as clobbered. This is reasonable, as
200 ;;- almost all floating point compare operations done with fpa code
201 ;;- enabled will be done in the fpa. It's even more reasonable since
202 ;;- we decided to make the 68881 and the fpa mutually exclusive.
204 ;;- We place to code to move the fpastatus register inside of a
205 ;;- define_expand so that we can do it conditionally based on whether
206 ;;- we are targeting an fpa or not.
208 ;;- This still leaves us with the question of where we wish to put the
209 ;;- code to move the fpastatus reg. If we put it in the compare
210 ;;- instruction, we can restrict the clobbering of the register to
211 ;;- floating point compares, but we can't take advantage of floating
212 ;;- point subtracts & etc. that alter the fpastatus register. If we
213 ;;- put it in the branch instruction, all branches compiled with fpa
214 ;;- code enabled will clobber a data register, but we will be able to
215 ;;- take advantage of fpa subtracts. This balance favors putting the
216 ;;- code in with the compare instruction.
218 ;;- Note that if some enterprising hacker should decide to switch
219 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
221 ;;- Usage of the top 16 fpa registers
223 ;;- The only locations which we may transfer fpa registers 16-31 from
224 ;;- or to are the fpa registers 0-15. (68000 registers and memory
225 ;;- locations are impossible). This causes problems in gcc, which
226 ;;- assumes that mov?? instructions require no additional registers
227 ;;- (see section 11.7) and since floating point moves *must* be
228 ;;- supported into general registers (see section 12.3 under
229 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
231 ;;- My solution was to reserve fpa0 for moves into or out of these top
232 ;;- 16 registers and to disparage the choice to reload into or out of
233 ;;- these registers as much as I could. That alternative is always
234 ;;- last in the list, so it will not be used unless all else fails. I
235 ;;- will note that according to my current information, sun's compiler
236 ;;- doesn't use these top 16 registers at all.
238 ;;- There is another possible way to do it. I *believe* that if you
239 ;;- make absolutely sure that the code will not be executed in the
240 ;;- reload pass, you can support the mov?? names with define_expands
241 ;;- which require new registers. This may be possible by the
242 ;;- appropriate juggling of constraints. I may come back to this later.
244 ;;- Usage of constant RAM
246 ;;- This has been handled correctly (I believe) but the way I've done
247 ;;- it could use a little explanation. The constant RAM can only be
248 ;;- accessed when the instruction is in "command register" mode.
249 ;;- "command register" mode means that no accessing of memory or the
250 ;;- 68000 registers is being done. This can be expressed easily in
251 ;;- constraints, so generally the mode of the instruction is
252 ;;- determined by a branch off of which_alternative. In outputting
253 ;;- instructions, a 'w' means to output an access to the constant ram
254 ;;- (if the arg is CONST_DOUBLE and is one of the available
255 ;;- constants), and 'x' means to output a register pair (if the arg is
256 ;;- a 68000 register) and a 'y' is the combination of the above two
257 ;;- processes. You use a 'y' in two operand DF instructions where you
258 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
259 ;;- instructions where the arg might be a 68000 register and the
260 ;;- instruction is *not* in "command register" mode, and you use a 'w'
261 ;;- in two situations: 1) The instruction *is* in command register
262 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
263 ;;- instruction is a two operand SF instruction where you know the
264 ;;- other operand is an fpa register.
266 ;;- Optimization issues
268 ;;- I actually think that I've included all of the fpa instructions
269 ;;- that should be included. Note that if someone is interested in
270 ;;- doing serious floating point work on the sun fpa, I would advise
271 ;;- the use of the "asm" instruction in gcc to allow you to use the
272 ;;- sin, cos, and exponential functions on the fpa board.
274 ;;- END FPA Explanation Section.
277 ;;- Some of these insn's are composites of several m68000 op codes.
278 ;;- The assembler (or final @@??) insures that the appropriate one is
282 [(set (match_operand:DF 0 "push_operand" "=m")
283 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
287 if (FP_REG_P (operands[1]))
288 return \"fmove%.d %f1,%0\";
289 if (FPA_REG_P (operands[1]))
290 return \"fpmove%.d %1, %x0\";
291 return output_move_double (operands);
294 (define_insn "pushdi"
295 [(set (match_operand:DI 0 "push_operand" "=m")
296 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
300 return output_move_double (operands);
303 ;; We don't want to allow a constant operand for test insns because
304 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
305 ;; be folded while optimizing anyway.
307 (define_expand "tstdi"
308 [(parallel [(set (cc0)
309 (match_operand:DI 0 "nonimmediate_operand" ""))
310 (clobber (match_scratch:SI 1 ""))
311 (clobber (match_scratch:DI 2 ""))])]
313 "m68k_last_compare_had_fp_operands = 0;")
317 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
318 (clobber (match_scratch:SI 1 "=X,d"))
319 (clobber (match_scratch:DI 2 "=d,X"))]
323 if (which_alternative == 0)
327 xoperands[0] = operands[2];
328 xoperands[1] = operands[0];
329 output_move_double (xoperands);
330 cc_status.flags |= CC_REVERSED;
331 return \"neg%.l %R2\;negx%.l %2\";
333 if (find_reg_note (insn, REG_DEAD, operands[0]))
335 cc_status.flags |= CC_REVERSED;
336 return \"neg%.l %R0\;negx%.l %0\";
340 ** 'sub' clears %1, and also clears the X cc bit
341 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
342 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
344 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
347 (define_expand "tstsi"
349 (match_operand:SI 0 "nonimmediate_operand" ""))]
351 "m68k_last_compare_had_fp_operands = 0;")
355 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
360 /* ISI's assembler fails to handle tstl a0. */
361 if (! ADDRESS_REG_P (operands[0]))
363 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
365 return \"tst%.l %0\";
366 /* If you think that the 68020 does not support tstl a0,
367 reread page B-167 of the 68020 manual more carefully. */
368 /* On an address reg, cmpw may replace cmpl. */
370 return \"cmp%.w %0,%#0\";
372 return \"cmp%.w %#0,%0\";
376 ;; This can't use an address register, because comparisons
377 ;; with address registers as second operand always test the whole word.
378 (define_expand "tsthi"
380 (match_operand:HI 0 "nonimmediate_operand" ""))]
382 "m68k_last_compare_had_fp_operands = 0;")
386 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
390 (define_expand "tstqi"
392 (match_operand:QI 0 "nonimmediate_operand" ""))]
394 "m68k_last_compare_had_fp_operands = 0;")
398 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
402 (define_expand "tstsf"
404 (match_operand:SF 0 "general_operand" ""))]
405 "TARGET_68881 || TARGET_FPA"
408 m68k_last_compare_had_fp_operands = 1;
411 emit_insn (gen_tstsf_fpa (operands[0]));
416 (define_insn "tstsf_fpa"
418 (match_operand:SF 0 "general_operand" "xmdF"))
419 (clobber (match_scratch:SI 1 "=d"))]
421 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
425 (match_operand:SF 0 "general_operand" "fdm"))]
429 cc_status.flags = CC_IN_68881;
430 if (FP_REG_P (operands[0]))
431 return \"ftst%.x %0\";
432 return \"ftst%.s %0\";
435 (define_expand "tstdf"
437 (match_operand:DF 0 "general_operand" ""))]
438 "TARGET_68881 || TARGET_FPA"
441 m68k_last_compare_had_fp_operands = 1;
444 emit_insn (gen_tstsf_fpa (operands[0]));
449 (define_insn "tstdf_fpa"
451 (match_operand:DF 0 "general_operand" "xrmF"))
452 (clobber (match_scratch:SI 1 "=d"))]
454 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
458 (match_operand:DF 0 "general_operand" "fm"))]
462 cc_status.flags = CC_IN_68881;
463 if (FP_REG_P (operands[0]))
464 return \"ftst%.x %0\";
465 return \"ftst%.d %0\";
468 ;; compare instructions.
470 (define_expand "cmpdi"
473 (compare (match_operand:DI 0 "nonimmediate_operand" "")
474 (match_operand:DI 1 "general_operand" "")))
475 (clobber (match_dup 2))])]
477 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
481 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
482 (match_operand:DI 2 "general_operand" "d,0")))
483 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
487 if (rtx_equal_p (operands[0], operands[1]))
488 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
491 cc_status.flags |= CC_REVERSED;
492 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
496 ;; This is the second "hook" for PIC code (in addition to movsi). See
497 ;; comment of movsi for a description of PIC handling.
498 (define_expand "cmpsi"
500 (compare (match_operand:SI 0 "nonimmediate_operand" "")
501 (match_operand:SI 1 "general_operand" "")))]
505 m68k_last_compare_had_fp_operands = 0;
506 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
508 /* The source is an address which requires PIC relocation.
509 Call legitimize_pic_address with the source, mode, and a relocation
510 register (a new pseudo, or the final destination if reload_in_progress
511 is set). Then fall through normally */
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
521 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
584 (match_operand:HI 1 "general_src_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
591 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
620 (match_operand:QI 1 "general_src_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
627 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adj_offsettable_operand (operands[0],
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adj_offsettable_operand (operands[0],
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "general_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "general_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "general_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
958 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
960 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
962 /* Don't allow writes to memory except via a register;
963 the m68k doesn't consider PC-relative addresses to be writable. */
964 if (symbolic_operand (operands[0], SImode))
965 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
966 else if (GET_CODE (operands[0]) == MEM
967 && symbolic_operand (XEXP (operands[0], 0), SImode))
968 operands[0] = gen_rtx (MEM, SImode,
969 force_reg (SImode, XEXP (operands[0], 0)));
973 ;; General case of fullword move. The register constraints
974 ;; force integer constants in range for a moveq to be reloaded
975 ;; if they are headed for memory.
977 ;; Notes: make sure no alternative allows g vs g.
978 ;; We don't allow f-regs since fixed point cannot go in them.
979 ;; We do allow y and x regs since fixed point is allowed in them.
980 [(set (match_operand:SI 0 "general_operand" "=g,d,a<,y,!*x*r*m")
981 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
986 if (which_alternative == 4)
987 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
988 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
989 return \"fpmove%.l %x1,%x0\";
990 return output_move_simode (operands);
994 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
995 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_simode (operands);")
999 ;; Special case of fullword move, where we need to get a non-GOT PIC
1000 ;; reference into an address register.
1002 [(set (match_operand:SI 0 "general_operand" "=a<")
1003 (match_operand:SI 1 "pcrel_address" ""))]
1007 if (push_operand (operands[0], SImode))
1009 return \"lea %a1,%0\";
1012 (define_expand "movhi"
1013 [(set (match_operand:HI 0 "general_operand" "")
1014 (match_operand:HI 1 "general_operand" ""))]
1019 [(set (match_operand:HI 0 "general_operand" "=g")
1020 (match_operand:HI 1 "general_src_operand" "gS"))]
1022 "* return output_move_himode (operands);")
1025 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
1026 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1028 "* return output_move_himode (operands);")
1030 (define_expand "movstricthi"
1031 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1032 (match_operand:HI 1 "general_src_operand" ""))]
1037 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1038 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1040 "* return output_move_stricthi (operands);")
1043 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1044 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1046 "* return output_move_stricthi (operands);")
1048 (define_expand "movqi"
1049 [(set (match_operand:QI 0 "general_operand" "")
1050 (match_operand:QI 1 "general_src_operand" ""))]
1055 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1056 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1058 "* return output_move_qimode (operands);")
1061 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1062 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
1064 "* return output_move_qimode (operands);")
1066 (define_expand "movstrictqi"
1067 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1068 (match_operand:QI 1 "general_src_operand" ""))]
1073 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1074 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1076 "* return output_move_strictqi (operands);")
1079 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1080 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
1082 "* return output_move_strictqi (operands);")
1084 (define_expand "movsf"
1085 [(set (match_operand:SF 0 "general_operand" "")
1086 (match_operand:SF 1 "general_operand" ""))]
1091 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1092 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1093 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1094 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1098 if (which_alternative >= 4)
1099 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1100 if (FPA_REG_P (operands[0]))
1102 if (FPA_REG_P (operands[1]))
1103 return \"fpmove%.s %x1,%x0\";
1104 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1105 return output_move_const_single (operands);
1106 else if (FP_REG_P (operands[1]))
1107 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1108 return \"fpmove%.s %x1,%x0\";
1110 if (FPA_REG_P (operands[1]))
1112 if (FP_REG_P (operands[0]))
1113 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1115 return \"fpmove%.s %x1,%x0\";
1117 if (FP_REG_P (operands[0]))
1119 if (FP_REG_P (operands[1]))
1120 return \"f%$move%.x %1,%0\";
1121 else if (ADDRESS_REG_P (operands[1]))
1122 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1123 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1124 return output_move_const_single (operands);
1125 return \"f%$move%.s %f1,%0\";
1127 if (FP_REG_P (operands[1]))
1129 if (ADDRESS_REG_P (operands[0]))
1130 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1131 return \"fmove%.s %f1,%0\";
1133 if (operands[1] == CONST0_RTX (SFmode)
1134 /* clr insns on 68000 read before writing.
1135 This isn't so on the 68010, but we have no TARGET_68010. */
1136 && ((TARGET_68020 || TARGET_5200)
1137 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1139 if (ADDRESS_REG_P (operands[0]))
1141 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1142 if (!TARGET_68040 && !TARGET_68060)
1143 return \"sub%.l %0,%0\";
1148 /* Many SGS assemblers croak on size specifiers for constants. */
1149 return \"lea 0,%0\";
1151 return \"lea 0.w,%0\";
1154 return \"lea 0:w,%0\";
1158 /* moveq is faster on the 68000. */
1159 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1161 #if defined(MOTOROLA) && !defined(CRDS)
1162 return \"moveq%.l %#0,%0\";
1164 return \"moveq %#0,%0\";
1167 return \"clr%.l %0\";
1169 return \"move%.l %1,%0\";
1173 [(set (match_operand:SF 0 "general_operand" "=r,g")
1174 (match_operand:SF 1 "general_operand" "g,r"))]
1176 "* return \"move%.l %1,%0\";")
1178 (define_expand "movdf"
1179 [(set (match_operand:DF 0 "general_operand" "")
1180 (match_operand:DF 1 "general_operand" ""))]
1185 [(set (match_operand:DF 0 "general_operand"
1186 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1187 (match_operand:DF 1 "general_operand"
1188 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1189 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1190 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1194 if (which_alternative == 7)
1195 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1196 if (FPA_REG_P (operands[0]))
1198 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1199 return output_move_const_double (operands);
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1202 return \"fpmove%.d %x1,%x0\";
1204 else if (FPA_REG_P (operands[1]))
1206 if (FP_REG_P(operands[0]))
1207 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1209 return \"fpmove%.d %x1,%x0\";
1211 if (FP_REG_P (operands[0]))
1213 if (FP_REG_P (operands[1]))
1214 return \"f%&move%.x %1,%0\";
1215 if (REG_P (operands[1]))
1218 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1219 output_asm_insn (\"move%.l %1,%-\", xoperands);
1220 output_asm_insn (\"move%.l %1,%-\", operands);
1221 return \"f%&move%.d %+,%0\";
1223 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1224 return output_move_const_double (operands);
1225 return \"f%&move%.d %f1,%0\";
1227 else if (FP_REG_P (operands[1]))
1229 if (REG_P (operands[0]))
1231 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1232 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1233 return \"move%.l %+,%0\";
1236 return \"fmove%.d %f1,%0\";
1238 return output_move_double (operands);
1242 [(set (match_operand:DF 0 "general_operand" "=r,g")
1243 (match_operand:DF 1 "general_operand" "g,r"))]
1245 "* return output_move_double (operands);")
1247 (define_expand "movxf"
1248 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1249 (match_operand:XF 1 "general_operand" ""))]
1253 if (CONSTANT_P (operands[1]))
1255 operands[1] = force_const_mem (XFmode, operands[1]);
1256 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1257 && ! reload_in_progress)
1258 operands[1] = adjust_address (operands[1], XFmode, 0);
1260 if (flag_pic && TARGET_PCREL && ! reload_in_progress)
1262 /* Don't allow writes to memory except via a register;
1263 the m68k doesn't consider PC-relative addresses to be writable. */
1264 if (GET_CODE (operands[0]) == MEM
1265 && symbolic_operand (XEXP (operands[0], 0), SImode))
1266 operands[0] = gen_rtx (MEM, XFmode,
1267 force_reg (SImode, XEXP (operands[0], 0)));
1272 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1273 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1277 if (FP_REG_P (operands[0]))
1279 if (FP_REG_P (operands[1]))
1280 return \"fmove%.x %1,%0\";
1281 if (REG_P (operands[1]))
1284 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1285 output_asm_insn (\"move%.l %1,%-\", xoperands);
1286 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1287 output_asm_insn (\"move%.l %1,%-\", xoperands);
1288 output_asm_insn (\"move%.l %1,%-\", operands);
1289 return \"fmove%.x %+,%0\";
1291 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1292 return \"fmove%.x %1,%0\";
1293 return \"fmove%.x %f1,%0\";
1295 if (FP_REG_P (operands[1]))
1297 if (REG_P (operands[0]))
1299 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1300 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1301 output_asm_insn (\"move%.l %+,%0\", operands);
1302 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1303 return \"move%.l %+,%0\";
1305 /* Must be memory destination. */
1306 return \"fmove%.x %f1,%0\";
1308 return output_move_double (operands);
1313 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1314 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1315 "! TARGET_68881 && ! TARGET_5200"
1318 if (FP_REG_P (operands[0]))
1320 if (FP_REG_P (operands[1]))
1321 return \"fmove%.x %1,%0\";
1322 if (REG_P (operands[1]))
1325 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1326 output_asm_insn (\"move%.l %1,%-\", xoperands);
1327 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1328 output_asm_insn (\"move%.l %1,%-\", xoperands);
1329 output_asm_insn (\"move%.l %1,%-\", operands);
1330 return \"fmove%.x %+,%0\";
1332 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1333 return \"fmove%.x %1,%0\";
1334 return \"fmove%.x %f1,%0\";
1336 if (FP_REG_P (operands[1]))
1338 if (REG_P (operands[0]))
1340 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1341 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1342 output_asm_insn (\"move%.l %+,%0\", operands);
1343 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1344 return \"move%.l %+,%0\";
1347 return \"fmove%.x %f1,%0\";
1349 return output_move_double (operands);
1354 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1355 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1356 "! TARGET_68881 && TARGET_5200"
1357 "* return output_move_double (operands);")
1359 (define_expand "movdi"
1360 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1361 [(set (match_operand:DI 0 "general_operand" "")
1362 (match_operand:DI 1 "general_operand" ""))]
1366 ;; movdi can apply to fp regs in some cases
1368 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1369 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1370 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1371 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1372 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1373 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1374 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1378 if (which_alternative == 8)
1379 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1380 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1381 return \"fpmove%.d %x1,%x0\";
1382 if (FP_REG_P (operands[0]))
1384 if (FP_REG_P (operands[1]))
1385 return \"fmove%.x %1,%0\";
1386 if (REG_P (operands[1]))
1389 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1390 output_asm_insn (\"move%.l %1,%-\", xoperands);
1391 output_asm_insn (\"move%.l %1,%-\", operands);
1392 return \"fmove%.d %+,%0\";
1394 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1395 return output_move_const_double (operands);
1396 return \"fmove%.d %f1,%0\";
1398 else if (FP_REG_P (operands[1]))
1400 if (REG_P (operands[0]))
1402 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1403 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1404 return \"move%.l %+,%0\";
1407 return \"fmove%.d %f1,%0\";
1409 return output_move_double (operands);
1413 [(set (match_operand:DI 0 "general_operand" "=r,g")
1414 (match_operand:DI 1 "general_operand" "g,r"))]
1416 "* return output_move_double (operands);")
1418 ;; Thus goes after the move instructions
1419 ;; because the move instructions are better (require no spilling)
1420 ;; when they can apply. It goes before the add/sub insns
1421 ;; so we will prefer it to them.
1423 (define_insn "pushasi"
1424 [(set (match_operand:SI 0 "push_operand" "=m")
1425 (match_operand:SI 1 "address_operand" "p"))]
1429 ;; truncation instructions
1430 (define_insn "truncsiqi2"
1431 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1433 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1437 if (GET_CODE (operands[0]) == REG)
1439 /* Must clear condition codes, since the move.l bases them on
1440 the entire 32 bits, not just the desired 8 bits. */
1442 return \"move%.l %1,%0\";
1444 if (GET_CODE (operands[1]) == MEM)
1445 operands[1] = adj_offsettable_operand (operands[1], 3);
1446 return \"move%.b %1,%0\";
1449 (define_insn "trunchiqi2"
1450 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1452 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1456 if (GET_CODE (operands[0]) == REG
1457 && (GET_CODE (operands[1]) == MEM
1458 || GET_CODE (operands[1]) == CONST_INT))
1460 /* Must clear condition codes, since the move.w bases them on
1461 the entire 16 bits, not just the desired 8 bits. */
1463 return \"move%.w %1,%0\";
1465 if (GET_CODE (operands[0]) == REG)
1467 /* Must clear condition codes, since the move.l bases them on
1468 the entire 32 bits, not just the desired 8 bits. */
1470 return \"move%.l %1,%0\";
1472 if (GET_CODE (operands[1]) == MEM)
1473 operands[1] = adj_offsettable_operand (operands[1], 1);
1474 return \"move%.b %1,%0\";
1477 (define_insn "truncsihi2"
1478 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1480 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1484 if (GET_CODE (operands[0]) == REG)
1486 /* Must clear condition codes, since the move.l bases them on
1487 the entire 32 bits, not just the desired 8 bits. */
1489 return \"move%.l %1,%0\";
1491 if (GET_CODE (operands[1]) == MEM)
1492 operands[1] = adj_offsettable_operand (operands[1], 2);
1493 return \"move%.w %1,%0\";
1496 ;; zero extension instructions
1498 (define_insn "zero_extendqidi2"
1499 [(set (match_operand:DI 0 "general_operand" "=&d")
1500 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1505 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1506 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1509 (define_insn "zero_extendhidi2"
1510 [(set (match_operand:DI 0 "general_operand" "=&d")
1511 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1516 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1517 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1520 ;; this is the canonical form for (lshiftrt:DI x 32)
1521 (define_insn "zero_extendsidi2"
1522 [(set (match_operand:DI 0 "general_operand" "=rm")
1523 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1528 if (GET_CODE (operands[0]) == REG)
1529 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1530 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1531 return \"move%.l %1,%0\;clr%.l %0\";
1532 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1533 return \"clr%.l %0\;move%.l %1,%0\";
1535 operands[2] = adj_offsettable_operand (operands[0], 4);
1536 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1537 || REGNO (operands[1]) != REGNO (operands[2]))
1538 output_asm_insn (\"move%.l %1,%2\", operands);
1539 if (ADDRESS_REG_P (operands[0]))
1540 return \"sub%.l %0,%0\";
1542 return \"clr%.l %0\";
1545 (define_expand "zero_extendhisi2"
1546 [(set (match_operand:SI 0 "register_operand" "")
1548 (set (strict_low_part (match_dup 2))
1549 (match_operand:HI 1 "general_operand" ""))]
1553 operands[1] = make_safe_from (operands[1], operands[0]);
1554 if (GET_CODE (operands[0]) == SUBREG)
1555 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1556 SUBREG_BYTE (operands[0]));
1558 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1561 (define_expand "zero_extendqihi2"
1562 [(set (match_operand:HI 0 "register_operand" "")
1564 (set (strict_low_part (match_dup 2))
1565 (match_operand:QI 1 "general_operand" ""))]
1569 operands[1] = make_safe_from (operands[1], operands[0]);
1570 if (GET_CODE (operands[0]) == SUBREG)
1571 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1572 SUBREG_BYTE (operands[0]));
1574 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1577 (define_expand "zero_extendqisi2"
1578 [(set (match_operand:SI 0 "register_operand" "")
1580 (set (strict_low_part (match_dup 2))
1581 (match_operand:QI 1 "general_operand" ""))]
1585 operands[1] = make_safe_from (operands[1], operands[0]);
1586 if (GET_CODE (operands[0]) == SUBREG)
1587 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1588 SUBREG_BYTE (operands[0]));
1590 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1593 ;; Patterns to recognize zero-extend insns produced by the combiner.
1594 ;; We don't allow both operands in memory, because of aliasing problems.
1595 ;; Explicitly disallow two memory operands via the condition since reloading
1596 ;; of this case will result in worse code than the uncombined patterns.
1599 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1600 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1601 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1604 if (DATA_REG_P (operands[0]))
1606 if (GET_CODE (operands[1]) == REG
1607 && REGNO (operands[0]) == REGNO (operands[1]))
1608 return \"and%.l %#0xFFFF,%0\";
1609 if (reg_mentioned_p (operands[0], operands[1]))
1610 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1611 return \"clr%.l %0\;move%.w %1,%0\";
1613 else if (GET_CODE (operands[0]) == MEM
1614 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1615 return \"move%.w %1,%0\;clr%.w %0\";
1616 else if (GET_CODE (operands[0]) == MEM
1617 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1618 return \"clr%.w %0\;move%.w %1,%0\";
1621 output_asm_insn (\"clr%.w %0\", operands);
1622 operands[0] = adj_offsettable_operand (operands[0], 2);
1623 return \"move%.w %1,%0\";
1628 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1629 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1630 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1633 if (DATA_REG_P (operands[0]))
1635 if (GET_CODE (operands[1]) == REG
1636 && REGNO (operands[0]) == REGNO (operands[1]))
1637 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1638 if (reg_mentioned_p (operands[0], operands[1]))
1639 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1640 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1641 return \"clr%.w %0\;move%.b %1,%0\";
1643 else if (GET_CODE (operands[0]) == MEM
1644 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1646 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1647 == STACK_POINTER_REGNUM)
1649 output_asm_insn (\"clr%.w %-\", operands);
1650 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1651 plus_constant (stack_pointer_rtx, 1));
1652 return \"move%.b %1,%0\";
1655 return \"move%.b %1,%0\;clr%.b %0\";
1657 else if (GET_CODE (operands[0]) == MEM
1658 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1659 return \"clr%.b %0\;move%.b %1,%0\";
1662 output_asm_insn (\"clr%.b %0\", operands);
1663 operands[0] = adj_offsettable_operand (operands[0], 1);
1664 return \"move%.b %1,%0\";
1669 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1670 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1671 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1674 if (DATA_REG_P (operands[0]))
1676 if (GET_CODE (operands[1]) == REG
1677 && REGNO (operands[0]) == REGNO (operands[1]))
1678 return \"and%.l %#0xFF,%0\";
1679 if (reg_mentioned_p (operands[0], operands[1]))
1680 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1681 return \"clr%.l %0\;move%.b %1,%0\";
1683 else if (GET_CODE (operands[0]) == MEM
1684 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1686 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1689 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1691 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1694 return \"clrl %0@-\;moveb %1,%0@(3)\";
1697 else if (GET_CODE (operands[0]) == MEM
1698 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1700 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1703 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1705 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1708 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1713 output_asm_insn (\"clr%.l %0\", operands);
1714 operands[0] = adj_offsettable_operand (operands[0], 3);
1715 return \"move%.b %1,%0\";
1719 ;; sign extension instructions
1721 (define_insn "extendqidi2"
1722 [(set (match_operand:DI 0 "general_operand" "=d")
1723 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1728 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1729 if (TARGET_68020 || TARGET_5200)
1730 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1732 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1735 (define_insn "extendhidi2"
1736 [(set (match_operand:DI 0 "general_operand" "=d")
1738 (match_operand:HI 1 "general_src_operand" "rmS")))]
1743 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1744 if (TARGET_68020 || TARGET_5200)
1745 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1747 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1750 (define_insn "extendsidi2"
1751 [(set (match_operand:DI 0 "general_operand" "=d")
1753 (match_operand:SI 1 "general_operand" "rm")))]
1758 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1759 if (TARGET_68020 || TARGET_5200)
1760 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1762 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1765 ;; Special case when one can avoid register clobbering, copy and test
1766 ;; Maybe there is a way to make that the general case, by forcing the
1767 ;; result of the SI tree to be in the lower register of the DI target
1769 (define_insn "extendplussidi"
1770 [(set (match_operand:DI 0 "register_operand" "=d")
1771 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1772 (match_operand:SI 2 "general_operand" "rmn"))))]
1777 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1778 if (GET_CODE (operands[1]) == CONST_INT
1779 && (unsigned) INTVAL (operands[1]) > 8)
1781 rtx tmp = operands[1];
1783 operands[1] = operands[2];
1786 if (GET_CODE (operands[1]) == REG
1787 && REGNO (operands[1]) == REGNO (operands[3]))
1788 output_asm_insn (\"add%.l %2,%3\", operands);
1790 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1791 if (TARGET_68020 || TARGET_5200)
1792 return \"smi %0\;extb%.l %0\";
1794 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1797 (define_insn "extendhisi2"
1798 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1800 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1804 if (ADDRESS_REG_P (operands[0]))
1805 return \"move%.w %1,%0\";
1806 return \"ext%.l %0\";
1809 (define_insn "extendqihi2"
1810 [(set (match_operand:HI 0 "general_operand" "=d")
1811 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1815 (define_insn "extendqisi2"
1816 [(set (match_operand:SI 0 "general_operand" "=d")
1817 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1818 "TARGET_68020 || TARGET_5200"
1821 ;; Conversions between float and double.
1823 (define_expand "extendsfdf2"
1824 [(set (match_operand:DF 0 "general_operand" "")
1826 (match_operand:SF 1 "general_operand" "")))]
1827 "TARGET_68881 || TARGET_FPA"
1831 [(set (match_operand:DF 0 "general_operand" "=x,y")
1833 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1838 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1840 (match_operand:SF 1 "general_operand" "f,dmF")))]
1844 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1846 if (REGNO (operands[0]) == REGNO (operands[1]))
1848 /* Extending float to double in an fp-reg is a no-op.
1849 NOTICE_UPDATE_CC has already assumed that the
1850 cc will be set. So cancel what it did. */
1851 cc_status = cc_prev_status;
1854 return \"f%&move%.x %1,%0\";
1856 if (FP_REG_P (operands[0]))
1857 return \"f%&move%.s %f1,%0\";
1858 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1860 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1861 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1862 return \"move%.l %+,%0\";
1864 return \"fmove%.d %f1,%0\";
1867 ;; This cannot output into an f-reg because there is no way to be
1868 ;; sure of truncating in that case.
1869 ;; But on the Sun FPA, we can be sure.
1870 (define_expand "truncdfsf2"
1871 [(set (match_operand:SF 0 "general_operand" "")
1873 (match_operand:DF 1 "general_operand" "")))]
1874 "TARGET_68881 || TARGET_FPA"
1878 [(set (match_operand:SF 0 "general_operand" "=x,y")
1880 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1884 ;; On the '040 we can truncate in a register accurately and easily.
1886 [(set (match_operand:SF 0 "general_operand" "=f")
1888 (match_operand:DF 1 "general_operand" "fmG")))]
1892 if (FP_REG_P (operands[1]))
1893 return \"f%$move%.x %1,%0\";
1894 return \"f%$move%.d %f1,%0\";
1898 [(set (match_operand:SF 0 "general_operand" "=dm")
1900 (match_operand:DF 1 "general_operand" "f")))]
1904 ;; Conversion between fixed point and floating point.
1905 ;; Note that among the fix-to-float insns
1906 ;; the ones that start with SImode come first.
1907 ;; That is so that an operand that is a CONST_INT
1908 ;; (and therefore lacks a specific machine mode).
1909 ;; will be recognized as SImode (which is always valid)
1910 ;; rather than as QImode or HImode.
1912 (define_expand "floatsisf2"
1913 [(set (match_operand:SF 0 "general_operand" "")
1914 (float:SF (match_operand:SI 1 "general_operand" "")))]
1915 "TARGET_68881 || TARGET_FPA"
1919 [(set (match_operand:SF 0 "general_operand" "=y,x")
1920 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1925 [(set (match_operand:SF 0 "general_operand" "=f")
1926 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1930 (define_expand "floatsidf2"
1931 [(set (match_operand:DF 0 "general_operand" "")
1932 (float:DF (match_operand:SI 1 "general_operand" "")))]
1933 "TARGET_68881 || TARGET_FPA"
1937 [(set (match_operand:DF 0 "general_operand" "=y,x")
1938 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1943 [(set (match_operand:DF 0 "general_operand" "=f")
1944 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1948 (define_insn "floathisf2"
1949 [(set (match_operand:SF 0 "general_operand" "=f")
1950 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1954 (define_insn "floathidf2"
1955 [(set (match_operand:DF 0 "general_operand" "=f")
1956 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1960 (define_insn "floatqisf2"
1961 [(set (match_operand:SF 0 "general_operand" "=f")
1962 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1966 (define_insn "floatqidf2"
1967 [(set (match_operand:DF 0 "general_operand" "=f")
1968 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1972 ;; New routines to convert floating-point values to integers
1973 ;; to be used on the '040. These should be faster than trapping
1974 ;; into the kernel to emulate fintrz. They should also be faster
1975 ;; than calling the subroutines fixsfsi or fixdfsi.
1977 (define_insn "fix_truncdfsi2"
1978 [(set (match_operand:SI 0 "general_operand" "=dm")
1979 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1980 (clobber (match_scratch:SI 2 "=d"))
1981 (clobber (match_scratch:SI 3 "=d"))]
1982 "TARGET_68881 && TARGET_68040"
1986 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1989 (define_insn "fix_truncdfhi2"
1990 [(set (match_operand:HI 0 "general_operand" "=dm")
1991 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1992 (clobber (match_scratch:SI 2 "=d"))
1993 (clobber (match_scratch:SI 3 "=d"))]
1994 "TARGET_68881 && TARGET_68040"
1998 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
2001 (define_insn "fix_truncdfqi2"
2002 [(set (match_operand:QI 0 "general_operand" "=dm")
2003 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2004 (clobber (match_scratch:SI 2 "=d"))
2005 (clobber (match_scratch:SI 3 "=d"))]
2006 "TARGET_68881 && TARGET_68040"
2010 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
2013 ;; Convert a float to a float whose value is an integer.
2014 ;; This is the first stage of converting it to an integer type.
2016 (define_insn "ftruncdf2"
2017 [(set (match_operand:DF 0 "general_operand" "=f")
2018 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
2019 "TARGET_68881 && !TARGET_68040"
2022 if (FP_REG_P (operands[1]))
2023 return \"fintrz%.x %f1,%0\";
2024 return \"fintrz%.d %f1,%0\";
2027 (define_insn "ftruncsf2"
2028 [(set (match_operand:SF 0 "general_operand" "=f")
2029 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
2030 "TARGET_68881 && !TARGET_68040"
2033 if (FP_REG_P (operands[1]))
2034 return \"fintrz%.x %f1,%0\";
2035 return \"fintrz%.s %f1,%0\";
2038 ;; Convert a float whose value is an integer
2039 ;; to an actual integer. Second stage of converting float to integer type.
2040 (define_insn "fixsfqi2"
2041 [(set (match_operand:QI 0 "general_operand" "=dm")
2042 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2046 (define_insn "fixsfhi2"
2047 [(set (match_operand:HI 0 "general_operand" "=dm")
2048 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2052 (define_insn "fixsfsi2"
2053 [(set (match_operand:SI 0 "general_operand" "=dm")
2054 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2058 (define_insn "fixdfqi2"
2059 [(set (match_operand:QI 0 "general_operand" "=dm")
2060 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2064 (define_insn "fixdfhi2"
2065 [(set (match_operand:HI 0 "general_operand" "=dm")
2066 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2070 (define_insn "fixdfsi2"
2071 [(set (match_operand:SI 0 "general_operand" "=dm")
2072 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2076 ;; Convert a float to an integer.
2077 ;; On the Sun FPA, this is done in one step.
2080 [(set (match_operand:SI 0 "general_operand" "=x,y")
2081 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2086 [(set (match_operand:SI 0 "general_operand" "=x,y")
2087 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2093 (define_insn "adddi_lshrdi_63"
2094 [(set (match_operand:DI 0 "general_operand" "=d")
2095 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2098 (clobber (match_scratch:SI 2 "=d"))]
2102 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2103 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2105 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2106 if (GET_CODE (operands[1]) == REG)
2107 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2108 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2109 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2110 operands[4] = operands[1];
2112 operands[4] = adj_offsettable_operand (operands[1], 4);
2113 if (GET_CODE (operands[1]) == MEM
2114 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2115 output_asm_insn (\"move%.l %4,%3\", operands);
2116 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2117 if (TARGET_68020 || TARGET_5200)
2118 output_asm_insn (\"extb%.l %2\", operands);
2120 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2121 if (GET_CODE (operands[1]) != MEM
2122 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2123 output_asm_insn (\"move%.l %4,%3\", operands);
2124 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2127 (define_insn "adddi_sexthishl32"
2128 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2129 (plus:DI (ashift:DI (sign_extend:DI
2130 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2132 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2133 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2138 if (ADDRESS_REG_P (operands[0]))
2139 return \"add%.w %1,%0\";
2140 else if (ADDRESS_REG_P (operands[3]))
2141 return \"move%.w %1,%3\;add%.l %3,%0\";
2143 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2146 (define_insn "adddi_dilshr32"
2147 [(set (match_operand:DI 0 "general_operand" "=d,o")
2148 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2149 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2150 ;; (const_int 32))))]
2151 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2153 (match_operand:DI 2 "general_operand" "0,0")))]
2158 if (GET_CODE (operands[0]) == REG)
2159 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2161 operands[2] = adj_offsettable_operand (operands[0], 4);
2162 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2165 (define_insn "adddi_dishl32"
2166 [(set (match_operand:DI 0 "general_operand" "=r,o")
2167 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2168 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2169 ;; (const_int 32))))]
2170 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2172 (match_operand:DI 2 "general_operand" "0,0")))]
2177 if (GET_CODE (operands[1]) == REG)
2178 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2180 operands[1] = adj_offsettable_operand (operands[1], 4);
2181 return \"add%.l %1,%0\";
2184 (define_insn "adddi3"
2185 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2186 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2187 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2188 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2192 if (DATA_REG_P (operands[0]))
2194 if (DATA_REG_P (operands[2]))
2195 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2196 else if (GET_CODE (operands[2]) == MEM
2197 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2198 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2204 if (GET_CODE (operands[2]) == REG)
2206 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2209 else if (CONSTANT_P (operands[2]))
2210 split_double (operands[2], &high, &low);
2213 low = adj_offsettable_operand (operands[2], 4);
2217 operands[1] = low, operands[2] = high;
2218 xoperands[0] = operands[3];
2219 if (GET_CODE (operands[1]) == CONST_INT
2220 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2221 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2223 xoperands[1] = operands[2];
2225 output_asm_insn (output_move_simode (xoperands), xoperands);
2226 if (GET_CODE (operands[1]) == CONST_INT)
2228 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2231 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2233 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2236 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2238 operands[1] = GEN_INT (-INTVAL (operands[1]));
2240 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2242 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2246 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2249 else if (GET_CODE (operands[0]) == MEM)
2251 if (GET_CODE (operands[2]) == MEM
2252 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2253 return \"add%.l %2,%0\;addx%.l %2,%0\";
2255 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2257 operands[1] = gen_rtx_MEM (SImode,
2258 plus_constant (XEXP(operands[0], 0), -8));
2259 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2261 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2263 operands[1] = XEXP(operands[0], 0);
2264 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2268 operands[1] = adj_offsettable_operand (operands[0], 4);
2269 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2276 (define_insn "addsi_lshrsi_31"
2277 [(set (match_operand:SI 0 "general_operand" "=dm")
2278 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2284 operands[2] = operands[0];
2285 operands[3] = gen_label_rtx();
2286 if (GET_CODE (operands[0]) == MEM)
2288 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2289 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2290 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2291 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2293 output_asm_insn (\"move%.l %1,%0\", operands);
2295 output_asm_insn (\"jbpl %l3\", operands);
2297 output_asm_insn (\"jpl %l3\", operands);
2300 output_asm_insn (\"addq%.l %#1,%2\", operands);
2302 output_asm_insn (\"add%.l %#1,%2\", operands);
2304 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2305 CODE_LABEL_NUMBER (operands[3]));
2309 (define_expand "addsi3"
2310 [(set (match_operand:SI 0 "general_operand" "")
2311 (plus:SI (match_operand:SI 1 "general_operand" "")
2312 (match_operand:SI 2 "general_src_operand" "")))]
2316 ;; Note that the middle two alternatives are near-duplicates
2317 ;; in order to handle insns generated by reload.
2318 ;; This is needed since they are not themselves reloaded,
2319 ;; so commutativity won't apply to them.
2320 (define_insn "*addsi3_internal"
2321 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,d,a")
2322 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2323 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2327 "* return output_addsi3 (operands);")
2329 (define_insn "*addsi3_5200"
2330 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2331 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2332 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2334 "* return output_addsi3 (operands);")
2337 [(set (match_operand:SI 0 "general_operand" "=a")
2338 (plus:SI (match_operand:SI 1 "general_operand" "0")
2340 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2344 (define_insn "addhi3"
2345 [(set (match_operand:HI 0 "general_operand" "=m,r")
2346 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2347 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2351 if (GET_CODE (operands[2]) == CONST_INT)
2354 /* If the constant would be a negative number when interpreted as
2355 HImode, make it negative. This is usually, but not always, done
2356 elsewhere in the compiler. First check for constants out of range,
2357 which could confuse us. */
2359 if (INTVAL (operands[2]) >= 32768)
2360 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2362 if (INTVAL (operands[2]) > 0
2363 && INTVAL (operands[2]) <= 8)
2364 return \"addq%.w %2,%0\";
2365 if (INTVAL (operands[2]) < 0
2366 && INTVAL (operands[2]) >= -8)
2368 operands[2] = GEN_INT (- INTVAL (operands[2]));
2369 return \"subq%.w %2,%0\";
2371 /* On the CPU32 it is faster to use two addqw instructions to
2372 add a small integer (8 < N <= 16) to a register.
2373 Likewise for subqw. */
2374 if (TARGET_CPU32 && REG_P (operands[0]))
2376 if (INTVAL (operands[2]) > 8
2377 && INTVAL (operands[2]) <= 16)
2379 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2380 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2382 if (INTVAL (operands[2]) < -8
2383 && INTVAL (operands[2]) >= -16)
2385 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2386 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2390 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2392 return \"lea (%c2,%0),%0\";
2394 return \"lea %0@(%c2),%0\";
2397 return \"add%.w %2,%0\";
2400 ;; These insns must use MATCH_DUP instead of the more expected
2401 ;; use of a matching constraint because the "output" here is also
2402 ;; an input, so you can't use the matching constraint. That also means
2403 ;; that you can't use the "%", so you need patterns with the matched
2404 ;; operand in both positions.
2407 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2408 (plus:HI (match_dup 0)
2409 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2413 if (GET_CODE (operands[1]) == CONST_INT)
2416 /* If the constant would be a negative number when interpreted as
2417 HImode, make it negative. This is usually, but not always, done
2418 elsewhere in the compiler. First check for constants out of range,
2419 which could confuse us. */
2421 if (INTVAL (operands[1]) >= 32768)
2422 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2424 if (INTVAL (operands[1]) > 0
2425 && INTVAL (operands[1]) <= 8)
2426 return \"addq%.w %1,%0\";
2427 if (INTVAL (operands[1]) < 0
2428 && INTVAL (operands[1]) >= -8)
2430 operands[1] = GEN_INT (- INTVAL (operands[1]));
2431 return \"subq%.w %1,%0\";
2433 /* On the CPU32 it is faster to use two addqw instructions to
2434 add a small integer (8 < N <= 16) to a register.
2435 Likewise for subqw. */
2436 if (TARGET_CPU32 && REG_P (operands[0]))
2438 if (INTVAL (operands[1]) > 8
2439 && INTVAL (operands[1]) <= 16)
2441 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2442 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2444 if (INTVAL (operands[1]) < -8
2445 && INTVAL (operands[1]) >= -16)
2447 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2448 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2452 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2454 return \"lea (%c1,%0),%0\";
2456 return \"lea %0@(%c1),%0\";
2459 return \"add%.w %1,%0\";
2463 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2464 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2469 if (GET_CODE (operands[1]) == CONST_INT)
2472 /* If the constant would be a negative number when interpreted as
2473 HImode, make it negative. This is usually, but not always, done
2474 elsewhere in the compiler. First check for constants out of range,
2475 which could confuse us. */
2477 if (INTVAL (operands[1]) >= 32768)
2478 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2480 if (INTVAL (operands[1]) > 0
2481 && INTVAL (operands[1]) <= 8)
2482 return \"addq%.w %1,%0\";
2483 if (INTVAL (operands[1]) < 0
2484 && INTVAL (operands[1]) >= -8)
2486 operands[1] = GEN_INT (- INTVAL (operands[1]));
2487 return \"subq%.w %1,%0\";
2489 /* On the CPU32 it is faster to use two addqw instructions to
2490 add a small integer (8 < N <= 16) to a register.
2491 Likewise for subqw. */
2492 if (TARGET_CPU32 && REG_P (operands[0]))
2494 if (INTVAL (operands[1]) > 8
2495 && INTVAL (operands[1]) <= 16)
2497 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2498 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2500 if (INTVAL (operands[1]) < -8
2501 && INTVAL (operands[1]) >= -16)
2503 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2504 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2508 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2510 return \"lea (%c1,%0),%0\";
2512 return \"lea %0@(%c1),%0\";
2515 return \"add%.w %1,%0\";
2518 (define_insn "addqi3"
2519 [(set (match_operand:QI 0 "general_operand" "=m,d")
2520 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2521 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2526 if (GET_CODE (operands[2]) == CONST_INT)
2528 if (INTVAL (operands[2]) >= 128)
2529 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2531 if (INTVAL (operands[2]) > 0
2532 && INTVAL (operands[2]) <= 8)
2533 return \"addq%.b %2,%0\";
2534 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2536 operands[2] = GEN_INT (- INTVAL (operands[2]));
2537 return \"subq%.b %2,%0\";
2541 return \"add%.b %2,%0\";
2545 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2546 (plus:QI (match_dup 0)
2547 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2552 if (GET_CODE (operands[1]) == CONST_INT)
2554 if (INTVAL (operands[1]) >= 128)
2555 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2557 if (INTVAL (operands[1]) > 0
2558 && INTVAL (operands[1]) <= 8)
2559 return \"addq%.b %1,%0\";
2560 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2562 operands[1] = GEN_INT (- INTVAL (operands[1]));
2563 return \"subq%.b %1,%0\";
2567 return \"add%.b %1,%0\";
2571 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2572 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2578 if (GET_CODE (operands[1]) == CONST_INT)
2580 if (INTVAL (operands[1]) >= 128)
2581 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2583 if (INTVAL (operands[1]) > 0
2584 && INTVAL (operands[1]) <= 8)
2585 return \"addq%.b %1,%0\";
2586 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2588 operands[1] = GEN_INT (- INTVAL (operands[1]));
2589 return \"subq%.b %1,%0\";
2593 return \"add%.b %1,%0\";
2596 (define_expand "adddf3"
2597 [(set (match_operand:DF 0 "general_operand" "")
2598 (plus:DF (match_operand:DF 1 "general_operand" "")
2599 (match_operand:DF 2 "general_operand" "")))]
2600 "TARGET_68881 || TARGET_FPA"
2604 [(set (match_operand:DF 0 "general_operand" "=x,y")
2605 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2606 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2610 if (rtx_equal_p (operands[0], operands[1]))
2611 return \"fpadd%.d %y2,%0\";
2612 if (rtx_equal_p (operands[0], operands[2]))
2613 return \"fpadd%.d %y1,%0\";
2614 if (which_alternative == 0)
2615 return \"fpadd3%.d %w2,%w1,%0\";
2616 return \"fpadd3%.d %x2,%x1,%0\";
2620 [(set (match_operand:DF 0 "general_operand" "=f")
2621 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2622 (match_operand:DF 1 "general_operand" "0")))]
2627 [(set (match_operand:DF 0 "general_operand" "=f")
2628 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2629 (match_operand:DF 1 "general_operand" "0")))]
2634 [(set (match_operand:DF 0 "general_operand" "=f")
2635 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2636 (match_operand:DF 1 "general_operand" "0")))]
2641 [(set (match_operand:DF 0 "general_operand" "=f")
2642 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2643 (match_operand:DF 2 "general_operand" "fmG")))]
2647 if (REG_P (operands[2]))
2648 return \"f%&add%.x %2,%0\";
2649 return \"f%&add%.d %f2,%0\";
2652 (define_expand "addsf3"
2653 [(set (match_operand:SF 0 "general_operand" "")
2654 (plus:SF (match_operand:SF 1 "general_operand" "")
2655 (match_operand:SF 2 "general_operand" "")))]
2656 "TARGET_68881 || TARGET_FPA"
2660 [(set (match_operand:SF 0 "general_operand" "=x,y")
2661 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2662 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2666 if (rtx_equal_p (operands[0], operands[1]))
2667 return \"fpadd%.s %w2,%0\";
2668 if (rtx_equal_p (operands[0], operands[2]))
2669 return \"fpadd%.s %w1,%0\";
2670 if (which_alternative == 0)
2671 return \"fpadd3%.s %w2,%w1,%0\";
2672 return \"fpadd3%.s %2,%1,%0\";
2676 [(set (match_operand:SF 0 "general_operand" "=f")
2677 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2678 (match_operand:SF 1 "general_operand" "0")))]
2683 [(set (match_operand:SF 0 "general_operand" "=f")
2684 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2685 (match_operand:SF 1 "general_operand" "0")))]
2690 [(set (match_operand:SF 0 "general_operand" "=f")
2691 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2692 (match_operand:SF 1 "general_operand" "0")))]
2697 [(set (match_operand:SF 0 "general_operand" "=f")
2698 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2699 (match_operand:SF 2 "general_operand" "fdmF")))]
2703 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2704 return \"f%$add%.x %2,%0\";
2705 return \"f%$add%.s %f2,%0\";
2708 ;; subtract instructions
2710 (define_insn "subdi_sexthishl32"
2711 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2712 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2713 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2715 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2720 if (ADDRESS_REG_P (operands[0]))
2721 return \"sub%.w %2,%0\";
2722 else if (ADDRESS_REG_P (operands[3]))
2723 return \"move%.w %2,%3\;sub%.l %3,%0\";
2725 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2728 (define_insn "subdi_dishl32"
2729 [(set (match_operand:DI 0 "general_operand" "+ro")
2730 (minus:DI (match_dup 0)
2731 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2737 if (GET_CODE (operands[1]) == REG)
2738 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2740 operands[1] = adj_offsettable_operand (operands[1], 4);
2741 return \"sub%.l %1,%0\";
2744 (define_insn "subdi3"
2745 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2746 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2747 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2748 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2752 if (DATA_REG_P (operands[0]))
2754 if (DATA_REG_P (operands[2]))
2755 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2756 else if (GET_CODE (operands[2]) == MEM
2757 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2759 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2766 if (GET_CODE (operands[2]) == REG)
2768 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2771 else if (CONSTANT_P (operands[2]))
2772 split_double (operands[2], &high, &low);
2775 low = adj_offsettable_operand (operands[2], 4);
2779 operands[1] = low, operands[2] = high;
2780 xoperands[0] = operands[3];
2781 if (GET_CODE (operands[1]) == CONST_INT
2782 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2783 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2785 xoperands[1] = operands[2];
2787 output_asm_insn (output_move_simode (xoperands), xoperands);
2788 if (GET_CODE (operands[1]) == CONST_INT)
2790 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2793 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2795 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2798 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2800 operands[1] = GEN_INT (-INTVAL (operands[1]));
2802 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2804 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2808 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2811 else if (GET_CODE (operands[0]) == MEM)
2813 if (GET_CODE (operands[2]) == MEM
2814 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2815 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2817 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2820 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2821 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2823 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2825 operands[1] = XEXP(operands[0], 0);
2826 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2830 operands[1] = adj_offsettable_operand (operands[0], 4);
2831 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2838 (define_insn "subsi3"
2839 [(set (match_operand:SI 0 "general_operand" "=m,d,a")
2840 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2841 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2846 [(set (match_operand:SI 0 "general_operand" "=a")
2847 (minus:SI (match_operand:SI 1 "general_operand" "0")
2849 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2853 (define_insn "subhi3"
2854 [(set (match_operand:HI 0 "general_operand" "=m,r")
2855 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2856 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2861 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2862 (minus:HI (match_dup 0)
2863 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2867 (define_insn "subqi3"
2868 [(set (match_operand:QI 0 "general_operand" "=m,d")
2869 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2870 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2875 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2876 (minus:QI (match_dup 0)
2877 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2881 (define_expand "subdf3"
2882 [(set (match_operand:DF 0 "general_operand" "")
2883 (minus:DF (match_operand:DF 1 "general_operand" "")
2884 (match_operand:DF 2 "general_operand" "")))]
2885 "TARGET_68881 || TARGET_FPA"
2889 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2890 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2891 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2895 if (rtx_equal_p (operands[0], operands[2]))
2896 return \"fprsub%.d %y1,%0\";
2897 if (rtx_equal_p (operands[0], operands[1]))
2898 return \"fpsub%.d %y2,%0\";
2899 if (which_alternative == 0)
2900 return \"fpsub3%.d %w2,%w1,%0\";
2901 return \"fpsub3%.d %x2,%x1,%0\";
2905 [(set (match_operand:DF 0 "general_operand" "=f")
2906 (minus:DF (match_operand:DF 1 "general_operand" "0")
2907 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2912 [(set (match_operand:DF 0 "general_operand" "=f")
2913 (minus:DF (match_operand:DF 1 "general_operand" "0")
2914 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2919 [(set (match_operand:DF 0 "general_operand" "=f")
2920 (minus:DF (match_operand:DF 1 "general_operand" "0")
2921 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2926 [(set (match_operand:DF 0 "general_operand" "=f")
2927 (minus:DF (match_operand:DF 1 "general_operand" "0")
2928 (match_operand:DF 2 "general_operand" "fmG")))]
2932 if (REG_P (operands[2]))
2933 return \"f%&sub%.x %2,%0\";
2934 return \"f%&sub%.d %f2,%0\";
2937 (define_expand "subsf3"
2938 [(set (match_operand:SF 0 "general_operand" "")
2939 (minus:SF (match_operand:SF 1 "general_operand" "")
2940 (match_operand:SF 2 "general_operand" "")))]
2941 "TARGET_68881 || TARGET_FPA"
2945 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2946 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2947 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2951 if (rtx_equal_p (operands[0], operands[2]))
2952 return \"fprsub%.s %w1,%0\";
2953 if (rtx_equal_p (operands[0], operands[1]))
2954 return \"fpsub%.s %w2,%0\";
2955 if (which_alternative == 0)
2956 return \"fpsub3%.s %w2,%w1,%0\";
2957 return \"fpsub3%.s %2,%1,%0\";
2961 [(set (match_operand:SF 0 "general_operand" "=f")
2962 (minus:SF (match_operand:SF 1 "general_operand" "0")
2963 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2968 [(set (match_operand:SF 0 "general_operand" "=f")
2969 (minus:SF (match_operand:SF 1 "general_operand" "0")
2970 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2975 [(set (match_operand:SF 0 "general_operand" "=f")
2976 (minus:SF (match_operand:SF 1 "general_operand" "0")
2977 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2982 [(set (match_operand:SF 0 "general_operand" "=f")
2983 (minus:SF (match_operand:SF 1 "general_operand" "0")
2984 (match_operand:SF 2 "general_operand" "fdmF")))]
2988 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2989 return \"f%$sub%.x %2,%0\";
2990 return \"f%$sub%.s %f2,%0\";
2993 ;; multiply instructions
2995 (define_insn "mulhi3"
2996 [(set (match_operand:HI 0 "general_operand" "=d")
2997 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2998 (match_operand:HI 2 "general_src_operand" "dmSn")))]
3002 #if defined(MOTOROLA) && !defined(CRDS)
3003 return \"muls%.w %2,%0\";
3005 return \"muls %2,%0\";
3009 (define_insn "mulhisi3"
3010 [(set (match_operand:SI 0 "general_operand" "=d")
3011 (mult:SI (sign_extend:SI
3012 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3014 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3018 #if defined(MOTOROLA) && !defined(CRDS)
3019 return \"muls%.w %2,%0\";
3021 return \"muls %2,%0\";
3026 [(set (match_operand:SI 0 "general_operand" "=d")
3027 (mult:SI (sign_extend:SI
3028 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3029 (match_operand:SI 2 "const_int_operand" "n")))]
3030 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3033 #if defined(MOTOROLA) && !defined(CRDS)
3034 return \"muls%.w %2,%0\";
3036 return \"muls %2,%0\";
3040 (define_expand "mulsi3"
3041 [(set (match_operand:SI 0 "general_operand" "")
3042 (mult:SI (match_operand:SI 1 "general_operand" "")
3043 (match_operand:SI 2 "general_operand" "")))]
3044 "TARGET_68020 || TARGET_5200"
3048 [(set (match_operand:SI 0 "general_operand" "=d")
3049 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3050 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3056 [(set (match_operand:SI 0 "general_operand" "=d")
3057 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3058 (match_operand:SI 2 "general_operand" "d<Q>")))]
3062 (define_insn "umulhisi3"
3063 [(set (match_operand:SI 0 "general_operand" "=d")
3064 (mult:SI (zero_extend:SI
3065 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3067 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3071 #if defined(MOTOROLA) && !defined(CRDS)
3072 return \"mulu%.w %2,%0\";
3074 return \"mulu %2,%0\";
3079 [(set (match_operand:SI 0 "general_operand" "=d")
3080 (mult:SI (zero_extend:SI
3081 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3082 (match_operand:SI 2 "const_int_operand" "n")))]
3083 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3086 #if defined(MOTOROLA) && !defined(CRDS)
3087 return \"mulu%.w %2,%0\";
3089 return \"mulu %2,%0\";
3093 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3094 ;; proper matching constraint. This is because the matching is between
3095 ;; the high-numbered word of the DImode operand[0] and operand[1].
3096 (define_expand "umulsidi3"
3098 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3099 (mult:SI (match_operand:SI 1 "register_operand" "")
3100 (match_operand:SI 2 "nonimmediate_operand" "")))
3101 (set (subreg:SI (match_dup 0) 0)
3102 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3103 (zero_extend:DI (match_dup 2)))
3104 (const_int 32))))])]
3105 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3109 [(set (match_operand:SI 0 "register_operand" "=d")
3110 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3111 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3112 (set (match_operand:SI 3 "register_operand" "=d")
3113 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3114 (zero_extend:DI (match_dup 2)))
3116 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3119 ; Match immediate case. For 2.4 only match things < 2^31.
3120 ; It's tricky with larger values in these patterns since we need to match
3121 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3124 [(set (match_operand:SI 0 "register_operand" "=d")
3125 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3126 (match_operand:SI 2 "const_int_operand" "n")))
3127 (set (match_operand:SI 3 "register_operand" "=d")
3128 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3131 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3132 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3135 (define_expand "mulsidi3"
3137 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3138 (mult:SI (match_operand:SI 1 "register_operand" "")
3139 (match_operand:SI 2 "nonimmediate_operand" "")))
3140 (set (subreg:SI (match_dup 0) 0)
3141 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3142 (sign_extend:DI (match_dup 2)))
3143 (const_int 32))))])]
3144 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3148 [(set (match_operand:SI 0 "register_operand" "=d")
3149 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3150 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3151 (set (match_operand:SI 3 "register_operand" "=d")
3152 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3153 (sign_extend:DI (match_dup 2)))
3155 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3159 [(set (match_operand:SI 0 "register_operand" "=d")
3160 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3161 (match_operand:SI 2 "const_sint32_operand" "")))
3162 (set (match_operand:SI 3 "register_operand" "=d")
3163 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3166 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3169 (define_expand "umulsi3_highpart"
3171 [(set (match_operand:SI 0 "register_operand" "")
3174 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3175 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3177 (clobber (match_dup 3))])]
3178 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3181 operands[3] = gen_reg_rtx (SImode);
3182 if (GET_CODE (operands[2]) == CONST_INT
3183 || GET_CODE (operands[2]) == CONST_DOUBLE)
3185 if (! const_uint32_operand (operands[2], VOIDmode))
3187 /* We have to adjust the operand order for the matching constraints. */
3188 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3189 operands[1], operands[2]));
3195 [(set (match_operand:SI 0 "register_operand" "=d")
3198 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3199 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3201 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3202 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3205 (define_insn "const_umulsi3_highpart"
3206 [(set (match_operand:SI 0 "register_operand" "=d")
3209 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3210 (match_operand 3 "const_uint32_operand" ""))
3212 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3213 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3216 (define_expand "smulsi3_highpart"
3218 [(set (match_operand:SI 0 "register_operand" "")
3221 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3222 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3224 (clobber (match_dup 3))])]
3225 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3228 operands[3] = gen_reg_rtx (SImode);
3229 if (GET_CODE (operands[2]) == CONST_INT
3230 || GET_CODE (operands[2]) == CONST_DOUBLE)
3232 if (! const_sint32_operand (operands[2], VOIDmode))
3234 /* We have to adjust the operand order for the matching constraints. */
3235 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3236 operands[1], operands[2]));
3242 [(set (match_operand:SI 0 "register_operand" "=d")
3245 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3246 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3248 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3249 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3252 (define_insn "const_smulsi3_highpart"
3253 [(set (match_operand:SI 0 "register_operand" "=d")
3256 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3257 (match_operand 3 "const_sint32_operand" ""))
3259 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3260 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3263 (define_expand "muldf3"
3264 [(set (match_operand:DF 0 "general_operand" "")
3265 (mult:DF (match_operand:DF 1 "general_operand" "")
3266 (match_operand:DF 2 "general_operand" "")))]
3267 "TARGET_68881 || TARGET_FPA"
3271 [(set (match_operand:DF 0 "general_operand" "=x,y")
3272 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3273 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3277 if (rtx_equal_p (operands[1], operands[2]))
3278 return \"fpsqr%.d %y1,%0\";
3279 if (rtx_equal_p (operands[0], operands[1]))
3280 return \"fpmul%.d %y2,%0\";
3281 if (rtx_equal_p (operands[0], operands[2]))
3282 return \"fpmul%.d %y1,%0\";
3283 if (which_alternative == 0)
3284 return \"fpmul3%.d %w2,%w1,%0\";
3285 return \"fpmul3%.d %x2,%x1,%0\";
3289 [(set (match_operand:DF 0 "general_operand" "=f")
3290 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3291 (match_operand:DF 1 "general_operand" "0")))]
3296 [(set (match_operand:DF 0 "general_operand" "=f")
3297 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3298 (match_operand:DF 1 "general_operand" "0")))]
3303 [(set (match_operand:DF 0 "general_operand" "=f")
3304 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3305 (match_operand:DF 1 "general_operand" "0")))]
3310 [(set (match_operand:DF 0 "general_operand" "=f")
3311 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3312 (match_operand:DF 2 "general_operand" "fmG")))]
3316 if (GET_CODE (operands[2]) == CONST_DOUBLE
3317 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3319 int i = floating_exact_log2 (operands[2]);
3320 operands[2] = GEN_INT (i);
3321 return \"fscale%.l %2,%0\";
3323 if (REG_P (operands[2]))
3324 return \"f%&mul%.x %2,%0\";
3325 return \"f%&mul%.d %f2,%0\";
3328 (define_expand "mulsf3"
3329 [(set (match_operand:SF 0 "general_operand" "")
3330 (mult:SF (match_operand:SF 1 "general_operand" "")
3331 (match_operand:SF 2 "general_operand" "")))]
3332 "TARGET_68881 || TARGET_FPA"
3336 [(set (match_operand:SF 0 "general_operand" "=x,y")
3337 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3338 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3342 if (rtx_equal_p (operands[1], operands[2]))
3343 return \"fpsqr%.s %w1,%0\";
3344 if (rtx_equal_p (operands[0], operands[1]))
3345 return \"fpmul%.s %w2,%0\";
3346 if (rtx_equal_p (operands[0], operands[2]))
3347 return \"fpmul%.s %w1,%0\";
3348 if (which_alternative == 0)
3349 return \"fpmul3%.s %w2,%w1,%0\";
3350 return \"fpmul3%.s %2,%1,%0\";
3354 [(set (match_operand:SF 0 "general_operand" "=f")
3355 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3356 (match_operand:SF 1 "general_operand" "0")))]
3360 return (TARGET_68040_ONLY
3361 ? \"fsmul%.l %2,%0\"
3362 : \"fsglmul%.l %2,%0\");
3366 [(set (match_operand:SF 0 "general_operand" "=f")
3367 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3368 (match_operand:SF 1 "general_operand" "0")))]
3372 return (TARGET_68040_ONLY
3373 ? \"fsmul%.w %2,%0\"
3374 : \"fsglmul%.w %2,%0\");
3378 [(set (match_operand:SF 0 "general_operand" "=f")
3379 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3380 (match_operand:SF 1 "general_operand" "0")))]
3384 return (TARGET_68040_ONLY
3385 ? \"fsmul%.b %2,%0\"
3386 : \"fsglmul%.b %2,%0\");
3390 [(set (match_operand:SF 0 "general_operand" "=f")
3391 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3392 (match_operand:SF 2 "general_operand" "fdmF")))]
3396 #ifdef FSGLMUL_USE_S
3397 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3398 return (TARGET_68040_ONLY
3399 ? \"fsmul%.s %2,%0\"
3400 : \"fsglmul%.s %2,%0\");
3402 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3403 return (TARGET_68040_ONLY
3404 ? \"fsmul%.x %2,%0\"
3405 : \"fsglmul%.x %2,%0\");
3407 return (TARGET_68040_ONLY
3408 ? \"fsmul%.s %f2,%0\"
3409 : \"fsglmul%.s %f2,%0\");
3412 ;; divide instructions
3414 (define_expand "divdf3"
3415 [(set (match_operand:DF 0 "general_operand" "")
3416 (div:DF (match_operand:DF 1 "general_operand" "")
3417 (match_operand:DF 2 "general_operand" "")))]
3418 "TARGET_68881 || TARGET_FPA"
3422 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3423 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3424 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3428 if (rtx_equal_p (operands[0], operands[2]))
3429 return \"fprdiv%.d %y1,%0\";
3430 if (rtx_equal_p (operands[0], operands[1]))
3431 return \"fpdiv%.d %y2,%0\";
3432 if (which_alternative == 0)
3433 return \"fpdiv3%.d %w2,%w1,%0\";
3434 return \"fpdiv3%.d %x2,%x1,%x0\";
3438 [(set (match_operand:DF 0 "general_operand" "=f")
3439 (div:DF (match_operand:DF 1 "general_operand" "0")
3440 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3445 [(set (match_operand:DF 0 "general_operand" "=f")
3446 (div:DF (match_operand:DF 1 "general_operand" "0")
3447 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3452 [(set (match_operand:DF 0 "general_operand" "=f")
3453 (div:DF (match_operand:DF 1 "general_operand" "0")
3454 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3459 [(set (match_operand:DF 0 "general_operand" "=f")
3460 (div:DF (match_operand:DF 1 "general_operand" "0")
3461 (match_operand:DF 2 "general_operand" "fmG")))]
3465 if (REG_P (operands[2]))
3466 return \"f%&div%.x %2,%0\";
3467 return \"f%&div%.d %f2,%0\";
3470 (define_expand "divsf3"
3471 [(set (match_operand:SF 0 "general_operand" "")
3472 (div:SF (match_operand:SF 1 "general_operand" "")
3473 (match_operand:SF 2 "general_operand" "")))]
3474 "TARGET_68881 || TARGET_FPA"
3478 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3479 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3480 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3484 if (rtx_equal_p (operands[0], operands[1]))
3485 return \"fpdiv%.s %w2,%0\";
3486 if (rtx_equal_p (operands[0], operands[2]))
3487 return \"fprdiv%.s %w1,%0\";
3488 if (which_alternative == 0)
3489 return \"fpdiv3%.s %w2,%w1,%0\";
3490 return \"fpdiv3%.s %2,%1,%0\";
3494 [(set (match_operand:SF 0 "general_operand" "=f")
3495 (div:SF (match_operand:SF 1 "general_operand" "0")
3496 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3500 return (TARGET_68040_ONLY
3501 ? \"fsdiv%.l %2,%0\"
3502 : \"fsgldiv%.l %2,%0\");
3506 [(set (match_operand:SF 0 "general_operand" "=f")
3507 (div:SF (match_operand:SF 1 "general_operand" "0")
3508 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3512 return (TARGET_68040_ONLY
3513 ? \"fsdiv%.w %2,%0\"
3514 : \"fsgldiv%.w %2,%0\");
3518 [(set (match_operand:SF 0 "general_operand" "=f")
3519 (div:SF (match_operand:SF 1 "general_operand" "0")
3520 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3524 return (TARGET_68040_ONLY
3525 ? \"fsdiv%.b %2,%0\"
3526 : \"fsgldiv%.b %2,%0\");
3530 [(set (match_operand:SF 0 "general_operand" "=f")
3531 (div:SF (match_operand:SF 1 "general_operand" "0")
3532 (match_operand:SF 2 "general_operand" "fdmF")))]
3536 #ifdef FSGLDIV_USE_S
3537 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3538 return (TARGET_68040_ONLY
3539 ? \"fsdiv%.s %2,%0\"
3540 : \"fsgldiv%.s %2,%0\");
3542 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3543 return (TARGET_68040_ONLY
3544 ? \"fsdiv%.x %2,%0\"
3545 : \"fsgldiv%.x %2,%0\");
3547 return (TARGET_68040_ONLY
3548 ? \"fsdiv%.s %f2,%0\"
3549 : \"fsgldiv%.s %f2,%0\");
3552 ;; Remainder instructions.
3554 (define_insn "divmodsi4"
3555 [(set (match_operand:SI 0 "general_operand" "=d")
3556 (div:SI (match_operand:SI 1 "general_operand" "0")
3557 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3558 (set (match_operand:SI 3 "general_operand" "=d")
3559 (mod:SI (match_dup 1) (match_dup 2)))]
3560 "TARGET_68020 && !TARGET_5200"
3563 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3564 return \"divs%.l %2,%0\";
3566 return \"divsl%.l %2,%3:%0\";
3569 (define_insn "udivmodsi4"
3570 [(set (match_operand:SI 0 "general_operand" "=d")
3571 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3572 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3573 (set (match_operand:SI 3 "general_operand" "=d")
3574 (umod:SI (match_dup 1) (match_dup 2)))]
3575 "TARGET_68020 && !TARGET_5200"
3578 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3579 return \"divu%.l %2,%0\";
3581 return \"divul%.l %2,%3:%0\";
3584 (define_insn "divmodhi4"
3585 [(set (match_operand:HI 0 "general_operand" "=d")
3586 (div:HI (match_operand:HI 1 "general_operand" "0")
3587 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3588 (set (match_operand:HI 3 "general_operand" "=d")
3589 (mod:HI (match_dup 1) (match_dup 2)))]
3594 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3596 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3598 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3601 return \"move%.l %0,%3\;swap %3\";
3607 (define_insn "udivmodhi4"
3608 [(set (match_operand:HI 0 "general_operand" "=d")
3609 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3610 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3611 (set (match_operand:HI 3 "general_operand" "=d")
3612 (umod:HI (match_dup 1) (match_dup 2)))]
3617 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3619 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3621 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3624 return \"move%.l %0,%3\;swap %3\";
3630 ;; logical-and instructions
3632 ;; "anddi3" is mainly here to help combine().
3633 (define_insn "anddi3"
3634 [(set (match_operand:DI 0 "general_operand" "=o,d")
3635 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3636 (match_operand:DI 2 "general_operand" "dn,don")))]
3641 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3642 if (CONSTANT_P (operands[2]))
3646 split_double (operands[2], &hi, &lo);
3648 switch (INTVAL (hi))
3651 output_asm_insn (\"clr%.l %0\", operands);
3659 xoperands[0] = operands[0];
3661 output_asm_insn (output_andsi3 (xoperands), xoperands);
3664 if (GET_CODE (operands[0]) == REG)
3665 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3667 operands[0] = adj_offsettable_operand (operands[0], 4);
3668 switch (INTVAL (lo))
3671 output_asm_insn (\"clr%.l %0\", operands);
3679 xoperands[0] = operands[0];
3681 output_asm_insn (output_andsi3 (xoperands), xoperands);
3686 if (GET_CODE (operands[0]) != REG)
3688 operands[1] = adj_offsettable_operand (operands[0], 4);
3689 return \"and%.l %2,%0\;and%.l %R2,%1\";
3691 if (GET_CODE (operands[2]) != REG)
3693 operands[1] = adj_offsettable_operand (operands[2], 4);
3694 return \"and%.l %2,%0\;and%.l %1,%R0\";
3696 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3699 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3700 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3701 ;; can't allocate pseudos into it.
3703 (define_expand "andsi3"
3704 [(set (match_operand:SI 0 "not_sp_operand" "")
3705 (and:SI (match_operand:SI 1 "general_operand" "")
3706 (match_operand:SI 2 "general_src_operand" "")))]
3710 (define_insn "andsi3_internal"
3711 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3712 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3713 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3717 return output_andsi3 (operands);
3720 (define_insn "andsi3_5200"
3721 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3722 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3723 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3727 (define_insn "andhi3"
3728 [(set (match_operand:HI 0 "general_operand" "=m,d")
3729 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3730 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3735 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3736 (and:HI (match_dup 0)
3737 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3742 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3743 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3748 (define_insn "andqi3"
3749 [(set (match_operand:QI 0 "general_operand" "=m,d")
3750 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3751 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3756 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3757 (and:QI (match_dup 0)
3758 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3763 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3764 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3769 ;; inclusive-or instructions
3771 (define_insn "iordi_zext"
3772 [(set (match_operand:DI 0 "general_operand" "=o,d")
3773 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3774 (match_operand:DI 2 "general_operand" "0,0")))]
3781 if (GET_CODE (operands[0]) == REG)
3782 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3784 operands[0] = adj_offsettable_operand (operands[0], 4);
3785 if (GET_MODE (operands[1]) == SImode)
3786 return \"or%.l %1,%0\";
3787 byte_mode = (GET_MODE (operands[1]) == QImode);
3788 if (GET_CODE (operands[0]) == MEM)
3789 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3791 return \"or%.b %1,%0\";
3793 return \"or%.w %1,%0\";
3796 ;; "iordi3" is mainly here to help combine().
3797 (define_insn "iordi3"
3798 [(set (match_operand:DI 0 "general_operand" "=o,d")
3799 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3800 (match_operand:DI 2 "general_operand" "dn,don")))]
3805 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3806 if (CONSTANT_P (operands[2]))
3810 split_double (operands[2], &hi, &lo);
3812 switch (INTVAL (hi))
3817 /* FIXME : a scratch register would be welcome here if operand[0]
3818 is not a register */
3819 output_asm_insn (\"move%.l %#-1,%0\", operands);
3825 xoperands[0] = operands[0];
3827 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3830 if (GET_CODE (operands[0]) == REG)
3831 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3833 operands[0] = adj_offsettable_operand (operands[0], 4);
3834 switch (INTVAL (lo))
3839 /* FIXME : a scratch register would be welcome here if operand[0]
3840 is not a register */
3841 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3847 xoperands[0] = operands[0];
3849 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3854 if (GET_CODE (operands[0]) != REG)
3856 operands[1] = adj_offsettable_operand (operands[0], 4);
3857 return \"or%.l %2,%0\;or%.l %R2,%1\";
3859 if (GET_CODE (operands[2]) != REG)
3861 operands[1] = adj_offsettable_operand (operands[2], 4);
3862 return \"or%.l %2,%0\;or%.l %1,%R0\";
3864 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3867 (define_expand "iorsi3"
3868 [(set (match_operand:SI 0 "general_operand" "")
3869 (ior:SI (match_operand:SI 1 "general_operand" "")
3870 (match_operand:SI 2 "general_src_operand" "")))]
3874 (define_insn "iorsi3_internal"
3875 [(set (match_operand:SI 0 "general_operand" "=m,d")
3876 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3877 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3881 return output_iorsi3 (operands);
3884 (define_insn "iorsi3_5200"
3885 [(set (match_operand:SI 0 "general_operand" "=m,d")
3886 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3887 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3891 (define_insn "iorhi3"
3892 [(set (match_operand:HI 0 "general_operand" "=m,d")
3893 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3894 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3899 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3900 (ior:HI (match_dup 0)
3901 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3906 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3907 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3912 (define_insn "iorqi3"
3913 [(set (match_operand:QI 0 "general_operand" "=m,d")
3914 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3915 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3920 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3921 (ior:QI (match_dup 0)
3922 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3927 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3928 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3933 ;; On all 68k models, this makes faster code in a special case.
3934 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3936 (define_insn "iorsi_zexthi_ashl16"
3937 [(set (match_operand:SI 0 "general_operand" "=&d")
3938 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3939 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3945 if (GET_CODE (operands[2]) != REG)
3946 operands[2] = adj_offsettable_operand (operands[2], 2);
3947 if (GET_CODE (operands[2]) != REG
3948 || REGNO (operands[2]) != REGNO (operands[0]))
3949 output_asm_insn (\"move%.w %2,%0\", operands);
3950 return \"swap %0\;mov%.w %1,%0\";
3953 (define_insn "iorsi_zext"
3954 [(set (match_operand:SI 0 "general_operand" "=o,d")
3955 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3956 (match_operand:SI 2 "general_operand" "0,0")))]
3963 byte_mode = (GET_MODE (operands[1]) == QImode);
3964 if (GET_CODE (operands[0]) == MEM)
3965 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3967 return \"or%.b %1,%0\";
3969 return \"or%.w %1,%0\";
3974 ;; "xordi3" is mainly here to help combine().
3975 (define_insn "xordi3"
3976 [(set (match_operand:DI 0 "general_operand" "=od")
3977 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3978 (match_operand:DI 2 "general_operand" "dn")))]
3983 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3985 if (CONSTANT_P (operands[2]))
3989 split_double (operands[2], &hi, &lo);
3991 switch (INTVAL (hi))
3996 output_asm_insn (\"not%.l %0\", operands);
3999 /* FIXME : a scratch register would be welcome here if
4000 -128 <= INTVAL (hi) < -1 */
4004 xoperands[0] = operands[0];
4006 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4009 if (GET_CODE (operands[0]) == REG)
4010 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4012 operands[0] = adj_offsettable_operand (operands[0], 4);
4013 switch (INTVAL (lo))
4018 output_asm_insn (\"not%.l %0\", operands);
4021 /* FIXME : a scratch register would be welcome here if
4022 -128 <= INTVAL (lo) < -1 */
4024 /* FIXME : this should be merged with xorsi3 */
4028 xoperands[0] = operands[0];
4030 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4035 if (GET_CODE (operands[0]) != REG)
4037 operands[1] = adj_offsettable_operand (operands[0], 4);
4038 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4040 if (GET_CODE (operands[2]) != REG)
4042 operands[1] = adj_offsettable_operand (operands[2], 4);
4043 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4045 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4048 (define_expand "xorsi3"
4049 [(set (match_operand:SI 0 "general_operand" "")
4050 (xor:SI (match_operand:SI 1 "general_operand" "")
4051 (match_operand:SI 2 "general_operand" "")))]
4055 (define_insn "xorsi3_internal"
4056 [(set (match_operand:SI 0 "general_operand" "=do,m")
4057 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4058 (match_operand:SI 2 "general_operand" "di,dKT")))]
4063 return output_xorsi3 (operands);
4066 (define_insn "xorsi3_5200"
4067 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4068 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4069 (match_operand:SI 2 "general_operand" "d,Ks")))]
4073 (define_insn "xorhi3"
4074 [(set (match_operand:HI 0 "general_operand" "=dm")
4075 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4076 (match_operand:HI 2 "general_operand" "dn")))]
4081 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4082 (xor:HI (match_dup 0)
4083 (match_operand:HI 1 "general_operand" "dn")))]
4088 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4089 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4094 (define_insn "xorqi3"
4095 [(set (match_operand:QI 0 "general_operand" "=dm")
4096 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4097 (match_operand:QI 2 "general_operand" "dn")))]
4102 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4103 (xor:QI (match_dup 0)
4104 (match_operand:QI 1 "general_operand" "dn")))]
4109 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4110 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4115 ;; negation instructions
4117 (define_expand "negdi2"
4118 [(set (match_operand:DI 0 "general_operand" "")
4119 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4124 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4126 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4130 (define_insn "negdi2_internal"
4131 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4132 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4136 if (which_alternative == 0)
4137 return \"neg%.l %0\;negx%.l %0\";
4138 if (GET_CODE (operands[0]) == REG)
4139 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4141 operands[1] = adj_offsettable_operand (operands[0], 4);
4142 if (ADDRESS_REG_P (operands[0]))
4143 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4145 return \"neg%.l %1\;negx%.l %0\";
4148 (define_insn "negdi2_5200"
4149 [(set (match_operand:DI 0 "general_operand" "=d")
4150 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4154 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4155 return \"neg%.l %1\;negx%.l %0\";
4158 (define_expand "negsi2"
4159 [(set (match_operand:SI 0 "general_operand" "")
4160 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4165 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4167 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4171 (define_insn "negsi2_internal"
4172 [(set (match_operand:SI 0 "general_operand" "=dm")
4173 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4177 (define_insn "negsi2_5200"
4178 [(set (match_operand:SI 0 "general_operand" "=d")
4179 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4183 (define_insn "neghi2"
4184 [(set (match_operand:HI 0 "general_operand" "=dm")
4185 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4190 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4191 (neg:HI (match_dup 0)))]
4195 (define_insn "negqi2"
4196 [(set (match_operand:QI 0 "general_operand" "=dm")
4197 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4202 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4203 (neg:QI (match_dup 0)))]
4207 ;; If using software floating point, just flip the sign bit.
4209 (define_expand "negsf2"
4210 [(set (match_operand:SF 0 "general_operand" "")
4211 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4215 if (!TARGET_FPA && !TARGET_68881)
4220 target = operand_subword_force (operands[0], 0, SFmode);
4221 result = expand_binop (SImode, xor_optab,
4222 operand_subword_force (operands[1], 0, SFmode),
4223 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4227 if (result != target)
4228 emit_move_insn (result, target);
4230 /* Make a place for REG_EQUAL. */
4231 emit_move_insn (operands[0], operands[0]);
4237 [(set (match_operand:SF 0 "general_operand" "=x,y")
4238 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4243 [(set (match_operand:SF 0 "general_operand" "=f,d")
4244 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4248 if (DATA_REG_P (operands[0]))
4250 operands[1] = GEN_INT (31);
4251 return \"bchg %1,%0\";
4253 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4254 return \"f%$neg%.x %1,%0\";
4255 return \"f%$neg%.s %f1,%0\";
4258 (define_expand "negdf2"
4259 [(set (match_operand:DF 0 "general_operand" "")
4260 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4264 if (!TARGET_FPA && !TARGET_68881)
4271 target = operand_subword (operands[0], 0, 1, DFmode);
4272 result = expand_binop (SImode, xor_optab,
4273 operand_subword_force (operands[1], 0, DFmode),
4274 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4278 if (result != target)
4279 emit_move_insn (result, target);
4281 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4282 operand_subword_force (operands[1], 1, DFmode));
4284 insns = get_insns ();
4287 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4293 [(set (match_operand:DF 0 "general_operand" "=x,y")
4294 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4299 [(set (match_operand:DF 0 "general_operand" "=f,d")
4300 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4304 if (DATA_REG_P (operands[0]))
4306 operands[1] = GEN_INT (31);
4307 return \"bchg %1,%0\";
4309 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4310 return \"f%&neg%.x %1,%0\";
4311 return \"f%&neg%.d %f1,%0\";
4314 ;; Sqrt instruction for the 68881
4316 (define_insn "sqrtsf2"
4317 [(set (match_operand:SF 0 "general_operand" "=f")
4318 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4322 if (FP_REG_P (operands[1]))
4323 return \"f%$sqrt%.x %1,%0\";
4325 return \"f%$sqrt%.s %1,%0\";
4328 (define_insn "sqrtdf2"
4329 [(set (match_operand:DF 0 "general_operand" "=f")
4330 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4334 if (FP_REG_P (operands[1]))
4335 return \"f%&sqrt%.x %1,%0\";
4337 return \"f%&sqrt%.d %1,%0\";
4340 ;; Absolute value instructions
4341 ;; If using software floating point, just zero the sign bit.
4343 (define_expand "abssf2"
4344 [(set (match_operand:SF 0 "general_operand" "")
4345 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4349 if (!TARGET_FPA && !TARGET_68881)
4354 target = operand_subword_force (operands[0], 0, SFmode);
4355 result = expand_binop (SImode, and_optab,
4356 operand_subword_force (operands[1], 0, SFmode),
4357 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4361 if (result != target)
4362 emit_move_insn (result, target);
4364 /* Make a place for REG_EQUAL. */
4365 emit_move_insn (operands[0], operands[0]);
4371 [(set (match_operand:SF 0 "general_operand" "=x,y")
4372 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4377 [(set (match_operand:SF 0 "general_operand" "=f")
4378 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4382 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4383 return \"f%$abs%.x %1,%0\";
4384 return \"f%$abs%.s %f1,%0\";
4387 (define_expand "absdf2"
4388 [(set (match_operand:DF 0 "general_operand" "")
4389 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4393 if (!TARGET_FPA && !TARGET_68881)
4400 target = operand_subword (operands[0], 0, 1, DFmode);
4401 result = expand_binop (SImode, and_optab,
4402 operand_subword_force (operands[1], 0, DFmode),
4403 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4407 if (result != target)
4408 emit_move_insn (result, target);
4410 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4411 operand_subword_force (operands[1], 1, DFmode));
4413 insns = get_insns ();
4416 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4422 [(set (match_operand:DF 0 "general_operand" "=x,y")
4423 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4428 [(set (match_operand:DF 0 "general_operand" "=f")
4429 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4433 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4434 return \"f%&abs%.x %1,%0\";
4435 return \"f%&abs%.d %f1,%0\";
4438 ;; one complement instructions
4440 ;; "one_cmpldi2" is mainly here to help combine().
4441 (define_insn "one_cmpldi2"
4442 [(set (match_operand:DI 0 "general_operand" "=dm")
4443 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4448 if (GET_CODE (operands[0]) == REG)
4449 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4450 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4451 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4452 operands[1] = operands[0];
4454 operands[1] = adj_offsettable_operand (operands[0], 4);
4455 return \"not%.l %1\;not%.l %0\";
4458 (define_expand "one_cmplsi2"
4459 [(set (match_operand:SI 0 "general_operand" "")
4460 (not:SI (match_operand:SI 1 "general_operand" "")))]
4465 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4467 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4471 (define_insn "one_cmplsi2_internal"
4472 [(set (match_operand:SI 0 "general_operand" "=dm")
4473 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4477 (define_insn "one_cmplsi2_5200"
4478 [(set (match_operand:SI 0 "general_operand" "=d")
4479 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4483 (define_insn "one_cmplhi2"
4484 [(set (match_operand:HI 0 "general_operand" "=dm")
4485 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4490 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4491 (not:HI (match_dup 0)))]
4495 (define_insn "one_cmplqi2"
4496 [(set (match_operand:QI 0 "general_operand" "=dm")
4497 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4502 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4503 (not:QI (match_dup 0)))]
4507 ;; arithmetic shift instructions
4508 ;; We don't need the shift memory by 1 bit instruction
4510 (define_insn "ashldi_extsi"
4511 [(set (match_operand:DI 0 "general_operand" "=ro")
4513 (match_operator:DI 2 "extend_operator"
4514 [(match_operand:SI 1 "general_operand" "rm")])
4520 if (GET_CODE (operands[0]) == REG)
4521 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4523 operands[2] = adj_offsettable_operand (operands[0], 4);
4524 if (ADDRESS_REG_P (operands[0]))
4525 return \"move%.l %1,%0\;sub%.l %2,%2\";
4527 return \"move%.l %1,%0\;clr%.l %2\";
4530 (define_insn "ashldi_sexthi"
4531 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4532 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4534 (clobber (match_scratch:SI 2 "=a,X"))]
4539 if (GET_CODE (operands[0]) == MEM)
4541 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4542 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4543 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4544 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4547 operands[3] = adj_offsettable_operand (operands[0], 4);
4548 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4551 else if (DATA_REG_P (operands[0]))
4552 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4554 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4557 (define_insn "ashldi_const32"
4558 [(set (match_operand:DI 0 "general_operand" "=rm")
4559 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4565 if (GET_CODE (operands[1]) == REG)
4566 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4568 operands[3] = adj_offsettable_operand (operands[1], 4);
4569 if (GET_CODE (operands[0]) == REG)
4570 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4571 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4572 return \"clr%.l %0\;move%.l %3,%0\";
4573 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4574 return \"move%.l %3,%0\;clr%.l %0\";
4576 operands[2] = adj_offsettable_operand (operands[0], 4);
4577 if (ADDRESS_REG_P (operands[2]))
4578 return \"move%.l %3,%0\;sub%.l %2,%2\";
4580 return \"move%.l %3,%0\;clr%.l %2\";
4583 ;; The predicate below must be general_operand, because ashldi3 allows that
4584 (define_insn "ashldi_const"
4585 [(set (match_operand:DI 0 "general_operand" "=d")
4586 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4587 (match_operand 2 "const_int_operand" "n")))]
4589 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4590 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4591 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4594 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4595 if (INTVAL (operands[2]) == 1)
4596 return \"add%.l %1,%1\;addx%.l %0,%0\";
4597 else if (INTVAL (operands[2]) == 8)
4598 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4599 else if (INTVAL (operands[2]) == 16)
4600 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4601 else if (INTVAL (operands[2]) == 48)
4602 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4603 else if (INTVAL (operands[2]) == 2)
4604 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4605 else if (INTVAL (operands[2]) == 3)
4606 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4607 else /* 32 < INTVAL (operands[2]) <= 63 */
4609 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4610 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4611 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4612 return \"mov%.l %1,%0\;moveq %#0,%1\";
4616 (define_expand "ashldi3"
4617 [(set (match_operand:DI 0 "general_operand" "")
4618 (ashift:DI (match_operand:DI 1 "general_operand" "")
4619 (match_operand 2 "const_int_operand" "")))]
4623 /* ??? This is a named pattern like this is not allowed to FAIL based
4625 if (GET_CODE (operands[2]) != CONST_INT
4626 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4627 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4628 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4632 ;; On most 68k models, this makes faster code in a special case.
4634 (define_insn "ashlsi_16"
4635 [(set (match_operand:SI 0 "register_operand" "=d")
4636 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4642 return \"swap %0\;clr%.w %0\";
4645 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4646 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4648 ;; On the 68000, this makes faster code in a special case.
4650 (define_insn "ashlsi_17_24"
4651 [(set (match_operand:SI 0 "register_operand" "=d")
4652 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4653 (match_operand:SI 2 "const_int_operand" "n")))]
4654 "(! TARGET_68020 && !TARGET_5200
4655 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4660 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4661 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4664 (define_insn "ashlsi3"
4665 [(set (match_operand:SI 0 "register_operand" "=d")
4666 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4667 (match_operand:SI 2 "general_operand" "dI")))]
4671 if (operands[2] == const1_rtx)
4673 cc_status.flags = CC_NO_OVERFLOW;
4674 return \"add%.l %0,%0\";
4676 return \"lsl%.l %2,%0\";
4679 (define_insn "ashlhi3"
4680 [(set (match_operand:HI 0 "register_operand" "=d")
4681 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4682 (match_operand:HI 2 "general_operand" "dI")))]
4687 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4688 (ashift:HI (match_dup 0)
4689 (match_operand:HI 1 "general_operand" "dI")))]
4693 (define_insn "ashlqi3"
4694 [(set (match_operand:QI 0 "register_operand" "=d")
4695 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4696 (match_operand:QI 2 "general_operand" "dI")))]
4701 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4702 (ashift:QI (match_dup 0)
4703 (match_operand:QI 1 "general_operand" "dI")))]
4707 ;; On most 68k models, this makes faster code in a special case.
4709 (define_insn "ashrsi_16"
4710 [(set (match_operand:SI 0 "register_operand" "=d")
4711 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4714 "swap %0\;ext%.l %0")
4716 ;; On the 68000, this makes faster code in a special case.
4719 [(set (match_operand:SI 0 "register_operand" "=d")
4720 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4721 (match_operand:SI 2 "const_int_operand" "n")))]
4722 "(! TARGET_68020 && !TARGET_5200
4723 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4726 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4727 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4730 (define_insn "subreghi1ashrdi_const32"
4731 [(set (match_operand:HI 0 "general_operand" "=rm")
4732 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4733 (const_int 32)) 4))]
4737 if (GET_CODE (operands[1]) != REG)
4738 operands[1] = adj_offsettable_operand (operands[1], 2);
4739 return \"move%.w %1,%0\";
4742 (define_insn "subregsi1ashrdi_const32"
4743 [(set (match_operand:SI 0 "general_operand" "=rm")
4744 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4745 (const_int 32)) 4))]
4749 return \"move%.l %1,%0\";
4752 (define_insn "ashrdi_const32"
4753 [(set (match_operand:DI 0 "register_operand" "=d")
4754 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4760 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4762 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4764 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4767 (define_insn "ashrdi_const32_mem"
4768 [(set (match_operand:DI 0 "general_operand" "=o,<")
4769 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4771 (clobber (match_scratch:SI 2 "=d,d"))]
4776 if (which_alternative == 1)
4777 operands[3] = operands[0];
4779 operands[3] = adj_offsettable_operand (operands[0], 4);
4781 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4783 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4786 ;; The predicate below must be general_operand, because ashrdi3 allows that
4787 (define_insn "ashrdi_const"
4788 [(set (match_operand:DI 0 "general_operand" "=d")
4789 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4790 (match_operand 2 "const_int_operand" "n")))]
4792 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4793 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4794 || INTVAL (operands[2]) == 31
4795 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4798 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4799 if (INTVAL (operands[2]) == 63)
4800 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4802 if (INTVAL (operands[2]) == 1)
4803 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4804 else if (INTVAL (operands[2]) == 8)
4805 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4806 else if (INTVAL (operands[2]) == 16)
4807 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4808 else if (INTVAL (operands[2]) == 48)
4809 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4810 else if (INTVAL (operands[2]) == 31)
4811 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4812 else if (INTVAL (operands[2]) == 2)
4813 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4814 else if (INTVAL (operands[2]) == 3)
4815 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4816 else /* 32 < INTVAL (operands[2]) <= 63 */
4818 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4819 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4820 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4821 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4822 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4823 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4827 (define_expand "ashrdi3"
4828 [(set (match_operand:DI 0 "general_operand" "")
4829 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4830 (match_operand 2 "const_int_operand" "")))]
4834 /* ??? This is a named pattern like this is not allowed to FAIL based
4836 if (GET_CODE (operands[2]) != CONST_INT
4837 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4838 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4839 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4843 ;; On all 68k models, this makes faster code in a special case.
4845 (define_insn "ashrsi_31"
4846 [(set (match_operand:SI 0 "register_operand" "=d")
4847 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4852 return \"add%.l %0,%0\;subx%.l %0,%0\";
4855 (define_insn "ashrsi3"
4856 [(set (match_operand:SI 0 "register_operand" "=d")
4857 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4858 (match_operand:SI 2 "general_operand" "dI")))]
4862 (define_insn "ashrhi3"
4863 [(set (match_operand:HI 0 "register_operand" "=d")
4864 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4865 (match_operand:HI 2 "general_operand" "dI")))]
4870 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4871 (ashiftrt:HI (match_dup 0)
4872 (match_operand:HI 1 "general_operand" "dI")))]
4876 (define_insn "ashrqi3"
4877 [(set (match_operand:QI 0 "register_operand" "=d")
4878 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4879 (match_operand:QI 2 "general_operand" "dI")))]
4884 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4885 (ashiftrt:QI (match_dup 0)
4886 (match_operand:QI 1 "general_operand" "dI")))]
4890 ;; logical shift instructions
4892 ;; commented out because of reload problems in 950612-1.c
4895 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4896 ;; (const_int 32)) 4))
4897 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4898 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4899 ;; (const_int 32)) 4))]
4903 ;; return \"move%.l %0,%1\";
4908 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4909 ;; (const_int 32)) 0))
4910 ;; (set (match_operand:DI 1 "general_operand" "=do")
4911 ;; (lshiftrt:DI (match_dup 0)
4912 ;; (const_int 32)))]
4916 ;; if (GET_CODE (operands[1]) == REG)
4917 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4919 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4920 ;; return \"move%.l %0,%2\;clr%.l %1\";
4923 (define_insn "subreg1lshrdi_const32"
4924 [(set (match_operand:SI 0 "general_operand" "=rm")
4925 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4926 (const_int 32)) 4))]
4930 return \"move%.l %1,%0\";
4933 (define_insn "lshrdi_const32"
4934 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4935 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4941 if (which_alternative == 1)
4942 return \"move%.l %1,%0\;clr%.l %0\";
4943 if (which_alternative == 2)
4944 return \"clr%.l %0\;move%.l %1,%0\";
4945 if (GET_CODE (operands[0]) == REG)
4946 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4948 operands[2] = adj_offsettable_operand (operands[0], 4);
4949 if (GET_CODE (operands[1]) == REG)
4950 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4952 operands[3] = adj_offsettable_operand (operands[1], 4);
4953 if (ADDRESS_REG_P (operands[0]))
4954 return \"move%.l %1,%2\;sub%.l %0,%0\";
4956 return \"move%.l %1,%2\;clr%.l %0\";
4959 ;; The predicate below must be general_operand, because lshrdi3 allows that
4960 (define_insn "lshrdi_const"
4961 [(set (match_operand:DI 0 "general_operand" "=d")
4962 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4963 (match_operand 2 "const_int_operand" "n")))]
4965 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4966 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4967 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4970 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4971 if (INTVAL (operands[2]) == 63)
4972 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4974 if (INTVAL (operands[2]) == 1)
4975 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4976 else if (INTVAL (operands[2]) == 8)
4977 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4978 else if (INTVAL (operands[2]) == 16)
4979 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4980 else if (INTVAL (operands[2]) == 48)
4981 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4982 else if (INTVAL (operands[2]) == 2)
4983 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4984 else if (INTVAL (operands[2]) == 3)
4985 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4986 else /* 32 < INTVAL (operands[2]) <= 63 */
4988 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4989 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4990 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4991 return \"mov%.l %0,%1\;moveq %#0,%0\";
4995 (define_expand "lshrdi3"
4996 [(set (match_operand:DI 0 "general_operand" "")
4997 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4998 (match_operand 2 "const_int_operand" "")))]
5002 /* ??? This is a named pattern like this is not allowed to FAIL based
5004 if (GET_CODE (operands[2]) != CONST_INT
5005 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5006 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5007 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5011 ;; On all 68k models, this makes faster code in a special case.
5013 (define_insn "lshrsi_31"
5014 [(set (match_operand:SI 0 "register_operand" "=d")
5015 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5020 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5023 ;; On most 68k models, this makes faster code in a special case.
5025 (define_insn "lshrsi_16"
5026 [(set (match_operand:SI 0 "register_operand" "=d")
5027 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5033 return \"clr%.w %0\;swap %0\";
5036 ;; On the 68000, this makes faster code in a special case.
5038 (define_insn "lshrsi_17_24"
5039 [(set (match_operand:SI 0 "register_operand" "=d")
5040 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5041 (match_operand:SI 2 "const_int_operand" "n")))]
5042 "(! TARGET_68020 && !TARGET_5200
5043 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5046 /* I think lsr%.w sets the CC properly. */
5047 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5048 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5051 (define_insn "lshrsi3"
5052 [(set (match_operand:SI 0 "register_operand" "=d")
5053 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5054 (match_operand:SI 2 "general_operand" "dI")))]
5058 (define_insn "lshrhi3"
5059 [(set (match_operand:HI 0 "register_operand" "=d")
5060 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5061 (match_operand:HI 2 "general_operand" "dI")))]
5066 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5067 (lshiftrt:HI (match_dup 0)
5068 (match_operand:HI 1 "general_operand" "dI")))]
5072 (define_insn "lshrqi3"
5073 [(set (match_operand:QI 0 "register_operand" "=d")
5074 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5075 (match_operand:QI 2 "general_operand" "dI")))]
5080 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5081 (lshiftrt:QI (match_dup 0)
5082 (match_operand:QI 1 "general_operand" "dI")))]
5086 ;; rotate instructions
5088 (define_insn "rotlsi3"
5089 [(set (match_operand:SI 0 "register_operand" "=d")
5090 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5091 (match_operand:SI 2 "general_operand" "dINO")))]
5095 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5097 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5099 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5100 return \"ror%.l %2,%0\";
5103 return \"rol%.l %2,%0\";
5106 (define_insn "rotlhi3"
5107 [(set (match_operand:HI 0 "register_operand" "=d")
5108 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5109 (match_operand:HI 2 "general_operand" "dIP")))]
5113 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5115 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5116 return \"ror%.w %2,%0\";
5119 return \"rol%.w %2,%0\";
5123 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5124 (rotate:HI (match_dup 0)
5125 (match_operand:HI 1 "general_operand" "dIP")))]
5129 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5131 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5132 return \"ror%.w %2,%0\";
5135 return \"rol%.w %2,%0\";
5138 (define_insn "rotlqi3"
5139 [(set (match_operand:QI 0 "register_operand" "=d")
5140 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5141 (match_operand:QI 2 "general_operand" "dI")))]
5145 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5147 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5148 return \"ror%.b %2,%0\";
5151 return \"rol%.b %2,%0\";
5155 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5156 (rotate:QI (match_dup 0)
5157 (match_operand:QI 1 "general_operand" "dI")))]
5161 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5163 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5164 return \"ror%.b %2,%0\";
5167 return \"rol%.b %2,%0\";
5170 (define_insn "rotrsi3"
5171 [(set (match_operand:SI 0 "register_operand" "=d")
5172 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5173 (match_operand:SI 2 "general_operand" "dI")))]
5177 (define_insn "rotrhi3"
5178 [(set (match_operand:HI 0 "register_operand" "=d")
5179 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5180 (match_operand:HI 2 "general_operand" "dI")))]
5185 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5186 (rotatert:HI (match_dup 0)
5187 (match_operand:HI 1 "general_operand" "dI")))]
5191 (define_insn "rotrqi3"
5192 [(set (match_operand:QI 0 "register_operand" "=d")
5193 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5194 (match_operand:QI 2 "general_operand" "dI")))]
5199 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5200 (rotatert:QI (match_dup 0)
5201 (match_operand:QI 1 "general_operand" "dI")))]
5206 ;; Bit set/clear in memory byte.
5208 ;; set bit, bit number is int
5209 (define_insn "bsetmemqi"
5210 [(set (match_operand:QI 0 "memory_operand" "+m")
5211 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5212 (match_operand:SI 1 "general_operand" "d")) 0)
5218 return \"bset %1,%0\";
5221 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5223 [(set (match_operand:QI 0 "memory_operand" "+m")
5224 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5225 (match_operator:SI 2 "extend_operator"
5226 [(match_operand 1 "general_operand" "d")])) 0)
5232 return \"bset %1,%0\";
5235 ;; clear bit, bit number is int
5236 (define_insn "bclrmemqi"
5237 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5239 (minus:SI (const_int 7)
5240 (match_operand:SI 1 "general_operand" "d")))
5246 return \"bclr %1,%0\";
5249 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5251 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5253 (minus:SI (const_int 7)
5254 (match_operator:SI 2 "extend_operator"
5255 [(match_operand 1 "general_operand" "d")])))
5261 return \"bclr %1,%0\";
5264 ;; Special cases of bit-field insns which we should
5265 ;; recognize in preference to the general case.
5266 ;; These handle aligned 8-bit and 16-bit fields,
5267 ;; which can usually be done with move instructions.
5270 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5271 ; alignment of structure members is specified.
5273 ; The move is allowed to be odd byte aligned, because that's still faster
5274 ; than an odd byte aligned bit field instruction.
5277 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5279 (match_operand:SI 1 "const_int_operand" "n"))
5280 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5281 "TARGET_68020 && TARGET_BITFIELD
5282 && (INTVAL (operands[1]) % 8) == 0
5283 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5287 = adj_offsettable_operand (operands[0], INTVAL (operands[1]) / 8);
5289 return \"move%.l %2,%0\";
5293 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5294 (match_operand:SI 1 "const_int_operand" "n")
5295 (match_operand:SI 2 "const_int_operand" "n"))
5296 (match_operand:SI 3 "register_operand" "d"))]
5297 "TARGET_68020 && TARGET_BITFIELD
5298 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5299 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5300 && (GET_CODE (operands[0]) == REG
5301 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5304 if (REG_P (operands[0]))
5306 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5307 return \"bfins %3,%0{%b2:%b1}\";
5311 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5313 if (GET_CODE (operands[3]) == MEM)
5314 operands[3] = adj_offsettable_operand (operands[3],
5315 (32 - INTVAL (operands[1])) / 8);
5316 if (INTVAL (operands[1]) == 8)
5317 return \"move%.b %3,%0\";
5318 return \"move%.w %3,%0\";
5323 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5324 ; alignment of structure members is specified.
5326 ; The move is allowed to be odd byte aligned, because that's still faster
5327 ; than an odd byte aligned bit field instruction.
5330 [(set (match_operand:SI 0 "general_operand" "=rm")
5331 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5333 (match_operand:SI 2 "const_int_operand" "n")))]
5334 "TARGET_68020 && TARGET_BITFIELD
5335 && (INTVAL (operands[2]) % 8) == 0
5336 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5340 = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
5342 return \"move%.l %1,%0\";
5346 [(set (match_operand:SI 0 "general_operand" "=&d")
5347 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5348 (match_operand:SI 2 "const_int_operand" "n")
5349 (match_operand:SI 3 "const_int_operand" "n")))]
5350 "TARGET_68020 && TARGET_BITFIELD
5351 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5352 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5353 && (GET_CODE (operands[1]) == REG
5354 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5357 cc_status.flags |= CC_NOT_NEGATIVE;
5358 if (REG_P (operands[1]))
5360 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5361 return \"bfextu %1{%b3:%b2},%0\";
5365 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5367 output_asm_insn (\"clr%.l %0\", operands);
5368 if (GET_CODE (operands[0]) == MEM)
5369 operands[0] = adj_offsettable_operand (operands[0],
5370 (32 - INTVAL (operands[1])) / 8);
5371 if (INTVAL (operands[2]) == 8)
5372 return \"move%.b %1,%0\";
5373 return \"move%.w %1,%0\";
5377 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5378 ; alignment of structure members is specified.
5380 ; The move is allowed to be odd byte aligned, because that's still faster
5381 ; than an odd byte aligned bit field instruction.
5384 [(set (match_operand:SI 0 "general_operand" "=rm")
5385 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5387 (match_operand:SI 2 "const_int_operand" "n")))]
5388 "TARGET_68020 && TARGET_BITFIELD
5389 && (INTVAL (operands[2]) % 8) == 0
5390 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5394 = adj_offsettable_operand (operands[1], INTVAL (operands[2]) / 8);
5396 return \"move%.l %1,%0\";
5400 [(set (match_operand:SI 0 "general_operand" "=d")
5401 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5402 (match_operand:SI 2 "const_int_operand" "n")
5403 (match_operand:SI 3 "const_int_operand" "n")))]
5404 "TARGET_68020 && TARGET_BITFIELD
5405 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5406 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5407 && (GET_CODE (operands[1]) == REG
5408 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5411 if (REG_P (operands[1]))
5413 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5414 return \"bfexts %1{%b3:%b2},%0\";
5418 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5420 if (INTVAL (operands[2]) == 8)
5421 return \"move%.b %1,%0\;extb%.l %0\";
5422 return \"move%.w %1,%0\;ext%.l %0\";
5425 ;; Bit field instructions, general cases.
5426 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5427 ;; so that its address is reloaded.
5429 (define_expand "extv"
5430 [(set (match_operand:SI 0 "general_operand" "")
5431 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5432 (match_operand:SI 2 "general_operand" "")
5433 (match_operand:SI 3 "general_operand" "")))]
5434 "TARGET_68020 && TARGET_BITFIELD"
5438 [(set (match_operand:SI 0 "general_operand" "=d")
5439 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5440 (match_operand:SI 2 "general_operand" "di")
5441 (match_operand:SI 3 "general_operand" "di")))]
5442 "TARGET_68020 && TARGET_BITFIELD"
5443 "bfexts %1{%b3:%b2},%0")
5445 (define_expand "extzv"
5446 [(set (match_operand:SI 0 "general_operand" "")
5447 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5448 (match_operand:SI 2 "general_operand" "")
5449 (match_operand:SI 3 "general_operand" "")))]
5450 "TARGET_68020 && TARGET_BITFIELD"
5454 [(set (match_operand:SI 0 "general_operand" "=d,d")
5455 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5456 (match_operand:SI 2 "general_operand" "di,di")
5457 (match_operand:SI 3 "general_operand" "di,di")))]
5458 "TARGET_68020 && TARGET_BITFIELD"
5461 if (GET_CODE (operands[2]) == CONST_INT)
5463 if (INTVAL (operands[2]) != 32)
5464 cc_status.flags |= CC_NOT_NEGATIVE;
5470 return \"bfextu %1{%b3:%b2},%0\";
5474 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5475 (match_operand:SI 1 "general_operand" "di")
5476 (match_operand:SI 2 "general_operand" "di"))
5477 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5478 (match_operand 3 "const_int_operand" "n")))]
5479 "TARGET_68020 && TARGET_BITFIELD
5480 && (INTVAL (operands[3]) == -1
5481 || (GET_CODE (operands[1]) == CONST_INT
5482 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5486 return \"bfchg %0{%b2:%b1}\";
5490 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5491 (match_operand:SI 1 "general_operand" "di")
5492 (match_operand:SI 2 "general_operand" "di"))
5494 "TARGET_68020 && TARGET_BITFIELD"
5498 return \"bfclr %0{%b2:%b1}\";
5502 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5503 (match_operand:SI 1 "general_operand" "di")
5504 (match_operand:SI 2 "general_operand" "di"))
5506 "TARGET_68020 && TARGET_BITFIELD"
5510 return \"bfset %0{%b2:%b1}\";
5513 (define_expand "insv"
5514 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5515 (match_operand:SI 1 "general_operand" "")
5516 (match_operand:SI 2 "general_operand" ""))
5517 (match_operand:SI 3 "register_operand" ""))]
5518 "TARGET_68020 && TARGET_BITFIELD"
5522 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5523 (match_operand:SI 1 "general_operand" "di")
5524 (match_operand:SI 2 "general_operand" "di"))
5525 (match_operand:SI 3 "register_operand" "d"))]
5526 "TARGET_68020 && TARGET_BITFIELD"
5527 "bfins %3,%0{%b2:%b1}")
5529 ;; Now recognize bit field insns that operate on registers
5530 ;; (or at least were intended to do so).
5533 [(set (match_operand:SI 0 "general_operand" "=d")
5534 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5535 (match_operand:SI 2 "general_operand" "di")
5536 (match_operand:SI 3 "general_operand" "di")))]
5537 "TARGET_68020 && TARGET_BITFIELD"
5538 "bfexts %1{%b3:%b2},%0")
5541 [(set (match_operand:SI 0 "general_operand" "=d")
5542 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5543 (match_operand:SI 2 "general_operand" "di")
5544 (match_operand:SI 3 "general_operand" "di")))]
5545 "TARGET_68020 && TARGET_BITFIELD"
5548 if (GET_CODE (operands[2]) == CONST_INT)
5550 if (INTVAL (operands[2]) != 32)
5551 cc_status.flags |= CC_NOT_NEGATIVE;
5557 return \"bfextu %1{%b3:%b2},%0\";
5561 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5562 (match_operand:SI 1 "general_operand" "di")
5563 (match_operand:SI 2 "general_operand" "di"))
5565 "TARGET_68020 && TARGET_BITFIELD"
5569 return \"bfclr %0{%b2:%b1}\";
5573 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5574 (match_operand:SI 1 "general_operand" "di")
5575 (match_operand:SI 2 "general_operand" "di"))
5577 "TARGET_68020 && TARGET_BITFIELD"
5581 return \"bfset %0{%b2:%b1}\";
5585 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5586 (match_operand:SI 1 "general_operand" "di")
5587 (match_operand:SI 2 "general_operand" "di"))
5588 (match_operand:SI 3 "register_operand" "d"))]
5589 "TARGET_68020 && TARGET_BITFIELD"
5593 /* These special cases are now recognized by a specific pattern. */
5594 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5595 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5596 return \"move%.w %3,%0\";
5597 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5598 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5599 return \"move%.b %3,%0\";
5601 return \"bfins %3,%0{%b2:%b1}\";
5604 ;; Special patterns for optimizing bit-field instructions.
5608 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5609 (match_operand:SI 1 "const_int_operand" "n")
5610 (match_operand:SI 2 "general_operand" "di")))]
5611 "TARGET_68020 && TARGET_BITFIELD"
5614 if (operands[1] == const1_rtx
5615 && GET_CODE (operands[2]) == CONST_INT)
5617 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5618 return output_btst (operands,
5619 GEN_INT (width - INTVAL (operands[2])),
5620 operands[0], insn, 1000);
5621 /* Pass 1000 as SIGNPOS argument so that btst will
5622 not think we are testing the sign bit for an `and'
5623 and assume that nonzero implies a negative result. */
5625 if (INTVAL (operands[1]) != 32)
5626 cc_status.flags = CC_NOT_NEGATIVE;
5627 return \"bftst %0{%b2:%b1}\";
5631 ;;; now handle the register cases
5634 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5635 (match_operand:SI 1 "const_int_operand" "n")
5636 (match_operand:SI 2 "general_operand" "di")))]
5637 "TARGET_68020 && TARGET_BITFIELD"
5640 if (operands[1] == const1_rtx
5641 && GET_CODE (operands[2]) == CONST_INT)
5643 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5644 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5645 operands[0], insn, 1000);
5646 /* Pass 1000 as SIGNPOS argument so that btst will
5647 not think we are testing the sign bit for an `and'
5648 and assume that nonzero implies a negative result. */
5650 if (INTVAL (operands[1]) != 32)
5651 cc_status.flags = CC_NOT_NEGATIVE;
5652 return \"bftst %0{%b2:%b1}\";
5655 (define_insn "scc0_di"
5656 [(set (match_operand:QI 0 "general_operand" "=dm")
5657 (match_operator 1 "valid_dbcc_comparison_p"
5658 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5662 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5665 (define_insn "scc0_di_5200"
5666 [(set (match_operand:QI 0 "general_operand" "=d")
5667 (match_operator 1 "valid_dbcc_comparison_p"
5668 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5672 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5675 (define_insn "scc_di"
5676 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5677 (match_operator 1 "valid_dbcc_comparison_p"
5678 [(match_operand:DI 2 "general_operand" "ro,r")
5679 (match_operand:DI 3 "general_operand" "r,ro")]))]
5683 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5686 (define_insn "scc_di_5200"
5687 [(set (match_operand:QI 0 "general_operand" "=d,d")
5688 (match_operator 1 "valid_dbcc_comparison_p"
5689 [(match_operand:DI 2 "general_operand" "ro,r")
5690 (match_operand:DI 3 "general_operand" "r,ro")]))]
5694 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5697 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5698 ;; memory, but we cannot allow it to be in memory in case the address
5699 ;; needs to be reloaded.
5701 (define_expand "seq"
5702 [(set (match_operand:QI 0 "register_operand" "")
5703 (eq:QI (cc0) (const_int 0)))]
5707 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5709 m68k_last_compare_had_fp_operands = 0;
5715 [(set (match_operand:QI 0 "register_operand" "=d")
5716 (eq:QI (cc0) (const_int 0)))]
5719 cc_status = cc_prev_status;
5720 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5723 (define_expand "sne"
5724 [(set (match_operand:QI 0 "register_operand" "")
5725 (ne:QI (cc0) (const_int 0)))]
5729 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5731 m68k_last_compare_had_fp_operands = 0;
5737 [(set (match_operand:QI 0 "register_operand" "=d")
5738 (ne:QI (cc0) (const_int 0)))]
5741 cc_status = cc_prev_status;
5742 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5745 (define_expand "sgt"
5746 [(set (match_operand:QI 0 "register_operand" "")
5747 (gt:QI (cc0) (const_int 0)))]
5751 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5753 m68k_last_compare_had_fp_operands = 0;
5759 [(set (match_operand:QI 0 "register_operand" "=d")
5760 (gt:QI (cc0) (const_int 0)))]
5763 cc_status = cc_prev_status;
5764 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5767 (define_expand "sgtu"
5768 [(set (match_operand:QI 0 "register_operand" "")
5769 (gtu:QI (cc0) (const_int 0)))]
5774 [(set (match_operand:QI 0 "register_operand" "=d")
5775 (gtu:QI (cc0) (const_int 0)))]
5778 cc_status = cc_prev_status;
5779 return \"shi %0\"; ")
5781 (define_expand "slt"
5782 [(set (match_operand:QI 0 "register_operand" "")
5783 (lt:QI (cc0) (const_int 0)))]
5787 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5789 m68k_last_compare_had_fp_operands = 0;
5795 [(set (match_operand:QI 0 "register_operand" "=d")
5796 (lt:QI (cc0) (const_int 0)))]
5799 cc_status = cc_prev_status;
5800 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5802 (define_expand "sltu"
5803 [(set (match_operand:QI 0 "register_operand" "")
5804 (ltu:QI (cc0) (const_int 0)))]
5809 [(set (match_operand:QI 0 "register_operand" "=d")
5810 (ltu:QI (cc0) (const_int 0)))]
5813 cc_status = cc_prev_status;
5814 return \"scs %0\"; ")
5816 (define_expand "sge"
5817 [(set (match_operand:QI 0 "register_operand" "")
5818 (ge:QI (cc0) (const_int 0)))]
5822 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5824 m68k_last_compare_had_fp_operands = 0;
5830 [(set (match_operand:QI 0 "register_operand" "=d")
5831 (ge:QI (cc0) (const_int 0)))]
5834 cc_status = cc_prev_status;
5835 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5837 (define_expand "sgeu"
5838 [(set (match_operand:QI 0 "register_operand" "")
5839 (geu:QI (cc0) (const_int 0)))]
5844 [(set (match_operand:QI 0 "register_operand" "=d")
5845 (geu:QI (cc0) (const_int 0)))]
5848 cc_status = cc_prev_status;
5849 return \"scc %0\"; ")
5851 (define_expand "sle"
5852 [(set (match_operand:QI 0 "register_operand" "")
5853 (le:QI (cc0) (const_int 0)))]
5857 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5859 m68k_last_compare_had_fp_operands = 0;
5865 [(set (match_operand:QI 0 "register_operand" "=d")
5866 (le:QI (cc0) (const_int 0)))]
5869 cc_status = cc_prev_status;
5870 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5873 (define_expand "sleu"
5874 [(set (match_operand:QI 0 "register_operand" "")
5875 (leu:QI (cc0) (const_int 0)))]
5880 [(set (match_operand:QI 0 "register_operand" "=d")
5881 (leu:QI (cc0) (const_int 0)))]
5884 cc_status = cc_prev_status;
5885 return \"sls %0\"; ")
5887 ;; Basic conditional jump instructions.
5889 (define_insn "beq0_di"
5891 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5893 (label_ref (match_operand 1 "" ","))
5895 (clobber (match_scratch:SI 2 "=d,d"))]
5900 if (which_alternative == 1)
5902 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5904 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5906 if ((cc_prev_status.value1
5907 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5908 || (cc_prev_status.value2
5909 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5911 cc_status = cc_prev_status;
5913 return \"jbeq %l1\";
5918 if (GET_CODE (operands[0]) == REG)
5919 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5921 operands[3] = adj_offsettable_operand (operands[0], 4);
5922 if (! ADDRESS_REG_P (operands[0]))
5924 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5926 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5929 return \"or%.l %0,%2\;jbeq %l1\";
5931 return \"or%.l %0,%2\;jeq %l1\";
5937 return \"or%.l %3,%2\;jbeq %l1\";
5939 return \"or%.l %3,%2\;jeq %l1\";
5944 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5946 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5949 operands[4] = gen_label_rtx();
5950 if (TARGET_68020 || TARGET_5200)
5953 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5955 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5961 #ifdef SGS_CMP_ORDER
5962 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5964 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5967 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5970 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5971 CODE_LABEL_NUMBER (operands[4]));
5975 (define_insn "bne0_di"
5977 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5979 (label_ref (match_operand 1 "" ","))
5981 (clobber (match_scratch:SI 2 "=d,X"))]
5985 if ((cc_prev_status.value1
5986 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5987 || (cc_prev_status.value2
5988 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5990 cc_status = cc_prev_status;
5992 return \"jbne %l1\";
5998 if (GET_CODE (operands[0]) == REG)
5999 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6001 operands[3] = adj_offsettable_operand (operands[0], 4);
6002 if (!ADDRESS_REG_P (operands[0]))
6004 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6006 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6009 return \"or%.l %0,%2\;jbne %l1\";
6011 return \"or%.l %0,%2\;jne %l1\";
6017 return \"or%.l %3,%2\;jbne %l1\";
6019 return \"or%.l %3,%2\;jne %l1\";
6024 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6026 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6029 if (TARGET_68020 || TARGET_5200)
6032 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6034 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6040 #ifdef SGS_CMP_ORDER
6041 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6043 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6046 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6051 (define_insn "bge0_di"
6053 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6055 (label_ref (match_operand 1 "" ""))
6060 if ((cc_prev_status.value1
6061 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6062 || (cc_prev_status.value2
6063 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6065 cc_status = cc_prev_status;
6066 if (cc_status.flags & CC_REVERSED)
6069 return \"jble %l1\";
6077 return \"jbpl %l1\";
6084 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6085 output_asm_insn(\"tst%.l %0\", operands);
6088 /* On an address reg, cmpw may replace cmpl. */
6089 #ifdef SGS_CMP_ORDER
6090 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6092 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6097 return \"jbpl %l1\";
6103 (define_insn "blt0_di"
6105 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6107 (label_ref (match_operand 1 "" ""))
6112 if ((cc_prev_status.value1
6113 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6114 || (cc_prev_status.value2
6115 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6117 cc_status = cc_prev_status;
6118 if (cc_status.flags & CC_REVERSED)
6121 return \"jbgt %l1\";
6129 return \"jbmi %l1\";
6136 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6137 output_asm_insn(\"tst%.l %0\", operands);
6140 /* On an address reg, cmpw may replace cmpl. */
6141 #ifdef SGS_CMP_ORDER
6142 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6144 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6149 return \"jbmi %l1\";
6157 (if_then_else (eq (cc0)
6159 (label_ref (match_operand 0 "" ""))
6165 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6167 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6173 (if_then_else (ne (cc0)
6175 (label_ref (match_operand 0 "" ""))
6181 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6183 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6189 (if_then_else (gt (cc0)
6191 (label_ref (match_operand 0 "" ""))
6196 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6198 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6204 (if_then_else (gtu (cc0)
6206 (label_ref (match_operand 0 "" ""))
6211 return \"jbhi %l0\";
6219 (if_then_else (lt (cc0)
6221 (label_ref (match_operand 0 "" ""))
6226 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6228 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6234 (if_then_else (ltu (cc0)
6236 (label_ref (match_operand 0 "" ""))
6241 return \"jbcs %l0\";
6249 (if_then_else (ge (cc0)
6251 (label_ref (match_operand 0 "" ""))
6256 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6258 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6264 (if_then_else (geu (cc0)
6266 (label_ref (match_operand 0 "" ""))
6271 return \"jbcc %l0\";
6279 (if_then_else (le (cc0)
6281 (label_ref (match_operand 0 "" ""))
6286 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6288 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6294 (if_then_else (leu (cc0)
6296 (label_ref (match_operand 0 "" ""))
6301 return \"jbls %l0\";
6307 ;; Negated conditional jump instructions.
6311 (if_then_else (eq (cc0)
6314 (label_ref (match_operand 0 "" ""))))]
6319 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6321 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6327 (if_then_else (ne (cc0)
6330 (label_ref (match_operand 0 "" ""))))]
6335 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6337 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6343 (if_then_else (gt (cc0)
6346 (label_ref (match_operand 0 "" ""))))]
6350 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6352 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6358 (if_then_else (gtu (cc0)
6361 (label_ref (match_operand 0 "" ""))))]
6365 return \"jbls %l0\";
6373 (if_then_else (lt (cc0)
6376 (label_ref (match_operand 0 "" ""))))]
6380 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6382 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6388 (if_then_else (ltu (cc0)
6391 (label_ref (match_operand 0 "" ""))))]
6395 return \"jbcc %l0\";
6403 (if_then_else (ge (cc0)
6406 (label_ref (match_operand 0 "" ""))))]
6410 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6412 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6418 (if_then_else (geu (cc0)
6421 (label_ref (match_operand 0 "" ""))))]
6425 return \"jbcs %l0\";
6433 (if_then_else (le (cc0)
6436 (label_ref (match_operand 0 "" ""))))]
6440 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6442 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6448 (if_then_else (leu (cc0)
6451 (label_ref (match_operand 0 "" ""))))]
6455 return \"jbhi %l0\";
6461 ;; Unconditional and other jump instructions
6464 (label_ref (match_operand 0 "" "")))]
6468 return \"jbra %l0\";
6474 ;; We support two different ways of handling dispatch tables.
6475 ;; The NeXT uses absolute tables, and other machines use relative.
6476 ;; This define_expand can generate either kind.
6477 (define_expand "tablejump"
6478 [(parallel [(set (pc) (match_operand 0 "" ""))
6479 (use (label_ref (match_operand 1 "" "")))])]
6483 #ifdef CASE_VECTOR_PC_RELATIVE
6484 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6485 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6489 ;; Jump to variable address from dispatch table of absolute addresses.
6491 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6492 (use (label_ref (match_operand 1 "" "")))]
6496 return \"jmp (%0)\";
6502 ;; Jump to variable address from dispatch table of relative addresses.
6506 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6507 (use (label_ref (match_operand 1 "" "")))]
6510 #ifdef ASM_RETURN_CASE_JUMP
6511 ASM_RETURN_CASE_JUMP;
6514 #ifdef ASM_OUTPUT_CASE_LABEL
6516 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6518 return \"jmp 6(%%pc,%0.w)\";
6523 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6525 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6526 #endif /* end !CRDS */
6531 return \"jmp 2(pc,%0.w)\";
6533 return \"jmp 2(%%pc,%0.w)\";
6534 #endif /* end !CRDS */
6541 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6543 return \"extl %0\;jmp pc@(2,%0:l)\";
6549 return \"jmp (2,pc,%0.w)\";
6551 return \"jmp pc@(2,%0:w)\";
6558 ;; Decrement-and-branch insns.
6562 (ne (match_operand:HI 0 "general_operand" "+d*g")
6564 (label_ref (match_operand 1 "" ""))
6567 (plus:HI (match_dup 0)
6573 if (DATA_REG_P (operands[0]))
6574 return \"dbra %0,%l1\";
6575 if (GET_CODE (operands[0]) == MEM)
6579 return \"sub%.w %#1,%0\;jbcc %l1\";
6581 return \"subq%.w %#1,%0\;jbcc %l1\";
6583 #else /* not MOTOROLA */
6584 return \"subqw %#1,%0\;jcc %l1\";
6588 #ifdef SGS_CMP_ORDER
6590 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6592 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6594 #else /* not SGS_CMP_ORDER */
6595 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6597 #else /* not MOTOROLA */
6598 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6605 (ne (match_operand:SI 0 "general_operand" "+d*g")
6607 (label_ref (match_operand 1 "" ""))
6610 (plus:SI (match_dup 0)
6618 if (DATA_REG_P (operands[0]))
6619 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6620 if (GET_CODE (operands[0]) == MEM)
6621 return \"sub%.l %#1,%0\;jbcc %l1\";
6623 if (DATA_REG_P (operands[0]))
6624 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6625 if (GET_CODE (operands[0]) == MEM)
6626 return \"subq%.l %#1,%0\;jbcc %l1\";
6627 #endif /* NO_ADDSUB_Q */
6628 #ifdef SGS_CMP_ORDER
6630 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6632 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6634 #else /* not SGS_CMP_ORDER */
6635 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6636 #endif /* not SGS_CMP_ORDER */
6637 #else /* not MOTOROLA */
6638 if (DATA_REG_P (operands[0]))
6639 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6640 if (GET_CODE (operands[0]) == MEM)
6641 return \"subql %#1,%0\;jcc %l1\";
6642 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6643 #endif /* not MOTOROLA */
6646 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6651 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6654 (label_ref (match_operand 1 "" ""))
6657 (plus:HI (match_dup 0)
6659 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6665 if (DATA_REG_P (operands[0]))
6666 return \"dbra %0,%l1\";
6667 if (GET_CODE (operands[0]) == MEM)
6668 return \"sub%.w %#1,%0\;jbcc %l1\";
6670 if (DATA_REG_P (operands[0]))
6671 return \"dbra %0,%l1\";
6672 if (GET_CODE (operands[0]) == MEM)
6673 return \"subq%.w %#1,%0\;jbcc %l1\";
6675 #ifdef SGS_CMP_ORDER
6677 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6679 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6681 #else /* not SGS_CMP_ORDER */
6682 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6683 #endif /* not SGS_CMP_ORDER */
6684 #else /* not MOTOROLA */
6685 if (DATA_REG_P (operands[0]))
6686 return \"dbra %0,%l1\";
6687 if (GET_CODE (operands[0]) == MEM)
6688 return \"subqw %#1,%0\;jcc %l1\";
6689 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6690 #endif /* not MOTOROLA */
6693 (define_expand "decrement_and_branch_until_zero"
6694 [(parallel [(set (pc)
6696 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6699 (label_ref (match_operand 1 "" ""))
6702 (plus:SI (match_dup 0)
6710 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6713 (label_ref (match_operand 1 "" ""))
6716 (plus:SI (match_dup 0)
6718 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6724 if (DATA_REG_P (operands[0]))
6725 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6726 if (GET_CODE (operands[0]) == MEM)
6727 return \"sub%.l %#1,%0\;jbcc %l1\";
6729 if (DATA_REG_P (operands[0]))
6730 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6731 if (GET_CODE (operands[0]) == MEM)
6732 return \"subq%.l %#1,%0\;jbcc %l1\";
6734 #ifdef SGS_CMP_ORDER
6736 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6738 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6740 #else /* not SGS_CMP_ORDER */
6741 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6742 #endif /* not SGS_CMP_ORDER */
6743 #else /* not MOTOROLA */
6744 if (DATA_REG_P (operands[0]))
6745 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6746 if (GET_CODE (operands[0]) == MEM)
6747 return \"subql %#1,%0\;jcc %l1\";
6748 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6749 #endif /* not MOTOROLA */
6753 ;; For PIC calls, in order to be able to support
6754 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6755 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6757 ;; PIC calls are handled by loading the address of the function into a
6758 ;; register (via movsi), then emitting a register indirect call using
6759 ;; the "jsr" function call syntax.
6761 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6762 ;; operand to the jbsr statement to indicate that this call should
6763 ;; go through the PLT (why? because this is the way that Sun does it).
6765 ;; We have different patterns for PIC calls and non-PIC calls. The
6766 ;; different patterns are only used to choose the right syntax.
6768 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6769 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6770 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6771 ;; section at link time. However, all global objects reference are still
6772 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6773 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6774 ;; We need to have a way to differentiate these two different operands.
6776 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6777 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6778 ;; to be changed to recognize function calls symbol_ref operand as a valid
6779 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6780 ;; avoid the compiler to load this symbol_ref operand into a register.
6781 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6782 ;; since the value is a PC relative offset, not a real address.
6784 ;; All global objects are treated in the similar way as in SUN3. The only
6785 ;; difference is: on m68k svr4, the reference of such global object needs
6786 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6787 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6790 ;; Call subroutine with no return value.
6791 (define_expand "call"
6792 [(call (match_operand:QI 0 "memory_operand" "")
6793 (match_operand:SI 1 "general_operand" ""))]
6794 ;; Operand 1 not really used on the m68000.
6799 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6800 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6803 ;; This is a normal call sequence.
6805 [(call (match_operand:QI 0 "memory_operand" "o")
6806 (match_operand:SI 1 "general_operand" "g"))]
6807 ;; Operand 1 not really used on the m68000.
6811 #if defined (MOTOROLA) && !defined (USE_GAS)
6813 if (GET_CODE (operands[0]) == MEM
6814 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6823 ;; This is a PIC call sequence.
6825 [(call (match_operand:QI 0 "memory_operand" "o")
6826 (match_operand:SI 1 "general_operand" "g"))]
6827 ;; Operand 1 not really used on the m68000.
6831 if (GET_CODE (operands[0]) == MEM
6832 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6834 if (TARGET_PCREL) return \"bsr.l %o0\";
6837 return \"bsr.l %0\";
6840 return \"bsr.l %0@PLTPC\";
6842 return \"bsr %0@PLTPC\";
6847 return \"bsr.l %0\";
6849 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6850 GAS just plain ignores it. FIXME: not anymore, gas doesnt! */
6851 return \"jbsr %0,a1\";
6858 ;; Call subroutine, returning value in operand 0
6859 ;; (which must be a hard register).
6860 ;; See comments before "call" regarding PIC calls.
6861 (define_expand "call_value"
6862 [(set (match_operand 0 "" "")
6863 (call (match_operand:QI 1 "memory_operand" "")
6864 (match_operand:SI 2 "general_operand" "")))]
6865 ;; Operand 2 not really used on the m68000.
6869 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6870 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6873 ;; This is a normal call_value
6875 [(set (match_operand 0 "" "=rf")
6876 (call (match_operand:QI 1 "memory_operand" "o")
6877 (match_operand:SI 2 "general_operand" "g")))]
6878 ;; Operand 2 not really used on the m68000.
6881 #if defined (MOTOROLA) && !defined (USE_GAS)
6883 if (GET_CODE (operands[1]) == MEM
6884 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6893 ;; This is a PIC call_value
6895 [(set (match_operand 0 "" "=rf")
6896 (call (match_operand:QI 1 "memory_operand" "o")
6897 (match_operand:SI 2 "general_operand" "g")))]
6898 ;; Operand 2 not really used on the m68000.
6901 if (GET_CODE (operands[1]) == MEM
6902 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6904 if (TARGET_PCREL) return \"bsr.l %o1\";
6907 return \"bsr.l %1\";
6910 return \"bsr.l %1@PLTPC\";
6912 return \"bsr %1@PLTPC\";
6917 return \"bsr.l %1\";
6919 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6920 GAS just plain ignores it. FIXME: Not anymore, gas doesnt! */
6921 return \"jbsr %1,a1\";
6928 ;; Call subroutine returning any type.
6930 (define_expand "untyped_call"
6931 [(parallel [(call (match_operand 0 "" "")
6933 (match_operand 1 "" "")
6934 (match_operand 2 "" "")])]
6935 "NEEDS_UNTYPED_CALL"
6940 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6942 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6944 rtx set = XVECEXP (operands[2], 0, i);
6945 emit_move_insn (SET_DEST (set), SET_SRC (set));
6948 /* The optimizer does not know that the call sets the function value
6949 registers we stored in the result block. We avoid problems by
6950 claiming that all hard registers are used and clobbered at this
6952 emit_insn (gen_blockage ());
6957 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6958 ;; all of memory. This blocks insns from being moved across this point.
6960 (define_insn "blockage"
6961 [(unspec_volatile [(const_int 0)] 0)]
6970 (define_insn "probe"
6975 operands[0] = plus_constant (stack_pointer_rtx, NEED_PROBE);
6976 return \"tstl %a0\";
6979 ;; Used for frameless functions which save no regs and allocate no locals.
6980 (define_insn "return"
6985 if (current_function_pops_args == 0)
6987 operands[0] = GEN_INT (current_function_pops_args);
6991 (define_insn "indirect_jump"
6992 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6996 ;; This should not be used unless the add/sub insns can't be.
6999 [(set (match_operand:SI 0 "general_operand" "=a")
7000 (match_operand:QI 1 "address_operand" "p"))]
7005 /* Recognize an insn that refers to a table of offsets. Such an insn will
7006 need to refer to a label on the insn. So output one. Use the
7007 label-number of the table of offsets to generate this label. This code,
7008 and similar code above, assumes that there will be at most one reference
7010 if (GET_CODE (operands[1]) == PLUS
7011 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7012 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7014 rtx labelref = XEXP (operands[1], 1);
7015 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7017 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7018 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7020 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7021 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7022 #endif /* not SGS */
7023 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7024 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7025 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7026 #ifdef SGS_SWITCH_TABLES
7027 /* Set flag saying we need to define the symbol
7028 LD%n (with value L%n-LI%n) at the end of the switch table. */
7029 switch_table_difference_label_flag = 1;
7030 #endif /* SGS_SWITCH_TABLES */
7031 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7033 #endif /* SGS_NO_LI */
7035 return \"lea %a1,%0\";
7038 ;; This is the first machine-dependent peephole optimization.
7039 ;; It is useful when a floating value is returned from a function call
7040 ;; and then is moved into an FP register.
7041 ;; But it is mainly intended to test the support for these optimizations.
7044 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7045 (set (match_operand:DF 0 "register_operand" "=f")
7046 (match_operand:DF 1 "register_operand" "ad"))]
7047 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7051 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7052 output_asm_insn (\"move%.l %1,%@\", xoperands);
7053 output_asm_insn (\"move%.l %1,%-\", operands);
7054 return \"fmove%.d %+,%0\";
7058 ;; Optimize a stack-adjust followed by a push of an argument.
7059 ;; This is said to happen frequently with -msoft-float
7060 ;; when there are consecutive library calls.
7063 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7064 (match_operand:SI 0 "const_int_operand" "n")))
7065 (set (match_operand:SF 1 "push_operand" "=m")
7066 (match_operand:SF 2 "general_operand" "rmfF"))]
7067 "INTVAL (operands[0]) >= 4
7068 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7071 if (INTVAL (operands[0]) > 4)
7074 xoperands[0] = stack_pointer_rtx;
7075 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7077 if (INTVAL (xoperands[1]) <= 8)
7080 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7082 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7084 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7086 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7087 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7091 if (INTVAL (xoperands[1]) <= 0x7FFF)
7094 output_asm_insn (\"add%.w %1,%0\", xoperands);
7097 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7099 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7103 output_asm_insn (\"add%.l %1,%0\", xoperands);
7105 if (FP_REG_P (operands[2]))
7106 return \"fmove%.s %2,%@\";
7107 return \"move%.l %2,%@\";
7110 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7113 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7114 (match_operand:SI 0 "const_int_operand" "n")))
7115 (set (match_operand:SI 1 "push_operand" "=m")
7116 (match_operand:SI 2 "general_operand" "g"))]
7117 "INTVAL (operands[0]) >= 4
7118 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7121 if (INTVAL (operands[0]) > 4)
7124 xoperands[0] = stack_pointer_rtx;
7125 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7127 if (INTVAL (xoperands[1]) <= 8)
7130 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7132 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7134 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7136 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7137 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7141 if (INTVAL (xoperands[1]) <= 0x7FFF)
7144 output_asm_insn (\"add%.w %1,%0\", xoperands);
7148 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7150 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7155 output_asm_insn (\"add%.l %1,%0\", xoperands);
7157 if (operands[2] == const0_rtx)
7158 return \"clr%.l %@\";
7159 return \"move%.l %2,%@\";
7162 ;; Speed up pushing a single byte but leaving four bytes of space.
7165 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7166 (match_operand:QI 1 "general_operand" "dami"))
7167 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7168 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7173 if (GET_CODE (operands[1]) == REG)
7174 return \"move%.l %1,%-\";
7176 xoperands[1] = operands[1];
7178 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7179 xoperands[3] = stack_pointer_rtx;
7181 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7183 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7188 [(set (match_operand:SI 0 "register_operand" "=d")
7190 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7191 (match_operand:HI 1 "general_operand" "rmn"))]
7192 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7195 if (GET_CODE (operands[1]) == CONST_INT)
7197 if (operands[1] == const0_rtx
7198 && (DATA_REG_P (operands[0])
7199 || GET_CODE (operands[0]) == MEM)
7200 /* clr insns on 68000 read before writing.
7201 This isn't so on the 68010, but we have no TARGET_68010. */
7202 && ((TARGET_68020 || TARGET_5200)
7203 || !(GET_CODE (operands[0]) == MEM
7204 && MEM_VOLATILE_P (operands[0]))))
7205 return \"clr%.w %0\";
7207 return \"move%.w %1,%0\";
7215 ;; jCC label ; abnormal loop termination
7216 ;; dbra dN, loop ; normal loop termination
7224 ;; Which moves the jCC condition outside the inner loop for free.
7227 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7228 [(cc0) (const_int 0)])
7229 (label_ref (match_operand 2 "" ""))
7234 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7237 (label_ref (match_operand 1 "" ""))
7240 (plus:HI (match_dup 0)
7242 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7246 output_dbcc_and_branch (operands);
7251 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7252 [(cc0) (const_int 0)])
7253 (label_ref (match_operand 2 "" ""))
7258 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7261 (label_ref (match_operand 1 "" ""))
7264 (plus:SI (match_dup 0)
7266 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7270 output_dbcc_and_branch (operands);
7275 ;; FPA multiply and add.
7277 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7278 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7279 (match_operand:DF 2 "general_operand" "xH,y,y"))
7280 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7283 fpma%.d %1,%w2,%w3,%0
7284 fpma%.d %x1,%x2,%x3,%0
7285 fpma%.d %x1,%x2,%x3,%0")
7288 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7289 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7290 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7291 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7294 fpma%.s %1,%w2,%w3,%0
7296 fpma%.s %1,%2,%3,%0")
7298 ;; FPA Multiply and subtract
7300 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7301 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7302 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7303 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7306 fpms%.d %3,%w2,%w1,%0
7307 fpms%.d %x3,%2,%x1,%0
7308 fpms%.d %x3,%2,%x1,%0")
7311 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7312 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7313 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7314 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7317 fpms%.s %3,%w2,%w1,%0
7319 fpms%.s %3,%2,%1,%0")
7322 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7323 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7324 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7325 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7328 fpmr%.d %2,%w1,%w3,%0
7329 fpmr%.d %x2,%1,%x3,%0
7330 fpmr%.d %x2,%1,%x3,%0")
7333 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7334 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7335 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7336 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7339 fpmr%.s %2,%w1,%w3,%0
7340 fpmr%.s %x2,%1,%x3,%0
7341 fpmr%.s %x2,%1,%x3,%0")
7343 ;; FPA Add and multiply
7345 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7346 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7347 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7348 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7351 fpam%.d %2,%w1,%w3,%0
7352 fpam%.d %x2,%1,%x3,%0
7353 fpam%.d %x2,%1,%x3,%0")
7356 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7357 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7358 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7359 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7362 fpam%.s %2,%w1,%w3,%0
7363 fpam%.s %x2,%1,%x3,%0
7364 fpam%.s %x2,%1,%x3,%0")
7366 ;;FPA Subtract and multiply
7368 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7369 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7370 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7371 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7374 fpsm%.d %2,%w1,%w3,%0
7375 fpsm%.d %x2,%1,%x3,%0
7376 fpsm%.d %x2,%1,%x3,%0")
7379 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7380 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7381 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7382 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7385 fpsm%.d %3,%w2,%w1,%0
7386 fpsm%.d %x3,%2,%x1,%0
7387 fpsm%.d %x3,%2,%x1,%0")
7390 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7391 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7392 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7393 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7396 fpsm%.s %2,%w1,%w3,%0
7397 fpsm%.s %x2,%1,%x3,%0
7398 fpsm%.s %x2,%1,%x3,%0")
7401 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7402 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7403 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7404 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7407 fpsm%.s %3,%w2,%w1,%0
7408 fpsm%.s %x3,%2,%x1,%0
7409 fpsm%.s %x3,%2,%x1,%0")
7411 (define_expand "tstxf"
7413 (match_operand:XF 0 "nonimmediate_operand" ""))]
7415 "m68k_last_compare_had_fp_operands = 1;")
7419 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7423 cc_status.flags = CC_IN_68881;
7424 return \"ftst%.x %0\";
7427 (define_expand "cmpxf"
7429 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7430 (match_operand:XF 1 "nonimmediate_operand" "")))]
7432 "m68k_last_compare_had_fp_operands = 1;")
7436 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7437 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7441 cc_status.flags = CC_IN_68881;
7442 #ifdef SGS_CMP_ORDER
7443 if (REG_P (operands[0]))
7445 if (REG_P (operands[1]))
7446 return \"fcmp%.x %0,%1\";
7448 return \"fcmp%.x %0,%f1\";
7450 cc_status.flags |= CC_REVERSED;
7451 return \"fcmp%.x %1,%f0\";
7453 if (REG_P (operands[0]))
7455 if (REG_P (operands[1]))
7456 return \"fcmp%.x %1,%0\";
7458 return \"fcmp%.x %f1,%0\";
7460 cc_status.flags |= CC_REVERSED;
7461 return \"fcmp%.x %f0,%1\";
7465 (define_insn "extendsfxf2"
7466 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7467 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7471 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7473 if (REGNO (operands[0]) == REGNO (operands[1]))
7475 /* Extending float to double in an fp-reg is a no-op.
7476 NOTICE_UPDATE_CC has already assumed that the
7477 cc will be set. So cancel what it did. */
7478 cc_status = cc_prev_status;
7481 return \"f%$move%.x %1,%0\";
7483 if (FP_REG_P (operands[0]))
7485 if (FP_REG_P (operands[1]))
7486 return \"f%$move%.x %1,%0\";
7487 else if (ADDRESS_REG_P (operands[1]))
7488 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7489 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7490 return output_move_const_single (operands);
7491 return \"f%$move%.s %f1,%0\";
7493 return \"fmove%.x %f1,%0\";
7497 (define_insn "extenddfxf2"
7498 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7500 (match_operand:DF 1 "general_operand" "f,rmE")))]
7504 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7506 if (REGNO (operands[0]) == REGNO (operands[1]))
7508 /* Extending float to double in an fp-reg is a no-op.
7509 NOTICE_UPDATE_CC has already assumed that the
7510 cc will be set. So cancel what it did. */
7511 cc_status = cc_prev_status;
7514 return \"fmove%.x %1,%0\";
7516 if (FP_REG_P (operands[0]))
7518 if (REG_P (operands[1]))
7521 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7522 output_asm_insn (\"move%.l %1,%-\", xoperands);
7523 output_asm_insn (\"move%.l %1,%-\", operands);
7524 return \"f%&move%.d %+,%0\";
7526 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7527 return output_move_const_double (operands);
7528 return \"f%&move%.d %f1,%0\";
7530 return \"fmove%.x %f1,%0\";
7533 (define_insn "truncxfdf2"
7534 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7536 (match_operand:XF 1 "general_operand" "f,f")))]
7540 if (REG_P (operands[0]))
7542 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7543 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7544 return \"move%.l %+,%0\";
7546 return \"fmove%.d %f1,%0\";
7549 (define_insn "truncxfsf2"
7550 [(set (match_operand:SF 0 "general_operand" "=dm")
7552 (match_operand:XF 1 "general_operand" "f")))]
7556 (define_insn "floatsixf2"
7557 [(set (match_operand:XF 0 "general_operand" "=f")
7558 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7562 (define_insn "floathixf2"
7563 [(set (match_operand:XF 0 "general_operand" "=f")
7564 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7568 (define_insn "floatqixf2"
7569 [(set (match_operand:XF 0 "general_operand" "=f")
7570 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7574 (define_insn "ftruncxf2"
7575 [(set (match_operand:XF 0 "general_operand" "=f")
7576 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7580 if (FP_REG_P (operands[1]))
7581 return \"fintrz%.x %f1,%0\";
7582 return \"fintrz%.x %f1,%0\";
7585 (define_insn "fixxfqi2"
7586 [(set (match_operand:QI 0 "general_operand" "=dm")
7587 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7591 (define_insn "fixxfhi2"
7592 [(set (match_operand:HI 0 "general_operand" "=dm")
7593 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7597 (define_insn "fixxfsi2"
7598 [(set (match_operand:SI 0 "general_operand" "=dm")
7599 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7604 [(set (match_operand:XF 0 "general_operand" "=f")
7605 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7606 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7611 [(set (match_operand:XF 0 "general_operand" "=f")
7612 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7613 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7618 [(set (match_operand:XF 0 "general_operand" "=f")
7619 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7620 (match_operand:XF 1 "general_operand" "0")))]
7624 (define_insn "addxf3"
7625 [(set (match_operand:XF 0 "general_operand" "=f")
7626 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7627 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7631 if (REG_P (operands[2]))
7632 return \"fadd%.x %2,%0\";
7633 return \"fadd%.x %f2,%0\";
7637 [(set (match_operand:XF 0 "general_operand" "=f")
7638 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7639 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7644 [(set (match_operand:XF 0 "general_operand" "=f")
7645 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7646 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7651 [(set (match_operand:XF 0 "general_operand" "=f")
7652 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7653 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7657 (define_insn "subxf3"
7658 [(set (match_operand:XF 0 "general_operand" "=f")
7659 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7660 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7664 if (REG_P (operands[2]))
7665 return \"fsub%.x %2,%0\";
7666 return \"fsub%.x %f2,%0\";
7670 [(set (match_operand:XF 0 "general_operand" "=f")
7671 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7672 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7677 [(set (match_operand:XF 0 "general_operand" "=f")
7678 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7679 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7684 [(set (match_operand:XF 0 "general_operand" "=f")
7685 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7686 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7690 (define_insn "mulxf3"
7691 [(set (match_operand:XF 0 "general_operand" "=f")
7692 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7693 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7697 if (REG_P (operands[2]))
7698 return \"fmul%.x %2,%0\";
7699 return \"fmul%.x %f2,%0\";
7703 [(set (match_operand:XF 0 "general_operand" "=f")
7704 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7705 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7710 [(set (match_operand:XF 0 "general_operand" "=f")
7711 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7712 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7717 [(set (match_operand:XF 0 "general_operand" "=f")
7718 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7719 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7723 (define_insn "divxf3"
7724 [(set (match_operand:XF 0 "general_operand" "=f")
7725 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7726 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7730 if (REG_P (operands[2]))
7731 return \"fdiv%.x %2,%0\";
7732 return \"fdiv%.x %f2,%0\";
7735 (define_expand "negxf2"
7736 [(set (match_operand:XF 0 "general_operand" "")
7737 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7741 /* ??? There isn't an FPA define_insn so we could handle it here too.
7742 For now we don't (paranoia). */
7750 target = operand_subword (operands[0], 0, 1, XFmode);
7751 result = expand_binop (SImode, xor_optab,
7752 operand_subword_force (operands[1], 0, XFmode),
7753 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7757 if (result != target)
7758 emit_move_insn (result, target);
7760 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7761 operand_subword_force (operands[1], 1, XFmode));
7762 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7763 operand_subword_force (operands[1], 2, XFmode));
7765 insns = get_insns ();
7768 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7773 (define_insn "negxf2_68881"
7774 [(set (match_operand:XF 0 "general_operand" "=f")
7775 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7779 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7780 return \"fneg%.x %1,%0\";
7781 return \"fneg%.x %f1,%0\";
7784 (define_expand "absxf2"
7785 [(set (match_operand:XF 0 "general_operand" "")
7786 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7790 /* ??? There isn't an FPA define_insn so we could handle it here too.
7791 For now we don't (paranoia). */
7799 target = operand_subword (operands[0], 0, 1, XFmode);
7800 result = expand_binop (SImode, and_optab,
7801 operand_subword_force (operands[1], 0, XFmode),
7802 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7806 if (result != target)
7807 emit_move_insn (result, target);
7809 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7810 operand_subword_force (operands[1], 1, XFmode));
7811 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7812 operand_subword_force (operands[1], 2, XFmode));
7814 insns = get_insns ();
7817 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7822 (define_insn "absxf2_68881"
7823 [(set (match_operand:XF 0 "general_operand" "=f")
7824 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7828 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7829 return \"fabs%.x %1,%0\";
7830 return \"fabs%.x %f1,%0\";
7833 (define_insn "sqrtxf2"
7834 [(set (match_operand:XF 0 "general_operand" "=f")
7835 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7839 (define_insn "sinsf2"
7840 [(set (match_operand:SF 0 "general_operand" "=f")
7841 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7842 "TARGET_68881 && flag_unsafe_math_optimizations"
7845 if (FP_REG_P (operands[1]))
7846 return \"fsin%.x %1,%0\";
7848 return \"fsin%.s %1,%0\";
7851 (define_insn "sindf2"
7852 [(set (match_operand:DF 0 "general_operand" "=f")
7853 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7854 "TARGET_68881 && flag_unsafe_math_optimizations"
7857 if (FP_REG_P (operands[1]))
7858 return \"fsin%.x %1,%0\";
7860 return \"fsin%.d %1,%0\";
7863 (define_insn "sinxf2"
7864 [(set (match_operand:XF 0 "general_operand" "=f")
7865 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7866 "TARGET_68881 && flag_unsafe_math_optimizations"
7869 (define_insn "cossf2"
7870 [(set (match_operand:SF 0 "general_operand" "=f")
7871 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7872 "TARGET_68881 && flag_unsafe_math_optimizations"
7875 if (FP_REG_P (operands[1]))
7876 return \"fcos%.x %1,%0\";
7878 return \"fcos%.s %1,%0\";
7881 (define_insn "cosdf2"
7882 [(set (match_operand:DF 0 "general_operand" "=f")
7883 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7884 "TARGET_68881 && flag_unsafe_math_optimizations"
7887 if (FP_REG_P (operands[1]))
7888 return \"fcos%.x %1,%0\";
7890 return \"fcos%.d %1,%0\";
7893 (define_insn "cosxf2"
7894 [(set (match_operand:XF 0 "general_operand" "=f")
7895 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7896 "TARGET_68881 && flag_unsafe_math_optimizations"
7900 [(trap_if (const_int -1) (const_int 7))]
7904 (define_insn "conditional_trap"
7905 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7906 [(cc0) (const_int 0)])
7907 (match_operand:SI 1 "const_int_operand" "I"))]
7908 "TARGET_68020 && ! flags_in_68881 ()"
7911 switch (GET_CODE (operands[0]))
7913 case EQ: return \"trapeq\";
7914 case NE: return \"trapne\";
7915 case GT: return \"trapgt\";
7916 case GTU: return \"traphi\";
7917 case LT: return \"traplt\";
7918 case LTU: return \"trapcs\";
7919 case GE: return \"trapge\";
7920 case GEU: return \"trapcc\";
7921 case LE: return \"traple\";
7922 case LEU: return \"trapls\";