1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
59 ;;- Immediate integer operand constraints:
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
64 ;;- 'M' all integers EXCEPT -256 .. 255
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
72 ;;- "%-" push operand "sp@-" move%.l d0,%-
73 ;;- "%+" pop operand "sp@+" move%.l d0,%+
74 ;;- "%@" top of stack "sp@" move%.l d0,%@
75 ;;- "%!" fpcr register
76 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
77 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;;- Information about 68040 port.
81 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
82 ;;- be emulated in software by the OS. It is faster to avoid these
83 ;;- instructions and issue a library call rather than trapping into
84 ;;- the kernel. The affected instructions are fintrz and fscale. The
85 ;;- TARGET_68040 flag turns the use of the opcodes off.
87 ;;- The '040 also implements a set of new floating-point instructions
88 ;;- which specify the rounding precision in the opcode. This finally
89 ;;- permit the 68k series to be truly IEEE compliant, and solves all
90 ;;- issues of excess precision accumulating in the extended registers.
91 ;;- By default, GCC does not use these instructions, since such code will
92 ;;- not run on an '030. To use these instructions, use the -m68040-only
93 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
94 ;;- you can make these instructions the default.
96 ;;- These new instructions aren't directly in the md. They are brought
97 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
100 ;;- Information about 68060 port.
102 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
103 ;;- be emulated in software by the OS. It is faster to avoid these
104 ;;- instructions and issue a library call rather than trapping into
105 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
106 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
107 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
109 ;;- Some of these insn's are composites of several m68000 op codes.
110 ;;- The assembler (or final @@??) insures that the appropriate one is
120 ;; UNSPEC_VOLATILE usage:
123 [(UNSPECV_BLOCKAGE 0)
127 [(set (match_operand:DF 0 "push_operand" "=m")
128 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
131 if (FP_REG_P (operands[1]))
132 return "fmove%.d %f1,%0";
133 return output_move_double (operands);
136 (define_insn "pushdi"
137 [(set (match_operand:DI 0 "push_operand" "=m")
138 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
141 return output_move_double (operands);
144 ;; We don't want to allow a constant operand for test insns because
145 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
146 ;; be folded while optimizing anyway.
148 (define_expand "tstdi"
149 [(parallel [(set (cc0)
150 (match_operand:DI 0 "nonimmediate_operand" ""))
151 (clobber (match_scratch:SI 1 ""))
152 (clobber (match_scratch:DI 2 ""))])]
154 "m68k_last_compare_had_fp_operands = 0;")
158 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
159 (clobber (match_scratch:SI 1 "=X,d"))
160 (clobber (match_scratch:DI 2 "=d,X"))]
163 if (which_alternative == 0)
167 xoperands[0] = operands[2];
168 xoperands[1] = operands[0];
169 output_move_double (xoperands);
170 cc_status.flags |= CC_REVERSED;
171 return "neg%.l %R2\;negx%.l %2";
173 if (find_reg_note (insn, REG_DEAD, operands[0]))
175 cc_status.flags |= CC_REVERSED;
176 return "neg%.l %R0\;negx%.l %0";
180 'sub' clears %1, and also clears the X cc bit
181 'tst' sets the Z cc bit according to the low part of the DImode operand
182 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
184 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
187 (define_expand "tstsi"
189 (match_operand:SI 0 "nonimmediate_operand" ""))]
191 "m68k_last_compare_had_fp_operands = 0;")
195 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
198 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
200 /* If you think that the 68020 does not support tstl a0,
201 reread page B-167 of the 68020 manual more carefully. */
202 /* On an address reg, cmpw may replace cmpl. */
204 return "cmp%.w %0,%#0";
206 return "cmp%.w %#0,%0";
210 ;; This can't use an address register, because comparisons
211 ;; with address registers as second operand always test the whole word.
212 (define_expand "tsthi"
214 (match_operand:HI 0 "nonimmediate_operand" ""))]
216 "m68k_last_compare_had_fp_operands = 0;")
220 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
224 (define_expand "tstqi"
226 (match_operand:QI 0 "nonimmediate_operand" ""))]
228 "m68k_last_compare_had_fp_operands = 0;")
232 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
236 (define_expand "tstsf"
238 (match_operand:SF 0 "general_operand" ""))]
242 m68k_last_compare_had_fp_operands = 1;
247 (match_operand:SF 0 "general_operand" "fdm"))]
250 cc_status.flags = CC_IN_68881;
251 if (FP_REG_P (operands[0]))
256 (define_expand "tstdf"
258 (match_operand:DF 0 "general_operand" ""))]
262 m68k_last_compare_had_fp_operands = 1;
267 (match_operand:DF 0 "general_operand" "fm"))]
270 cc_status.flags = CC_IN_68881;
271 if (FP_REG_P (operands[0]))
276 ;; compare instructions.
278 (define_expand "cmpdi"
281 (compare (match_operand:DI 0 "nonimmediate_operand" "")
282 (match_operand:DI 1 "general_operand" "")))
283 (clobber (match_dup 2))])]
285 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
289 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
290 (match_operand:DI 2 "general_operand" "d,0")))
291 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
294 if (rtx_equal_p (operands[0], operands[1]))
295 return "sub%.l %R2,%R0\;subx%.l %2,%0";
298 cc_status.flags |= CC_REVERSED;
299 return "sub%.l %R1,%R0\;subx%.l %1,%0";
303 ;; This is the second "hook" for PIC code (in addition to movsi). See
304 ;; comment of movsi for a description of PIC handling.
305 (define_expand "cmpsi"
307 (compare (match_operand:SI 0 "nonimmediate_operand" "")
308 (match_operand:SI 1 "general_operand" "")))]
312 m68k_last_compare_had_fp_operands = 0;
313 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
315 /* The source is an address which requires PIC relocation.
316 Call legitimize_pic_address with the source, mode, and a relocation
317 register (a new pseudo, or the final destination if reload_in_progress
318 is set). Then fall through normally */
319 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
320 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
324 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
327 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
328 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
331 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
333 return "cmpm%.l %0,%1";
335 return "cmpm%.l %1,%0";
337 if (REG_P (operands[1])
338 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
339 { cc_status.flags |= CC_REVERSED;
341 return "cmp%.l %d1,%d0";
343 return "cmp%.l %d0,%d1";
346 if (ADDRESS_REG_P (operands[0])
347 && GET_CODE (operands[1]) == CONST_INT
348 && INTVAL (operands[1]) < 0x8000
349 && INTVAL (operands[1]) >= -0x8000)
352 return "cmp%.w %0,%1";
354 return "cmp%.w %1,%0";
358 return "cmp%.l %d0,%d1";
360 return "cmp%.l %d1,%d0";
366 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
367 (match_operand:SI 1 "general_operand" "r,mrKs")))]
370 if (REG_P (operands[1])
371 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
372 { cc_status.flags |= CC_REVERSED;
374 return "cmp%.l %d1,%d0";
376 return "cmp%.l %d0,%d1";
380 return "cmp%.l %d0,%d1";
382 return "cmp%.l %d1,%d0";
386 (define_expand "cmphi"
388 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
389 (match_operand:HI 1 "general_src_operand" "")))]
391 "m68k_last_compare_had_fp_operands = 0;")
395 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
396 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
399 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
401 return "cmpm%.w %0,%1";
403 return "cmpm%.w %1,%0";
405 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
406 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
407 { cc_status.flags |= CC_REVERSED;
409 return "cmp%.w %d1,%d0";
411 return "cmp%.w %d0,%d1";
415 return "cmp%.w %d0,%d1";
417 return "cmp%.w %d1,%d0";
421 (define_expand "cmpqi"
423 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
424 (match_operand:QI 1 "general_src_operand" "")))]
426 "m68k_last_compare_had_fp_operands = 0;")
430 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
431 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
434 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
436 return "cmpm%.b %0,%1";
438 return "cmpm%.b %1,%0";
440 if (REG_P (operands[1])
441 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
442 { cc_status.flags |= CC_REVERSED;
444 return "cmp%.b %d1,%d0";
446 return "cmp%.b %d0,%d1";
450 return "cmp%.b %d0,%d1";
452 return "cmp%.b %d1,%d0";
456 (define_expand "cmpdf"
458 (compare (match_operand:DF 0 "general_operand" "")
459 (match_operand:DF 1 "general_operand" "")))]
463 m68k_last_compare_had_fp_operands = 1;
468 (compare (match_operand:DF 0 "general_operand" "f,mG")
469 (match_operand:DF 1 "general_operand" "fmG,f")))]
472 cc_status.flags = CC_IN_68881;
474 if (REG_P (operands[0]))
476 if (REG_P (operands[1]))
477 return "fcmp%.x %0,%1";
479 return "fcmp%.d %0,%f1";
481 cc_status.flags |= CC_REVERSED;
482 return "fcmp%.d %1,%f0";
484 if (REG_P (operands[0]))
486 if (REG_P (operands[1]))
487 return "fcmp%.x %1,%0";
489 return "fcmp%.d %f1,%0";
491 cc_status.flags |= CC_REVERSED;
492 return "fcmp%.d %f0,%1";
496 (define_expand "cmpsf"
498 (compare (match_operand:SF 0 "general_operand" "")
499 (match_operand:SF 1 "general_operand" "")))]
503 m68k_last_compare_had_fp_operands = 1;
508 (compare (match_operand:SF 0 "general_operand" "f,mdG")
509 (match_operand:SF 1 "general_operand" "fmdG,f")))]
512 cc_status.flags = CC_IN_68881;
514 if (FP_REG_P (operands[0]))
516 if (FP_REG_P (operands[1]))
517 return "fcmp%.x %0,%1";
519 return "fcmp%.s %0,%f1";
521 cc_status.flags |= CC_REVERSED;
522 return "fcmp%.s %1,%f0";
524 if (FP_REG_P (operands[0]))
526 if (FP_REG_P (operands[1]))
527 return "fcmp%.x %1,%0";
529 return "fcmp%.s %f1,%0";
531 cc_status.flags |= CC_REVERSED;
532 return "fcmp%.s %f0,%1";
536 ;; Recognizers for btst instructions.
538 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
539 ;; specified as a constant, so we must disable all patterns that may extract
540 ;; from a MEM at a constant bit position if we can't use this as a constraint.
543 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
545 (minus:SI (const_int 7)
546 (match_operand:SI 1 "general_operand" "di"))))]
549 return output_btst (operands, operands[1], operands[0], insn, 7);
552 ;; This is the same as the above pattern except for the constraints. The 'i'
556 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
558 (minus:SI (const_int 7)
559 (match_operand:SI 1 "general_operand" "d"))))]
562 return output_btst (operands, operands[1], operands[0], insn, 7);
566 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
568 (minus:SI (const_int 31)
569 (match_operand:SI 1 "general_operand" "di"))))]
572 return output_btst (operands, operands[1], operands[0], insn, 31);
575 ;; The following two patterns are like the previous two
576 ;; except that they use the fact that bit-number operands
577 ;; are automatically masked to 3 or 5 bits.
580 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
582 (minus:SI (const_int 7)
584 (match_operand:SI 1 "register_operand" "d")
588 return output_btst (operands, operands[1], operands[0], insn, 7);
592 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
594 (minus:SI (const_int 31)
596 (match_operand:SI 1 "register_operand" "d")
600 return output_btst (operands, operands[1], operands[0], insn, 31);
603 ;; Nonoffsettable mem refs are ok in this one pattern
604 ;; since we don't try to adjust them.
606 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
608 (match_operand:SI 1 "const_int_operand" "n")))]
609 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
611 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
612 return output_btst (operands, operands[1], operands[0], insn, 7);
616 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
618 (match_operand:SI 1 "const_int_operand" "n")))]
621 if (GET_CODE (operands[0]) == MEM)
623 operands[0] = adjust_address (operands[0], QImode,
624 INTVAL (operands[1]) / 8);
625 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
626 return output_btst (operands, operands[1], operands[0], insn, 7);
628 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
629 return output_btst (operands, operands[1], operands[0], insn, 31);
632 ;; This is the same as the above pattern except for the constraints.
633 ;; The 'o' has been replaced with 'Q'.
636 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
638 (match_operand:SI 1 "const_int_operand" "n")))]
641 if (GET_CODE (operands[0]) == MEM)
643 operands[0] = adjust_address (operands[0], QImode,
644 INTVAL (operands[1]) / 8);
645 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
646 return output_btst (operands, operands[1], operands[0], insn, 7);
648 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
649 return output_btst (operands, operands[1], operands[0], insn, 31);
655 ;; A special case in which it is not desirable
656 ;; to reload the constant into a data register.
657 (define_insn "pushexthisi_const"
658 [(set (match_operand:SI 0 "push_operand" "=m")
659 (match_operand:SI 1 "const_int_operand" "J"))]
660 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
662 if (operands[1] == const0_rtx)
668 ;(define_insn "swapsi"
669 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
670 ; (match_operand:SI 1 "general_operand" "+r"))
671 ; (set (match_dup 1) (match_dup 0))]
675 ;; Special case of fullword move when source is zero.
676 ;; The reason this is special is to avoid loading a zero
677 ;; into a data reg with moveq in order to store it elsewhere.
679 (define_insn "movsi_const0"
680 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
682 ;; clr insns on 68000 read before writing.
683 ;; This isn't so on the 68010, but we have no TARGET_68010.
684 "((TARGET_68020 || TARGET_COLDFIRE)
685 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
687 if (ADDRESS_REG_P (operands[0]))
689 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
690 if (!TARGET_68040 && !TARGET_68060)
691 return "sub%.l %0,%0";
695 /* Many SGS assemblers croak on size specifiers for constants. */
702 /* moveq is faster on the 68000. */
703 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
704 return "moveq %#0,%0";
708 ;; General case of fullword move.
710 ;; This is the main "hook" for PIC code. When generating
711 ;; PIC, movsi is responsible for determining when the source address
712 ;; needs PIC relocation and appropriately calling legitimize_pic_address
713 ;; to perform the actual relocation.
715 ;; In both the PIC and non-PIC cases the patterns generated will
716 ;; matched by the next define_insn.
717 (define_expand "movsi"
718 [(set (match_operand:SI 0 "nonimmediate_operand" "")
719 (match_operand:SI 1 "general_operand" ""))]
723 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
725 /* The source is an address which requires PIC relocation.
726 Call legitimize_pic_address with the source, mode, and a relocation
727 register (a new pseudo, or the final destination if reload_in_progress
728 is set). Then fall through normally */
729 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
730 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
732 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
734 /* Don't allow writes to memory except via a register;
735 the m68k doesn't consider PC-relative addresses to be writable. */
736 if (symbolic_operand (operands[0], SImode))
737 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
738 else if (GET_CODE (operands[0]) == MEM
739 && symbolic_operand (XEXP (operands[0], 0), SImode))
740 operands[0] = gen_rtx (MEM, SImode,
741 force_reg (SImode, XEXP (operands[0], 0)));
745 ;; General case of fullword move. The register constraints
746 ;; force integer constants in range for a moveq to be reloaded
747 ;; if they are headed for memory.
749 ;; Notes: make sure no alternative allows g vs g.
750 ;; We don't allow f-regs since fixed point cannot go in them.
751 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
752 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
756 return output_move_simode (operands);
760 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
761 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
763 "* return output_move_simode (operands);")
765 ;; Special case of fullword move, where we need to get a non-GOT PIC
766 ;; reference into an address register.
768 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
769 (match_operand:SI 1 "pcrel_address" ""))]
772 if (push_operand (operands[0], SImode))
777 (define_expand "movhi"
778 [(set (match_operand:HI 0 "nonimmediate_operand" "")
779 (match_operand:HI 1 "general_operand" ""))]
784 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
785 (match_operand:HI 1 "general_src_operand" "gS"))]
787 "* return output_move_himode (operands);")
790 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
791 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
793 "* return output_move_himode (operands);")
795 (define_expand "movstricthi"
796 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
797 (match_operand:HI 1 "general_src_operand" ""))]
802 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
803 (match_operand:HI 1 "general_src_operand" "rmSn"))]
805 "* return output_move_stricthi (operands);")
808 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
809 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
811 "* return output_move_stricthi (operands);")
813 (define_expand "movqi"
814 [(set (match_operand:QI 0 "nonimmediate_operand" "")
815 (match_operand:QI 1 "general_src_operand" ""))]
820 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
821 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
823 "* return output_move_qimode (operands);")
826 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
827 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
829 "* return output_move_qimode (operands);")
831 (define_expand "movstrictqi"
832 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
833 (match_operand:QI 1 "general_src_operand" ""))]
838 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
839 (match_operand:QI 1 "general_src_operand" "dmSn"))]
841 "* return output_move_strictqi (operands);")
844 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
845 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
847 "* return output_move_strictqi (operands);")
849 (define_expand "pushqi1"
850 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
851 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
852 (match_operand:QI 0 "general_operand" ""))]
856 (define_expand "movsf"
857 [(set (match_operand:SF 0 "nonimmediate_operand" "")
858 (match_operand:SF 1 "general_operand" ""))]
863 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
864 (match_operand:SF 1 "general_operand" "rmfF"))]
867 if (FP_REG_P (operands[0]))
869 if (FP_REG_P (operands[1]))
870 return "f%$move%.x %1,%0";
871 else if (ADDRESS_REG_P (operands[1]))
872 return "move%.l %1,%-\;f%$move%.s %+,%0";
873 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
874 return output_move_const_single (operands);
875 return "f%$move%.s %f1,%0";
877 if (FP_REG_P (operands[1]))
879 if (ADDRESS_REG_P (operands[0]))
880 return "fmove%.s %1,%-\;move%.l %+,%0";
881 return "fmove%.s %f1,%0";
883 if (operands[1] == CONST0_RTX (SFmode)
884 /* clr insns on 68000 read before writing.
885 This isn't so on the 68010, but we have no TARGET_68010. */
886 && ((TARGET_68020 || TARGET_COLDFIRE)
887 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
889 if (ADDRESS_REG_P (operands[0]))
891 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
892 if (!TARGET_68040 && !TARGET_68060)
893 return "sub%.l %0,%0";
897 /* Many SGS assemblers croak on size specifiers for constants. */
904 /* moveq is faster on the 68000. */
905 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
907 return "moveq %#0,%0";
911 return "move%.l %1,%0";
915 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
916 (match_operand:SF 1 "general_operand" "g,r"))]
919 return "move%.l %1,%0";
922 (define_expand "movdf"
923 [(set (match_operand:DF 0 "nonimmediate_operand" "")
924 (match_operand:DF 1 "general_operand" ""))]
929 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
930 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
931 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
932 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
935 if (FP_REG_P (operands[0]))
937 if (FP_REG_P (operands[1]))
938 return "f%&move%.x %1,%0";
939 if (REG_P (operands[1]))
942 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
943 output_asm_insn ("move%.l %1,%-", xoperands);
944 output_asm_insn ("move%.l %1,%-", operands);
945 return "f%&move%.d %+,%0";
947 if (GET_CODE (operands[1]) == CONST_DOUBLE)
948 return output_move_const_double (operands);
949 return "f%&move%.d %f1,%0";
951 else if (FP_REG_P (operands[1]))
953 if (REG_P (operands[0]))
955 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
956 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
957 return "move%.l %+,%0";
960 return "fmove%.d %f1,%0";
962 return output_move_double (operands);
966 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
967 (match_operand:DF 1 "general_operand" "g,r"))]
970 return output_move_double (operands);
973 ;; ??? The XFmode patterns are schizophrenic about whether constants are
974 ;; allowed. Most but not all have predicates and constraint that disallow
975 ;; constants. Most but not all have output templates that handle constants.
976 ;; See also LEGITIMATE_CONSTANT_P.
978 (define_expand "movxf"
979 [(set (match_operand:XF 0 "nonimmediate_operand" "")
980 (match_operand:XF 1 "general_operand" ""))]
984 /* We can't rewrite operands during reload. */
985 if (! reload_in_progress)
987 if (CONSTANT_P (operands[1]))
989 operands[1] = force_const_mem (XFmode, operands[1]);
990 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
991 operands[1] = adjust_address (operands[1], XFmode, 0);
993 if (flag_pic && TARGET_PCREL)
995 /* Don't allow writes to memory except via a register; the
996 m68k doesn't consider PC-relative addresses to be writable. */
997 if (GET_CODE (operands[0]) == MEM
998 && symbolic_operand (XEXP (operands[0], 0), SImode))
999 operands[0] = gen_rtx (MEM, XFmode,
1000 force_reg (SImode, XEXP (operands[0], 0)));
1006 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1007 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1010 if (FP_REG_P (operands[0]))
1012 if (FP_REG_P (operands[1]))
1013 return "fmove%.x %1,%0";
1014 if (REG_P (operands[1]))
1017 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1018 output_asm_insn ("move%.l %1,%-", xoperands);
1019 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1020 output_asm_insn ("move%.l %1,%-", xoperands);
1021 output_asm_insn ("move%.l %1,%-", operands);
1022 return "fmove%.x %+,%0";
1024 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1025 return "fmove%.x %1,%0";
1026 return "fmove%.x %f1,%0";
1028 if (FP_REG_P (operands[1]))
1030 if (REG_P (operands[0]))
1032 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1033 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1034 output_asm_insn ("move%.l %+,%0", operands);
1035 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1036 return "move%.l %+,%0";
1038 /* Must be memory destination. */
1039 return "fmove%.x %f1,%0";
1041 return output_move_double (operands);
1045 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1046 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1047 "! TARGET_68881 && ! TARGET_COLDFIRE"
1049 if (FP_REG_P (operands[0]))
1051 if (FP_REG_P (operands[1]))
1052 return "fmove%.x %1,%0";
1053 if (REG_P (operands[1]))
1056 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1057 output_asm_insn ("move%.l %1,%-", xoperands);
1058 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1059 output_asm_insn ("move%.l %1,%-", xoperands);
1060 output_asm_insn ("move%.l %1,%-", operands);
1061 return "fmove%.x %+,%0";
1063 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1064 return "fmove%.x %1,%0";
1065 return "fmove%.x %f1,%0";
1067 if (FP_REG_P (operands[1]))
1069 if (REG_P (operands[0]))
1071 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1072 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1073 output_asm_insn ("move%.l %+,%0", operands);
1074 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1075 return "move%.l %+,%0";
1078 return "fmove%.x %f1,%0";
1080 return output_move_double (operands);
1084 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1085 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1086 "! TARGET_68881 && TARGET_COLDFIRE"
1087 "* return output_move_double (operands);")
1089 (define_expand "movdi"
1090 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1091 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1092 (match_operand:DI 1 "general_operand" ""))]
1096 ;; movdi can apply to fp regs in some cases
1098 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1099 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1100 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1101 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1102 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1103 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1104 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1107 if (FP_REG_P (operands[0]))
1109 if (FP_REG_P (operands[1]))
1110 return "fmove%.x %1,%0";
1111 if (REG_P (operands[1]))
1114 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1115 output_asm_insn ("move%.l %1,%-", xoperands);
1116 output_asm_insn ("move%.l %1,%-", operands);
1117 return "fmove%.d %+,%0";
1119 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1120 return output_move_const_double (operands);
1121 return "fmove%.d %f1,%0";
1123 else if (FP_REG_P (operands[1]))
1125 if (REG_P (operands[0]))
1127 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1128 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1129 return "move%.l %+,%0";
1132 return "fmove%.d %f1,%0";
1134 return output_move_double (operands);
1138 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1139 (match_operand:DI 1 "general_operand" "g,r"))]
1141 "* return output_move_double (operands);")
1143 ;; Thus goes after the move instructions
1144 ;; because the move instructions are better (require no spilling)
1145 ;; when they can apply. It goes before the add/sub insns
1146 ;; so we will prefer it to them.
1148 (define_insn "pushasi"
1149 [(set (match_operand:SI 0 "push_operand" "=m")
1150 (match_operand:SI 1 "address_operand" "p"))]
1154 ;; truncation instructions
1155 (define_insn "truncsiqi2"
1156 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1158 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1161 if (GET_CODE (operands[0]) == REG)
1163 /* Must clear condition codes, since the move.l bases them on
1164 the entire 32 bits, not just the desired 8 bits. */
1166 return "move%.l %1,%0";
1168 if (GET_CODE (operands[1]) == MEM)
1169 operands[1] = adjust_address (operands[1], QImode, 3);
1170 return "move%.b %1,%0";
1173 (define_insn "trunchiqi2"
1174 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1176 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1179 if (GET_CODE (operands[0]) == REG
1180 && (GET_CODE (operands[1]) == MEM
1181 || GET_CODE (operands[1]) == CONST_INT))
1183 /* Must clear condition codes, since the move.w bases them on
1184 the entire 16 bits, not just the desired 8 bits. */
1186 return "move%.w %1,%0";
1188 if (GET_CODE (operands[0]) == REG)
1190 /* Must clear condition codes, since the move.l bases them on
1191 the entire 32 bits, not just the desired 8 bits. */
1193 return "move%.l %1,%0";
1195 if (GET_CODE (operands[1]) == MEM)
1196 operands[1] = adjust_address (operands[1], QImode, 1);
1197 return "move%.b %1,%0";
1200 (define_insn "truncsihi2"
1201 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1203 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1206 if (GET_CODE (operands[0]) == REG)
1208 /* Must clear condition codes, since the move.l bases them on
1209 the entire 32 bits, not just the desired 8 bits. */
1211 return "move%.l %1,%0";
1213 if (GET_CODE (operands[1]) == MEM)
1214 operands[1] = adjust_address (operands[1], QImode, 2);
1215 return "move%.w %1,%0";
1218 ;; zero extension instructions
1220 (define_insn "zero_extendqidi2"
1221 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1222 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1226 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1227 return "moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2";
1230 (define_insn "zero_extendhidi2"
1231 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d")
1232 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1236 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1237 return "moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2";
1240 ;; this is the canonical form for (lshiftrt:DI x 32)
1241 (define_expand "zero_extendsidi2"
1242 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1243 (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
1247 (define_insn "*zero_extendsidi2_cf"
1248 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
1249 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
1253 if (GET_CODE (operands[0]) == REG)
1254 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1255 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1256 return "move%.l %1,%0\;clr%.l %0";
1257 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1258 return "clr%.l %0\;move%.l %1,%0";
1260 operands[2] = adjust_address (operands[0], SImode, 4);
1261 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1262 || REGNO (operands[1]) != REGNO (operands[2]))
1263 output_asm_insn ("move%.l %1,%2", operands);
1264 if (ADDRESS_REG_P (operands[0]))
1265 return "sub%.l %0,%0";
1270 (define_insn "*zero_extendsidi2"
1271 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
1272 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1276 if (GET_CODE (operands[0]) == REG)
1277 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1278 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1279 return "move%.l %1,%0\;clr%.l %0";
1280 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1281 return "clr%.l %0\;move%.l %1,%0";
1283 operands[2] = adjust_address (operands[0], SImode, 4);
1284 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1285 || REGNO (operands[1]) != REGNO (operands[2]))
1286 output_asm_insn ("move%.l %1,%2", operands);
1287 if (ADDRESS_REG_P (operands[0]))
1288 return "sub%.l %0,%0";
1293 (define_expand "zero_extendhisi2"
1294 [(set (match_operand:SI 0 "register_operand" "")
1296 (set (strict_low_part (match_dup 2))
1297 (match_operand:HI 1 "general_operand" ""))]
1301 operands[1] = make_safe_from (operands[1], operands[0]);
1302 operands[2] = gen_lowpart_SUBREG (HImode, operands[0]);
1305 (define_expand "zero_extendqihi2"
1306 [(set (match_operand:HI 0 "register_operand" "")
1308 (set (strict_low_part (match_dup 2))
1309 (match_operand:QI 1 "general_operand" ""))]
1313 operands[1] = make_safe_from (operands[1], operands[0]);
1314 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1317 (define_expand "zero_extendqisi2"
1318 [(set (match_operand:SI 0 "register_operand" "")
1320 (set (strict_low_part (match_dup 2))
1321 (match_operand:QI 1 "general_operand" ""))]
1325 operands[1] = make_safe_from (operands[1], operands[0]);
1326 operands[2] = gen_lowpart_SUBREG (QImode, operands[0]);
1329 ;; Patterns to recognize zero-extend insns produced by the combiner.
1330 ;; We don't allow both operands in memory, because of aliasing problems.
1331 ;; Explicitly disallow two memory operands via the condition since reloading
1332 ;; of this case will result in worse code than the uncombined patterns.
1335 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d<")
1336 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1337 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1339 if (DATA_REG_P (operands[0]))
1341 if (GET_CODE (operands[1]) == REG
1342 && REGNO (operands[0]) == REGNO (operands[1]))
1343 return "and%.l %#0xFFFF,%0";
1344 if (reg_mentioned_p (operands[0], operands[1]))
1345 return "move%.w %1,%0\;and%.l %#0xFFFF,%0";
1346 return "clr%.l %0\;move%.w %1,%0";
1348 else if (GET_CODE (operands[0]) == MEM
1349 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1350 return "move%.w %1,%0\;clr%.w %0";
1351 else if (GET_CODE (operands[0]) == MEM
1352 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1353 return "clr%.w %0\;move%.w %1,%0";
1356 output_asm_insn ("clr%.w %0", operands);
1357 operands[0] = adjust_address (operands[0], HImode, 2);
1358 return "move%.w %1,%0";
1363 [(set (match_operand:HI 0 "nonimmediate_operand" "=do<>,d")
1364 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1365 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1367 if (DATA_REG_P (operands[0]))
1369 if (GET_CODE (operands[1]) == REG
1370 && REGNO (operands[0]) == REGNO (operands[1]))
1371 return (!TARGET_COLDFIRE ? "and%.w %#0xFF,%0" : "and%.l %#0xFF,%0");
1372 if (reg_mentioned_p (operands[0], operands[1]))
1373 return (!TARGET_COLDFIRE ? "move%.b %1,%0\;and%.w %#0xFF,%0"
1374 : "move%.b %1,%0\;and%.l %#0xFF,%0");
1375 return "clr%.w %0\;move%.b %1,%0";
1377 else if (GET_CODE (operands[0]) == MEM
1378 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1380 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1381 == STACK_POINTER_REGNUM)
1383 output_asm_insn ("clr%.w %-", operands);
1384 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1385 plus_constant (stack_pointer_rtx, 1));
1386 return "move%.b %1,%0";
1389 return "move%.b %1,%0\;clr%.b %0";
1391 else if (GET_CODE (operands[0]) == MEM
1392 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1393 return "clr%.b %0\;move%.b %1,%0";
1396 output_asm_insn ("clr%.b %0", operands);
1397 operands[0] = adjust_address (operands[0], QImode, 1);
1398 return "move%.b %1,%0";
1403 [(set (match_operand:SI 0 "nonimmediate_operand" "=do<>,d")
1404 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1405 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1407 if (DATA_REG_P (operands[0]))
1409 if (GET_CODE (operands[1]) == REG
1410 && REGNO (operands[0]) == REGNO (operands[1]))
1411 return "and%.l %#0xFF,%0";
1412 if (reg_mentioned_p (operands[0], operands[1]))
1413 return "move%.b %1,%0\;and%.l %#0xFF,%0";
1414 return "clr%.l %0\;move%.b %1,%0";
1416 else if (GET_CODE (operands[0]) == MEM
1417 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1419 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1422 "clr%.l -(%0)\;move%.b %1,3(%0)" :
1424 "clr%.l -(%0)\;move%.b %1,(3,%0)" :
1426 "clrl %0@-\;moveb %1,%0@(3)";
1428 else if (GET_CODE (operands[0]) == MEM
1429 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1431 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1434 "clr%.l (%0)+\;move%.b %1,-1(%0)" :
1436 "clr%.l (%0)+\;move%.b %1,(-1,%0)" :
1438 "clrl %0@+\;moveb %1,%0@(-1)";
1442 output_asm_insn ("clr%.l %0", operands);
1443 operands[0] = adjust_address (operands[0], QImode, 3);
1444 return "move%.b %1,%0";
1448 ;; sign extension instructions
1450 (define_insn "extendqidi2"
1451 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1452 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1456 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1457 if (TARGET_68020 || TARGET_COLDFIRE)
1458 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1460 return "move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0";
1463 (define_insn "extendhidi2"
1464 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1466 (match_operand:HI 1 "general_src_operand" "rmS")))]
1470 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1471 if (TARGET_68020 || TARGET_COLDFIRE)
1472 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
1474 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
1477 (define_insn "extendsidi2"
1478 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1480 (match_operand:SI 1 "general_operand" "rm")))]
1484 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1485 if (TARGET_68020 || TARGET_COLDFIRE)
1486 return "move%.l %1,%2\;smi %0\;extb%.l %0";
1488 return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
1491 ;; Special case when one can avoid register clobbering, copy and test
1492 ;; Maybe there is a way to make that the general case, by forcing the
1493 ;; result of the SI tree to be in the lower register of the DI target
1495 (define_insn "extendplussidi"
1496 [(set (match_operand:DI 0 "register_operand" "=d")
1497 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1498 (match_operand:SI 2 "general_operand" "rmn"))))]
1502 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1503 if (GET_CODE (operands[1]) == CONST_INT
1504 && (unsigned) INTVAL (operands[1]) > 8)
1506 rtx tmp = operands[1];
1508 operands[1] = operands[2];
1511 if (GET_CODE (operands[1]) == REG
1512 && REGNO (operands[1]) == REGNO (operands[3]))
1513 output_asm_insn ("add%.l %2,%3", operands);
1515 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
1516 if (TARGET_68020 || TARGET_COLDFIRE)
1517 return "smi %0\;extb%.l %0";
1519 return "smi %0\;ext%.w %0\;ext%.l %0";
1522 (define_insn "extendhisi2"
1523 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1525 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1528 if (ADDRESS_REG_P (operands[0]))
1529 return "move%.w %1,%0";
1533 (define_insn "extendqihi2"
1534 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1535 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1539 (define_insn "extendqisi2"
1540 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1541 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1542 "TARGET_68020 || TARGET_COLDFIRE"
1545 ;; Conversions between float and double.
1547 (define_expand "extendsfdf2"
1548 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1550 (match_operand:SF 1 "general_operand" "")))]
1555 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1557 (match_operand:SF 1 "general_operand" "f,dmF")))]
1560 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1562 if (REGNO (operands[0]) == REGNO (operands[1]))
1564 /* Extending float to double in an fp-reg is a no-op.
1565 NOTICE_UPDATE_CC has already assumed that the
1566 cc will be set. So cancel what it did. */
1567 cc_status = cc_prev_status;
1570 return "f%&move%.x %1,%0";
1572 if (FP_REG_P (operands[0]))
1573 return "f%&move%.s %f1,%0";
1574 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1576 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1577 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1578 return "move%.l %+,%0";
1580 return "fmove%.d %f1,%0";
1583 ;; This cannot output into an f-reg because there is no way to be
1584 ;; sure of truncating in that case.
1585 (define_expand "truncdfsf2"
1586 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1588 (match_operand:DF 1 "general_operand" "")))]
1592 ;; On the '040 we can truncate in a register accurately and easily.
1594 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1596 (match_operand:DF 1 "general_operand" "fmG")))]
1599 if (FP_REG_P (operands[1]))
1600 return "f%$move%.x %1,%0";
1601 return "f%$move%.d %f1,%0";
1605 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
1607 (match_operand:DF 1 "general_operand" "f")))]
1611 ;; Conversion between fixed point and floating point.
1612 ;; Note that among the fix-to-float insns
1613 ;; the ones that start with SImode come first.
1614 ;; That is so that an operand that is a CONST_INT
1615 ;; (and therefore lacks a specific machine mode).
1616 ;; will be recognized as SImode (which is always valid)
1617 ;; rather than as QImode or HImode.
1619 (define_expand "floatsisf2"
1620 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1621 (float:SF (match_operand:SI 1 "general_operand" "")))]
1626 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1627 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1631 (define_expand "floatsidf2"
1632 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1633 (float:DF (match_operand:SI 1 "general_operand" "")))]
1638 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1639 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1643 (define_insn "floathisf2"
1644 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1645 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1649 (define_insn "floathidf2"
1650 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1651 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1655 (define_insn "floatqisf2"
1656 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1657 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1661 (define_insn "floatqidf2"
1662 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1663 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1667 ;; New routines to convert floating-point values to integers
1668 ;; to be used on the '040. These should be faster than trapping
1669 ;; into the kernel to emulate fintrz. They should also be faster
1670 ;; than calling the subroutines fixsfsi or fixdfsi.
1672 (define_insn "fix_truncdfsi2"
1673 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1674 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1675 (clobber (match_scratch:SI 2 "=d"))
1676 (clobber (match_scratch:SI 3 "=d"))]
1677 "TARGET_68881 && TARGET_68040"
1680 return "fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
1683 (define_insn "fix_truncdfhi2"
1684 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1685 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1686 (clobber (match_scratch:SI 2 "=d"))
1687 (clobber (match_scratch:SI 3 "=d"))]
1688 "TARGET_68881 && TARGET_68040"
1691 return "fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
1694 (define_insn "fix_truncdfqi2"
1695 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1696 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1697 (clobber (match_scratch:SI 2 "=d"))
1698 (clobber (match_scratch:SI 3 "=d"))]
1699 "TARGET_68881 && TARGET_68040"
1702 return "fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
1705 ;; Convert a float to a float whose value is an integer.
1706 ;; This is the first stage of converting it to an integer type.
1708 (define_insn "ftruncdf2"
1709 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1710 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1711 "TARGET_68881 && !TARGET_68040"
1713 if (FP_REG_P (operands[1]))
1714 return "fintrz%.x %f1,%0";
1715 return "fintrz%.d %f1,%0";
1718 (define_insn "ftruncsf2"
1719 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1720 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1721 "TARGET_68881 && !TARGET_68040"
1723 if (FP_REG_P (operands[1]))
1724 return "fintrz%.x %f1,%0";
1725 return "fintrz%.s %f1,%0";
1728 ;; Convert a float whose value is an integer
1729 ;; to an actual integer. Second stage of converting float to integer type.
1730 (define_insn "fixsfqi2"
1731 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1732 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1736 (define_insn "fixsfhi2"
1737 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1738 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1742 (define_insn "fixsfsi2"
1743 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1744 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1748 (define_insn "fixdfqi2"
1749 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
1750 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1754 (define_insn "fixdfhi2"
1755 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
1756 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1760 (define_insn "fixdfsi2"
1761 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1762 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1768 (define_insn "adddi_lshrdi_63"
1769 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1770 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1773 (clobber (match_scratch:SI 2 "=d"))]
1776 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1777 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1779 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
1780 if (GET_CODE (operands[1]) == REG)
1781 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1782 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1783 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1784 operands[4] = operands[1];
1786 operands[4] = adjust_address (operands[1], SImode, 4);
1787 if (GET_CODE (operands[1]) == MEM
1788 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1789 output_asm_insn ("move%.l %4,%3", operands);
1790 output_asm_insn ("move%.l %1,%0\;smi %2", operands);
1791 if (TARGET_68020 || TARGET_COLDFIRE)
1792 output_asm_insn ("extb%.l %2", operands);
1794 output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
1795 if (GET_CODE (operands[1]) != MEM
1796 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1797 output_asm_insn ("move%.l %4,%3", operands);
1798 return "sub%.l %2,%3\;subx%.l %2,%0";
1801 (define_insn "adddi_sexthishl32"
1802 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
1803 (plus:DI (ashift:DI (sign_extend:DI
1804 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1806 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1807 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1811 if (ADDRESS_REG_P (operands[0]))
1812 return "add%.w %1,%0";
1813 else if (ADDRESS_REG_P (operands[3]))
1814 return "move%.w %1,%3\;add%.l %3,%0";
1816 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
1819 (define_insn "adddi_dilshr32"
1820 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
1821 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1822 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1823 ;; (const_int 32))))]
1824 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
1826 (match_operand:DI 2 "general_operand" "0,0")))]
1830 if (GET_CODE (operands[0]) == REG)
1831 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1833 operands[2] = adjust_address (operands[0], SImode, 4);
1834 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
1837 (define_insn "adddi_dishl32"
1838 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
1839 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1840 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
1841 ;; (const_int 32))))]
1842 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
1844 (match_operand:DI 2 "general_operand" "0,0")))]
1848 if (GET_CODE (operands[1]) == REG)
1849 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1851 operands[1] = adjust_address (operands[1], SImode, 4);
1852 return "add%.l %1,%0";
1855 (define_insn "adddi3"
1856 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
1857 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
1858 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
1859 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
1862 if (DATA_REG_P (operands[0]))
1864 if (DATA_REG_P (operands[2]))
1865 return "add%.l %R2,%R0\;addx%.l %2,%0";
1866 else if (GET_CODE (operands[2]) == MEM
1867 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
1868 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
1874 if (GET_CODE (operands[2]) == REG)
1876 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
1879 else if (CONSTANT_P (operands[2]))
1880 split_double (operands[2], &high, &low);
1883 low = adjust_address (operands[2], SImode, 4);
1887 operands[1] = low, operands[2] = high;
1888 xoperands[0] = operands[3];
1889 if (GET_CODE (operands[1]) == CONST_INT
1890 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1891 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
1893 xoperands[1] = operands[2];
1895 output_asm_insn (output_move_simode (xoperands), xoperands);
1896 if (GET_CODE (operands[1]) == CONST_INT)
1898 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
1899 return "addq%.l %1,%R0\;addx%.l %3,%0";
1900 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
1902 operands[1] = GEN_INT (-INTVAL (operands[1]));
1903 return "subq%.l %1,%R0\;subx%.l %3,%0";
1906 return "add%.l %1,%R0\;addx%.l %3,%0";
1909 else if (GET_CODE (operands[0]) == MEM)
1911 if (GET_CODE (operands[2]) == MEM
1912 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
1913 return "add%.l %2,%0\;addx%.l %2,%0";
1915 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1917 operands[1] = gen_rtx_MEM (SImode,
1918 plus_constant (XEXP(operands[0], 0), -8));
1919 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
1921 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1923 operands[1] = XEXP(operands[0], 0);
1924 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
1928 operands[1] = adjust_address (operands[0], SImode, 4);
1929 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
1936 (define_insn "addsi_lshrsi_31"
1937 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
1938 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
1943 operands[2] = operands[0];
1944 operands[3] = gen_label_rtx();
1945 if (GET_CODE (operands[0]) == MEM)
1947 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1948 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
1949 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1950 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
1952 output_asm_insn ("move%.l %1,%0", operands);
1953 output_asm_insn (MOTOROLA ? "jbpl %l3" : "jpl %l3", operands);
1954 output_asm_insn ("addq%.l %#1,%2", operands);
1955 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1956 CODE_LABEL_NUMBER (operands[3]));
1960 (define_expand "addsi3"
1961 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1962 (plus:SI (match_operand:SI 1 "general_operand" "")
1963 (match_operand:SI 2 "general_src_operand" "")))]
1967 ;; Note that the middle two alternatives are near-duplicates
1968 ;; in order to handle insns generated by reload.
1969 ;; This is needed since they are not themselves reloaded,
1970 ;; so commutativity won't apply to them.
1971 (define_insn "*addsi3_internal"
1972 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
1973 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
1974 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
1978 "* return output_addsi3 (operands);")
1980 (define_insn "*addsi3_5200"
1981 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
1982 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
1983 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
1985 "* return output_addsi3 (operands);")
1988 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
1989 (plus:SI (match_operand:SI 1 "general_operand" "0")
1991 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
1995 (define_insn "addhi3"
1996 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
1997 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1998 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2001 if (GET_CODE (operands[2]) == CONST_INT)
2003 /* If the constant would be a negative number when interpreted as
2004 HImode, make it negative. This is usually, but not always, done
2005 elsewhere in the compiler. First check for constants out of range,
2006 which could confuse us. */
2008 if (INTVAL (operands[2]) >= 32768)
2009 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2011 if (INTVAL (operands[2]) > 0
2012 && INTVAL (operands[2]) <= 8)
2013 return "addq%.w %2,%0";
2014 if (INTVAL (operands[2]) < 0
2015 && INTVAL (operands[2]) >= -8)
2017 operands[2] = GEN_INT (- INTVAL (operands[2]));
2018 return "subq%.w %2,%0";
2020 /* On the CPU32 it is faster to use two addqw instructions to
2021 add a small integer (8 < N <= 16) to a register.
2022 Likewise for subqw. */
2023 if (TARGET_CPU32 && REG_P (operands[0]))
2025 if (INTVAL (operands[2]) > 8
2026 && INTVAL (operands[2]) <= 16)
2028 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2029 return "addq%.w %#8,%0\;addq%.w %2,%0";
2031 if (INTVAL (operands[2]) < -8
2032 && INTVAL (operands[2]) >= -16)
2034 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2035 return "subq%.w %#8,%0\;subq%.w %2,%0";
2038 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2039 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2041 return "add%.w %2,%0";
2044 ;; These insns must use MATCH_DUP instead of the more expected
2045 ;; use of a matching constraint because the "output" here is also
2046 ;; an input, so you can't use the matching constraint. That also means
2047 ;; that you can't use the "%", so you need patterns with the matched
2048 ;; operand in both positions.
2051 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2052 (plus:HI (match_dup 0)
2053 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2056 if (GET_CODE (operands[1]) == CONST_INT)
2058 /* If the constant would be a negative number when interpreted as
2059 HImode, make it negative. This is usually, but not always, done
2060 elsewhere in the compiler. First check for constants out of range,
2061 which could confuse us. */
2063 if (INTVAL (operands[1]) >= 32768)
2064 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2066 if (INTVAL (operands[1]) > 0
2067 && INTVAL (operands[1]) <= 8)
2068 return "addq%.w %1,%0";
2069 if (INTVAL (operands[1]) < 0
2070 && INTVAL (operands[1]) >= -8)
2072 operands[1] = GEN_INT (- INTVAL (operands[1]));
2073 return "subq%.w %1,%0";
2075 /* On the CPU32 it is faster to use two addqw instructions to
2076 add a small integer (8 < N <= 16) to a register.
2077 Likewise for subqw. */
2078 if (TARGET_CPU32 && REG_P (operands[0]))
2080 if (INTVAL (operands[1]) > 8
2081 && INTVAL (operands[1]) <= 16)
2083 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2084 return "addq%.w %#8,%0\;addq%.w %1,%0";
2086 if (INTVAL (operands[1]) < -8
2087 && INTVAL (operands[1]) >= -16)
2089 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2090 return "subq%.w %#8,%0\;subq%.w %1,%0";
2093 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2094 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2096 return "add%.w %1,%0";
2100 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2101 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2105 if (GET_CODE (operands[1]) == CONST_INT)
2107 /* If the constant would be a negative number when interpreted as
2108 HImode, make it negative. This is usually, but not always, done
2109 elsewhere in the compiler. First check for constants out of range,
2110 which could confuse us. */
2112 if (INTVAL (operands[1]) >= 32768)
2113 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2115 if (INTVAL (operands[1]) > 0
2116 && INTVAL (operands[1]) <= 8)
2117 return "addq%.w %1,%0";
2118 if (INTVAL (operands[1]) < 0
2119 && INTVAL (operands[1]) >= -8)
2121 operands[1] = GEN_INT (- INTVAL (operands[1]));
2122 return "subq%.w %1,%0";
2124 /* On the CPU32 it is faster to use two addqw instructions to
2125 add a small integer (8 < N <= 16) to a register.
2126 Likewise for subqw. */
2127 if (TARGET_CPU32 && REG_P (operands[0]))
2129 if (INTVAL (operands[1]) > 8
2130 && INTVAL (operands[1]) <= 16)
2132 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2133 return "addq%.w %#8,%0\;addq%.w %1,%0";
2135 if (INTVAL (operands[1]) < -8
2136 && INTVAL (operands[1]) >= -16)
2138 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2139 return "subq%.w %#8,%0\;subq%.w %1,%0";
2142 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2143 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2145 return "add%.w %1,%0";
2148 (define_insn "addqi3"
2149 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2150 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2151 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2154 if (GET_CODE (operands[2]) == CONST_INT)
2156 if (INTVAL (operands[2]) >= 128)
2157 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2159 if (INTVAL (operands[2]) > 0
2160 && INTVAL (operands[2]) <= 8)
2161 return "addq%.b %2,%0";
2162 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2164 operands[2] = GEN_INT (- INTVAL (operands[2]));
2165 return "subq%.b %2,%0";
2168 return "add%.b %2,%0";
2172 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2173 (plus:QI (match_dup 0)
2174 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2177 if (GET_CODE (operands[1]) == CONST_INT)
2179 if (INTVAL (operands[1]) >= 128)
2180 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2182 if (INTVAL (operands[1]) > 0
2183 && INTVAL (operands[1]) <= 8)
2184 return "addq%.b %1,%0";
2185 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2187 operands[1] = GEN_INT (- INTVAL (operands[1]));
2188 return "subq%.b %1,%0";
2191 return "add%.b %1,%0";
2195 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2196 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2200 if (GET_CODE (operands[1]) == CONST_INT)
2202 if (INTVAL (operands[1]) >= 128)
2203 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2205 if (INTVAL (operands[1]) > 0
2206 && INTVAL (operands[1]) <= 8)
2207 return "addq%.b %1,%0";
2208 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2210 operands[1] = GEN_INT (- INTVAL (operands[1]));
2211 return "subq%.b %1,%0";
2214 return "add%.b %1,%0";
2217 (define_expand "adddf3"
2218 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2219 (plus:DF (match_operand:DF 1 "general_operand" "")
2220 (match_operand:DF 2 "general_operand" "")))]
2225 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2226 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2227 (match_operand:DF 1 "general_operand" "0")))]
2232 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2233 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2234 (match_operand:DF 1 "general_operand" "0")))]
2239 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2240 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2241 (match_operand:DF 1 "general_operand" "0")))]
2246 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2247 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2248 (match_operand:DF 2 "general_operand" "fmG")))]
2251 if (REG_P (operands[2]))
2252 return "f%&add%.x %2,%0";
2253 return "f%&add%.d %f2,%0";
2256 (define_expand "addsf3"
2257 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2258 (plus:SF (match_operand:SF 1 "general_operand" "")
2259 (match_operand:SF 2 "general_operand" "")))]
2264 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2265 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2266 (match_operand:SF 1 "general_operand" "0")))]
2271 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2272 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2273 (match_operand:SF 1 "general_operand" "0")))]
2278 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2279 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2280 (match_operand:SF 1 "general_operand" "0")))]
2285 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2286 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2287 (match_operand:SF 2 "general_operand" "fdmF")))]
2290 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2291 return "f%$add%.x %2,%0";
2292 return "f%$add%.s %f2,%0";
2295 ;; subtract instructions
2297 (define_insn "subdi_sexthishl32"
2298 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2299 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2300 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2302 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2306 if (ADDRESS_REG_P (operands[0]))
2307 return "sub%.w %2,%0";
2308 else if (ADDRESS_REG_P (operands[3]))
2309 return "move%.w %2,%3\;sub%.l %3,%0";
2311 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
2314 (define_insn "subdi_dishl32"
2315 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2316 (minus:DI (match_dup 0)
2317 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2322 if (GET_CODE (operands[1]) == REG)
2323 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2325 operands[1] = adjust_address (operands[1], SImode, 4);
2326 return "sub%.l %1,%0";
2329 (define_insn "subdi3"
2330 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,o<>,d,d,d")
2331 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2332 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2333 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2336 if (DATA_REG_P (operands[0]))
2338 if (DATA_REG_P (operands[2]))
2339 return "sub%.l %R2,%R0\;subx%.l %2,%0";
2340 else if (GET_CODE (operands[2]) == MEM
2341 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2343 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
2350 if (GET_CODE (operands[2]) == REG)
2352 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2355 else if (CONSTANT_P (operands[2]))
2356 split_double (operands[2], &high, &low);
2359 low = adjust_address (operands[2], SImode, 4);
2363 operands[1] = low, operands[2] = high;
2364 xoperands[0] = operands[3];
2365 if (GET_CODE (operands[1]) == CONST_INT
2366 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2367 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2369 xoperands[1] = operands[2];
2371 output_asm_insn (output_move_simode (xoperands), xoperands);
2372 if (GET_CODE (operands[1]) == CONST_INT)
2374 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2375 return "subq%.l %1,%R0\;subx%.l %3,%0";
2376 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2378 operands[1] = GEN_INT (-INTVAL (operands[1]));
2379 return "addq%.l %1,%R0\;addx%.l %3,%0";
2382 return "sub%.l %1,%R0\;subx%.l %3,%0";
2385 else if (GET_CODE (operands[0]) == MEM)
2387 if (GET_CODE (operands[2]) == MEM
2388 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2389 return "sub%.l %2,%0\;subx%.l %2,%0";
2391 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2394 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2395 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2397 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2399 operands[1] = XEXP(operands[0], 0);
2400 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
2404 operands[1] = adjust_address (operands[0], SImode, 4);
2405 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
2412 (define_insn "subsi3"
2413 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d,a")
2414 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2415 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2420 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2421 (minus:SI (match_operand:SI 1 "general_operand" "0")
2423 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2427 (define_insn "subhi3"
2428 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2429 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2430 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2435 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2436 (minus:HI (match_dup 0)
2437 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2441 (define_insn "subqi3"
2442 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2443 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2444 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2449 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2450 (minus:QI (match_dup 0)
2451 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2455 (define_expand "subdf3"
2456 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2457 (minus:DF (match_operand:DF 1 "general_operand" "")
2458 (match_operand:DF 2 "general_operand" "")))]
2463 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2464 (minus:DF (match_operand:DF 1 "general_operand" "0")
2465 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2470 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2471 (minus:DF (match_operand:DF 1 "general_operand" "0")
2472 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2477 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2478 (minus:DF (match_operand:DF 1 "general_operand" "0")
2479 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2484 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2485 (minus:DF (match_operand:DF 1 "general_operand" "0")
2486 (match_operand:DF 2 "general_operand" "fmG")))]
2489 if (REG_P (operands[2]))
2490 return "f%&sub%.x %2,%0";
2491 return "f%&sub%.d %f2,%0";
2494 (define_expand "subsf3"
2495 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2496 (minus:SF (match_operand:SF 1 "general_operand" "")
2497 (match_operand:SF 2 "general_operand" "")))]
2502 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2503 (minus:SF (match_operand:SF 1 "general_operand" "0")
2504 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2509 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2510 (minus:SF (match_operand:SF 1 "general_operand" "0")
2511 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2516 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2517 (minus:SF (match_operand:SF 1 "general_operand" "0")
2518 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2523 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2524 (minus:SF (match_operand:SF 1 "general_operand" "0")
2525 (match_operand:SF 2 "general_operand" "fdmF")))]
2528 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2529 return "f%$sub%.x %2,%0";
2530 return "f%$sub%.s %f2,%0";
2533 ;; multiply instructions
2535 (define_insn "mulhi3"
2536 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
2537 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2538 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2541 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2544 (define_insn "mulhisi3"
2545 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2546 (mult:SI (sign_extend:SI
2547 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2549 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2552 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2556 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2557 (mult:SI (sign_extend:SI
2558 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2559 (match_operand:SI 2 "const_int_operand" "n")))]
2560 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2562 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
2565 (define_expand "mulsi3"
2566 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2567 (mult:SI (match_operand:SI 1 "general_operand" "")
2568 (match_operand:SI 2 "general_operand" "")))]
2569 "TARGET_68020 || TARGET_COLDFIRE"
2573 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2574 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2575 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
2581 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2582 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2583 (match_operand:SI 2 "general_operand" "d<Q>")))]
2587 (define_insn "umulhisi3"
2588 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2589 (mult:SI (zero_extend:SI
2590 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2592 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
2595 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2599 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2600 (mult:SI (zero_extend:SI
2601 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2602 (match_operand:SI 2 "const_int_operand" "n")))]
2603 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2605 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
2608 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2609 ;; proper matching constraint. This is because the matching is between
2610 ;; the high-numbered word of the DImode operand[0] and operand[1].
2611 (define_expand "umulsidi3"
2613 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2614 (mult:SI (match_operand:SI 1 "register_operand" "")
2615 (match_operand:SI 2 "register_operand" "")))
2616 (set (subreg:SI (match_dup 0) 0)
2617 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2618 (zero_extend:DI (match_dup 2)))
2619 (const_int 32))))])]
2620 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2624 [(set (match_operand:SI 0 "register_operand" "=d")
2625 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2626 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2627 (set (match_operand:SI 3 "register_operand" "=d")
2628 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2629 (zero_extend:DI (match_dup 2)))
2631 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2634 ; Match immediate case. For 2.4 only match things < 2^31.
2635 ; It's tricky with larger values in these patterns since we need to match
2636 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2639 [(set (match_operand:SI 0 "register_operand" "=d")
2640 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2641 (match_operand:SI 2 "const_int_operand" "n")))
2642 (set (match_operand:SI 3 "register_operand" "=d")
2643 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2646 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
2647 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2650 (define_expand "mulsidi3"
2652 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
2653 (mult:SI (match_operand:SI 1 "register_operand" "")
2654 (match_operand:SI 2 "register_operand" "")))
2655 (set (subreg:SI (match_dup 0) 0)
2656 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2657 (sign_extend:DI (match_dup 2)))
2658 (const_int 32))))])]
2659 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2663 [(set (match_operand:SI 0 "register_operand" "=d")
2664 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2665 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2666 (set (match_operand:SI 3 "register_operand" "=d")
2667 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2668 (sign_extend:DI (match_dup 2)))
2670 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2674 [(set (match_operand:SI 0 "register_operand" "=d")
2675 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2676 (match_operand:SI 2 "const_int_operand" "n")))
2677 (set (match_operand:SI 3 "register_operand" "=d")
2678 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2681 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2684 (define_expand "umulsi3_highpart"
2686 [(set (match_operand:SI 0 "register_operand" "")
2689 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2690 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2692 (clobber (match_dup 3))])]
2693 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2696 operands[3] = gen_reg_rtx (SImode);
2698 if (GET_CODE (operands[2]) == CONST_INT)
2700 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
2703 /* We have to adjust the operand order for the matching constraints. */
2704 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2705 operands[1], operands[2]));
2711 [(set (match_operand:SI 0 "register_operand" "=d")
2714 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2715 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2717 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2718 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2721 (define_insn "const_umulsi3_highpart"
2722 [(set (match_operand:SI 0 "register_operand" "=d")
2725 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2726 (match_operand:DI 3 "const_uint32_operand" "n"))
2728 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2729 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2732 (define_expand "smulsi3_highpart"
2734 [(set (match_operand:SI 0 "register_operand" "")
2737 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
2738 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2740 (clobber (match_dup 3))])]
2741 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2744 operands[3] = gen_reg_rtx (SImode);
2745 if (GET_CODE (operands[2]) == CONST_INT)
2747 /* We have to adjust the operand order for the matching constraints. */
2748 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
2749 operands[1], operands[2]));
2755 [(set (match_operand:SI 0 "register_operand" "=d")
2758 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2759 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2761 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2762 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2765 (define_insn "const_smulsi3_highpart"
2766 [(set (match_operand:SI 0 "register_operand" "=d")
2769 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
2770 (match_operand:DI 3 "const_sint32_operand" "n"))
2772 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2773 "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2776 (define_expand "muldf3"
2777 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2778 (mult:DF (match_operand:DF 1 "general_operand" "")
2779 (match_operand:DF 2 "general_operand" "")))]
2784 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2785 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2786 (match_operand:DF 1 "general_operand" "0")))]
2791 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2792 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2793 (match_operand:DF 1 "general_operand" "0")))]
2798 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2799 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2800 (match_operand:DF 1 "general_operand" "0")))]
2805 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2806 (mult:DF (match_operand:DF 1 "general_operand" "%0")
2807 (match_operand:DF 2 "general_operand" "fmG")))]
2810 if (GET_CODE (operands[2]) == CONST_DOUBLE
2811 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
2813 int i = floating_exact_log2 (operands[2]);
2814 operands[2] = GEN_INT (i);
2815 return "fscale%.l %2,%0";
2817 if (REG_P (operands[2]))
2818 return "f%&mul%.x %2,%0";
2819 return "f%&mul%.d %f2,%0";
2822 (define_expand "mulsf3"
2823 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2824 (mult:SF (match_operand:SF 1 "general_operand" "")
2825 (match_operand:SF 2 "general_operand" "")))]
2830 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2831 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2832 (match_operand:SF 1 "general_operand" "0")))]
2835 return (TARGET_68040_ONLY
2837 : "fsglmul%.l %2,%0");
2841 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2842 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2843 (match_operand:SF 1 "general_operand" "0")))]
2846 return (TARGET_68040_ONLY
2848 : "fsglmul%.w %2,%0");
2852 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2853 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2854 (match_operand:SF 1 "general_operand" "0")))]
2857 return (TARGET_68040_ONLY
2859 : "fsglmul%.b %2,%0");
2863 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2864 (mult:SF (match_operand:SF 1 "general_operand" "%0")
2865 (match_operand:SF 2 "general_operand" "fdmF")))]
2868 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2869 return (TARGET_68040_ONLY
2871 : "fsglmul%.x %2,%0");
2872 return (TARGET_68040_ONLY
2874 : "fsglmul%.s %f2,%0");
2877 ;; divide instructions
2879 (define_expand "divdf3"
2880 [(set (match_operand:DF 0 "nonimmediate_operand" "")
2881 (div:DF (match_operand:DF 1 "general_operand" "")
2882 (match_operand:DF 2 "general_operand" "")))]
2887 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2888 (div:DF (match_operand:DF 1 "general_operand" "0")
2889 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2894 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2895 (div:DF (match_operand:DF 1 "general_operand" "0")
2896 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2901 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2902 (div:DF (match_operand:DF 1 "general_operand" "0")
2903 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2908 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
2909 (div:DF (match_operand:DF 1 "general_operand" "0")
2910 (match_operand:DF 2 "general_operand" "fmG")))]
2913 if (REG_P (operands[2]))
2914 return "f%&div%.x %2,%0";
2915 return "f%&div%.d %f2,%0";
2918 (define_expand "divsf3"
2919 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2920 (div:SF (match_operand:SF 1 "general_operand" "")
2921 (match_operand:SF 2 "general_operand" "")))]
2926 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2927 (div:SF (match_operand:SF 1 "general_operand" "0")
2928 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2931 return (TARGET_68040_ONLY
2933 : "fsgldiv%.l %2,%0");
2937 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2938 (div:SF (match_operand:SF 1 "general_operand" "0")
2939 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2942 return (TARGET_68040_ONLY
2944 : "fsgldiv%.w %2,%0");
2948 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2949 (div:SF (match_operand:SF 1 "general_operand" "0")
2950 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2953 return (TARGET_68040_ONLY
2955 : "fsgldiv%.b %2,%0");
2959 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2960 (div:SF (match_operand:SF 1 "general_operand" "0")
2961 (match_operand:SF 2 "general_operand" "fdmF")))]
2964 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2965 return (TARGET_68040_ONLY
2967 : "fsgldiv%.x %2,%0");
2968 return (TARGET_68040_ONLY
2970 : "fsgldiv%.s %f2,%0");
2973 ;; Remainder instructions.
2975 (define_expand "divmodsi4"
2977 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2978 (div:SI (match_operand:SI 1 "general_operand" "")
2979 (match_operand:SI 2 "general_src_operand" "")))
2980 (set (match_operand:SI 3 "nonimmediate_operand" "")
2981 (mod:SI (match_dup 1) (match_dup 2)))])]
2982 "TARGET_68020 || TARGET_CF_HWDIV"
2986 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2987 (div:SI (match_operand:SI 1 "general_operand" "0")
2988 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
2989 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
2990 (mod:SI (match_dup 1) (match_dup 2)))]
2993 if (find_reg_note (insn, REG_UNUSED, operands[3]))
2994 return "divs%.l %2,%0";
2995 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
2996 return "rems%.l %2,%3:%0";
2998 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3002 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3003 (div:SI (match_operand:SI 1 "general_operand" "0")
3004 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3005 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3006 (mod:SI (match_dup 1) (match_dup 2)))]
3009 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3010 return "divs%.l %2,%0";
3012 return "divsl%.l %2,%3:%0";
3015 (define_expand "udivmodsi4"
3017 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3018 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3019 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3020 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3021 (umod:SI (match_dup 1) (match_dup 2)))])]
3022 "TARGET_68020 || TARGET_CF_HWDIV"
3026 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3027 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3028 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3029 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3030 (umod:SI (match_dup 1) (match_dup 2)))]
3033 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3034 return "divu%.l %2,%0";
3035 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3036 return "remu%.l %2,%3:%0";
3038 return "remu%.l %2,%3:%0\;divu%.l %2,%0";
3042 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3043 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3044 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3045 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3046 (umod:SI (match_dup 1) (match_dup 2)))]
3047 "TARGET_68020 && !TARGET_COLDFIRE"
3049 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3050 return "divu%.l %2,%0";
3052 return "divul%.l %2,%3:%0";
3055 (define_insn "divmodhi4"
3056 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3057 (div:HI (match_operand:HI 1 "general_operand" "0")
3058 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3059 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3060 (mod:HI (match_dup 1) (match_dup 2)))]
3061 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3063 output_asm_insn (MOTOROLA ?
3064 "ext%.l %0\;divs%.w %2,%0" :
3065 "extl %0\;divs %2,%0",
3067 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3070 return "move%.l %0,%3\;swap %3";
3076 (define_insn "udivmodhi4"
3077 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3078 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3079 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3080 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3081 (umod:HI (match_dup 1) (match_dup 2)))]
3082 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3084 output_asm_insn (MOTOROLA ?
3085 "and%.l %#0xFFFF,%0\;divu%.w %2,%0" :
3086 "and%.l %#0xFFFF,%0\;divu %2,%0",
3088 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3091 return "move%.l %0,%3\;swap %3";
3097 ;; logical-and instructions
3099 ;; "anddi3" is mainly here to help combine().
3100 (define_insn "anddi3"
3101 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3102 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3103 (match_operand:DI 2 "general_operand" "dn,don")))]
3107 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3108 if (CONSTANT_P (operands[2]))
3112 split_double (operands[2], &hi, &lo);
3114 switch (INTVAL (hi))
3117 output_asm_insn ("clr%.l %0", operands);
3125 xoperands[0] = operands[0];
3127 output_asm_insn (output_andsi3 (xoperands), xoperands);
3130 if (GET_CODE (operands[0]) == REG)
3131 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3133 operands[0] = adjust_address (operands[0], SImode, 4);
3134 switch (INTVAL (lo))
3137 output_asm_insn ("clr%.l %0", operands);
3145 xoperands[0] = operands[0];
3147 output_asm_insn (output_andsi3 (xoperands), xoperands);
3152 if (GET_CODE (operands[0]) != REG)
3154 operands[1] = adjust_address (operands[0], SImode, 4);
3155 return "and%.l %2,%0\;and%.l %R2,%1";
3157 if (GET_CODE (operands[2]) != REG)
3159 operands[1] = adjust_address (operands[2], SImode, 4);
3160 return "and%.l %2,%0\;and%.l %1,%R0";
3162 return "and%.l %2,%0\;and%.l %R2,%R0";
3165 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3166 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3167 ;; can't allocate pseudos into it.
3169 (define_expand "andsi3"
3170 [(set (match_operand:SI 0 "not_sp_operand" "")
3171 (and:SI (match_operand:SI 1 "general_operand" "")
3172 (match_operand:SI 2 "general_src_operand" "")))]
3176 (define_insn "andsi3_internal"
3177 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3178 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3179 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3182 return output_andsi3 (operands);
3185 (define_insn "andsi3_5200"
3186 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3187 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3188 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3192 (define_insn "andhi3"
3193 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3194 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3195 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3200 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3201 (and:HI (match_dup 0)
3202 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3207 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3208 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3213 (define_insn "andqi3"
3214 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3215 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3216 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3221 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3222 (and:QI (match_dup 0)
3223 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3228 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3229 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3234 ;; inclusive-or instructions
3236 (define_insn "iordi_zext"
3237 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3238 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3239 (match_operand:DI 2 "general_operand" "0,0")))]
3245 if (GET_CODE (operands[0]) == REG)
3246 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3248 operands[0] = adjust_address (operands[0], SImode, 4);
3249 if (GET_MODE (operands[1]) == SImode)
3250 return "or%.l %1,%0";
3251 byte_mode = (GET_MODE (operands[1]) == QImode);
3252 if (GET_CODE (operands[0]) == MEM)
3253 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3256 return "or%.b %1,%0";
3258 return "or%.w %1,%0";
3261 ;; "iordi3" is mainly here to help combine().
3262 (define_insn "iordi3"
3263 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3264 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3265 (match_operand:DI 2 "general_operand" "dn,don")))]
3269 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3270 if (CONSTANT_P (operands[2]))
3274 split_double (operands[2], &hi, &lo);
3276 switch (INTVAL (hi))
3281 /* FIXME : a scratch register would be welcome here if operand[0]
3282 is not a register */
3283 output_asm_insn ("move%.l %#-1,%0", operands);
3289 xoperands[0] = operands[0];
3291 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3294 if (GET_CODE (operands[0]) == REG)
3295 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3297 operands[0] = adjust_address (operands[0], SImode, 4);
3298 switch (INTVAL (lo))
3303 /* FIXME : a scratch register would be welcome here if operand[0]
3304 is not a register */
3305 output_asm_insn ("move%.l %#-1,%0", operands);
3311 xoperands[0] = operands[0];
3313 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3318 if (GET_CODE (operands[0]) != REG)
3320 operands[1] = adjust_address (operands[0], SImode, 4);
3321 return "or%.l %2,%0\;or%.l %R2,%1";
3323 if (GET_CODE (operands[2]) != REG)
3325 operands[1] = adjust_address (operands[2], SImode, 4);
3326 return "or%.l %2,%0\;or%.l %1,%R0";
3328 return "or%.l %2,%0\;or%.l %R2,%R0";
3331 (define_expand "iorsi3"
3332 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3333 (ior:SI (match_operand:SI 1 "general_operand" "")
3334 (match_operand:SI 2 "general_src_operand" "")))]
3338 (define_insn "iorsi3_internal"
3339 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3340 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3341 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3344 return output_iorsi3 (operands);
3347 (define_insn "iorsi3_5200"
3348 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3349 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3350 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3354 (define_insn "iorhi3"
3355 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3356 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3357 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3362 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3363 (ior:HI (match_dup 0)
3364 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3369 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3370 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3375 (define_insn "iorqi3"
3376 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3377 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3378 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3383 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3384 (ior:QI (match_dup 0)
3385 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3390 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3391 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3396 ;; On all 68k models, this makes faster code in a special case.
3397 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3399 (define_insn "iorsi_zexthi_ashl16"
3400 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3401 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3402 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3407 if (GET_CODE (operands[2]) != REG)
3408 operands[2] = adjust_address (operands[2], HImode, 2);
3409 if (GET_CODE (operands[2]) != REG
3410 || REGNO (operands[2]) != REGNO (operands[0]))
3411 output_asm_insn ("move%.w %2,%0", operands);
3412 return "swap %0\;mov%.w %1,%0";
3415 (define_insn "iorsi_zext"
3416 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3417 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3418 (match_operand:SI 2 "general_operand" "0,0")))]
3424 byte_mode = (GET_MODE (operands[1]) == QImode);
3425 if (GET_CODE (operands[0]) == MEM)
3426 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3429 return "or%.b %1,%0";
3431 return "or%.w %1,%0";
3436 ;; "xordi3" is mainly here to help combine().
3437 (define_insn "xordi3"
3438 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3439 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3440 (match_operand:DI 2 "general_operand" "dn")))]
3444 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3446 if (CONSTANT_P (operands[2]))
3450 split_double (operands[2], &hi, &lo);
3452 switch (INTVAL (hi))
3457 output_asm_insn ("not%.l %0", operands);
3460 /* FIXME : a scratch register would be welcome here if
3461 -128 <= INTVAL (hi) < -1 */
3465 xoperands[0] = operands[0];
3467 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3470 if (GET_CODE (operands[0]) == REG)
3471 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3473 operands[0] = adjust_address (operands[0], SImode, 4);
3474 switch (INTVAL (lo))
3479 output_asm_insn ("not%.l %0", operands);
3482 /* FIXME : a scratch register would be welcome here if
3483 -128 <= INTVAL (lo) < -1 */
3485 /* FIXME : this should be merged with xorsi3 */
3489 xoperands[0] = operands[0];
3491 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3496 if (GET_CODE (operands[0]) != REG)
3498 operands[1] = adjust_address (operands[0], SImode, 4);
3499 return "eor%.l %2,%0\;eor%.l %R2,%1";
3501 if (GET_CODE (operands[2]) != REG)
3503 operands[1] = adjust_address (operands[2], SImode, 4);
3504 return "eor%.l %2,%0\;eor%.l %1,%R0";
3506 return "eor%.l %2,%0\;eor%.l %R2,%R0";
3509 (define_expand "xorsi3"
3510 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3511 (xor:SI (match_operand:SI 1 "general_operand" "")
3512 (match_operand:SI 2 "general_operand" "")))]
3516 (define_insn "xorsi3_internal"
3517 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
3518 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3519 (match_operand:SI 2 "general_operand" "di,dKT")))]
3523 return output_xorsi3 (operands);
3526 (define_insn "xorsi3_5200"
3527 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
3528 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3529 (match_operand:SI 2 "general_operand" "d,Ks")))]
3533 (define_insn "xorhi3"
3534 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3535 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3536 (match_operand:HI 2 "general_operand" "dn")))]
3541 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3542 (xor:HI (match_dup 0)
3543 (match_operand:HI 1 "general_operand" "dn")))]
3548 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3549 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3554 (define_insn "xorqi3"
3555 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3556 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3557 (match_operand:QI 2 "general_operand" "dn")))]
3562 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3563 (xor:QI (match_dup 0)
3564 (match_operand:QI 1 "general_operand" "dn")))]
3569 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3570 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3575 ;; negation instructions
3577 (define_expand "negdi2"
3578 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3579 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3583 if (TARGET_COLDFIRE)
3584 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3586 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3590 (define_insn "negdi2_internal"
3591 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
3592 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3595 if (which_alternative == 0)
3596 return "neg%.l %0\;negx%.l %0";
3597 if (GET_CODE (operands[0]) == REG)
3598 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3600 operands[1] = adjust_address (operands[0], SImode, 4);
3601 if (ADDRESS_REG_P (operands[0]))
3602 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
3604 return "neg%.l %1\;negx%.l %0";
3607 (define_insn "negdi2_5200"
3608 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3609 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3612 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3613 return "neg%.l %1\;negx%.l %0";
3616 (define_expand "negsi2"
3617 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3618 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3622 if (TARGET_COLDFIRE)
3623 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3625 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3629 (define_insn "negsi2_internal"
3630 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3631 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3635 (define_insn "negsi2_5200"
3636 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3637 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3641 (define_insn "neghi2"
3642 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3643 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3648 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3649 (neg:HI (match_dup 0)))]
3653 (define_insn "negqi2"
3654 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3655 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3660 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3661 (neg:QI (match_dup 0)))]
3665 ;; If using software floating point, just flip the sign bit.
3667 (define_expand "negsf2"
3668 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3669 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3678 target = operand_subword_force (operands[0], 0, SFmode);
3679 result = expand_binop (SImode, xor_optab,
3680 operand_subword_force (operands[1], 0, SFmode),
3681 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3685 if (result != target)
3686 emit_move_insn (result, target);
3688 /* Make a place for REG_EQUAL. */
3689 emit_move_insn (operands[0], operands[0]);
3695 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d")
3696 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3699 if (DATA_REG_P (operands[0]))
3701 operands[1] = GEN_INT (31);
3702 return "bchg %1,%0";
3704 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3705 return "f%$neg%.x %1,%0";
3706 return "f%$neg%.s %f1,%0";
3709 (define_expand "negdf2"
3710 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3711 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3722 target = operand_subword (operands[0], 0, 1, DFmode);
3723 result = expand_binop (SImode, xor_optab,
3724 operand_subword_force (operands[1], 0, DFmode),
3725 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
3729 if (result != target)
3730 emit_move_insn (result, target);
3732 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3733 operand_subword_force (operands[1], 1, DFmode));
3735 insns = get_insns ();
3738 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3744 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,d")
3745 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3748 if (DATA_REG_P (operands[0]))
3750 operands[1] = GEN_INT (31);
3751 return "bchg %1,%0";
3753 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3754 return "f%&neg%.x %1,%0";
3755 return "f%&neg%.d %f1,%0";
3758 ;; Sqrt instruction for the 68881
3760 (define_insn "sqrtsf2"
3761 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3762 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3765 if (FP_REG_P (operands[1]))
3766 return "f%$sqrt%.x %1,%0";
3768 return "f%$sqrt%.s %1,%0";
3771 (define_insn "sqrtdf2"
3772 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3773 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3776 if (FP_REG_P (operands[1]))
3777 return "f%&sqrt%.x %1,%0";
3779 return "f%&sqrt%.d %1,%0";
3782 ;; Absolute value instructions
3783 ;; If using software floating point, just zero the sign bit.
3785 (define_expand "abssf2"
3786 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3787 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3796 target = operand_subword_force (operands[0], 0, SFmode);
3797 result = expand_binop (SImode, and_optab,
3798 operand_subword_force (operands[1], 0, SFmode),
3799 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3803 if (result != target)
3804 emit_move_insn (result, target);
3806 /* Make a place for REG_EQUAL. */
3807 emit_move_insn (operands[0], operands[0]);
3813 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3814 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
3817 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3818 return "f%$abs%.x %1,%0";
3819 return "f%$abs%.s %f1,%0";
3822 (define_expand "absdf2"
3823 [(set (match_operand:DF 0 "nonimmediate_operand" "")
3824 (abs:DF (match_operand:DF 1 "general_operand" "")))]
3835 target = operand_subword (operands[0], 0, 1, DFmode);
3836 result = expand_binop (SImode, and_optab,
3837 operand_subword_force (operands[1], 0, DFmode),
3838 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
3842 if (result != target)
3843 emit_move_insn (result, target);
3845 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3846 operand_subword_force (operands[1], 1, DFmode));
3848 insns = get_insns ();
3851 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3857 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3858 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
3861 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3862 return "f%&abs%.x %1,%0";
3863 return "f%&abs%.d %f1,%0";
3866 ;; one complement instructions
3868 ;; "one_cmpldi2" is mainly here to help combine().
3869 (define_insn "one_cmpldi2"
3870 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
3871 (not:DI (match_operand:DI 1 "general_operand" "0")))]
3875 if (GET_CODE (operands[0]) == REG)
3876 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3877 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
3878 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3879 operands[1] = operands[0];
3881 operands[1] = adjust_address (operands[0], SImode, 4);
3882 return "not%.l %1\;not%.l %0";
3885 (define_expand "one_cmplsi2"
3886 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3887 (not:SI (match_operand:SI 1 "general_operand" "")))]
3891 if (TARGET_COLDFIRE)
3892 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
3894 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
3898 (define_insn "one_cmplsi2_internal"
3899 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3900 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3904 (define_insn "one_cmplsi2_5200"
3905 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3906 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3910 (define_insn "one_cmplhi2"
3911 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3912 (not:HI (match_operand:HI 1 "general_operand" "0")))]
3917 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3918 (not:HI (match_dup 0)))]
3922 (define_insn "one_cmplqi2"
3923 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3924 (not:QI (match_operand:QI 1 "general_operand" "0")))]
3929 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3930 (not:QI (match_dup 0)))]
3934 ;; arithmetic shift instructions
3935 ;; We don't need the shift memory by 1 bit instruction
3937 (define_insn "ashldi_extsi"
3938 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
3940 (match_operator:DI 2 "extend_operator"
3941 [(match_operand:SI 1 "general_operand" "rm")])
3946 if (GET_CODE (operands[0]) == REG)
3947 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3949 operands[2] = adjust_address (operands[0], SImode, 4);
3950 if (ADDRESS_REG_P (operands[0]))
3951 return "move%.l %1,%0\;sub%.l %2,%2";
3953 return "move%.l %1,%0\;clr%.l %2";
3956 (define_insn "ashldi_sexthi"
3957 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
3958 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
3960 (clobber (match_scratch:SI 2 "=a,X"))]
3964 if (GET_CODE (operands[0]) == MEM)
3966 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3967 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
3968 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
3969 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
3972 operands[3] = adjust_address (operands[0], SImode, 4);
3973 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
3976 else if (DATA_REG_P (operands[0]))
3977 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
3979 return "move%.w %1,%0\;sub%.l %R0,%R0";
3982 (define_insn "ashldi_const32"
3983 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
3984 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
3989 if (GET_CODE (operands[1]) == REG)
3990 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3992 operands[3] = adjust_address (operands[1], SImode, 4);
3993 if (GET_CODE (operands[0]) == REG)
3994 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3995 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3996 return "clr%.l %0\;move%.l %3,%0";
3997 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
3998 return "move%.l %3,%0\;clr%.l %0";
4000 operands[2] = adjust_address (operands[0], SImode, 4);
4001 if (ADDRESS_REG_P (operands[2]))
4002 return "move%.l %3,%0\;sub%.l %2,%2";
4004 return "move%.l %3,%0\;clr%.l %2";
4007 ;; The predicate below must be general_operand, because ashldi3 allows that
4008 (define_insn "ashldi_const"
4009 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4010 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4011 (match_operand 2 "const_int_operand" "n")))]
4013 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4014 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4015 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4017 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4018 if (INTVAL (operands[2]) == 1)
4019 return "add%.l %1,%1\;addx%.l %0,%0";
4020 else if (INTVAL (operands[2]) == 8)
4021 return "rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1";
4022 else if (INTVAL (operands[2]) == 16)
4023 return "swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1";
4024 else if (INTVAL (operands[2]) == 48)
4025 return "mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0";
4026 else if (INTVAL (operands[2]) == 2)
4027 return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
4028 else if (INTVAL (operands[2]) == 3)
4029 return "add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0";
4030 else /* 32 < INTVAL (operands[2]) <= 63 */
4032 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4033 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asl%.l %2,%1" :
4034 "moveq %2,%0\;asl%.l %0,%1", operands);
4035 return "mov%.l %1,%0\;moveq %#0,%1";
4039 (define_expand "ashldi3"
4040 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4041 (ashift:DI (match_operand:DI 1 "general_operand" "")
4042 (match_operand 2 "const_int_operand" "")))]
4046 /* ??? This is a named pattern like this is not allowed to FAIL based
4048 if (GET_CODE (operands[2]) != CONST_INT
4049 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4050 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4051 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4055 ;; On most 68k models, this makes faster code in a special case.
4057 (define_insn "ashlsi_16"
4058 [(set (match_operand:SI 0 "register_operand" "=d")
4059 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4064 return "swap %0\;clr%.w %0";
4067 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4068 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4070 ;; On the 68000, this makes faster code in a special case.
4072 (define_insn "ashlsi_17_24"
4073 [(set (match_operand:SI 0 "register_operand" "=d")
4074 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4075 (match_operand:SI 2 "const_int_operand" "n")))]
4076 "(! TARGET_68020 && !TARGET_COLDFIRE
4077 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4081 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4082 return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
4085 (define_insn "ashlsi3"
4086 [(set (match_operand:SI 0 "register_operand" "=d")
4087 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4088 (match_operand:SI 2 "general_operand" "dI")))]
4091 if (operands[2] == const1_rtx)
4093 cc_status.flags = CC_NO_OVERFLOW;
4094 return "add%.l %0,%0";
4096 return "lsl%.l %2,%0";
4099 (define_insn "ashlhi3"
4100 [(set (match_operand:HI 0 "register_operand" "=d")
4101 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4102 (match_operand:HI 2 "general_operand" "dI")))]
4107 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4108 (ashift:HI (match_dup 0)
4109 (match_operand:HI 1 "general_operand" "dI")))]
4113 (define_insn "ashlqi3"
4114 [(set (match_operand:QI 0 "register_operand" "=d")
4115 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4116 (match_operand:QI 2 "general_operand" "dI")))]
4121 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4122 (ashift:QI (match_dup 0)
4123 (match_operand:QI 1 "general_operand" "dI")))]
4127 ;; On most 68k models, this makes faster code in a special case.
4129 (define_insn "ashrsi_16"
4130 [(set (match_operand:SI 0 "register_operand" "=d")
4131 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4134 "swap %0\;ext%.l %0")
4136 ;; On the 68000, this makes faster code in a special case.
4139 [(set (match_operand:SI 0 "register_operand" "=d")
4140 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4141 (match_operand:SI 2 "const_int_operand" "n")))]
4142 "(! TARGET_68020 && !TARGET_COLDFIRE
4143 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4145 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4146 return "swap %0\;asr%.w %2,%0\;ext%.l %0";
4149 (define_insn "subreghi1ashrdi_const32"
4150 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4151 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4152 (const_int 32)) 6))]
4155 if (GET_CODE (operands[1]) != REG)
4156 operands[1] = adjust_address (operands[1], HImode, 2);
4157 return "move%.w %1,%0";
4160 (define_insn "subregsi1ashrdi_const32"
4161 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4162 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4163 (const_int 32)) 4))]
4166 return "move%.l %1,%0";
4169 (define_insn "ashrdi_const32"
4170 [(set (match_operand:DI 0 "register_operand" "=d")
4171 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4176 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4178 return "move%.l %1,%2\;smi %0\;extb%.l %0";
4180 return "move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0";
4183 (define_insn "ashrdi_const32_mem"
4184 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,<")
4185 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4187 (clobber (match_scratch:SI 2 "=d,d"))]
4191 if (which_alternative == 1)
4192 operands[3] = operands[0];
4194 operands[3] = adjust_address (operands[0], SImode, 4);
4196 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
4198 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
4201 ;; The predicate below must be general_operand, because ashrdi3 allows that
4202 (define_insn "ashrdi_const"
4203 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4204 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4205 (match_operand 2 "const_int_operand" "n")))]
4207 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4208 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4209 || INTVAL (operands[2]) == 31
4210 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4212 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4213 if (INTVAL (operands[2]) == 63)
4214 return "add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1";
4216 if (INTVAL (operands[2]) == 1)
4217 return "asr%.l %#1,%0\;roxr%.l %#1,%1";
4218 else if (INTVAL (operands[2]) == 8)
4219 return "move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1";
4220 else if (INTVAL (operands[2]) == 16)
4221 return "move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1";
4222 else if (INTVAL (operands[2]) == 48)
4223 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
4224 else if (INTVAL (operands[2]) == 31)
4225 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
4226 else if (INTVAL (operands[2]) == 2)
4227 return "asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1";
4228 else if (INTVAL (operands[2]) == 3)
4229 return "asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1";
4230 else /* 32 < INTVAL (operands[2]) <= 63 */
4232 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4233 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
4234 "moveq %2,%1\;asr%.l %1,%0", operands);
4235 output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
4236 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
4237 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
4241 (define_expand "ashrdi3"
4242 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4243 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4244 (match_operand 2 "const_int_operand" "")))]
4248 /* ??? This is a named pattern like this is not allowed to FAIL based
4250 if (GET_CODE (operands[2]) != CONST_INT
4251 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4252 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4253 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4257 ;; On all 68k models, this makes faster code in a special case.
4259 (define_insn "ashrsi_31"
4260 [(set (match_operand:SI 0 "register_operand" "=d")
4261 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4265 return "add%.l %0,%0\;subx%.l %0,%0";
4268 (define_insn "ashrsi3"
4269 [(set (match_operand:SI 0 "register_operand" "=d")
4270 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4271 (match_operand:SI 2 "general_operand" "dI")))]
4275 (define_insn "ashrhi3"
4276 [(set (match_operand:HI 0 "register_operand" "=d")
4277 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4278 (match_operand:HI 2 "general_operand" "dI")))]
4283 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4284 (ashiftrt:HI (match_dup 0)
4285 (match_operand:HI 1 "general_operand" "dI")))]
4289 (define_insn "ashrqi3"
4290 [(set (match_operand:QI 0 "register_operand" "=d")
4291 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4292 (match_operand:QI 2 "general_operand" "dI")))]
4297 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4298 (ashiftrt:QI (match_dup 0)
4299 (match_operand:QI 1 "general_operand" "dI")))]
4303 ;; logical shift instructions
4305 ;; commented out because of reload problems in 950612-1.c
4308 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4309 ;; (const_int 32)) 4))
4310 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
4311 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4312 ;; (const_int 32)) 4))]
4315 ;; return "move%.l %0,%1";
4320 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4321 ;; (const_int 32)) 0))
4322 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
4323 ;; (lshiftrt:DI (match_dup 0)
4324 ;; (const_int 32)))]
4327 ;; if (GET_CODE (operands[1]) == REG)
4328 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4330 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4331 ;; return "move%.l %0,%2\;clr%.l %1";
4334 (define_insn "subreg1lshrdi_const32"
4335 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4336 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4337 (const_int 32)) 4))]
4340 return "move%.l %1,%0";
4343 (define_insn "lshrdi_const32"
4344 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,<,>")
4345 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4350 if (which_alternative == 1)
4351 return "move%.l %1,%0\;clr%.l %0";
4352 if (which_alternative == 2)
4353 return "clr%.l %0\;move%.l %1,%0";
4354 if (GET_CODE (operands[0]) == REG)
4355 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4357 operands[2] = adjust_address (operands[0], SImode, 4);
4358 if (GET_CODE (operands[1]) == REG)
4359 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4361 operands[3] = adjust_address (operands[1], SImode, 4);
4362 if (ADDRESS_REG_P (operands[0]))
4363 return "move%.l %1,%2\;sub%.l %0,%0";
4365 return "move%.l %1,%2\;clr%.l %0";
4368 ;; The predicate below must be general_operand, because lshrdi3 allows that
4369 (define_insn "lshrdi_const"
4370 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4371 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4372 (match_operand 2 "const_int_operand" "n")))]
4374 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4375 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4376 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4378 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4379 if (INTVAL (operands[2]) == 63)
4380 return "add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1";
4382 if (INTVAL (operands[2]) == 1)
4383 return "lsr%.l %#1,%0\;roxr%.l %#1,%1";
4384 else if (INTVAL (operands[2]) == 8)
4385 return "move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1";
4386 else if (INTVAL (operands[2]) == 16)
4387 return "move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0";
4388 else if (INTVAL (operands[2]) == 48)
4389 return "move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1";
4390 else if (INTVAL (operands[2]) == 2)
4391 return "lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1";
4392 else if (INTVAL (operands[2]) == 3)
4393 return "lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1";
4394 else /* 32 < INTVAL (operands[2]) <= 63 */
4396 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4397 output_asm_insn (INTVAL (operands[2]) <= 8 ? "lsr%.l %2,%0" :
4398 "moveq %2,%1\;lsr%.l %1,%0", operands);
4399 return "mov%.l %0,%1\;moveq %#0,%0";
4403 (define_expand "lshrdi3"
4404 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4405 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4406 (match_operand 2 "const_int_operand" "")))]
4409 /* ??? This is a named pattern like this is not allowed to FAIL based
4411 if (GET_CODE (operands[2]) != CONST_INT
4412 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4413 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4414 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4418 ;; On all 68k models, this makes faster code in a special case.
4420 (define_insn "lshrsi_31"
4421 [(set (match_operand:SI 0 "register_operand" "=d")
4422 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4426 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
4429 ;; On most 68k models, this makes faster code in a special case.
4431 (define_insn "lshrsi_16"
4432 [(set (match_operand:SI 0 "register_operand" "=d")
4433 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4438 return "clr%.w %0\;swap %0";
4441 ;; On the 68000, this makes faster code in a special case.
4443 (define_insn "lshrsi_17_24"
4444 [(set (match_operand:SI 0 "register_operand" "=d")
4445 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4446 (match_operand:SI 2 "const_int_operand" "n")))]
4447 "(! TARGET_68020 && !TARGET_COLDFIRE
4448 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4450 /* I think lsr%.w sets the CC properly. */
4451 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4452 return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
4455 (define_insn "lshrsi3"
4456 [(set (match_operand:SI 0 "register_operand" "=d")
4457 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4458 (match_operand:SI 2 "general_operand" "dI")))]
4462 (define_insn "lshrhi3"
4463 [(set (match_operand:HI 0 "register_operand" "=d")
4464 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4465 (match_operand:HI 2 "general_operand" "dI")))]
4470 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4471 (lshiftrt:HI (match_dup 0)
4472 (match_operand:HI 1 "general_operand" "dI")))]
4476 (define_insn "lshrqi3"
4477 [(set (match_operand:QI 0 "register_operand" "=d")
4478 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4479 (match_operand:QI 2 "general_operand" "dI")))]
4484 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4485 (lshiftrt:QI (match_dup 0)
4486 (match_operand:QI 1 "general_operand" "dI")))]
4490 ;; rotate instructions
4492 (define_insn "rotlsi3"
4493 [(set (match_operand:SI 0 "register_operand" "=d")
4494 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4495 (match_operand:SI 2 "general_operand" "dINO")))]
4498 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4500 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4502 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
4503 return "ror%.l %2,%0";
4506 return "rol%.l %2,%0";
4509 (define_insn "rotlhi3"
4510 [(set (match_operand:HI 0 "register_operand" "=d")
4511 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4512 (match_operand:HI 2 "general_operand" "dIP")))]
4515 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4517 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4518 return "ror%.w %2,%0";
4521 return "rol%.w %2,%0";
4525 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4526 (rotate:HI (match_dup 0)
4527 (match_operand:HI 1 "general_operand" "dIP")))]
4530 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4532 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
4533 return "ror%.w %2,%0";
4536 return "rol%.w %2,%0";
4539 (define_insn "rotlqi3"
4540 [(set (match_operand:QI 0 "register_operand" "=d")
4541 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4542 (match_operand:QI 2 "general_operand" "dI")))]
4545 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4547 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4548 return "ror%.b %2,%0";
4551 return "rol%.b %2,%0";
4555 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4556 (rotate:QI (match_dup 0)
4557 (match_operand:QI 1 "general_operand" "dI")))]
4560 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4562 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
4563 return "ror%.b %2,%0";
4566 return "rol%.b %2,%0";
4569 (define_insn "rotrsi3"
4570 [(set (match_operand:SI 0 "register_operand" "=d")
4571 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4572 (match_operand:SI 2 "general_operand" "dI")))]
4576 (define_insn "rotrhi3"
4577 [(set (match_operand:HI 0 "register_operand" "=d")
4578 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4579 (match_operand:HI 2 "general_operand" "dI")))]
4584 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4585 (rotatert:HI (match_dup 0)
4586 (match_operand:HI 1 "general_operand" "dI")))]
4590 (define_insn "rotrqi3"
4591 [(set (match_operand:QI 0 "register_operand" "=d")
4592 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4593 (match_operand:QI 2 "general_operand" "dI")))]
4598 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4599 (rotatert:QI (match_dup 0)
4600 (match_operand:QI 1 "general_operand" "dI")))]
4605 ;; Bit set/clear in memory byte.
4607 ;; set bit, bit number is int
4608 (define_insn "bsetmemqi"
4609 [(set (match_operand:QI 0 "memory_operand" "+m")
4610 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4611 (match_operand:SI 1 "general_operand" "d")) 3)
4616 return "bset %1,%0";
4619 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4621 [(set (match_operand:QI 0 "memory_operand" "+m")
4622 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4623 (match_operator:SI 2 "extend_operator"
4624 [(match_operand 1 "general_operand" "d")])) 3)
4629 return "bset %1,%0";
4632 ;; clear bit, bit number is int
4633 (define_insn "bclrmemqi"
4634 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4636 (minus:SI (const_int 7)
4637 (match_operand:SI 1 "general_operand" "d")))
4642 return "bclr %1,%0";
4645 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4647 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4649 (minus:SI (const_int 7)
4650 (match_operator:SI 2 "extend_operator"
4651 [(match_operand 1 "general_operand" "d")])))
4656 return "bclr %1,%0";
4659 ;; Special cases of bit-field insns which we should
4660 ;; recognize in preference to the general case.
4661 ;; These handle aligned 8-bit and 16-bit fields,
4662 ;; which can usually be done with move instructions.
4665 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4666 ; alignment of structure members is specified.
4668 ; The move is allowed to be odd byte aligned, because that's still faster
4669 ; than an odd byte aligned bit-field instruction.
4672 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4674 (match_operand:SI 1 "const_int_operand" "n"))
4675 (match_operand:SI 2 "general_src_operand" "rmSi"))]
4676 "TARGET_68020 && TARGET_BITFIELD
4677 && (INTVAL (operands[1]) % 8) == 0
4678 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4681 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
4683 return "move%.l %2,%0";
4687 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4688 (match_operand:SI 1 "const_int_operand" "n")
4689 (match_operand:SI 2 "const_int_operand" "n"))
4690 (match_operand:SI 3 "register_operand" "d"))]
4691 "TARGET_68020 && TARGET_BITFIELD
4692 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4693 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4694 && (GET_CODE (operands[0]) == REG
4695 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4697 if (REG_P (operands[0]))
4699 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4700 return "bfins %3,%0{%b2:%b1}";
4703 operands[0] = adjust_address (operands[0],
4704 INTVAL (operands[1]) == 8 ? QImode : HImode,
4705 INTVAL (operands[2]) / 8);
4707 if (GET_CODE (operands[3]) == MEM)
4708 operands[3] = adjust_address (operands[3],
4709 INTVAL (operands[1]) == 8 ? QImode : HImode,
4710 (32 - INTVAL (operands[1])) / 8);
4712 if (INTVAL (operands[1]) == 8)
4713 return "move%.b %3,%0";
4714 return "move%.w %3,%0";
4719 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4720 ; alignment of structure members is specified.
4722 ; The move is allowed to be odd byte aligned, because that's still faster
4723 ; than an odd byte aligned bit-field instruction.
4726 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4727 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4729 (match_operand:SI 2 "const_int_operand" "n")))]
4730 "TARGET_68020 && TARGET_BITFIELD
4731 && (INTVAL (operands[2]) % 8) == 0
4732 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4735 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4737 return "move%.l %1,%0";
4741 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
4742 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4743 (match_operand:SI 2 "const_int_operand" "n")
4744 (match_operand:SI 3 "const_int_operand" "n")))]
4745 "TARGET_68020 && TARGET_BITFIELD
4746 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4747 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4748 && (GET_CODE (operands[1]) == REG
4749 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4751 cc_status.flags |= CC_NOT_NEGATIVE;
4752 if (REG_P (operands[1]))
4754 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4755 return "bfextu %1{%b3:%b2},%0";
4759 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
4761 output_asm_insn ("clr%.l %0", operands);
4762 if (GET_CODE (operands[0]) == MEM)
4763 operands[0] = adjust_address (operands[0],
4764 INTVAL (operands[2]) == 8 ? QImode : HImode,
4765 (32 - INTVAL (operands[1])) / 8);
4767 if (INTVAL (operands[2]) == 8)
4768 return "move%.b %1,%0";
4769 return "move%.w %1,%0";
4773 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4774 ; alignment of structure members is specified.
4776 ; The move is allowed to be odd byte aligned, because that's still faster
4777 ; than an odd byte aligned bit-field instruction.
4780 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4781 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
4783 (match_operand:SI 2 "const_int_operand" "n")))]
4784 "TARGET_68020 && TARGET_BITFIELD
4785 && (INTVAL (operands[2]) % 8) == 0
4786 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4789 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
4791 return "move%.l %1,%0";
4795 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4796 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4797 (match_operand:SI 2 "const_int_operand" "n")
4798 (match_operand:SI 3 "const_int_operand" "n")))]
4799 "TARGET_68020 && TARGET_BITFIELD
4800 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4801 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4802 && (GET_CODE (operands[1]) == REG
4803 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4805 if (REG_P (operands[1]))
4807 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4808 return "bfexts %1{%b3:%b2},%0";
4812 = adjust_address (operands[1],
4813 INTVAL (operands[2]) == 8 ? QImode : HImode,
4814 INTVAL (operands[3]) / 8);
4816 if (INTVAL (operands[2]) == 8)
4817 return "move%.b %1,%0\;extb%.l %0";
4818 return "move%.w %1,%0\;ext%.l %0";
4821 ;; Bit-field instructions, general cases.
4822 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
4823 ;; so that its address is reloaded.
4825 (define_expand "extv"
4826 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4827 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
4828 (match_operand:SI 2 "general_operand" "")
4829 (match_operand:SI 3 "general_operand" "")))]
4830 "TARGET_68020 && TARGET_BITFIELD"
4834 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4835 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4836 (match_operand:SI 2 "general_operand" "di")
4837 (match_operand:SI 3 "general_operand" "di")))]
4838 "TARGET_68020 && TARGET_BITFIELD"
4839 "bfexts %1{%b3:%b2},%0")
4841 (define_expand "extzv"
4842 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4843 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
4844 (match_operand:SI 2 "general_operand" "")
4845 (match_operand:SI 3 "general_operand" "")))]
4846 "TARGET_68020 && TARGET_BITFIELD"
4850 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d")
4851 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
4852 (match_operand:SI 2 "general_operand" "di,di")
4853 (match_operand:SI 3 "general_operand" "di,di")))]
4854 "TARGET_68020 && TARGET_BITFIELD"
4856 if (GET_CODE (operands[2]) == CONST_INT)
4858 if (INTVAL (operands[2]) != 32)
4859 cc_status.flags |= CC_NOT_NEGATIVE;
4865 return "bfextu %1{%b3:%b2},%0";
4869 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4870 (match_operand:SI 1 "general_operand" "di")
4871 (match_operand:SI 2 "general_operand" "di"))
4872 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
4873 (match_operand 3 "const_int_operand" "n")))]
4874 "TARGET_68020 && TARGET_BITFIELD
4875 && (INTVAL (operands[3]) == -1
4876 || (GET_CODE (operands[1]) == CONST_INT
4877 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
4880 return "bfchg %0{%b2:%b1}";
4884 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4885 (match_operand:SI 1 "general_operand" "di")
4886 (match_operand:SI 2 "general_operand" "di"))
4888 "TARGET_68020 && TARGET_BITFIELD"
4891 return "bfclr %0{%b2:%b1}";
4895 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4896 (match_operand:SI 1 "general_operand" "di")
4897 (match_operand:SI 2 "general_operand" "di"))
4899 "TARGET_68020 && TARGET_BITFIELD"
4902 return "bfset %0{%b2:%b1}";
4905 (define_expand "insv"
4906 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
4907 (match_operand:SI 1 "general_operand" "")
4908 (match_operand:SI 2 "general_operand" ""))
4909 (match_operand:SI 3 "register_operand" ""))]
4910 "TARGET_68020 && TARGET_BITFIELD"
4914 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4915 (match_operand:SI 1 "general_operand" "di")
4916 (match_operand:SI 2 "general_operand" "di"))
4917 (match_operand:SI 3 "register_operand" "d"))]
4918 "TARGET_68020 && TARGET_BITFIELD"
4919 "bfins %3,%0{%b2:%b1}")
4921 ;; Now recognize bit-field insns that operate on registers
4922 ;; (or at least were intended to do so).
4925 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4926 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
4927 (match_operand:SI 2 "general_operand" "di")
4928 (match_operand:SI 3 "general_operand" "di")))]
4929 "TARGET_68020 && TARGET_BITFIELD"
4930 "bfexts %1{%b3:%b2},%0")
4933 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4934 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
4935 (match_operand:SI 2 "general_operand" "di")
4936 (match_operand:SI 3 "general_operand" "di")))]
4937 "TARGET_68020 && TARGET_BITFIELD"
4939 if (GET_CODE (operands[2]) == CONST_INT)
4941 if (INTVAL (operands[2]) != 32)
4942 cc_status.flags |= CC_NOT_NEGATIVE;
4948 return "bfextu %1{%b3:%b2},%0";
4952 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
4953 (match_operand:SI 1 "general_operand" "di")
4954 (match_operand:SI 2 "general_operand" "di"))
4956 "TARGET_68020 && TARGET_BITFIELD"
4959 return "bfclr %0{%b2:%b1}";
4963 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
4964 (match_operand:SI 1 "general_operand" "di")
4965 (match_operand:SI 2 "general_operand" "di"))
4967 "TARGET_68020 && TARGET_BITFIELD"
4970 return "bfset %0{%b2:%b1}";
4974 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
4975 (match_operand:SI 1 "general_operand" "di")
4976 (match_operand:SI 2 "general_operand" "di"))
4977 (match_operand:SI 3 "register_operand" "d"))]
4978 "TARGET_68020 && TARGET_BITFIELD"
4981 /* These special cases are now recognized by a specific pattern. */
4982 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
4983 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
4984 return "move%.w %3,%0";
4985 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
4986 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
4987 return "move%.b %3,%0";
4989 return "bfins %3,%0{%b2:%b1}";
4992 ;; Special patterns for optimizing bit-field instructions.
4996 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
4997 (match_operand:SI 1 "const_int_operand" "n")
4998 (match_operand:SI 2 "general_operand" "di")))]
4999 "TARGET_68020 && TARGET_BITFIELD"
5001 if (operands[1] == const1_rtx
5002 && GET_CODE (operands[2]) == CONST_INT)
5004 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5005 return output_btst (operands,
5006 GEN_INT (width - INTVAL (operands[2])),
5007 operands[0], insn, 1000);
5008 /* Pass 1000 as SIGNPOS argument so that btst will
5009 not think we are testing the sign bit for an `and'
5010 and assume that nonzero implies a negative result. */
5012 if (INTVAL (operands[1]) != 32)
5013 cc_status.flags = CC_NOT_NEGATIVE;
5014 return "bftst %0{%b2:%b1}";
5018 ;;; now handle the register cases
5021 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5022 (match_operand:SI 1 "const_int_operand" "n")
5023 (match_operand:SI 2 "general_operand" "di")))]
5024 "TARGET_68020 && TARGET_BITFIELD"
5026 if (operands[1] == const1_rtx
5027 && GET_CODE (operands[2]) == CONST_INT)
5029 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5030 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5031 operands[0], insn, 1000);
5032 /* Pass 1000 as SIGNPOS argument so that btst will
5033 not think we are testing the sign bit for an `and'
5034 and assume that nonzero implies a negative result. */
5036 if (INTVAL (operands[1]) != 32)
5037 cc_status.flags = CC_NOT_NEGATIVE;
5038 return "bftst %0{%b2:%b1}";
5041 (define_insn "scc0_di"
5042 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5043 (match_operator 1 "valid_dbcc_comparison_p"
5044 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5047 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5050 (define_insn "scc0_di_5200"
5051 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5052 (match_operator 1 "valid_dbcc_comparison_p"
5053 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5056 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5059 (define_insn "scc_di"
5060 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5061 (match_operator 1 "valid_dbcc_comparison_p"
5062 [(match_operand:DI 2 "general_operand" "ro,r")
5063 (match_operand:DI 3 "general_operand" "r,ro")]))]
5066 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5069 (define_insn "scc_di_5200"
5070 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5071 (match_operator 1 "valid_dbcc_comparison_p"
5072 [(match_operand:DI 2 "general_operand" "ro,r")
5073 (match_operand:DI 3 "general_operand" "r,ro")]))]
5076 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5079 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5080 ;; memory, but we cannot allow it to be in memory in case the address
5081 ;; needs to be reloaded.
5083 (define_expand "seq"
5084 [(set (match_operand:QI 0 "register_operand" "")
5085 (eq:QI (cc0) (const_int 0)))]
5089 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5091 m68k_last_compare_had_fp_operands = 0;
5097 [(set (match_operand:QI 0 "register_operand" "=d")
5098 (eq:QI (cc0) (const_int 0)))]
5101 cc_status = cc_prev_status;
5102 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
5105 (define_expand "sne"
5106 [(set (match_operand:QI 0 "register_operand" "")
5107 (ne:QI (cc0) (const_int 0)))]
5111 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5113 m68k_last_compare_had_fp_operands = 0;
5119 [(set (match_operand:QI 0 "register_operand" "=d")
5120 (ne:QI (cc0) (const_int 0)))]
5123 cc_status = cc_prev_status;
5124 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
5127 (define_expand "sgt"
5128 [(set (match_operand:QI 0 "register_operand" "")
5129 (gt:QI (cc0) (const_int 0)))]
5133 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5135 m68k_last_compare_had_fp_operands = 0;
5141 [(set (match_operand:QI 0 "register_operand" "=d")
5142 (gt:QI (cc0) (const_int 0)))]
5145 cc_status = cc_prev_status;
5146 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
5149 (define_expand "sgtu"
5150 [(set (match_operand:QI 0 "register_operand" "")
5151 (gtu:QI (cc0) (const_int 0)))]
5156 [(set (match_operand:QI 0 "register_operand" "=d")
5157 (gtu:QI (cc0) (const_int 0)))]
5160 cc_status = cc_prev_status;
5164 (define_expand "slt"
5165 [(set (match_operand:QI 0 "register_operand" "")
5166 (lt:QI (cc0) (const_int 0)))]
5170 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5172 m68k_last_compare_had_fp_operands = 0;
5178 [(set (match_operand:QI 0 "register_operand" "=d")
5179 (lt:QI (cc0) (const_int 0)))]
5182 cc_status = cc_prev_status;
5183 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
5186 (define_expand "sltu"
5187 [(set (match_operand:QI 0 "register_operand" "")
5188 (ltu:QI (cc0) (const_int 0)))]
5193 [(set (match_operand:QI 0 "register_operand" "=d")
5194 (ltu:QI (cc0) (const_int 0)))]
5197 cc_status = cc_prev_status;
5201 (define_expand "sge"
5202 [(set (match_operand:QI 0 "register_operand" "")
5203 (ge:QI (cc0) (const_int 0)))]
5207 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5209 m68k_last_compare_had_fp_operands = 0;
5215 [(set (match_operand:QI 0 "register_operand" "=d")
5216 (ge:QI (cc0) (const_int 0)))]
5219 cc_status = cc_prev_status;
5220 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
5223 (define_expand "sgeu"
5224 [(set (match_operand:QI 0 "register_operand" "")
5225 (geu:QI (cc0) (const_int 0)))]
5230 [(set (match_operand:QI 0 "register_operand" "=d")
5231 (geu:QI (cc0) (const_int 0)))]
5234 cc_status = cc_prev_status;
5238 (define_expand "sle"
5239 [(set (match_operand:QI 0 "register_operand" "")
5240 (le:QI (cc0) (const_int 0)))]
5244 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5246 m68k_last_compare_had_fp_operands = 0;
5252 [(set (match_operand:QI 0 "register_operand" "=d")
5253 (le:QI (cc0) (const_int 0)))]
5256 cc_status = cc_prev_status;
5257 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
5260 (define_expand "sleu"
5261 [(set (match_operand:QI 0 "register_operand" "")
5262 (leu:QI (cc0) (const_int 0)))]
5267 [(set (match_operand:QI 0 "register_operand" "=d")
5268 (leu:QI (cc0) (const_int 0)))]
5271 cc_status = cc_prev_status;
5275 (define_expand "sordered"
5276 [(set (match_operand:QI 0 "register_operand" "")
5277 (ordered:QI (cc0) (const_int 0)))]
5278 "TARGET_68881 && !TARGET_68060"
5280 if (! m68k_last_compare_had_fp_operands)
5282 m68k_last_compare_had_fp_operands = 0;
5285 (define_insn "*sordered_1"
5286 [(set (match_operand:QI 0 "register_operand" "=d")
5287 (ordered:QI (cc0) (const_int 0)))]
5288 "TARGET_68881 && !TARGET_68060"
5290 cc_status = cc_prev_status;
5294 (define_expand "sunordered"
5295 [(set (match_operand:QI 0 "register_operand" "")
5296 (unordered:QI (cc0) (const_int 0)))]
5297 "TARGET_68881 && !TARGET_68060"
5299 if (! m68k_last_compare_had_fp_operands)
5301 m68k_last_compare_had_fp_operands = 0;
5304 (define_insn "*sunordered_1"
5305 [(set (match_operand:QI 0 "register_operand" "=d")
5306 (unordered:QI (cc0) (const_int 0)))]
5307 "TARGET_68881 && !TARGET_68060"
5309 cc_status = cc_prev_status;
5313 (define_expand "suneq"
5314 [(set (match_operand:QI 0 "register_operand" "")
5315 (uneq:QI (cc0) (const_int 0)))]
5316 "TARGET_68881 && !TARGET_68060"
5318 if (! m68k_last_compare_had_fp_operands)
5320 m68k_last_compare_had_fp_operands = 0;
5323 (define_insn "*suneq_1"
5324 [(set (match_operand:QI 0 "register_operand" "=d")
5325 (uneq:QI (cc0) (const_int 0)))]
5326 "TARGET_68881 && !TARGET_68060"
5328 cc_status = cc_prev_status;
5332 (define_expand "sunge"
5333 [(set (match_operand:QI 0 "register_operand" "")
5334 (unge:QI (cc0) (const_int 0)))]
5335 "TARGET_68881 && !TARGET_68060"
5337 if (! m68k_last_compare_had_fp_operands)
5339 m68k_last_compare_had_fp_operands = 0;
5342 (define_insn "*sunge_1"
5343 [(set (match_operand:QI 0 "register_operand" "=d")
5344 (unge:QI (cc0) (const_int 0)))]
5345 "TARGET_68881 && !TARGET_68060"
5347 cc_status = cc_prev_status;
5351 (define_expand "sungt"
5352 [(set (match_operand:QI 0 "register_operand" "")
5353 (ungt:QI (cc0) (const_int 0)))]
5354 "TARGET_68881 && !TARGET_68060"
5356 if (! m68k_last_compare_had_fp_operands)
5358 m68k_last_compare_had_fp_operands = 0;
5361 (define_insn "*sungt_1"
5362 [(set (match_operand:QI 0 "register_operand" "=d")
5363 (ungt:QI (cc0) (const_int 0)))]
5364 "TARGET_68881 && !TARGET_68060"
5366 cc_status = cc_prev_status;
5370 (define_expand "sunle"
5371 [(set (match_operand:QI 0 "register_operand" "")
5372 (unle:QI (cc0) (const_int 0)))]
5373 "TARGET_68881 && !TARGET_68060"
5375 if (! m68k_last_compare_had_fp_operands)
5377 m68k_last_compare_had_fp_operands = 0;
5380 (define_insn "*sunle_1"
5381 [(set (match_operand:QI 0 "register_operand" "=d")
5382 (unle:QI (cc0) (const_int 0)))]
5383 "TARGET_68881 && !TARGET_68060"
5385 cc_status = cc_prev_status;
5389 (define_expand "sunlt"
5390 [(set (match_operand:QI 0 "register_operand" "")
5391 (unlt:QI (cc0) (const_int 0)))]
5392 "TARGET_68881 && !TARGET_68060"
5394 if (! m68k_last_compare_had_fp_operands)
5396 m68k_last_compare_had_fp_operands = 0;
5399 (define_insn "*sunlt_1"
5400 [(set (match_operand:QI 0 "register_operand" "=d")
5401 (unlt:QI (cc0) (const_int 0)))]
5402 "TARGET_68881 && !TARGET_68060"
5404 cc_status = cc_prev_status;
5408 (define_expand "sltgt"
5409 [(set (match_operand:QI 0 "register_operand" "")
5410 (ltgt:QI (cc0) (const_int 0)))]
5411 "TARGET_68881 && !TARGET_68060"
5413 if (! m68k_last_compare_had_fp_operands)
5415 m68k_last_compare_had_fp_operands = 0;
5418 (define_insn "*sltgt_1"
5419 [(set (match_operand:QI 0 "register_operand" "=d")
5420 (ltgt:QI (cc0) (const_int 0)))]
5421 "TARGET_68881 && !TARGET_68060"
5423 cc_status = cc_prev_status;
5427 (define_insn "*fsogt_1"
5428 [(set (match_operand:QI 0 "register_operand" "=d")
5429 (not:QI (unle:QI (cc0) (const_int 0))))]
5430 "TARGET_68881 && !TARGET_68060"
5432 cc_status = cc_prev_status;
5436 (define_insn "*fsoge_1"
5437 [(set (match_operand:QI 0 "register_operand" "=d")
5438 (not:QI (unlt:QI (cc0) (const_int 0))))]
5439 "TARGET_68881 && !TARGET_68060"
5441 cc_status = cc_prev_status;
5445 (define_insn "*fsolt_1"
5446 [(set (match_operand:QI 0 "register_operand" "=d")
5447 (not:QI (unge:QI (cc0) (const_int 0))))]
5448 "TARGET_68881 && !TARGET_68060"
5450 cc_status = cc_prev_status;
5454 (define_insn "*fsole_1"
5455 [(set (match_operand:QI 0 "register_operand" "=d")
5456 (not:QI (ungt:QI (cc0) (const_int 0))))]
5457 "TARGET_68881 && !TARGET_68060"
5459 cc_status = cc_prev_status;
5463 ;; Basic conditional jump instructions.
5465 (define_insn "beq0_di"
5467 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5469 (label_ref (match_operand 1 "" ","))
5471 (clobber (match_scratch:SI 2 "=d,d"))]
5475 if (which_alternative == 1)
5478 return "move%.l %0,%2\;or%.l %0,%2\;jbeq %l1";
5480 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
5482 if ((cc_prev_status.value1
5483 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5484 || (cc_prev_status.value2
5485 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5487 cc_status = cc_prev_status;
5488 return MOTOROLA ? "jbeq %l1" : "jeq %l1";
5490 if (GET_CODE (operands[0]) == REG)
5491 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5493 operands[3] = adjust_address (operands[0], SImode, 4);
5494 if (! ADDRESS_REG_P (operands[0]))
5496 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5498 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5501 return "or%.l %0,%2\;jbeq %l1";
5503 return "or%.l %0,%2\;jeq %l1";
5508 return "or%.l %3,%2\;jbeq %l1";
5510 return "or%.l %3,%2\;jeq %l1";
5514 return "move%.l %0,%2\;or%.l %3,%2\;jbeq %l1";
5516 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
5518 operands[4] = gen_label_rtx();
5519 if (TARGET_68020 || TARGET_COLDFIRE)
5522 output_asm_insn ("tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1", operands);
5524 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
5529 #ifdef SGS_CMP_ORDER
5530 output_asm_insn ("cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1", operands);
5532 output_asm_insn ("cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1", operands);
5535 output_asm_insn ("cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1", operands);
5537 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5538 CODE_LABEL_NUMBER (operands[4]));
5542 (define_insn "bne0_di"
5544 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5546 (label_ref (match_operand 1 "" ","))
5548 (clobber (match_scratch:SI 2 "=d,X"))]
5551 if ((cc_prev_status.value1
5552 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5553 || (cc_prev_status.value2
5554 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5556 cc_status = cc_prev_status;
5557 return MOTOROLA ? "jbne %l1" : "jne %l1";
5560 if (GET_CODE (operands[0]) == REG)
5561 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5563 operands[3] = adjust_address (operands[0], SImode, 4);
5564 if (!ADDRESS_REG_P (operands[0]))
5566 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5568 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5571 return "or%.l %0,%2\;jbne %l1";
5573 return "or%.l %0,%2\;jne %l1";
5578 return "or%.l %3,%2\;jbne %l1";
5580 return "or%.l %3,%2\;jne %l1";
5584 return "move%.l %0,%2\;or%.l %3,%2\;jbne %l1";
5586 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
5588 if (TARGET_68020 || TARGET_COLDFIRE)
5591 return "tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1";
5593 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
5598 #ifdef SGS_CMP_ORDER
5599 return "cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1";
5601 return "cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1";
5604 return "cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1";
5608 (define_insn "bge0_di"
5610 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5612 (label_ref (match_operand 1 "" ""))
5616 if ((cc_prev_status.value1
5617 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5618 || (cc_prev_status.value2
5619 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5621 cc_status = cc_prev_status;
5622 if (cc_status.flags & CC_REVERSED)
5624 return MOTOROLA ? "jble %l1" : "jle %l1";
5628 return MOTOROLA ? "jbpl %l1" : "jpl %l1";
5632 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5633 output_asm_insn("tst%.l %0", operands);
5636 /* On an address reg, cmpw may replace cmpl. */
5637 #ifdef SGS_CMP_ORDER
5638 output_asm_insn("cmp%.w %0,%#0", operands);
5640 output_asm_insn("cmp%.w %#0,%0", operands);
5644 return MOTOROLA ? "jbpl %l1" : "jpl %l1";
5647 (define_insn "blt0_di"
5649 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5651 (label_ref (match_operand 1 "" ""))
5655 if ((cc_prev_status.value1
5656 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5657 || (cc_prev_status.value2
5658 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5660 cc_status = cc_prev_status;
5661 if (cc_status.flags & CC_REVERSED)
5663 return MOTOROLA ? "jbgt %l1" : "jgt %l1";
5667 return MOTOROLA ? "jbmi %l1" : "jmi %l1";
5671 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
5672 output_asm_insn("tst%.l %0", operands);
5675 /* On an address reg, cmpw may replace cmpl. */
5676 #ifdef SGS_CMP_ORDER
5677 output_asm_insn("cmp%.w %0,%#0", operands);
5679 output_asm_insn("cmp%.w %#0,%0", operands);
5683 return MOTOROLA ? "jbmi %l1" : "jmi %l1";
5688 (if_then_else (eq (cc0)
5690 (label_ref (match_operand 0 "" ""))
5695 OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
5697 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
5702 (if_then_else (ne (cc0)
5704 (label_ref (match_operand 0 "" ""))
5709 OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
5711 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
5716 (if_then_else (gt (cc0)
5718 (label_ref (match_operand 0 "" ""))
5723 OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0);
5725 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
5730 (if_then_else (gtu (cc0)
5732 (label_ref (match_operand 0 "" ""))
5736 return MOTOROLA ? "jbhi %l0" : "jhi %l0";
5741 (if_then_else (lt (cc0)
5743 (label_ref (match_operand 0 "" ""))
5748 OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0");
5750 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
5755 (if_then_else (ltu (cc0)
5757 (label_ref (match_operand 0 "" ""))
5761 return MOTOROLA ? "jbcs %l0" : "jcs %l0";
5766 (if_then_else (ge (cc0)
5768 (label_ref (match_operand 0 "" ""))
5773 OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0");
5775 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
5780 (if_then_else (geu (cc0)
5782 (label_ref (match_operand 0 "" ""))
5786 return MOTOROLA ? "jbcc %l0" : "jcc %l0";
5791 (if_then_else (le (cc0)
5793 (label_ref (match_operand 0 "" ""))
5798 OUTPUT_JUMP ("jble %l0", "fble %l0", 0);
5800 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
5805 (if_then_else (leu (cc0)
5807 (label_ref (match_operand 0 "" ""))
5811 return MOTOROLA ? "jbls %l0" : "jls %l0";
5814 (define_insn "bordered"
5816 (if_then_else (ordered (cc0) (const_int 0))
5817 (label_ref (match_operand 0 "" ""))
5821 if (!(cc_prev_status.flags & CC_IN_68881))
5823 return MOTOROLA ? "fbor %l0" : "fjor %l0";
5826 (define_insn "bunordered"
5828 (if_then_else (unordered (cc0) (const_int 0))
5829 (label_ref (match_operand 0 "" ""))
5833 if (!(cc_prev_status.flags & CC_IN_68881))
5835 return MOTOROLA ? "fbun %l0" : "fjun %l0";
5838 (define_insn "buneq"
5840 (if_then_else (uneq (cc0) (const_int 0))
5841 (label_ref (match_operand 0 "" ""))
5845 if (!(cc_prev_status.flags & CC_IN_68881))
5847 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
5850 (define_insn "bunge"
5852 (if_then_else (unge (cc0) (const_int 0))
5853 (label_ref (match_operand 0 "" ""))
5857 if (!(cc_prev_status.flags & CC_IN_68881))
5859 return MOTOROLA ? "fbuge %l0" : "fjuge %l0";
5862 (define_insn "bungt"
5864 (if_then_else (ungt (cc0) (const_int 0))
5865 (label_ref (match_operand 0 "" ""))
5869 if (!(cc_prev_status.flags & CC_IN_68881))
5871 return MOTOROLA ? "fbugt %l0" : "fjugt %l0";
5874 (define_insn "bunle"
5876 (if_then_else (unle (cc0) (const_int 0))
5877 (label_ref (match_operand 0 "" ""))
5881 if (!(cc_prev_status.flags & CC_IN_68881))
5883 return MOTOROLA ? "fbule %l0" : "fjule %l0";
5886 (define_insn "bunlt"
5888 (if_then_else (unlt (cc0) (const_int 0))
5889 (label_ref (match_operand 0 "" ""))
5893 if (!(cc_prev_status.flags & CC_IN_68881))
5895 return MOTOROLA ? "fbult %l0" : "fjult %l0";
5898 (define_insn "bltgt"
5900 (if_then_else (ltgt (cc0) (const_int 0))
5901 (label_ref (match_operand 0 "" ""))
5905 if (!(cc_prev_status.flags & CC_IN_68881))
5907 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
5910 ;; Negated conditional jump instructions.
5914 (if_then_else (eq (cc0)
5917 (label_ref (match_operand 0 "" ""))))]
5921 OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
5923 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
5928 (if_then_else (ne (cc0)
5931 (label_ref (match_operand 0 "" ""))))]
5935 OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
5937 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
5942 (if_then_else (gt (cc0)
5945 (label_ref (match_operand 0 "" ""))))]
5949 OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0);
5951 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
5956 (if_then_else (gtu (cc0)
5959 (label_ref (match_operand 0 "" ""))))]
5962 return MOTOROLA ? "jbls %l0" : "jls %l0";
5967 (if_then_else (lt (cc0)
5970 (label_ref (match_operand 0 "" ""))))]
5974 OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0");
5976 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
5981 (if_then_else (ltu (cc0)
5984 (label_ref (match_operand 0 "" ""))))]
5987 return MOTOROLA ? "jbcc %l0" : "jcc %l0";
5992 (if_then_else (ge (cc0)
5995 (label_ref (match_operand 0 "" ""))))]
5999 OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0");
6001 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
6006 (if_then_else (geu (cc0)
6009 (label_ref (match_operand 0 "" ""))))]
6012 return MOTOROLA ? "jbcs %l0" : "jcs %l0";
6017 (if_then_else (le (cc0)
6020 (label_ref (match_operand 0 "" ""))))]
6024 OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0);
6026 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
6031 (if_then_else (leu (cc0)
6034 (label_ref (match_operand 0 "" ""))))]
6037 return MOTOROLA ? "jbhi %l0" : "jhi %l0";
6040 (define_insn "*bordered_rev"
6042 (if_then_else (ordered (cc0) (const_int 0))
6044 (label_ref (match_operand 0 "" ""))))]
6047 if (!(cc_prev_status.flags & CC_IN_68881))
6049 return MOTOROLA ? "fbun %l0" : "fjun %l0";
6052 (define_insn "*bunordered_rev"
6054 (if_then_else (unordered (cc0) (const_int 0))
6056 (label_ref (match_operand 0 "" ""))))]
6059 if (!(cc_prev_status.flags & CC_IN_68881))
6061 return MOTOROLA ? "fbor %l0" : "fjor %l0";
6064 (define_insn "*buneq_rev"
6066 (if_then_else (uneq (cc0) (const_int 0))
6068 (label_ref (match_operand 0 "" ""))))]
6071 if (!(cc_prev_status.flags & CC_IN_68881))
6073 return MOTOROLA ? "fbogl %l0" : "fjogl %l0";
6076 (define_insn "*bunge_rev"
6078 (if_then_else (unge (cc0) (const_int 0))
6080 (label_ref (match_operand 0 "" ""))))]
6083 if (!(cc_prev_status.flags & CC_IN_68881))
6085 return MOTOROLA ? "fbolt %l0" : "fjolt %l0";
6088 (define_insn "*bunle_rev"
6090 (if_then_else (unle (cc0) (const_int 0))
6092 (label_ref (match_operand 0 "" ""))))]
6095 if (!(cc_prev_status.flags & CC_IN_68881))
6097 return MOTOROLA ? "fbogt %l0" : "fjogt %l0";
6100 (define_insn "*bunlt_rev"
6102 (if_then_else (unlt (cc0) (const_int 0))
6104 (label_ref (match_operand 0 "" ""))))]
6107 if (!(cc_prev_status.flags & CC_IN_68881))
6109 return MOTOROLA ? "fboge %l0" : "fjoge %l0";
6112 (define_insn "*bltgt_rev"
6114 (if_then_else (ltgt (cc0) (const_int 0))
6116 (label_ref (match_operand 0 "" ""))))]
6119 if (!(cc_prev_status.flags & CC_IN_68881))
6121 return MOTOROLA ? "fbueq %l0" : "fjueq %l0";
6124 ;; Unconditional and other jump instructions
6127 (label_ref (match_operand 0 "" "")))]
6130 return MOTOROLA ? "jbra %l0" : "jra %l0";
6133 (define_expand "tablejump"
6134 [(parallel [(set (pc) (match_operand 0 "" ""))
6135 (use (label_ref (match_operand 1 "" "")))])]
6139 #ifdef CASE_VECTOR_PC_RELATIVE
6140 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6141 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6145 ;; Jump to variable address from dispatch table of absolute addresses.
6147 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6148 (use (label_ref (match_operand 1 "" "")))]
6151 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6154 ;; Jump to variable address from dispatch table of relative addresses.
6158 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6159 (use (label_ref (match_operand 1 "" "")))]
6162 #ifdef ASM_RETURN_CASE_JUMP
6163 ASM_RETURN_CASE_JUMP;
6166 #ifdef ASM_OUTPUT_CASE_LABEL
6167 if (TARGET_COLDFIRE)
6169 if (ADDRESS_REG_P (operands[0]))
6170 return "jmp 6(%%pc,%0.l)";
6172 return "ext%.l %0\;jmp 6(%%pc,%0.l)";
6175 return "jmp 6(%%pc,%0.w)";
6177 if (TARGET_COLDFIRE)
6179 if (ADDRESS_REG_P (operands[0]))
6180 return "jmp 2(%%pc,%0.l)";
6182 return "extl %0\;jmp 2(%%pc,%0.l)";
6185 return "jmp 2(%%pc,%0.w)";
6188 if (TARGET_COLDFIRE)
6190 if (ADDRESS_REG_P (operands[0]))
6192 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6195 return "ext%.l %0\;jmp (2,pc,%0.l)";
6197 return "extl %0\;jmp pc@(2,%0:l)";
6201 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
6207 ;; Decrement-and-branch insns.
6211 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6213 (label_ref (match_operand 1 "" ""))
6216 (plus:HI (match_dup 0)
6221 if (DATA_REG_P (operands[0]))
6222 return "dbra %0,%l1";
6223 if (GET_CODE (operands[0]) == MEM)
6226 return "subq%.w %#1,%0\;jbcc %l1";
6228 return "subqw %#1,%0\;jcc %l1";
6231 #ifdef SGS_CMP_ORDER
6232 return "subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1";
6233 #else /* not SGS_CMP_ORDER */
6234 return "subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1";
6237 return "subqw %#1,%0\;cmpw %#-1,%0\;jne %l1";
6243 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6245 (label_ref (match_operand 1 "" ""))
6248 (plus:SI (match_dup 0)
6255 if (DATA_REG_P (operands[0]))
6256 return "dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1";
6257 if (GET_CODE (operands[0]) == MEM)
6258 return "subq%.l %#1,%0\;jbcc %l1";
6259 #ifdef SGS_CMP_ORDER
6260 return "subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1";
6261 #else /* not SGS_CMP_ORDER */
6262 return "subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1";
6263 #endif /* not SGS_CMP_ORDER */
6267 if (DATA_REG_P (operands[0]))
6268 return "dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1";
6269 if (GET_CODE (operands[0]) == MEM)
6270 return "subql %#1,%0\;jcc %l1";
6271 return "subql %#1,%0\;cmpl %#-1,%0\;jne %l1";
6275 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6280 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6283 (label_ref (match_operand 1 "" ""))
6286 (plus:HI (match_dup 0)
6288 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6293 if (DATA_REG_P (operands[0]))
6294 return "dbra %0,%l1";
6295 if (GET_CODE (operands[0]) == MEM)
6296 return "subq%.w %#1,%0\;jbcc %l1";
6297 #ifdef SGS_CMP_ORDER
6298 return "subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1";
6299 #else /* not SGS_CMP_ORDER */
6300 return "subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1";
6301 #endif /* not SGS_CMP_ORDER */
6305 if (DATA_REG_P (operands[0]))
6306 return "dbra %0,%l1";
6307 if (GET_CODE (operands[0]) == MEM)
6308 return "subqw %#1,%0\;jcc %l1";
6309 return "subqw %#1,%0\;cmpw %#-1,%0\;jne %l1";
6313 (define_expand "decrement_and_branch_until_zero"
6314 [(parallel [(set (pc)
6316 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6319 (label_ref (match_operand 1 "" ""))
6322 (plus:SI (match_dup 0)
6330 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
6333 (label_ref (match_operand 1 "" ""))
6336 (plus:SI (match_dup 0)
6338 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6343 if (DATA_REG_P (operands[0]))
6344 return "dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1";
6345 if (GET_CODE (operands[0]) == MEM)
6346 return "subq%.l %#1,%0\;jbcc %l1";
6347 #ifdef SGS_CMP_ORDER
6348 return "subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1";
6349 #else /* not SGS_CMP_ORDER */
6350 return "subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1";
6351 #endif /* not SGS_CMP_ORDER */
6355 if (DATA_REG_P (operands[0]))
6356 return "dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1";
6357 if (GET_CODE (operands[0]) == MEM)
6358 return "subql %#1,%0\;jcc %l1";
6359 return "subql %#1,%0\;cmpl %#-1,%0\;jne %l1";
6364 ;; For PIC calls, in order to be able to support
6365 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6366 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6368 ;; PIC calls are handled by loading the address of the function into a
6369 ;; register (via movsi), then emitting a register indirect call using
6370 ;; the "jsr" function call syntax.
6372 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6373 ;; operand to the jbsr statement to indicate that this call should
6374 ;; go through the PLT (why? because this is the way that Sun does it).
6376 ;; We have different patterns for PIC calls and non-PIC calls. The
6377 ;; different patterns are only used to choose the right syntax.
6379 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6380 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6381 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6382 ;; section at link time. However, all global objects reference are still
6383 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6384 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6385 ;; We need to have a way to differentiate these two different operands.
6387 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6388 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6389 ;; to be changed to recognize function calls symbol_ref operand as a valid
6390 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6391 ;; avoid the compiler to load this symbol_ref operand into a register.
6392 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6393 ;; since the value is a PC relative offset, not a real address.
6395 ;; All global objects are treated in the similar way as in SUN3. The only
6396 ;; difference is: on m68k svr4, the reference of such global object needs
6397 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6398 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6401 ;; Call subroutine with no return value.
6402 (define_expand "call"
6403 [(call (match_operand:QI 0 "memory_operand" "")
6404 (match_operand:SI 1 "general_operand" ""))]
6405 ;; Operand 1 not really used on the m68000.
6410 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6411 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6414 ;; This is a normal call sequence.
6416 [(call (match_operand:QI 0 "memory_operand" "o")
6417 (match_operand:SI 1 "general_operand" "g"))]
6418 ;; Operand 1 not really used on the m68000.
6422 #if MOTOROLA && !defined (USE_GAS)
6429 ;; This is a PIC call sequence.
6431 [(call (match_operand:QI 0 "memory_operand" "o")
6432 (match_operand:SI 1 "general_operand" "g"))]
6433 ;; Operand 1 not really used on the m68000.
6437 m68k_output_pic_call(operands[0]);
6441 ;; Call subroutine, returning value in operand 0
6442 ;; (which must be a hard register).
6443 ;; See comments before "call" regarding PIC calls.
6444 (define_expand "call_value"
6445 [(set (match_operand 0 "" "")
6446 (call (match_operand:QI 1 "memory_operand" "")
6447 (match_operand:SI 2 "general_operand" "")))]
6448 ;; Operand 2 not really used on the m68000.
6452 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6453 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6456 ;; This is a normal call_value
6458 [(set (match_operand 0 "" "=rf")
6459 (call (match_operand:QI 1 "memory_operand" "o")
6460 (match_operand:SI 2 "general_operand" "g")))]
6461 ;; Operand 2 not really used on the m68000.
6464 #if MOTOROLA && !defined (USE_GAS)
6471 ;; This is a PIC call_value
6473 [(set (match_operand 0 "" "=rf")
6474 (call (match_operand:QI 1 "memory_operand" "o")
6475 (match_operand:SI 2 "general_operand" "g")))]
6476 ;; Operand 2 not really used on the m68000.
6479 m68k_output_pic_call(operands[1]);
6483 ;; Call subroutine returning any type.
6485 (define_expand "untyped_call"
6486 [(parallel [(call (match_operand 0 "" "")
6488 (match_operand 1 "" "")
6489 (match_operand 2 "" "")])]
6490 "NEEDS_UNTYPED_CALL"
6495 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6497 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6499 rtx set = XVECEXP (operands[2], 0, i);
6500 emit_move_insn (SET_DEST (set), SET_SRC (set));
6503 /* The optimizer does not know that the call sets the function value
6504 registers we stored in the result block. We avoid problems by
6505 claiming that all hard registers are used and clobbered at this
6507 emit_insn (gen_blockage ());
6512 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6513 ;; all of memory. This blocks insns from being moved across this point.
6515 (define_insn "blockage"
6516 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
6525 ;; Used for frameless functions which save no regs and allocate no locals.
6526 (define_insn "return"
6530 if (current_function_pops_args == 0)
6532 operands[0] = GEN_INT (current_function_pops_args);
6536 (define_insn "indirect_jump"
6537 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6541 ;; This should not be used unless the add/sub insns can't be.
6544 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
6545 (match_operand:QI 1 "address_operand" "p"))]
6548 /* Recognize an insn that refers to a table of offsets. Such an insn will
6549 need to refer to a label on the insn. So output one. Use the
6550 label-number of the table of offsets to generate this label. This code,
6551 and similar code above, assumes that there will be at most one reference
6553 if (GET_CODE (operands[1]) == PLUS
6554 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6555 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6557 rtx labelref = XEXP (operands[1], 1);
6558 #if MOTOROLA && !defined (SGS_SWITCH_TABLES)
6560 asm_fprintf (asm_out_file, "\\tset %LLI%d,.+2\\n",
6561 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6563 asm_fprintf (asm_out_file, "\\t.set %LLI%d,.+2\\n",
6564 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6565 #endif /* not SGS */
6566 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6567 (*targetm.asm_out.internal_label) (asm_out_file, "LI",
6568 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6569 #ifdef SGS_SWITCH_TABLES
6570 /* Set flag saying we need to define the symbol
6571 LD%n (with value L%n-LI%n) at the end of the switch table. */
6572 switch_table_difference_label_flag = 1;
6573 #endif /* SGS_SWITCH_TABLES */
6574 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6577 return "lea %a1,%0";
6580 ;; This is the first machine-dependent peephole optimization.
6581 ;; It is useful when a floating value is returned from a function call
6582 ;; and then is moved into an FP register.
6583 ;; But it is mainly intended to test the support for these optimizations.
6586 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6587 (set (match_operand:DF 0 "register_operand" "=f")
6588 (match_operand:DF 1 "register_operand" "ad"))]
6589 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6592 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6593 output_asm_insn ("move%.l %1,%@", xoperands);
6594 output_asm_insn ("move%.l %1,%-", operands);
6595 return "fmove%.d %+,%0";
6598 ;; Optimize a stack-adjust followed by a push of an argument.
6599 ;; This is said to happen frequently with -msoft-float
6600 ;; when there are consecutive library calls.
6603 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6604 (match_operand:SI 0 "const_int_operand" "n")))
6605 (set (match_operand:SF 1 "push_operand" "=m")
6606 (match_operand:SF 2 "general_operand" "rmfF"))]
6607 "INTVAL (operands[0]) >= 4
6608 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6610 if (INTVAL (operands[0]) > 4)
6613 xoperands[0] = stack_pointer_rtx;
6614 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6615 if (INTVAL (xoperands[1]) <= 8)
6617 if (!TARGET_COLDFIRE)
6618 output_asm_insn ("addq%.w %1,%0", xoperands);
6620 output_asm_insn ("addq%.l %1,%0", xoperands);
6622 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6624 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6625 output_asm_insn ("addq%.w %#8,%0\;addq%.w %1,%0", xoperands);
6627 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6630 output_asm_insn ("add%.w %1,%0", xoperands);
6632 output_asm_insn ("lea (%c1,%0),%0", xoperands);
6634 output_asm_insn ("lea %0@(%c1),%0", xoperands);
6637 output_asm_insn ("add%.l %1,%0", xoperands);
6639 if (FP_REG_P (operands[2]))
6640 return "fmove%.s %2,%@";
6641 return "move%.l %2,%@";
6644 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6647 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6648 (match_operand:SI 0 "const_int_operand" "n")))
6649 (set (match_operand:SI 1 "push_operand" "=m")
6650 (match_operand:SI 2 "general_operand" "g"))]
6651 "INTVAL (operands[0]) >= 4
6652 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6654 if (INTVAL (operands[0]) > 4)
6657 xoperands[0] = stack_pointer_rtx;
6658 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
6659 if (INTVAL (xoperands[1]) <= 8)
6661 if (!TARGET_COLDFIRE)
6662 output_asm_insn ("addq%.w %1,%0", xoperands);
6664 output_asm_insn ("addq%.l %1,%0", xoperands);
6666 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6668 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
6669 output_asm_insn ("addq%.w %#8,%0\;addq%.w %1,%0", xoperands);
6671 else if (INTVAL (xoperands[1]) <= 0x7FFF)
6674 output_asm_insn ("add%.w %1,%0", xoperands);
6676 output_asm_insn ("lea (%c1,%0),%0", xoperands);
6678 output_asm_insn ("lea %0@(%c1),%0", xoperands);
6681 output_asm_insn ("add%.l %1,%0", xoperands);
6683 if (operands[2] == const0_rtx)
6685 return "move%.l %2,%@";
6688 ;; Speed up pushing a single byte but leaving four bytes of space.
6691 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6692 (match_operand:QI 1 "general_operand" "dami"))
6693 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6694 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6698 if (GET_CODE (operands[1]) == REG)
6699 return "move%.l %1,%-";
6701 xoperands[1] = operands[1];
6703 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
6704 xoperands[3] = stack_pointer_rtx;
6705 if (!TARGET_COLDFIRE)
6706 output_asm_insn ("subq%.w %#4,%3\;move%.b %1,%2", xoperands);
6708 output_asm_insn ("subq%.l %#4,%3\;move%.b %1,%2", xoperands);
6713 [(set (match_operand:SI 0 "register_operand" "=d")
6715 (set (strict_low_part (subreg:HI (match_dup 0) 2))
6716 (match_operand:HI 1 "general_operand" "rmn"))]
6717 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6719 if (GET_CODE (operands[1]) == CONST_INT)
6721 if (operands[1] == const0_rtx
6722 && (DATA_REG_P (operands[0])
6723 || GET_CODE (operands[0]) == MEM)
6724 /* clr insns on 68000 read before writing.
6725 This isn't so on the 68010, but we have no TARGET_68010. */
6726 && ((TARGET_68020 || TARGET_COLDFIRE)
6727 || !(GET_CODE (operands[0]) == MEM
6728 && MEM_VOLATILE_P (operands[0]))))
6731 return "move%.w %1,%0";
6739 ;; jCC label ; abnormal loop termination
6740 ;; dbra dN, loop ; normal loop termination
6748 ;; Which moves the jCC condition outside the inner loop for free.
6752 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6753 [(cc0) (const_int 0)])
6754 (label_ref (match_operand 2 "" ""))
6759 (ne (match_operand:HI 0 "register_operand" "")
6761 (label_ref (match_operand 1 "" ""))
6764 (plus:HI (match_dup 0)
6766 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6769 output_dbcc_and_branch (operands);
6774 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6775 [(cc0) (const_int 0)])
6776 (label_ref (match_operand 2 "" ""))
6781 (ne (match_operand:SI 0 "register_operand" "")
6783 (label_ref (match_operand 1 "" ""))
6786 (plus:SI (match_dup 0)
6788 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6791 output_dbcc_and_branch (operands);
6796 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6797 [(cc0) (const_int 0)])
6798 (label_ref (match_operand 2 "" ""))
6803 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
6806 (label_ref (match_operand 1 "" ""))
6809 (plus:HI (match_dup 0)
6811 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6814 output_dbcc_and_branch (operands);
6819 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6820 [(cc0) (const_int 0)])
6821 (label_ref (match_operand 2 "" ""))
6826 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
6829 (label_ref (match_operand 1 "" ""))
6832 (plus:SI (match_dup 0)
6834 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6837 output_dbcc_and_branch (operands);
6842 (define_expand "tstxf"
6844 (match_operand:XF 0 "nonimmediate_operand" ""))]
6846 "m68k_last_compare_had_fp_operands = 1;")
6850 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6853 cc_status.flags = CC_IN_68881;
6854 return "ftst%.x %0";
6857 (define_expand "cmpxf"
6859 (compare (match_operand:XF 0 "nonimmediate_operand" "")
6860 (match_operand:XF 1 "nonimmediate_operand" "")))]
6862 "m68k_last_compare_had_fp_operands = 1;")
6866 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6867 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6870 cc_status.flags = CC_IN_68881;
6871 #ifdef SGS_CMP_ORDER
6872 if (REG_P (operands[0]))
6874 if (REG_P (operands[1]))
6875 return "fcmp%.x %0,%1";
6877 return "fcmp%.x %0,%f1";
6879 cc_status.flags |= CC_REVERSED;
6880 return "fcmp%.x %1,%f0";
6882 if (REG_P (operands[0]))
6884 if (REG_P (operands[1]))
6885 return "fcmp%.x %1,%0";
6887 return "fcmp%.x %f1,%0";
6889 cc_status.flags |= CC_REVERSED;
6890 return "fcmp%.x %f0,%1";
6894 (define_insn "extendsfxf2"
6895 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
6896 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
6899 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6901 if (REGNO (operands[0]) == REGNO (operands[1]))
6903 /* Extending float to double in an fp-reg is a no-op.
6904 NOTICE_UPDATE_CC has already assumed that the
6905 cc will be set. So cancel what it did. */
6906 cc_status = cc_prev_status;
6909 return "f%$move%.x %1,%0";
6911 if (FP_REG_P (operands[0]))
6913 if (FP_REG_P (operands[1]))
6914 return "f%$move%.x %1,%0";
6915 else if (ADDRESS_REG_P (operands[1]))
6916 return "move%.l %1,%-\;f%$move%.s %+,%0";
6917 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
6918 return output_move_const_single (operands);
6919 return "f%$move%.s %f1,%0";
6921 return "fmove%.x %f1,%0";
6925 (define_insn "extenddfxf2"
6926 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
6928 (match_operand:DF 1 "general_operand" "f,rmE")))]
6931 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6933 if (REGNO (operands[0]) == REGNO (operands[1]))
6935 /* Extending float to double in an fp-reg is a no-op.
6936 NOTICE_UPDATE_CC has already assumed that the
6937 cc will be set. So cancel what it did. */
6938 cc_status = cc_prev_status;
6941 return "fmove%.x %1,%0";
6943 if (FP_REG_P (operands[0]))
6945 if (REG_P (operands[1]))
6948 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
6949 output_asm_insn ("move%.l %1,%-", xoperands);
6950 output_asm_insn ("move%.l %1,%-", operands);
6951 return "f%&move%.d %+,%0";
6953 if (GET_CODE (operands[1]) == CONST_DOUBLE)
6954 return output_move_const_double (operands);
6955 return "f%&move%.d %f1,%0";
6957 return "fmove%.x %f1,%0";
6960 (define_insn "truncxfdf2"
6961 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
6963 (match_operand:XF 1 "general_operand" "f,f")))]
6966 if (REG_P (operands[0]))
6968 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
6969 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6970 return "move%.l %+,%0";
6972 return "fmove%.d %f1,%0";
6975 (define_insn "truncxfsf2"
6976 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
6978 (match_operand:XF 1 "general_operand" "f")))]
6982 (define_insn "floatsixf2"
6983 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
6984 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
6988 (define_insn "floathixf2"
6989 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
6990 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
6994 (define_insn "floatqixf2"
6995 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
6996 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7000 (define_insn "ftruncxf2"
7001 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7002 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7005 if (FP_REG_P (operands[1]))
7006 return "fintrz%.x %f1,%0";
7007 return "fintrz%.x %f1,%0";
7010 (define_insn "fixxfqi2"
7011 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
7012 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7016 (define_insn "fixxfhi2"
7017 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
7018 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7022 (define_insn "fixxfsi2"
7023 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
7024 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7029 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7030 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7031 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7036 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7037 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7038 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7043 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7044 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7045 (match_operand:XF 1 "general_operand" "0")))]
7049 (define_insn "addxf3"
7050 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7051 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7052 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7055 if (REG_P (operands[2]))
7056 return "fadd%.x %2,%0";
7057 return "fadd%.x %f2,%0";
7061 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7062 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7063 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7068 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7069 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7070 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7075 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7076 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7077 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7081 (define_insn "subxf3"
7082 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7083 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7084 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7087 if (REG_P (operands[2]))
7088 return "fsub%.x %2,%0";
7089 return "fsub%.x %f2,%0";
7093 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7094 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7095 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7100 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7101 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7102 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7107 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7108 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7109 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7113 (define_insn "mulxf3"
7114 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7115 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7116 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7119 if (REG_P (operands[2]))
7120 return "fmul%.x %2,%0";
7121 return "fmul%.x %f2,%0";
7125 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7126 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7127 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7132 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7133 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7134 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7139 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7140 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7141 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7145 (define_insn "divxf3"
7146 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7147 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7148 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7151 if (REG_P (operands[2]))
7152 return "fdiv%.x %2,%0";
7153 return "fdiv%.x %f2,%0";
7156 (define_expand "negxf2"
7157 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7158 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7169 target = operand_subword (operands[0], 0, 1, XFmode);
7170 result = expand_binop (SImode, xor_optab,
7171 operand_subword_force (operands[1], 0, XFmode),
7172 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7176 if (result != target)
7177 emit_move_insn (result, target);
7179 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7180 operand_subword_force (operands[1], 1, XFmode));
7181 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7182 operand_subword_force (operands[1], 2, XFmode));
7184 insns = get_insns ();
7187 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7192 (define_insn "negxf2_68881"
7193 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7194 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7197 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7198 return "fneg%.x %1,%0";
7199 return "fneg%.x %f1,%0";
7202 (define_expand "absxf2"
7203 [(set (match_operand:XF 0 "nonimmediate_operand" "")
7204 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7215 target = operand_subword (operands[0], 0, 1, XFmode);
7216 result = expand_binop (SImode, and_optab,
7217 operand_subword_force (operands[1], 0, XFmode),
7218 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7222 if (result != target)
7223 emit_move_insn (result, target);
7225 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7226 operand_subword_force (operands[1], 1, XFmode));
7227 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7228 operand_subword_force (operands[1], 2, XFmode));
7230 insns = get_insns ();
7233 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7238 (define_insn "absxf2_68881"
7239 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7240 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7243 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7244 return "fabs%.x %1,%0";
7245 return "fabs%.x %f1,%0";
7248 (define_insn "sqrtxf2"
7249 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7250 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7254 (define_insn "sinsf2"
7255 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7256 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_SIN))]
7257 "TARGET_68881 && flag_unsafe_math_optimizations"
7259 if (FP_REG_P (operands[1]))
7260 return "fsin%.x %1,%0";
7262 return "fsin%.s %1,%0";
7265 (define_insn "sindf2"
7266 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7267 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_SIN))]
7268 "TARGET_68881 && flag_unsafe_math_optimizations"
7270 if (FP_REG_P (operands[1]))
7271 return "fsin%.x %1,%0";
7273 return "fsin%.d %1,%0";
7276 (define_insn "sinxf2"
7277 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7278 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_SIN))]
7279 "TARGET_68881 && flag_unsafe_math_optimizations"
7282 (define_insn "cossf2"
7283 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
7284 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] UNSPEC_COS))]
7285 "TARGET_68881 && flag_unsafe_math_optimizations"
7287 if (FP_REG_P (operands[1]))
7288 return "fcos%.x %1,%0";
7290 return "fcos%.s %1,%0";
7293 (define_insn "cosdf2"
7294 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
7295 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] UNSPEC_COS))]
7296 "TARGET_68881 && flag_unsafe_math_optimizations"
7298 if (FP_REG_P (operands[1]))
7299 return "fcos%.x %1,%0";
7301 return "fcos%.d %1,%0";
7304 (define_insn "cosxf2"
7305 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
7306 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] UNSPEC_COS))]
7307 "TARGET_68881 && flag_unsafe_math_optimizations"
7311 [(trap_if (const_int -1) (const_int 7))]
7315 (define_insn "conditional_trap"
7316 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7317 [(cc0) (const_int 0)])
7318 (match_operand:SI 1 "const_int_operand" "I"))]
7319 "TARGET_68020 && ! flags_in_68881 ()"
7321 switch (GET_CODE (operands[0]))
7323 case EQ: return "trapeq";
7324 case NE: return "trapne";
7325 case GT: return "trapgt";
7326 case GTU: return "traphi";
7327 case LT: return "traplt";
7328 case LTU: return "trapcs";
7329 case GE: return "trapge";
7330 case GEU: return "trapcc";
7331 case LE: return "traple";
7332 case LEU: return "trapls";