1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_5200 flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881 registers can be used
49 ;;- 'r' either a data or an address register can be used.
50 ;;- 'x' if one of the Sun FPA registers
51 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
53 ;;- Immediate Floating point operator constraints
54 ;;- 'G' a floating point constant that is *NOT* one of the standard
55 ;; 68881 constant values (to force calling output_move_const_double
56 ;; to get it from rom if it is a 68881 constant).
57 ;;- 'H' one of the standard FPA constant values
59 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
62 ;;- Immediate integer operand constraints:
64 ;;- 'J' -32768 .. 32767
65 ;;- 'K' all integers EXCEPT -128 .. 127
67 ;;- 'M' all integers EXCEPT -256 .. 255
73 ;;- "%." size separator ("." or "") move%.l d0,d1
74 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
75 ;;- "%-" push operand "sp@-" move%.l d0,%-
76 ;;- "%+" pop operand "sp@+" move%.l d0,%+
77 ;;- "%@" top of stack "sp@" move%.l d0,%@
78 ;;- "%!" fpcr register
79 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
80 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
83 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
84 ;; operand 1 is the argument for `sin'.
85 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
86 ;; operand 1 is the argument for `cos'.
88 ;;- Information about 68040 port.
90 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
91 ;;- be emulated in software by the OS. It is faster to avoid these
92 ;;- instructions and issue a library call rather than trapping into
93 ;;- the kernel. The affected instructions are fintrz and fscale. The
94 ;;- TARGET_68040 flag turns the use of the opcodes off.
96 ;;- The '040 also implements a set of new floating-point instructions
97 ;;- which specify the rounding precision in the opcode. This finally
98 ;;- permit the 68k series to be truly IEEE compliant, and solves all
99 ;;- issues of excess precision accumulating in the extended registers.
100 ;;- By default, GCC does not use these instructions, since such code will
101 ;;- not run on an '030. To use these instructions, use the -m68040-only
102 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
103 ;;- you can make these instructions the default.
105 ;;- These new instructions aren't directly in the md. They are brought
106 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
109 ;;- Information about 68060 port.
111 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
112 ;;- be emulated in software by the OS. It is faster to avoid these
113 ;;- instructions and issue a library call rather than trapping into
114 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
115 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
116 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
118 ;;- FPA port explanation:
120 ;;- Usage of the Sun FPA and the 68881 together
122 ;;- The current port of gcc to the sun fpa disallows use of the m68881
123 ;;- instructions completely if code is targeted for the fpa. This is
124 ;;- for the following reasons:
126 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
127 ;;- can, the 68881 otherwise, and data registers only if you are
128 ;;- forced to it) is a bitch with the current constraint scheme,
129 ;;- especially since it would have to work for any combination of
132 ;;- 2) There are no instructions to move between the two types of
133 ;;- registers; the stack must be used as an intermediary.
135 ;;- It could indeed be done; I think the best way would be to have
136 ;;- separate patterns for TARGET_FPA (which implies a 68881),
137 ;;- TARGET_68881, and no floating point co-processor. Use
138 ;;- define_expands for all of the named instruction patterns, and
139 ;;- include code in the FPA instruction to deal with the 68881 with
140 ;;- preferences specifically set to favor the fpa. Some of this has
141 ;;- already been done:
143 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
144 ;;- case and a TARGET_68881 case (the exceptions are the patterns
145 ;;- which would need one define_expand and three define_insn's under
146 ;;- it (with a lot of duplicate code between them) to replace the
147 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
148 ;;- first two patterns in the md.
150 ;;- Some would still have to be done:
152 ;;- 1) Add code to the fpa patterns which correspond to 68881
153 ;;- patterns to deal with the 68881 case (including preferences!).
154 ;;- What you might actually do here is combine the fpa and 68881 code
155 ;;- back together into one pattern for those instructions where it's
156 ;;- absolutely necessary and save yourself some duplicate code. I'm
157 ;;- not completely sure as to whether you could get away with doing
158 ;;- this only for the mov* insns, or if you'd have to do it for all
160 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
161 ;;- moving between fpa regs and 68881 regs.
163 ;;- Since the fpa is more powerful than the 68881 and also has more
164 ;;- registers, and since I think the resultant md would be medium ugly
165 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
166 ;;- to do this change.
168 ;;- Another reason why someone *might* want to do the change is to
169 ;;- control which register classes are accessed in a slightly cleaner
170 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
171 ;;- the internals manual.
173 ;;- Yet another reason why someone might want to do this change is to
174 ;;- allow use of some of the 68881 insns which have no equivalent on
175 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
177 ;;- If this is ever done, don't forget to change sun3.h so that
178 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
180 ;;- Condition code hack
182 ;;- When a floating point compare is done in the fpa, the resulting
183 ;;- condition codes are left in the fpastatus register. The values in
184 ;;- this register must be moved into the 68000 cc register before any
185 ;;- jump is executed. Once this has been done, regular jump
186 ;;- instructions are fine (ie. floating point jumps are not necessary.
187 ;;- They are only done if the cc is in the 68881).
189 ;;- The instructions that move the fpastatus register to the 68000
190 ;;- register clobber a data register (the move cannot be done direct).
191 ;;- These instructions might be bundled either with the compare
192 ;;- instruction, or the branch instruction. If we were using both the
193 ;;- fpa and the 68881 together, we would wish to only mark the
194 ;;- register clobbered if we were doing the compare in the fpa, but I
195 ;;- think that that decision (whether to clobber the register or not)
196 ;;- must be done before register allocation (makes sense) and hence we
197 ;;- can't know if the floating point compare will be done in the fpa
198 ;;- or the fp. So whenever we are asked for code that uses the fpa,
199 ;;- we will mark a data register as clobbered. This is reasonable, as
200 ;;- almost all floating point compare operations done with fpa code
201 ;;- enabled will be done in the fpa. It's even more reasonable since
202 ;;- we decided to make the 68881 and the fpa mutually exclusive.
204 ;;- We place to code to move the fpastatus register inside of a
205 ;;- define_expand so that we can do it conditionally based on whether
206 ;;- we are targeting an fpa or not.
208 ;;- This still leaves us with the question of where we wish to put the
209 ;;- code to move the fpastatus reg. If we put it in the compare
210 ;;- instruction, we can restrict the clobbering of the register to
211 ;;- floating point compares, but we can't take advantage of floating
212 ;;- point subtracts & etc. that alter the fpastatus register. If we
213 ;;- put it in the branch instruction, all branches compiled with fpa
214 ;;- code enabled will clobber a data register, but we will be able to
215 ;;- take advantage of fpa subtracts. This balance favors putting the
216 ;;- code in with the compare instruction.
218 ;;- Note that if some enterprising hacker should decide to switch
219 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
221 ;;- Usage of the top 16 fpa registers
223 ;;- The only locations which we may transfer fpa registers 16-31 from
224 ;;- or to are the fpa registers 0-15. (68000 registers and memory
225 ;;- locations are impossible). This causes problems in gcc, which
226 ;;- assumes that mov?? instructions require no additional registers
227 ;;- (see section 11.7) and since floating point moves *must* be
228 ;;- supported into general registers (see section 12.3 under
229 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
231 ;;- My solution was to reserve fpa0 for moves into or out of these top
232 ;;- 16 registers and to disparage the choice to reload into or out of
233 ;;- these registers as much as I could. That alternative is always
234 ;;- last in the list, so it will not be used unless all else fails. I
235 ;;- will note that according to my current information, sun's compiler
236 ;;- doesn't use these top 16 registers at all.
238 ;;- There is another possible way to do it. I *believe* that if you
239 ;;- make absolutely sure that the code will not be executed in the
240 ;;- reload pass, you can support the mov?? names with define_expands
241 ;;- which require new registers. This may be possible by the
242 ;;- appropriate juggling of constraints. I may come back to this later.
244 ;;- Usage of constant RAM
246 ;;- This has been handled correctly (I believe) but the way I've done
247 ;;- it could use a little explanation. The constant RAM can only be
248 ;;- accessed when the instruction is in "command register" mode.
249 ;;- "command register" mode means that no accessing of memory or the
250 ;;- 68000 registers is being done. This can be expressed easily in
251 ;;- constraints, so generally the mode of the instruction is
252 ;;- determined by a branch off of which_alternative. In outputting
253 ;;- instructions, a 'w' means to output an access to the constant ram
254 ;;- (if the arg is CONST_DOUBLE and is one of the available
255 ;;- constants), and 'x' means to output a register pair (if the arg is
256 ;;- a 68000 register) and a 'y' is the combination of the above two
257 ;;- processes. You use a 'y' in two operand DF instructions where you
258 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
259 ;;- instructions where the arg might be a 68000 register and the
260 ;;- instruction is *not* in "command register" mode, and you use a 'w'
261 ;;- in two situations: 1) The instruction *is* in command register
262 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
263 ;;- instruction is a two operand SF instruction where you know the
264 ;;- other operand is an fpa register.
266 ;;- Optimization issues
268 ;;- I actually think that I've included all of the fpa instructions
269 ;;- that should be included. Note that if someone is interested in
270 ;;- doing serious floating point work on the sun fpa, I would advise
271 ;;- the use of the "asm" instruction in gcc to allow you to use the
272 ;;- sin, cos, and exponential functions on the fpa board.
274 ;;- END FPA Explanation Section.
277 ;;- Some of these insn's are composites of several m68000 op codes.
278 ;;- The assembler (or final @@??) insures that the appropriate one is
282 [(set (match_operand:DF 0 "push_operand" "=m")
283 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
287 if (FP_REG_P (operands[1]))
288 return \"fmove%.d %f1,%0\";
289 if (FPA_REG_P (operands[1]))
290 return \"fpmove%.d %1, %x0\";
291 return output_move_double (operands);
294 (define_insn "pushdi"
295 [(set (match_operand:DI 0 "push_operand" "=m")
296 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
300 return output_move_double (operands);
303 ;; We don't want to allow a constant operand for test insns because
304 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
305 ;; be folded while optimizing anyway.
307 (define_expand "tstdi"
308 [(parallel [(set (cc0)
309 (match_operand:DI 0 "nonimmediate_operand" ""))
310 (clobber (match_scratch:SI 1 ""))
311 (clobber (match_scratch:DI 2 ""))])]
313 "m68k_last_compare_had_fp_operands = 0;")
317 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
318 (clobber (match_scratch:SI 1 "=X,d"))
319 (clobber (match_scratch:DI 2 "=d,X"))]
323 if (which_alternative == 0)
327 xoperands[0] = operands[2];
328 xoperands[1] = operands[0];
329 output_move_double (xoperands);
330 cc_status.flags |= CC_REVERSED;
331 return \"neg%.l %R2\;negx%.l %2\";
333 if (find_reg_note (insn, REG_DEAD, operands[0]))
335 cc_status.flags |= CC_REVERSED;
336 return \"neg%.l %R0\;negx%.l %0\";
340 ** 'sub' clears %1, and also clears the X cc bit
341 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
342 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
344 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
347 (define_expand "tstsi"
349 (match_operand:SI 0 "nonimmediate_operand" ""))]
351 "m68k_last_compare_had_fp_operands = 0;")
355 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
360 /* ISI's assembler fails to handle tstl a0. */
361 if (! ADDRESS_REG_P (operands[0]))
363 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
365 return \"tst%.l %0\";
366 /* If you think that the 68020 does not support tstl a0,
367 reread page B-167 of the 68020 manual more carefully. */
368 /* On an address reg, cmpw may replace cmpl. */
370 return \"cmp%.w %0,%#0\";
372 return \"cmp%.w %#0,%0\";
376 ;; This can't use an address register, because comparisons
377 ;; with address registers as second operand always test the whole word.
378 (define_expand "tsthi"
380 (match_operand:HI 0 "nonimmediate_operand" ""))]
382 "m68k_last_compare_had_fp_operands = 0;")
386 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
390 (define_expand "tstqi"
392 (match_operand:QI 0 "nonimmediate_operand" ""))]
394 "m68k_last_compare_had_fp_operands = 0;")
398 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
402 (define_expand "tstsf"
404 (match_operand:SF 0 "general_operand" ""))]
405 "TARGET_68881 || TARGET_FPA"
408 m68k_last_compare_had_fp_operands = 1;
411 emit_insn (gen_tstsf_fpa (operands[0]));
416 (define_insn "tstsf_fpa"
418 (match_operand:SF 0 "general_operand" "xmdF"))
419 (clobber (match_scratch:SI 1 "=d"))]
421 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
425 (match_operand:SF 0 "general_operand" "fdm"))]
429 cc_status.flags = CC_IN_68881;
430 if (FP_REG_P (operands[0]))
431 return \"ftst%.x %0\";
432 return \"ftst%.s %0\";
435 (define_expand "tstdf"
437 (match_operand:DF 0 "general_operand" ""))]
438 "TARGET_68881 || TARGET_FPA"
441 m68k_last_compare_had_fp_operands = 1;
444 emit_insn (gen_tstsf_fpa (operands[0]));
449 (define_insn "tstdf_fpa"
451 (match_operand:DF 0 "general_operand" "xrmF"))
452 (clobber (match_scratch:SI 1 "=d"))]
454 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
458 (match_operand:DF 0 "general_operand" "fm"))]
462 cc_status.flags = CC_IN_68881;
463 if (FP_REG_P (operands[0]))
464 return \"ftst%.x %0\";
465 return \"ftst%.d %0\";
468 ;; compare instructions.
470 (define_expand "cmpdi"
473 (compare (match_operand:DI 0 "nonimmediate_operand" "")
474 (match_operand:DI 1 "general_operand" "")))
475 (clobber (match_dup 2))])]
477 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
481 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
482 (match_operand:DI 2 "general_operand" "d,0")))
483 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
487 if (rtx_equal_p (operands[0], operands[1]))
488 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
491 cc_status.flags |= CC_REVERSED;
492 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
496 ;; This is the second "hook" for PIC code (in addition to movsi). See
497 ;; comment of movsi for a description of PIC handling.
498 (define_expand "cmpsi"
500 (compare (match_operand:SI 0 "nonimmediate_operand" "")
501 (match_operand:SI 1 "general_operand" "")))]
505 m68k_last_compare_had_fp_operands = 0;
506 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
508 /* The source is an address which requires PIC relocation.
509 Call legitimize_pic_address with the source, mode, and a relocation
510 register (a new pseudo, or the final destination if reload_in_progress
511 is set). Then fall through normally */
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
521 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
584 (match_operand:HI 1 "general_src_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
591 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
620 (match_operand:QI 1 "general_src_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
627 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_src_operand" "oS")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adjust_address (operands[0], QImode,
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adjust_address (operands[0], QImode,
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "general_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "general_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "general_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
958 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
960 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
962 /* Don't allow writes to memory except via a register;
963 the m68k doesn't consider PC-relative addresses to be writable. */
964 if (symbolic_operand (operands[0], SImode))
965 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
966 else if (GET_CODE (operands[0]) == MEM
967 && symbolic_operand (XEXP (operands[0], 0), SImode))
968 operands[0] = gen_rtx (MEM, SImode,
969 force_reg (SImode, XEXP (operands[0], 0)));
973 ;; General case of fullword move. The register constraints
974 ;; force integer constants in range for a moveq to be reloaded
975 ;; if they are headed for memory.
977 ;; Notes: make sure no alternative allows g vs g.
978 ;; We don't allow f-regs since fixed point cannot go in them.
979 ;; We do allow y and x regs since fixed point is allowed in them.
980 [(set (match_operand:SI 0 "general_operand" "=g,d,a<,y,!*x*r*m")
981 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
986 if (which_alternative == 4)
987 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
988 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
989 return \"fpmove%.l %x1,%x0\";
990 return output_move_simode (operands);
994 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
995 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_simode (operands);")
999 ;; Special case of fullword move, where we need to get a non-GOT PIC
1000 ;; reference into an address register.
1002 [(set (match_operand:SI 0 "general_operand" "=a<")
1003 (match_operand:SI 1 "pcrel_address" ""))]
1007 if (push_operand (operands[0], SImode))
1009 return \"lea %a1,%0\";
1012 (define_expand "movhi"
1013 [(set (match_operand:HI 0 "general_operand" "")
1014 (match_operand:HI 1 "general_operand" ""))]
1019 [(set (match_operand:HI 0 "general_operand" "=g")
1020 (match_operand:HI 1 "general_src_operand" "gS"))]
1022 "* return output_move_himode (operands);")
1025 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
1026 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1028 "* return output_move_himode (operands);")
1030 (define_expand "movstricthi"
1031 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1032 (match_operand:HI 1 "general_src_operand" ""))]
1037 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1038 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1040 "* return output_move_stricthi (operands);")
1043 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1044 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1046 "* return output_move_stricthi (operands);")
1048 (define_expand "movqi"
1049 [(set (match_operand:QI 0 "general_operand" "")
1050 (match_operand:QI 1 "general_src_operand" ""))]
1055 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1056 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1058 "* return output_move_qimode (operands);")
1061 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1062 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
1064 "* return output_move_qimode (operands);")
1066 (define_expand "movstrictqi"
1067 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1068 (match_operand:QI 1 "general_src_operand" ""))]
1073 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1074 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1076 "* return output_move_strictqi (operands);")
1079 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1080 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
1082 "* return output_move_strictqi (operands);")
1084 (define_expand "movsf"
1085 [(set (match_operand:SF 0 "general_operand" "")
1086 (match_operand:SF 1 "general_operand" ""))]
1091 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1092 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1093 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1094 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1098 if (which_alternative >= 4)
1099 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1100 if (FPA_REG_P (operands[0]))
1102 if (FPA_REG_P (operands[1]))
1103 return \"fpmove%.s %x1,%x0\";
1104 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1105 return output_move_const_single (operands);
1106 else if (FP_REG_P (operands[1]))
1107 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1108 return \"fpmove%.s %x1,%x0\";
1110 if (FPA_REG_P (operands[1]))
1112 if (FP_REG_P (operands[0]))
1113 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1115 return \"fpmove%.s %x1,%x0\";
1117 if (FP_REG_P (operands[0]))
1119 if (FP_REG_P (operands[1]))
1120 return \"f%$move%.x %1,%0\";
1121 else if (ADDRESS_REG_P (operands[1]))
1122 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1123 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1124 return output_move_const_single (operands);
1125 return \"f%$move%.s %f1,%0\";
1127 if (FP_REG_P (operands[1]))
1129 if (ADDRESS_REG_P (operands[0]))
1130 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1131 return \"fmove%.s %f1,%0\";
1133 if (operands[1] == CONST0_RTX (SFmode)
1134 /* clr insns on 68000 read before writing.
1135 This isn't so on the 68010, but we have no TARGET_68010. */
1136 && ((TARGET_68020 || TARGET_5200)
1137 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1139 if (ADDRESS_REG_P (operands[0]))
1141 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1142 if (!TARGET_68040 && !TARGET_68060)
1143 return \"sub%.l %0,%0\";
1148 /* Many SGS assemblers croak on size specifiers for constants. */
1149 return \"lea 0,%0\";
1151 return \"lea 0.w,%0\";
1154 return \"lea 0:w,%0\";
1158 /* moveq is faster on the 68000. */
1159 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1161 #if defined(MOTOROLA) && !defined(CRDS)
1162 return \"moveq%.l %#0,%0\";
1164 return \"moveq %#0,%0\";
1167 return \"clr%.l %0\";
1169 return \"move%.l %1,%0\";
1173 [(set (match_operand:SF 0 "general_operand" "=r,g")
1174 (match_operand:SF 1 "general_operand" "g,r"))]
1176 "* return \"move%.l %1,%0\";")
1178 (define_expand "movdf"
1179 [(set (match_operand:DF 0 "general_operand" "")
1180 (match_operand:DF 1 "general_operand" ""))]
1185 [(set (match_operand:DF 0 "general_operand"
1186 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1187 (match_operand:DF 1 "general_operand"
1188 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1189 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1190 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1194 if (which_alternative == 7)
1195 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1196 if (FPA_REG_P (operands[0]))
1198 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1199 return output_move_const_double (operands);
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1202 return \"fpmove%.d %x1,%x0\";
1204 else if (FPA_REG_P (operands[1]))
1206 if (FP_REG_P(operands[0]))
1207 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1209 return \"fpmove%.d %x1,%x0\";
1211 if (FP_REG_P (operands[0]))
1213 if (FP_REG_P (operands[1]))
1214 return \"f%&move%.x %1,%0\";
1215 if (REG_P (operands[1]))
1218 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1219 output_asm_insn (\"move%.l %1,%-\", xoperands);
1220 output_asm_insn (\"move%.l %1,%-\", operands);
1221 return \"f%&move%.d %+,%0\";
1223 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1224 return output_move_const_double (operands);
1225 return \"f%&move%.d %f1,%0\";
1227 else if (FP_REG_P (operands[1]))
1229 if (REG_P (operands[0]))
1231 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1232 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1233 return \"move%.l %+,%0\";
1236 return \"fmove%.d %f1,%0\";
1238 return output_move_double (operands);
1242 [(set (match_operand:DF 0 "general_operand" "=r,g")
1243 (match_operand:DF 1 "general_operand" "g,r"))]
1245 "* return output_move_double (operands);")
1247 (define_expand "movxf"
1248 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1249 (match_operand:XF 1 "general_operand" ""))]
1253 if (CONSTANT_P (operands[1]))
1255 operands[1] = force_const_mem (XFmode, operands[1]);
1256 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1257 && ! reload_in_progress)
1258 operands[1] = adjust_address (operands[1], XFmode, 0);
1260 if (flag_pic && TARGET_PCREL && ! reload_in_progress)
1262 /* Don't allow writes to memory except via a register;
1263 the m68k doesn't consider PC-relative addresses to be writable. */
1264 if (GET_CODE (operands[0]) == MEM
1265 && symbolic_operand (XEXP (operands[0], 0), SImode))
1266 operands[0] = gen_rtx (MEM, XFmode,
1267 force_reg (SImode, XEXP (operands[0], 0)));
1272 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1273 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1277 if (FP_REG_P (operands[0]))
1279 if (FP_REG_P (operands[1]))
1280 return \"fmove%.x %1,%0\";
1281 if (REG_P (operands[1]))
1284 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1285 output_asm_insn (\"move%.l %1,%-\", xoperands);
1286 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1287 output_asm_insn (\"move%.l %1,%-\", xoperands);
1288 output_asm_insn (\"move%.l %1,%-\", operands);
1289 return \"fmove%.x %+,%0\";
1291 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1292 return \"fmove%.x %1,%0\";
1293 return \"fmove%.x %f1,%0\";
1295 if (FP_REG_P (operands[1]))
1297 if (REG_P (operands[0]))
1299 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1300 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1301 output_asm_insn (\"move%.l %+,%0\", operands);
1302 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1303 return \"move%.l %+,%0\";
1305 /* Must be memory destination. */
1306 return \"fmove%.x %f1,%0\";
1308 return output_move_double (operands);
1313 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1314 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1315 "! TARGET_68881 && ! TARGET_5200"
1318 if (FP_REG_P (operands[0]))
1320 if (FP_REG_P (operands[1]))
1321 return \"fmove%.x %1,%0\";
1322 if (REG_P (operands[1]))
1325 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1326 output_asm_insn (\"move%.l %1,%-\", xoperands);
1327 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1328 output_asm_insn (\"move%.l %1,%-\", xoperands);
1329 output_asm_insn (\"move%.l %1,%-\", operands);
1330 return \"fmove%.x %+,%0\";
1332 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1333 return \"fmove%.x %1,%0\";
1334 return \"fmove%.x %f1,%0\";
1336 if (FP_REG_P (operands[1]))
1338 if (REG_P (operands[0]))
1340 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1341 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1342 output_asm_insn (\"move%.l %+,%0\", operands);
1343 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1344 return \"move%.l %+,%0\";
1347 return \"fmove%.x %f1,%0\";
1349 return output_move_double (operands);
1354 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1355 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1356 "! TARGET_68881 && TARGET_5200"
1357 "* return output_move_double (operands);")
1359 (define_expand "movdi"
1360 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1361 [(set (match_operand:DI 0 "general_operand" "")
1362 (match_operand:DI 1 "general_operand" ""))]
1366 ;; movdi can apply to fp regs in some cases
1368 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1369 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1370 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1371 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1372 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1373 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1374 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1378 if (which_alternative == 8)
1379 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1380 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1381 return \"fpmove%.d %x1,%x0\";
1382 if (FP_REG_P (operands[0]))
1384 if (FP_REG_P (operands[1]))
1385 return \"fmove%.x %1,%0\";
1386 if (REG_P (operands[1]))
1389 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1390 output_asm_insn (\"move%.l %1,%-\", xoperands);
1391 output_asm_insn (\"move%.l %1,%-\", operands);
1392 return \"fmove%.d %+,%0\";
1394 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1395 return output_move_const_double (operands);
1396 return \"fmove%.d %f1,%0\";
1398 else if (FP_REG_P (operands[1]))
1400 if (REG_P (operands[0]))
1402 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1403 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1404 return \"move%.l %+,%0\";
1407 return \"fmove%.d %f1,%0\";
1409 return output_move_double (operands);
1413 [(set (match_operand:DI 0 "general_operand" "=r,g")
1414 (match_operand:DI 1 "general_operand" "g,r"))]
1416 "* return output_move_double (operands);")
1418 ;; Thus goes after the move instructions
1419 ;; because the move instructions are better (require no spilling)
1420 ;; when they can apply. It goes before the add/sub insns
1421 ;; so we will prefer it to them.
1423 (define_insn "pushasi"
1424 [(set (match_operand:SI 0 "push_operand" "=m")
1425 (match_operand:SI 1 "address_operand" "p"))]
1429 ;; truncation instructions
1430 (define_insn "truncsiqi2"
1431 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1433 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1437 if (GET_CODE (operands[0]) == REG)
1439 /* Must clear condition codes, since the move.l bases them on
1440 the entire 32 bits, not just the desired 8 bits. */
1442 return \"move%.l %1,%0\";
1444 if (GET_CODE (operands[1]) == MEM)
1445 operands[1] = adjust_address (operands[1], QImode, 3);
1446 return \"move%.b %1,%0\";
1449 (define_insn "trunchiqi2"
1450 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1452 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1456 if (GET_CODE (operands[0]) == REG
1457 && (GET_CODE (operands[1]) == MEM
1458 || GET_CODE (operands[1]) == CONST_INT))
1460 /* Must clear condition codes, since the move.w bases them on
1461 the entire 16 bits, not just the desired 8 bits. */
1463 return \"move%.w %1,%0\";
1465 if (GET_CODE (operands[0]) == REG)
1467 /* Must clear condition codes, since the move.l bases them on
1468 the entire 32 bits, not just the desired 8 bits. */
1470 return \"move%.l %1,%0\";
1472 if (GET_CODE (operands[1]) == MEM)
1473 operands[1] = adjust_address (operands[1], QImode, 1);
1474 return \"move%.b %1,%0\";
1477 (define_insn "truncsihi2"
1478 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1480 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1484 if (GET_CODE (operands[0]) == REG)
1486 /* Must clear condition codes, since the move.l bases them on
1487 the entire 32 bits, not just the desired 8 bits. */
1489 return \"move%.l %1,%0\";
1491 if (GET_CODE (operands[1]) == MEM)
1492 operands[1] = adjust_address (operands[1], QImode, 2);
1493 return \"move%.w %1,%0\";
1496 ;; zero extension instructions
1498 (define_insn "zero_extendqidi2"
1499 [(set (match_operand:DI 0 "general_operand" "=&d")
1500 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1505 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1506 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1509 (define_insn "zero_extendhidi2"
1510 [(set (match_operand:DI 0 "general_operand" "=&d")
1511 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1516 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1517 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1520 ;; this is the canonical form for (lshiftrt:DI x 32)
1521 (define_insn "zero_extendsidi2"
1522 [(set (match_operand:DI 0 "general_operand" "=rm")
1523 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1528 if (GET_CODE (operands[0]) == REG)
1529 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1530 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1531 return \"move%.l %1,%0\;clr%.l %0\";
1532 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1533 return \"clr%.l %0\;move%.l %1,%0\";
1535 operands[2] = adjust_address (operands[0], SImode, 4);
1536 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1537 || REGNO (operands[1]) != REGNO (operands[2]))
1538 output_asm_insn (\"move%.l %1,%2\", operands);
1539 if (ADDRESS_REG_P (operands[0]))
1540 return \"sub%.l %0,%0\";
1542 return \"clr%.l %0\";
1545 (define_expand "zero_extendhisi2"
1546 [(set (match_operand:SI 0 "register_operand" "")
1548 (set (strict_low_part (match_dup 2))
1549 (match_operand:HI 1 "general_operand" ""))]
1553 operands[1] = make_safe_from (operands[1], operands[0]);
1554 operands[2] = gen_lowpart (HImode, operands[0]);
1557 (define_expand "zero_extendqihi2"
1558 [(set (match_operand:HI 0 "register_operand" "")
1560 (set (strict_low_part (match_dup 2))
1561 (match_operand:QI 1 "general_operand" ""))]
1565 operands[1] = make_safe_from (operands[1], operands[0]);
1566 operands[2] = gen_lowpart (QImode, operands[0]);
1569 (define_expand "zero_extendqisi2"
1570 [(set (match_operand:SI 0 "register_operand" "")
1572 (set (strict_low_part (match_dup 2))
1573 (match_operand:QI 1 "general_operand" ""))]
1577 operands[1] = make_safe_from (operands[1], operands[0]);
1578 operands[2] = gen_lowpart (QImode, operands[0]);
1581 ;; Patterns to recognize zero-extend insns produced by the combiner.
1582 ;; We don't allow both operands in memory, because of aliasing problems.
1583 ;; Explicitly disallow two memory operands via the condition since reloading
1584 ;; of this case will result in worse code than the uncombined patterns.
1587 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1588 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "r,mS")))]
1589 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1592 if (DATA_REG_P (operands[0]))
1594 if (GET_CODE (operands[1]) == REG
1595 && REGNO (operands[0]) == REGNO (operands[1]))
1596 return \"and%.l %#0xFFFF,%0\";
1597 if (reg_mentioned_p (operands[0], operands[1]))
1598 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1599 return \"clr%.l %0\;move%.w %1,%0\";
1601 else if (GET_CODE (operands[0]) == MEM
1602 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1603 return \"move%.w %1,%0\;clr%.w %0\";
1604 else if (GET_CODE (operands[0]) == MEM
1605 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1606 return \"clr%.w %0\;move%.w %1,%0\";
1609 output_asm_insn (\"clr%.w %0\", operands);
1610 operands[0] = adjust_address (operands[0], HImode, 2);
1611 return \"move%.w %1,%0\";
1616 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1617 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1618 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1621 if (DATA_REG_P (operands[0]))
1623 if (GET_CODE (operands[1]) == REG
1624 && REGNO (operands[0]) == REGNO (operands[1]))
1625 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1626 if (reg_mentioned_p (operands[0], operands[1]))
1627 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1628 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1629 return \"clr%.w %0\;move%.b %1,%0\";
1631 else if (GET_CODE (operands[0]) == MEM
1632 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1634 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1635 == STACK_POINTER_REGNUM)
1637 output_asm_insn (\"clr%.w %-\", operands);
1638 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1639 plus_constant (stack_pointer_rtx, 1));
1640 return \"move%.b %1,%0\";
1643 return \"move%.b %1,%0\;clr%.b %0\";
1645 else if (GET_CODE (operands[0]) == MEM
1646 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1647 return \"clr%.b %0\;move%.b %1,%0\";
1650 output_asm_insn (\"clr%.b %0\", operands);
1651 operands[0] = adjust_address (operands[0], QImode, 1);
1652 return \"move%.b %1,%0\";
1657 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1658 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "d,mS")))]
1659 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1662 if (DATA_REG_P (operands[0]))
1664 if (GET_CODE (operands[1]) == REG
1665 && REGNO (operands[0]) == REGNO (operands[1]))
1666 return \"and%.l %#0xFF,%0\";
1667 if (reg_mentioned_p (operands[0], operands[1]))
1668 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1669 return \"clr%.l %0\;move%.b %1,%0\";
1671 else if (GET_CODE (operands[0]) == MEM
1672 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1674 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1677 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1679 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1682 return \"clrl %0@-\;moveb %1,%0@(3)\";
1685 else if (GET_CODE (operands[0]) == MEM
1686 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1688 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1691 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1693 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1696 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1701 output_asm_insn (\"clr%.l %0\", operands);
1702 operands[0] = adjust_address (operands[0], QImode, 3);
1703 return \"move%.b %1,%0\";
1707 ;; sign extension instructions
1709 (define_insn "extendqidi2"
1710 [(set (match_operand:DI 0 "general_operand" "=d")
1711 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1716 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1717 if (TARGET_68020 || TARGET_5200)
1718 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1720 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1723 (define_insn "extendhidi2"
1724 [(set (match_operand:DI 0 "general_operand" "=d")
1726 (match_operand:HI 1 "general_src_operand" "rmS")))]
1731 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1732 if (TARGET_68020 || TARGET_5200)
1733 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1735 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1738 (define_insn "extendsidi2"
1739 [(set (match_operand:DI 0 "general_operand" "=d")
1741 (match_operand:SI 1 "general_operand" "rm")))]
1746 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1747 if (TARGET_68020 || TARGET_5200)
1748 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1750 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1753 ;; Special case when one can avoid register clobbering, copy and test
1754 ;; Maybe there is a way to make that the general case, by forcing the
1755 ;; result of the SI tree to be in the lower register of the DI target
1757 (define_insn "extendplussidi"
1758 [(set (match_operand:DI 0 "register_operand" "=d")
1759 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1760 (match_operand:SI 2 "general_operand" "rmn"))))]
1765 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1766 if (GET_CODE (operands[1]) == CONST_INT
1767 && (unsigned) INTVAL (operands[1]) > 8)
1769 rtx tmp = operands[1];
1771 operands[1] = operands[2];
1774 if (GET_CODE (operands[1]) == REG
1775 && REGNO (operands[1]) == REGNO (operands[3]))
1776 output_asm_insn (\"add%.l %2,%3\", operands);
1778 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1779 if (TARGET_68020 || TARGET_5200)
1780 return \"smi %0\;extb%.l %0\";
1782 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1785 (define_insn "extendhisi2"
1786 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1788 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1792 if (ADDRESS_REG_P (operands[0]))
1793 return \"move%.w %1,%0\";
1794 return \"ext%.l %0\";
1797 (define_insn "extendqihi2"
1798 [(set (match_operand:HI 0 "general_operand" "=d")
1799 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1803 (define_insn "extendqisi2"
1804 [(set (match_operand:SI 0 "general_operand" "=d")
1805 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1806 "TARGET_68020 || TARGET_5200"
1809 ;; Conversions between float and double.
1811 (define_expand "extendsfdf2"
1812 [(set (match_operand:DF 0 "general_operand" "")
1814 (match_operand:SF 1 "general_operand" "")))]
1815 "TARGET_68881 || TARGET_FPA"
1819 [(set (match_operand:DF 0 "general_operand" "=x,y")
1821 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1826 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1828 (match_operand:SF 1 "general_operand" "f,dmF")))]
1832 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1834 if (REGNO (operands[0]) == REGNO (operands[1]))
1836 /* Extending float to double in an fp-reg is a no-op.
1837 NOTICE_UPDATE_CC has already assumed that the
1838 cc will be set. So cancel what it did. */
1839 cc_status = cc_prev_status;
1842 return \"f%&move%.x %1,%0\";
1844 if (FP_REG_P (operands[0]))
1845 return \"f%&move%.s %f1,%0\";
1846 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1848 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1849 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1850 return \"move%.l %+,%0\";
1852 return \"fmove%.d %f1,%0\";
1855 ;; This cannot output into an f-reg because there is no way to be
1856 ;; sure of truncating in that case.
1857 ;; But on the Sun FPA, we can be sure.
1858 (define_expand "truncdfsf2"
1859 [(set (match_operand:SF 0 "general_operand" "")
1861 (match_operand:DF 1 "general_operand" "")))]
1862 "TARGET_68881 || TARGET_FPA"
1866 [(set (match_operand:SF 0 "general_operand" "=x,y")
1868 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1872 ;; On the '040 we can truncate in a register accurately and easily.
1874 [(set (match_operand:SF 0 "general_operand" "=f")
1876 (match_operand:DF 1 "general_operand" "fmG")))]
1880 if (FP_REG_P (operands[1]))
1881 return \"f%$move%.x %1,%0\";
1882 return \"f%$move%.d %f1,%0\";
1886 [(set (match_operand:SF 0 "general_operand" "=dm")
1888 (match_operand:DF 1 "general_operand" "f")))]
1892 ;; Conversion between fixed point and floating point.
1893 ;; Note that among the fix-to-float insns
1894 ;; the ones that start with SImode come first.
1895 ;; That is so that an operand that is a CONST_INT
1896 ;; (and therefore lacks a specific machine mode).
1897 ;; will be recognized as SImode (which is always valid)
1898 ;; rather than as QImode or HImode.
1900 (define_expand "floatsisf2"
1901 [(set (match_operand:SF 0 "general_operand" "")
1902 (float:SF (match_operand:SI 1 "general_operand" "")))]
1903 "TARGET_68881 || TARGET_FPA"
1907 [(set (match_operand:SF 0 "general_operand" "=y,x")
1908 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1913 [(set (match_operand:SF 0 "general_operand" "=f")
1914 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1918 (define_expand "floatsidf2"
1919 [(set (match_operand:DF 0 "general_operand" "")
1920 (float:DF (match_operand:SI 1 "general_operand" "")))]
1921 "TARGET_68881 || TARGET_FPA"
1925 [(set (match_operand:DF 0 "general_operand" "=y,x")
1926 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1931 [(set (match_operand:DF 0 "general_operand" "=f")
1932 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1936 (define_insn "floathisf2"
1937 [(set (match_operand:SF 0 "general_operand" "=f")
1938 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1942 (define_insn "floathidf2"
1943 [(set (match_operand:DF 0 "general_operand" "=f")
1944 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1948 (define_insn "floatqisf2"
1949 [(set (match_operand:SF 0 "general_operand" "=f")
1950 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1954 (define_insn "floatqidf2"
1955 [(set (match_operand:DF 0 "general_operand" "=f")
1956 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1960 ;; New routines to convert floating-point values to integers
1961 ;; to be used on the '040. These should be faster than trapping
1962 ;; into the kernel to emulate fintrz. They should also be faster
1963 ;; than calling the subroutines fixsfsi or fixdfsi.
1965 (define_insn "fix_truncdfsi2"
1966 [(set (match_operand:SI 0 "general_operand" "=dm")
1967 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1968 (clobber (match_scratch:SI 2 "=d"))
1969 (clobber (match_scratch:SI 3 "=d"))]
1970 "TARGET_68881 && TARGET_68040"
1974 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1977 (define_insn "fix_truncdfhi2"
1978 [(set (match_operand:HI 0 "general_operand" "=dm")
1979 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1980 (clobber (match_scratch:SI 2 "=d"))
1981 (clobber (match_scratch:SI 3 "=d"))]
1982 "TARGET_68881 && TARGET_68040"
1986 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1989 (define_insn "fix_truncdfqi2"
1990 [(set (match_operand:QI 0 "general_operand" "=dm")
1991 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1992 (clobber (match_scratch:SI 2 "=d"))
1993 (clobber (match_scratch:SI 3 "=d"))]
1994 "TARGET_68881 && TARGET_68040"
1998 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
2001 ;; Convert a float to a float whose value is an integer.
2002 ;; This is the first stage of converting it to an integer type.
2004 (define_insn "ftruncdf2"
2005 [(set (match_operand:DF 0 "general_operand" "=f")
2006 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
2007 "TARGET_68881 && !TARGET_68040"
2010 if (FP_REG_P (operands[1]))
2011 return \"fintrz%.x %f1,%0\";
2012 return \"fintrz%.d %f1,%0\";
2015 (define_insn "ftruncsf2"
2016 [(set (match_operand:SF 0 "general_operand" "=f")
2017 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
2018 "TARGET_68881 && !TARGET_68040"
2021 if (FP_REG_P (operands[1]))
2022 return \"fintrz%.x %f1,%0\";
2023 return \"fintrz%.s %f1,%0\";
2026 ;; Convert a float whose value is an integer
2027 ;; to an actual integer. Second stage of converting float to integer type.
2028 (define_insn "fixsfqi2"
2029 [(set (match_operand:QI 0 "general_operand" "=dm")
2030 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2034 (define_insn "fixsfhi2"
2035 [(set (match_operand:HI 0 "general_operand" "=dm")
2036 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2040 (define_insn "fixsfsi2"
2041 [(set (match_operand:SI 0 "general_operand" "=dm")
2042 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2046 (define_insn "fixdfqi2"
2047 [(set (match_operand:QI 0 "general_operand" "=dm")
2048 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2052 (define_insn "fixdfhi2"
2053 [(set (match_operand:HI 0 "general_operand" "=dm")
2054 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2058 (define_insn "fixdfsi2"
2059 [(set (match_operand:SI 0 "general_operand" "=dm")
2060 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2064 ;; Convert a float to an integer.
2065 ;; On the Sun FPA, this is done in one step.
2068 [(set (match_operand:SI 0 "general_operand" "=x,y")
2069 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2074 [(set (match_operand:SI 0 "general_operand" "=x,y")
2075 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2081 (define_insn "adddi_lshrdi_63"
2082 [(set (match_operand:DI 0 "general_operand" "=d")
2083 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2086 (clobber (match_scratch:SI 2 "=d"))]
2090 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2091 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2093 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2094 if (GET_CODE (operands[1]) == REG)
2095 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2096 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2097 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2098 operands[4] = operands[1];
2100 operands[4] = adjust_address (operands[1], SImode, 4);
2101 if (GET_CODE (operands[1]) == MEM
2102 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2103 output_asm_insn (\"move%.l %4,%3\", operands);
2104 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2105 if (TARGET_68020 || TARGET_5200)
2106 output_asm_insn (\"extb%.l %2\", operands);
2108 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2109 if (GET_CODE (operands[1]) != MEM
2110 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2111 output_asm_insn (\"move%.l %4,%3\", operands);
2112 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2115 (define_insn "adddi_sexthishl32"
2116 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2117 (plus:DI (ashift:DI (sign_extend:DI
2118 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2120 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2121 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2126 if (ADDRESS_REG_P (operands[0]))
2127 return \"add%.w %1,%0\";
2128 else if (ADDRESS_REG_P (operands[3]))
2129 return \"move%.w %1,%3\;add%.l %3,%0\";
2131 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2134 (define_insn "adddi_dilshr32"
2135 [(set (match_operand:DI 0 "general_operand" "=d,o")
2136 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2137 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2138 ;; (const_int 32))))]
2139 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2141 (match_operand:DI 2 "general_operand" "0,0")))]
2146 if (GET_CODE (operands[0]) == REG)
2147 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2149 operands[2] = adjust_address (operands[0], SImode, 4);
2150 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2153 (define_insn "adddi_dishl32"
2154 [(set (match_operand:DI 0 "general_operand" "=r,o")
2155 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2156 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2157 ;; (const_int 32))))]
2158 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2160 (match_operand:DI 2 "general_operand" "0,0")))]
2165 if (GET_CODE (operands[1]) == REG)
2166 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2168 operands[1] = adjust_address (operands[1], SImode, 4);
2169 return \"add%.l %1,%0\";
2172 (define_insn "adddi3"
2173 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2174 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2175 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2176 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2180 if (DATA_REG_P (operands[0]))
2182 if (DATA_REG_P (operands[2]))
2183 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2184 else if (GET_CODE (operands[2]) == MEM
2185 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2186 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2192 if (GET_CODE (operands[2]) == REG)
2194 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2197 else if (CONSTANT_P (operands[2]))
2198 split_double (operands[2], &high, &low);
2201 low = adjust_address (operands[2], SImode, 4);
2205 operands[1] = low, operands[2] = high;
2206 xoperands[0] = operands[3];
2207 if (GET_CODE (operands[1]) == CONST_INT
2208 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2209 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2211 xoperands[1] = operands[2];
2213 output_asm_insn (output_move_simode (xoperands), xoperands);
2214 if (GET_CODE (operands[1]) == CONST_INT)
2216 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2219 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2221 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2224 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2226 operands[1] = GEN_INT (-INTVAL (operands[1]));
2228 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2230 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2234 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2237 else if (GET_CODE (operands[0]) == MEM)
2239 if (GET_CODE (operands[2]) == MEM
2240 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2241 return \"add%.l %2,%0\;addx%.l %2,%0\";
2243 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2245 operands[1] = gen_rtx_MEM (SImode,
2246 plus_constant (XEXP(operands[0], 0), -8));
2247 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2249 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2251 operands[1] = XEXP(operands[0], 0);
2252 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2256 operands[1] = adjust_address (operands[0], SImode, 4);
2257 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2264 (define_insn "addsi_lshrsi_31"
2265 [(set (match_operand:SI 0 "general_operand" "=dm")
2266 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2272 operands[2] = operands[0];
2273 operands[3] = gen_label_rtx();
2274 if (GET_CODE (operands[0]) == MEM)
2276 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2277 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2278 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2279 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2281 output_asm_insn (\"move%.l %1,%0\", operands);
2283 output_asm_insn (\"jbpl %l3\", operands);
2285 output_asm_insn (\"jpl %l3\", operands);
2288 output_asm_insn (\"addq%.l %#1,%2\", operands);
2290 output_asm_insn (\"add%.l %#1,%2\", operands);
2292 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2293 CODE_LABEL_NUMBER (operands[3]));
2297 (define_expand "addsi3"
2298 [(set (match_operand:SI 0 "general_operand" "")
2299 (plus:SI (match_operand:SI 1 "general_operand" "")
2300 (match_operand:SI 2 "general_src_operand" "")))]
2304 ;; Note that the middle two alternatives are near-duplicates
2305 ;; in order to handle insns generated by reload.
2306 ;; This is needed since they are not themselves reloaded,
2307 ;; so commutativity won't apply to them.
2308 (define_insn "*addsi3_internal"
2309 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,d,a")
2310 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2311 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2315 "* return output_addsi3 (operands);")
2317 (define_insn "*addsi3_5200"
2318 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2319 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2320 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2322 "* return output_addsi3 (operands);")
2325 [(set (match_operand:SI 0 "general_operand" "=a")
2326 (plus:SI (match_operand:SI 1 "general_operand" "0")
2328 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2332 (define_insn "addhi3"
2333 [(set (match_operand:HI 0 "general_operand" "=m,r")
2334 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2335 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2339 if (GET_CODE (operands[2]) == CONST_INT)
2342 /* If the constant would be a negative number when interpreted as
2343 HImode, make it negative. This is usually, but not always, done
2344 elsewhere in the compiler. First check for constants out of range,
2345 which could confuse us. */
2347 if (INTVAL (operands[2]) >= 32768)
2348 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2350 if (INTVAL (operands[2]) > 0
2351 && INTVAL (operands[2]) <= 8)
2352 return \"addq%.w %2,%0\";
2353 if (INTVAL (operands[2]) < 0
2354 && INTVAL (operands[2]) >= -8)
2356 operands[2] = GEN_INT (- INTVAL (operands[2]));
2357 return \"subq%.w %2,%0\";
2359 /* On the CPU32 it is faster to use two addqw instructions to
2360 add a small integer (8 < N <= 16) to a register.
2361 Likewise for subqw. */
2362 if (TARGET_CPU32 && REG_P (operands[0]))
2364 if (INTVAL (operands[2]) > 8
2365 && INTVAL (operands[2]) <= 16)
2367 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2368 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2370 if (INTVAL (operands[2]) < -8
2371 && INTVAL (operands[2]) >= -16)
2373 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2374 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2378 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2380 return \"lea (%c2,%0),%0\";
2382 return \"lea %0@(%c2),%0\";
2385 return \"add%.w %2,%0\";
2388 ;; These insns must use MATCH_DUP instead of the more expected
2389 ;; use of a matching constraint because the "output" here is also
2390 ;; an input, so you can't use the matching constraint. That also means
2391 ;; that you can't use the "%", so you need patterns with the matched
2392 ;; operand in both positions.
2395 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2396 (plus:HI (match_dup 0)
2397 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2401 if (GET_CODE (operands[1]) == CONST_INT)
2404 /* If the constant would be a negative number when interpreted as
2405 HImode, make it negative. This is usually, but not always, done
2406 elsewhere in the compiler. First check for constants out of range,
2407 which could confuse us. */
2409 if (INTVAL (operands[1]) >= 32768)
2410 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2412 if (INTVAL (operands[1]) > 0
2413 && INTVAL (operands[1]) <= 8)
2414 return \"addq%.w %1,%0\";
2415 if (INTVAL (operands[1]) < 0
2416 && INTVAL (operands[1]) >= -8)
2418 operands[1] = GEN_INT (- INTVAL (operands[1]));
2419 return \"subq%.w %1,%0\";
2421 /* On the CPU32 it is faster to use two addqw instructions to
2422 add a small integer (8 < N <= 16) to a register.
2423 Likewise for subqw. */
2424 if (TARGET_CPU32 && REG_P (operands[0]))
2426 if (INTVAL (operands[1]) > 8
2427 && INTVAL (operands[1]) <= 16)
2429 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2430 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2432 if (INTVAL (operands[1]) < -8
2433 && INTVAL (operands[1]) >= -16)
2435 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2436 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2440 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2442 return \"lea (%c1,%0),%0\";
2444 return \"lea %0@(%c1),%0\";
2447 return \"add%.w %1,%0\";
2451 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2452 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2457 if (GET_CODE (operands[1]) == CONST_INT)
2460 /* If the constant would be a negative number when interpreted as
2461 HImode, make it negative. This is usually, but not always, done
2462 elsewhere in the compiler. First check for constants out of range,
2463 which could confuse us. */
2465 if (INTVAL (operands[1]) >= 32768)
2466 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2468 if (INTVAL (operands[1]) > 0
2469 && INTVAL (operands[1]) <= 8)
2470 return \"addq%.w %1,%0\";
2471 if (INTVAL (operands[1]) < 0
2472 && INTVAL (operands[1]) >= -8)
2474 operands[1] = GEN_INT (- INTVAL (operands[1]));
2475 return \"subq%.w %1,%0\";
2477 /* On the CPU32 it is faster to use two addqw instructions to
2478 add a small integer (8 < N <= 16) to a register.
2479 Likewise for subqw. */
2480 if (TARGET_CPU32 && REG_P (operands[0]))
2482 if (INTVAL (operands[1]) > 8
2483 && INTVAL (operands[1]) <= 16)
2485 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2486 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2488 if (INTVAL (operands[1]) < -8
2489 && INTVAL (operands[1]) >= -16)
2491 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2492 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2496 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2498 return \"lea (%c1,%0),%0\";
2500 return \"lea %0@(%c1),%0\";
2503 return \"add%.w %1,%0\";
2506 (define_insn "addqi3"
2507 [(set (match_operand:QI 0 "general_operand" "=m,d")
2508 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2509 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2514 if (GET_CODE (operands[2]) == CONST_INT)
2516 if (INTVAL (operands[2]) >= 128)
2517 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2519 if (INTVAL (operands[2]) > 0
2520 && INTVAL (operands[2]) <= 8)
2521 return \"addq%.b %2,%0\";
2522 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2524 operands[2] = GEN_INT (- INTVAL (operands[2]));
2525 return \"subq%.b %2,%0\";
2529 return \"add%.b %2,%0\";
2533 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2534 (plus:QI (match_dup 0)
2535 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2540 if (GET_CODE (operands[1]) == CONST_INT)
2542 if (INTVAL (operands[1]) >= 128)
2543 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2545 if (INTVAL (operands[1]) > 0
2546 && INTVAL (operands[1]) <= 8)
2547 return \"addq%.b %1,%0\";
2548 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2550 operands[1] = GEN_INT (- INTVAL (operands[1]));
2551 return \"subq%.b %1,%0\";
2555 return \"add%.b %1,%0\";
2559 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2560 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2566 if (GET_CODE (operands[1]) == CONST_INT)
2568 if (INTVAL (operands[1]) >= 128)
2569 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2571 if (INTVAL (operands[1]) > 0
2572 && INTVAL (operands[1]) <= 8)
2573 return \"addq%.b %1,%0\";
2574 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2576 operands[1] = GEN_INT (- INTVAL (operands[1]));
2577 return \"subq%.b %1,%0\";
2581 return \"add%.b %1,%0\";
2584 (define_expand "adddf3"
2585 [(set (match_operand:DF 0 "general_operand" "")
2586 (plus:DF (match_operand:DF 1 "general_operand" "")
2587 (match_operand:DF 2 "general_operand" "")))]
2588 "TARGET_68881 || TARGET_FPA"
2592 [(set (match_operand:DF 0 "general_operand" "=x,y")
2593 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2594 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2598 if (rtx_equal_p (operands[0], operands[1]))
2599 return \"fpadd%.d %y2,%0\";
2600 if (rtx_equal_p (operands[0], operands[2]))
2601 return \"fpadd%.d %y1,%0\";
2602 if (which_alternative == 0)
2603 return \"fpadd3%.d %w2,%w1,%0\";
2604 return \"fpadd3%.d %x2,%x1,%0\";
2608 [(set (match_operand:DF 0 "general_operand" "=f")
2609 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2610 (match_operand:DF 1 "general_operand" "0")))]
2615 [(set (match_operand:DF 0 "general_operand" "=f")
2616 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2617 (match_operand:DF 1 "general_operand" "0")))]
2622 [(set (match_operand:DF 0 "general_operand" "=f")
2623 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2624 (match_operand:DF 1 "general_operand" "0")))]
2629 [(set (match_operand:DF 0 "general_operand" "=f")
2630 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2631 (match_operand:DF 2 "general_operand" "fmG")))]
2635 if (REG_P (operands[2]))
2636 return \"f%&add%.x %2,%0\";
2637 return \"f%&add%.d %f2,%0\";
2640 (define_expand "addsf3"
2641 [(set (match_operand:SF 0 "general_operand" "")
2642 (plus:SF (match_operand:SF 1 "general_operand" "")
2643 (match_operand:SF 2 "general_operand" "")))]
2644 "TARGET_68881 || TARGET_FPA"
2648 [(set (match_operand:SF 0 "general_operand" "=x,y")
2649 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2650 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2654 if (rtx_equal_p (operands[0], operands[1]))
2655 return \"fpadd%.s %w2,%0\";
2656 if (rtx_equal_p (operands[0], operands[2]))
2657 return \"fpadd%.s %w1,%0\";
2658 if (which_alternative == 0)
2659 return \"fpadd3%.s %w2,%w1,%0\";
2660 return \"fpadd3%.s %2,%1,%0\";
2664 [(set (match_operand:SF 0 "general_operand" "=f")
2665 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2666 (match_operand:SF 1 "general_operand" "0")))]
2671 [(set (match_operand:SF 0 "general_operand" "=f")
2672 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2673 (match_operand:SF 1 "general_operand" "0")))]
2678 [(set (match_operand:SF 0 "general_operand" "=f")
2679 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2680 (match_operand:SF 1 "general_operand" "0")))]
2685 [(set (match_operand:SF 0 "general_operand" "=f")
2686 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2687 (match_operand:SF 2 "general_operand" "fdmF")))]
2691 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2692 return \"f%$add%.x %2,%0\";
2693 return \"f%$add%.s %f2,%0\";
2696 ;; subtract instructions
2698 (define_insn "subdi_sexthishl32"
2699 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2700 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2701 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2703 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2708 if (ADDRESS_REG_P (operands[0]))
2709 return \"sub%.w %2,%0\";
2710 else if (ADDRESS_REG_P (operands[3]))
2711 return \"move%.w %2,%3\;sub%.l %3,%0\";
2713 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2716 (define_insn "subdi_dishl32"
2717 [(set (match_operand:DI 0 "general_operand" "+ro")
2718 (minus:DI (match_dup 0)
2719 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2725 if (GET_CODE (operands[1]) == REG)
2726 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2728 operands[1] = adjust_address (operands[1], SImode, 4);
2729 return \"sub%.l %1,%0\";
2732 (define_insn "subdi3"
2733 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2734 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2735 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2736 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2740 if (DATA_REG_P (operands[0]))
2742 if (DATA_REG_P (operands[2]))
2743 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2744 else if (GET_CODE (operands[2]) == MEM
2745 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2747 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2754 if (GET_CODE (operands[2]) == REG)
2756 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2759 else if (CONSTANT_P (operands[2]))
2760 split_double (operands[2], &high, &low);
2763 low = adjust_address (operands[2], SImode, 4);
2767 operands[1] = low, operands[2] = high;
2768 xoperands[0] = operands[3];
2769 if (GET_CODE (operands[1]) == CONST_INT
2770 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2771 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2773 xoperands[1] = operands[2];
2775 output_asm_insn (output_move_simode (xoperands), xoperands);
2776 if (GET_CODE (operands[1]) == CONST_INT)
2778 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2781 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2783 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2786 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2788 operands[1] = GEN_INT (-INTVAL (operands[1]));
2790 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2792 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2796 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2799 else if (GET_CODE (operands[0]) == MEM)
2801 if (GET_CODE (operands[2]) == MEM
2802 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2803 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2805 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2808 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8));
2809 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2811 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2813 operands[1] = XEXP(operands[0], 0);
2814 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2818 operands[1] = adjust_address (operands[0], SImode, 4);
2819 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2826 (define_insn "subsi3"
2827 [(set (match_operand:SI 0 "general_operand" "=m,d,a")
2828 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0")
2829 (match_operand:SI 2 "general_src_operand" "dT,mSrT,mSrs")))]
2834 [(set (match_operand:SI 0 "general_operand" "=a")
2835 (minus:SI (match_operand:SI 1 "general_operand" "0")
2837 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2841 (define_insn "subhi3"
2842 [(set (match_operand:HI 0 "general_operand" "=m,r")
2843 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2844 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2849 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2850 (minus:HI (match_dup 0)
2851 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2855 (define_insn "subqi3"
2856 [(set (match_operand:QI 0 "general_operand" "=m,d")
2857 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2858 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2863 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2864 (minus:QI (match_dup 0)
2865 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2869 (define_expand "subdf3"
2870 [(set (match_operand:DF 0 "general_operand" "")
2871 (minus:DF (match_operand:DF 1 "general_operand" "")
2872 (match_operand:DF 2 "general_operand" "")))]
2873 "TARGET_68881 || TARGET_FPA"
2877 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2878 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2879 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2883 if (rtx_equal_p (operands[0], operands[2]))
2884 return \"fprsub%.d %y1,%0\";
2885 if (rtx_equal_p (operands[0], operands[1]))
2886 return \"fpsub%.d %y2,%0\";
2887 if (which_alternative == 0)
2888 return \"fpsub3%.d %w2,%w1,%0\";
2889 return \"fpsub3%.d %x2,%x1,%0\";
2893 [(set (match_operand:DF 0 "general_operand" "=f")
2894 (minus:DF (match_operand:DF 1 "general_operand" "0")
2895 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2900 [(set (match_operand:DF 0 "general_operand" "=f")
2901 (minus:DF (match_operand:DF 1 "general_operand" "0")
2902 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2907 [(set (match_operand:DF 0 "general_operand" "=f")
2908 (minus:DF (match_operand:DF 1 "general_operand" "0")
2909 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2914 [(set (match_operand:DF 0 "general_operand" "=f")
2915 (minus:DF (match_operand:DF 1 "general_operand" "0")
2916 (match_operand:DF 2 "general_operand" "fmG")))]
2920 if (REG_P (operands[2]))
2921 return \"f%&sub%.x %2,%0\";
2922 return \"f%&sub%.d %f2,%0\";
2925 (define_expand "subsf3"
2926 [(set (match_operand:SF 0 "general_operand" "")
2927 (minus:SF (match_operand:SF 1 "general_operand" "")
2928 (match_operand:SF 2 "general_operand" "")))]
2929 "TARGET_68881 || TARGET_FPA"
2933 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2934 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2935 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2939 if (rtx_equal_p (operands[0], operands[2]))
2940 return \"fprsub%.s %w1,%0\";
2941 if (rtx_equal_p (operands[0], operands[1]))
2942 return \"fpsub%.s %w2,%0\";
2943 if (which_alternative == 0)
2944 return \"fpsub3%.s %w2,%w1,%0\";
2945 return \"fpsub3%.s %2,%1,%0\";
2949 [(set (match_operand:SF 0 "general_operand" "=f")
2950 (minus:SF (match_operand:SF 1 "general_operand" "0")
2951 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2956 [(set (match_operand:SF 0 "general_operand" "=f")
2957 (minus:SF (match_operand:SF 1 "general_operand" "0")
2958 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2963 [(set (match_operand:SF 0 "general_operand" "=f")
2964 (minus:SF (match_operand:SF 1 "general_operand" "0")
2965 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2970 [(set (match_operand:SF 0 "general_operand" "=f")
2971 (minus:SF (match_operand:SF 1 "general_operand" "0")
2972 (match_operand:SF 2 "general_operand" "fdmF")))]
2976 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2977 return \"f%$sub%.x %2,%0\";
2978 return \"f%$sub%.s %f2,%0\";
2981 ;; multiply instructions
2983 (define_insn "mulhi3"
2984 [(set (match_operand:HI 0 "general_operand" "=d")
2985 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2986 (match_operand:HI 2 "general_src_operand" "dmSn")))]
2990 #if defined(MOTOROLA) && !defined(CRDS)
2991 return \"muls%.w %2,%0\";
2993 return \"muls %2,%0\";
2997 (define_insn "mulhisi3"
2998 [(set (match_operand:SI 0 "general_operand" "=d")
2999 (mult:SI (sign_extend:SI
3000 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3002 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3006 #if defined(MOTOROLA) && !defined(CRDS)
3007 return \"muls%.w %2,%0\";
3009 return \"muls %2,%0\";
3014 [(set (match_operand:SI 0 "general_operand" "=d")
3015 (mult:SI (sign_extend:SI
3016 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3017 (match_operand:SI 2 "const_int_operand" "n")))]
3018 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3021 #if defined(MOTOROLA) && !defined(CRDS)
3022 return \"muls%.w %2,%0\";
3024 return \"muls %2,%0\";
3028 (define_expand "mulsi3"
3029 [(set (match_operand:SI 0 "general_operand" "")
3030 (mult:SI (match_operand:SI 1 "general_operand" "")
3031 (match_operand:SI 2 "general_operand" "")))]
3032 "TARGET_68020 || TARGET_5200"
3036 [(set (match_operand:SI 0 "general_operand" "=d")
3037 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3038 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3044 [(set (match_operand:SI 0 "general_operand" "=d")
3045 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3046 (match_operand:SI 2 "general_operand" "d<Q>")))]
3050 (define_insn "umulhisi3"
3051 [(set (match_operand:SI 0 "general_operand" "=d")
3052 (mult:SI (zero_extend:SI
3053 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3055 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3059 #if defined(MOTOROLA) && !defined(CRDS)
3060 return \"mulu%.w %2,%0\";
3062 return \"mulu %2,%0\";
3067 [(set (match_operand:SI 0 "general_operand" "=d")
3068 (mult:SI (zero_extend:SI
3069 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3070 (match_operand:SI 2 "const_int_operand" "n")))]
3071 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3074 #if defined(MOTOROLA) && !defined(CRDS)
3075 return \"mulu%.w %2,%0\";
3077 return \"mulu %2,%0\";
3081 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3082 ;; proper matching constraint. This is because the matching is between
3083 ;; the high-numbered word of the DImode operand[0] and operand[1].
3084 (define_expand "umulsidi3"
3086 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3087 (mult:SI (match_operand:SI 1 "register_operand" "")
3088 (match_operand:SI 2 "nonimmediate_operand" "")))
3089 (set (subreg:SI (match_dup 0) 0)
3090 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3091 (zero_extend:DI (match_dup 2)))
3092 (const_int 32))))])]
3093 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3097 [(set (match_operand:SI 0 "register_operand" "=d")
3098 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3099 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3100 (set (match_operand:SI 3 "register_operand" "=d")
3101 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3102 (zero_extend:DI (match_dup 2)))
3104 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3107 ; Match immediate case. For 2.4 only match things < 2^31.
3108 ; It's tricky with larger values in these patterns since we need to match
3109 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3112 [(set (match_operand:SI 0 "register_operand" "=d")
3113 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3114 (match_operand:SI 2 "const_int_operand" "n")))
3115 (set (match_operand:SI 3 "register_operand" "=d")
3116 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3119 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3120 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3123 (define_expand "mulsidi3"
3125 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3126 (mult:SI (match_operand:SI 1 "register_operand" "")
3127 (match_operand:SI 2 "nonimmediate_operand" "")))
3128 (set (subreg:SI (match_dup 0) 0)
3129 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3130 (sign_extend:DI (match_dup 2)))
3131 (const_int 32))))])]
3132 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3136 [(set (match_operand:SI 0 "register_operand" "=d")
3137 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3138 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3139 (set (match_operand:SI 3 "register_operand" "=d")
3140 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3141 (sign_extend:DI (match_dup 2)))
3143 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3147 [(set (match_operand:SI 0 "register_operand" "=d")
3148 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3149 (match_operand:SI 2 "const_sint32_operand" "")))
3150 (set (match_operand:SI 3 "register_operand" "=d")
3151 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3154 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3157 (define_expand "umulsi3_highpart"
3159 [(set (match_operand:SI 0 "register_operand" "")
3162 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3163 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3165 (clobber (match_dup 3))])]
3166 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3169 operands[3] = gen_reg_rtx (SImode);
3170 if (GET_CODE (operands[2]) == CONST_INT
3171 || GET_CODE (operands[2]) == CONST_DOUBLE)
3173 if (! const_uint32_operand (operands[2], VOIDmode))
3175 /* We have to adjust the operand order for the matching constraints. */
3176 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3177 operands[1], operands[2]));
3183 [(set (match_operand:SI 0 "register_operand" "=d")
3186 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3187 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3189 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3190 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3193 (define_insn "const_umulsi3_highpart"
3194 [(set (match_operand:SI 0 "register_operand" "=d")
3197 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3198 (match_operand 3 "const_uint32_operand" ""))
3200 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3201 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3204 (define_expand "smulsi3_highpart"
3206 [(set (match_operand:SI 0 "register_operand" "")
3209 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3210 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3212 (clobber (match_dup 3))])]
3213 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3216 operands[3] = gen_reg_rtx (SImode);
3217 if (GET_CODE (operands[2]) == CONST_INT
3218 || GET_CODE (operands[2]) == CONST_DOUBLE)
3220 if (! const_sint32_operand (operands[2], VOIDmode))
3222 /* We have to adjust the operand order for the matching constraints. */
3223 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3224 operands[1], operands[2]));
3230 [(set (match_operand:SI 0 "register_operand" "=d")
3233 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3234 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3236 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3237 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3240 (define_insn "const_smulsi3_highpart"
3241 [(set (match_operand:SI 0 "register_operand" "=d")
3244 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3245 (match_operand 3 "const_sint32_operand" ""))
3247 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3248 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3251 (define_expand "muldf3"
3252 [(set (match_operand:DF 0 "general_operand" "")
3253 (mult:DF (match_operand:DF 1 "general_operand" "")
3254 (match_operand:DF 2 "general_operand" "")))]
3255 "TARGET_68881 || TARGET_FPA"
3259 [(set (match_operand:DF 0 "general_operand" "=x,y")
3260 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3261 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3265 if (rtx_equal_p (operands[1], operands[2]))
3266 return \"fpsqr%.d %y1,%0\";
3267 if (rtx_equal_p (operands[0], operands[1]))
3268 return \"fpmul%.d %y2,%0\";
3269 if (rtx_equal_p (operands[0], operands[2]))
3270 return \"fpmul%.d %y1,%0\";
3271 if (which_alternative == 0)
3272 return \"fpmul3%.d %w2,%w1,%0\";
3273 return \"fpmul3%.d %x2,%x1,%0\";
3277 [(set (match_operand:DF 0 "general_operand" "=f")
3278 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3279 (match_operand:DF 1 "general_operand" "0")))]
3284 [(set (match_operand:DF 0 "general_operand" "=f")
3285 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3286 (match_operand:DF 1 "general_operand" "0")))]
3291 [(set (match_operand:DF 0 "general_operand" "=f")
3292 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3293 (match_operand:DF 1 "general_operand" "0")))]
3298 [(set (match_operand:DF 0 "general_operand" "=f")
3299 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3300 (match_operand:DF 2 "general_operand" "fmG")))]
3304 if (GET_CODE (operands[2]) == CONST_DOUBLE
3305 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3307 int i = floating_exact_log2 (operands[2]);
3308 operands[2] = GEN_INT (i);
3309 return \"fscale%.l %2,%0\";
3311 if (REG_P (operands[2]))
3312 return \"f%&mul%.x %2,%0\";
3313 return \"f%&mul%.d %f2,%0\";
3316 (define_expand "mulsf3"
3317 [(set (match_operand:SF 0 "general_operand" "")
3318 (mult:SF (match_operand:SF 1 "general_operand" "")
3319 (match_operand:SF 2 "general_operand" "")))]
3320 "TARGET_68881 || TARGET_FPA"
3324 [(set (match_operand:SF 0 "general_operand" "=x,y")
3325 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3326 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3330 if (rtx_equal_p (operands[1], operands[2]))
3331 return \"fpsqr%.s %w1,%0\";
3332 if (rtx_equal_p (operands[0], operands[1]))
3333 return \"fpmul%.s %w2,%0\";
3334 if (rtx_equal_p (operands[0], operands[2]))
3335 return \"fpmul%.s %w1,%0\";
3336 if (which_alternative == 0)
3337 return \"fpmul3%.s %w2,%w1,%0\";
3338 return \"fpmul3%.s %2,%1,%0\";
3342 [(set (match_operand:SF 0 "general_operand" "=f")
3343 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3344 (match_operand:SF 1 "general_operand" "0")))]
3348 return (TARGET_68040_ONLY
3349 ? \"fsmul%.l %2,%0\"
3350 : \"fsglmul%.l %2,%0\");
3354 [(set (match_operand:SF 0 "general_operand" "=f")
3355 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3356 (match_operand:SF 1 "general_operand" "0")))]
3360 return (TARGET_68040_ONLY
3361 ? \"fsmul%.w %2,%0\"
3362 : \"fsglmul%.w %2,%0\");
3366 [(set (match_operand:SF 0 "general_operand" "=f")
3367 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3368 (match_operand:SF 1 "general_operand" "0")))]
3372 return (TARGET_68040_ONLY
3373 ? \"fsmul%.b %2,%0\"
3374 : \"fsglmul%.b %2,%0\");
3378 [(set (match_operand:SF 0 "general_operand" "=f")
3379 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3380 (match_operand:SF 2 "general_operand" "fdmF")))]
3384 #ifdef FSGLMUL_USE_S
3385 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3386 return (TARGET_68040_ONLY
3387 ? \"fsmul%.s %2,%0\"
3388 : \"fsglmul%.s %2,%0\");
3390 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3391 return (TARGET_68040_ONLY
3392 ? \"fsmul%.x %2,%0\"
3393 : \"fsglmul%.x %2,%0\");
3395 return (TARGET_68040_ONLY
3396 ? \"fsmul%.s %f2,%0\"
3397 : \"fsglmul%.s %f2,%0\");
3400 ;; divide instructions
3402 (define_expand "divdf3"
3403 [(set (match_operand:DF 0 "general_operand" "")
3404 (div:DF (match_operand:DF 1 "general_operand" "")
3405 (match_operand:DF 2 "general_operand" "")))]
3406 "TARGET_68881 || TARGET_FPA"
3410 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3411 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3412 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3416 if (rtx_equal_p (operands[0], operands[2]))
3417 return \"fprdiv%.d %y1,%0\";
3418 if (rtx_equal_p (operands[0], operands[1]))
3419 return \"fpdiv%.d %y2,%0\";
3420 if (which_alternative == 0)
3421 return \"fpdiv3%.d %w2,%w1,%0\";
3422 return \"fpdiv3%.d %x2,%x1,%x0\";
3426 [(set (match_operand:DF 0 "general_operand" "=f")
3427 (div:DF (match_operand:DF 1 "general_operand" "0")
3428 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3433 [(set (match_operand:DF 0 "general_operand" "=f")
3434 (div:DF (match_operand:DF 1 "general_operand" "0")
3435 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3440 [(set (match_operand:DF 0 "general_operand" "=f")
3441 (div:DF (match_operand:DF 1 "general_operand" "0")
3442 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3447 [(set (match_operand:DF 0 "general_operand" "=f")
3448 (div:DF (match_operand:DF 1 "general_operand" "0")
3449 (match_operand:DF 2 "general_operand" "fmG")))]
3453 if (REG_P (operands[2]))
3454 return \"f%&div%.x %2,%0\";
3455 return \"f%&div%.d %f2,%0\";
3458 (define_expand "divsf3"
3459 [(set (match_operand:SF 0 "general_operand" "")
3460 (div:SF (match_operand:SF 1 "general_operand" "")
3461 (match_operand:SF 2 "general_operand" "")))]
3462 "TARGET_68881 || TARGET_FPA"
3466 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3467 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3468 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3472 if (rtx_equal_p (operands[0], operands[1]))
3473 return \"fpdiv%.s %w2,%0\";
3474 if (rtx_equal_p (operands[0], operands[2]))
3475 return \"fprdiv%.s %w1,%0\";
3476 if (which_alternative == 0)
3477 return \"fpdiv3%.s %w2,%w1,%0\";
3478 return \"fpdiv3%.s %2,%1,%0\";
3482 [(set (match_operand:SF 0 "general_operand" "=f")
3483 (div:SF (match_operand:SF 1 "general_operand" "0")
3484 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3488 return (TARGET_68040_ONLY
3489 ? \"fsdiv%.l %2,%0\"
3490 : \"fsgldiv%.l %2,%0\");
3494 [(set (match_operand:SF 0 "general_operand" "=f")
3495 (div:SF (match_operand:SF 1 "general_operand" "0")
3496 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3500 return (TARGET_68040_ONLY
3501 ? \"fsdiv%.w %2,%0\"
3502 : \"fsgldiv%.w %2,%0\");
3506 [(set (match_operand:SF 0 "general_operand" "=f")
3507 (div:SF (match_operand:SF 1 "general_operand" "0")
3508 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3512 return (TARGET_68040_ONLY
3513 ? \"fsdiv%.b %2,%0\"
3514 : \"fsgldiv%.b %2,%0\");
3518 [(set (match_operand:SF 0 "general_operand" "=f")
3519 (div:SF (match_operand:SF 1 "general_operand" "0")
3520 (match_operand:SF 2 "general_operand" "fdmF")))]
3524 #ifdef FSGLDIV_USE_S
3525 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3526 return (TARGET_68040_ONLY
3527 ? \"fsdiv%.s %2,%0\"
3528 : \"fsgldiv%.s %2,%0\");
3530 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3531 return (TARGET_68040_ONLY
3532 ? \"fsdiv%.x %2,%0\"
3533 : \"fsgldiv%.x %2,%0\");
3535 return (TARGET_68040_ONLY
3536 ? \"fsdiv%.s %f2,%0\"
3537 : \"fsgldiv%.s %f2,%0\");
3540 ;; Remainder instructions.
3542 (define_insn "divmodsi4"
3543 [(set (match_operand:SI 0 "general_operand" "=d")
3544 (div:SI (match_operand:SI 1 "general_operand" "0")
3545 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3546 (set (match_operand:SI 3 "general_operand" "=d")
3547 (mod:SI (match_dup 1) (match_dup 2)))]
3548 "TARGET_68020 && !TARGET_5200"
3551 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3552 return \"divs%.l %2,%0\";
3554 return \"divsl%.l %2,%3:%0\";
3557 (define_insn "udivmodsi4"
3558 [(set (match_operand:SI 0 "general_operand" "=d")
3559 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3560 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3561 (set (match_operand:SI 3 "general_operand" "=d")
3562 (umod:SI (match_dup 1) (match_dup 2)))]
3563 "TARGET_68020 && !TARGET_5200"
3566 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3567 return \"divu%.l %2,%0\";
3569 return \"divul%.l %2,%3:%0\";
3572 (define_insn "divmodhi4"
3573 [(set (match_operand:HI 0 "general_operand" "=d")
3574 (div:HI (match_operand:HI 1 "general_operand" "0")
3575 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3576 (set (match_operand:HI 3 "general_operand" "=d")
3577 (mod:HI (match_dup 1) (match_dup 2)))]
3582 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3584 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3586 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3589 return \"move%.l %0,%3\;swap %3\";
3595 (define_insn "udivmodhi4"
3596 [(set (match_operand:HI 0 "general_operand" "=d")
3597 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3598 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3599 (set (match_operand:HI 3 "general_operand" "=d")
3600 (umod:HI (match_dup 1) (match_dup 2)))]
3605 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3607 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3609 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3612 return \"move%.l %0,%3\;swap %3\";
3618 ;; logical-and instructions
3620 ;; "anddi3" is mainly here to help combine().
3621 (define_insn "anddi3"
3622 [(set (match_operand:DI 0 "general_operand" "=o,d")
3623 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3624 (match_operand:DI 2 "general_operand" "dn,don")))]
3629 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3630 if (CONSTANT_P (operands[2]))
3634 split_double (operands[2], &hi, &lo);
3636 switch (INTVAL (hi))
3639 output_asm_insn (\"clr%.l %0\", operands);
3647 xoperands[0] = operands[0];
3649 output_asm_insn (output_andsi3 (xoperands), xoperands);
3652 if (GET_CODE (operands[0]) == REG)
3653 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3655 operands[0] = adjust_address (operands[0], SImode, 4);
3656 switch (INTVAL (lo))
3659 output_asm_insn (\"clr%.l %0\", operands);
3667 xoperands[0] = operands[0];
3669 output_asm_insn (output_andsi3 (xoperands), xoperands);
3674 if (GET_CODE (operands[0]) != REG)
3676 operands[1] = adjust_address (operands[0], SImode, 4);
3677 return \"and%.l %2,%0\;and%.l %R2,%1\";
3679 if (GET_CODE (operands[2]) != REG)
3681 operands[1] = adjust_address (operands[2], SImode, 4);
3682 return \"and%.l %2,%0\;and%.l %1,%R0\";
3684 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3687 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3688 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3689 ;; can't allocate pseudos into it.
3691 (define_expand "andsi3"
3692 [(set (match_operand:SI 0 "not_sp_operand" "")
3693 (and:SI (match_operand:SI 1 "general_operand" "")
3694 (match_operand:SI 2 "general_src_operand" "")))]
3698 (define_insn "andsi3_internal"
3699 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3700 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3701 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3705 return output_andsi3 (operands);
3708 (define_insn "andsi3_5200"
3709 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3710 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3711 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3715 (define_insn "andhi3"
3716 [(set (match_operand:HI 0 "general_operand" "=m,d")
3717 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3718 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3723 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3724 (and:HI (match_dup 0)
3725 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3730 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3731 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3736 (define_insn "andqi3"
3737 [(set (match_operand:QI 0 "general_operand" "=m,d")
3738 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3739 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3744 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3745 (and:QI (match_dup 0)
3746 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3751 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3752 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3757 ;; inclusive-or instructions
3759 (define_insn "iordi_zext"
3760 [(set (match_operand:DI 0 "general_operand" "=o,d")
3761 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3762 (match_operand:DI 2 "general_operand" "0,0")))]
3769 if (GET_CODE (operands[0]) == REG)
3770 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3772 operands[0] = adjust_address (operands[0], SImode, 4);
3773 if (GET_MODE (operands[1]) == SImode)
3774 return \"or%.l %1,%0\";
3775 byte_mode = (GET_MODE (operands[1]) == QImode);
3776 if (GET_CODE (operands[0]) == MEM)
3777 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3780 return \"or%.b %1,%0\";
3782 return \"or%.w %1,%0\";
3785 ;; "iordi3" is mainly here to help combine().
3786 (define_insn "iordi3"
3787 [(set (match_operand:DI 0 "general_operand" "=o,d")
3788 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3789 (match_operand:DI 2 "general_operand" "dn,don")))]
3794 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3795 if (CONSTANT_P (operands[2]))
3799 split_double (operands[2], &hi, &lo);
3801 switch (INTVAL (hi))
3806 /* FIXME : a scratch register would be welcome here if operand[0]
3807 is not a register */
3808 output_asm_insn (\"move%.l %#-1,%0\", operands);
3814 xoperands[0] = operands[0];
3816 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3819 if (GET_CODE (operands[0]) == REG)
3820 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3822 operands[0] = adjust_address (operands[0], SImode, 4);
3823 switch (INTVAL (lo))
3828 /* FIXME : a scratch register would be welcome here if operand[0]
3829 is not a register */
3830 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3836 xoperands[0] = operands[0];
3838 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3843 if (GET_CODE (operands[0]) != REG)
3845 operands[1] = adjust_address (operands[0], SImode, 4);
3846 return \"or%.l %2,%0\;or%.l %R2,%1\";
3848 if (GET_CODE (operands[2]) != REG)
3850 operands[1] = adjust_address (operands[2], SImode, 4);
3851 return \"or%.l %2,%0\;or%.l %1,%R0\";
3853 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3856 (define_expand "iorsi3"
3857 [(set (match_operand:SI 0 "general_operand" "")
3858 (ior:SI (match_operand:SI 1 "general_operand" "")
3859 (match_operand:SI 2 "general_src_operand" "")))]
3863 (define_insn "iorsi3_internal"
3864 [(set (match_operand:SI 0 "general_operand" "=m,d")
3865 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3866 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3870 return output_iorsi3 (operands);
3873 (define_insn "iorsi3_5200"
3874 [(set (match_operand:SI 0 "general_operand" "=m,d")
3875 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3876 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3880 (define_insn "iorhi3"
3881 [(set (match_operand:HI 0 "general_operand" "=m,d")
3882 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3883 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3888 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3889 (ior:HI (match_dup 0)
3890 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3895 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3896 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3901 (define_insn "iorqi3"
3902 [(set (match_operand:QI 0 "general_operand" "=m,d")
3903 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3904 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3909 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3910 (ior:QI (match_dup 0)
3911 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3916 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3917 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3922 ;; On all 68k models, this makes faster code in a special case.
3923 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3925 (define_insn "iorsi_zexthi_ashl16"
3926 [(set (match_operand:SI 0 "general_operand" "=&d")
3927 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3928 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3934 if (GET_CODE (operands[2]) != REG)
3935 operands[2] = adjust_address (operands[2], HImode, 2);
3936 if (GET_CODE (operands[2]) != REG
3937 || REGNO (operands[2]) != REGNO (operands[0]))
3938 output_asm_insn (\"move%.w %2,%0\", operands);
3939 return \"swap %0\;mov%.w %1,%0\";
3942 (define_insn "iorsi_zext"
3943 [(set (match_operand:SI 0 "general_operand" "=o,d")
3944 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3945 (match_operand:SI 2 "general_operand" "0,0")))]
3952 byte_mode = (GET_MODE (operands[1]) == QImode);
3953 if (GET_CODE (operands[0]) == MEM)
3954 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3957 return \"or%.b %1,%0\";
3959 return \"or%.w %1,%0\";
3964 ;; "xordi3" is mainly here to help combine().
3965 (define_insn "xordi3"
3966 [(set (match_operand:DI 0 "general_operand" "=od")
3967 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3968 (match_operand:DI 2 "general_operand" "dn")))]
3973 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3975 if (CONSTANT_P (operands[2]))
3979 split_double (operands[2], &hi, &lo);
3981 switch (INTVAL (hi))
3986 output_asm_insn (\"not%.l %0\", operands);
3989 /* FIXME : a scratch register would be welcome here if
3990 -128 <= INTVAL (hi) < -1 */
3994 xoperands[0] = operands[0];
3996 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3999 if (GET_CODE (operands[0]) == REG)
4000 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4002 operands[0] = adjust_address (operands[0], SImode, 4);
4003 switch (INTVAL (lo))
4008 output_asm_insn (\"not%.l %0\", operands);
4011 /* FIXME : a scratch register would be welcome here if
4012 -128 <= INTVAL (lo) < -1 */
4014 /* FIXME : this should be merged with xorsi3 */
4018 xoperands[0] = operands[0];
4020 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4025 if (GET_CODE (operands[0]) != REG)
4027 operands[1] = adjust_address (operands[0], SImode, 4);
4028 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4030 if (GET_CODE (operands[2]) != REG)
4032 operands[1] = adjust_address (operands[2], SImode, 4);
4033 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4035 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4038 (define_expand "xorsi3"
4039 [(set (match_operand:SI 0 "general_operand" "")
4040 (xor:SI (match_operand:SI 1 "general_operand" "")
4041 (match_operand:SI 2 "general_operand" "")))]
4045 (define_insn "xorsi3_internal"
4046 [(set (match_operand:SI 0 "general_operand" "=do,m")
4047 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4048 (match_operand:SI 2 "general_operand" "di,dKT")))]
4053 return output_xorsi3 (operands);
4056 (define_insn "xorsi3_5200"
4057 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4058 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4059 (match_operand:SI 2 "general_operand" "d,Ks")))]
4063 (define_insn "xorhi3"
4064 [(set (match_operand:HI 0 "general_operand" "=dm")
4065 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4066 (match_operand:HI 2 "general_operand" "dn")))]
4071 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4072 (xor:HI (match_dup 0)
4073 (match_operand:HI 1 "general_operand" "dn")))]
4078 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4079 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4084 (define_insn "xorqi3"
4085 [(set (match_operand:QI 0 "general_operand" "=dm")
4086 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4087 (match_operand:QI 2 "general_operand" "dn")))]
4092 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4093 (xor:QI (match_dup 0)
4094 (match_operand:QI 1 "general_operand" "dn")))]
4099 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4100 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4105 ;; negation instructions
4107 (define_expand "negdi2"
4108 [(set (match_operand:DI 0 "general_operand" "")
4109 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4114 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4116 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4120 (define_insn "negdi2_internal"
4121 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4122 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4126 if (which_alternative == 0)
4127 return \"neg%.l %0\;negx%.l %0\";
4128 if (GET_CODE (operands[0]) == REG)
4129 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4131 operands[1] = adjust_address (operands[0], SImode, 4);
4132 if (ADDRESS_REG_P (operands[0]))
4133 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4135 return \"neg%.l %1\;negx%.l %0\";
4138 (define_insn "negdi2_5200"
4139 [(set (match_operand:DI 0 "general_operand" "=d")
4140 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4144 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4145 return \"neg%.l %1\;negx%.l %0\";
4148 (define_expand "negsi2"
4149 [(set (match_operand:SI 0 "general_operand" "")
4150 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4155 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4157 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4161 (define_insn "negsi2_internal"
4162 [(set (match_operand:SI 0 "general_operand" "=dm")
4163 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4167 (define_insn "negsi2_5200"
4168 [(set (match_operand:SI 0 "general_operand" "=d")
4169 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4173 (define_insn "neghi2"
4174 [(set (match_operand:HI 0 "general_operand" "=dm")
4175 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4180 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4181 (neg:HI (match_dup 0)))]
4185 (define_insn "negqi2"
4186 [(set (match_operand:QI 0 "general_operand" "=dm")
4187 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4192 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4193 (neg:QI (match_dup 0)))]
4197 ;; If using software floating point, just flip the sign bit.
4199 (define_expand "negsf2"
4200 [(set (match_operand:SF 0 "general_operand" "")
4201 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4205 if (!TARGET_FPA && !TARGET_68881)
4210 target = operand_subword_force (operands[0], 0, SFmode);
4211 result = expand_binop (SImode, xor_optab,
4212 operand_subword_force (operands[1], 0, SFmode),
4213 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4217 if (result != target)
4218 emit_move_insn (result, target);
4220 /* Make a place for REG_EQUAL. */
4221 emit_move_insn (operands[0], operands[0]);
4227 [(set (match_operand:SF 0 "general_operand" "=x,y")
4228 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4233 [(set (match_operand:SF 0 "general_operand" "=f,d")
4234 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4238 if (DATA_REG_P (operands[0]))
4240 operands[1] = GEN_INT (31);
4241 return \"bchg %1,%0\";
4243 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4244 return \"f%$neg%.x %1,%0\";
4245 return \"f%$neg%.s %f1,%0\";
4248 (define_expand "negdf2"
4249 [(set (match_operand:DF 0 "general_operand" "")
4250 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4254 if (!TARGET_FPA && !TARGET_68881)
4261 target = operand_subword (operands[0], 0, 1, DFmode);
4262 result = expand_binop (SImode, xor_optab,
4263 operand_subword_force (operands[1], 0, DFmode),
4264 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
4268 if (result != target)
4269 emit_move_insn (result, target);
4271 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4272 operand_subword_force (operands[1], 1, DFmode));
4274 insns = get_insns ();
4277 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4283 [(set (match_operand:DF 0 "general_operand" "=x,y")
4284 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4289 [(set (match_operand:DF 0 "general_operand" "=f,d")
4290 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4294 if (DATA_REG_P (operands[0]))
4296 operands[1] = GEN_INT (31);
4297 return \"bchg %1,%0\";
4299 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4300 return \"f%&neg%.x %1,%0\";
4301 return \"f%&neg%.d %f1,%0\";
4304 ;; Sqrt instruction for the 68881
4306 (define_insn "sqrtsf2"
4307 [(set (match_operand:SF 0 "general_operand" "=f")
4308 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4312 if (FP_REG_P (operands[1]))
4313 return \"f%$sqrt%.x %1,%0\";
4315 return \"f%$sqrt%.s %1,%0\";
4318 (define_insn "sqrtdf2"
4319 [(set (match_operand:DF 0 "general_operand" "=f")
4320 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4324 if (FP_REG_P (operands[1]))
4325 return \"f%&sqrt%.x %1,%0\";
4327 return \"f%&sqrt%.d %1,%0\";
4330 ;; Absolute value instructions
4331 ;; If using software floating point, just zero the sign bit.
4333 (define_expand "abssf2"
4334 [(set (match_operand:SF 0 "general_operand" "")
4335 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4339 if (!TARGET_FPA && !TARGET_68881)
4344 target = operand_subword_force (operands[0], 0, SFmode);
4345 result = expand_binop (SImode, and_optab,
4346 operand_subword_force (operands[1], 0, SFmode),
4347 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4351 if (result != target)
4352 emit_move_insn (result, target);
4354 /* Make a place for REG_EQUAL. */
4355 emit_move_insn (operands[0], operands[0]);
4361 [(set (match_operand:SF 0 "general_operand" "=x,y")
4362 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4367 [(set (match_operand:SF 0 "general_operand" "=f")
4368 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4372 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4373 return \"f%$abs%.x %1,%0\";
4374 return \"f%$abs%.s %f1,%0\";
4377 (define_expand "absdf2"
4378 [(set (match_operand:DF 0 "general_operand" "")
4379 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4383 if (!TARGET_FPA && !TARGET_68881)
4390 target = operand_subword (operands[0], 0, 1, DFmode);
4391 result = expand_binop (SImode, and_optab,
4392 operand_subword_force (operands[1], 0, DFmode),
4393 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4397 if (result != target)
4398 emit_move_insn (result, target);
4400 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4401 operand_subword_force (operands[1], 1, DFmode));
4403 insns = get_insns ();
4406 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4412 [(set (match_operand:DF 0 "general_operand" "=x,y")
4413 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4418 [(set (match_operand:DF 0 "general_operand" "=f")
4419 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4423 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4424 return \"f%&abs%.x %1,%0\";
4425 return \"f%&abs%.d %f1,%0\";
4428 ;; one complement instructions
4430 ;; "one_cmpldi2" is mainly here to help combine().
4431 (define_insn "one_cmpldi2"
4432 [(set (match_operand:DI 0 "general_operand" "=dm")
4433 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4438 if (GET_CODE (operands[0]) == REG)
4439 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4440 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4441 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4442 operands[1] = operands[0];
4444 operands[1] = adjust_address (operands[0], SImode, 4);
4445 return \"not%.l %1\;not%.l %0\";
4448 (define_expand "one_cmplsi2"
4449 [(set (match_operand:SI 0 "general_operand" "")
4450 (not:SI (match_operand:SI 1 "general_operand" "")))]
4455 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4457 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4461 (define_insn "one_cmplsi2_internal"
4462 [(set (match_operand:SI 0 "general_operand" "=dm")
4463 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4467 (define_insn "one_cmplsi2_5200"
4468 [(set (match_operand:SI 0 "general_operand" "=d")
4469 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4473 (define_insn "one_cmplhi2"
4474 [(set (match_operand:HI 0 "general_operand" "=dm")
4475 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4480 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4481 (not:HI (match_dup 0)))]
4485 (define_insn "one_cmplqi2"
4486 [(set (match_operand:QI 0 "general_operand" "=dm")
4487 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4492 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4493 (not:QI (match_dup 0)))]
4497 ;; arithmetic shift instructions
4498 ;; We don't need the shift memory by 1 bit instruction
4500 (define_insn "ashldi_extsi"
4501 [(set (match_operand:DI 0 "general_operand" "=ro")
4503 (match_operator:DI 2 "extend_operator"
4504 [(match_operand:SI 1 "general_operand" "rm")])
4510 if (GET_CODE (operands[0]) == REG)
4511 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4513 operands[2] = adjust_address (operands[0], SImode, 4);
4514 if (ADDRESS_REG_P (operands[0]))
4515 return \"move%.l %1,%0\;sub%.l %2,%2\";
4517 return \"move%.l %1,%0\;clr%.l %2\";
4520 (define_insn "ashldi_sexthi"
4521 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4522 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4524 (clobber (match_scratch:SI 2 "=a,X"))]
4529 if (GET_CODE (operands[0]) == MEM)
4531 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4532 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4533 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4534 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4537 operands[3] = adjust_address (operands[0], SImode, 4);
4538 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4541 else if (DATA_REG_P (operands[0]))
4542 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4544 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4547 (define_insn "ashldi_const32"
4548 [(set (match_operand:DI 0 "general_operand" "=rm")
4549 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4555 if (GET_CODE (operands[1]) == REG)
4556 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4558 operands[3] = adjust_address (operands[1], SImode, 4);
4559 if (GET_CODE (operands[0]) == REG)
4560 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4561 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4562 return \"clr%.l %0\;move%.l %3,%0\";
4563 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4564 return \"move%.l %3,%0\;clr%.l %0\";
4566 operands[2] = adjust_address (operands[0], SImode, 4);
4567 if (ADDRESS_REG_P (operands[2]))
4568 return \"move%.l %3,%0\;sub%.l %2,%2\";
4570 return \"move%.l %3,%0\;clr%.l %2\";
4573 ;; The predicate below must be general_operand, because ashldi3 allows that
4574 (define_insn "ashldi_const"
4575 [(set (match_operand:DI 0 "general_operand" "=d")
4576 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4577 (match_operand 2 "const_int_operand" "n")))]
4579 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4580 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4581 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4584 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4585 if (INTVAL (operands[2]) == 1)
4586 return \"add%.l %1,%1\;addx%.l %0,%0\";
4587 else if (INTVAL (operands[2]) == 8)
4588 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4589 else if (INTVAL (operands[2]) == 16)
4590 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4591 else if (INTVAL (operands[2]) == 48)
4592 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4593 else if (INTVAL (operands[2]) == 2)
4594 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4595 else if (INTVAL (operands[2]) == 3)
4596 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4597 else /* 32 < INTVAL (operands[2]) <= 63 */
4599 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4600 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4601 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4602 return \"mov%.l %1,%0\;moveq %#0,%1\";
4606 (define_expand "ashldi3"
4607 [(set (match_operand:DI 0 "general_operand" "")
4608 (ashift:DI (match_operand:DI 1 "general_operand" "")
4609 (match_operand 2 "const_int_operand" "")))]
4613 /* ??? This is a named pattern like this is not allowed to FAIL based
4615 if (GET_CODE (operands[2]) != CONST_INT
4616 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4617 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4618 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4622 ;; On most 68k models, this makes faster code in a special case.
4624 (define_insn "ashlsi_16"
4625 [(set (match_operand:SI 0 "register_operand" "=d")
4626 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4632 return \"swap %0\;clr%.w %0\";
4635 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4636 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4638 ;; On the 68000, this makes faster code in a special case.
4640 (define_insn "ashlsi_17_24"
4641 [(set (match_operand:SI 0 "register_operand" "=d")
4642 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4643 (match_operand:SI 2 "const_int_operand" "n")))]
4644 "(! TARGET_68020 && !TARGET_5200
4645 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4650 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4651 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4654 (define_insn "ashlsi3"
4655 [(set (match_operand:SI 0 "register_operand" "=d")
4656 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4657 (match_operand:SI 2 "general_operand" "dI")))]
4661 if (operands[2] == const1_rtx)
4663 cc_status.flags = CC_NO_OVERFLOW;
4664 return \"add%.l %0,%0\";
4666 return \"lsl%.l %2,%0\";
4669 (define_insn "ashlhi3"
4670 [(set (match_operand:HI 0 "register_operand" "=d")
4671 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4672 (match_operand:HI 2 "general_operand" "dI")))]
4677 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4678 (ashift:HI (match_dup 0)
4679 (match_operand:HI 1 "general_operand" "dI")))]
4683 (define_insn "ashlqi3"
4684 [(set (match_operand:QI 0 "register_operand" "=d")
4685 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4686 (match_operand:QI 2 "general_operand" "dI")))]
4691 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4692 (ashift:QI (match_dup 0)
4693 (match_operand:QI 1 "general_operand" "dI")))]
4697 ;; On most 68k models, this makes faster code in a special case.
4699 (define_insn "ashrsi_16"
4700 [(set (match_operand:SI 0 "register_operand" "=d")
4701 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4704 "swap %0\;ext%.l %0")
4706 ;; On the 68000, this makes faster code in a special case.
4709 [(set (match_operand:SI 0 "register_operand" "=d")
4710 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4711 (match_operand:SI 2 "const_int_operand" "n")))]
4712 "(! TARGET_68020 && !TARGET_5200
4713 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4716 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4717 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4720 (define_insn "subreghi1ashrdi_const32"
4721 [(set (match_operand:HI 0 "general_operand" "=rm")
4722 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4723 (const_int 32)) 4))]
4727 if (GET_CODE (operands[1]) != REG)
4728 operands[1] = adjust_address (operands[1], HImode, 2);
4729 return \"move%.w %1,%0\";
4732 (define_insn "subregsi1ashrdi_const32"
4733 [(set (match_operand:SI 0 "general_operand" "=rm")
4734 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4735 (const_int 32)) 4))]
4739 return \"move%.l %1,%0\";
4742 (define_insn "ashrdi_const32"
4743 [(set (match_operand:DI 0 "register_operand" "=d")
4744 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4750 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4752 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4754 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4757 (define_insn "ashrdi_const32_mem"
4758 [(set (match_operand:DI 0 "general_operand" "=o,<")
4759 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4761 (clobber (match_scratch:SI 2 "=d,d"))]
4766 if (which_alternative == 1)
4767 operands[3] = operands[0];
4769 operands[3] = adjust_address (operands[0], SImode, 4);
4771 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4773 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4776 ;; The predicate below must be general_operand, because ashrdi3 allows that
4777 (define_insn "ashrdi_const"
4778 [(set (match_operand:DI 0 "general_operand" "=d")
4779 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4780 (match_operand 2 "const_int_operand" "n")))]
4782 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4783 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4784 || INTVAL (operands[2]) == 31
4785 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4788 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4789 if (INTVAL (operands[2]) == 63)
4790 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4792 if (INTVAL (operands[2]) == 1)
4793 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4794 else if (INTVAL (operands[2]) == 8)
4795 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4796 else if (INTVAL (operands[2]) == 16)
4797 return \"move%.w %0,%1\;swap %0\;ext%.l %0\;swap %1\";
4798 else if (INTVAL (operands[2]) == 48)
4799 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4800 else if (INTVAL (operands[2]) == 31)
4801 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4802 else if (INTVAL (operands[2]) == 2)
4803 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4804 else if (INTVAL (operands[2]) == 3)
4805 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4806 else /* 32 < INTVAL (operands[2]) <= 63 */
4808 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4809 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4810 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4811 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4812 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4813 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4817 (define_expand "ashrdi3"
4818 [(set (match_operand:DI 0 "general_operand" "")
4819 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4820 (match_operand 2 "const_int_operand" "")))]
4824 /* ??? This is a named pattern like this is not allowed to FAIL based
4826 if (GET_CODE (operands[2]) != CONST_INT
4827 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4828 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4829 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4833 ;; On all 68k models, this makes faster code in a special case.
4835 (define_insn "ashrsi_31"
4836 [(set (match_operand:SI 0 "register_operand" "=d")
4837 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4842 return \"add%.l %0,%0\;subx%.l %0,%0\";
4845 (define_insn "ashrsi3"
4846 [(set (match_operand:SI 0 "register_operand" "=d")
4847 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4848 (match_operand:SI 2 "general_operand" "dI")))]
4852 (define_insn "ashrhi3"
4853 [(set (match_operand:HI 0 "register_operand" "=d")
4854 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4855 (match_operand:HI 2 "general_operand" "dI")))]
4860 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4861 (ashiftrt:HI (match_dup 0)
4862 (match_operand:HI 1 "general_operand" "dI")))]
4866 (define_insn "ashrqi3"
4867 [(set (match_operand:QI 0 "register_operand" "=d")
4868 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4869 (match_operand:QI 2 "general_operand" "dI")))]
4874 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4875 (ashiftrt:QI (match_dup 0)
4876 (match_operand:QI 1 "general_operand" "dI")))]
4880 ;; logical shift instructions
4882 ;; commented out because of reload problems in 950612-1.c
4885 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4886 ;; (const_int 32)) 4))
4887 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4888 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4889 ;; (const_int 32)) 4))]
4893 ;; return \"move%.l %0,%1\";
4898 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4899 ;; (const_int 32)) 0))
4900 ;; (set (match_operand:DI 1 "general_operand" "=do")
4901 ;; (lshiftrt:DI (match_dup 0)
4902 ;; (const_int 32)))]
4906 ;; if (GET_CODE (operands[1]) == REG)
4907 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4909 ;; operands[2] = adjust_address (operands[1], SImode, 4);
4910 ;; return \"move%.l %0,%2\;clr%.l %1\";
4913 (define_insn "subreg1lshrdi_const32"
4914 [(set (match_operand:SI 0 "general_operand" "=rm")
4915 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4916 (const_int 32)) 4))]
4920 return \"move%.l %1,%0\";
4923 (define_insn "lshrdi_const32"
4924 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4925 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4931 if (which_alternative == 1)
4932 return \"move%.l %1,%0\;clr%.l %0\";
4933 if (which_alternative == 2)
4934 return \"clr%.l %0\;move%.l %1,%0\";
4935 if (GET_CODE (operands[0]) == REG)
4936 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4938 operands[2] = adjust_address (operands[0], SImode, 4);
4939 if (GET_CODE (operands[1]) == REG)
4940 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4942 operands[3] = adjust_address (operands[1], SImode, 4);
4943 if (ADDRESS_REG_P (operands[0]))
4944 return \"move%.l %1,%2\;sub%.l %0,%0\";
4946 return \"move%.l %1,%2\;clr%.l %0\";
4949 ;; The predicate below must be general_operand, because lshrdi3 allows that
4950 (define_insn "lshrdi_const"
4951 [(set (match_operand:DI 0 "general_operand" "=d")
4952 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4953 (match_operand 2 "const_int_operand" "n")))]
4955 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4956 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4957 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4960 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4961 if (INTVAL (operands[2]) == 63)
4962 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4964 if (INTVAL (operands[2]) == 1)
4965 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4966 else if (INTVAL (operands[2]) == 8)
4967 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4968 else if (INTVAL (operands[2]) == 16)
4969 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4970 else if (INTVAL (operands[2]) == 48)
4971 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4972 else if (INTVAL (operands[2]) == 2)
4973 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4974 else if (INTVAL (operands[2]) == 3)
4975 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4976 else /* 32 < INTVAL (operands[2]) <= 63 */
4978 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4979 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4980 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4981 return \"mov%.l %0,%1\;moveq %#0,%0\";
4985 (define_expand "lshrdi3"
4986 [(set (match_operand:DI 0 "general_operand" "")
4987 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4988 (match_operand 2 "const_int_operand" "")))]
4992 /* ??? This is a named pattern like this is not allowed to FAIL based
4994 if (GET_CODE (operands[2]) != CONST_INT
4995 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4996 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4997 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5001 ;; On all 68k models, this makes faster code in a special case.
5003 (define_insn "lshrsi_31"
5004 [(set (match_operand:SI 0 "register_operand" "=d")
5005 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5010 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5013 ;; On most 68k models, this makes faster code in a special case.
5015 (define_insn "lshrsi_16"
5016 [(set (match_operand:SI 0 "register_operand" "=d")
5017 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5023 return \"clr%.w %0\;swap %0\";
5026 ;; On the 68000, this makes faster code in a special case.
5028 (define_insn "lshrsi_17_24"
5029 [(set (match_operand:SI 0 "register_operand" "=d")
5030 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5031 (match_operand:SI 2 "const_int_operand" "n")))]
5032 "(! TARGET_68020 && !TARGET_5200
5033 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5036 /* I think lsr%.w sets the CC properly. */
5037 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5038 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5041 (define_insn "lshrsi3"
5042 [(set (match_operand:SI 0 "register_operand" "=d")
5043 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5044 (match_operand:SI 2 "general_operand" "dI")))]
5048 (define_insn "lshrhi3"
5049 [(set (match_operand:HI 0 "register_operand" "=d")
5050 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5051 (match_operand:HI 2 "general_operand" "dI")))]
5056 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5057 (lshiftrt:HI (match_dup 0)
5058 (match_operand:HI 1 "general_operand" "dI")))]
5062 (define_insn "lshrqi3"
5063 [(set (match_operand:QI 0 "register_operand" "=d")
5064 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5065 (match_operand:QI 2 "general_operand" "dI")))]
5070 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5071 (lshiftrt:QI (match_dup 0)
5072 (match_operand:QI 1 "general_operand" "dI")))]
5076 ;; rotate instructions
5078 (define_insn "rotlsi3"
5079 [(set (match_operand:SI 0 "register_operand" "=d")
5080 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5081 (match_operand:SI 2 "general_operand" "dINO")))]
5085 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5087 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5089 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5090 return \"ror%.l %2,%0\";
5093 return \"rol%.l %2,%0\";
5096 (define_insn "rotlhi3"
5097 [(set (match_operand:HI 0 "register_operand" "=d")
5098 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5099 (match_operand:HI 2 "general_operand" "dIP")))]
5103 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5105 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5106 return \"ror%.w %2,%0\";
5109 return \"rol%.w %2,%0\";
5113 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5114 (rotate:HI (match_dup 0)
5115 (match_operand:HI 1 "general_operand" "dIP")))]
5119 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5121 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5122 return \"ror%.w %2,%0\";
5125 return \"rol%.w %2,%0\";
5128 (define_insn "rotlqi3"
5129 [(set (match_operand:QI 0 "register_operand" "=d")
5130 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5131 (match_operand:QI 2 "general_operand" "dI")))]
5135 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5137 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5138 return \"ror%.b %2,%0\";
5141 return \"rol%.b %2,%0\";
5145 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5146 (rotate:QI (match_dup 0)
5147 (match_operand:QI 1 "general_operand" "dI")))]
5151 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5153 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5154 return \"ror%.b %2,%0\";
5157 return \"rol%.b %2,%0\";
5160 (define_insn "rotrsi3"
5161 [(set (match_operand:SI 0 "register_operand" "=d")
5162 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5163 (match_operand:SI 2 "general_operand" "dI")))]
5167 (define_insn "rotrhi3"
5168 [(set (match_operand:HI 0 "register_operand" "=d")
5169 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5170 (match_operand:HI 2 "general_operand" "dI")))]
5175 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5176 (rotatert:HI (match_dup 0)
5177 (match_operand:HI 1 "general_operand" "dI")))]
5181 (define_insn "rotrqi3"
5182 [(set (match_operand:QI 0 "register_operand" "=d")
5183 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5184 (match_operand:QI 2 "general_operand" "dI")))]
5189 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5190 (rotatert:QI (match_dup 0)
5191 (match_operand:QI 1 "general_operand" "dI")))]
5196 ;; Bit set/clear in memory byte.
5198 ;; set bit, bit number is int
5199 (define_insn "bsetmemqi"
5200 [(set (match_operand:QI 0 "memory_operand" "+m")
5201 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5202 (match_operand:SI 1 "general_operand" "d")) 0)
5208 return \"bset %1,%0\";
5211 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5213 [(set (match_operand:QI 0 "memory_operand" "+m")
5214 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5215 (match_operator:SI 2 "extend_operator"
5216 [(match_operand 1 "general_operand" "d")])) 0)
5222 return \"bset %1,%0\";
5225 ;; clear bit, bit number is int
5226 (define_insn "bclrmemqi"
5227 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5229 (minus:SI (const_int 7)
5230 (match_operand:SI 1 "general_operand" "d")))
5236 return \"bclr %1,%0\";
5239 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5241 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5243 (minus:SI (const_int 7)
5244 (match_operator:SI 2 "extend_operator"
5245 [(match_operand 1 "general_operand" "d")])))
5251 return \"bclr %1,%0\";
5254 ;; Special cases of bit-field insns which we should
5255 ;; recognize in preference to the general case.
5256 ;; These handle aligned 8-bit and 16-bit fields,
5257 ;; which can usually be done with move instructions.
5260 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5261 ; alignment of structure members is specified.
5263 ; The move is allowed to be odd byte aligned, because that's still faster
5264 ; than an odd byte aligned bit field instruction.
5267 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5269 (match_operand:SI 1 "const_int_operand" "n"))
5270 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5271 "TARGET_68020 && TARGET_BITFIELD
5272 && (INTVAL (operands[1]) % 8) == 0
5273 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5277 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5279 return \"move%.l %2,%0\";
5283 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5284 (match_operand:SI 1 "const_int_operand" "n")
5285 (match_operand:SI 2 "const_int_operand" "n"))
5286 (match_operand:SI 3 "register_operand" "d"))]
5287 "TARGET_68020 && TARGET_BITFIELD
5288 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5289 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5290 && (GET_CODE (operands[0]) == REG
5291 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5294 if (REG_P (operands[0]))
5296 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5297 return \"bfins %3,%0{%b2:%b1}\";
5300 operands[0] = adjust_address (operands[0],
5301 INTVAL (operands[1]) == 8 ? QImode : HImode,
5302 INTVAL (operands[2]) / 8);
5304 if (GET_CODE (operands[3]) == MEM)
5305 operands[3] = adjust_address (operands[3],
5306 INTVAL (operands[1]) == 8 ? QImode : HImode,
5307 (32 - INTVAL (operands[1])) / 8);
5309 if (INTVAL (operands[1]) == 8)
5310 return \"move%.b %3,%0\";
5311 return \"move%.w %3,%0\";
5316 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5317 ; alignment of structure members is specified.
5319 ; The move is allowed to be odd byte aligned, because that's still faster
5320 ; than an odd byte aligned bit field instruction.
5323 [(set (match_operand:SI 0 "general_operand" "=rm")
5324 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5326 (match_operand:SI 2 "const_int_operand" "n")))]
5327 "TARGET_68020 && TARGET_BITFIELD
5328 && (INTVAL (operands[2]) % 8) == 0
5329 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5333 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5335 return \"move%.l %1,%0\";
5339 [(set (match_operand:SI 0 "general_operand" "=&d")
5340 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5341 (match_operand:SI 2 "const_int_operand" "n")
5342 (match_operand:SI 3 "const_int_operand" "n")))]
5343 "TARGET_68020 && TARGET_BITFIELD
5344 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5345 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5346 && (GET_CODE (operands[1]) == REG
5347 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5350 cc_status.flags |= CC_NOT_NEGATIVE;
5351 if (REG_P (operands[1]))
5353 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5354 return \"bfextu %1{%b3:%b2},%0\";
5358 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5360 output_asm_insn (\"clr%.l %0\", operands);
5361 if (GET_CODE (operands[0]) == MEM)
5362 operands[0] = adjust_address (operands[0],
5363 INTVAL (operands[2]) == 8 ? QImode : HImode,
5364 (32 - INTVAL (operands[1])) / 8);
5366 if (INTVAL (operands[2]) == 8)
5367 return \"move%.b %1,%0\";
5368 return \"move%.w %1,%0\";
5372 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5373 ; alignment of structure members is specified.
5375 ; The move is allowed to be odd byte aligned, because that's still faster
5376 ; than an odd byte aligned bit field instruction.
5379 [(set (match_operand:SI 0 "general_operand" "=rm")
5380 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5382 (match_operand:SI 2 "const_int_operand" "n")))]
5383 "TARGET_68020 && TARGET_BITFIELD
5384 && (INTVAL (operands[2]) % 8) == 0
5385 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5389 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5391 return \"move%.l %1,%0\";
5395 [(set (match_operand:SI 0 "general_operand" "=d")
5396 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5397 (match_operand:SI 2 "const_int_operand" "n")
5398 (match_operand:SI 3 "const_int_operand" "n")))]
5399 "TARGET_68020 && TARGET_BITFIELD
5400 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5401 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5402 && (GET_CODE (operands[1]) == REG
5403 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5406 if (REG_P (operands[1]))
5408 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5409 return \"bfexts %1{%b3:%b2},%0\";
5413 = adjust_address (operands[1],
5414 INTVAL (operands[2]) == 8 ? QImode : HImode,
5415 INTVAL (operands[3]) / 8);
5417 if (INTVAL (operands[2]) == 8)
5418 return \"move%.b %1,%0\;extb%.l %0\";
5419 return \"move%.w %1,%0\;ext%.l %0\";
5422 ;; Bit field instructions, general cases.
5423 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5424 ;; so that its address is reloaded.
5426 (define_expand "extv"
5427 [(set (match_operand:SI 0 "general_operand" "")
5428 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5429 (match_operand:SI 2 "general_operand" "")
5430 (match_operand:SI 3 "general_operand" "")))]
5431 "TARGET_68020 && TARGET_BITFIELD"
5435 [(set (match_operand:SI 0 "general_operand" "=d")
5436 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5437 (match_operand:SI 2 "general_operand" "di")
5438 (match_operand:SI 3 "general_operand" "di")))]
5439 "TARGET_68020 && TARGET_BITFIELD"
5440 "bfexts %1{%b3:%b2},%0")
5442 (define_expand "extzv"
5443 [(set (match_operand:SI 0 "general_operand" "")
5444 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5445 (match_operand:SI 2 "general_operand" "")
5446 (match_operand:SI 3 "general_operand" "")))]
5447 "TARGET_68020 && TARGET_BITFIELD"
5451 [(set (match_operand:SI 0 "general_operand" "=d,d")
5452 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5453 (match_operand:SI 2 "general_operand" "di,di")
5454 (match_operand:SI 3 "general_operand" "di,di")))]
5455 "TARGET_68020 && TARGET_BITFIELD"
5458 if (GET_CODE (operands[2]) == CONST_INT)
5460 if (INTVAL (operands[2]) != 32)
5461 cc_status.flags |= CC_NOT_NEGATIVE;
5467 return \"bfextu %1{%b3:%b2},%0\";
5471 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5472 (match_operand:SI 1 "general_operand" "di")
5473 (match_operand:SI 2 "general_operand" "di"))
5474 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5475 (match_operand 3 "const_int_operand" "n")))]
5476 "TARGET_68020 && TARGET_BITFIELD
5477 && (INTVAL (operands[3]) == -1
5478 || (GET_CODE (operands[1]) == CONST_INT
5479 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5483 return \"bfchg %0{%b2:%b1}\";
5487 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5488 (match_operand:SI 1 "general_operand" "di")
5489 (match_operand:SI 2 "general_operand" "di"))
5491 "TARGET_68020 && TARGET_BITFIELD"
5495 return \"bfclr %0{%b2:%b1}\";
5499 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5500 (match_operand:SI 1 "general_operand" "di")
5501 (match_operand:SI 2 "general_operand" "di"))
5503 "TARGET_68020 && TARGET_BITFIELD"
5507 return \"bfset %0{%b2:%b1}\";
5510 (define_expand "insv"
5511 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5512 (match_operand:SI 1 "general_operand" "")
5513 (match_operand:SI 2 "general_operand" ""))
5514 (match_operand:SI 3 "register_operand" ""))]
5515 "TARGET_68020 && TARGET_BITFIELD"
5519 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5520 (match_operand:SI 1 "general_operand" "di")
5521 (match_operand:SI 2 "general_operand" "di"))
5522 (match_operand:SI 3 "register_operand" "d"))]
5523 "TARGET_68020 && TARGET_BITFIELD"
5524 "bfins %3,%0{%b2:%b1}")
5526 ;; Now recognize bit field insns that operate on registers
5527 ;; (or at least were intended to do so).
5530 [(set (match_operand:SI 0 "general_operand" "=d")
5531 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5532 (match_operand:SI 2 "general_operand" "di")
5533 (match_operand:SI 3 "general_operand" "di")))]
5534 "TARGET_68020 && TARGET_BITFIELD"
5535 "bfexts %1{%b3:%b2},%0")
5538 [(set (match_operand:SI 0 "general_operand" "=d")
5539 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5540 (match_operand:SI 2 "general_operand" "di")
5541 (match_operand:SI 3 "general_operand" "di")))]
5542 "TARGET_68020 && TARGET_BITFIELD"
5545 if (GET_CODE (operands[2]) == CONST_INT)
5547 if (INTVAL (operands[2]) != 32)
5548 cc_status.flags |= CC_NOT_NEGATIVE;
5554 return \"bfextu %1{%b3:%b2},%0\";
5558 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5559 (match_operand:SI 1 "general_operand" "di")
5560 (match_operand:SI 2 "general_operand" "di"))
5562 "TARGET_68020 && TARGET_BITFIELD"
5566 return \"bfclr %0{%b2:%b1}\";
5570 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5571 (match_operand:SI 1 "general_operand" "di")
5572 (match_operand:SI 2 "general_operand" "di"))
5574 "TARGET_68020 && TARGET_BITFIELD"
5578 return \"bfset %0{%b2:%b1}\";
5582 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5583 (match_operand:SI 1 "general_operand" "di")
5584 (match_operand:SI 2 "general_operand" "di"))
5585 (match_operand:SI 3 "register_operand" "d"))]
5586 "TARGET_68020 && TARGET_BITFIELD"
5590 /* These special cases are now recognized by a specific pattern. */
5591 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5592 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5593 return \"move%.w %3,%0\";
5594 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5595 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5596 return \"move%.b %3,%0\";
5598 return \"bfins %3,%0{%b2:%b1}\";
5601 ;; Special patterns for optimizing bit-field instructions.
5605 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5606 (match_operand:SI 1 "const_int_operand" "n")
5607 (match_operand:SI 2 "general_operand" "di")))]
5608 "TARGET_68020 && TARGET_BITFIELD"
5611 if (operands[1] == const1_rtx
5612 && GET_CODE (operands[2]) == CONST_INT)
5614 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5615 return output_btst (operands,
5616 GEN_INT (width - INTVAL (operands[2])),
5617 operands[0], insn, 1000);
5618 /* Pass 1000 as SIGNPOS argument so that btst will
5619 not think we are testing the sign bit for an `and'
5620 and assume that nonzero implies a negative result. */
5622 if (INTVAL (operands[1]) != 32)
5623 cc_status.flags = CC_NOT_NEGATIVE;
5624 return \"bftst %0{%b2:%b1}\";
5628 ;;; now handle the register cases
5631 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5632 (match_operand:SI 1 "const_int_operand" "n")
5633 (match_operand:SI 2 "general_operand" "di")))]
5634 "TARGET_68020 && TARGET_BITFIELD"
5637 if (operands[1] == const1_rtx
5638 && GET_CODE (operands[2]) == CONST_INT)
5640 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5641 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5642 operands[0], insn, 1000);
5643 /* Pass 1000 as SIGNPOS argument so that btst will
5644 not think we are testing the sign bit for an `and'
5645 and assume that nonzero implies a negative result. */
5647 if (INTVAL (operands[1]) != 32)
5648 cc_status.flags = CC_NOT_NEGATIVE;
5649 return \"bftst %0{%b2:%b1}\";
5652 (define_insn "scc0_di"
5653 [(set (match_operand:QI 0 "general_operand" "=dm")
5654 (match_operator 1 "valid_dbcc_comparison_p"
5655 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5659 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5662 (define_insn "scc0_di_5200"
5663 [(set (match_operand:QI 0 "general_operand" "=d")
5664 (match_operator 1 "valid_dbcc_comparison_p"
5665 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5669 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5672 (define_insn "scc_di"
5673 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5674 (match_operator 1 "valid_dbcc_comparison_p"
5675 [(match_operand:DI 2 "general_operand" "ro,r")
5676 (match_operand:DI 3 "general_operand" "r,ro")]))]
5680 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5683 (define_insn "scc_di_5200"
5684 [(set (match_operand:QI 0 "general_operand" "=d,d")
5685 (match_operator 1 "valid_dbcc_comparison_p"
5686 [(match_operand:DI 2 "general_operand" "ro,r")
5687 (match_operand:DI 3 "general_operand" "r,ro")]))]
5691 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5694 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5695 ;; memory, but we cannot allow it to be in memory in case the address
5696 ;; needs to be reloaded.
5698 (define_expand "seq"
5699 [(set (match_operand:QI 0 "register_operand" "")
5700 (eq:QI (cc0) (const_int 0)))]
5704 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5706 m68k_last_compare_had_fp_operands = 0;
5712 [(set (match_operand:QI 0 "register_operand" "=d")
5713 (eq:QI (cc0) (const_int 0)))]
5716 cc_status = cc_prev_status;
5717 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5720 (define_expand "sne"
5721 [(set (match_operand:QI 0 "register_operand" "")
5722 (ne:QI (cc0) (const_int 0)))]
5726 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5728 m68k_last_compare_had_fp_operands = 0;
5734 [(set (match_operand:QI 0 "register_operand" "=d")
5735 (ne:QI (cc0) (const_int 0)))]
5738 cc_status = cc_prev_status;
5739 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5742 (define_expand "sgt"
5743 [(set (match_operand:QI 0 "register_operand" "")
5744 (gt:QI (cc0) (const_int 0)))]
5748 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5750 m68k_last_compare_had_fp_operands = 0;
5756 [(set (match_operand:QI 0 "register_operand" "=d")
5757 (gt:QI (cc0) (const_int 0)))]
5760 cc_status = cc_prev_status;
5761 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5764 (define_expand "sgtu"
5765 [(set (match_operand:QI 0 "register_operand" "")
5766 (gtu:QI (cc0) (const_int 0)))]
5771 [(set (match_operand:QI 0 "register_operand" "=d")
5772 (gtu:QI (cc0) (const_int 0)))]
5775 cc_status = cc_prev_status;
5776 return \"shi %0\"; ")
5778 (define_expand "slt"
5779 [(set (match_operand:QI 0 "register_operand" "")
5780 (lt:QI (cc0) (const_int 0)))]
5784 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5786 m68k_last_compare_had_fp_operands = 0;
5792 [(set (match_operand:QI 0 "register_operand" "=d")
5793 (lt:QI (cc0) (const_int 0)))]
5796 cc_status = cc_prev_status;
5797 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5799 (define_expand "sltu"
5800 [(set (match_operand:QI 0 "register_operand" "")
5801 (ltu:QI (cc0) (const_int 0)))]
5806 [(set (match_operand:QI 0 "register_operand" "=d")
5807 (ltu:QI (cc0) (const_int 0)))]
5810 cc_status = cc_prev_status;
5811 return \"scs %0\"; ")
5813 (define_expand "sge"
5814 [(set (match_operand:QI 0 "register_operand" "")
5815 (ge:QI (cc0) (const_int 0)))]
5819 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5821 m68k_last_compare_had_fp_operands = 0;
5827 [(set (match_operand:QI 0 "register_operand" "=d")
5828 (ge:QI (cc0) (const_int 0)))]
5831 cc_status = cc_prev_status;
5832 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5834 (define_expand "sgeu"
5835 [(set (match_operand:QI 0 "register_operand" "")
5836 (geu:QI (cc0) (const_int 0)))]
5841 [(set (match_operand:QI 0 "register_operand" "=d")
5842 (geu:QI (cc0) (const_int 0)))]
5845 cc_status = cc_prev_status;
5846 return \"scc %0\"; ")
5848 (define_expand "sle"
5849 [(set (match_operand:QI 0 "register_operand" "")
5850 (le:QI (cc0) (const_int 0)))]
5854 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5856 m68k_last_compare_had_fp_operands = 0;
5862 [(set (match_operand:QI 0 "register_operand" "=d")
5863 (le:QI (cc0) (const_int 0)))]
5866 cc_status = cc_prev_status;
5867 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5870 (define_expand "sleu"
5871 [(set (match_operand:QI 0 "register_operand" "")
5872 (leu:QI (cc0) (const_int 0)))]
5877 [(set (match_operand:QI 0 "register_operand" "=d")
5878 (leu:QI (cc0) (const_int 0)))]
5881 cc_status = cc_prev_status;
5882 return \"sls %0\"; ")
5884 ;; Basic conditional jump instructions.
5886 (define_insn "beq0_di"
5888 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5890 (label_ref (match_operand 1 "" ","))
5892 (clobber (match_scratch:SI 2 "=d,d"))]
5897 if (which_alternative == 1)
5899 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5901 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5903 if ((cc_prev_status.value1
5904 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5905 || (cc_prev_status.value2
5906 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5908 cc_status = cc_prev_status;
5910 return \"jbeq %l1\";
5915 if (GET_CODE (operands[0]) == REG)
5916 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5918 operands[3] = adjust_address (operands[0], SImode, 4);
5919 if (! ADDRESS_REG_P (operands[0]))
5921 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5923 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5926 return \"or%.l %0,%2\;jbeq %l1\";
5928 return \"or%.l %0,%2\;jeq %l1\";
5934 return \"or%.l %3,%2\;jbeq %l1\";
5936 return \"or%.l %3,%2\;jeq %l1\";
5941 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5943 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5946 operands[4] = gen_label_rtx();
5947 if (TARGET_68020 || TARGET_5200)
5950 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5952 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5958 #ifdef SGS_CMP_ORDER
5959 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5961 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5964 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5967 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5968 CODE_LABEL_NUMBER (operands[4]));
5972 (define_insn "bne0_di"
5974 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5976 (label_ref (match_operand 1 "" ","))
5978 (clobber (match_scratch:SI 2 "=d,X"))]
5982 if ((cc_prev_status.value1
5983 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5984 || (cc_prev_status.value2
5985 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5987 cc_status = cc_prev_status;
5989 return \"jbne %l1\";
5995 if (GET_CODE (operands[0]) == REG)
5996 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5998 operands[3] = adjust_address (operands[0], SImode, 4);
5999 if (!ADDRESS_REG_P (operands[0]))
6001 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6003 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6006 return \"or%.l %0,%2\;jbne %l1\";
6008 return \"or%.l %0,%2\;jne %l1\";
6014 return \"or%.l %3,%2\;jbne %l1\";
6016 return \"or%.l %3,%2\;jne %l1\";
6021 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6023 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6026 if (TARGET_68020 || TARGET_5200)
6029 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6031 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6037 #ifdef SGS_CMP_ORDER
6038 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6040 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6043 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6048 (define_insn "bge0_di"
6050 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6052 (label_ref (match_operand 1 "" ""))
6057 if ((cc_prev_status.value1
6058 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6059 || (cc_prev_status.value2
6060 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6062 cc_status = cc_prev_status;
6063 if (cc_status.flags & CC_REVERSED)
6066 return \"jble %l1\";
6074 return \"jbpl %l1\";
6081 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6082 output_asm_insn(\"tst%.l %0\", operands);
6085 /* On an address reg, cmpw may replace cmpl. */
6086 #ifdef SGS_CMP_ORDER
6087 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6089 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6094 return \"jbpl %l1\";
6100 (define_insn "blt0_di"
6102 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6104 (label_ref (match_operand 1 "" ""))
6109 if ((cc_prev_status.value1
6110 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6111 || (cc_prev_status.value2
6112 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6114 cc_status = cc_prev_status;
6115 if (cc_status.flags & CC_REVERSED)
6118 return \"jbgt %l1\";
6126 return \"jbmi %l1\";
6133 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6134 output_asm_insn(\"tst%.l %0\", operands);
6137 /* On an address reg, cmpw may replace cmpl. */
6138 #ifdef SGS_CMP_ORDER
6139 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6141 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6146 return \"jbmi %l1\";
6154 (if_then_else (eq (cc0)
6156 (label_ref (match_operand 0 "" ""))
6162 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6164 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6170 (if_then_else (ne (cc0)
6172 (label_ref (match_operand 0 "" ""))
6178 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6180 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6186 (if_then_else (gt (cc0)
6188 (label_ref (match_operand 0 "" ""))
6193 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6195 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6201 (if_then_else (gtu (cc0)
6203 (label_ref (match_operand 0 "" ""))
6208 return \"jbhi %l0\";
6216 (if_then_else (lt (cc0)
6218 (label_ref (match_operand 0 "" ""))
6223 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6225 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6231 (if_then_else (ltu (cc0)
6233 (label_ref (match_operand 0 "" ""))
6238 return \"jbcs %l0\";
6246 (if_then_else (ge (cc0)
6248 (label_ref (match_operand 0 "" ""))
6253 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6255 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6261 (if_then_else (geu (cc0)
6263 (label_ref (match_operand 0 "" ""))
6268 return \"jbcc %l0\";
6276 (if_then_else (le (cc0)
6278 (label_ref (match_operand 0 "" ""))
6283 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6285 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6291 (if_then_else (leu (cc0)
6293 (label_ref (match_operand 0 "" ""))
6298 return \"jbls %l0\";
6304 ;; Negated conditional jump instructions.
6308 (if_then_else (eq (cc0)
6311 (label_ref (match_operand 0 "" ""))))]
6316 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6318 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6324 (if_then_else (ne (cc0)
6327 (label_ref (match_operand 0 "" ""))))]
6332 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6334 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6340 (if_then_else (gt (cc0)
6343 (label_ref (match_operand 0 "" ""))))]
6347 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6349 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6355 (if_then_else (gtu (cc0)
6358 (label_ref (match_operand 0 "" ""))))]
6362 return \"jbls %l0\";
6370 (if_then_else (lt (cc0)
6373 (label_ref (match_operand 0 "" ""))))]
6377 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6379 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6385 (if_then_else (ltu (cc0)
6388 (label_ref (match_operand 0 "" ""))))]
6392 return \"jbcc %l0\";
6400 (if_then_else (ge (cc0)
6403 (label_ref (match_operand 0 "" ""))))]
6407 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6409 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6415 (if_then_else (geu (cc0)
6418 (label_ref (match_operand 0 "" ""))))]
6422 return \"jbcs %l0\";
6430 (if_then_else (le (cc0)
6433 (label_ref (match_operand 0 "" ""))))]
6437 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6439 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6445 (if_then_else (leu (cc0)
6448 (label_ref (match_operand 0 "" ""))))]
6452 return \"jbhi %l0\";
6458 ;; Unconditional and other jump instructions
6461 (label_ref (match_operand 0 "" "")))]
6465 return \"jbra %l0\";
6471 ;; We support two different ways of handling dispatch tables.
6472 ;; The NeXT uses absolute tables, and other machines use relative.
6473 ;; This define_expand can generate either kind.
6474 (define_expand "tablejump"
6475 [(parallel [(set (pc) (match_operand 0 "" ""))
6476 (use (label_ref (match_operand 1 "" "")))])]
6480 #ifdef CASE_VECTOR_PC_RELATIVE
6481 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6482 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6486 ;; Jump to variable address from dispatch table of absolute addresses.
6488 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6489 (use (label_ref (match_operand 1 "" "")))]
6493 return \"jmp (%0)\";
6499 ;; Jump to variable address from dispatch table of relative addresses.
6503 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6504 (use (label_ref (match_operand 1 "" "")))]
6507 #ifdef ASM_RETURN_CASE_JUMP
6508 ASM_RETURN_CASE_JUMP;
6511 #ifdef ASM_OUTPUT_CASE_LABEL
6513 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6515 return \"jmp 6(%%pc,%0.w)\";
6520 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6522 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6523 #endif /* end !CRDS */
6528 return \"jmp 2(pc,%0.w)\";
6530 return \"jmp 2(%%pc,%0.w)\";
6531 #endif /* end !CRDS */
6538 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6540 return \"extl %0\;jmp pc@(2,%0:l)\";
6546 return \"jmp (2,pc,%0.w)\";
6548 return \"jmp pc@(2,%0:w)\";
6555 ;; Decrement-and-branch insns.
6559 (ne (match_operand:HI 0 "general_operand" "+d*g")
6561 (label_ref (match_operand 1 "" ""))
6564 (plus:HI (match_dup 0)
6570 if (DATA_REG_P (operands[0]))
6571 return \"dbra %0,%l1\";
6572 if (GET_CODE (operands[0]) == MEM)
6576 return \"sub%.w %#1,%0\;jbcc %l1\";
6578 return \"subq%.w %#1,%0\;jbcc %l1\";
6580 #else /* not MOTOROLA */
6581 return \"subqw %#1,%0\;jcc %l1\";
6585 #ifdef SGS_CMP_ORDER
6587 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6589 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6591 #else /* not SGS_CMP_ORDER */
6592 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6594 #else /* not MOTOROLA */
6595 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6602 (ne (match_operand:SI 0 "general_operand" "+d*g")
6604 (label_ref (match_operand 1 "" ""))
6607 (plus:SI (match_dup 0)
6615 if (DATA_REG_P (operands[0]))
6616 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6617 if (GET_CODE (operands[0]) == MEM)
6618 return \"sub%.l %#1,%0\;jbcc %l1\";
6620 if (DATA_REG_P (operands[0]))
6621 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6622 if (GET_CODE (operands[0]) == MEM)
6623 return \"subq%.l %#1,%0\;jbcc %l1\";
6624 #endif /* NO_ADDSUB_Q */
6625 #ifdef SGS_CMP_ORDER
6627 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6629 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6631 #else /* not SGS_CMP_ORDER */
6632 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6633 #endif /* not SGS_CMP_ORDER */
6634 #else /* not MOTOROLA */
6635 if (DATA_REG_P (operands[0]))
6636 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6637 if (GET_CODE (operands[0]) == MEM)
6638 return \"subql %#1,%0\;jcc %l1\";
6639 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6640 #endif /* not MOTOROLA */
6643 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6648 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6651 (label_ref (match_operand 1 "" ""))
6654 (plus:HI (match_dup 0)
6656 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6662 if (DATA_REG_P (operands[0]))
6663 return \"dbra %0,%l1\";
6664 if (GET_CODE (operands[0]) == MEM)
6665 return \"sub%.w %#1,%0\;jbcc %l1\";
6667 if (DATA_REG_P (operands[0]))
6668 return \"dbra %0,%l1\";
6669 if (GET_CODE (operands[0]) == MEM)
6670 return \"subq%.w %#1,%0\;jbcc %l1\";
6672 #ifdef SGS_CMP_ORDER
6674 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6676 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6678 #else /* not SGS_CMP_ORDER */
6679 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6680 #endif /* not SGS_CMP_ORDER */
6681 #else /* not MOTOROLA */
6682 if (DATA_REG_P (operands[0]))
6683 return \"dbra %0,%l1\";
6684 if (GET_CODE (operands[0]) == MEM)
6685 return \"subqw %#1,%0\;jcc %l1\";
6686 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6687 #endif /* not MOTOROLA */
6690 (define_expand "decrement_and_branch_until_zero"
6691 [(parallel [(set (pc)
6693 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6696 (label_ref (match_operand 1 "" ""))
6699 (plus:SI (match_dup 0)
6707 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6710 (label_ref (match_operand 1 "" ""))
6713 (plus:SI (match_dup 0)
6715 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6721 if (DATA_REG_P (operands[0]))
6722 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6723 if (GET_CODE (operands[0]) == MEM)
6724 return \"sub%.l %#1,%0\;jbcc %l1\";
6726 if (DATA_REG_P (operands[0]))
6727 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6728 if (GET_CODE (operands[0]) == MEM)
6729 return \"subq%.l %#1,%0\;jbcc %l1\";
6731 #ifdef SGS_CMP_ORDER
6733 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6735 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6737 #else /* not SGS_CMP_ORDER */
6738 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6739 #endif /* not SGS_CMP_ORDER */
6740 #else /* not MOTOROLA */
6741 if (DATA_REG_P (operands[0]))
6742 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6743 if (GET_CODE (operands[0]) == MEM)
6744 return \"subql %#1,%0\;jcc %l1\";
6745 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6746 #endif /* not MOTOROLA */
6750 ;; For PIC calls, in order to be able to support
6751 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6752 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6754 ;; PIC calls are handled by loading the address of the function into a
6755 ;; register (via movsi), then emitting a register indirect call using
6756 ;; the "jsr" function call syntax.
6758 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6759 ;; operand to the jbsr statement to indicate that this call should
6760 ;; go through the PLT (why? because this is the way that Sun does it).
6762 ;; We have different patterns for PIC calls and non-PIC calls. The
6763 ;; different patterns are only used to choose the right syntax.
6765 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6766 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6767 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6768 ;; section at link time. However, all global objects reference are still
6769 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6770 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6771 ;; We need to have a way to differentiate these two different operands.
6773 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6774 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6775 ;; to be changed to recognize function calls symbol_ref operand as a valid
6776 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6777 ;; avoid the compiler to load this symbol_ref operand into a register.
6778 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6779 ;; since the value is a PC relative offset, not a real address.
6781 ;; All global objects are treated in the similar way as in SUN3. The only
6782 ;; difference is: on m68k svr4, the reference of such global object needs
6783 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6784 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6787 ;; Call subroutine with no return value.
6788 (define_expand "call"
6789 [(call (match_operand:QI 0 "memory_operand" "")
6790 (match_operand:SI 1 "general_operand" ""))]
6791 ;; Operand 1 not really used on the m68000.
6796 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6797 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6800 ;; This is a normal call sequence.
6802 [(call (match_operand:QI 0 "memory_operand" "o")
6803 (match_operand:SI 1 "general_operand" "g"))]
6804 ;; Operand 1 not really used on the m68000.
6808 #if defined (MOTOROLA) && !defined (USE_GAS)
6810 if (GET_CODE (operands[0]) == MEM
6811 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6820 ;; This is a PIC call sequence.
6822 [(call (match_operand:QI 0 "memory_operand" "o")
6823 (match_operand:SI 1 "general_operand" "g"))]
6824 ;; Operand 1 not really used on the m68000.
6828 if (GET_CODE (operands[0]) == MEM
6829 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6831 if (TARGET_PCREL) return \"bsr.l %o0\";
6834 return \"bsr.l %0\";
6837 return \"bsr.l %0@PLTPC\";
6839 return \"bsr %0@PLTPC\";
6844 return \"bsr.l %0\";
6846 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6847 GAS just plain ignores it. FIXME: not anymore, gas doesnt! */
6848 return \"jbsr %0,a1\";
6855 ;; Call subroutine, returning value in operand 0
6856 ;; (which must be a hard register).
6857 ;; See comments before "call" regarding PIC calls.
6858 (define_expand "call_value"
6859 [(set (match_operand 0 "" "")
6860 (call (match_operand:QI 1 "memory_operand" "")
6861 (match_operand:SI 2 "general_operand" "")))]
6862 ;; Operand 2 not really used on the m68000.
6866 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6867 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6870 ;; This is a normal call_value
6872 [(set (match_operand 0 "" "=rf")
6873 (call (match_operand:QI 1 "memory_operand" "o")
6874 (match_operand:SI 2 "general_operand" "g")))]
6875 ;; Operand 2 not really used on the m68000.
6878 #if defined (MOTOROLA) && !defined (USE_GAS)
6880 if (GET_CODE (operands[1]) == MEM
6881 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6890 ;; This is a PIC call_value
6892 [(set (match_operand 0 "" "=rf")
6893 (call (match_operand:QI 1 "memory_operand" "o")
6894 (match_operand:SI 2 "general_operand" "g")))]
6895 ;; Operand 2 not really used on the m68000.
6898 if (GET_CODE (operands[1]) == MEM
6899 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6901 if (TARGET_PCREL) return \"bsr.l %o1\";
6904 return \"bsr.l %1\";
6907 return \"bsr.l %1@PLTPC\";
6909 return \"bsr %1@PLTPC\";
6914 return \"bsr.l %1\";
6916 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6917 GAS just plain ignores it. FIXME: Not anymore, gas doesnt! */
6918 return \"jbsr %1,a1\";
6925 ;; Call subroutine returning any type.
6927 (define_expand "untyped_call"
6928 [(parallel [(call (match_operand 0 "" "")
6930 (match_operand 1 "" "")
6931 (match_operand 2 "" "")])]
6932 "NEEDS_UNTYPED_CALL"
6937 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6939 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6941 rtx set = XVECEXP (operands[2], 0, i);
6942 emit_move_insn (SET_DEST (set), SET_SRC (set));
6945 /* The optimizer does not know that the call sets the function value
6946 registers we stored in the result block. We avoid problems by
6947 claiming that all hard registers are used and clobbered at this
6949 emit_insn (gen_blockage ());
6954 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6955 ;; all of memory. This blocks insns from being moved across this point.
6957 (define_insn "blockage"
6958 [(unspec_volatile [(const_int 0)] 0)]
6967 (define_insn "probe"
6972 operands[0] = plus_constant (stack_pointer_rtx, NEED_PROBE);
6973 return \"tstl %a0\";
6976 ;; Used for frameless functions which save no regs and allocate no locals.
6977 (define_insn "return"
6982 if (current_function_pops_args == 0)
6984 operands[0] = GEN_INT (current_function_pops_args);
6988 (define_insn "indirect_jump"
6989 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6993 ;; This should not be used unless the add/sub insns can't be.
6996 [(set (match_operand:SI 0 "general_operand" "=a")
6997 (match_operand:QI 1 "address_operand" "p"))]
7002 /* Recognize an insn that refers to a table of offsets. Such an insn will
7003 need to refer to a label on the insn. So output one. Use the
7004 label-number of the table of offsets to generate this label. This code,
7005 and similar code above, assumes that there will be at most one reference
7007 if (GET_CODE (operands[1]) == PLUS
7008 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
7009 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
7011 rtx labelref = XEXP (operands[1], 1);
7012 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
7014 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7015 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7017 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7018 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7019 #endif /* not SGS */
7020 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7021 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7022 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7023 #ifdef SGS_SWITCH_TABLES
7024 /* Set flag saying we need to define the symbol
7025 LD%n (with value L%n-LI%n) at the end of the switch table. */
7026 switch_table_difference_label_flag = 1;
7027 #endif /* SGS_SWITCH_TABLES */
7028 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7030 #endif /* SGS_NO_LI */
7032 return \"lea %a1,%0\";
7035 ;; This is the first machine-dependent peephole optimization.
7036 ;; It is useful when a floating value is returned from a function call
7037 ;; and then is moved into an FP register.
7038 ;; But it is mainly intended to test the support for these optimizations.
7041 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7042 (set (match_operand:DF 0 "register_operand" "=f")
7043 (match_operand:DF 1 "register_operand" "ad"))]
7044 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7048 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7049 output_asm_insn (\"move%.l %1,%@\", xoperands);
7050 output_asm_insn (\"move%.l %1,%-\", operands);
7051 return \"fmove%.d %+,%0\";
7055 ;; Optimize a stack-adjust followed by a push of an argument.
7056 ;; This is said to happen frequently with -msoft-float
7057 ;; when there are consecutive library calls.
7060 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7061 (match_operand:SI 0 "const_int_operand" "n")))
7062 (set (match_operand:SF 1 "push_operand" "=m")
7063 (match_operand:SF 2 "general_operand" "rmfF"))]
7064 "INTVAL (operands[0]) >= 4
7065 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7068 if (INTVAL (operands[0]) > 4)
7071 xoperands[0] = stack_pointer_rtx;
7072 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7074 if (INTVAL (xoperands[1]) <= 8)
7077 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7079 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7081 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7083 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7084 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7088 if (INTVAL (xoperands[1]) <= 0x7FFF)
7091 output_asm_insn (\"add%.w %1,%0\", xoperands);
7094 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7096 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7100 output_asm_insn (\"add%.l %1,%0\", xoperands);
7102 if (FP_REG_P (operands[2]))
7103 return \"fmove%.s %2,%@\";
7104 return \"move%.l %2,%@\";
7107 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7110 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7111 (match_operand:SI 0 "const_int_operand" "n")))
7112 (set (match_operand:SI 1 "push_operand" "=m")
7113 (match_operand:SI 2 "general_operand" "g"))]
7114 "INTVAL (operands[0]) >= 4
7115 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7118 if (INTVAL (operands[0]) > 4)
7121 xoperands[0] = stack_pointer_rtx;
7122 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7124 if (INTVAL (xoperands[1]) <= 8)
7127 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7129 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7131 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7133 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7134 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7138 if (INTVAL (xoperands[1]) <= 0x7FFF)
7141 output_asm_insn (\"add%.w %1,%0\", xoperands);
7145 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7147 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7152 output_asm_insn (\"add%.l %1,%0\", xoperands);
7154 if (operands[2] == const0_rtx)
7155 return \"clr%.l %@\";
7156 return \"move%.l %2,%@\";
7159 ;; Speed up pushing a single byte but leaving four bytes of space.
7162 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7163 (match_operand:QI 1 "general_operand" "dami"))
7164 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7165 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7170 if (GET_CODE (operands[1]) == REG)
7171 return \"move%.l %1,%-\";
7173 xoperands[1] = operands[1];
7175 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
7176 xoperands[3] = stack_pointer_rtx;
7178 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7180 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7185 [(set (match_operand:SI 0 "register_operand" "=d")
7187 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7188 (match_operand:HI 1 "general_operand" "rmn"))]
7189 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7192 if (GET_CODE (operands[1]) == CONST_INT)
7194 if (operands[1] == const0_rtx
7195 && (DATA_REG_P (operands[0])
7196 || GET_CODE (operands[0]) == MEM)
7197 /* clr insns on 68000 read before writing.
7198 This isn't so on the 68010, but we have no TARGET_68010. */
7199 && ((TARGET_68020 || TARGET_5200)
7200 || !(GET_CODE (operands[0]) == MEM
7201 && MEM_VOLATILE_P (operands[0]))))
7202 return \"clr%.w %0\";
7204 return \"move%.w %1,%0\";
7212 ;; jCC label ; abnormal loop termination
7213 ;; dbra dN, loop ; normal loop termination
7221 ;; Which moves the jCC condition outside the inner loop for free.
7224 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7225 [(cc0) (const_int 0)])
7226 (label_ref (match_operand 2 "" ""))
7231 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7234 (label_ref (match_operand 1 "" ""))
7237 (plus:HI (match_dup 0)
7239 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7243 output_dbcc_and_branch (operands);
7248 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7249 [(cc0) (const_int 0)])
7250 (label_ref (match_operand 2 "" ""))
7255 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7258 (label_ref (match_operand 1 "" ""))
7261 (plus:SI (match_dup 0)
7263 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7267 output_dbcc_and_branch (operands);
7272 ;; FPA multiply and add.
7274 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7275 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7276 (match_operand:DF 2 "general_operand" "xH,y,y"))
7277 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7280 fpma%.d %1,%w2,%w3,%0
7281 fpma%.d %x1,%x2,%x3,%0
7282 fpma%.d %x1,%x2,%x3,%0")
7285 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7286 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7287 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7288 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7291 fpma%.s %1,%w2,%w3,%0
7293 fpma%.s %1,%2,%3,%0")
7295 ;; FPA Multiply and subtract
7297 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7298 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7299 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7300 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7303 fpms%.d %3,%w2,%w1,%0
7304 fpms%.d %x3,%2,%x1,%0
7305 fpms%.d %x3,%2,%x1,%0")
7308 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7309 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7310 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7311 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7314 fpms%.s %3,%w2,%w1,%0
7316 fpms%.s %3,%2,%1,%0")
7319 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7320 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7321 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7322 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7325 fpmr%.d %2,%w1,%w3,%0
7326 fpmr%.d %x2,%1,%x3,%0
7327 fpmr%.d %x2,%1,%x3,%0")
7330 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7331 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7332 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7333 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7336 fpmr%.s %2,%w1,%w3,%0
7337 fpmr%.s %x2,%1,%x3,%0
7338 fpmr%.s %x2,%1,%x3,%0")
7340 ;; FPA Add and multiply
7342 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7343 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7344 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7345 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7348 fpam%.d %2,%w1,%w3,%0
7349 fpam%.d %x2,%1,%x3,%0
7350 fpam%.d %x2,%1,%x3,%0")
7353 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7354 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7355 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7356 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7359 fpam%.s %2,%w1,%w3,%0
7360 fpam%.s %x2,%1,%x3,%0
7361 fpam%.s %x2,%1,%x3,%0")
7363 ;;FPA Subtract and multiply
7365 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7366 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7367 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7368 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7371 fpsm%.d %2,%w1,%w3,%0
7372 fpsm%.d %x2,%1,%x3,%0
7373 fpsm%.d %x2,%1,%x3,%0")
7376 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7377 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7378 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7379 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7382 fpsm%.d %3,%w2,%w1,%0
7383 fpsm%.d %x3,%2,%x1,%0
7384 fpsm%.d %x3,%2,%x1,%0")
7387 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7388 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7389 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7390 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7393 fpsm%.s %2,%w1,%w3,%0
7394 fpsm%.s %x2,%1,%x3,%0
7395 fpsm%.s %x2,%1,%x3,%0")
7398 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7399 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7400 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7401 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7404 fpsm%.s %3,%w2,%w1,%0
7405 fpsm%.s %x3,%2,%x1,%0
7406 fpsm%.s %x3,%2,%x1,%0")
7408 (define_expand "tstxf"
7410 (match_operand:XF 0 "nonimmediate_operand" ""))]
7412 "m68k_last_compare_had_fp_operands = 1;")
7416 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7420 cc_status.flags = CC_IN_68881;
7421 return \"ftst%.x %0\";
7424 (define_expand "cmpxf"
7426 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7427 (match_operand:XF 1 "nonimmediate_operand" "")))]
7429 "m68k_last_compare_had_fp_operands = 1;")
7433 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7434 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7438 cc_status.flags = CC_IN_68881;
7439 #ifdef SGS_CMP_ORDER
7440 if (REG_P (operands[0]))
7442 if (REG_P (operands[1]))
7443 return \"fcmp%.x %0,%1\";
7445 return \"fcmp%.x %0,%f1\";
7447 cc_status.flags |= CC_REVERSED;
7448 return \"fcmp%.x %1,%f0\";
7450 if (REG_P (operands[0]))
7452 if (REG_P (operands[1]))
7453 return \"fcmp%.x %1,%0\";
7455 return \"fcmp%.x %f1,%0\";
7457 cc_status.flags |= CC_REVERSED;
7458 return \"fcmp%.x %f0,%1\";
7462 (define_insn "extendsfxf2"
7463 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7464 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7468 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7470 if (REGNO (operands[0]) == REGNO (operands[1]))
7472 /* Extending float to double in an fp-reg is a no-op.
7473 NOTICE_UPDATE_CC has already assumed that the
7474 cc will be set. So cancel what it did. */
7475 cc_status = cc_prev_status;
7478 return \"f%$move%.x %1,%0\";
7480 if (FP_REG_P (operands[0]))
7482 if (FP_REG_P (operands[1]))
7483 return \"f%$move%.x %1,%0\";
7484 else if (ADDRESS_REG_P (operands[1]))
7485 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7486 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7487 return output_move_const_single (operands);
7488 return \"f%$move%.s %f1,%0\";
7490 return \"fmove%.x %f1,%0\";
7494 (define_insn "extenddfxf2"
7495 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7497 (match_operand:DF 1 "general_operand" "f,rmE")))]
7501 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7503 if (REGNO (operands[0]) == REGNO (operands[1]))
7505 /* Extending float to double in an fp-reg is a no-op.
7506 NOTICE_UPDATE_CC has already assumed that the
7507 cc will be set. So cancel what it did. */
7508 cc_status = cc_prev_status;
7511 return \"fmove%.x %1,%0\";
7513 if (FP_REG_P (operands[0]))
7515 if (REG_P (operands[1]))
7518 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7519 output_asm_insn (\"move%.l %1,%-\", xoperands);
7520 output_asm_insn (\"move%.l %1,%-\", operands);
7521 return \"f%&move%.d %+,%0\";
7523 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7524 return output_move_const_double (operands);
7525 return \"f%&move%.d %f1,%0\";
7527 return \"fmove%.x %f1,%0\";
7530 (define_insn "truncxfdf2"
7531 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7533 (match_operand:XF 1 "general_operand" "f,f")))]
7537 if (REG_P (operands[0]))
7539 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7540 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7541 return \"move%.l %+,%0\";
7543 return \"fmove%.d %f1,%0\";
7546 (define_insn "truncxfsf2"
7547 [(set (match_operand:SF 0 "general_operand" "=dm")
7549 (match_operand:XF 1 "general_operand" "f")))]
7553 (define_insn "floatsixf2"
7554 [(set (match_operand:XF 0 "general_operand" "=f")
7555 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7559 (define_insn "floathixf2"
7560 [(set (match_operand:XF 0 "general_operand" "=f")
7561 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7565 (define_insn "floatqixf2"
7566 [(set (match_operand:XF 0 "general_operand" "=f")
7567 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7571 (define_insn "ftruncxf2"
7572 [(set (match_operand:XF 0 "general_operand" "=f")
7573 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7577 if (FP_REG_P (operands[1]))
7578 return \"fintrz%.x %f1,%0\";
7579 return \"fintrz%.x %f1,%0\";
7582 (define_insn "fixxfqi2"
7583 [(set (match_operand:QI 0 "general_operand" "=dm")
7584 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7588 (define_insn "fixxfhi2"
7589 [(set (match_operand:HI 0 "general_operand" "=dm")
7590 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7594 (define_insn "fixxfsi2"
7595 [(set (match_operand:SI 0 "general_operand" "=dm")
7596 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7601 [(set (match_operand:XF 0 "general_operand" "=f")
7602 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7603 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7608 [(set (match_operand:XF 0 "general_operand" "=f")
7609 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7610 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7615 [(set (match_operand:XF 0 "general_operand" "=f")
7616 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7617 (match_operand:XF 1 "general_operand" "0")))]
7621 (define_insn "addxf3"
7622 [(set (match_operand:XF 0 "general_operand" "=f")
7623 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7624 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7628 if (REG_P (operands[2]))
7629 return \"fadd%.x %2,%0\";
7630 return \"fadd%.x %f2,%0\";
7634 [(set (match_operand:XF 0 "general_operand" "=f")
7635 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7636 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7641 [(set (match_operand:XF 0 "general_operand" "=f")
7642 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7643 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7648 [(set (match_operand:XF 0 "general_operand" "=f")
7649 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7650 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7654 (define_insn "subxf3"
7655 [(set (match_operand:XF 0 "general_operand" "=f")
7656 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7657 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7661 if (REG_P (operands[2]))
7662 return \"fsub%.x %2,%0\";
7663 return \"fsub%.x %f2,%0\";
7667 [(set (match_operand:XF 0 "general_operand" "=f")
7668 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7669 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7674 [(set (match_operand:XF 0 "general_operand" "=f")
7675 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7676 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7681 [(set (match_operand:XF 0 "general_operand" "=f")
7682 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7683 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7687 (define_insn "mulxf3"
7688 [(set (match_operand:XF 0 "general_operand" "=f")
7689 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7690 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7694 if (REG_P (operands[2]))
7695 return \"fmul%.x %2,%0\";
7696 return \"fmul%.x %f2,%0\";
7700 [(set (match_operand:XF 0 "general_operand" "=f")
7701 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7702 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7707 [(set (match_operand:XF 0 "general_operand" "=f")
7708 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7709 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7714 [(set (match_operand:XF 0 "general_operand" "=f")
7715 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7716 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7720 (define_insn "divxf3"
7721 [(set (match_operand:XF 0 "general_operand" "=f")
7722 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7723 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7727 if (REG_P (operands[2]))
7728 return \"fdiv%.x %2,%0\";
7729 return \"fdiv%.x %f2,%0\";
7732 (define_expand "negxf2"
7733 [(set (match_operand:XF 0 "general_operand" "")
7734 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7738 /* ??? There isn't an FPA define_insn so we could handle it here too.
7739 For now we don't (paranoia). */
7747 target = operand_subword (operands[0], 0, 1, XFmode);
7748 result = expand_binop (SImode, xor_optab,
7749 operand_subword_force (operands[1], 0, XFmode),
7750 GEN_INT (0x80000000), target, 0, OPTAB_WIDEN);
7754 if (result != target)
7755 emit_move_insn (result, target);
7757 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7758 operand_subword_force (operands[1], 1, XFmode));
7759 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7760 operand_subword_force (operands[1], 2, XFmode));
7762 insns = get_insns ();
7765 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7770 (define_insn "negxf2_68881"
7771 [(set (match_operand:XF 0 "general_operand" "=f")
7772 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7776 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7777 return \"fneg%.x %1,%0\";
7778 return \"fneg%.x %f1,%0\";
7781 (define_expand "absxf2"
7782 [(set (match_operand:XF 0 "general_operand" "")
7783 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7787 /* ??? There isn't an FPA define_insn so we could handle it here too.
7788 For now we don't (paranoia). */
7796 target = operand_subword (operands[0], 0, 1, XFmode);
7797 result = expand_binop (SImode, and_optab,
7798 operand_subword_force (operands[1], 0, XFmode),
7799 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
7803 if (result != target)
7804 emit_move_insn (result, target);
7806 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7807 operand_subword_force (operands[1], 1, XFmode));
7808 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7809 operand_subword_force (operands[1], 2, XFmode));
7811 insns = get_insns ();
7814 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7819 (define_insn "absxf2_68881"
7820 [(set (match_operand:XF 0 "general_operand" "=f")
7821 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7825 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7826 return \"fabs%.x %1,%0\";
7827 return \"fabs%.x %f1,%0\";
7830 (define_insn "sqrtxf2"
7831 [(set (match_operand:XF 0 "general_operand" "=f")
7832 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7836 (define_insn "sinsf2"
7837 [(set (match_operand:SF 0 "general_operand" "=f")
7838 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7839 "TARGET_68881 && flag_unsafe_math_optimizations"
7842 if (FP_REG_P (operands[1]))
7843 return \"fsin%.x %1,%0\";
7845 return \"fsin%.s %1,%0\";
7848 (define_insn "sindf2"
7849 [(set (match_operand:DF 0 "general_operand" "=f")
7850 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7851 "TARGET_68881 && flag_unsafe_math_optimizations"
7854 if (FP_REG_P (operands[1]))
7855 return \"fsin%.x %1,%0\";
7857 return \"fsin%.d %1,%0\";
7860 (define_insn "sinxf2"
7861 [(set (match_operand:XF 0 "general_operand" "=f")
7862 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7863 "TARGET_68881 && flag_unsafe_math_optimizations"
7866 (define_insn "cossf2"
7867 [(set (match_operand:SF 0 "general_operand" "=f")
7868 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7869 "TARGET_68881 && flag_unsafe_math_optimizations"
7872 if (FP_REG_P (operands[1]))
7873 return \"fcos%.x %1,%0\";
7875 return \"fcos%.s %1,%0\";
7878 (define_insn "cosdf2"
7879 [(set (match_operand:DF 0 "general_operand" "=f")
7880 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7881 "TARGET_68881 && flag_unsafe_math_optimizations"
7884 if (FP_REG_P (operands[1]))
7885 return \"fcos%.x %1,%0\";
7887 return \"fcos%.d %1,%0\";
7890 (define_insn "cosxf2"
7891 [(set (match_operand:XF 0 "general_operand" "=f")
7892 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7893 "TARGET_68881 && flag_unsafe_math_optimizations"
7897 [(trap_if (const_int -1) (const_int 7))]
7901 (define_insn "conditional_trap"
7902 [(trap_if (match_operator 0 "valid_dbcc_comparison_p"
7903 [(cc0) (const_int 0)])
7904 (match_operand:SI 1 "const_int_operand" "I"))]
7905 "TARGET_68020 && ! flags_in_68881 ()"
7908 switch (GET_CODE (operands[0]))
7910 case EQ: return \"trapeq\";
7911 case NE: return \"trapne\";
7912 case GT: return \"trapgt\";
7913 case GTU: return \"traphi\";
7914 case LT: return \"traplt\";
7915 case LTU: return \"trapcs\";
7916 case GE: return \"trapge\";
7917 case GEU: return \"trapcc\";
7918 case LE: return \"traple\";
7919 case LEU: return \"trapls\";