1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93-98, 1999 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
540 if (ADDRESS_REG_P (operands[0])
541 && GET_CODE (operands[1]) == CONST_INT
542 && INTVAL (operands[1]) < 0x8000
543 && INTVAL (operands[1]) >= -0x8000)
546 return \"cmp%.w %0,%1\";
548 return \"cmp%.w %1,%0\";
552 return \"cmp%.l %d0,%d1\";
554 return \"cmp%.l %d1,%d0\";
560 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
561 (match_operand:SI 1 "general_operand" "r,mrKs")))]
565 if (REG_P (operands[1])
566 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
567 { cc_status.flags |= CC_REVERSED;
569 return \"cmp%.l %d1,%d0\";
571 return \"cmp%.l %d0,%d1\";
575 return \"cmp%.l %d0,%d1\";
577 return \"cmp%.l %d1,%d0\";
581 (define_expand "cmphi"
583 (compare (match_operand:HI 0 "nonimmediate_operand" "")
584 (match_operand:HI 1 "general_operand" "")))]
586 "m68k_last_compare_had_fp_operands = 0;")
590 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
591 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
595 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
597 return \"cmpm%.w %0,%1\";
599 return \"cmpm%.w %1,%0\";
601 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
603 { cc_status.flags |= CC_REVERSED;
605 return \"cmp%.w %d1,%d0\";
607 return \"cmp%.w %d0,%d1\";
611 return \"cmp%.w %d0,%d1\";
613 return \"cmp%.w %d1,%d0\";
617 (define_expand "cmpqi"
619 (compare (match_operand:QI 0 "nonimmediate_operand" "")
620 (match_operand:QI 1 "general_operand" "")))]
622 "m68k_last_compare_had_fp_operands = 0;")
626 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
627 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
631 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
633 return \"cmpm%.b %0,%1\";
635 return \"cmpm%.b %1,%0\";
637 if (REG_P (operands[1])
638 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
639 { cc_status.flags |= CC_REVERSED;
641 return \"cmp%.b %d1,%d0\";
643 return \"cmp%.b %d0,%d1\";
647 return \"cmp%.b %d0,%d1\";
649 return \"cmp%.b %d1,%d0\";
653 (define_expand "cmpdf"
655 (compare (match_operand:DF 0 "general_operand" "")
656 (match_operand:DF 1 "general_operand" "")))]
657 "TARGET_68881 || TARGET_FPA"
660 m68k_last_compare_had_fp_operands = 1;
663 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
668 (define_insn "cmpdf_fpa"
670 (compare (match_operand:DF 0 "general_operand" "x,y")
671 (match_operand:DF 1 "general_operand" "xH,rmF")))
672 (clobber (match_scratch:SI 2 "=d,d"))]
674 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
678 (compare (match_operand:DF 0 "general_operand" "f,mG")
679 (match_operand:DF 1 "general_operand" "fmG,f")))]
683 cc_status.flags = CC_IN_68881;
685 if (REG_P (operands[0]))
687 if (REG_P (operands[1]))
688 return \"fcmp%.x %0,%1\";
690 return \"fcmp%.d %0,%f1\";
692 cc_status.flags |= CC_REVERSED;
693 return \"fcmp%.d %1,%f0\";
695 if (REG_P (operands[0]))
697 if (REG_P (operands[1]))
698 return \"fcmp%.x %1,%0\";
700 return \"fcmp%.d %f1,%0\";
702 cc_status.flags |= CC_REVERSED;
703 return \"fcmp%.d %f0,%1\";
707 (define_expand "cmpsf"
709 (compare (match_operand:SF 0 "general_operand" "")
710 (match_operand:SF 1 "general_operand" "")))]
711 "TARGET_68881 || TARGET_FPA"
714 m68k_last_compare_had_fp_operands = 1;
717 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
722 (define_insn "cmpsf_fpa"
724 (compare (match_operand:SF 0 "general_operand" "x,y")
725 (match_operand:SF 1 "general_operand" "xH,rmF")))
726 (clobber (match_scratch:SI 2 "=d,d"))]
728 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
732 (compare (match_operand:SF 0 "general_operand" "f,mdG")
733 (match_operand:SF 1 "general_operand" "fmdG,f")))]
737 cc_status.flags = CC_IN_68881;
739 if (FP_REG_P (operands[0]))
741 if (FP_REG_P (operands[1]))
742 return \"fcmp%.x %0,%1\";
744 return \"fcmp%.s %0,%f1\";
746 cc_status.flags |= CC_REVERSED;
747 return \"fcmp%.s %1,%f0\";
749 if (FP_REG_P (operands[0]))
751 if (FP_REG_P (operands[1]))
752 return \"fcmp%.x %1,%0\";
754 return \"fcmp%.s %f1,%0\";
756 cc_status.flags |= CC_REVERSED;
757 return \"fcmp%.s %f0,%1\";
761 ;; Recognizers for btst instructions.
763 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
764 ;; specified as a constant, so we must disable all patterns that may extract
765 ;; from a MEM at a constant bit position if we can't use this as a constraint.
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "di"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
775 ;; This is the same as the above pattern except for the constraints. The 'i'
779 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
781 (minus:SI (const_int 7)
782 (match_operand:SI 1 "general_operand" "d"))))]
784 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
787 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
789 (minus:SI (const_int 31)
790 (match_operand:SI 1 "general_operand" "di"))))]
792 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
794 ;; The following two patterns are like the previous two
795 ;; except that they use the fact that bit-number operands
796 ;; are automatically masked to 3 or 5 bits.
799 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
801 (minus:SI (const_int 7)
803 (match_operand:SI 1 "register_operand" "d")
806 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
809 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
811 (minus:SI (const_int 31)
813 (match_operand:SI 1 "register_operand" "d")
816 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
818 ;; Nonoffsettable mem refs are ok in this one pattern
819 ;; since we don't try to adjust them.
821 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
823 (match_operand:SI 1 "const_int_operand" "n")))]
824 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
827 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
828 return output_btst (operands, operands[1], operands[0], insn, 7);
832 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
834 (match_operand:SI 1 "const_int_operand" "n")))]
838 if (GET_CODE (operands[0]) == MEM)
840 operands[0] = adj_offsettable_operand (operands[0],
841 INTVAL (operands[1]) / 8);
842 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
843 return output_btst (operands, operands[1], operands[0], insn, 7);
845 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
846 return output_btst (operands, operands[1], operands[0], insn, 31);
849 ;; This is the same as the above pattern except for the constraints.
850 ;; The 'o' has been replaced with 'Q'.
853 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
855 (match_operand:SI 1 "const_int_operand" "n")))]
859 if (GET_CODE (operands[0]) == MEM)
861 operands[0] = adj_offsettable_operand (operands[0],
862 INTVAL (operands[1]) / 8);
863 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
864 return output_btst (operands, operands[1], operands[0], insn, 7);
866 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
867 return output_btst (operands, operands[1], operands[0], insn, 31);
873 ;; A special case in which it is not desirable
874 ;; to reload the constant into a data register.
875 (define_insn "pushexthisi_const"
876 [(set (match_operand:SI 0 "push_operand" "=m")
877 (match_operand:SI 1 "const_int_operand" "J"))]
878 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
881 if (operands[1] == const0_rtx)
882 return \"clr%.l %0\";
887 ;(define_insn "swapsi"
888 ; [(set (match_operand:SI 0 "general_operand" "+r")
889 ; (match_operand:SI 1 "general_operand" "+r"))
890 ; (set (match_dup 1) (match_dup 0))]
894 ;; Special case of fullword move when source is zero.
895 ;; The reason this is special is to avoid loading a zero
896 ;; into a data reg with moveq in order to store it elsewhere.
898 (define_insn "movsi_const0"
899 [(set (match_operand:SI 0 "general_operand" "=g")
901 ;; clr insns on 68000 read before writing.
902 ;; This isn't so on the 68010, but we have no TARGET_68010.
903 "((TARGET_68020 || TARGET_5200)
904 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
907 if (ADDRESS_REG_P (operands[0]))
909 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
910 if (!TARGET_68040 && !TARGET_68060)
911 return \"sub%.l %0,%0\";
916 /* Many SGS assemblers croak on size specifiers for constants. */
919 return \"lea 0.w,%0\";
922 return \"lea 0:w,%0\";
926 /* moveq is faster on the 68000. */
927 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
928 #if defined(MOTOROLA) && !defined(CRDS)
929 return \"moveq%.l %#0,%0\";
931 return \"moveq %#0,%0\";
933 return \"clr%.l %0\";
936 ;; General case of fullword move.
938 ;; This is the main "hook" for PIC code. When generating
939 ;; PIC, movsi is responsible for determining when the source address
940 ;; needs PIC relocation and appropriately calling legitimize_pic_address
941 ;; to perform the actual relocation.
943 ;; In both the PIC and non-PIC cases the patterns generated will
944 ;; matched by the next define_insn.
945 (define_expand "movsi"
946 [(set (match_operand:SI 0 "general_operand" "")
947 (match_operand:SI 1 "general_operand" ""))]
951 if (flag_pic && symbolic_operand (operands[1], SImode))
953 /* The source is an address which requires PIC relocation.
954 Call legitimize_pic_address with the source, mode, and a relocation
955 register (a new pseudo, or the final destination if reload_in_progress
956 is set). Then fall through normally */
957 extern rtx legitimize_pic_address();
958 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
959 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
963 ;; General case of fullword move. The register constraints
964 ;; force integer constants in range for a moveq to be reloaded
965 ;; if they are headed for memory.
967 ;; Notes: make sure no alternative allows g vs g.
968 ;; We don't allow f-regs since fixed point cannot go in them.
969 ;; We do allow y and x regs since fixed point is allowed in them.
970 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
971 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
975 if (which_alternative == 3)
976 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
977 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
978 return \"fpmove%.l %x1,%x0\";
979 return output_move_simode (operands);
983 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
984 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
986 "* return output_move_simode (operands);")
988 (define_expand "movhi"
989 [(set (match_operand:HI 0 "general_operand" "")
990 (match_operand:HI 1 "general_operand" ""))]
995 [(set (match_operand:HI 0 "general_operand" "=g")
996 (match_operand:HI 1 "general_operand" "g"))]
998 "* return output_move_himode (operands);")
1001 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
1002 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
1004 "* return output_move_himode (operands);")
1006 (define_expand "movstricthi"
1007 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1008 (match_operand:HI 1 "general_operand" ""))]
1013 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1014 (match_operand:HI 1 "general_operand" "rmn"))]
1016 "* return output_move_stricthi (operands);")
1019 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1020 (match_operand:HI 1 "general_operand" "rmn,r"))]
1022 "* return output_move_stricthi (operands);")
1024 (define_expand "movqi"
1025 [(set (match_operand:QI 0 "general_operand" "")
1026 (match_operand:QI 1 "general_operand" ""))]
1031 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1032 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1034 "* return output_move_qimode (operands);")
1037 [(set (match_operand:QI 0 "general_operand" "=d<Q>,dm,d*a")
1038 (match_operand:QI 1 "general_operand" "dmi,d<Q>,di*a"))]
1040 "* return output_move_qimode (operands);")
1042 (define_expand "movstrictqi"
1043 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1044 (match_operand:QI 1 "general_operand" ""))]
1049 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1050 (match_operand:QI 1 "general_operand" "dmn"))]
1052 "* return output_move_strictqi (operands);")
1055 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1056 (match_operand:QI 1 "general_operand" "dmn,d"))]
1058 "* return output_move_strictqi (operands);")
1060 (define_expand "movsf"
1061 [(set (match_operand:SF 0 "general_operand" "")
1062 (match_operand:SF 1 "general_operand" ""))]
1067 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1068 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1069 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1070 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1074 if (which_alternative >= 4)
1075 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1076 if (FPA_REG_P (operands[0]))
1078 if (FPA_REG_P (operands[1]))
1079 return \"fpmove%.s %x1,%x0\";
1080 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1081 return output_move_const_single (operands);
1082 else if (FP_REG_P (operands[1]))
1083 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1084 return \"fpmove%.s %x1,%x0\";
1086 if (FPA_REG_P (operands[1]))
1088 if (FP_REG_P (operands[0]))
1089 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1091 return \"fpmove%.s %x1,%x0\";
1093 if (FP_REG_P (operands[0]))
1095 if (FP_REG_P (operands[1]))
1096 return \"f%$move%.x %1,%0\";
1097 else if (ADDRESS_REG_P (operands[1]))
1098 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1099 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1100 return output_move_const_single (operands);
1101 return \"f%$move%.s %f1,%0\";
1103 if (FP_REG_P (operands[1]))
1105 if (ADDRESS_REG_P (operands[0]))
1106 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1107 return \"fmove%.s %f1,%0\";
1109 if (operands[1] == CONST0_RTX (SFmode)
1110 /* clr insns on 68000 read before writing.
1111 This isn't so on the 68010, but we have no TARGET_68010. */
1112 && ((TARGET_68020 || TARGET_5200)
1113 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1115 if (ADDRESS_REG_P (operands[0]))
1117 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1118 if (!TARGET_68040 && !TARGET_68060)
1119 return \"sub%.l %0,%0\";
1124 /* Many SGS assemblers croak on size specifiers for constants. */
1125 return \"lea 0,%0\";
1127 return \"lea 0.w,%0\";
1130 return \"lea 0:w,%0\";
1134 /* moveq is faster on the 68000. */
1135 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1137 #if defined(MOTOROLA) && !defined(CRDS)
1138 return \"moveq%.l %#0,%0\";
1140 return \"moveq %#0,%0\";
1143 return \"clr%.l %0\";
1145 return \"move%.l %1,%0\";
1149 [(set (match_operand:SF 0 "general_operand" "=r,g")
1150 (match_operand:SF 1 "general_operand" "g,r"))]
1152 "* return \"move%.l %1,%0\";")
1154 (define_expand "movdf"
1155 [(set (match_operand:DF 0 "general_operand" "")
1156 (match_operand:DF 1 "general_operand" ""))]
1161 [(set (match_operand:DF 0 "general_operand"
1162 "=*rm,*rf,*rf,&*rof<>,y,*rm,x,!x,!*rm")
1163 (match_operand:DF 1 "general_operand"
1164 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
1165 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1166 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1170 if (which_alternative == 7)
1171 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1172 if (FPA_REG_P (operands[0]))
1174 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1175 return output_move_const_double (operands);
1176 if (FP_REG_P (operands[1]))
1177 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1178 return \"fpmove%.d %x1,%x0\";
1180 else if (FPA_REG_P (operands[1]))
1182 if (FP_REG_P(operands[0]))
1183 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1185 return \"fpmove%.d %x1,%x0\";
1187 if (FP_REG_P (operands[0]))
1189 if (FP_REG_P (operands[1]))
1190 return \"f%&move%.x %1,%0\";
1191 if (REG_P (operands[1]))
1194 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1195 output_asm_insn (\"move%.l %1,%-\", xoperands);
1196 output_asm_insn (\"move%.l %1,%-\", operands);
1197 return \"f%&move%.d %+,%0\";
1199 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1200 return output_move_const_double (operands);
1201 return \"f%&move%.d %f1,%0\";
1203 else if (FP_REG_P (operands[1]))
1205 if (REG_P (operands[0]))
1207 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1208 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1209 return \"move%.l %+,%0\";
1212 return \"fmove%.d %f1,%0\";
1214 return output_move_double (operands);
1218 [(set (match_operand:DF 0 "general_operand" "=r,g")
1219 (match_operand:DF 1 "general_operand" "g,r"))]
1221 "* return output_move_double (operands);")
1223 (define_expand "movxf"
1224 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1225 (match_operand:XF 1 "general_operand" ""))]
1229 if (CONSTANT_P (operands[1]))
1231 operands[1] = force_const_mem (XFmode, operands[1]);
1232 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1233 && ! reload_in_progress)
1234 operands[1] = change_address (operands[1], XFmode,
1235 XEXP (operands[1], 0));
1240 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r")
1241 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r"))]
1245 if (FP_REG_P (operands[0]))
1247 if (FP_REG_P (operands[1]))
1248 return \"fmove%.x %1,%0\";
1249 if (REG_P (operands[1]))
1252 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1253 output_asm_insn (\"move%.l %1,%-\", xoperands);
1254 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1255 output_asm_insn (\"move%.l %1,%-\", xoperands);
1256 output_asm_insn (\"move%.l %1,%-\", operands);
1257 return \"fmove%.x %+,%0\";
1259 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1260 return \"fmove%.x %1,%0\";
1261 return \"fmove%.x %f1,%0\";
1263 if (FP_REG_P (operands[1]))
1265 if (REG_P (operands[0]))
1267 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1268 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1269 output_asm_insn (\"move%.l %+,%0\", operands);
1270 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1271 return \"move%.l %+,%0\";
1273 /* Must be memory destination. */
1274 return \"fmove%.x %f1,%0\";
1276 return output_move_double (operands);
1281 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1282 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1283 "! TARGET_68881 && ! TARGET_5200"
1286 if (FP_REG_P (operands[0]))
1288 if (FP_REG_P (operands[1]))
1289 return \"fmove%.x %1,%0\";
1290 if (REG_P (operands[1]))
1293 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1294 output_asm_insn (\"move%.l %1,%-\", xoperands);
1295 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1296 output_asm_insn (\"move%.l %1,%-\", xoperands);
1297 output_asm_insn (\"move%.l %1,%-\", operands);
1298 return \"fmove%.x %+,%0\";
1300 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1301 return \"fmove%.x %1,%0\";
1302 return \"fmove%.x %f1,%0\";
1304 if (FP_REG_P (operands[1]))
1306 if (REG_P (operands[0]))
1308 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1309 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1310 output_asm_insn (\"move%.l %+,%0\", operands);
1311 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1312 return \"move%.l %+,%0\";
1315 return \"fmove%.x %f1,%0\";
1317 return output_move_double (operands);
1322 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1323 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1324 "! TARGET_68881 && TARGET_5200"
1325 "* return output_move_double (operands);")
1327 (define_expand "movdi"
1328 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1329 [(set (match_operand:DI 0 "general_operand" "")
1330 (match_operand:DI 1 "general_operand" ""))]
1334 ;; movdi can apply to fp regs in some cases
1336 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1337 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1338 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1339 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1340 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1341 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1342 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1346 if (which_alternative == 8)
1347 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1348 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1349 return \"fpmove%.d %x1,%x0\";
1350 if (FP_REG_P (operands[0]))
1352 if (FP_REG_P (operands[1]))
1353 return \"fmove%.x %1,%0\";
1354 if (REG_P (operands[1]))
1357 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1358 output_asm_insn (\"move%.l %1,%-\", xoperands);
1359 output_asm_insn (\"move%.l %1,%-\", operands);
1360 return \"fmove%.d %+,%0\";
1362 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1363 return output_move_const_double (operands);
1364 return \"fmove%.d %f1,%0\";
1366 else if (FP_REG_P (operands[1]))
1368 if (REG_P (operands[0]))
1370 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1371 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1372 return \"move%.l %+,%0\";
1375 return \"fmove%.d %f1,%0\";
1377 return output_move_double (operands);
1381 [(set (match_operand:DI 0 "general_operand" "=r,g")
1382 (match_operand:DI 1 "general_operand" "g,r"))]
1384 "* return output_move_double (operands);")
1386 ;; Thus goes after the move instructions
1387 ;; because the move instructions are better (require no spilling)
1388 ;; when they can apply. It goes before the add/sub insns
1389 ;; so we will prefer it to them.
1391 (define_insn "pushasi"
1392 [(set (match_operand:SI 0 "push_operand" "=m")
1393 (match_operand:SI 1 "address_operand" "p"))]
1397 ;; truncation instructions
1398 (define_insn "truncsiqi2"
1399 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1401 (match_operand:SI 1 "general_operand" "doJ,i")))]
1405 if (GET_CODE (operands[0]) == REG)
1407 /* Must clear condition codes, since the move.l bases them on
1408 the entire 32 bits, not just the desired 8 bits. */
1410 return \"move%.l %1,%0\";
1412 if (GET_CODE (operands[1]) == MEM)
1413 operands[1] = adj_offsettable_operand (operands[1], 3);
1414 return \"move%.b %1,%0\";
1417 (define_insn "trunchiqi2"
1418 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1420 (match_operand:HI 1 "general_operand" "doJ,i")))]
1424 if (GET_CODE (operands[0]) == REG
1425 && (GET_CODE (operands[1]) == MEM
1426 || GET_CODE (operands[1]) == CONST_INT))
1428 /* Must clear condition codes, since the move.w bases them on
1429 the entire 16 bits, not just the desired 8 bits. */
1431 return \"move%.w %1,%0\";
1433 if (GET_CODE (operands[0]) == REG)
1435 /* Must clear condition codes, since the move.l bases them on
1436 the entire 32 bits, not just the desired 8 bits. */
1438 return \"move%.l %1,%0\";
1440 if (GET_CODE (operands[1]) == MEM)
1441 operands[1] = adj_offsettable_operand (operands[1], 1);
1442 return \"move%.b %1,%0\";
1445 (define_insn "truncsihi2"
1446 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1448 (match_operand:SI 1 "general_operand" "roJ,i")))]
1452 if (GET_CODE (operands[0]) == REG)
1454 /* Must clear condition codes, since the move.l bases them on
1455 the entire 32 bits, not just the desired 8 bits. */
1457 return \"move%.l %1,%0\";
1459 if (GET_CODE (operands[1]) == MEM)
1460 operands[1] = adj_offsettable_operand (operands[1], 2);
1461 return \"move%.w %1,%0\";
1464 ;; zero extension instructions
1466 (define_insn "zero_extendqidi2"
1467 [(set (match_operand:DI 0 "general_operand" "=&d")
1468 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1473 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1474 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1477 (define_insn "zero_extendhidi2"
1478 [(set (match_operand:DI 0 "general_operand" "=&d")
1479 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1484 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1485 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1488 ;; this is the canonical form for (lshiftrt:DI x 32)
1489 (define_insn "zero_extendsidi2"
1490 [(set (match_operand:DI 0 "general_operand" "rm")
1491 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1496 if (GET_CODE (operands[0]) == REG)
1497 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1498 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1499 return \"move%.l %1,%0\;clr%.l %0\";
1500 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1501 return \"clr%.l %0\;move%.l %1,%0\";
1503 operands[2] = adj_offsettable_operand (operands[0], 4);
1504 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
1505 || REGNO (operands[1]) != REGNO (operands[2]))
1506 output_asm_insn (\"move%.l %1,%2\", operands);
1507 if (ADDRESS_REG_P (operands[0]))
1508 return \"sub%.l %0,%0\";
1510 return \"clr%.l %0\";
1513 (define_expand "zero_extendhisi2"
1514 [(set (match_operand:SI 0 "register_operand" "")
1516 (set (strict_low_part (match_dup 2))
1517 (match_operand:HI 1 "general_operand" ""))]
1521 operands[1] = make_safe_from (operands[1], operands[0]);
1522 if (GET_CODE (operands[0]) == SUBREG)
1523 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1524 SUBREG_WORD (operands[0]));
1526 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1529 (define_expand "zero_extendqihi2"
1530 [(set (match_operand:HI 0 "register_operand" "")
1532 (set (strict_low_part (match_dup 2))
1533 (match_operand:QI 1 "general_operand" ""))]
1537 operands[1] = make_safe_from (operands[1], operands[0]);
1538 if (GET_CODE (operands[0]) == SUBREG)
1539 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1540 SUBREG_WORD (operands[0]));
1542 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1545 (define_expand "zero_extendqisi2"
1546 [(set (match_operand:SI 0 "register_operand" "")
1548 (set (strict_low_part (match_dup 2))
1549 (match_operand:QI 1 "general_operand" ""))]
1553 operands[1] = make_safe_from (operands[1], operands[0]);
1554 if (GET_CODE (operands[0]) == SUBREG)
1555 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1556 SUBREG_WORD (operands[0]));
1558 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1561 ;; Patterns to recognize zero-extend insns produced by the combiner.
1562 ;; We don't allow both operands in memory, because of aliasing problems.
1563 ;; Explicitly disallow two memory operands via the condition since reloading
1564 ;; of this case will result in worse code than the uncombined patterns.
1567 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1568 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1569 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1572 if (DATA_REG_P (operands[0]))
1574 if (GET_CODE (operands[1]) == REG
1575 && REGNO (operands[0]) == REGNO (operands[1]))
1576 return \"and%.l %#0xFFFF,%0\";
1577 if (reg_mentioned_p (operands[0], operands[1]))
1578 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1579 return \"clr%.l %0\;move%.w %1,%0\";
1581 else if (GET_CODE (operands[0]) == MEM
1582 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1583 return \"move%.w %1,%0\;clr%.w %0\";
1584 else if (GET_CODE (operands[0]) == MEM
1585 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1586 return \"clr%.w %0\;move%.w %1,%0\";
1589 output_asm_insn (\"clr%.w %0\", operands);
1590 operands[0] = adj_offsettable_operand (operands[0], 2);
1591 return \"move%.w %1,%0\";
1596 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1597 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1598 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1601 if (DATA_REG_P (operands[0]))
1603 if (GET_CODE (operands[1]) == REG
1604 && REGNO (operands[0]) == REGNO (operands[1]))
1605 return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
1606 if (reg_mentioned_p (operands[0], operands[1]))
1607 return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
1608 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
1609 return \"clr%.w %0\;move%.b %1,%0\";
1611 else if (GET_CODE (operands[0]) == MEM
1612 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1614 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1615 == STACK_POINTER_REGNUM)
1617 output_asm_insn (\"clr%.w %-\", operands);
1618 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1619 plus_constant (stack_pointer_rtx, 1));
1620 return \"move%.b %1,%0\";
1623 return \"move%.b %1,%0\;clr%.b %0\";
1625 else if (GET_CODE (operands[0]) == MEM
1626 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1627 return \"clr%.b %0\;move%.b %1,%0\";
1630 output_asm_insn (\"clr%.b %0\", operands);
1631 operands[0] = adj_offsettable_operand (operands[0], 1);
1632 return \"move%.b %1,%0\";
1637 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1638 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1639 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1642 if (DATA_REG_P (operands[0]))
1644 if (GET_CODE (operands[1]) == REG
1645 && REGNO (operands[0]) == REGNO (operands[1]))
1646 return \"and%.l %#0xFF,%0\";
1647 if (reg_mentioned_p (operands[0], operands[1]))
1648 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1649 return \"clr%.l %0\;move%.b %1,%0\";
1651 else if (GET_CODE (operands[0]) == MEM
1652 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1654 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1657 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1659 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1662 return \"clrl %0@-\;moveb %1,%0@(3)\";
1665 else if (GET_CODE (operands[0]) == MEM
1666 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1668 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1671 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1673 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1676 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1681 output_asm_insn (\"clr%.l %0\", operands);
1682 operands[0] = adj_offsettable_operand (operands[0], 3);
1683 return \"move%.b %1,%0\";
1687 ;; sign extension instructions
1689 (define_insn "extendqidi2"
1690 [(set (match_operand:DI 0 "general_operand" "=d")
1691 (sign_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1696 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1697 if (TARGET_68020 || TARGET_5200)
1698 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1700 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1703 (define_insn "extendhidi2"
1704 [(set (match_operand:DI 0 "general_operand" "=d")
1706 (match_operand:HI 1 "general_operand" "rm")))]
1711 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1712 if (TARGET_68020 || TARGET_5200)
1713 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1715 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1718 (define_insn "extendsidi2"
1719 [(set (match_operand:DI 0 "general_operand" "=d")
1721 (match_operand:SI 1 "general_operand" "rm")))]
1726 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1727 if (TARGET_68020 || TARGET_5200)
1728 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1730 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1733 ;; Special case when one can avoid register clobbering, copy and test
1734 ;; Maybe there is a way to make that the general case, by forcing the
1735 ;; result of the SI tree to be in the lower register of the DI target
1737 (define_insn "extendplussidi"
1738 [(set (match_operand:DI 0 "register_operand" "=d")
1739 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1740 (match_operand:SI 2 "general_operand" "rmn"))))]
1745 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1746 if (GET_CODE (operands[1]) == CONST_INT
1747 && (unsigned) INTVAL (operands[1]) > 8)
1749 rtx tmp = operands[1];
1751 operands[1] = operands[2];
1754 if (GET_CODE (operands[1]) == REG
1755 && REGNO (operands[1]) == REGNO (operands[3]))
1756 output_asm_insn (\"add%.l %2,%3\", operands);
1758 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1759 if (TARGET_68020 || TARGET_5200)
1760 return \"smi %0\;extb%.l %0\";
1762 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1765 (define_insn "extendhisi2"
1766 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1768 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1772 if (ADDRESS_REG_P (operands[0]))
1773 return \"move%.w %1,%0\";
1774 return \"ext%.l %0\";
1777 (define_insn "extendqihi2"
1778 [(set (match_operand:HI 0 "general_operand" "=d")
1779 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1783 (define_insn "extendqisi2"
1784 [(set (match_operand:SI 0 "general_operand" "=d")
1785 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1786 "TARGET_68020 || TARGET_5200"
1789 ;; Conversions between float and double.
1791 (define_expand "extendsfdf2"
1792 [(set (match_operand:DF 0 "general_operand" "")
1794 (match_operand:SF 1 "general_operand" "")))]
1795 "TARGET_68881 || TARGET_FPA"
1799 [(set (match_operand:DF 0 "general_operand" "=x,y")
1801 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1806 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1808 (match_operand:SF 1 "general_operand" "f,dmF")))]
1812 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1814 if (REGNO (operands[0]) == REGNO (operands[1]))
1816 /* Extending float to double in an fp-reg is a no-op.
1817 NOTICE_UPDATE_CC has already assumed that the
1818 cc will be set. So cancel what it did. */
1819 cc_status = cc_prev_status;
1822 return \"f%&move%.x %1,%0\";
1824 if (FP_REG_P (operands[0]))
1825 return \"f%&move%.s %f1,%0\";
1826 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1828 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1829 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1830 return \"move%.l %+,%0\";
1832 return \"fmove%.d %f1,%0\";
1835 ;; This cannot output into an f-reg because there is no way to be
1836 ;; sure of truncating in that case.
1837 ;; But on the Sun FPA, we can be sure.
1838 (define_expand "truncdfsf2"
1839 [(set (match_operand:SF 0 "general_operand" "")
1841 (match_operand:DF 1 "general_operand" "")))]
1842 "TARGET_68881 || TARGET_FPA"
1846 [(set (match_operand:SF 0 "general_operand" "=x,y")
1848 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1852 ;; On the '040 we can truncate in a register accurately and easily.
1854 [(set (match_operand:SF 0 "general_operand" "=f")
1856 (match_operand:DF 1 "general_operand" "fmG")))]
1860 if (FP_REG_P (operands[1]))
1861 return \"f%$move%.x %1,%0\";
1862 return \"f%$move%.d %f1,%0\";
1866 [(set (match_operand:SF 0 "general_operand" "=dm")
1868 (match_operand:DF 1 "general_operand" "f")))]
1872 ;; Conversion between fixed point and floating point.
1873 ;; Note that among the fix-to-float insns
1874 ;; the ones that start with SImode come first.
1875 ;; That is so that an operand that is a CONST_INT
1876 ;; (and therefore lacks a specific machine mode).
1877 ;; will be recognized as SImode (which is always valid)
1878 ;; rather than as QImode or HImode.
1880 (define_expand "floatsisf2"
1881 [(set (match_operand:SF 0 "general_operand" "")
1882 (float:SF (match_operand:SI 1 "general_operand" "")))]
1883 "TARGET_68881 || TARGET_FPA"
1887 [(set (match_operand:SF 0 "general_operand" "=y,x")
1888 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1893 [(set (match_operand:SF 0 "general_operand" "=f")
1894 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1898 (define_expand "floatsidf2"
1899 [(set (match_operand:DF 0 "general_operand" "")
1900 (float:DF (match_operand:SI 1 "general_operand" "")))]
1901 "TARGET_68881 || TARGET_FPA"
1905 [(set (match_operand:DF 0 "general_operand" "=y,x")
1906 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1911 [(set (match_operand:DF 0 "general_operand" "=f")
1912 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1916 (define_insn "floathisf2"
1917 [(set (match_operand:SF 0 "general_operand" "=f")
1918 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1922 (define_insn "floathidf2"
1923 [(set (match_operand:DF 0 "general_operand" "=f")
1924 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1928 (define_insn "floatqisf2"
1929 [(set (match_operand:SF 0 "general_operand" "=f")
1930 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1934 (define_insn "floatqidf2"
1935 [(set (match_operand:DF 0 "general_operand" "=f")
1936 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1940 ;; New routines to convert floating-point values to integers
1941 ;; to be used on the '040. These should be faster than trapping
1942 ;; into the kernel to emulate fintrz. They should also be faster
1943 ;; than calling the subroutines fixsfsi or fixdfsi.
1945 (define_insn "fix_truncdfsi2"
1946 [(set (match_operand:SI 0 "general_operand" "=dm")
1947 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1948 (clobber (match_scratch:SI 2 "=d"))
1949 (clobber (match_scratch:SI 3 "=d"))]
1950 "TARGET_68881 && TARGET_68040"
1954 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1957 (define_insn "fix_truncdfhi2"
1958 [(set (match_operand:HI 0 "general_operand" "=dm")
1959 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1960 (clobber (match_scratch:SI 2 "=d"))
1961 (clobber (match_scratch:SI 3 "=d"))]
1962 "TARGET_68881 && TARGET_68040"
1966 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1969 (define_insn "fix_truncdfqi2"
1970 [(set (match_operand:QI 0 "general_operand" "=dm")
1971 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1972 (clobber (match_scratch:SI 2 "=d"))
1973 (clobber (match_scratch:SI 3 "=d"))]
1974 "TARGET_68881 && TARGET_68040"
1978 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1981 ;; Convert a float to a float whose value is an integer.
1982 ;; This is the first stage of converting it to an integer type.
1984 (define_insn "ftruncdf2"
1985 [(set (match_operand:DF 0 "general_operand" "=f")
1986 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1987 "TARGET_68881 && !TARGET_68040"
1990 if (FP_REG_P (operands[1]))
1991 return \"fintrz%.x %f1,%0\";
1992 return \"fintrz%.d %f1,%0\";
1995 (define_insn "ftruncsf2"
1996 [(set (match_operand:SF 0 "general_operand" "=f")
1997 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1998 "TARGET_68881 && !TARGET_68040"
2001 if (FP_REG_P (operands[1]))
2002 return \"fintrz%.x %f1,%0\";
2003 return \"fintrz%.s %f1,%0\";
2006 ;; Convert a float whose value is an integer
2007 ;; to an actual integer. Second stage of converting float to integer type.
2008 (define_insn "fixsfqi2"
2009 [(set (match_operand:QI 0 "general_operand" "=dm")
2010 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
2014 (define_insn "fixsfhi2"
2015 [(set (match_operand:HI 0 "general_operand" "=dm")
2016 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2020 (define_insn "fixsfsi2"
2021 [(set (match_operand:SI 0 "general_operand" "=dm")
2022 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2026 (define_insn "fixdfqi2"
2027 [(set (match_operand:QI 0 "general_operand" "=dm")
2028 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2032 (define_insn "fixdfhi2"
2033 [(set (match_operand:HI 0 "general_operand" "=dm")
2034 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2038 (define_insn "fixdfsi2"
2039 [(set (match_operand:SI 0 "general_operand" "=dm")
2040 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2044 ;; Convert a float to an integer.
2045 ;; On the Sun FPA, this is done in one step.
2048 [(set (match_operand:SI 0 "general_operand" "=x,y")
2049 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2054 [(set (match_operand:SI 0 "general_operand" "=x,y")
2055 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2061 (define_insn "adddi_lshrdi_63"
2062 [(set (match_operand:DI 0 "general_operand" "=d")
2063 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2066 (clobber (match_scratch:SI 2 "=d"))]
2070 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2071 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2073 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2074 if (GET_CODE (operands[1]) == REG)
2075 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2076 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2077 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2078 operands[4] = operands[1];
2080 operands[4] = adj_offsettable_operand (operands[1], 4);
2081 if (GET_CODE (operands[1]) == MEM
2082 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2083 output_asm_insn (\"move%.l %4,%3\", operands);
2084 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2085 if (TARGET_68020 || TARGET_5200)
2086 output_asm_insn (\"extb%.l %2\", operands);
2088 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2089 if (GET_CODE (operands[1]) != MEM
2090 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2091 output_asm_insn (\"move%.l %4,%3\", operands);
2092 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2095 (define_insn "adddi_sexthishl32"
2096 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2097 (plus:DI (ashift:DI (sign_extend:DI
2098 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2100 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2101 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2106 if (ADDRESS_REG_P (operands[0]))
2107 return \"add%.w %1,%0\";
2108 else if (ADDRESS_REG_P (operands[3]))
2109 return \"move%.w %1,%3\;add%.l %3,%0\";
2111 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2114 (define_insn "adddi_dilshr32"
2115 [(set (match_operand:DI 0 "general_operand" "=d,o")
2116 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2117 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2118 ;; (const_int 32))))]
2119 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,r")
2121 (match_operand:DI 2 "general_operand" "0,0")))]
2126 if (GET_CODE (operands[0]) == REG)
2127 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2129 operands[2] = adj_offsettable_operand (operands[0], 4);
2130 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2133 (define_insn "adddi_dishl32"
2134 [(set (match_operand:DI 0 "general_operand" "=r,o")
2135 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2136 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2137 ;; (const_int 32))))]
2138 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,r")
2140 (match_operand:DI 2 "general_operand" "0,0")))]
2145 if (GET_CODE (operands[1]) == REG)
2146 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2148 operands[1] = adj_offsettable_operand (operands[1], 4);
2149 return \"add%.l %1,%0\";
2152 (define_insn "adddi3"
2153 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2154 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2155 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2156 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2160 if (DATA_REG_P (operands[0]))
2162 if (DATA_REG_P (operands[2]))
2163 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2164 else if (GET_CODE (operands[2]) == MEM
2165 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2167 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2172 if (GET_CODE (operands[2]) == REG)
2173 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2174 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2176 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2177 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2179 else if (GET_CODE (operands[2]) == CONST_INT)
2181 operands[1] = operands[2];
2182 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2185 operands[1] = adj_offsettable_operand (operands[2], 4);
2186 xoperands[0] = operands[3];
2187 if (GET_CODE (operands[1]) == CONST_INT
2188 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2189 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2191 xoperands[1] = operands[2];
2192 output_asm_insn (output_move_simode (xoperands), xoperands);
2193 if (GET_CODE (operands[1]) == CONST_INT)
2195 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2198 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2200 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2203 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2205 operands[1] = GEN_INT (-INTVAL (operands[1]));
2207 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2209 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2213 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2216 else if (GET_CODE (operands[0]) == MEM)
2218 if (GET_CODE (operands[2]) == MEM
2219 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2220 return \"add%.l %2,%0\;addx%.l %2,%0\";
2222 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2225 = gen_rtx_MEM (SImode,
2226 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2228 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2230 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2232 operands[1] = XEXP(operands[0], 0);
2233 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2237 operands[1] = adj_offsettable_operand (operands[0], 4);
2238 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2245 (define_insn "addsi_lshrsi_31"
2246 [(set (match_operand:SI 0 "general_operand" "=dm")
2247 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2253 operands[2] = operands[0];
2254 operands[3] = gen_label_rtx();
2255 if (GET_CODE (operands[0]) == MEM)
2257 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2258 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2259 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2260 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2262 output_asm_insn (\"move%.l %1,%0\", operands);
2264 output_asm_insn (\"jbpl %l3\", operands);
2266 output_asm_insn (\"jpl %l3\", operands);
2269 output_asm_insn (\"addq%.l %#1,%2\", operands);
2271 output_asm_insn (\"add%.l %#1,%2\", operands);
2273 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2274 CODE_LABEL_NUMBER (operands[3]));
2278 (define_expand "addsi3"
2279 [(set (match_operand:SI 0 "general_operand" "")
2280 (plus:SI (match_operand:SI 1 "general_operand" "")
2281 (match_operand:SI 2 "general_operand" "")))]
2285 ;; Note that the middle two alternatives are near-duplicates
2286 ;; in order to handle insns generated by reload.
2287 ;; This is needed since they are not themselves reloaded,
2288 ;; so commutativity won't apply to them.
2289 (define_insn "*addsi3_internal"
2290 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2291 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2292 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2294 "* return output_addsi3 (operands);")
2296 (define_insn "*addsi3_5200"
2297 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2298 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2299 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2301 "* return output_addsi3 (operands);")
2304 [(set (match_operand:SI 0 "general_operand" "=a")
2305 (plus:SI (match_operand:SI 1 "general_operand" "0")
2307 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2311 (define_insn "addhi3"
2312 [(set (match_operand:HI 0 "general_operand" "=m,r")
2313 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2314 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2318 if (GET_CODE (operands[2]) == CONST_INT)
2321 /* If the constant would be a negative number when interpreted as
2322 HImode, make it negative. This is usually, but not always, done
2323 elsewhere in the compiler. First check for constants out of range,
2324 which could confuse us. */
2326 if (INTVAL (operands[2]) >= 32768)
2327 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2329 if (INTVAL (operands[2]) > 0
2330 && INTVAL (operands[2]) <= 8)
2331 return \"addq%.w %2,%0\";
2332 if (INTVAL (operands[2]) < 0
2333 && INTVAL (operands[2]) >= -8)
2335 operands[2] = GEN_INT (-INTVAL (operands[2]));
2336 return \"subq%.w %2,%0\";
2338 /* On the CPU32 it is faster to use two addqw instructions to
2339 add a small integer (8 < N <= 16) to a register.
2340 Likewise for subqw. */
2341 if (TARGET_CPU32 && REG_P (operands[0]))
2343 if (INTVAL (operands[2]) > 8
2344 && INTVAL (operands[2]) <= 16)
2346 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2347 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2349 if (INTVAL (operands[2]) < -8
2350 && INTVAL (operands[2]) >= -16)
2352 operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
2353 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2357 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2359 return \"lea (%c2,%0),%0\";
2361 return \"lea %0@(%c2),%0\";
2364 return \"add%.w %2,%0\";
2367 ;; These insns must use MATCH_DUP instead of the more expected
2368 ;; use of a matching constraint because the "output" here is also
2369 ;; an input, so you can't use the matching constraint. That also means
2370 ;; that you can't use the "%", so you need patterns with the matched
2371 ;; operand in both positions.
2374 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2375 (plus:HI (match_dup 0)
2376 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2380 if (GET_CODE (operands[1]) == CONST_INT)
2383 /* If the constant would be a negative number when interpreted as
2384 HImode, make it negative. This is usually, but not always, done
2385 elsewhere in the compiler. First check for constants out of range,
2386 which could confuse us. */
2388 if (INTVAL (operands[1]) >= 32768)
2389 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2391 if (INTVAL (operands[1]) > 0
2392 && INTVAL (operands[1]) <= 8)
2393 return \"addq%.w %1,%0\";
2394 if (INTVAL (operands[1]) < 0
2395 && INTVAL (operands[1]) >= -8)
2397 operands[1] = GEN_INT (-INTVAL (operands[1]));
2398 return \"subq%.w %1,%0\";
2400 /* On the CPU32 it is faster to use two addqw instructions to
2401 add a small integer (8 < N <= 16) to a register.
2402 Likewise for subqw. */
2403 if (TARGET_CPU32 && REG_P (operands[0]))
2405 if (INTVAL (operands[1]) > 8
2406 && INTVAL (operands[1]) <= 16)
2408 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2409 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2411 if (INTVAL (operands[1]) < -8
2412 && INTVAL (operands[1]) >= -16)
2414 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2415 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2419 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2421 return \"lea (%c1,%0),%0\";
2423 return \"lea %0@(%c1),%0\";
2426 return \"add%.w %1,%0\";
2430 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2431 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2436 if (GET_CODE (operands[1]) == CONST_INT)
2439 /* If the constant would be a negative number when interpreted as
2440 HImode, make it negative. This is usually, but not always, done
2441 elsewhere in the compiler. First check for constants out of range,
2442 which could confuse us. */
2444 if (INTVAL (operands[1]) >= 32768)
2445 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2447 if (INTVAL (operands[1]) > 0
2448 && INTVAL (operands[1]) <= 8)
2449 return \"addq%.w %1,%0\";
2450 if (INTVAL (operands[1]) < 0
2451 && INTVAL (operands[1]) >= -8)
2453 operands[1] = GEN_INT (-INTVAL (operands[1]));
2454 return \"subq%.w %1,%0\";
2456 /* On the CPU32 it is faster to use two addqw instructions to
2457 add a small integer (8 < N <= 16) to a register.
2458 Likewise for subqw. */
2459 if (TARGET_CPU32 && REG_P (operands[0]))
2461 if (INTVAL (operands[1]) > 8
2462 && INTVAL (operands[1]) <= 16)
2464 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2465 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2467 if (INTVAL (operands[1]) < -8
2468 && INTVAL (operands[1]) >= -16)
2470 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2471 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2475 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2477 return \"lea (%c1,%0),%0\";
2479 return \"lea %0@(%c1),%0\";
2482 return \"add%.w %1,%0\";
2485 (define_insn "addqi3"
2486 [(set (match_operand:QI 0 "general_operand" "=m,d")
2487 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2488 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2493 if (GET_CODE (operands[2]) == CONST_INT)
2495 if (INTVAL (operands[2]) >= 128)
2496 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2498 if (INTVAL (operands[2]) > 0
2499 && INTVAL (operands[2]) <= 8)
2500 return \"addq%.b %2,%0\";
2501 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2503 operands[2] = GEN_INT (-INTVAL (operands[2]));
2504 return \"subq%.b %2,%0\";
2508 return \"add%.b %2,%0\";
2512 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2513 (plus:QI (match_dup 0)
2514 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2519 if (GET_CODE (operands[1]) == CONST_INT)
2521 if (INTVAL (operands[1]) >= 128)
2522 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2524 if (INTVAL (operands[1]) > 0
2525 && INTVAL (operands[1]) <= 8)
2526 return \"addq%.b %1,%0\";
2527 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2529 operands[1] = GEN_INT (-INTVAL (operands[1]));
2530 return \"subq%.b %1,%0\";
2534 return \"add%.b %1,%0\";
2538 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2539 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2545 if (GET_CODE (operands[1]) == CONST_INT)
2547 if (INTVAL (operands[1]) >= 128)
2548 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2550 if (INTVAL (operands[1]) > 0
2551 && INTVAL (operands[1]) <= 8)
2552 return \"addq%.b %1,%0\";
2553 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2555 operands[1] = GEN_INT (-INTVAL (operands[1]));
2556 return \"subq%.b %1,%0\";
2560 return \"add%.b %1,%0\";
2563 (define_expand "adddf3"
2564 [(set (match_operand:DF 0 "general_operand" "")
2565 (plus:DF (match_operand:DF 1 "general_operand" "")
2566 (match_operand:DF 2 "general_operand" "")))]
2567 "TARGET_68881 || TARGET_FPA"
2571 [(set (match_operand:DF 0 "general_operand" "=x,y")
2572 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2573 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2577 if (rtx_equal_p (operands[0], operands[1]))
2578 return \"fpadd%.d %y2,%0\";
2579 if (rtx_equal_p (operands[0], operands[2]))
2580 return \"fpadd%.d %y1,%0\";
2581 if (which_alternative == 0)
2582 return \"fpadd3%.d %w2,%w1,%0\";
2583 return \"fpadd3%.d %x2,%x1,%0\";
2587 [(set (match_operand:DF 0 "general_operand" "=f")
2588 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2589 (match_operand:DF 1 "general_operand" "0")))]
2594 [(set (match_operand:DF 0 "general_operand" "=f")
2595 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2596 (match_operand:DF 1 "general_operand" "0")))]
2601 [(set (match_operand:DF 0 "general_operand" "=f")
2602 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2603 (match_operand:DF 1 "general_operand" "0")))]
2608 [(set (match_operand:DF 0 "general_operand" "=f")
2609 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2610 (match_operand:DF 2 "general_operand" "fmG")))]
2614 if (REG_P (operands[2]))
2615 return \"f%&add%.x %2,%0\";
2616 return \"f%&add%.d %f2,%0\";
2619 (define_expand "addsf3"
2620 [(set (match_operand:SF 0 "general_operand" "")
2621 (plus:SF (match_operand:SF 1 "general_operand" "")
2622 (match_operand:SF 2 "general_operand" "")))]
2623 "TARGET_68881 || TARGET_FPA"
2627 [(set (match_operand:SF 0 "general_operand" "=x,y")
2628 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2629 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2633 if (rtx_equal_p (operands[0], operands[1]))
2634 return \"fpadd%.s %w2,%0\";
2635 if (rtx_equal_p (operands[0], operands[2]))
2636 return \"fpadd%.s %w1,%0\";
2637 if (which_alternative == 0)
2638 return \"fpadd3%.s %w2,%w1,%0\";
2639 return \"fpadd3%.s %2,%1,%0\";
2643 [(set (match_operand:SF 0 "general_operand" "=f")
2644 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2645 (match_operand:SF 1 "general_operand" "0")))]
2650 [(set (match_operand:SF 0 "general_operand" "=f")
2651 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2652 (match_operand:SF 1 "general_operand" "0")))]
2657 [(set (match_operand:SF 0 "general_operand" "=f")
2658 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2659 (match_operand:SF 1 "general_operand" "0")))]
2664 [(set (match_operand:SF 0 "general_operand" "=f")
2665 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2666 (match_operand:SF 2 "general_operand" "fdmF")))]
2670 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2671 return \"f%$add%.x %2,%0\";
2672 return \"f%$add%.s %f2,%0\";
2675 ;; subtract instructions
2677 (define_insn "subdi_sexthishl32"
2678 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2679 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2680 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2682 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2687 if (ADDRESS_REG_P (operands[0]))
2688 return \"sub%.w %2,%0\";
2689 else if (ADDRESS_REG_P (operands[3]))
2690 return \"move%.w %2,%3\;sub%.l %3,%0\";
2692 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2695 (define_insn "subdi_dishl32"
2696 [(set (match_operand:DI 0 "general_operand" "+ro")
2697 (minus:DI (match_dup 0)
2698 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2704 if (GET_CODE (operands[1]) == REG)
2705 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2707 operands[1] = adj_offsettable_operand (operands[1], 4);
2708 return \"sub%.l %1,%0\";
2711 (define_insn "subdi3"
2712 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2713 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2714 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2715 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2719 if (DATA_REG_P (operands[0]))
2721 if (DATA_REG_P (operands[2]))
2722 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2723 else if (GET_CODE (operands[2]) == MEM
2724 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2726 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2731 if (GET_CODE (operands[2]) == REG)
2732 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2733 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2735 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2736 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2738 else if (GET_CODE (operands[2]) == CONST_INT)
2740 operands[1] = operands[2];
2741 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2744 operands[1] = adj_offsettable_operand (operands[2], 4);
2745 xoperands[0] = operands[3];
2746 if (GET_CODE (operands[1]) == CONST_INT
2747 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2748 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2750 xoperands[1] = operands[2];
2751 output_asm_insn (output_move_simode (xoperands), xoperands);
2752 if (GET_CODE (operands[1]) == CONST_INT)
2754 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2757 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2759 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2762 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2764 operands[1] = GEN_INT (-INTVAL (operands[1]));
2766 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2768 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2772 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2775 else if (GET_CODE (operands[0]) == MEM)
2777 if (GET_CODE (operands[2]) == MEM
2778 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2779 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2781 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2784 = gen_rtx_MEM (SImode,
2785 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2787 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2789 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2791 operands[1] = XEXP(operands[0], 0);
2792 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2796 operands[1] = adj_offsettable_operand (operands[0], 4);
2797 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2804 (define_insn "subsi3"
2805 [(set (match_operand:SI 0 "general_operand" "=m,r")
2806 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2807 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2812 [(set (match_operand:SI 0 "general_operand" "=a")
2813 (minus:SI (match_operand:SI 1 "general_operand" "0")
2815 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2819 (define_insn "subhi3"
2820 [(set (match_operand:HI 0 "general_operand" "=m,r")
2821 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2822 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2827 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2828 (minus:HI (match_dup 0)
2829 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2833 (define_insn "subqi3"
2834 [(set (match_operand:QI 0 "general_operand" "=m,d")
2835 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2836 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2841 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2842 (minus:QI (match_dup 0)
2843 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2847 (define_expand "subdf3"
2848 [(set (match_operand:DF 0 "general_operand" "")
2849 (minus:DF (match_operand:DF 1 "general_operand" "")
2850 (match_operand:DF 2 "general_operand" "")))]
2851 "TARGET_68881 || TARGET_FPA"
2855 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2856 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2857 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2861 if (rtx_equal_p (operands[0], operands[2]))
2862 return \"fprsub%.d %y1,%0\";
2863 if (rtx_equal_p (operands[0], operands[1]))
2864 return \"fpsub%.d %y2,%0\";
2865 if (which_alternative == 0)
2866 return \"fpsub3%.d %w2,%w1,%0\";
2867 return \"fpsub3%.d %x2,%x1,%0\";
2871 [(set (match_operand:DF 0 "general_operand" "=f")
2872 (minus:DF (match_operand:DF 1 "general_operand" "0")
2873 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2878 [(set (match_operand:DF 0 "general_operand" "=f")
2879 (minus:DF (match_operand:DF 1 "general_operand" "0")
2880 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2885 [(set (match_operand:DF 0 "general_operand" "=f")
2886 (minus:DF (match_operand:DF 1 "general_operand" "0")
2887 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2892 [(set (match_operand:DF 0 "general_operand" "=f")
2893 (minus:DF (match_operand:DF 1 "general_operand" "0")
2894 (match_operand:DF 2 "general_operand" "fmG")))]
2898 if (REG_P (operands[2]))
2899 return \"f%&sub%.x %2,%0\";
2900 return \"f%&sub%.d %f2,%0\";
2903 (define_expand "subsf3"
2904 [(set (match_operand:SF 0 "general_operand" "")
2905 (minus:SF (match_operand:SF 1 "general_operand" "")
2906 (match_operand:SF 2 "general_operand" "")))]
2907 "TARGET_68881 || TARGET_FPA"
2911 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2912 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2913 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2917 if (rtx_equal_p (operands[0], operands[2]))
2918 return \"fprsub%.s %w1,%0\";
2919 if (rtx_equal_p (operands[0], operands[1]))
2920 return \"fpsub%.s %w2,%0\";
2921 if (which_alternative == 0)
2922 return \"fpsub3%.s %w2,%w1,%0\";
2923 return \"fpsub3%.s %2,%1,%0\";
2927 [(set (match_operand:SF 0 "general_operand" "=f")
2928 (minus:SF (match_operand:SF 1 "general_operand" "0")
2929 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2934 [(set (match_operand:SF 0 "general_operand" "=f")
2935 (minus:SF (match_operand:SF 1 "general_operand" "0")
2936 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2941 [(set (match_operand:SF 0 "general_operand" "=f")
2942 (minus:SF (match_operand:SF 1 "general_operand" "0")
2943 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2948 [(set (match_operand:SF 0 "general_operand" "=f")
2949 (minus:SF (match_operand:SF 1 "general_operand" "0")
2950 (match_operand:SF 2 "general_operand" "fdmF")))]
2954 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2955 return \"f%$sub%.x %2,%0\";
2956 return \"f%$sub%.s %f2,%0\";
2959 ;; multiply instructions
2961 (define_insn "mulhi3"
2962 [(set (match_operand:HI 0 "general_operand" "=d")
2963 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2964 (match_operand:HI 2 "general_operand" "dmn")))]
2968 #if defined(MOTOROLA) && !defined(CRDS)
2969 return \"muls%.w %2,%0\";
2971 return \"muls %2,%0\";
2975 (define_insn "mulhisi3"
2976 [(set (match_operand:SI 0 "general_operand" "=d")
2977 (mult:SI (sign_extend:SI
2978 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2980 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2984 #if defined(MOTOROLA) && !defined(CRDS)
2985 return \"muls%.w %2,%0\";
2987 return \"muls %2,%0\";
2992 [(set (match_operand:SI 0 "general_operand" "=d")
2993 (mult:SI (sign_extend:SI
2994 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2995 (match_operand:SI 2 "const_int_operand" "n")))]
2996 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2999 #if defined(MOTOROLA) && !defined(CRDS)
3000 return \"muls%.w %2,%0\";
3002 return \"muls %2,%0\";
3006 (define_expand "mulsi3"
3007 [(set (match_operand:SI 0 "general_operand" "")
3008 (mult:SI (match_operand:SI 1 "general_operand" "")
3009 (match_operand:SI 2 "general_operand" "")))]
3010 "TARGET_68020 || TARGET_5200"
3014 [(set (match_operand:SI 0 "general_operand" "=d")
3015 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3016 (match_operand:SI 2 "general_operand" "dmsK")))]
3021 [(set (match_operand:SI 0 "general_operand" "=d")
3022 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3023 (match_operand:SI 2 "general_operand" "d<Q>")))]
3027 (define_insn "umulhisi3"
3028 [(set (match_operand:SI 0 "general_operand" "=d")
3029 (mult:SI (zero_extend:SI
3030 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3032 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
3036 #if defined(MOTOROLA) && !defined(CRDS)
3037 return \"mulu%.w %2,%0\";
3039 return \"mulu %2,%0\";
3044 [(set (match_operand:SI 0 "general_operand" "=d")
3045 (mult:SI (zero_extend:SI
3046 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3047 (match_operand:SI 2 "const_int_operand" "n")))]
3048 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3051 #if defined(MOTOROLA) && !defined(CRDS)
3052 return \"mulu%.w %2,%0\";
3054 return \"mulu %2,%0\";
3058 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3059 ;; proper matching constraint. This is because the matching is between
3060 ;; the high-numbered word of the DImode operand[0] and operand[1].
3061 (define_expand "umulsidi3"
3063 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3064 (mult:SI (match_operand:SI 1 "register_operand" "")
3065 (match_operand:SI 2 "nonimmediate_operand" "")))
3066 (set (subreg:SI (match_dup 0) 0)
3067 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3068 (zero_extend:DI (match_dup 2)))
3069 (const_int 32))))])]
3070 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3074 [(set (match_operand:SI 0 "register_operand" "=d")
3075 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3076 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3077 (set (match_operand:SI 3 "register_operand" "=d")
3078 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3079 (zero_extend:DI (match_dup 2)))
3081 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3084 ; Match immediate case. For 2.4 only match things < 2^31.
3085 ; It's tricky with larger values in these patterns since we need to match
3086 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3089 [(set (match_operand:SI 0 "register_operand" "=d")
3090 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3091 (match_operand:SI 2 "const_int_operand" "n")))
3092 (set (match_operand:SI 3 "register_operand" "=d")
3093 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3096 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3097 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3100 (define_expand "mulsidi3"
3102 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3103 (mult:SI (match_operand:SI 1 "register_operand" "")
3104 (match_operand:SI 2 "nonimmediate_operand" "")))
3105 (set (subreg:SI (match_dup 0) 0)
3106 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3107 (sign_extend:DI (match_dup 2)))
3108 (const_int 32))))])]
3109 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3113 [(set (match_operand:SI 0 "register_operand" "=d")
3114 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3115 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3116 (set (match_operand:SI 3 "register_operand" "=d")
3117 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3118 (sign_extend:DI (match_dup 2)))
3120 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3124 [(set (match_operand:SI 0 "register_operand" "=d")
3125 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3126 (match_operand:SI 2 "const_sint32_operand" "")))
3127 (set (match_operand:SI 3 "register_operand" "=d")
3128 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3131 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3134 (define_expand "umulsi3_highpart"
3136 [(set (match_operand:SI 0 "register_operand" "")
3139 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3140 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3142 (clobber (match_dup 3))])]
3143 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3146 operands[3] = gen_reg_rtx (SImode);
3147 if (GET_CODE (operands[2]) == CONST_INT
3148 || GET_CODE (operands[2]) == CONST_DOUBLE)
3150 if (! const_uint32_operand (operands[2], VOIDmode))
3152 /* We have to adjust the operand order for the matching constraints. */
3153 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3154 operands[1], operands[2]));
3160 [(set (match_operand:SI 0 "register_operand" "=d")
3163 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3164 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3166 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3167 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3170 (define_insn "const_umulsi3_highpart"
3171 [(set (match_operand:SI 0 "register_operand" "=d")
3174 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3175 (match_operand 3 "const_uint32_operand" ""))
3177 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3178 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3181 (define_expand "smulsi3_highpart"
3183 [(set (match_operand:SI 0 "register_operand" "")
3186 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3187 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3189 (clobber (match_dup 3))])]
3190 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3193 operands[3] = gen_reg_rtx (SImode);
3194 if (GET_CODE (operands[2]) == CONST_INT
3195 || GET_CODE (operands[2]) == CONST_DOUBLE)
3197 if (! const_sint32_operand (operands[2], VOIDmode))
3199 /* We have to adjust the operand order for the matching constraints. */
3200 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3201 operands[1], operands[2]));
3207 [(set (match_operand:SI 0 "register_operand" "=d")
3210 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3211 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3213 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3214 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3217 (define_insn "const_smulsi3_highpart"
3218 [(set (match_operand:SI 0 "register_operand" "=d")
3221 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3222 (match_operand 3 "const_sint32_operand" ""))
3224 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3225 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3228 (define_expand "muldf3"
3229 [(set (match_operand:DF 0 "general_operand" "")
3230 (mult:DF (match_operand:DF 1 "general_operand" "")
3231 (match_operand:DF 2 "general_operand" "")))]
3232 "TARGET_68881 || TARGET_FPA"
3236 [(set (match_operand:DF 0 "general_operand" "=x,y")
3237 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3238 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3242 if (rtx_equal_p (operands[1], operands[2]))
3243 return \"fpsqr%.d %y1,%0\";
3244 if (rtx_equal_p (operands[0], operands[1]))
3245 return \"fpmul%.d %y2,%0\";
3246 if (rtx_equal_p (operands[0], operands[2]))
3247 return \"fpmul%.d %y1,%0\";
3248 if (which_alternative == 0)
3249 return \"fpmul3%.d %w2,%w1,%0\";
3250 return \"fpmul3%.d %x2,%x1,%0\";
3254 [(set (match_operand:DF 0 "general_operand" "=f")
3255 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3256 (match_operand:DF 1 "general_operand" "0")))]
3261 [(set (match_operand:DF 0 "general_operand" "=f")
3262 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3263 (match_operand:DF 1 "general_operand" "0")))]
3268 [(set (match_operand:DF 0 "general_operand" "=f")
3269 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3270 (match_operand:DF 1 "general_operand" "0")))]
3275 [(set (match_operand:DF 0 "general_operand" "=f")
3276 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3277 (match_operand:DF 2 "general_operand" "fmG")))]
3281 if (GET_CODE (operands[2]) == CONST_DOUBLE
3282 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3284 int i = floating_exact_log2 (operands[2]);
3285 operands[2] = GEN_INT (i);
3286 return \"fscale%.l %2,%0\";
3288 if (REG_P (operands[2]))
3289 return \"f%&mul%.x %2,%0\";
3290 return \"f%&mul%.d %f2,%0\";
3293 (define_expand "mulsf3"
3294 [(set (match_operand:SF 0 "general_operand" "")
3295 (mult:SF (match_operand:SF 1 "general_operand" "")
3296 (match_operand:SF 2 "general_operand" "")))]
3297 "TARGET_68881 || TARGET_FPA"
3301 [(set (match_operand:SF 0 "general_operand" "=x,y")
3302 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3303 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3307 if (rtx_equal_p (operands[1], operands[2]))
3308 return \"fpsqr%.s %w1,%0\";
3309 if (rtx_equal_p (operands[0], operands[1]))
3310 return \"fpmul%.s %w2,%0\";
3311 if (rtx_equal_p (operands[0], operands[2]))
3312 return \"fpmul%.s %w1,%0\";
3313 if (which_alternative == 0)
3314 return \"fpmul3%.s %w2,%w1,%0\";
3315 return \"fpmul3%.s %2,%1,%0\";
3319 [(set (match_operand:SF 0 "general_operand" "=f")
3320 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3321 (match_operand:SF 1 "general_operand" "0")))]
3325 return (TARGET_68040_ONLY
3326 ? \"fsmul%.l %2,%0\"
3327 : \"fsglmul%.l %2,%0\");
3331 [(set (match_operand:SF 0 "general_operand" "=f")
3332 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3333 (match_operand:SF 1 "general_operand" "0")))]
3337 return (TARGET_68040_ONLY
3338 ? \"fsmul%.w %2,%0\"
3339 : \"fsglmul%.w %2,%0\");
3343 [(set (match_operand:SF 0 "general_operand" "=f")
3344 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3345 (match_operand:SF 1 "general_operand" "0")))]
3349 return (TARGET_68040_ONLY
3350 ? \"fsmul%.b %2,%0\"
3351 : \"fsglmul%.b %2,%0\");
3355 [(set (match_operand:SF 0 "general_operand" "=f")
3356 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3357 (match_operand:SF 2 "general_operand" "fdmF")))]
3361 #ifdef FSGLMUL_USE_S
3362 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3363 return (TARGET_68040_ONLY
3364 ? \"fsmul%.s %2,%0\"
3365 : \"fsglmul%.s %2,%0\");
3367 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3368 return (TARGET_68040_ONLY
3369 ? \"fsmul%.x %2,%0\"
3370 : \"fsglmul%.x %2,%0\");
3372 return (TARGET_68040_ONLY
3373 ? \"fsmul%.s %f2,%0\"
3374 : \"fsglmul%.s %f2,%0\");
3377 ;; divide instructions
3379 (define_expand "divdf3"
3380 [(set (match_operand:DF 0 "general_operand" "")
3381 (div:DF (match_operand:DF 1 "general_operand" "")
3382 (match_operand:DF 2 "general_operand" "")))]
3383 "TARGET_68881 || TARGET_FPA"
3387 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3388 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3389 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3393 if (rtx_equal_p (operands[0], operands[2]))
3394 return \"fprdiv%.d %y1,%0\";
3395 if (rtx_equal_p (operands[0], operands[1]))
3396 return \"fpdiv%.d %y2,%0\";
3397 if (which_alternative == 0)
3398 return \"fpdiv3%.d %w2,%w1,%0\";
3399 return \"fpdiv3%.d %x2,%x1,%x0\";
3403 [(set (match_operand:DF 0 "general_operand" "=f")
3404 (div:DF (match_operand:DF 1 "general_operand" "0")
3405 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3410 [(set (match_operand:DF 0 "general_operand" "=f")
3411 (div:DF (match_operand:DF 1 "general_operand" "0")
3412 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3417 [(set (match_operand:DF 0 "general_operand" "=f")
3418 (div:DF (match_operand:DF 1 "general_operand" "0")
3419 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3424 [(set (match_operand:DF 0 "general_operand" "=f")
3425 (div:DF (match_operand:DF 1 "general_operand" "0")
3426 (match_operand:DF 2 "general_operand" "fmG")))]
3430 if (REG_P (operands[2]))
3431 return \"f%&div%.x %2,%0\";
3432 return \"f%&div%.d %f2,%0\";
3435 (define_expand "divsf3"
3436 [(set (match_operand:SF 0 "general_operand" "")
3437 (div:SF (match_operand:SF 1 "general_operand" "")
3438 (match_operand:SF 2 "general_operand" "")))]
3439 "TARGET_68881 || TARGET_FPA"
3443 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3444 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3445 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3449 if (rtx_equal_p (operands[0], operands[1]))
3450 return \"fpdiv%.s %w2,%0\";
3451 if (rtx_equal_p (operands[0], operands[2]))
3452 return \"fprdiv%.s %w1,%0\";
3453 if (which_alternative == 0)
3454 return \"fpdiv3%.s %w2,%w1,%0\";
3455 return \"fpdiv3%.s %2,%1,%0\";
3459 [(set (match_operand:SF 0 "general_operand" "=f")
3460 (div:SF (match_operand:SF 1 "general_operand" "0")
3461 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3465 return (TARGET_68040_ONLY
3466 ? \"fsdiv%.l %2,%0\"
3467 : \"fsgldiv%.l %2,%0\");
3471 [(set (match_operand:SF 0 "general_operand" "=f")
3472 (div:SF (match_operand:SF 1 "general_operand" "0")
3473 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3477 return (TARGET_68040_ONLY
3478 ? \"fsdiv%.w %2,%0\"
3479 : \"fsgldiv%.w %2,%0\");
3483 [(set (match_operand:SF 0 "general_operand" "=f")
3484 (div:SF (match_operand:SF 1 "general_operand" "0")
3485 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3489 return (TARGET_68040_ONLY
3490 ? \"fsdiv%.b %2,%0\"
3491 : \"fsgldiv%.b %2,%0\");
3495 [(set (match_operand:SF 0 "general_operand" "=f")
3496 (div:SF (match_operand:SF 1 "general_operand" "0")
3497 (match_operand:SF 2 "general_operand" "fdmF")))]
3501 #ifdef FSGLDIV_USE_S
3502 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3503 return (TARGET_68040_ONLY
3504 ? \"fsdiv%.s %2,%0\"
3505 : \"fsgldiv%.s %2,%0\");
3507 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3508 return (TARGET_68040_ONLY
3509 ? \"fsdiv%.x %2,%0\"
3510 : \"fsgldiv%.x %2,%0\");
3512 return (TARGET_68040_ONLY
3513 ? \"fsdiv%.s %f2,%0\"
3514 : \"fsgldiv%.s %f2,%0\");
3517 ;; Remainder instructions.
3519 (define_insn "divmodsi4"
3520 [(set (match_operand:SI 0 "general_operand" "=d")
3521 (div:SI (match_operand:SI 1 "general_operand" "0")
3522 (match_operand:SI 2 "general_operand" "dmsK")))
3523 (set (match_operand:SI 3 "general_operand" "=d")
3524 (mod:SI (match_dup 1) (match_dup 2)))]
3525 "TARGET_68020 && !TARGET_5200"
3528 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3529 return \"divs%.l %2,%0\";
3531 return \"divsl%.l %2,%3:%0\";
3534 (define_insn "udivmodsi4"
3535 [(set (match_operand:SI 0 "general_operand" "=d")
3536 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3537 (match_operand:SI 2 "general_operand" "dmsK")))
3538 (set (match_operand:SI 3 "general_operand" "=d")
3539 (umod:SI (match_dup 1) (match_dup 2)))]
3540 "TARGET_68020 && !TARGET_5200"
3543 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3544 return \"divu%.l %2,%0\";
3546 return \"divul%.l %2,%3:%0\";
3549 (define_insn "divmodhi4"
3550 [(set (match_operand:HI 0 "general_operand" "=d")
3551 (div:HI (match_operand:HI 1 "general_operand" "0")
3552 (match_operand:HI 2 "general_operand" "dmsK")))
3553 (set (match_operand:HI 3 "general_operand" "=d")
3554 (mod:HI (match_dup 1) (match_dup 2)))]
3559 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3561 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3563 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3566 return \"move%.l %0,%3\;swap %3\";
3572 (define_insn "udivmodhi4"
3573 [(set (match_operand:HI 0 "general_operand" "=d")
3574 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3575 (match_operand:HI 2 "general_operand" "dmsK")))
3576 (set (match_operand:HI 3 "general_operand" "=d")
3577 (umod:HI (match_dup 1) (match_dup 2)))]
3582 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3584 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3586 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3589 return \"move%.l %0,%3\;swap %3\";
3595 ;; logical-and instructions
3597 ;; "anddi3" is mainly here to help combine().
3598 (define_insn "anddi3"
3599 [(set (match_operand:DI 0 "general_operand" "=o,d")
3600 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3601 (match_operand:DI 2 "general_operand" "dn,don")))]
3606 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3607 if (GET_CODE (operands[2]) == CONST_DOUBLE
3608 || GET_CODE (operands[2]) == CONST_INT)
3612 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3614 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3615 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3620 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3622 switch (INTVAL (hi))
3625 output_asm_insn (\"clr%.l %0\", operands);
3633 xoperands[0] = operands[0];
3635 output_asm_insn (output_andsi3 (xoperands), xoperands);
3638 if (GET_CODE (operands[0]) == REG)
3639 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3641 operands[0] = adj_offsettable_operand (operands[0], 4);
3642 switch (INTVAL (lo))
3645 output_asm_insn (\"clr%.l %0\", operands);
3653 xoperands[0] = operands[0];
3655 output_asm_insn (output_andsi3 (xoperands), xoperands);
3660 if (GET_CODE (operands[0]) != REG)
3662 operands[1] = adj_offsettable_operand (operands[0], 4);
3663 return \"and%.l %2,%0\;and%.l %R2,%1\";
3665 if (GET_CODE (operands[2]) != REG)
3667 operands[1] = adj_offsettable_operand (operands[2], 4);
3668 return \"and%.l %2,%0\;and%.l %1,%R0\";
3670 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3673 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3674 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3675 ;; can't allocate pseudos into it.
3677 (define_expand "andsi3"
3678 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3679 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3680 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3684 (define_insn "andsi3_internal"
3685 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3686 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3687 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3691 return output_andsi3 (operands);
3694 (define_insn "andsi3_5200"
3695 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3696 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3697 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3701 (define_insn "andhi3"
3702 [(set (match_operand:HI 0 "general_operand" "=m,d")
3703 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3704 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3709 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3710 (and:HI (match_dup 0)
3711 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3716 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3717 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3722 (define_insn "andqi3"
3723 [(set (match_operand:QI 0 "general_operand" "=m,d")
3724 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3725 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3730 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3731 (and:QI (match_dup 0)
3732 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3737 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3738 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3743 ;; inclusive-or instructions
3745 (define_insn "iordi_zext"
3746 [(set (match_operand:DI 0 "general_operand" "=o,d")
3747 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3748 (match_operand:DI 2 "general_operand" "0,0")))]
3755 if (GET_CODE (operands[0]) == REG)
3756 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3758 operands[0] = adj_offsettable_operand (operands[0], 4);
3759 if (GET_MODE (operands[1]) == SImode)
3760 return \"or%.l %1,%0\";
3761 byte_mode = (GET_MODE (operands[1]) == QImode);
3762 if (GET_CODE (operands[0]) == MEM)
3763 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3765 return \"or%.b %1,%0\";
3767 return \"or%.w %1,%0\";
3770 ;; "iordi3" is mainly here to help combine().
3771 (define_insn "iordi3"
3772 [(set (match_operand:DI 0 "general_operand" "=o,d")
3773 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3774 (match_operand:DI 2 "general_operand" "dn,don")))]
3779 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3780 if (GET_CODE (operands[2]) == CONST_DOUBLE
3781 || GET_CODE (operands[2]) == CONST_INT)
3785 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3787 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3788 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3793 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3795 switch (INTVAL (hi))
3800 /* FIXME : a scratch register would be welcome here if operand[0]
3801 is not a register */
3802 output_asm_insn (\"move%.l %#-1,%0\", operands);
3808 xoperands[0] = operands[0];
3810 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3813 if (GET_CODE (operands[0]) == REG)
3814 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3816 operands[0] = adj_offsettable_operand (operands[0], 4);
3817 switch (INTVAL (lo))
3822 /* FIXME : a scratch register would be welcome here if operand[0]
3823 is not a register */
3824 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3830 xoperands[0] = operands[0];
3832 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3837 if (GET_CODE (operands[0]) != REG)
3839 operands[1] = adj_offsettable_operand (operands[0], 4);
3840 return \"or%.l %2,%0\;or%.l %R2,%1\";
3842 if (GET_CODE (operands[2]) != REG)
3844 operands[1] = adj_offsettable_operand (operands[2], 4);
3845 return \"or%.l %2,%0\;or%.l %1,%R0\";
3847 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3850 (define_expand "iorsi3"
3851 [(set (match_operand:SI 0 "general_operand" "")
3852 (ior:SI (match_operand:SI 1 "general_operand" "")
3853 (match_operand:SI 2 "general_operand" "")))]
3857 (define_insn "iorsi3_internal"
3858 [(set (match_operand:SI 0 "general_operand" "=m,d")
3859 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3860 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3864 return output_iorsi3 (operands);
3867 (define_insn "iorsi3_5200"
3868 [(set (match_operand:SI 0 "general_operand" "=m,d")
3869 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3870 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3874 (define_insn "iorhi3"
3875 [(set (match_operand:HI 0 "general_operand" "=m,d")
3876 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3877 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3882 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3883 (ior:HI (match_dup 0)
3884 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3889 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3890 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3895 (define_insn "iorqi3"
3896 [(set (match_operand:QI 0 "general_operand" "=m,d")
3897 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3898 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3903 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3904 (ior:QI (match_dup 0)
3905 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3910 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3911 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3916 ;; On all 68k models, this makes faster code in a special case.
3917 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3919 (define_insn "iorsi_zexthi_ashl16"
3920 [(set (match_operand:SI 0 "general_operand" "=&d")
3921 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3922 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3928 if (GET_CODE (operands[2]) != REG)
3929 operands[2] = adj_offsettable_operand (operands[2], 2);
3930 if (GET_CODE (operands[2]) != REG
3931 || REGNO (operands[2]) != REGNO (operands[0]))
3932 output_asm_insn (\"move%.w %2,%0\", operands);
3933 return \"swap %0\;mov%.w %1,%0\";
3936 (define_insn "iorsi_zext"
3937 [(set (match_operand:SI 0 "general_operand" "=o,d")
3938 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3939 (match_operand:SI 2 "general_operand" "0,0")))]
3946 byte_mode = (GET_MODE (operands[1]) == QImode);
3947 if (GET_CODE (operands[0]) == MEM)
3948 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3950 return \"or%.b %1,%0\";
3952 return \"or%.w %1,%0\";
3957 ;; "xordi3" is mainly here to help combine().
3958 (define_insn "xordi3"
3959 [(set (match_operand:DI 0 "general_operand" "=od")
3960 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3961 (match_operand:DI 2 "general_operand" "dn")))]
3966 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3967 if (GET_CODE (operands[2]) == CONST_DOUBLE
3968 || GET_CODE (operands[2]) == CONST_INT)
3972 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3974 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3975 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3980 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3982 switch (INTVAL (hi))
3987 output_asm_insn (\"not%.l %0\", operands);
3990 /* FIXME : a scratch register would be welcome here if
3991 -128 <= INTVAL (hi) < -1 */
3995 xoperands[0] = operands[0];
3997 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4000 if (GET_CODE (operands[0]) == REG)
4001 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4003 operands[0] = adj_offsettable_operand (operands[0], 4);
4004 switch (INTVAL (lo))
4009 output_asm_insn (\"not%.l %0\", operands);
4012 /* FIXME : a scratch register would be welcome here if
4013 -128 <= INTVAL (lo) < -1 */
4015 /* FIXME : this should be merged with xorsi3 */
4019 xoperands[0] = operands[0];
4021 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4026 if (GET_CODE (operands[0]) != REG)
4028 operands[1] = adj_offsettable_operand (operands[0], 4);
4029 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4031 if (GET_CODE (operands[2]) != REG)
4033 operands[1] = adj_offsettable_operand (operands[2], 4);
4034 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4036 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4039 (define_expand "xorsi3"
4040 [(set (match_operand:SI 0 "general_operand" "")
4041 (xor:SI (match_operand:SI 1 "general_operand" "")
4042 (match_operand:SI 2 "general_operand" "")))]
4046 (define_insn "xorsi3_internal"
4047 [(set (match_operand:SI 0 "general_operand" "=do,m")
4048 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4049 (match_operand:SI 2 "general_operand" "di,dKs")))]
4053 return output_xorsi3 (operands);
4056 (define_insn "xorsi3_5200"
4057 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4058 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4059 (match_operand:SI 2 "general_operand" "d,Ks")))]
4063 (define_insn "xorhi3"
4064 [(set (match_operand:HI 0 "general_operand" "=dm")
4065 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4066 (match_operand:HI 2 "general_operand" "dn")))]
4071 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4072 (xor:HI (match_dup 0)
4073 (match_operand:HI 1 "general_operand" "dn")))]
4078 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4079 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4084 (define_insn "xorqi3"
4085 [(set (match_operand:QI 0 "general_operand" "=dm")
4086 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4087 (match_operand:QI 2 "general_operand" "dn")))]
4092 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4093 (xor:QI (match_dup 0)
4094 (match_operand:QI 1 "general_operand" "dn")))]
4099 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4100 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4105 ;; negation instructions
4107 (define_expand "negdi2"
4108 [(set (match_operand:DI 0 "general_operand" "")
4109 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4114 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4116 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4120 (define_insn "negdi2_internal"
4121 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4122 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4126 if (which_alternative == 0)
4127 return \"neg%.l %0\;negx%.l %0\";
4128 if (GET_CODE (operands[0]) == REG)
4129 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4131 operands[1] = adj_offsettable_operand (operands[0], 4);
4132 if (ADDRESS_REG_P (operands[0]))
4133 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4135 return \"neg%.l %1\;negx%.l %0\";
4138 (define_insn "negdi2_5200"
4139 [(set (match_operand:DI 0 "general_operand" "=d")
4140 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4144 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4145 return \"neg%.l %1\;negx%.l %0\";
4148 (define_expand "negsi2"
4149 [(set (match_operand:SI 0 "general_operand" "")
4150 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4155 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4157 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4161 (define_insn "negsi2_internal"
4162 [(set (match_operand:SI 0 "general_operand" "=dm")
4163 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4167 (define_insn "negsi2_5200"
4168 [(set (match_operand:SI 0 "general_operand" "=d")
4169 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4173 (define_insn "neghi2"
4174 [(set (match_operand:HI 0 "general_operand" "=dm")
4175 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4180 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4181 (neg:HI (match_dup 0)))]
4185 (define_insn "negqi2"
4186 [(set (match_operand:QI 0 "general_operand" "=dm")
4187 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4192 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4193 (neg:QI (match_dup 0)))]
4197 ;; If using software floating point, just flip the sign bit.
4199 (define_expand "negsf2"
4200 [(set (match_operand:SF 0 "general_operand" "")
4201 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4205 if (!TARGET_FPA && !TARGET_68881)
4210 target = operand_subword_force (operands[0], 0, SFmode);
4211 result = expand_binop (SImode, xor_optab,
4212 operand_subword_force (operands[1], 0, SFmode),
4213 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4217 if (result != target)
4218 emit_move_insn (result, target);
4220 /* Make a place for REG_EQUAL. */
4221 emit_move_insn (operands[0], operands[0]);
4227 [(set (match_operand:SF 0 "general_operand" "=x,y")
4228 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4233 [(set (match_operand:SF 0 "general_operand" "=f,d")
4234 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4238 if (DATA_REG_P (operands[0]))
4240 operands[1] = GEN_INT (31);
4241 return \"bchg %1,%0\";
4243 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4244 return \"f%$neg%.x %1,%0\";
4245 return \"f%$neg%.s %f1,%0\";
4248 (define_expand "negdf2"
4249 [(set (match_operand:DF 0 "general_operand" "")
4250 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4254 if (!TARGET_FPA && !TARGET_68881)
4261 target = operand_subword (operands[0], 0, 1, DFmode);
4262 result = expand_binop (SImode, xor_optab,
4263 operand_subword_force (operands[1], 0, DFmode),
4264 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4268 if (result != target)
4269 emit_move_insn (result, target);
4271 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4272 operand_subword_force (operands[1], 1, DFmode));
4274 insns = get_insns ();
4277 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4283 [(set (match_operand:DF 0 "general_operand" "=x,y")
4284 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4289 [(set (match_operand:DF 0 "general_operand" "=f,d")
4290 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4294 if (DATA_REG_P (operands[0]))
4296 operands[1] = GEN_INT (31);
4297 return \"bchg %1,%0\";
4299 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4300 return \"f%&neg%.x %1,%0\";
4301 return \"f%&neg%.d %f1,%0\";
4304 ;; Sqrt instruction for the 68881
4306 (define_insn "sqrtsf2"
4307 [(set (match_operand:SF 0 "general_operand" "=f")
4308 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4312 if (FP_REG_P (operands[1]))
4313 return \"f%$sqrt%.x %1,%0\";
4315 return \"f%$sqrt%.s %1,%0\";
4318 (define_insn "sqrtdf2"
4319 [(set (match_operand:DF 0 "general_operand" "=f")
4320 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4324 if (FP_REG_P (operands[1]))
4325 return \"f%&sqrt%.x %1,%0\";
4327 return \"f%&sqrt%.d %1,%0\";
4330 ;; Absolute value instructions
4331 ;; If using software floating point, just zero the sign bit.
4333 (define_expand "abssf2"
4334 [(set (match_operand:SF 0 "general_operand" "")
4335 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4339 if (!TARGET_FPA && !TARGET_68881)
4344 target = operand_subword_force (operands[0], 0, SFmode);
4345 result = expand_binop (SImode, and_optab,
4346 operand_subword_force (operands[1], 0, SFmode),
4347 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4351 if (result != target)
4352 emit_move_insn (result, target);
4354 /* Make a place for REG_EQUAL. */
4355 emit_move_insn (operands[0], operands[0]);
4361 [(set (match_operand:SF 0 "general_operand" "=x,y")
4362 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4367 [(set (match_operand:SF 0 "general_operand" "=f")
4368 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4372 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4373 return \"f%$abs%.x %1,%0\";
4374 return \"f%$abs%.s %f1,%0\";
4377 (define_expand "absdf2"
4378 [(set (match_operand:DF 0 "general_operand" "")
4379 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4383 if (!TARGET_FPA && !TARGET_68881)
4390 target = operand_subword (operands[0], 0, 1, DFmode);
4391 result = expand_binop (SImode, and_optab,
4392 operand_subword_force (operands[1], 0, DFmode),
4393 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4397 if (result != target)
4398 emit_move_insn (result, target);
4400 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4401 operand_subword_force (operands[1], 1, DFmode));
4403 insns = get_insns ();
4406 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4412 [(set (match_operand:DF 0 "general_operand" "=x,y")
4413 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4418 [(set (match_operand:DF 0 "general_operand" "=f")
4419 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4423 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4424 return \"f%&abs%.x %1,%0\";
4425 return \"f%&abs%.d %f1,%0\";
4428 ;; one complement instructions
4430 ;; "one_cmpldi2" is mainly here to help combine().
4431 (define_insn "one_cmpldi2"
4432 [(set (match_operand:DI 0 "general_operand" "=dm")
4433 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4438 if (GET_CODE (operands[0]) == REG)
4439 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4440 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4441 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4442 operands[1] = operands[0];
4444 operands[1] = adj_offsettable_operand (operands[0], 4);
4445 return \"not%.l %1\;not%.l %0\";
4448 (define_expand "one_cmplsi2"
4449 [(set (match_operand:SI 0 "general_operand" "")
4450 (not:SI (match_operand:SI 1 "general_operand" "")))]
4455 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4457 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4461 (define_insn "one_cmplsi2_internal"
4462 [(set (match_operand:SI 0 "general_operand" "=dm")
4463 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4467 (define_insn "one_cmplsi2_5200"
4468 [(set (match_operand:SI 0 "general_operand" "=d")
4469 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4473 (define_insn "one_cmplhi2"
4474 [(set (match_operand:HI 0 "general_operand" "=dm")
4475 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4480 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4481 (not:HI (match_dup 0)))]
4485 (define_insn "one_cmplqi2"
4486 [(set (match_operand:QI 0 "general_operand" "=dm")
4487 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4492 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4493 (not:QI (match_dup 0)))]
4497 ;; arithmetic shift instructions
4498 ;; We don't need the shift memory by 1 bit instruction
4500 (define_insn "ashldi_extsi"
4501 [(set (match_operand:DI 0 "general_operand" "=ro")
4503 (match_operator:DI 2 "extend_operator"
4504 [(match_operand:SI 1 "general_operand" "rm")])
4510 if (GET_CODE (operands[0]) == REG)
4511 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4513 operands[2] = adj_offsettable_operand (operands[0], 4);
4514 if (ADDRESS_REG_P (operands[0]))
4515 return \"move%.l %1,%0\;sub%.l %2,%2\";
4517 return \"move%.l %1,%0\;clr%.l %2\";
4520 (define_insn "ashldi_sexthi"
4521 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4522 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4524 (clobber (match_scratch:SI 2 "=a,X"))]
4529 if (GET_CODE (operands[0]) == MEM)
4531 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4532 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4533 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4534 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4537 operands[3] = adj_offsettable_operand (operands[0], 4);
4538 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4541 else if (DATA_REG_P (operands[0]))
4542 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4544 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4547 (define_insn "ashldi_const32"
4548 [(set (match_operand:DI 0 "general_operand" "=rm")
4549 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4555 if (GET_CODE (operands[1]) == REG)
4556 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4558 operands[3] = adj_offsettable_operand (operands[1], 4);
4559 if (GET_CODE (operands[0]) == REG)
4560 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4561 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4562 return \"clr%.l %0\;move%.l %3,%0\";
4563 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4564 return \"move%.l %3,%0\;clr%.l %0\";
4566 operands[2] = adj_offsettable_operand (operands[0], 4);
4567 if (ADDRESS_REG_P (operands[2]))
4568 return \"move%.l %3,%0\;sub%.l %2,%2\";
4570 return \"move%.l %3,%0\;clr%.l %2\";
4573 ;; The predicate below must be general_operand, because ashldi3 allows that
4574 (define_insn "ashldi_const"
4575 [(set (match_operand:DI 0 "general_operand" "=d")
4576 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4577 (match_operand 2 "const_int_operand" "n")))]
4579 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4580 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4581 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4584 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4585 if (INTVAL (operands[2]) == 1)
4586 return \"add%.l %1,%1\;addx%.l %0,%0\";
4587 else if (INTVAL (operands[2]) == 8)
4588 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4589 else if (INTVAL (operands[2]) == 16)
4590 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4591 else if (INTVAL (operands[2]) == 48)
4592 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4593 else if (INTVAL (operands[2]) == 2)
4594 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4595 else if (INTVAL (operands[2]) == 3)
4596 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4597 else /* 32 < INTVAL (operands[2]) <= 63 */
4599 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4600 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4601 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4602 return \"mov%.l %1,%0\;moveq %#0,%1\";
4606 (define_expand "ashldi3"
4607 [(set (match_operand:DI 0 "general_operand" "")
4608 (ashift:DI (match_operand:DI 1 "general_operand" "")
4609 (match_operand 2 "const_int_operand" "")))]
4613 /* ??? This is a named pattern like this is not allowed to FAIL based
4615 if (GET_CODE (operands[2]) != CONST_INT
4616 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4617 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4618 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4622 ;; On most 68k models, this makes faster code in a special case.
4624 (define_insn "ashlsi_16"
4625 [(set (match_operand:SI 0 "register_operand" "=d")
4626 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4632 return \"swap %0\;clr%.w %0\";
4635 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4636 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4638 ;; On the 68000, this makes faster code in a special case.
4640 (define_insn "ashlsi_17_24"
4641 [(set (match_operand:SI 0 "register_operand" "=d")
4642 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4643 (match_operand:SI 2 "const_int_operand" "n")))]
4644 "(! TARGET_68020 && !TARGET_5200
4645 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4650 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4651 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4654 (define_insn "ashlsi3"
4655 [(set (match_operand:SI 0 "register_operand" "=d")
4656 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4657 (match_operand:SI 2 "general_operand" "dI")))]
4661 if (operands[2] == const1_rtx)
4663 cc_status.flags = CC_NO_OVERFLOW;
4664 return \"add%.l %0,%0\";
4666 return \"lsl%.l %2,%0\";
4669 (define_insn "ashlhi3"
4670 [(set (match_operand:HI 0 "register_operand" "=d")
4671 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4672 (match_operand:HI 2 "general_operand" "dI")))]
4677 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4678 (ashift:HI (match_dup 0)
4679 (match_operand:HI 1 "general_operand" "dI")))]
4683 (define_insn "ashlqi3"
4684 [(set (match_operand:QI 0 "register_operand" "=d")
4685 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4686 (match_operand:QI 2 "general_operand" "dI")))]
4691 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4692 (ashift:QI (match_dup 0)
4693 (match_operand:QI 1 "general_operand" "dI")))]
4697 ;; On most 68k models, this makes faster code in a special case.
4699 (define_insn "ashrsi_16"
4700 [(set (match_operand:SI 0 "register_operand" "=d")
4701 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4704 "swap %0\;ext%.l %0")
4706 ;; On the 68000, this makes faster code in a special case.
4709 [(set (match_operand:SI 0 "register_operand" "=d")
4710 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4711 (match_operand:SI 2 "const_int_operand" "n")))]
4712 "(! TARGET_68020 && !TARGET_5200
4713 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4716 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4717 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4720 (define_insn "subreghi1ashrdi_const32"
4721 [(set (match_operand:HI 0 "general_operand" "=rm")
4722 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4723 (const_int 32)) 1))]
4727 if (GET_CODE (operands[1]) != REG)
4728 operands[1] = adj_offsettable_operand (operands[1], 2);
4729 return \"move%.w %1,%0\";
4732 (define_insn "subregsi1ashrdi_const32"
4733 [(set (match_operand:SI 0 "general_operand" "=rm")
4734 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4735 (const_int 32)) 1))]
4739 return \"move%.l %1,%0\";
4742 (define_insn "ashrdi_const32"
4743 [(set (match_operand:DI 0 "register_operand" "=d")
4744 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4750 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4752 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4754 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4757 (define_insn "ashrdi_const32_mem"
4758 [(set (match_operand:DI 0 "general_operand" "=o,<")
4759 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4761 (clobber (match_scratch:SI 2 "=d,d"))]
4766 if (which_alternative == 1)
4767 operands[3] = operands[0];
4769 operands[3] = adj_offsettable_operand (operands[0], 4);
4771 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4773 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4776 ;; The predicate below must be general_operand, because ashrdi3 allows that
4777 (define_insn "ashrdi_const"
4778 [(set (match_operand:DI 0 "general_operand" "=d")
4779 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4780 (match_operand 2 "const_int_operand" "n")))]
4782 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4783 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4784 || INTVAL (operands[2]) == 31
4785 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4788 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4789 if (INTVAL (operands[2]) == 63)
4790 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4792 if (INTVAL (operands[2]) == 1)
4793 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4794 else if (INTVAL (operands[2]) == 8)
4795 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4796 else if (INTVAL (operands[2]) == 16)
4797 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4798 else if (INTVAL (operands[2]) == 48)
4799 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4800 else if (INTVAL (operands[2]) == 31)
4801 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4802 else if (INTVAL (operands[2]) == 2)
4803 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4804 else if (INTVAL (operands[2]) == 3)
4805 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4806 else /* 32 < INTVAL (operands[2]) <= 63 */
4808 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4809 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4810 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4811 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4812 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4813 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4817 (define_expand "ashrdi3"
4818 [(set (match_operand:DI 0 "general_operand" "")
4819 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4820 (match_operand 2 "const_int_operand" "")))]
4824 /* ??? This is a named pattern like this is not allowed to FAIL based
4826 if (GET_CODE (operands[2]) != CONST_INT
4827 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4828 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4829 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4833 ;; On all 68k models, this makes faster code in a special case.
4835 (define_insn "ashrsi_31"
4836 [(set (match_operand:SI 0 "register_operand" "=d")
4837 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4842 return \"add%.l %0,%0\;subx%.l %0,%0\";
4845 (define_insn "ashrsi3"
4846 [(set (match_operand:SI 0 "register_operand" "=d")
4847 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4848 (match_operand:SI 2 "general_operand" "dI")))]
4852 (define_insn "ashrhi3"
4853 [(set (match_operand:HI 0 "register_operand" "=d")
4854 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4855 (match_operand:HI 2 "general_operand" "dI")))]
4860 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4861 (ashiftrt:HI (match_dup 0)
4862 (match_operand:HI 1 "general_operand" "dI")))]
4866 (define_insn "ashrqi3"
4867 [(set (match_operand:QI 0 "register_operand" "=d")
4868 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4869 (match_operand:QI 2 "general_operand" "dI")))]
4874 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4875 (ashiftrt:QI (match_dup 0)
4876 (match_operand:QI 1 "general_operand" "dI")))]
4880 ;; logical shift instructions
4882 ;; commented out because of reload problems in 950612-1.c
4885 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4886 ;; (const_int 32)) 1))
4887 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4888 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4889 ;; (const_int 32)) 1))]
4893 ;; return \"move%.l %0,%1\";
4898 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4899 ;; (const_int 32)) 0))
4900 ;; (set (match_operand:DI 1 "general_operand" "=do")
4901 ;; (lshiftrt:DI (match_dup 0)
4902 ;; (const_int 32)))]
4906 ;; if (GET_CODE (operands[1]) == REG)
4907 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4909 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4910 ;; return \"move%.l %0,%2\;clr%.l %1\";
4913 (define_insn "subreg1lshrdi_const32"
4914 [(set (match_operand:SI 0 "general_operand" "=rm")
4915 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4916 (const_int 32)) 1))]
4920 return \"move%.l %1,%0\";
4923 (define_insn "lshrdi_const32"
4924 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4925 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4931 if (which_alternative == 1)
4932 return \"move%.l %1,%0\;clr%.l %0\";
4933 if (which_alternative == 2)
4934 return \"clr%.l %0\;move%.l %1,%0\";
4935 if (GET_CODE (operands[0]) == REG)
4936 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4938 operands[2] = adj_offsettable_operand (operands[0], 4);
4939 if (GET_CODE (operands[1]) == REG)
4940 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4942 operands[3] = adj_offsettable_operand (operands[1], 4);
4943 if (ADDRESS_REG_P (operands[0]))
4944 return \"move%.l %1,%2\;sub%.l %0,%0\";
4946 return \"move%.l %1,%2\;clr%.l %0\";
4949 ;; The predicate below must be general_operand, because lshrdi3 allows that
4950 (define_insn "lshrdi_const"
4951 [(set (match_operand:DI 0 "general_operand" "=d")
4952 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4953 (match_operand 2 "const_int_operand" "n")))]
4955 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4956 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4957 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
4960 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4961 if (INTVAL (operands[2]) == 63)
4962 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4964 if (INTVAL (operands[2]) == 1)
4965 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4966 else if (INTVAL (operands[2]) == 8)
4967 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4968 else if (INTVAL (operands[2]) == 16)
4969 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4970 else if (INTVAL (operands[2]) == 48)
4971 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4972 else if (INTVAL (operands[2]) == 2)
4973 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4974 else if (INTVAL (operands[2]) == 3)
4975 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4976 else /* 32 < INTVAL (operands[2]) <= 63 */
4978 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4979 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4980 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4981 return \"mov%.l %0,%1\;moveq %#0,%0\";
4985 (define_expand "lshrdi3"
4986 [(set (match_operand:DI 0 "general_operand" "")
4987 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4988 (match_operand 2 "const_int_operand" "")))]
4992 /* ??? This is a named pattern like this is not allowed to FAIL based
4994 if (GET_CODE (operands[2]) != CONST_INT
4995 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4996 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4997 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5001 ;; On all 68k models, this makes faster code in a special case.
5003 (define_insn "lshrsi_31"
5004 [(set (match_operand:SI 0 "register_operand" "=d")
5005 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5010 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
5013 ;; On most 68k models, this makes faster code in a special case.
5015 (define_insn "lshrsi_16"
5016 [(set (match_operand:SI 0 "register_operand" "=d")
5017 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5023 return \"clr%.w %0\;swap %0\";
5026 ;; On the 68000, this makes faster code in a special case.
5028 (define_insn "lshrsi_17_24"
5029 [(set (match_operand:SI 0 "register_operand" "=d")
5030 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5031 (match_operand:SI 2 "const_int_operand" "n")))]
5032 "(! TARGET_68020 && !TARGET_5200
5033 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
5036 /* I think lsr%.w sets the CC properly. */
5037 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5038 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5041 (define_insn "lshrsi3"
5042 [(set (match_operand:SI 0 "register_operand" "=d")
5043 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5044 (match_operand:SI 2 "general_operand" "dI")))]
5048 (define_insn "lshrhi3"
5049 [(set (match_operand:HI 0 "register_operand" "=d")
5050 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5051 (match_operand:HI 2 "general_operand" "dI")))]
5056 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5057 (lshiftrt:HI (match_dup 0)
5058 (match_operand:HI 1 "general_operand" "dI")))]
5062 (define_insn "lshrqi3"
5063 [(set (match_operand:QI 0 "register_operand" "=d")
5064 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5065 (match_operand:QI 2 "general_operand" "dI")))]
5070 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5071 (lshiftrt:QI (match_dup 0)
5072 (match_operand:QI 1 "general_operand" "dI")))]
5076 ;; rotate instructions
5078 (define_insn "rotlsi3"
5079 [(set (match_operand:SI 0 "register_operand" "=d")
5080 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5081 (match_operand:SI 2 "general_operand" "dINO")))]
5085 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5087 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5089 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5090 return \"ror%.l %2,%0\";
5093 return \"rol%.l %2,%0\";
5096 (define_insn "rotlhi3"
5097 [(set (match_operand:HI 0 "register_operand" "=d")
5098 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5099 (match_operand:HI 2 "general_operand" "dIP")))]
5103 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5105 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5106 return \"ror%.w %2,%0\";
5109 return \"rol%.w %2,%0\";
5113 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5114 (rotate:HI (match_dup 0)
5115 (match_operand:HI 1 "general_operand" "dIP")))]
5119 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5121 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5122 return \"ror%.w %2,%0\";
5125 return \"rol%.w %2,%0\";
5128 (define_insn "rotlqi3"
5129 [(set (match_operand:QI 0 "register_operand" "=d")
5130 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5131 (match_operand:QI 2 "general_operand" "dI")))]
5135 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5137 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5138 return \"ror%.b %2,%0\";
5141 return \"rol%.b %2,%0\";
5145 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5146 (rotate:QI (match_dup 0)
5147 (match_operand:QI 1 "general_operand" "dI")))]
5151 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5153 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5154 return \"ror%.b %2,%0\";
5157 return \"rol%.b %2,%0\";
5160 (define_insn "rotrsi3"
5161 [(set (match_operand:SI 0 "register_operand" "=d")
5162 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5163 (match_operand:SI 2 "general_operand" "dI")))]
5167 (define_insn "rotrhi3"
5168 [(set (match_operand:HI 0 "register_operand" "=d")
5169 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5170 (match_operand:HI 2 "general_operand" "dI")))]
5175 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5176 (rotatert:HI (match_dup 0)
5177 (match_operand:HI 1 "general_operand" "dI")))]
5181 (define_insn "rotrqi3"
5182 [(set (match_operand:QI 0 "register_operand" "=d")
5183 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5184 (match_operand:QI 2 "general_operand" "dI")))]
5189 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5190 (rotatert:QI (match_dup 0)
5191 (match_operand:QI 1 "general_operand" "dI")))]
5196 ;; Bit set/clear in memory byte.
5198 ;; set bit, bit number is int
5199 (define_insn "bsetmemqi"
5200 [(set (match_operand:QI 0 "memory_operand" "+m")
5201 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5202 (match_operand:SI 1 "general_operand" "d")) 0)
5208 return \"bset %1,%0\";
5211 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5213 [(set (match_operand:QI 0 "memory_operand" "+m")
5214 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5215 (match_operator:SI 2 "extend_operator"
5216 [(match_operand 1 "general_operand" "d")])) 0)
5222 return \"bset %1,%0\";
5225 ;; clear bit, bit number is int
5226 (define_insn "bclrmemqi"
5227 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5229 (minus:SI (const_int 7)
5230 (match_operand:SI 1 "general_operand" "d")))
5236 return \"bclr %1,%0\";
5239 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5241 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5243 (minus:SI (const_int 7)
5244 (match_operator:SI 2 "extend_operator"
5245 [(match_operand 1 "general_operand" "d")])))
5251 return \"bclr %1,%0\";
5254 ;; Special cases of bit-field insns which we should
5255 ;; recognize in preference to the general case.
5256 ;; These handle aligned 8-bit and 16-bit fields,
5257 ;; which can usually be done with move instructions.
5260 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5261 ; alignment of structure members is specified.
5263 ; The move is allowed to be odd byte aligned, because that's still faster
5264 ; than an odd byte aligned bit field instruction.
5267 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5269 (match_operand:SI 2 "const_int_operand" "n"))
5270 (match_operand:SI 3 "general_operand" "rmi"))]
5271 "TARGET_68020 && TARGET_BITFIELD
5272 && (INTVAL (operands[2]) % 8) == 0
5273 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5277 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5279 return \"move%.l %3,%0\";
5283 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5284 (match_operand:SI 1 "const_int_operand" "n")
5285 (match_operand:SI 2 "const_int_operand" "n"))
5286 (match_operand:SI 3 "register_operand" "d"))]
5287 "TARGET_68020 && TARGET_BITFIELD
5288 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5289 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5290 && (GET_CODE (operands[0]) == REG
5291 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5294 if (REG_P (operands[0]))
5296 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5297 return \"bfins %3,%0{%b2:%b1}\";
5301 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5303 if (GET_CODE (operands[3]) == MEM)
5304 operands[3] = adj_offsettable_operand (operands[3],
5305 (32 - INTVAL (operands[1])) / 8);
5306 if (INTVAL (operands[1]) == 8)
5307 return \"move%.b %3,%0\";
5308 return \"move%.w %3,%0\";
5313 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5314 ; alignment of structure members is specified.
5316 ; The move is allowed to be odd byte aligned, because that's still faster
5317 ; than an odd byte aligned bit field instruction.
5320 [(set (match_operand:SI 0 "general_operand" "=rm")
5321 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5323 (match_operand:SI 3 "const_int_operand" "n")))]
5324 "TARGET_68020 && TARGET_BITFIELD
5325 && (INTVAL (operands[3]) % 8) == 0
5326 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5330 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5332 return \"move%.l %1,%0\";
5336 [(set (match_operand:SI 0 "general_operand" "=&d")
5337 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5338 (match_operand:SI 2 "const_int_operand" "n")
5339 (match_operand:SI 3 "const_int_operand" "n")))]
5340 "TARGET_68020 && TARGET_BITFIELD
5341 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5342 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5343 && (GET_CODE (operands[1]) == REG
5344 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5347 cc_status.flags |= CC_NOT_NEGATIVE;
5348 if (REG_P (operands[1]))
5350 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5351 return \"bfextu %1{%b3:%b2},%0\";
5355 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5357 output_asm_insn (\"clr%.l %0\", operands);
5358 if (GET_CODE (operands[0]) == MEM)
5359 operands[0] = adj_offsettable_operand (operands[0],
5360 (32 - INTVAL (operands[1])) / 8);
5361 if (INTVAL (operands[2]) == 8)
5362 return \"move%.b %1,%0\";
5363 return \"move%.w %1,%0\";
5367 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5368 ; alignment of structure members is specified.
5370 ; The move is allowed to be odd byte aligned, because that's still faster
5371 ; than an odd byte aligned bit field instruction.
5374 [(set (match_operand:SI 0 "general_operand" "=rm")
5375 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5377 (match_operand:SI 3 "const_int_operand" "n")))]
5378 "TARGET_68020 && TARGET_BITFIELD
5379 && (INTVAL (operands[3]) % 8) == 0
5380 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5384 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5386 return \"move%.l %1,%0\";
5390 [(set (match_operand:SI 0 "general_operand" "=d")
5391 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5392 (match_operand:SI 2 "const_int_operand" "n")
5393 (match_operand:SI 3 "const_int_operand" "n")))]
5394 "TARGET_68020 && TARGET_BITFIELD
5395 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5396 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5397 && (GET_CODE (operands[1]) == REG
5398 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5401 if (REG_P (operands[1]))
5403 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5404 return \"bfexts %1{%b3:%b2},%0\";
5408 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5410 if (INTVAL (operands[2]) == 8)
5411 return \"move%.b %1,%0\;extb%.l %0\";
5412 return \"move%.w %1,%0\;ext%.l %0\";
5415 ;; Bit field instructions, general cases.
5416 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5417 ;; so that its address is reloaded.
5419 (define_expand "extv"
5420 [(set (match_operand:SI 0 "general_operand" "")
5421 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5422 (match_operand:SI 2 "general_operand" "")
5423 (match_operand:SI 3 "general_operand" "")))]
5424 "TARGET_68020 && TARGET_BITFIELD"
5428 [(set (match_operand:SI 0 "general_operand" "=d")
5429 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5430 (match_operand:SI 2 "general_operand" "di")
5431 (match_operand:SI 3 "general_operand" "di")))]
5432 "TARGET_68020 && TARGET_BITFIELD"
5433 "bfexts %1{%b3:%b2},%0")
5435 (define_expand "extzv"
5436 [(set (match_operand:SI 0 "general_operand" "")
5437 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5438 (match_operand:SI 2 "general_operand" "")
5439 (match_operand:SI 3 "general_operand" "")))]
5440 "TARGET_68020 && TARGET_BITFIELD"
5444 [(set (match_operand:SI 0 "general_operand" "=d,d")
5445 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5446 (match_operand:SI 2 "general_operand" "di,di")
5447 (match_operand:SI 3 "general_operand" "di,di")))]
5448 "TARGET_68020 && TARGET_BITFIELD"
5451 if (GET_CODE (operands[2]) == CONST_INT)
5453 if (INTVAL (operands[2]) != 32)
5454 cc_status.flags |= CC_NOT_NEGATIVE;
5460 return \"bfextu %1{%b3:%b2},%0\";
5464 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5465 (match_operand:SI 1 "general_operand" "di")
5466 (match_operand:SI 2 "general_operand" "di"))
5467 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5468 (match_operand 3 "const_int_operand" "n")))]
5469 "TARGET_68020 && TARGET_BITFIELD
5470 && (INTVAL (operands[3]) == -1
5471 || (GET_CODE (operands[1]) == CONST_INT
5472 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5476 return \"bfchg %0{%b2:%b1}\";
5480 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5481 (match_operand:SI 1 "general_operand" "di")
5482 (match_operand:SI 2 "general_operand" "di"))
5484 "TARGET_68020 && TARGET_BITFIELD"
5488 return \"bfclr %0{%b2:%b1}\";
5492 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5493 (match_operand:SI 1 "general_operand" "di")
5494 (match_operand:SI 2 "general_operand" "di"))
5496 "TARGET_68020 && TARGET_BITFIELD"
5500 return \"bfset %0{%b2:%b1}\";
5503 (define_expand "insv"
5504 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5505 (match_operand:SI 1 "general_operand" "")
5506 (match_operand:SI 2 "general_operand" ""))
5507 (match_operand:SI 3 "register_operand" ""))]
5508 "TARGET_68020 && TARGET_BITFIELD"
5512 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5513 (match_operand:SI 1 "general_operand" "di")
5514 (match_operand:SI 2 "general_operand" "di"))
5515 (match_operand:SI 3 "register_operand" "d"))]
5516 "TARGET_68020 && TARGET_BITFIELD"
5517 "bfins %3,%0{%b2:%b1}")
5519 ;; Now recognize bit field insns that operate on registers
5520 ;; (or at least were intended to do so).
5523 [(set (match_operand:SI 0 "general_operand" "=d")
5524 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5525 (match_operand:SI 2 "general_operand" "di")
5526 (match_operand:SI 3 "general_operand" "di")))]
5527 "TARGET_68020 && TARGET_BITFIELD"
5528 "bfexts %1{%b3:%b2},%0")
5531 [(set (match_operand:SI 0 "general_operand" "=d")
5532 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5533 (match_operand:SI 2 "general_operand" "di")
5534 (match_operand:SI 3 "general_operand" "di")))]
5535 "TARGET_68020 && TARGET_BITFIELD"
5538 if (GET_CODE (operands[2]) == CONST_INT)
5540 if (INTVAL (operands[2]) != 32)
5541 cc_status.flags |= CC_NOT_NEGATIVE;
5547 return \"bfextu %1{%b3:%b2},%0\";
5551 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5552 (match_operand:SI 1 "general_operand" "di")
5553 (match_operand:SI 2 "general_operand" "di"))
5555 "TARGET_68020 && TARGET_BITFIELD"
5559 return \"bfclr %0{%b2:%b1}\";
5563 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5564 (match_operand:SI 1 "general_operand" "di")
5565 (match_operand:SI 2 "general_operand" "di"))
5567 "TARGET_68020 && TARGET_BITFIELD"
5571 return \"bfset %0{%b2:%b1}\";
5575 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5576 (match_operand:SI 1 "general_operand" "di")
5577 (match_operand:SI 2 "general_operand" "di"))
5578 (match_operand:SI 3 "register_operand" "d"))]
5579 "TARGET_68020 && TARGET_BITFIELD"
5583 /* These special cases are now recognized by a specific pattern. */
5584 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5585 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5586 return \"move%.w %3,%0\";
5587 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5588 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5589 return \"move%.b %3,%0\";
5591 return \"bfins %3,%0{%b2:%b1}\";
5594 ;; Special patterns for optimizing bit-field instructions.
5598 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5599 (match_operand:SI 1 "const_int_operand" "n")
5600 (match_operand:SI 2 "general_operand" "di")))]
5601 "TARGET_68020 && TARGET_BITFIELD"
5604 if (operands[1] == const1_rtx
5605 && GET_CODE (operands[2]) == CONST_INT)
5607 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5608 return output_btst (operands,
5609 GEN_INT (width - INTVAL (operands[2])),
5612 /* Pass 1000 as SIGNPOS argument so that btst will
5613 not think we are testing the sign bit for an `and'
5614 and assume that nonzero implies a negative result. */
5616 if (INTVAL (operands[1]) != 32)
5617 cc_status.flags = CC_NOT_NEGATIVE;
5618 return \"bftst %0{%b2:%b1}\";
5622 ;;; now handle the register cases
5625 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5626 (match_operand:SI 1 "const_int_operand" "n")
5627 (match_operand:SI 2 "general_operand" "di")))]
5628 "TARGET_68020 && TARGET_BITFIELD"
5631 if (operands[1] == const1_rtx
5632 && GET_CODE (operands[2]) == CONST_INT)
5634 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5635 return output_btst (operands,
5636 GEN_INT (width - INTVAL (operands[2])),
5639 /* Pass 1000 as SIGNPOS argument so that btst will
5640 not think we are testing the sign bit for an `and'
5641 and assume that nonzero implies a negative result. */
5643 if (INTVAL (operands[1]) != 32)
5644 cc_status.flags = CC_NOT_NEGATIVE;
5645 return \"bftst %0{%b2:%b1}\";
5648 (define_insn "scc0_di"
5649 [(set (match_operand:QI 0 "general_operand" "=dm")
5650 (match_operator 1 "valid_dbcc_comparison_p"
5651 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5655 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5658 (define_insn "scc0_di_5200"
5659 [(set (match_operand:QI 0 "general_operand" "=d")
5660 (match_operator 1 "valid_dbcc_comparison_p"
5661 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5665 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5668 (define_insn "scc_di"
5669 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5670 (match_operator 1 "valid_dbcc_comparison_p"
5671 [(match_operand:DI 2 "general_operand" "ro,r")
5672 (match_operand:DI 3 "general_operand" "r,ro")]))]
5676 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5679 (define_insn "scc_di_5200"
5680 [(set (match_operand:QI 0 "general_operand" "=d,d")
5681 (match_operator 1 "valid_dbcc_comparison_p"
5682 [(match_operand:DI 2 "general_operand" "ro,r")
5683 (match_operand:DI 3 "general_operand" "r,ro")]))]
5687 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5690 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5691 ;; memory, but we cannot allow it to be in memory in case the address
5692 ;; needs to be reloaded.
5694 (define_expand "seq"
5695 [(set (match_operand:QI 0 "register_operand" "")
5696 (eq:QI (cc0) (const_int 0)))]
5700 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5702 m68k_last_compare_had_fp_operands = 0;
5708 [(set (match_operand:QI 0 "register_operand" "=d")
5709 (eq:QI (cc0) (const_int 0)))]
5712 cc_status = cc_prev_status;
5713 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5716 (define_expand "sne"
5717 [(set (match_operand:QI 0 "register_operand" "")
5718 (ne:QI (cc0) (const_int 0)))]
5722 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5724 m68k_last_compare_had_fp_operands = 0;
5730 [(set (match_operand:QI 0 "register_operand" "=d")
5731 (ne:QI (cc0) (const_int 0)))]
5734 cc_status = cc_prev_status;
5735 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5738 (define_expand "sgt"
5739 [(set (match_operand:QI 0 "register_operand" "")
5740 (gt:QI (cc0) (const_int 0)))]
5744 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5746 m68k_last_compare_had_fp_operands = 0;
5752 [(set (match_operand:QI 0 "register_operand" "=d")
5753 (gt:QI (cc0) (const_int 0)))]
5756 cc_status = cc_prev_status;
5757 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5760 (define_expand "sgtu"
5761 [(set (match_operand:QI 0 "register_operand" "")
5762 (gtu:QI (cc0) (const_int 0)))]
5767 [(set (match_operand:QI 0 "register_operand" "=d")
5768 (gtu:QI (cc0) (const_int 0)))]
5771 cc_status = cc_prev_status;
5772 return \"shi %0\"; ")
5774 (define_expand "slt"
5775 [(set (match_operand:QI 0 "register_operand" "")
5776 (lt:QI (cc0) (const_int 0)))]
5780 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5782 m68k_last_compare_had_fp_operands = 0;
5788 [(set (match_operand:QI 0 "register_operand" "=d")
5789 (lt:QI (cc0) (const_int 0)))]
5792 cc_status = cc_prev_status;
5793 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5795 (define_expand "sltu"
5796 [(set (match_operand:QI 0 "register_operand" "")
5797 (ltu:QI (cc0) (const_int 0)))]
5802 [(set (match_operand:QI 0 "register_operand" "=d")
5803 (ltu:QI (cc0) (const_int 0)))]
5806 cc_status = cc_prev_status;
5807 return \"scs %0\"; ")
5809 (define_expand "sge"
5810 [(set (match_operand:QI 0 "register_operand" "")
5811 (ge:QI (cc0) (const_int 0)))]
5815 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5817 m68k_last_compare_had_fp_operands = 0;
5823 [(set (match_operand:QI 0 "register_operand" "=d")
5824 (ge:QI (cc0) (const_int 0)))]
5827 cc_status = cc_prev_status;
5828 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5830 (define_expand "sgeu"
5831 [(set (match_operand:QI 0 "register_operand" "")
5832 (geu:QI (cc0) (const_int 0)))]
5837 [(set (match_operand:QI 0 "register_operand" "=d")
5838 (geu:QI (cc0) (const_int 0)))]
5841 cc_status = cc_prev_status;
5842 return \"scc %0\"; ")
5844 (define_expand "sle"
5845 [(set (match_operand:QI 0 "register_operand" "")
5846 (le:QI (cc0) (const_int 0)))]
5850 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5852 m68k_last_compare_had_fp_operands = 0;
5858 [(set (match_operand:QI 0 "register_operand" "=d")
5859 (le:QI (cc0) (const_int 0)))]
5862 cc_status = cc_prev_status;
5863 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5866 (define_expand "sleu"
5867 [(set (match_operand:QI 0 "register_operand" "")
5868 (leu:QI (cc0) (const_int 0)))]
5873 [(set (match_operand:QI 0 "register_operand" "=d")
5874 (leu:QI (cc0) (const_int 0)))]
5877 cc_status = cc_prev_status;
5878 return \"sls %0\"; ")
5880 ;; Basic conditional jump instructions.
5882 (define_insn "beq0_di"
5884 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5886 (label_ref (match_operand 1 "" ","))
5888 (clobber (match_scratch:SI 2 "=d,d"))]
5893 if (which_alternative == 1)
5895 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5897 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5899 if ((cc_prev_status.value1
5900 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5901 || (cc_prev_status.value2
5902 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5904 cc_status = cc_prev_status;
5906 return \"jbeq %l1\";
5911 if (GET_CODE (operands[0]) == REG)
5912 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5914 operands[3] = adj_offsettable_operand (operands[0], 4);
5915 if (! ADDRESS_REG_P (operands[0]))
5917 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5919 if (reg_overlap_mentioned_p (operands[2], operands[3]))
5922 return \"or%.l %0,%2\;jbeq %l1\";
5924 return \"or%.l %0,%2\;jeq %l1\";
5930 return \"or%.l %3,%2\;jbeq %l1\";
5932 return \"or%.l %3,%2\;jeq %l1\";
5937 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5939 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5942 operands[4] = gen_label_rtx();
5943 if (TARGET_68020 || TARGET_5200)
5946 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5948 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5954 #ifdef SGS_CMP_ORDER
5955 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5957 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5960 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5963 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5964 CODE_LABEL_NUMBER (operands[4]));
5968 (define_insn "bne0_di"
5970 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5972 (label_ref (match_operand 1 "" ","))
5974 (clobber (match_scratch:SI 2 "=d,X"))]
5978 if ((cc_prev_status.value1
5979 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5980 || (cc_prev_status.value2
5981 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5983 cc_status = cc_prev_status;
5985 return \"jbne %l1\";
5991 if (GET_CODE (operands[0]) == REG)
5992 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5994 operands[3] = adj_offsettable_operand (operands[0], 4);
5995 if (!ADDRESS_REG_P (operands[0]))
5997 if (reg_overlap_mentioned_p (operands[2], operands[0]))
5999 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6002 return \"or%.l %0,%2\;jbne %l1\";
6004 return \"or%.l %0,%2\;jne %l1\";
6010 return \"or%.l %3,%2\;jbne %l1\";
6012 return \"or%.l %3,%2\;jne %l1\";
6017 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6019 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6022 if (TARGET_68020 || TARGET_5200)
6025 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6027 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6033 #ifdef SGS_CMP_ORDER
6034 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6036 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6039 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6044 (define_insn "bge0_di"
6046 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6048 (label_ref (match_operand 1 "" ""))
6053 if ((cc_prev_status.value1
6054 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6055 || (cc_prev_status.value2
6056 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6058 cc_status = cc_prev_status;
6059 if (cc_status.flags & CC_REVERSED)
6062 return \"jble %l1\";
6070 return \"jbpl %l1\";
6077 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6078 output_asm_insn(\"tst%.l %0\", operands);
6081 /* On an address reg, cmpw may replace cmpl. */
6082 #ifdef SGS_CMP_ORDER
6083 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6085 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6090 return \"jbpl %l1\";
6096 (define_insn "blt0_di"
6098 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6100 (label_ref (match_operand 1 "" ""))
6105 if ((cc_prev_status.value1
6106 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6107 || (cc_prev_status.value2
6108 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6110 cc_status = cc_prev_status;
6111 if (cc_status.flags & CC_REVERSED)
6114 return \"jbgt %l1\";
6122 return \"jbmi %l1\";
6129 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6130 output_asm_insn(\"tst%.l %0\", operands);
6133 /* On an address reg, cmpw may replace cmpl. */
6134 #ifdef SGS_CMP_ORDER
6135 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6137 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6142 return \"jbmi %l1\";
6150 (if_then_else (eq (cc0)
6152 (label_ref (match_operand 0 "" ""))
6158 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6160 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6166 (if_then_else (ne (cc0)
6168 (label_ref (match_operand 0 "" ""))
6174 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6176 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6182 (if_then_else (gt (cc0)
6184 (label_ref (match_operand 0 "" ""))
6189 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6191 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6197 (if_then_else (gtu (cc0)
6199 (label_ref (match_operand 0 "" ""))
6204 return \"jbhi %l0\";
6212 (if_then_else (lt (cc0)
6214 (label_ref (match_operand 0 "" ""))
6219 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6221 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6227 (if_then_else (ltu (cc0)
6229 (label_ref (match_operand 0 "" ""))
6234 return \"jbcs %l0\";
6242 (if_then_else (ge (cc0)
6244 (label_ref (match_operand 0 "" ""))
6249 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6251 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6257 (if_then_else (geu (cc0)
6259 (label_ref (match_operand 0 "" ""))
6264 return \"jbcc %l0\";
6272 (if_then_else (le (cc0)
6274 (label_ref (match_operand 0 "" ""))
6279 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6281 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6287 (if_then_else (leu (cc0)
6289 (label_ref (match_operand 0 "" ""))
6294 return \"jbls %l0\";
6300 ;; Negated conditional jump instructions.
6304 (if_then_else (eq (cc0)
6307 (label_ref (match_operand 0 "" ""))))]
6312 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6314 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6320 (if_then_else (ne (cc0)
6323 (label_ref (match_operand 0 "" ""))))]
6328 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6330 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6336 (if_then_else (gt (cc0)
6339 (label_ref (match_operand 0 "" ""))))]
6343 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6345 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6351 (if_then_else (gtu (cc0)
6354 (label_ref (match_operand 0 "" ""))))]
6358 return \"jbls %l0\";
6366 (if_then_else (lt (cc0)
6369 (label_ref (match_operand 0 "" ""))))]
6373 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6375 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6381 (if_then_else (ltu (cc0)
6384 (label_ref (match_operand 0 "" ""))))]
6388 return \"jbcc %l0\";
6396 (if_then_else (ge (cc0)
6399 (label_ref (match_operand 0 "" ""))))]
6403 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6405 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6411 (if_then_else (geu (cc0)
6414 (label_ref (match_operand 0 "" ""))))]
6418 return \"jbcs %l0\";
6426 (if_then_else (le (cc0)
6429 (label_ref (match_operand 0 "" ""))))]
6433 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6435 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6441 (if_then_else (leu (cc0)
6444 (label_ref (match_operand 0 "" ""))))]
6448 return \"jbhi %l0\";
6454 ;; Unconditional and other jump instructions
6457 (label_ref (match_operand 0 "" "")))]
6461 return \"jbra %l0\";
6467 ;; We support two different ways of handling dispatch tables.
6468 ;; The NeXT uses absolute tables, and other machines use relative.
6469 ;; This define_expand can generate either kind.
6470 (define_expand "tablejump"
6471 [(parallel [(set (pc) (match_operand 0 "" ""))
6472 (use (label_ref (match_operand 1 "" "")))])]
6476 #ifdef CASE_VECTOR_PC_RELATIVE
6477 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6478 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6482 ;; Jump to variable address from dispatch table of absolute addresses.
6484 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6485 (use (label_ref (match_operand 1 "" "")))]
6489 return \"jmp (%0)\";
6495 ;; Jump to variable address from dispatch table of relative addresses.
6499 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6500 (use (label_ref (match_operand 1 "" "")))]
6503 #ifdef ASM_RETURN_CASE_JUMP
6504 ASM_RETURN_CASE_JUMP;
6507 #ifdef ASM_OUTPUT_CASE_LABEL
6509 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6511 return \"jmp 6(%%pc,%0.w)\";
6516 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6518 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6519 #endif /* end !CRDS */
6524 return \"jmp 2(pc,%0.w)\";
6526 return \"jmp 2(%%pc,%0.w)\";
6527 #endif /* end !CRDS */
6534 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6536 return \"extl %0\;jmp pc@(2,%0:l)\";
6542 return \"jmp (2,pc,%0.w)\";
6544 return \"jmp pc@(2,%0:w)\";
6551 ;; Decrement-and-branch insns.
6555 (ne (match_operand:HI 0 "general_operand" "+d*g")
6557 (label_ref (match_operand 1 "" ""))
6560 (plus:HI (match_dup 0)
6566 if (DATA_REG_P (operands[0]))
6567 return \"dbra %0,%l1\";
6568 if (GET_CODE (operands[0]) == MEM)
6572 return \"sub%.w %#1,%0\;jbcc %l1\";
6574 return \"subq%.w %#1,%0\;jbcc %l1\";
6576 #else /* not MOTOROLA */
6577 return \"subqw %#1,%0\;jcc %l1\";
6581 #ifdef SGS_CMP_ORDER
6583 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6585 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6587 #else /* not SGS_CMP_ORDER */
6588 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6590 #else /* not MOTOROLA */
6591 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6598 (ne (match_operand:SI 0 "general_operand" "+d*g")
6600 (label_ref (match_operand 1 "" ""))
6603 (plus:SI (match_dup 0)
6611 if (DATA_REG_P (operands[0]))
6612 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6613 if (GET_CODE (operands[0]) == MEM)
6614 return \"sub%.l %#1,%0\;jbcc %l1\";
6616 if (DATA_REG_P (operands[0]))
6617 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6618 if (GET_CODE (operands[0]) == MEM)
6619 return \"subq%.l %#1,%0\;jbcc %l1\";
6620 #endif /* NO_ADDSUB_Q */
6621 #ifdef SGS_CMP_ORDER
6623 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6625 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6627 #else /* not SGS_CMP_ORDER */
6628 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6629 #endif /* not SGS_CMP_ORDER */
6630 #else /* not MOTOROLA */
6631 if (DATA_REG_P (operands[0]))
6632 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6633 if (GET_CODE (operands[0]) == MEM)
6634 return \"subql %#1,%0\;jcc %l1\";
6635 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6636 #endif /* not MOTOROLA */
6639 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6644 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6647 (label_ref (match_operand 1 "" ""))
6650 (plus:HI (match_dup 0)
6652 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6658 if (DATA_REG_P (operands[0]))
6659 return \"dbra %0,%l1\";
6660 if (GET_CODE (operands[0]) == MEM)
6661 return \"sub%.w %#1,%0\;jbcc %l1\";
6663 if (DATA_REG_P (operands[0]))
6664 return \"dbra %0,%l1\";
6665 if (GET_CODE (operands[0]) == MEM)
6666 return \"subq%.w %#1,%0\;jbcc %l1\";
6668 #ifdef SGS_CMP_ORDER
6670 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6672 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6674 #else /* not SGS_CMP_ORDER */
6675 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6676 #endif /* not SGS_CMP_ORDER */
6677 #else /* not MOTOROLA */
6678 if (DATA_REG_P (operands[0]))
6679 return \"dbra %0,%l1\";
6680 if (GET_CODE (operands[0]) == MEM)
6681 return \"subqw %#1,%0\;jcc %l1\";
6682 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6683 #endif /* not MOTOROLA */
6686 (define_expand "decrement_and_branch_until_zero"
6687 [(parallel [(set (pc)
6689 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6692 (label_ref (match_operand 1 "" ""))
6695 (plus:SI (match_dup 0)
6703 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6706 (label_ref (match_operand 1 "" ""))
6709 (plus:SI (match_dup 0)
6711 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6717 if (DATA_REG_P (operands[0]))
6718 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6719 if (GET_CODE (operands[0]) == MEM)
6720 return \"sub%.l %#1,%0\;jbcc %l1\";
6722 if (DATA_REG_P (operands[0]))
6723 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6724 if (GET_CODE (operands[0]) == MEM)
6725 return \"subq%.l %#1,%0\;jbcc %l1\";
6727 #ifdef SGS_CMP_ORDER
6729 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6731 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6733 #else /* not SGS_CMP_ORDER */
6734 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6735 #endif /* not SGS_CMP_ORDER */
6736 #else /* not MOTOROLA */
6737 if (DATA_REG_P (operands[0]))
6738 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6739 if (GET_CODE (operands[0]) == MEM)
6740 return \"subql %#1,%0\;jcc %l1\";
6741 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6742 #endif /* not MOTOROLA */
6746 ;; For PIC calls, in order to be able to support
6747 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6748 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6750 ;; PIC calls are handled by loading the address of the function into a
6751 ;; register (via movsi), then emitting a register indirect call using
6752 ;; the "jsr" function call syntax.
6754 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6755 ;; operand to the jbsr statement to indicate that this call should
6756 ;; go through the PLT (why? because this is the way that Sun does it).
6758 ;; We have different patterns for PIC calls and non-PIC calls. The
6759 ;; different patterns are only used to choose the right syntax.
6761 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6762 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6763 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6764 ;; section at link time. However, all global objects reference are still
6765 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6766 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6767 ;; We need to have a way to differentiate these two different operands.
6769 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6770 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6771 ;; to be changed to recognize function calls symbol_ref operand as a valid
6772 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6773 ;; avoid the compiler to load this symbol_ref operand into a register.
6774 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6775 ;; since the value is a PC relative offset, not a real address.
6777 ;; All global objects are treated in the similar way as in SUN3. The only
6778 ;; difference is: on m68k svr4, the reference of such global object needs
6779 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6780 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6783 ;; Call subroutine with no return value.
6784 (define_expand "call"
6785 [(call (match_operand:QI 0 "memory_operand" "")
6786 (match_operand:SI 1 "general_operand" ""))]
6787 ;; Operand 1 not really used on the m68000.
6792 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6793 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6796 ;; This is a normal call sequence.
6798 [(call (match_operand:QI 0 "memory_operand" "o")
6799 (match_operand:SI 1 "general_operand" "g"))]
6800 ;; Operand 1 not really used on the m68000.
6804 #if defined (MOTOROLA) && !defined (USE_GAS)
6806 if (GET_CODE (operands[0]) == MEM
6807 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6816 ;; This is a PIC call sequence.
6818 [(call (match_operand:QI 0 "memory_operand" "o")
6819 (match_operand:SI 1 "general_operand" "g"))]
6820 ;; Operand 1 not really used on the m68000.
6824 if (GET_CODE (operands[0]) == MEM
6825 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6828 return \"bsr.l %0\";
6831 return \"bsr.l %0@PLTPC\";
6833 return \"bsr %0@PLTPC\";
6837 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6838 GAS just plain ignores it. */
6839 return \"jbsr %0,a1\";
6844 ;; Call subroutine, returning value in operand 0
6845 ;; (which must be a hard register).
6846 ;; See comments before "call" regarding PIC calls.
6847 (define_expand "call_value"
6848 [(set (match_operand 0 "" "")
6849 (call (match_operand:QI 1 "memory_operand" "")
6850 (match_operand:SI 2 "general_operand" "")))]
6851 ;; Operand 2 not really used on the m68000.
6855 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6856 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6859 ;; This is a normal call_value
6861 [(set (match_operand 0 "" "=rf")
6862 (call (match_operand:QI 1 "memory_operand" "o")
6863 (match_operand:SI 2 "general_operand" "g")))]
6864 ;; Operand 2 not really used on the m68000.
6867 #if defined (MOTOROLA) && !defined (USE_GAS)
6869 if (GET_CODE (operands[1]) == MEM
6870 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6879 ;; This is a PIC call_value
6881 [(set (match_operand 0 "" "=rf")
6882 (call (match_operand:QI 1 "memory_operand" "o")
6883 (match_operand:SI 2 "general_operand" "g")))]
6884 ;; Operand 2 not really used on the m68000.
6887 if (GET_CODE (operands[1]) == MEM
6888 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6892 return \"bsr.l %1\";
6895 return \"bsr.l %1@PLTPC\";
6897 return \"bsr %1@PLTPC\";
6901 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6902 GAS just plain ignores it. */
6903 return \"jbsr %1,a1\";
6909 ;; Call subroutine returning any type.
6911 (define_expand "untyped_call"
6912 [(parallel [(call (match_operand 0 "" "")
6914 (match_operand 1 "" "")
6915 (match_operand 2 "" "")])]
6916 "NEEDS_UNTYPED_CALL"
6921 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6923 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6925 rtx set = XVECEXP (operands[2], 0, i);
6926 emit_move_insn (SET_DEST (set), SET_SRC (set));
6929 /* The optimizer does not know that the call sets the function value
6930 registers we stored in the result block. We avoid problems by
6931 claiming that all hard registers are used and clobbered at this
6933 emit_insn (gen_blockage ());
6938 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6939 ;; all of memory. This blocks insns from being moved across this point.
6941 (define_insn "blockage"
6942 [(unspec_volatile [(const_int 0)] 0)]
6951 (define_insn "probe"
6956 operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
6957 GEN_INT (NEED_PROBE));
6958 return \"tstl %a0\";
6961 ;; Used for frameless functions which save no regs and allocate no locals.
6962 (define_insn "return"
6967 if (current_function_pops_args == 0)
6969 operands[0] = GEN_INT (current_function_pops_args);
6973 (define_insn "indirect_jump"
6974 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6978 ;; This should not be used unless the add/sub insns can't be.
6981 [(set (match_operand:SI 0 "general_operand" "=a")
6982 (match_operand:QI 1 "address_operand" "p"))]
6987 /* Recognize an insn that refers to a table of offsets. Such an insn will
6988 need to refer to a label on the insn. So output one. Use the
6989 label-number of the table of offsets to generate this label. This code,
6990 and similar code above, assumes that there will be at most one reference
6992 if (GET_CODE (operands[1]) == PLUS
6993 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6994 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6996 rtx labelref = XEXP (operands[1], 1);
6997 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6999 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
7000 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7002 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
7003 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7004 #endif /* not SGS */
7005 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
7006 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7007 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7008 #ifdef SGS_SWITCH_TABLES
7009 /* Set flag saying we need to define the symbol
7010 LD%n (with value L%n-LI%n) at the end of the switch table. */
7011 switch_table_difference_label_flag = 1;
7012 #endif /* SGS_SWITCH_TABLES */
7013 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7015 #endif /* SGS_NO_LI */
7017 return \"lea %a1,%0\";
7020 ;; This is the first machine-dependent peephole optimization.
7021 ;; It is useful when a floating value is returned from a function call
7022 ;; and then is moved into an FP register.
7023 ;; But it is mainly intended to test the support for these optimizations.
7026 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7027 (set (match_operand:DF 0 "register_operand" "=f")
7028 (match_operand:DF 1 "register_operand" "ad"))]
7029 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7033 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7034 output_asm_insn (\"move%.l %1,%@\", xoperands);
7035 output_asm_insn (\"move%.l %1,%-\", operands);
7036 return \"fmove%.d %+,%0\";
7040 ;; Optimize a stack-adjust followed by a push of an argument.
7041 ;; This is said to happen frequently with -msoft-float
7042 ;; when there are consecutive library calls.
7045 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7046 (match_operand:SI 0 "const_int_operand" "n")))
7047 (set (match_operand:SF 1 "push_operand" "=m")
7048 (match_operand:SF 2 "general_operand" "rmfF"))]
7049 "INTVAL (operands[0]) >= 4
7050 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7053 if (INTVAL (operands[0]) > 4)
7056 xoperands[0] = stack_pointer_rtx;
7057 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7059 if (INTVAL (xoperands[1]) <= 8)
7062 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7064 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7066 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7068 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7069 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7073 if (INTVAL (xoperands[1]) <= 0x7FFF)
7076 output_asm_insn (\"add%.w %1,%0\", xoperands);
7079 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7081 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7085 output_asm_insn (\"add%.l %1,%0\", xoperands);
7087 if (FP_REG_P (operands[2]))
7088 return \"fmove%.s %2,%@\";
7089 return \"move%.l %2,%@\";
7092 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7095 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7096 (match_operand:SI 0 "const_int_operand" "n")))
7097 (set (match_operand:SI 1 "push_operand" "=m")
7098 (match_operand:SI 2 "general_operand" "g"))]
7099 "INTVAL (operands[0]) >= 4
7100 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7103 if (INTVAL (operands[0]) > 4)
7106 xoperands[0] = stack_pointer_rtx;
7107 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7109 if (INTVAL (xoperands[1]) <= 8)
7112 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7114 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7116 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7118 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7119 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7123 if (INTVAL (xoperands[1]) <= 0x7FFF)
7126 output_asm_insn (\"add%.w %1,%0\", xoperands);
7130 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7132 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7137 output_asm_insn (\"add%.l %1,%0\", xoperands);
7139 if (operands[2] == const0_rtx)
7140 return \"clr%.l %@\";
7141 return \"move%.l %2,%@\";
7144 ;; Speed up pushing a single byte but leaving four bytes of space.
7147 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7148 (match_operand:QI 1 "general_operand" "dami"))
7149 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7150 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7155 if (GET_CODE (operands[1]) == REG)
7156 return \"move%.l %1,%-\";
7158 xoperands[1] = operands[1];
7160 = gen_rtx_MEM (QImode,
7161 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
7163 xoperands[3] = stack_pointer_rtx;
7165 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7167 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7172 [(set (match_operand:SI 0 "register_operand" "=d")
7174 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7175 (match_operand:HI 1 "general_operand" "rmn"))]
7176 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7179 if (GET_CODE (operands[1]) == CONST_INT)
7181 if (operands[1] == const0_rtx
7182 && (DATA_REG_P (operands[0])
7183 || GET_CODE (operands[0]) == MEM)
7184 /* clr insns on 68000 read before writing.
7185 This isn't so on the 68010, but we have no TARGET_68010. */
7186 && ((TARGET_68020 || TARGET_5200)
7187 || !(GET_CODE (operands[0]) == MEM
7188 && MEM_VOLATILE_P (operands[0]))))
7189 return \"clr%.w %0\";
7191 return \"move%.w %1,%0\";
7199 ;; jCC label ; abnormal loop termination
7200 ;; dbra dN, loop ; normal loop termination
7208 ;; Which moves the jCC condition outside the inner loop for free.
7211 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7212 [(cc0) (const_int 0)])
7213 (label_ref (match_operand 2 "" ""))
7218 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7221 (label_ref (match_operand 1 "" ""))
7224 (plus:HI (match_dup 0)
7226 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7230 output_dbcc_and_branch (operands);
7235 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7236 [(cc0) (const_int 0)])
7237 (label_ref (match_operand 2 "" ""))
7242 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7245 (label_ref (match_operand 1 "" ""))
7248 (plus:SI (match_dup 0)
7250 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7254 output_dbcc_and_branch (operands);
7259 ;; FPA multiply and add.
7261 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7262 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7263 (match_operand:DF 2 "general_operand" "xH,y,y"))
7264 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7267 fpma%.d %1,%w2,%w3,%0
7268 fpma%.d %x1,%x2,%x3,%0
7269 fpma%.d %x1,%x2,%x3,%0")
7272 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7273 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7274 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7275 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7278 fpma%.s %1,%w2,%w3,%0
7280 fpma%.s %1,%2,%3,%0")
7282 ;; FPA Multiply and subtract
7284 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7285 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7286 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7287 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7290 fpms%.d %3,%w2,%w1,%0
7291 fpms%.d %x3,%2,%x1,%0
7292 fpms%.d %x3,%2,%x1,%0")
7295 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7296 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7297 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7298 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7301 fpms%.s %3,%w2,%w1,%0
7303 fpms%.s %3,%2,%1,%0")
7306 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7307 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7308 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7309 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7312 fpmr%.d %2,%w1,%w3,%0
7313 fpmr%.d %x2,%1,%x3,%0
7314 fpmr%.d %x2,%1,%x3,%0")
7317 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7318 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7319 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7320 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7323 fpmr%.s %2,%w1,%w3,%0
7324 fpmr%.s %x2,%1,%x3,%0
7325 fpmr%.s %x2,%1,%x3,%0")
7327 ;; FPA Add and multiply
7329 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7330 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7331 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7332 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7335 fpam%.d %2,%w1,%w3,%0
7336 fpam%.d %x2,%1,%x3,%0
7337 fpam%.d %x2,%1,%x3,%0")
7340 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7341 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7342 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7343 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7346 fpam%.s %2,%w1,%w3,%0
7347 fpam%.s %x2,%1,%x3,%0
7348 fpam%.s %x2,%1,%x3,%0")
7350 ;;FPA Subtract and multiply
7352 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7353 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7354 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7355 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7358 fpsm%.d %2,%w1,%w3,%0
7359 fpsm%.d %x2,%1,%x3,%0
7360 fpsm%.d %x2,%1,%x3,%0")
7363 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7364 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7365 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7366 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7369 fpsm%.d %3,%w2,%w1,%0
7370 fpsm%.d %x3,%2,%x1,%0
7371 fpsm%.d %x3,%2,%x1,%0")
7374 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7375 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7376 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7377 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7380 fpsm%.s %2,%w1,%w3,%0
7381 fpsm%.s %x2,%1,%x3,%0
7382 fpsm%.s %x2,%1,%x3,%0")
7385 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7386 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7387 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7388 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7391 fpsm%.s %3,%w2,%w1,%0
7392 fpsm%.s %x3,%2,%x1,%0
7393 fpsm%.s %x3,%2,%x1,%0")
7395 (define_expand "tstxf"
7397 (match_operand:XF 0 "nonimmediate_operand" ""))]
7399 "m68k_last_compare_had_fp_operands = 1;")
7403 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7407 cc_status.flags = CC_IN_68881;
7408 return \"ftst%.x %0\";
7411 (define_expand "cmpxf"
7413 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7414 (match_operand:XF 1 "nonimmediate_operand" "")))]
7416 "m68k_last_compare_had_fp_operands = 1;")
7420 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7421 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7425 cc_status.flags = CC_IN_68881;
7426 #ifdef SGS_CMP_ORDER
7427 if (REG_P (operands[0]))
7429 if (REG_P (operands[1]))
7430 return \"fcmp%.x %0,%1\";
7432 return \"fcmp%.x %0,%f1\";
7434 cc_status.flags |= CC_REVERSED;
7435 return \"fcmp%.x %1,%f0\";
7437 if (REG_P (operands[0]))
7439 if (REG_P (operands[1]))
7440 return \"fcmp%.x %1,%0\";
7442 return \"fcmp%.x %f1,%0\";
7444 cc_status.flags |= CC_REVERSED;
7445 return \"fcmp%.x %f0,%1\";
7449 (define_insn "extendsfxf2"
7450 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7451 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7455 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7457 if (REGNO (operands[0]) == REGNO (operands[1]))
7459 /* Extending float to double in an fp-reg is a no-op.
7460 NOTICE_UPDATE_CC has already assumed that the
7461 cc will be set. So cancel what it did. */
7462 cc_status = cc_prev_status;
7465 return \"f%$move%.x %1,%0\";
7467 if (FP_REG_P (operands[0]))
7469 if (FP_REG_P (operands[1]))
7470 return \"f%$move%.x %1,%0\";
7471 else if (ADDRESS_REG_P (operands[1]))
7472 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
7473 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7474 return output_move_const_single (operands);
7475 return \"f%$move%.s %f1,%0\";
7477 return \"fmove%.x %f1,%0\";
7481 (define_insn "extenddfxf2"
7482 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7484 (match_operand:DF 1 "general_operand" "f,rmE")))]
7488 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7490 if (REGNO (operands[0]) == REGNO (operands[1]))
7492 /* Extending float to double in an fp-reg is a no-op.
7493 NOTICE_UPDATE_CC has already assumed that the
7494 cc will be set. So cancel what it did. */
7495 cc_status = cc_prev_status;
7498 return \"fmove%.x %1,%0\";
7500 if (FP_REG_P (operands[0]))
7502 if (REG_P (operands[1]))
7505 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
7506 output_asm_insn (\"move%.l %1,%-\", xoperands);
7507 output_asm_insn (\"move%.l %1,%-\", operands);
7508 return \"f%&move%.d %+,%0\";
7510 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7511 return output_move_const_double (operands);
7512 return \"f%&move%.d %f1,%0\";
7514 return \"fmove%.x %f1,%0\";
7517 (define_insn "truncxfdf2"
7518 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7520 (match_operand:XF 1 "general_operand" "f,f")))]
7524 if (REG_P (operands[0]))
7526 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7527 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7528 return \"move%.l %+,%0\";
7530 return \"fmove%.d %f1,%0\";
7533 (define_insn "truncxfsf2"
7534 [(set (match_operand:SF 0 "general_operand" "=dm")
7536 (match_operand:XF 1 "general_operand" "f")))]
7540 (define_insn "floatsixf2"
7541 [(set (match_operand:XF 0 "general_operand" "=f")
7542 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7546 (define_insn "floathixf2"
7547 [(set (match_operand:XF 0 "general_operand" "=f")
7548 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7552 (define_insn "floatqixf2"
7553 [(set (match_operand:XF 0 "general_operand" "=f")
7554 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7558 (define_insn "ftruncxf2"
7559 [(set (match_operand:XF 0 "general_operand" "=f")
7560 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7564 if (FP_REG_P (operands[1]))
7565 return \"fintrz%.x %f1,%0\";
7566 return \"fintrz%.x %f1,%0\";
7569 (define_insn "fixxfqi2"
7570 [(set (match_operand:QI 0 "general_operand" "=dm")
7571 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7575 (define_insn "fixxfhi2"
7576 [(set (match_operand:HI 0 "general_operand" "=dm")
7577 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7581 (define_insn "fixxfsi2"
7582 [(set (match_operand:SI 0 "general_operand" "=dm")
7583 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7588 [(set (match_operand:XF 0 "general_operand" "=f")
7589 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7590 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7595 [(set (match_operand:XF 0 "general_operand" "=f")
7596 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7597 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7602 [(set (match_operand:XF 0 "general_operand" "=f")
7603 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7604 (match_operand:XF 1 "general_operand" "0")))]
7608 (define_insn "addxf3"
7609 [(set (match_operand:XF 0 "general_operand" "=f")
7610 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7611 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7615 if (REG_P (operands[2]))
7616 return \"fadd%.x %2,%0\";
7617 return \"fadd%.x %f2,%0\";
7621 [(set (match_operand:XF 0 "general_operand" "=f")
7622 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7623 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7628 [(set (match_operand:XF 0 "general_operand" "=f")
7629 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7630 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7635 [(set (match_operand:XF 0 "general_operand" "=f")
7636 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7637 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7641 (define_insn "subxf3"
7642 [(set (match_operand:XF 0 "general_operand" "=f")
7643 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7644 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7648 if (REG_P (operands[2]))
7649 return \"fsub%.x %2,%0\";
7650 return \"fsub%.x %f2,%0\";
7654 [(set (match_operand:XF 0 "general_operand" "=f")
7655 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7656 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7661 [(set (match_operand:XF 0 "general_operand" "=f")
7662 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7663 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7668 [(set (match_operand:XF 0 "general_operand" "=f")
7669 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7670 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7674 (define_insn "mulxf3"
7675 [(set (match_operand:XF 0 "general_operand" "=f")
7676 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7677 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7681 if (REG_P (operands[2]))
7682 return \"fmul%.x %2,%0\";
7683 return \"fmul%.x %f2,%0\";
7687 [(set (match_operand:XF 0 "general_operand" "=f")
7688 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7689 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7694 [(set (match_operand:XF 0 "general_operand" "=f")
7695 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7696 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7701 [(set (match_operand:XF 0 "general_operand" "=f")
7702 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7703 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7707 (define_insn "divxf3"
7708 [(set (match_operand:XF 0 "general_operand" "=f")
7709 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7710 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7714 if (REG_P (operands[2]))
7715 return \"fdiv%.x %2,%0\";
7716 return \"fdiv%.x %f2,%0\";
7719 (define_expand "negxf2"
7720 [(set (match_operand:XF 0 "general_operand" "")
7721 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7725 /* ??? There isn't an FPA define_insn so we could handle it here too.
7726 For now we don't (paranoia). */
7734 target = operand_subword (operands[0], 0, 1, XFmode);
7735 result = expand_binop (SImode, xor_optab,
7736 operand_subword_force (operands[1], 0, XFmode),
7737 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7741 if (result != target)
7742 emit_move_insn (result, target);
7744 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7745 operand_subword_force (operands[1], 1, XFmode));
7746 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7747 operand_subword_force (operands[1], 2, XFmode));
7749 insns = get_insns ();
7752 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7757 (define_insn "negxf2_68881"
7758 [(set (match_operand:XF 0 "general_operand" "=f")
7759 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7763 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7764 return \"fneg%.x %1,%0\";
7765 return \"fneg%.x %f1,%0\";
7768 (define_expand "absxf2"
7769 [(set (match_operand:XF 0 "general_operand" "")
7770 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7774 /* ??? There isn't an FPA define_insn so we could handle it here too.
7775 For now we don't (paranoia). */
7783 target = operand_subword (operands[0], 0, 1, XFmode);
7784 result = expand_binop (SImode, and_optab,
7785 operand_subword_force (operands[1], 0, XFmode),
7786 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7790 if (result != target)
7791 emit_move_insn (result, target);
7793 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7794 operand_subword_force (operands[1], 1, XFmode));
7795 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7796 operand_subword_force (operands[1], 2, XFmode));
7798 insns = get_insns ();
7801 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7806 (define_insn "absxf2_68881"
7807 [(set (match_operand:XF 0 "general_operand" "=f")
7808 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7812 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7813 return \"fabs%.x %1,%0\";
7814 return \"fabs%.x %f1,%0\";
7817 (define_insn "sqrtxf2"
7818 [(set (match_operand:XF 0 "general_operand" "=f")
7819 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7823 (define_insn "sinsf2"
7824 [(set (match_operand:SF 0 "general_operand" "=f")
7825 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7826 "TARGET_68881 && flag_fast_math"
7829 if (FP_REG_P (operands[1]))
7830 return \"fsin%.x %1,%0\";
7832 return \"fsin%.s %1,%0\";
7835 (define_insn "sindf2"
7836 [(set (match_operand:DF 0 "general_operand" "=f")
7837 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7838 "TARGET_68881 && flag_fast_math"
7841 if (FP_REG_P (operands[1]))
7842 return \"fsin%.x %1,%0\";
7844 return \"fsin%.d %1,%0\";
7847 (define_insn "sinxf2"
7848 [(set (match_operand:XF 0 "general_operand" "=f")
7849 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7850 "TARGET_68881 && flag_fast_math"
7853 (define_insn "cossf2"
7854 [(set (match_operand:SF 0 "general_operand" "=f")
7855 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7856 "TARGET_68881 && flag_fast_math"
7859 if (FP_REG_P (operands[1]))
7860 return \"fcos%.x %1,%0\";
7862 return \"fcos%.s %1,%0\";
7865 (define_insn "cosdf2"
7866 [(set (match_operand:DF 0 "general_operand" "=f")
7867 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7868 "TARGET_68881 && flag_fast_math"
7871 if (FP_REG_P (operands[1]))
7872 return \"fcos%.x %1,%0\";
7874 return \"fcos%.d %1,%0\";
7877 (define_insn "cosxf2"
7878 [(set (match_operand:XF 0 "general_operand" "=f")
7879 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7880 "TARGET_68881 && flag_fast_math"