1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
753 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
755 (minus:SI (const_int 7)
756 (match_operand:SI 1 "general_operand" "di"))))]
758 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
761 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
763 (minus:SI (const_int 31)
764 (match_operand:SI 1 "general_operand" "di"))))]
766 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
768 ;; The following two patterns are like the previous two
769 ;; except that they use the fact that bit-number operands
770 ;; are automatically masked to 3 or 5 bits.
773 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
775 (minus:SI (const_int 7)
777 (match_operand:SI 1 "register_operand" "d")
780 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
783 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
785 (minus:SI (const_int 31)
787 (match_operand:SI 1 "register_operand" "d")
790 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
792 ;; Nonoffsettable mem refs are ok in this one pattern
793 ;; since we don't try to adjust them.
795 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
797 (match_operand:SI 1 "const_int_operand" "n")))]
798 "(unsigned) INTVAL (operands[1]) < 8"
801 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
802 return output_btst (operands, operands[1], operands[0], insn, 7);
806 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
808 (match_operand:SI 1 "const_int_operand" "n")))]
812 if (GET_CODE (operands[0]) == MEM)
814 operands[0] = adj_offsettable_operand (operands[0],
815 INTVAL (operands[1]) / 8);
816 operands[1] = gen_rtx (CONST_INT, VOIDmode,
817 7 - INTVAL (operands[1]) % 8);
818 return output_btst (operands, operands[1], operands[0], insn, 7);
820 operands[1] = gen_rtx (CONST_INT, VOIDmode,
821 31 - INTVAL (operands[1]));
822 return output_btst (operands, operands[1], operands[0], insn, 31);
828 ;; A special case in which it is not desirable
829 ;; to reload the constant into a data register.
830 (define_insn "pushexthisi_const"
831 [(set (match_operand:SI 0 "push_operand" "=m")
832 (match_operand:SI 1 "const_int_operand" "J"))]
833 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
836 if (operands[1] == const0_rtx)
837 return \"clr%.l %0\";
842 ;(define_insn "swapsi"
843 ; [(set (match_operand:SI 0 "general_operand" "+r")
844 ; (match_operand:SI 1 "general_operand" "+r"))
845 ; (set (match_dup 1) (match_dup 0))]
849 ;; Special case of fullword move when source is zero.
850 ;; The reason this is special is to avoid loading a zero
851 ;; into a data reg with moveq in order to store it elsewhere.
853 (define_insn "movsi_const0"
854 [(set (match_operand:SI 0 "general_operand" "=g")
856 ;; clr insns on 68000 read before writing.
857 ;; This isn't so on the 68010, but we have no TARGET_68010.
858 "((TARGET_68020 || TARGET_5200)
859 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
862 if (ADDRESS_REG_P (operands[0]))
864 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
865 if (!TARGET_68040 && !TARGET_68060)
866 return \"sub%.l %0,%0\";
871 /* Many SGS assemblers croak on size specifiers for constants. */
874 return \"lea 0.w,%0\";
877 return \"lea 0:w,%0\";
881 /* moveq is faster on the 68000. */
882 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
883 #if defined(MOTOROLA) && !defined(CRDS)
884 return \"moveq%.l %#0,%0\";
886 return \"moveq %#0,%0\";
888 return \"clr%.l %0\";
891 ;; General case of fullword move.
893 ;; This is the main "hook" for PIC code. When generating
894 ;; PIC, movsi is responsible for determining when the source address
895 ;; needs PIC relocation and appropriately calling legitimize_pic_address
896 ;; to perform the actual relocation.
898 ;; In both the PIC and non-PIC cases the patterns generated will
899 ;; matched by the next define_insn.
900 (define_expand "movsi"
901 [(set (match_operand:SI 0 "general_operand" "")
902 (match_operand:SI 1 "general_operand" ""))]
906 if (flag_pic && symbolic_operand (operands[1], SImode))
908 /* The source is an address which requires PIC relocation.
909 Call legitimize_pic_address with the source, mode, and a relocation
910 register (a new pseudo, or the final destination if reload_in_progress
911 is set). Then fall through normally */
912 extern rtx legitimize_pic_address();
913 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
914 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
918 ;; General case of fullword move. The register constraints
919 ;; force integer constants in range for a moveq to be reloaded
920 ;; if they are headed for memory.
922 ;; Notes: make sure no alternative allows g vs g.
923 ;; We don't allow f-regs since fixed point cannot go in them.
924 ;; We do allow y and x regs since fixed point is allowed in them.
925 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
926 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
930 if (which_alternative == 3)
931 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
932 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
933 return \"fpmove%.l %x1,%x0\";
934 return output_move_simode (operands);
938 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g,o")
939 (match_operand:SI 1 "general_operand" "g,r<Q>,o"))]
941 "* return output_move_simode (operands);")
943 (define_expand "movhi"
944 [(set (match_operand:HI 0 "general_operand" "")
945 (match_operand:HI 1 "general_operand" ""))]
950 [(set (match_operand:HI 0 "general_operand" "=g")
951 (match_operand:HI 1 "general_operand" "g"))]
953 "* return output_move_himode (operands);")
956 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g,o")
957 (match_operand:HI 1 "general_operand" "g,r<Q>,o"))]
959 "* return output_move_himode (operands);")
961 (define_expand "movstricthi"
962 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
963 (match_operand:HI 1 "general_operand" ""))]
968 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
969 (match_operand:HI 1 "general_operand" "rmn"))]
971 "* return output_move_stricthi (operands);")
974 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
975 (match_operand:HI 1 "general_operand" "rmn,r"))]
977 "* return output_move_stricthi (operands);")
979 (define_expand "movqi"
980 [(set (match_operand:QI 0 "general_operand" "")
981 (match_operand:QI 1 "general_operand" ""))]
986 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
987 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
989 "* return output_move_qimode (operands);")
992 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am,o")
993 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>,o"))]
995 "* return output_move_qimode (operands);")
997 (define_expand "movstrictqi"
998 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
999 (match_operand:QI 1 "general_operand" ""))]
1004 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1005 (match_operand:QI 1 "general_operand" "dmn"))]
1007 "* return output_move_strictqi (operands);")
1010 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1011 (match_operand:QI 1 "general_operand" "dmn,d"))]
1013 "* return output_move_strictqi (operands);")
1015 (define_expand "movsf"
1016 [(set (match_operand:SF 0 "general_operand" "")
1017 (match_operand:SF 1 "general_operand" ""))]
1022 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1023 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1024 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1025 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1029 if (which_alternative >= 4)
1030 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1031 if (FPA_REG_P (operands[0]))
1033 if (FPA_REG_P (operands[1]))
1034 return \"fpmove%.s %x1,%x0\";
1035 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1036 return output_move_const_single (operands);
1037 else if (FP_REG_P (operands[1]))
1038 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1039 return \"fpmove%.s %x1,%x0\";
1041 if (FPA_REG_P (operands[1]))
1043 if (FP_REG_P (operands[0]))
1044 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1046 return \"fpmove%.s %x1,%x0\";
1048 if (FP_REG_P (operands[0]))
1050 if (FP_REG_P (operands[1]))
1051 return \"f%$move%.x %1,%0\";
1052 else if (ADDRESS_REG_P (operands[1]))
1053 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1054 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1055 return output_move_const_single (operands);
1056 return \"f%$move%.s %f1,%0\";
1058 if (FP_REG_P (operands[1]))
1060 if (ADDRESS_REG_P (operands[0]))
1061 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1062 return \"fmove%.s %f1,%0\";
1064 return \"move%.l %1,%0\";
1068 [(set (match_operand:SF 0 "general_operand" "=r,g")
1069 (match_operand:SF 1 "general_operand" "g,r"))]
1071 "* return \"move%.l %1,%0\";")
1073 (define_expand "movdf"
1074 [(set (match_operand:DF 0 "general_operand" "")
1075 (match_operand:DF 1 "general_operand" ""))]
1080 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1081 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1082 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1083 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1087 if (which_alternative == 7)
1088 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1089 if (FPA_REG_P (operands[0]))
1091 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1092 return output_move_const_double (operands);
1093 if (FP_REG_P (operands[1]))
1094 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1095 return \"fpmove%.d %x1,%x0\";
1097 else if (FPA_REG_P (operands[1]))
1099 if (FP_REG_P(operands[0]))
1100 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1102 return \"fpmove%.d %x1,%x0\";
1104 if (FP_REG_P (operands[0]))
1106 if (FP_REG_P (operands[1]))
1107 return \"f%&move%.x %1,%0\";
1108 if (REG_P (operands[1]))
1111 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1112 output_asm_insn (\"move%.l %1,%-\", xoperands);
1113 output_asm_insn (\"move%.l %1,%-\", operands);
1114 return \"f%&move%.d %+,%0\";
1116 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1117 return output_move_const_double (operands);
1118 return \"f%&move%.d %f1,%0\";
1120 else if (FP_REG_P (operands[1]))
1122 if (REG_P (operands[0]))
1124 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1125 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1126 return \"move%.l %+,%0\";
1129 return \"fmove%.d %f1,%0\";
1131 return output_move_double (operands);
1135 [(set (match_operand:DF 0 "general_operand" "=r,g")
1136 (match_operand:DF 1 "general_operand" "g,r"))]
1138 "* return output_move_double (operands);")
1140 (define_expand "movxf"
1141 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1142 (match_operand:XF 1 "general_operand" ""))]
1146 if (CONSTANT_P (operands[1]))
1148 operands[1] = force_const_mem (XFmode, operands[1]);
1149 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1150 && ! reload_in_progress)
1151 operands[1] = change_address (operands[1], XFmode,
1152 XEXP (operands[1], 0));
1157 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1158 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1162 if (FP_REG_P (operands[0]))
1164 if (FP_REG_P (operands[1]))
1165 return \"fmove%.x %1,%0\";
1166 if (REG_P (operands[1]))
1169 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1170 output_asm_insn (\"move%.l %1,%-\", xoperands);
1171 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1172 output_asm_insn (\"move%.l %1,%-\", xoperands);
1173 output_asm_insn (\"move%.l %1,%-\", operands);
1174 return \"fmove%.x %+,%0\";
1176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1177 return \"fmove%.x %1,%0\";
1178 return \"fmove%.x %f1,%0\";
1180 if (REG_P (operands[0]))
1182 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1183 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1184 output_asm_insn (\"move%.l %+,%0\", operands);
1185 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1186 return \"move%.l %+,%0\";
1188 return \"fmove%.x %f1,%0\";
1193 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1194 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1195 "! TARGET_68881 && ! TARGET_5200"
1198 if (FP_REG_P (operands[0]))
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.x %1,%0\";
1202 if (REG_P (operands[1]))
1205 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1206 output_asm_insn (\"move%.l %1,%-\", xoperands);
1207 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1208 output_asm_insn (\"move%.l %1,%-\", xoperands);
1209 output_asm_insn (\"move%.l %1,%-\", operands);
1210 return \"fmove%.x %+,%0\";
1212 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1213 return \"fmove%.x %1,%0\";
1214 return \"fmove%.x %f1,%0\";
1216 if (FP_REG_P (operands[1]))
1218 if (REG_P (operands[0]))
1220 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1221 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1222 output_asm_insn (\"move%.l %+,%0\", operands);
1223 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1224 return \"move%.l %+,%0\";
1227 return \"fmove%.x %f1,%0\";
1229 return output_move_double (operands);
1234 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1235 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1236 "! TARGET_68881 && TARGET_5200"
1237 "* return output_move_double (operands);")
1239 (define_expand "movdi"
1240 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1241 [(set (match_operand:DI 0 "general_operand" "")
1242 (match_operand:DI 1 "general_operand" ""))]
1246 ;; movdi can apply to fp regs in some cases
1248 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1249 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1250 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1251 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1252 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1253 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1254 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1258 if (which_alternative == 8)
1259 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1260 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1261 return \"fpmove%.d %x1,%x0\";
1262 if (FP_REG_P (operands[0]))
1264 if (FP_REG_P (operands[1]))
1265 return \"fmove%.x %1,%0\";
1266 if (REG_P (operands[1]))
1269 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1270 output_asm_insn (\"move%.l %1,%-\", xoperands);
1271 output_asm_insn (\"move%.l %1,%-\", operands);
1272 return \"fmove%.d %+,%0\";
1274 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1275 return output_move_const_double (operands);
1276 return \"fmove%.d %f1,%0\";
1278 else if (FP_REG_P (operands[1]))
1280 if (REG_P (operands[0]))
1282 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1283 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1284 return \"move%.l %+,%0\";
1287 return \"fmove%.d %f1,%0\";
1289 return output_move_double (operands);
1293 [(set (match_operand:DI 0 "general_operand" "=r,g")
1294 (match_operand:DI 1 "general_operand" "g,r"))]
1296 "* return output_move_double (operands);")
1298 ;; Thus goes after the move instructions
1299 ;; because the move instructions are better (require no spilling)
1300 ;; when they can apply. It goes before the add/sub insns
1301 ;; so we will prefer it to them.
1303 (define_insn "pushasi"
1304 [(set (match_operand:SI 0 "push_operand" "=m")
1305 (match_operand:SI 1 "address_operand" "p"))]
1309 ;; truncation instructions
1310 (define_insn "truncsiqi2"
1311 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1313 (match_operand:SI 1 "general_operand" "doJ,i")))]
1317 if (GET_CODE (operands[0]) == REG)
1319 /* Must clear condition codes, since the move.l bases them on
1320 the entire 32 bits, not just the desired 8 bits. */
1322 return \"move%.l %1,%0\";
1324 if (GET_CODE (operands[1]) == MEM)
1325 operands[1] = adj_offsettable_operand (operands[1], 3);
1326 return \"move%.b %1,%0\";
1329 (define_insn "trunchiqi2"
1330 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1332 (match_operand:HI 1 "general_operand" "doJ,i")))]
1336 if (GET_CODE (operands[0]) == REG
1337 && (GET_CODE (operands[1]) == MEM
1338 || GET_CODE (operands[1]) == CONST_INT))
1340 /* Must clear condition codes, since the move.w bases them on
1341 the entire 16 bits, not just the desired 8 bits. */
1343 return \"move%.w %1,%0\";
1345 if (GET_CODE (operands[0]) == REG)
1347 /* Must clear condition codes, since the move.l bases them on
1348 the entire 32 bits, not just the desired 8 bits. */
1350 return \"move%.l %1,%0\";
1352 if (GET_CODE (operands[1]) == MEM)
1353 operands[1] = adj_offsettable_operand (operands[1], 1);
1354 return \"move%.b %1,%0\";
1357 (define_insn "truncsihi2"
1358 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1360 (match_operand:SI 1 "general_operand" "roJ,i")))]
1364 if (GET_CODE (operands[0]) == REG)
1366 /* Must clear condition codes, since the move.l bases them on
1367 the entire 32 bits, not just the desired 8 bits. */
1369 return \"move%.l %1,%0\";
1371 if (GET_CODE (operands[1]) == MEM)
1372 operands[1] = adj_offsettable_operand (operands[1], 2);
1373 return \"move%.w %1,%0\";
1376 ;; zero extension instructions
1378 ;; this is the canonical form for (lshiftrt:DI x 32)
1379 (define_insn "zero_extendsidi2"
1380 [(set (match_operand:DI 0 "general_operand" "rm")
1381 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1386 if (GET_CODE (operands[0]) == REG)
1387 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1388 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1389 return \"move%.l %1,%0\;clr%.l %0\";
1390 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1391 return \"clr%.l %0\;move%.l %1,%0\";
1393 operands[2] = adj_offsettable_operand (operands[0], 4);
1394 if (ADDRESS_REG_P (operands[0]))
1395 return \"move%.l %1,%2\;sub%.l %0,%0\";
1397 return \"move%.l %1,%2\;clr%.l %0\";
1400 (define_expand "zero_extendhisi2"
1401 [(set (match_operand:SI 0 "register_operand" "")
1403 (set (strict_low_part (match_dup 2))
1404 (match_operand:HI 1 "general_operand" ""))]
1408 operands[1] = make_safe_from (operands[1], operands[0]);
1409 if (GET_CODE (operands[0]) == SUBREG)
1410 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1411 SUBREG_WORD (operands[0]));
1413 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1416 (define_expand "zero_extendqihi2"
1417 [(set (match_operand:HI 0 "register_operand" "")
1419 (set (strict_low_part (match_dup 2))
1420 (match_operand:QI 1 "general_operand" ""))]
1424 operands[1] = make_safe_from (operands[1], operands[0]);
1425 if (GET_CODE (operands[0]) == SUBREG)
1426 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1427 SUBREG_WORD (operands[0]));
1429 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1432 (define_expand "zero_extendqisi2"
1433 [(set (match_operand:SI 0 "register_operand" "")
1435 (set (strict_low_part (match_dup 2))
1436 (match_operand:QI 1 "general_operand" ""))]
1440 operands[1] = make_safe_from (operands[1], operands[0]);
1441 if (GET_CODE (operands[0]) == SUBREG)
1442 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1443 SUBREG_WORD (operands[0]));
1445 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1448 ;; Patterns to recognize zero-extend insns produced by the combiner.
1449 ;; We don't allow both operands in memory, because of aliasing problems.
1450 ;; Explicitly disallow two memory operands via the condition since reloading
1451 ;; of this case will result in worse code than the uncombined patterns.
1454 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1455 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1456 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1459 if (DATA_REG_P (operands[0]))
1461 if (GET_CODE (operands[1]) == REG
1462 && REGNO (operands[0]) == REGNO (operands[1]))
1463 return \"and%.l %#0xFFFF,%0\";
1464 if (reg_mentioned_p (operands[0], operands[1]))
1465 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1466 return \"clr%.l %0\;move%.w %1,%0\";
1468 else if (GET_CODE (operands[0]) == MEM
1469 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1470 return \"move%.w %1,%0\;clr%.w %0\";
1471 else if (GET_CODE (operands[0]) == MEM
1472 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1473 return \"clr%.w %0\;move%.w %1,%0\";
1476 output_asm_insn (\"clr%.w %0\", operands);
1477 operands[0] = adj_offsettable_operand (operands[0], 2);
1478 return \"move%.w %1,%0\";
1483 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1484 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1485 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1488 if (DATA_REG_P (operands[0]))
1490 if (GET_CODE (operands[1]) == REG
1491 && REGNO (operands[0]) == REGNO (operands[1]))
1492 return \"and%.w %#0xFF,%0\";
1493 if (reg_mentioned_p (operands[0], operands[1]))
1494 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1495 return \"clr%.w %0\;move%.b %1,%0\";
1497 else if (GET_CODE (operands[0]) == MEM
1498 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1500 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1501 == STACK_POINTER_REGNUM)
1503 output_asm_insn (\"clr%.w %-\", operands);
1504 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1505 plus_constant (stack_pointer_rtx, 1));
1506 return \"move%.b %1,%0\";
1509 return \"move%.b %1,%0\;clr%.b %0\";
1511 else if (GET_CODE (operands[0]) == MEM
1512 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1513 return \"clr%.b %0\;move%.b %1,%0\";
1516 output_asm_insn (\"clr%.b %0\", operands);
1517 operands[0] = adj_offsettable_operand (operands[0], 1);
1518 return \"move%.b %1,%0\";
1523 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1524 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1525 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1528 if (DATA_REG_P (operands[0]))
1530 if (GET_CODE (operands[1]) == REG
1531 && REGNO (operands[0]) == REGNO (operands[1]))
1532 return \"and%.l %#0xFF,%0\";
1533 if (reg_mentioned_p (operands[0], operands[1]))
1534 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1535 return \"clr%.l %0\;move%.b %1,%0\";
1537 else if (GET_CODE (operands[0]) == MEM
1538 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1540 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1543 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1545 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1548 return \"clrl %0@-\;moveb %1,%0@(3)\";
1551 else if (GET_CODE (operands[0]) == MEM
1552 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1554 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1557 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1559 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1562 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1567 output_asm_insn (\"clr%.l %0\", operands);
1568 operands[0] = adj_offsettable_operand (operands[0], 3);
1569 return \"move%.b %1,%0\";
1573 ;; sign extension instructions
1575 (define_insn "extendqidi2"
1576 [(set (match_operand:DI 0 "general_operand" "=d")
1578 (match_operand:QI 1 "general_operand" "rm")))]
1583 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1584 if (TARGET_68020 || TARGET_5200)
1585 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1587 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1590 (define_insn "extendhidi2"
1591 [(set (match_operand:DI 0 "general_operand" "=d")
1593 (match_operand:HI 1 "general_operand" "rm")))]
1598 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1599 if (TARGET_68020 || TARGET_5200)
1600 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1602 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1605 (define_insn "extendsidi2"
1606 [(set (match_operand:DI 0 "general_operand" "=d")
1608 (match_operand:SI 1 "general_operand" "rm")))]
1613 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1614 if (TARGET_68020 || TARGET_5200)
1615 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1617 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1620 ;; Special case when one can avoid register clobbering, copy and test
1621 ;; Maybe there is a way to make that the general case, by forcing the
1622 ;; result of the SI tree to be in the lower register of the DI target
1624 (define_insn "extendplussidi"
1625 [(set (match_operand:DI 0 "register_operand" "=d")
1626 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1627 (match_operand:SI 2 "general_operand" "rmn"))))]
1632 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1633 if (GET_CODE (operands[1]) == CONST_INT
1634 && (unsigned) INTVAL (operands[1]) > 8)
1636 rtx tmp = operands[1];
1638 operands[1] = operands[2];
1641 if (GET_CODE (operands[1]) == REG
1642 && REGNO (operands[1]) == REGNO (operands[3]))
1643 output_asm_insn (\"add%.l %2,%3\", operands);
1645 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1646 if (TARGET_68020 || TARGET_5200)
1647 return \"smi %0\;extb%.l %0\";
1649 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1652 (define_insn "extendhisi2"
1653 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1655 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1659 if (ADDRESS_REG_P (operands[0]))
1660 return \"move%.w %1,%0\";
1661 return \"ext%.l %0\";
1664 (define_insn "extendqihi2"
1665 [(set (match_operand:HI 0 "general_operand" "=d")
1666 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1670 (define_insn "extendqisi2"
1671 [(set (match_operand:SI 0 "general_operand" "=d")
1672 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1673 "TARGET_68020 || TARGET_5200"
1676 ;; Conversions between float and double.
1678 (define_expand "extendsfdf2"
1679 [(set (match_operand:DF 0 "general_operand" "")
1681 (match_operand:SF 1 "general_operand" "")))]
1682 "TARGET_68881 || TARGET_FPA"
1686 [(set (match_operand:DF 0 "general_operand" "=x,y")
1688 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1693 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1695 (match_operand:SF 1 "general_operand" "f,dmF")))]
1699 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1701 if (REGNO (operands[0]) == REGNO (operands[1]))
1703 /* Extending float to double in an fp-reg is a no-op.
1704 NOTICE_UPDATE_CC has already assumed that the
1705 cc will be set. So cancel what it did. */
1706 cc_status = cc_prev_status;
1709 return \"f%&move%.x %1,%0\";
1711 if (FP_REG_P (operands[0]))
1712 return \"f%&move%.s %f1,%0\";
1713 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1715 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1716 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1717 return \"move%.l %+,%0\";
1719 return \"fmove%.d %f1,%0\";
1722 ;; This cannot output into an f-reg because there is no way to be
1723 ;; sure of truncating in that case.
1724 ;; But on the Sun FPA, we can be sure.
1725 (define_expand "truncdfsf2"
1726 [(set (match_operand:SF 0 "general_operand" "")
1728 (match_operand:DF 1 "general_operand" "")))]
1729 "TARGET_68881 || TARGET_FPA"
1733 [(set (match_operand:SF 0 "general_operand" "=x,y")
1735 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1739 ;; On the '040 we can truncate in a register accurately and easily.
1741 [(set (match_operand:SF 0 "general_operand" "=f")
1743 (match_operand:DF 1 "general_operand" "fmG")))]
1747 if (FP_REG_P (operands[1]))
1748 return \"f%$move%.x %1,%0\";
1749 return \"f%$move%.d %f1,%0\";
1753 [(set (match_operand:SF 0 "general_operand" "=dm")
1755 (match_operand:DF 1 "general_operand" "f")))]
1759 ;; Conversion between fixed point and floating point.
1760 ;; Note that among the fix-to-float insns
1761 ;; the ones that start with SImode come first.
1762 ;; That is so that an operand that is a CONST_INT
1763 ;; (and therefore lacks a specific machine mode).
1764 ;; will be recognized as SImode (which is always valid)
1765 ;; rather than as QImode or HImode.
1767 (define_expand "floatsisf2"
1768 [(set (match_operand:SF 0 "general_operand" "")
1769 (float:SF (match_operand:SI 1 "general_operand" "")))]
1770 "TARGET_68881 || TARGET_FPA"
1774 [(set (match_operand:SF 0 "general_operand" "=y,x")
1775 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1780 [(set (match_operand:SF 0 "general_operand" "=f")
1781 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1785 (define_expand "floatsidf2"
1786 [(set (match_operand:DF 0 "general_operand" "")
1787 (float:DF (match_operand:SI 1 "general_operand" "")))]
1788 "TARGET_68881 || TARGET_FPA"
1792 [(set (match_operand:DF 0 "general_operand" "=y,x")
1793 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1798 [(set (match_operand:DF 0 "general_operand" "=f")
1799 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1803 (define_insn "floathisf2"
1804 [(set (match_operand:SF 0 "general_operand" "=f")
1805 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1809 (define_insn "floathidf2"
1810 [(set (match_operand:DF 0 "general_operand" "=f")
1811 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1815 (define_insn "floatqisf2"
1816 [(set (match_operand:SF 0 "general_operand" "=f")
1817 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1821 (define_insn "floatqidf2"
1822 [(set (match_operand:DF 0 "general_operand" "=f")
1823 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1827 ;; New routines to convert floating-point values to integers
1828 ;; to be used on the '040. These should be faster than trapping
1829 ;; into the kernel to emulate fintrz. They should also be faster
1830 ;; than calling the subroutines fixsfsi or fixdfsi.
1832 (define_insn "fix_truncdfsi2"
1833 [(set (match_operand:SI 0 "general_operand" "=dm")
1834 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1835 (clobber (match_scratch:SI 2 "=d"))
1836 (clobber (match_scratch:SI 3 "=d"))]
1837 "TARGET_68881 && TARGET_68040"
1841 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1844 (define_insn "fix_truncdfhi2"
1845 [(set (match_operand:HI 0 "general_operand" "=dm")
1846 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1847 (clobber (match_scratch:SI 2 "=d"))
1848 (clobber (match_scratch:SI 3 "=d"))]
1849 "TARGET_68881 && TARGET_68040"
1853 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1856 (define_insn "fix_truncdfqi2"
1857 [(set (match_operand:QI 0 "general_operand" "=dm")
1858 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1859 (clobber (match_scratch:SI 2 "=d"))
1860 (clobber (match_scratch:SI 3 "=d"))]
1861 "TARGET_68881 && TARGET_68040"
1865 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1868 ;; Convert a float to a float whose value is an integer.
1869 ;; This is the first stage of converting it to an integer type.
1871 (define_insn "ftruncdf2"
1872 [(set (match_operand:DF 0 "general_operand" "=f")
1873 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1874 "TARGET_68881 && !TARGET_68040"
1877 if (FP_REG_P (operands[1]))
1878 return \"fintrz%.x %f1,%0\";
1879 return \"fintrz%.d %f1,%0\";
1882 (define_insn "ftruncsf2"
1883 [(set (match_operand:SF 0 "general_operand" "=f")
1884 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1885 "TARGET_68881 && !TARGET_68040"
1888 if (FP_REG_P (operands[1]))
1889 return \"fintrz%.x %f1,%0\";
1890 return \"fintrz%.s %f1,%0\";
1893 ;; Convert a float whose value is an integer
1894 ;; to an actual integer. Second stage of converting float to integer type.
1895 (define_insn "fixsfqi2"
1896 [(set (match_operand:QI 0 "general_operand" "=dm")
1897 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1901 (define_insn "fixsfhi2"
1902 [(set (match_operand:HI 0 "general_operand" "=dm")
1903 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1907 (define_insn "fixsfsi2"
1908 [(set (match_operand:SI 0 "general_operand" "=dm")
1909 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1913 (define_insn "fixdfqi2"
1914 [(set (match_operand:QI 0 "general_operand" "=dm")
1915 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1919 (define_insn "fixdfhi2"
1920 [(set (match_operand:HI 0 "general_operand" "=dm")
1921 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1925 (define_insn "fixdfsi2"
1926 [(set (match_operand:SI 0 "general_operand" "=dm")
1927 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1931 ;; Convert a float to an integer.
1932 ;; On the Sun FPA, this is done in one step.
1935 [(set (match_operand:SI 0 "general_operand" "=x,y")
1936 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1941 [(set (match_operand:SI 0 "general_operand" "=x,y")
1942 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1948 (define_insn "adddi_lshrdi_63"
1949 [(set (match_operand:DI 0 "general_operand" "=d")
1950 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1953 (clobber (match_scratch:SI 2 "=d"))]
1957 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1958 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1960 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1961 if (GET_CODE (operands[1]) == REG)
1962 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1963 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1964 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1965 operands[4] = operands[1];
1967 operands[4] = adj_offsettable_operand (operands[1], 4);
1968 if (GET_CODE (operands[1]) == MEM
1969 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1970 output_asm_insn (\"move%.l %4,%3\", operands);
1971 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1972 if (TARGET_68020 || TARGET_5200)
1973 output_asm_insn (\"extb%.l %2\", operands);
1975 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1976 if (GET_CODE (operands[1]) != MEM
1977 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1978 output_asm_insn (\"move%.l %4,%3\", operands);
1979 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1982 (define_insn "adddi_sexthishl32"
1983 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1984 (plus:DI (ashift:DI (sign_extend:DI
1985 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1987 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1988 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1993 if (ADDRESS_REG_P (operands[0]))
1994 return \"add%.w %1,%0\";
1995 else if (ADDRESS_REG_P (operands[3]))
1996 return \"move%.w %1,%3\;add%.l %3,%0\";
1998 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2001 (define_insn "adddi_dilshr32"
2002 [(set (match_operand:DI 0 "general_operand" "=do")
2003 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2004 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2005 ;; (const_int 32))))]
2006 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2008 (match_operand:DI 2 "general_operand" "0")))]
2013 if (GET_CODE (operands[0]) == REG)
2014 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2016 operands[2] = adj_offsettable_operand (operands[0], 4);
2017 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2020 (define_insn "adddi_dishl32"
2021 [(set (match_operand:DI 0 "general_operand" "=ro")
2022 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2023 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2024 ;; (const_int 32))))]
2025 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2027 (match_operand:DI 2 "general_operand" "0")))]
2032 if (GET_CODE (operands[1]) == REG)
2033 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2035 operands[1] = adj_offsettable_operand (operands[1], 4);
2036 return \"add%.l %1,%0\";
2039 (define_insn "adddi3"
2040 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2041 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2042 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2043 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2047 if (DATA_REG_P (operands[0]))
2049 if (DATA_REG_P (operands[2]))
2050 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2051 else if (GET_CODE (operands[2]) == MEM
2052 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2054 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2058 /* TODO : this should work also for CONST operands[2] */
2059 if (GET_CODE (operands[2]) == REG)
2060 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2062 operands[1] = adj_offsettable_operand (operands[2], 4);
2063 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2066 else if (GET_CODE (operands[0]) == MEM)
2068 if (GET_CODE (operands[2]) == MEM
2069 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2070 return \"add%.l %2,%0\;addx%.l %2,%0\";
2072 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2074 operands[1] = gen_rtx (MEM, SImode,
2075 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2076 gen_rtx (CONST_INT, VOIDmode, -8)));
2077 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2079 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2081 operands[1] = XEXP(operands[0], 0);
2082 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2086 operands[1] = adj_offsettable_operand (operands[0], 4);
2087 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2092 (define_insn "addsi_lshrsi_31"
2093 [(set (match_operand:SI 0 "general_operand" "=dm")
2094 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2100 operands[2] = operands[0];
2101 operands[3] = gen_label_rtx();
2102 if (GET_CODE (operands[0]) == MEM)
2104 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2105 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2106 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2107 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2109 output_asm_insn (\"move%.l %1,%0\", operands);
2111 output_asm_insn (\"jbpl %l3\", operands);
2113 output_asm_insn (\"jpl %l3\", operands);
2116 output_asm_insn (\"addq%.l %#1,%2\", operands);
2118 output_asm_insn (\"add%.l %#1,%2\", operands);
2120 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2121 CODE_LABEL_NUMBER (operands[3]));
2125 (define_expand "addsi3"
2126 [(set (match_operand:SI 0 "general_operand" "")
2127 (plus:SI (match_operand:SI 1 "general_operand" "")
2128 (match_operand:SI 2 "general_operand" "")))]
2132 ;; Note that the middle two alternatives are near-duplicates
2133 ;; in order to handle insns generated by reload.
2134 ;; This is needed since they are not themselves reloaded,
2135 ;; so commutativity won't apply to them.
2136 (define_insn "*addsi3_internal"
2137 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2138 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2139 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2141 "* return output_addsi3 (operands);")
2143 (define_insn "*addsi3_5200"
2144 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2145 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2146 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2148 "* return output_addsi3 (operands);")
2151 [(set (match_operand:SI 0 "general_operand" "=a")
2152 (plus:SI (match_operand:SI 1 "general_operand" "0")
2154 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2158 (define_insn "addhi3"
2159 [(set (match_operand:HI 0 "general_operand" "=m,r")
2160 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2161 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2165 if (GET_CODE (operands[2]) == CONST_INT)
2168 /* If the constant would be a negative number when interpreted as
2169 HImode, make it negative. This is usually, but not always, done
2170 elsewhere in the compiler. First check for constants out of range,
2171 which could confuse us. */
2173 if (INTVAL (operands[2]) >= 32768)
2174 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2175 INTVAL (operands[2]) - 65536);
2177 if (INTVAL (operands[2]) > 0
2178 && INTVAL (operands[2]) <= 8)
2179 return \"addq%.w %2,%0\";
2180 if (INTVAL (operands[2]) < 0
2181 && INTVAL (operands[2]) >= -8)
2183 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2184 - INTVAL (operands[2]));
2185 return \"subq%.w %2,%0\";
2187 /* On the CPU32 it is faster to use two addqw instructions to
2188 add a small integer (8 < N <= 16) to a register.
2189 Likewise for subqw. */
2190 if (TARGET_CPU32 && REG_P (operands[0]))
2192 if (INTVAL (operands[2]) > 8
2193 && INTVAL (operands[2]) <= 16)
2195 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2196 INTVAL (operands[2]) - 8);
2197 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2199 if (INTVAL (operands[2]) < -8
2200 && INTVAL (operands[2]) >= -16)
2202 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2203 - INTVAL (operands[2]) - 8);
2204 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2208 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2210 return \"lea (%c2,%0),%0\";
2212 return \"lea %0@(%c2),%0\";
2215 return \"add%.w %2,%0\";
2218 ;; These insns must use MATCH_DUP instead of the more expected
2219 ;; use of a matching constraint because the "output" here is also
2220 ;; an input, so you can't use the matching constraint. That also means
2221 ;; that you can't use the "%", so you need patterns with the matched
2222 ;; operand in both positions.
2225 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2226 (plus:HI (match_dup 0)
2227 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2231 if (GET_CODE (operands[1]) == CONST_INT)
2234 /* If the constant would be a negative number when interpreted as
2235 HImode, make it negative. This is usually, but not always, done
2236 elsewhere in the compiler. First check for constants out of range,
2237 which could confuse us. */
2239 if (INTVAL (operands[1]) >= 32768)
2240 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2241 INTVAL (operands[1]) - 65536);
2243 if (INTVAL (operands[1]) > 0
2244 && INTVAL (operands[1]) <= 8)
2245 return \"addq%.w %1,%0\";
2246 if (INTVAL (operands[1]) < 0
2247 && INTVAL (operands[1]) >= -8)
2249 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2250 - INTVAL (operands[1]));
2251 return \"subq%.w %1,%0\";
2253 /* On the CPU32 it is faster to use two addqw instructions to
2254 add a small integer (8 < N <= 16) to a register.
2255 Likewise for subqw. */
2256 if (TARGET_CPU32 && REG_P (operands[0]))
2258 if (INTVAL (operands[1]) > 8
2259 && INTVAL (operands[1]) <= 16)
2261 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2262 INTVAL (operands[1]) - 8);
2263 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2265 if (INTVAL (operands[1]) < -8
2266 && INTVAL (operands[1]) >= -16)
2268 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2269 - INTVAL (operands[1]) - 8);
2270 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2274 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2276 return \"lea (%c1,%0),%0\";
2278 return \"lea %0@(%c1),%0\";
2281 return \"add%.w %1,%0\";
2285 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2286 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2291 if (GET_CODE (operands[1]) == CONST_INT)
2294 /* If the constant would be a negative number when interpreted as
2295 HImode, make it negative. This is usually, but not always, done
2296 elsewhere in the compiler. First check for constants out of range,
2297 which could confuse us. */
2299 if (INTVAL (operands[1]) >= 32768)
2300 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2301 INTVAL (operands[1]) - 65536);
2303 if (INTVAL (operands[1]) > 0
2304 && INTVAL (operands[1]) <= 8)
2305 return \"addq%.w %1,%0\";
2306 if (INTVAL (operands[1]) < 0
2307 && INTVAL (operands[1]) >= -8)
2309 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2310 - INTVAL (operands[1]));
2311 return \"subq%.w %1,%0\";
2313 /* On the CPU32 it is faster to use two addqw instructions to
2314 add a small integer (8 < N <= 16) to a register.
2315 Likewise for subqw. */
2316 if (TARGET_CPU32 && REG_P (operands[0]))
2318 if (INTVAL (operands[1]) > 8
2319 && INTVAL (operands[1]) <= 16)
2321 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2322 INTVAL (operands[1]) - 8);
2323 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2325 if (INTVAL (operands[1]) < -8
2326 && INTVAL (operands[1]) >= -16)
2328 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2329 - INTVAL (operands[1]) - 8);
2330 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2334 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2336 return \"lea (%c1,%0),%0\";
2338 return \"lea %0@(%c1),%0\";
2341 return \"add%.w %1,%0\";
2344 (define_insn "addqi3"
2345 [(set (match_operand:QI 0 "general_operand" "=m,d")
2346 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2347 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2352 if (GET_CODE (operands[2]) == CONST_INT)
2354 if (INTVAL (operands[2]) >= 128)
2355 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2356 INTVAL (operands[2]) - 256);
2358 if (INTVAL (operands[2]) > 0
2359 && INTVAL (operands[2]) <= 8)
2360 return \"addq%.b %2,%0\";
2361 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2363 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2364 return \"subq%.b %2,%0\";
2368 return \"add%.b %2,%0\";
2372 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2373 (plus:QI (match_dup 0)
2374 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2379 if (GET_CODE (operands[1]) == CONST_INT)
2381 if (INTVAL (operands[1]) >= 128)
2382 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2383 INTVAL (operands[1]) - 256);
2385 if (INTVAL (operands[1]) > 0
2386 && INTVAL (operands[1]) <= 8)
2387 return \"addq%.b %1,%0\";
2388 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2390 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2391 return \"subq%.b %1,%0\";
2395 return \"add%.b %1,%0\";
2399 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2400 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2406 if (GET_CODE (operands[1]) == CONST_INT)
2408 if (INTVAL (operands[1]) >= 128)
2409 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2410 INTVAL (operands[1]) - 256);
2412 if (INTVAL (operands[1]) > 0
2413 && INTVAL (operands[1]) <= 8)
2414 return \"addq%.b %1,%0\";
2415 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2417 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2418 return \"subq%.b %1,%0\";
2422 return \"add%.b %1,%0\";
2425 (define_expand "adddf3"
2426 [(set (match_operand:DF 0 "general_operand" "")
2427 (plus:DF (match_operand:DF 1 "general_operand" "")
2428 (match_operand:DF 2 "general_operand" "")))]
2429 "TARGET_68881 || TARGET_FPA"
2433 [(set (match_operand:DF 0 "general_operand" "=x,y")
2434 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2435 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2439 if (rtx_equal_p (operands[0], operands[1]))
2440 return \"fpadd%.d %y2,%0\";
2441 if (rtx_equal_p (operands[0], operands[2]))
2442 return \"fpadd%.d %y1,%0\";
2443 if (which_alternative == 0)
2444 return \"fpadd3%.d %w2,%w1,%0\";
2445 return \"fpadd3%.d %x2,%x1,%0\";
2449 [(set (match_operand:DF 0 "general_operand" "=f")
2450 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2451 (match_operand:DF 1 "general_operand" "0")))]
2456 [(set (match_operand:DF 0 "general_operand" "=f")
2457 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2458 (match_operand:DF 1 "general_operand" "0")))]
2463 [(set (match_operand:DF 0 "general_operand" "=f")
2464 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2465 (match_operand:DF 1 "general_operand" "0")))]
2470 [(set (match_operand:DF 0 "general_operand" "=f")
2471 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2472 (match_operand:DF 2 "general_operand" "fmG")))]
2476 if (REG_P (operands[2]))
2477 return \"f%&add%.x %2,%0\";
2478 return \"f%&add%.d %f2,%0\";
2481 (define_expand "addsf3"
2482 [(set (match_operand:SF 0 "general_operand" "")
2483 (plus:SF (match_operand:SF 1 "general_operand" "")
2484 (match_operand:SF 2 "general_operand" "")))]
2485 "TARGET_68881 || TARGET_FPA"
2489 [(set (match_operand:SF 0 "general_operand" "=x,y")
2490 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2491 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2495 if (rtx_equal_p (operands[0], operands[1]))
2496 return \"fpadd%.s %w2,%0\";
2497 if (rtx_equal_p (operands[0], operands[2]))
2498 return \"fpadd%.s %w1,%0\";
2499 if (which_alternative == 0)
2500 return \"fpadd3%.s %w2,%w1,%0\";
2501 return \"fpadd3%.s %2,%1,%0\";
2505 [(set (match_operand:SF 0 "general_operand" "=f")
2506 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2507 (match_operand:SF 1 "general_operand" "0")))]
2512 [(set (match_operand:SF 0 "general_operand" "=f")
2513 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2514 (match_operand:SF 1 "general_operand" "0")))]
2519 [(set (match_operand:SF 0 "general_operand" "=f")
2520 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2521 (match_operand:SF 1 "general_operand" "0")))]
2526 [(set (match_operand:SF 0 "general_operand" "=f")
2527 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2528 (match_operand:SF 2 "general_operand" "fdmF")))]
2532 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2533 return \"f%$add%.x %2,%0\";
2534 return \"f%$add%.s %f2,%0\";
2537 ;; subtract instructions
2539 (define_insn "subdi_sexthishl32"
2540 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2541 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2542 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2544 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2549 if (ADDRESS_REG_P (operands[0]))
2550 return \"sub%.w %2,%0\";
2551 else if (ADDRESS_REG_P (operands[3]))
2552 return \"move%.w %2,%3\;sub%.l %3,%0\";
2554 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2557 (define_insn "subdi_dishl32"
2558 [(set (match_operand:DI 0 "general_operand" "+ro")
2559 (minus:DI (match_dup 0)
2560 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2566 if (GET_CODE (operands[1]) == REG)
2567 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2569 operands[1] = adj_offsettable_operand (operands[1], 4);
2570 return \"sub%.l %1,%0\";
2573 (define_insn "subdi3"
2574 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2575 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2576 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2577 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2581 if (DATA_REG_P (operands[0]))
2583 if (DATA_REG_P (operands[2]))
2584 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2585 else if (GET_CODE (operands[2]) == MEM
2586 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2588 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2592 /* TODO : this should work also for CONST operands[2] */
2593 if (GET_CODE (operands[2]) == REG)
2594 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2596 operands[1] = adj_offsettable_operand (operands[2], 4);
2597 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2600 else if (GET_CODE (operands[0]) == MEM)
2602 if (GET_CODE (operands[2]) == MEM
2603 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2604 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2606 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2608 operands[1] = gen_rtx (MEM, SImode,
2609 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2610 gen_rtx (CONST_INT, VOIDmode, -8)));
2611 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2613 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2615 operands[1] = XEXP(operands[0], 0);
2616 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2620 operands[1] = adj_offsettable_operand (operands[0], 4);
2621 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2626 (define_insn "subsi3"
2627 [(set (match_operand:SI 0 "general_operand" "=m,r")
2628 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2629 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2634 [(set (match_operand:SI 0 "general_operand" "=a")
2635 (minus:SI (match_operand:SI 1 "general_operand" "0")
2637 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2641 (define_insn "subhi3"
2642 [(set (match_operand:HI 0 "general_operand" "=m,r")
2643 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2644 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2649 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2650 (minus:HI (match_dup 0)
2651 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2655 (define_insn "subqi3"
2656 [(set (match_operand:QI 0 "general_operand" "=m,d")
2657 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2658 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2663 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2664 (minus:QI (match_dup 0)
2665 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2669 (define_expand "subdf3"
2670 [(set (match_operand:DF 0 "general_operand" "")
2671 (minus:DF (match_operand:DF 1 "general_operand" "")
2672 (match_operand:DF 2 "general_operand" "")))]
2673 "TARGET_68881 || TARGET_FPA"
2677 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2678 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2679 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2683 if (rtx_equal_p (operands[0], operands[2]))
2684 return \"fprsub%.d %y1,%0\";
2685 if (rtx_equal_p (operands[0], operands[1]))
2686 return \"fpsub%.d %y2,%0\";
2687 if (which_alternative == 0)
2688 return \"fpsub3%.d %w2,%w1,%0\";
2689 return \"fpsub3%.d %x2,%x1,%0\";
2693 [(set (match_operand:DF 0 "general_operand" "=f")
2694 (minus:DF (match_operand:DF 1 "general_operand" "0")
2695 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2700 [(set (match_operand:DF 0 "general_operand" "=f")
2701 (minus:DF (match_operand:DF 1 "general_operand" "0")
2702 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2707 [(set (match_operand:DF 0 "general_operand" "=f")
2708 (minus:DF (match_operand:DF 1 "general_operand" "0")
2709 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2714 [(set (match_operand:DF 0 "general_operand" "=f")
2715 (minus:DF (match_operand:DF 1 "general_operand" "0")
2716 (match_operand:DF 2 "general_operand" "fmG")))]
2720 if (REG_P (operands[2]))
2721 return \"f%&sub%.x %2,%0\";
2722 return \"f%&sub%.d %f2,%0\";
2725 (define_expand "subsf3"
2726 [(set (match_operand:SF 0 "general_operand" "")
2727 (minus:SF (match_operand:SF 1 "general_operand" "")
2728 (match_operand:SF 2 "general_operand" "")))]
2729 "TARGET_68881 || TARGET_FPA"
2733 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2734 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2735 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2739 if (rtx_equal_p (operands[0], operands[2]))
2740 return \"fprsub%.s %w1,%0\";
2741 if (rtx_equal_p (operands[0], operands[1]))
2742 return \"fpsub%.s %w2,%0\";
2743 if (which_alternative == 0)
2744 return \"fpsub3%.s %w2,%w1,%0\";
2745 return \"fpsub3%.s %2,%1,%0\";
2749 [(set (match_operand:SF 0 "general_operand" "=f")
2750 (minus:SF (match_operand:SF 1 "general_operand" "0")
2751 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2756 [(set (match_operand:SF 0 "general_operand" "=f")
2757 (minus:SF (match_operand:SF 1 "general_operand" "0")
2758 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2763 [(set (match_operand:SF 0 "general_operand" "=f")
2764 (minus:SF (match_operand:SF 1 "general_operand" "0")
2765 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2770 [(set (match_operand:SF 0 "general_operand" "=f")
2771 (minus:SF (match_operand:SF 1 "general_operand" "0")
2772 (match_operand:SF 2 "general_operand" "fdmF")))]
2776 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2777 return \"f%$sub%.x %2,%0\";
2778 return \"f%$sub%.s %f2,%0\";
2781 ;; multiply instructions
2783 (define_insn "mulhi3"
2784 [(set (match_operand:HI 0 "general_operand" "=d")
2785 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2786 (match_operand:HI 2 "general_operand" "dmn")))]
2790 #if defined(MOTOROLA) && !defined(CRDS)
2791 return \"muls%.w %2,%0\";
2793 return \"muls %2,%0\";
2797 (define_insn "mulhisi3"
2798 [(set (match_operand:SI 0 "general_operand" "=d")
2799 (mult:SI (sign_extend:SI
2800 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2802 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2806 #if defined(MOTOROLA) && !defined(CRDS)
2807 return \"muls%.w %2,%0\";
2809 return \"muls %2,%0\";
2814 [(set (match_operand:SI 0 "general_operand" "=d")
2815 (mult:SI (sign_extend:SI
2816 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2817 (match_operand:SI 2 "const_int_operand" "n")))]
2818 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2821 #if defined(MOTOROLA) && !defined(CRDS)
2822 return \"muls%.w %2,%0\";
2824 return \"muls %2,%0\";
2828 (define_expand "mulsi3"
2829 [(set (match_operand:SI 0 "general_operand" "")
2830 (mult:SI (match_operand:SI 1 "general_operand" "")
2831 (match_operand:SI 2 "general_operand" "")))]
2832 "TARGET_68020 || TARGET_5200"
2836 [(set (match_operand:SI 0 "general_operand" "=d")
2837 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2838 (match_operand:SI 2 "general_operand" "dmsK")))]
2843 [(set (match_operand:SI 0 "general_operand" "=d")
2844 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2845 (match_operand:SI 2 "general_operand" "d<Q>")))]
2849 (define_insn "umulhisi3"
2850 [(set (match_operand:SI 0 "general_operand" "=d")
2851 (mult:SI (zero_extend:SI
2852 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2854 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2858 #if defined(MOTOROLA) && !defined(CRDS)
2859 return \"mulu%.w %2,%0\";
2861 return \"mulu %2,%0\";
2866 [(set (match_operand:SI 0 "general_operand" "=d")
2867 (mult:SI (zero_extend:SI
2868 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2869 (match_operand:SI 2 "const_int_operand" "n")))]
2870 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2873 #if defined(MOTOROLA) && !defined(CRDS)
2874 return \"mulu%.w %2,%0\";
2876 return \"mulu %2,%0\";
2880 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2881 ;; proper matching constraint. This is because the matching is between
2882 ;; the high-numbered word of the DImode operand[0] and operand[1].
2883 (define_expand "umulsidi3"
2885 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2886 (mult:SI (match_operand:SI 1 "register_operand" "")
2887 (match_operand:SI 2 "nonimmediate_operand" "")))
2888 (set (subreg:SI (match_dup 0) 0)
2889 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2890 (zero_extend:DI (match_dup 2)))
2891 (const_int 32))))])]
2892 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2896 [(set (match_operand:SI 0 "register_operand" "=d")
2897 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2898 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2899 (set (match_operand:SI 3 "register_operand" "=d")
2900 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2901 (zero_extend:DI (match_dup 2)))
2903 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2906 ; Match immediate case. For 2.4 only match things < 2^31.
2907 ; It's tricky with larger values in these patterns since we need to match
2908 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2911 [(set (match_operand:SI 0 "register_operand" "=d")
2912 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2913 (match_operand:SI 2 "const_int_operand" "n")))
2914 (set (match_operand:SI 3 "register_operand" "=d")
2915 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2918 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2919 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2922 (define_expand "mulsidi3"
2924 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2925 (mult:SI (match_operand:SI 1 "register_operand" "")
2926 (match_operand:SI 2 "nonimmediate_operand" "")))
2927 (set (subreg:SI (match_dup 0) 0)
2928 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2929 (sign_extend:DI (match_dup 2)))
2930 (const_int 32))))])]
2931 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2935 [(set (match_operand:SI 0 "register_operand" "=d")
2936 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2937 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2938 (set (match_operand:SI 3 "register_operand" "=d")
2939 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2940 (sign_extend:DI (match_dup 2)))
2942 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2946 [(set (match_operand:SI 0 "register_operand" "=d")
2947 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2948 (match_operand:SI 2 "const_sint32_operand" "")))
2949 (set (match_operand:SI 3 "register_operand" "=d")
2950 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2953 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2956 (define_expand "umulsi3_highpart"
2958 [(set (match_operand:SI 0 "register_operand" "")
2961 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
2962 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2964 (clobber (match_dup 3))])]
2965 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2968 operands[3] = gen_reg_rtx (SImode);
2969 if (GET_CODE (operands[2]) == CONST_INT
2970 || GET_CODE (operands[2]) == CONST_DOUBLE)
2972 if (! const_uint32_operand (operands[2], VOIDmode))
2974 /* We have to adjust the operand order for the matching constraints. */
2975 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
2976 operands[1], operands[2]));
2982 [(set (match_operand:SI 0 "register_operand" "=d")
2985 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
2986 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2988 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2989 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2992 (define_insn "const_umulsi3_highpart"
2993 [(set (match_operand:SI 0 "register_operand" "=d")
2996 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
2997 (match_operand 3 "const_uint32_operand" ""))
2999 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3000 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3003 (define_expand "smulsi3_highpart"
3005 [(set (match_operand:SI 0 "register_operand" "")
3008 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3009 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3011 (clobber (match_dup 3))])]
3012 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3015 operands[3] = gen_reg_rtx (SImode);
3016 if (GET_CODE (operands[2]) == CONST_INT
3017 || GET_CODE (operands[2]) == CONST_DOUBLE)
3019 if (! const_sint32_operand (operands[2], VOIDmode))
3021 /* We have to adjust the operand order for the matching constraints. */
3022 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3023 operands[1], operands[2]));
3029 [(set (match_operand:SI 0 "register_operand" "=d")
3032 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3033 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3035 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3036 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3039 (define_insn "const_smulsi3_highpart"
3040 [(set (match_operand:SI 0 "register_operand" "=d")
3043 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3044 (match_operand 3 "const_sint32_operand" ""))
3046 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3047 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3050 (define_expand "muldf3"
3051 [(set (match_operand:DF 0 "general_operand" "")
3052 (mult:DF (match_operand:DF 1 "general_operand" "")
3053 (match_operand:DF 2 "general_operand" "")))]
3054 "TARGET_68881 || TARGET_FPA"
3058 [(set (match_operand:DF 0 "general_operand" "=x,y")
3059 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3060 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3064 if (rtx_equal_p (operands[1], operands[2]))
3065 return \"fpsqr%.d %y1,%0\";
3066 if (rtx_equal_p (operands[0], operands[1]))
3067 return \"fpmul%.d %y2,%0\";
3068 if (rtx_equal_p (operands[0], operands[2]))
3069 return \"fpmul%.d %y1,%0\";
3070 if (which_alternative == 0)
3071 return \"fpmul3%.d %w2,%w1,%0\";
3072 return \"fpmul3%.d %x2,%x1,%0\";
3076 [(set (match_operand:DF 0 "general_operand" "=f")
3077 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3078 (match_operand:DF 1 "general_operand" "0")))]
3083 [(set (match_operand:DF 0 "general_operand" "=f")
3084 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3085 (match_operand:DF 1 "general_operand" "0")))]
3090 [(set (match_operand:DF 0 "general_operand" "=f")
3091 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3092 (match_operand:DF 1 "general_operand" "0")))]
3097 [(set (match_operand:DF 0 "general_operand" "=f")
3098 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3099 (match_operand:DF 2 "general_operand" "fmG")))]
3103 if (GET_CODE (operands[2]) == CONST_DOUBLE
3104 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3106 int i = floating_exact_log2 (operands[2]);
3107 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3108 return \"fscale%.l %2,%0\";
3110 if (REG_P (operands[2]))
3111 return \"f%&mul%.x %2,%0\";
3112 return \"f%&mul%.d %f2,%0\";
3115 (define_expand "mulsf3"
3116 [(set (match_operand:SF 0 "general_operand" "")
3117 (mult:SF (match_operand:SF 1 "general_operand" "")
3118 (match_operand:SF 2 "general_operand" "")))]
3119 "TARGET_68881 || TARGET_FPA"
3123 [(set (match_operand:SF 0 "general_operand" "=x,y")
3124 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3125 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3129 if (rtx_equal_p (operands[1], operands[2]))
3130 return \"fpsqr%.s %w1,%0\";
3131 if (rtx_equal_p (operands[0], operands[1]))
3132 return \"fpmul%.s %w2,%0\";
3133 if (rtx_equal_p (operands[0], operands[2]))
3134 return \"fpmul%.s %w1,%0\";
3135 if (which_alternative == 0)
3136 return \"fpmul3%.s %w2,%w1,%0\";
3137 return \"fpmul3%.s %2,%1,%0\";
3141 [(set (match_operand:SF 0 "general_operand" "=f")
3142 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3143 (match_operand:SF 1 "general_operand" "0")))]
3147 return (TARGET_68040_ONLY
3148 ? \"fsmul%.l %2,%0\"
3149 : \"fsglmul%.l %2,%0\");
3153 [(set (match_operand:SF 0 "general_operand" "=f")
3154 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3155 (match_operand:SF 1 "general_operand" "0")))]
3159 return (TARGET_68040_ONLY
3160 ? \"fsmul%.w %2,%0\"
3161 : \"fsglmul%.w %2,%0\");
3165 [(set (match_operand:SF 0 "general_operand" "=f")
3166 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3167 (match_operand:SF 1 "general_operand" "0")))]
3171 return (TARGET_68040_ONLY
3172 ? \"fsmul%.b %2,%0\"
3173 : \"fsglmul%.b %2,%0\");
3177 [(set (match_operand:SF 0 "general_operand" "=f")
3178 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3179 (match_operand:SF 2 "general_operand" "fdmF")))]
3183 #ifdef FSGLMUL_USE_S
3184 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3185 return (TARGET_68040_ONLY
3186 ? \"fsmul%.s %2,%0\"
3187 : \"fsglmul%.s %2,%0\");
3189 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3190 return (TARGET_68040_ONLY
3191 ? \"fsmul%.x %2,%0\"
3192 : \"fsglmul%.x %2,%0\");
3194 return (TARGET_68040_ONLY
3195 ? \"fsmul%.s %f2,%0\"
3196 : \"fsglmul%.s %f2,%0\");
3199 ;; divide instructions
3201 (define_expand "divdf3"
3202 [(set (match_operand:DF 0 "general_operand" "")
3203 (div:DF (match_operand:DF 1 "general_operand" "")
3204 (match_operand:DF 2 "general_operand" "")))]
3205 "TARGET_68881 || TARGET_FPA"
3209 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3210 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3211 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3215 if (rtx_equal_p (operands[0], operands[2]))
3216 return \"fprdiv%.d %y1,%0\";
3217 if (rtx_equal_p (operands[0], operands[1]))
3218 return \"fpdiv%.d %y2,%0\";
3219 if (which_alternative == 0)
3220 return \"fpdiv3%.d %w2,%w1,%0\";
3221 return \"fpdiv3%.d %x2,%x1,%x0\";
3225 [(set (match_operand:DF 0 "general_operand" "=f")
3226 (div:DF (match_operand:DF 1 "general_operand" "0")
3227 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3232 [(set (match_operand:DF 0 "general_operand" "=f")
3233 (div:DF (match_operand:DF 1 "general_operand" "0")
3234 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3239 [(set (match_operand:DF 0 "general_operand" "=f")
3240 (div:DF (match_operand:DF 1 "general_operand" "0")
3241 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3246 [(set (match_operand:DF 0 "general_operand" "=f")
3247 (div:DF (match_operand:DF 1 "general_operand" "0")
3248 (match_operand:DF 2 "general_operand" "fmG")))]
3252 if (REG_P (operands[2]))
3253 return \"f%&div%.x %2,%0\";
3254 return \"f%&div%.d %f2,%0\";
3257 (define_expand "divsf3"
3258 [(set (match_operand:SF 0 "general_operand" "")
3259 (div:SF (match_operand:SF 1 "general_operand" "")
3260 (match_operand:SF 2 "general_operand" "")))]
3261 "TARGET_68881 || TARGET_FPA"
3265 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3266 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3267 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3271 if (rtx_equal_p (operands[0], operands[1]))
3272 return \"fpdiv%.s %w2,%0\";
3273 if (rtx_equal_p (operands[0], operands[2]))
3274 return \"fprdiv%.s %w1,%0\";
3275 if (which_alternative == 0)
3276 return \"fpdiv3%.s %w2,%w1,%0\";
3277 return \"fpdiv3%.s %2,%1,%0\";
3281 [(set (match_operand:SF 0 "general_operand" "=f")
3282 (div:SF (match_operand:SF 1 "general_operand" "0")
3283 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3287 return (TARGET_68040_ONLY
3288 ? \"fsdiv%.l %2,%0\"
3289 : \"fsgldiv%.l %2,%0\");
3293 [(set (match_operand:SF 0 "general_operand" "=f")
3294 (div:SF (match_operand:SF 1 "general_operand" "0")
3295 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3299 return (TARGET_68040_ONLY
3300 ? \"fsdiv%.w %2,%0\"
3301 : \"fsgldiv%.w %2,%0\");
3305 [(set (match_operand:SF 0 "general_operand" "=f")
3306 (div:SF (match_operand:SF 1 "general_operand" "0")
3307 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3311 return (TARGET_68040_ONLY
3312 ? \"fsdiv%.b %2,%0\"
3313 : \"fsgldiv%.b %2,%0\");
3317 [(set (match_operand:SF 0 "general_operand" "=f")
3318 (div:SF (match_operand:SF 1 "general_operand" "0")
3319 (match_operand:SF 2 "general_operand" "fdmF")))]
3323 #ifdef FSGLDIV_USE_S
3324 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3325 return (TARGET_68040_ONLY
3326 ? \"fsdiv%.s %2,%0\"
3327 : \"fsgldiv%.s %2,%0\");
3329 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3330 return (TARGET_68040_ONLY
3331 ? \"fsdiv%.x %2,%0\"
3332 : \"fsgldiv%.x %2,%0\");
3334 return (TARGET_68040_ONLY
3335 ? \"fsdiv%.s %f2,%0\"
3336 : \"fsgldiv%.s %f2,%0\");
3339 ;; Remainder instructions.
3341 (define_insn "divmodsi4"
3342 [(set (match_operand:SI 0 "general_operand" "=d")
3343 (div:SI (match_operand:SI 1 "general_operand" "0")
3344 (match_operand:SI 2 "general_operand" "dmsK")))
3345 (set (match_operand:SI 3 "general_operand" "=d")
3346 (mod:SI (match_dup 1) (match_dup 2)))]
3347 "TARGET_68020 && !TARGET_5200"
3350 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3351 return \"divs%.l %2,%0\";
3353 return \"divsl%.l %2,%3:%0\";
3356 (define_insn "udivmodsi4"
3357 [(set (match_operand:SI 0 "general_operand" "=d")
3358 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3359 (match_operand:SI 2 "general_operand" "dmsK")))
3360 (set (match_operand:SI 3 "general_operand" "=d")
3361 (umod:SI (match_dup 1) (match_dup 2)))]
3362 "TARGET_68020 && !TARGET_5200"
3365 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3366 return \"divu%.l %2,%0\";
3368 return \"divul%.l %2,%3:%0\";
3371 (define_insn "divmodhi4"
3372 [(set (match_operand:HI 0 "general_operand" "=d")
3373 (div:HI (match_operand:HI 1 "general_operand" "0")
3374 (match_operand:HI 2 "general_operand" "dmsK")))
3375 (set (match_operand:HI 3 "general_operand" "=d")
3376 (mod:HI (match_dup 1) (match_dup 2)))]
3381 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3383 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3385 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3388 return \"move%.l %0,%3\;swap %3\";
3394 (define_insn "udivmodhi4"
3395 [(set (match_operand:HI 0 "general_operand" "=d")
3396 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3397 (match_operand:HI 2 "general_operand" "dmsK")))
3398 (set (match_operand:HI 3 "general_operand" "=d")
3399 (umod:HI (match_dup 1) (match_dup 2)))]
3404 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3406 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3408 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3411 return \"move%.l %0,%3\;swap %3\";
3417 ;; logical-and instructions
3419 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3420 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3421 ;; can't allocate pseudos into it.
3423 (define_expand "andsi3"
3424 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3425 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3426 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3430 (define_insn "andsi3_internal"
3431 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3432 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3433 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3438 if (GET_CODE (operands[2]) == CONST_INT
3439 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3440 && (DATA_REG_P (operands[0])
3441 || offsettable_memref_p (operands[0])))
3443 if (GET_CODE (operands[0]) != REG)
3444 operands[0] = adj_offsettable_operand (operands[0], 2);
3445 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3446 INTVAL (operands[2]) & 0xffff);
3447 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3449 if (operands[2] == const0_rtx)
3450 return \"clr%.w %0\";
3451 return \"and%.w %2,%0\";
3453 if (GET_CODE (operands[2]) == CONST_INT
3454 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3455 && (DATA_REG_P (operands[0])
3456 || offsettable_memref_p (operands[0])))
3458 if (DATA_REG_P (operands[0]))
3460 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3464 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3465 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3467 /* This does not set condition codes in a standard way. */
3469 return \"bclr %1,%0\";
3471 return \"and%.l %2,%0\";
3474 (define_insn "andsi3_5200"
3475 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3476 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3477 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3481 (define_insn "andhi3"
3482 [(set (match_operand:HI 0 "general_operand" "=m,d")
3483 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3484 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3489 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3490 (and:HI (match_dup 0)
3491 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3496 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3497 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3502 (define_insn "andqi3"
3503 [(set (match_operand:QI 0 "general_operand" "=m,d")
3504 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3505 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3510 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3511 (and:QI (match_dup 0)
3512 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3517 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3518 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3523 ;; inclusive-or instructions
3525 (define_expand "iorsi3"
3526 [(set (match_operand:SI 0 "general_operand" "")
3527 (ior:SI (match_operand:SI 1 "general_operand" "")
3528 (match_operand:SI 2 "general_operand" "")))]
3532 (define_insn "iorsi3_internal"
3533 [(set (match_operand:SI 0 "general_operand" "=m,d")
3534 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3535 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3539 register int logval;
3540 if (GET_CODE (operands[2]) == CONST_INT
3541 && INTVAL (operands[2]) >> 16 == 0
3542 && (DATA_REG_P (operands[0])
3543 || offsettable_memref_p (operands[0])))
3545 if (GET_CODE (operands[0]) != REG)
3546 operands[0] = adj_offsettable_operand (operands[0], 2);
3547 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3549 return \"or%.w %2,%0\";
3551 if (GET_CODE (operands[2]) == CONST_INT
3552 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3553 && (DATA_REG_P (operands[0])
3554 || offsettable_memref_p (operands[0])))
3556 if (DATA_REG_P (operands[0]))
3558 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3562 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3563 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3566 return \"bset %1,%0\";
3568 return \"or%.l %2,%0\";
3571 (define_insn "iorsi3_5200"
3572 [(set (match_operand:SI 0 "general_operand" "=m,d")
3573 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3574 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3578 (define_insn "iorhi3"
3579 [(set (match_operand:HI 0 "general_operand" "=m,d")
3580 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3581 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3586 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3587 (ior:HI (match_dup 0)
3588 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3593 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3594 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3599 (define_insn "iorqi3"
3600 [(set (match_operand:QI 0 "general_operand" "=m,d")
3601 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3602 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3607 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3608 (ior:QI (match_dup 0)
3609 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3614 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3615 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3620 ;; On all 68k models, this makes faster code in a special case.
3621 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3623 (define_insn "iorsi_zexthi_ashl16"
3624 [(set (match_operand:SI 0 "general_operand" "=d,d")
3625 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3626 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3632 if (GET_CODE (operands[2]) != REG)
3634 operands[2] = adj_offsettable_operand (operands[2], 2);
3635 output_asm_insn (\"move%.w %2,%0\", operands);
3637 return \"swap %0\;mov%.w %1,%0\";
3641 [(set (match_operand:SI 0 "general_operand" "=o,d")
3642 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3643 (match_operand:SI 2 "general_operand" "0,0")))]
3650 byte_mode = (GET_MODE(operands[1]) == QImode);
3651 if (GET_CODE (operands[0]) == MEM)
3652 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3654 return \"or%.b %1,%0\";
3656 return \"or%.w %1,%0\";
3661 (define_expand "xorsi3"
3662 [(set (match_operand:SI 0 "general_operand" "")
3663 (xor:SI (match_operand:SI 1 "general_operand" "")
3664 (match_operand:SI 2 "general_operand" "")))]
3668 (define_insn "xorsi3_internal"
3669 [(set (match_operand:SI 0 "general_operand" "=do,m")
3670 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3671 (match_operand:SI 2 "general_operand" "di,dKs")))]
3675 if (GET_CODE (operands[2]) == CONST_INT
3676 && INTVAL (operands[2]) >> 16 == 0
3677 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3679 if (! DATA_REG_P (operands[0]))
3680 operands[0] = adj_offsettable_operand (operands[0], 2);
3681 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3683 return \"eor%.w %2,%0\";
3685 return \"eor%.l %2,%0\";
3688 (define_insn "xorsi3_5200"
3689 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3690 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3691 (match_operand:SI 2 "general_operand" "d,Ks")))]
3695 (define_insn "xorhi3"
3696 [(set (match_operand:HI 0 "general_operand" "=dm")
3697 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3698 (match_operand:HI 2 "general_operand" "dn")))]
3703 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3704 (xor:HI (match_dup 0)
3705 (match_operand:HI 1 "general_operand" "dn")))]
3710 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3711 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3716 (define_insn "xorqi3"
3717 [(set (match_operand:QI 0 "general_operand" "=dm")
3718 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3719 (match_operand:QI 2 "general_operand" "dn")))]
3724 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3725 (xor:QI (match_dup 0)
3726 (match_operand:QI 1 "general_operand" "dn")))]
3731 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3732 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3737 ;; negation instructions
3739 (define_expand "negdi2"
3740 [(set (match_operand:DI 0 "general_operand" "")
3741 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3746 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3748 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3752 (define_insn "negdi2_internal"
3753 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3754 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3758 if (which_alternative == 0)
3759 return \"neg%.l %0\;negx%.l %0\";
3760 if (GET_CODE (operands[0]) == REG)
3761 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3763 operands[1] = adj_offsettable_operand (operands[0], 4);
3764 if (ADDRESS_REG_P (operands[0]))
3765 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3767 return \"neg%.l %1\;negx%.l %0\";
3770 (define_insn "negdi2_5200"
3771 [(set (match_operand:DI 0 "general_operand" "=d")
3772 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3776 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3777 return \"neg%.l %1\;negx%.l %0\";
3780 (define_expand "negsi2"
3781 [(set (match_operand:SI 0 "general_operand" "")
3782 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3787 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3789 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3793 (define_insn "negsi2_internal"
3794 [(set (match_operand:SI 0 "general_operand" "=dm")
3795 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3799 (define_insn "negsi2_5200"
3800 [(set (match_operand:SI 0 "general_operand" "=d")
3801 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3805 (define_insn "neghi2"
3806 [(set (match_operand:HI 0 "general_operand" "=dm")
3807 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3812 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3813 (neg:HI (match_dup 0)))]
3817 (define_insn "negqi2"
3818 [(set (match_operand:QI 0 "general_operand" "=dm")
3819 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3824 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3825 (neg:QI (match_dup 0)))]
3829 ;; If using software floating point, just flip the sign bit.
3831 (define_expand "negsf2"
3832 [(set (match_operand:SF 0 "general_operand" "")
3833 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3837 if (!TARGET_FPA && !TARGET_68881)
3842 target = operand_subword_force (operands[0], 0, SFmode);
3843 result = expand_binop (SImode, xor_optab,
3844 operand_subword_force (operands[1], 0, SFmode),
3845 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3849 if (result != target)
3850 emit_move_insn (result, target);
3852 /* Make a place for REG_EQUAL. */
3853 emit_move_insn (operands[0], operands[0]);
3859 [(set (match_operand:SF 0 "general_operand" "=x,y")
3860 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3865 [(set (match_operand:SF 0 "general_operand" "=f,d")
3866 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3870 if (DATA_REG_P (operands[0]))
3872 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3873 return \"bchg %1,%0\";
3875 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3876 return \"f%$neg%.x %1,%0\";
3877 return \"f%$neg%.s %f1,%0\";
3880 (define_expand "negdf2"
3881 [(set (match_operand:DF 0 "general_operand" "")
3882 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3886 if (!TARGET_FPA && !TARGET_68881)
3893 target = operand_subword (operands[0], 0, 1, DFmode);
3894 result = expand_binop (SImode, xor_optab,
3895 operand_subword_force (operands[1], 0, DFmode),
3896 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3900 if (result != target)
3901 emit_move_insn (result, target);
3903 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3904 operand_subword_force (operands[1], 1, DFmode));
3906 insns = get_insns ();
3909 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3915 [(set (match_operand:DF 0 "general_operand" "=x,y")
3916 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3921 [(set (match_operand:DF 0 "general_operand" "=f,d")
3922 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3926 if (DATA_REG_P (operands[0]))
3928 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3929 return \"bchg %1,%0\";
3931 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3932 return \"f%&neg%.x %1,%0\";
3933 return \"f%&neg%.d %f1,%0\";
3936 ;; Sqrt instruction for the 68881
3938 (define_insn "sqrtsf2"
3939 [(set (match_operand:SF 0 "general_operand" "=f")
3940 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3944 if (FP_REG_P (operands[1]))
3945 return \"f%$sqrt%.x %1,%0\";
3947 return \"f%$sqrt%.s %1,%0\";
3950 (define_insn "sqrtdf2"
3951 [(set (match_operand:DF 0 "general_operand" "=f")
3952 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3956 if (FP_REG_P (operands[1]))
3957 return \"f%&sqrt%.x %1,%0\";
3959 return \"f%&sqrt%.d %1,%0\";
3962 ;; Absolute value instructions
3963 ;; If using software floating point, just zero the sign bit.
3965 (define_expand "abssf2"
3966 [(set (match_operand:SF 0 "general_operand" "")
3967 (abs:SF (match_operand:SF 1 "general_operand" "")))]
3971 if (!TARGET_FPA && !TARGET_68881)
3976 target = operand_subword_force (operands[0], 0, SFmode);
3977 result = expand_binop (SImode, and_optab,
3978 operand_subword_force (operands[1], 0, SFmode),
3979 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
3983 if (result != target)
3984 emit_move_insn (result, target);
3986 /* Make a place for REG_EQUAL. */
3987 emit_move_insn (operands[0], operands[0]);
3993 [(set (match_operand:SF 0 "general_operand" "=x,y")
3994 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3999 [(set (match_operand:SF 0 "general_operand" "=f")
4000 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4004 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4005 return \"f%$abs%.x %1,%0\";
4006 return \"f%$abs%.s %f1,%0\";
4009 (define_expand "absdf2"
4010 [(set (match_operand:DF 0 "general_operand" "")
4011 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4015 if (!TARGET_FPA && !TARGET_68881)
4022 target = operand_subword (operands[0], 0, 1, DFmode);
4023 result = expand_binop (SImode, and_optab,
4024 operand_subword_force (operands[1], 0, DFmode),
4025 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4029 if (result != target)
4030 emit_move_insn (result, target);
4032 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4033 operand_subword_force (operands[1], 1, DFmode));
4035 insns = get_insns ();
4038 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4044 [(set (match_operand:DF 0 "general_operand" "=x,y")
4045 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4050 [(set (match_operand:DF 0 "general_operand" "=f")
4051 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4055 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4056 return \"f%&abs%.x %1,%0\";
4057 return \"f%&abs%.d %f1,%0\";
4060 ;; one complement instructions
4062 ;; "one_cmpldi2" is only here to help combine().
4063 (define_insn "one_cmpldi2"
4064 [(set (match_operand:DI 0 "general_operand" "=dm")
4065 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4070 if (GET_CODE (operands[0]) == REG)
4071 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4072 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4073 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4074 operands[1] = operands[0];
4076 operands[1] = adj_offsettable_operand (operands[0], 4);
4077 return \"not%.l %1\;not%.l %0\";
4080 (define_expand "one_cmplsi2"
4081 [(set (match_operand:SI 0 "general_operand" "")
4082 (not:SI (match_operand:SI 1 "general_operand" "")))]
4087 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4089 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4093 (define_insn "one_cmplsi2_internal"
4094 [(set (match_operand:SI 0 "general_operand" "=dm")
4095 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4099 (define_insn "one_cmplsi2_5200"
4100 [(set (match_operand:SI 0 "general_operand" "=d")
4101 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4105 (define_insn "one_cmplhi2"
4106 [(set (match_operand:HI 0 "general_operand" "=dm")
4107 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4112 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4113 (not:HI (match_dup 0)))]
4117 (define_insn "one_cmplqi2"
4118 [(set (match_operand:QI 0 "general_operand" "=dm")
4119 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4124 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4125 (not:QI (match_dup 0)))]
4129 ;; arithmetic shift instructions
4130 ;; We don't need the shift memory by 1 bit instruction
4132 (define_insn "ashldi_extsi"
4133 [(set (match_operand:DI 0 "general_operand" "=ro")
4135 (match_operator:DI 2 "extend_operator"
4136 [(match_operand:SI 1 "general_operand" "rm")])
4142 if (GET_CODE (operands[0]) == REG)
4143 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4145 operands[2] = adj_offsettable_operand (operands[0], 4);
4146 if (ADDRESS_REG_P (operands[0]))
4147 return \"move%.l %1,%0\;sub%.l %2,%2\";
4149 return \"move%.l %1,%0\;clr%.l %2\";
4152 (define_insn "ashldi_sexthi"
4153 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4154 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4156 (clobber (match_scratch:SI 2 "=a,X"))]
4161 if (GET_CODE (operands[0]) == MEM)
4163 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4164 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4165 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4166 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4169 operands[3] = adj_offsettable_operand (operands[0], 4);
4170 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4173 else if (DATA_REG_P (operands[0]))
4174 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4176 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4179 (define_insn "ashldi_const32"
4180 [(set (match_operand:DI 0 "general_operand" "=rm")
4181 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4187 if (GET_CODE (operands[1]) == REG)
4188 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4190 operands[3] = adj_offsettable_operand (operands[1], 4);
4191 if (GET_CODE (operands[0]) == REG)
4192 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4193 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4194 return \"clr%.l %0\;move%.l %3,%0\";
4195 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4196 return \"move%.l %3,%0\;clr%.l %0\";
4198 operands[2] = adj_offsettable_operand (operands[0], 4);
4199 if (ADDRESS_REG_P (operands[2]))
4200 return \"move%.l %3,%0\;sub%.l %2,%2\";
4202 return \"move%.l %3,%0\;clr%.l %2\";
4205 ;; The predicate below must be general_operand, because ashldi3 allows that
4206 (define_insn "ashldi_const"
4207 [(set (match_operand:DI 0 "general_operand" "=d")
4208 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4209 (match_operand 2 "const_int_operand" "n")))]
4210 "(INTVAL (operands[2]) == 1
4211 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4212 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4215 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4216 if (INTVAL (operands[2]) == 1)
4217 return \"add%.l %1,%1\;addx%.l %0,%0\";
4218 else if (INTVAL (operands[2]) == 8)
4219 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4220 else if (INTVAL (operands[2]) == 16)
4221 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4222 else if (INTVAL (operands[2]) == 2)
4223 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4224 else/* if (INTVAL (operands[2]) == 3)*/
4225 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4228 (define_expand "ashldi3"
4229 [(set (match_operand:DI 0 "general_operand" "")
4230 (ashift:DI (match_operand:DI 1 "general_operand" "")
4231 (match_operand 2 "const_int_operand" "")))]
4235 if (GET_CODE (operands[2]) != CONST_INT
4236 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4237 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4238 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4242 ;; On most 68k models, this makes faster code in a special case.
4244 (define_insn "ashlsi_16"
4245 [(set (match_operand:SI 0 "register_operand" "=d")
4246 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4252 return \"swap %0\;clr%.w %0\";
4255 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4256 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4258 ;; On the 68000, this makes faster code in a special case.
4260 (define_insn "ashlsi_17_24"
4261 [(set (match_operand:SI 0 "register_operand" "=d")
4262 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4263 (match_operand:SI 2 "const_int_operand" "n")))]
4264 "(! TARGET_68020 && !TARGET_5200
4265 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4270 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4271 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4274 (define_insn "ashlsi3"
4275 [(set (match_operand:SI 0 "register_operand" "=d")
4276 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4277 (match_operand:SI 2 "general_operand" "dI")))]
4281 if (operands[2] == const1_rtx)
4283 cc_status.flags = CC_NO_OVERFLOW;
4284 return \"add%.l %0,%0\";
4286 return \"lsl%.l %2,%0\";
4289 (define_insn "ashlhi3"
4290 [(set (match_operand:HI 0 "register_operand" "=d")
4291 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4292 (match_operand:HI 2 "general_operand" "dI")))]
4297 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4298 (ashift:HI (match_dup 0)
4299 (match_operand:HI 1 "general_operand" "dI")))]
4303 (define_insn "ashlqi3"
4304 [(set (match_operand:QI 0 "register_operand" "=d")
4305 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4306 (match_operand:QI 2 "general_operand" "dI")))]
4311 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4312 (ashift:QI (match_dup 0)
4313 (match_operand:QI 1 "general_operand" "dI")))]
4317 ;; On most 68k models, this makes faster code in a special case.
4319 (define_insn "ashrsi_16"
4320 [(set (match_operand:SI 0 "register_operand" "=d")
4321 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4324 "swap %0\;ext%.l %0")
4326 ;; On the 68000, this makes faster code in a special case.
4329 [(set (match_operand:SI 0 "register_operand" "=d")
4330 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4331 (match_operand:SI 2 "const_int_operand" "n")))]
4332 "(! TARGET_68020 && !TARGET_5200
4333 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4336 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4337 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4340 (define_insn "subreghi1ashrdi_const32"
4341 [(set (match_operand:HI 0 "general_operand" "=rm")
4342 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4343 (const_int 32)) 1))]
4347 if (GET_CODE (operands[1]) != REG)
4348 operands[1] = adj_offsettable_operand (operands[1], 2);
4349 return \"move%.w %1,%0\";
4352 (define_insn "subregsi1ashrdi_const32"
4353 [(set (match_operand:SI 0 "general_operand" "=rm")
4354 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4355 (const_int 32)) 1))]
4359 return \"move%.l %1,%0\";
4362 (define_insn "ashrdi_const32"
4363 [(set (match_operand:DI 0 "register_operand" "=d")
4364 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4370 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4372 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4374 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4377 (define_insn "ashrdi_const32_mem"
4378 [(set (match_operand:DI 0 "general_operand" "=o,<")
4379 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4381 (clobber (match_scratch:SI 2 "=d,d"))]
4386 if (which_alternative == 1)
4387 operands[3] = operands[0];
4389 operands[3] = adj_offsettable_operand (operands[0], 4);
4391 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4393 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4396 ;; The predicate below must be general_operand, because ashrdi3 allows that
4397 (define_insn "ashrdi_const"
4398 [(set (match_operand:DI 0 "general_operand" "=d")
4399 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4400 (match_operand 2 "const_int_operand" "n")))]
4402 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4403 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4404 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31
4405 || INTVAL (operands[2]) == 63))"
4408 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4409 if (INTVAL (operands[2]) == 63)
4410 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4412 if (INTVAL (operands[2]) == 1)
4413 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4414 else if (INTVAL (operands[2]) == 8)
4415 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4416 else if (INTVAL (operands[2]) == 16)
4417 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4418 else if (INTVAL (operands[2]) == 31)
4419 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4420 else if (INTVAL (operands[2]) == 2)
4421 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4422 else/* if (INTVAL (operands[2]) == 3)*/
4423 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4426 (define_expand "ashrdi3"
4427 [(set (match_operand:DI 0 "general_operand" "")
4428 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4429 (match_operand 2 "const_int_operand" "")))]
4433 if (GET_CODE (operands[2]) != CONST_INT
4434 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4435 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4436 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31
4437 && INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
4441 ;; On all 68k models, this makes faster code in a special case.
4443 (define_insn "ashrsi_31"
4444 [(set (match_operand:SI 0 "register_operand" "=d")
4445 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4450 return \"add%.l %0,%0\;subx%.l %0,%0\";
4453 (define_insn "ashrsi3"
4454 [(set (match_operand:SI 0 "register_operand" "=d")
4455 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4456 (match_operand:SI 2 "general_operand" "dI")))]
4460 (define_insn "ashrhi3"
4461 [(set (match_operand:HI 0 "register_operand" "=d")
4462 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4463 (match_operand:HI 2 "general_operand" "dI")))]
4468 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4469 (ashiftrt:HI (match_dup 0)
4470 (match_operand:HI 1 "general_operand" "dI")))]
4474 (define_insn "ashrqi3"
4475 [(set (match_operand:QI 0 "register_operand" "=d")
4476 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4477 (match_operand:QI 2 "general_operand" "dI")))]
4482 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4483 (ashiftrt:QI (match_dup 0)
4484 (match_operand:QI 1 "general_operand" "dI")))]
4488 ;; logical shift instructions
4490 ;; commented out because of reload problems in 950612-1.c
4493 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4494 ;; (const_int 32)) 1))
4495 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4496 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4497 ;; (const_int 32)) 1))]
4501 ;; return \"move%.l %0,%1\";
4506 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4507 ;; (const_int 32)) 0))
4508 ;; (set (match_operand:DI 1 "general_operand" "=do")
4509 ;; (lshiftrt:DI (match_dup 0)
4510 ;; (const_int 32)))]
4514 ;; if (GET_CODE (operands[1]) == REG)
4515 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4517 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4518 ;; return \"move%.l %0,%2\;clr%.l %1\";
4521 (define_insn "subreg1lshrdi_const32"
4522 [(set (match_operand:SI 0 "general_operand" "=rm")
4523 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4524 (const_int 32)) 1))]
4528 return \"move%.l %1,%0\";
4531 (define_insn "lshrdi_const32"
4532 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4533 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4539 if (which_alternative == 1)
4540 return \"move%.l %1,%0\;clr%.l %0\";
4541 if (which_alternative == 2)
4542 return \"clr%.l %0\;move%.l %1,%0\";
4543 if (GET_CODE (operands[0]) == REG)
4544 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4546 operands[2] = adj_offsettable_operand (operands[0], 4);
4547 if (GET_CODE (operands[1]) == REG)
4548 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4550 operands[3] = adj_offsettable_operand (operands[1], 4);
4551 if (ADDRESS_REG_P (operands[0]))
4552 return \"move%.l %1,%2\;sub%.l %0,%0\";
4554 return \"move%.l %1,%2\;clr%.l %0\";
4557 ;; The predicate below must be general_operand, because lshrdi3 allows that
4558 (define_insn "lshrdi_const"
4559 [(set (match_operand:DI 0 "general_operand" "=d")
4560 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4561 (match_operand 2 "const_int_operand" "n")))]
4563 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4564 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4565 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4568 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4569 if (INTVAL (operands[2]) == 63)
4570 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4572 if (INTVAL (operands[2]) == 1)
4573 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4574 else if (INTVAL (operands[2]) == 8)
4575 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4576 else if (INTVAL (operands[2]) == 16)
4577 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4578 else if (INTVAL (operands[2]) == 2)
4579 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4580 else /*if (INTVAL (operands[2]) == 3)*/
4581 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4584 (define_expand "lshrdi3"
4585 [(set (match_operand:DI 0 "general_operand" "")
4586 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4587 (match_operand 2 "const_int_operand" "")))]
4591 if (GET_CODE (operands[2]) != CONST_INT
4592 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4593 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4594 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4595 && INTVAL (operands[2]) != 63))
4599 ;; On all 68k models, this makes faster code in a special case.
4601 (define_insn "lshrsi_31"
4602 [(set (match_operand:SI 0 "register_operand" "=d")
4603 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4608 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4611 ;; On most 68k models, this makes faster code in a special case.
4613 (define_insn "lshrsi_16"
4614 [(set (match_operand:SI 0 "register_operand" "=d")
4615 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4621 return \"clr%.w %0\;swap %0\";
4624 ;; On the 68000, this makes faster code in a special case.
4626 (define_insn "lshrsi_17_24"
4627 [(set (match_operand:SI 0 "register_operand" "=d")
4628 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4629 (match_operand:SI 2 "const_int_operand" "n")))]
4630 "(! TARGET_68020 && !TARGET_5200
4631 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4634 /* I think lsr%.w sets the CC properly. */
4635 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4636 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4639 (define_insn "lshrsi3"
4640 [(set (match_operand:SI 0 "register_operand" "=d")
4641 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4642 (match_operand:SI 2 "general_operand" "dI")))]
4646 (define_insn "lshrhi3"
4647 [(set (match_operand:HI 0 "register_operand" "=d")
4648 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4649 (match_operand:HI 2 "general_operand" "dI")))]
4654 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4655 (lshiftrt:HI (match_dup 0)
4656 (match_operand:HI 1 "general_operand" "dI")))]
4660 (define_insn "lshrqi3"
4661 [(set (match_operand:QI 0 "register_operand" "=d")
4662 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4663 (match_operand:QI 2 "general_operand" "dI")))]
4668 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4669 (lshiftrt:QI (match_dup 0)
4670 (match_operand:QI 1 "general_operand" "dI")))]
4674 ;; rotate instructions
4676 (define_insn "rotlsi3"
4677 [(set (match_operand:SI 0 "register_operand" "=d")
4678 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4679 (match_operand:SI 2 "general_operand" "dINO")))]
4683 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4685 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4687 operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - INTVAL (operands[2]));
4688 return \"ror%.l %2,%0\";
4691 return \"rol%.l %2,%0\";
4694 (define_insn "rotlhi3"
4695 [(set (match_operand:HI 0 "register_operand" "=d")
4696 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4697 (match_operand:HI 2 "general_operand" "dIP")))]
4701 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4703 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4704 return \"ror%.w %2,%0\";
4707 return \"rol%.w %2,%0\";
4711 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4712 (rotate:HI (match_dup 0)
4713 (match_operand:HI 1 "general_operand" "dIP")))]
4717 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4719 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4720 return \"ror%.w %2,%0\";
4723 return \"rol%.w %2,%0\";
4726 (define_insn "rotlqi3"
4727 [(set (match_operand:QI 0 "register_operand" "=d")
4728 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4729 (match_operand:QI 2 "general_operand" "dI")))]
4733 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4735 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
4736 return \"ror%.b %2,%0\";
4739 return \"rol%.b %2,%0\";
4743 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4744 (rotate:QI (match_dup 0)
4745 (match_operand:QI 1 "general_operand" "dI")))]
4749 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
4751 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
4752 return \"ror%.b %2,%0\";
4755 return \"rol%.b %2,%0\";
4758 (define_insn "rotrsi3"
4759 [(set (match_operand:SI 0 "register_operand" "=d")
4760 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4761 (match_operand:SI 2 "general_operand" "dI")))]
4765 (define_insn "rotrhi3"
4766 [(set (match_operand:HI 0 "register_operand" "=d")
4767 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4768 (match_operand:HI 2 "general_operand" "dI")))]
4773 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4774 (rotatert:HI (match_dup 0)
4775 (match_operand:HI 1 "general_operand" "dI")))]
4779 (define_insn "rotrqi3"
4780 [(set (match_operand:QI 0 "register_operand" "=d")
4781 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4782 (match_operand:QI 2 "general_operand" "dI")))]
4787 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4788 (rotatert:QI (match_dup 0)
4789 (match_operand:QI 1 "general_operand" "dI")))]
4794 ;; Bit set/clear in memory byte.
4796 ;; set bit, bit number is int
4797 (define_insn "bsetmemqi"
4798 [(set (match_operand:QI 0 "memory_operand" "+m")
4799 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4800 (match_operand:SI 1 "general_operand" "d")) 0)
4806 return \"bset %1,%0\";
4809 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4811 [(set (match_operand:QI 0 "memory_operand" "+m")
4812 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4813 (match_operator:SI 2 "extend_operator"
4814 [(match_operand 1 "general_operand" "d")])) 0)
4820 return \"bset %1,%0\";
4823 ;; clear bit, bit number is int
4824 (define_insn "bclrmemqi"
4825 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4827 (minus:SI (const_int 7)
4828 (match_operand:SI 1 "general_operand" "d")))
4834 return \"bclr %1,%0\";
4837 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4839 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4841 (minus:SI (const_int 7)
4842 (match_operator:SI 2 "extend_operator"
4843 [(match_operand 1 "general_operand" "d")])))
4849 return \"bclr %1,%0\";
4852 ;; Special cases of bit-field insns which we should
4853 ;; recognize in preference to the general case.
4854 ;; These handle aligned 8-bit and 16-bit fields,
4855 ;; which can usually be done with move instructions.
4858 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4859 ; alignment of structure members is specified.
4861 ; The move is allowed to be odd byte aligned, because that's still faster
4862 ; than an odd byte aligned bit field instruction.
4865 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4867 (match_operand:SI 2 "const_int_operand" "n"))
4868 (match_operand:SI 3 "general_operand" "rmi"))]
4869 "TARGET_68020 && TARGET_BITFIELD
4870 && (INTVAL (operands[2]) % 8) == 0
4871 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4875 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4877 return \"move%.l %3,%0\";
4881 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4882 (match_operand:SI 1 "const_int_operand" "n")
4883 (match_operand:SI 2 "const_int_operand" "n"))
4884 (match_operand:SI 3 "register_operand" "d"))]
4885 "TARGET_68020 && TARGET_BITFIELD
4886 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4887 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4888 && (GET_CODE (operands[0]) == REG
4889 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4892 if (REG_P (operands[0]))
4894 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4895 return \"bfins %3,%0{%b2:%b1}\";
4899 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4901 if (GET_CODE (operands[3]) == MEM)
4902 operands[3] = adj_offsettable_operand (operands[3],
4903 (32 - INTVAL (operands[1])) / 8);
4904 if (INTVAL (operands[1]) == 8)
4905 return \"move%.b %3,%0\";
4906 return \"move%.w %3,%0\";
4911 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4912 ; alignment of structure members is specified.
4914 ; The move is allowed to be odd byte aligned, because that's still faster
4915 ; than an odd byte aligned bit field instruction.
4918 [(set (match_operand:SI 0 "general_operand" "=rm")
4919 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4921 (match_operand:SI 3 "const_int_operand" "n")))]
4922 "TARGET_68020 && TARGET_BITFIELD
4923 && (INTVAL (operands[3]) % 8) == 0
4924 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4928 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4930 return \"move%.l %1,%0\";
4934 [(set (match_operand:SI 0 "general_operand" "=&d")
4935 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4936 (match_operand:SI 2 "const_int_operand" "n")
4937 (match_operand:SI 3 "const_int_operand" "n")))]
4938 "TARGET_68020 && TARGET_BITFIELD
4939 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4940 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4941 && (GET_CODE (operands[1]) == REG
4942 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4945 cc_status.flags |= CC_NOT_NEGATIVE;
4946 if (REG_P (operands[1]))
4948 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4949 return \"bfextu %1{%b3:%b2},%0\";
4953 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4955 output_asm_insn (\"clr%.l %0\", operands);
4956 if (GET_CODE (operands[0]) == MEM)
4957 operands[0] = adj_offsettable_operand (operands[0],
4958 (32 - INTVAL (operands[1])) / 8);
4959 if (INTVAL (operands[2]) == 8)
4960 return \"move%.b %1,%0\";
4961 return \"move%.w %1,%0\";
4965 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4966 ; alignment of structure members is specified.
4968 ; The move is allowed to be odd byte aligned, because that's still faster
4969 ; than an odd byte aligned bit field instruction.
4972 [(set (match_operand:SI 0 "general_operand" "=rm")
4973 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4975 (match_operand:SI 3 "const_int_operand" "n")))]
4976 "TARGET_68020 && TARGET_BITFIELD
4977 && (INTVAL (operands[3]) % 8) == 0
4978 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4982 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4984 return \"move%.l %1,%0\";
4988 [(set (match_operand:SI 0 "general_operand" "=d")
4989 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4990 (match_operand:SI 2 "const_int_operand" "n")
4991 (match_operand:SI 3 "const_int_operand" "n")))]
4992 "TARGET_68020 && TARGET_BITFIELD
4993 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4994 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4995 && (GET_CODE (operands[1]) == REG
4996 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4999 if (REG_P (operands[1]))
5001 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5002 return \"bfexts %1{%b3:%b2},%0\";
5006 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5008 if (INTVAL (operands[2]) == 8)
5009 return \"move%.b %1,%0\;extb%.l %0\";
5010 return \"move%.w %1,%0\;ext%.l %0\";
5013 ;; Bit field instructions, general cases.
5014 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5015 ;; so that its address is reloaded.
5017 (define_expand "extv"
5018 [(set (match_operand:SI 0 "general_operand" "")
5019 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5020 (match_operand:SI 2 "general_operand" "")
5021 (match_operand:SI 3 "general_operand" "")))]
5022 "TARGET_68020 && TARGET_BITFIELD"
5026 [(set (match_operand:SI 0 "general_operand" "=d")
5027 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5028 (match_operand:SI 2 "general_operand" "di")
5029 (match_operand:SI 3 "general_operand" "di")))]
5030 "TARGET_68020 && TARGET_BITFIELD"
5031 "bfexts %1{%b3:%b2},%0")
5033 (define_expand "extzv"
5034 [(set (match_operand:SI 0 "general_operand" "")
5035 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5036 (match_operand:SI 2 "general_operand" "")
5037 (match_operand:SI 3 "general_operand" "")))]
5038 "TARGET_68020 && TARGET_BITFIELD"
5042 [(set (match_operand:SI 0 "general_operand" "=d,d")
5043 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5044 (match_operand:SI 2 "general_operand" "di,di")
5045 (match_operand:SI 3 "general_operand" "di,di")))]
5046 "TARGET_68020 && TARGET_BITFIELD"
5049 if (GET_CODE (operands[2]) == CONST_INT)
5051 if (INTVAL (operands[2]) != 32)
5052 cc_status.flags |= CC_NOT_NEGATIVE;
5058 return \"bfextu %1{%b3:%b2},%0\";
5062 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5063 (match_operand:SI 1 "general_operand" "di")
5064 (match_operand:SI 2 "general_operand" "di"))
5065 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5066 (match_operand 3 "const_int_operand" "n")))]
5067 "TARGET_68020 && TARGET_BITFIELD
5068 && (INTVAL (operands[3]) == -1
5069 || (GET_CODE (operands[1]) == CONST_INT
5070 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5074 return \"bfchg %0{%b2:%b1}\";
5078 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5079 (match_operand:SI 1 "general_operand" "di")
5080 (match_operand:SI 2 "general_operand" "di"))
5082 "TARGET_68020 && TARGET_BITFIELD"
5086 return \"bfclr %0{%b2:%b1}\";
5090 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5091 (match_operand:SI 1 "general_operand" "di")
5092 (match_operand:SI 2 "general_operand" "di"))
5094 "TARGET_68020 && TARGET_BITFIELD"
5098 return \"bfset %0{%b2:%b1}\";
5101 (define_expand "insv"
5102 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5103 (match_operand:SI 1 "general_operand" "")
5104 (match_operand:SI 2 "general_operand" ""))
5105 (match_operand:SI 3 "register_operand" ""))]
5106 "TARGET_68020 && TARGET_BITFIELD"
5110 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5111 (match_operand:SI 1 "general_operand" "di")
5112 (match_operand:SI 2 "general_operand" "di"))
5113 (match_operand:SI 3 "register_operand" "d"))]
5114 "TARGET_68020 && TARGET_BITFIELD"
5115 "bfins %3,%0{%b2:%b1}")
5117 ;; Now recognize bit field insns that operate on registers
5118 ;; (or at least were intended to do so).
5121 [(set (match_operand:SI 0 "general_operand" "=d")
5122 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5123 (match_operand:SI 2 "general_operand" "di")
5124 (match_operand:SI 3 "general_operand" "di")))]
5125 "TARGET_68020 && TARGET_BITFIELD"
5126 "bfexts %1{%b3:%b2},%0")
5129 [(set (match_operand:SI 0 "general_operand" "=d")
5130 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5131 (match_operand:SI 2 "general_operand" "di")
5132 (match_operand:SI 3 "general_operand" "di")))]
5133 "TARGET_68020 && TARGET_BITFIELD"
5136 if (GET_CODE (operands[2]) == CONST_INT)
5138 if (INTVAL (operands[2]) != 32)
5139 cc_status.flags |= CC_NOT_NEGATIVE;
5145 return \"bfextu %1{%b3:%b2},%0\";
5149 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5150 (match_operand:SI 1 "general_operand" "di")
5151 (match_operand:SI 2 "general_operand" "di"))
5153 "TARGET_68020 && TARGET_BITFIELD"
5157 return \"bfclr %0{%b2:%b1}\";
5161 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5162 (match_operand:SI 1 "general_operand" "di")
5163 (match_operand:SI 2 "general_operand" "di"))
5165 "TARGET_68020 && TARGET_BITFIELD"
5169 return \"bfset %0{%b2:%b1}\";
5173 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5174 (match_operand:SI 1 "general_operand" "di")
5175 (match_operand:SI 2 "general_operand" "di"))
5176 (match_operand:SI 3 "register_operand" "d"))]
5177 "TARGET_68020 && TARGET_BITFIELD"
5181 /* These special cases are now recognized by a specific pattern. */
5182 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5183 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5184 return \"move%.w %3,%0\";
5185 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5186 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5187 return \"move%.b %3,%0\";
5189 return \"bfins %3,%0{%b2:%b1}\";
5192 ;; Special patterns for optimizing bit-field instructions.
5196 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5197 (match_operand:SI 1 "const_int_operand" "n")
5198 (match_operand:SI 2 "general_operand" "di")))]
5199 "TARGET_68020 && TARGET_BITFIELD"
5202 if (operands[1] == const1_rtx
5203 && GET_CODE (operands[2]) == CONST_INT)
5205 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5206 return output_btst (operands,
5207 gen_rtx (CONST_INT, VOIDmode,
5208 width - INTVAL (operands[2])),
5211 /* Pass 1000 as SIGNPOS argument so that btst will
5212 not think we are testing the sign bit for an `and'
5213 and assume that nonzero implies a negative result. */
5215 if (INTVAL (operands[1]) != 32)
5216 cc_status.flags = CC_NOT_NEGATIVE;
5217 return \"bftst %0{%b2:%b1}\";
5221 ;;; now handle the register cases
5224 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5225 (match_operand:SI 1 "const_int_operand" "n")
5226 (match_operand:SI 2 "general_operand" "di")))]
5227 "TARGET_68020 && TARGET_BITFIELD"
5230 if (operands[1] == const1_rtx
5231 && GET_CODE (operands[2]) == CONST_INT)
5233 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5234 return output_btst (operands,
5235 gen_rtx (CONST_INT, VOIDmode,
5236 width - INTVAL (operands[2])),
5239 /* Pass 1000 as SIGNPOS argument so that btst will
5240 not think we are testing the sign bit for an `and'
5241 and assume that nonzero implies a negative result. */
5243 if (INTVAL (operands[1]) != 32)
5244 cc_status.flags = CC_NOT_NEGATIVE;
5245 return \"bftst %0{%b2:%b1}\";
5248 (define_insn "scc0_di"
5249 [(set (match_operand:QI 0 "general_operand" "=dm")
5250 (match_operator 1 "valid_dbcc_comparison_p"
5251 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5255 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5258 (define_insn "scc_di"
5259 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5260 (match_operator 1 "valid_dbcc_comparison_p"
5261 [(match_operand:DI 2 "general_operand" "ro,r")
5262 (match_operand:DI 3 "general_operand" "r,ro")]))]
5266 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5269 (define_expand "seq"
5270 [(set (match_operand:QI 0 "general_operand" "")
5271 (eq:QI (cc0) (const_int 0)))]
5275 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5277 m68k_last_compare_had_fp_operands = 0;
5283 [(set (match_operand:QI 0 "general_operand" "=dm")
5284 (eq:QI (cc0) (const_int 0)))]
5287 cc_status = cc_prev_status;
5288 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5291 (define_expand "sne"
5292 [(set (match_operand:QI 0 "general_operand" "")
5293 (ne:QI (cc0) (const_int 0)))]
5297 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5299 m68k_last_compare_had_fp_operands = 0;
5305 [(set (match_operand:QI 0 "general_operand" "=dm")
5306 (ne:QI (cc0) (const_int 0)))]
5309 cc_status = cc_prev_status;
5310 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5313 (define_expand "sgt"
5314 [(set (match_operand:QI 0 "general_operand" "")
5315 (gt:QI (cc0) (const_int 0)))]
5319 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5321 m68k_last_compare_had_fp_operands = 0;
5327 [(set (match_operand:QI 0 "general_operand" "=dm")
5328 (gt:QI (cc0) (const_int 0)))]
5331 cc_status = cc_prev_status;
5332 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5336 [(set (match_operand:QI 0 "general_operand" "=dm")
5337 (gtu:QI (cc0) (const_int 0)))]
5339 "* cc_status = cc_prev_status;
5340 return \"shi %0\"; ")
5342 (define_expand "slt"
5343 [(set (match_operand:QI 0 "general_operand" "")
5344 (lt:QI (cc0) (const_int 0)))]
5348 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5350 m68k_last_compare_had_fp_operands = 0;
5356 [(set (match_operand:QI 0 "general_operand" "=dm")
5357 (lt:QI (cc0) (const_int 0)))]
5359 "* cc_status = cc_prev_status;
5360 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5363 [(set (match_operand:QI 0 "general_operand" "=dm")
5364 (ltu:QI (cc0) (const_int 0)))]
5366 "* cc_status = cc_prev_status;
5367 return \"scs %0\"; ")
5369 (define_expand "sge"
5370 [(set (match_operand:QI 0 "general_operand" "")
5371 (ge:QI (cc0) (const_int 0)))]
5375 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5377 m68k_last_compare_had_fp_operands = 0;
5383 [(set (match_operand:QI 0 "general_operand" "=dm")
5384 (ge:QI (cc0) (const_int 0)))]
5386 "* cc_status = cc_prev_status;
5387 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5390 [(set (match_operand:QI 0 "general_operand" "=dm")
5391 (geu:QI (cc0) (const_int 0)))]
5393 "* cc_status = cc_prev_status;
5394 return \"scc %0\"; ")
5396 (define_expand "sle"
5397 [(set (match_operand:QI 0 "general_operand" "")
5398 (le:QI (cc0) (const_int 0)))]
5402 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5404 m68k_last_compare_had_fp_operands = 0;
5410 [(set (match_operand:QI 0 "general_operand" "=dm")
5411 (le:QI (cc0) (const_int 0)))]
5414 cc_status = cc_prev_status;
5415 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5419 [(set (match_operand:QI 0 "general_operand" "=dm")
5420 (leu:QI (cc0) (const_int 0)))]
5422 "* cc_status = cc_prev_status;
5423 return \"sls %0\"; ")
5425 ;; Basic conditional jump instructions.
5427 (define_insn "beq0_di"
5429 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5431 (label_ref (match_operand 1 "" ","))
5433 (clobber (match_scratch:SI 2 "=d,d"))]
5438 if (which_alternative == 1)
5440 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5442 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5444 if ((cc_prev_status.value1
5445 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5446 || (cc_prev_status.value2
5447 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5449 cc_status = cc_prev_status;
5451 return \"jbeq %l1\";
5456 if (GET_CODE (operands[0]) == REG)
5457 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5459 operands[3] = adj_offsettable_operand (operands[0], 4);
5460 if (! ADDRESS_REG_P (operands[0]))
5462 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5464 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5466 operands[4] = gen_label_rtx();
5467 if (TARGET_68020 || TARGET_5200)
5469 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5471 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5475 #ifdef SGS_CMP_ORDER
5476 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5478 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5481 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5483 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5484 CODE_LABEL_NUMBER (operands[4]));
5488 (define_insn "bne0_di"
5490 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5492 (label_ref (match_operand 1 "" ","))
5494 (clobber (match_scratch:SI 2 "=d,X"))]
5498 if ((cc_prev_status.value1
5499 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5500 || (cc_prev_status.value2
5501 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5503 cc_status = cc_prev_status;
5505 return \"jbne %l1\";
5511 if (GET_CODE (operands[0]) == REG)
5512 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5514 operands[3] = adj_offsettable_operand (operands[0], 4);
5515 if (!ADDRESS_REG_P (operands[0]))
5517 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5519 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5521 if (TARGET_68020 || TARGET_5200)
5523 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5525 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5529 #ifdef SGS_CMP_ORDER
5530 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5532 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5535 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5539 (define_insn "bge0_di"
5541 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5543 (label_ref (match_operand 1 "" ""))
5548 if ((cc_prev_status.value1
5549 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5550 || (cc_prev_status.value2
5551 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5553 cc_status = cc_prev_status;
5554 if (cc_status.flags & CC_REVERSED)
5557 return \"jble %l1\";
5565 return \"jbpl %l1\";
5572 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5573 output_asm_insn(\"tst%.l %0\", operands);
5575 /* On an address reg, cmpw may replace cmpl. */
5576 #ifdef SGS_CMP_ORDER
5577 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5579 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5583 return \"jbpl %l1\";
5589 (define_insn "blt0_di"
5591 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5593 (label_ref (match_operand 1 "" ""))
5598 if ((cc_prev_status.value1
5599 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5600 || (cc_prev_status.value2
5601 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5603 cc_status = cc_prev_status;
5604 if (cc_status.flags & CC_REVERSED)
5607 return \"jbgt %l1\";
5615 return \"jbmi %l1\";
5622 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5623 output_asm_insn(\"tst%.l %0\", operands);
5625 /* On an address reg, cmpw may replace cmpl. */
5626 #ifdef SGS_CMP_ORDER
5627 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5629 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5633 return \"jbmi %l1\";
5641 (if_then_else (eq (cc0)
5643 (label_ref (match_operand 0 "" ""))
5649 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5651 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5657 (if_then_else (ne (cc0)
5659 (label_ref (match_operand 0 "" ""))
5665 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5667 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5673 (if_then_else (gt (cc0)
5675 (label_ref (match_operand 0 "" ""))
5680 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5682 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5688 (if_then_else (gtu (cc0)
5690 (label_ref (match_operand 0 "" ""))
5695 return \"jbhi %l0\";
5703 (if_then_else (lt (cc0)
5705 (label_ref (match_operand 0 "" ""))
5710 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5712 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5718 (if_then_else (ltu (cc0)
5720 (label_ref (match_operand 0 "" ""))
5725 return \"jbcs %l0\";
5733 (if_then_else (ge (cc0)
5735 (label_ref (match_operand 0 "" ""))
5740 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5742 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5748 (if_then_else (geu (cc0)
5750 (label_ref (match_operand 0 "" ""))
5755 return \"jbcc %l0\";
5763 (if_then_else (le (cc0)
5765 (label_ref (match_operand 0 "" ""))
5770 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5772 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5778 (if_then_else (leu (cc0)
5780 (label_ref (match_operand 0 "" ""))
5785 return \"jbls %l0\";
5791 ;; Negated conditional jump instructions.
5795 (if_then_else (eq (cc0)
5798 (label_ref (match_operand 0 "" ""))))]
5803 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5805 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5811 (if_then_else (ne (cc0)
5814 (label_ref (match_operand 0 "" ""))))]
5819 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5821 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5827 (if_then_else (gt (cc0)
5830 (label_ref (match_operand 0 "" ""))))]
5834 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5836 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5842 (if_then_else (gtu (cc0)
5845 (label_ref (match_operand 0 "" ""))))]
5849 return \"jbls %l0\";
5857 (if_then_else (lt (cc0)
5860 (label_ref (match_operand 0 "" ""))))]
5864 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5866 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5872 (if_then_else (ltu (cc0)
5875 (label_ref (match_operand 0 "" ""))))]
5879 return \"jbcc %l0\";
5887 (if_then_else (ge (cc0)
5890 (label_ref (match_operand 0 "" ""))))]
5894 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5896 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5902 (if_then_else (geu (cc0)
5905 (label_ref (match_operand 0 "" ""))))]
5909 return \"jbcs %l0\";
5917 (if_then_else (le (cc0)
5920 (label_ref (match_operand 0 "" ""))))]
5924 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5926 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5932 (if_then_else (leu (cc0)
5935 (label_ref (match_operand 0 "" ""))))]
5939 return \"jbhi %l0\";
5945 ;; Unconditional and other jump instructions
5948 (label_ref (match_operand 0 "" "")))]
5952 return \"jbra %l0\";
5958 ;; We support two different ways of handling dispatch tables.
5959 ;; The NeXT uses absolute tables, and other machines use relative.
5960 ;; This define_expand can generate either kind.
5961 (define_expand "tablejump"
5962 [(parallel [(set (pc) (match_operand 0 "" ""))
5963 (use (label_ref (match_operand 1 "" "")))])]
5967 #ifdef CASE_VECTOR_PC_RELATIVE
5968 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
5969 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
5973 ;; Jump to variable address from dispatch table of absolute addresses.
5975 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5976 (use (label_ref (match_operand 1 "" "")))]
5980 return \"jmp (%0)\";
5986 ;; Jump to variable address from dispatch table of relative addresses.
5990 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
5991 (use (label_ref (match_operand 1 "" "")))]
5994 #ifdef ASM_RETURN_CASE_JUMP
5995 ASM_RETURN_CASE_JUMP;
5998 #ifdef ASM_OUTPUT_CASE_LABEL
6000 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6002 return \"jmp 6(%%pc,%0.w)\";
6007 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6009 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6010 #endif /* end !CRDS */
6015 return \"jmp 2(pc,%0.w)\";
6017 return \"jmp 2(%%pc,%0.w)\";
6018 #endif /* end !CRDS */
6025 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6027 return \"extl %0\;jmp pc@(2,%0:l)\";
6033 return \"jmp (2,pc,%0.w)\";
6035 return \"jmp pc@(2,%0:w)\";
6042 ;; Decrement-and-branch insns.
6046 (ne (match_operand:HI 0 "general_operand" "+d*g")
6048 (label_ref (match_operand 1 "" ""))
6051 (plus:HI (match_dup 0)
6057 if (DATA_REG_P (operands[0]))
6058 return \"dbra %0,%l1\";
6059 if (GET_CODE (operands[0]) == MEM)
6063 return \"sub%.w %#1,%0\;jbcc %l1\";
6065 return \"subq%.w %#1,%0\;jbcc %l1\";
6067 #else /* not MOTOROLA */
6068 return \"subqw %#1,%0\;jcc %l1\";
6072 #ifdef SGS_CMP_ORDER
6074 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6076 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6078 #else /* not SGS_CMP_ORDER */
6079 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6081 #else /* not MOTOROLA */
6082 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6089 (ne (match_operand:SI 0 "general_operand" "+d*g")
6091 (label_ref (match_operand 1 "" ""))
6094 (plus:SI (match_dup 0)
6102 if (DATA_REG_P (operands[0]))
6103 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6104 if (GET_CODE (operands[0]) == MEM)
6105 return \"sub%.l %#1,%0\;jbcc %l1\";
6107 if (DATA_REG_P (operands[0]))
6108 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6109 if (GET_CODE (operands[0]) == MEM)
6110 return \"subq%.l %#1,%0\;jbcc %l1\";
6111 #endif /* NO_ADDSUB_Q */
6112 #ifdef SGS_CMP_ORDER
6114 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6116 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6118 #else /* not SGS_CMP_ORDER */
6119 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6120 #endif /* not SGS_CMP_ORDER */
6121 #else /* not MOTOROLA */
6122 if (DATA_REG_P (operands[0]))
6123 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6124 if (GET_CODE (operands[0]) == MEM)
6125 return \"subql %#1,%0\;jcc %l1\";
6126 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6127 #endif /* not MOTOROLA */
6130 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6135 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6138 (label_ref (match_operand 1 "" ""))
6141 (plus:HI (match_dup 0)
6143 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6149 if (DATA_REG_P (operands[0]))
6150 return \"dbra %0,%l1\";
6151 if (GET_CODE (operands[0]) == MEM)
6152 return \"sub%.w %#1,%0\;jbcc %l1\";
6154 if (DATA_REG_P (operands[0]))
6155 return \"dbra %0,%l1\";
6156 if (GET_CODE (operands[0]) == MEM)
6157 return \"subq%.w %#1,%0\;jbcc %l1\";
6159 #ifdef SGS_CMP_ORDER
6161 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6163 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6165 #else /* not SGS_CMP_ORDER */
6166 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6167 #endif /* not SGS_CMP_ORDER */
6168 #else /* not MOTOROLA */
6169 if (DATA_REG_P (operands[0]))
6170 return \"dbra %0,%l1\";
6171 if (GET_CODE (operands[0]) == MEM)
6172 return \"subqw %#1,%0\;jcc %l1\";
6173 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6174 #endif /* not MOTOROLA */
6177 (define_expand "decrement_and_branch_until_zero"
6178 [(parallel [(set (pc)
6180 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6183 (label_ref (match_operand 1 "" ""))
6186 (plus:SI (match_dup 0)
6194 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6197 (label_ref (match_operand 1 "" ""))
6200 (plus:SI (match_dup 0)
6202 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6208 if (DATA_REG_P (operands[0]))
6209 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6210 if (GET_CODE (operands[0]) == MEM)
6211 return \"sub%.l %#1,%0\;jbcc %l1\";
6213 if (DATA_REG_P (operands[0]))
6214 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6215 if (GET_CODE (operands[0]) == MEM)
6216 return \"subq%.l %#1,%0\;jbcc %l1\";
6218 #ifdef SGS_CMP_ORDER
6220 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6222 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6224 #else /* not SGS_CMP_ORDER */
6225 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6226 #endif /* not SGS_CMP_ORDER */
6227 #else /* not MOTOROLA */
6228 if (DATA_REG_P (operands[0]))
6229 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6230 if (GET_CODE (operands[0]) == MEM)
6231 return \"subql %#1,%0\;jcc %l1\";
6232 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6233 #endif /* not MOTOROLA */
6237 ;; For PIC calls, in order to be able to support
6238 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6239 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6241 ;; PIC calls are handled by loading the address of the function into a
6242 ;; register (via movsi), then emitting a register indirect call using
6243 ;; the "jsr" function call syntax.
6245 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6246 ;; operand to the jbsr statement to indicate that this call should
6247 ;; go through the PLT (why? because this is the way that Sun does it).
6249 ;; We have different patterns for PIC calls and non-PIC calls. The
6250 ;; different patterns are only used to choose the right syntax.
6252 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6253 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6254 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6255 ;; section at link time. However, all global objects reference are still
6256 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6257 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6258 ;; We need to have a way to differentiate these two different operands.
6260 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6261 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6262 ;; to be changed to recognize function calls symbol_ref operand as a valid
6263 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6264 ;; avoid the compiler to load this symbol_ref operand into a register.
6265 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6266 ;; since the value is a PC relative offset, not a real address.
6268 ;; All global objects are treated in the similar way as in SUN3. The only
6269 ;; difference is: on m68k svr4, the reference of such global object needs
6270 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6271 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6274 ;; Call subroutine with no return value.
6275 (define_expand "call"
6276 [(call (match_operand:QI 0 "memory_operand" "")
6277 (match_operand:SI 1 "general_operand" ""))]
6278 ;; Operand 1 not really used on the m68000.
6283 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6284 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6287 ;; This is a normal call sequence.
6289 [(call (match_operand:QI 0 "memory_operand" "o")
6290 (match_operand:SI 1 "general_operand" "g"))]
6291 ;; Operand 1 not really used on the m68000.
6295 #if defined (MOTOROLA) && !defined (USE_GAS)
6297 if (GET_CODE (operands[0]) == MEM
6298 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6307 ;; This is a PIC call sequence.
6309 [(call (match_operand:QI 0 "memory_operand" "o")
6310 (match_operand:SI 1 "general_operand" "g"))]
6311 ;; Operand 1 not really used on the m68000.
6315 if (GET_CODE (operands[0]) == MEM
6316 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6319 return \"bsr.l %0\";
6322 return \"bsr.l %0@PLTPC\";
6324 return \"bsr %0@PLTPC\";
6328 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6329 GAS just plain ignores it. */
6330 return \"jbsr %0,a1\";
6335 ;; Call subroutine, returning value in operand 0
6336 ;; (which must be a hard register).
6337 ;; See comments before "call" regarding PIC calls.
6338 (define_expand "call_value"
6339 [(set (match_operand 0 "" "")
6340 (call (match_operand:QI 1 "memory_operand" "")
6341 (match_operand:SI 2 "general_operand" "")))]
6342 ;; Operand 2 not really used on the m68000.
6346 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6347 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6350 ;; This is a normal call_value
6352 [(set (match_operand 0 "" "=rf")
6353 (call (match_operand:QI 1 "memory_operand" "o")
6354 (match_operand:SI 2 "general_operand" "g")))]
6355 ;; Operand 2 not really used on the m68000.
6358 #if defined (MOTOROLA) && !defined (USE_GAS)
6360 if (GET_CODE (operands[1]) == MEM
6361 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6370 ;; This is a PIC call_value
6372 [(set (match_operand 0 "" "=rf")
6373 (call (match_operand:QI 1 "memory_operand" "o")
6374 (match_operand:SI 2 "general_operand" "g")))]
6375 ;; Operand 2 not really used on the m68000.
6378 if (GET_CODE (operands[1]) == MEM
6379 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6382 return \"bsr.l %1\";
6385 return \"bsr.l %1@PLTPC\";
6387 return \"bsr %1@PLTPC\";
6391 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6392 GAS just plain ignores it. */
6393 return \"jbsr %1,a1\";
6398 ;; Call subroutine returning any type.
6400 (define_expand "untyped_call"
6401 [(parallel [(call (match_operand 0 "" "")
6403 (match_operand 1 "" "")
6404 (match_operand 2 "" "")])]
6405 "NEEDS_UNTYPED_CALL"
6410 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6412 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6414 rtx set = XVECEXP (operands[2], 0, i);
6415 emit_move_insn (SET_DEST (set), SET_SRC (set));
6418 /* The optimizer does not know that the call sets the function value
6419 registers we stored in the result block. We avoid problems by
6420 claiming that all hard registers are used and clobbered at this
6422 emit_insn (gen_blockage ());
6427 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6428 ;; all of memory. This blocks insns from being moved across this point.
6430 (define_insn "blockage"
6431 [(unspec_volatile [(const_int 0)] 0)]
6440 (define_insn "probe"
6445 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6446 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6447 return \"tstl %a0\";
6450 ;; Used for frameless functions which save no regs and allocate no locals.
6451 (define_insn "return"
6456 if (current_function_pops_args == 0)
6458 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6462 (define_insn "indirect_jump"
6463 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6467 ;; This should not be used unless the add/sub insns can't be.
6470 [(set (match_operand:SI 0 "general_operand" "=a")
6471 (match_operand:QI 1 "address_operand" "p"))]
6476 /* Recognize an insn that refers to a table of offsets. Such an insn will
6477 need to refer to a label on the insn. So output one. Use the
6478 label-number of the table of offsets to generate this label. This code,
6479 and similar code above, assumes that there will be at most one reference
6481 if (GET_CODE (operands[1]) == PLUS
6482 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6483 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6485 rtx labelref = XEXP (operands[1], 1);
6486 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6488 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6489 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6491 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6492 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6493 #endif /* not SGS */
6494 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6495 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6496 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6497 #ifdef SGS_SWITCH_TABLES
6498 /* Set flag saying we need to define the symbol
6499 LD%n (with value L%n-LI%n) at the end of the switch table. */
6500 switch_table_difference_label_flag = 1;
6501 #endif /* SGS_SWITCH_TABLES */
6502 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6504 #endif /* SGS_NO_LI */
6506 return \"lea %a1,%0\";
6509 ;; This is the first machine-dependent peephole optimization.
6510 ;; It is useful when a floating value is returned from a function call
6511 ;; and then is moved into an FP register.
6512 ;; But it is mainly intended to test the support for these optimizations.
6515 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6516 (set (match_operand:DF 0 "register_operand" "=f")
6517 (match_operand:DF 1 "register_operand" "ad"))]
6518 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6522 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6523 output_asm_insn (\"move%.l %1,%@\", xoperands);
6524 output_asm_insn (\"move%.l %1,%-\", operands);
6525 return \"fmove%.d %+,%0\";
6529 ;; Optimize a stack-adjust followed by a push of an argument.
6530 ;; This is said to happen frequently with -msoft-float
6531 ;; when there are consecutive library calls.
6534 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6535 (match_operand:SI 0 "const_int_operand" "n")))
6536 (set (match_operand:SF 1 "push_operand" "=m")
6537 (match_operand:SF 2 "general_operand" "rmfF"))]
6538 "INTVAL (operands[0]) >= 4
6539 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6542 if (INTVAL (operands[0]) > 4)
6545 xoperands[0] = stack_pointer_rtx;
6546 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6548 if (INTVAL (xoperands[1]) <= 8)
6551 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6553 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6555 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6557 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6558 INTVAL (xoperands[1]) - 8);
6559 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6563 if (INTVAL (xoperands[1]) <= 0x7FFF)
6566 output_asm_insn (\"add%.w %1,%0\", xoperands);
6569 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6571 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6575 output_asm_insn (\"add%.l %1,%0\", xoperands);
6577 if (FP_REG_P (operands[2]))
6578 return \"fmove%.s %2,%@\";
6579 return \"move%.l %2,%@\";
6582 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6585 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6586 (match_operand:SI 0 "const_int_operand" "n")))
6587 (set (match_operand:SI 1 "push_operand" "=m")
6588 (match_operand:SI 2 "general_operand" "g"))]
6589 "INTVAL (operands[0]) >= 4
6590 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6593 if (INTVAL (operands[0]) > 4)
6596 xoperands[0] = stack_pointer_rtx;
6597 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6599 if (INTVAL (xoperands[1]) <= 8)
6602 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6604 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6606 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6608 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6609 INTVAL (xoperands[1]) - 8);
6610 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6614 if (INTVAL (xoperands[1]) <= 0x7FFF)
6617 output_asm_insn (\"add%.w %1,%0\", xoperands);
6620 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6622 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6626 output_asm_insn (\"add%.l %1,%0\", xoperands);
6628 if (operands[2] == const0_rtx)
6629 return \"clr%.l %@\";
6630 return \"move%.l %2,%@\";
6633 ;; Speed up pushing a single byte but leaving four bytes of space.
6636 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6637 (match_operand:QI 1 "general_operand" "dami"))
6638 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6639 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6644 if (GET_CODE (operands[1]) == REG)
6645 return \"move%.l %1,%-\";
6647 xoperands[1] = operands[1];
6649 = gen_rtx (MEM, QImode,
6650 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6651 gen_rtx (CONST_INT, VOIDmode, 3)));
6652 xoperands[3] = stack_pointer_rtx;
6654 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6656 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6661 [(set (match_operand:SI 0 "register_operand" "=d")
6663 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6664 (match_operand:HI 1 "general_operand" "rmn"))]
6665 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6668 if (GET_CODE (operands[1]) == CONST_INT)
6670 if (operands[1] == const0_rtx
6671 && (DATA_REG_P (operands[0])
6672 || GET_CODE (operands[0]) == MEM)
6673 /* clr insns on 68000 read before writing.
6674 This isn't so on the 68010, but we have no TARGET_68010. */
6675 && ((TARGET_68020 || TARGET_5200)
6676 || !(GET_CODE (operands[0]) == MEM
6677 && MEM_VOLATILE_P (operands[0]))))
6678 return \"clr%.w %0\";
6680 return \"move%.w %1,%0\";
6688 ;; jCC label ; abnormal loop termination
6689 ;; dbra dN, loop ; normal loop termination
6697 ;; Which moves the jCC condition outside the inner loop for free.
6700 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6701 [(cc0) (const_int 0)])
6702 (label_ref (match_operand 2 "" ""))
6707 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6710 (label_ref (match_operand 1 "" ""))
6713 (plus:HI (match_dup 0)
6715 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6719 output_dbcc_and_branch (operands);
6724 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6725 [(cc0) (const_int 0)])
6726 (label_ref (match_operand 2 "" ""))
6731 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6734 (label_ref (match_operand 1 "" ""))
6737 (plus:SI (match_dup 0)
6739 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6743 output_dbcc_and_branch (operands);
6748 ;; FPA multiply and add.
6750 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6751 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6752 (match_operand:DF 2 "general_operand" "xH,y,y"))
6753 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6756 fpma%.d %1,%w2,%w3,%0
6757 fpma%.d %x1,%x2,%x3,%0
6758 fpma%.d %x1,%x2,%x3,%0")
6761 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6762 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6763 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6764 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6767 fpma%.s %1,%w2,%w3,%0
6769 fpma%.s %1,%2,%3,%0")
6771 ;; FPA Multiply and subtract
6773 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6774 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6775 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6776 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6779 fpms%.d %3,%w2,%w1,%0
6780 fpms%.d %x3,%2,%x1,%0
6781 fpms%.d %x3,%2,%x1,%0")
6784 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6785 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6786 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6787 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6790 fpms%.s %3,%w2,%w1,%0
6792 fpms%.s %3,%2,%1,%0")
6795 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6796 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6797 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6798 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6801 fpmr%.d %2,%w1,%w3,%0
6802 fpmr%.d %x2,%1,%x3,%0
6803 fpmr%.d %x2,%1,%x3,%0")
6806 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6807 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6808 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6809 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6812 fpmr%.s %2,%w1,%w3,%0
6813 fpmr%.s %x2,%1,%x3,%0
6814 fpmr%.s %x2,%1,%x3,%0")
6816 ;; FPA Add and multiply
6818 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6819 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6820 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6821 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6824 fpam%.d %2,%w1,%w3,%0
6825 fpam%.d %x2,%1,%x3,%0
6826 fpam%.d %x2,%1,%x3,%0")
6829 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6830 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6831 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6832 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6835 fpam%.s %2,%w1,%w3,%0
6836 fpam%.s %x2,%1,%x3,%0
6837 fpam%.s %x2,%1,%x3,%0")
6839 ;;FPA Subtract and multiply
6841 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6842 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6843 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6844 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6847 fpsm%.d %2,%w1,%w3,%0
6848 fpsm%.d %x2,%1,%x3,%0
6849 fpsm%.d %x2,%1,%x3,%0")
6852 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6853 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6854 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6855 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6858 fpsm%.d %3,%w2,%w1,%0
6859 fpsm%.d %x3,%2,%x1,%0
6860 fpsm%.d %x3,%2,%x1,%0")
6863 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6864 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6865 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6866 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6869 fpsm%.s %2,%w1,%w3,%0
6870 fpsm%.s %x2,%1,%x3,%0
6871 fpsm%.s %x2,%1,%x3,%0")
6874 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6875 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6876 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6877 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6880 fpsm%.s %3,%w2,%w1,%0
6881 fpsm%.s %x3,%2,%x1,%0
6882 fpsm%.s %x3,%2,%x1,%0")
6884 (define_expand "tstxf"
6886 (match_operand:XF 0 "nonimmediate_operand" ""))]
6888 "m68k_last_compare_had_fp_operands = 1;")
6892 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6896 cc_status.flags = CC_IN_68881;
6897 return \"ftst%.x %0\";
6900 (define_expand "cmpxf"
6902 (compare (match_operand:XF 0 "nonimmediate_operand" "")
6903 (match_operand:XF 1 "nonimmediate_operand" "")))]
6905 "m68k_last_compare_had_fp_operands = 1;")
6909 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6910 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6914 cc_status.flags = CC_IN_68881;
6915 #ifdef SGS_CMP_ORDER
6916 if (REG_P (operands[0]))
6918 if (REG_P (operands[1]))
6919 return \"fcmp%.x %0,%1\";
6921 return \"fcmp%.x %0,%f1\";
6923 cc_status.flags |= CC_REVERSED;
6924 return \"fcmp%.x %1,%f0\";
6926 if (REG_P (operands[0]))
6928 if (REG_P (operands[1]))
6929 return \"fcmp%.x %1,%0\";
6931 return \"fcmp%.x %f1,%0\";
6933 cc_status.flags |= CC_REVERSED;
6934 return \"fcmp%.x %f0,%1\";
6938 (define_insn "extendsfxf2"
6939 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6940 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6944 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6946 if (REGNO (operands[0]) == REGNO (operands[1]))
6948 /* Extending float to double in an fp-reg is a no-op.
6949 NOTICE_UPDATE_CC has already assumed that the
6950 cc will be set. So cancel what it did. */
6951 cc_status = cc_prev_status;
6954 return \"f%$move%.x %1,%0\";
6956 if (FP_REG_P (operands[0]))
6957 return \"f%$move%.s %f1,%0\";
6958 return \"fmove%.x %f1,%0\";
6962 (define_insn "extenddfxf2"
6963 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6965 (match_operand:DF 1 "general_operand" "f,m")))]
6969 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6971 if (REGNO (operands[0]) == REGNO (operands[1]))
6973 /* Extending float to double in an fp-reg is a no-op.
6974 NOTICE_UPDATE_CC has already assumed that the
6975 cc will be set. So cancel what it did. */
6976 cc_status = cc_prev_status;
6979 return \"fmove%.x %1,%0\";
6981 if (FP_REG_P (operands[0]))
6982 return \"f%&move%.d %f1,%0\";
6983 return \"fmove%.x %f1,%0\";
6986 (define_insn "truncxfdf2"
6987 [(set (match_operand:DF 0 "general_operand" "=m,!r")
6989 (match_operand:XF 1 "general_operand" "f,f")))]
6993 if (REG_P (operands[0]))
6995 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
6996 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
6997 return \"move%.l %+,%0\";
6999 return \"fmove%.d %f1,%0\";
7002 (define_insn "truncxfsf2"
7003 [(set (match_operand:SF 0 "general_operand" "=dm")
7005 (match_operand:XF 1 "general_operand" "f")))]
7009 (define_insn "floatsixf2"
7010 [(set (match_operand:XF 0 "general_operand" "=f")
7011 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7015 (define_insn "floathixf2"
7016 [(set (match_operand:XF 0 "general_operand" "=f")
7017 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7021 (define_insn "floatqixf2"
7022 [(set (match_operand:XF 0 "general_operand" "=f")
7023 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7027 (define_insn "ftruncxf2"
7028 [(set (match_operand:XF 0 "general_operand" "=f")
7029 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7033 if (FP_REG_P (operands[1]))
7034 return \"fintrz%.x %f1,%0\";
7035 return \"fintrz%.x %f1,%0\";
7038 (define_insn "fixxfqi2"
7039 [(set (match_operand:QI 0 "general_operand" "=dm")
7040 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7044 (define_insn "fixxfhi2"
7045 [(set (match_operand:HI 0 "general_operand" "=dm")
7046 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7050 (define_insn "fixxfsi2"
7051 [(set (match_operand:SI 0 "general_operand" "=dm")
7052 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7057 [(set (match_operand:XF 0 "general_operand" "=f")
7058 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7059 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7064 [(set (match_operand:XF 0 "general_operand" "=f")
7065 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7066 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7071 [(set (match_operand:XF 0 "general_operand" "=f")
7072 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7073 (match_operand:XF 1 "general_operand" "0")))]
7077 (define_insn "addxf3"
7078 [(set (match_operand:XF 0 "general_operand" "=f")
7079 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7080 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7084 if (REG_P (operands[2]))
7085 return \"fadd%.x %2,%0\";
7086 return \"fadd%.x %f2,%0\";
7090 [(set (match_operand:XF 0 "general_operand" "=f")
7091 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7092 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7097 [(set (match_operand:XF 0 "general_operand" "=f")
7098 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7099 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7104 [(set (match_operand:XF 0 "general_operand" "=f")
7105 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7106 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7110 (define_insn "subxf3"
7111 [(set (match_operand:XF 0 "general_operand" "=f")
7112 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7113 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7117 if (REG_P (operands[2]))
7118 return \"fsub%.x %2,%0\";
7119 return \"fsub%.x %f2,%0\";
7123 [(set (match_operand:XF 0 "general_operand" "=f")
7124 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7125 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7130 [(set (match_operand:XF 0 "general_operand" "=f")
7131 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7132 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7137 [(set (match_operand:XF 0 "general_operand" "=f")
7138 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7139 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7143 (define_insn "mulxf3"
7144 [(set (match_operand:XF 0 "general_operand" "=f")
7145 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7146 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7150 if (REG_P (operands[2]))
7151 return \"fmul%.x %2,%0\";
7152 return \"fmul%.x %f2,%0\";
7156 [(set (match_operand:XF 0 "general_operand" "=f")
7157 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7158 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7163 [(set (match_operand:XF 0 "general_operand" "=f")
7164 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7165 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7170 [(set (match_operand:XF 0 "general_operand" "=f")
7171 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7172 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7176 (define_insn "divxf3"
7177 [(set (match_operand:XF 0 "general_operand" "=f")
7178 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7179 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7183 if (REG_P (operands[2]))
7184 return \"fdiv%.x %2,%0\";
7185 return \"fdiv%.x %f2,%0\";
7188 (define_expand "negxf2"
7189 [(set (match_operand:XF 0 "general_operand" "")
7190 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7194 /* ??? There isn't an FPA define_insn so we could handle it here too.
7195 For now we don't (paranoia). */
7203 target = operand_subword (operands[0], 0, 1, XFmode);
7204 result = expand_binop (SImode, xor_optab,
7205 operand_subword_force (operands[1], 0, XFmode),
7206 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7210 if (result != target)
7211 emit_move_insn (result, target);
7213 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7214 operand_subword_force (operands[1], 1, XFmode));
7215 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7216 operand_subword_force (operands[1], 2, XFmode));
7218 insns = get_insns ();
7221 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7226 (define_insn "negxf2_68881"
7227 [(set (match_operand:XF 0 "general_operand" "=f")
7228 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7232 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7233 return \"fneg%.x %1,%0\";
7234 return \"fneg%.x %f1,%0\";
7237 (define_expand "absxf2"
7238 [(set (match_operand:XF 0 "general_operand" "")
7239 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7243 /* ??? There isn't an FPA define_insn so we could handle it here too.
7244 For now we don't (paranoia). */
7252 target = operand_subword (operands[0], 0, 1, XFmode);
7253 result = expand_binop (SImode, and_optab,
7254 operand_subword_force (operands[1], 0, XFmode),
7255 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7259 if (result != target)
7260 emit_move_insn (result, target);
7262 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7263 operand_subword_force (operands[1], 1, XFmode));
7264 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7265 operand_subword_force (operands[1], 2, XFmode));
7267 insns = get_insns ();
7270 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7275 (define_insn "absxf2_68881"
7276 [(set (match_operand:XF 0 "general_operand" "=f")
7277 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7281 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7282 return \"fabs%.x %1,%0\";
7283 return \"fabs%.x %f1,%0\";
7286 (define_insn "sqrtxf2"
7287 [(set (match_operand:XF 0 "general_operand" "=f")
7288 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7292 (define_insn "sinsf2"
7293 [(set (match_operand:SF 0 "general_operand" "=f")
7294 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7295 "TARGET_68881 && flag_fast_math"
7298 if (FP_REG_P (operands[1]))
7299 return \"fsin%.x %1,%0\";
7301 return \"fsin%.s %1,%0\";
7304 (define_insn "sindf2"
7305 [(set (match_operand:DF 0 "general_operand" "=f")
7306 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7307 "TARGET_68881 && flag_fast_math"
7310 if (FP_REG_P (operands[1]))
7311 return \"fsin%.x %1,%0\";
7313 return \"fsin%.d %1,%0\";
7316 (define_insn "sinxf2"
7317 [(set (match_operand:XF 0 "general_operand" "=f")
7318 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7319 "TARGET_68881 && flag_fast_math"
7322 (define_insn "cossf2"
7323 [(set (match_operand:SF 0 "general_operand" "=f")
7324 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7325 "TARGET_68881 && flag_fast_math"
7328 if (FP_REG_P (operands[1]))
7329 return \"fcos%.x %1,%0\";
7331 return \"fcos%.s %1,%0\";
7334 (define_insn "cosdf2"
7335 [(set (match_operand:DF 0 "general_operand" "=f")
7336 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7337 "TARGET_68881 && flag_fast_math"
7340 if (FP_REG_P (operands[1]))
7341 return \"fcos%.x %1,%0\";
7343 return \"fcos%.d %1,%0\";
7346 (define_insn "cosxf2"
7347 [(set (match_operand:XF 0 "general_operand" "=f")
7348 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7349 "TARGET_68881 && flag_fast_math"