1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
69 ;;- "%." size separator ("." or "") move%.l d0,d1
70 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
71 ;;- "%-" push operand "sp@-" move%.l d0,%-
72 ;;- "%+" pop operand "sp@+" move%.l d0,%+
73 ;;- "%@" top of stack "sp@" move%.l d0,%@
74 ;;- "%!" fpcr register
75 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
76 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
79 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
80 ;; operand 1 is the argument for `sin'.
81 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
82 ;; operand 1 is the argument for `cos'.
84 ;;- Information about 68040 port.
86 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
87 ;;- be emulated in software by the OS. It is faster to avoid these
88 ;;- instructions and issue a library call rather than trapping into
89 ;;- the kernel. The affected instructions are fintrz and fscale. The
90 ;;- TARGET_68040 flag turns the use of the opcodes off.
92 ;;- The '040 also implements a set of new floating-point instructions
93 ;;- which specify the rounding precision in the opcode. This finally
94 ;;- permit the 68k series to be truly IEEE compliant, and solves all
95 ;;- issues of excess precision accumulating in the extended registers.
96 ;;- By default, GCC does not use these instructions, since such code will
97 ;;- not run on an '030. To use these instructions, use the -m68040-only
98 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
99 ;;- you can make these instructions the default.
101 ;;- These new instructions aren't directly in the md. They are brought
102 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
105 ;;- Information about 68060 port.
107 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
108 ;;- be emulated in software by the OS. It is faster to avoid these
109 ;;- instructions and issue a library call rather than trapping into
110 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
111 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
112 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
114 ;;- FPA port explanation:
116 ;;- Usage of the Sun FPA and the 68881 together
118 ;;- The current port of gcc to the sun fpa disallows use of the m68881
119 ;;- instructions completely if code is targeted for the fpa. This is
120 ;;- for the following reasons:
122 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
123 ;;- can, the 68881 otherwise, and data registers only if you are
124 ;;- forced to it) is a bitch with the current constraint scheme,
125 ;;- especially since it would have to work for any combination of
128 ;;- 2) There are no instructions to move between the two types of
129 ;;- registers; the stack must be used as an intermediary.
131 ;;- It could indeed be done; I think the best way would be to have
132 ;;- separate patterns for TARGET_FPA (which implies a 68881),
133 ;;- TARGET_68881, and no floating point co-processor. Use
134 ;;- define_expands for all of the named instruction patterns, and
135 ;;- include code in the FPA instruction to deal with the 68881 with
136 ;;- preferences specifically set to favor the fpa. Some of this has
137 ;;- already been done:
139 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
140 ;;- case and a TARGET_68881 case (the exceptions are the patterns
141 ;;- which would need one define_expand and three define_insn's under
142 ;;- it (with a lot of duplicate code between them) to replace the
143 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
144 ;;- first two patterns in the md.
146 ;;- Some would still have to be done:
148 ;;- 1) Add code to the fpa patterns which correspond to 68881
149 ;;- patterns to deal with the 68881 case (including preferences!).
150 ;;- What you might actually do here is combine the fpa and 68881 code
151 ;;- back together into one pattern for those instructions where it's
152 ;;- absolutely necessary and save yourself some duplicate code. I'm
153 ;;- not completely sure as to whether you could get away with doing
154 ;;- this only for the mov* insns, or if you'd have to do it for all
156 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
157 ;;- moving between fpa regs and 68881 regs.
159 ;;- Since the fpa is more powerful than the 68881 and also has more
160 ;;- registers, and since I think the resultant md would be medium ugly
161 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
162 ;;- to do this change.
164 ;;- Another reason why someone *might* want to do the change is to
165 ;;- control which register classes are accessed in a slightly cleaner
166 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
167 ;;- the internals manual.
169 ;;- Yet another reason why someone might want to do this change is to
170 ;;- allow use of some of the 68881 insns which have no equivalent on
171 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
173 ;;- If this is ever done, don't forget to change sun3.h so that
174 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
176 ;;- Condition code hack
178 ;;- When a floating point compare is done in the fpa, the resulting
179 ;;- condition codes are left in the fpastatus register. The values in
180 ;;- this register must be moved into the 68000 cc register before any
181 ;;- jump is executed. Once this has been done, regular jump
182 ;;- instructions are fine (ie. floating point jumps are not necessary.
183 ;;- They are only done if the cc is in the 68881).
185 ;;- The instructions that move the fpastatus register to the 68000
186 ;;- register clobber a data register (the move cannot be done direct).
187 ;;- These instructions might be bundled either with the compare
188 ;;- instruction, or the branch instruction. If we were using both the
189 ;;- fpa and the 68881 together, we would wish to only mark the
190 ;;- register clobbered if we were doing the compare in the fpa, but I
191 ;;- think that that decision (whether to clobber the register or not)
192 ;;- must be done before register allocation (makes sense) and hence we
193 ;;- can't know if the floating point compare will be done in the fpa
194 ;;- or the fp. So whenever we are asked for code that uses the fpa,
195 ;;- we will mark a data register as clobbered. This is reasonable, as
196 ;;- almost all floating point compare operations done with fpa code
197 ;;- enabled will be done in the fpa. It's even more reasonable since
198 ;;- we decided to make the 68881 and the fpa mutually exclusive.
200 ;;- We place to code to move the fpastatus register inside of a
201 ;;- define_expand so that we can do it conditionally based on whether
202 ;;- we are targeting an fpa or not.
204 ;;- This still leaves us with the question of where we wish to put the
205 ;;- code to move the fpastatus reg. If we put it in the compare
206 ;;- instruction, we can restrict the clobbering of the register to
207 ;;- floating point compares, but we can't take advantage of floating
208 ;;- point subtracts & etc. that alter the fpastatus register. If we
209 ;;- put it in the branch instruction, all branches compiled with fpa
210 ;;- code enabled will clobber a data register, but we will be able to
211 ;;- take advantage of fpa subtracts. This balance favors putting the
212 ;;- code in with the compare instruction.
214 ;;- Note that if some enterprising hacker should decide to switch
215 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
217 ;;- Usage of the top 16 fpa registers
219 ;;- The only locations which we may transfer fpa registers 16-31 from
220 ;;- or to are the fpa registers 0-15. (68000 registers and memory
221 ;;- locations are impossible). This causes problems in gcc, which
222 ;;- assumes that mov?? instructions require no additional registers
223 ;;- (see section 11.7) and since floating point moves *must* be
224 ;;- supported into general registers (see section 12.3 under
225 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
227 ;;- My solution was to reserve fpa0 for moves into or out of these top
228 ;;- 16 registers and to disparage the choice to reload into or out of
229 ;;- these registers as much as I could. That alternative is always
230 ;;- last in the list, so it will not be used unless all else fails. I
231 ;;- will note that according to my current information, sun's compiler
232 ;;- doesn't use these top 16 registers at all.
234 ;;- There is another possible way to do it. I *believe* that if you
235 ;;- make absolutely sure that the code will not be executed in the
236 ;;- reload pass, you can support the mov?? names with define_expands
237 ;;- which require new registers. This may be possible by the
238 ;;- appropriate juggling of constraints. I may come back to this later.
240 ;;- Usage of constant RAM
242 ;;- This has been handled correctly (I believe) but the way I've done
243 ;;- it could use a little explanation. The constant RAM can only be
244 ;;- accessed when the instruction is in "command register" mode.
245 ;;- "command register" mode means that no accessing of memory or the
246 ;;- 68000 registers is being done. This can be expressed easily in
247 ;;- constraints, so generally the mode of the instruction is
248 ;;- determined by a branch off of which_alternative. In outputting
249 ;;- instructions, a 'w' means to output an access to the constant ram
250 ;;- (if the arg is CONST_DOUBLE and is one of the available
251 ;;- constants), and 'x' means to output a register pair (if the arg is
252 ;;- a 68000 register) and a 'y' is the combination of the above two
253 ;;- processes. You use a 'y' in two operand DF instructions where you
254 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
255 ;;- instructions where the arg might be a 68000 register and the
256 ;;- instruction is *not* in "command register" mode, and you use a 'w'
257 ;;- in two situations: 1) The instruction *is* in command register
258 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
259 ;;- instruction is a two operand SF instruction where you know the
260 ;;- other operand is an fpa register.
262 ;;- Optimization issues
264 ;;- I actually think that I've included all of the fpa instructions
265 ;;- that should be included. Note that if someone is interested in
266 ;;- doing serious floating point work on the sun fpa, I would advise
267 ;;- the use of the "asm" instruction in gcc to allow you to use the
268 ;;- sin, cos, and exponential functions on the fpa board.
270 ;;- END FPA Explanation Section.
273 ;;- Some of these insn's are composites of several m68000 op codes.
274 ;;- The assembler (or final @@??) insures that the appropriate one is
278 [(set (match_operand:DF 0 "push_operand" "=m")
279 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
283 if (FP_REG_P (operands[1]))
284 return \"fmove%.d %f1,%0\";
285 if (FPA_REG_P (operands[1]))
286 return \"fpmove%.d %1, %x0\";
287 return output_move_double (operands);
290 (define_insn "pushdi"
291 [(set (match_operand:DI 0 "push_operand" "=m")
292 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
296 return output_move_double (operands);
299 ;; We don't want to allow a constant operand for test insns because
300 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
301 ;; be folded while optimizing anyway.
305 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
306 (clobber (match_scratch:SI 1 "=X,d"))
307 (clobber (match_scratch:DI 2 "=d,X"))]
311 if (which_alternative == 0)
315 xoperands[0] = operands[2];
316 xoperands[1] = operands[0];
317 output_move_double (xoperands);
318 cc_status.flags |= CC_REVERSED;
319 return \"neg%.l %R2\;negx%.l %2\";
321 if (find_reg_note (insn, REG_DEAD, operands[0]))
323 cc_status.flags |= CC_REVERSED;
324 return \"neg%.l %R0\;negx%.l %0\";
328 ** 'sub' clears %1, and also clears the X cc bit
329 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
330 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
332 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
337 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
342 /* ISI's assembler fails to handle tstl a0. */
343 if (! ADDRESS_REG_P (operands[0]))
345 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
347 return \"tst%.l %0\";
348 /* If you think that the 68020 does not support tstl a0,
349 reread page B-167 of the 68020 manual more carefully. */
350 /* On an address reg, cmpw may replace cmpl. */
352 return \"cmp%.w %0,%#0\";
354 return \"cmp%.w %#0,%0\";
358 ;; This can't use an address register, because comparisons
359 ;; with address registers as second operand always test the whole word.
362 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
368 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
372 (define_expand "tstsf"
374 (match_operand:SF 0 "general_operand" ""))]
375 "TARGET_68881 || TARGET_FPA"
380 emit_insn (gen_tstsf_fpa (operands[0]));
385 (define_insn "tstsf_fpa"
387 (match_operand:SF 0 "general_operand" "xmdF"))
388 (clobber (match_scratch:SI 1 "=d"))]
390 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
394 (match_operand:SF 0 "general_operand" "fdm"))]
398 cc_status.flags = CC_IN_68881;
399 if (FP_REG_P (operands[0]))
400 return \"ftst%.x %0\";
401 return \"ftst%.s %0\";
404 (define_expand "tstdf"
406 (match_operand:DF 0 "general_operand" ""))]
407 "TARGET_68881 || TARGET_FPA"
412 emit_insn (gen_tstsf_fpa (operands[0]));
417 (define_insn "tstdf_fpa"
419 (match_operand:DF 0 "general_operand" "xrmF"))
420 (clobber (match_scratch:SI 1 "=d"))]
422 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
426 (match_operand:DF 0 "general_operand" "fm"))]
430 cc_status.flags = CC_IN_68881;
431 if (FP_REG_P (operands[0]))
432 return \"ftst%.x %0\";
433 return \"ftst%.d %0\";
436 ;; compare instructions.
438 (define_expand "cmpdi"
441 (compare (match_operand:DI 0 "nonimmediate_operand" "")
442 (match_operand:DI 1 "general_operand" "")))
443 (clobber (match_dup 2))])]
445 "operands[2] = gen_reg_rtx (DImode);")
449 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
450 (match_operand:DI 2 "general_operand" "d,0")))
451 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
455 if (rtx_equal_p (operands[0], operands[1]))
456 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
459 cc_status.flags |= CC_REVERSED;
460 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
464 ;; This is the second "hook" for PIC code (in addition to movsi). See
465 ;; comment of movsi for a description of PIC handling.
466 (define_expand "cmpsi"
468 (compare (match_operand:SI 0 "nonimmediate_operand" "")
469 (match_operand:SI 1 "general_operand" "")))]
473 if (flag_pic && symbolic_operand (operands[1], SImode))
475 /* The source is an address which requires PIC relocation.
476 Call legitimize_pic_address with the source, mode, and a relocation
477 register (a new pseudo, or the final destination if reload_in_progress
478 is set). Then fall through normally */
479 extern rtx legitimize_pic_address();
480 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
481 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
485 ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
488 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
489 (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
493 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
495 return \"cmpm%.l %0,%1\";
497 return \"cmpm%.l %1,%0\";
499 if (REG_P (operands[1])
500 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
501 { cc_status.flags |= CC_REVERSED;
503 return \"cmp%.l %d1,%d0\";
505 return \"cmp%.l %d0,%d1\";
509 return \"cmp%.l %d0,%d1\";
511 return \"cmp%.l %d1,%d0\";
517 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
518 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
522 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
524 return \"cmpm%.w %0,%1\";
526 return \"cmpm%.w %1,%0\";
528 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
529 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
530 { cc_status.flags |= CC_REVERSED;
532 return \"cmp%.w %d1,%d0\";
534 return \"cmp%.w %d0,%d1\";
538 return \"cmp%.w %d0,%d1\";
540 return \"cmp%.w %d1,%d0\";
546 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
547 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
551 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
553 return \"cmpm%.b %0,%1\";
555 return \"cmpm%.b %1,%0\";
557 if (REG_P (operands[1])
558 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
559 { cc_status.flags |= CC_REVERSED;
561 return \"cmp%.b %d1,%d0\";
563 return \"cmp%.b %d0,%d1\";
567 return \"cmp%.b %d0,%d1\";
569 return \"cmp%.b %d1,%d0\";
573 (define_expand "cmpdf"
575 (compare (match_operand:DF 0 "general_operand" "")
576 (match_operand:DF 1 "general_operand" "")))]
577 "TARGET_68881 || TARGET_FPA"
582 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
587 (define_insn "cmpdf_fpa"
589 (compare (match_operand:DF 0 "general_operand" "x,y")
590 (match_operand:DF 1 "general_operand" "xH,rmF")))
591 (clobber (match_scratch:SI 2 "=d,d"))]
593 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
597 (compare (match_operand:DF 0 "general_operand" "f,mG")
598 (match_operand:DF 1 "general_operand" "fmG,f")))]
602 cc_status.flags = CC_IN_68881;
604 if (REG_P (operands[0]))
606 if (REG_P (operands[1]))
607 return \"fcmp%.x %0,%1\";
609 return \"fcmp%.d %0,%f1\";
611 cc_status.flags |= CC_REVERSED;
612 return \"fcmp%.d %1,%f0\";
614 if (REG_P (operands[0]))
616 if (REG_P (operands[1]))
617 return \"fcmp%.x %1,%0\";
619 return \"fcmp%.d %f1,%0\";
621 cc_status.flags |= CC_REVERSED;
622 return \"fcmp%.d %f0,%1\";
626 (define_expand "cmpsf"
628 (compare (match_operand:SF 0 "general_operand" "")
629 (match_operand:SF 1 "general_operand" "")))]
630 "TARGET_68881 || TARGET_FPA"
635 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
640 (define_insn "cmpsf_fpa"
642 (compare (match_operand:SF 0 "general_operand" "x,y")
643 (match_operand:SF 1 "general_operand" "xH,rmF")))
644 (clobber (match_scratch:SI 2 "=d,d"))]
646 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
650 (compare (match_operand:SF 0 "general_operand" "f,mdG")
651 (match_operand:SF 1 "general_operand" "fmdG,f")))]
655 cc_status.flags = CC_IN_68881;
657 if (FP_REG_P (operands[0]))
659 if (FP_REG_P (operands[1]))
660 return \"fcmp%.x %0,%1\";
662 return \"fcmp%.s %0,%f1\";
664 cc_status.flags |= CC_REVERSED;
665 return \"fcmp%.s %1,%f0\";
667 if (FP_REG_P (operands[0]))
669 if (FP_REG_P (operands[1]))
670 return \"fcmp%.x %1,%0\";
672 return \"fcmp%.s %f1,%0\";
674 cc_status.flags |= CC_REVERSED;
675 return \"fcmp%.s %f0,%1\";
679 ;; Recognizers for btst instructions.
682 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
684 (minus:SI (const_int 7)
685 (match_operand:SI 1 "general_operand" "di"))))]
687 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
690 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
692 (minus:SI (const_int 31)
693 (match_operand:SI 1 "general_operand" "di"))))]
695 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
697 ;; The following two patterns are like the previous two
698 ;; except that they use the fact that bit-number operands
699 ;; are automatically masked to 3 or 5 bits.
702 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
704 (minus:SI (const_int 7)
706 (match_operand:SI 1 "register_operand" "d")
709 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
712 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
714 (minus:SI (const_int 31)
716 (match_operand:SI 1 "register_operand" "d")
719 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
721 ;; Nonoffsettable mem refs are ok in this one pattern
722 ;; since we don't try to adjust them.
724 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
726 (match_operand:SI 1 "const_int_operand" "n")))]
727 "(unsigned) INTVAL (operands[1]) < 8"
730 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
731 return output_btst (operands, operands[1], operands[0], insn, 7);
735 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
737 (match_operand:SI 1 "const_int_operand" "n")))]
741 if (GET_CODE (operands[0]) == MEM)
743 operands[0] = adj_offsettable_operand (operands[0],
744 INTVAL (operands[1]) / 8);
745 operands[1] = gen_rtx (CONST_INT, VOIDmode,
746 7 - INTVAL (operands[1]) % 8);
747 return output_btst (operands, operands[1], operands[0], insn, 7);
749 operands[1] = gen_rtx (CONST_INT, VOIDmode,
750 31 - INTVAL (operands[1]));
751 return output_btst (operands, operands[1], operands[0], insn, 31);
757 ;; A special case in which it is not desirable
758 ;; to reload the constant into a data register.
759 (define_insn "pushexthisi_const"
760 [(set (match_operand:SI 0 "push_operand" "=m")
761 (match_operand:SI 1 "const_int_operand" "J"))]
762 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
765 if (operands[1] == const0_rtx)
766 return \"clr%.l %0\";
771 ;(define_insn "swapsi"
772 ; [(set (match_operand:SI 0 "general_operand" "+r")
773 ; (match_operand:SI 1 "general_operand" "+r"))
774 ; (set (match_dup 1) (match_dup 0))]
778 ;; Special case of fullword move when source is zero.
779 ;; The reason this is special is to avoid loading a zero
780 ;; into a data reg with moveq in order to store it elsewhere.
782 (define_insn "movsi_const0"
783 [(set (match_operand:SI 0 "general_operand" "=g")
785 ;; clr insns on 68000 read before writing.
786 ;; This isn't so on the 68010, but we have no TARGET_68010.
787 "((TARGET_68020 || TARGET_5200)
788 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
791 if (ADDRESS_REG_P (operands[0]))
793 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
794 if (!TARGET_68040 && !TARGET_68060)
795 return \"sub%.l %0,%0\";
800 /* Many SGS assemblers croak on size specifiers for constants. */
803 return \"lea 0.w,%0\";
806 return \"lea 0:w,%0\";
810 /* moveq is faster on the 68000. */
811 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
812 #if defined(MOTOROLA) && !defined(CRDS)
813 return \"moveq%.l %#0,%0\";
815 return \"moveq %#0,%0\";
817 return \"clr%.l %0\";
820 ;; General case of fullword move.
822 ;; This is the main "hook" for PIC code. When generating
823 ;; PIC, movsi is responsible for determining when the source address
824 ;; needs PIC relocation and appropriately calling legitimize_pic_address
825 ;; to perform the actual relocation.
827 ;; In both the PIC and non-PIC cases the patterns generated will
828 ;; matched by the next define_insn.
829 (define_expand "movsi"
830 [(set (match_operand:SI 0 "general_operand" "")
831 (match_operand:SI 1 "general_operand" ""))]
835 if (flag_pic && symbolic_operand (operands[1], SImode))
837 /* The source is an address which requires PIC relocation.
838 Call legitimize_pic_address with the source, mode, and a relocation
839 register (a new pseudo, or the final destination if reload_in_progress
840 is set). Then fall through normally */
841 extern rtx legitimize_pic_address();
842 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
843 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
847 ;; General case of fullword move. The register constraints
848 ;; force integer constants in range for a moveq to be reloaded
849 ;; if they are headed for memory.
851 ;; Notes: make sure no alternative allows g vs g.
852 ;; We don't allow f-regs since fixed point cannot go in them.
853 ;; We do allow y and x regs since fixed point is allowed in them.
854 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
855 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
859 if (which_alternative == 3)
860 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
861 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
862 return \"fpmove%.l %x1,%x0\";
863 if (GET_CODE (operands[1]) == CONST_INT)
864 return output_move_simode_const (operands);
865 else if ((GET_CODE (operands[1]) == SYMBOL_REF
866 || GET_CODE (operands[1]) == CONST)
867 && push_operand (operands[0], SImode))
869 else if ((GET_CODE (operands[1]) == SYMBOL_REF
870 || GET_CODE (operands[1]) == CONST)
871 && ADDRESS_REG_P (operands[0]))
872 return \"lea %a1,%0\";
873 return \"move%.l %1,%0\";
877 [(set (match_operand:HI 0 "general_operand" "=g")
878 (match_operand:HI 1 "general_operand" "g"))]
882 if (GET_CODE (operands[1]) == CONST_INT)
884 if (operands[1] == const0_rtx
885 && (DATA_REG_P (operands[0])
886 || GET_CODE (operands[0]) == MEM)
887 /* clr insns on 68000 read before writing.
888 This isn't so on the 68010, but we have no TARGET_68010. */
889 && ((TARGET_68020 || TARGET_5200)
890 || !(GET_CODE (operands[0]) == MEM
891 && MEM_VOLATILE_P (operands[0]))))
892 return \"clr%.w %0\";
893 else if (DATA_REG_P (operands[0])
894 && INTVAL (operands[1]) < 128
895 && INTVAL (operands[1]) >= -128)
897 #if defined(MOTOROLA) && !defined(CRDS)
898 return \"moveq%.l %1,%0\";
900 return \"moveq %1,%0\";
903 else if (INTVAL (operands[1]) < 0x8000
904 && INTVAL (operands[1]) >= -0x8000)
905 return \"move%.w %1,%0\";
907 else if (CONSTANT_P (operands[1]))
908 return \"move%.l %1,%0\";
910 /* Recognize the insn before a tablejump, one that refers
911 to a table of offsets. Such an insn will need to refer
912 to a label on the insn. So output one. Use the label-number
913 of the table of offsets to generate this label. This code,
914 and similar code below, assumes that there will be at most one
915 reference to each table. */
916 if (GET_CODE (operands[1]) == MEM
917 && GET_CODE (XEXP (operands[1], 0)) == PLUS
918 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
919 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
921 rtx labelref = XEXP (XEXP (operands[1], 0), 1);
922 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
924 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
925 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
927 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
928 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
930 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
931 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
932 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
933 #ifdef SGS_SWITCH_TABLES
934 /* Set flag saying we need to define the symbol
935 LD%n (with value L%n-LI%n) at the end of the switch table. */
936 switch_table_difference_label_flag = 1;
937 #endif /* SGS_SWITCH_TABLES */
938 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
940 #endif /* SGS_NO_LI */
941 return \"move%.w %1,%0\";
944 (define_insn "movstricthi"
945 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
946 (match_operand:HI 1 "general_operand" "rmn"))]
950 if (GET_CODE (operands[1]) == CONST_INT)
952 if (operands[1] == const0_rtx
953 && (DATA_REG_P (operands[0])
954 || GET_CODE (operands[0]) == MEM)
955 /* clr insns on 68000 read before writing.
956 This isn't so on the 68010, but we have no TARGET_68010. */
957 && ((TARGET_68020 || TARGET_5200)
958 || !(GET_CODE (operands[0]) == MEM
959 && MEM_VOLATILE_P (operands[0]))))
960 return \"clr%.w %0\";
962 return \"move%.w %1,%0\";
966 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
967 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
973 /* This is probably useless, since it loses for pushing a struct
974 of several bytes a byte at a time. */
975 if (GET_CODE (operands[0]) == MEM
976 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
977 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
978 && ! ADDRESS_REG_P (operands[1]))
980 xoperands[1] = operands[1];
982 = gen_rtx (MEM, QImode,
983 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
984 /* Just pushing a byte puts it in the high byte of the halfword. */
985 /* We must put it in the low-order, high-numbered byte. */
986 output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands);
990 /* clr and st insns on 68000 read before writing.
991 This isn't so on the 68010, but we have no TARGET_68010. */
992 if (!ADDRESS_REG_P (operands[0])
994 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
996 if (operands[1] == const0_rtx)
997 return \"clr%.b %0\";
998 if (GET_CODE (operands[1]) == CONST_INT
999 && (INTVAL (operands[1]) & 255) == 255)
1005 if (GET_CODE (operands[1]) == CONST_INT
1006 && DATA_REG_P (operands[0])
1007 && INTVAL (operands[1]) < 128
1008 && INTVAL (operands[1]) >= -128)
1010 #if defined(MOTOROLA) && !defined(CRDS)
1011 return \"moveq%.l %1,%0\";
1013 return \"moveq %1,%0\";
1016 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
1017 return \"move%.l %1,%0\";
1018 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
1019 return \"move%.w %1,%0\";
1020 return \"move%.b %1,%0\";
1023 (define_insn "movstrictqi"
1024 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1025 (match_operand:QI 1 "general_operand" "dmn"))]
1029 if (operands[1] == const0_rtx
1030 /* clr insns on 68000 read before writing.
1031 This isn't so on the 68010, but we have no TARGET_68010. */
1032 && ((TARGET_68020 || TARGET_5200)
1033 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1034 return \"clr%.b %0\";
1035 return \"move%.b %1,%0\";
1038 (define_insn "movsf"
1039 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1040 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1041 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1042 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1046 if (which_alternative >= 4)
1047 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1048 if (FPA_REG_P (operands[0]))
1050 if (FPA_REG_P (operands[1]))
1051 return \"fpmove%.s %x1,%x0\";
1052 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1053 return output_move_const_single (operands);
1054 else if (FP_REG_P (operands[1]))
1055 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1056 return \"fpmove%.s %x1,%x0\";
1058 if (FPA_REG_P (operands[1]))
1060 if (FP_REG_P (operands[0]))
1061 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1063 return \"fpmove%.s %x1,%x0\";
1065 if (FP_REG_P (operands[0]))
1067 if (FP_REG_P (operands[1]))
1068 return \"f%$move%.x %1,%0\";
1069 else if (ADDRESS_REG_P (operands[1]))
1070 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1071 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1072 return output_move_const_single (operands);
1073 return \"f%$move%.s %f1,%0\";
1075 if (FP_REG_P (operands[1]))
1077 if (ADDRESS_REG_P (operands[0]))
1078 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1079 return \"fmove%.s %f1,%0\";
1081 return \"move%.l %1,%0\";
1084 (define_insn "movdf"
1085 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1086 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1087 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1088 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1092 if (which_alternative == 7)
1093 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1094 if (FPA_REG_P (operands[0]))
1096 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1097 return output_move_const_double (operands);
1098 if (FP_REG_P (operands[1]))
1099 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1100 return \"fpmove%.d %x1,%x0\";
1102 else if (FPA_REG_P (operands[1]))
1104 if (FP_REG_P(operands[0]))
1105 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1107 return \"fpmove%.d %x1,%x0\";
1109 if (FP_REG_P (operands[0]))
1111 if (FP_REG_P (operands[1]))
1112 return \"f%&move%.x %1,%0\";
1113 if (REG_P (operands[1]))
1116 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1117 output_asm_insn (\"move%.l %1,%-\", xoperands);
1118 output_asm_insn (\"move%.l %1,%-\", operands);
1119 return \"f%&move%.d %+,%0\";
1121 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1122 return output_move_const_double (operands);
1123 return \"f%&move%.d %f1,%0\";
1125 else if (FP_REG_P (operands[1]))
1127 if (REG_P (operands[0]))
1129 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1130 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1131 return \"move%.l %+,%0\";
1134 return \"fmove%.d %f1,%0\";
1136 return output_move_double (operands);
1140 (define_expand "movxf"
1141 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1142 (match_operand:XF 1 "general_operand" ""))]
1146 if (CONSTANT_P (operands[1]))
1148 operands[1] = force_const_mem (XFmode, operands[1]);
1149 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1150 && ! reload_in_progress)
1151 operands[1] = change_address (operands[1], XFmode,
1152 XEXP (operands[1], 0));
1157 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1158 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1162 if (FP_REG_P (operands[0]))
1164 if (FP_REG_P (operands[1]))
1165 return \"fmove%.x %1,%0\";
1166 if (REG_P (operands[1]))
1169 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1170 output_asm_insn (\"move%.l %1,%-\", xoperands);
1171 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1172 output_asm_insn (\"move%.l %1,%-\", xoperands);
1173 output_asm_insn (\"move%.l %1,%-\", operands);
1174 return \"fmove%.x %+,%0\";
1176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1177 return \"fmove%.x %1,%0\";
1178 return \"fmove%.x %f1,%0\";
1180 if (REG_P (operands[0]))
1182 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1183 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1184 output_asm_insn (\"move%.l %+,%0\", operands);
1185 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1186 return \"move%.l %+,%0\";
1188 return \"fmove%.x %f1,%0\";
1193 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1194 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1198 if (FP_REG_P (operands[0]))
1200 if (FP_REG_P (operands[1]))
1201 return \"fmove%.x %1,%0\";
1202 if (REG_P (operands[1]))
1205 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1206 output_asm_insn (\"move%.l %1,%-\", xoperands);
1207 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1208 output_asm_insn (\"move%.l %1,%-\", xoperands);
1209 output_asm_insn (\"move%.l %1,%-\", operands);
1210 return \"fmove%.x %+,%0\";
1212 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1213 return \"fmove%.x %1,%0\";
1214 return \"fmove%.x %f1,%0\";
1216 if (FP_REG_P (operands[1]))
1218 if (REG_P (operands[0]))
1220 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1221 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1222 output_asm_insn (\"move%.l %+,%0\", operands);
1223 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1224 return \"move%.l %+,%0\";
1227 return \"fmove%.x %f1,%0\";
1229 return output_move_double (operands);
1233 ;; movdi can apply to fp regs in some cases
1234 (define_insn "movdi"
1235 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1236 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1237 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1238 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1239 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1240 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1241 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1245 if (which_alternative == 8)
1246 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1247 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1248 return \"fpmove%.d %x1,%x0\";
1249 if (FP_REG_P (operands[0]))
1251 if (FP_REG_P (operands[1]))
1252 return \"fmove%.x %1,%0\";
1253 if (REG_P (operands[1]))
1256 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1257 output_asm_insn (\"move%.l %1,%-\", xoperands);
1258 output_asm_insn (\"move%.l %1,%-\", operands);
1259 return \"fmove%.d %+,%0\";
1261 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1262 return output_move_const_double (operands);
1263 return \"fmove%.d %f1,%0\";
1265 else if (FP_REG_P (operands[1]))
1267 if (REG_P (operands[0]))
1269 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1270 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1271 return \"move%.l %+,%0\";
1274 return \"fmove%.d %f1,%0\";
1276 return output_move_double (operands);
1280 ;; Thus goes after the move instructions
1281 ;; because the move instructions are better (require no spilling)
1282 ;; when they can apply. It goes before the add/sub insns
1283 ;; so we will prefer it to them.
1285 (define_insn "pushasi"
1286 [(set (match_operand:SI 0 "push_operand" "=m")
1287 (match_operand:SI 1 "address_operand" "p"))]
1291 ;; truncation instructions
1292 (define_insn "truncsiqi2"
1293 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1295 (match_operand:SI 1 "general_operand" "doJ,i")))]
1299 if (GET_CODE (operands[0]) == REG)
1301 /* Must clear condition codes, since the move.l bases them on
1302 the entire 32 bits, not just the desired 8 bits. */
1304 return \"move%.l %1,%0\";
1306 if (GET_CODE (operands[1]) == MEM)
1307 operands[1] = adj_offsettable_operand (operands[1], 3);
1308 return \"move%.b %1,%0\";
1311 (define_insn "trunchiqi2"
1312 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1314 (match_operand:HI 1 "general_operand" "doJ,i")))]
1318 if (GET_CODE (operands[0]) == REG
1319 && (GET_CODE (operands[1]) == MEM
1320 || GET_CODE (operands[1]) == CONST_INT))
1322 /* Must clear condition codes, since the move.w bases them on
1323 the entire 16 bits, not just the desired 8 bits. */
1325 return \"move%.w %1,%0\";
1327 if (GET_CODE (operands[0]) == REG)
1329 /* Must clear condition codes, since the move.l bases them on
1330 the entire 32 bits, not just the desired 8 bits. */
1332 return \"move%.l %1,%0\";
1334 if (GET_CODE (operands[1]) == MEM)
1335 operands[1] = adj_offsettable_operand (operands[1], 1);
1336 return \"move%.b %1,%0\";
1339 (define_insn "truncsihi2"
1340 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1342 (match_operand:SI 1 "general_operand" "roJ,i")))]
1346 if (GET_CODE (operands[0]) == REG)
1348 /* Must clear condition codes, since the move.l bases them on
1349 the entire 32 bits, not just the desired 8 bits. */
1351 return \"move%.l %1,%0\";
1353 if (GET_CODE (operands[1]) == MEM)
1354 operands[1] = adj_offsettable_operand (operands[1], 2);
1355 return \"move%.w %1,%0\";
1358 ;; zero extension instructions
1360 ;; this is the canonical form for (lshiftrt:DI x 32)
1361 (define_insn "zero_extendsidi2"
1362 [(set (match_operand:DI 0 "general_operand" "rm")
1363 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1368 if (GET_CODE (operands[0]) == REG)
1369 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1370 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1371 return \"move%.l %1,%0\;clr%.l %0\";
1372 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1373 return \"clr%.l %0\;move%.l %1,%0\";
1375 operands[2] = adj_offsettable_operand (operands[0], 4);
1376 if (ADDRESS_REG_P (operands[0]))
1377 return \"move%.l %1,%2\;sub%.l %0,%0\";
1379 return \"move%.l %1,%2\;clr%.l %0\";
1382 (define_expand "zero_extendhisi2"
1383 [(set (match_operand:SI 0 "register_operand" "")
1385 (set (strict_low_part (match_dup 2))
1386 (match_operand:HI 1 "general_operand" ""))]
1390 operands[1] = make_safe_from (operands[1], operands[0]);
1391 if (GET_CODE (operands[0]) == SUBREG)
1392 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1393 SUBREG_WORD (operands[0]));
1395 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1398 (define_expand "zero_extendqihi2"
1399 [(set (match_operand:HI 0 "register_operand" "")
1401 (set (strict_low_part (match_dup 2))
1402 (match_operand:QI 1 "general_operand" ""))]
1406 operands[1] = make_safe_from (operands[1], operands[0]);
1407 if (GET_CODE (operands[0]) == SUBREG)
1408 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1409 SUBREG_WORD (operands[0]));
1411 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1414 (define_expand "zero_extendqisi2"
1415 [(set (match_operand:SI 0 "register_operand" "")
1417 (set (strict_low_part (match_dup 2))
1418 (match_operand:QI 1 "general_operand" ""))]
1422 operands[1] = make_safe_from (operands[1], operands[0]);
1423 if (GET_CODE (operands[0]) == SUBREG)
1424 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1425 SUBREG_WORD (operands[0]));
1427 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1430 ;; Patterns to recognize zero-extend insns produced by the combiner.
1431 ;; We don't allow both operands in memory, because of aliasing problems.
1432 ;; Explicitly disallow two memory operands via the condition since reloading
1433 ;; of this case will result in worse code than the uncombined patterns.
1436 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1437 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1438 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1441 if (DATA_REG_P (operands[0]))
1443 if (GET_CODE (operands[1]) == REG
1444 && REGNO (operands[0]) == REGNO (operands[1]))
1445 return \"and%.l %#0xFFFF,%0\";
1446 if (reg_mentioned_p (operands[0], operands[1]))
1447 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1448 return \"clr%.l %0\;move%.w %1,%0\";
1450 else if (GET_CODE (operands[0]) == MEM
1451 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1452 return \"move%.w %1,%0\;clr%.w %0\";
1453 else if (GET_CODE (operands[0]) == MEM
1454 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1455 return \"clr%.w %0\;move%.w %1,%0\";
1458 output_asm_insn (\"clr%.w %0\", operands);
1459 operands[0] = adj_offsettable_operand (operands[0], 2);
1460 return \"move%.w %1,%0\";
1465 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1466 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1467 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1470 if (DATA_REG_P (operands[0]))
1472 if (GET_CODE (operands[1]) == REG
1473 && REGNO (operands[0]) == REGNO (operands[1]))
1474 return \"and%.w %#0xFF,%0\";
1475 if (reg_mentioned_p (operands[0], operands[1]))
1476 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1477 return \"clr%.w %0\;move%.b %1,%0\";
1479 else if (GET_CODE (operands[0]) == MEM
1480 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1482 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1483 == STACK_POINTER_REGNUM)
1485 output_asm_insn (\"clr%.w %-\", operands);
1486 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1487 plus_constant (stack_pointer_rtx, 1));
1488 return \"move%.b %1,%0\";
1491 return \"move%.b %1,%0\;clr%.b %0\";
1493 else if (GET_CODE (operands[0]) == MEM
1494 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1495 return \"clr%.b %0\;move%.b %1,%0\";
1498 output_asm_insn (\"clr%.b %0\", operands);
1499 operands[0] = adj_offsettable_operand (operands[0], 1);
1500 return \"move%.b %1,%0\";
1505 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1506 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1507 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1510 if (DATA_REG_P (operands[0]))
1512 if (GET_CODE (operands[1]) == REG
1513 && REGNO (operands[0]) == REGNO (operands[1]))
1514 return \"and%.l %#0xFF,%0\";
1515 if (reg_mentioned_p (operands[0], operands[1]))
1516 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1517 return \"clr%.l %0\;move%.b %1,%0\";
1519 else if (GET_CODE (operands[0]) == MEM
1520 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1522 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1525 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1527 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1530 return \"clrl %0@-\;moveb %1,%0@(3)\";
1533 else if (GET_CODE (operands[0]) == MEM
1534 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1536 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1539 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1541 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1544 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1549 output_asm_insn (\"clr%.l %0\", operands);
1550 operands[0] = adj_offsettable_operand (operands[0], 3);
1551 return \"move%.b %1,%0\";
1555 ;; sign extension instructions
1557 (define_insn "extendqidi2"
1558 [(set (match_operand:DI 0 "general_operand" "=d")
1560 (match_operand:QI 1 "general_operand" "rm")))]
1565 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1566 if (TARGET_68020 || TARGET_5200)
1567 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1569 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1572 (define_insn "extendhidi2"
1573 [(set (match_operand:DI 0 "general_operand" "=d")
1575 (match_operand:HI 1 "general_operand" "rm")))]
1580 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1581 if (TARGET_68020 || TARGET_5200)
1582 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1584 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1587 (define_insn "extendsidi2"
1588 [(set (match_operand:DI 0 "general_operand" "=d")
1590 (match_operand:SI 1 "general_operand" "rm")))]
1595 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1596 if (TARGET_68020 || TARGET_5200)
1597 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1599 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1602 ;; Special case when one can avoid register clobbering, copy and test
1603 ;; Maybe there is a way to make that the general case, by forcing the
1604 ;; result of the SI tree to be in the lower register of the DI target
1606 (define_insn "extendplussidi"
1607 [(set (match_operand:DI 0 "register_operand" "=d")
1608 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1609 (match_operand:SI 2 "general_operand" "rmn"))))]
1614 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1615 if (GET_CODE (operands[1]) == CONST_INT
1616 && (unsigned) INTVAL (operands[1]) > 8)
1618 rtx tmp = operands[1];
1620 operands[1] = operands[2];
1623 if (GET_CODE (operands[1]) == REG
1624 && REGNO (operands[1]) == REGNO (operands[3]))
1625 output_asm_insn (\"add%.l %2,%3\", operands);
1627 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1628 if (TARGET_68020 || TARGET_5200)
1629 return \"smi %0\;extb%.l %0\";
1631 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1634 (define_insn "extendhisi2"
1635 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1637 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1641 if (ADDRESS_REG_P (operands[0]))
1642 return \"move%.w %1,%0\";
1643 return \"ext%.l %0\";
1646 (define_insn "extendqihi2"
1647 [(set (match_operand:HI 0 "general_operand" "=d")
1648 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1652 (define_insn "extendqisi2"
1653 [(set (match_operand:SI 0 "general_operand" "=d")
1654 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1655 "TARGET_68020 || TARGET_5200"
1658 ;; Conversions between float and double.
1660 (define_expand "extendsfdf2"
1661 [(set (match_operand:DF 0 "general_operand" "")
1663 (match_operand:SF 1 "general_operand" "")))]
1664 "TARGET_68881 || TARGET_FPA"
1668 [(set (match_operand:DF 0 "general_operand" "=x,y")
1670 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1675 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1677 (match_operand:SF 1 "general_operand" "f,dmF")))]
1681 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1683 if (REGNO (operands[0]) == REGNO (operands[1]))
1685 /* Extending float to double in an fp-reg is a no-op.
1686 NOTICE_UPDATE_CC has already assumed that the
1687 cc will be set. So cancel what it did. */
1688 cc_status = cc_prev_status;
1691 return \"f%&move%.x %1,%0\";
1693 if (FP_REG_P (operands[0]))
1694 return \"f%&move%.s %f1,%0\";
1695 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1697 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1698 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1699 return \"move%.l %+,%0\";
1701 return \"fmove%.d %f1,%0\";
1704 ;; This cannot output into an f-reg because there is no way to be
1705 ;; sure of truncating in that case.
1706 ;; But on the Sun FPA, we can be sure.
1707 (define_expand "truncdfsf2"
1708 [(set (match_operand:SF 0 "general_operand" "")
1710 (match_operand:DF 1 "general_operand" "")))]
1711 "TARGET_68881 || TARGET_FPA"
1715 [(set (match_operand:SF 0 "general_operand" "=x,y")
1717 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1721 ;; On the '040 we can truncate in a register accurately and easily.
1723 [(set (match_operand:SF 0 "general_operand" "=f")
1725 (match_operand:DF 1 "general_operand" "fmG")))]
1729 if (FP_REG_P (operands[1]))
1730 return \"f%$move%.x %1,%0\";
1731 return \"f%$move%.d %f1,%0\";
1735 [(set (match_operand:SF 0 "general_operand" "=dm")
1737 (match_operand:DF 1 "general_operand" "f")))]
1741 ;; Conversion between fixed point and floating point.
1742 ;; Note that among the fix-to-float insns
1743 ;; the ones that start with SImode come first.
1744 ;; That is so that an operand that is a CONST_INT
1745 ;; (and therefore lacks a specific machine mode).
1746 ;; will be recognized as SImode (which is always valid)
1747 ;; rather than as QImode or HImode.
1749 (define_expand "floatsisf2"
1750 [(set (match_operand:SF 0 "general_operand" "")
1751 (float:SF (match_operand:SI 1 "general_operand" "")))]
1752 "TARGET_68881 || TARGET_FPA"
1756 [(set (match_operand:SF 0 "general_operand" "=y,x")
1757 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1762 [(set (match_operand:SF 0 "general_operand" "=f")
1763 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1767 (define_expand "floatsidf2"
1768 [(set (match_operand:DF 0 "general_operand" "")
1769 (float:DF (match_operand:SI 1 "general_operand" "")))]
1770 "TARGET_68881 || TARGET_FPA"
1774 [(set (match_operand:DF 0 "general_operand" "=y,x")
1775 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1780 [(set (match_operand:DF 0 "general_operand" "=f")
1781 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1785 (define_insn "floathisf2"
1786 [(set (match_operand:SF 0 "general_operand" "=f")
1787 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1791 (define_insn "floathidf2"
1792 [(set (match_operand:DF 0 "general_operand" "=f")
1793 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1797 (define_insn "floatqisf2"
1798 [(set (match_operand:SF 0 "general_operand" "=f")
1799 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1803 (define_insn "floatqidf2"
1804 [(set (match_operand:DF 0 "general_operand" "=f")
1805 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1809 ;; New routines to convert floating-point values to integers
1810 ;; to be used on the '040. These should be faster than trapping
1811 ;; into the kernel to emulate fintrz. They should also be faster
1812 ;; than calling the subroutines fixsfsi or fixdfsi.
1814 (define_insn "fix_truncdfsi2"
1815 [(set (match_operand:SI 0 "general_operand" "=dm")
1816 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1817 (clobber (match_scratch:SI 2 "=d"))
1818 (clobber (match_scratch:SI 3 "=d"))]
1819 "TARGET_68881 && TARGET_68040"
1823 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1826 (define_insn "fix_truncdfhi2"
1827 [(set (match_operand:HI 0 "general_operand" "=dm")
1828 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1829 (clobber (match_scratch:SI 2 "=d"))
1830 (clobber (match_scratch:SI 3 "=d"))]
1831 "TARGET_68881 && TARGET_68040"
1835 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1838 (define_insn "fix_truncdfqi2"
1839 [(set (match_operand:QI 0 "general_operand" "=dm")
1840 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1841 (clobber (match_scratch:SI 2 "=d"))
1842 (clobber (match_scratch:SI 3 "=d"))]
1843 "TARGET_68881 && TARGET_68040"
1847 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1850 ;; Convert a float to a float whose value is an integer.
1851 ;; This is the first stage of converting it to an integer type.
1853 (define_insn "ftruncdf2"
1854 [(set (match_operand:DF 0 "general_operand" "=f")
1855 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1856 "TARGET_68881 && !TARGET_68040"
1859 if (FP_REG_P (operands[1]))
1860 return \"fintrz%.x %f1,%0\";
1861 return \"fintrz%.d %f1,%0\";
1864 (define_insn "ftruncsf2"
1865 [(set (match_operand:SF 0 "general_operand" "=f")
1866 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1867 "TARGET_68881 && !TARGET_68040"
1870 if (FP_REG_P (operands[1]))
1871 return \"fintrz%.x %f1,%0\";
1872 return \"fintrz%.s %f1,%0\";
1875 ;; Convert a float whose value is an integer
1876 ;; to an actual integer. Second stage of converting float to integer type.
1877 (define_insn "fixsfqi2"
1878 [(set (match_operand:QI 0 "general_operand" "=dm")
1879 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1883 (define_insn "fixsfhi2"
1884 [(set (match_operand:HI 0 "general_operand" "=dm")
1885 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1889 (define_insn "fixsfsi2"
1890 [(set (match_operand:SI 0 "general_operand" "=dm")
1891 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1895 (define_insn "fixdfqi2"
1896 [(set (match_operand:QI 0 "general_operand" "=dm")
1897 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1901 (define_insn "fixdfhi2"
1902 [(set (match_operand:HI 0 "general_operand" "=dm")
1903 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1907 (define_insn "fixdfsi2"
1908 [(set (match_operand:SI 0 "general_operand" "=dm")
1909 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1913 ;; Convert a float to an integer.
1914 ;; On the Sun FPA, this is done in one step.
1917 [(set (match_operand:SI 0 "general_operand" "=x,y")
1918 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1923 [(set (match_operand:SI 0 "general_operand" "=x,y")
1924 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1930 (define_insn "adddi_lshrdi_63"
1931 [(set (match_operand:DI 0 "general_operand" "=d")
1932 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
1935 (clobber (match_scratch:SI 2 "=d"))]
1939 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1940 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
1942 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
1943 if (GET_CODE (operands[1]) == REG)
1944 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1945 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
1946 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1947 operands[4] = operands[1];
1949 operands[4] = adj_offsettable_operand (operands[1], 4);
1950 if (GET_CODE (operands[1]) == MEM
1951 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
1952 output_asm_insn (\"move%.l %4,%3\", operands);
1953 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
1954 if (TARGET_68020 || TARGET_5200)
1955 output_asm_insn (\"extb%.l %2\", operands);
1957 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
1958 if (GET_CODE (operands[1]) != MEM
1959 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
1960 output_asm_insn (\"move%.l %4,%3\", operands);
1961 return \"sub%.l %2,%3\;subx%.l %2,%0\";
1964 (define_insn "adddi_sexthishl32"
1965 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
1966 (plus:DI (ashift:DI (sign_extend:DI
1967 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
1969 (match_operand:DI 2 "general_operand" "0,0,0,0")))
1970 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
1975 if (ADDRESS_REG_P (operands[0]))
1976 return \"add%.w %1,%0\";
1977 else if (ADDRESS_REG_P (operands[3]))
1978 return \"move%.w %1,%3\;add%.l %3,%0\";
1980 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
1983 (define_insn "adddi_dilshr32"
1984 [(set (match_operand:DI 0 "general_operand" "=do")
1985 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
1986 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1987 ;; (const_int 32))))]
1988 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
1990 (match_operand:DI 2 "general_operand" "0")))]
1995 if (GET_CODE (operands[0]) == REG)
1996 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1998 operands[2] = adj_offsettable_operand (operands[0], 4);
1999 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2002 (define_insn "adddi_dishl32"
2003 [(set (match_operand:DI 0 "general_operand" "=ro")
2004 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2005 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2006 ;; (const_int 32))))]
2007 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2009 (match_operand:DI 2 "general_operand" "0")))]
2014 if (GET_CODE (operands[1]) == REG)
2015 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2017 operands[1] = adj_offsettable_operand (operands[1], 4);
2018 return \"add%.l %1,%0\";
2021 (define_insn "adddi3"
2022 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2023 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2024 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2025 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2029 if (DATA_REG_P (operands[0]))
2031 if (DATA_REG_P (operands[2]))
2032 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2033 else if (GET_CODE (operands[2]) == MEM
2034 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2036 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2040 /* TODO : this should work also for CONST operands[2] */
2041 if (GET_CODE (operands[2]) == REG)
2042 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2044 operands[1] = adj_offsettable_operand (operands[2], 4);
2045 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2048 else if (GET_CODE (operands[0]) == MEM)
2050 if (GET_CODE (operands[2]) == MEM
2051 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2052 return \"add%.l %2,%0\;addx%.l %2,%0\";
2054 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2056 operands[1] = gen_rtx (MEM, SImode,
2057 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2058 gen_rtx (CONST_INT, VOIDmode, -8)));
2059 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2061 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2063 operands[1] = XEXP(operands[0], 0);
2064 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2068 operands[1] = adj_offsettable_operand (operands[0], 4);
2069 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2074 (define_insn "addsi_lshrsi_31"
2075 [(set (match_operand:SI 0 "general_operand" "=dm")
2076 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2082 operands[2] = operands[0];
2083 operands[3] = gen_label_rtx();
2084 if (GET_CODE (operands[0]) == MEM)
2086 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2087 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2088 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2089 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2091 output_asm_insn (\"move%.l %1,%0\", operands);
2093 output_asm_insn (\"jbpl %l3\", operands);
2095 output_asm_insn (\"jpl %l3\", operands);
2098 output_asm_insn (\"addq%.l %#1,%2\", operands);
2100 output_asm_insn (\"add%.l %#1,%2\", operands);
2102 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2103 CODE_LABEL_NUMBER (operands[3]));
2107 ;; Note that the middle two alternatives are near-duplicates
2108 ;; in order to handle insns generated by reload.
2109 ;; This is needed since they are not themselves reloaded,
2110 ;; so commutativity won't apply to them.
2111 (define_insn "addsi3"
2112 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2113 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2114 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2118 if (! operands_match_p (operands[0], operands[1]))
2120 if (!ADDRESS_REG_P (operands[1]))
2122 rtx tmp = operands[1];
2124 operands[1] = operands[2];
2128 /* These insns can result from reloads to access
2129 stack slots over 64k from the frame pointer. */
2130 if (GET_CODE (operands[2]) == CONST_INT
2131 && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
2132 return \"move%.l %2,%0\;add%.l %1,%0\";
2134 if (GET_CODE (operands[2]) == REG)
2135 return \"lea 0(%1,%2.l),%0\";
2137 return \"lea %c2(%1),%0\";
2140 if (GET_CODE (operands[2]) == REG)
2141 return \"lea (%1,%2.l),%0\";
2143 return \"lea (%c2,%1),%0\";
2144 #else /* not MOTOROLA (MIT syntax) */
2145 if (GET_CODE (operands[2]) == REG)
2146 return \"lea %1@(0,%2:l),%0\";
2148 return \"lea %1@(%c2),%0\";
2149 #endif /* not MOTOROLA */
2150 #endif /* not SGS */
2152 if (GET_CODE (operands[2]) == CONST_INT)
2155 if (INTVAL (operands[2]) > 0
2156 && INTVAL (operands[2]) <= 8)
2157 return \"addq%.l %2,%0\";
2158 if (INTVAL (operands[2]) < 0
2159 && INTVAL (operands[2]) >= -8)
2161 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2162 - INTVAL (operands[2]));
2163 return \"subq%.l %2,%0\";
2165 /* On the CPU32 it is faster to use two addql instructions to
2166 add a small integer (8 < N <= 16) to a register.
2167 Likewise for subql. */
2168 if (TARGET_CPU32 && REG_P (operands[0]))
2170 if (INTVAL (operands[2]) > 8
2171 && INTVAL (operands[2]) <= 16)
2173 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2174 INTVAL (operands[2]) - 8);
2175 return \"addq%.l %#8,%0\;addq%.l %2,%0\";
2177 if (INTVAL (operands[2]) < -8
2178 && INTVAL (operands[2]) >= -16)
2180 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2181 - INTVAL (operands[2]) - 8);
2182 return \"subq%.l %#8,%0\;subq%.l %2,%0\";
2186 if (ADDRESS_REG_P (operands[0])
2187 && INTVAL (operands[2]) >= -0x8000
2188 && INTVAL (operands[2]) < 0x8000)
2191 return \"add%.w %2,%0\";
2194 return \"lea (%c2,%0),%0\";
2196 return \"lea %0@(%c2),%0\";
2200 return \"add%.l %2,%0\";
2204 [(set (match_operand:SI 0 "general_operand" "=a")
2205 (plus:SI (match_operand:SI 1 "general_operand" "0")
2207 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2211 (define_insn "addhi3"
2212 [(set (match_operand:HI 0 "general_operand" "=m,r")
2213 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2214 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2218 if (GET_CODE (operands[2]) == CONST_INT)
2221 /* If the constant would be a negative number when interpreted as
2222 HImode, make it negative. This is usually, but not always, done
2223 elsewhere in the compiler. First check for constants out of range,
2224 which could confuse us. */
2226 if (INTVAL (operands[2]) >= 32768)
2227 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2228 INTVAL (operands[2]) - 65536);
2230 if (INTVAL (operands[2]) > 0
2231 && INTVAL (operands[2]) <= 8)
2232 return \"addq%.w %2,%0\";
2233 if (INTVAL (operands[2]) < 0
2234 && INTVAL (operands[2]) >= -8)
2236 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2237 - INTVAL (operands[2]));
2238 return \"subq%.w %2,%0\";
2240 /* On the CPU32 it is faster to use two addqw instructions to
2241 add a small integer (8 < N <= 16) to a register.
2242 Likewise for subqw. */
2243 if (TARGET_CPU32 && REG_P (operands[0]))
2245 if (INTVAL (operands[2]) > 8
2246 && INTVAL (operands[2]) <= 16)
2248 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2249 INTVAL (operands[2]) - 8);
2250 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2252 if (INTVAL (operands[2]) < -8
2253 && INTVAL (operands[2]) >= -16)
2255 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2256 - INTVAL (operands[2]) - 8);
2257 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2261 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2263 return \"lea (%c2,%0),%0\";
2265 return \"lea %0@(%c2),%0\";
2268 return \"add%.w %2,%0\";
2271 ;; These insns must use MATCH_DUP instead of the more expected
2272 ;; use of a matching constraint because the "output" here is also
2273 ;; an input, so you can't use the matching constraint. That also means
2274 ;; that you can't use the "%", so you need patterns with the matched
2275 ;; operand in both positions.
2278 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2279 (plus:HI (match_dup 0)
2280 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2284 if (GET_CODE (operands[1]) == CONST_INT)
2287 /* If the constant would be a negative number when interpreted as
2288 HImode, make it negative. This is usually, but not always, done
2289 elsewhere in the compiler. First check for constants out of range,
2290 which could confuse us. */
2292 if (INTVAL (operands[1]) >= 32768)
2293 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2294 INTVAL (operands[1]) - 65536);
2296 if (INTVAL (operands[1]) > 0
2297 && INTVAL (operands[1]) <= 8)
2298 return \"addq%.w %1,%0\";
2299 if (INTVAL (operands[1]) < 0
2300 && INTVAL (operands[1]) >= -8)
2302 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2303 - INTVAL (operands[1]));
2304 return \"subq%.w %1,%0\";
2306 /* On the CPU32 it is faster to use two addqw instructions to
2307 add a small integer (8 < N <= 16) to a register.
2308 Likewise for subqw. */
2309 if (TARGET_CPU32 && REG_P (operands[0]))
2311 if (INTVAL (operands[1]) > 8
2312 && INTVAL (operands[1]) <= 16)
2314 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2315 INTVAL (operands[1]) - 8);
2316 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2318 if (INTVAL (operands[1]) < -8
2319 && INTVAL (operands[1]) >= -16)
2321 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2322 - INTVAL (operands[1]) - 8);
2323 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2327 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2329 return \"lea (%c1,%0),%0\";
2331 return \"lea %0@(%c1),%0\";
2334 return \"add%.w %1,%0\";
2338 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2339 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2344 if (GET_CODE (operands[1]) == CONST_INT)
2347 /* If the constant would be a negative number when interpreted as
2348 HImode, make it negative. This is usually, but not always, done
2349 elsewhere in the compiler. First check for constants out of range,
2350 which could confuse us. */
2352 if (INTVAL (operands[1]) >= 32768)
2353 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2354 INTVAL (operands[1]) - 65536);
2356 if (INTVAL (operands[1]) > 0
2357 && INTVAL (operands[1]) <= 8)
2358 return \"addq%.w %1,%0\";
2359 if (INTVAL (operands[1]) < 0
2360 && INTVAL (operands[1]) >= -8)
2362 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2363 - INTVAL (operands[1]));
2364 return \"subq%.w %1,%0\";
2366 /* On the CPU32 it is faster to use two addqw instructions to
2367 add a small integer (8 < N <= 16) to a register.
2368 Likewise for subqw. */
2369 if (TARGET_CPU32 && REG_P (operands[0]))
2371 if (INTVAL (operands[1]) > 8
2372 && INTVAL (operands[1]) <= 16)
2374 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2375 INTVAL (operands[1]) - 8);
2376 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2378 if (INTVAL (operands[1]) < -8
2379 && INTVAL (operands[1]) >= -16)
2381 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2382 - INTVAL (operands[1]) - 8);
2383 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2387 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2389 return \"lea (%c1,%0),%0\";
2391 return \"lea %0@(%c1),%0\";
2394 return \"add%.w %1,%0\";
2397 (define_insn "addqi3"
2398 [(set (match_operand:QI 0 "general_operand" "=m,d")
2399 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2400 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2405 if (GET_CODE (operands[2]) == CONST_INT)
2407 if (INTVAL (operands[2]) >= 128)
2408 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2409 INTVAL (operands[2]) - 256);
2411 if (INTVAL (operands[2]) > 0
2412 && INTVAL (operands[2]) <= 8)
2413 return \"addq%.b %2,%0\";
2414 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2416 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2417 return \"subq%.b %2,%0\";
2421 return \"add%.b %2,%0\";
2425 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2426 (plus:QI (match_dup 0)
2427 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2432 if (GET_CODE (operands[1]) == CONST_INT)
2434 if (INTVAL (operands[1]) >= 128)
2435 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2436 INTVAL (operands[1]) - 256);
2438 if (INTVAL (operands[1]) > 0
2439 && INTVAL (operands[1]) <= 8)
2440 return \"addq%.b %1,%0\";
2441 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2443 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2444 return \"subq%.b %1,%0\";
2448 return \"add%.b %1,%0\";
2452 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2453 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2459 if (GET_CODE (operands[1]) == CONST_INT)
2461 if (INTVAL (operands[1]) >= 128)
2462 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2463 INTVAL (operands[1]) - 256);
2465 if (INTVAL (operands[1]) > 0
2466 && INTVAL (operands[1]) <= 8)
2467 return \"addq%.b %1,%0\";
2468 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2470 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2471 return \"subq%.b %1,%0\";
2475 return \"add%.b %1,%0\";
2478 (define_expand "adddf3"
2479 [(set (match_operand:DF 0 "general_operand" "")
2480 (plus:DF (match_operand:DF 1 "general_operand" "")
2481 (match_operand:DF 2 "general_operand" "")))]
2482 "TARGET_68881 || TARGET_FPA"
2486 [(set (match_operand:DF 0 "general_operand" "=x,y")
2487 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2488 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2492 if (rtx_equal_p (operands[0], operands[1]))
2493 return \"fpadd%.d %y2,%0\";
2494 if (rtx_equal_p (operands[0], operands[2]))
2495 return \"fpadd%.d %y1,%0\";
2496 if (which_alternative == 0)
2497 return \"fpadd3%.d %w2,%w1,%0\";
2498 return \"fpadd3%.d %x2,%x1,%0\";
2502 [(set (match_operand:DF 0 "general_operand" "=f")
2503 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2504 (match_operand:DF 1 "general_operand" "0")))]
2509 [(set (match_operand:DF 0 "general_operand" "=f")
2510 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2511 (match_operand:DF 1 "general_operand" "0")))]
2516 [(set (match_operand:DF 0 "general_operand" "=f")
2517 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2518 (match_operand:DF 1 "general_operand" "0")))]
2523 [(set (match_operand:DF 0 "general_operand" "=f")
2524 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2525 (match_operand:DF 2 "general_operand" "fmG")))]
2529 if (REG_P (operands[2]))
2530 return \"f%&add%.x %2,%0\";
2531 return \"f%&add%.d %f2,%0\";
2534 (define_expand "addsf3"
2535 [(set (match_operand:SF 0 "general_operand" "")
2536 (plus:SF (match_operand:SF 1 "general_operand" "")
2537 (match_operand:SF 2 "general_operand" "")))]
2538 "TARGET_68881 || TARGET_FPA"
2542 [(set (match_operand:SF 0 "general_operand" "=x,y")
2543 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2544 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2548 if (rtx_equal_p (operands[0], operands[1]))
2549 return \"fpadd%.s %w2,%0\";
2550 if (rtx_equal_p (operands[0], operands[2]))
2551 return \"fpadd%.s %w1,%0\";
2552 if (which_alternative == 0)
2553 return \"fpadd3%.s %w2,%w1,%0\";
2554 return \"fpadd3%.s %2,%1,%0\";
2558 [(set (match_operand:SF 0 "general_operand" "=f")
2559 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2560 (match_operand:SF 1 "general_operand" "0")))]
2565 [(set (match_operand:SF 0 "general_operand" "=f")
2566 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2567 (match_operand:SF 1 "general_operand" "0")))]
2572 [(set (match_operand:SF 0 "general_operand" "=f")
2573 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2574 (match_operand:SF 1 "general_operand" "0")))]
2579 [(set (match_operand:SF 0 "general_operand" "=f")
2580 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2581 (match_operand:SF 2 "general_operand" "fdmF")))]
2585 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2586 return \"f%$add%.x %2,%0\";
2587 return \"f%$add%.s %f2,%0\";
2590 ;; subtract instructions
2592 (define_insn "subdi_sexthishl32"
2593 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2594 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2595 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2597 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2602 if (ADDRESS_REG_P (operands[0]))
2603 return \"sub%.w %2,%0\";
2604 else if (ADDRESS_REG_P (operands[3]))
2605 return \"move%.w %2,%3\;sub%.l %3,%0\";
2607 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2610 (define_insn "subdi_dishl32"
2611 [(set (match_operand:DI 0 "general_operand" "+ro")
2612 (minus:DI (match_dup 0)
2613 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2619 if (GET_CODE (operands[1]) == REG)
2620 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2622 operands[1] = adj_offsettable_operand (operands[1], 4);
2623 return \"sub%.l %1,%0\";
2626 (define_insn "subdi3"
2627 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2628 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2629 (match_operand:DI 2 "general_operand" "<,d,o>,d,a")))
2630 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2634 if (DATA_REG_P (operands[0]))
2636 if (DATA_REG_P (operands[2]))
2637 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2638 else if (GET_CODE (operands[2]) == MEM
2639 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2641 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2645 /* TODO : this should work also for CONST operands[2] */
2646 if (GET_CODE (operands[2]) == REG)
2647 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2649 operands[1] = adj_offsettable_operand (operands[2], 4);
2650 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2653 else if (GET_CODE (operands[0]) == MEM)
2655 if (GET_CODE (operands[2]) == MEM
2656 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2657 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2659 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2661 operands[1] = gen_rtx (MEM, SImode,
2662 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2663 gen_rtx (CONST_INT, VOIDmode, -8)));
2664 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2666 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2668 operands[1] = XEXP(operands[0], 0);
2669 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2673 operands[1] = adj_offsettable_operand (operands[0], 4);
2674 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2679 (define_insn "subsi3"
2680 [(set (match_operand:SI 0 "general_operand" "=m,r")
2681 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2682 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2687 [(set (match_operand:SI 0 "general_operand" "=a")
2688 (minus:SI (match_operand:SI 1 "general_operand" "0")
2690 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2694 (define_insn "subhi3"
2695 [(set (match_operand:HI 0 "general_operand" "=m,r")
2696 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2697 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2702 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2703 (minus:HI (match_dup 0)
2704 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2708 (define_insn "subqi3"
2709 [(set (match_operand:QI 0 "general_operand" "=m,d")
2710 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2711 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2716 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2717 (minus:QI (match_dup 0)
2718 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2722 (define_expand "subdf3"
2723 [(set (match_operand:DF 0 "general_operand" "")
2724 (minus:DF (match_operand:DF 1 "general_operand" "")
2725 (match_operand:DF 2 "general_operand" "")))]
2726 "TARGET_68881 || TARGET_FPA"
2730 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2731 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2732 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2736 if (rtx_equal_p (operands[0], operands[2]))
2737 return \"fprsub%.d %y1,%0\";
2738 if (rtx_equal_p (operands[0], operands[1]))
2739 return \"fpsub%.d %y2,%0\";
2740 if (which_alternative == 0)
2741 return \"fpsub3%.d %w2,%w1,%0\";
2742 return \"fpsub3%.d %x2,%x1,%0\";
2746 [(set (match_operand:DF 0 "general_operand" "=f")
2747 (minus:DF (match_operand:DF 1 "general_operand" "0")
2748 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2753 [(set (match_operand:DF 0 "general_operand" "=f")
2754 (minus:DF (match_operand:DF 1 "general_operand" "0")
2755 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2760 [(set (match_operand:DF 0 "general_operand" "=f")
2761 (minus:DF (match_operand:DF 1 "general_operand" "0")
2762 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2767 [(set (match_operand:DF 0 "general_operand" "=f")
2768 (minus:DF (match_operand:DF 1 "general_operand" "0")
2769 (match_operand:DF 2 "general_operand" "fmG")))]
2773 if (REG_P (operands[2]))
2774 return \"f%&sub%.x %2,%0\";
2775 return \"f%&sub%.d %f2,%0\";
2778 (define_expand "subsf3"
2779 [(set (match_operand:SF 0 "general_operand" "")
2780 (minus:SF (match_operand:SF 1 "general_operand" "")
2781 (match_operand:SF 2 "general_operand" "")))]
2782 "TARGET_68881 || TARGET_FPA"
2786 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2787 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2788 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2792 if (rtx_equal_p (operands[0], operands[2]))
2793 return \"fprsub%.s %w1,%0\";
2794 if (rtx_equal_p (operands[0], operands[1]))
2795 return \"fpsub%.s %w2,%0\";
2796 if (which_alternative == 0)
2797 return \"fpsub3%.s %w2,%w1,%0\";
2798 return \"fpsub3%.s %2,%1,%0\";
2802 [(set (match_operand:SF 0 "general_operand" "=f")
2803 (minus:SF (match_operand:SF 1 "general_operand" "0")
2804 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2809 [(set (match_operand:SF 0 "general_operand" "=f")
2810 (minus:SF (match_operand:SF 1 "general_operand" "0")
2811 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2816 [(set (match_operand:SF 0 "general_operand" "=f")
2817 (minus:SF (match_operand:SF 1 "general_operand" "0")
2818 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2823 [(set (match_operand:SF 0 "general_operand" "=f")
2824 (minus:SF (match_operand:SF 1 "general_operand" "0")
2825 (match_operand:SF 2 "general_operand" "fdmF")))]
2829 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2830 return \"f%$sub%.x %2,%0\";
2831 return \"f%$sub%.s %f2,%0\";
2834 ;; multiply instructions
2836 (define_insn "mulhi3"
2837 [(set (match_operand:HI 0 "general_operand" "=d")
2838 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2839 (match_operand:HI 2 "general_operand" "dmn")))]
2843 #if defined(MOTOROLA) && !defined(CRDS)
2844 return \"muls%.w %2,%0\";
2846 return \"muls %2,%0\";
2850 (define_insn "mulhisi3"
2851 [(set (match_operand:SI 0 "general_operand" "=d")
2852 (mult:SI (sign_extend:SI
2853 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2855 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2859 #if defined(MOTOROLA) && !defined(CRDS)
2860 return \"muls%.w %2,%0\";
2862 return \"muls %2,%0\";
2867 [(set (match_operand:SI 0 "general_operand" "=d")
2868 (mult:SI (sign_extend:SI
2869 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2870 (match_operand:SI 2 "const_int_operand" "n")))]
2871 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2874 #if defined(MOTOROLA) && !defined(CRDS)
2875 return \"muls%.w %2,%0\";
2877 return \"muls %2,%0\";
2881 (define_insn "mulsi3"
2882 [(set (match_operand:SI 0 "general_operand" "=d")
2883 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2884 (match_operand:SI 2 "general_operand" "dmsK")))]
2885 "TARGET_68020 || TARGET_5200"
2888 (define_insn "umulhisi3"
2889 [(set (match_operand:SI 0 "general_operand" "=d")
2890 (mult:SI (zero_extend:SI
2891 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2893 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2897 #if defined(MOTOROLA) && !defined(CRDS)
2898 return \"mulu%.w %2,%0\";
2900 return \"mulu %2,%0\";
2905 [(set (match_operand:SI 0 "general_operand" "=d")
2906 (mult:SI (zero_extend:SI
2907 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2908 (match_operand:SI 2 "const_int_operand" "n")))]
2909 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2912 #if defined(MOTOROLA) && !defined(CRDS)
2913 return \"mulu%.w %2,%0\";
2915 return \"mulu %2,%0\";
2919 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2920 ;; proper matching constraint. This is because the matching is between
2921 ;; the high-numbered word of the DImode operand[0] and operand[1].
2922 (define_expand "umulsidi3"
2924 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2925 (mult:SI (match_operand:SI 1 "register_operand" "")
2926 (match_operand:SI 2 "nonimmediate_operand" "")))
2927 (set (subreg:SI (match_dup 0) 0)
2928 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2929 (zero_extend:DI (match_dup 2)))
2930 (const_int 32))))])]
2931 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2935 [(set (match_operand:SI 0 "register_operand" "=d")
2936 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2937 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2938 (set (match_operand:SI 3 "register_operand" "=d")
2939 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2940 (zero_extend:DI (match_dup 2)))
2942 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2945 ; Match immediate case. For 2.4 only match things < 2^31.
2946 ; It's tricky with larger values in these patterns since we need to match
2947 ; values between the two parallel multiplies, between a CONST_DOUBLE and
2950 [(set (match_operand:SI 0 "register_operand" "=d")
2951 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2952 (match_operand:SI 2 "const_int_operand" "n")))
2953 (set (match_operand:SI 3 "register_operand" "=d")
2954 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2957 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2958 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2961 (define_expand "mulsidi3"
2963 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2964 (mult:SI (match_operand:SI 1 "register_operand" "")
2965 (match_operand:SI 2 "nonimmediate_operand" "")))
2966 (set (subreg:SI (match_dup 0) 0)
2967 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2968 (sign_extend:DI (match_dup 2)))
2969 (const_int 32))))])]
2970 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2974 [(set (match_operand:SI 0 "register_operand" "=d")
2975 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2976 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2977 (set (match_operand:SI 3 "register_operand" "=d")
2978 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2979 (sign_extend:DI (match_dup 2)))
2981 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2985 [(set (match_operand:SI 0 "register_operand" "=d")
2986 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2987 (match_operand:SI 2 "const_sint32_operand" "")))
2988 (set (match_operand:SI 3 "register_operand" "=d")
2989 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2992 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2995 (define_expand "umulsi3_highpart"
2997 [(set (match_operand:SI 0 "register_operand" "")
3000 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3001 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3003 (clobber (match_dup 3))])]
3004 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3007 operands[3] = gen_reg_rtx (SImode);
3008 if (GET_CODE (operands[2]) == CONST_INT
3009 || GET_CODE (operands[2]) == CONST_DOUBLE)
3011 if (! const_uint32_operand (operands[2], VOIDmode))
3013 /* We have to adjust the operand order for the matching constraints. */
3014 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3015 operands[1], operands[2]));
3021 [(set (match_operand:SI 0 "register_operand" "=d")
3024 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3025 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3027 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3028 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3031 (define_insn "const_umulsi3_highpart"
3032 [(set (match_operand:SI 0 "register_operand" "=d")
3035 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3036 (match_operand 3 "const_uint32_operand" ""))
3038 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3039 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3042 (define_expand "smulsi3_highpart"
3044 [(set (match_operand:SI 0 "register_operand" "")
3047 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3048 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3050 (clobber (match_dup 3))])]
3051 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3054 operands[3] = gen_reg_rtx (SImode);
3055 if (GET_CODE (operands[2]) == CONST_INT
3056 || GET_CODE (operands[2]) == CONST_DOUBLE)
3058 if (! const_sint32_operand (operands[2], VOIDmode))
3060 /* We have to adjust the operand order for the matching constraints. */
3061 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3062 operands[1], operands[2]));
3068 [(set (match_operand:SI 0 "register_operand" "=d")
3071 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3072 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3074 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3075 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3078 (define_insn "const_smulsi3_highpart"
3079 [(set (match_operand:SI 0 "register_operand" "=d")
3082 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3083 (match_operand 3 "const_sint32_operand" ""))
3085 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3086 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3089 (define_expand "muldf3"
3090 [(set (match_operand:DF 0 "general_operand" "")
3091 (mult:DF (match_operand:DF 1 "general_operand" "")
3092 (match_operand:DF 2 "general_operand" "")))]
3093 "TARGET_68881 || TARGET_FPA"
3097 [(set (match_operand:DF 0 "general_operand" "=x,y")
3098 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3099 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3103 if (rtx_equal_p (operands[1], operands[2]))
3104 return \"fpsqr%.d %y1,%0\";
3105 if (rtx_equal_p (operands[0], operands[1]))
3106 return \"fpmul%.d %y2,%0\";
3107 if (rtx_equal_p (operands[0], operands[2]))
3108 return \"fpmul%.d %y1,%0\";
3109 if (which_alternative == 0)
3110 return \"fpmul3%.d %w2,%w1,%0\";
3111 return \"fpmul3%.d %x2,%x1,%0\";
3115 [(set (match_operand:DF 0 "general_operand" "=f")
3116 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3117 (match_operand:DF 1 "general_operand" "0")))]
3122 [(set (match_operand:DF 0 "general_operand" "=f")
3123 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3124 (match_operand:DF 1 "general_operand" "0")))]
3129 [(set (match_operand:DF 0 "general_operand" "=f")
3130 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3131 (match_operand:DF 1 "general_operand" "0")))]
3136 [(set (match_operand:DF 0 "general_operand" "=f")
3137 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3138 (match_operand:DF 2 "general_operand" "fmG")))]
3142 if (GET_CODE (operands[2]) == CONST_DOUBLE
3143 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3145 int i = floating_exact_log2 (operands[2]);
3146 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3147 return \"fscale%.l %2,%0\";
3149 if (REG_P (operands[2]))
3150 return \"f%&mul%.x %2,%0\";
3151 return \"f%&mul%.d %f2,%0\";
3154 (define_expand "mulsf3"
3155 [(set (match_operand:SF 0 "general_operand" "")
3156 (mult:SF (match_operand:SF 1 "general_operand" "")
3157 (match_operand:SF 2 "general_operand" "")))]
3158 "TARGET_68881 || TARGET_FPA"
3162 [(set (match_operand:SF 0 "general_operand" "=x,y")
3163 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3164 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3168 if (rtx_equal_p (operands[1], operands[2]))
3169 return \"fpsqr%.s %w1,%0\";
3170 if (rtx_equal_p (operands[0], operands[1]))
3171 return \"fpmul%.s %w2,%0\";
3172 if (rtx_equal_p (operands[0], operands[2]))
3173 return \"fpmul%.s %w1,%0\";
3174 if (which_alternative == 0)
3175 return \"fpmul3%.s %w2,%w1,%0\";
3176 return \"fpmul3%.s %2,%1,%0\";
3180 [(set (match_operand:SF 0 "general_operand" "=f")
3181 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3182 (match_operand:SF 1 "general_operand" "0")))]
3186 return (TARGET_68040_ONLY
3187 ? \"fsmul%.l %2,%0\"
3188 : \"fsglmul%.l %2,%0\");
3192 [(set (match_operand:SF 0 "general_operand" "=f")
3193 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3194 (match_operand:SF 1 "general_operand" "0")))]
3198 return (TARGET_68040_ONLY
3199 ? \"fsmul%.w %2,%0\"
3200 : \"fsglmul%.w %2,%0\");
3204 [(set (match_operand:SF 0 "general_operand" "=f")
3205 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3206 (match_operand:SF 1 "general_operand" "0")))]
3210 return (TARGET_68040_ONLY
3211 ? \"fsmul%.b %2,%0\"
3212 : \"fsglmul%.b %2,%0\");
3216 [(set (match_operand:SF 0 "general_operand" "=f")
3217 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3218 (match_operand:SF 2 "general_operand" "fdmF")))]
3222 #ifdef FSGLMUL_USE_S
3223 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3224 return (TARGET_68040_ONLY
3225 ? \"fsmul%.s %2,%0\"
3226 : \"fsglmul%.s %2,%0\");
3228 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3229 return (TARGET_68040_ONLY
3230 ? \"fsmul%.x %2,%0\"
3231 : \"fsglmul%.x %2,%0\");
3233 return (TARGET_68040_ONLY
3234 ? \"fsmul%.s %f2,%0\"
3235 : \"fsglmul%.s %f2,%0\");
3238 ;; divide instructions
3240 (define_expand "divdf3"
3241 [(set (match_operand:DF 0 "general_operand" "")
3242 (div:DF (match_operand:DF 1 "general_operand" "")
3243 (match_operand:DF 2 "general_operand" "")))]
3244 "TARGET_68881 || TARGET_FPA"
3248 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3249 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3250 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3254 if (rtx_equal_p (operands[0], operands[2]))
3255 return \"fprdiv%.d %y1,%0\";
3256 if (rtx_equal_p (operands[0], operands[1]))
3257 return \"fpdiv%.d %y2,%0\";
3258 if (which_alternative == 0)
3259 return \"fpdiv3%.d %w2,%w1,%0\";
3260 return \"fpdiv3%.d %x2,%x1,%x0\";
3264 [(set (match_operand:DF 0 "general_operand" "=f")
3265 (div:DF (match_operand:DF 1 "general_operand" "0")
3266 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3271 [(set (match_operand:DF 0 "general_operand" "=f")
3272 (div:DF (match_operand:DF 1 "general_operand" "0")
3273 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3278 [(set (match_operand:DF 0 "general_operand" "=f")
3279 (div:DF (match_operand:DF 1 "general_operand" "0")
3280 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3285 [(set (match_operand:DF 0 "general_operand" "=f")
3286 (div:DF (match_operand:DF 1 "general_operand" "0")
3287 (match_operand:DF 2 "general_operand" "fmG")))]
3291 if (REG_P (operands[2]))
3292 return \"f%&div%.x %2,%0\";
3293 return \"f%&div%.d %f2,%0\";
3296 (define_expand "divsf3"
3297 [(set (match_operand:SF 0 "general_operand" "")
3298 (div:SF (match_operand:SF 1 "general_operand" "")
3299 (match_operand:SF 2 "general_operand" "")))]
3300 "TARGET_68881 || TARGET_FPA"
3304 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3305 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3306 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3310 if (rtx_equal_p (operands[0], operands[1]))
3311 return \"fpdiv%.s %w2,%0\";
3312 if (rtx_equal_p (operands[0], operands[2]))
3313 return \"fprdiv%.s %w1,%0\";
3314 if (which_alternative == 0)
3315 return \"fpdiv3%.s %w2,%w1,%0\";
3316 return \"fpdiv3%.s %2,%1,%0\";
3320 [(set (match_operand:SF 0 "general_operand" "=f")
3321 (div:SF (match_operand:SF 1 "general_operand" "0")
3322 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3326 return (TARGET_68040_ONLY
3327 ? \"fsdiv%.l %2,%0\"
3328 : \"fsgldiv%.l %2,%0\");
3332 [(set (match_operand:SF 0 "general_operand" "=f")
3333 (div:SF (match_operand:SF 1 "general_operand" "0")
3334 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3338 return (TARGET_68040_ONLY
3339 ? \"fsdiv%.w %2,%0\"
3340 : \"fsgldiv%.w %2,%0\");
3344 [(set (match_operand:SF 0 "general_operand" "=f")
3345 (div:SF (match_operand:SF 1 "general_operand" "0")
3346 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3350 return (TARGET_68040_ONLY
3351 ? \"fsdiv%.b %2,%0\"
3352 : \"fsgldiv%.b %2,%0\");
3356 [(set (match_operand:SF 0 "general_operand" "=f")
3357 (div:SF (match_operand:SF 1 "general_operand" "0")
3358 (match_operand:SF 2 "general_operand" "fdmF")))]
3362 #ifdef FSGLDIV_USE_S
3363 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3364 return (TARGET_68040_ONLY
3365 ? \"fsdiv%.s %2,%0\"
3366 : \"fsgldiv%.s %2,%0\");
3368 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3369 return (TARGET_68040_ONLY
3370 ? \"fsdiv%.x %2,%0\"
3371 : \"fsgldiv%.x %2,%0\");
3373 return (TARGET_68040_ONLY
3374 ? \"fsdiv%.s %f2,%0\"
3375 : \"fsgldiv%.s %f2,%0\");
3378 ;; Remainder instructions.
3380 (define_insn "divmodsi4"
3381 [(set (match_operand:SI 0 "general_operand" "=d")
3382 (div:SI (match_operand:SI 1 "general_operand" "0")
3383 (match_operand:SI 2 "general_operand" "dmsK")))
3384 (set (match_operand:SI 3 "general_operand" "=d")
3385 (mod:SI (match_dup 1) (match_dup 2)))]
3386 "TARGET_68020 && !TARGET_5200"
3389 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3390 return \"divs%.l %2,%0\";
3392 return \"divsl%.l %2,%3:%0\";
3395 (define_insn "udivmodsi4"
3396 [(set (match_operand:SI 0 "general_operand" "=d")
3397 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3398 (match_operand:SI 2 "general_operand" "dmsK")))
3399 (set (match_operand:SI 3 "general_operand" "=d")
3400 (umod:SI (match_dup 1) (match_dup 2)))]
3401 "TARGET_68020 && !TARGET_5200"
3404 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3405 return \"divu%.l %2,%0\";
3407 return \"divul%.l %2,%3:%0\";
3410 (define_insn "divmodhi4"
3411 [(set (match_operand:HI 0 "general_operand" "=d")
3412 (div:HI (match_operand:HI 1 "general_operand" "0")
3413 (match_operand:HI 2 "general_operand" "dmsK")))
3414 (set (match_operand:HI 3 "general_operand" "=d")
3415 (mod:HI (match_dup 1) (match_dup 2)))]
3420 output_asm_insn(\"ext%.l %0\;divs%.w %2,%0\", operands);
3422 output_asm_insn(\"extl %0\;divs %2,%0\", operands);
3424 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3427 return \"move%.l %0,%3\;swap %3\";
3433 (define_insn "udivmodhi4"
3434 [(set (match_operand:HI 0 "general_operand" "=d")
3435 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3436 (match_operand:HI 2 "general_operand" "dmsK")))
3437 (set (match_operand:HI 3 "general_operand" "=d")
3438 (umod:HI (match_dup 1) (match_dup 2)))]
3443 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3445 output_asm_insn(\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3447 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3450 return \"move%.l %0,%3\;swap %3\";
3456 ;; logical-and instructions
3458 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3459 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3460 ;; can't allocate pseudos into it.
3462 (define_expand "andsi3"
3463 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3464 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3465 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3469 (define_insn "andsi3_internal"
3470 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3471 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3472 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3477 if (GET_CODE (operands[2]) == CONST_INT
3478 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
3479 && (DATA_REG_P (operands[0])
3480 || offsettable_memref_p (operands[0])))
3482 if (GET_CODE (operands[0]) != REG)
3483 operands[0] = adj_offsettable_operand (operands[0], 2);
3484 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3485 INTVAL (operands[2]) & 0xffff);
3486 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3488 if (operands[2] == const0_rtx)
3489 return \"clr%.w %0\";
3490 return \"and%.w %2,%0\";
3492 if (GET_CODE (operands[2]) == CONST_INT
3493 && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0
3494 && (DATA_REG_P (operands[0])
3495 || offsettable_memref_p (operands[0])))
3497 if (DATA_REG_P (operands[0]))
3499 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3503 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3504 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3506 /* This does not set condition codes in a standard way. */
3508 return \"bclr %1,%0\";
3510 return \"and%.l %2,%0\";
3513 (define_insn "andsi3_5200"
3514 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3515 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3516 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3520 (define_insn "andhi3"
3521 [(set (match_operand:HI 0 "general_operand" "=m,d")
3522 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3523 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3528 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3529 (and:HI (match_dup 0)
3530 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3535 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3536 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3541 (define_insn "andqi3"
3542 [(set (match_operand:QI 0 "general_operand" "=m,d")
3543 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3544 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3549 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3550 (and:QI (match_dup 0)
3551 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3556 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3557 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3562 ;; inclusive-or instructions
3564 (define_expand "iorsi3"
3565 [(set (match_operand:SI 0 "general_operand" "")
3566 (ior:SI (match_operand:SI 1 "general_operand" "")
3567 (match_operand:SI 2 "general_operand" "")))]
3571 (define_insn "iorsi3_internal"
3572 [(set (match_operand:SI 0 "general_operand" "=m,d")
3573 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3574 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3578 register int logval;
3579 if (GET_CODE (operands[2]) == CONST_INT
3580 && INTVAL (operands[2]) >> 16 == 0
3581 && (DATA_REG_P (operands[0])
3582 || offsettable_memref_p (operands[0])))
3584 if (GET_CODE (operands[0]) != REG)
3585 operands[0] = adj_offsettable_operand (operands[0], 2);
3586 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3588 return \"or%.w %2,%0\";
3590 if (GET_CODE (operands[2]) == CONST_INT
3591 && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
3592 && (DATA_REG_P (operands[0])
3593 || offsettable_memref_p (operands[0])))
3595 if (DATA_REG_P (operands[0]))
3597 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
3601 operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
3602 operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
3605 return \"bset %1,%0\";
3607 return \"or%.l %2,%0\";
3610 (define_insn "iorsi3_5200"
3611 [(set (match_operand:SI 0 "general_operand" "=m,d")
3612 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3613 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3617 (define_insn "iorhi3"
3618 [(set (match_operand:HI 0 "general_operand" "=m,d")
3619 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3620 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3625 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3626 (ior:HI (match_dup 0)
3627 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3632 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3633 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3638 (define_insn "iorqi3"
3639 [(set (match_operand:QI 0 "general_operand" "=m,d")
3640 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3641 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3646 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3647 (ior:QI (match_dup 0)
3648 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3653 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3654 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3659 ;; On all 68k models, this makes faster code in a special case.
3660 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3662 (define_insn "iorsi_zexthi_ashl16"
3663 [(set (match_operand:SI 0 "general_operand" "=d,d")
3664 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3665 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3671 if (GET_CODE (operands[2]) != REG)
3673 operands[2] = adj_offsettable_operand (operands[2], 2);
3674 output_asm_insn (\"move%.w %2,%0\", operands);
3676 return \"swap %0\;mov%.w %1,%0\";
3680 [(set (match_operand:SI 0 "general_operand" "=o,d")
3681 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3682 (match_operand:SI 2 "general_operand" "0,0")))]
3689 byte_mode = (GET_MODE(operands[1]) == QImode);
3690 if (GET_CODE (operands[0]) == MEM)
3691 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3693 return \"or%.b %1,%0\";
3695 return \"or%.w %1,%0\";
3700 (define_expand "xorsi3"
3701 [(set (match_operand:SI 0 "general_operand" "")
3702 (xor:SI (match_operand:SI 1 "general_operand" "")
3703 (match_operand:SI 2 "general_operand" "")))]
3707 (define_insn "xorsi3_internal"
3708 [(set (match_operand:SI 0 "general_operand" "=do,m")
3709 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3710 (match_operand:SI 2 "general_operand" "di,dKs")))]
3714 if (GET_CODE (operands[2]) == CONST_INT
3715 && INTVAL (operands[2]) >> 16 == 0
3716 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
3718 if (! DATA_REG_P (operands[0]))
3719 operands[0] = adj_offsettable_operand (operands[0], 2);
3720 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3722 return \"eor%.w %2,%0\";
3724 return \"eor%.l %2,%0\";
3727 (define_insn "xorsi3_5200"
3728 [(set (match_operand:SI 0 "general_operand" "=dm")
3729 (xor:SI (match_operand:SI 1 "general_operand" "%0")
3730 (match_operand:SI 2 "general_operand" "dn")))]
3734 (define_insn "xorhi3"
3735 [(set (match_operand:HI 0 "general_operand" "=dm")
3736 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3737 (match_operand:HI 2 "general_operand" "dn")))]
3742 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3743 (xor:HI (match_dup 0)
3744 (match_operand:HI 1 "general_operand" "dn")))]
3749 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3750 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3755 (define_insn "xorqi3"
3756 [(set (match_operand:QI 0 "general_operand" "=dm")
3757 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3758 (match_operand:QI 2 "general_operand" "dn")))]
3763 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3764 (xor:QI (match_dup 0)
3765 (match_operand:QI 1 "general_operand" "dn")))]
3770 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3771 (xor:QI (match_operand:QI 1 "general_operand" "dn")
3776 ;; negation instructions
3778 (define_expand "negdi2"
3779 [(set (match_operand:DI 0 "general_operand" "")
3780 (neg:DI (match_operand:DI 1 "general_operand" "")))]
3785 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
3787 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
3791 (define_insn "negdi2_internal"
3792 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
3793 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
3797 if (which_alternative == 0)
3798 return \"neg%.l %0\;negx%.l %0\";
3799 if (GET_CODE (operands[0]) == REG)
3800 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3802 operands[1] = adj_offsettable_operand (operands[0], 4);
3803 if (ADDRESS_REG_P (operands[0]))
3804 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
3806 return \"neg%.l %1\;negx%.l %0\";
3809 (define_insn "negdi2_5200"
3810 [(set (match_operand:DI 0 "general_operand" "=d")
3811 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3815 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3816 return \"neg%.l %1\;negx%.l %0\";
3819 (define_expand "negsi2"
3820 [(set (match_operand:SI 0 "general_operand" "")
3821 (neg:SI (match_operand:SI 1 "general_operand" "")))]
3826 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3828 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3832 (define_insn "negsi2_internal"
3833 [(set (match_operand:SI 0 "general_operand" "=dm")
3834 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3838 (define_insn "negsi2_5200"
3839 [(set (match_operand:SI 0 "general_operand" "=d")
3840 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3844 (define_insn "neghi2"
3845 [(set (match_operand:HI 0 "general_operand" "=dm")
3846 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3851 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3852 (neg:HI (match_dup 0)))]
3856 (define_insn "negqi2"
3857 [(set (match_operand:QI 0 "general_operand" "=dm")
3858 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3863 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3864 (neg:QI (match_dup 0)))]
3868 ;; If using software floating point, just flip the sign bit.
3870 (define_expand "negsf2"
3871 [(set (match_operand:SF 0 "general_operand" "")
3872 (neg:SF (match_operand:SF 1 "general_operand" "")))]
3876 if (!TARGET_FPA && !TARGET_68881)
3881 target = operand_subword_force (operands[0], 0, SFmode);
3882 result = expand_binop (SImode, xor_optab,
3883 operand_subword_force (operands[1], 0, SFmode),
3884 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3888 if (result != target)
3889 emit_move_insn (result, target);
3891 /* Make a place for REG_EQUAL. */
3892 emit_move_insn (operands[0], operands[0]);
3898 [(set (match_operand:SF 0 "general_operand" "=x,y")
3899 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
3904 [(set (match_operand:SF 0 "general_operand" "=f,d")
3905 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
3909 if (DATA_REG_P (operands[0]))
3911 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3912 return \"bchg %1,%0\";
3914 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3915 return \"f%$neg%.x %1,%0\";
3916 return \"f%$neg%.s %f1,%0\";
3919 (define_expand "negdf2"
3920 [(set (match_operand:DF 0 "general_operand" "")
3921 (neg:DF (match_operand:DF 1 "general_operand" "")))]
3925 if (!TARGET_FPA && !TARGET_68881)
3932 target = operand_subword (operands[0], 0, 1, DFmode);
3933 result = expand_binop (SImode, xor_optab,
3934 operand_subword_force (operands[1], 0, DFmode),
3935 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
3939 if (result != target)
3940 emit_move_insn (result, target);
3942 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
3943 operand_subword_force (operands[1], 1, DFmode));
3945 insns = get_insns ();
3948 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
3954 [(set (match_operand:DF 0 "general_operand" "=x,y")
3955 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
3960 [(set (match_operand:DF 0 "general_operand" "=f,d")
3961 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
3965 if (DATA_REG_P (operands[0]))
3967 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
3968 return \"bchg %1,%0\";
3970 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
3971 return \"f%&neg%.x %1,%0\";
3972 return \"f%&neg%.d %f1,%0\";
3975 ;; Sqrt instruction for the 68881
3977 (define_insn "sqrtsf2"
3978 [(set (match_operand:SF 0 "general_operand" "=f")
3979 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
3983 if (FP_REG_P (operands[1]))
3984 return \"f%$sqrt%.x %1,%0\";
3986 return \"f%$sqrt%.s %1,%0\";
3989 (define_insn "sqrtdf2"
3990 [(set (match_operand:DF 0 "general_operand" "=f")
3991 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
3995 if (FP_REG_P (operands[1]))
3996 return \"f%&sqrt%.x %1,%0\";
3998 return \"f%&sqrt%.d %1,%0\";
4001 ;; Absolute value instructions
4002 ;; If using software floating point, just zero the sign bit.
4004 (define_expand "abssf2"
4005 [(set (match_operand:SF 0 "general_operand" "")
4006 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4010 if (!TARGET_FPA && !TARGET_68881)
4015 target = operand_subword_force (operands[0], 0, SFmode);
4016 result = expand_binop (SImode, and_optab,
4017 operand_subword_force (operands[1], 0, SFmode),
4018 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4022 if (result != target)
4023 emit_move_insn (result, target);
4025 /* Make a place for REG_EQUAL. */
4026 emit_move_insn (operands[0], operands[0]);
4032 [(set (match_operand:SF 0 "general_operand" "=x,y")
4033 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4038 [(set (match_operand:SF 0 "general_operand" "=f")
4039 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4043 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4044 return \"f%$abs%.x %1,%0\";
4045 return \"f%$abs%.s %f1,%0\";
4048 (define_expand "absdf2"
4049 [(set (match_operand:DF 0 "general_operand" "")
4050 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4054 if (!TARGET_FPA && !TARGET_68881)
4061 target = operand_subword (operands[0], 0, 1, DFmode);
4062 result = expand_binop (SImode, and_optab,
4063 operand_subword_force (operands[1], 0, DFmode),
4064 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4068 if (result != target)
4069 emit_move_insn (result, target);
4071 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4072 operand_subword_force (operands[1], 1, DFmode));
4074 insns = get_insns ();
4077 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4083 [(set (match_operand:DF 0 "general_operand" "=x,y")
4084 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4089 [(set (match_operand:DF 0 "general_operand" "=f")
4090 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4094 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4095 return \"f%&abs%.x %1,%0\";
4096 return \"f%&abs%.d %f1,%0\";
4099 ;; one complement instructions
4101 ;; "one_cmpldi2" is only here to help combine().
4102 (define_insn "one_cmpldi2"
4103 [(set (match_operand:DI 0 "general_operand" "=dm")
4104 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4109 if (GET_CODE (operands[0]) == REG)
4110 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4111 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4112 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4113 operands[1] = operands[0];
4115 operands[1] = adj_offsettable_operand (operands[0], 4);
4116 return \"not%.l %1\;not%.l %0\";
4119 (define_expand "one_cmplsi2"
4120 [(set (match_operand:SI 0 "general_operand" "")
4121 (not:SI (match_operand:SI 1 "general_operand" "")))]
4126 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4128 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4132 (define_insn "one_cmplsi2_internal"
4133 [(set (match_operand:SI 0 "general_operand" "=dm")
4134 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4138 (define_insn "one_cmplsi2_5200"
4139 [(set (match_operand:SI 0 "general_operand" "=d")
4140 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4144 (define_insn "one_cmplhi2"
4145 [(set (match_operand:HI 0 "general_operand" "=dm")
4146 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4151 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4152 (not:HI (match_dup 0)))]
4156 (define_insn "one_cmplqi2"
4157 [(set (match_operand:QI 0 "general_operand" "=dm")
4158 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4163 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4164 (not:QI (match_dup 0)))]
4168 ;; arithmetic shift instructions
4169 ;; We don't need the shift memory by 1 bit instruction
4171 (define_insn "ashldi_extsi"
4172 [(set (match_operand:DI 0 "general_operand" "=ro")
4174 (match_operator:DI 2 "extend_operator"
4175 [(match_operand:SI 1 "general_operand" "rm")])
4181 if (GET_CODE (operands[0]) == REG)
4182 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4184 operands[2] = adj_offsettable_operand (operands[0], 4);
4185 if (ADDRESS_REG_P (operands[0]))
4186 return \"move%.l %1,%0\;sub%.l %2,%2\";
4188 return \"move%.l %1,%0\;clr%.l %2\";
4191 (define_insn "ashldi_sexthi"
4192 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4193 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4195 (clobber (match_scratch:SI 2 "=a,X"))]
4200 if (GET_CODE (operands[0]) == MEM)
4202 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4203 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4204 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4205 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4208 operands[3] = adj_offsettable_operand (operands[0], 4);
4209 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4212 else if (DATA_REG_P (operands[0]))
4213 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4215 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4218 (define_insn "ashldi_const32"
4219 [(set (match_operand:DI 0 "general_operand" "=rm")
4220 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4226 if (GET_CODE (operands[1]) == REG)
4227 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4229 operands[3] = adj_offsettable_operand (operands[1], 4);
4230 if (GET_CODE (operands[0]) == REG)
4231 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4232 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4233 return \"clr%.l %0\;move%.l %3,%0\";
4234 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4235 return \"move%.l %3,%0\;clr%.l %0\";
4237 operands[2] = adj_offsettable_operand (operands[0], 4);
4238 if (ADDRESS_REG_P (operands[2]))
4239 return \"move%.l %3,%0\;sub%.l %2,%2\";
4241 return \"move%.l %3,%0\;clr%.l %2\";
4244 ;; The predicate below must be general_operand, because ashldi3 allows that
4245 (define_insn "ashldi_const"
4246 [(set (match_operand:DI 0 "general_operand" "=d")
4247 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4248 (match_operand 2 "const_int_operand" "n")))]
4249 "(INTVAL (operands[2]) == 1
4250 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4251 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4254 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4255 if (INTVAL (operands[2]) == 1)
4256 return \"add%.l %1,%1\;addx%.l %0,%0\";
4257 else if (INTVAL (operands[2]) == 8)
4258 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4259 else if (INTVAL (operands[2]) == 16)
4260 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4261 else if (INTVAL (operands[2]) == 2)
4262 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4263 else/* if (INTVAL (operands[2]) == 3)*/
4264 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4267 (define_expand "ashldi3"
4268 [(set (match_operand:DI 0 "general_operand" "")
4269 (ashift:DI (match_operand:DI 1 "general_operand" "")
4270 (match_operand 2 "const_int_operand" "")))]
4274 if (GET_CODE (operands[2]) != CONST_INT
4275 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4276 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4277 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4281 ;; On most 68k models, this makes faster code in a special case.
4283 (define_insn "ashlsi_16"
4284 [(set (match_operand:SI 0 "register_operand" "=d")
4285 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4291 return \"swap %0\;clr%.w %0\";
4294 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4295 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4297 ;; On the 68000, this makes faster code in a special case.
4299 (define_insn "ashlsi_17_24"
4300 [(set (match_operand:SI 0 "register_operand" "=d")
4301 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4302 (match_operand:SI 2 "const_int_operand" "n")))]
4303 "(! TARGET_68020 && !TARGET_5200
4304 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4309 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4310 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4313 (define_insn "ashlsi3"
4314 [(set (match_operand:SI 0 "register_operand" "=d")
4315 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4316 (match_operand:SI 2 "general_operand" "dI")))]
4320 if (operands[2] == const1_rtx)
4322 cc_status.flags = CC_NO_OVERFLOW;
4323 return \"add%.l %0,%0\";
4325 return \"lsl%.l %2,%0\";
4328 (define_insn "ashlhi3"
4329 [(set (match_operand:HI 0 "register_operand" "=d")
4330 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4331 (match_operand:HI 2 "general_operand" "dI")))]
4336 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4337 (ashift:HI (match_dup 0)
4338 (match_operand:HI 1 "general_operand" "dI")))]
4342 (define_insn "ashlqi3"
4343 [(set (match_operand:QI 0 "register_operand" "=d")
4344 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4345 (match_operand:QI 2 "general_operand" "dI")))]
4350 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4351 (ashift:QI (match_dup 0)
4352 (match_operand:QI 1 "general_operand" "dI")))]
4356 ;; On all 68k models, this makes faster code in a special case.
4358 (define_insn "ashrsi_16"
4359 [(set (match_operand:SI 0 "register_operand" "=d")
4360 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4363 "swap %0\;ext%.l %0")
4365 ;; On the 68000, this makes faster code in a special case.
4368 [(set (match_operand:SI 0 "register_operand" "=d")
4369 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4370 (match_operand:SI 2 "const_int_operand" "n")))]
4371 "(! TARGET_68020 && !TARGET_5200
4372 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4375 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4376 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4379 (define_insn "subreghi1ashrdi_const32"
4380 [(set (match_operand:HI 0 "general_operand" "=rm")
4381 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4382 (const_int 32)) 1))]
4386 if (GET_CODE (operands[1]) != REG)
4387 operands[1] = adj_offsettable_operand (operands[1], 2);
4388 return \"move%.w %1,%0\";
4391 (define_insn "subregsi1ashrdi_const32"
4392 [(set (match_operand:SI 0 "general_operand" "=rm")
4393 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4394 (const_int 32)) 1))]
4398 return \"move%.l %1,%0\";
4401 (define_insn "ashrdi_const32"
4402 [(set (match_operand:DI 0 "register_operand" "=d")
4403 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4409 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4411 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4413 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4416 (define_insn "ashrdi_const32_mem"
4417 [(set (match_operand:DI 0 "general_operand" "=o,<")
4418 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4420 (clobber (match_scratch:SI 2 "=d,d"))]
4425 if (which_alternative == 1)
4426 operands[3] = operands[0];
4428 operands[3] = adj_offsettable_operand (operands[0], 4);
4430 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4432 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4435 ;; The predicate below must be general_operand, because ashrdi3 allows that
4436 (define_insn "ashrdi_const"
4437 [(set (match_operand:DI 0 "general_operand" "=d")
4438 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4439 (match_operand 2 "const_int_operand" "n")))]
4441 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4442 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4443 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4446 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4447 if (INTVAL (operands[2]) == 63)
4448 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4450 if (INTVAL (operands[2]) == 1)
4451 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4452 else if (INTVAL (operands[2]) == 8)
4453 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4454 else if (INTVAL (operands[2]) == 16)
4455 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4456 else if (INTVAL (operands[2]) == 2)
4457 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4458 else/* if (INTVAL (operands[2]) == 3)*/
4459 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4462 (define_expand "ashrdi3"
4463 [(set (match_operand:DI 0 "general_operand" "")
4464 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4465 (match_operand 2 "const_int_operand" "")))]
4469 if (GET_CODE (operands[2]) != CONST_INT
4470 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4471 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4472 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4473 && INTVAL (operands[2]) != 63))
4477 ;; On all 68k models, this makes faster code in a special case.
4479 (define_insn "ashrsi_31"
4480 [(set (match_operand:SI 0 "register_operand" "=d")
4481 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4486 return \"add%.l %0,%0\;subx%.l %0,%0\";
4489 (define_insn "ashrsi3"
4490 [(set (match_operand:SI 0 "register_operand" "=d")
4491 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4492 (match_operand:SI 2 "general_operand" "dI")))]
4496 (define_insn "ashrhi3"
4497 [(set (match_operand:HI 0 "register_operand" "=d")
4498 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4499 (match_operand:HI 2 "general_operand" "dI")))]
4504 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4505 (ashiftrt:HI (match_dup 0)
4506 (match_operand:HI 1 "general_operand" "dI")))]
4510 (define_insn "ashrqi3"
4511 [(set (match_operand:QI 0 "register_operand" "=d")
4512 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4513 (match_operand:QI 2 "general_operand" "dI")))]
4518 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4519 (ashiftrt:QI (match_dup 0)
4520 (match_operand:QI 1 "general_operand" "dI")))]
4524 ;; logical shift instructions
4526 ;; commented out because of reload problems in 950612-1.c
4529 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4530 ;; (const_int 32)) 1))
4531 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4532 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4533 ;; (const_int 32)) 1))]
4537 ;; return \"move%.l %0,%1\";
4542 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4543 ;; (const_int 32)) 0))
4544 ;; (set (match_operand:DI 1 "general_operand" "=do")
4545 ;; (lshiftrt:DI (match_dup 0)
4546 ;; (const_int 32)))]
4550 ;; if (GET_CODE (operands[1]) == REG)
4551 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4553 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4554 ;; return \"move%.l %0,%2\;clr%.l %1\";
4557 (define_insn "subreg1lshrdi_const32"
4558 [(set (match_operand:SI 0 "general_operand" "=rm")
4559 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4560 (const_int 32)) 1))]
4564 return \"move%.l %1,%0\";
4567 (define_insn "lshrdi_const32"
4568 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4569 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4575 if (which_alternative == 1)
4576 return \"move%.l %1,%0\;clr%.l %0\";
4577 if (which_alternative == 2)
4578 return \"clr%.l %0\;move%.l %1,%0\";
4579 if (GET_CODE (operands[0]) == REG)
4580 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4582 operands[2] = adj_offsettable_operand (operands[0], 4);
4583 if (GET_CODE (operands[1]) == REG)
4584 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4586 operands[3] = adj_offsettable_operand (operands[1], 4);
4587 if (ADDRESS_REG_P (operands[0]))
4588 return \"move%.l %1,%2\;sub%.l %0,%0\";
4590 return \"move%.l %1,%2\;clr%.l %0\";
4593 ;; The predicate below must be general_operand, because lshrdi3 allows that
4594 (define_insn "lshrdi_const"
4595 [(set (match_operand:DI 0 "general_operand" "=d")
4596 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4597 (match_operand 2 "const_int_operand" "n")))]
4599 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4600 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4601 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4604 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4605 if (INTVAL (operands[2]) == 63)
4606 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4608 if (INTVAL (operands[2]) == 1)
4609 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4610 else if (INTVAL (operands[2]) == 8)
4611 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4612 else if (INTVAL (operands[2]) == 16)
4613 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4614 else if (INTVAL (operands[2]) == 2)
4615 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4616 else /*if (INTVAL (operands[2]) == 3)*/
4617 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4620 (define_expand "lshrdi3"
4621 [(set (match_operand:DI 0 "general_operand" "")
4622 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4623 (match_operand 2 "const_int_operand" "")))]
4627 if (GET_CODE (operands[2]) != CONST_INT
4628 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4629 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4630 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4631 && INTVAL (operands[2]) != 63))
4635 ;; On all 68k models, this makes faster code in a special case.
4637 (define_insn "lshrsi_31"
4638 [(set (match_operand:SI 0 "register_operand" "=d")
4639 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4644 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4647 ;; On most 68k models, this makes faster code in a special case.
4649 (define_insn "lshrsi_16"
4650 [(set (match_operand:SI 0 "register_operand" "=d")
4651 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4657 return \"clr%.w %0\;swap %0\";
4660 ;; On the 68000, this makes faster code in a special case.
4662 (define_insn "lshrsi_17_24"
4663 [(set (match_operand:SI 0 "register_operand" "=d")
4664 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4665 (match_operand:SI 2 "const_int_operand" "n")))]
4666 "(! TARGET_68020 && !TARGET_5200
4667 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4670 /* I think lsr%.w sets the CC properly. */
4671 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4672 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4675 (define_insn "lshrsi3"
4676 [(set (match_operand:SI 0 "register_operand" "=d")
4677 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4678 (match_operand:SI 2 "general_operand" "dI")))]
4682 (define_insn "lshrhi3"
4683 [(set (match_operand:HI 0 "register_operand" "=d")
4684 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4685 (match_operand:HI 2 "general_operand" "dI")))]
4690 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4691 (lshiftrt:HI (match_dup 0)
4692 (match_operand:HI 1 "general_operand" "dI")))]
4696 (define_insn "lshrqi3"
4697 [(set (match_operand:QI 0 "register_operand" "=d")
4698 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4699 (match_operand:QI 2 "general_operand" "dI")))]
4704 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4705 (lshiftrt:QI (match_dup 0)
4706 (match_operand:QI 1 "general_operand" "dI")))]
4710 ;; rotate instructions
4712 (define_insn "rotlsi3"
4713 [(set (match_operand:SI 0 "register_operand" "=d")
4714 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4715 (match_operand:SI 2 "general_operand" "dI")))]
4719 (define_insn "rotlhi3"
4720 [(set (match_operand:HI 0 "register_operand" "=d")
4721 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4722 (match_operand:HI 2 "general_operand" "dI")))]
4728 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4729 (rotate:HI (match_dup 0)
4730 (match_operand:HI 1 "general_operand" "dI")))]
4734 (define_insn "rotlqi3"
4735 [(set (match_operand:QI 0 "register_operand" "=d")
4736 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4737 (match_operand:QI 2 "general_operand" "dI")))]
4742 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4743 (rotate:QI (match_dup 0)
4744 (match_operand:QI 1 "general_operand" "dI")))]
4748 (define_insn "rotrsi3"
4749 [(set (match_operand:SI 0 "register_operand" "=d")
4750 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
4751 (match_operand:SI 2 "general_operand" "dI")))]
4755 (define_insn "rotrhi3"
4756 [(set (match_operand:HI 0 "register_operand" "=d")
4757 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
4758 (match_operand:HI 2 "general_operand" "dI")))]
4763 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4764 (rotatert:HI (match_dup 0)
4765 (match_operand:HI 1 "general_operand" "dI")))]
4769 (define_insn "rotrqi3"
4770 [(set (match_operand:QI 0 "register_operand" "=d")
4771 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
4772 (match_operand:QI 2 "general_operand" "dI")))]
4777 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4778 (rotatert:QI (match_dup 0)
4779 (match_operand:QI 1 "general_operand" "dI")))]
4784 ;; Bit set/clear in memory byte.
4786 ;; set bit, bit number is int
4787 (define_insn "bsetmemqi"
4788 [(set (match_operand:QI 0 "memory_operand" "+m")
4789 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4790 (match_operand:SI 1 "general_operand" "d")) 0)
4796 return \"bset %1,%0\";
4799 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
4801 [(set (match_operand:QI 0 "memory_operand" "+m")
4802 (ior:QI (subreg:QI (ashift:SI (const_int 1)
4803 (match_operator:SI 2 "extend_operator"
4804 [(match_operand 1 "general_operand" "d")])) 0)
4810 return \"bset %1,%0\";
4813 ;; clear bit, bit number is int
4814 (define_insn "bclrmemqi"
4815 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4817 (minus:SI (const_int 7)
4818 (match_operand:SI 1 "general_operand" "d")))
4824 return \"bclr %1,%0\";
4827 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
4829 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
4831 (minus:SI (const_int 7)
4832 (match_operator:SI 2 "extend_operator"
4833 [(match_operand 1 "general_operand" "d")])))
4839 return \"bclr %1,%0\";
4842 ;; Special cases of bit-field insns which we should
4843 ;; recognize in preference to the general case.
4844 ;; These handle aligned 8-bit and 16-bit fields,
4845 ;; which can usually be done with move instructions.
4848 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4849 ; alignment of structure members is specified.
4851 ; The move is allowed to be odd byte aligned, because that's still faster
4852 ; than an odd byte aligned bit field instruction.
4855 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
4857 (match_operand:SI 2 "const_int_operand" "n"))
4858 (match_operand:SI 3 "general_operand" "rmi"))]
4859 "TARGET_68020 && TARGET_BITFIELD
4860 && (INTVAL (operands[2]) % 8) == 0
4861 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
4865 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4867 return \"move%.l %3,%0\";
4871 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
4872 (match_operand:SI 1 "const_int_operand" "n")
4873 (match_operand:SI 2 "const_int_operand" "n"))
4874 (match_operand:SI 3 "register_operand" "d"))]
4875 "TARGET_68020 && TARGET_BITFIELD
4876 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
4877 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
4878 && (GET_CODE (operands[0]) == REG
4879 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
4882 if (REG_P (operands[0]))
4884 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
4885 return \"bfins %3,%0{%b2:%b1}\";
4889 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
4891 if (GET_CODE (operands[3]) == MEM)
4892 operands[3] = adj_offsettable_operand (operands[3],
4893 (32 - INTVAL (operands[1])) / 8);
4894 if (INTVAL (operands[1]) == 8)
4895 return \"move%.b %3,%0\";
4896 return \"move%.w %3,%0\";
4901 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4902 ; alignment of structure members is specified.
4904 ; The move is allowed to be odd byte aligned, because that's still faster
4905 ; than an odd byte aligned bit field instruction.
4908 [(set (match_operand:SI 0 "general_operand" "=rm")
4909 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
4911 (match_operand:SI 3 "const_int_operand" "n")))]
4912 "TARGET_68020 && TARGET_BITFIELD
4913 && (INTVAL (operands[3]) % 8) == 0
4914 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4918 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4920 return \"move%.l %1,%0\";
4924 [(set (match_operand:SI 0 "general_operand" "=&d")
4925 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
4926 (match_operand:SI 2 "const_int_operand" "n")
4927 (match_operand:SI 3 "const_int_operand" "n")))]
4928 "TARGET_68020 && TARGET_BITFIELD
4929 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4930 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4931 && (GET_CODE (operands[1]) == REG
4932 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4935 cc_status.flags |= CC_NOT_NEGATIVE;
4936 if (REG_P (operands[1]))
4938 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4939 return \"bfextu %1{%b3:%b2},%0\";
4943 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4945 output_asm_insn (\"clr%.l %0\", operands);
4946 if (GET_CODE (operands[0]) == MEM)
4947 operands[0] = adj_offsettable_operand (operands[0],
4948 (32 - INTVAL (operands[1])) / 8);
4949 if (INTVAL (operands[2]) == 8)
4950 return \"move%.b %1,%0\";
4951 return \"move%.w %1,%0\";
4955 ; Special case for 32-bit field in memory. This only occurs when 32-bit
4956 ; alignment of structure members is specified.
4958 ; The move is allowed to be odd byte aligned, because that's still faster
4959 ; than an odd byte aligned bit field instruction.
4962 [(set (match_operand:SI 0 "general_operand" "=rm")
4963 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
4965 (match_operand:SI 3 "const_int_operand" "n")))]
4966 "TARGET_68020 && TARGET_BITFIELD
4967 && (INTVAL (operands[3]) % 8) == 0
4968 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
4972 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4974 return \"move%.l %1,%0\";
4978 [(set (match_operand:SI 0 "general_operand" "=d")
4979 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
4980 (match_operand:SI 2 "const_int_operand" "n")
4981 (match_operand:SI 3 "const_int_operand" "n")))]
4982 "TARGET_68020 && TARGET_BITFIELD
4983 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
4984 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
4985 && (GET_CODE (operands[1]) == REG
4986 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
4989 if (REG_P (operands[1]))
4991 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
4992 return \"bfexts %1{%b3:%b2},%0\";
4996 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
4998 if (INTVAL (operands[2]) == 8)
4999 return \"move%.b %1,%0\;extb%.l %0\";
5000 return \"move%.w %1,%0\;ext%.l %0\";
5003 ;; Bit field instructions, general cases.
5004 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5005 ;; so that its address is reloaded.
5007 (define_expand "extv"
5008 [(set (match_operand:SI 0 "general_operand" "")
5009 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5010 (match_operand:SI 2 "general_operand" "")
5011 (match_operand:SI 3 "general_operand" "")))]
5012 "TARGET_68020 && TARGET_BITFIELD"
5016 [(set (match_operand:SI 0 "general_operand" "=d")
5017 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5018 (match_operand:SI 2 "general_operand" "di")
5019 (match_operand:SI 3 "general_operand" "di")))]
5020 "TARGET_68020 && TARGET_BITFIELD"
5021 "bfexts %1{%b3:%b2},%0")
5023 (define_expand "extzv"
5024 [(set (match_operand:SI 0 "general_operand" "")
5025 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5026 (match_operand:SI 2 "general_operand" "")
5027 (match_operand:SI 3 "general_operand" "")))]
5028 "TARGET_68020 && TARGET_BITFIELD"
5032 [(set (match_operand:SI 0 "general_operand" "=d,d")
5033 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5034 (match_operand:SI 2 "general_operand" "di,di")
5035 (match_operand:SI 3 "general_operand" "di,di")))]
5036 "TARGET_68020 && TARGET_BITFIELD"
5039 if (GET_CODE (operands[2]) == CONST_INT)
5041 if (INTVAL (operands[2]) != 32)
5042 cc_status.flags |= CC_NOT_NEGATIVE;
5048 return \"bfextu %1{%b3:%b2},%0\";
5052 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5053 (match_operand:SI 1 "general_operand" "di")
5054 (match_operand:SI 2 "general_operand" "di"))
5055 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5056 (match_operand 3 "const_int_operand" "n")))]
5057 "TARGET_68020 && TARGET_BITFIELD
5058 && (INTVAL (operands[3]) == -1
5059 || (GET_CODE (operands[1]) == CONST_INT
5060 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5064 return \"bfchg %0{%b2:%b1}\";
5068 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5069 (match_operand:SI 1 "general_operand" "di")
5070 (match_operand:SI 2 "general_operand" "di"))
5072 "TARGET_68020 && TARGET_BITFIELD"
5076 return \"bfclr %0{%b2:%b1}\";
5080 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5081 (match_operand:SI 1 "general_operand" "di")
5082 (match_operand:SI 2 "general_operand" "di"))
5084 "TARGET_68020 && TARGET_BITFIELD"
5088 return \"bfset %0{%b2:%b1}\";
5091 (define_expand "insv"
5092 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5093 (match_operand:SI 1 "general_operand" "")
5094 (match_operand:SI 2 "general_operand" ""))
5095 (match_operand:SI 3 "register_operand" ""))]
5096 "TARGET_68020 && TARGET_BITFIELD"
5100 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5101 (match_operand:SI 1 "general_operand" "di")
5102 (match_operand:SI 2 "general_operand" "di"))
5103 (match_operand:SI 3 "register_operand" "d"))]
5104 "TARGET_68020 && TARGET_BITFIELD"
5105 "bfins %3,%0{%b2:%b1}")
5107 ;; Now recognize bit field insns that operate on registers
5108 ;; (or at least were intended to do so).
5111 [(set (match_operand:SI 0 "general_operand" "=d")
5112 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5113 (match_operand:SI 2 "general_operand" "di")
5114 (match_operand:SI 3 "general_operand" "di")))]
5115 "TARGET_68020 && TARGET_BITFIELD"
5116 "bfexts %1{%b3:%b2},%0")
5119 [(set (match_operand:SI 0 "general_operand" "=d")
5120 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5121 (match_operand:SI 2 "general_operand" "di")
5122 (match_operand:SI 3 "general_operand" "di")))]
5123 "TARGET_68020 && TARGET_BITFIELD"
5126 if (GET_CODE (operands[2]) == CONST_INT)
5128 if (INTVAL (operands[2]) != 32)
5129 cc_status.flags |= CC_NOT_NEGATIVE;
5135 return \"bfextu %1{%b3:%b2},%0\";
5139 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5140 (match_operand:SI 1 "general_operand" "di")
5141 (match_operand:SI 2 "general_operand" "di"))
5143 "TARGET_68020 && TARGET_BITFIELD"
5147 return \"bfclr %0{%b2:%b1}\";
5151 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5152 (match_operand:SI 1 "general_operand" "di")
5153 (match_operand:SI 2 "general_operand" "di"))
5155 "TARGET_68020 && TARGET_BITFIELD"
5159 return \"bfset %0{%b2:%b1}\";
5163 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5164 (match_operand:SI 1 "general_operand" "di")
5165 (match_operand:SI 2 "general_operand" "di"))
5166 (match_operand:SI 3 "register_operand" "d"))]
5167 "TARGET_68020 && TARGET_BITFIELD"
5171 /* These special cases are now recognized by a specific pattern. */
5172 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5173 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5174 return \"move%.w %3,%0\";
5175 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5176 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5177 return \"move%.b %3,%0\";
5179 return \"bfins %3,%0{%b2:%b1}\";
5182 ;; Special patterns for optimizing bit-field instructions.
5186 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5187 (match_operand:SI 1 "const_int_operand" "n")
5188 (match_operand:SI 2 "general_operand" "di")))]
5189 "TARGET_68020 && TARGET_BITFIELD"
5192 if (operands[1] == const1_rtx
5193 && GET_CODE (operands[2]) == CONST_INT)
5195 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5196 return output_btst (operands,
5197 gen_rtx (CONST_INT, VOIDmode,
5198 width - INTVAL (operands[2])),
5201 /* Pass 1000 as SIGNPOS argument so that btst will
5202 not think we are testing the sign bit for an `and'
5203 and assume that nonzero implies a negative result. */
5205 if (INTVAL (operands[1]) != 32)
5206 cc_status.flags = CC_NOT_NEGATIVE;
5207 return \"bftst %0{%b2:%b1}\";
5211 ;;; now handle the register cases
5214 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5215 (match_operand:SI 1 "const_int_operand" "n")
5216 (match_operand:SI 2 "general_operand" "di")))]
5217 "TARGET_68020 && TARGET_BITFIELD"
5220 if (operands[1] == const1_rtx
5221 && GET_CODE (operands[2]) == CONST_INT)
5223 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5224 return output_btst (operands,
5225 gen_rtx (CONST_INT, VOIDmode,
5226 width - INTVAL (operands[2])),
5229 /* Pass 1000 as SIGNPOS argument so that btst will
5230 not think we are testing the sign bit for an `and'
5231 and assume that nonzero implies a negative result. */
5233 if (INTVAL (operands[1]) != 32)
5234 cc_status.flags = CC_NOT_NEGATIVE;
5235 return \"bftst %0{%b2:%b1}\";
5238 (define_insn "scc0_di"
5239 [(set (match_operand:QI 0 "general_operand" "=dm")
5240 (match_operator 1 "valid_dbcc_comparison_p"
5241 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5245 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5248 (define_insn "scc_di"
5249 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5250 (match_operator 1 "valid_dbcc_comparison_p"
5251 [(match_operand:DI 2 "general_operand" "ro,r")
5252 (match_operand:DI 3 "general_operand" "r,ro")]))]
5256 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5260 [(set (match_operand:QI 0 "general_operand" "=dm")
5261 (eq:QI (cc0) (const_int 0)))]
5264 cc_status = cc_prev_status;
5265 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5269 [(set (match_operand:QI 0 "general_operand" "=dm")
5270 (ne:QI (cc0) (const_int 0)))]
5273 cc_status = cc_prev_status;
5274 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5278 [(set (match_operand:QI 0 "general_operand" "=dm")
5279 (gt:QI (cc0) (const_int 0)))]
5282 cc_status = cc_prev_status;
5283 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5287 [(set (match_operand:QI 0 "general_operand" "=dm")
5288 (gtu:QI (cc0) (const_int 0)))]
5290 "* cc_status = cc_prev_status;
5291 return \"shi %0\"; ")
5294 [(set (match_operand:QI 0 "general_operand" "=dm")
5295 (lt:QI (cc0) (const_int 0)))]
5297 "* cc_status = cc_prev_status;
5298 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5301 [(set (match_operand:QI 0 "general_operand" "=dm")
5302 (ltu:QI (cc0) (const_int 0)))]
5304 "* cc_status = cc_prev_status;
5305 return \"scs %0\"; ")
5308 [(set (match_operand:QI 0 "general_operand" "=dm")
5309 (ge:QI (cc0) (const_int 0)))]
5311 "* cc_status = cc_prev_status;
5312 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5315 [(set (match_operand:QI 0 "general_operand" "=dm")
5316 (geu:QI (cc0) (const_int 0)))]
5318 "* cc_status = cc_prev_status;
5319 return \"scc %0\"; ")
5322 [(set (match_operand:QI 0 "general_operand" "=dm")
5323 (le:QI (cc0) (const_int 0)))]
5326 cc_status = cc_prev_status;
5327 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5331 [(set (match_operand:QI 0 "general_operand" "=dm")
5332 (leu:QI (cc0) (const_int 0)))]
5334 "* cc_status = cc_prev_status;
5335 return \"sls %0\"; ")
5337 ;; Basic conditional jump instructions.
5339 (define_insn "beq0_di"
5341 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5343 (label_ref (match_operand 1 "" ","))
5345 (clobber (match_scratch:SI 2 "=d,d"))]
5350 if (which_alternative == 1)
5352 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5354 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5356 if ((cc_prev_status.value1
5357 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5358 || (cc_prev_status.value2
5359 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5361 cc_status = cc_prev_status;
5363 return \"jbeq %l1\";
5368 if (GET_CODE (operands[0]) == REG)
5369 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5371 operands[3] = adj_offsettable_operand (operands[0], 4);
5372 if (! ADDRESS_REG_P (operands[0]))
5374 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5376 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5378 operands[4] = gen_label_rtx();
5380 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5382 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5384 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5385 CODE_LABEL_NUMBER (operands[4]));
5389 (define_insn "bne0_di"
5391 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5393 (label_ref (match_operand 1 "" ","))
5395 (clobber (match_scratch:SI 2 "=d,X"))]
5399 if ((cc_prev_status.value1
5400 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5401 || (cc_prev_status.value2
5402 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5404 cc_status = cc_prev_status;
5406 return \"jbne %l1\";
5412 if (GET_CODE (operands[0]) == REG)
5413 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5415 operands[3] = adj_offsettable_operand (operands[0], 4);
5416 if (ADDRESS_REG_P (operands[0]))
5418 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5420 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5424 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5426 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5430 (define_insn "bge0_di"
5432 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5434 (label_ref (match_operand 1 "" ""))
5439 if ((cc_prev_status.value1
5440 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5441 || (cc_prev_status.value2
5442 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5444 cc_status = cc_prev_status;
5445 if (cc_status.flags & CC_REVERSED)
5448 return \"jble %l1\";
5456 return \"jbpl %l1\";
5464 return \"tst%.l %0\;jbpl %l1\";
5466 return \"tst%.l %0\;jpl %l1\";
5470 (define_insn "blt0_di"
5472 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5474 (label_ref (match_operand 1 "" ""))
5479 if ((cc_prev_status.value1
5480 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5481 || (cc_prev_status.value2
5482 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5484 cc_status = cc_prev_status;
5485 if (cc_status.flags & CC_REVERSED)
5488 return \"jbgt %l1\";
5496 return \"jbmi %l1\";
5504 return \"tst%.l %0\;jbmi %l1\";
5506 return \"tst%.l %0\;jmi %l1\";
5512 (if_then_else (eq (cc0)
5514 (label_ref (match_operand 0 "" ""))
5520 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5522 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5528 (if_then_else (ne (cc0)
5530 (label_ref (match_operand 0 "" ""))
5536 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5538 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5544 (if_then_else (gt (cc0)
5546 (label_ref (match_operand 0 "" ""))
5551 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
5553 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
5559 (if_then_else (gtu (cc0)
5561 (label_ref (match_operand 0 "" ""))
5566 return \"jbhi %l0\";
5574 (if_then_else (lt (cc0)
5576 (label_ref (match_operand 0 "" ""))
5581 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
5583 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
5589 (if_then_else (ltu (cc0)
5591 (label_ref (match_operand 0 "" ""))
5596 return \"jbcs %l0\";
5604 (if_then_else (ge (cc0)
5606 (label_ref (match_operand 0 "" ""))
5611 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
5613 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
5619 (if_then_else (geu (cc0)
5621 (label_ref (match_operand 0 "" ""))
5626 return \"jbcc %l0\";
5634 (if_then_else (le (cc0)
5636 (label_ref (match_operand 0 "" ""))
5641 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
5643 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
5649 (if_then_else (leu (cc0)
5651 (label_ref (match_operand 0 "" ""))
5656 return \"jbls %l0\";
5662 ;; Negated conditional jump instructions.
5666 (if_then_else (eq (cc0)
5669 (label_ref (match_operand 0 "" ""))))]
5674 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
5676 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
5682 (if_then_else (ne (cc0)
5685 (label_ref (match_operand 0 "" ""))))]
5690 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
5692 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
5698 (if_then_else (gt (cc0)
5701 (label_ref (match_operand 0 "" ""))))]
5705 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
5707 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
5713 (if_then_else (gtu (cc0)
5716 (label_ref (match_operand 0 "" ""))))]
5720 return \"jbls %l0\";
5728 (if_then_else (lt (cc0)
5731 (label_ref (match_operand 0 "" ""))))]
5735 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
5737 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
5743 (if_then_else (ltu (cc0)
5746 (label_ref (match_operand 0 "" ""))))]
5750 return \"jbcc %l0\";
5758 (if_then_else (ge (cc0)
5761 (label_ref (match_operand 0 "" ""))))]
5765 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
5767 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
5773 (if_then_else (geu (cc0)
5776 (label_ref (match_operand 0 "" ""))))]
5780 return \"jbcs %l0\";
5788 (if_then_else (le (cc0)
5791 (label_ref (match_operand 0 "" ""))))]
5795 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
5797 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
5803 (if_then_else (leu (cc0)
5806 (label_ref (match_operand 0 "" ""))))]
5810 return \"jbhi %l0\";
5816 ;; Unconditional and other jump instructions
5819 (label_ref (match_operand 0 "" "")))]
5823 return \"jbra %l0\";
5829 ;; We support two different ways of handling dispatch tables.
5830 ;; The NeXT uses absolute tables, and other machines use relative.
5831 ;; This define_expand can generate either kind.
5832 (define_expand "tablejump"
5833 [(parallel [(set (pc) (match_operand 0 "" ""))
5834 (use (label_ref (match_operand 1 "" "")))])]
5838 #ifdef CASE_VECTOR_PC_RELATIVE
5839 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
5840 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
5844 ;; Jump to variable address from dispatch table of absolute addresses.
5846 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5847 (use (label_ref (match_operand 1 "" "")))]
5851 return \"jmp (%0)\";
5857 ;; Jump to variable address from dispatch table of relative addresses.
5861 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
5862 (use (label_ref (match_operand 1 "" "")))]
5865 #ifdef ASM_RETURN_CASE_JUMP
5866 ASM_RETURN_CASE_JUMP;
5869 #ifdef ASM_OUTPUT_CASE_LABEL
5870 return \"jmp 6(%%pc,%0.w)\";
5873 return \"jmp 2(pc,%0.w)\";
5875 return \"jmp 2(%%pc,%0.w)\";
5876 #endif /* end !CRDS */
5880 return \"jmp (2,pc,%0.w)\";
5882 return \"jmp pc@(2,%0:w)\";
5888 ;; Decrement-and-branch insns.
5892 (ne (match_operand:HI 0 "general_operand" "+d*g")
5894 (label_ref (match_operand 1 "" ""))
5897 (plus:HI (match_dup 0)
5903 if (DATA_REG_P (operands[0]))
5904 return \"dbra %0,%l1\";
5905 if (GET_CODE (operands[0]) == MEM)
5909 return \"sub%.w %#1,%0\;jbcc %l1\";
5911 return \"subq%.w %#1,%0\;jbcc %l1\";
5913 #else /* not MOTOROLA */
5914 return \"subqw %#1,%0\;jcc %l1\";
5918 #ifdef SGS_CMP_ORDER
5920 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5922 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
5924 #else /* not SGS_CMP_ORDER */
5925 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
5927 #else /* not MOTOROLA */
5928 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
5935 (ne (match_operand:SI 0 "general_operand" "+d*g")
5937 (label_ref (match_operand 1 "" ""))
5940 (plus:SI (match_dup 0)
5948 if (DATA_REG_P (operands[0]))
5949 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
5950 if (GET_CODE (operands[0]) == MEM)
5951 return \"sub%.l %#1,%0\;jbcc %l1\";
5953 if (DATA_REG_P (operands[0]))
5954 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
5955 if (GET_CODE (operands[0]) == MEM)
5956 return \"subq%.l %#1,%0\;jbcc %l1\";
5957 #endif /* NO_ADDSUB_Q */
5958 #ifdef SGS_CMP_ORDER
5960 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5962 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
5964 #else /* not SGS_CMP_ORDER */
5965 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
5966 #endif /* not SGS_CMP_ORDER */
5967 #else /* not MOTOROLA */
5968 if (DATA_REG_P (operands[0]))
5969 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
5970 if (GET_CODE (operands[0]) == MEM)
5971 return \"subql %#1,%0\;jcc %l1\";
5972 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
5973 #endif /* not MOTOROLA */
5976 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
5981 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
5984 (label_ref (match_operand 1 "" ""))
5987 (plus:HI (match_dup 0)
5989 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
5995 if (DATA_REG_P (operands[0]))
5996 return \"dbra %0,%l1\";
5997 if (GET_CODE (operands[0]) == MEM)
5998 return \"sub%.w %#1,%0\;jbcc %l1\";
6000 if (DATA_REG_P (operands[0]))
6001 return \"dbra %0,%l1\";
6002 if (GET_CODE (operands[0]) == MEM)
6003 return \"subq%.w %#1,%0\;jbcc %l1\";
6005 #ifdef SGS_CMP_ORDER
6007 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6009 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6011 #else /* not SGS_CMP_ORDER */
6012 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6013 #endif /* not SGS_CMP_ORDER */
6014 #else /* not MOTOROLA */
6015 if (DATA_REG_P (operands[0]))
6016 return \"dbra %0,%l1\";
6017 if (GET_CODE (operands[0]) == MEM)
6018 return \"subqw %#1,%0\;jcc %l1\";
6019 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6020 #endif /* not MOTOROLA */
6023 (define_expand "decrement_and_branch_until_zero"
6024 [(parallel [(set (pc)
6026 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6029 (label_ref (match_operand 1 "" ""))
6032 (plus:SI (match_dup 0)
6040 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6043 (label_ref (match_operand 1 "" ""))
6046 (plus:SI (match_dup 0)
6048 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6054 if (DATA_REG_P (operands[0]))
6055 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6056 if (GET_CODE (operands[0]) == MEM)
6057 return \"sub%.l %#1,%0\;jbcc %l1\";
6059 if (DATA_REG_P (operands[0]))
6060 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6061 if (GET_CODE (operands[0]) == MEM)
6062 return \"subq%.l %#1,%0\;jbcc %l1\";
6064 #ifdef SGS_CMP_ORDER
6066 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6068 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6070 #else /* not SGS_CMP_ORDER */
6071 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6072 #endif /* not SGS_CMP_ORDER */
6073 #else /* not MOTOROLA */
6074 if (DATA_REG_P (operands[0]))
6075 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6076 if (GET_CODE (operands[0]) == MEM)
6077 return \"subql %#1,%0\;jcc %l1\";
6078 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6079 #endif /* not MOTOROLA */
6083 ;; For PIC calls, in order to be able to support
6084 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6085 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6087 ;; PIC calls are handled by loading the address of the function into a
6088 ;; register (via movsi), then emitting a register indirect call using
6089 ;; the "jsr" function call syntax.
6091 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6092 ;; operand to the jbsr statement to indicate that this call should
6093 ;; go through the PLT (why? because this is the way that Sun does it).
6095 ;; We have different patterns for PIC calls and non-PIC calls. The
6096 ;; different patterns are only used to choose the right syntax.
6098 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6099 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6100 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6101 ;; section at link time. However, all global objects reference are still
6102 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6103 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6104 ;; We need to have a way to differentiate these two different operands.
6106 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6107 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6108 ;; to be changed to recognize function calls symbol_ref operand as a valid
6109 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6110 ;; avoid the compiler to load this symbol_ref operand into a register.
6111 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6112 ;; since the value is a PC relative offset, not a real address.
6114 ;; All global objects are treated in the similar way as in SUN3. The only
6115 ;; difference is: on m68k svr4, the reference of such global object needs
6116 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6117 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6120 ;; Call subroutine with no return value.
6121 (define_expand "call"
6122 [(call (match_operand:QI 0 "memory_operand" "")
6123 (match_operand:SI 1 "general_operand" ""))]
6124 ;; Operand 1 not really used on the m68000.
6129 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6130 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6133 ;; This is a normal call sequence.
6135 [(call (match_operand:QI 0 "memory_operand" "o")
6136 (match_operand:SI 1 "general_operand" "g"))]
6137 ;; Operand 1 not really used on the m68000.
6141 #if defined (MOTOROLA) && !defined (USE_GAS)
6143 if (GET_CODE (operands[0]) == MEM
6144 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6153 ;; This is a PIC call sequence.
6155 [(call (match_operand:QI 0 "memory_operand" "o")
6156 (match_operand:SI 1 "general_operand" "g"))]
6157 ;; Operand 1 not really used on the m68000.
6161 if (GET_CODE (operands[0]) == MEM
6162 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6165 return \"bsr.l %0\";
6168 return \"bsr.l %0@PLTPC\";
6170 return \"bsr %0@PLTPC\";
6174 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6175 GAS just plain ignores it. */
6176 return \"jbsr %0,a1\";
6181 ;; Call subroutine, returning value in operand 0
6182 ;; (which must be a hard register).
6183 ;; See comments before "call" regarding PIC calls.
6184 (define_expand "call_value"
6185 [(set (match_operand 0 "" "")
6186 (call (match_operand:QI 1 "memory_operand" "")
6187 (match_operand:SI 2 "general_operand" "")))]
6188 ;; Operand 2 not really used on the m68000.
6192 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6193 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6196 ;; This is a normal call_value
6198 [(set (match_operand 0 "" "=rf")
6199 (call (match_operand:QI 1 "memory_operand" "o")
6200 (match_operand:SI 2 "general_operand" "g")))]
6201 ;; Operand 2 not really used on the m68000.
6204 #if defined (MOTOROLA) && !defined (USE_GAS)
6206 if (GET_CODE (operands[1]) == MEM
6207 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6216 ;; This is a PIC call_value
6218 [(set (match_operand 0 "" "=rf")
6219 (call (match_operand:QI 1 "memory_operand" "o")
6220 (match_operand:SI 2 "general_operand" "g")))]
6221 ;; Operand 2 not really used on the m68000.
6224 if (GET_CODE (operands[1]) == MEM
6225 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6228 return \"bsr.l %1\";
6231 return \"bsr.l %1@PLTPC\";
6233 return \"bsr %1@PLTPC\";
6237 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6238 GAS just plain ignores it. */
6239 return \"jbsr %1,a1\";
6244 ;; Call subroutine returning any type.
6246 (define_expand "untyped_call"
6247 [(parallel [(call (match_operand 0 "" "")
6249 (match_operand 1 "" "")
6250 (match_operand 2 "" "")])]
6251 "NEEDS_UNTYPED_CALL"
6256 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6258 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6260 rtx set = XVECEXP (operands[2], 0, i);
6261 emit_move_insn (SET_DEST (set), SET_SRC (set));
6264 /* The optimizer does not know that the call sets the function value
6265 registers we stored in the result block. We avoid problems by
6266 claiming that all hard registers are used and clobbered at this
6268 emit_insn (gen_blockage ());
6273 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6274 ;; all of memory. This blocks insns from being moved across this point.
6276 (define_insn "blockage"
6277 [(unspec_volatile [(const_int 0)] 0)]
6286 (define_insn "probe"
6291 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6292 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6293 return \"tstl %a0\";
6296 ;; Used for frameless functions which save no regs and allocate no locals.
6297 (define_insn "return"
6302 if (current_function_pops_args == 0)
6304 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6308 (define_insn "indirect_jump"
6309 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6313 ;; This should not be used unless the add/sub insns can't be.
6316 [(set (match_operand:SI 0 "general_operand" "=a")
6317 (match_operand:QI 1 "address_operand" "p"))]
6322 /* Recognize an insn that refers to a table of offsets. Such an insn will
6323 need to refer to a label on the insn. So output one. Use the
6324 label-number of the table of offsets to generate this label. This code,
6325 and similar code above, assumes that there will be at most one reference
6327 if (GET_CODE (operands[1]) == PLUS
6328 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6329 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6331 rtx labelref = XEXP (operands[1], 1);
6332 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6334 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6335 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6337 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6338 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6339 #endif /* not SGS */
6340 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6341 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6342 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6343 #ifdef SGS_SWITCH_TABLES
6344 /* Set flag saying we need to define the symbol
6345 LD%n (with value L%n-LI%n) at the end of the switch table. */
6346 switch_table_difference_label_flag = 1;
6347 #endif /* SGS_SWITCH_TABLES */
6348 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6350 #endif /* SGS_NO_LI */
6352 return \"lea %a1,%0\";
6355 ;; This is the first machine-dependent peephole optimization.
6356 ;; It is useful when a floating value is returned from a function call
6357 ;; and then is moved into an FP register.
6358 ;; But it is mainly intended to test the support for these optimizations.
6361 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6362 (set (match_operand:DF 0 "register_operand" "=f")
6363 (match_operand:DF 1 "register_operand" "ad"))]
6364 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6368 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6369 output_asm_insn (\"move%.l %1,%@\", xoperands);
6370 output_asm_insn (\"move%.l %1,%-\", operands);
6371 return \"fmove%.d %+,%0\";
6375 ;; Optimize a stack-adjust followed by a push of an argument.
6376 ;; This is said to happen frequently with -msoft-float
6377 ;; when there are consecutive library calls.
6380 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6381 (match_operand:SI 0 "const_int_operand" "n")))
6382 (set (match_operand:SF 1 "push_operand" "=m")
6383 (match_operand:SF 2 "general_operand" "rmfF"))]
6384 "INTVAL (operands[0]) >= 4
6385 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6388 if (INTVAL (operands[0]) > 4)
6391 xoperands[0] = stack_pointer_rtx;
6392 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6394 if (INTVAL (xoperands[1]) <= 8)
6397 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6399 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6401 else if (INTVAL (xoperands[1]) <= 16
6402 && TARGET_68020 && !TARGET_68040 && !TARGET_68060)
6404 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6405 INTVAL (xoperands[1]) - 8);
6406 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6410 if (INTVAL (xoperands[1]) <= 0x7FFF && !TARGET_5200)
6411 output_asm_insn (\"add%.w %1,%0\", xoperands);
6413 output_asm_insn (\"add%.l %1,%0\", xoperands);
6415 if (FP_REG_P (operands[2]))
6416 return \"fmove%.s %2,%@\";
6417 return \"move%.l %2,%@\";
6420 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6423 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6424 (match_operand:SI 0 "const_int_operand" "n")))
6425 (set (match_operand:SI 1 "push_operand" "=m")
6426 (match_operand:SI 2 "general_operand" "g"))]
6427 "INTVAL (operands[0]) >= 4
6428 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6431 if (INTVAL (operands[0]) > 4)
6434 xoperands[0] = stack_pointer_rtx;
6435 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6437 if (INTVAL (xoperands[1]) <= 8)
6440 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6442 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6444 else if (INTVAL (xoperands[1]) <= 16
6445 && TARGET_68020 && !TARGET_68040 && !TARGET_68060)
6447 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6448 INTVAL (xoperands[1]) - 8);
6449 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6453 if (INTVAL (xoperands[1]) <= 0x7FFF && !TARGET_5200)
6454 output_asm_insn (\"add%.w %1,%0\", xoperands);
6456 output_asm_insn (\"add%.l %1,%0\", xoperands);
6458 if (operands[2] == const0_rtx)
6459 return \"clr%.l %@\";
6460 return \"move%.l %2,%@\";
6463 ;; Speed up pushing a single byte but leaving four bytes of space.
6466 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
6467 (match_operand:QI 1 "general_operand" "dami"))
6468 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
6469 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
6474 if (GET_CODE (operands[1]) == REG)
6475 return \"move%.l %1,%-\";
6477 xoperands[1] = operands[1];
6479 = gen_rtx (MEM, QImode,
6480 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
6481 gen_rtx (CONST_INT, VOIDmode, 3)));
6482 xoperands[3] = stack_pointer_rtx;
6484 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
6486 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
6491 [(set (match_operand:SI 0 "register_operand" "=d")
6493 (set (strict_low_part (subreg:HI (match_dup 0) 0))
6494 (match_operand:HI 1 "general_operand" "rmn"))]
6495 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
6498 if (GET_CODE (operands[1]) == CONST_INT)
6500 if (operands[1] == const0_rtx
6501 && (DATA_REG_P (operands[0])
6502 || GET_CODE (operands[0]) == MEM)
6503 /* clr insns on 68000 read before writing.
6504 This isn't so on the 68010, but we have no TARGET_68010. */
6505 && ((TARGET_68020 || TARGET_5200)
6506 || !(GET_CODE (operands[0]) == MEM
6507 && MEM_VOLATILE_P (operands[0]))))
6508 return \"clr%.w %0\";
6510 return \"move%.w %1,%0\";
6518 ;; jCC label ; abnormal loop termination
6519 ;; dbra dN, loop ; normal loop termination
6527 ;; Which moves the jCC condition outside the inner loop for free.
6530 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6531 [(cc0) (const_int 0)])
6532 (label_ref (match_operand 2 "" ""))
6537 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
6540 (label_ref (match_operand 1 "" ""))
6543 (plus:HI (match_dup 0)
6545 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6549 output_dbcc_and_branch (operands);
6554 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
6555 [(cc0) (const_int 0)])
6556 (label_ref (match_operand 2 "" ""))
6561 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
6564 (label_ref (match_operand 1 "" ""))
6567 (plus:SI (match_dup 0)
6569 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
6573 output_dbcc_and_branch (operands);
6578 ;; FPA multiply and add.
6580 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6581 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
6582 (match_operand:DF 2 "general_operand" "xH,y,y"))
6583 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
6586 fpma%.d %1,%w2,%w3,%0
6587 fpma%.d %x1,%x2,%x3,%0
6588 fpma%.d %x1,%x2,%x3,%0")
6591 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6592 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
6593 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
6594 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
6597 fpma%.s %1,%w2,%w3,%0
6599 fpma%.s %1,%2,%3,%0")
6601 ;; FPA Multiply and subtract
6603 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6604 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6605 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
6606 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6609 fpms%.d %3,%w2,%w1,%0
6610 fpms%.d %x3,%2,%x1,%0
6611 fpms%.d %x3,%2,%x1,%0")
6614 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6615 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6616 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
6617 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6620 fpms%.s %3,%w2,%w1,%0
6622 fpms%.s %3,%2,%1,%0")
6625 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6626 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6627 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6628 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6631 fpmr%.d %2,%w1,%w3,%0
6632 fpmr%.d %x2,%1,%x3,%0
6633 fpmr%.d %x2,%1,%x3,%0")
6636 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6637 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6638 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6639 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6642 fpmr%.s %2,%w1,%w3,%0
6643 fpmr%.s %x2,%1,%x3,%0
6644 fpmr%.s %x2,%1,%x3,%0")
6646 ;; FPA Add and multiply
6648 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6649 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
6650 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6651 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6654 fpam%.d %2,%w1,%w3,%0
6655 fpam%.d %x2,%1,%x3,%0
6656 fpam%.d %x2,%1,%x3,%0")
6659 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6660 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
6661 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6662 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6665 fpam%.s %2,%w1,%w3,%0
6666 fpam%.s %x2,%1,%x3,%0
6667 fpam%.s %x2,%1,%x3,%0")
6669 ;;FPA Subtract and multiply
6671 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6672 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
6673 (match_operand:DF 2 "general_operand" "x,y,rmF"))
6674 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
6677 fpsm%.d %2,%w1,%w3,%0
6678 fpsm%.d %x2,%1,%x3,%0
6679 fpsm%.d %x2,%1,%x3,%0")
6682 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
6683 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
6684 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
6685 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
6688 fpsm%.d %3,%w2,%w1,%0
6689 fpsm%.d %x3,%2,%x1,%0
6690 fpsm%.d %x3,%2,%x1,%0")
6693 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6694 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
6695 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
6696 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
6699 fpsm%.s %2,%w1,%w3,%0
6700 fpsm%.s %x2,%1,%x3,%0
6701 fpsm%.s %x2,%1,%x3,%0")
6704 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
6705 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
6706 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
6707 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
6710 fpsm%.s %3,%w2,%w1,%0
6711 fpsm%.s %x3,%2,%x1,%0
6712 fpsm%.s %x3,%2,%x1,%0")
6714 (define_insn "tstxf"
6716 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
6720 cc_status.flags = CC_IN_68881;
6721 return \"ftst%.x %0\";
6724 (define_insn "cmpxf"
6726 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
6727 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
6731 cc_status.flags = CC_IN_68881;
6732 #ifdef SGS_CMP_ORDER
6733 if (REG_P (operands[0]))
6735 if (REG_P (operands[1]))
6736 return \"fcmp%.x %0,%1\";
6738 return \"fcmp%.x %0,%f1\";
6740 cc_status.flags |= CC_REVERSED;
6741 return \"fcmp%.x %1,%f0\";
6743 if (REG_P (operands[0]))
6745 if (REG_P (operands[1]))
6746 return \"fcmp%.x %1,%0\";
6748 return \"fcmp%.x %f1,%0\";
6750 cc_status.flags |= CC_REVERSED;
6751 return \"fcmp%.x %f0,%1\";
6755 (define_insn "extendsfxf2"
6756 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6757 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
6761 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6763 if (REGNO (operands[0]) == REGNO (operands[1]))
6765 /* Extending float to double in an fp-reg is a no-op.
6766 NOTICE_UPDATE_CC has already assumed that the
6767 cc will be set. So cancel what it did. */
6768 cc_status = cc_prev_status;
6771 return \"f%$move%.x %1,%0\";
6773 if (FP_REG_P (operands[0]))
6774 return \"f%$move%.s %f1,%0\";
6775 return \"fmove%.x %f1,%0\";
6779 (define_insn "extenddfxf2"
6780 [(set (match_operand:XF 0 "general_operand" "=fm,f")
6782 (match_operand:DF 1 "general_operand" "f,m")))]
6786 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
6788 if (REGNO (operands[0]) == REGNO (operands[1]))
6790 /* Extending float to double in an fp-reg is a no-op.
6791 NOTICE_UPDATE_CC has already assumed that the
6792 cc will be set. So cancel what it did. */
6793 cc_status = cc_prev_status;
6796 return \"fmove%.x %1,%0\";
6798 if (FP_REG_P (operands[0]))
6799 return \"f%&move%.d %f1,%0\";
6800 return \"fmove%.x %f1,%0\";
6803 (define_insn "truncxfdf2"
6804 [(set (match_operand:DF 0 "general_operand" "=m,!r")
6806 (match_operand:XF 1 "general_operand" "f,f")))]
6810 if (REG_P (operands[0]))
6812 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
6813 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
6814 return \"move%.l %+,%0\";
6816 return \"fmove%.d %f1,%0\";
6819 (define_insn "truncxfsf2"
6820 [(set (match_operand:SF 0 "general_operand" "=dm")
6822 (match_operand:XF 1 "general_operand" "f")))]
6826 (define_insn "floatsixf2"
6827 [(set (match_operand:XF 0 "general_operand" "=f")
6828 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
6832 (define_insn "floathixf2"
6833 [(set (match_operand:XF 0 "general_operand" "=f")
6834 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
6838 (define_insn "floatqixf2"
6839 [(set (match_operand:XF 0 "general_operand" "=f")
6840 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
6844 (define_insn "ftruncxf2"
6845 [(set (match_operand:XF 0 "general_operand" "=f")
6846 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
6850 if (FP_REG_P (operands[1]))
6851 return \"fintrz%.x %f1,%0\";
6852 return \"fintrz%.x %f1,%0\";
6855 (define_insn "fixxfqi2"
6856 [(set (match_operand:QI 0 "general_operand" "=dm")
6857 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
6861 (define_insn "fixxfhi2"
6862 [(set (match_operand:HI 0 "general_operand" "=dm")
6863 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
6867 (define_insn "fixxfsi2"
6868 [(set (match_operand:SI 0 "general_operand" "=dm")
6869 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
6874 [(set (match_operand:XF 0 "general_operand" "=f")
6875 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6876 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6881 [(set (match_operand:XF 0 "general_operand" "=f")
6882 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6883 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6888 [(set (match_operand:XF 0 "general_operand" "=f")
6889 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6890 (match_operand:XF 1 "general_operand" "0")))]
6894 (define_insn "addxf3"
6895 [(set (match_operand:XF 0 "general_operand" "=f")
6896 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6897 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6901 if (REG_P (operands[2]))
6902 return \"fadd%.x %2,%0\";
6903 return \"fadd%.x %f2,%0\";
6907 [(set (match_operand:XF 0 "general_operand" "=f")
6908 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6909 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6914 [(set (match_operand:XF 0 "general_operand" "=f")
6915 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6916 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6921 [(set (match_operand:XF 0 "general_operand" "=f")
6922 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6923 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6927 (define_insn "subxf3"
6928 [(set (match_operand:XF 0 "general_operand" "=f")
6929 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6930 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6934 if (REG_P (operands[2]))
6935 return \"fsub%.x %2,%0\";
6936 return \"fsub%.x %f2,%0\";
6940 [(set (match_operand:XF 0 "general_operand" "=f")
6941 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
6942 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6947 [(set (match_operand:XF 0 "general_operand" "=f")
6948 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
6949 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6954 [(set (match_operand:XF 0 "general_operand" "=f")
6955 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
6956 (match_operand:XF 1 "nonimmediate_operand" "0")))]
6960 (define_insn "mulxf3"
6961 [(set (match_operand:XF 0 "general_operand" "=f")
6962 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
6963 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
6967 if (REG_P (operands[2]))
6968 return \"fmul%.x %2,%0\";
6969 return \"fmul%.x %f2,%0\";
6973 [(set (match_operand:XF 0 "general_operand" "=f")
6974 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6975 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
6980 [(set (match_operand:XF 0 "general_operand" "=f")
6981 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6982 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
6987 [(set (match_operand:XF 0 "general_operand" "=f")
6988 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6989 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
6993 (define_insn "divxf3"
6994 [(set (match_operand:XF 0 "general_operand" "=f")
6995 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
6996 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7000 if (REG_P (operands[2]))
7001 return \"fdiv%.x %2,%0\";
7002 return \"fdiv%.x %f2,%0\";
7005 (define_expand "negxf2"
7006 [(set (match_operand:XF 0 "general_operand" "")
7007 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7011 /* ??? There isn't an FPA define_insn so we could handle it here too.
7012 For now we don't (paranoia). */
7020 target = operand_subword (operands[0], 0, 1, XFmode);
7021 result = expand_binop (SImode, xor_optab,
7022 operand_subword_force (operands[1], 0, XFmode),
7023 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7027 if (result != target)
7028 emit_move_insn (result, target);
7030 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7031 operand_subword_force (operands[1], 1, XFmode));
7032 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7033 operand_subword_force (operands[1], 2, XFmode));
7035 insns = get_insns ();
7038 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7043 (define_insn "negxf2_68881"
7044 [(set (match_operand:XF 0 "general_operand" "=f")
7045 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7049 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7050 return \"fneg%.x %1,%0\";
7051 return \"fneg%.x %f1,%0\";
7054 (define_expand "absxf2"
7055 [(set (match_operand:XF 0 "general_operand" "")
7056 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7060 /* ??? There isn't an FPA define_insn so we could handle it here too.
7061 For now we don't (paranoia). */
7069 target = operand_subword (operands[0], 0, 1, XFmode);
7070 result = expand_binop (SImode, and_optab,
7071 operand_subword_force (operands[1], 0, XFmode),
7072 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7076 if (result != target)
7077 emit_move_insn (result, target);
7079 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7080 operand_subword_force (operands[1], 1, XFmode));
7081 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7082 operand_subword_force (operands[1], 2, XFmode));
7084 insns = get_insns ();
7087 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7092 (define_insn "absxf2_68881"
7093 [(set (match_operand:XF 0 "general_operand" "=f")
7094 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7098 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7099 return \"fabs%.x %1,%0\";
7100 return \"fabs%.x %f1,%0\";
7103 (define_insn "sqrtxf2"
7104 [(set (match_operand:XF 0 "general_operand" "=f")
7105 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7109 (define_insn "sinsf2"
7110 [(set (match_operand:SF 0 "general_operand" "=f")
7111 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7112 "TARGET_68881 && flag_fast_math"
7115 if (FP_REG_P (operands[1]))
7116 return \"fsin%.x %1,%0\";
7118 return \"fsin%.s %1,%0\";
7121 (define_insn "sindf2"
7122 [(set (match_operand:DF 0 "general_operand" "=f")
7123 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7124 "TARGET_68881 && flag_fast_math"
7127 if (FP_REG_P (operands[1]))
7128 return \"fsin%.x %1,%0\";
7130 return \"fsin%.d %1,%0\";
7133 (define_insn "sinxf2"
7134 [(set (match_operand:XF 0 "general_operand" "=f")
7135 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7136 "TARGET_68881 && flag_fast_math"
7139 (define_insn "cossf2"
7140 [(set (match_operand:SF 0 "general_operand" "=f")
7141 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7142 "TARGET_68881 && flag_fast_math"
7145 if (FP_REG_P (operands[1]))
7146 return \"fcos%.x %1,%0\";
7148 return \"fcos%.s %1,%0\";
7151 (define_insn "cosdf2"
7152 [(set (match_operand:DF 0 "general_operand" "=f")
7153 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7154 "TARGET_68881 && flag_fast_math"
7157 if (FP_REG_P (operands[1]))
7158 return \"fcos%.x %1,%0\";
7160 return \"fcos%.d %1,%0\";
7163 (define_insn "cosxf2"
7164 [(set (match_operand:XF 0 "general_operand" "=f")
7165 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7166 "TARGET_68881 && flag_fast_math"