1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93, 94, 95, 96, 97, 98 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
752 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
753 ;; specified as a constant, so we must disable all patterns that may extract
754 ;; from a MEM at a constant bit position if we can't use this as a constraint.
757 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
759 (minus:SI (const_int 7)
760 (match_operand:SI 1 "general_operand" "di"))))]
762 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
764 ;; This is the same as the above pattern except for the constraints. The 'i'
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "d"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
776 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
778 (minus:SI (const_int 31)
779 (match_operand:SI 1 "general_operand" "di"))))]
781 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
783 ;; The following two patterns are like the previous two
784 ;; except that they use the fact that bit-number operands
785 ;; are automatically masked to 3 or 5 bits.
788 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
790 (minus:SI (const_int 7)
792 (match_operand:SI 1 "register_operand" "d")
795 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
798 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
800 (minus:SI (const_int 31)
802 (match_operand:SI 1 "register_operand" "d")
805 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
807 ;; Nonoffsettable mem refs are ok in this one pattern
808 ;; since we don't try to adjust them.
810 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
812 (match_operand:SI 1 "const_int_operand" "n")))]
813 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
816 operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
817 return output_btst (operands, operands[1], operands[0], insn, 7);
821 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
823 (match_operand:SI 1 "const_int_operand" "n")))]
827 if (GET_CODE (operands[0]) == MEM)
829 operands[0] = adj_offsettable_operand (operands[0],
830 INTVAL (operands[1]) / 8);
831 operands[1] = gen_rtx (CONST_INT, VOIDmode,
832 7 - INTVAL (operands[1]) % 8);
833 return output_btst (operands, operands[1], operands[0], insn, 7);
835 operands[1] = gen_rtx (CONST_INT, VOIDmode,
836 31 - INTVAL (operands[1]));
837 return output_btst (operands, operands[1], operands[0], insn, 31);
840 ;; This is the same as the above pattern except for the constraints.
841 ;; The 'o' has been replaced with 'Q'.
844 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
846 (match_operand:SI 1 "const_int_operand" "n")))]
850 if (GET_CODE (operands[0]) == MEM)
852 operands[0] = adj_offsettable_operand (operands[0],
853 INTVAL (operands[1]) / 8);
854 operands[1] = gen_rtx (CONST_INT, VOIDmode,
855 7 - INTVAL (operands[1]) % 8);
856 return output_btst (operands, operands[1], operands[0], insn, 7);
858 operands[1] = gen_rtx (CONST_INT, VOIDmode,
859 31 - INTVAL (operands[1]));
860 return output_btst (operands, operands[1], operands[0], insn, 31);
866 ;; A special case in which it is not desirable
867 ;; to reload the constant into a data register.
868 (define_insn "pushexthisi_const"
869 [(set (match_operand:SI 0 "push_operand" "=m")
870 (match_operand:SI 1 "const_int_operand" "J"))]
871 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
874 if (operands[1] == const0_rtx)
875 return \"clr%.l %0\";
880 ;(define_insn "swapsi"
881 ; [(set (match_operand:SI 0 "general_operand" "+r")
882 ; (match_operand:SI 1 "general_operand" "+r"))
883 ; (set (match_dup 1) (match_dup 0))]
887 ;; Special case of fullword move when source is zero.
888 ;; The reason this is special is to avoid loading a zero
889 ;; into a data reg with moveq in order to store it elsewhere.
891 (define_insn "movsi_const0"
892 [(set (match_operand:SI 0 "general_operand" "=g")
894 ;; clr insns on 68000 read before writing.
895 ;; This isn't so on the 68010, but we have no TARGET_68010.
896 "((TARGET_68020 || TARGET_5200)
897 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
900 if (ADDRESS_REG_P (operands[0]))
902 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
903 if (!TARGET_68040 && !TARGET_68060)
904 return \"sub%.l %0,%0\";
909 /* Many SGS assemblers croak on size specifiers for constants. */
912 return \"lea 0.w,%0\";
915 return \"lea 0:w,%0\";
919 /* moveq is faster on the 68000. */
920 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
921 #if defined(MOTOROLA) && !defined(CRDS)
922 return \"moveq%.l %#0,%0\";
924 return \"moveq %#0,%0\";
926 return \"clr%.l %0\";
929 ;; General case of fullword move.
931 ;; This is the main "hook" for PIC code. When generating
932 ;; PIC, movsi is responsible for determining when the source address
933 ;; needs PIC relocation and appropriately calling legitimize_pic_address
934 ;; to perform the actual relocation.
936 ;; In both the PIC and non-PIC cases the patterns generated will
937 ;; matched by the next define_insn.
938 (define_expand "movsi"
939 [(set (match_operand:SI 0 "general_operand" "")
940 (match_operand:SI 1 "general_operand" ""))]
944 if (flag_pic && symbolic_operand (operands[1], SImode))
946 /* The source is an address which requires PIC relocation.
947 Call legitimize_pic_address with the source, mode, and a relocation
948 register (a new pseudo, or the final destination if reload_in_progress
949 is set). Then fall through normally */
950 extern rtx legitimize_pic_address();
951 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
952 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
956 ;; General case of fullword move. The register constraints
957 ;; force integer constants in range for a moveq to be reloaded
958 ;; if they are headed for memory.
960 ;; Notes: make sure no alternative allows g vs g.
961 ;; We don't allow f-regs since fixed point cannot go in them.
962 ;; We do allow y and x regs since fixed point is allowed in them.
963 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
964 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
968 if (which_alternative == 3)
969 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
970 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
971 return \"fpmove%.l %x1,%x0\";
972 return output_move_simode (operands);
976 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
977 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
979 "* return output_move_simode (operands);")
981 (define_expand "movhi"
982 [(set (match_operand:HI 0 "general_operand" "")
983 (match_operand:HI 1 "general_operand" ""))]
988 [(set (match_operand:HI 0 "general_operand" "=g")
989 (match_operand:HI 1 "general_operand" "g"))]
991 "* return output_move_himode (operands);")
994 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
995 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
997 "* return output_move_himode (operands);")
999 (define_expand "movstricthi"
1000 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
1001 (match_operand:HI 1 "general_operand" ""))]
1006 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1007 (match_operand:HI 1 "general_operand" "rmn"))]
1009 "* return output_move_stricthi (operands);")
1012 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1013 (match_operand:HI 1 "general_operand" "rmn,r"))]
1015 "* return output_move_stricthi (operands);")
1017 (define_expand "movqi"
1018 [(set (match_operand:QI 0 "general_operand" "")
1019 (match_operand:QI 1 "general_operand" ""))]
1024 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1025 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1027 "* return output_move_qimode (operands);")
1030 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am")
1031 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>"))]
1033 "* return output_move_qimode (operands);")
1035 (define_expand "movstrictqi"
1036 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1037 (match_operand:QI 1 "general_operand" ""))]
1042 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1043 (match_operand:QI 1 "general_operand" "dmn"))]
1045 "* return output_move_strictqi (operands);")
1048 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1049 (match_operand:QI 1 "general_operand" "dmn,d"))]
1051 "* return output_move_strictqi (operands);")
1053 (define_expand "movsf"
1054 [(set (match_operand:SF 0 "general_operand" "")
1055 (match_operand:SF 1 "general_operand" ""))]
1060 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1061 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1062 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1063 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1067 if (which_alternative >= 4)
1068 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1069 if (FPA_REG_P (operands[0]))
1071 if (FPA_REG_P (operands[1]))
1072 return \"fpmove%.s %x1,%x0\";
1073 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1074 return output_move_const_single (operands);
1075 else if (FP_REG_P (operands[1]))
1076 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1077 return \"fpmove%.s %x1,%x0\";
1079 if (FPA_REG_P (operands[1]))
1081 if (FP_REG_P (operands[0]))
1082 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1084 return \"fpmove%.s %x1,%x0\";
1086 if (FP_REG_P (operands[0]))
1088 if (FP_REG_P (operands[1]))
1089 return \"f%$move%.x %1,%0\";
1090 else if (ADDRESS_REG_P (operands[1]))
1091 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1092 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1093 return output_move_const_single (operands);
1094 return \"f%$move%.s %f1,%0\";
1096 if (FP_REG_P (operands[1]))
1098 if (ADDRESS_REG_P (operands[0]))
1099 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1100 return \"fmove%.s %f1,%0\";
1102 if (operands[1] == CONST0_RTX (SFmode)
1103 /* clr insns on 68000 read before writing.
1104 This isn't so on the 68010, but we have no TARGET_68010. */
1105 && ((TARGET_68020 || TARGET_5200)
1106 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1108 if (ADDRESS_REG_P (operands[0]))
1110 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1111 if (!TARGET_68040 && !TARGET_68060)
1112 return \"sub%.l %0,%0\";
1117 /* Many SGS assemblers croak on size specifiers for constants. */
1118 return \"lea 0,%0\";
1120 return \"lea 0.w,%0\";
1123 return \"lea 0:w,%0\";
1127 /* moveq is faster on the 68000. */
1128 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1130 #if defined(MOTOROLA) && !defined(CRDS)
1131 return \"moveq%.l %#0,%0\";
1133 return \"moveq %#0,%0\";
1136 return \"clr%.l %0\";
1138 return \"move%.l %1,%0\";
1142 [(set (match_operand:SF 0 "general_operand" "=r,g")
1143 (match_operand:SF 1 "general_operand" "g,r"))]
1145 "* return \"move%.l %1,%0\";")
1147 (define_expand "movdf"
1148 [(set (match_operand:DF 0 "general_operand" "")
1149 (match_operand:DF 1 "general_operand" ""))]
1154 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1155 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1156 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1157 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1161 if (which_alternative == 7)
1162 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1163 if (FPA_REG_P (operands[0]))
1165 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1166 return output_move_const_double (operands);
1167 if (FP_REG_P (operands[1]))
1168 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1169 return \"fpmove%.d %x1,%x0\";
1171 else if (FPA_REG_P (operands[1]))
1173 if (FP_REG_P(operands[0]))
1174 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1176 return \"fpmove%.d %x1,%x0\";
1178 if (FP_REG_P (operands[0]))
1180 if (FP_REG_P (operands[1]))
1181 return \"f%&move%.x %1,%0\";
1182 if (REG_P (operands[1]))
1185 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1186 output_asm_insn (\"move%.l %1,%-\", xoperands);
1187 output_asm_insn (\"move%.l %1,%-\", operands);
1188 return \"f%&move%.d %+,%0\";
1190 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1191 return output_move_const_double (operands);
1192 return \"f%&move%.d %f1,%0\";
1194 else if (FP_REG_P (operands[1]))
1196 if (REG_P (operands[0]))
1198 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1199 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1200 return \"move%.l %+,%0\";
1203 return \"fmove%.d %f1,%0\";
1205 return output_move_double (operands);
1209 [(set (match_operand:DF 0 "general_operand" "=r,g")
1210 (match_operand:DF 1 "general_operand" "g,r"))]
1212 "* return output_move_double (operands);")
1214 (define_expand "movxf"
1215 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1216 (match_operand:XF 1 "general_operand" ""))]
1220 if (CONSTANT_P (operands[1]))
1222 operands[1] = force_const_mem (XFmode, operands[1]);
1223 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1224 && ! reload_in_progress)
1225 operands[1] = change_address (operands[1], XFmode,
1226 XEXP (operands[1], 0));
1231 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1232 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1236 if (FP_REG_P (operands[0]))
1238 if (FP_REG_P (operands[1]))
1239 return \"fmove%.x %1,%0\";
1240 if (REG_P (operands[1]))
1243 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1244 output_asm_insn (\"move%.l %1,%-\", xoperands);
1245 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1246 output_asm_insn (\"move%.l %1,%-\", xoperands);
1247 output_asm_insn (\"move%.l %1,%-\", operands);
1248 return \"fmove%.x %+,%0\";
1250 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1251 return \"fmove%.x %1,%0\";
1252 return \"fmove%.x %f1,%0\";
1254 if (REG_P (operands[0]))
1256 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1257 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1258 output_asm_insn (\"move%.l %+,%0\", operands);
1259 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1260 return \"move%.l %+,%0\";
1262 return \"fmove%.x %f1,%0\";
1267 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1268 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1269 "! TARGET_68881 && ! TARGET_5200"
1272 if (FP_REG_P (operands[0]))
1274 if (FP_REG_P (operands[1]))
1275 return \"fmove%.x %1,%0\";
1276 if (REG_P (operands[1]))
1279 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2);
1280 output_asm_insn (\"move%.l %1,%-\", xoperands);
1281 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1282 output_asm_insn (\"move%.l %1,%-\", xoperands);
1283 output_asm_insn (\"move%.l %1,%-\", operands);
1284 return \"fmove%.x %+,%0\";
1286 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1287 return \"fmove%.x %1,%0\";
1288 return \"fmove%.x %f1,%0\";
1290 if (FP_REG_P (operands[1]))
1292 if (REG_P (operands[0]))
1294 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1295 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1296 output_asm_insn (\"move%.l %+,%0\", operands);
1297 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1298 return \"move%.l %+,%0\";
1301 return \"fmove%.x %f1,%0\";
1303 return output_move_double (operands);
1308 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1309 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1310 "! TARGET_68881 && TARGET_5200"
1311 "* return output_move_double (operands);")
1313 (define_expand "movdi"
1314 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1315 [(set (match_operand:DI 0 "general_operand" "")
1316 (match_operand:DI 1 "general_operand" ""))]
1320 ;; movdi can apply to fp regs in some cases
1322 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1323 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1324 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1325 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1326 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1327 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1328 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1332 if (which_alternative == 8)
1333 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1334 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1335 return \"fpmove%.d %x1,%x0\";
1336 if (FP_REG_P (operands[0]))
1338 if (FP_REG_P (operands[1]))
1339 return \"fmove%.x %1,%0\";
1340 if (REG_P (operands[1]))
1343 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1344 output_asm_insn (\"move%.l %1,%-\", xoperands);
1345 output_asm_insn (\"move%.l %1,%-\", operands);
1346 return \"fmove%.d %+,%0\";
1348 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1349 return output_move_const_double (operands);
1350 return \"fmove%.d %f1,%0\";
1352 else if (FP_REG_P (operands[1]))
1354 if (REG_P (operands[0]))
1356 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1357 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1358 return \"move%.l %+,%0\";
1361 return \"fmove%.d %f1,%0\";
1363 return output_move_double (operands);
1367 [(set (match_operand:DI 0 "general_operand" "=r,g")
1368 (match_operand:DI 1 "general_operand" "g,r"))]
1370 "* return output_move_double (operands);")
1372 ;; Thus goes after the move instructions
1373 ;; because the move instructions are better (require no spilling)
1374 ;; when they can apply. It goes before the add/sub insns
1375 ;; so we will prefer it to them.
1377 (define_insn "pushasi"
1378 [(set (match_operand:SI 0 "push_operand" "=m")
1379 (match_operand:SI 1 "address_operand" "p"))]
1383 ;; truncation instructions
1384 (define_insn "truncsiqi2"
1385 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1387 (match_operand:SI 1 "general_operand" "doJ,i")))]
1391 if (GET_CODE (operands[0]) == REG)
1393 /* Must clear condition codes, since the move.l bases them on
1394 the entire 32 bits, not just the desired 8 bits. */
1396 return \"move%.l %1,%0\";
1398 if (GET_CODE (operands[1]) == MEM)
1399 operands[1] = adj_offsettable_operand (operands[1], 3);
1400 return \"move%.b %1,%0\";
1403 (define_insn "trunchiqi2"
1404 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1406 (match_operand:HI 1 "general_operand" "doJ,i")))]
1410 if (GET_CODE (operands[0]) == REG
1411 && (GET_CODE (operands[1]) == MEM
1412 || GET_CODE (operands[1]) == CONST_INT))
1414 /* Must clear condition codes, since the move.w bases them on
1415 the entire 16 bits, not just the desired 8 bits. */
1417 return \"move%.w %1,%0\";
1419 if (GET_CODE (operands[0]) == REG)
1421 /* Must clear condition codes, since the move.l bases them on
1422 the entire 32 bits, not just the desired 8 bits. */
1424 return \"move%.l %1,%0\";
1426 if (GET_CODE (operands[1]) == MEM)
1427 operands[1] = adj_offsettable_operand (operands[1], 1);
1428 return \"move%.b %1,%0\";
1431 (define_insn "truncsihi2"
1432 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1434 (match_operand:SI 1 "general_operand" "roJ,i")))]
1438 if (GET_CODE (operands[0]) == REG)
1440 /* Must clear condition codes, since the move.l bases them on
1441 the entire 32 bits, not just the desired 8 bits. */
1443 return \"move%.l %1,%0\";
1445 if (GET_CODE (operands[1]) == MEM)
1446 operands[1] = adj_offsettable_operand (operands[1], 2);
1447 return \"move%.w %1,%0\";
1450 ;; zero extension instructions
1452 ;; this is the canonical form for (lshiftrt:DI x 32)
1453 (define_insn "zero_extendsidi2"
1454 [(set (match_operand:DI 0 "general_operand" "rm")
1455 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1460 if (GET_CODE (operands[0]) == REG)
1461 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1462 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1463 return \"move%.l %1,%0\;clr%.l %0\";
1464 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1465 return \"clr%.l %0\;move%.l %1,%0\";
1467 operands[2] = adj_offsettable_operand (operands[0], 4);
1468 if (ADDRESS_REG_P (operands[0]))
1469 return \"move%.l %1,%2\;sub%.l %0,%0\";
1471 return \"move%.l %1,%2\;clr%.l %0\";
1474 (define_expand "zero_extendhisi2"
1475 [(set (match_operand:SI 0 "register_operand" "")
1477 (set (strict_low_part (match_dup 2))
1478 (match_operand:HI 1 "general_operand" ""))]
1482 operands[1] = make_safe_from (operands[1], operands[0]);
1483 if (GET_CODE (operands[0]) == SUBREG)
1484 operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]),
1485 SUBREG_WORD (operands[0]));
1487 operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0);
1490 (define_expand "zero_extendqihi2"
1491 [(set (match_operand:HI 0 "register_operand" "")
1493 (set (strict_low_part (match_dup 2))
1494 (match_operand:QI 1 "general_operand" ""))]
1498 operands[1] = make_safe_from (operands[1], operands[0]);
1499 if (GET_CODE (operands[0]) == SUBREG)
1500 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1501 SUBREG_WORD (operands[0]));
1503 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1506 (define_expand "zero_extendqisi2"
1507 [(set (match_operand:SI 0 "register_operand" "")
1509 (set (strict_low_part (match_dup 2))
1510 (match_operand:QI 1 "general_operand" ""))]
1514 operands[1] = make_safe_from (operands[1], operands[0]);
1515 if (GET_CODE (operands[0]) == SUBREG)
1516 operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]),
1517 SUBREG_WORD (operands[0]));
1519 operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0);
1522 ;; Patterns to recognize zero-extend insns produced by the combiner.
1523 ;; We don't allow both operands in memory, because of aliasing problems.
1524 ;; Explicitly disallow two memory operands via the condition since reloading
1525 ;; of this case will result in worse code than the uncombined patterns.
1528 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1529 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1530 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1533 if (DATA_REG_P (operands[0]))
1535 if (GET_CODE (operands[1]) == REG
1536 && REGNO (operands[0]) == REGNO (operands[1]))
1537 return \"and%.l %#0xFFFF,%0\";
1538 if (reg_mentioned_p (operands[0], operands[1]))
1539 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1540 return \"clr%.l %0\;move%.w %1,%0\";
1542 else if (GET_CODE (operands[0]) == MEM
1543 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1544 return \"move%.w %1,%0\;clr%.w %0\";
1545 else if (GET_CODE (operands[0]) == MEM
1546 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1547 return \"clr%.w %0\;move%.w %1,%0\";
1550 output_asm_insn (\"clr%.w %0\", operands);
1551 operands[0] = adj_offsettable_operand (operands[0], 2);
1552 return \"move%.w %1,%0\";
1557 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1558 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1559 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1562 if (DATA_REG_P (operands[0]))
1564 if (GET_CODE (operands[1]) == REG
1565 && REGNO (operands[0]) == REGNO (operands[1]))
1566 return \"and%.w %#0xFF,%0\";
1567 if (reg_mentioned_p (operands[0], operands[1]))
1568 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1569 return \"clr%.w %0\;move%.b %1,%0\";
1571 else if (GET_CODE (operands[0]) == MEM
1572 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1574 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1575 == STACK_POINTER_REGNUM)
1577 output_asm_insn (\"clr%.w %-\", operands);
1578 operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1579 plus_constant (stack_pointer_rtx, 1));
1580 return \"move%.b %1,%0\";
1583 return \"move%.b %1,%0\;clr%.b %0\";
1585 else if (GET_CODE (operands[0]) == MEM
1586 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1587 return \"clr%.b %0\;move%.b %1,%0\";
1590 output_asm_insn (\"clr%.b %0\", operands);
1591 operands[0] = adj_offsettable_operand (operands[0], 1);
1592 return \"move%.b %1,%0\";
1597 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1598 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1599 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1602 if (DATA_REG_P (operands[0]))
1604 if (GET_CODE (operands[1]) == REG
1605 && REGNO (operands[0]) == REGNO (operands[1]))
1606 return \"and%.l %#0xFF,%0\";
1607 if (reg_mentioned_p (operands[0], operands[1]))
1608 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1609 return \"clr%.l %0\;move%.b %1,%0\";
1611 else if (GET_CODE (operands[0]) == MEM
1612 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1614 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1617 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1619 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1622 return \"clrl %0@-\;moveb %1,%0@(3)\";
1625 else if (GET_CODE (operands[0]) == MEM
1626 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1628 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1631 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1633 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1636 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1641 output_asm_insn (\"clr%.l %0\", operands);
1642 operands[0] = adj_offsettable_operand (operands[0], 3);
1643 return \"move%.b %1,%0\";
1647 ;; sign extension instructions
1649 (define_insn "extendqidi2"
1650 [(set (match_operand:DI 0 "general_operand" "=d")
1652 (match_operand:QI 1 "general_operand" "rm")))]
1657 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1658 if (TARGET_68020 || TARGET_5200)
1659 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1661 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1664 (define_insn "extendhidi2"
1665 [(set (match_operand:DI 0 "general_operand" "=d")
1667 (match_operand:HI 1 "general_operand" "rm")))]
1672 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1673 if (TARGET_68020 || TARGET_5200)
1674 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1676 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1679 (define_insn "extendsidi2"
1680 [(set (match_operand:DI 0 "general_operand" "=d")
1682 (match_operand:SI 1 "general_operand" "rm")))]
1687 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1688 if (TARGET_68020 || TARGET_5200)
1689 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1691 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1694 ;; Special case when one can avoid register clobbering, copy and test
1695 ;; Maybe there is a way to make that the general case, by forcing the
1696 ;; result of the SI tree to be in the lower register of the DI target
1698 (define_insn "extendplussidi"
1699 [(set (match_operand:DI 0 "register_operand" "=d")
1700 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1701 (match_operand:SI 2 "general_operand" "rmn"))))]
1706 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1707 if (GET_CODE (operands[1]) == CONST_INT
1708 && (unsigned) INTVAL (operands[1]) > 8)
1710 rtx tmp = operands[1];
1712 operands[1] = operands[2];
1715 if (GET_CODE (operands[1]) == REG
1716 && REGNO (operands[1]) == REGNO (operands[3]))
1717 output_asm_insn (\"add%.l %2,%3\", operands);
1719 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1720 if (TARGET_68020 || TARGET_5200)
1721 return \"smi %0\;extb%.l %0\";
1723 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1726 (define_insn "extendhisi2"
1727 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1729 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1733 if (ADDRESS_REG_P (operands[0]))
1734 return \"move%.w %1,%0\";
1735 return \"ext%.l %0\";
1738 (define_insn "extendqihi2"
1739 [(set (match_operand:HI 0 "general_operand" "=d")
1740 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1744 (define_insn "extendqisi2"
1745 [(set (match_operand:SI 0 "general_operand" "=d")
1746 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1747 "TARGET_68020 || TARGET_5200"
1750 ;; Conversions between float and double.
1752 (define_expand "extendsfdf2"
1753 [(set (match_operand:DF 0 "general_operand" "")
1755 (match_operand:SF 1 "general_operand" "")))]
1756 "TARGET_68881 || TARGET_FPA"
1760 [(set (match_operand:DF 0 "general_operand" "=x,y")
1762 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1767 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1769 (match_operand:SF 1 "general_operand" "f,dmF")))]
1773 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1775 if (REGNO (operands[0]) == REGNO (operands[1]))
1777 /* Extending float to double in an fp-reg is a no-op.
1778 NOTICE_UPDATE_CC has already assumed that the
1779 cc will be set. So cancel what it did. */
1780 cc_status = cc_prev_status;
1783 return \"f%&move%.x %1,%0\";
1785 if (FP_REG_P (operands[0]))
1786 return \"f%&move%.s %f1,%0\";
1787 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1789 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1790 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1791 return \"move%.l %+,%0\";
1793 return \"fmove%.d %f1,%0\";
1796 ;; This cannot output into an f-reg because there is no way to be
1797 ;; sure of truncating in that case.
1798 ;; But on the Sun FPA, we can be sure.
1799 (define_expand "truncdfsf2"
1800 [(set (match_operand:SF 0 "general_operand" "")
1802 (match_operand:DF 1 "general_operand" "")))]
1803 "TARGET_68881 || TARGET_FPA"
1807 [(set (match_operand:SF 0 "general_operand" "=x,y")
1809 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1813 ;; On the '040 we can truncate in a register accurately and easily.
1815 [(set (match_operand:SF 0 "general_operand" "=f")
1817 (match_operand:DF 1 "general_operand" "fmG")))]
1821 if (FP_REG_P (operands[1]))
1822 return \"f%$move%.x %1,%0\";
1823 return \"f%$move%.d %f1,%0\";
1827 [(set (match_operand:SF 0 "general_operand" "=dm")
1829 (match_operand:DF 1 "general_operand" "f")))]
1833 ;; Conversion between fixed point and floating point.
1834 ;; Note that among the fix-to-float insns
1835 ;; the ones that start with SImode come first.
1836 ;; That is so that an operand that is a CONST_INT
1837 ;; (and therefore lacks a specific machine mode).
1838 ;; will be recognized as SImode (which is always valid)
1839 ;; rather than as QImode or HImode.
1841 (define_expand "floatsisf2"
1842 [(set (match_operand:SF 0 "general_operand" "")
1843 (float:SF (match_operand:SI 1 "general_operand" "")))]
1844 "TARGET_68881 || TARGET_FPA"
1848 [(set (match_operand:SF 0 "general_operand" "=y,x")
1849 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1854 [(set (match_operand:SF 0 "general_operand" "=f")
1855 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1859 (define_expand "floatsidf2"
1860 [(set (match_operand:DF 0 "general_operand" "")
1861 (float:DF (match_operand:SI 1 "general_operand" "")))]
1862 "TARGET_68881 || TARGET_FPA"
1866 [(set (match_operand:DF 0 "general_operand" "=y,x")
1867 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1872 [(set (match_operand:DF 0 "general_operand" "=f")
1873 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1877 (define_insn "floathisf2"
1878 [(set (match_operand:SF 0 "general_operand" "=f")
1879 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1883 (define_insn "floathidf2"
1884 [(set (match_operand:DF 0 "general_operand" "=f")
1885 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1889 (define_insn "floatqisf2"
1890 [(set (match_operand:SF 0 "general_operand" "=f")
1891 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1895 (define_insn "floatqidf2"
1896 [(set (match_operand:DF 0 "general_operand" "=f")
1897 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1901 ;; New routines to convert floating-point values to integers
1902 ;; to be used on the '040. These should be faster than trapping
1903 ;; into the kernel to emulate fintrz. They should also be faster
1904 ;; than calling the subroutines fixsfsi or fixdfsi.
1906 (define_insn "fix_truncdfsi2"
1907 [(set (match_operand:SI 0 "general_operand" "=dm")
1908 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1909 (clobber (match_scratch:SI 2 "=d"))
1910 (clobber (match_scratch:SI 3 "=d"))]
1911 "TARGET_68881 && TARGET_68040"
1915 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1918 (define_insn "fix_truncdfhi2"
1919 [(set (match_operand:HI 0 "general_operand" "=dm")
1920 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1921 (clobber (match_scratch:SI 2 "=d"))
1922 (clobber (match_scratch:SI 3 "=d"))]
1923 "TARGET_68881 && TARGET_68040"
1927 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1930 (define_insn "fix_truncdfqi2"
1931 [(set (match_operand:QI 0 "general_operand" "=dm")
1932 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1933 (clobber (match_scratch:SI 2 "=d"))
1934 (clobber (match_scratch:SI 3 "=d"))]
1935 "TARGET_68881 && TARGET_68040"
1939 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1942 ;; Convert a float to a float whose value is an integer.
1943 ;; This is the first stage of converting it to an integer type.
1945 (define_insn "ftruncdf2"
1946 [(set (match_operand:DF 0 "general_operand" "=f")
1947 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1948 "TARGET_68881 && !TARGET_68040"
1951 if (FP_REG_P (operands[1]))
1952 return \"fintrz%.x %f1,%0\";
1953 return \"fintrz%.d %f1,%0\";
1956 (define_insn "ftruncsf2"
1957 [(set (match_operand:SF 0 "general_operand" "=f")
1958 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1959 "TARGET_68881 && !TARGET_68040"
1962 if (FP_REG_P (operands[1]))
1963 return \"fintrz%.x %f1,%0\";
1964 return \"fintrz%.s %f1,%0\";
1967 ;; Convert a float whose value is an integer
1968 ;; to an actual integer. Second stage of converting float to integer type.
1969 (define_insn "fixsfqi2"
1970 [(set (match_operand:QI 0 "general_operand" "=dm")
1971 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1975 (define_insn "fixsfhi2"
1976 [(set (match_operand:HI 0 "general_operand" "=dm")
1977 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1981 (define_insn "fixsfsi2"
1982 [(set (match_operand:SI 0 "general_operand" "=dm")
1983 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1987 (define_insn "fixdfqi2"
1988 [(set (match_operand:QI 0 "general_operand" "=dm")
1989 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1993 (define_insn "fixdfhi2"
1994 [(set (match_operand:HI 0 "general_operand" "=dm")
1995 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1999 (define_insn "fixdfsi2"
2000 [(set (match_operand:SI 0 "general_operand" "=dm")
2001 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2005 ;; Convert a float to an integer.
2006 ;; On the Sun FPA, this is done in one step.
2009 [(set (match_operand:SI 0 "general_operand" "=x,y")
2010 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2015 [(set (match_operand:SI 0 "general_operand" "=x,y")
2016 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2022 (define_insn "adddi_lshrdi_63"
2023 [(set (match_operand:DI 0 "general_operand" "=d")
2024 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2027 (clobber (match_scratch:SI 2 "=d"))]
2031 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2032 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2034 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2035 if (GET_CODE (operands[1]) == REG)
2036 operands[4] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2037 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2038 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2039 operands[4] = operands[1];
2041 operands[4] = adj_offsettable_operand (operands[1], 4);
2042 if (GET_CODE (operands[1]) == MEM
2043 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2044 output_asm_insn (\"move%.l %4,%3\", operands);
2045 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2046 if (TARGET_68020 || TARGET_5200)
2047 output_asm_insn (\"extb%.l %2\", operands);
2049 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2050 if (GET_CODE (operands[1]) != MEM
2051 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2052 output_asm_insn (\"move%.l %4,%3\", operands);
2053 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2056 (define_insn "adddi_sexthishl32"
2057 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2058 (plus:DI (ashift:DI (sign_extend:DI
2059 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2061 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2062 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2067 if (ADDRESS_REG_P (operands[0]))
2068 return \"add%.w %1,%0\";
2069 else if (ADDRESS_REG_P (operands[3]))
2070 return \"move%.w %1,%3\;add%.l %3,%0\";
2072 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2075 (define_insn "adddi_dilshr32"
2076 [(set (match_operand:DI 0 "general_operand" "=do")
2077 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2078 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2079 ;; (const_int 32))))]
2080 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2082 (match_operand:DI 2 "general_operand" "0")))]
2087 if (GET_CODE (operands[0]) == REG)
2088 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
2090 operands[2] = adj_offsettable_operand (operands[0], 4);
2091 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2094 (define_insn "adddi_dishl32"
2095 [(set (match_operand:DI 0 "general_operand" "=ro")
2096 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2097 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2098 ;; (const_int 32))))]
2099 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2101 (match_operand:DI 2 "general_operand" "0")))]
2106 if (GET_CODE (operands[1]) == REG)
2107 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2109 operands[1] = adj_offsettable_operand (operands[1], 4);
2110 return \"add%.l %1,%0\";
2113 (define_insn "adddi3"
2114 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2115 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2116 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2117 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2121 if (DATA_REG_P (operands[0]))
2123 if (DATA_REG_P (operands[2]))
2124 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2125 else if (GET_CODE (operands[2]) == MEM
2126 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2128 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2132 if (GET_CODE (operands[2]) == REG)
2133 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2134 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2136 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2137 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2139 else if (GET_CODE (operands[2]) == CONST_INT)
2141 operands[1] = operands[2];
2142 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2145 operands[1] = adj_offsettable_operand (operands[2], 4);
2146 /* TODO : for consts, optimize move and add */
2147 return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
2150 else if (GET_CODE (operands[0]) == MEM)
2152 if (GET_CODE (operands[2]) == MEM
2153 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2154 return \"add%.l %2,%0\;addx%.l %2,%0\";
2156 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2158 operands[1] = gen_rtx (MEM, SImode,
2159 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2160 gen_rtx (CONST_INT, VOIDmode, -8)));
2161 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2163 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2165 operands[1] = XEXP(operands[0], 0);
2166 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2170 operands[1] = adj_offsettable_operand (operands[0], 4);
2171 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2176 (define_insn "addsi_lshrsi_31"
2177 [(set (match_operand:SI 0 "general_operand" "=dm")
2178 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2184 operands[2] = operands[0];
2185 operands[3] = gen_label_rtx();
2186 if (GET_CODE (operands[0]) == MEM)
2188 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2189 operands[0] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2190 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2191 operands[2] = gen_rtx (MEM, SImode, XEXP (XEXP (operands[0], 0), 0));
2193 output_asm_insn (\"move%.l %1,%0\", operands);
2195 output_asm_insn (\"jbpl %l3\", operands);
2197 output_asm_insn (\"jpl %l3\", operands);
2200 output_asm_insn (\"addq%.l %#1,%2\", operands);
2202 output_asm_insn (\"add%.l %#1,%2\", operands);
2204 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2205 CODE_LABEL_NUMBER (operands[3]));
2209 (define_expand "addsi3"
2210 [(set (match_operand:SI 0 "general_operand" "")
2211 (plus:SI (match_operand:SI 1 "general_operand" "")
2212 (match_operand:SI 2 "general_operand" "")))]
2216 ;; Note that the middle two alternatives are near-duplicates
2217 ;; in order to handle insns generated by reload.
2218 ;; This is needed since they are not themselves reloaded,
2219 ;; so commutativity won't apply to them.
2220 (define_insn "*addsi3_internal"
2221 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2222 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2223 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2225 "* return output_addsi3 (operands);")
2227 (define_insn "*addsi3_5200"
2228 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2229 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2230 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2232 "* return output_addsi3 (operands);")
2235 [(set (match_operand:SI 0 "general_operand" "=a")
2236 (plus:SI (match_operand:SI 1 "general_operand" "0")
2238 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2242 (define_insn "addhi3"
2243 [(set (match_operand:HI 0 "general_operand" "=m,r")
2244 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2245 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2249 if (GET_CODE (operands[2]) == CONST_INT)
2252 /* If the constant would be a negative number when interpreted as
2253 HImode, make it negative. This is usually, but not always, done
2254 elsewhere in the compiler. First check for constants out of range,
2255 which could confuse us. */
2257 if (INTVAL (operands[2]) >= 32768)
2258 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2259 INTVAL (operands[2]) - 65536);
2261 if (INTVAL (operands[2]) > 0
2262 && INTVAL (operands[2]) <= 8)
2263 return \"addq%.w %2,%0\";
2264 if (INTVAL (operands[2]) < 0
2265 && INTVAL (operands[2]) >= -8)
2267 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2268 - INTVAL (operands[2]));
2269 return \"subq%.w %2,%0\";
2271 /* On the CPU32 it is faster to use two addqw instructions to
2272 add a small integer (8 < N <= 16) to a register.
2273 Likewise for subqw. */
2274 if (TARGET_CPU32 && REG_P (operands[0]))
2276 if (INTVAL (operands[2]) > 8
2277 && INTVAL (operands[2]) <= 16)
2279 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2280 INTVAL (operands[2]) - 8);
2281 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2283 if (INTVAL (operands[2]) < -8
2284 && INTVAL (operands[2]) >= -16)
2286 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2287 - INTVAL (operands[2]) - 8);
2288 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2292 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2294 return \"lea (%c2,%0),%0\";
2296 return \"lea %0@(%c2),%0\";
2299 return \"add%.w %2,%0\";
2302 ;; These insns must use MATCH_DUP instead of the more expected
2303 ;; use of a matching constraint because the "output" here is also
2304 ;; an input, so you can't use the matching constraint. That also means
2305 ;; that you can't use the "%", so you need patterns with the matched
2306 ;; operand in both positions.
2309 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2310 (plus:HI (match_dup 0)
2311 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2315 if (GET_CODE (operands[1]) == CONST_INT)
2318 /* If the constant would be a negative number when interpreted as
2319 HImode, make it negative. This is usually, but not always, done
2320 elsewhere in the compiler. First check for constants out of range,
2321 which could confuse us. */
2323 if (INTVAL (operands[1]) >= 32768)
2324 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2325 INTVAL (operands[1]) - 65536);
2327 if (INTVAL (operands[1]) > 0
2328 && INTVAL (operands[1]) <= 8)
2329 return \"addq%.w %1,%0\";
2330 if (INTVAL (operands[1]) < 0
2331 && INTVAL (operands[1]) >= -8)
2333 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2334 - INTVAL (operands[1]));
2335 return \"subq%.w %1,%0\";
2337 /* On the CPU32 it is faster to use two addqw instructions to
2338 add a small integer (8 < N <= 16) to a register.
2339 Likewise for subqw. */
2340 if (TARGET_CPU32 && REG_P (operands[0]))
2342 if (INTVAL (operands[1]) > 8
2343 && INTVAL (operands[1]) <= 16)
2345 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2346 INTVAL (operands[1]) - 8);
2347 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2349 if (INTVAL (operands[1]) < -8
2350 && INTVAL (operands[1]) >= -16)
2352 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2353 - INTVAL (operands[1]) - 8);
2354 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2358 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2360 return \"lea (%c1,%0),%0\";
2362 return \"lea %0@(%c1),%0\";
2365 return \"add%.w %1,%0\";
2369 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2370 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2375 if (GET_CODE (operands[1]) == CONST_INT)
2378 /* If the constant would be a negative number when interpreted as
2379 HImode, make it negative. This is usually, but not always, done
2380 elsewhere in the compiler. First check for constants out of range,
2381 which could confuse us. */
2383 if (INTVAL (operands[1]) >= 32768)
2384 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2385 INTVAL (operands[1]) - 65536);
2387 if (INTVAL (operands[1]) > 0
2388 && INTVAL (operands[1]) <= 8)
2389 return \"addq%.w %1,%0\";
2390 if (INTVAL (operands[1]) < 0
2391 && INTVAL (operands[1]) >= -8)
2393 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2394 - INTVAL (operands[1]));
2395 return \"subq%.w %1,%0\";
2397 /* On the CPU32 it is faster to use two addqw instructions to
2398 add a small integer (8 < N <= 16) to a register.
2399 Likewise for subqw. */
2400 if (TARGET_CPU32 && REG_P (operands[0]))
2402 if (INTVAL (operands[1]) > 8
2403 && INTVAL (operands[1]) <= 16)
2405 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2406 INTVAL (operands[1]) - 8);
2407 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2409 if (INTVAL (operands[1]) < -8
2410 && INTVAL (operands[1]) >= -16)
2412 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2413 - INTVAL (operands[1]) - 8);
2414 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2418 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2420 return \"lea (%c1,%0),%0\";
2422 return \"lea %0@(%c1),%0\";
2425 return \"add%.w %1,%0\";
2428 (define_insn "addqi3"
2429 [(set (match_operand:QI 0 "general_operand" "=m,d")
2430 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2431 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2436 if (GET_CODE (operands[2]) == CONST_INT)
2438 if (INTVAL (operands[2]) >= 128)
2439 operands[2] = gen_rtx (CONST_INT, VOIDmode,
2440 INTVAL (operands[2]) - 256);
2442 if (INTVAL (operands[2]) > 0
2443 && INTVAL (operands[2]) <= 8)
2444 return \"addq%.b %2,%0\";
2445 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2447 operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
2448 return \"subq%.b %2,%0\";
2452 return \"add%.b %2,%0\";
2456 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2457 (plus:QI (match_dup 0)
2458 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2463 if (GET_CODE (operands[1]) == CONST_INT)
2465 if (INTVAL (operands[1]) >= 128)
2466 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2467 INTVAL (operands[1]) - 256);
2469 if (INTVAL (operands[1]) > 0
2470 && INTVAL (operands[1]) <= 8)
2471 return \"addq%.b %1,%0\";
2472 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2474 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2475 return \"subq%.b %1,%0\";
2479 return \"add%.b %1,%0\";
2483 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2484 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2490 if (GET_CODE (operands[1]) == CONST_INT)
2492 if (INTVAL (operands[1]) >= 128)
2493 operands[1] = gen_rtx (CONST_INT, VOIDmode,
2494 INTVAL (operands[1]) - 256);
2496 if (INTVAL (operands[1]) > 0
2497 && INTVAL (operands[1]) <= 8)
2498 return \"addq%.b %1,%0\";
2499 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2501 operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
2502 return \"subq%.b %1,%0\";
2506 return \"add%.b %1,%0\";
2509 (define_expand "adddf3"
2510 [(set (match_operand:DF 0 "general_operand" "")
2511 (plus:DF (match_operand:DF 1 "general_operand" "")
2512 (match_operand:DF 2 "general_operand" "")))]
2513 "TARGET_68881 || TARGET_FPA"
2517 [(set (match_operand:DF 0 "general_operand" "=x,y")
2518 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2519 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2523 if (rtx_equal_p (operands[0], operands[1]))
2524 return \"fpadd%.d %y2,%0\";
2525 if (rtx_equal_p (operands[0], operands[2]))
2526 return \"fpadd%.d %y1,%0\";
2527 if (which_alternative == 0)
2528 return \"fpadd3%.d %w2,%w1,%0\";
2529 return \"fpadd3%.d %x2,%x1,%0\";
2533 [(set (match_operand:DF 0 "general_operand" "=f")
2534 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2535 (match_operand:DF 1 "general_operand" "0")))]
2540 [(set (match_operand:DF 0 "general_operand" "=f")
2541 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2542 (match_operand:DF 1 "general_operand" "0")))]
2547 [(set (match_operand:DF 0 "general_operand" "=f")
2548 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2549 (match_operand:DF 1 "general_operand" "0")))]
2554 [(set (match_operand:DF 0 "general_operand" "=f")
2555 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2556 (match_operand:DF 2 "general_operand" "fmG")))]
2560 if (REG_P (operands[2]))
2561 return \"f%&add%.x %2,%0\";
2562 return \"f%&add%.d %f2,%0\";
2565 (define_expand "addsf3"
2566 [(set (match_operand:SF 0 "general_operand" "")
2567 (plus:SF (match_operand:SF 1 "general_operand" "")
2568 (match_operand:SF 2 "general_operand" "")))]
2569 "TARGET_68881 || TARGET_FPA"
2573 [(set (match_operand:SF 0 "general_operand" "=x,y")
2574 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2575 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2579 if (rtx_equal_p (operands[0], operands[1]))
2580 return \"fpadd%.s %w2,%0\";
2581 if (rtx_equal_p (operands[0], operands[2]))
2582 return \"fpadd%.s %w1,%0\";
2583 if (which_alternative == 0)
2584 return \"fpadd3%.s %w2,%w1,%0\";
2585 return \"fpadd3%.s %2,%1,%0\";
2589 [(set (match_operand:SF 0 "general_operand" "=f")
2590 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2591 (match_operand:SF 1 "general_operand" "0")))]
2596 [(set (match_operand:SF 0 "general_operand" "=f")
2597 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2598 (match_operand:SF 1 "general_operand" "0")))]
2603 [(set (match_operand:SF 0 "general_operand" "=f")
2604 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2605 (match_operand:SF 1 "general_operand" "0")))]
2610 [(set (match_operand:SF 0 "general_operand" "=f")
2611 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2612 (match_operand:SF 2 "general_operand" "fdmF")))]
2616 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2617 return \"f%$add%.x %2,%0\";
2618 return \"f%$add%.s %f2,%0\";
2621 ;; subtract instructions
2623 (define_insn "subdi_sexthishl32"
2624 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2625 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2626 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2628 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2633 if (ADDRESS_REG_P (operands[0]))
2634 return \"sub%.w %2,%0\";
2635 else if (ADDRESS_REG_P (operands[3]))
2636 return \"move%.w %2,%3\;sub%.l %3,%0\";
2638 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2641 (define_insn "subdi_dishl32"
2642 [(set (match_operand:DI 0 "general_operand" "+ro")
2643 (minus:DI (match_dup 0)
2644 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2650 if (GET_CODE (operands[1]) == REG)
2651 operands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2653 operands[1] = adj_offsettable_operand (operands[1], 4);
2654 return \"sub%.l %1,%0\";
2657 (define_insn "subdi3"
2658 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2659 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2660 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2661 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2665 if (DATA_REG_P (operands[0]))
2667 if (DATA_REG_P (operands[2]))
2668 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2669 else if (GET_CODE (operands[2]) == MEM
2670 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2672 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2676 if (GET_CODE (operands[2]) == REG)
2677 operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
2678 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2680 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2681 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2683 else if (GET_CODE (operands[2]) == CONST_INT)
2685 operands[1] = operands[2];
2686 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2689 operands[1] = adj_offsettable_operand (operands[2], 4);
2690 /* TODO : for consts, optimize move and sub */
2691 return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
2694 else if (GET_CODE (operands[0]) == MEM)
2696 if (GET_CODE (operands[2]) == MEM
2697 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2698 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2700 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2702 operands[1] = gen_rtx (MEM, SImode,
2703 gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
2704 gen_rtx (CONST_INT, VOIDmode, -8)));
2705 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2707 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2709 operands[1] = XEXP(operands[0], 0);
2710 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2714 operands[1] = adj_offsettable_operand (operands[0], 4);
2715 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2720 (define_insn "subsi3"
2721 [(set (match_operand:SI 0 "general_operand" "=m,r")
2722 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2723 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2728 [(set (match_operand:SI 0 "general_operand" "=a")
2729 (minus:SI (match_operand:SI 1 "general_operand" "0")
2731 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2735 (define_insn "subhi3"
2736 [(set (match_operand:HI 0 "general_operand" "=m,r")
2737 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2738 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2743 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2744 (minus:HI (match_dup 0)
2745 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2749 (define_insn "subqi3"
2750 [(set (match_operand:QI 0 "general_operand" "=m,d")
2751 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2752 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2757 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2758 (minus:QI (match_dup 0)
2759 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2763 (define_expand "subdf3"
2764 [(set (match_operand:DF 0 "general_operand" "")
2765 (minus:DF (match_operand:DF 1 "general_operand" "")
2766 (match_operand:DF 2 "general_operand" "")))]
2767 "TARGET_68881 || TARGET_FPA"
2771 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2772 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2773 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2777 if (rtx_equal_p (operands[0], operands[2]))
2778 return \"fprsub%.d %y1,%0\";
2779 if (rtx_equal_p (operands[0], operands[1]))
2780 return \"fpsub%.d %y2,%0\";
2781 if (which_alternative == 0)
2782 return \"fpsub3%.d %w2,%w1,%0\";
2783 return \"fpsub3%.d %x2,%x1,%0\";
2787 [(set (match_operand:DF 0 "general_operand" "=f")
2788 (minus:DF (match_operand:DF 1 "general_operand" "0")
2789 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2794 [(set (match_operand:DF 0 "general_operand" "=f")
2795 (minus:DF (match_operand:DF 1 "general_operand" "0")
2796 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2801 [(set (match_operand:DF 0 "general_operand" "=f")
2802 (minus:DF (match_operand:DF 1 "general_operand" "0")
2803 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2808 [(set (match_operand:DF 0 "general_operand" "=f")
2809 (minus:DF (match_operand:DF 1 "general_operand" "0")
2810 (match_operand:DF 2 "general_operand" "fmG")))]
2814 if (REG_P (operands[2]))
2815 return \"f%&sub%.x %2,%0\";
2816 return \"f%&sub%.d %f2,%0\";
2819 (define_expand "subsf3"
2820 [(set (match_operand:SF 0 "general_operand" "")
2821 (minus:SF (match_operand:SF 1 "general_operand" "")
2822 (match_operand:SF 2 "general_operand" "")))]
2823 "TARGET_68881 || TARGET_FPA"
2827 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2828 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2829 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2833 if (rtx_equal_p (operands[0], operands[2]))
2834 return \"fprsub%.s %w1,%0\";
2835 if (rtx_equal_p (operands[0], operands[1]))
2836 return \"fpsub%.s %w2,%0\";
2837 if (which_alternative == 0)
2838 return \"fpsub3%.s %w2,%w1,%0\";
2839 return \"fpsub3%.s %2,%1,%0\";
2843 [(set (match_operand:SF 0 "general_operand" "=f")
2844 (minus:SF (match_operand:SF 1 "general_operand" "0")
2845 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2850 [(set (match_operand:SF 0 "general_operand" "=f")
2851 (minus:SF (match_operand:SF 1 "general_operand" "0")
2852 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2857 [(set (match_operand:SF 0 "general_operand" "=f")
2858 (minus:SF (match_operand:SF 1 "general_operand" "0")
2859 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2864 [(set (match_operand:SF 0 "general_operand" "=f")
2865 (minus:SF (match_operand:SF 1 "general_operand" "0")
2866 (match_operand:SF 2 "general_operand" "fdmF")))]
2870 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2871 return \"f%$sub%.x %2,%0\";
2872 return \"f%$sub%.s %f2,%0\";
2875 ;; multiply instructions
2877 (define_insn "mulhi3"
2878 [(set (match_operand:HI 0 "general_operand" "=d")
2879 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2880 (match_operand:HI 2 "general_operand" "dmn")))]
2884 #if defined(MOTOROLA) && !defined(CRDS)
2885 return \"muls%.w %2,%0\";
2887 return \"muls %2,%0\";
2891 (define_insn "mulhisi3"
2892 [(set (match_operand:SI 0 "general_operand" "=d")
2893 (mult:SI (sign_extend:SI
2894 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2896 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2900 #if defined(MOTOROLA) && !defined(CRDS)
2901 return \"muls%.w %2,%0\";
2903 return \"muls %2,%0\";
2908 [(set (match_operand:SI 0 "general_operand" "=d")
2909 (mult:SI (sign_extend:SI
2910 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2911 (match_operand:SI 2 "const_int_operand" "n")))]
2912 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2915 #if defined(MOTOROLA) && !defined(CRDS)
2916 return \"muls%.w %2,%0\";
2918 return \"muls %2,%0\";
2922 (define_expand "mulsi3"
2923 [(set (match_operand:SI 0 "general_operand" "")
2924 (mult:SI (match_operand:SI 1 "general_operand" "")
2925 (match_operand:SI 2 "general_operand" "")))]
2926 "TARGET_68020 || TARGET_5200"
2930 [(set (match_operand:SI 0 "general_operand" "=d")
2931 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2932 (match_operand:SI 2 "general_operand" "dmsK")))]
2937 [(set (match_operand:SI 0 "general_operand" "=d")
2938 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2939 (match_operand:SI 2 "general_operand" "d<Q>")))]
2943 (define_insn "umulhisi3"
2944 [(set (match_operand:SI 0 "general_operand" "=d")
2945 (mult:SI (zero_extend:SI
2946 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2948 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2952 #if defined(MOTOROLA) && !defined(CRDS)
2953 return \"mulu%.w %2,%0\";
2955 return \"mulu %2,%0\";
2960 [(set (match_operand:SI 0 "general_operand" "=d")
2961 (mult:SI (zero_extend:SI
2962 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2963 (match_operand:SI 2 "const_int_operand" "n")))]
2964 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
2967 #if defined(MOTOROLA) && !defined(CRDS)
2968 return \"mulu%.w %2,%0\";
2970 return \"mulu %2,%0\";
2974 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
2975 ;; proper matching constraint. This is because the matching is between
2976 ;; the high-numbered word of the DImode operand[0] and operand[1].
2977 (define_expand "umulsidi3"
2979 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
2980 (mult:SI (match_operand:SI 1 "register_operand" "")
2981 (match_operand:SI 2 "nonimmediate_operand" "")))
2982 (set (subreg:SI (match_dup 0) 0)
2983 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2984 (zero_extend:DI (match_dup 2)))
2985 (const_int 32))))])]
2986 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2990 [(set (match_operand:SI 0 "register_operand" "=d")
2991 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2992 (match_operand:SI 2 "nonimmediate_operand" "dm")))
2993 (set (match_operand:SI 3 "register_operand" "=d")
2994 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2995 (zero_extend:DI (match_dup 2)))
2997 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3000 ; Match immediate case. For 2.4 only match things < 2^31.
3001 ; It's tricky with larger values in these patterns since we need to match
3002 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3005 [(set (match_operand:SI 0 "register_operand" "=d")
3006 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3007 (match_operand:SI 2 "const_int_operand" "n")))
3008 (set (match_operand:SI 3 "register_operand" "=d")
3009 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3012 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3013 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3016 (define_expand "mulsidi3"
3018 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3019 (mult:SI (match_operand:SI 1 "register_operand" "")
3020 (match_operand:SI 2 "nonimmediate_operand" "")))
3021 (set (subreg:SI (match_dup 0) 0)
3022 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3023 (sign_extend:DI (match_dup 2)))
3024 (const_int 32))))])]
3025 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3029 [(set (match_operand:SI 0 "register_operand" "=d")
3030 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3031 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3032 (set (match_operand:SI 3 "register_operand" "=d")
3033 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3034 (sign_extend:DI (match_dup 2)))
3036 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3040 [(set (match_operand:SI 0 "register_operand" "=d")
3041 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3042 (match_operand:SI 2 "const_sint32_operand" "")))
3043 (set (match_operand:SI 3 "register_operand" "=d")
3044 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3047 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3050 (define_expand "umulsi3_highpart"
3052 [(set (match_operand:SI 0 "register_operand" "")
3055 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3056 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3058 (clobber (match_dup 3))])]
3059 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3062 operands[3] = gen_reg_rtx (SImode);
3063 if (GET_CODE (operands[2]) == CONST_INT
3064 || GET_CODE (operands[2]) == CONST_DOUBLE)
3066 if (! const_uint32_operand (operands[2], VOIDmode))
3068 /* We have to adjust the operand order for the matching constraints. */
3069 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3070 operands[1], operands[2]));
3076 [(set (match_operand:SI 0 "register_operand" "=d")
3079 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3080 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3082 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3083 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3086 (define_insn "const_umulsi3_highpart"
3087 [(set (match_operand:SI 0 "register_operand" "=d")
3090 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3091 (match_operand 3 "const_uint32_operand" ""))
3093 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3094 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3097 (define_expand "smulsi3_highpart"
3099 [(set (match_operand:SI 0 "register_operand" "")
3102 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3103 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3105 (clobber (match_dup 3))])]
3106 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3109 operands[3] = gen_reg_rtx (SImode);
3110 if (GET_CODE (operands[2]) == CONST_INT
3111 || GET_CODE (operands[2]) == CONST_DOUBLE)
3113 if (! const_sint32_operand (operands[2], VOIDmode))
3115 /* We have to adjust the operand order for the matching constraints. */
3116 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3117 operands[1], operands[2]));
3123 [(set (match_operand:SI 0 "register_operand" "=d")
3126 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3127 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3129 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3130 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3133 (define_insn "const_smulsi3_highpart"
3134 [(set (match_operand:SI 0 "register_operand" "=d")
3137 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3138 (match_operand 3 "const_sint32_operand" ""))
3140 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3141 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3144 (define_expand "muldf3"
3145 [(set (match_operand:DF 0 "general_operand" "")
3146 (mult:DF (match_operand:DF 1 "general_operand" "")
3147 (match_operand:DF 2 "general_operand" "")))]
3148 "TARGET_68881 || TARGET_FPA"
3152 [(set (match_operand:DF 0 "general_operand" "=x,y")
3153 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3154 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3158 if (rtx_equal_p (operands[1], operands[2]))
3159 return \"fpsqr%.d %y1,%0\";
3160 if (rtx_equal_p (operands[0], operands[1]))
3161 return \"fpmul%.d %y2,%0\";
3162 if (rtx_equal_p (operands[0], operands[2]))
3163 return \"fpmul%.d %y1,%0\";
3164 if (which_alternative == 0)
3165 return \"fpmul3%.d %w2,%w1,%0\";
3166 return \"fpmul3%.d %x2,%x1,%0\";
3170 [(set (match_operand:DF 0 "general_operand" "=f")
3171 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3172 (match_operand:DF 1 "general_operand" "0")))]
3177 [(set (match_operand:DF 0 "general_operand" "=f")
3178 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3179 (match_operand:DF 1 "general_operand" "0")))]
3184 [(set (match_operand:DF 0 "general_operand" "=f")
3185 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3186 (match_operand:DF 1 "general_operand" "0")))]
3191 [(set (match_operand:DF 0 "general_operand" "=f")
3192 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3193 (match_operand:DF 2 "general_operand" "fmG")))]
3197 if (GET_CODE (operands[2]) == CONST_DOUBLE
3198 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3200 int i = floating_exact_log2 (operands[2]);
3201 operands[2] = gen_rtx (CONST_INT, VOIDmode, i);
3202 return \"fscale%.l %2,%0\";
3204 if (REG_P (operands[2]))
3205 return \"f%&mul%.x %2,%0\";
3206 return \"f%&mul%.d %f2,%0\";
3209 (define_expand "mulsf3"
3210 [(set (match_operand:SF 0 "general_operand" "")
3211 (mult:SF (match_operand:SF 1 "general_operand" "")
3212 (match_operand:SF 2 "general_operand" "")))]
3213 "TARGET_68881 || TARGET_FPA"
3217 [(set (match_operand:SF 0 "general_operand" "=x,y")
3218 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3219 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3223 if (rtx_equal_p (operands[1], operands[2]))
3224 return \"fpsqr%.s %w1,%0\";
3225 if (rtx_equal_p (operands[0], operands[1]))
3226 return \"fpmul%.s %w2,%0\";
3227 if (rtx_equal_p (operands[0], operands[2]))
3228 return \"fpmul%.s %w1,%0\";
3229 if (which_alternative == 0)
3230 return \"fpmul3%.s %w2,%w1,%0\";
3231 return \"fpmul3%.s %2,%1,%0\";
3235 [(set (match_operand:SF 0 "general_operand" "=f")
3236 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3237 (match_operand:SF 1 "general_operand" "0")))]
3241 return (TARGET_68040_ONLY
3242 ? \"fsmul%.l %2,%0\"
3243 : \"fsglmul%.l %2,%0\");
3247 [(set (match_operand:SF 0 "general_operand" "=f")
3248 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3249 (match_operand:SF 1 "general_operand" "0")))]
3253 return (TARGET_68040_ONLY
3254 ? \"fsmul%.w %2,%0\"
3255 : \"fsglmul%.w %2,%0\");
3259 [(set (match_operand:SF 0 "general_operand" "=f")
3260 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3261 (match_operand:SF 1 "general_operand" "0")))]
3265 return (TARGET_68040_ONLY
3266 ? \"fsmul%.b %2,%0\"
3267 : \"fsglmul%.b %2,%0\");
3271 [(set (match_operand:SF 0 "general_operand" "=f")
3272 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3273 (match_operand:SF 2 "general_operand" "fdmF")))]
3277 #ifdef FSGLMUL_USE_S
3278 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3279 return (TARGET_68040_ONLY
3280 ? \"fsmul%.s %2,%0\"
3281 : \"fsglmul%.s %2,%0\");
3283 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3284 return (TARGET_68040_ONLY
3285 ? \"fsmul%.x %2,%0\"
3286 : \"fsglmul%.x %2,%0\");
3288 return (TARGET_68040_ONLY
3289 ? \"fsmul%.s %f2,%0\"
3290 : \"fsglmul%.s %f2,%0\");
3293 ;; divide instructions
3295 (define_expand "divdf3"
3296 [(set (match_operand:DF 0 "general_operand" "")
3297 (div:DF (match_operand:DF 1 "general_operand" "")
3298 (match_operand:DF 2 "general_operand" "")))]
3299 "TARGET_68881 || TARGET_FPA"
3303 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3304 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3305 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3309 if (rtx_equal_p (operands[0], operands[2]))
3310 return \"fprdiv%.d %y1,%0\";
3311 if (rtx_equal_p (operands[0], operands[1]))
3312 return \"fpdiv%.d %y2,%0\";
3313 if (which_alternative == 0)
3314 return \"fpdiv3%.d %w2,%w1,%0\";
3315 return \"fpdiv3%.d %x2,%x1,%x0\";
3319 [(set (match_operand:DF 0 "general_operand" "=f")
3320 (div:DF (match_operand:DF 1 "general_operand" "0")
3321 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3326 [(set (match_operand:DF 0 "general_operand" "=f")
3327 (div:DF (match_operand:DF 1 "general_operand" "0")
3328 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3333 [(set (match_operand:DF 0 "general_operand" "=f")
3334 (div:DF (match_operand:DF 1 "general_operand" "0")
3335 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3340 [(set (match_operand:DF 0 "general_operand" "=f")
3341 (div:DF (match_operand:DF 1 "general_operand" "0")
3342 (match_operand:DF 2 "general_operand" "fmG")))]
3346 if (REG_P (operands[2]))
3347 return \"f%&div%.x %2,%0\";
3348 return \"f%&div%.d %f2,%0\";
3351 (define_expand "divsf3"
3352 [(set (match_operand:SF 0 "general_operand" "")
3353 (div:SF (match_operand:SF 1 "general_operand" "")
3354 (match_operand:SF 2 "general_operand" "")))]
3355 "TARGET_68881 || TARGET_FPA"
3359 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3360 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3361 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3365 if (rtx_equal_p (operands[0], operands[1]))
3366 return \"fpdiv%.s %w2,%0\";
3367 if (rtx_equal_p (operands[0], operands[2]))
3368 return \"fprdiv%.s %w1,%0\";
3369 if (which_alternative == 0)
3370 return \"fpdiv3%.s %w2,%w1,%0\";
3371 return \"fpdiv3%.s %2,%1,%0\";
3375 [(set (match_operand:SF 0 "general_operand" "=f")
3376 (div:SF (match_operand:SF 1 "general_operand" "0")
3377 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3381 return (TARGET_68040_ONLY
3382 ? \"fsdiv%.l %2,%0\"
3383 : \"fsgldiv%.l %2,%0\");
3387 [(set (match_operand:SF 0 "general_operand" "=f")
3388 (div:SF (match_operand:SF 1 "general_operand" "0")
3389 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3393 return (TARGET_68040_ONLY
3394 ? \"fsdiv%.w %2,%0\"
3395 : \"fsgldiv%.w %2,%0\");
3399 [(set (match_operand:SF 0 "general_operand" "=f")
3400 (div:SF (match_operand:SF 1 "general_operand" "0")
3401 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3405 return (TARGET_68040_ONLY
3406 ? \"fsdiv%.b %2,%0\"
3407 : \"fsgldiv%.b %2,%0\");
3411 [(set (match_operand:SF 0 "general_operand" "=f")
3412 (div:SF (match_operand:SF 1 "general_operand" "0")
3413 (match_operand:SF 2 "general_operand" "fdmF")))]
3417 #ifdef FSGLDIV_USE_S
3418 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3419 return (TARGET_68040_ONLY
3420 ? \"fsdiv%.s %2,%0\"
3421 : \"fsgldiv%.s %2,%0\");
3423 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3424 return (TARGET_68040_ONLY
3425 ? \"fsdiv%.x %2,%0\"
3426 : \"fsgldiv%.x %2,%0\");
3428 return (TARGET_68040_ONLY
3429 ? \"fsdiv%.s %f2,%0\"
3430 : \"fsgldiv%.s %f2,%0\");
3433 ;; Remainder instructions.
3435 (define_insn "divmodsi4"
3436 [(set (match_operand:SI 0 "general_operand" "=d")
3437 (div:SI (match_operand:SI 1 "general_operand" "0")
3438 (match_operand:SI 2 "general_operand" "dmsK")))
3439 (set (match_operand:SI 3 "general_operand" "=d")
3440 (mod:SI (match_dup 1) (match_dup 2)))]
3441 "TARGET_68020 && !TARGET_5200"
3444 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3445 return \"divs%.l %2,%0\";
3447 return \"divsl%.l %2,%3:%0\";
3450 (define_insn "udivmodsi4"
3451 [(set (match_operand:SI 0 "general_operand" "=d")
3452 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3453 (match_operand:SI 2 "general_operand" "dmsK")))
3454 (set (match_operand:SI 3 "general_operand" "=d")
3455 (umod:SI (match_dup 1) (match_dup 2)))]
3456 "TARGET_68020 && !TARGET_5200"
3459 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3460 return \"divu%.l %2,%0\";
3462 return \"divul%.l %2,%3:%0\";
3465 (define_insn "divmodhi4"
3466 [(set (match_operand:HI 0 "general_operand" "=d")
3467 (div:HI (match_operand:HI 1 "general_operand" "0")
3468 (match_operand:HI 2 "general_operand" "dmsK")))
3469 (set (match_operand:HI 3 "general_operand" "=d")
3470 (mod:HI (match_dup 1) (match_dup 2)))]
3475 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3477 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3479 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3482 return \"move%.l %0,%3\;swap %3\";
3488 (define_insn "udivmodhi4"
3489 [(set (match_operand:HI 0 "general_operand" "=d")
3490 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3491 (match_operand:HI 2 "general_operand" "dmsK")))
3492 (set (match_operand:HI 3 "general_operand" "=d")
3493 (umod:HI (match_dup 1) (match_dup 2)))]
3498 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3500 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3502 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3505 return \"move%.l %0,%3\;swap %3\";
3511 ;; logical-and instructions
3513 ;; "anddi3" is mainly here to help combine().
3514 (define_insn "anddi3"
3515 [(set (match_operand:DI 0 "general_operand" "=o,d")
3516 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3517 (match_operand:DI 2 "general_operand" "dn,don")))]
3522 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3523 if (GET_CODE (operands[2]) == CONST_DOUBLE
3524 || GET_CODE (operands[2]) == CONST_INT)
3528 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3530 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3531 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3536 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3538 switch (INTVAL (hi))
3541 output_asm_insn (\"clr%.l %0\", operands);
3549 xoperands[0] = operands[0];
3551 output_asm_insn (output_andsi3 (xoperands), xoperands);
3554 if (GET_CODE (operands[0]) == REG)
3555 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3557 operands[0] = adj_offsettable_operand (operands[0], 4);
3558 switch (INTVAL (lo))
3561 output_asm_insn (\"clr%.l %0\", operands);
3569 xoperands[0] = operands[0];
3571 output_asm_insn (output_andsi3 (xoperands), xoperands);
3576 if (GET_CODE (operands[0]) != REG)
3578 operands[1] = adj_offsettable_operand (operands[0], 4);
3579 return \"and%.l %2,%0\;and%.l %R2,%1\";
3581 if (GET_CODE (operands[2]) != REG)
3583 operands[1] = adj_offsettable_operand (operands[2], 4);
3584 return \"and%.l %2,%0\;and%.l %1,%R0\";
3586 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3589 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3590 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3591 ;; can't allocate pseudos into it.
3593 (define_expand "andsi3"
3594 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3595 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3596 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3600 (define_insn "andsi3_internal"
3601 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3602 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3603 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3607 return output_andsi3 (operands);
3610 (define_insn "andsi3_5200"
3611 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3612 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3613 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3617 (define_insn "andhi3"
3618 [(set (match_operand:HI 0 "general_operand" "=m,d")
3619 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3620 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3625 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3626 (and:HI (match_dup 0)
3627 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3632 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3633 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3638 (define_insn "andqi3"
3639 [(set (match_operand:QI 0 "general_operand" "=m,d")
3640 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3641 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3646 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3647 (and:QI (match_dup 0)
3648 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3653 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3654 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3659 ;; inclusive-or instructions
3661 ;; "iordi3" is mainly here to help combine().
3662 (define_insn "iordi3"
3663 [(set (match_operand:DI 0 "general_operand" "=o,d")
3664 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3665 (match_operand:DI 2 "general_operand" "dn,don")))]
3670 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3671 if (GET_CODE (operands[2]) == CONST_DOUBLE
3672 || GET_CODE (operands[2]) == CONST_INT)
3676 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3678 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3679 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3684 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3686 switch (INTVAL (hi))
3691 /* FIXME : a scratch register would be welcome here if operand[0]
3692 is not a register */
3693 output_asm_insn (\"move%.l %#-1,%0\", operands);
3699 xoperands[0] = operands[0];
3701 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3704 if (GET_CODE (operands[0]) == REG)
3705 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3707 operands[0] = adj_offsettable_operand (operands[0], 4);
3708 switch (INTVAL (lo))
3713 /* FIXME : a scratch register would be welcome here if operand[0]
3714 is not a register */
3715 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3721 xoperands[0] = operands[0];
3723 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3728 if (GET_CODE (operands[0]) != REG)
3730 operands[1] = adj_offsettable_operand (operands[0], 4);
3731 return \"or%.l %2,%0\;or%.l %R2,%1\";
3733 if (GET_CODE (operands[2]) != REG)
3735 operands[1] = adj_offsettable_operand (operands[2], 4);
3736 return \"or%.l %2,%0\;or%.l %1,%R0\";
3738 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3741 (define_expand "iorsi3"
3742 [(set (match_operand:SI 0 "general_operand" "")
3743 (ior:SI (match_operand:SI 1 "general_operand" "")
3744 (match_operand:SI 2 "general_operand" "")))]
3748 (define_insn "iorsi3_internal"
3749 [(set (match_operand:SI 0 "general_operand" "=m,d")
3750 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3751 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3755 return output_iorsi3 (operands);
3758 (define_insn "iorsi3_5200"
3759 [(set (match_operand:SI 0 "general_operand" "=m,d")
3760 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3761 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3765 (define_insn "iorhi3"
3766 [(set (match_operand:HI 0 "general_operand" "=m,d")
3767 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3768 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3773 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3774 (ior:HI (match_dup 0)
3775 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3780 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3781 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3786 (define_insn "iorqi3"
3787 [(set (match_operand:QI 0 "general_operand" "=m,d")
3788 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3789 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3794 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3795 (ior:QI (match_dup 0)
3796 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3801 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3802 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3807 ;; On all 68k models, this makes faster code in a special case.
3808 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3810 ;; ??? This pattern can not work as written, because it fails if operand 0
3811 ;; and operand 1 are the same register. This can happen for alternative 1.
3812 ;; This will still fail even if an early clobber is added to the output
3813 ;; for alternative 1. This is because reload may satisfy the matching
3814 ;; constraint by forcing the output to use exactly the same register as
3815 ;; operand 2, without noticing that this then causes a conflict with operand 1.
3816 ;; Possible fix: check for operand 0/1 overlap, and emit correct but slower
3817 ;; code. This should be rare if the early clobber is added.
3819 (define_insn "iorsi_zexthi_ashl16"
3820 [(set (match_operand:SI 0 "general_operand" "=&d,d")
3821 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
3822 (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
3828 if (GET_CODE (operands[2]) != REG)
3830 operands[2] = adj_offsettable_operand (operands[2], 2);
3831 output_asm_insn (\"move%.w %2,%0\", operands);
3833 return \"swap %0\;mov%.w %1,%0\";
3837 [(set (match_operand:SI 0 "general_operand" "=o,d")
3838 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3839 (match_operand:SI 2 "general_operand" "0,0")))]
3846 byte_mode = (GET_MODE(operands[1]) == QImode);
3847 if (GET_CODE (operands[0]) == MEM)
3848 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3850 return \"or%.b %1,%0\";
3852 return \"or%.w %1,%0\";
3857 ;; "xordi3" is mainly here to help combine().
3858 (define_insn "xordi3"
3859 [(set (match_operand:DI 0 "general_operand" "=od")
3860 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3861 (match_operand:DI 2 "general_operand" "dn")))]
3866 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3867 if (GET_CODE (operands[2]) == CONST_DOUBLE
3868 || GET_CODE (operands[2]) == CONST_INT)
3872 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3874 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3875 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3880 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3882 switch (INTVAL (hi))
3887 output_asm_insn (\"not%.l %0\", operands);
3890 /* FIXME : a scratch register would be welcome here if
3891 -128 <= INTVAL (hi) < -1 */
3895 xoperands[0] = operands[0];
3897 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3900 if (GET_CODE (operands[0]) == REG)
3901 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3903 operands[0] = adj_offsettable_operand (operands[0], 4);
3904 switch (INTVAL (lo))
3909 output_asm_insn (\"not%.l %0\", operands);
3912 /* FIXME : a scratch register would be welcome here if
3913 -128 <= INTVAL (lo) < -1 */
3915 /* FIXME : this should be merged with xorsi3 */
3919 xoperands[0] = operands[0];
3921 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3926 if (GET_CODE (operands[0]) != REG)
3928 operands[1] = adj_offsettable_operand (operands[0], 4);
3929 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
3931 if (GET_CODE (operands[2]) != REG)
3933 operands[1] = adj_offsettable_operand (operands[2], 4);
3934 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
3936 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
3939 (define_expand "xorsi3"
3940 [(set (match_operand:SI 0 "general_operand" "")
3941 (xor:SI (match_operand:SI 1 "general_operand" "")
3942 (match_operand:SI 2 "general_operand" "")))]
3946 (define_insn "xorsi3_internal"
3947 [(set (match_operand:SI 0 "general_operand" "=do,m")
3948 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3949 (match_operand:SI 2 "general_operand" "di,dKs")))]
3953 return output_xorsi3 (operands);
3956 (define_insn "xorsi3_5200"
3957 [(set (match_operand:SI 0 "general_operand" "=dm,d")
3958 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
3959 (match_operand:SI 2 "general_operand" "d,Ks")))]
3963 (define_insn "xorhi3"
3964 [(set (match_operand:HI 0 "general_operand" "=dm")
3965 (xor:HI (match_operand:HI 1 "general_operand" "%0")
3966 (match_operand:HI 2 "general_operand" "dn")))]
3971 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3972 (xor:HI (match_dup 0)
3973 (match_operand:HI 1 "general_operand" "dn")))]
3978 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
3979 (xor:HI (match_operand:HI 1 "general_operand" "dn")
3984 (define_insn "xorqi3"
3985 [(set (match_operand:QI 0 "general_operand" "=dm")
3986 (xor:QI (match_operand:QI 1 "general_operand" "%0")
3987 (match_operand:QI 2 "general_operand" "dn")))]
3992 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
3993 (xor:QI (match_dup 0)
3994 (match_operand:QI 1 "general_operand" "dn")))]
3999 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4000 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4005 ;; negation instructions
4007 (define_expand "negdi2"
4008 [(set (match_operand:DI 0 "general_operand" "")
4009 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4014 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4016 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4020 (define_insn "negdi2_internal"
4021 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4022 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4026 if (which_alternative == 0)
4027 return \"neg%.l %0\;negx%.l %0\";
4028 if (GET_CODE (operands[0]) == REG)
4029 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4031 operands[1] = adj_offsettable_operand (operands[0], 4);
4032 if (ADDRESS_REG_P (operands[0]))
4033 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4035 return \"neg%.l %1\;negx%.l %0\";
4038 (define_insn "negdi2_5200"
4039 [(set (match_operand:DI 0 "general_operand" "=d")
4040 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4044 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4045 return \"neg%.l %1\;negx%.l %0\";
4048 (define_expand "negsi2"
4049 [(set (match_operand:SI 0 "general_operand" "")
4050 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4055 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4057 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4061 (define_insn "negsi2_internal"
4062 [(set (match_operand:SI 0 "general_operand" "=dm")
4063 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4067 (define_insn "negsi2_5200"
4068 [(set (match_operand:SI 0 "general_operand" "=d")
4069 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4073 (define_insn "neghi2"
4074 [(set (match_operand:HI 0 "general_operand" "=dm")
4075 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4080 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4081 (neg:HI (match_dup 0)))]
4085 (define_insn "negqi2"
4086 [(set (match_operand:QI 0 "general_operand" "=dm")
4087 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4092 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4093 (neg:QI (match_dup 0)))]
4097 ;; If using software floating point, just flip the sign bit.
4099 (define_expand "negsf2"
4100 [(set (match_operand:SF 0 "general_operand" "")
4101 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4105 if (!TARGET_FPA && !TARGET_68881)
4110 target = operand_subword_force (operands[0], 0, SFmode);
4111 result = expand_binop (SImode, xor_optab,
4112 operand_subword_force (operands[1], 0, SFmode),
4113 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4117 if (result != target)
4118 emit_move_insn (result, target);
4120 /* Make a place for REG_EQUAL. */
4121 emit_move_insn (operands[0], operands[0]);
4127 [(set (match_operand:SF 0 "general_operand" "=x,y")
4128 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4133 [(set (match_operand:SF 0 "general_operand" "=f,d")
4134 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4138 if (DATA_REG_P (operands[0]))
4140 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4141 return \"bchg %1,%0\";
4143 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4144 return \"f%$neg%.x %1,%0\";
4145 return \"f%$neg%.s %f1,%0\";
4148 (define_expand "negdf2"
4149 [(set (match_operand:DF 0 "general_operand" "")
4150 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4154 if (!TARGET_FPA && !TARGET_68881)
4161 target = operand_subword (operands[0], 0, 1, DFmode);
4162 result = expand_binop (SImode, xor_optab,
4163 operand_subword_force (operands[1], 0, DFmode),
4164 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4168 if (result != target)
4169 emit_move_insn (result, target);
4171 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4172 operand_subword_force (operands[1], 1, DFmode));
4174 insns = get_insns ();
4177 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4183 [(set (match_operand:DF 0 "general_operand" "=x,y")
4184 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4189 [(set (match_operand:DF 0 "general_operand" "=f,d")
4190 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4194 if (DATA_REG_P (operands[0]))
4196 operands[1] = gen_rtx (CONST_INT, VOIDmode, 31);
4197 return \"bchg %1,%0\";
4199 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4200 return \"f%&neg%.x %1,%0\";
4201 return \"f%&neg%.d %f1,%0\";
4204 ;; Sqrt instruction for the 68881
4206 (define_insn "sqrtsf2"
4207 [(set (match_operand:SF 0 "general_operand" "=f")
4208 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4212 if (FP_REG_P (operands[1]))
4213 return \"f%$sqrt%.x %1,%0\";
4215 return \"f%$sqrt%.s %1,%0\";
4218 (define_insn "sqrtdf2"
4219 [(set (match_operand:DF 0 "general_operand" "=f")
4220 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4224 if (FP_REG_P (operands[1]))
4225 return \"f%&sqrt%.x %1,%0\";
4227 return \"f%&sqrt%.d %1,%0\";
4230 ;; Absolute value instructions
4231 ;; If using software floating point, just zero the sign bit.
4233 (define_expand "abssf2"
4234 [(set (match_operand:SF 0 "general_operand" "")
4235 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4239 if (!TARGET_FPA && !TARGET_68881)
4244 target = operand_subword_force (operands[0], 0, SFmode);
4245 result = expand_binop (SImode, and_optab,
4246 operand_subword_force (operands[1], 0, SFmode),
4247 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4251 if (result != target)
4252 emit_move_insn (result, target);
4254 /* Make a place for REG_EQUAL. */
4255 emit_move_insn (operands[0], operands[0]);
4261 [(set (match_operand:SF 0 "general_operand" "=x,y")
4262 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4267 [(set (match_operand:SF 0 "general_operand" "=f")
4268 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4272 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4273 return \"f%$abs%.x %1,%0\";
4274 return \"f%$abs%.s %f1,%0\";
4277 (define_expand "absdf2"
4278 [(set (match_operand:DF 0 "general_operand" "")
4279 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4283 if (!TARGET_FPA && !TARGET_68881)
4290 target = operand_subword (operands[0], 0, 1, DFmode);
4291 result = expand_binop (SImode, and_optab,
4292 operand_subword_force (operands[1], 0, DFmode),
4293 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4297 if (result != target)
4298 emit_move_insn (result, target);
4300 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4301 operand_subword_force (operands[1], 1, DFmode));
4303 insns = get_insns ();
4306 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4312 [(set (match_operand:DF 0 "general_operand" "=x,y")
4313 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4318 [(set (match_operand:DF 0 "general_operand" "=f")
4319 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4323 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4324 return \"f%&abs%.x %1,%0\";
4325 return \"f%&abs%.d %f1,%0\";
4328 ;; one complement instructions
4330 ;; "one_cmpldi2" is mainly here to help combine().
4331 (define_insn "one_cmpldi2"
4332 [(set (match_operand:DI 0 "general_operand" "=dm")
4333 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4338 if (GET_CODE (operands[0]) == REG)
4339 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4340 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4341 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4342 operands[1] = operands[0];
4344 operands[1] = adj_offsettable_operand (operands[0], 4);
4345 return \"not%.l %1\;not%.l %0\";
4348 (define_expand "one_cmplsi2"
4349 [(set (match_operand:SI 0 "general_operand" "")
4350 (not:SI (match_operand:SI 1 "general_operand" "")))]
4355 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4357 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4361 (define_insn "one_cmplsi2_internal"
4362 [(set (match_operand:SI 0 "general_operand" "=dm")
4363 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4367 (define_insn "one_cmplsi2_5200"
4368 [(set (match_operand:SI 0 "general_operand" "=d")
4369 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4373 (define_insn "one_cmplhi2"
4374 [(set (match_operand:HI 0 "general_operand" "=dm")
4375 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4380 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4381 (not:HI (match_dup 0)))]
4385 (define_insn "one_cmplqi2"
4386 [(set (match_operand:QI 0 "general_operand" "=dm")
4387 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4392 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4393 (not:QI (match_dup 0)))]
4397 ;; arithmetic shift instructions
4398 ;; We don't need the shift memory by 1 bit instruction
4400 (define_insn "ashldi_extsi"
4401 [(set (match_operand:DI 0 "general_operand" "=ro")
4403 (match_operator:DI 2 "extend_operator"
4404 [(match_operand:SI 1 "general_operand" "rm")])
4410 if (GET_CODE (operands[0]) == REG)
4411 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4413 operands[2] = adj_offsettable_operand (operands[0], 4);
4414 if (ADDRESS_REG_P (operands[0]))
4415 return \"move%.l %1,%0\;sub%.l %2,%2\";
4417 return \"move%.l %1,%0\;clr%.l %2\";
4420 (define_insn "ashldi_sexthi"
4421 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4422 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4424 (clobber (match_scratch:SI 2 "=a,X"))]
4429 if (GET_CODE (operands[0]) == MEM)
4431 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4432 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4433 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4434 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4437 operands[3] = adj_offsettable_operand (operands[0], 4);
4438 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4441 else if (DATA_REG_P (operands[0]))
4442 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4444 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4447 (define_insn "ashldi_const32"
4448 [(set (match_operand:DI 0 "general_operand" "=rm")
4449 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4455 if (GET_CODE (operands[1]) == REG)
4456 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4458 operands[3] = adj_offsettable_operand (operands[1], 4);
4459 if (GET_CODE (operands[0]) == REG)
4460 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4461 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4462 return \"clr%.l %0\;move%.l %3,%0\";
4463 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4464 return \"move%.l %3,%0\;clr%.l %0\";
4466 operands[2] = adj_offsettable_operand (operands[0], 4);
4467 if (ADDRESS_REG_P (operands[2]))
4468 return \"move%.l %3,%0\;sub%.l %2,%2\";
4470 return \"move%.l %3,%0\;clr%.l %2\";
4473 ;; The predicate below must be general_operand, because ashldi3 allows that
4474 (define_insn "ashldi_const"
4475 [(set (match_operand:DI 0 "general_operand" "=d")
4476 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4477 (match_operand 2 "const_int_operand" "n")))]
4478 "(INTVAL (operands[2]) == 1
4479 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4480 || INTVAL (operands[2]) == 2 || INTVAL (operands[2]) == 3)"
4483 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4484 if (INTVAL (operands[2]) == 1)
4485 return \"add%.l %1,%1\;addx%.l %0,%0\";
4486 else if (INTVAL (operands[2]) == 8)
4487 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4488 else if (INTVAL (operands[2]) == 16)
4489 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4490 else if (INTVAL (operands[2]) == 2)
4491 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4492 else/* if (INTVAL (operands[2]) == 3)*/
4493 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4496 (define_expand "ashldi3"
4497 [(set (match_operand:DI 0 "general_operand" "")
4498 (ashift:DI (match_operand:DI 1 "general_operand" "")
4499 (match_operand 2 "const_int_operand" "")))]
4503 if (GET_CODE (operands[2]) != CONST_INT
4504 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 32
4505 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4506 && INTVAL (operands[2]) != 2 && INTVAL (operands[2]) != 3))
4510 ;; On most 68k models, this makes faster code in a special case.
4512 (define_insn "ashlsi_16"
4513 [(set (match_operand:SI 0 "register_operand" "=d")
4514 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4520 return \"swap %0\;clr%.w %0\";
4523 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4524 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4526 ;; On the 68000, this makes faster code in a special case.
4528 (define_insn "ashlsi_17_24"
4529 [(set (match_operand:SI 0 "register_operand" "=d")
4530 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4531 (match_operand:SI 2 "const_int_operand" "n")))]
4532 "(! TARGET_68020 && !TARGET_5200
4533 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4538 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4539 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4542 (define_insn "ashlsi3"
4543 [(set (match_operand:SI 0 "register_operand" "=d")
4544 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4545 (match_operand:SI 2 "general_operand" "dI")))]
4549 if (operands[2] == const1_rtx)
4551 cc_status.flags = CC_NO_OVERFLOW;
4552 return \"add%.l %0,%0\";
4554 return \"lsl%.l %2,%0\";
4557 (define_insn "ashlhi3"
4558 [(set (match_operand:HI 0 "register_operand" "=d")
4559 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4560 (match_operand:HI 2 "general_operand" "dI")))]
4565 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4566 (ashift:HI (match_dup 0)
4567 (match_operand:HI 1 "general_operand" "dI")))]
4571 (define_insn "ashlqi3"
4572 [(set (match_operand:QI 0 "register_operand" "=d")
4573 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4574 (match_operand:QI 2 "general_operand" "dI")))]
4579 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4580 (ashift:QI (match_dup 0)
4581 (match_operand:QI 1 "general_operand" "dI")))]
4585 ;; On most 68k models, this makes faster code in a special case.
4587 (define_insn "ashrsi_16"
4588 [(set (match_operand:SI 0 "register_operand" "=d")
4589 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4592 "swap %0\;ext%.l %0")
4594 ;; On the 68000, this makes faster code in a special case.
4597 [(set (match_operand:SI 0 "register_operand" "=d")
4598 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4599 (match_operand:SI 2 "const_int_operand" "n")))]
4600 "(! TARGET_68020 && !TARGET_5200
4601 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4604 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4605 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4608 (define_insn "subreghi1ashrdi_const32"
4609 [(set (match_operand:HI 0 "general_operand" "=rm")
4610 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4611 (const_int 32)) 1))]
4615 if (GET_CODE (operands[1]) != REG)
4616 operands[1] = adj_offsettable_operand (operands[1], 2);
4617 return \"move%.w %1,%0\";
4620 (define_insn "subregsi1ashrdi_const32"
4621 [(set (match_operand:SI 0 "general_operand" "=rm")
4622 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4623 (const_int 32)) 1))]
4627 return \"move%.l %1,%0\";
4630 (define_insn "ashrdi_const32"
4631 [(set (match_operand:DI 0 "register_operand" "=d")
4632 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4638 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4640 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4642 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4645 (define_insn "ashrdi_const32_mem"
4646 [(set (match_operand:DI 0 "general_operand" "=o,<")
4647 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4649 (clobber (match_scratch:SI 2 "=d,d"))]
4654 if (which_alternative == 1)
4655 operands[3] = operands[0];
4657 operands[3] = adj_offsettable_operand (operands[0], 4);
4659 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4661 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4664 ;; The predicate below must be general_operand, because ashrdi3 allows that
4665 (define_insn "ashrdi_const"
4666 [(set (match_operand:DI 0 "general_operand" "=d")
4667 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4668 (match_operand 2 "const_int_operand" "n")))]
4670 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4671 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4672 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 31
4673 || INTVAL (operands[2]) == 63))"
4676 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4677 if (INTVAL (operands[2]) == 63)
4678 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4680 if (INTVAL (operands[2]) == 1)
4681 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4682 else if (INTVAL (operands[2]) == 8)
4683 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4684 else if (INTVAL (operands[2]) == 16)
4685 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4686 else if (INTVAL (operands[2]) == 31)
4687 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4688 else if (INTVAL (operands[2]) == 2)
4689 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4690 else/* if (INTVAL (operands[2]) == 3)*/
4691 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4694 (define_expand "ashrdi3"
4695 [(set (match_operand:DI 0 "general_operand" "")
4696 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4697 (match_operand 2 "const_int_operand" "")))]
4701 if (GET_CODE (operands[2]) != CONST_INT
4702 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4703 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4704 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 31
4705 && INTVAL (operands[2]) != 32 && INTVAL (operands[2]) != 63))
4709 ;; On all 68k models, this makes faster code in a special case.
4711 (define_insn "ashrsi_31"
4712 [(set (match_operand:SI 0 "register_operand" "=d")
4713 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4718 return \"add%.l %0,%0\;subx%.l %0,%0\";
4721 (define_insn "ashrsi3"
4722 [(set (match_operand:SI 0 "register_operand" "=d")
4723 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4724 (match_operand:SI 2 "general_operand" "dI")))]
4728 (define_insn "ashrhi3"
4729 [(set (match_operand:HI 0 "register_operand" "=d")
4730 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4731 (match_operand:HI 2 "general_operand" "dI")))]
4736 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4737 (ashiftrt:HI (match_dup 0)
4738 (match_operand:HI 1 "general_operand" "dI")))]
4742 (define_insn "ashrqi3"
4743 [(set (match_operand:QI 0 "register_operand" "=d")
4744 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4745 (match_operand:QI 2 "general_operand" "dI")))]
4750 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4751 (ashiftrt:QI (match_dup 0)
4752 (match_operand:QI 1 "general_operand" "dI")))]
4756 ;; logical shift instructions
4758 ;; commented out because of reload problems in 950612-1.c
4761 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4762 ;; (const_int 32)) 1))
4763 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4764 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4765 ;; (const_int 32)) 1))]
4769 ;; return \"move%.l %0,%1\";
4774 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4775 ;; (const_int 32)) 0))
4776 ;; (set (match_operand:DI 1 "general_operand" "=do")
4777 ;; (lshiftrt:DI (match_dup 0)
4778 ;; (const_int 32)))]
4782 ;; if (GET_CODE (operands[1]) == REG)
4783 ;; operands[2] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4785 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4786 ;; return \"move%.l %0,%2\;clr%.l %1\";
4789 (define_insn "subreg1lshrdi_const32"
4790 [(set (match_operand:SI 0 "general_operand" "=rm")
4791 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4792 (const_int 32)) 1))]
4796 return \"move%.l %1,%0\";
4799 (define_insn "lshrdi_const32"
4800 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4801 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4807 if (which_alternative == 1)
4808 return \"move%.l %1,%0\;clr%.l %0\";
4809 if (which_alternative == 2)
4810 return \"clr%.l %0\;move%.l %1,%0\";
4811 if (GET_CODE (operands[0]) == REG)
4812 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4814 operands[2] = adj_offsettable_operand (operands[0], 4);
4815 if (GET_CODE (operands[1]) == REG)
4816 operands[3] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
4818 operands[3] = adj_offsettable_operand (operands[1], 4);
4819 if (ADDRESS_REG_P (operands[0]))
4820 return \"move%.l %1,%2\;sub%.l %0,%0\";
4822 return \"move%.l %1,%2\;clr%.l %0\";
4825 ;; The predicate below must be general_operand, because lshrdi3 allows that
4826 (define_insn "lshrdi_const"
4827 [(set (match_operand:DI 0 "general_operand" "=d")
4828 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4829 (match_operand 2 "const_int_operand" "n")))]
4831 && ((INTVAL (operands[2]) == 1 || INTVAL (operands[2]) == 2
4832 || INTVAL (operands[2]) == 3 || INTVAL (operands[2]) == 8
4833 || INTVAL (operands[2]) == 16 || INTVAL (operands[2]) == 63))"
4836 operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
4837 if (INTVAL (operands[2]) == 63)
4838 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4840 if (INTVAL (operands[2]) == 1)
4841 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4842 else if (INTVAL (operands[2]) == 8)
4843 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4844 else if (INTVAL (operands[2]) == 16)
4845 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4846 else if (INTVAL (operands[2]) == 2)
4847 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4848 else /*if (INTVAL (operands[2]) == 3)*/
4849 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4852 (define_expand "lshrdi3"
4853 [(set (match_operand:DI 0 "general_operand" "")
4854 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4855 (match_operand 2 "const_int_operand" "")))]
4859 if (GET_CODE (operands[2]) != CONST_INT
4860 || (INTVAL (operands[2]) != 1 && INTVAL (operands[2]) != 2
4861 && INTVAL (operands[2]) != 3 && INTVAL (operands[2]) != 8
4862 && INTVAL (operands[2]) != 16 && INTVAL (operands[2]) != 32
4863 && INTVAL (operands[2]) != 63))
4867 ;; On all 68k models, this makes faster code in a special case.
4869 (define_insn "lshrsi_31"
4870 [(set (match_operand:SI 0 "register_operand" "=d")
4871 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4876 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4879 ;; On most 68k models, this makes faster code in a special case.
4881 (define_insn "lshrsi_16"
4882 [(set (match_operand:SI 0 "register_operand" "=d")
4883 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4889 return \"clr%.w %0\;swap %0\";
4892 ;; On the 68000, this makes faster code in a special case.
4894 (define_insn "lshrsi_17_24"
4895 [(set (match_operand:SI 0 "register_operand" "=d")
4896 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4897 (match_operand:SI 2 "const_int_operand" "n")))]
4898 "(! TARGET_68020 && !TARGET_5200
4899 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4902 /* I think lsr%.w sets the CC properly. */
4903 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
4904 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
4907 (define_insn "lshrsi3"
4908 [(set (match_operand:SI 0 "register_operand" "=d")
4909 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4910 (match_operand:SI 2 "general_operand" "dI")))]
4914 (define_insn "lshrhi3"
4915 [(set (match_operand:HI 0 "register_operand" "=d")
4916 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
4917 (match_operand:HI 2 "general_operand" "dI")))]
4922 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4923 (lshiftrt:HI (match_dup 0)
4924 (match_operand:HI 1 "general_operand" "dI")))]
4928 (define_insn "lshrqi3"
4929 [(set (match_operand:QI 0 "register_operand" "=d")
4930 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
4931 (match_operand:QI 2 "general_operand" "dI")))]
4936 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4937 (lshiftrt:QI (match_dup 0)
4938 (match_operand:QI 1 "general_operand" "dI")))]
4942 ;; rotate instructions
4944 (define_insn "rotlsi3"
4945 [(set (match_operand:SI 0 "register_operand" "=d")
4946 (rotate:SI (match_operand:SI 1 "register_operand" "0")
4947 (match_operand:SI 2 "general_operand" "dINO")))]
4951 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
4953 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
4955 operands[2] = gen_rtx (CONST_INT, VOIDmode, 32 - INTVAL (operands[2]));
4956 return \"ror%.l %2,%0\";
4959 return \"rol%.l %2,%0\";
4962 (define_insn "rotlhi3"
4963 [(set (match_operand:HI 0 "register_operand" "=d")
4964 (rotate:HI (match_operand:HI 1 "register_operand" "0")
4965 (match_operand:HI 2 "general_operand" "dIP")))]
4969 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4971 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4972 return \"ror%.w %2,%0\";
4975 return \"rol%.w %2,%0\";
4979 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4980 (rotate:HI (match_dup 0)
4981 (match_operand:HI 1 "general_operand" "dIP")))]
4985 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
4987 operands[2] = gen_rtx (CONST_INT, VOIDmode, 16 - INTVAL (operands[2]));
4988 return \"ror%.w %2,%0\";
4991 return \"rol%.w %2,%0\";
4994 (define_insn "rotlqi3"
4995 [(set (match_operand:QI 0 "register_operand" "=d")
4996 (rotate:QI (match_operand:QI 1 "register_operand" "0")
4997 (match_operand:QI 2 "general_operand" "dI")))]
5001 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5003 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
5004 return \"ror%.b %2,%0\";
5007 return \"rol%.b %2,%0\";
5011 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5012 (rotate:QI (match_dup 0)
5013 (match_operand:QI 1 "general_operand" "dI")))]
5017 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5019 operands[2] = gen_rtx (CONST_INT, VOIDmode, 8 - INTVAL (operands[2]));
5020 return \"ror%.b %2,%0\";
5023 return \"rol%.b %2,%0\";
5026 (define_insn "rotrsi3"
5027 [(set (match_operand:SI 0 "register_operand" "=d")
5028 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5029 (match_operand:SI 2 "general_operand" "dI")))]
5033 (define_insn "rotrhi3"
5034 [(set (match_operand:HI 0 "register_operand" "=d")
5035 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5036 (match_operand:HI 2 "general_operand" "dI")))]
5041 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5042 (rotatert:HI (match_dup 0)
5043 (match_operand:HI 1 "general_operand" "dI")))]
5047 (define_insn "rotrqi3"
5048 [(set (match_operand:QI 0 "register_operand" "=d")
5049 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5050 (match_operand:QI 2 "general_operand" "dI")))]
5055 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5056 (rotatert:QI (match_dup 0)
5057 (match_operand:QI 1 "general_operand" "dI")))]
5062 ;; Bit set/clear in memory byte.
5064 ;; set bit, bit number is int
5065 (define_insn "bsetmemqi"
5066 [(set (match_operand:QI 0 "memory_operand" "+m")
5067 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5068 (match_operand:SI 1 "general_operand" "d")) 0)
5074 return \"bset %1,%0\";
5077 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5079 [(set (match_operand:QI 0 "memory_operand" "+m")
5080 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5081 (match_operator:SI 2 "extend_operator"
5082 [(match_operand 1 "general_operand" "d")])) 0)
5088 return \"bset %1,%0\";
5091 ;; clear bit, bit number is int
5092 (define_insn "bclrmemqi"
5093 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5095 (minus:SI (const_int 7)
5096 (match_operand:SI 1 "general_operand" "d")))
5102 return \"bclr %1,%0\";
5105 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5107 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5109 (minus:SI (const_int 7)
5110 (match_operator:SI 2 "extend_operator"
5111 [(match_operand 1 "general_operand" "d")])))
5117 return \"bclr %1,%0\";
5120 ;; Special cases of bit-field insns which we should
5121 ;; recognize in preference to the general case.
5122 ;; These handle aligned 8-bit and 16-bit fields,
5123 ;; which can usually be done with move instructions.
5126 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5127 ; alignment of structure members is specified.
5129 ; The move is allowed to be odd byte aligned, because that's still faster
5130 ; than an odd byte aligned bit field instruction.
5133 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5135 (match_operand:SI 2 "const_int_operand" "n"))
5136 (match_operand:SI 3 "general_operand" "rmi"))]
5137 "TARGET_68020 && TARGET_BITFIELD
5138 && (INTVAL (operands[2]) % 8) == 0
5139 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5143 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5145 return \"move%.l %3,%0\";
5149 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5150 (match_operand:SI 1 "const_int_operand" "n")
5151 (match_operand:SI 2 "const_int_operand" "n"))
5152 (match_operand:SI 3 "register_operand" "d"))]
5153 "TARGET_68020 && TARGET_BITFIELD
5154 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5155 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5156 && (GET_CODE (operands[0]) == REG
5157 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5160 if (REG_P (operands[0]))
5162 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5163 return \"bfins %3,%0{%b2:%b1}\";
5167 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5169 if (GET_CODE (operands[3]) == MEM)
5170 operands[3] = adj_offsettable_operand (operands[3],
5171 (32 - INTVAL (operands[1])) / 8);
5172 if (INTVAL (operands[1]) == 8)
5173 return \"move%.b %3,%0\";
5174 return \"move%.w %3,%0\";
5179 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5180 ; alignment of structure members is specified.
5182 ; The move is allowed to be odd byte aligned, because that's still faster
5183 ; than an odd byte aligned bit field instruction.
5186 [(set (match_operand:SI 0 "general_operand" "=rm")
5187 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5189 (match_operand:SI 3 "const_int_operand" "n")))]
5190 "TARGET_68020 && TARGET_BITFIELD
5191 && (INTVAL (operands[3]) % 8) == 0
5192 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5196 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5198 return \"move%.l %1,%0\";
5202 [(set (match_operand:SI 0 "general_operand" "=&d")
5203 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5204 (match_operand:SI 2 "const_int_operand" "n")
5205 (match_operand:SI 3 "const_int_operand" "n")))]
5206 "TARGET_68020 && TARGET_BITFIELD
5207 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5208 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5209 && (GET_CODE (operands[1]) == REG
5210 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5213 cc_status.flags |= CC_NOT_NEGATIVE;
5214 if (REG_P (operands[1]))
5216 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5217 return \"bfextu %1{%b3:%b2},%0\";
5221 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5223 output_asm_insn (\"clr%.l %0\", operands);
5224 if (GET_CODE (operands[0]) == MEM)
5225 operands[0] = adj_offsettable_operand (operands[0],
5226 (32 - INTVAL (operands[1])) / 8);
5227 if (INTVAL (operands[2]) == 8)
5228 return \"move%.b %1,%0\";
5229 return \"move%.w %1,%0\";
5233 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5234 ; alignment of structure members is specified.
5236 ; The move is allowed to be odd byte aligned, because that's still faster
5237 ; than an odd byte aligned bit field instruction.
5240 [(set (match_operand:SI 0 "general_operand" "=rm")
5241 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5243 (match_operand:SI 3 "const_int_operand" "n")))]
5244 "TARGET_68020 && TARGET_BITFIELD
5245 && (INTVAL (operands[3]) % 8) == 0
5246 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5250 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5252 return \"move%.l %1,%0\";
5256 [(set (match_operand:SI 0 "general_operand" "=d")
5257 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5258 (match_operand:SI 2 "const_int_operand" "n")
5259 (match_operand:SI 3 "const_int_operand" "n")))]
5260 "TARGET_68020 && TARGET_BITFIELD
5261 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5262 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5263 && (GET_CODE (operands[1]) == REG
5264 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5267 if (REG_P (operands[1]))
5269 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5270 return \"bfexts %1{%b3:%b2},%0\";
5274 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5276 if (INTVAL (operands[2]) == 8)
5277 return \"move%.b %1,%0\;extb%.l %0\";
5278 return \"move%.w %1,%0\;ext%.l %0\";
5281 ;; Bit field instructions, general cases.
5282 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5283 ;; so that its address is reloaded.
5285 (define_expand "extv"
5286 [(set (match_operand:SI 0 "general_operand" "")
5287 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5288 (match_operand:SI 2 "general_operand" "")
5289 (match_operand:SI 3 "general_operand" "")))]
5290 "TARGET_68020 && TARGET_BITFIELD"
5294 [(set (match_operand:SI 0 "general_operand" "=d")
5295 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5296 (match_operand:SI 2 "general_operand" "di")
5297 (match_operand:SI 3 "general_operand" "di")))]
5298 "TARGET_68020 && TARGET_BITFIELD"
5299 "bfexts %1{%b3:%b2},%0")
5301 (define_expand "extzv"
5302 [(set (match_operand:SI 0 "general_operand" "")
5303 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5304 (match_operand:SI 2 "general_operand" "")
5305 (match_operand:SI 3 "general_operand" "")))]
5306 "TARGET_68020 && TARGET_BITFIELD"
5310 [(set (match_operand:SI 0 "general_operand" "=d,d")
5311 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5312 (match_operand:SI 2 "general_operand" "di,di")
5313 (match_operand:SI 3 "general_operand" "di,di")))]
5314 "TARGET_68020 && TARGET_BITFIELD"
5317 if (GET_CODE (operands[2]) == CONST_INT)
5319 if (INTVAL (operands[2]) != 32)
5320 cc_status.flags |= CC_NOT_NEGATIVE;
5326 return \"bfextu %1{%b3:%b2},%0\";
5330 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5331 (match_operand:SI 1 "general_operand" "di")
5332 (match_operand:SI 2 "general_operand" "di"))
5333 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5334 (match_operand 3 "const_int_operand" "n")))]
5335 "TARGET_68020 && TARGET_BITFIELD
5336 && (INTVAL (operands[3]) == -1
5337 || (GET_CODE (operands[1]) == CONST_INT
5338 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5342 return \"bfchg %0{%b2:%b1}\";
5346 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5347 (match_operand:SI 1 "general_operand" "di")
5348 (match_operand:SI 2 "general_operand" "di"))
5350 "TARGET_68020 && TARGET_BITFIELD"
5354 return \"bfclr %0{%b2:%b1}\";
5358 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5359 (match_operand:SI 1 "general_operand" "di")
5360 (match_operand:SI 2 "general_operand" "di"))
5362 "TARGET_68020 && TARGET_BITFIELD"
5366 return \"bfset %0{%b2:%b1}\";
5369 (define_expand "insv"
5370 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5371 (match_operand:SI 1 "general_operand" "")
5372 (match_operand:SI 2 "general_operand" ""))
5373 (match_operand:SI 3 "register_operand" ""))]
5374 "TARGET_68020 && TARGET_BITFIELD"
5378 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5379 (match_operand:SI 1 "general_operand" "di")
5380 (match_operand:SI 2 "general_operand" "di"))
5381 (match_operand:SI 3 "register_operand" "d"))]
5382 "TARGET_68020 && TARGET_BITFIELD"
5383 "bfins %3,%0{%b2:%b1}")
5385 ;; Now recognize bit field insns that operate on registers
5386 ;; (or at least were intended to do so).
5389 [(set (match_operand:SI 0 "general_operand" "=d")
5390 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5391 (match_operand:SI 2 "general_operand" "di")
5392 (match_operand:SI 3 "general_operand" "di")))]
5393 "TARGET_68020 && TARGET_BITFIELD"
5394 "bfexts %1{%b3:%b2},%0")
5397 [(set (match_operand:SI 0 "general_operand" "=d")
5398 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5399 (match_operand:SI 2 "general_operand" "di")
5400 (match_operand:SI 3 "general_operand" "di")))]
5401 "TARGET_68020 && TARGET_BITFIELD"
5404 if (GET_CODE (operands[2]) == CONST_INT)
5406 if (INTVAL (operands[2]) != 32)
5407 cc_status.flags |= CC_NOT_NEGATIVE;
5413 return \"bfextu %1{%b3:%b2},%0\";
5417 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5418 (match_operand:SI 1 "general_operand" "di")
5419 (match_operand:SI 2 "general_operand" "di"))
5421 "TARGET_68020 && TARGET_BITFIELD"
5425 return \"bfclr %0{%b2:%b1}\";
5429 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5430 (match_operand:SI 1 "general_operand" "di")
5431 (match_operand:SI 2 "general_operand" "di"))
5433 "TARGET_68020 && TARGET_BITFIELD"
5437 return \"bfset %0{%b2:%b1}\";
5441 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5442 (match_operand:SI 1 "general_operand" "di")
5443 (match_operand:SI 2 "general_operand" "di"))
5444 (match_operand:SI 3 "register_operand" "d"))]
5445 "TARGET_68020 && TARGET_BITFIELD"
5449 /* These special cases are now recognized by a specific pattern. */
5450 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5451 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5452 return \"move%.w %3,%0\";
5453 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5454 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5455 return \"move%.b %3,%0\";
5457 return \"bfins %3,%0{%b2:%b1}\";
5460 ;; Special patterns for optimizing bit-field instructions.
5464 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5465 (match_operand:SI 1 "const_int_operand" "n")
5466 (match_operand:SI 2 "general_operand" "di")))]
5467 "TARGET_68020 && TARGET_BITFIELD"
5470 if (operands[1] == const1_rtx
5471 && GET_CODE (operands[2]) == CONST_INT)
5473 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5474 return output_btst (operands,
5475 gen_rtx (CONST_INT, VOIDmode,
5476 width - INTVAL (operands[2])),
5479 /* Pass 1000 as SIGNPOS argument so that btst will
5480 not think we are testing the sign bit for an `and'
5481 and assume that nonzero implies a negative result. */
5483 if (INTVAL (operands[1]) != 32)
5484 cc_status.flags = CC_NOT_NEGATIVE;
5485 return \"bftst %0{%b2:%b1}\";
5489 ;;; now handle the register cases
5492 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5493 (match_operand:SI 1 "const_int_operand" "n")
5494 (match_operand:SI 2 "general_operand" "di")))]
5495 "TARGET_68020 && TARGET_BITFIELD"
5498 if (operands[1] == const1_rtx
5499 && GET_CODE (operands[2]) == CONST_INT)
5501 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5502 return output_btst (operands,
5503 gen_rtx (CONST_INT, VOIDmode,
5504 width - INTVAL (operands[2])),
5507 /* Pass 1000 as SIGNPOS argument so that btst will
5508 not think we are testing the sign bit for an `and'
5509 and assume that nonzero implies a negative result. */
5511 if (INTVAL (operands[1]) != 32)
5512 cc_status.flags = CC_NOT_NEGATIVE;
5513 return \"bftst %0{%b2:%b1}\";
5516 (define_insn "scc0_di"
5517 [(set (match_operand:QI 0 "general_operand" "=dm")
5518 (match_operator 1 "valid_dbcc_comparison_p"
5519 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5523 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5526 (define_insn "scc0_di_5200"
5527 [(set (match_operand:QI 0 "general_operand" "=d")
5528 (match_operator 1 "valid_dbcc_comparison_p"
5529 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5533 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5536 (define_insn "scc_di"
5537 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5538 (match_operator 1 "valid_dbcc_comparison_p"
5539 [(match_operand:DI 2 "general_operand" "ro,r")
5540 (match_operand:DI 3 "general_operand" "r,ro")]))]
5544 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5547 (define_insn "scc_di_5200"
5548 [(set (match_operand:QI 0 "general_operand" "=d,d")
5549 (match_operator 1 "valid_dbcc_comparison_p"
5550 [(match_operand:DI 2 "general_operand" "ro,r")
5551 (match_operand:DI 3 "general_operand" "r,ro")]))]
5555 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5558 (define_expand "seq"
5559 [(set (match_operand:QI 0 "general_operand" "")
5560 (eq:QI (cc0) (const_int 0)))]
5564 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5566 m68k_last_compare_had_fp_operands = 0;
5572 [(set (match_operand:QI 0 "general_operand" "=dm")
5573 (eq:QI (cc0) (const_int 0)))]
5576 cc_status = cc_prev_status;
5577 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5581 [(set (match_operand:QI 0 "general_operand" "=d")
5582 (eq:QI (cc0) (const_int 0)))]
5585 cc_status = cc_prev_status;
5586 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5589 (define_expand "sne"
5590 [(set (match_operand:QI 0 "general_operand" "")
5591 (ne:QI (cc0) (const_int 0)))]
5595 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5597 m68k_last_compare_had_fp_operands = 0;
5603 [(set (match_operand:QI 0 "general_operand" "=dm")
5604 (ne:QI (cc0) (const_int 0)))]
5607 cc_status = cc_prev_status;
5608 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5612 [(set (match_operand:QI 0 "general_operand" "=d")
5613 (ne:QI (cc0) (const_int 0)))]
5616 cc_status = cc_prev_status;
5617 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5620 (define_expand "sgt"
5621 [(set (match_operand:QI 0 "general_operand" "")
5622 (gt:QI (cc0) (const_int 0)))]
5626 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5628 m68k_last_compare_had_fp_operands = 0;
5634 [(set (match_operand:QI 0 "general_operand" "=dm")
5635 (gt:QI (cc0) (const_int 0)))]
5638 cc_status = cc_prev_status;
5639 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5643 [(set (match_operand:QI 0 "general_operand" "=d")
5644 (gt:QI (cc0) (const_int 0)))]
5647 cc_status = cc_prev_status;
5648 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5651 (define_expand "sgtu"
5652 [(set (match_operand:QI 0 "general_operand" "")
5653 (gtu:QI (cc0) (const_int 0)))]
5658 [(set (match_operand:QI 0 "general_operand" "=dm")
5659 (gtu:QI (cc0) (const_int 0)))]
5661 "* cc_status = cc_prev_status;
5662 return \"shi %0\"; ")
5665 [(set (match_operand:QI 0 "general_operand" "=d")
5666 (gtu:QI (cc0) (const_int 0)))]
5668 "* cc_status = cc_prev_status;
5669 return \"shi %0\"; ")
5671 (define_expand "slt"
5672 [(set (match_operand:QI 0 "general_operand" "")
5673 (lt:QI (cc0) (const_int 0)))]
5677 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5679 m68k_last_compare_had_fp_operands = 0;
5685 [(set (match_operand:QI 0 "general_operand" "=dm")
5686 (lt:QI (cc0) (const_int 0)))]
5688 "* cc_status = cc_prev_status;
5689 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5692 [(set (match_operand:QI 0 "general_operand" "=d")
5693 (lt:QI (cc0) (const_int 0)))]
5695 "* cc_status = cc_prev_status;
5696 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5698 (define_expand "sltu"
5699 [(set (match_operand:QI 0 "general_operand" "")
5700 (ltu:QI (cc0) (const_int 0)))]
5705 [(set (match_operand:QI 0 "general_operand" "=dm")
5706 (ltu:QI (cc0) (const_int 0)))]
5708 "* cc_status = cc_prev_status;
5709 return \"scs %0\"; ")
5712 [(set (match_operand:QI 0 "general_operand" "=d")
5713 (ltu:QI (cc0) (const_int 0)))]
5715 "* cc_status = cc_prev_status;
5716 return \"scs %0\"; ")
5718 (define_expand "sge"
5719 [(set (match_operand:QI 0 "general_operand" "")
5720 (ge:QI (cc0) (const_int 0)))]
5724 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5726 m68k_last_compare_had_fp_operands = 0;
5732 [(set (match_operand:QI 0 "general_operand" "=dm")
5733 (ge:QI (cc0) (const_int 0)))]
5735 "* cc_status = cc_prev_status;
5736 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5739 [(set (match_operand:QI 0 "general_operand" "=d")
5740 (ge:QI (cc0) (const_int 0)))]
5742 "* cc_status = cc_prev_status;
5743 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5745 (define_expand "sgeu"
5746 [(set (match_operand:QI 0 "general_operand" "")
5747 (geu:QI (cc0) (const_int 0)))]
5752 [(set (match_operand:QI 0 "general_operand" "=dm")
5753 (geu:QI (cc0) (const_int 0)))]
5755 "* cc_status = cc_prev_status;
5756 return \"scc %0\"; ")
5759 [(set (match_operand:QI 0 "general_operand" "=d")
5760 (geu:QI (cc0) (const_int 0)))]
5762 "* cc_status = cc_prev_status;
5763 return \"scc %0\"; ")
5765 (define_expand "sle"
5766 [(set (match_operand:QI 0 "general_operand" "")
5767 (le:QI (cc0) (const_int 0)))]
5771 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5773 m68k_last_compare_had_fp_operands = 0;
5779 [(set (match_operand:QI 0 "general_operand" "=dm")
5780 (le:QI (cc0) (const_int 0)))]
5783 cc_status = cc_prev_status;
5784 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5788 [(set (match_operand:QI 0 "general_operand" "=d")
5789 (le:QI (cc0) (const_int 0)))]
5792 cc_status = cc_prev_status;
5793 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5796 (define_expand "sleu"
5797 [(set (match_operand:QI 0 "general_operand" "")
5798 (leu:QI (cc0) (const_int 0)))]
5803 [(set (match_operand:QI 0 "general_operand" "=dm")
5804 (leu:QI (cc0) (const_int 0)))]
5806 "* cc_status = cc_prev_status;
5807 return \"sls %0\"; ")
5810 [(set (match_operand:QI 0 "general_operand" "=d")
5811 (leu:QI (cc0) (const_int 0)))]
5813 "* cc_status = cc_prev_status;
5814 return \"sls %0\"; ")
5816 ;; Basic conditional jump instructions.
5818 (define_insn "beq0_di"
5820 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5822 (label_ref (match_operand 1 "" ","))
5824 (clobber (match_scratch:SI 2 "=d,d"))]
5829 if (which_alternative == 1)
5831 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5833 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5835 if ((cc_prev_status.value1
5836 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5837 || (cc_prev_status.value2
5838 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5840 cc_status = cc_prev_status;
5842 return \"jbeq %l1\";
5847 if (GET_CODE (operands[0]) == REG)
5848 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5850 operands[3] = adj_offsettable_operand (operands[0], 4);
5851 if (! ADDRESS_REG_P (operands[0]))
5854 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5856 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5859 operands[4] = gen_label_rtx();
5860 if (TARGET_68020 || TARGET_5200)
5863 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5865 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5871 #ifdef SGS_CMP_ORDER
5872 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5874 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5877 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5880 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5881 CODE_LABEL_NUMBER (operands[4]));
5885 (define_insn "bne0_di"
5887 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5889 (label_ref (match_operand 1 "" ","))
5891 (clobber (match_scratch:SI 2 "=d,X"))]
5895 if ((cc_prev_status.value1
5896 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5897 || (cc_prev_status.value2
5898 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5900 cc_status = cc_prev_status;
5902 return \"jbne %l1\";
5908 if (GET_CODE (operands[0]) == REG)
5909 operands[3] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
5911 operands[3] = adj_offsettable_operand (operands[0], 4);
5912 if (!ADDRESS_REG_P (operands[0]))
5915 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
5917 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
5920 if (TARGET_68020 || TARGET_5200)
5923 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
5925 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
5931 #ifdef SGS_CMP_ORDER
5932 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
5934 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
5937 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
5942 (define_insn "bge0_di"
5944 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
5946 (label_ref (match_operand 1 "" ""))
5951 if ((cc_prev_status.value1
5952 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5953 || (cc_prev_status.value2
5954 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5956 cc_status = cc_prev_status;
5957 if (cc_status.flags & CC_REVERSED)
5960 return \"jble %l1\";
5968 return \"jbpl %l1\";
5975 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
5976 output_asm_insn(\"tst%.l %0\", operands);
5979 /* On an address reg, cmpw may replace cmpl. */
5980 #ifdef SGS_CMP_ORDER
5981 output_asm_insn(\"cmp%.w %0,%#0\", operands);
5983 output_asm_insn(\"cmp%.w %#0,%0\", operands);
5988 return \"jbpl %l1\";
5994 (define_insn "blt0_di"
5996 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
5998 (label_ref (match_operand 1 "" ""))
6003 if ((cc_prev_status.value1
6004 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6005 || (cc_prev_status.value2
6006 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6008 cc_status = cc_prev_status;
6009 if (cc_status.flags & CC_REVERSED)
6012 return \"jbgt %l1\";
6020 return \"jbmi %l1\";
6027 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6028 output_asm_insn(\"tst%.l %0\", operands);
6031 /* On an address reg, cmpw may replace cmpl. */
6032 #ifdef SGS_CMP_ORDER
6033 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6035 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6040 return \"jbmi %l1\";
6048 (if_then_else (eq (cc0)
6050 (label_ref (match_operand 0 "" ""))
6056 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6058 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6064 (if_then_else (ne (cc0)
6066 (label_ref (match_operand 0 "" ""))
6072 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6074 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6080 (if_then_else (gt (cc0)
6082 (label_ref (match_operand 0 "" ""))
6087 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6089 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6095 (if_then_else (gtu (cc0)
6097 (label_ref (match_operand 0 "" ""))
6102 return \"jbhi %l0\";
6110 (if_then_else (lt (cc0)
6112 (label_ref (match_operand 0 "" ""))
6117 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6119 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6125 (if_then_else (ltu (cc0)
6127 (label_ref (match_operand 0 "" ""))
6132 return \"jbcs %l0\";
6140 (if_then_else (ge (cc0)
6142 (label_ref (match_operand 0 "" ""))
6147 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6149 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6155 (if_then_else (geu (cc0)
6157 (label_ref (match_operand 0 "" ""))
6162 return \"jbcc %l0\";
6170 (if_then_else (le (cc0)
6172 (label_ref (match_operand 0 "" ""))
6177 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6179 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6185 (if_then_else (leu (cc0)
6187 (label_ref (match_operand 0 "" ""))
6192 return \"jbls %l0\";
6198 ;; Negated conditional jump instructions.
6202 (if_then_else (eq (cc0)
6205 (label_ref (match_operand 0 "" ""))))]
6210 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6212 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6218 (if_then_else (ne (cc0)
6221 (label_ref (match_operand 0 "" ""))))]
6226 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6228 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6234 (if_then_else (gt (cc0)
6237 (label_ref (match_operand 0 "" ""))))]
6241 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6243 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6249 (if_then_else (gtu (cc0)
6252 (label_ref (match_operand 0 "" ""))))]
6256 return \"jbls %l0\";
6264 (if_then_else (lt (cc0)
6267 (label_ref (match_operand 0 "" ""))))]
6271 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6273 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6279 (if_then_else (ltu (cc0)
6282 (label_ref (match_operand 0 "" ""))))]
6286 return \"jbcc %l0\";
6294 (if_then_else (ge (cc0)
6297 (label_ref (match_operand 0 "" ""))))]
6301 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6303 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6309 (if_then_else (geu (cc0)
6312 (label_ref (match_operand 0 "" ""))))]
6316 return \"jbcs %l0\";
6324 (if_then_else (le (cc0)
6327 (label_ref (match_operand 0 "" ""))))]
6331 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6333 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6339 (if_then_else (leu (cc0)
6342 (label_ref (match_operand 0 "" ""))))]
6346 return \"jbhi %l0\";
6352 ;; Unconditional and other jump instructions
6355 (label_ref (match_operand 0 "" "")))]
6359 return \"jbra %l0\";
6365 ;; We support two different ways of handling dispatch tables.
6366 ;; The NeXT uses absolute tables, and other machines use relative.
6367 ;; This define_expand can generate either kind.
6368 (define_expand "tablejump"
6369 [(parallel [(set (pc) (match_operand 0 "" ""))
6370 (use (label_ref (match_operand 1 "" "")))])]
6374 #ifdef CASE_VECTOR_PC_RELATIVE
6375 operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
6376 gen_rtx (SIGN_EXTEND, SImode, operands[0]));
6380 ;; Jump to variable address from dispatch table of absolute addresses.
6382 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6383 (use (label_ref (match_operand 1 "" "")))]
6387 return \"jmp (%0)\";
6393 ;; Jump to variable address from dispatch table of relative addresses.
6397 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6398 (use (label_ref (match_operand 1 "" "")))]
6401 #ifdef ASM_RETURN_CASE_JUMP
6402 ASM_RETURN_CASE_JUMP;
6405 #ifdef ASM_OUTPUT_CASE_LABEL
6407 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6409 return \"jmp 6(%%pc,%0.w)\";
6414 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6416 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6417 #endif /* end !CRDS */
6422 return \"jmp 2(pc,%0.w)\";
6424 return \"jmp 2(%%pc,%0.w)\";
6425 #endif /* end !CRDS */
6432 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6434 return \"extl %0\;jmp pc@(2,%0:l)\";
6440 return \"jmp (2,pc,%0.w)\";
6442 return \"jmp pc@(2,%0:w)\";
6449 ;; Decrement-and-branch insns.
6453 (ne (match_operand:HI 0 "general_operand" "+d*g")
6455 (label_ref (match_operand 1 "" ""))
6458 (plus:HI (match_dup 0)
6464 if (DATA_REG_P (operands[0]))
6465 return \"dbra %0,%l1\";
6466 if (GET_CODE (operands[0]) == MEM)
6470 return \"sub%.w %#1,%0\;jbcc %l1\";
6472 return \"subq%.w %#1,%0\;jbcc %l1\";
6474 #else /* not MOTOROLA */
6475 return \"subqw %#1,%0\;jcc %l1\";
6479 #ifdef SGS_CMP_ORDER
6481 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6483 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6485 #else /* not SGS_CMP_ORDER */
6486 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6488 #else /* not MOTOROLA */
6489 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6496 (ne (match_operand:SI 0 "general_operand" "+d*g")
6498 (label_ref (match_operand 1 "" ""))
6501 (plus:SI (match_dup 0)
6509 if (DATA_REG_P (operands[0]))
6510 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6511 if (GET_CODE (operands[0]) == MEM)
6512 return \"sub%.l %#1,%0\;jbcc %l1\";
6514 if (DATA_REG_P (operands[0]))
6515 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6516 if (GET_CODE (operands[0]) == MEM)
6517 return \"subq%.l %#1,%0\;jbcc %l1\";
6518 #endif /* NO_ADDSUB_Q */
6519 #ifdef SGS_CMP_ORDER
6521 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6523 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6525 #else /* not SGS_CMP_ORDER */
6526 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6527 #endif /* not SGS_CMP_ORDER */
6528 #else /* not MOTOROLA */
6529 if (DATA_REG_P (operands[0]))
6530 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6531 if (GET_CODE (operands[0]) == MEM)
6532 return \"subql %#1,%0\;jcc %l1\";
6533 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6534 #endif /* not MOTOROLA */
6537 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6542 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6545 (label_ref (match_operand 1 "" ""))
6548 (plus:HI (match_dup 0)
6550 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6556 if (DATA_REG_P (operands[0]))
6557 return \"dbra %0,%l1\";
6558 if (GET_CODE (operands[0]) == MEM)
6559 return \"sub%.w %#1,%0\;jbcc %l1\";
6561 if (DATA_REG_P (operands[0]))
6562 return \"dbra %0,%l1\";
6563 if (GET_CODE (operands[0]) == MEM)
6564 return \"subq%.w %#1,%0\;jbcc %l1\";
6566 #ifdef SGS_CMP_ORDER
6568 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6570 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6572 #else /* not SGS_CMP_ORDER */
6573 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6574 #endif /* not SGS_CMP_ORDER */
6575 #else /* not MOTOROLA */
6576 if (DATA_REG_P (operands[0]))
6577 return \"dbra %0,%l1\";
6578 if (GET_CODE (operands[0]) == MEM)
6579 return \"subqw %#1,%0\;jcc %l1\";
6580 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6581 #endif /* not MOTOROLA */
6584 (define_expand "decrement_and_branch_until_zero"
6585 [(parallel [(set (pc)
6587 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6590 (label_ref (match_operand 1 "" ""))
6593 (plus:SI (match_dup 0)
6601 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6604 (label_ref (match_operand 1 "" ""))
6607 (plus:SI (match_dup 0)
6609 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6615 if (DATA_REG_P (operands[0]))
6616 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6617 if (GET_CODE (operands[0]) == MEM)
6618 return \"sub%.l %#1,%0\;jbcc %l1\";
6620 if (DATA_REG_P (operands[0]))
6621 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6622 if (GET_CODE (operands[0]) == MEM)
6623 return \"subq%.l %#1,%0\;jbcc %l1\";
6625 #ifdef SGS_CMP_ORDER
6627 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6629 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6631 #else /* not SGS_CMP_ORDER */
6632 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6633 #endif /* not SGS_CMP_ORDER */
6634 #else /* not MOTOROLA */
6635 if (DATA_REG_P (operands[0]))
6636 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6637 if (GET_CODE (operands[0]) == MEM)
6638 return \"subql %#1,%0\;jcc %l1\";
6639 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6640 #endif /* not MOTOROLA */
6644 ;; For PIC calls, in order to be able to support
6645 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6646 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6648 ;; PIC calls are handled by loading the address of the function into a
6649 ;; register (via movsi), then emitting a register indirect call using
6650 ;; the "jsr" function call syntax.
6652 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6653 ;; operand to the jbsr statement to indicate that this call should
6654 ;; go through the PLT (why? because this is the way that Sun does it).
6656 ;; We have different patterns for PIC calls and non-PIC calls. The
6657 ;; different patterns are only used to choose the right syntax.
6659 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6660 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6661 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6662 ;; section at link time. However, all global objects reference are still
6663 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6664 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6665 ;; We need to have a way to differentiate these two different operands.
6667 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6668 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6669 ;; to be changed to recognize function calls symbol_ref operand as a valid
6670 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6671 ;; avoid the compiler to load this symbol_ref operand into a register.
6672 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6673 ;; since the value is a PC relative offset, not a real address.
6675 ;; All global objects are treated in the similar way as in SUN3. The only
6676 ;; difference is: on m68k svr4, the reference of such global object needs
6677 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6678 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6681 ;; Call subroutine with no return value.
6682 (define_expand "call"
6683 [(call (match_operand:QI 0 "memory_operand" "")
6684 (match_operand:SI 1 "general_operand" ""))]
6685 ;; Operand 1 not really used on the m68000.
6690 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6691 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6694 ;; This is a normal call sequence.
6696 [(call (match_operand:QI 0 "memory_operand" "o")
6697 (match_operand:SI 1 "general_operand" "g"))]
6698 ;; Operand 1 not really used on the m68000.
6702 #if defined (MOTOROLA) && !defined (USE_GAS)
6704 if (GET_CODE (operands[0]) == MEM
6705 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6714 ;; This is a PIC call sequence.
6716 [(call (match_operand:QI 0 "memory_operand" "o")
6717 (match_operand:SI 1 "general_operand" "g"))]
6718 ;; Operand 1 not really used on the m68000.
6722 if (GET_CODE (operands[0]) == MEM
6723 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6726 return \"bsr.l %0\";
6729 return \"bsr.l %0@PLTPC\";
6731 return \"bsr %0@PLTPC\";
6735 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6736 GAS just plain ignores it. */
6737 return \"jbsr %0,a1\";
6742 ;; Call subroutine, returning value in operand 0
6743 ;; (which must be a hard register).
6744 ;; See comments before "call" regarding PIC calls.
6745 (define_expand "call_value"
6746 [(set (match_operand 0 "" "")
6747 (call (match_operand:QI 1 "memory_operand" "")
6748 (match_operand:SI 2 "general_operand" "")))]
6749 ;; Operand 2 not really used on the m68000.
6753 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6754 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6757 ;; This is a normal call_value
6759 [(set (match_operand 0 "" "=rf")
6760 (call (match_operand:QI 1 "memory_operand" "o")
6761 (match_operand:SI 2 "general_operand" "g")))]
6762 ;; Operand 2 not really used on the m68000.
6765 #if defined (MOTOROLA) && !defined (USE_GAS)
6767 if (GET_CODE (operands[1]) == MEM
6768 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6777 ;; This is a PIC call_value
6779 [(set (match_operand 0 "" "=rf")
6780 (call (match_operand:QI 1 "memory_operand" "o")
6781 (match_operand:SI 2 "general_operand" "g")))]
6782 ;; Operand 2 not really used on the m68000.
6785 if (GET_CODE (operands[1]) == MEM
6786 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6790 return \"bsr.l %1\";
6793 return \"bsr.l %1@PLTPC\";
6795 return \"bsr %1@PLTPC\";
6799 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6800 GAS just plain ignores it. */
6801 return \"jbsr %1,a1\";
6807 ;; Call subroutine returning any type.
6809 (define_expand "untyped_call"
6810 [(parallel [(call (match_operand 0 "" "")
6812 (match_operand 1 "" "")
6813 (match_operand 2 "" "")])]
6814 "NEEDS_UNTYPED_CALL"
6819 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6821 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6823 rtx set = XVECEXP (operands[2], 0, i);
6824 emit_move_insn (SET_DEST (set), SET_SRC (set));
6827 /* The optimizer does not know that the call sets the function value
6828 registers we stored in the result block. We avoid problems by
6829 claiming that all hard registers are used and clobbered at this
6831 emit_insn (gen_blockage ());
6836 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6837 ;; all of memory. This blocks insns from being moved across this point.
6839 (define_insn "blockage"
6840 [(unspec_volatile [(const_int 0)] 0)]
6849 (define_insn "probe"
6854 operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx,
6855 gen_rtx (CONST_INT, VOIDmode, NEED_PROBE));
6856 return \"tstl %a0\";
6859 ;; Used for frameless functions which save no regs and allocate no locals.
6860 (define_insn "return"
6865 if (current_function_pops_args == 0)
6867 operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args);
6871 (define_insn "indirect_jump"
6872 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6876 ;; This should not be used unless the add/sub insns can't be.
6879 [(set (match_operand:SI 0 "general_operand" "=a")
6880 (match_operand:QI 1 "address_operand" "p"))]
6885 /* Recognize an insn that refers to a table of offsets. Such an insn will
6886 need to refer to a label on the insn. So output one. Use the
6887 label-number of the table of offsets to generate this label. This code,
6888 and similar code above, assumes that there will be at most one reference
6890 if (GET_CODE (operands[1]) == PLUS
6891 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6892 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6894 rtx labelref = XEXP (operands[1], 1);
6895 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6897 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6898 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6900 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6901 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6902 #endif /* not SGS */
6903 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6904 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
6905 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6906 #ifdef SGS_SWITCH_TABLES
6907 /* Set flag saying we need to define the symbol
6908 LD%n (with value L%n-LI%n) at the end of the switch table. */
6909 switch_table_difference_label_flag = 1;
6910 #endif /* SGS_SWITCH_TABLES */
6911 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
6913 #endif /* SGS_NO_LI */
6915 return \"lea %a1,%0\";
6918 ;; This is the first machine-dependent peephole optimization.
6919 ;; It is useful when a floating value is returned from a function call
6920 ;; and then is moved into an FP register.
6921 ;; But it is mainly intended to test the support for these optimizations.
6924 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
6925 (set (match_operand:DF 0 "register_operand" "=f")
6926 (match_operand:DF 1 "register_operand" "ad"))]
6927 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
6931 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
6932 output_asm_insn (\"move%.l %1,%@\", xoperands);
6933 output_asm_insn (\"move%.l %1,%-\", operands);
6934 return \"fmove%.d %+,%0\";
6938 ;; Optimize a stack-adjust followed by a push of an argument.
6939 ;; This is said to happen frequently with -msoft-float
6940 ;; when there are consecutive library calls.
6943 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6944 (match_operand:SI 0 "const_int_operand" "n")))
6945 (set (match_operand:SF 1 "push_operand" "=m")
6946 (match_operand:SF 2 "general_operand" "rmfF"))]
6947 "INTVAL (operands[0]) >= 4
6948 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
6951 if (INTVAL (operands[0]) > 4)
6954 xoperands[0] = stack_pointer_rtx;
6955 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
6957 if (INTVAL (xoperands[1]) <= 8)
6960 output_asm_insn (\"addq%.w %1,%0\", xoperands);
6962 output_asm_insn (\"addq%.l %1,%0\", xoperands);
6964 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
6966 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
6967 INTVAL (xoperands[1]) - 8);
6968 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
6972 if (INTVAL (xoperands[1]) <= 0x7FFF)
6975 output_asm_insn (\"add%.w %1,%0\", xoperands);
6978 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
6980 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
6984 output_asm_insn (\"add%.l %1,%0\", xoperands);
6986 if (FP_REG_P (operands[2]))
6987 return \"fmove%.s %2,%@\";
6988 return \"move%.l %2,%@\";
6991 ;; Speed up stack adjust followed by a fullword fixedpoint push.
6994 [(set (reg:SI 15) (plus:SI (reg:SI 15)
6995 (match_operand:SI 0 "const_int_operand" "n")))
6996 (set (match_operand:SI 1 "push_operand" "=m")
6997 (match_operand:SI 2 "general_operand" "g"))]
6998 "INTVAL (operands[0]) >= 4
6999 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7002 if (INTVAL (operands[0]) > 4)
7005 xoperands[0] = stack_pointer_rtx;
7006 xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4);
7008 if (INTVAL (xoperands[1]) <= 8)
7011 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7013 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7015 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7017 xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
7018 INTVAL (xoperands[1]) - 8);
7019 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7023 if (INTVAL (xoperands[1]) <= 0x7FFF)
7026 output_asm_insn (\"add%.w %1,%0\", xoperands);
7030 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7032 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7037 output_asm_insn (\"add%.l %1,%0\", xoperands);
7039 if (operands[2] == const0_rtx)
7040 return \"clr%.l %@\";
7041 return \"move%.l %2,%@\";
7044 ;; Speed up pushing a single byte but leaving four bytes of space.
7047 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7048 (match_operand:QI 1 "general_operand" "dami"))
7049 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7050 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7055 if (GET_CODE (operands[1]) == REG)
7056 return \"move%.l %1,%-\";
7058 xoperands[1] = operands[1];
7060 = gen_rtx (MEM, QImode,
7061 gen_rtx (PLUS, VOIDmode, stack_pointer_rtx,
7062 gen_rtx (CONST_INT, VOIDmode, 3)));
7063 xoperands[3] = stack_pointer_rtx;
7065 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7067 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7072 [(set (match_operand:SI 0 "register_operand" "=d")
7074 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7075 (match_operand:HI 1 "general_operand" "rmn"))]
7076 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7079 if (GET_CODE (operands[1]) == CONST_INT)
7081 if (operands[1] == const0_rtx
7082 && (DATA_REG_P (operands[0])
7083 || GET_CODE (operands[0]) == MEM)
7084 /* clr insns on 68000 read before writing.
7085 This isn't so on the 68010, but we have no TARGET_68010. */
7086 && ((TARGET_68020 || TARGET_5200)
7087 || !(GET_CODE (operands[0]) == MEM
7088 && MEM_VOLATILE_P (operands[0]))))
7089 return \"clr%.w %0\";
7091 return \"move%.w %1,%0\";
7099 ;; jCC label ; abnormal loop termination
7100 ;; dbra dN, loop ; normal loop termination
7108 ;; Which moves the jCC condition outside the inner loop for free.
7111 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7112 [(cc0) (const_int 0)])
7113 (label_ref (match_operand 2 "" ""))
7118 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7121 (label_ref (match_operand 1 "" ""))
7124 (plus:HI (match_dup 0)
7126 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7130 output_dbcc_and_branch (operands);
7135 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7136 [(cc0) (const_int 0)])
7137 (label_ref (match_operand 2 "" ""))
7142 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7145 (label_ref (match_operand 1 "" ""))
7148 (plus:SI (match_dup 0)
7150 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7154 output_dbcc_and_branch (operands);
7159 ;; FPA multiply and add.
7161 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7162 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7163 (match_operand:DF 2 "general_operand" "xH,y,y"))
7164 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7167 fpma%.d %1,%w2,%w3,%0
7168 fpma%.d %x1,%x2,%x3,%0
7169 fpma%.d %x1,%x2,%x3,%0")
7172 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7173 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7174 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7175 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7178 fpma%.s %1,%w2,%w3,%0
7180 fpma%.s %1,%2,%3,%0")
7182 ;; FPA Multiply and subtract
7184 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7185 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7186 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7187 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7190 fpms%.d %3,%w2,%w1,%0
7191 fpms%.d %x3,%2,%x1,%0
7192 fpms%.d %x3,%2,%x1,%0")
7195 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7196 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7197 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7198 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7201 fpms%.s %3,%w2,%w1,%0
7203 fpms%.s %3,%2,%1,%0")
7206 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7207 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7208 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7209 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7212 fpmr%.d %2,%w1,%w3,%0
7213 fpmr%.d %x2,%1,%x3,%0
7214 fpmr%.d %x2,%1,%x3,%0")
7217 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7218 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7219 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7220 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7223 fpmr%.s %2,%w1,%w3,%0
7224 fpmr%.s %x2,%1,%x3,%0
7225 fpmr%.s %x2,%1,%x3,%0")
7227 ;; FPA Add and multiply
7229 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7230 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7231 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7232 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7235 fpam%.d %2,%w1,%w3,%0
7236 fpam%.d %x2,%1,%x3,%0
7237 fpam%.d %x2,%1,%x3,%0")
7240 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7241 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7242 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7243 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7246 fpam%.s %2,%w1,%w3,%0
7247 fpam%.s %x2,%1,%x3,%0
7248 fpam%.s %x2,%1,%x3,%0")
7250 ;;FPA Subtract and multiply
7252 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7253 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7254 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7255 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7258 fpsm%.d %2,%w1,%w3,%0
7259 fpsm%.d %x2,%1,%x3,%0
7260 fpsm%.d %x2,%1,%x3,%0")
7263 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7264 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7265 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7266 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7269 fpsm%.d %3,%w2,%w1,%0
7270 fpsm%.d %x3,%2,%x1,%0
7271 fpsm%.d %x3,%2,%x1,%0")
7274 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7275 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7276 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7277 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7280 fpsm%.s %2,%w1,%w3,%0
7281 fpsm%.s %x2,%1,%x3,%0
7282 fpsm%.s %x2,%1,%x3,%0")
7285 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7286 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7287 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7288 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7291 fpsm%.s %3,%w2,%w1,%0
7292 fpsm%.s %x3,%2,%x1,%0
7293 fpsm%.s %x3,%2,%x1,%0")
7295 (define_expand "tstxf"
7297 (match_operand:XF 0 "nonimmediate_operand" ""))]
7299 "m68k_last_compare_had_fp_operands = 1;")
7303 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7307 cc_status.flags = CC_IN_68881;
7308 return \"ftst%.x %0\";
7311 (define_expand "cmpxf"
7313 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7314 (match_operand:XF 1 "nonimmediate_operand" "")))]
7316 "m68k_last_compare_had_fp_operands = 1;")
7320 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7321 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7325 cc_status.flags = CC_IN_68881;
7326 #ifdef SGS_CMP_ORDER
7327 if (REG_P (operands[0]))
7329 if (REG_P (operands[1]))
7330 return \"fcmp%.x %0,%1\";
7332 return \"fcmp%.x %0,%f1\";
7334 cc_status.flags |= CC_REVERSED;
7335 return \"fcmp%.x %1,%f0\";
7337 if (REG_P (operands[0]))
7339 if (REG_P (operands[1]))
7340 return \"fcmp%.x %1,%0\";
7342 return \"fcmp%.x %f1,%0\";
7344 cc_status.flags |= CC_REVERSED;
7345 return \"fcmp%.x %f0,%1\";
7349 (define_insn "extendsfxf2"
7350 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7351 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
7355 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7357 if (REGNO (operands[0]) == REGNO (operands[1]))
7359 /* Extending float to double in an fp-reg is a no-op.
7360 NOTICE_UPDATE_CC has already assumed that the
7361 cc will be set. So cancel what it did. */
7362 cc_status = cc_prev_status;
7365 return \"f%$move%.x %1,%0\";
7367 if (FP_REG_P (operands[0]))
7368 return \"f%$move%.s %f1,%0\";
7369 return \"fmove%.x %f1,%0\";
7373 (define_insn "extenddfxf2"
7374 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7376 (match_operand:DF 1 "general_operand" "f,m")))]
7380 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7382 if (REGNO (operands[0]) == REGNO (operands[1]))
7384 /* Extending float to double in an fp-reg is a no-op.
7385 NOTICE_UPDATE_CC has already assumed that the
7386 cc will be set. So cancel what it did. */
7387 cc_status = cc_prev_status;
7390 return \"fmove%.x %1,%0\";
7392 if (FP_REG_P (operands[0]))
7393 return \"f%&move%.d %f1,%0\";
7394 return \"fmove%.x %f1,%0\";
7397 (define_insn "truncxfdf2"
7398 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7400 (match_operand:XF 1 "general_operand" "f,f")))]
7404 if (REG_P (operands[0]))
7406 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7407 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
7408 return \"move%.l %+,%0\";
7410 return \"fmove%.d %f1,%0\";
7413 (define_insn "truncxfsf2"
7414 [(set (match_operand:SF 0 "general_operand" "=dm")
7416 (match_operand:XF 1 "general_operand" "f")))]
7420 (define_insn "floatsixf2"
7421 [(set (match_operand:XF 0 "general_operand" "=f")
7422 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7426 (define_insn "floathixf2"
7427 [(set (match_operand:XF 0 "general_operand" "=f")
7428 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7432 (define_insn "floatqixf2"
7433 [(set (match_operand:XF 0 "general_operand" "=f")
7434 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7438 (define_insn "ftruncxf2"
7439 [(set (match_operand:XF 0 "general_operand" "=f")
7440 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7444 if (FP_REG_P (operands[1]))
7445 return \"fintrz%.x %f1,%0\";
7446 return \"fintrz%.x %f1,%0\";
7449 (define_insn "fixxfqi2"
7450 [(set (match_operand:QI 0 "general_operand" "=dm")
7451 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7455 (define_insn "fixxfhi2"
7456 [(set (match_operand:HI 0 "general_operand" "=dm")
7457 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7461 (define_insn "fixxfsi2"
7462 [(set (match_operand:SI 0 "general_operand" "=dm")
7463 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7468 [(set (match_operand:XF 0 "general_operand" "=f")
7469 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7470 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7475 [(set (match_operand:XF 0 "general_operand" "=f")
7476 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7477 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7482 [(set (match_operand:XF 0 "general_operand" "=f")
7483 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7484 (match_operand:XF 1 "general_operand" "0")))]
7488 (define_insn "addxf3"
7489 [(set (match_operand:XF 0 "general_operand" "=f")
7490 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7491 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7495 if (REG_P (operands[2]))
7496 return \"fadd%.x %2,%0\";
7497 return \"fadd%.x %f2,%0\";
7501 [(set (match_operand:XF 0 "general_operand" "=f")
7502 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7503 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7508 [(set (match_operand:XF 0 "general_operand" "=f")
7509 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7510 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7515 [(set (match_operand:XF 0 "general_operand" "=f")
7516 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7517 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7521 (define_insn "subxf3"
7522 [(set (match_operand:XF 0 "general_operand" "=f")
7523 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7524 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7528 if (REG_P (operands[2]))
7529 return \"fsub%.x %2,%0\";
7530 return \"fsub%.x %f2,%0\";
7534 [(set (match_operand:XF 0 "general_operand" "=f")
7535 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7536 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7541 [(set (match_operand:XF 0 "general_operand" "=f")
7542 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7543 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7548 [(set (match_operand:XF 0 "general_operand" "=f")
7549 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7550 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7554 (define_insn "mulxf3"
7555 [(set (match_operand:XF 0 "general_operand" "=f")
7556 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7557 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7561 if (REG_P (operands[2]))
7562 return \"fmul%.x %2,%0\";
7563 return \"fmul%.x %f2,%0\";
7567 [(set (match_operand:XF 0 "general_operand" "=f")
7568 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7569 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7574 [(set (match_operand:XF 0 "general_operand" "=f")
7575 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7576 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7581 [(set (match_operand:XF 0 "general_operand" "=f")
7582 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7583 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7587 (define_insn "divxf3"
7588 [(set (match_operand:XF 0 "general_operand" "=f")
7589 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7590 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7594 if (REG_P (operands[2]))
7595 return \"fdiv%.x %2,%0\";
7596 return \"fdiv%.x %f2,%0\";
7599 (define_expand "negxf2"
7600 [(set (match_operand:XF 0 "general_operand" "")
7601 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7605 /* ??? There isn't an FPA define_insn so we could handle it here too.
7606 For now we don't (paranoia). */
7614 target = operand_subword (operands[0], 0, 1, XFmode);
7615 result = expand_binop (SImode, xor_optab,
7616 operand_subword_force (operands[1], 0, XFmode),
7617 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7621 if (result != target)
7622 emit_move_insn (result, target);
7624 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7625 operand_subword_force (operands[1], 1, XFmode));
7626 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7627 operand_subword_force (operands[1], 2, XFmode));
7629 insns = get_insns ();
7632 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7637 (define_insn "negxf2_68881"
7638 [(set (match_operand:XF 0 "general_operand" "=f")
7639 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7643 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7644 return \"fneg%.x %1,%0\";
7645 return \"fneg%.x %f1,%0\";
7648 (define_expand "absxf2"
7649 [(set (match_operand:XF 0 "general_operand" "")
7650 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7654 /* ??? There isn't an FPA define_insn so we could handle it here too.
7655 For now we don't (paranoia). */
7663 target = operand_subword (operands[0], 0, 1, XFmode);
7664 result = expand_binop (SImode, and_optab,
7665 operand_subword_force (operands[1], 0, XFmode),
7666 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7670 if (result != target)
7671 emit_move_insn (result, target);
7673 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7674 operand_subword_force (operands[1], 1, XFmode));
7675 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7676 operand_subword_force (operands[1], 2, XFmode));
7678 insns = get_insns ();
7681 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7686 (define_insn "absxf2_68881"
7687 [(set (match_operand:XF 0 "general_operand" "=f")
7688 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7692 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7693 return \"fabs%.x %1,%0\";
7694 return \"fabs%.x %f1,%0\";
7697 (define_insn "sqrtxf2"
7698 [(set (match_operand:XF 0 "general_operand" "=f")
7699 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7703 (define_insn "sinsf2"
7704 [(set (match_operand:SF 0 "general_operand" "=f")
7705 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7706 "TARGET_68881 && flag_fast_math"
7709 if (FP_REG_P (operands[1]))
7710 return \"fsin%.x %1,%0\";
7712 return \"fsin%.s %1,%0\";
7715 (define_insn "sindf2"
7716 [(set (match_operand:DF 0 "general_operand" "=f")
7717 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7718 "TARGET_68881 && flag_fast_math"
7721 if (FP_REG_P (operands[1]))
7722 return \"fsin%.x %1,%0\";
7724 return \"fsin%.d %1,%0\";
7727 (define_insn "sinxf2"
7728 [(set (match_operand:XF 0 "general_operand" "=f")
7729 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7730 "TARGET_68881 && flag_fast_math"
7733 (define_insn "cossf2"
7734 [(set (match_operand:SF 0 "general_operand" "=f")
7735 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7736 "TARGET_68881 && flag_fast_math"
7739 if (FP_REG_P (operands[1]))
7740 return \"fcos%.x %1,%0\";
7742 return \"fcos%.s %1,%0\";
7745 (define_insn "cosdf2"
7746 [(set (match_operand:DF 0 "general_operand" "=f")
7747 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7748 "TARGET_68881 && flag_fast_math"
7751 if (FP_REG_P (operands[1]))
7752 return \"fcos%.x %1,%0\";
7754 return \"fcos%.d %1,%0\";
7757 (define_insn "cosxf2"
7758 [(set (match_operand:XF 0 "general_operand" "=f")
7759 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7760 "TARGET_68881 && flag_fast_math"