1 /* Definitions of target machine for GNU compiler.
2 Sun 68000/68020 version.
3 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions that relate to assembler syntax. */
27 /* Target CPU builtins. */
28 #define TARGET_CPU_CPP_BUILTINS() \
31 builtin_define ("__mc68000__"); \
32 builtin_define ("__mc68020__"); \
33 builtin_define ("__m68k__"); \
34 builtin_assert ("cpu=m68k"); \
35 builtin_assert ("machine=m68k"); \
40 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
42 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
43 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
44 #define INT_OP_NO_DOT 2 /* byte, short, long */
45 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
48 #define INT_OP_GROUP INT_OP_DOT_WORD
50 /* Print subsidiary information on the compiler version in use. */
52 #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
54 #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
57 /* Run-time compilation parameters selecting different hardware subsets. */
59 extern int target_flags;
61 /* Macros used in the machine description to test the flags. */
63 /* Compile for a 68020 (not a 68000 or 68010). */
65 #define TARGET_68020 (target_flags & MASK_68020)
67 /* Compile 68881 insns for floating point (not library calls). */
69 #define TARGET_68881 (target_flags & MASK_68881)
71 /* Compile using 68020 bit-field insns. */
72 #define MASK_BITFIELD 4
73 #define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
75 /* Compile using rtd insn calling sequence.
76 This will not work unless you use prototypes at least
77 for all functions that can take varying numbers of args. */
79 #define TARGET_RTD (target_flags & MASK_RTD)
81 /* Compile passing first two args in regs 0 and 1.
82 This exists only to test compiler features that will
83 be needed for RISC chips. It is not usable
84 and is not intended to be usable on this cpu. */
85 #define MASK_REGPARM 16
86 #define TARGET_REGPARM (target_flags & MASK_REGPARM)
88 /* Compile with 16-bit `int'. */
90 #define TARGET_SHORT (target_flags & MASK_SHORT)
92 /* Optimize for 68040, but still allow execution on 68020
93 (-m68020-40 or -m68040).
94 The 68040 will execute all 68030 and 68881/2 instructions, but some
95 of them must be emulated in software by the OS. When TARGET_68040 is
96 turned on, these instructions won't be used. This code will still
97 run on a 68030 and 68881/2. */
98 #define MASK_68040 256
99 #define TARGET_68040 (target_flags & MASK_68040)
101 /* Use the 68040-only fp instructions (-m68040 or -m68060). */
102 #define MASK_68040_ONLY 512
103 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
105 /* Optimize for 68060, but still allow execution on 68020
106 (-m68020-60 or -m68060).
107 The 68060 will execute all 68030 and 68881/2 instructions, but some
108 of them must be emulated in software by the OS. When TARGET_68060 is
109 turned on, these instructions won't be used. This code will still
110 run on a 68030 and 68881/2. */
111 #define MASK_68060 1024
112 #define TARGET_68060 (target_flags & MASK_68060)
114 /* Compile for mcf5200 */
115 #define MASK_5200 2048
116 #define TARGET_5200 (target_flags & MASK_5200)
118 /* Align ints to a word boundary. This breaks compatibility with the
119 published ABI's for structures containing ints, but produces faster
120 code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
121 It's required for coldfire cpus without a misalignment module. */
122 #define MASK_ALIGN_INT 4096
123 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
125 /* Compile for a CPU32 */
126 /* A 68020 without bitfields is a good heuristic for a CPU32 */
127 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
129 /* Use PC-relative addressing modes (without using a global offset table).
130 The m68000 supports 16-bit PC-relative addressing.
131 The m68020 supports 32-bit PC-relative addressing
132 (using outer displacements).
134 Under this model, all SYMBOL_REFs (and CONSTs) and LABEL_REFs are
135 treated as all containing an implicit PC-relative component, and hence
136 cannot be used directly as addresses for memory writes. See the comments
137 in m68k.c for more information. */
138 #define MASK_PCREL 8192
139 #define TARGET_PCREL (target_flags & MASK_PCREL)
141 /* Relax strict alignment. */
142 #define MASK_NO_STRICT_ALIGNMENT 16384
143 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
145 /* Macro to define tables used to set the flags.
146 This is a list in braces of pairs in braces,
147 each pair being { "NAME", VALUE }
148 where VALUE is the bits to set or minus the bits to clear.
149 An empty string NAME is used to identify the default VALUE. */
151 #define TARGET_SWITCHES \
152 { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
153 N_("Generate code for a 68020") }, \
154 { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
155 N_("Generate code for a 68020") }, \
156 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
157 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
158 { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
159 |MASK_68020|MASK_BITFIELD|MASK_68881), \
160 N_("Generate code for a 68000") }, \
161 { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
162 |MASK_68020|MASK_BITFIELD|MASK_68881), \
163 N_("Generate code for a 68000") }, \
164 { "bitfield", MASK_BITFIELD, \
165 N_("Use the bit-field instructions") }, \
166 { "nobitfield", - MASK_BITFIELD, \
167 N_("Do not use the bit-field instructions") }, \
169 N_("Use different calling convention using 'rtd'") }, \
170 { "nortd", - MASK_RTD, \
171 N_("Use normal calling convention") }, \
172 { "short", MASK_SHORT, \
173 N_("Consider type `int' to be 16 bits wide") }, \
174 { "noshort", - MASK_SHORT, \
175 N_("Consider type `int' to be 32 bits wide") }, \
176 { "68881", MASK_68881, "" }, \
177 { "soft-float", - (MASK_68040_ONLY|MASK_68881), \
178 N_("Generate code with library calls for floating point") }, \
179 { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
180 N_("Generate code for a 68040, without any new instructions") }, \
181 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
182 { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
183 N_("Generate code for a 68060, without any new instructions") }, \
184 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
185 |MASK_68060), "" }, \
186 { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
187 N_("Generate code for a 68030") }, \
188 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
189 { "68040", - (MASK_5200|MASK_68060), \
190 N_("Generate code for a 68040") }, \
191 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
192 |MASK_68040_ONLY|MASK_68040), "" }, \
193 { "68060", - (MASK_5200|MASK_68040), \
194 N_("Generate code for a 68060") }, \
195 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
196 |MASK_68040_ONLY|MASK_68060), "" }, \
197 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
198 |MASK_BITFIELD|MASK_68881), \
199 N_("Generate code for a 520X") }, \
200 { "5200", (MASK_5200), "" }, \
202 N_("Generate code for a 68851") }, \
204 N_("Do no generate code for a 68851") }, \
205 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
206 |MASK_68020|MASK_BITFIELD|MASK_68881), \
207 N_("Generate code for a 68302") }, \
208 { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
209 |MASK_BITFIELD|MASK_68881), \
210 N_("Generate code for a 68332") }, \
211 { "68332", MASK_68020, "" }, \
212 { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
213 |MASK_BITFIELD|MASK_68881), \
214 N_("Generate code for a cpu32") }, \
215 { "cpu32", MASK_68020, "" }, \
216 { "align-int", MASK_ALIGN_INT, \
217 N_("Align variables on a 32-bit boundary") }, \
218 { "no-align-int", -MASK_ALIGN_INT, \
219 N_("Align variables on a 16-bit boundary") }, \
220 { "pcrel", MASK_PCREL, \
221 N_("Generate pc-relative code") }, \
222 { "strict-align", -MASK_NO_STRICT_ALIGNMENT, \
223 N_("Do not use unaligned memory references") }, \
224 { "no-strict-align", MASK_NO_STRICT_ALIGNMENT, \
225 N_("Use unaligned memory references") }, \
227 { "", TARGET_DEFAULT, "" }}
228 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
230 /* This macro is similar to `TARGET_SWITCHES' but defines names of
231 command options that have values. Its definition is an
232 initializer with a subgrouping for each command option.
234 Each subgrouping contains a string constant, that defines the
235 fixed part of the option name, and the address of a variable. The
236 variable, type `char *', is set to the variable part of the given
237 option if the fixed part matches. The actual option name is made
238 by appending `-m' to the specified name. */
239 #define TARGET_OPTIONS \
240 { { "align-loops=", &m68k_align_loops_string, \
241 N_("Loop code aligned to this power of 2"), 0}, \
242 { "align-jumps=", &m68k_align_jumps_string, \
243 N_("Jump targets are aligned to this power of 2"), 0}, \
244 { "align-functions=", &m68k_align_funcs_string, \
245 N_("Function starts are aligned to this power of 2"), 0}, \
249 /* Sometimes certain combinations of command options do not make
250 sense on a particular target machine. You can define a macro
251 `OVERRIDE_OPTIONS' to take account of this. This macro, if
252 defined, is executed once just after all the command options have
255 Don't use this macro to turn on various extra optimizations for
256 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
258 #define OVERRIDE_OPTIONS override_options()
260 /* These are meant to be redefined in the host dependent files */
261 #define SUBTARGET_SWITCHES
262 #define SUBTARGET_OPTIONS
263 #define SUBTARGET_OVERRIDE_OPTIONS
265 /* target machine storage layout */
267 /* Define for XFmode extended real floating point support. */
268 #define LONG_DOUBLE_TYPE_SIZE 96
270 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
271 instructions, we get proper intermediate rounding, otherwise we
272 get extended precision results. */
273 #define TARGET_FLT_EVAL_METHOD (TARGET_68040_ONLY ? 0 : 2)
275 /* Define this if most significant bit is lowest numbered
276 in instructions that operate on numbered bit-fields.
277 This is true for 68020 insns such as bfins and bfexts.
278 We make it true always by avoiding using the single-bit insns
279 except in special cases with constant bit numbers. */
280 #define BITS_BIG_ENDIAN 1
282 /* Define this if most significant byte of a word is the lowest numbered. */
283 /* That is true on the 68000. */
284 #define BYTES_BIG_ENDIAN 1
286 /* Define this if most significant word of a multiword number is the lowest
288 /* For 68000 we can decide arbitrarily
289 since there are no machine instructions for them.
290 So let's be consistent. */
291 #define WORDS_BIG_ENDIAN 1
293 /* Width of a word, in units (bytes). */
294 #define UNITS_PER_WORD 4
296 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
297 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
299 /* Boundary (in *bits*) on which stack pointer should be aligned. */
300 #define STACK_BOUNDARY 16
302 /* Allocation boundary (in *bits*) for the code of a function. */
303 #define FUNCTION_BOUNDARY (1 << (m68k_align_funcs + 3))
305 /* Alignment of field after `int : 0' in a structure. */
306 #define EMPTY_FIELD_BOUNDARY 16
308 /* No data type wants to be aligned rounder than this.
309 Most published ABIs say that ints should be aligned on 16 bit
310 boundaries, but cpus with 32 bit busses get better performance
311 aligned on 32 bit boundaries. Coldfires without a misalignment
312 module require 32 bit alignment. */
313 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
315 /* Set this nonzero if move instructions will actually fail to work
316 when given unaligned data. */
317 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
319 /* Maximum power of 2 that code can be aligned to. */
320 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
322 /* Align loop starts for optimal branching. */
323 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
325 /* This is how to align an instruction for optimal branching. */
326 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (m68k_align_jumps)
328 /* Define number of bits in most basic integer type.
329 (If undefined, default is BITS_PER_WORD). */
331 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
333 /* Define these to avoid dependence on meaning of `int'. */
335 #define WCHAR_TYPE "long int"
336 #define WCHAR_TYPE_SIZE 32
338 /* Standard register usage. */
340 /* Number of actual hardware registers.
341 The hardware registers are assigned numbers for the compiler
342 from 0 to just below FIRST_PSEUDO_REGISTER.
343 All registers that the compiler knows about must be given numbers,
344 even those that are not normally considered general registers.
345 For the 68000, we give the data registers numbers 0-7,
346 the address registers numbers 010-017,
347 and the 68881 floating point registers numbers 020-027. */
348 #define FIRST_PSEUDO_REGISTER 24
350 /* This defines the register which is used to hold the offset table for PIC. */
351 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
353 /* 1 for registers that have pervasive standard uses
354 and are not available for the register allocator.
355 On the 68000, only the stack pointer is such. */
357 #define FIXED_REGISTERS \
358 {/* Data registers. */ \
359 0, 0, 0, 0, 0, 0, 0, 0, \
361 /* Address registers. */ \
362 0, 0, 0, 0, 0, 0, 0, 1, \
364 /* Floating point registers \
366 0, 0, 0, 0, 0, 0, 0, 0 }
368 /* 1 for registers not available across function calls.
369 These must include the FIXED_REGISTERS and also any
370 registers that can be used without being saved.
371 The latter must include the registers where values are returned
372 and the register where structure-value addresses are passed.
373 Aside from that, you can include as many other registers as you like. */
374 #define CALL_USED_REGISTERS \
375 {1, 1, 0, 0, 0, 0, 0, 0, \
376 1, 1, 0, 0, 0, 0, 0, 1, \
377 1, 1, 0, 0, 0, 0, 0, 0 }
380 /* Make sure everything's fine if we *don't* have a given processor.
381 This assumes that putting a register in fixed_regs will keep the
382 compiler's mitts completely off it. We don't bother to zero it out
383 of register classes. */
385 #define CONDITIONAL_REGISTER_USAGE \
389 if (! TARGET_68881) \
391 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
392 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
393 if (TEST_HARD_REG_BIT (x, i)) \
394 fixed_regs[i] = call_used_regs[i] = 1; \
396 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
397 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
398 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
401 /* Return number of consecutive hard regs needed starting at reg REGNO
402 to hold something of mode MODE.
403 This is ordinarily the length in words of a value of mode MODE
404 but can be less for certain modes in special long registers.
406 On the 68000, ordinary registers hold 32 bits worth;
407 for the 68881 registers, a single register is always enough for
408 anything that can be stored in them at all. */
409 #define HARD_REGNO_NREGS(REGNO, MODE) \
410 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
411 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
413 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
414 On the 68000, the cpu registers can hold any mode but the 68881 registers
415 can hold only SFmode or DFmode. */
417 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
419 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
420 || ((REGNO) >= 16 && (REGNO) < 24 \
421 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
422 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
423 && GET_MODE_UNIT_SIZE (MODE) <= 12))
426 /* Value is 1 if it is a good idea to tie two pseudo registers
427 when one has mode MODE1 and one has mode MODE2.
428 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
429 for any hard reg, then this must be 0 for correct output. */
430 #define MODES_TIEABLE_P(MODE1, MODE2) \
432 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
433 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
434 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
435 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
437 /* Specify the registers used for certain standard purposes.
438 The values of these macros are register numbers. */
440 /* m68000 pc isn't overloaded on a register. */
441 /* #define PC_REGNUM */
443 /* Register to use for pushing function arguments. */
444 #define STACK_POINTER_REGNUM 15
446 /* Base register for access to local variables of the function. */
447 #define FRAME_POINTER_REGNUM 14
449 /* Value should be nonzero if functions must have frame pointers.
450 Zero means the frame pointer need not be set up (and parms
451 may be accessed via the stack pointer) in functions that seem suitable.
452 This is computed in `reload', in reload1.c. */
453 #define FRAME_POINTER_REQUIRED 0
455 /* Base register for access to arguments of the function. */
456 #define ARG_POINTER_REGNUM 14
458 /* Register in which static-chain is passed to a function. */
459 #define STATIC_CHAIN_REGNUM 8
461 /* Register in which address to store a structure value
462 is passed to a function. */
463 #define STRUCT_VALUE_REGNUM 9
465 /* Define the classes of registers for register constraints in the
466 machine description. Also define ranges of constants.
468 One of the classes must always be named ALL_REGS and include all hard regs.
469 If there is more than one class, another class must be named NO_REGS
470 and contain no registers.
472 The name GENERAL_REGS must be the name of a class (or an alias for
473 another name such as ALL_REGS). This is the class of registers
474 that is allowed by "g" or "r" in a register constraint.
475 Also, registers outside this class are allocated only when
476 instructions express preferences for them.
478 The classes must be numbered in nondecreasing order; that is,
479 a larger-numbered class must never be contained completely
480 in a smaller-numbered class.
482 For any two classes, it is very desirable that there be another
483 class that represents their union. */
485 /* The 68000 has three kinds of registers, so eight classes would be
486 a complete set. One of them is not needed. */
491 GENERAL_REGS, DATA_OR_FP_REGS,
492 ADDR_OR_FP_REGS, ALL_REGS,
495 #define N_REG_CLASSES (int) LIM_REG_CLASSES
497 /* Give names of register classes as strings for dump file. */
499 #define REG_CLASS_NAMES \
500 { "NO_REGS", "DATA_REGS", \
501 "ADDR_REGS", "FP_REGS", \
502 "GENERAL_REGS", "DATA_OR_FP_REGS", \
503 "ADDR_OR_FP_REGS", "ALL_REGS" }
505 /* Define which registers fit in which classes.
506 This is an initializer for a vector of HARD_REG_SET
507 of length N_REG_CLASSES. */
509 #define REG_CLASS_CONTENTS \
511 {0x00000000}, /* NO_REGS */ \
512 {0x000000ff}, /* DATA_REGS */ \
513 {0x0000ff00}, /* ADDR_REGS */ \
514 {0x00ff0000}, /* FP_REGS */ \
515 {0x0000ffff}, /* GENERAL_REGS */ \
516 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
517 {0x00ffff00}, /* ADDR_OR_FP_REGS */ \
518 {0x00ffffff}, /* ALL_REGS */ \
521 /* The same information, inverted:
522 Return the class number of the smallest class containing
523 reg number REGNO. This could be a conditional expression
524 or could index an array. */
526 #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
528 /* The class value for index registers, and the one for base regs. */
530 #define INDEX_REG_CLASS GENERAL_REGS
531 #define BASE_REG_CLASS ADDR_REGS
533 /* Get reg_class from a letter such as appears in the machine description.
534 We do a trick here to modify the effective constraints on the
535 machine description; we zorch the constraint letters that aren't
536 appropriate for a specific target. This allows us to guarantee
537 that a specific kind of register will not be used for a given target
538 without fiddling with the register classes above. */
540 #define REG_CLASS_FROM_LETTER(C) \
541 ((C) == 'a' ? ADDR_REGS : \
542 ((C) == 'd' ? DATA_REGS : \
543 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
547 /* The letters I, J, K, L and M in a register constraint string
548 can be used to stand for particular ranges of immediate operands.
549 This macro defines what the ranges are.
550 C is the letter, and VALUE is a constant value.
551 Return 1 if VALUE is in the range specified by C.
553 For the 68000, `I' is used for the range 1 to 8
554 allowed as immediate shift counts and in addq.
555 `J' is used for the range of signed numbers that fit in 16 bits.
556 `K' is for numbers that moveq can't handle.
557 `L' is for range -8 to -1, range of values that can be added with subq.
558 `M' is for numbers that moveq+notb can't handle.
559 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
560 'O' is for 16 (for rotate using swap).
561 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
563 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
564 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
565 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
566 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
567 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
568 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
569 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
570 (C) == 'O' ? (VALUE) == 16 : \
571 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
574 * A small bit of explanation:
575 * "G" defines all of the floating constants that are *NOT* 68881
576 * constants. this is so 68881 constants get reloaded and the
579 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
580 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
582 /* A C expression that defines the optional machine-dependent constraint
583 letters that can be used to segregate specific types of operands,
584 usually memory references, for the target machine. It should return 1 if
585 VALUE corresponds to the operand type represented by the constraint letter
586 C. If C is not defined as an extra constraint, the value returned should
587 be 0 regardless of VALUE. */
589 /* Letters in the range `Q' through `U' may be defined in a
590 machine-dependent fashion to stand for arbitrary operand types.
591 The machine description macro `EXTRA_CONSTRAINT' is passed the
592 operand as its first argument and the constraint letter as its
595 `Q' means address register indirect addressing mode.
596 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
597 `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
599 #define EXTRA_CONSTRAINT(OP,CODE) \
602 && GET_CODE (OP) == MEM \
603 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
604 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
605 || GET_CODE (XEXP (OP, 0)) == CONST)) \
609 && (GET_CODE (OP) == SYMBOL_REF \
610 || GET_CODE (OP) == LABEL_REF \
611 || GET_CODE (OP) == CONST)) \
614 ? (GET_CODE (OP) == MEM \
615 && GET_CODE (XEXP (OP, 0)) == REG) \
619 /* Given an rtx X being reloaded into a reg required to be
620 in class CLASS, return the class of reg to actually use.
621 In general this is just CLASS; but on some machines
622 in some cases it is preferable to use a more restrictive class.
623 On the 68000 series, use a data reg if possible when the
624 value is a constant in the range where moveq could be used
625 and we ensure that QImodes are reloaded into data regs. */
627 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
628 ((GET_CODE (X) == CONST_INT \
629 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
630 && (CLASS) != ADDR_REGS) \
632 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
634 : (GET_CODE (X) == CONST_DOUBLE \
635 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
636 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
637 ? FP_REGS : NO_REGS) \
639 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
640 || GET_CODE (X) == LABEL_REF)) \
644 /* Force QImode output reloads from subregs to be allocated to data regs,
645 since QImode stores from address regs are not supported. We make the
646 assumption that if the class is not ADDR_REGS, then it must be a superset
649 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
650 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
654 /* Return the maximum number of consecutive registers
655 needed to represent mode MODE in a register of class CLASS. */
656 /* On the 68000, this is the size of MODE in words,
657 except in the FP regs, where a single reg is always enough. */
658 #define CLASS_MAX_NREGS(CLASS, MODE) \
659 ((CLASS) == FP_REGS ? 1 \
660 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
662 /* Moves between fp regs and other regs are two insns. */
663 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
664 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
665 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
668 /* Stack layout; function entry, exit and calling. */
670 /* Define this if pushing a word on the stack
671 makes the stack pointer a smaller address. */
672 #define STACK_GROWS_DOWNWARD
674 /* Nonzero if we need to generate stack-probe insns.
675 On most systems they are not needed.
676 When they are needed, define this as the stack offset to probe at. */
679 /* Define this if the nominal address of the stack frame
680 is at the high-address end of the local variables;
681 that is, each additional local variable allocated
682 goes at a more negative offset in the frame. */
683 #define FRAME_GROWS_DOWNWARD
685 /* Offset within stack frame to start allocating local variables at.
686 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
687 first local allocated. Otherwise, it is the offset to the BEGINNING
688 of the first local allocated. */
689 #define STARTING_FRAME_OFFSET 0
691 /* If we generate an insn to push BYTES bytes,
692 this says how many the stack pointer really advances by.
693 On the 68000, sp@- in a byte insn really pushes a word.
694 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
695 #define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
697 /* We want to avoid trying to push bytes. */
698 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
699 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
700 && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
702 /* Offset of first parameter from the argument pointer register value. */
703 #define FIRST_PARM_OFFSET(FNDECL) 8
705 /* Value is the number of byte of arguments automatically
706 popped when returning from a subroutine call.
707 FUNDECL is the declaration node of the function (as a tree),
708 FUNTYPE is the data type of the function (as a tree),
709 or for a library call it is an identifier node for the subroutine name.
710 SIZE is the number of bytes of arguments passed on the stack.
712 On the 68000, the RTS insn cannot pop anything.
713 On the 68010, the RTD insn may be used to pop them if the number
714 of args is fixed, but if the number is variable then the caller
715 must pop them all. RTD can't be used for library calls now
716 because the library is compiled with the Unix compiler.
717 Use of RTD is a selectable option, since it is incompatible with
718 standard Unix calling sequences. If the option is not selected,
719 the caller must always pop the args. */
721 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
722 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
723 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
724 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
725 == void_type_node))) \
728 /* Define how to find the value returned by a function.
729 VALTYPE is the data type of the value (as a tree).
730 If the precise function being called is known, FUNC is its FUNCTION_DECL;
731 otherwise, FUNC is 0. */
733 /* On the 68000 the return value is in D0 regardless. */
735 #define FUNCTION_VALUE(VALTYPE, FUNC) \
736 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
738 /* Define how to find the value returned by a library function
739 assuming the value has mode MODE. */
741 /* On the 68000 the return value is in D0 regardless. */
743 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
745 /* 1 if N is a possible register number for a function value.
746 On the 68000, d0 is the only register thus used. */
748 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
750 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
751 more than one register. */
753 #define NEEDS_UNTYPED_CALL 0
755 /* Define this if PCC uses the nonreentrant convention for returning
756 structure and union values. */
758 #define PCC_STATIC_STRUCT_RETURN
760 /* 1 if N is a possible register number for function argument passing.
761 On the 68000, no registers are used in this way. */
763 #define FUNCTION_ARG_REGNO_P(N) 0
765 /* Define a data type for recording info about an argument list
766 during the scan of that argument list. This data type should
767 hold all necessary information about the function itself
768 and about the args processed so far, enough to enable macros
769 such as FUNCTION_ARG to determine where the next arg should go.
771 On the m68k, this is a single integer, which is a number of bytes
772 of arguments scanned so far. */
774 #define CUMULATIVE_ARGS int
776 /* Initialize a variable CUM of type CUMULATIVE_ARGS
777 for a call to a function whose data type is FNTYPE.
778 For a library call, FNTYPE is 0.
780 On the m68k, the offset starts at 0. */
782 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
785 /* Update the data in CUM to advance over an argument
786 of mode MODE and data type TYPE.
787 (TYPE is null for libcalls where that information may not be available.) */
789 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
790 ((CUM) += ((MODE) != BLKmode \
791 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
792 : (int_size_in_bytes (TYPE) + 3) & ~3))
794 /* Define where to put the arguments to a function.
795 Value is zero to push the argument on the stack,
796 or a hard register in which to store the argument.
798 MODE is the argument's machine mode.
799 TYPE is the data type of the argument (as a tree).
800 This is null for libcalls where that information may
802 CUM is a variable of type CUMULATIVE_ARGS which gives info about
803 the preceding args and about the function being called.
804 NAMED is nonzero if this argument is a named parameter
805 (otherwise it is an extra parameter matching an ellipsis). */
807 /* On the 68000 all args are pushed, except if -mregparm is specified
808 then the first two words of arguments are passed in d0, d1.
809 *NOTE* -mregparm does not work.
810 It exists only to test register calling conventions. */
812 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
813 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
815 /* For an arg passed partly in registers and partly in memory,
816 this is the number of registers used.
817 For args passed entirely in registers or entirely in memory, zero. */
819 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
820 ((TARGET_REGPARM && (CUM) < 8 \
821 && 8 < ((CUM) + ((MODE) == BLKmode \
822 ? int_size_in_bytes (TYPE) \
823 : GET_MODE_SIZE (MODE)))) \
826 /* Output assembler code to FILE to increment profiler label # LABELNO
827 for profiling a function entry. */
829 #define FUNCTION_PROFILER(FILE, LABELNO) \
830 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
832 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
833 the stack pointer does not matter. The value is tested only in
834 functions that have frame pointers.
835 No definition is equivalent to always zero. */
837 #define EXIT_IGNORE_STACK 1
839 /* This is a hook for other tm files to change. */
840 /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
842 /* Determine if the epilogue should be output as RTL.
843 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
844 #define USE_RETURN_INSN use_return_insn ()
846 /* Store in the variable DEPTH the initial difference between the
847 frame pointer reg contents and the stack pointer reg contents,
848 as of the start of the function body. This depends on the layout
849 of the fixed parts of the stack frame and on how registers are saved.
851 On the 68k, if we have a frame, we must add one word to its length
852 to allow for the place that a6 is stored when we do have a frame pointer.
853 Otherwise, we would need to compute the offset from the frame pointer
854 of a local variable as a function of frame_pointer_needed, which
857 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
860 for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
861 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
863 for (regno = 0; regno < 16; regno++) \
864 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
866 if (flag_pic && current_function_uses_pic_offset_table) \
868 (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
869 + (get_frame_size () == 0 ? 0 : 4)); \
872 /* Output assembler code for a block containing the constant parts
873 of a trampoline, leaving space for the variable parts. */
875 /* On the 68k, the trampoline looks like this:
879 WARNING: Targets that may run on 68040+ cpus must arrange for
880 the instruction cache to be flushed. Previous incarnations of
881 the m68k trampoline code attempted to get around this by either
882 using an out-of-line transfer function or pc-relative data, but
883 the fact remains that the code to jump to the transfer function
884 or the code to load the pc-relative data needs to be flushed
885 just as much as the "variable" portion of the trampoline.
886 Recognizing that a cache flush is going to be required anyway,
887 dispense with such notions and build a smaller trampoline. */
889 /* Since more instructions are required to move a template into
890 place than to create it on the spot, don't use a template. */
892 /* Length in units of the trampoline for entering a nested function. */
894 #define TRAMPOLINE_SIZE 12
896 /* Alignment required for a trampoline in bits. */
898 #define TRAMPOLINE_ALIGNMENT 16
900 /* Targets redefine this to invoke code to either flush the cache,
901 or enable stack execution (or both). */
903 #ifndef FINALIZE_TRAMPOLINE
904 #define FINALIZE_TRAMPOLINE(TRAMP)
907 /* Emit RTL insns to initialize the variable parts of a trampoline.
908 FNADDR is an RTX for the address of the function's pure code.
909 CXT is an RTX for the static chain value for the function.
911 We generate a two-instructions program at address TRAMP :
915 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
917 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
918 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
919 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
921 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
922 FINALIZE_TRAMPOLINE(TRAMP); \
925 /* This is the library routine that is used
926 to transfer control from the trampoline
927 to the actual nested function.
928 It is defined for backward compatibility,
929 for linking with object code that used the old
930 trampoline definition. */
932 /* A colon is used with no explicit operands
933 to cause the template string to be scanned for %-constructs. */
934 /* The function name __transfer_from_trampoline is not actually used.
935 The function definition just permits use of "asm with operands"
936 (though the operand list is empty). */
937 #define TRANSFER_FROM_TRAMPOLINE \
939 __transfer_from_trampoline () \
941 register char *a0 asm ("%a0"); \
942 asm (GLOBAL_ASM_OP "___trampoline"); \
943 asm ("___trampoline:"); \
944 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
945 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
949 /* Addressing modes, and classification of registers for them. */
951 #define HAVE_POST_INCREMENT 1
953 #define HAVE_PRE_DECREMENT 1
955 /* Macros to check register numbers against specific register classes. */
957 /* These assume that REGNO is a hard or pseudo reg number.
958 They give nonzero only if REGNO is a hard reg of the suitable class
959 or a pseudo reg currently allocated to a suitable hard reg.
960 Since they use reg_renumber, they are safe only once reg_renumber
961 has been allocated, which happens in local-alloc.c. */
963 #define REGNO_OK_FOR_INDEX_P(REGNO) \
964 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
965 #define REGNO_OK_FOR_BASE_P(REGNO) \
966 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
967 #define REGNO_OK_FOR_DATA_P(REGNO) \
968 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
969 #define REGNO_OK_FOR_FP_P(REGNO) \
970 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
972 /* Now macros that check whether X is a register and also,
973 strictly, whether it is in a specified class.
975 These macros are specific to the 68000, and may be used only
976 in code for printing assembler insns and in conditions for
977 define_optimization. */
979 /* 1 if X is a data register. */
981 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
983 /* 1 if X is an fp register. */
985 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
987 /* 1 if X is an address register */
989 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
991 /* Maximum number of registers that can appear in a valid memory address. */
993 #define MAX_REGS_PER_ADDRESS 2
995 /* Recognize any constant value that is a valid address. */
997 #define CONSTANT_ADDRESS_P(X) \
998 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
999 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1000 || GET_CODE (X) == HIGH)
1002 /* Nonzero if the constant value X is a legitimate general operand.
1003 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1005 #define LEGITIMATE_CONSTANT_P(X) 1
1007 /* Nonzero if the constant value X is a legitimate general operand
1008 when generating PIC code. It is given that flag_pic is on and
1009 that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1011 PCREL_GENERAL_OPERAND_OK makes reload accept addresses that are
1012 accepted by insn predicates, but which would otherwise fail the
1013 `general_operand' test. */
1015 #ifndef REG_OK_STRICT
1016 #define PCREL_GENERAL_OPERAND_OK 0
1018 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
1021 #define LEGITIMATE_PIC_OPERAND_P(X) \
1022 ((! symbolic_operand (X, VOIDmode) \
1023 && ! (GET_CODE (X) == CONST_DOUBLE && mem_for_const_double (X) != 0 \
1024 && GET_CODE (mem_for_const_double (X)) == MEM \
1025 && symbolic_operand (XEXP (mem_for_const_double (X), 0), \
1027 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
1028 || PCREL_GENERAL_OPERAND_OK)
1030 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1031 and check its validity for a certain class.
1032 We have two alternate definitions for each of them.
1033 The usual definition accepts all pseudo regs; the other rejects
1034 them unless they have been allocated suitable hard regs.
1035 The symbol REG_OK_STRICT causes the latter definition to be used.
1037 Most source files want to accept pseudo regs in the hope that
1038 they will get allocated to the class that the insn wants them to be in.
1039 Source files for reload pass need to be strict.
1040 After reload, it makes no difference, since pseudo regs have
1041 been eliminated by then. */
1043 #ifndef REG_OK_STRICT
1045 /* Nonzero if X is a hard reg that can be used as an index
1046 or if it is a pseudo reg. */
1047 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1048 /* Nonzero if X is a hard reg that can be used as a base reg
1049 or if it is a pseudo reg. */
1050 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1054 /* Nonzero if X is a hard reg that can be used as an index. */
1055 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1056 /* Nonzero if X is a hard reg that can be used as a base reg. */
1057 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1061 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1062 that is a valid memory address for an instruction.
1063 The MODE argument is the machine mode for the MEM expression
1064 that wants to use this address.
1066 When generating PIC, an address involving a SYMBOL_REF is legitimate
1067 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1068 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1069 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1071 Likewise for a LABEL_REF when generating PIC.
1073 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1075 /* Allow SUBREG everywhere we allow REG. This results in better code. It
1076 also makes function inlining work when inline functions are called with
1077 arguments that are SUBREGs. */
1079 #define LEGITIMATE_BASE_REG_P(X) \
1080 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1081 || (GET_CODE (X) == SUBREG \
1082 && GET_CODE (SUBREG_REG (X)) == REG \
1083 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1085 #define INDIRECTABLE_1_ADDRESS_P(X) \
1086 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1087 || LEGITIMATE_BASE_REG_P (X) \
1088 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1089 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
1090 || (GET_CODE (X) == PLUS \
1091 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
1092 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1094 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
1095 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1096 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1097 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1098 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
1100 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1101 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1103 /* Only labels on dispatch tables are valid for indexing from. */
1104 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
1106 if (GET_CODE (X) == LABEL_REF \
1107 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
1108 && GET_CODE (temp) == JUMP_INSN \
1109 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
1110 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
1112 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
1114 #define GO_IF_INDEXING(X, ADDR) \
1115 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1116 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1117 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1118 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1120 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1121 { GO_IF_INDEXING (X, ADDR); \
1122 if (GET_CODE (X) == PLUS) \
1123 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1124 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
1125 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1126 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1127 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
1128 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1130 /* coldfire/5200 does not allow HImode index registers. */
1131 #define LEGITIMATE_INDEX_REG_P(X) \
1132 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1134 && GET_CODE (X) == SIGN_EXTEND \
1135 && GET_CODE (XEXP (X, 0)) == REG \
1136 && GET_MODE (XEXP (X, 0)) == HImode \
1137 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1138 || (GET_CODE (X) == SUBREG \
1139 && GET_CODE (SUBREG_REG (X)) == REG \
1140 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1142 #define LEGITIMATE_INDEX_P(X) \
1143 (LEGITIMATE_INDEX_REG_P (X) \
1144 || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1145 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1146 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1147 && (INTVAL (XEXP (X, 1)) == 2 \
1148 || INTVAL (XEXP (X, 1)) == 4 \
1149 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1151 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1152 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1153 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1154 GO_IF_INDEXED_ADDRESS (X, ADDR); \
1155 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
1156 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
1157 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
1160 /* Don't call memory_address_noforce for the address to fetch
1161 the switch offset. This address is ok as it stands (see above),
1162 but memory_address_noforce would alter it. */
1163 #define PIC_CASE_VECTOR_ADDRESS(index) index
1165 /* Try machine-dependent ways of modifying an illegitimate address
1166 to be legitimate. If we find one, return the new, valid address.
1167 This macro is used in only one place: `memory_address' in explow.c.
1169 OLDX is the address as it was before break_out_memory_refs was called.
1170 In some cases it is useful to look at this to decide what needs to be done.
1172 MODE and WIN are passed so that this macro can use
1173 GO_IF_LEGITIMATE_ADDRESS.
1175 It is always safe for this macro to do nothing. It exists to recognize
1176 opportunities to optimize the output.
1178 For the 68000, we handle X+REG by loading X into a register R and
1179 using R+REG. R will go in an address reg and indexing will be used.
1180 However, if REG is a broken-out memory address or multiplication,
1181 nothing needs to be done because REG can certainly go in an address reg. */
1183 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1184 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1185 { register int ch = (X) != (OLDX); \
1186 if (GET_CODE (X) == PLUS) \
1188 if (GET_CODE (XEXP (X, 0)) == MULT) \
1189 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1190 if (GET_CODE (XEXP (X, 1)) == MULT) \
1191 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1192 if (ch && GET_CODE (XEXP (X, 1)) == REG \
1193 && GET_CODE (XEXP (X, 0)) == REG) \
1195 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1196 if (GET_CODE (XEXP (X, 0)) == REG \
1197 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1198 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1199 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1200 { register rtx temp = gen_reg_rtx (Pmode); \
1201 register rtx val = force_operand (XEXP (X, 1), 0); \
1202 emit_move_insn (temp, val); \
1204 XEXP (X, 1) = temp; \
1206 else if (GET_CODE (XEXP (X, 1)) == REG \
1207 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1208 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1209 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1210 { register rtx temp = gen_reg_rtx (Pmode); \
1211 register rtx val = force_operand (XEXP (X, 0), 0); \
1212 emit_move_insn (temp, val); \
1214 XEXP (X, 0) = temp; \
1217 /* Go to LABEL if ADDR (a legitimate address expression)
1218 has an effect that depends on the machine mode it is used for.
1219 On the 68000, only predecrement and postincrement address depend thus
1220 (the amount of decrement or increment being the length of the operand). */
1222 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1223 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1225 /* Specify the machine mode that this machine uses
1226 for the index in the tablejump instruction. */
1227 #define CASE_VECTOR_MODE HImode
1229 /* Define as C expression which evaluates to nonzero if the tablejump
1230 instruction expects the table to contain offsets from the address of the
1232 Do not define this if the table should contain absolute addresses. */
1233 #define CASE_VECTOR_PC_RELATIVE 1
1235 /* Define this as 1 if `char' should by default be signed; else as 0. */
1236 #define DEFAULT_SIGNED_CHAR 1
1238 /* Don't cse the address of the function being compiled. */
1239 #define NO_RECURSIVE_FUNCTION_CSE
1241 /* Max number of bytes we can move from memory to memory
1242 in one reasonably fast instruction. */
1245 /* Nonzero if access to memory by bytes is slow and undesirable. */
1246 #define SLOW_BYTE_ACCESS 0
1248 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1249 is done just by pretending it is already truncated. */
1250 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1252 /* We assume that the store-condition-codes instructions store 0 for false
1253 and some other value for true. This is the value stored for true. */
1255 #define STORE_FLAG_VALUE (-1)
1257 /* When a prototype says `char' or `short', really pass an `int'. */
1258 #define PROMOTE_PROTOTYPES 1
1260 /* Specify the machine mode that pointers have.
1261 After generation of rtl, the compiler makes no further distinction
1262 between pointers and any other objects of this machine mode. */
1263 #define Pmode SImode
1265 /* A function address in a call instruction
1266 is a byte address (for indexing purposes)
1267 so give the MEM rtx a byte's mode. */
1268 #define FUNCTION_MODE QImode
1271 /* Tell final.c how to eliminate redundant test instructions. */
1273 /* Here we define machine-dependent flags and fields in cc_status
1274 (see `conditions.h'). */
1276 /* Set if the cc value is actually in the 68881, so a floating point
1277 conditional branch must be output. */
1278 #define CC_IN_68881 04000
1280 /* Store in cc_status the expressions that the condition codes will
1281 describe after execution of an instruction whose pattern is EXP.
1282 Do not alter them if the instruction would not alter the cc's. */
1284 /* On the 68000, all the insns to store in an address register fail to
1285 set the cc's. However, in some cases these instructions can make it
1286 possibly invalid to use the saved cc's. In those cases we clear out
1287 some or all of the saved cc's so they won't be used. */
1289 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1291 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1292 { if (cc_prev_status.flags & CC_IN_68881) \
1294 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1298 /* Control the assembler format that we output. */
1300 /* Output at beginning of assembler file. */
1302 #define ASM_FILE_START(FILE) \
1303 fprintf (FILE, "#NO_APP\n");
1305 /* Output to assembler file text saying following lines
1306 may contain character constants, extra white space, comments, etc. */
1308 #define ASM_APP_ON "#APP\n"
1310 /* Output to assembler file text saying following lines
1311 no longer contain unusual constructs. */
1313 #define ASM_APP_OFF "#NO_APP\n"
1315 /* Output before read-only data. */
1317 #define TEXT_SECTION_ASM_OP "\t.text"
1319 /* Output before writable data. */
1321 #define DATA_SECTION_ASM_OP "\t.data"
1323 #define GLOBAL_ASM_OP "\t.globl\t"
1325 /* Here are four prefixes that are used by asm_fprintf to
1326 facilitate customization for alternate assembler syntaxes.
1327 Machines with no likelihood of an alternate syntax need not
1328 define these and need not use asm_fprintf. */
1330 /* The prefix for register names. Note that REGISTER_NAMES
1331 is supposed to include this prefix. */
1333 #define REGISTER_PREFIX ""
1335 /* The prefix for local labels. You should be able to define this as
1336 an empty string, or any arbitrary string (such as ".", ".L%", etc)
1337 without having to make any other changes to account for the specific
1338 definition. Note it is a string literal, not interpreted by printf
1341 #define LOCAL_LABEL_PREFIX ""
1343 /* The prefix to add to user-visible assembler symbols. */
1345 #define USER_LABEL_PREFIX "_"
1347 /* The prefix for immediate operands. */
1349 #define IMMEDIATE_PREFIX "#"
1351 /* How to refer to registers in assembler output.
1352 This sequence is indexed by compiler's hard-register-number (see above). */
1354 #define REGISTER_NAMES \
1355 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1356 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1357 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1359 /* How to renumber registers for dbx and gdb.
1360 On the Sun-3, the floating point registers have numbers
1361 18 to 25, not 16 to 23 as they do in the compiler. */
1363 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1365 /* Before the prologue, RA is at 0(%sp). */
1366 #define INCOMING_RETURN_ADDR_RTX \
1367 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
1369 /* We must not use the DBX register numbers for the DWARF 2 CFA column
1370 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
1371 Instead use the identity mapping. */
1372 #define DWARF_FRAME_REGNUM(REG) REG
1374 /* Before the prologue, the top of the frame is at 4(%sp). */
1375 #define INCOMING_FRAME_SP_OFFSET 4
1377 /* Describe how we implement __builtin_eh_return. */
1378 #define EH_RETURN_DATA_REGNO(N) \
1379 ((N) < 2 ? (N) : INVALID_REGNUM)
1380 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
1381 #define EH_RETURN_HANDLER_RTX \
1382 gen_rtx_MEM (Pmode, \
1383 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
1384 plus_constant (EH_RETURN_STACKADJ_RTX, \
1387 /* Select a format to encode pointers in exception handling data. CODE
1388 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1389 true if the symbol may be affected by dynamic relocations. */
1390 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
1392 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
1395 /* This is how to output a reference to a user-level label named NAME.
1396 `assemble_name' uses this. */
1398 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1399 asm_fprintf (FILE, "%0U%s", NAME)
1401 /* This is how to store into the string LABEL
1402 the symbol_ref name of an internal numbered label where
1403 PREFIX is the class of label and NUM is the number within the class.
1404 This is suitable for output with `assemble_name'. */
1406 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1407 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
1409 /* This is how to output an insn to push a register on the stack.
1410 It need not be very fast code. */
1412 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1413 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1415 /* This is how to output an insn to pop a register from the stack.
1416 It need not be very fast code. */
1418 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1419 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1421 /* This is how to output an element of a case-vector that is absolute.
1422 (The 68000 does not use such vectors,
1423 but we must define this macro anyway.) */
1425 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1426 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1428 /* This is how to output an element of a case-vector that is relative. */
1430 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1431 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1433 /* This is how to output an assembler line
1434 that says to advance the location counter
1435 to a multiple of 2**LOG bytes. */
1437 /* We don't have a way to align to more than a two-byte boundary, so do the
1438 best we can and don't complain. */
1439 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1441 fprintf (FILE, "\t.even\n");
1443 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1444 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1446 /* This says how to output an assembler line
1447 to define a global common symbol. */
1449 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1450 ( fputs (".comm ", (FILE)), \
1451 assemble_name ((FILE), (NAME)), \
1452 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1454 /* This says how to output an assembler line
1455 to define a local common symbol. */
1457 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1458 ( fputs (".lcomm ", (FILE)), \
1459 assemble_name ((FILE), (NAME)), \
1460 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1462 /* Output a float value (represented as a C double) as an immediate operand.
1463 This macro is a 68k-specific macro. */
1465 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1470 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1471 asm_fprintf ((FILE), "%I0r%s", dstr); \
1476 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1477 asm_fprintf ((FILE), "%I0x%lx", l); \
1481 /* Output a double value (represented as a C double) as an immediate operand.
1482 This macro is a 68k-specific macro. */
1483 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1484 do { char dstr[30]; \
1485 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1486 asm_fprintf (FILE, "%I0r%s", dstr); \
1489 /* Note, long double immediate operands are not actually
1490 generated by m68k.md. */
1491 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1492 do { char dstr[30]; \
1493 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1494 asm_fprintf (FILE, "%I0r%s", dstr); \
1497 /* Print operand X (an rtx) in assembler syntax to file FILE.
1498 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1499 For `%' followed by punctuation, CODE is the punctuation and X is null.
1501 On the 68000, we use several CODE characters:
1502 '.' for dot needed in Motorola-style opcode names.
1503 '-' for an operand pushing on the stack:
1504 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1505 '+' for an operand pushing on the stack:
1506 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1507 '@' for a reference to the top word on the stack:
1508 sp@, (sp) or (%sp) depending on the style of syntax.
1509 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1510 but & in SGS syntax).
1511 '!' for the fpcr register (used in some float-to-fixed conversions).
1512 '$' for the letter `s' in an op code, but only on the 68040.
1513 '&' for the letter `d' in an op code, but only on the 68040.
1514 '/' for register prefix needed by longlong.h.
1516 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1517 'd' to force memory addressing to be absolute, not relative.
1518 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1519 'o' for operands to go directly to output_operand_address (bypassing
1520 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1521 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1522 or print pair of registers as rx:ry. */
1524 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1525 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1526 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1527 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1529 /* A C compound statement to output to stdio stream STREAM the
1530 assembler syntax for an instruction operand X. X is an RTL
1533 CODE is a value that can be used to specify one of several ways
1534 of printing the operand. It is used when identical operands
1535 must be printed differently depending on the context. CODE
1536 comes from the `%' specification that was used to request
1537 printing of the operand. If the specification was just `%DIGIT'
1538 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1539 is the ASCII code for LTR.
1541 If X is a register, this macro should print the register's name.
1542 The names can be found in an array `reg_names' whose type is
1543 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1545 When the machine description has a specification `%PUNCT' (a `%'
1546 followed by a punctuation character), this macro is called with
1547 a null pointer for X and the punctuation character for CODE.
1549 See m68k.c for the m68k specific codes. */
1551 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1553 /* A C compound statement to output to stdio stream STREAM the
1554 assembler syntax for an instruction operand that is a memory
1555 reference whose address is ADDR. ADDR is an RTL expression. */
1557 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1559 /* Variables in m68k.c */
1560 extern const char *m68k_align_loops_string;
1561 extern const char *m68k_align_jumps_string;
1562 extern const char *m68k_align_funcs_string;
1563 extern int m68k_align_loops;
1564 extern int m68k_align_jumps;
1565 extern int m68k_align_funcs;
1566 extern int m68k_last_compare_had_fp_operands;
1569 /* Define the codes that are matched by predicates in m68k.c. */
1571 #define PREDICATE_CODES \
1572 {"general_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1573 LABEL_REF, SUBREG, REG, MEM}}, \
1574 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1575 {"memory_src_operand", {SUBREG, MEM}}, \
1576 {"not_sp_operand", {SUBREG, REG, MEM}}, \
1577 {"pcrel_address", {SYMBOL_REF, LABEL_REF, CONST}}, \
1578 {"const_uint32_operand", {CONST_INT, CONST_DOUBLE}}, \
1579 {"const_sint32_operand", {CONST_INT}}, \
1580 {"valid_dbcc_comparison_p", {EQ, NE, GTU, LTU, GEU, LEU, \
1582 {"extend_operator", {SIGN_EXTEND, ZERO_EXTEND}},