1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
23 if-statements and ?: on it. This way we have compile-time error checking
24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
25 to optimize away all constant tests. */
28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
35 /* Note that some other tm.h files include this one and then override
36 many of the definitions that relate to assembler syntax. */
38 #define TARGET_CPU_CPP_BUILTINS() \
41 builtin_define ("__m68k__"); \
42 builtin_define_std ("mc68000"); \
43 if (TARGET_68040_ONLY) \
46 builtin_define_std ("mc68060"); \
48 builtin_define_std ("mc68040"); \
50 else if (TARGET_68060) /* -m68020-60 */ \
52 builtin_define_std ("mc68060"); \
53 builtin_define_std ("mc68040"); \
54 builtin_define_std ("mc68030"); \
55 builtin_define_std ("mc68020"); \
57 else if (TARGET_68040) /* -m68020-40 */ \
59 builtin_define_std ("mc68040"); \
60 builtin_define_std ("mc68030"); \
61 builtin_define_std ("mc68020"); \
63 else if (TARGET_68030) \
64 builtin_define_std ("mc68030"); \
65 else if (TARGET_68020) \
66 builtin_define_std ("mc68020"); \
68 builtin_define ("__HAVE_68881__"); \
71 builtin_define_std ("mc68332"); \
72 builtin_define_std ("mcpu32"); \
74 if (TARGET_COLDFIRE) \
75 builtin_define ("__mcoldfire__"); \
77 builtin_define ("__mcf5200__"); \
80 builtin_define ("__mcf528x__"); \
81 builtin_define ("__mcf5200__"); \
85 builtin_define ("__mcf5300__"); \
86 builtin_define ("__mcf5307__"); \
90 builtin_define ("__mcf5400__"); \
91 builtin_define ("__mcf5407__"); \
93 if (TARGET_CF_HWDIV) \
94 builtin_define ("__mcfhwdiv__"); \
97 builtin_define ("__pic__"); \
99 builtin_define ("__PIC__"); \
101 builtin_assert ("cpu=m68k"); \
102 builtin_assert ("machine=m68k"); \
106 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
108 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
109 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
110 #define INT_OP_NO_DOT 2 /* byte, short, long */
111 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
113 /* Set the default. */
114 #define INT_OP_GROUP INT_OP_DOT_WORD
116 /* Compile for a CPU32. A 68020 without bitfields is a good
117 heuristic for a CPU32. */
118 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
120 /* Is the target a ColdFire? */
121 #define MASK_COLDFIRE (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4)
122 #define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0)
124 #define OVERRIDE_OPTIONS override_options()
126 /* These are meant to be redefined in the host dependent files */
127 #define SUBTARGET_OVERRIDE_OPTIONS
129 /* target machine storage layout */
131 #define LONG_DOUBLE_TYPE_SIZE 80
133 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
134 instructions, we get proper intermediate rounding, otherwise we
135 get extended precision results. */
136 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2)
138 #define BITS_BIG_ENDIAN 1
139 #define BYTES_BIG_ENDIAN 1
140 #define WORDS_BIG_ENDIAN 1
142 #define UNITS_PER_WORD 4
144 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
145 #define STACK_BOUNDARY 16
146 #define FUNCTION_BOUNDARY 16
147 #define EMPTY_FIELD_BOUNDARY 16
149 /* No data type wants to be aligned rounder than this.
150 Most published ABIs say that ints should be aligned on 16 bit
151 boundaries, but CPUs with 32-bit busses get better performance
152 aligned on 32-bit boundaries. ColdFires without a misalignment
153 module require 32-bit alignment. */
154 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
156 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
158 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
160 /* Define these to avoid dependence on meaning of `int'. */
161 #define WCHAR_TYPE "long int"
162 #define WCHAR_TYPE_SIZE 32
164 /* Maximum number of library IDs we permit with -mid-shared-library. */
165 #define MAX_LIBRARY_ID 255
168 /* Standard register usage. */
170 /* For the m68k, we give the data registers numbers 0-7,
171 the address registers numbers 010-017 (8-15),
172 and the 68881 floating point registers numbers 020-027 (16-24).
173 We also have a fake `arg-pointer' register 030 (25) used for
174 register elimination. */
175 #define FIRST_PSEUDO_REGISTER 25
177 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
178 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
180 /* 1 for registers that have pervasive standard uses
181 and are not available for the register allocator.
182 On the m68k, only the stack pointer is such.
183 Our fake arg-pointer is obviously fixed as well. */
184 #define FIXED_REGISTERS \
185 {/* Data registers. */ \
186 0, 0, 0, 0, 0, 0, 0, 0, \
188 /* Address registers. */ \
189 0, 0, 0, 0, 0, 0, 0, 1, \
191 /* Floating point registers \
193 0, 0, 0, 0, 0, 0, 0, 0, \
198 /* 1 for registers not available across function calls.
199 These must include the FIXED_REGISTERS and also any
200 registers that can be used without being saved.
201 The latter must include the registers where values are returned
202 and the register where structure-value addresses are passed.
203 Aside from that, you can include as many other registers as you like. */
204 #define CALL_USED_REGISTERS \
205 {/* Data registers. */ \
206 1, 1, 0, 0, 0, 0, 0, 0, \
208 /* Address registers. */ \
209 1, 1, 0, 0, 0, 0, 0, 1, \
211 /* Floating point registers \
213 1, 1, 0, 0, 0, 0, 0, 0, \
218 #define REG_ALLOC_ORDER \
219 { /* d0/d1/a0/a1 */ \
224 10, 11, 12, 13, 14, 15, 24, \
226 16, 17, 18, 19, 20, 21, 22, 23\
230 /* Make sure everything's fine if we *don't* have a given processor.
231 This assumes that putting a register in fixed_regs will keep the
232 compiler's mitts completely off it. We don't bother to zero it out
233 of register classes. */
234 #define CONDITIONAL_REGISTER_USAGE \
238 if (! TARGET_68881) \
240 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
241 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
242 if (TEST_HARD_REG_BIT (x, i)) \
243 fixed_regs[i] = call_used_regs[i] = 1; \
245 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
246 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \
247 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
250 /* On the m68k, ordinary registers hold 32 bits worth;
251 for the 68881 registers, a single register is always enough for
252 anything that can be stored in them at all. */
253 #define HARD_REGNO_NREGS(REGNO, MODE) \
254 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
255 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
257 /* A C expression that is nonzero if hard register NEW_REG can be
258 considered for use as a rename register for OLD_REG register. */
260 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
261 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
263 /* On the m68k, the cpu registers can hold any mode but the 68881 registers
264 can hold only SFmode or DFmode. */
265 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
267 && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE (MODE) / 4 > 8)) \
268 || ((REGNO) >= 16 && (REGNO) < 24 \
269 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
270 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
271 && GET_MODE_UNIT_SIZE (MODE) <= 12))
273 #define MODES_TIEABLE_P(MODE1, MODE2) \
275 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
276 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
277 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
278 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
280 /* Specify the registers used for certain standard purposes.
281 The values of these macros are register numbers. */
283 #define STACK_POINTER_REGNUM 15
285 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
286 ABI uses %a6 for shared library calls, therefore the frame
287 pointer is shifted to %a5 on this target. */
288 #define FRAME_POINTER_REGNUM 14
290 #define FRAME_POINTER_REQUIRED 0
292 /* Base register for access to arguments of the function.
293 * This isn't a hardware register. It will be eliminated to the
294 * stack pointer or frame pointer.
296 #define ARG_POINTER_REGNUM 24
298 #define STATIC_CHAIN_REGNUM 8
300 /* Register in which address to store a structure value
301 is passed to a function. */
302 #define M68K_STRUCT_VALUE_REGNUM 9
306 /* The m68k has three kinds of registers, so eight classes would be
307 a complete set. One of them is not needed. */
311 GENERAL_REGS, DATA_OR_FP_REGS,
312 ADDR_OR_FP_REGS, ALL_REGS,
315 #define N_REG_CLASSES (int) LIM_REG_CLASSES
317 #define REG_CLASS_NAMES \
318 { "NO_REGS", "DATA_REGS", \
319 "ADDR_REGS", "FP_REGS", \
320 "GENERAL_REGS", "DATA_OR_FP_REGS", \
321 "ADDR_OR_FP_REGS", "ALL_REGS" }
323 #define REG_CLASS_CONTENTS \
325 {0x00000000}, /* NO_REGS */ \
326 {0x000000ff}, /* DATA_REGS */ \
327 {0x0100ff00}, /* ADDR_REGS */ \
328 {0x00ff0000}, /* FP_REGS */ \
329 {0x0100ffff}, /* GENERAL_REGS */ \
330 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
331 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
332 {0x01ffffff}, /* ALL_REGS */ \
335 extern enum reg_class regno_reg_class[];
336 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
337 #define INDEX_REG_CLASS GENERAL_REGS
338 #define BASE_REG_CLASS ADDR_REGS
340 /* We do a trick here to modify the effective constraints on the
341 machine description; we zorch the constraint letters that aren't
342 appropriate for a specific target. This allows us to guarantee
343 that a specific kind of register will not be used for a given target
344 without fiddling with the register classes above. */
345 #define REG_CLASS_FROM_LETTER(C) \
346 ((C) == 'a' ? ADDR_REGS : \
347 ((C) == 'd' ? DATA_REGS : \
348 ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
352 /* For the m68k, `I' is used for the range 1 to 8
353 allowed as immediate shift counts and in addq.
354 `J' is used for the range of signed numbers that fit in 16 bits.
355 `K' is for numbers that moveq can't handle.
356 `L' is for range -8 to -1, range of values that can be added with subq.
357 `M' is for numbers that moveq+notb can't handle.
358 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
359 'O' is for 16 (for rotate using swap).
360 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
361 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
362 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
363 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
364 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
365 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
366 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \
367 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \
368 (C) == 'O' ? (VALUE) == 16 : \
369 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
371 /* "G" defines all of the floating constants that are *NOT* 68881
372 constants. This is so 68881 constants get reloaded and the
374 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
375 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
377 /* `Q' means address register indirect addressing mode.
378 `S' is for operands that satisfy 'm' when -mpcrel is in effect.
379 `T' is for operands that satisfy 's' when -mpcrel is not in effect.
380 `U' is for register offset addressing. */
381 #define EXTRA_CONSTRAINT(OP,CODE) \
384 && GET_CODE (OP) == MEM \
385 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
386 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \
387 || GET_CODE (XEXP (OP, 0)) == CONST)) \
391 && (GET_CODE (OP) == SYMBOL_REF \
392 || GET_CODE (OP) == LABEL_REF \
393 || GET_CODE (OP) == CONST)) \
396 ? (GET_CODE (OP) == MEM \
397 && GET_CODE (XEXP (OP, 0)) == REG) \
400 ? (GET_CODE (OP) == MEM \
401 && GET_CODE (XEXP (OP, 0)) == PLUS \
402 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
403 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
407 /* On the m68k, use a data reg if possible when the
408 value is a constant in the range where moveq could be used
409 and we ensure that QImodes are reloaded into data regs. */
410 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
411 ((GET_CODE (X) == CONST_INT \
412 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
413 && (CLASS) != ADDR_REGS) \
415 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
417 : (GET_CODE (X) == CONST_DOUBLE \
418 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
419 ? (TARGET_68881 && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \
420 ? FP_REGS : NO_REGS) \
422 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
423 || GET_CODE (X) == LABEL_REF)) \
427 /* Force QImode output reloads from subregs to be allocated to data regs,
428 since QImode stores from address regs are not supported. We make the
429 assumption that if the class is not ADDR_REGS, then it must be a superset
431 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
432 (((MODE) == QImode && (CLASS) != ADDR_REGS) \
436 /* On the m68k, this is the size of MODE in words,
437 except in the FP regs, where a single reg is always enough. */
438 #define CLASS_MAX_NREGS(CLASS, MODE) \
439 ((CLASS) == FP_REGS ? 1 \
440 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
442 /* Moves between fp regs and other regs are two insns. */
443 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
444 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
445 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
448 /* Stack layout; function entry, exit and calling. */
450 #define STACK_GROWS_DOWNWARD
451 #define FRAME_GROWS_DOWNWARD
452 #define STARTING_FRAME_OFFSET 0
454 /* On the 680x0, sp@- in a byte insn really pushes a word.
455 On the ColdFire, sp@- in a byte insn pushes just a byte. */
456 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
458 #define FIRST_PARM_OFFSET(FNDECL) 8
460 /* On the 68000, the RTS insn cannot pop anything.
461 On the 68010, the RTD insn may be used to pop them if the number
462 of args is fixed, but if the number is variable then the caller
463 must pop them all. RTD can't be used for library calls now
464 because the library is compiled with the Unix compiler.
465 Use of RTD is a selectable option, since it is incompatible with
466 standard Unix calling sequences. If the option is not selected,
467 the caller must always pop the args. */
468 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
469 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
470 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
471 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
472 == void_type_node))) \
475 /* On the m68k the return value is always in D0. */
476 #define FUNCTION_VALUE(VALTYPE, FUNC) \
477 gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
479 /* On the m68k the return value is always in D0. */
480 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
482 /* On the m68k, D0 is the only register used. */
483 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
485 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
486 more than one register.
487 XXX This macro is m68k specific and used only for m68kemb.h. */
488 #define NEEDS_UNTYPED_CALL 0
490 #define PCC_STATIC_STRUCT_RETURN
492 /* On the m68k, all arguments are usually pushed on the stack. */
493 #define FUNCTION_ARG_REGNO_P(N) 0
495 /* On the m68k, this is a single integer, which is a number of bytes
496 of arguments scanned so far. */
497 #define CUMULATIVE_ARGS int
499 /* On the m68k, the offset starts at 0. */
500 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
503 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
504 ((CUM) += ((MODE) != BLKmode \
505 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
506 : (int_size_in_bytes (TYPE) + 3) & ~3))
508 /* On the m68k all args are always pushed. */
509 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
511 #define FUNCTION_PROFILER(FILE, LABELNO) \
512 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
514 #define EXIT_IGNORE_STACK 1
516 /* Determine if the epilogue should be output as RTL.
517 You should override this if you define FUNCTION_EXTRA_EPILOGUE.
519 XXX This macro is m68k-specific and only used in m68k.md. */
520 #define USE_RETURN_INSN use_return_insn ()
522 /* Output assembler code for a block containing the constant parts
523 of a trampoline, leaving space for the variable parts.
525 On the m68k, the trampoline looks like this:
529 WARNING: Targets that may run on 68040+ cpus must arrange for
530 the instruction cache to be flushed. Previous incarnations of
531 the m68k trampoline code attempted to get around this by either
532 using an out-of-line transfer function or pc-relative data, but
533 the fact remains that the code to jump to the transfer function
534 or the code to load the pc-relative data needs to be flushed
535 just as much as the "variable" portion of the trampoline.
536 Recognizing that a cache flush is going to be required anyway,
537 dispense with such notions and build a smaller trampoline.
539 Since more instructions are required to move a template into
540 place than to create it on the spot, don't use a template. */
542 #define TRAMPOLINE_SIZE 12
543 #define TRAMPOLINE_ALIGNMENT 16
545 /* Targets redefine this to invoke code to either flush the cache,
546 or enable stack execution (or both). */
547 #ifndef FINALIZE_TRAMPOLINE
548 #define FINALIZE_TRAMPOLINE(TRAMP)
551 /* We generate a two-instructions program at address TRAMP :
554 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
556 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \
557 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
558 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
560 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
561 FINALIZE_TRAMPOLINE(TRAMP); \
564 /* This is the library routine that is used to transfer control from the
565 trampoline to the actual nested function. It is defined for backward
566 compatibility, for linking with object code that used the old trampoline
569 A colon is used with no explicit operands to cause the template string
570 to be scanned for %-constructs.
572 The function name __transfer_from_trampoline is not actually used.
573 The function definition just permits use of "asm with operands"
574 (though the operand list is empty). */
575 #define TRANSFER_FROM_TRAMPOLINE \
577 __transfer_from_trampoline () \
579 register char *a0 asm ("%a0"); \
580 asm (GLOBAL_ASM_OP "___trampoline"); \
581 asm ("___trampoline:"); \
582 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
583 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
587 /* There are two registers that can always be eliminated on the m68k.
588 The frame pointer and the arg pointer can be replaced by either the
589 hard frame pointer or to the stack pointer, depending upon the
590 circumstances. The hard frame pointer is not used before reload and
591 so it is not eligible for elimination. */
592 #define ELIMINABLE_REGS \
593 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
594 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
595 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
597 #define CAN_ELIMINATE(FROM, TO) \
598 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
600 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
601 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
603 /* Addressing modes, and classification of registers for them. */
605 #define HAVE_POST_INCREMENT 1
606 #define HAVE_PRE_DECREMENT 1
608 /* Macros to check register numbers against specific register classes. */
610 #define REGNO_OK_FOR_INDEX_P(REGNO) \
611 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
612 #define REGNO_OK_FOR_BASE_P(REGNO) \
613 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
614 #define REGNO_OK_FOR_DATA_P(REGNO) \
615 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
616 #define REGNO_OK_FOR_FP_P(REGNO) \
617 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
619 /* Now macros that check whether X is a register and also,
620 strictly, whether it is in a specified class.
622 These macros are specific to the m68k, and may be used only
623 in code for printing assembler insns and in conditions for
624 define_optimization. */
626 /* 1 if X is a data register. */
627 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
629 /* 1 if X is an fp register. */
630 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
632 /* 1 if X is an address register */
633 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
636 #define MAX_REGS_PER_ADDRESS 2
638 #define CONSTANT_ADDRESS_P(X) \
639 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
640 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
641 || GET_CODE (X) == HIGH)
643 /* Nonzero if the constant value X is a legitimate general operand.
644 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
645 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode)
647 #ifndef REG_OK_STRICT
648 #define PCREL_GENERAL_OPERAND_OK 0
650 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL)
653 #define LEGITIMATE_PIC_OPERAND_P(X) \
654 (! symbolic_operand (X, VOIDmode) \
655 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \
656 || PCREL_GENERAL_OPERAND_OK)
658 #ifndef REG_OK_STRICT
660 /* Nonzero if X is a hard reg that can be used as an index
661 or if it is a pseudo reg. */
662 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
663 /* Nonzero if X is a hard reg that can be used as a base reg
664 or if it is a pseudo reg. */
665 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
669 /* Nonzero if X is a hard reg that can be used as an index. */
670 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
671 /* Nonzero if X is a hard reg that can be used as a base reg. */
672 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
676 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
677 that is a valid memory address for an instruction.
678 The MODE argument is the machine mode for the MEM expression
679 that wants to use this address.
681 When generating PIC, an address involving a SYMBOL_REF is legitimate
682 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
683 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
684 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
686 Likewise for a LABEL_REF when generating PIC.
688 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
690 /* Allow SUBREG everywhere we allow REG. This results in better code. It
691 also makes function inlining work when inline functions are called with
692 arguments that are SUBREGs. */
694 #define LEGITIMATE_BASE_REG_P(X) \
695 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
696 || (GET_CODE (X) == SUBREG \
697 && GET_CODE (SUBREG_REG (X)) == REG \
698 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
700 #define INDIRECTABLE_1_ADDRESS_P(X) \
701 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
702 || LEGITIMATE_BASE_REG_P (X) \
703 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
704 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \
705 || (GET_CODE (X) == PLUS \
706 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \
707 && GET_CODE (XEXP (X, 1)) == CONST_INT \
709 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \
710 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
711 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
712 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
713 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF))
715 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
716 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
718 /* Only labels on dispatch tables are valid for indexing from. */
719 #define GO_IF_INDEXABLE_BASE(X, ADDR) \
721 if (GET_CODE (X) == LABEL_REF \
722 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
723 && GET_CODE (temp) == JUMP_INSN \
724 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
725 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
727 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; }
729 #define GO_IF_INDEXING(X, ADDR) \
730 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
731 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
732 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
733 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
735 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
736 { GO_IF_INDEXING (X, ADDR); \
737 if (GET_CODE (X) == PLUS) \
738 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
739 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \
740 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
741 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
742 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
743 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
745 /* ColdFire/5200 does not allow HImode index registers. */
746 #define LEGITIMATE_INDEX_REG_P(X) \
747 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
748 || (! TARGET_COLDFIRE \
749 && GET_CODE (X) == SIGN_EXTEND \
750 && GET_CODE (XEXP (X, 0)) == REG \
751 && GET_MODE (XEXP (X, 0)) == HImode \
752 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
753 || (GET_CODE (X) == SUBREG \
754 && GET_CODE (SUBREG_REG (X)) == REG \
755 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
757 #define LEGITIMATE_INDEX_P(X) \
758 (LEGITIMATE_INDEX_REG_P (X) \
759 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
760 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
761 && GET_CODE (XEXP (X, 1)) == CONST_INT \
762 && (INTVAL (XEXP (X, 1)) == 2 \
763 || INTVAL (XEXP (X, 1)) == 4 \
764 || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
766 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
767 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
768 { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
769 GO_IF_INDEXED_ADDRESS (X, ADDR); \
770 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \
771 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \
772 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \
775 /* Don't call memory_address_noforce for the address to fetch
776 the switch offset. This address is ok as it stands (see above),
777 but memory_address_noforce would alter it. */
778 #define PIC_CASE_VECTOR_ADDRESS(index) index
780 /* For the 68000, we handle X+REG by loading X into a register R and
781 using R+REG. R will go in an address reg and indexing will be used.
782 However, if REG is a broken-out memory address or multiplication,
783 nothing needs to be done because REG can certainly go in an address reg. */
784 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
785 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
786 { register int ch = (X) != (OLDX); \
787 if (GET_CODE (X) == PLUS) \
789 if (GET_CODE (XEXP (X, 0)) == MULT) \
790 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
791 if (GET_CODE (XEXP (X, 1)) == MULT) \
792 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
793 if (ch && GET_CODE (XEXP (X, 1)) == REG \
794 && GET_CODE (XEXP (X, 0)) == REG) \
796 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
797 if (GET_CODE (XEXP (X, 0)) == REG \
798 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
799 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
800 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
801 { register rtx temp = gen_reg_rtx (Pmode); \
802 register rtx val = force_operand (XEXP (X, 1), 0); \
803 emit_move_insn (temp, val); \
805 XEXP (X, 1) = temp; \
807 else if (GET_CODE (XEXP (X, 1)) == REG \
808 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
809 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
810 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
811 { register rtx temp = gen_reg_rtx (Pmode); \
812 register rtx val = force_operand (XEXP (X, 0), 0); \
813 emit_move_insn (temp, val); \
815 XEXP (X, 0) = temp; \
818 /* On the 68000, only predecrement and postincrement address depend thus
819 (the amount of decrement or increment being the length of the operand). */
820 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
821 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
823 #define CASE_VECTOR_MODE HImode
824 #define CASE_VECTOR_PC_RELATIVE 1
826 #define DEFAULT_SIGNED_CHAR 1
828 #define SLOW_BYTE_ACCESS 0
830 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
832 #define STORE_FLAG_VALUE (-1)
835 #define FUNCTION_MODE QImode
838 /* Tell final.c how to eliminate redundant test instructions. */
840 /* Here we define machine-dependent flags and fields in cc_status
841 (see `conditions.h'). */
843 /* Set if the cc value is actually in the 68881, so a floating point
844 conditional branch must be output. */
845 #define CC_IN_68881 04000
847 /* On the 68000, all the insns to store in an address register fail to
848 set the cc's. However, in some cases these instructions can make it
849 possibly invalid to use the saved cc's. In those cases we clear out
850 some or all of the saved cc's so they won't be used. */
851 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
853 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
854 do { if (cc_prev_status.flags & CC_IN_68881) \
856 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
858 return NORMAL; } while (0)
860 /* Control the assembler format that we output. */
862 #define ASM_APP_ON "#APP\n"
863 #define ASM_APP_OFF "#NO_APP\n"
864 #define TEXT_SECTION_ASM_OP "\t.text"
865 #define DATA_SECTION_ASM_OP "\t.data"
866 #define GLOBAL_ASM_OP "\t.globl\t"
867 #define REGISTER_PREFIX ""
868 #define LOCAL_LABEL_PREFIX ""
869 #define USER_LABEL_PREFIX "_"
870 #define IMMEDIATE_PREFIX "#"
872 #define REGISTER_NAMES \
873 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
874 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
875 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
876 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
877 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
878 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
879 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
880 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
881 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
883 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
885 /* Return a register name by index, handling %fp nicely.
886 We don't replace %fp for targets that don't map it to %a6
887 since it may confuse GAS. */
888 #define M68K_REGNAME(r) ( \
889 ((FRAME_POINTER_REGNUM == 14) \
890 && ((r) == FRAME_POINTER_REGNUM) \
891 && frame_pointer_needed) ? \
892 M68K_FP_REG_NAME : reg_names[(r)])
894 /* On the Sun-3, the floating point registers have numbers
895 18 to 25, not 16 to 23 as they do in the compiler. */
896 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
898 /* Before the prologue, RA is at 0(%sp). */
899 #define INCOMING_RETURN_ADDR_RTX \
900 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
902 /* We must not use the DBX register numbers for the DWARF 2 CFA column
903 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
904 Instead use the identity mapping. */
905 #define DWARF_FRAME_REGNUM(REG) REG
907 /* Before the prologue, the top of the frame is at 4(%sp). */
908 #define INCOMING_FRAME_SP_OFFSET 4
910 /* Describe how we implement __builtin_eh_return. */
911 #define EH_RETURN_DATA_REGNO(N) \
912 ((N) < 2 ? (N) : INVALID_REGNUM)
913 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8)
914 #define EH_RETURN_HANDLER_RTX \
915 gen_rtx_MEM (Pmode, \
916 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
917 plus_constant (EH_RETURN_STACKADJ_RTX, \
920 /* Select a format to encode pointers in exception handling data. CODE
921 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
922 true if the symbol may be affected by dynamic relocations. */
923 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
925 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
928 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
929 asm_fprintf (FILE, "%U%s", NAME)
931 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
932 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
934 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
935 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
936 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
937 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
939 /* The m68k does not use absolute case-vectors, but we must define this macro
941 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
942 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
944 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
945 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
947 /* We don't have a way to align to more than a two-byte boundary, so do the
948 best we can and don't complain. */
949 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
951 fprintf (FILE, "\t.even\n");
953 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
954 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
956 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
957 ( fputs (".comm ", (FILE)), \
958 assemble_name ((FILE), (NAME)), \
959 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
961 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
962 ( fputs (".lcomm ", (FILE)), \
963 assemble_name ((FILE), (NAME)), \
964 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
966 /* Output a float value (represented as a C double) as an immediate operand.
967 This macro is m68k-specific. */
968 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
973 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
974 asm_fprintf ((FILE), "%I0r%s", dstr); \
979 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
980 asm_fprintf ((FILE), "%I0x%lx", l); \
984 /* Output a double value (represented as a C double) as an immediate operand.
985 This macro is m68k-specific. */
986 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
987 do { char dstr[30]; \
988 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
989 asm_fprintf (FILE, "%I0r%s", dstr); \
992 /* Note, long double immediate operands are not actually
993 generated by m68k.md. */
994 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
995 do { char dstr[30]; \
996 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
997 asm_fprintf (FILE, "%I0r%s", dstr); \
1000 /* On the 68000, we use several CODE characters:
1001 '.' for dot needed in Motorola-style opcode names.
1002 '-' for an operand pushing on the stack:
1003 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1004 '+' for an operand pushing on the stack:
1005 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1006 '@' for a reference to the top word on the stack:
1007 sp@, (sp) or (%sp) depending on the style of syntax.
1008 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1009 but & in SGS syntax).
1010 '!' for the fpcr register (used in some float-to-fixed conversions).
1011 '$' for the letter `s' in an op code, but only on the 68040.
1012 '&' for the letter `d' in an op code, but only on the 68040.
1013 '/' for register prefix needed by longlong.h.
1015 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1016 'd' to force memory addressing to be absolute, not relative.
1017 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1018 'o' for operands to go directly to output_operand_address (bypassing
1019 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL)
1020 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1021 or print pair of registers as rx:ry. */
1023 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1024 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1025 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1026 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/')
1029 /* See m68k.c for the m68k specific codes. */
1030 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1032 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1034 /* Variables in m68k.c */
1035 extern const char *m68k_library_id_string;
1036 extern int m68k_last_compare_had_fp_operands;