1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* We need to have MOTOROLA always defined (either 0 or 1) because we use
22 if-statements and ?: on it. This way we have compile-time error checking
23 for both the MOTOROLA and MIT code paths. We do rely on the host compiler
24 to optimize away all constant tests. */
25 #if MOTOROLA /* Use the Motorola assembly syntax. */
26 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)")
28 # define MOTOROLA 0 /* Use the MIT assembly syntax. */
29 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)")
32 /* Options 0 and 1 are the Motorola and MIT syntaxes,
34 #define ASSEMBLER_DIALECT !MOTOROLA
36 /* Handle --with-cpu default option from configure script. */
37 #define OPTION_DEFAULT_SPECS \
38 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\
39 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\
40 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\
41 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" },
43 /* Pass flags to gas indicating which type of processor we have. This
44 can be simplified when we can rely on the assembler supporting .cpu
45 and .arch directives. */
47 #define ASM_CPU_SPEC "\
48 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \
49 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\
50 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\
51 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\
52 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\
54 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \
55 %{msep-data|mid-shared-library:--pcrel} \
58 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)"
61 { "asm_cpu_spec", ASM_CPU_SPEC }, \
62 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \
65 #define SUBTARGET_EXTRA_SPECS
67 /* Note that some other tm.h files include this one and then override
68 many of the definitions that relate to assembler syntax. */
70 #define TARGET_CPU_CPP_BUILTINS() \
73 builtin_define ("__m68k__"); \
74 builtin_define_std ("mc68000"); \
75 /* The other mc680x0 macros have traditionally been derived \
76 from the tuning setting. For example, -m68020-60 defines \
77 m68060, even though it generates pure 68020 code. */ \
81 builtin_define_std ("mc68010"); \
85 builtin_define_std ("mc68020"); \
89 builtin_define_std ("mc68030"); \
93 builtin_define_std ("mc68040"); \
97 builtin_define_std ("mc68060"); \
101 builtin_define_std ("mc68060"); \
102 /* Fall through. */ \
104 builtin_define_std ("mc68040"); \
105 builtin_define_std ("mc68030"); \
106 builtin_define_std ("mc68020"); \
110 builtin_define_std ("mc68332"); \
111 builtin_define_std ("mcpu32"); \
112 builtin_define_std ("mc68020"); \
116 builtin_define ("__mcfv1__"); \
120 builtin_define ("__mcfv2__"); \
124 builtin_define ("__mcfv3__"); \
128 builtin_define ("__mcfv4__"); \
132 builtin_define ("__mcfv4e__"); \
136 builtin_define ("__mcfv5__"); \
144 builtin_define ("__HAVE_68881__"); \
146 if (TARGET_COLDFIRE) \
150 tmp = m68k_cpp_cpu_ident ("cf"); \
152 builtin_define (tmp); \
153 tmp = m68k_cpp_cpu_family ("cf"); \
155 builtin_define (tmp); \
156 builtin_define ("__mcoldfire__"); \
159 builtin_define ("__mcfisac__"); \
160 else if (TARGET_ISAB) \
162 builtin_define ("__mcfisab__"); \
163 /* ISA_B: Legacy 5407 defines. */ \
164 builtin_define ("__mcf5400__"); \
165 builtin_define ("__mcf5407__"); \
167 else if (TARGET_ISAAPLUS) \
169 builtin_define ("__mcfisaaplus__"); \
170 /* ISA_A+: legacy defines. */ \
171 builtin_define ("__mcf528x__"); \
172 builtin_define ("__mcf5200__"); \
176 builtin_define ("__mcfisaa__"); \
177 /* ISA_A: legacy defines. */ \
181 builtin_define ("__mcf5200__"); \
185 builtin_define ("__mcf5307__"); \
186 builtin_define ("__mcf5300__"); \
195 if (TARGET_COLDFIRE_FPU) \
196 builtin_define ("__mcffpu__"); \
198 if (TARGET_CF_HWDIV) \
199 builtin_define ("__mcfhwdiv__"); \
202 builtin_define ("__mfido__"); \
204 builtin_assert ("cpu=m68k"); \
205 builtin_assert ("machine=m68k"); \
209 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI
211 #define INT_OP_STANDARD 0 /* .byte, .short, .long */
212 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */
213 #define INT_OP_NO_DOT 2 /* byte, short, long */
214 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */
216 /* Set the default. */
217 #define INT_OP_GROUP INT_OP_DOT_WORD
219 /* Bit values used by m68k-devices.def to identify processor capabilities. */
220 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */
221 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */
222 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */
223 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */
224 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */
225 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */
226 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */
227 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */
228 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */
229 #define FL_ISA_68000 (1 << 9)
230 #define FL_ISA_68010 (1 << 10)
231 #define FL_ISA_68020 (1 << 11)
232 #define FL_ISA_68040 (1 << 12)
233 #define FL_ISA_A (1 << 13)
234 #define FL_ISA_APLUS (1 << 14)
235 #define FL_ISA_B (1 << 15)
236 #define FL_ISA_C (1 << 16)
237 #define FL_FIDOA (1 << 17)
238 #define FL_MMU 0 /* Used by multilib machinery. */
240 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
241 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
242 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0)
243 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0)
244 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE)
245 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881)
246 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0)
248 /* Size (in bytes) of FPU registers. */
249 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12)
251 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0)
252 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0)
253 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0)
255 /* Some instructions are common to more than one ISA. */
256 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC)
257 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC)
259 #define TUNE_68000 (m68k_tune == u68000)
260 #define TUNE_68010 (m68k_tune == u68010)
261 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010)
262 #define TUNE_68030 (m68k_tune == u68030 \
263 || m68k_tune == u68020_40 \
264 || m68k_tune == u68020_60)
265 #define TUNE_68040 (m68k_tune == u68040 \
266 || m68k_tune == u68020_40 \
267 || m68k_tune == u68020_60)
268 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60)
269 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060)
270 #define TUNE_CPU32 (m68k_tune == ucpu32)
271 #define TUNE_CFV1 (m68k_tune == ucfv1)
272 #define TUNE_CFV2 (m68k_tune == ucfv2)
274 #define OVERRIDE_OPTIONS override_options()
276 /* These are meant to be redefined in the host dependent files */
277 #define SUBTARGET_OVERRIDE_OPTIONS
279 /* target machine storage layout */
281 /* "long double" is the same as "double" on ColdFire and fido
284 #define LONG_DOUBLE_TYPE_SIZE \
285 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80)
287 /* We need to know the size of long double at compile-time in libgcc2. */
289 #if defined(__mcoldfire__) || defined(__mfido__)
290 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
292 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80
295 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
296 instructions, we get proper intermediate rounding, otherwise we
297 get extended precision results. */
298 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2)
300 #define BITS_BIG_ENDIAN 1
301 #define BYTES_BIG_ENDIAN 1
302 #define WORDS_BIG_ENDIAN 1
304 #define UNITS_PER_WORD 4
306 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
307 #define STACK_BOUNDARY 16
308 #define FUNCTION_BOUNDARY 16
309 #define EMPTY_FIELD_BOUNDARY 16
310 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */
311 #define PREFERRED_STACK_BOUNDARY \
312 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16)
314 /* No data type wants to be aligned rounder than this.
315 Most published ABIs say that ints should be aligned on 16-bit
316 boundaries, but CPUs with 32-bit busses get better performance
317 aligned on 32-bit boundaries. */
318 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
320 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT)
321 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1
323 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
325 /* Define these to avoid dependence on meaning of `int'. */
326 #define WCHAR_TYPE "long int"
327 #define WCHAR_TYPE_SIZE 32
329 /* Maximum number of library IDs we permit with -mid-shared-library. */
330 #define MAX_LIBRARY_ID 255
333 /* Standard register usage. */
335 /* For the m68k, we give the data registers numbers 0-7,
336 the address registers numbers 010-017 (8-15),
337 and the 68881 floating point registers numbers 020-027 (16-23).
338 We also have a fake `arg-pointer' register 030 (24) used for
339 register elimination. */
340 #define FIRST_PSEUDO_REGISTER 25
342 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */
343 #define PIC_OFFSET_TABLE_REGNUM \
344 (!flag_pic ? INVALID_REGNUM \
345 : reload_completed ? REGNO (pic_offset_table_rtx) \
348 /* 1 for registers that have pervasive standard uses
349 and are not available for the register allocator.
350 On the m68k, only the stack pointer is such.
351 Our fake arg-pointer is obviously fixed as well. */
352 #define FIXED_REGISTERS \
353 {/* Data registers. */ \
354 0, 0, 0, 0, 0, 0, 0, 0, \
356 /* Address registers. */ \
357 0, 0, 0, 0, 0, 0, 0, 1, \
359 /* Floating point registers \
361 0, 0, 0, 0, 0, 0, 0, 0, \
366 /* 1 for registers not available across function calls.
367 These must include the FIXED_REGISTERS and also any
368 registers that can be used without being saved.
369 The latter must include the registers where values are returned
370 and the register where structure-value addresses are passed.
371 Aside from that, you can include as many other registers as you like. */
372 #define CALL_USED_REGISTERS \
373 {/* Data registers. */ \
374 1, 1, 0, 0, 0, 0, 0, 0, \
376 /* Address registers. */ \
377 1, 1, 0, 0, 0, 0, 0, 1, \
379 /* Floating point registers \
381 1, 1, 0, 0, 0, 0, 0, 0, \
386 #define REG_ALLOC_ORDER \
387 { /* d0/d1/a0/a1 */ \
392 10, 11, 12, 13, 14, 15, 24, \
394 16, 17, 18, 19, 20, 21, 22, 23\
398 /* Make sure everything's fine if we *don't* have a given processor.
399 This assumes that putting a register in fixed_regs will keep the
400 compiler's mitts completely off it. We don't bother to zero it out
401 of register classes. */
402 #define CONDITIONAL_REGISTER_USAGE \
406 if (!TARGET_HARD_FLOAT) \
408 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
409 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \
410 if (TEST_HARD_REG_BIT (x, i)) \
411 fixed_regs[i] = call_used_regs[i] = 1; \
414 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \
417 /* On the m68k, ordinary registers hold 32 bits worth;
418 for the 68881 registers, a single register is always enough for
419 anything that can be stored in them at all. */
420 #define HARD_REGNO_NREGS(REGNO, MODE) \
421 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
422 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
424 /* A C expression that is nonzero if hard register NEW_REG can be
425 considered for use as a rename register for OLD_REG register. */
427 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
428 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG)
430 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
431 m68k_regno_mode_ok ((REGNO), (MODE))
433 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
434 m68k_secondary_reload_class (CLASS, MODE, X)
436 #define MODES_TIEABLE_P(MODE1, MODE2) \
437 (! TARGET_HARD_FLOAT \
438 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
439 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
440 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
441 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
443 /* Specify the registers used for certain standard purposes.
444 The values of these macros are register numbers. */
446 #define STACK_POINTER_REGNUM SP_REG
448 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS
449 ABI uses %a6 for shared library calls, therefore the frame
450 pointer is shifted to %a5 on this target. */
451 #define FRAME_POINTER_REGNUM A6_REG
453 #define FRAME_POINTER_REQUIRED 0
455 /* Base register for access to arguments of the function.
456 * This isn't a hardware register. It will be eliminated to the
457 * stack pointer or frame pointer.
459 #define ARG_POINTER_REGNUM 24
461 #define STATIC_CHAIN_REGNUM A0_REG
462 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0"
464 /* Register in which address to store a structure value
465 is passed to a function. */
466 #define M68K_STRUCT_VALUE_REGNUM A1_REG
470 /* The m68k has three kinds of registers, so eight classes would be
471 a complete set. One of them is not needed. */
475 GENERAL_REGS, DATA_OR_FP_REGS,
476 ADDR_OR_FP_REGS, ALL_REGS,
479 #define N_REG_CLASSES (int) LIM_REG_CLASSES
481 #define REG_CLASS_NAMES \
482 { "NO_REGS", "DATA_REGS", \
483 "ADDR_REGS", "FP_REGS", \
484 "GENERAL_REGS", "DATA_OR_FP_REGS", \
485 "ADDR_OR_FP_REGS", "ALL_REGS" }
487 #define REG_CLASS_CONTENTS \
489 {0x00000000}, /* NO_REGS */ \
490 {0x000000ff}, /* DATA_REGS */ \
491 {0x0100ff00}, /* ADDR_REGS */ \
492 {0x00ff0000}, /* FP_REGS */ \
493 {0x0100ffff}, /* GENERAL_REGS */ \
494 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \
495 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \
496 {0x01ffffff}, /* ALL_REGS */ \
499 extern enum reg_class regno_reg_class[];
500 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
501 #define INDEX_REG_CLASS GENERAL_REGS
502 #define BASE_REG_CLASS ADDR_REGS
504 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
505 m68k_preferred_reload_class (X, CLASS)
507 /* On the m68k, this is the size of MODE in words,
508 except in the FP regs, where a single reg is always enough. */
509 #define CLASS_MAX_NREGS(CLASS, MODE) \
510 ((CLASS) == FP_REGS ? 1 \
511 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
513 /* Moves between fp regs and other regs are two insns. */
514 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
515 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2)
517 /* Stack layout; function entry, exit and calling. */
519 #define STACK_GROWS_DOWNWARD 1
520 #define FRAME_GROWS_DOWNWARD 1
521 #define STARTING_FRAME_OFFSET 0
523 /* On the 680x0, sp@- in a byte insn really pushes a word.
524 On the ColdFire, sp@- in a byte insn pushes just a byte. */
525 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
527 #define FIRST_PARM_OFFSET(FNDECL) 8
529 /* On the 68000, the RTS insn cannot pop anything.
530 On the 68010, the RTD insn may be used to pop them if the number
531 of args is fixed, but if the number is variable then the caller
532 must pop them all. RTD can't be used for library calls now
533 because the library is compiled with the Unix compiler.
534 Use of RTD is a selectable option, since it is incompatible with
535 standard Unix calling sequences. If the option is not selected,
536 the caller must always pop the args. */
537 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
538 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \
539 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
540 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
541 == void_type_node))) \
544 /* On the m68k the return value defaults to D0. */
545 #define FUNCTION_VALUE(VALTYPE, FUNC) \
546 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG)
548 /* On the m68k the return value defaults to D0. */
549 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG)
551 /* On the m68k, D0 is usually the only register used. */
552 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG)
554 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for
555 more than one register.
556 XXX This macro is m68k specific and used only for m68kemb.h. */
557 #define NEEDS_UNTYPED_CALL 0
559 /* On the m68k, all arguments are usually pushed on the stack. */
560 #define FUNCTION_ARG_REGNO_P(N) 0
562 /* On the m68k, this is a single integer, which is a number of bytes
563 of arguments scanned so far. */
564 #define CUMULATIVE_ARGS int
566 /* On the m68k, the offset starts at 0. */
567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
570 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
571 ((CUM) += ((MODE) != BLKmode \
572 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
573 : (int_size_in_bytes (TYPE) + 3) & ~3))
575 /* On the m68k all args are always pushed. */
576 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
578 #define FUNCTION_PROFILER(FILE, LABELNO) \
579 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
581 #define EXIT_IGNORE_STACK 1
583 /* Output assembler code for a block containing the constant parts
584 of a trampoline, leaving space for the variable parts.
586 On the m68k, the trampoline looks like this:
590 WARNING: Targets that may run on 68040+ cpus must arrange for
591 the instruction cache to be flushed. Previous incarnations of
592 the m68k trampoline code attempted to get around this by either
593 using an out-of-line transfer function or pc-relative data, but
594 the fact remains that the code to jump to the transfer function
595 or the code to load the pc-relative data needs to be flushed
596 just as much as the "variable" portion of the trampoline.
597 Recognizing that a cache flush is going to be required anyway,
598 dispense with such notions and build a smaller trampoline.
600 Since more instructions are required to move a template into
601 place than to create it on the spot, don't use a template. */
603 #define TRAMPOLINE_SIZE 12
604 #define TRAMPOLINE_ALIGNMENT 16
606 /* Targets redefine this to invoke code to either flush the cache,
607 or enable stack execution (or both). */
608 #ifndef FINALIZE_TRAMPOLINE
609 #define FINALIZE_TRAMPOLINE(TRAMP)
612 /* We generate a two-instructions program at address TRAMP :
615 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
617 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), \
618 GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); \
619 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \
620 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \
622 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \
623 FINALIZE_TRAMPOLINE(TRAMP); \
626 /* This is the library routine that is used to transfer control from the
627 trampoline to the actual nested function. It is defined for backward
628 compatibility, for linking with object code that used the old trampoline
631 A colon is used with no explicit operands to cause the template string
632 to be scanned for %-constructs.
634 The function name __transfer_from_trampoline is not actually used.
635 The function definition just permits use of "asm with operands"
636 (though the operand list is empty). */
637 #define TRANSFER_FROM_TRAMPOLINE \
639 __transfer_from_trampoline () \
641 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
642 asm (GLOBAL_ASM_OP "___trampoline"); \
643 asm ("___trampoline:"); \
644 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
645 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
649 /* There are two registers that can always be eliminated on the m68k.
650 The frame pointer and the arg pointer can be replaced by either the
651 hard frame pointer or to the stack pointer, depending upon the
652 circumstances. The hard frame pointer is not used before reload and
653 so it is not eligible for elimination. */
654 #define ELIMINABLE_REGS \
655 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
656 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
657 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
659 #define CAN_ELIMINATE(FROM, TO) \
660 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
662 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
663 (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
665 /* Addressing modes, and classification of registers for them. */
667 #define HAVE_POST_INCREMENT 1
668 #define HAVE_PRE_DECREMENT 1
670 /* Macros to check register numbers against specific register classes. */
672 /* True for data registers, D0 through D7. */
673 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7)
675 /* True for address registers, A0 through A7. */
676 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15)
678 /* True for integer registers, D0 through D7 and A0 through A7. */
679 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15)
681 /* True for floating point registers, FP0 through FP7. */
682 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
684 #define REGNO_OK_FOR_INDEX_P(REGNO) \
685 (INT_REGNO_P (REGNO) \
686 || INT_REGNO_P (reg_renumber[REGNO]))
688 #define REGNO_OK_FOR_BASE_P(REGNO) \
689 (ADDRESS_REGNO_P (REGNO) \
690 || ADDRESS_REGNO_P (reg_renumber[REGNO]))
692 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \
693 (INT_REGNO_P (REGNO) \
694 || REGNO == ARG_POINTER_REGNUM \
695 || REGNO >= FIRST_PSEUDO_REGISTER)
697 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \
698 (ADDRESS_REGNO_P (REGNO) \
699 || REGNO == ARG_POINTER_REGNUM \
700 || REGNO >= FIRST_PSEUDO_REGISTER)
702 /* Now macros that check whether X is a register and also,
703 strictly, whether it is in a specified class.
705 These macros are specific to the m68k, and may be used only
706 in code for printing assembler insns and in conditions for
707 define_optimization. */
709 /* 1 if X is a data register. */
710 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X)))
712 /* 1 if X is an fp register. */
713 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X)))
715 /* 1 if X is an address register */
716 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X)))
718 /* True if SYMBOL + OFFSET constants must refer to something within
720 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
721 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0
724 #define MAX_REGS_PER_ADDRESS 2
726 #define CONSTANT_ADDRESS_P(X) \
727 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
728 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
729 || GET_CODE (X) == HIGH) \
730 && LEGITIMATE_CONSTANT_P (X))
732 /* Nonzero if the constant value X is a legitimate general operand.
733 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
734 #define LEGITIMATE_CONSTANT_P(X) \
735 (GET_MODE (X) != XFmode \
736 && !m68k_illegitimate_symbolic_constant_p (X))
738 #ifndef REG_OK_STRICT
739 #define REG_STRICT_P 0
741 #define REG_STRICT_P 1
744 #define LEGITIMATE_PIC_OPERAND_P(X) \
745 (!symbolic_operand (X, VOIDmode) \
746 || (TARGET_PCREL && REG_STRICT_P))
748 #define REG_OK_FOR_BASE_P(X) \
749 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
751 #define REG_OK_FOR_INDEX_P(X) \
752 m68k_legitimate_index_reg_p (X, REG_STRICT_P)
754 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
757 if (m68k_legitimate_address_p (MODE, X, REG_STRICT_P)) \
762 /* Don't call memory_address_noforce for the address to fetch
763 the switch offset. This address is ok as it stands,
764 but memory_address_noforce would alter it. */
765 #define PIC_CASE_VECTOR_ADDRESS(index) index
767 /* For the 68000, we handle X+REG by loading X into a register R and
768 using R+REG. R will go in an address reg and indexing will be used.
769 However, if REG is a broken-out memory address or multiplication,
770 nothing needs to be done because REG can certainly go in an address reg. */
771 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
772 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
773 { register int ch = (X) != (OLDX); \
774 if (GET_CODE (X) == PLUS) \
776 if (GET_CODE (XEXP (X, 0)) == MULT) \
777 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
778 if (GET_CODE (XEXP (X, 1)) == MULT) \
779 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
780 if (ch && GET_CODE (XEXP (X, 1)) == REG \
781 && GET_CODE (XEXP (X, 0)) == REG) \
782 { if (TARGET_COLDFIRE_FPU \
783 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
784 { COPY_ONCE (X); X = force_operand (X, 0);} \
786 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
787 if (GET_CODE (XEXP (X, 0)) == REG \
788 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
789 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
790 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
791 { register rtx temp = gen_reg_rtx (Pmode); \
792 register rtx val = force_operand (XEXP (X, 1), 0); \
793 emit_move_insn (temp, val); \
795 XEXP (X, 1) = temp; \
796 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
797 && GET_CODE (XEXP (X, 0)) == REG) \
798 X = force_operand (X, 0); \
800 else if (GET_CODE (XEXP (X, 1)) == REG \
801 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
802 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
803 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
804 { register rtx temp = gen_reg_rtx (Pmode); \
805 register rtx val = force_operand (XEXP (X, 0), 0); \
806 emit_move_insn (temp, val); \
808 XEXP (X, 0) = temp; \
809 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
810 && GET_CODE (XEXP (X, 1)) == REG) \
811 X = force_operand (X, 0); \
814 /* On the 68000, only predecrement and postincrement address depend thus
815 (the amount of decrement or increment being the length of the operand).
816 These are now treated generically in recog.c. */
817 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
819 #define CASE_VECTOR_MODE HImode
820 #define CASE_VECTOR_PC_RELATIVE 1
822 #define DEFAULT_SIGNED_CHAR 1
824 #define SLOW_BYTE_ACCESS 0
826 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
828 /* The ColdFire FF1 instruction returns 32 for zero. */
829 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
831 #define STORE_FLAG_VALUE (-1)
834 #define FUNCTION_MODE QImode
837 /* Tell final.c how to eliminate redundant test instructions. */
839 /* Here we define machine-dependent flags and fields in cc_status
840 (see `conditions.h'). */
842 /* Set if the cc value is actually in the 68881, so a floating point
843 conditional branch must be output. */
844 #define CC_IN_68881 04000
846 /* On the 68000, all the insns to store in an address register fail to
847 set the cc's. However, in some cases these instructions can make it
848 possibly invalid to use the saved cc's. In those cases we clear out
849 some or all of the saved cc's so they won't be used. */
850 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
852 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
853 do { if (cc_prev_status.flags & CC_IN_68881) \
855 if (cc_prev_status.flags & CC_NO_OVERFLOW) \
857 return NORMAL; } while (0)
859 /* Control the assembler format that we output. */
861 #define ASM_APP_ON "#APP\n"
862 #define ASM_APP_OFF "#NO_APP\n"
863 #define TEXT_SECTION_ASM_OP "\t.text"
864 #define DATA_SECTION_ASM_OP "\t.data"
865 #define GLOBAL_ASM_OP "\t.globl\t"
866 #define REGISTER_PREFIX ""
867 #define LOCAL_LABEL_PREFIX ""
868 #define USER_LABEL_PREFIX "_"
869 #define IMMEDIATE_PREFIX "#"
871 #define REGISTER_NAMES \
872 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \
873 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \
874 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \
875 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \
876 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \
877 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \
878 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \
879 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \
880 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" }
882 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp"
884 /* Return a register name by index, handling %fp nicely.
885 We don't replace %fp for targets that don't map it to %a6
886 since it may confuse GAS. */
887 #define M68K_REGNAME(r) ( \
888 ((FRAME_POINTER_REGNUM == A6_REG) \
889 && ((r) == FRAME_POINTER_REGNUM) \
890 && frame_pointer_needed) ? \
891 M68K_FP_REG_NAME : reg_names[(r)])
893 /* On the Sun-3, the floating point registers have numbers
894 18 to 25, not 16 to 23 as they do in the compiler. */
895 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
897 /* Before the prologue, RA is at 0(%sp). */
898 #define INCOMING_RETURN_ADDR_RTX \
899 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
901 /* After the prologue, RA is at 4(AP) in the current frame. */
902 #define RETURN_ADDR_RTX(COUNT, FRAME) \
904 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \
905 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD)))
907 /* We must not use the DBX register numbers for the DWARF 2 CFA column
908 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
909 Instead use the identity mapping. */
910 #define DWARF_FRAME_REGNUM(REG) \
911 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM)
913 /* The return column was originally 24, but gcc used 25 for a while too.
914 Define both registers 24 and 25 as Pmode ones and use 24 in our own
915 unwind information. */
916 #define DWARF_FRAME_REGISTERS 25
917 #define DWARF_FRAME_RETURN_COLUMN 24
918 #define DWARF_ALT_FRAME_RETURN_COLUMN 25
920 /* Before the prologue, the top of the frame is at 4(%sp). */
921 #define INCOMING_FRAME_SP_OFFSET 4
923 /* All registers are live on exit from an interrupt routine. */
924 #define EPILOGUE_USES(REGNO) \
926 && (m68k_get_function_kind (current_function_decl) \
927 == m68k_fk_interrupt_handler))
929 /* Describe how we implement __builtin_eh_return. */
930 #define EH_RETURN_DATA_REGNO(N) \
931 ((N) < 2 ? (N) : INVALID_REGNUM)
932 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG)
933 #define EH_RETURN_HANDLER_RTX \
934 gen_rtx_MEM (Pmode, \
935 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \
936 plus_constant (EH_RETURN_STACKADJ_RTX, \
939 /* Select a format to encode pointers in exception handling data. CODE
940 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
941 true if the symbol may be affected by dynamic relocations.
943 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support
944 a read-only text segment without imposing a fixed gap between the
945 text and data segments. As a result, the text segment cannot refer
946 to anything in the data segment, even in PC-relative form. Because
947 .eh_frame refers to both code and data, it follows that .eh_frame
948 must be in the data segment itself, and that the offset between
949 .eh_frame and code will not be a link-time constant.
951 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel
952 | DW_EH_PE_indirect for all code references. However, gcc currently
953 handles indirect references using a per-TU constant pool. This means
954 that if a function and its eh_frame are removed by the linker, the
955 eh_frame's indirect references to the removed function will not be
956 removed, leading to an unresolved symbol error.
958 It isn't clear that any -msep-data or -mid-shared-library target
959 would benefit from a read-only .eh_frame anyway. In particular,
960 no known target that supports these options has a feature like
961 PT_GNU_RELRO. Without any such feature to motivate them, indirect
962 references would be unnecessary bloat, so we simply use an absolute
963 pointer for code and global references. We still use pc-relative
964 references to data, as this avoids a relocation. */
965 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
967 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \
968 && ((GLOBAL) || (CODE))) \
969 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \
972 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
973 asm_fprintf (FILE, "%U%s", NAME)
975 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
976 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM))
978 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
979 asm_fprintf (FILE, "\tmove%.l %s,{-(%Rsp)|%Rsp@-}\n", reg_names[REGNO])
981 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
982 asm_fprintf (FILE, "\tmove%.l {(%Rsp)+|%Rsp@+},%s\n", reg_names[REGNO])
984 /* The m68k does not use absolute case-vectors, but we must define this macro
986 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
987 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
989 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
990 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
992 /* We don't have a way to align to more than a two-byte boundary, so do the
993 best we can and don't complain. */
994 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
996 fprintf (FILE, "\t.even\n");
998 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
999 fprintf (FILE, "\t.skip %u\n", (int)(SIZE))
1001 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1002 ( fputs (".comm ", (FILE)), \
1003 assemble_name ((FILE), (NAME)), \
1004 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1006 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1007 ( fputs (".lcomm ", (FILE)), \
1008 assemble_name ((FILE), (NAME)), \
1009 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
1011 /* Output a float value (represented as a C double) as an immediate operand.
1012 This macro is m68k-specific. */
1013 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \
1018 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \
1019 asm_fprintf ((FILE), "%I0r%s", dstr); \
1024 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1025 asm_fprintf ((FILE), "%I0x%lx", l); \
1029 /* Output a double value (represented as a C double) as an immediate operand.
1030 This macro is m68k-specific. */
1031 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1032 do { char dstr[30]; \
1033 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1034 asm_fprintf (FILE, "%I0r%s", dstr); \
1037 /* Note, long double immediate operands are not actually
1038 generated by m68k.md. */
1039 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \
1040 do { char dstr[30]; \
1041 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \
1042 asm_fprintf (FILE, "%I0r%s", dstr); \
1045 /* On the 68000, we use several CODE characters:
1046 '.' for dot needed in Motorola-style opcode names.
1047 '-' for an operand pushing on the stack:
1048 sp@-, -(sp) or -(%sp) depending on the style of syntax.
1049 '+' for an operand pushing on the stack:
1050 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1051 '@' for a reference to the top word on the stack:
1052 sp@, (sp) or (%sp) depending on the style of syntax.
1053 '#' for an immediate operand prefix (# in MIT and Motorola syntax
1054 but & in SGS syntax).
1055 '!' for the fpcr register (used in some float-to-fixed conversions).
1056 '$' for the letter `s' in an op code, but only on the 68040.
1057 '&' for the letter `d' in an op code, but only on the 68040.
1058 '/' for register prefix needed by longlong.h.
1059 '?' for m68k_library_id_string
1063 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1064 'd' to force memory addressing to be absolute, not relative.
1065 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1066 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1067 or print pair of registers as rx:ry. */
1069 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1070 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1071 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1072 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?' \
1073 || (CODE) == '{' || (CODE) == '}')
1076 /* See m68k.c for the m68k specific codes. */
1077 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1079 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1081 /* Values used in the MICROARCH argument to M68K_DEVICE. */
1102 /* An enumeration of all supported target devices. */
1105 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
1107 #include "m68k-devices.def"
1119 enum m68k_function_kind
1121 m68k_fk_normal_function,
1122 m68k_fk_interrupt_handler,
1123 m68k_fk_interrupt_thread
1126 /* Variables in m68k.c; see there for details. */
1127 extern const char *m68k_library_id_string;
1128 extern int m68k_last_compare_had_fp_operands;
1129 extern enum target_device m68k_cpu;
1130 extern enum uarch_type m68k_tune;
1131 extern enum fpu_type m68k_fpu;
1132 extern unsigned int m68k_cpu_flags;
1133 extern const char *m68k_symbolic_call;
1134 extern const char *m68k_symbolic_jump;
1136 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR,
1137 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P };
1139 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
1141 /* ??? HOST_WIDE_INT is not being defined for auto-generated files.
1143 #ifdef HOST_WIDE_INT
1144 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ }
1147 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT);
1150 extern void m68k_emit_move_double (rtx [2]);
1152 extern enum attr_cpu m68k_sched_cpu;
1154 extern enum attr_opx_type m68k_sched_attr_opx_type (rtx, int);
1155 extern enum attr_opy_type m68k_sched_attr_opy_type (rtx, int);
1156 extern int m68k_sched_attr_size (rtx);
1157 extern enum attr_op_mem m68k_sched_attr_op_mem (rtx);
1158 extern enum attr_type m68k_sched_branch_type (rtx);